diff --git a/articles/20220701-cpu-design-part1-riscv-instruction.md b/articles/20220701-cpu-design-part1-riscv-instruction.md
index 4d737f359a0835549ba444c9df7de03ac5b64680..84c5d221387e8209ddcd8c22b1d53c3d67bdb603 100644
--- a/articles/20220701-cpu-design-part1-riscv-instruction.md
+++ b/articles/20220701-cpu-design-part1-riscv-instruction.md
@@ -5,7 +5,7 @@
 > Project: [RISC-V CPU Design](https://gitee.com/tinylab/riscv-linux)<br/>
 > Sponsor: PLCT Lab, ISCAS
 
-# RISC-V 指令集
+# RISC-V CPU 设计（1）：RISC-V 指令集
 
 为了设计出一款基于 RISC-V 指令集的 CPU，我们必须先对 RISC-V 指令集本身进行一定的了解。本文以 RV32 为主来做介绍。
 
diff --git a/articles/20220710-cpu-design-part1-riscv-privilleged-instruction.md b/articles/20220710-cpu-design-part1-riscv-privilleged-instruction.md
index d0093b80ebd11c6168007d71e97f1dd6d57f3527..6712cbd93e3d2da72dfb5569a8e4e6b00beb8595 100644
--- a/articles/20220710-cpu-design-part1-riscv-privilleged-instruction.md
+++ b/articles/20220710-cpu-design-part1-riscv-privilleged-instruction.md
@@ -6,7 +6,7 @@
 > Environment: [Linux Lab](https://tinylab.org/linux-lab)<br/>
 > Sponsor: PLCT Lab, ISCAS
 
-# RISC-V 特权指令架构
+# RISC-V CPU 设计（2）：RISC-V 特权指令架构
 
 RISC-V 的指令集架构 ISA 是由两大部分组成，分别是**非特权级 ISA** 和**特权级 ISA**。而正是因为**特权级 ISA** 的存在，才使得 RISC-V 可以在硬件层面（硬件线程）至多拥有 3 个不同的特权级模式，从而对不同的软件栈部件之间提供保护。
 
diff --git a/articles/20220722-digital-electronic-with-spinalhdl.md b/articles/20220722-cpu-design-digital-electronic-with-spinalhdl.md
similarity index 99%
rename from articles/20220722-digital-electronic-with-spinalhdl.md
rename to articles/20220722-cpu-design-digital-electronic-with-spinalhdl.md
index e1fc1553ab70924e7a1e9d0c125ed6f8852b1044..ae090503fe80a96a449ad2c835d2943cc4143757 100644
--- a/articles/20220722-digital-electronic-with-spinalhdl.md
+++ b/articles/20220722-cpu-design-digital-electronic-with-spinalhdl.md
@@ -6,7 +6,7 @@
 > Proposal: [RISC-V CPU Design](https://gitee.com/tinylab/riscv-linux/issues/I5EIOA)<br/>
 > Sponsor:  PLCT Lab, ISCAS
 
-# CPU 设计——数电基本知识与基于 Scala 的硬件设计框架 SpinalHDL
+# RISC-V CPU 设计（3）：数电基本知识与基于 Scala 的硬件设计框架 SpinalHDL
 
 ## 前言
 
diff --git a/articles/20220803-cpu-design-analysis-and-main-module-implement.md b/articles/20220803-cpu-design-analysis-and-main-module-implement.md
index 87a8d0efec30b5fca90eff1c39e1446db5b41e1c..1d675b90cff68ef06ac38608a03d8d21711308c5 100644
--- a/articles/20220803-cpu-design-analysis-and-main-module-implement.md
+++ b/articles/20220803-cpu-design-analysis-and-main-module-implement.md
@@ -6,7 +6,7 @@
 > Proposal: [RISC-V CPU Design](https://gitee.com/tinylab/riscv-linux/issues/I5EIOA)<br/>
 > Sponsor:  PLCT Lab, ISCAS
 
-# RISC-V CPU 设计理论分析与主要模块的实现
+# RISC-V CPU 设计（4）： RISC-V CPU 设计理论分析与主要模块的实现
 
 ## 前言
 
@@ -779,7 +779,7 @@ object Register_fileSim {
 本文部分图片来自参考资料（Wiki 和 RISC-V 手册等），感谢原作者的辛苦工作！
 
 [1]: https://gitee.com/tinylab/riscv-linux/blob/master/articles/20220701-cpu-design-part1-riscv-instruction.md
-[2]: https://gitee.com/tinylab/riscv-linux/blob/master/articles/20220722-digital-electronic-with-spinalhdl.md
+[2]: https://gitee.com/tinylab/riscv-linux/blob/master/articles/20220722-cpu-design-digital-electronic-with-spinalhdl.md
 [003]: https://github.com/SpinalHDL/SpinalTemplateSbt
 [004]: https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html
 [005]: images/riscv_cpu_design/part2/mermaid-cpu-design-analysis-and-main-module-implement-1.png
diff --git a/articles/20220816-cpu-design-module-board-test.md b/articles/20220816-cpu-design-module-board-test.md
index 626bb6c4780e29d12add2b54bb9cd25bcdf3b6fd..2891da07e9bf348ea53293dcb067054b36078504 100644
--- a/articles/20220816-cpu-design-module-board-test.md
+++ b/articles/20220816-cpu-design-module-board-test.md
@@ -6,7 +6,7 @@
 > Proposal: [RISC-V CPU Design](https://gitee.com/tinylab/riscv-linux/issues/I5EIOA)<br/>
 > Sponsor:  PLCT Lab, ISCAS
 
-# RISC-V CPU 设计模块软件行为仿真与下板实验调试
+# RISC-V CPU 设计（5）：RISC-V CPU 设计模块软件行为仿真与下板实验调试
 
 ## 前言
 
diff --git a/articles/20220826-riscv-cpu-controller-module-design.md b/articles/20220826-cpu-design-riscv-cpu-controller-module-design.md
similarity index 99%
rename from articles/20220826-riscv-cpu-controller-module-design.md
rename to articles/20220826-cpu-design-riscv-cpu-controller-module-design.md
index 352ce886d1fecbcef0e361bf6cf03f39ad5e029c..733ce4bc318ddee65de807f43266147600b923e8 100644
--- a/articles/20220826-riscv-cpu-controller-module-design.md
+++ b/articles/20220826-cpu-design-riscv-cpu-controller-module-design.md
@@ -6,7 +6,7 @@
 > Proposal: [RISC-V CPU Design](https://gitee.com/tinylab/riscv-linux/issues/I5EIOA)<br/>
 > Sponsor:  PLCT Lab, ISCAS
 
-# RV64I CPU 控制器模块设计思路与实现
+# RISC-V CPU 设计（6）： RV64I CPU 控制器模块设计思路与实现
 
 ## 前言