diff --git a/news/README.md b/news/README.md index 0c30e7ae4c442e8ef7a2f2f952b5c2af680ecddb..21b5d594bef833b3c3883ba6a66f6d9fe05317f5 100644 --- a/news/README.md +++ b/news/README.md @@ -5,6 +5,203 @@ * [2022 年](2022.md) * [2023 年 - 上半年](2023-1st-half.md) +## 20230709：第 53 期 + +### 内核动态 + +#### RISC-V 架构支持 + +**[v3: RISC-V: archrandom support](http://lore.kernel.org/linux-riscv/20230709115549.2666557-1-sameo@rivosinc.com/)** + +> This patchset adds support for the archrandom API to the RISC-V +> architecture. +> +> The ratified crypto scalar extensions provide entropy bits via the seed +> CSR, as exposed by the Zkr extension. +> + +**[v1: riscv: support PREEMPT_DYNAMIC with static keys](http://lore.kernel.org/linux-riscv/20230709101653.720-1-jszhang@kernel.org/)** + +> Currently, each architecture can support PREEMPT_DYNAMIC through +> either static calls or static keys. To support PREEMPT_DYNAMIC on +> riscv, we face three choices: +> +> 1. only add static calls support to riscv +> As Mark pointed out in commit 99cf983cc8bc ("sched/preempt: Add +> PREEMPT_DYNAMIC using static keys"), static keys "...should have +> slightly lower overhead than non-inline static calls, as this +> effectively inlines each trampoline into the start of its callee. This +> may avoid redundant work, and may integrate better with CFI schemes." +> So even we add static calls(without inline static calls) to riscv, +> static keys is still a better choice. +> +> 2. add static calls and inline static calls to riscv +> Per my understanding, inline static calls requires objtool support +> which is not easy. +> + +**[v4: RISC-V: mm: Make SV48 the default address space](http://lore.kernel.org/linux-riscv/20230708011156.2697409-1-charlie@rivosinc.com/)** + +> Make sv48 the default address space for mmap as some applications +> currently depend on this assumption. Also enable users to select +> desired address space using a non-zero hint address to mmap. Previous +> kernel changes caused Java and other applications to be broken on sv57 +> which this patch fixes. +> + +**[v2: module: Ignore RISC-V mapping symbols too](http://lore.kernel.org/linux-riscv/20230707160051.2305-2-palmer@rivosinc.com/)** + +> RISC-V has an extended form of mapping symbols that we use to encode +> the ISA when it changes in the middle of an ELF. This trips up modpost +> as a build failure, I haven't yet verified it yet but I believe the +> kallsyms difference should result in stacks looking sane again. +> + +**[GIT PULL: RISC-V Patches for the 6.5 Merge Window, Part 2](http://lore.kernel.org/linux-riscv/mhng-4bd23a4e-dd7c-4f62-90c8-804c137c2621@palmer-ri-x1c9/)** + +> merged tag 'riscv-for-linus-6.5-mw1' +> The following changes since commit 533925cb760431cb496a8c965cfd765a1a21d37e: +> +> Merge tag 'riscv-for-linus-6.5-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux (2023-06-30 09:37:26 -0700) +> +> are available in the Git repository at: +> +> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.5-mw2 +> + +**[v6: tools/nolibc: add a new syscall helper](http://lore.kernel.org/linux-riscv/cover.1688739492.git.falcon@tinylab.org/)** + +> Here is the v6 of the __sysret series [1], applies your suggestions. +> additionally, the sbrk() also uses the __sysret helper. +> + +**[v1: RISC-V: Support querying vendor extensions](http://lore.kernel.org/linux-riscv/20230705-thead_vendor_extensions-v1-0-ad6915349c4d@rivosinc.com/)** + +> Introduce extensible method of querying vendor extensions. Keys above +> 1UL<<63 passed into the riscv_hwprobe syscall are reserved for vendor +> extensions. The appropriate vendor is resolved using the discovered +> mvendorid. Vendor specific code is then entered which determines how to +> respond to the input hwprobe key. +> + +**[v2: RISC-V: Show accurate per-hart isa in /proc/cpuinfo](http://lore.kernel.org/linux-riscv/20230705172931.1099183-1-evan@rivosinc.com/)** + +> In /proc/cpuinfo, most of the information we show for each processor is +> specific to that hart: marchid, mvendorid, mimpid, processor, hart, +> compatible, and the mmu size. But the ISA string gets filtered through a +> lowest common denominator mask, so that if one CPU is missing an ISA +> extension, no CPUs will show it. +> + +**[v3: Obtain SMBIOS and ACPI entry from FFI](http://lore.kernel.org/linux-riscv/20230705114251.661-1-cuiyunhui@bytedance.com/)** + +> Here's version 3 of patch series. +> + +**[v1: RISC-V: KVM: provide UAPI for host SATP mode](http://lore.kernel.org/linux-riscv/20230705091535.237765-1-dbarboza@ventanamicro.com/)** + +> KVM userspaces need to be aware of the host SATP to allow them to +> advertise it back to the guest OS. +> +> Since this information is used to build the guest FDT we can't wait for +> the SATP reg to be readable. We just need to read the SATP mode, thus +> we can use the existing 'satp_mode' global that represents the SATP reg +> with MODE set and both ASID and PPN cleared. E.g. for a 32 bit host +> running with sv32 satp_mode is 0x80000000, for a 64 bit host running +> sv57 satp_mode is 0xa000000000000000, and so on. +> + +**[v7: -next: support allocating crashkernel above 4G explicitly on riscv](http://lore.kernel.org/linux-riscv/20230704212327.1687310-1-chenjiahao16@huawei.com/)** + +> On riscv, the current crash kernel allocation logic is trying to +> allocate within 32bit addressible memory region by default, if +> failed, try to allocate without 4G restriction. +> +> In need of saving DMA zone memory while allocating a relatively large +> crash kernel region, allocating the reserved memory top down in +> high memory, without overlapping the DMA zone, is a mature solution. +> Hence this patchset introduces the parameter option crashkernel=X,[high,low]. +> + +#### 异步 IO + +**[v1: io_uring: A new function has been defined to make get/put exist in pairs](http://lore.kernel.org/io-uring/20230706093208.6072-1-luhongfei@vivo.com/)** + +> A new function called io_put_task_refs has been defined for pairing +> with io_get_task_refs. +> +> In io_submit_sqes(), when req is not fully sent(i.e. left != 0), it is +> necessary to call the io_put_task_refs() to recover the current process's +> cached_refs and pair it with the io_get_task_refs(), which is easy to +> understand and looks more regular. +> + +### 周边技术动态 + +#### Qemu + +**[v3: target/riscv: improve code accuracy and](http://lore.kernel.org/qemu-devel/20230708091055.38505-1-reaperlu@hust.edu.cn/)** + +> I'm so sorry. As a newcomer, I'm not familiar with the patch mechanism. I mistakenly added the reviewer's "Reviewed-by" line into the wrong commit, So I have resent this patchset +> + +**[v1: target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly](http://lore.kernel.org/qemu-devel/20230707032306.4606-1-gaoshanliukou@163.com/)** + +> Should set/get riscv all reg timer,i.e, time/compare/frequency/state. +> + +**[v2: riscv: Generate devicetree only after machine initialization is complete](http://lore.kernel.org/qemu-devel/20230706035937.1870483-1-linux@roeck-us.net/)** + +> If the devicetree is created before machine initialization is complete, +> it misses dynamic devices. Specifically, the tpm device is not added +> to the devicetree file and is therefore not instantiated in Linux. +> Load/create devicetree in virt_machine_done() to solve the problem. +> + +**[v1: riscv: add config for asid size](http://lore.kernel.org/qemu-devel/20230705105838.68806-1-ben.dooks@codethink.co.uk/)** + +> Add a config to the cpu state to control the size of the ASID area +> in the SATP CSR to enable testing with smaller than the default (which +> is currently maximum for both rv32 and rv64). It also adds the ability +> to stop the ASID feature by using 0 to disable it. +> + +#### U-Boot + +**[v2: riscv: Initial support for Lichee PI 4A board](http://lore.kernel.org/u-boot/20230708112435.23583-1-dlan@gentoo.org/)** + +> Sipeed's Lichee PI 4A board is based on T-HEAD's TH1520 SoC which consists of +> quad core XuanTie C910 CPU, plus one C906 CPU and one E902 CPU. +> +> In this series, we add a basic device tree, including UART CPU, PLIC, make it +> capable of running into a serial console. +> +> Please note that, we rely on pre shipped vendor u-boot which run in M-Mode to +> chain load this mainline u-boot either via eMMC storage or from tftp, thus the +> pinctrl and clock setting are not implemented in this series, which certainly +> can be improved later accordingly. +> + +**[v1: riscv: (visionfive2:) device tree binding for riscv_timer](http://lore.kernel.org/u-boot/20230707135333.GA30112@lst.de/)** + +> following the existing device tree binding[1], here is a draft to use it +> in drivers/timer/riscv_timer.c. This would also fix the regression we see +> with commit 55171aedda8 ("dm: Emit the arch_cpu_init_dm() even only +> before relocation"), at least on the VisionFive2, as sketched out below. +> The device tree addition suits the Linux kernel dirver +> + +**[v1: u-boot-riscv/riscv-for-next](http://lore.kernel.org/u-boot/ZKabX3HI7USoCEEt@ubuntu01/)** + +> The following changes since commit e80f4079b3a3db0961b73fa7a96e6c90242d8d25: +> +> Merge tag 'v2023.07-rc6' into next (2023-07-05 11:28:55 -0400) +> +> are available in the Git repository at: +> +> https://source.denx.de/u-boot/custodians/u-boot-riscv.git riscv-for-next +> + ## 20230705：第 52 期 ### 内核动态