From c3e4b20d1f14500cb9fd70aea8579d1107f5a902 Mon Sep 17 00:00:00 2001
From: wayling <9m77fans@gmail.com>
Date: Thu, 25 Aug 2022 02:33:37 +0000
Subject: [PATCH] update plan/README.md.

Signed-off-by: wayling <9m77fans@gmail.com>
---
 plan/README.md | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/plan/README.md b/plan/README.md
index 341876b..d8d2a5f 100644
--- a/plan/README.md
+++ b/plan/README.md
@@ -157,11 +157,12 @@
 
 * Atomics
     * [RISC-V 原子指令与用法介绍](https://tinylab.org/riscv-atomics/), [直播回放](https://www.cctalk.com/v/16489499392383) @pingbo
-
-* [Generic Ticket Spinlock](https://lore.kernel.org/linux-riscv/11364105.8ZH9dyz9j6@diego/T/#t)
+    * [RISC-V vs Aarch 64 atomic PK] @aabb5566
+* [Generic Ticket Spinlock](https://lore.kernel.org/linux-riscv/11364105.8ZH9dyz9j6@diego/T/#t) @aabb5566
+* [Mutex] https://lwn.net/Articles/164802/ @aabb5566
 * [Restartable Sequence (RSEQ)](https://lore.kernel.org/linux-riscv/20220308083253.12285-1-vincent.chen@sifive.com/T/#t)
 * [Qspinlock](https://lore.kernel.org/linux-riscv/CAJF2gTT9YHgTzPaBN4ekYS7UcBOj_9k9xEcrsoXgW6PCZc8x3Q@mail.gmail.com/T/#t)
-
+* [A Memory Model for RISC-V] (https://riscv.org/wp-content/uploads/2018/05/14.25-15.00-RISCVMemoryModelTutorial.pdf) @aabb5566
 ## Multi-core
 
 * SMP support @user_11186799
-- 
Gitee