From 74ba39e03151c9edfd5146c678cb4ac065082259 Mon Sep 17 00:00:00 2001 From: yooyoyo <11251868+yooyoyo@user.noreply.gitee.com> Date: Sun, 14 Aug 2022 07:40:03 +0000 Subject: [PATCH] update news/README.md. Signed-off-by: yooyoyo <11251868+yooyoyo@user.noreply.gitee.com> --- news/README.md | 76 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/news/README.md b/news/README.md index c8c527f..b48a504 100644 --- a/news/README.md +++ b/news/README.md @@ -1,5 +1,81 @@ # RISC-V Linux 内核及周边技术动态 +## 20220814：第 7 期 + +### 内核动态 + +* GIT PULL: [RISC-V Patches for the 5.20 Merge Window, Part 2](https://lore.kernel.org/linux-riscv/mhng-563e7d68-e504-4e0a-b666-f7c2fbab62db@palmer-ri-x1c9/) + + There's still a handful of new features in here, but there are a lot of fixes/cleanups as well: + * Support for the Zicbom for explicit cache-block management, along with + the necessary bits to make the non-standard cache management ops on + the Allwinner D1 function. + * Support for the Zihintpause extension, which codifies a go-slow + instruction used for cpu_relax(). + * Support for the Sstc extension for supervisor-mode timer/counter + management. + * Many device tree fixes and cleanups, including a large set for the + Canaan device trees. + * A handful of fixes and cleanups for the PMU driver. + +* V3: [Support RISCV64 arch and common commands](https://lore.kernel.org/linux-riscv/20220813031753.3097720-1-xianting.tian@linux.alibaba.com/) + + This series of patches are for Crash-utility tool, it make crash tool support RISCV64 arch and the common commands(*, bt, p, rd, mod, log, set, struct, task, dis, help -r, help -m, and so on). + +* V1: [riscv: enable CD-ROM file systems in defconfig](https://lore.kernel.org/linux-riscv/20220812200853.311474-1-heinrich.schuchardt@canonical.com/) + + CD-ROM images are still commonly used for installer images and other data exchange. These file systems should be supported on RISC-V by default like they are on x86_64. + +* V2: [RISC-V: Clean up the Zicbom block size probing](https://lore.kernel.org/linux-riscv/20220812154010.18280-1-palmer@rivosinc.com/) + + This fixes two issues: I truncated the warning's hart ID when porting to the 64-bit hart ID code, and the original code's warning handling could fire on an uninitialized hart ID. + +* V3: [Risc-V Svinval support](https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale@ventanamicro.com/) + + This patch adds support for the Svinval extension as defined in the Risc V Privileged specification. + +* V1: [Fix RISC-V/PCI dt-schema issues with dt-schema v2022.08](https://lore.kernel.org/linux-riscv/20220811203306.179744-1-mail@conchuod.ie/) + + Got a few fixes for PCI dt-bindings that I noticed after upgrading my dt-schema to v2022.08. I am unsure if some of these patches are the right fixes, which I noted in the patches themselves, especially the address translation property. + +* V6: [RISC-V fixups to work with crash tool](https://lore.kernel.org/linux-riscv/20220811074150.3020189-1-xianting.tian@linux.alibaba.com/) + + This patch set just put these patches together, and with three new patch 4, 5, 6. these six patches are the fixups for machine_kexec, kernel mode PC for vmcore and improvements for vmcoreinfo, memory layout dump and fixup schedule out issue in machine_crash_shutdown(). + +* V1: [wireguard: selftests: set CONFIG_NONPORTABLE on riscv32](https://lore.kernel.org/linux-riscv/20220809145757.83673-1-Jason@zx2c4.com/) + + When the CONFIG_PORTABLE/CONFIG_NONPORTABLE switches were added, various configs were updated, but the wireguard config was forgotten about. This leads to unbootable test kernels, causing CI fails. + +* V9: [arch: Add qspinlock support and atomic cleanup](https://lore.kernel.org/linux-riscv/20220808071318.3335746-1-guoren@kernel.org/) + + RISC-V LR/SC pairs could provide a strong/weak forward guarantee that depends on micro-architecture. And RISC-V ISA spec has given out several limitations to let hardware support strict forward guarantee. + +### 周边技术动态 + +#### Qemu + +* V2: [riscv: Make semihosting configurable for all privilege modes](https://lore.kernel.org/qemu-devel/CA+tJHD4Fdv54_u9vffu9tNuor4Tu_Ld-eYZkLRmTxi=X2wknnw@mail.gmail.com/) + + Unlike ARM, RISC-V does not define a separate breakpoint type for semihosting. Instead, it is entirely ABI. However, RISC-V debug specification provides ebreak{m,s,u,vs,vu} configuration bits to allow ebreak behavior to be configured to trap into debug mode instead. + +* V3: [QEMU: Fix RISC-V virt & spike machines' dtbs](https://lore.kernel.org/qemu-devel/20220810184612.157317-1-mail@conchuod.ie/) + + The device trees produced automatically for the virt and spike machines fail dt-validate on several grounds. Some of these need to be fixed in the linux kernel's dt-bindings, but others are caused by bugs in QEMU. + +* V9: [Implement Sstc extension](https://lore.kernel.org/qemu-devel/20220810184548.3620153-1-atishp@rivosinc.com/) + + This series implements Sstc extension[1] which was ratified recently. The first patch is a prepartory patches while PATCH 2 adds stimecmp support while PATCH 3 adds vstimecmp support. This series is based on top of upstream commit (faee5441a038). + +* V8: [RISC-V Smstateen support](https://lore.kernel.org/qemu-devel/20220809041643.124888-1-mchitale@ventanamicro.com/) + + This series adds support for the Smstateen specification which provides a mechanism to plug the potential covert channels which are opened by extensions that add to processor state that may not get context-switched. + +#### Buildroot + +* GIT COMMIT: [board/riscv/nommu: bump kernel version and drop no longer needed patch](https://lore.kernel.org/buildroot/20220811202816.E96F487348@busybox.osuosl.org/) + + Bump the kernel version for all riscv nommu configs from 5.18 to 5.19. That way, we can remove the one and only riscv nommu patch, since this patch is included in kernel 5.19. + ## 20220807：第 6 期 ### 内核动态 -- Gitee