From 5ae303d4f36f2e63a90eb20b26dabf2977871a0d Mon Sep 17 00:00:00 2001 From: yooyoyo <11251868+yooyoyo@user.noreply.gitee.com> Date: Sun, 31 Jul 2022 06:59:57 +0000 Subject: [PATCH] update news/README.md. --- news/README.md | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/news/README.md b/news/README.md index 513bc8a..b7b448a 100644 --- a/news/README.md +++ b/news/README.md @@ -1,5 +1,71 @@ # RISC-V Linux 内核及周边技术动态 +## 202200731：第 5 期 + +### 内核动态 + +* GIT PULL: [A Single RISC-V Fix for 5.19](https://lore.kernel.org/linux-riscv/mhng-b20f34d5-a1cb-4254-8cc5-d3c7752b3908@palmer-mbp2014/) + + The following changes since commit c1f6eff304e4dfa4558b6a8c6b2d26a91db6c998: riscv: add as-options for modules with assembly compontents + +* GIT PULL: [KVM/riscv changes for 5.20](https://lore.kernel.org/linux-riscv/CAAhSdy2iH-WpitweQ_nCYm6p0S5S_fmQ3x37FdAe7tEmu_np0A@mail.gmail.com/) + + We have following KVM RISC-V changes for 5.20: Track ISA extensions used by Guest using bitmap. Added system instruction emulation framework. Added + CSR emulation framework. + +* V1: [riscv: enable software resend of irqs](https://lore.kernel.org/linux-riscv/20220729111116.259146-1-conor.dooley@microchip.com/) + + The PLIC specification does not describe the interrupt pendings bits as read-write, only that they "can be read". To allow for retriggering of + interrupts enable HARDIRQS_SW_RESEND for RISC-V. + +* V1: [doc: RISC-V: Document that misaligned accesses are supported](https://lore.kernel.org/linux-riscv/20220728210715.17214-1-palmer@rivosinc.com/) + + The RISC-V ISA manual used to mandate that misaligned accesses were supported in user mode, but that requirement was removed in 2018 via riscv-isa- + manual commit 61cadb9 Since the Linux uABI was already frozen at that point it's just been demoted to part of the uABI, but that was never written + down. + +* V2: [Improve CLOCK_EVT_FEAT_C3STOP feature setting](https://lore.kernel.org/linux-riscv/20220727114302.302201-1-apatel@ventanamicro.com/) + + This series improves the RISC-V timer driver to set CLOCK_EVT_FEAT_C3STOP feature based on RISC-V platform capabilities. + +* V1: [Add support for Renesas RZ/Five SoC](https://lore.kernel.org/linux-riscv/20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com/) + + The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces + such as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as entry-class social infrastructure gateway control and industrial + gateway control. + +* V4: [RISC-V fixups to work with crash tool](https://lore.kernel.org/linux-riscv/20220726093729.1231867-1-xianting.tian@linux.alibaba.com/) + + This patch series just put these patches together, and with two new patch 4, 5. these five patches are the fixups for machine_kexec, + kernel mode PC for vmcore and improvements for vmcoreinfo and memory layout dump. + +* V8: [arch: Add qspinlock support with combo style](https://lore.kernel.org/linux-riscv/20220724122517.1019187-1-guoren@kernel.org/) + + Enable qspinlock and meet the requirements mentioned in a8ad07e5240c9 RISC-V LR/SC pairs could provide a strong/weak forward guarantee + that depends on micro-architecture. + +### 周边技术动态 + +#### Qemu + +* V11: [Improve PMU support](https://lore.kernel.org/qemu-devel/20220727064913.1041427-1-atishp@rivosinc.com/) + + The latest version of the SBI specification includes a Performance Monitoring Unit(PMU) extension which allows the supervisor to + start/stop/configure various PMU events.This series implements remaining PMU infrastructure to support PMU in virt machine. + +* V5: [target/riscv: Add Zihintpause support](https://lore.kernel.org/qemu-devel/20220725034728.2620750-1-daolu@rivosinc.com/) + + This patch adds RISC-V Zihintpause support. The extension is set to be enabled by default and opcode has been added to insn32.decode. + Added trans_pause to exit the TB and return to main loop. + +#### Buildroot + +* V2: [arch/Config.in.riscv: lp64f ABI is only supported if MMU is enabled](https://lore.kernel.org/buildroot/20220726163951.2111731-1-thomas.petazzoni@bootlin.com/) + + Even though that seems weird, the LP64F ABI is only supported when MMU support is enabled. In deed, as per commit + 9a51381cedc16e6d70cb85e1144f6e0fa89af69a ("package/uclibc: prevent config with unsupported RISC-V float ABI"), + uClibc does not support LP64F. But uClibc is the only C library that support RISC-V 64-bit noMMU. + ## 20220723：第 4 期 ### 内核动态 -- Gitee