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-# RISC-V Linux 内核及周边技术动态
+# RISC-V Linux 内核及周边技术动态 
+
+## 20220716：第三期
+
+### 内核动态
+
+* v5: [use static key to optimize pgtable_l4_enabled](https://lore.kernel.org/linux-riscv/20220715134847.2190-1-jszhang@kernel.org/T/#t)
+    
+    The pgtable_l4|[l5]_enabled check sits at hot code path, performance is impacted a lot. Since pgtable_l4|[l5]_enabled isn't 
+    changed after boot, so static key can be used to solve the performance issue[1].
+ 
+* v4: [Fix RISC-V's arch-topology reporting](https://lore.kernel.org/linux-riscv/20220715175155.3567243-1-mail@conchuod.ie/T/#t)
+    
+    The goal here is the fix the incorrectly reported arch topology on RISC-V which seems to have been broken since it was added.
+    
+* next: [arch_topology: Fix cache attributes detection in the CPU hotplug pat](https://lore.kernel.org/linux-riscv/YtBX8WX+oyPww%2Fm+@arm.com/T/#t)
+    
+    Move the call to detect_cache_attributes() inside update_siblings_masks() to ensure the cacheinfo is updated before the LLC 
+    sibling masks are updated.
+    
+* v3: [clear riscv dtbs_check errors](https://lore.kernel.org/linux-riscv/mhng-91bfbf9d-d8cc-4642-9688-20ef7ab21512@palmer-ri-x1c9/T/#t)
+
+    Couple conversions from txt to yaml here with the intent of fixing the the dtbs_check warnings for riscv when building with "defconfig". 
+    Atul Khare already sent patches for the gpio-line-names & cache-sets (which went awol) and will clear the remaining two errors.
+
+* v3: [Improve vmcoreinfo and memory layout dump](https://lore.kernel.org/linux-riscv/20220714113300.367854-2-xianting.tian@linux.alibaba.com/T/#u)
+
+    This patch series are the improvements for vmcoreinfo and memory layout dump.
+    
+* v2: [riscv: dts: starfive: correct number of external interrupts](https://lore.kernel.org/linux-riscv/27617ba6-addf-6f29-e1a8-2cb813dc303a@microchip.com/T/#t)
+
+    The PLIC integrated on the Vic_U7_Core integrated on the StarFive JH7100 SoC actually supports 133 external interrupts. 
+    127 of these are exposed to the outside world; the remainder are used by other devices that are part of the core-complex 
+    such as the L2 cache controller.
+
+* v5: [Microchip soft ip corePWM driver](https://lore.kernel.org/linux-riscv/20220708143923.1129928-1-conor.dooley@microchip.com/T/#t)
+
+    The duty cycle calculation has been fixed - the problem was exactly what I suspected in my replies to your review. I had 
+    to block the use of a 0xFF period_steps register value (which I think should be covered by the updated comment and limitation #2).
+    
+* v1: [Proof of concept for rv32 svpbmt support](https://lore.kernel.org/linux-riscv/20220705100523.1204595-1-guoren@kernel.org/T/#t)
+
+    RISC-V 32bit also requires svpbmt in cost-down chip embedded scenarios, and their RAM is limited (No more than 1GB). It is worth 
+    mentioning that rv32-Linux currently only supports 1GB of DRAM, and there is no plan for high-memory.
+
+* v2: [riscv: always honor the CONFIG_CMDLINE_FORCE when parsing dtb](https://lore.kernel.org/linux-riscv/PSBPR04MB399135DFC54928AB958D0638B1829@PSBPR04MB3991.apcprd04.prod.outlook.com/T/#u)
+
+    his especially fixes the case where a device tree without the chosen node is supplied to the kernel. In such cases, 
+    early_init_dt_scan would return true.
+
+* v2: [riscv: mm: add Svnapot support](https://lore.kernel.org/linux-riscv/20220716085648.4156408-1-panqinglin2020@iscas.ac.cn/T/#t)
+
+    Svnapot is a RISC-V extension for marking contiguous 4K pages as a non-4K page. This patch set is for using Svnapot in 
+    Linux Kernel's boot process and hugetlb fs.
+
+### 周边技术动态
+
+#### Qemu
+
+* v1:[RISC-V: Allow both Zmmul and M](https://lore.kernel.org/qemu-devel/20220714180033.22385-1-palmer@rivosinc.com/)
+
+    We got to talking about how Zmmul and M interact with each other https://github.com/riscv/riscv-isa-manual/issues/869,
+    and it turns out that QEMU's behavior is slightly wrong: having Zmmul and M is a legal combination, it just means that 
+    the multiplication instructions are supported even when M is disabled at runtime via misa.
+
+#### Buildroot
+
+* v3:[Fix RV64 NOMMU and add Canaan K210 SoC support](https://lore.kernel.org/buildroot/bd4eeaff-f4ce-ecd3-8e3b-03d5a924b53a@opensource.wdc.com/)
+
+     This series adds support for building 64-bits RISC-V NOMMU kernels (both bootable kernels and u-boot sdcard boot envronements) 
+     for NOMMU RISC-V 64-bits boards.
+
+* v1:[arch/riscv: Added support for RISC-V vector extension on the architecture menu.](https://lore.kernel.org/buildroot/CAF2ART_=XUWL8bgtdV7vUgz5SQJXVyBAAS0ixcYLVbaaA++_4w@mail.gmail.com/)
+
+    This new setting will allow to test new toolchains already available that support the vector extension (more patches coming soon).
 
 ## 20220707：第二期