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 # RISC-V Linux 内核及周边技术动态
 
+## 20220707:第二期
+
+### 内核动态
+
+* v5:[RISC-V: Create unique identification for SoC PMU](https://lore.kernel.org/linux-riscv/165710198557.2545727.12369986485829448520.b4-ty@kernel.org/T/#t)
+
+    This series aims to provide matching vendor SoC with corresponded JSON bindings.Where MIMPID can vary as all impl supported the same number of 
+    events, this might not be true for all future SoC however.Also added SBI firmware events pretty names, as any firmware that supports SBI PMU 
+    should also support firmare events. 
+    
+* v7:[riscv: implement Zicbom-based CMO instructions + the t-head variant](https://lore.kernel.org/linux-riscv/20220706231536.2041855-1-heiko@sntech.de/T/#t)
+
+    This series is based on the alternatives changes done in my svpbmt series and thus also depends on Atish's isa-extension parsing series.
+    It implements using the cache-management instructions from the  Zicbom-extension to handle cache flush, etc actions on platforms needing them.
+
+* v3:[clear riscv dtbs_check errors](https://lore.kernel.org/linux-riscv/20220606201343.514391-1-mail@conchuod.ie/T/#t)
+
+    Couple conversions from txt to yaml here with the intent of fixing the dtbs_check warnings for riscv when building with "defconfig". 
+    Atul Khare already sent patches for the gpio-line-names & cache-sets (which went awol) and will clear the remaining two errors.
+    
+* v4:[riscv: Optimize atomic implementation](https://lore.kernel.org/linux-riscv/YsYivaDEksXPQPaH@boqun-archlinux/T/#t)
+
+    Here are some optimizations for riscv atomic implementation, the first three patches are normal cleanup and custom implementation without 
+    relating to atomic semantics.
+    
+* v4:[use static key to optimize pgtable_l4_enabled](https://lore.kernel.org/linux-riscv/mhng-17913c13-57bd-42f9-9136-b4eb9632253c@palmer-mbp2014/T/#t)
+
+    The pgtable_l4|[l5]_enabled check sits at hot code path, performance is impacted a lot. Since pgtable_l4|[l5]_enabled isn't changed after boot, 
+    so static key can be used to solve the performance issue[1].
+    
+* v5:[arch_topology: Updates to add socket support and fix cluster ids](https://lore.kernel.org/linux-riscv/20220627165047.336669-1-sudeep.holla@arm.com/T/#t)
+
+    This series intends to fix some discrepancies we have in the CPU topology parsing from the device tree /cpu-map node. 
+    Also this diverges from the behaviour on a ACPI enabled platform. The expectation is that both DT and ACPI enabled systems 
+    must present consistent view of the CPU topology.
+
+* v5:[RISC-V: three fixup and cleanups](https://lore.kernel.org/linux-riscv/20220701120548.228261-1-xianting.tian@linux.alibaba.com/T/#t)
+
+    Use __smp_processor_id() to avoid check the preemption context when CONFIG_DEBUG_PREEMPT enabled, as we will enter crash kernel and no return.
+    
+* v3:[Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow](https://lore.kernel.org/linux-riscv/92a45bf04cfe140c7605559fa3d8f4eb@kernel.org/T/#t)
+
+    This patch series adds PLIC support for Renesas RZ/Five SoC. Since the T-HEAD C900 PLIC has the same behavior, it also applies the fix for 
+    that variant. This series is an update of v2 of the RZ/Five series[0], and replaces the separate T-HEAD series[1].
+
+* v2:[Improve instruction and CSR emulation in KVM RISC-V](https://lore.kernel.org/linux-riscv/CAAhSdy3gmnqB6La125i2hdVh6eNiwqG6saqz4RTTYF=2Gqo6cA@mail.gmail.com/T/#t)
+
+    Currently, the instruction emulation for MMIO traps and Virtual instruction traps co-exist with general VCPU exit handling. 
+    The instruction and CSR emulation will grow with upcoming SBI PMU, AIA, and Nested virtualization in KVM RISC-V. 
+
+* v3:[irqchip: RISC-V PLIC cleanup and optimization](https://lore.kernel.org/linux-riscv/20220701202440.59059-1-samuel@sholland.org/T/#t)
+
+    This series depends on my other series[2] making the IRQ affinity mask behavior more consistent between uniprocessor and SMP configurations.
+    (The Allwinner D1 is a uniprocessor SoC containing a PLIC.)
+
+* v2:[dt-bindings: sifive: fix dt-schema errors](https://lore.kernel.org/linux-riscv/fb861221-2e9d-7d4a-dd52-b16b3b581fd6@microchip.com/T/#t)
+
+    The patch series fixes dt-schema validation errors that can be reproduced using the following: make ARCH=riscv defconfig; 
+    make ARCH=riscv dt_binding_check dtbs_check
+
+* v2:[riscv: Fix missing PAGE_PFN_MASK](https://lore.kernel.org/linux-riscv/d5d1a6ef-1153-272b-af9b-9f369bbdd4e5@ghiti.fr/T/#t)
+
+    here are a bunch of functions that use the PFN from a page table entry that end up with the svpbmt upper-bits because they are 
+    missing the newly introduced PAGE_PFN_MASK which leads to wrong addresses conversions and then crash: fix this by adding this mask.
+    
+### 周边技术动态
+
+#### Qemu
+
+* v7:[KVM: Add KVM_EXIT_MEMORY_FAULT exit](https://lore.kernel.org/qemu-devel/20220706082016.2603916-11-chao.p.peng@linux.intel.com/)
+
+    This new KVM exit allows userspace to handle memory-related errors. It indicates an error happens in KVM at guest memory range (gpa, gpa+size). 
+    The flags includes additional information for userspace to handle the error. 
+    
+* v4:[target/riscv: Add Zihintpause support ](https://lore.kernel.org/qemu-devel/20220705174933.2898412-1-daolu@rivosinc.com/)   
+
+    This patch adds RISC-V Zihintpause support. The extension is set to be enabled by default and opcode has been added to insn32.decode.    
+    
+* v2:[target/riscv: Support mcycle/minstret write operation](https://lore.kernel.org/qemu-devel/20220703001234.439716-13-alistair.francis@opensource.wdc.com/)
+
+    mcycle/minstret are actually WARL registers and can be written with any given value. With SBI PMU extension, it will be used to store a 
+    initial value provided from supervisor OS.     
+
+* v2:[target/riscv: Set env->bins in gen_exception_illegal ](https://lore.kernel.org/qemu-devel/20220703001234.439716-3-alistair.francis@opensource.wdc.com/)
+
+    While we set env->bins when unwinding for ILLEGAL_INST, from e.g. csrrw, we weren't setting it for immediately illegal instructions.    
+    
+* v2:[target/riscv: Fixup MSECCFG minimum priv check](https://lore.kernel.org/qemu-devel/20220703001234.439716-14-alistair.francis@opensource.wdc.com/)
+
+    There is nothing in the RISC-V spec that mandates version 1.12 is required for ePMP and there is currently hardware that implements ePMP 
+    (a draft version though) with the 1.11 priv spec.   
+
+#### U-Boot
+
+* v1:[riscv: Remove additional ifdef from code guarded by CONFIG_IS_ENABLED](https://lore.kernel.org/u-boot/f8e3ff9124195cbd957874de9a65ef79760ef5e7.1657183634.git.michal.simek@amd.com/)
+
+    CONFIG_OF_LIBFDT is used twice for guarding the same code. It is enough to do it once 
+    that's why remove additional ifdefs from arm and risc-v code.
+
+#### Buildroot
+
+* v1:[arch/riscv: Added support for RISC-V vector extension on the architecture menu.](https://lore.kernel.org/buildroot/20220704085552.3499243-2-abel@x-silicon.com/)
+
+    This new setting will allow to test new toolchains already available that support the vector extension (more patches coming soon).
+
+* v1:[package/llvm: Support for RISC-V on the LLVM package](https://lore.kernel.org/buildroot/20220704085552.3499243-1-abel@x-silicon.com/)
+
+    There is a new configuration parameter added(BR2_PACKAGE_LLVM_TARGETS_TO_BUILD) for dealing with the fact that the LLVM target and 
+    the architecture have different naming for RISC-V.
+    
+
+
+
+
+
+
+
 ## 20220630：第一期
 
 ### 内核动态