diff --git a/news/README.md b/news/README.md index 3ce76a1b060df4b8e1545e7a8a6fd0b6e7059c27..1e8c84d6fe77925032b25cfb0358b03dd28c975a 100644 --- a/news/README.md +++ b/news/README.md @@ -1,55 +1,91 @@ -# RISV-V Linux 内核技术动态 +# RISV-V Linux 内核及周边技术动态 ## 20220630：第一期 -### v5: [riscv: implement Zicbom-based CMO instructions + the t-head variant](https://lore.kernel.org/linux-riscv/20220629215944.397952-1-heiko@sntech.de/T/#t) +### 内核动态 -It implements using the cache-management instructions from the Zicbom-extension to handle cache flush, etc actions on platforms needing them. +* v5: [riscv: implement Zicbom-based CMO instructions + the t-head variant](https://lore.kernel.org/linux-riscv/20220629215944.397952-1-heiko@sntech.de/T/#t) -### next: [riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit](https://lore.kernel.org/linux-riscv/11a0698c-5726-15e8-2448-3529d2d0b098@huawei.com/T/#t) + It implements using the cache-management instructions from the Zicbom-extension to handle cache flush, etc actions on platforms needing them. -Since commit 5d8544e2d007 ("RISC-V: Generic library routines and assembly") -and commit ebcbd75e3962 ("riscv: Fix the bug in memory access fixup code"), -if __clear_user and __copy_user return from an fixup branch, CSR_STATUS SR_SUM bit will be set, it is a vulnerability, so that -S-mode memory accesses to pages that are accessible by U-mode will success. Disable S-mode access to U-mode memory should clear SR_SUM bit. +* next: [riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit](https://lore.kernel.org/linux-riscv/11a0698c-5726-15e8-2448-3529d2d0b098@huawei.com/T/#t) -### v7: [riscv: Add qspinlock support with combo style](https://lore.kernel.org/linux-riscv/20220628081707.1997728-1-guoren@kernel.org/T/#t) + Since commit 5d8544e2d007 ("RISC-V: Generic library routines and assembly")and commit ebcbd75e3962 ("riscv: Fix the bug in memory access fixup code"),if __clear_user and __copy_user return from an fixup branch, CSR_STATUS SR_SUM bit will be set, it is a vulnerability, so that S-mode memory accesses to pages that are accessible by U-mode will success. Disable S-mode access to U-mode memory should clear SR_SUM bit. -RISC-V LR/SC pairs could provide a strong/weak forward guarantee that depends on micro-architecture. And RISC-V ISA spec has given out -several limitations to let hardware support strict forward guarantee -(RISC-V User ISA - 8.3 Eventual Success of Store-ConditionalInstructions):We restricted the length of LR/SC loops to fit within 64 contiguous -instruction bytes in the base ISA to avoid undue restrictions on instruction cache and TLB size and associativity. +* v7: [riscv: Add qspinlock support with combo style](https://lore.kernel.org/linux-riscv/20220628081707.1997728-1-guoren@kernel.org/T/#t) -### v4: [RISC-V: Create unique identification for SoC PMU](https://lore.kernel.org/linux-riscv/20220624160117.3206-1-nikita.shubin@maquefel.me/T/#t) + RISC-V LR/SC pairs could provide a strong/weak forward guarantee that depends on micro-architecture. And RISC-V ISA spec has given out several limitations to let hardware support strict forward guarantee (RISC-V User ISA - 8.3 Eventual Success of Store-ConditionalInstructions):We restricted the length of LR/SC loops to fit within 64 contiguous instruction bytes in the base ISA to avoid undue restrictions on instruction cache and TLB size and associativity. -This series aims to provide matching vendor SoC with corresponded JSON bindings.The ID string is proposed to be in form of MVENDORID-MARCHID-MIMPID +* v4: [RISC-V: Create unique identification for SoC PMU](https://lore.kernel.org/linux-riscv/20220624160117.3206-1-nikita.shubin@maquefel.me/T/#t) -### v2: [Add PLIC support for Renesas RZ/Five SoC](https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/T/#t) + This series aims to provide matching vendor SoC with corresponded JSON bindings.The ID string is proposed to be in form of MVENDORID-MARCHID-MIMPID -This patch series adds PLIC support for Renesas RZ/Five SoC.Sending this as an RFC based on the discussion [0].This patches have been tested with -I2C and DMAC interface as these blocks have EDGE interrupts. +* v2: [Add PLIC support for Renesas RZ/Five SoC](https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/T/#t) -### v1: [riscv: atomic: Clean up unnecessary acquire and release definitions](https://lore.kernel.org/linux-riscv/20220625093945.423974-1-guoren@kernel.org/T/#u) + This patch series adds PLIC support for Renesas RZ/Five SoC.Sending this as an RFC based on the discussion [0].This patches have been tested with I2C and DMAC interface as these blocks have EDGE interrupts. -Clean up unnecessary xchg_acquire, xchg_release, and cmpxchg_release custom definitions, because the generic implementation is the same as the -riscv custom implementation. +* v1: [riscv: atomic: Clean up unnecessary acquire and release definitions](https://lore.kernel.org/linux-riscv/20220625093945.423974-1-guoren@kernel.org/T/#u) -### v5: [rtc: microchip: Add driver for PolarFire SoC](https://lore.kernel.org/linux-riscv/165609877582.32831.3964876505949828769.b4-ty@bootlin.com/T/#t) + Clean up unnecessary xchg_acquire, xchg_release, and cmpxchg_release custom definitions, because the generic implementation is the same as the riscv custom implementation. -This is technically a v5 of [0], although a fair bit of time has passed since then. In the meantime I upstreamed the dt-binding, which -was in the v1, and this patch depends on the fixes to the dt-binding and device tree etc which landed in v5.18-rc5. +* v5: [rtc: microchip: Add driver for PolarFire SoC](https://lore.kernel.org/linux-riscv/165609877582.32831.3964876505949828769.b4-ty@bootlin.com/T/#t) -### v2: [RISC-V: fix access beyond allocated array](https://lore.kernel.org/linux-riscv/20220624135902.520748-1-geomatsi@gmail.com/T/#t) + This is technically a v5 of [0], although a fair bit of time has passed since then. In the meantime I upstreamed the dt-binding, which was in the v1, and this patch depends on the fixes to the dt-binding and device tree etc which landed in v5.18-rc5. -These patches suggest some fixes and cleanups for the handling of pmu counters. The first patch fixes access beyond the allocated pmu_ctr_list -array. The second patch fixes the counters mask sent to SBI firmware: it excludes counters that were not fully specified by SBI firmware on init. +* v2: [RISC-V: fix access beyond allocated array](https://lore.kernel.org/linux-riscv/20220624135902.520748-1-geomatsi@gmail.com/T/#t) + + These patches suggest some fixes and cleanups for the handling of pmu counters. The first patch fixes access beyond the allocated pmu_ctr_list array. The second patch fixes the counters mask sent to SBI firmware: it excludes counters that were not fully specified by SBI firmware on init. + +* v6: [riscv: Support qspinlock with generic headers](https://lore.kernel.org/linux-riscv/7adc9e19-7ffc-4b11-3e18-6e3a5225638f@redhat.com/T/#t) + + RISC-V LR/SC pairs could provide a strong/weak forward guarantee that depends on micro-architecture. And RISC-V ISA spec has given out several limitations to let hardware support strict forward guarantee (RISC-V User ISA - 8.3 Eventual Success of Store-Conditional Instructions) + +* v1: [RISC-V: KVM: Improve ISA extension by using a bitmap](https://lore.kernel.org/linux-riscv/20220620234254.2610040-1-atishp@rivosinc.com/T/#u) + + Using a bitmap allows the ISA extension to support any number of extensions. The CONFIG one reg interface implementation is modified to support the bitmap as well. + +### 周边技术动态 + +#### Qemu + +* v9: [QEMU RISC-V nested virtualization fixes](https://lore.kernel.org/qemu-devel/CAAhSdy2iTPwqzUAhV8s97k1d4sK-bne1z-T6pg__p3xfsUrdHg@mail.gmail.com/) + + This series does fixes and improvements to have nested virtualization on QEMU RISC-V. The RISC-V nested virtualization was tested on QEMU RISC-V using Xvisor RISC-V which has required hypervisor support to run another hypervisor as Guest/VM. + +* v9：[target/riscv: Force disable extensions if priv spec version does not match ](https://lore.kernel.org/qemu-devel/20220630061150.905174-3-apatel@ventanamicro.com/) + + We should disable extensions in riscv_cpu_realize() if minimum required priv spec version is not satisfied. This also ensures that machines with priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter extensions. + +* v10：[target/riscv: Add sscofpmf extension support](https://lore.kernel.org/qemu-devel/20220620231603.2547260-9-atishp@rivosinc.com/) + + The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) extension allows the perf to handle overflow interrupts and filtering support. + +#### Bulidroot + +* v2: [board: Add Sipeed MAIX-Go board support](https://lore.kernel.org/buildroot/20220530033836.474926-11-damien.lemoal@opensource.wdc.com/) + + Add two buildroot configuration files to build a minimal Linux environment for the Sipeed MAIX Bit board. + +* git commit: [configs/qemu_riscv64_nommu_virt_defconfig: new defconfig](https://lore.kernel.org/buildroot/20220607190455.B6C6E869E1@busybox.osuosl.org/) + + Add RISC-V 64-bit nommu defconfig for QEMU virt machine with MMU disabled. Unlike qemu_riscv64_virt, qemu_riscv64_nommu_virt does not use OpenSBI, since the kernel is running in machine mode (M-mode). + +#### Yocto + +* [looking to build meta-riscv based HDMI image for nezha board](https://lore.kernel.org/yocto/8d419e1-2a74-36ee-effe-c3b622ee6195@crashcourse.ca/) + + After finally unpacking my risc-v nezha SBC, i'm trying to download/build an image that will boot to a desktop with as little effort as possible. + +#### U-Boot + +* v2: [cpu: add CPU driver for microblaze](https://lore.kernel.org/u-boot/20220531181435.3473549-14-ovpanait@gmail.com/) + + Add a basic CPU driver that retrieves information about the microblaze CPU core. + +* v3: [valgrind: Disable on Risc-V](https://lore.kernel.org/u-boot/20220527140300.682989-2-seanga2@gmail.com/) + + There are no defined instruction sequences in include/valgrind.h for Risc-V, so CONFIG_VALGRIND will do nothing on this arch. -### v6: [riscv: Support qspinlock with generic headers](https://lore.kernel.org/linux-riscv/7adc9e19-7ffc-4b11-3e18-6e3a5225638f@redhat.com/T/#t) -RISC-V LR/SC pairs could provide a strong/weak forward guarantee that depends on micro-architecture. And RISC-V ISA spec has given out several -limitations to let hardware support strict forward guarantee (RISC-V User ISA - 8.3 Eventual Success of Store-Conditional Instructions) -### v1: [RISC-V: KVM: Improve ISA extension by using a bitmap](https://lore.kernel.org/linux-riscv/20220620234254.2610040-1-atishp@rivosinc.com/T/#u) -Using a bitmap allows the ISA extension to support any number of extensions. The CONFIG one reg interface implementation is modified to support the -bitmap as well.