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+# RISV-V Linux 内核技术动态
+
+## 20220630 :第一期
+
+### [riscv: implement Zicbom-based CMO instructions + the t-head variant](https://lore.kernel.org/linux-riscv/20220629215944.397952-1-heiko@sntech.de/T/#t)
+
+It implements using the cache-management instructions from the  Zicbom-extension to handle cache flush, etc actions on platforms needing them. 
+
+### [riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit](https://lore.kernel.org/linux-riscv/11a0698c-5726-15e8-2448-3529d2d0b098@huawei.com/T/#t)
+
+Since commit 5d8544e2d007 ("RISC-V: Generic library routines and assembly")
+and commit ebcbd75e3962 ("riscv: Fix the bug in memory access fixup code"),
+if __clear_user and __copy_user return from an fixup branch, CSR_STATUS SR_SUM bit will be set, it is a vulnerability, so that
+S-mode memory accesses to pages that are accessible by U-mode will success. Disable S-mode access to U-mode memory should clear SR_SUM bit.
+
+### [riscv: Add qspinlock support with combo style](https://lore.kernel.org/linux-riscv/20220628081707.1997728-1-guoren@kernel.org/T/#t)
+
+RISC-V LR/SC pairs could provide a strong/weak forward guarantee that depends on micro-architecture. And RISC-V ISA spec has given out
+several limitations to let hardware support strict forward guarantee
+(RISC-V User ISA - 8.3 Eventual Success of Store-ConditionalInstructions):We restricted the length of LR/SC loops to fit within 64 contiguous 
+instruction bytes in the base ISA to avoid undue restrictions on instruction cache and TLB size and associativity.
+
+### [RISC-V: Create unique identification for SoC PMU](https://lore.kernel.org/linux-riscv/20220624160117.3206-1-nikita.shubin@maquefel.me/T/#t)
+
+This series aims to provide matching vendor SoC with corresponded JSON bindings.The ID string is proposed to be in form of MVENDORID-MARCHID-MIMPID
+
+### [Add PLIC support for Renesas RZ/Five SoC](https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/T/#t)
+
+This patch series adds PLIC support for Renesas RZ/Five SoC.Sending this as an RFC based on the discussion [0].This patches have been tested with
+I2C and DMAC interface as these blocks have EDGE interrupts.
+
+### [riscv: atomic: Clean up unnecessary acquire and release definitions](https://lore.kernel.org/linux-riscv/20220625093945.423974-1-guoren@kernel.org/T/#u)
+
+Clean up unnecessary xchg_acquire, xchg_release, and cmpxchg_release custom definitions, because the generic implementation is the same as the
+riscv custom implementation.
+
+### [rtc: microchip: Add driver for PolarFire SoC](https://lore.kernel.org/linux-riscv/165609877582.32831.3964876505949828769.b4-ty@bootlin.com/T/#t)
+
+This is technically a v5 of [0], although a fair bit of time has passed since then. In the meantime I upstreamed the dt-binding, which
+was in the v1, and this patch depends on the fixes to the dt-binding and device tree etc which landed in v5.18-rc5.
+
+### [RISC-V: fix access beyond allocated array](https://lore.kernel.org/linux-riscv/20220624135902.520748-1-geomatsi@gmail.com/T/#t)
+
+These patches suggest some fixes and cleanups for the handling of pmu counters. The first patch fixes access beyond the allocated pmu_ctr_list  
+array. The second patch fixes the counters mask sent to SBI firmware: it excludes counters that were not fully specified by SBI firmware on init.
+
+### [riscv: Support qspinlock with generic headers](https://lore.kernel.org/linux-riscv/7adc9e19-7ffc-4b11-3e18-6e3a5225638f@redhat.com/T/#t)
+
+RISC-V LR/SC pairs could provide a strong/weak forward guarantee that depends on micro-architecture. And RISC-V ISA spec has given out several 
+limitations to let hardware support strict forward guarantee (RISC-V User ISA - 8.3 Eventual Success of Store-Conditional Instructions)
+
+### [RISC-V: KVM: Improve ISA extension by using a bitmap](https://lore.kernel.org/linux-riscv/20220620234254.2610040-1-atishp@rivosinc.com/T/#u)
+
+Using a bitmap allows the ISA extension to support any number of extensions. The CONFIG one reg interface implementation is modified to support the 
+bitmap as well.