diff --git a/0007-enable-unaligned-access-optimizations-for-RISC-V-wit.patch b/0007-enable-unaligned-access-optimizations-for-RISC-V-wit.patch
new file mode 100644
index 0000000000000000000000000000000000000000..ba88baf35f5779cb793f7ea171727f58abc33072
--- /dev/null
+++ b/0007-enable-unaligned-access-optimizations-for-RISC-V-wit.patch
@@ -0,0 +1,83 @@
+From f6617cae8d463a532781732e0ba5356cc9bc2acf Mon Sep 17 00:00:00 2001
+From: huangshangcheng <huang.shangcheng@zte.com.cn>
+Date: Wed, 12 Nov 2025 16:56:56 +0800
+Subject: [PATCH] enable unaligned access optimizations for RISC-V with Zicclsm
+
+While reviewing the Redis code, we discovered that optimizations 
+for unaligned memory accesses are not enabled on RISC-V. After 
+testing siphash separately, we found some performance improvements 
+in this area and hope to add them.
+
+The zicclsm extension, which includes unaligned memory accesses, 
+is required on RISC-V, as specified in the RVA20U64 specification. 
+GCC also provides the macro zicclsm to detect the zicclsm extension.
+
+Supported versions: GCC 14.1.0 and above
+
+Test data
+Test Configuration​​
+​​Test Iterations:​​ 10,000,000 hashes per run
+Test Runs:​​ 10 consecutive runs
+
+Improvement
+6482733.40 --> 10732524.90 (​​+65.5%​)
+
+Disable UNALIGNED_LE_CPU
+
+Running performance test (10 runs)...
+Run 1: 6491958.63 hashes/sec
+Run 2: 6487366.83 hashes/sec
+Run 3: 6481576.94 hashes/sec
+Run 4: 6484129.18 hashes/sec
+Run 5: 6486451.34 hashes/sec
+Run 6: 6476159.22 hashes/sec
+Run 7: 6479075.32 hashes/sec
+Run 8: 6476821.02 hashes/sec
+Run 9: 6482822.05 hashes/sec
+Run 10: 6480973.47 hashes/sec
+
+Average performance: 6482733.40 hashes/sec
+
+Enable UNALIGNED_LE_CPU
+
+Running performance test (10 runs)...
+Run 1: 10724141.20 hashes/sec
+Run 2: 10736134.67 hashes/sec
+Run 3: 10733149.45 hashes/sec
+Run 4: 10732901.09 hashes/sec
+Run 5: 10731710.56 hashes/sec
+Run 6: 10734029.89 hashes/sec
+Run 7: 10733342.07 hashes/sec
+Run 8: 10732782.90 hashes/sec
+Run 9: 10733797.15 hashes/sec
+Run 10: 10733260.05 hashes/sec
+
+Average performance: 10732524.90 hashes/sec
+
+Signed-off-by: lanjing <lan.jing3@zte.com.cn>
+---
+ src/siphash.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/src/siphash.c b/src/siphash.c
+index 2713d89..721b34b 100644
+--- a/src/siphash.c
++++ b/src/siphash.c
+@@ -67,9 +67,12 @@ int siptlw(int c) {
+ 
+ /* Test of the CPU is Little Endian and supports not aligned accesses.
+  * Two interesting conditions to speedup the function that happen to be
+- * in most of x86 servers. */
++ * in most of x86 servers.
++ * Additionally supports RISC-V CPUs implementing the Zicclsm extension
++ * for unaligned access. */
+ #if defined(__X86_64__) || defined(__x86_64__) || defined (__i386__) \
+-	|| defined (__aarch64__) || defined (__arm64__)
++	|| defined (__aarch64__) || defined (__arm64__) \
++    || (defined(__riscv) && defined(__riscv_zicclsm))
+ #define UNALIGNED_LE_CPU
+ #endif
+ 
+-- 
+2.45.2.windows.1
+
diff --git a/redis.spec b/redis.spec
index e107dd73b8cf69942ad51f7975096380164753eb..48cfbf9ec3e8a89ddce9ea96a99588a8f49fa35a 100644
--- a/redis.spec
+++ b/redis.spec
@@ -1,4 +1,4 @@
-%define anolis_release 3
+%define anolis_release 4
 
 # temp workaround to https://bugzilla.redhat.com/2059488
 %undefine _package_note_file
@@ -37,6 +37,7 @@ Patch0004:         0004-Fix-CVE-2025-46819.patch
 # https://github.com/redis/redis/commit/fc9abc775e308374f667fdf3e723ef4b7eb0e3ca
 Patch0005:         0005-Fix-CVE-2025-46817.patch
 Patch0006:         0006-bugfix-for-CVE-2025-49844.patch
+Patch0007:         0007-enable-unaligned-access-optimizations-for-RISC-V-wit.patch
 
 BuildRequires: make
 BuildRequires:     gcc
@@ -125,6 +126,7 @@ mv ../%{name}-doc-%{doc_commit} doc
 %patch -P0003 -p1
 %patch -P0004 -p1
 %patch -P0005 -p1
+%patch -P0007 -p1
 
 mv deps/lua/COPYRIGHT             COPYRIGHT-lua
 mv deps/jemalloc/COPYING          COPYING-jemalloc
@@ -299,6 +301,9 @@ fi
 
 
 %changelog
+* Wed Nov 12 2025 Lan Jing <lan.jing3@zte.com.cn> - 7.2.10-4
+- Added support for unaligned access optimizations on RISC-V with Zicclsm extension.
+
 * Sat Nov 01 2025 tomcruiseqi <tomcruiseqi@inspur.com> - 7.2.10-3
 - Fix CVE-2025-49844