From cfbf518df4a841c73e6a6206d42947f361fbef75 Mon Sep 17 00:00:00 2001 From: wh02252983 Date: Thu, 9 Oct 2025 11:06:38 +0800 Subject: [PATCH] RISC-V: ACPI: Enable AIA and update RHCT and update hct device, to support latest HCT version (HCT2.1) Signed-off-by: wh02252983 --- ...-build-c-migrate-fw-cfg-creation-to-.patch | 180 +++++++++++++ ...-build-c-migrate-virtio-creation-to-.patch | 158 ++++++++++++ ...rovm-c-use-common-function-to-add-vi.patch | 57 +++++ ...ke-few-imsic-macros-and-functions-pu.patch | 116 +++++++++ ...cpi-build-c-add-aia-support-in-rintc.patch | 114 +++++++++ ...t-acpi-build-c-add-imsic-in-the-madt.patch | 76 ++++++ ...t-acpi-build-c-add-aplic-in-the-madt.patch | 76 ++++++ ...pi-build-c-add-cmo-information-in-rh.patch | 131 ++++++++++ ...rt-acpi-build-c-add-mmu-node-in-rhct.patch | 102 ++++++++ ...ex-define-properties-for-mmio-ranges.patch | 126 ++++++++++ ...-update-gpex-mmio-related-properties.patch | 117 +++++++++ ...pi-build-c-add-io-controllers-and-de.patch | 159 ++++++++++++ ...v-virt-acpi-build-c-add-plic-in-madt.patch | 72 ++++++ ...fix-the-interrupts-extended-property.patch | 92 +++++++ ...pi-build-c-add-namespace-devices-for.patch | 78 ++++++ ...pi-build-c-update-the-hid-of-risc-v-.patch | 40 +++ ...-pci-link-devices-outside-pci-root-b.patch | 94 +++++++ ...-build-c-migrate-spcr-creation-to-co.patch | 238 ++++++++++++++++++ ...irt-acpi-build-c-generate-spcr-table.patch | 78 ++++++ ...gainst-rop-exploits-with-fzero-call-.patch | 133 ++++++++++ ...gainst-use-of-uninitialize-stack-for.patch | 65 +++++ ...ing-ccp-resources-between-host-and-v.patch | 186 ++++++++++++++ ...atible-with-hct-ko-modules-in-versio.patch | 105 ++++++++ ...ccp-index-error-caused-by-uninitiali.patch | 36 +++ ...ve-the-operation-of-reading-the-valu.patch | 131 ++++++++++ qemu.spec | 31 ++- 26 files changed, 2790 insertions(+), 1 deletion(-) create mode 100644 0498-hw-arm-virt-acpi-build-c-migrate-fw-cfg-creation-to-.patch create mode 100644 0499-hw-arm-virt-acpi-build-c-migrate-virtio-creation-to-.patch create mode 100644 0500-hw-i386-acpi-microvm-c-use-common-function-to-add-vi.patch create mode 100644 0501-hw-riscv-virt-make-few-imsic-macros-and-functions-pu.patch create mode 100644 0502-hw-riscv-virt-acpi-build-c-add-aia-support-in-rintc.patch create mode 100644 0503-hw-riscv-virt-acpi-build-c-add-imsic-in-the-madt.patch create mode 100644 0504-hw-riscv-virt-acpi-build-c-add-aplic-in-the-madt.patch create mode 100644 0505-hw-riscv-virt-acpi-build-c-add-cmo-information-in-rh.patch create mode 100644 0506-hw-riscv-virt-acpi-build-c-add-mmu-node-in-rhct.patch create mode 100644 0507-hw-pci-host-gpex-define-properties-for-mmio-ranges.patch create mode 100644 0508-hw-riscv-virt-update-gpex-mmio-related-properties.patch create mode 100644 0509-hw-riscv-virt-acpi-build-c-add-io-controllers-and-de.patch create mode 100644 0510-hw-riscv-virt-acpi-build-c-add-plic-in-madt.patch create mode 100644 0511-hw-riscv-virt-c-fix-the-interrupts-extended-property.patch create mode 100644 0512-hw-riscv-virt-acpi-build-c-add-namespace-devices-for.patch create mode 100644 0513-hw-riscv-virt-acpi-build-c-update-the-hid-of-risc-v-.patch create mode 100644 0514-acpi-gpex-create-pci-link-devices-outside-pci-root-b.patch create mode 100644 0515-hw-arm-virt-acpi-build-c-migrate-spcr-creation-to-co.patch create mode 100644 0516-hw-riscv-virt-acpi-build-c-generate-spcr-table.patch create mode 100644 0517-meson-mitigate-against-rop-exploits-with-fzero-call-.patch create mode 100644 0518-meson-mitigate-against-use-of-uninitialize-stack-for.patch create mode 100644 0519-hw-vfio-hct-sharing-ccp-resources-between-host-and-v.patch create mode 100644 0520-hw-vfio-hct-compatible-with-hct-ko-modules-in-versio.patch create mode 100644 0521-hw-vfio-hct-fix-ccp-index-error-caused-by-uninitiali.patch create mode 100644 0522-hw-vfio-hct-remove-the-operation-of-reading-the-valu.patch diff --git a/0498-hw-arm-virt-acpi-build-c-migrate-fw-cfg-creation-to-.patch b/0498-hw-arm-virt-acpi-build-c-migrate-fw-cfg-creation-to-.patch new file mode 100644 index 0000000..fb3d7ba --- /dev/null +++ b/0498-hw-arm-virt-acpi-build-c-migrate-fw-cfg-creation-to-.patch @@ -0,0 +1,180 @@ +From fc0151fd8fb5392a11270d323dcf41fb6dcfaf5b Mon Sep 17 00:00:00 2001 +From: Sunil V L +Date: Mon, 18 Dec 2023 20:32:35 +0530 +Subject: [PATCH] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common + location + +commit 4c7f4f4f0516ad1bad45b011235202f5be6899de upstream + +RISC-V also needs to use the same code to create fw_cfg in DSDT. So, +avoid code duplication by moving the code in arm and riscv to a device +specific file. + +Suggested-by: Igor Mammedov +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Reviewed-by: Alistair Francis +Reviewed-by: Andrew Jones +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-2-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/arm/virt-acpi-build.c | 19 ++----------------- + hw/nvram/fw_cfg-acpi.c | 23 +++++++++++++++++++++++ + hw/nvram/meson.build | 1 + + hw/riscv/virt-acpi-build.c | 19 ++----------------- + include/hw/nvram/fw_cfg_acpi.h | 15 +++++++++++++++ + 5 files changed, 43 insertions(+), 34 deletions(-) + create mode 100644 hw/nvram/fw_cfg-acpi.c + create mode 100644 include/hw/nvram/fw_cfg_acpi.h + +diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c +index 8bc35a483c..565af9b7ea 100644 +--- a/hw/arm/virt-acpi-build.c ++++ b/hw/arm/virt-acpi-build.c +@@ -35,7 +35,7 @@ + #include "target/arm/cpu.h" + #include "hw/acpi/acpi-defs.h" + #include "hw/acpi/acpi.h" +-#include "hw/nvram/fw_cfg.h" ++#include "hw/nvram/fw_cfg_acpi.h" + #include "hw/acpi/bios-linker-loader.h" + #include "hw/acpi/aml-build.h" + #include "hw/acpi/utils.h" +@@ -94,21 +94,6 @@ static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, + aml_append(scope, dev); + } + +-static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) +-{ +- Aml *dev = aml_device("FWCF"); +- aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); +- /* device present, functioning, decoding, not shown in UI */ +- aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); +- aml_append(dev, aml_name_decl("_CCA", aml_int(1))); +- +- Aml *crs = aml_resource_template(); +- aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, +- fw_cfg_memmap->size, AML_READ_WRITE)); +- aml_append(dev, aml_name_decl("_CRS", crs)); +- aml_append(scope, dev); +-} +- + static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) + { + Aml *dev, *crs; +@@ -864,7 +849,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) + if (vmc->acpi_expose_flash) { + acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); + } +- acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); ++ fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); + acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], + (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); + acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms); +diff --git a/hw/nvram/fw_cfg-acpi.c b/hw/nvram/fw_cfg-acpi.c +new file mode 100644 +index 0000000000..4e48baeaa0 +--- /dev/null ++++ b/hw/nvram/fw_cfg-acpi.c +@@ -0,0 +1,23 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Add fw_cfg device in DSDT ++ * ++ */ ++ ++#include "hw/nvram/fw_cfg_acpi.h" ++#include "hw/acpi/aml-build.h" ++ ++void fw_cfg_acpi_dsdt_add(Aml *scope, const MemMapEntry *fw_cfg_memmap) ++{ ++ Aml *dev = aml_device("FWCF"); ++ aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); ++ /* device present, functioning, decoding, not shown in UI */ ++ aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); ++ aml_append(dev, aml_name_decl("_CCA", aml_int(1))); ++ ++ Aml *crs = aml_resource_template(); ++ aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, ++ fw_cfg_memmap->size, AML_READ_WRITE)); ++ aml_append(dev, aml_name_decl("_CRS", crs)); ++ aml_append(scope, dev); ++} +diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build +index 75e415b1a0..4996c72456 100644 +--- a/hw/nvram/meson.build ++++ b/hw/nvram/meson.build +@@ -17,3 +17,4 @@ system_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files( + system_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c')) + + specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c')) ++specific_ss.add(when: 'CONFIG_ACPI', if_true: files('fw_cfg-acpi.c')) +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 171d56a6ad..2b069b8e2d 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -28,6 +28,7 @@ + #include "hw/acpi/acpi.h" + #include "hw/acpi/aml-build.h" + #include "hw/acpi/utils.h" ++#include "hw/nvram/fw_cfg_acpi.h" + #include "qapi/error.h" + #include "qemu/error-report.h" + #include "sysemu/reset.h" +@@ -97,22 +98,6 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) + } + } + +-static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) +-{ +- Aml *dev = aml_device("FWCF"); +- aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); +- +- /* device present, functioning, decoding, not shown in UI */ +- aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); +- aml_append(dev, aml_name_decl("_CCA", aml_int(1))); +- +- Aml *crs = aml_resource_template(); +- aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, +- fw_cfg_memmap->size, AML_READ_WRITE)); +- aml_append(dev, aml_name_decl("_CRS", crs)); +- aml_append(scope, dev); +-} +- + /* RHCT Node[N] starts at offset 56 */ + #define RHCT_NODE_ARRAY_OFFSET 56 + +@@ -226,7 +211,7 @@ static void build_dsdt(GArray *table_data, + scope = aml_scope("\\_SB"); + acpi_dsdt_add_cpus(scope, s); + +- acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); ++ fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); + + aml_append(dsdt, scope); + +diff --git a/include/hw/nvram/fw_cfg_acpi.h b/include/hw/nvram/fw_cfg_acpi.h +new file mode 100644 +index 0000000000..b6553d86fc +--- /dev/null ++++ b/include/hw/nvram/fw_cfg_acpi.h +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * ACPI support for fw_cfg ++ * ++ */ ++ ++#ifndef FW_CFG_ACPI_H ++#define FW_CFG_ACPI_H ++ ++#include "qemu/osdep.h" ++#include "exec/hwaddr.h" ++ ++void fw_cfg_acpi_dsdt_add(Aml *scope, const MemMapEntry *fw_cfg_memmap); ++ ++#endif +-- +2.39.3 + diff --git a/0499-hw-arm-virt-acpi-build-c-migrate-virtio-creation-to-.patch b/0499-hw-arm-virt-acpi-build-c-migrate-virtio-creation-to-.patch new file mode 100644 index 0000000..58f9b81 --- /dev/null +++ b/0499-hw-arm-virt-acpi-build-c-migrate-virtio-creation-to-.patch @@ -0,0 +1,158 @@ +From b865948851afc3d1ff8e126131e7303dec153220 Mon Sep 17 00:00:00 2001 +From: Sunil V L +Date: Mon, 18 Dec 2023 20:32:36 +0530 +Subject: [PATCH] hw/arm/virt-acpi-build.c: Migrate virtio creation to common + location + +commit 57ba8436282940b59d9a069cc01a601bbc8036c5 upstream + +RISC-V also needs to create the virtio in DSDT in the same way as ARM. +So, instead of duplicating the code, move this function to the device +specific file which is common across architectures. + +Suggested-by: Igor Mammedov +Signed-off-by: Sunil V L +Reviewed-by: Alistair Francis +Reviewed-by: Andrew Jones +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-3-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/arm/virt-acpi-build.c | 32 ++++---------------------------- + hw/virtio/meson.build | 1 + + hw/virtio/virtio-acpi.c | 33 +++++++++++++++++++++++++++++++++ + include/hw/virtio/virtio-acpi.h | 16 ++++++++++++++++ + 4 files changed, 54 insertions(+), 28 deletions(-) + create mode 100644 hw/virtio/virtio-acpi.c + create mode 100644 include/hw/virtio/virtio-acpi.h + +diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c +index 565af9b7ea..510ab0dcca 100644 +--- a/hw/arm/virt-acpi-build.c ++++ b/hw/arm/virt-acpi-build.c +@@ -58,6 +58,7 @@ + #include "migration/vmstate.h" + #include "hw/acpi/ghes.h" + #include "hw/acpi/viot.h" ++#include "hw/virtio/virtio-acpi.h" + + #define ARM_SPI_BASE 32 + +@@ -118,32 +119,6 @@ static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) + aml_append(scope, dev); + } + +-static void acpi_dsdt_add_virtio(Aml *scope, +- const MemMapEntry *virtio_mmio_memmap, +- uint32_t mmio_irq, int num) +-{ +- hwaddr base = virtio_mmio_memmap->base; +- hwaddr size = virtio_mmio_memmap->size; +- int i; +- +- for (i = 0; i < num; i++) { +- uint32_t irq = mmio_irq + i; +- Aml *dev = aml_device("VR%02u", i); +- aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); +- aml_append(dev, aml_name_decl("_UID", aml_int(i))); +- aml_append(dev, aml_name_decl("_CCA", aml_int(1))); +- +- Aml *crs = aml_resource_template(); +- aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); +- aml_append(crs, +- aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, +- AML_EXCLUSIVE, &irq, 1)); +- aml_append(dev, aml_name_decl("_CRS", crs)); +- aml_append(scope, dev); +- base += size; +- } +-} +- + static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, + uint32_t irq, VirtMachineState *vms) + { +@@ -850,8 +825,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) + acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); + } + fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); +- acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], +- (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); ++ virtio_acpi_dsdt_add(scope, memmap[VIRT_MMIO].base, memmap[VIRT_MMIO].size, ++ (irqmap[VIRT_MMIO] + ARM_SPI_BASE), ++ 0, NUM_VIRTIO_TRANSPORTS); + acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms); + if (vms->acpi_dev) { + build_ged_aml(scope, "\\_SB."GED_DEVICE, +diff --git a/hw/virtio/meson.build b/hw/virtio/meson.build +index c0055a7832..9d62097a21 100644 +--- a/hw/virtio/meson.build ++++ b/hw/virtio/meson.build +@@ -79,3 +79,4 @@ system_ss.add(when: 'CONFIG_ALL', if_true: files('virtio-stub.c')) + system_ss.add(files('virtio-hmp-cmds.c')) + + specific_ss.add_all(when: 'CONFIG_VIRTIO', if_true: specific_virtio_ss) ++system_ss.add(when: 'CONFIG_ACPI', if_true: files('virtio-acpi.c')) +diff --git a/hw/virtio/virtio-acpi.c b/hw/virtio/virtio-acpi.c +new file mode 100644 +index 0000000000..e18cb38bdb +--- /dev/null ++++ b/hw/virtio/virtio-acpi.c +@@ -0,0 +1,33 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * virtio ACPI Support ++ * ++ */ ++ ++#include "hw/virtio/virtio-acpi.h" ++#include "hw/acpi/aml-build.h" ++ ++void virtio_acpi_dsdt_add(Aml *scope, const hwaddr base, const hwaddr size, ++ uint32_t mmio_irq, long int start_index, int num) ++{ ++ hwaddr virtio_base = base; ++ uint32_t irq = mmio_irq; ++ long int i; ++ ++ for (i = start_index; i < start_index + num; i++) { ++ Aml *dev = aml_device("VR%02u", (unsigned)i); ++ aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); ++ aml_append(dev, aml_name_decl("_UID", aml_int(i))); ++ aml_append(dev, aml_name_decl("_CCA", aml_int(1))); ++ ++ Aml *crs = aml_resource_template(); ++ aml_append(crs, aml_memory32_fixed(virtio_base, size, AML_READ_WRITE)); ++ aml_append(crs, ++ aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, ++ AML_EXCLUSIVE, &irq, 1)); ++ aml_append(dev, aml_name_decl("_CRS", crs)); ++ aml_append(scope, dev); ++ virtio_base += size; ++ irq++; ++ } ++} +diff --git a/include/hw/virtio/virtio-acpi.h b/include/hw/virtio/virtio-acpi.h +new file mode 100644 +index 0000000000..844e102569 +--- /dev/null ++++ b/include/hw/virtio/virtio-acpi.h +@@ -0,0 +1,16 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * ACPI support for virtio ++ */ ++ ++#ifndef VIRTIO_ACPI_H ++#define VIRTIO_ACPI_H ++ ++#include "qemu/osdep.h" ++#include "exec/hwaddr.h" ++ ++void virtio_acpi_dsdt_add(Aml *scope, const hwaddr virtio_mmio_base, ++ const hwaddr virtio_mmio_size, uint32_t mmio_irq, ++ long int start_index, int num); ++ ++#endif +-- +2.39.3 + diff --git a/0500-hw-i386-acpi-microvm-c-use-common-function-to-add-vi.patch b/0500-hw-i386-acpi-microvm-c-use-common-function-to-add-vi.patch new file mode 100644 index 0000000..c04a814 --- /dev/null +++ b/0500-hw-i386-acpi-microvm-c-use-common-function-to-add-vi.patch @@ -0,0 +1,57 @@ +From 3c56e8e34a7d119360097ad416e68107769b5315 Mon Sep 17 00:00:00 2001 +From: Sunil V L +Date: Mon, 18 Dec 2023 20:32:37 +0530 +Subject: [PATCH] hw/i386/acpi-microvm.c: Use common function to add virtio in + DSDT + +commit 8199bf48ea1fdb8e491311a0dc28cea30af18c95 upstream + +With common function to add virtio in DSDT created now, update microvm +code also to use it instead of duplicate code. + +Suggested-by: Andrew Jones +Signed-off-by: Sunil V L +Acked-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-4-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/i386/acpi-microvm.c | 15 ++------------- + 1 file changed, 2 insertions(+), 13 deletions(-) + +diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c +index 2909a73933..279da6b4aa 100644 +--- a/hw/i386/acpi-microvm.c ++++ b/hw/i386/acpi-microvm.c +@@ -37,6 +37,7 @@ + #include "hw/pci/pci.h" + #include "hw/pci/pcie_host.h" + #include "hw/usb/xhci.h" ++#include "hw/virtio/virtio-acpi.h" + #include "hw/virtio/virtio-mmio.h" + #include "hw/input/i8042.h" + +@@ -77,19 +78,7 @@ static void acpi_dsdt_add_virtio(Aml *scope, + uint32_t irq = mms->virtio_irq_base + index; + hwaddr base = VIRTIO_MMIO_BASE + index * 512; + hwaddr size = 512; +- +- Aml *dev = aml_device("VR%02u", (unsigned)index); +- aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); +- aml_append(dev, aml_name_decl("_UID", aml_int(index))); +- aml_append(dev, aml_name_decl("_CCA", aml_int(1))); +- +- Aml *crs = aml_resource_template(); +- aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); +- aml_append(crs, +- aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, +- AML_EXCLUSIVE, &irq, 1)); +- aml_append(dev, aml_name_decl("_CRS", crs)); +- aml_append(scope, dev); ++ virtio_acpi_dsdt_add(scope, base, size, irq, index, 1); + } + } + } +-- +2.39.3 + diff --git a/0501-hw-riscv-virt-make-few-imsic-macros-and-functions-pu.patch b/0501-hw-riscv-virt-make-few-imsic-macros-and-functions-pu.patch new file mode 100644 index 0000000..17ab944 --- /dev/null +++ b/0501-hw-riscv-virt-make-few-imsic-macros-and-functions-pu.patch @@ -0,0 +1,116 @@ +From 79ed39477457711226e14b3867960cda37617839 Mon Sep 17 00:00:00 2001 +From: Sunil V L +Date: Mon, 18 Dec 2023 20:32:38 +0530 +Subject: [PATCH] hw/riscv: virt: Make few IMSIC macros and functions public + +commit 68c8b403c78b8f20acbebba3cdc46320853fe5ca upstream + +Some macros and static function related to IMSIC are defined in virt.c. +They are required in virt-acpi-build.c. So, make them public. + +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Reviewed-by: Alistair Francis +Reviewed-by: Andrew Jones +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-5-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt.c | 25 +------------------------ + include/hw/riscv/virt.h | 25 +++++++++++++++++++++++++ + 2 files changed, 26 insertions(+), 24 deletions(-) + +diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c +index 9b29ed1108..30b9f8cab6 100644 +--- a/hw/riscv/virt.c ++++ b/hw/riscv/virt.c +@@ -39,7 +39,6 @@ + #include "hw/firmware/smbios.h" + #include "hw/intc/riscv_aclint.h" + #include "hw/intc/riscv_aplic.h" +-#include "hw/intc/riscv_imsic.h" + #include "hw/intc/sifive_plic.h" + #include "hw/misc/sifive_test.h" + #include "hw/platform-bus.h" +@@ -55,28 +54,6 @@ + #include "hw/acpi/aml-build.h" + #include "qapi/qapi-visit-common.h" + +-/* +- * The virt machine physical address space used by some of the devices +- * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, +- * number of CPUs, and number of IMSIC guest files. +- * +- * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, +- * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization +- * of virt machine physical address space. +- */ +- +-#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) +-#if VIRT_IMSIC_GROUP_MAX_SIZE < \ +- IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) +-#error "Can't accommodate single IMSIC group in address space" +-#endif +- +-#define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ +- VIRT_IMSIC_GROUP_MAX_SIZE) +-#if 0x4000000 < VIRT_IMSIC_MAX_SIZE +-#error "Can't accommodate all IMSIC groups in address space" +-#endif +- + /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ + static bool virt_use_kvm_aia(RISCVVirtState *s) + { +@@ -513,7 +490,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s, + g_free(plic_cells); + } + +-static uint32_t imsic_num_bits(uint32_t count) ++uint32_t imsic_num_bits(uint32_t count) + { + uint32_t ret = 0; + +diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h +index e5c474b26e..5b03575ed3 100644 +--- a/include/hw/riscv/virt.h ++++ b/include/hw/riscv/virt.h +@@ -23,6 +23,7 @@ + #include "hw/riscv/riscv_hart.h" + #include "hw/sysbus.h" + #include "hw/block/flash.h" ++#include "hw/intc/riscv_imsic.h" + + #define VIRT_CPUS_MAX_BITS 9 + #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) +@@ -127,4 +128,28 @@ enum { + + bool virt_is_acpi_enabled(RISCVVirtState *s); + void virt_acpi_setup(RISCVVirtState *vms); ++uint32_t imsic_num_bits(uint32_t count); ++ ++/* ++ * The virt machine physical address space used by some of the devices ++ * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, ++ * number of CPUs, and number of IMSIC guest files. ++ * ++ * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, ++ * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization ++ * of virt machine physical address space. ++ */ ++ ++#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) ++#if VIRT_IMSIC_GROUP_MAX_SIZE < \ ++ IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) ++#error "Can't accomodate single IMSIC group in address space" ++#endif ++ ++#define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ ++ VIRT_IMSIC_GROUP_MAX_SIZE) ++#if 0x4000000 < VIRT_IMSIC_MAX_SIZE ++#error "Can't accomodate all IMSIC groups in address space" ++#endif ++ + #endif +-- +2.39.3 + diff --git a/0502-hw-riscv-virt-acpi-build-c-add-aia-support-in-rintc.patch b/0502-hw-riscv-virt-acpi-build-c-add-aia-support-in-rintc.patch new file mode 100644 index 0000000..b5001bd --- /dev/null +++ b/0502-hw-riscv-virt-acpi-build-c-add-aia-support-in-rintc.patch @@ -0,0 +1,114 @@ +From 97f5720c3d433c95d213f7e27206a43bec216935 Mon Sep 17 00:00:00 2001 +From: Sunil V L +Date: Mon, 18 Dec 2023 20:32:39 +0530 +Subject: [PATCH] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC + +commit 0efb12b713338e2be713b689d1c9743f7163f85d upstream + +Update the RINTC structure in MADT with AIA related fields. + +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Acked-by: Alistair Francis +Reviewed-by: Andrew Jones +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-6-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt-acpi-build.c | 43 ++++++++++++++++++++++++++++++++++---- + 1 file changed, 39 insertions(+), 4 deletions(-) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 2b069b8e2d..1f6c188f7d 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -38,6 +38,7 @@ + #include "hw/intc/riscv_aclint.h" + + #define ACPI_BUILD_TABLE_SIZE 0x20000 ++#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index)) + + typedef struct AcpiBuildState { + /* Copy of table in RAM (for patching) */ +@@ -59,17 +60,50 @@ static void acpi_align_size(GArray *blob, unsigned align) + + static void riscv_acpi_madt_add_rintc(uint32_t uid, + const CPUArchIdList *arch_ids, +- GArray *entry) ++ GArray *entry, ++ RISCVVirtState *s) + { ++ uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1); + uint64_t hart_id = arch_ids->cpus[uid].arch_id; ++ uint32_t imsic_size, local_cpu_id, socket_id; ++ uint64_t imsic_socket_addr, imsic_addr; ++ MachineState *ms = MACHINE(s); + ++ socket_id = arch_ids->cpus[uid].props.node_id; ++ local_cpu_id = (arch_ids->cpus[uid].arch_id - ++ riscv_socket_first_hartid(ms, socket_id)) % ++ riscv_socket_hart_count(ms, socket_id); ++ imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base + ++ (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE); ++ imsic_size = IMSIC_HART_SIZE(guest_index_bits); ++ imsic_addr = imsic_socket_addr + local_cpu_id * imsic_size; + build_append_int_noprefix(entry, 0x18, 1); /* Type */ +- build_append_int_noprefix(entry, 20, 1); /* Length */ ++ build_append_int_noprefix(entry, 36, 1); /* Length */ + build_append_int_noprefix(entry, 1, 1); /* Version */ + build_append_int_noprefix(entry, 0, 1); /* Reserved */ + build_append_int_noprefix(entry, 0x1, 4); /* Flags */ + build_append_int_noprefix(entry, hart_id, 8); /* Hart ID */ + build_append_int_noprefix(entry, uid, 4); /* ACPI Processor UID */ ++ /* External Interrupt Controller ID */ ++ if (s->aia_type == VIRT_AIA_TYPE_APLIC) { ++ build_append_int_noprefix(entry, ++ ACPI_BUILD_INTC_ID( ++ arch_ids->cpus[uid].props.node_id, ++ local_cpu_id), ++ 4); ++ } else { ++ build_append_int_noprefix(entry, 0, 4); ++ } ++ ++ if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { ++ /* IMSIC Base address */ ++ build_append_int_noprefix(entry, imsic_addr, 8); ++ /* IMSIC Size */ ++ build_append_int_noprefix(entry, imsic_size, 4); ++ } else { ++ build_append_int_noprefix(entry, 0, 8); ++ build_append_int_noprefix(entry, 0, 4); ++ } + } + + static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) +@@ -88,7 +122,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) + aml_int(arch_ids->cpus[i].arch_id))); + + /* build _MAT object */ +- riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf); ++ riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf, s); + aml_append(dev, aml_name_decl("_MAT", + aml_buffer(madt_buf->len, + (uint8_t *)madt_buf->data))); +@@ -227,6 +261,7 @@ static void build_dsdt(GArray *table_data, + * 5.2.12 Multiple APIC Description Table (MADT) + * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15 + * https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view ++ * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view + */ + static void build_madt(GArray *table_data, + BIOSLinker *linker, +@@ -246,7 +281,7 @@ static void build_madt(GArray *table_data, + + /* RISC-V Local INTC structures per HART */ + for (int i = 0; i < arch_ids->len; i++) { +- riscv_acpi_madt_add_rintc(i, arch_ids, table_data); ++ riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s); + } + + acpi_table_end(linker, &table); +-- +2.39.3 + diff --git a/0503-hw-riscv-virt-acpi-build-c-add-imsic-in-the-madt.patch b/0503-hw-riscv-virt-acpi-build-c-add-imsic-in-the-madt.patch new file mode 100644 index 0000000..060db4d --- /dev/null +++ b/0503-hw-riscv-virt-acpi-build-c-add-imsic-in-the-madt.patch @@ -0,0 +1,76 @@ +From 10179312861b2007653ecec4fcbcc76252f877d4 Mon Sep 17 00:00:00 2001 +From: Sunil V L +Date: Mon, 18 Dec 2023 20:32:40 +0530 +Subject: [PATCH] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT + +commit 66ac45b75975a64aa3fbcaa038aecfbc11ac8547 upstream + +Add IMSIC structure in MADT when IMSIC is configured. + +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Reviewed-by: Andrew Jones +Acked-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-7-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt-acpi-build.c | 35 +++++++++++++++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 1f6c188f7d..0576c58bb1 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -270,6 +270,19 @@ static void build_madt(GArray *table_data, + MachineClass *mc = MACHINE_GET_CLASS(s); + MachineState *ms = MACHINE(s); + const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); ++ uint8_t group_index_bits = imsic_num_bits(riscv_socket_count(ms)); ++ uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1); ++ uint16_t imsic_max_hart_per_socket = 0; ++ uint8_t hart_index_bits; ++ uint8_t socket; ++ ++ for (socket = 0; socket < riscv_socket_count(ms); socket++) { ++ if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { ++ imsic_max_hart_per_socket = s->soc[socket].num_harts; ++ } ++ } ++ ++ hart_index_bits = imsic_num_bits(imsic_max_hart_per_socket); + + AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id, + .oem_table_id = s->oem_table_id }; +@@ -284,6 +297,28 @@ static void build_madt(GArray *table_data, + riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s); + } + ++ /* IMSIC */ ++ if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { ++ /* IMSIC */ ++ build_append_int_noprefix(table_data, 0x19, 1); /* Type */ ++ build_append_int_noprefix(table_data, 16, 1); /* Length */ ++ build_append_int_noprefix(table_data, 1, 1); /* Version */ ++ build_append_int_noprefix(table_data, 0, 1); /* Reserved */ ++ build_append_int_noprefix(table_data, 0, 4); /* Flags */ ++ /* Number of supervisor mode Interrupt Identities */ ++ build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2); ++ /* Number of guest mode Interrupt Identities */ ++ build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2); ++ /* Guest Index Bits */ ++ build_append_int_noprefix(table_data, guest_index_bits, 1); ++ /* Hart Index Bits */ ++ build_append_int_noprefix(table_data, hart_index_bits, 1); ++ /* Group Index Bits */ ++ build_append_int_noprefix(table_data, group_index_bits, 1); ++ /* Group Index Shift */ ++ build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1); ++ } ++ + acpi_table_end(linker, &table); + } + +-- +2.39.3 + diff --git a/0504-hw-riscv-virt-acpi-build-c-add-aplic-in-the-madt.patch b/0504-hw-riscv-virt-acpi-build-c-add-aplic-in-the-madt.patch new file mode 100644 index 0000000..52db302 --- /dev/null +++ b/0504-hw-riscv-virt-acpi-build-c-add-aplic-in-the-madt.patch @@ -0,0 +1,76 @@ +From 4442e204edb23a5a3840746d689fec127c41a31a Mon Sep 17 00:00:00 2001 +From: Sunil V L +Date: Mon, 18 Dec 2023 20:32:41 +0530 +Subject: [PATCH] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT + +commit 7d189186f68b2b249c0bd6c84984f3aad2bcd1ca upstream + +Add APLIC structures for each socket in the MADT when system is configured +with APLIC as the external wired interrupt controller. + +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Reviewed-by: Andrew Jones +Acked-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-8-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt-acpi-build.c | 34 ++++++++++++++++++++++++++++++++++ + 1 file changed, 34 insertions(+) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 0576c58bb1..52bdaa69f1 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -274,6 +274,8 @@ static void build_madt(GArray *table_data, + uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1); + uint16_t imsic_max_hart_per_socket = 0; + uint8_t hart_index_bits; ++ uint64_t aplic_addr; ++ uint32_t gsi_base; + uint8_t socket; + + for (socket = 0; socket < riscv_socket_count(ms); socket++) { +@@ -319,6 +321,38 @@ static void build_madt(GArray *table_data, + build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1); + } + ++ if (s->aia_type != VIRT_AIA_TYPE_NONE) { ++ /* APLICs */ ++ for (socket = 0; socket < riscv_socket_count(ms); socket++) { ++ aplic_addr = s->memmap[VIRT_APLIC_S].base + ++ s->memmap[VIRT_APLIC_S].size * socket; ++ gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket; ++ build_append_int_noprefix(table_data, 0x1A, 1); /* Type */ ++ build_append_int_noprefix(table_data, 36, 1); /* Length */ ++ build_append_int_noprefix(table_data, 1, 1); /* Version */ ++ build_append_int_noprefix(table_data, socket, 1); /* APLIC ID */ ++ build_append_int_noprefix(table_data, 0, 4); /* Flags */ ++ build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */ ++ /* Number of IDCs */ ++ if (s->aia_type == VIRT_AIA_TYPE_APLIC) { ++ build_append_int_noprefix(table_data, ++ s->soc[socket].num_harts, ++ 2); ++ } else { ++ build_append_int_noprefix(table_data, 0, 2); ++ } ++ /* Total External Interrupt Sources Supported */ ++ build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_SOURCES, 2); ++ /* Global System Interrupt Base */ ++ build_append_int_noprefix(table_data, gsi_base, 4); ++ /* APLIC Address */ ++ build_append_int_noprefix(table_data, aplic_addr, 8); ++ /* APLIC size */ ++ build_append_int_noprefix(table_data, ++ s->memmap[VIRT_APLIC_S].size, 4); ++ } ++ } ++ + acpi_table_end(linker, &table); + } + +-- +2.39.3 + diff --git a/0505-hw-riscv-virt-acpi-build-c-add-cmo-information-in-rh.patch b/0505-hw-riscv-virt-acpi-build-c-add-cmo-information-in-rh.patch new file mode 100644 index 0000000..5d2f33d --- /dev/null +++ b/0505-hw-riscv-virt-acpi-build-c-add-cmo-information-in-rh.patch @@ -0,0 +1,131 @@ +From 3554acc9d0f8612db1c30842c0afac3e03ea1924 Mon Sep 17 00:00:00 2001 +From: Sunil V L +Date: Mon, 18 Dec 2023 20:32:42 +0530 +Subject: [PATCH] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT + +commit e810a5177c44509e17293d4c7e6cffab8ce197c9 upstream + +When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the +block size for those extensions need to be communicated via CMO node in +RHCT. Add CMO node in RHCT if any of those CMO extensions are detected. + +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Reviewed-by: Andrew Jones +Acked-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-9-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt-acpi-build.c | 64 +++++++++++++++++++++++++++++++++----- + 1 file changed, 56 insertions(+), 8 deletions(-) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 52bdaa69f1..b2fda17fa3 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -140,6 +140,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) + * 5.2.36 RISC-V Hart Capabilities Table (RHCT) + * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16 + * https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view ++ * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view + */ + static void build_rhct(GArray *table_data, + BIOSLinker *linker, +@@ -149,8 +150,8 @@ static void build_rhct(GArray *table_data, + MachineState *ms = MACHINE(s); + const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); + size_t len, aligned_len; +- uint32_t isa_offset, num_rhct_nodes; +- RISCVCPU *cpu; ++ uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0; ++ RISCVCPU *cpu = &s->soc[0].harts[0]; + g_autofree char *isa = NULL; + + AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id, +@@ -166,6 +167,9 @@ static void build_rhct(GArray *table_data, + + /* ISA + N hart info */ + num_rhct_nodes = 1 + ms->smp.cpus; ++ if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) { ++ num_rhct_nodes++; ++ } + + /* Number of RHCT nodes*/ + build_append_int_noprefix(table_data, num_rhct_nodes, 4); +@@ -177,7 +181,6 @@ static void build_rhct(GArray *table_data, + isa_offset = table_data->len - table.table_offset; + build_append_int_noprefix(table_data, 0, 2); /* Type 0 */ + +- cpu = &s->soc[0].harts[0]; + isa = riscv_isa_string(cpu); + len = 8 + strlen(isa) + 1; + aligned_len = (len % 2) ? (len + 1) : len; +@@ -193,14 +196,59 @@ static void build_rhct(GArray *table_data, + build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */ + } + ++ /* CMO node */ ++ if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) { ++ cmo_offset = table_data->len - table.table_offset; ++ build_append_int_noprefix(table_data, 1, 2); /* Type */ ++ build_append_int_noprefix(table_data, 10, 2); /* Length */ ++ build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ ++ build_append_int_noprefix(table_data, 0, 1); /* Reserved */ ++ ++ /* CBOM block size */ ++ if (cpu->cfg.cbom_blocksize) { ++ build_append_int_noprefix(table_data, ++ __builtin_ctz(cpu->cfg.cbom_blocksize), ++ 1); ++ } else { ++ build_append_int_noprefix(table_data, 0, 1); ++ } ++ ++ /* CBOP block size */ ++ build_append_int_noprefix(table_data, 0, 1); ++ ++ /* CBOZ block size */ ++ if (cpu->cfg.cboz_blocksize) { ++ build_append_int_noprefix(table_data, ++ __builtin_ctz(cpu->cfg.cboz_blocksize), ++ 1); ++ } else { ++ build_append_int_noprefix(table_data, 0, 1); ++ } ++ } ++ + /* Hart Info Node */ + for (int i = 0; i < arch_ids->len; i++) { ++ len = 16; ++ int num_offsets = 1; + build_append_int_noprefix(table_data, 0xFFFF, 2); /* Type */ +- build_append_int_noprefix(table_data, 16, 2); /* Length */ +- build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ +- build_append_int_noprefix(table_data, 1, 2); /* Number of offsets */ +- build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ +- build_append_int_noprefix(table_data, isa_offset, 4); /* Offsets[0] */ ++ ++ /* Length */ ++ if (cmo_offset) { ++ len += 4; ++ num_offsets++; ++ } ++ ++ build_append_int_noprefix(table_data, len, 2); ++ build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ ++ /* Number of offsets */ ++ build_append_int_noprefix(table_data, num_offsets, 2); ++ build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ ++ ++ /* Offsets */ ++ build_append_int_noprefix(table_data, isa_offset, 4); ++ if (cmo_offset) { ++ build_append_int_noprefix(table_data, cmo_offset, 4); ++ } + } + + acpi_table_end(linker, &table); +-- +2.39.3 + diff --git a/0506-hw-riscv-virt-acpi-build-c-add-mmu-node-in-rhct.patch b/0506-hw-riscv-virt-acpi-build-c-add-mmu-node-in-rhct.patch new file mode 100644 index 0000000..ed4ed86 --- /dev/null +++ b/0506-hw-riscv-virt-acpi-build-c-add-mmu-node-in-rhct.patch @@ -0,0 +1,102 @@ +From 239359392f884d5673b939a4ee8b6d055210fa1c Mon Sep 17 00:00:00 2001 +From: Sunil V L +Date: Mon, 18 Dec 2023 20:32:43 +0530 +Subject: [PATCH] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT + +commit a52aea263e0f25993e368ee682d96f32aff52499 upstream + +MMU type information is available via MMU node in RHCT. Add this node in +RHCT. + +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Reviewed-by: Andrew Jones +Acked-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-10-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt-acpi-build.c | 36 +++++++++++++++++++++++++++++++++++- + 1 file changed, 35 insertions(+), 1 deletion(-) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index b2fda17fa3..82bb2902a4 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -152,6 +152,8 @@ static void build_rhct(GArray *table_data, + size_t len, aligned_len; + uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0; + RISCVCPU *cpu = &s->soc[0].harts[0]; ++ uint32_t mmu_offset = 0; ++ uint8_t satp_mode_max; + g_autofree char *isa = NULL; + + AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id, +@@ -171,6 +173,10 @@ static void build_rhct(GArray *table_data, + num_rhct_nodes++; + } + ++ if (cpu->cfg.satp_mode.supported != 0) { ++ num_rhct_nodes++; ++ } ++ + /* Number of RHCT nodes*/ + build_append_int_noprefix(table_data, num_rhct_nodes, 4); + +@@ -226,6 +232,26 @@ static void build_rhct(GArray *table_data, + } + } + ++ /* MMU node structure */ ++ if (cpu->cfg.satp_mode.supported != 0) { ++ satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); ++ mmu_offset = table_data->len - table.table_offset; ++ build_append_int_noprefix(table_data, 2, 2); /* Type */ ++ build_append_int_noprefix(table_data, 8, 2); /* Length */ ++ build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ ++ build_append_int_noprefix(table_data, 0, 1); /* Reserved */ ++ /* MMU Type */ ++ if (satp_mode_max == VM_1_10_SV57) { ++ build_append_int_noprefix(table_data, 2, 1); /* Sv57 */ ++ } else if (satp_mode_max == VM_1_10_SV48) { ++ build_append_int_noprefix(table_data, 1, 1); /* Sv48 */ ++ } else if (satp_mode_max == VM_1_10_SV39) { ++ build_append_int_noprefix(table_data, 0, 1); /* Sv39 */ ++ } else { ++ assert(1); ++ } ++ } ++ + /* Hart Info Node */ + for (int i = 0; i < arch_ids->len; i++) { + len = 16; +@@ -238,17 +264,25 @@ static void build_rhct(GArray *table_data, + num_offsets++; + } + ++ if (mmu_offset) { ++ len += 4; ++ num_offsets++; ++ } ++ + build_append_int_noprefix(table_data, len, 2); + build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ + /* Number of offsets */ + build_append_int_noprefix(table_data, num_offsets, 2); + build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ +- + /* Offsets */ + build_append_int_noprefix(table_data, isa_offset, 4); + if (cmo_offset) { + build_append_int_noprefix(table_data, cmo_offset, 4); + } ++ ++ if (mmu_offset) { ++ build_append_int_noprefix(table_data, mmu_offset, 4); ++ } + } + + acpi_table_end(linker, &table); +-- +2.39.3 + diff --git a/0507-hw-pci-host-gpex-define-properties-for-mmio-ranges.patch b/0507-hw-pci-host-gpex-define-properties-for-mmio-ranges.patch new file mode 100644 index 0000000..b831585 --- /dev/null +++ b/0507-hw-pci-host-gpex-define-properties-for-mmio-ranges.patch @@ -0,0 +1,126 @@ +From 2d4d26fe9daacbbea2b64d012267dd6dc333c276 Mon Sep 17 00:00:00 2001 +From: Sunil V L +Date: Mon, 18 Dec 2023 20:32:44 +0530 +Subject: [PATCH] hw/pci-host/gpex: Define properties for MMIO ranges + +commit 8f6a4874887c226b0df35f5b78fa77f197507d96 upstream + +ACPI DSDT generator needs information like ECAM range, PIO range, 32-bit +and 64-bit PCI MMIO range etc related to the PCI host bridge. Instead of +making these values machine specific, create properties for the GPEX +host bridge with default value 0. During initialization, the firmware +can initialize these properties with correct values for the platform. +This basically allows DSDT generator code independent of the machine +specific memory map accesses. + +Suggested-by: Igor Mammedov +Signed-off-by: Sunil V L +Acked-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Reviewed-by: Daniel Henrique Barboza +Message-ID: <20231218150247.466427-11-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/pci-host/gpex-acpi.c | 13 +++++++++++++ + hw/pci-host/gpex.c | 12 ++++++++++++ + include/hw/pci-host/gpex.h | 28 ++++++++++++++++++++-------- + 3 files changed, 45 insertions(+), 8 deletions(-) + +diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c +index 1092dc3b70..f69413ea2c 100644 +--- a/hw/pci-host/gpex-acpi.c ++++ b/hw/pci-host/gpex-acpi.c +@@ -281,3 +281,16 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) + + crs_range_set_free(&crs_range_set); + } ++ ++void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq) ++{ ++ bool ambig; ++ Object *obj = object_resolve_path_type("", TYPE_GPEX_HOST, &ambig); ++ ++ if (!obj || ambig) { ++ return; ++ } ++ ++ GPEX_HOST(obj)->gpex_cfg.irq = irq; ++ acpi_dsdt_add_gpex(scope, &GPEX_HOST(obj)->gpex_cfg); ++} +diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c +index a6752fac5e..41f4e73f6e 100644 +--- a/hw/pci-host/gpex.c ++++ b/hw/pci-host/gpex.c +@@ -154,6 +154,18 @@ static Property gpex_host_properties[] = { + */ + DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost, + allow_unmapped_accesses, true), ++ DEFINE_PROP_UINT64(PCI_HOST_ECAM_BASE, GPEXHost, gpex_cfg.ecam.base, 0), ++ DEFINE_PROP_SIZE(PCI_HOST_ECAM_SIZE, GPEXHost, gpex_cfg.ecam.size, 0), ++ DEFINE_PROP_UINT64(PCI_HOST_PIO_BASE, GPEXHost, gpex_cfg.pio.base, 0), ++ DEFINE_PROP_SIZE(PCI_HOST_PIO_SIZE, GPEXHost, gpex_cfg.pio.size, 0), ++ DEFINE_PROP_UINT64(PCI_HOST_BELOW_4G_MMIO_BASE, GPEXHost, ++ gpex_cfg.mmio32.base, 0), ++ DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MMIO_SIZE, GPEXHost, ++ gpex_cfg.mmio32.size, 0), ++ DEFINE_PROP_UINT64(PCI_HOST_ABOVE_4G_MMIO_BASE, GPEXHost, ++ gpex_cfg.mmio64.base, 0), ++ DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MMIO_SIZE, GPEXHost, ++ gpex_cfg.mmio64.size, 0), + DEFINE_PROP_END_OF_LIST(), + }; + +diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h +index b0240bd768..dce883573b 100644 +--- a/include/hw/pci-host/gpex.h ++++ b/include/hw/pci-host/gpex.h +@@ -40,6 +40,15 @@ struct GPEXRootState { + /*< public >*/ + }; + ++struct GPEXConfig { ++ MemMapEntry ecam; ++ MemMapEntry mmio32; ++ MemMapEntry mmio64; ++ MemMapEntry pio; ++ int irq; ++ PCIBus *bus; ++}; ++ + struct GPEXHost { + /*< private >*/ + PCIExpressHost parent_obj; +@@ -55,19 +64,22 @@ struct GPEXHost { + int irq_num[GPEX_NUM_IRQS]; + + bool allow_unmapped_accesses; +-}; + +-struct GPEXConfig { +- MemMapEntry ecam; +- MemMapEntry mmio32; +- MemMapEntry mmio64; +- MemMapEntry pio; +- int irq; +- PCIBus *bus; ++ struct GPEXConfig gpex_cfg; + }; + + int gpex_set_irq_num(GPEXHost *s, int index, int gsi); + + void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg); ++void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq); ++ ++#define PCI_HOST_PIO_BASE "x-pio-base" ++#define PCI_HOST_PIO_SIZE "x-pio-size" ++#define PCI_HOST_ECAM_BASE "x-ecam-base" ++#define PCI_HOST_ECAM_SIZE "x-ecam-size" ++#define PCI_HOST_BELOW_4G_MMIO_BASE "x-below-4g-mmio-base" ++#define PCI_HOST_BELOW_4G_MMIO_SIZE "x-below-4g-mmio-size" ++#define PCI_HOST_ABOVE_4G_MMIO_BASE "x-above-4g-mmio-base" ++#define PCI_HOST_ABOVE_4G_MMIO_SIZE "x-above-4g-mmio-size" + + #endif /* HW_GPEX_H */ +-- +2.39.3 + diff --git a/0508-hw-riscv-virt-update-gpex-mmio-related-properties.patch b/0508-hw-riscv-virt-update-gpex-mmio-related-properties.patch new file mode 100644 index 0000000..1e63878 --- /dev/null +++ b/0508-hw-riscv-virt-update-gpex-mmio-related-properties.patch @@ -0,0 +1,117 @@ +From 90b601b0dbce8a4c4d33a2b154707362c11e006a Mon Sep 17 00:00:00 2001 +From: Sunil V L +Date: Mon, 18 Dec 2023 20:32:45 +0530 +Subject: [PATCH] hw/riscv/virt: Update GPEX MMIO related properties + +commit e86e95270e2b10e57c69852778452b54b31e1c19 upstream + +Update the GPEX host bridge properties related to MMIO ranges with +values set for the virt machine. + +Suggested-by: Igor Mammedov +Signed-off-by: Sunil V L +Reviewed-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-12-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt.c | 47 ++++++++++++++++++++++++++++------------- + include/hw/riscv/virt.h | 1 + + 2 files changed, 33 insertions(+), 15 deletions(-) + +diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c +index 30b9f8cab6..c47df46bfc 100644 +--- a/hw/riscv/virt.c ++++ b/hw/riscv/virt.c +@@ -1055,21 +1055,45 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) + } + + static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, +- hwaddr ecam_base, hwaddr ecam_size, +- hwaddr mmio_base, hwaddr mmio_size, +- hwaddr high_mmio_base, +- hwaddr high_mmio_size, +- hwaddr pio_base, +- DeviceState *irqchip) ++ DeviceState *irqchip, ++ RISCVVirtState *s) + { + DeviceState *dev; + MemoryRegion *ecam_alias, *ecam_reg; + MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; ++ hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; ++ hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; ++ hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; ++ hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; ++ hwaddr high_mmio_base = virt_high_pcie_memmap.base; ++ hwaddr high_mmio_size = virt_high_pcie_memmap.size; ++ hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; ++ hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; + qemu_irq irq; + int i; + + dev = qdev_new(TYPE_GPEX_HOST); + ++ /* Set GPEX object properties for the virt machine */ ++ object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE, ++ ecam_base, NULL); ++ object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE, ++ ecam_size, NULL); ++ object_property_set_uint(OBJECT(GPEX_HOST(dev)), ++ PCI_HOST_BELOW_4G_MMIO_BASE, ++ mmio_base, NULL); ++ object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE, ++ mmio_size, NULL); ++ object_property_set_uint(OBJECT(GPEX_HOST(dev)), ++ PCI_HOST_ABOVE_4G_MMIO_BASE, ++ high_mmio_base, NULL); ++ object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE, ++ high_mmio_size, NULL); ++ object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE, ++ pio_base, NULL); ++ object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE, ++ pio_size, NULL); ++ + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + ecam_alias = g_new0(MemoryRegion, 1); +@@ -1100,6 +1124,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, + gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); + } + ++ GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus; + return dev; + } + +@@ -1536,15 +1561,7 @@ static void virt_machine_init(MachineState *machine) + qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); + } + +- gpex_pcie_init(system_memory, +- memmap[VIRT_PCIE_ECAM].base, +- memmap[VIRT_PCIE_ECAM].size, +- memmap[VIRT_PCIE_MMIO].base, +- memmap[VIRT_PCIE_MMIO].size, +- virt_high_pcie_memmap.base, +- virt_high_pcie_memmap.size, +- memmap[VIRT_PCIE_PIO].base, +- pcie_irqchip); ++ gpex_pcie_init(system_memory, pcie_irqchip, s); + + create_platform_bus(s, mmio_irqchip); + +diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h +index 5b03575ed3..f89790fd58 100644 +--- a/include/hw/riscv/virt.h ++++ b/include/hw/riscv/virt.h +@@ -61,6 +61,7 @@ struct RISCVVirtState { + char *oem_table_id; + OnOffAuto acpi; + const MemMapEntry *memmap; ++ struct GPEXHost *gpex_host; + }; + + enum { +-- +2.39.3 + diff --git a/0509-hw-riscv-virt-acpi-build-c-add-io-controllers-and-de.patch b/0509-hw-riscv-virt-acpi-build-c-add-io-controllers-and-de.patch new file mode 100644 index 0000000..fe9e4b5 --- /dev/null +++ b/0509-hw-riscv-virt-acpi-build-c-add-io-controllers-and-de.patch @@ -0,0 +1,159 @@ +From edad4e20d9bedcbcb18a31aa9e075de0e40aa921 Mon Sep 17 00:00:00 2001 +From: Sunil V L +Date: Mon, 18 Dec 2023 20:32:46 +0530 +Subject: [PATCH] hw/riscv/virt-acpi-build.c: Add IO controllers and devices + +commit 55ecd83b3697d0e4002c1dfde3265ebe6fa887cc upstream + +Add basic IO controllers and devices like PCI, VirtIO and UART in the +ACPI namespace. + +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Acked-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-13-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/Kconfig | 1 + + hw/riscv/virt-acpi-build.c | 79 ++++++++++++++++++++++++++++++++++++-- + 2 files changed, 76 insertions(+), 4 deletions(-) + +diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig +index 1e11ac9432..5d644eb7b1 100644 +--- a/hw/riscv/Kconfig ++++ b/hw/riscv/Kconfig +@@ -46,6 +46,7 @@ config RISCV_VIRT + select FW_CFG_DMA + select PLATFORM_BUS + select ACPI ++ select ACPI_PCI + + config SHAKTI_C + bool +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 82bb2902a4..43038381db 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -27,15 +27,18 @@ + #include "hw/acpi/acpi-defs.h" + #include "hw/acpi/acpi.h" + #include "hw/acpi/aml-build.h" ++#include "hw/acpi/pci.h" + #include "hw/acpi/utils.h" ++#include "hw/intc/riscv_aclint.h" + #include "hw/nvram/fw_cfg_acpi.h" ++#include "hw/pci-host/gpex.h" ++#include "hw/riscv/virt.h" ++#include "hw/riscv/numa.h" ++#include "hw/virtio/virtio-acpi.h" ++#include "migration/vmstate.h" + #include "qapi/error.h" + #include "qemu/error-report.h" + #include "sysemu/reset.h" +-#include "migration/vmstate.h" +-#include "hw/riscv/virt.h" +-#include "hw/riscv/numa.h" +-#include "hw/intc/riscv_aclint.h" + + #define ACPI_BUILD_TABLE_SIZE 0x20000 + #define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index)) +@@ -132,6 +135,39 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) + } + } + ++static void ++acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, ++ uint32_t uart_irq) ++{ ++ Aml *dev = aml_device("COM0"); ++ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501"))); ++ aml_append(dev, aml_name_decl("_UID", aml_int(0))); ++ ++ Aml *crs = aml_resource_template(); ++ aml_append(crs, aml_memory32_fixed(uart_memmap->base, ++ uart_memmap->size, AML_READ_WRITE)); ++ aml_append(crs, ++ aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, ++ AML_EXCLUSIVE, &uart_irq, 1)); ++ aml_append(dev, aml_name_decl("_CRS", crs)); ++ ++ Aml *pkg = aml_package(2); ++ aml_append(pkg, aml_string("clock-frequency")); ++ aml_append(pkg, aml_int(3686400)); ++ ++ Aml *UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301"); ++ ++ Aml *pkg1 = aml_package(1); ++ aml_append(pkg1, pkg); ++ ++ Aml *package = aml_package(2); ++ aml_append(package, UUID); ++ aml_append(package, pkg1); ++ ++ aml_append(dev, aml_name_decl("_DSD", package)); ++ aml_append(scope, dev); ++} ++ + /* RHCT Node[N] starts at offset 56 */ + #define RHCT_NODE_ARRAY_OFFSET 56 + +@@ -310,6 +346,8 @@ static void build_dsdt(GArray *table_data, + RISCVVirtState *s) + { + Aml *scope, *dsdt; ++ MachineState *ms = MACHINE(s); ++ uint8_t socket_count; + const MemMapEntry *memmap = s->memmap; + AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id, + .oem_table_id = s->oem_table_id }; +@@ -329,6 +367,29 @@ static void build_dsdt(GArray *table_data, + + fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); + ++ socket_count = riscv_socket_count(ms); ++ ++ acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ); ++ ++ if (socket_count == 1) { ++ virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, ++ memmap[VIRT_VIRTIO].size, ++ VIRTIO_IRQ, 0, VIRTIO_COUNT); ++ acpi_dsdt_add_gpex_host(scope, PCIE_IRQ); ++ } else if (socket_count == 2) { ++ virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, ++ memmap[VIRT_VIRTIO].size, ++ VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0, ++ VIRTIO_COUNT); ++ acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES); ++ } else { ++ virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, ++ memmap[VIRT_VIRTIO].size, ++ VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0, ++ VIRTIO_COUNT); ++ acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES * 2); ++ } ++ + aml_append(dsdt, scope); + + /* copy AML table into ACPI tables blob and patch header there */ +@@ -465,6 +526,16 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) + acpi_add_table(table_offsets, tables_blob); + build_rhct(tables_blob, tables->linker, s); + ++ acpi_add_table(table_offsets, tables_blob); ++ { ++ AcpiMcfgInfo mcfg = { ++ .base = s->memmap[VIRT_PCIE_MMIO].base, ++ .size = s->memmap[VIRT_PCIE_MMIO].size, ++ }; ++ build_mcfg(tables_blob, tables->linker, &mcfg, s->oem_id, ++ s->oem_table_id); ++ } ++ + /* XSDT is pointed to by RSDP */ + xsdt = tables_blob->len; + build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id, +-- +2.39.3 + diff --git a/0510-hw-riscv-virt-acpi-build-c-add-plic-in-madt.patch b/0510-hw-riscv-virt-acpi-build-c-add-plic-in-madt.patch new file mode 100644 index 0000000..af2d2e3 --- /dev/null +++ b/0510-hw-riscv-virt-acpi-build-c-add-plic-in-madt.patch @@ -0,0 +1,72 @@ +From 141921d7bd38a324a0920301c3f91110a2e16fc9 Mon Sep 17 00:00:00 2001 +From: Sunil V L +Date: Mon, 18 Dec 2023 20:32:47 +0530 +Subject: [PATCH] hw/riscv/virt-acpi-build.c: Add PLIC in MADT + +commit d641da6ed431f497b763a6e6bf30e0b4dc00e0d9 upstream + +Add PLIC structures for each socket in the MADT when system is +configured with PLIC as the external interrupt controller. + +Signed-off-by: Haibo Xu +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Reviewed-by: Andrew Jones +Acked-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-14-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt-acpi-build.c | 29 +++++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 43038381db..53f33791c2 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -94,6 +94,12 @@ static void riscv_acpi_madt_add_rintc(uint32_t uid, + arch_ids->cpus[uid].props.node_id, + local_cpu_id), + 4); ++ } else if (s->aia_type == VIRT_AIA_TYPE_NONE) { ++ build_append_int_noprefix(entry, ++ ACPI_BUILD_INTC_ID( ++ arch_ids->cpus[uid].props.node_id, ++ 2 * local_cpu_id + 1), ++ 4); + } else { + build_append_int_noprefix(entry, 0, 4); + } +@@ -494,6 +500,29 @@ static void build_madt(GArray *table_data, + build_append_int_noprefix(table_data, + s->memmap[VIRT_APLIC_S].size, 4); + } ++ } else { ++ /* PLICs */ ++ for (socket = 0; socket < riscv_socket_count(ms); socket++) { ++ aplic_addr = s->memmap[VIRT_PLIC].base + ++ s->memmap[VIRT_PLIC].size * socket; ++ gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket; ++ build_append_int_noprefix(table_data, 0x1B, 1); /* Type */ ++ build_append_int_noprefix(table_data, 36, 1); /* Length */ ++ build_append_int_noprefix(table_data, 1, 1); /* Version */ ++ build_append_int_noprefix(table_data, socket, 1); /* PLIC ID */ ++ build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */ ++ /* Total External Interrupt Sources Supported */ ++ build_append_int_noprefix(table_data, ++ VIRT_IRQCHIP_NUM_SOURCES - 1, 2); ++ build_append_int_noprefix(table_data, 0, 2); /* Max Priority */ ++ build_append_int_noprefix(table_data, 0, 4); /* Flags */ ++ /* PLIC Size */ ++ build_append_int_noprefix(table_data, s->memmap[VIRT_PLIC].size, 4); ++ /* PLIC Address */ ++ build_append_int_noprefix(table_data, aplic_addr, 8); ++ /* Global System Interrupt Vector Base */ ++ build_append_int_noprefix(table_data, gsi_base, 4); ++ } + } + + acpi_table_end(linker, &table); +-- +2.39.3 + diff --git a/0511-hw-riscv-virt-c-fix-the-interrupts-extended-property.patch b/0511-hw-riscv-virt-c-fix-the-interrupts-extended-property.patch new file mode 100644 index 0000000..b3ed0bc --- /dev/null +++ b/0511-hw-riscv-virt-c-fix-the-interrupts-extended-property.patch @@ -0,0 +1,92 @@ +From 5268a38fa74ae602137ed79f5d8dac22f6bc4dcd Mon Sep 17 00:00:00 2001 +From: Yong-Xuan Wang +Date: Mon, 18 Dec 2023 09:05:40 +0000 +Subject: [PATCH] hw/riscv/virt.c: fix the interrupts-extended property format + of PLIC + +commit ca334e10dcd1f0f3a3c08f8dc3f9945d574d0e6b upstream + +The interrupts-extended property of PLIC only has 2 * hart number +fields when KVM enabled, copy 4 * hart number fields to fdt will +expose some uninitialized value. + +In this patch, I also refactor the code about the setting of +interrupts-extended property of PLIC for improved readability. + +Signed-off-by: Yong-Xuan Wang +Reviewed-by: Jim Shu +Reviewed-by: Daniel Henrique Barboza +Message-ID: <20231218090543.22353-1-yongxuan.wang@sifive.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt.c | 47 +++++++++++++++++++++++++++-------------------- + 1 file changed, 27 insertions(+), 20 deletions(-) + +diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c +index c47df46bfc..8f01ec7f61 100644 +--- a/hw/riscv/virt.c ++++ b/hw/riscv/virt.c +@@ -438,24 +438,6 @@ static void create_fdt_socket_plic(RISCVVirtState *s, + "sifive,plic-1.0.0", "riscv,plic0" + }; + +- if (kvm_enabled()) { +- plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); +- } else { +- plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); +- } +- +- for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { +- if (kvm_enabled()) { +- plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); +- plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); +- } else { +- plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); +- plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); +- plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); +- plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); +- } +- } +- + plic_phandles[socket] = (*phandle)++; + plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); + plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); +@@ -468,8 +450,33 @@ static void create_fdt_socket_plic(RISCVVirtState *s, + (char **)&plic_compat, + ARRAY_SIZE(plic_compat)); + qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); +- qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", +- plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); ++ ++ if (kvm_enabled()) { ++ plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); ++ ++ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { ++ plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); ++ plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); ++ } ++ ++ qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", ++ plic_cells, ++ s->soc[socket].num_harts * sizeof(uint32_t) * 2); ++ } else { ++ plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); ++ ++ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { ++ plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); ++ plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); ++ plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); ++ plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); ++ } ++ ++ qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", ++ plic_cells, ++ s->soc[socket].num_harts * sizeof(uint32_t) * 4); ++ } ++ + qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", + 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); + qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", +-- +2.39.3 + diff --git a/0512-hw-riscv-virt-acpi-build-c-add-namespace-devices-for.patch b/0512-hw-riscv-virt-acpi-build-c-add-namespace-devices-for.patch new file mode 100644 index 0000000..b78573e --- /dev/null +++ b/0512-hw-riscv-virt-acpi-build-c-add-namespace-devices-for.patch @@ -0,0 +1,78 @@ +From c05e14c546b1cb3a749a3f98c933a3cc17676bbf Mon Sep 17 00:00:00 2001 +From: Sunil V L +Date: Tue, 16 Jul 2024 20:12:58 +0530 +Subject: [PATCH] hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC + and APLIC + +commit a54dd0cd6b9119c44d52547f51a529122f0ec1f1 upstream + +As per the requirement ACPI_080 in the RISC-V Boot and Runtime Services +(BRS) specification [1], PLIC and APLIC should be in namespace as well. +So, add them using the defined HID. + +[1] - https://github.com/riscv-non-isa/riscv-brs/releases/download/v0.0.2/riscv-brs-spec.pdf + (Chapter 6) + +Signed-off-by: Sunil V L +Acked-by: Alistair Francis +Acked-by: Igor Mammedov +Message-Id: <20240716144306.2432257-2-sunilvl@ventanamicro.com> +Reviewed-by: Michael S. Tsirkin +Signed-off-by: Michael S. Tsirkin +--- + hw/riscv/virt-acpi-build.c | 32 ++++++++++++++++++++++++++++++++ + 1 file changed, 32 insertions(+) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 53f33791c2..3ffa774015 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -141,6 +141,30 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) + } + } + ++static void acpi_dsdt_add_plic_aplic(Aml *scope, uint8_t socket_count, ++ uint64_t mmio_base, uint64_t mmio_size, ++ const char *hid) ++{ ++ uint64_t plic_aplic_addr; ++ uint32_t gsi_base; ++ uint8_t socket; ++ ++ for (socket = 0; socket < socket_count; socket++) { ++ plic_aplic_addr = mmio_base + mmio_size * socket; ++ gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket; ++ Aml *dev = aml_device("IC%.02X", socket); ++ aml_append(dev, aml_name_decl("_HID", aml_string("%s", hid))); ++ aml_append(dev, aml_name_decl("_UID", aml_int(socket))); ++ aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base))); ++ ++ Aml *crs = aml_resource_template(); ++ aml_append(crs, aml_memory32_fixed(plic_aplic_addr, mmio_size, ++ AML_READ_WRITE)); ++ aml_append(dev, aml_name_decl("_CRS", crs)); ++ aml_append(scope, dev); ++ } ++} ++ + static void + acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, + uint32_t uart_irq) +@@ -375,6 +399,14 @@ static void build_dsdt(GArray *table_data, + + socket_count = riscv_socket_count(ms); + ++ if (s->aia_type == VIRT_AIA_TYPE_NONE) { ++ acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_PLIC].base, ++ memmap[VIRT_PLIC].size, "RSCV0001"); ++ } else { ++ acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_APLIC_S].base, ++ memmap[VIRT_APLIC_S].size, "RSCV0002"); ++ } ++ + acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ); + + if (socket_count == 1) { +-- +2.39.3 + diff --git a/0513-hw-riscv-virt-acpi-build-c-update-the-hid-of-risc-v-.patch b/0513-hw-riscv-virt-acpi-build-c-update-the-hid-of-risc-v-.patch new file mode 100644 index 0000000..11af068 --- /dev/null +++ b/0513-hw-riscv-virt-acpi-build-c-update-the-hid-of-risc-v-.patch @@ -0,0 +1,40 @@ +From a2ffa96392b6c4766d8fc89a2b5d0a154d00b438 Mon Sep 17 00:00:00 2001 +From: Sunil V L +Date: Tue, 16 Jul 2024 20:12:59 +0530 +Subject: [PATCH] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART + +commit faacd2e6b6a85a5eee2472e5a7f50bf69c4ad44a upstream + +The requirement ACPI_060 in the RISC-V BRS specification [1], requires +NS16550 compatible UART to have the HID RSCV0003. So, update the HID for +the UART. + +[1] - https://github.com/riscv-non-isa/riscv-brs/releases/download/v0.0.2/riscv-brs-spec.pdf + (Chapter 6) + +Signed-off-by: Sunil V L +Acked-by: Alistair Francis +Reviewed-by: Igor Mammedov +Message-Id: <20240716144306.2432257-3-sunilvl@ventanamicro.com> +Reviewed-by: Michael S. Tsirkin +Signed-off-by: Michael S. Tsirkin +--- + hw/riscv/virt-acpi-build.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 3ffa774015..bb6036db89 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -170,7 +170,7 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, + uint32_t uart_irq) + { + Aml *dev = aml_device("COM0"); +- aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501"))); ++ aml_append(dev, aml_name_decl("_HID", aml_string("RSCV0003"))); + aml_append(dev, aml_name_decl("_UID", aml_int(0))); + + Aml *crs = aml_resource_template(); +-- +2.39.3 + diff --git a/0514-acpi-gpex-create-pci-link-devices-outside-pci-root-b.patch b/0514-acpi-gpex-create-pci-link-devices-outside-pci-root-b.patch new file mode 100644 index 0000000..6fd6ffe --- /dev/null +++ b/0514-acpi-gpex-create-pci-link-devices-outside-pci-root-b.patch @@ -0,0 +1,94 @@ +From 0915286aa844028c36e7569d85b2a38d9fbca55d Mon Sep 17 00:00:00 2001 +From: Sunil V L +Date: Tue, 16 Jul 2024 20:13:01 +0530 +Subject: [PATCH] acpi/gpex: Create PCI link devices outside PCI root bridge + +commit 35520bc702a8c3d7b434305ac403de437003d4bc upstream + +Currently, PCI link devices (PNP0C0F) are always created within the +scope of the PCI root bridge. However, RISC-V needs these link devices +to be created outside to ensure the probing order in the OS. This +matches the example given in the ACPI specification [1] as well. Hence, +create these link devices directly under _SB instead of under the PCI +root bridge. + +To keep these link device names unique for multiple PCI bridges, change +the device name from GSIx to LXXY format where XX is the PCI bus number +and Y is the INTx. + +GPEX is currently used by riscv, aarch64/virt and x86/microvm machines. +So, this change will alter the DSDT for those systems. + +[1] - ACPI 5.1: 6.2.13.1 Example: Using _PRT to Describe PCI IRQ Routing + +Signed-off-by: Sunil V L +Acked-by: Igor Mammedov +Message-Id: <20240716144306.2432257-5-sunilvl@ventanamicro.com> +Reviewed-by: Michael S. Tsirkin +Signed-off-by: Michael S. Tsirkin +--- + hw/pci-host/gpex-acpi.c | 13 +++++++------ + 1 file changed, 7 insertions(+), 6 deletions(-) + +diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c +index f69413ea2c..391fabb8a8 100644 +--- a/hw/pci-host/gpex-acpi.c ++++ b/hw/pci-host/gpex-acpi.c +@@ -7,7 +7,8 @@ + #include "hw/pci/pcie_host.h" + #include "hw/acpi/cxl.h" + +-static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq) ++static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq, ++ Aml *scope, uint8_t bus_num) + { + Aml *method, *crs; + int i, slot_no; +@@ -20,7 +21,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq) + Aml *pkg = aml_package(4); + aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF)); + aml_append(pkg, aml_int(i)); +- aml_append(pkg, aml_name("GSI%d", gsi)); ++ aml_append(pkg, aml_name("L%.02X%X", bus_num, gsi)); + aml_append(pkg, aml_int(0)); + aml_append(rt_pkg, pkg); + } +@@ -30,7 +31,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq) + /* Create GSI link device */ + for (i = 0; i < PCI_NUM_PINS; i++) { + uint32_t irqs = irq + i; +- Aml *dev_gsi = aml_device("GSI%d", i); ++ Aml *dev_gsi = aml_device("L%.02X%X", bus_num, i); + aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); + aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i))); + crs = aml_resource_template(); +@@ -45,7 +46,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq) + aml_append(dev_gsi, aml_name_decl("_CRS", crs)); + method = aml_method("_SRS", 1, AML_NOTSERIALIZED); + aml_append(dev_gsi, method); +- aml_append(dev, dev_gsi); ++ aml_append(scope, dev_gsi); + } + } + +@@ -174,7 +175,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) + aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); + } + +- acpi_dsdt_add_pci_route_table(dev, cfg->irq); ++ acpi_dsdt_add_pci_route_table(dev, cfg->irq, scope, bus_num); + + /* + * Resources defined for PXBs are composed of the following parts: +@@ -205,7 +206,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) + aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + +- acpi_dsdt_add_pci_route_table(dev, cfg->irq); ++ acpi_dsdt_add_pci_route_table(dev, cfg->irq, scope, 0); + + method = aml_method("_CBA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(cfg->ecam.base))); +-- +2.39.3 + diff --git a/0515-hw-arm-virt-acpi-build-c-migrate-spcr-creation-to-co.patch b/0515-hw-arm-virt-acpi-build-c-migrate-spcr-creation-to-co.patch new file mode 100644 index 0000000..eb0fac3 --- /dev/null +++ b/0515-hw-arm-virt-acpi-build-c-migrate-spcr-creation-to-co.patch @@ -0,0 +1,238 @@ +From eb5e9f2f49671894ce3eb88c8e44d8f4b3333431 Mon Sep 17 00:00:00 2001 +From: Sia Jee Heng +Date: Sun, 28 Jan 2024 18:14:39 -0800 +Subject: [PATCH] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common + location + +commit 7dd0b070fa09311a0330d0309c8cd9afeb081e79 upstream + +RISC-V should also generate the SPCR in a manner similar to ARM. +Therefore, instead of replicating the code, relocate this function +to the common AML build. + +Signed-off-by: Sia Jee Heng +Reviewed-by: Alistair Francis +Message-ID: <20240129021440.17640-2-jeeheng.sia@starfivetech.com> +[ Changes by AF: + - Add missing Language SPCR entry +] +Signed-off-by: Alistair Francis +--- + hw/acpi/aml-build.c | 53 +++++++++++++++++++++++++++++ + hw/arm/virt-acpi-build.c | 68 +++++++++++++++---------------------- + include/hw/acpi/acpi-defs.h | 33 ++++++++++++++++++ + include/hw/acpi/aml-build.h | 4 +++ + 4 files changed, 117 insertions(+), 41 deletions(-) + +diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c +index 0d4dea266a..730efcbd51 100644 +--- a/hw/acpi/aml-build.c ++++ b/hw/acpi/aml-build.c +@@ -2006,6 +2006,59 @@ static void build_processor_hierarchy_node(GArray *tbl, uint32_t flags, + } + } + ++void build_spcr(GArray *table_data, BIOSLinker *linker, ++ const AcpiSpcrData *f, const uint8_t rev, ++ const char *oem_id, const char *oem_table_id) ++{ ++ AcpiTable table = { .sig = "SPCR", .rev = rev, .oem_id = oem_id, ++ .oem_table_id = oem_table_id }; ++ ++ acpi_table_begin(&table, table_data); ++ /* Interface type */ ++ build_append_int_noprefix(table_data, f->interface_type, 1); ++ /* Reserved */ ++ build_append_int_noprefix(table_data, 0, 3); ++ /* Base Address */ ++ build_append_gas(table_data, f->base_addr.id, f->base_addr.width, ++ f->base_addr.offset, f->base_addr.size, ++ f->base_addr.addr); ++ /* Interrupt type */ ++ build_append_int_noprefix(table_data, f->interrupt_type, 1); ++ /* IRQ */ ++ build_append_int_noprefix(table_data, f->pc_interrupt, 1); ++ /* Global System Interrupt */ ++ build_append_int_noprefix(table_data, f->interrupt, 4); ++ /* Baud Rate */ ++ build_append_int_noprefix(table_data, f->baud_rate, 1); ++ /* Parity */ ++ build_append_int_noprefix(table_data, f->parity, 1); ++ /* Stop Bits */ ++ build_append_int_noprefix(table_data, f->stop_bits, 1); ++ /* Flow Control */ ++ build_append_int_noprefix(table_data, f->flow_control, 1); ++ /* Language */ ++ build_append_int_noprefix(table_data, f->language, 1); ++ /* Terminal Type */ ++ build_append_int_noprefix(table_data, f->terminal_type, 1); ++ /* PCI Device ID */ ++ build_append_int_noprefix(table_data, f->pci_device_id, 2); ++ /* PCI Vendor ID */ ++ build_append_int_noprefix(table_data, f->pci_vendor_id, 2); ++ /* PCI Bus Number */ ++ build_append_int_noprefix(table_data, f->pci_bus, 1); ++ /* PCI Device Number */ ++ build_append_int_noprefix(table_data, f->pci_device, 1); ++ /* PCI Function Number */ ++ build_append_int_noprefix(table_data, f->pci_function, 1); ++ /* PCI Flags */ ++ build_append_int_noprefix(table_data, f->pci_flags, 4); ++ /* PCI Segment */ ++ build_append_int_noprefix(table_data, f->pci_segment, 1); ++ /* Reserved */ ++ build_append_int_noprefix(table_data, 0, 4); ++ ++ acpi_table_end(linker, &table); ++} + /* + * ACPI spec, Revision 6.3 + * 5.2.29 Processor Properties Topology Table (PPTT) +diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c +index 510ab0dcca..e1fda3fadd 100644 +--- a/hw/arm/virt-acpi-build.c ++++ b/hw/arm/virt-acpi-build.c +@@ -431,48 +431,34 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) + * Rev: 1.07 + */ + static void +-build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) ++spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) + { +- AcpiTable table = { .sig = "SPCR", .rev = 2, .oem_id = vms->oem_id, +- .oem_table_id = vms->oem_table_id }; +- +- acpi_table_begin(&table, table_data); +- +- /* Interface Type */ +- build_append_int_noprefix(table_data, 3, 1); /* ARM PL011 UART */ +- build_append_int_noprefix(table_data, 0, 3); /* Reserved */ +- /* Base Address */ +- build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3, +- vms->memmap[VIRT_UART].base); +- /* Interrupt Type */ +- build_append_int_noprefix(table_data, +- (1 << 3) /* Bit[3] ARMH GIC interrupt */, 1); +- build_append_int_noprefix(table_data, 0, 1); /* IRQ */ +- /* Global System Interrupt */ +- build_append_int_noprefix(table_data, +- vms->irqmap[VIRT_UART] + ARM_SPI_BASE, 4); +- build_append_int_noprefix(table_data, 3 /* 9600 */, 1); /* Baud Rate */ +- build_append_int_noprefix(table_data, 0 /* No Parity */, 1); /* Parity */ +- /* Stop Bits */ +- build_append_int_noprefix(table_data, 1 /* 1 Stop bit */, 1); +- /* Flow Control */ +- build_append_int_noprefix(table_data, +- (1 << 1) /* RTS/CTS hardware flow control */, 1); +- /* Terminal Type */ +- build_append_int_noprefix(table_data, 0 /* VT100 */, 1); +- build_append_int_noprefix(table_data, 0, 1); /* Language */ +- /* PCI Device ID */ +- build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2); +- /* PCI Vendor ID */ +- build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2); +- build_append_int_noprefix(table_data, 0, 1); /* PCI Bus Number */ +- build_append_int_noprefix(table_data, 0, 1); /* PCI Device Number */ +- build_append_int_noprefix(table_data, 0, 1); /* PCI Function Number */ +- build_append_int_noprefix(table_data, 0, 4); /* PCI Flags */ +- build_append_int_noprefix(table_data, 0, 1); /* PCI Segment */ +- build_append_int_noprefix(table_data, 0, 4); /* Reserved */ ++ AcpiSpcrData serial = { ++ .interface_type = 3, /* ARM PL011 UART */ ++ .base_addr.id = AML_AS_SYSTEM_MEMORY, ++ .base_addr.width = 32, ++ .base_addr.offset = 0, ++ .base_addr.size = 3, ++ .base_addr.addr = vms->memmap[VIRT_UART].base, ++ .interrupt_type = (1 << 3),/* Bit[3] ARMH GIC interrupt*/ ++ .pc_interrupt = 0, /* IRQ */ ++ .interrupt = (vms->irqmap[VIRT_UART] + ARM_SPI_BASE), ++ .baud_rate = 3, /* 9600 */ ++ .parity = 0, /* No Parity */ ++ .stop_bits = 1, /* 1 Stop bit */ ++ .flow_control = 1 << 1, /* RTS/CTS hardware flow control */ ++ .terminal_type = 0, /* VT100 */ ++ .language = 0, /* Language */ ++ .pci_device_id = 0xffff, /* not a PCI device*/ ++ .pci_vendor_id = 0xffff, /* not a PCI device*/ ++ .pci_bus = 0, ++ .pci_device = 0, ++ .pci_function = 0, ++ .pci_flags = 0, ++ .pci_segment = 0, ++ }; + +- acpi_table_end(linker, &table); ++ build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id); + } + + /* +@@ -930,7 +916,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) + } + + acpi_add_table(table_offsets, tables_blob); +- build_spcr(tables_blob, tables->linker, vms); ++ spcr_setup(tables_blob, tables->linker, vms); + + acpi_add_table(table_offsets, tables_blob); + build_dbg2(tables_blob, tables->linker, vms); +diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h +index 2b42e4192b..0e6e82b339 100644 +--- a/include/hw/acpi/acpi-defs.h ++++ b/include/hw/acpi/acpi-defs.h +@@ -90,6 +90,39 @@ typedef struct AcpiFadtData { + unsigned *xdsdt_tbl_offset; + } AcpiFadtData; + ++typedef struct AcpiGas { ++ uint8_t id; /* Address space ID */ ++ uint8_t width; /* Register bit width */ ++ uint8_t offset; /* Register bit offset */ ++ uint8_t size; /* Access size */ ++ uint64_t addr; /* Address */ ++} AcpiGas; ++ ++/* SPCR (Serial Port Console Redirection table) */ ++typedef struct AcpiSpcrData { ++ uint8_t interface_type; ++ uint8_t reserved[3]; ++ struct AcpiGas base_addr; ++ uint8_t interrupt_type; ++ uint8_t pc_interrupt; ++ uint32_t interrupt; /* Global system interrupt */ ++ uint8_t baud_rate; ++ uint8_t parity; ++ uint8_t stop_bits; ++ uint8_t flow_control; ++ uint8_t terminal_type; ++ uint8_t language; ++ uint8_t reserved1; ++ uint16_t pci_device_id; /* Must be 0xffff if not PCI device */ ++ uint16_t pci_vendor_id; /* Must be 0xffff if not PCI device */ ++ uint8_t pci_bus; ++ uint8_t pci_device; ++ uint8_t pci_function; ++ uint32_t pci_flags; ++ uint8_t pci_segment; ++ uint32_t reserved2; ++} AcpiSpcrData; ++ + #define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0) + #define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1) + +diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h +index 472940fcb1..5ede485780 100644 +--- a/include/hw/acpi/aml-build.h ++++ b/include/hw/acpi/aml-build.h +@@ -502,4 +502,8 @@ void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, + + void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, + const char *oem_id, const char *oem_table_id); ++ ++void build_spcr(GArray *table_data, BIOSLinker *linker, ++ const AcpiSpcrData *f, const uint8_t rev, ++ const char *oem_id, const char *oem_table_id); + #endif +-- +2.39.3 + diff --git a/0516-hw-riscv-virt-acpi-build-c-generate-spcr-table.patch b/0516-hw-riscv-virt-acpi-build-c-generate-spcr-table.patch new file mode 100644 index 0000000..0ee014e --- /dev/null +++ b/0516-hw-riscv-virt-acpi-build-c-generate-spcr-table.patch @@ -0,0 +1,78 @@ +From 135f6c7d08faa52112769db2beb820a12f82051d Mon Sep 17 00:00:00 2001 +From: Sia Jee Heng +Date: Sun, 28 Jan 2024 18:14:40 -0800 +Subject: [PATCH] hw/riscv/virt-acpi-build.c: Generate SPCR table + +commit 3e6f1e61b4bc0facd13967580feed47d96a2c28c upstream + +Generate Serial Port Console Redirection Table (SPCR) for RISC-V +virtual machine. + +Signed-off-by: Sia Jee Heng +Reviewed-by: Daniel Henrique Barboza +Message-ID: <20240129021440.17640-3-jeeheng.sia@starfivetech.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt-acpi-build.c | 39 ++++++++++++++++++++++++++++++++++++++ + 1 file changed, 39 insertions(+) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index bb6036db89..4b5a8b600b 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -198,6 +198,42 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, + aml_append(scope, dev); + } + ++/* ++ * Serial Port Console Redirection Table (SPCR) ++ * Rev: 1.07 ++ */ ++ ++static void ++spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s) ++{ ++ AcpiSpcrData serial = { ++ .interface_type = 0, /* 16550 compatible */ ++ .base_addr.id = AML_AS_SYSTEM_MEMORY, ++ .base_addr.width = 32, ++ .base_addr.offset = 0, ++ .base_addr.size = 1, ++ .base_addr.addr = s->memmap[VIRT_UART0].base, ++ .interrupt_type = (1 << 4),/* Bit[4] RISC-V PLIC/APLIC */ ++ .pc_interrupt = 0, ++ .interrupt = UART0_IRQ, ++ .baud_rate = 7, /* 15200 */ ++ .parity = 0, ++ .stop_bits = 1, ++ .flow_control = 0, ++ .terminal_type = 3, /* ANSI */ ++ .language = 0, /* Language */ ++ .pci_device_id = 0xffff, /* not a PCI device*/ ++ .pci_vendor_id = 0xffff, /* not a PCI device*/ ++ .pci_bus = 0, ++ .pci_device = 0, ++ .pci_function = 0, ++ .pci_flags = 0, ++ .pci_segment = 0, ++ }; ++ ++ build_spcr(table_data, linker, &serial, 2, s->oem_id, s->oem_table_id); ++} ++ + /* RHCT Node[N] starts at offset 56 */ + #define RHCT_NODE_ARRAY_OFFSET 56 + +@@ -587,6 +623,9 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) + acpi_add_table(table_offsets, tables_blob); + build_rhct(tables_blob, tables->linker, s); + ++ acpi_add_table(table_offsets, tables_blob); ++ spcr_setup(tables_blob, tables->linker, s); ++ + acpi_add_table(table_offsets, tables_blob); + { + AcpiMcfgInfo mcfg = { +-- +2.39.3 + diff --git a/0517-meson-mitigate-against-rop-exploits-with-fzero-call-.patch b/0517-meson-mitigate-against-rop-exploits-with-fzero-call-.patch new file mode 100644 index 0000000..66e9022 --- /dev/null +++ b/0517-meson-mitigate-against-rop-exploits-with-fzero-call-.patch @@ -0,0 +1,133 @@ +From 50e7bae89ce6a1bc6503537ace976f9c6770cf19 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= +Date: Wed, 3 Jan 2024 12:34:13 +0000 +Subject: [PATCH] meson: mitigate against ROP exploits with + -fzero-call-used-regs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +commit commit 043eaa0f0c8618382b2dba2f2e4fe762215b2e29 upstream + +To quote wikipedia: + + "Return-oriented programming (ROP) is a computer security exploit + technique that allows an attacker to execute code in the presence + of security defenses such as executable space protection and code + signing. + + In this technique, an attacker gains control of the call stack to + hijack program control flow and then executes carefully chosen + machine instruction sequences that are already present in the + machine's memory, called "gadgets". Each gadget typically ends in + a return instruction and is located in a subroutine within the + existing program and/or shared library code. Chained together, + these gadgets allow an attacker to perform arbitrary operations + on a machine employing defenses that thwart simpler attacks." + +QEMU is by no means perfect with an ever growing set of CVEs from +flawed hardware device emulation, which could potentially be +exploited using ROP techniques. + +Since GCC 11 there has been a compiler option that can mitigate +against this exploit technique: + + -fzero-call-user-regs + +To understand it refer to these two resources: + + https://www.jerkeby.se/newsletter/posts/rop-reduction-zero-call-user-regs/ + https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552262.html + +I used two programs to scan qemu-system-x86_64 for ROP gadgets: + + https://github.com/0vercl0k/rp + https://github.com/JonathanSalwan/ROPgadget + +When asked to find 8 byte gadgets, the 'rp' tool reports: + + A total of 440278 gadgets found. + You decided to keep only the unique ones, 156143 unique gadgets found. + +While the ROPgadget tool reports: + + Unique gadgets found: 353122 + +With the --ropchain argument, the latter attempts to use the found +gadgets to product a chain that can execute arbitrary syscalls. With +current QEMU it succeeds in this task, which is an undesirable +situation. + +With QEMU modified to use -fzero-call-user-regs=used-gpr the 'rp' tool +reports + + A total of 528991 gadgets found. + You decided to keep only the unique ones, 121128 unique gadgets found. + +This is 22% fewer unique gadgets + +While the ROPgadget tool reports: + + Unique gadgets found: 328605 + +This is 7% fewer unique gadgets. Crucially though, despite this more +modest reduction, the ROPgadget tool is no longer able to identify a +chain of gadgets for executing arbitrary syscalls. It fails at the +very first step, unable to find gadgets for populating registers for +a future syscall. Having said that, more advanced tools do still +manage to put together a viable ROP chain. + +Also this only takes into account QEMU code. QEMU links to many 3rd +party shared libraries and ideally all of them would be compiled with +this same hardening. That becomes a distro policy question though. + +In terms of performance impact, TCG was used as an evaluation test +case. We're not interested in protecting TCG since it isn't designed +to provide a security barrier, but it is performance sensitive code, +so useful as a guide to how other areas of QEMU might be impacted. +With the -fzero-call-user-regs=used-gpr argument present, using the +real world test of booting a linux kernel and having init immediately +poweroff, there is a ~1% slow down in performance under TCG. The QEMU +binary size also grows by approximately 1%. + +By comparison, using the more aggressive -fzero-call-user-regs=all, +results in a slowdown of over 25% in TCG, which is clearly not an +acceptable impact, and a binary size increase of 5%. + +Considering that 'used-gpr' successfully stopped ROPgadget assembling +a chain, this more targeted protection is a justifiable hardening +/ performance tradeoff. + +Reviewed-by: Thomas Huth +Signed-off-by: "Daniel P. Berrangé" +Message-ID: <20240103123414.2401208-2-berrange@redhat.com> +Signed-off-by: Thomas Huth +--- + meson.build | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/meson.build b/meson.build +index 5318b28e44..6d88831dc5 100644 +--- a/meson.build ++++ b/meson.build +@@ -558,6 +558,17 @@ if get_option('cfi') + add_global_link_arguments(cfi_flags, native: false, language: all_languages) + endif + ++# Check further flags that make QEMU more robust against malicious parties ++ ++hardening_flags = [ ++ # Zero out registers used during a function call ++ # upon its return. This makes it harder to assemble ++ # ROP gadgets into something usable ++ '-fzero-call-used-regs=used-gpr', ++] ++ ++qemu_common_flags += cc.get_supported_arguments(hardening_flags) ++ + add_global_arguments(qemu_common_flags, native: false, language: all_languages) + add_global_link_arguments(qemu_ldflags, native: false, language: all_languages) + +-- +2.39.3 + diff --git a/0518-meson-mitigate-against-use-of-uninitialize-stack-for.patch b/0518-meson-mitigate-against-use-of-uninitialize-stack-for.patch new file mode 100644 index 0000000..89a2749 --- /dev/null +++ b/0518-meson-mitigate-against-use-of-uninitialize-stack-for.patch @@ -0,0 +1,65 @@ +From 4ad2960c4bf57aa163190b4d06d2537e950f23bb Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= +Date: Wed, 3 Jan 2024 12:34:14 +0000 +Subject: [PATCH] meson: mitigate against use of uninitialize stack for + exploits +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +commit 7ff9ff039380008952c6fd32011dd2a4d5666906 upstream + +When variables are used without being initialized, there is potential +to take advantage of data that was pre-existing on the stack from an +earlier call, to drive an exploit. + +It is good practice to always initialize variables, and the compiler +can warn about flaws when -Wuninitialized is present. This warning, +however, is by no means foolproof with its output varying depending +on compiler version and which optimizations are enabled. + +The -ftrivial-auto-var-init option can be used to tell the compiler +to always initialize all variables. This increases the security and +predictability of the program, closing off certain attack vectors, +reducing the risk of unsafe memory disclosure. + +While the option takes several possible values, using 'zero' is +considered to be the option that is likely to lead to semantically +correct or safe behaviour[1]. eg sizes/indexes are not likely to +lead to out-of-bounds accesses when initialized to zero. Pointers +are less likely to point something useful if initialized to zero. + +Even with -ftrivial-auto-var-init=zero set, GCC will still issue +warnings with -Wuninitialized if it discovers a problem, so we are +not loosing diagnostics for developers, just hardening runtime +behaviour and making QEMU behave more predictably in case of hitting +bad codepaths. + +[1] https://lists.llvm.org/pipermail/cfe-dev/2020-April/065221.html + +Signed-off-by: "Daniel P. Berrangé" +Message-ID: <20240103123414.2401208-3-berrange@redhat.com> +Signed-off-by: Thomas Huth +--- + meson.build | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/meson.build b/meson.build +index 6d88831dc5..ba68cb6759 100644 +--- a/meson.build ++++ b/meson.build +@@ -565,6 +565,11 @@ hardening_flags = [ + # upon its return. This makes it harder to assemble + # ROP gadgets into something usable + '-fzero-call-used-regs=used-gpr', ++ ++ # Initialize all stack variables to zero. This makes ++ # it harder to take advantage of uninitialized stack ++ # data to drive exploits ++ '-ftrivial-auto-var-init=zero', + ] + + qemu_common_flags += cc.get_supported_arguments(hardening_flags) +-- +2.39.3 + diff --git a/0519-hw-vfio-hct-sharing-ccp-resources-between-host-and-v.patch b/0519-hw-vfio-hct-sharing-ccp-resources-between-host-and-v.patch new file mode 100644 index 0000000..2224c2a --- /dev/null +++ b/0519-hw-vfio-hct-sharing-ccp-resources-between-host-and-v.patch @@ -0,0 +1,186 @@ +From a36d2a0a1f773ff1582b0ac3e1bd4c00b22bb02b Mon Sep 17 00:00:00 2001 +From: Yabin Li +Date: Fri, 19 Jul 2024 15:45:27 +0800 +Subject: [PATCH] hw/vfio/hct: sharing CCP resources between host and virtual + machines. + +ccp support been used by guest and host at same time + +Signed-off-by: liyabin +Signed-off-by: yangdepei +--- + hw/vfio/hct.c | 112 ++++++++++++++++++++++++++++++++++---------------- + 1 file changed, 76 insertions(+), 36 deletions(-) + +diff --git a/hw/vfio/hct.c b/hw/vfio/hct.c +index 2f40bf5c93..dd541f7f8b 100644 +--- a/hw/vfio/hct.c ++++ b/hw/vfio/hct.c +@@ -43,7 +43,7 @@ + + #define HCT_SHARE_DEV "/dev/hct_share" + +-#define HCT_VERSION_STRING "0.5" ++#define HCT_VERSION_STRING "0.6" + #define DEF_VERSION_STRING "0.1" + #define VERSION_SIZE 16 + +@@ -64,6 +64,8 @@ + #define HCT_PASID_BAR_IDX 4 + + #define PASID_OFFSET 40 ++#define HCT_PASID_MEM_GID_OFFSET 1024 ++#define HCT_PASID_MEM_MDEV_OFFSET 2048 + + static volatile struct hct_data { + int init; +@@ -94,31 +96,91 @@ struct hct_dev_ctrl { + unsigned char rsvd[3]; + union { + unsigned char version[VERSION_SIZE]; ++ unsigned int id; ++ unsigned int pasid; + struct { + unsigned long vaddr; + unsigned long iova; + unsigned long size; + }; +- unsigned int id; + }; + }; + ++ ++static int hct_get_sysfs_value(const char *path, int *val) ++{ ++ FILE *fp = NULL; ++ char buf[CCP_INDEX_BYTES]; ++ unsigned long v; ++ ++ fp = fopen(path, "r"); ++ if (!fp) { ++ error_report("fail to open %s, errno %d.\n", path, errno); ++ return -EINVAL; ++ } ++ ++ if (fgets(buf, sizeof(buf), fp) == NULL) { ++ fclose(fp); ++ return -EINVAL; ++ } ++ ++ if (1 != sscanf(buf, "%lu", &v)) { ++ fclose(fp); ++ return -EINVAL; ++ } ++ ++ *val = (int)v; ++ ++ fclose(fp); ++ return 0; ++} ++ ++/* ++ * the memory layout of pasid_memory is as follows: ++ * offset -- 0 1024 2048 4096 ++ * a page -- |pasid(8B) --- |gid(8B) --- |mdev_idx(8B) --- | ++ */ + static int pasid_get_and_init(HCTDevState *state) + { ++ void *base = (void *)hct_data.pasid_memory; + struct hct_dev_ctrl ctrl; ++ unsigned long *gid = NULL; ++ unsigned long *mdev_idx = NULL; ++ char path[PATH_MAX]; ++ int index; + int ret; + + ctrl.op = HCT_SHARE_OP_GET_PASID; +- ctrl.id = -1; + ret = ioctl(hct_data.hct_fd, HCT_SHARE_OP, &ctrl); + if (ret < 0) { + ret = -errno; +- error_report("GET_PASID fail: %d", -errno); ++ error_report("get pasid fail, errno: %d.", errno); + goto out; + } + +- *hct_data.pasid_memory = ctrl.id; +- hct_data.pasid = ctrl.id; ++ hct_data.pasid = (unsigned long)ctrl.pasid; ++ *(unsigned long *)base = (unsigned long)ctrl.pasid; ++ ++ ctrl.op = HCT_SHARE_OP_GET_ID; ++ ret = ioctl(hct_data.hct_fd, HCT_SHARE_OP, &ctrl); ++ if (ret < 0) { ++ ret = -errno; ++ error_report("get gid fail, errno: %d", errno); ++ goto out; ++ } ++ ++ gid = (unsigned long *)((unsigned long)base + HCT_PASID_MEM_GID_OFFSET); ++ *(unsigned long *)gid = (unsigned long)ctrl.id; ++ ++ snprintf(path, PATH_MAX, "%s/vendor/idx", state->vdev.sysfsdev); ++ if (hct_get_sysfs_value(path, &index)) { ++ ret = -EINVAL; ++ error_report("get %s sysfs value fail.\n", path); ++ goto out; ++ } ++ ++ mdev_idx = (unsigned long *)((unsigned long)base + HCT_PASID_MEM_MDEV_OFFSET); ++ *(unsigned long *)mdev_idx = (unsigned long)index; + + out: + return ret; +@@ -236,41 +298,19 @@ static int hct_check_duplicated_index(int index) + static int hct_get_ccp_index(HCTDevState *state) + { + char path[PATH_MAX]; +- char buf[CCP_INDEX_BYTES]; +- int fd; +- int ret; +- int ccp_index; ++ int index; + + snprintf(path, PATH_MAX, "%s/vendor/id", state->vdev.sysfsdev); +- fd = qemu_open_old(path, O_RDONLY); +- if (fd < 0) { +- error_report("open %s fail\n", path); +- return -errno; +- } +- +- memset(buf, 0, sizeof(buf)); +- ret = read(fd, buf, sizeof(buf)); +- if (ret < 0) { +- ret = -errno; +- error_report("read %s fail\n", path); +- goto out; +- } +- +- if (1 != sscanf(buf, "%d", &ccp_index)) { +- ret = -errno; +- error_report("format addr %s fail\n", buf); +- goto out; ++ if (hct_get_sysfs_value(path, &index)) { ++ error_report("get %s sysfs value fail.\n", path); ++ return -1; + } + +- if (!hct_check_duplicated_index(ccp_index)) { +- state->sdev.shared_memory_offset = ccp_index; +- } else { +- ret = -1; +- } ++ if (hct_check_duplicated_index(index)) ++ return -1; + +-out: +- qemu_close(fd); +- return ret; ++ state->sdev.shared_memory_offset = index; ++ return 0; + } + + static int hct_api_version_check(void) +-- +2.39.3 + diff --git a/0520-hw-vfio-hct-compatible-with-hct-ko-modules-in-versio.patch b/0520-hw-vfio-hct-compatible-with-hct-ko-modules-in-versio.patch new file mode 100644 index 0000000..20f4bfd --- /dev/null +++ b/0520-hw-vfio-hct-compatible-with-hct-ko-modules-in-versio.patch @@ -0,0 +1,105 @@ +From 37224712dfbac6f1ff6075f3b05afd9418fc1a72 Mon Sep 17 00:00:00 2001 +From: Yabin Li +Date: Wed, 31 Jul 2024 14:27:58 +0800 +Subject: [PATCH] hw/vfio/hct: compatible with hct.ko modules in versions 0.5 + and earlier. + +Signed-off-by: liyabin +Signed-off-by: yangdepei +--- + hw/vfio/hct.c | 33 +++++++++++++++++++++------------ + 1 file changed, 21 insertions(+), 12 deletions(-) + +diff --git a/hw/vfio/hct.c b/hw/vfio/hct.c +index dd541f7f8b..83e15e18d3 100644 +--- a/hw/vfio/hct.c ++++ b/hw/vfio/hct.c +@@ -29,6 +29,7 @@ + #include "hw/qdev-properties.h" + + #define MAX_CCP_CNT 48 ++#define DEF_CCP_CNT_MAX 16 + #define PAGE_SIZE 4096 + #define HCT_SHARED_MEMORY_SIZE (PAGE_SIZE * MAX_CCP_CNT) + #define CCP_INDEX_BYTES 4 +@@ -45,6 +46,8 @@ + + #define HCT_VERSION_STRING "0.6" + #define DEF_VERSION_STRING "0.1" ++#define HCT_VERSION_STR_02 "0.2" ++#define HCT_VERSION_STR_05 "0.5" + #define VERSION_SIZE 16 + + #define HCT_SHARE_IOC_TYPE 'C' +@@ -71,6 +74,7 @@ static volatile struct hct_data { + int init; + int hct_fd; + unsigned long pasid; ++ unsigned long hct_shared_size; + uint8_t *pasid_memory; + uint8_t *hct_shared_memory; + uint8_t ccp_index[MAX_CCP_CNT]; +@@ -322,17 +326,22 @@ static int hct_api_version_check(void) + memcpy(ctrl.version, DEF_VERSION_STRING, sizeof(DEF_VERSION_STRING)); + ret = ioctl(hct_data.hct_fd, HCT_SHARE_OP, &ctrl); + if (ret < 0) { +- error_report("ret %d, errno %d: fail to get hct.ko version.\n", ret, +- errno); ++ error_report("ret %d, errno %d: fail to get hct.ko version.\n", ret, errno); + return -1; +- } else if (memcmp(ctrl.version, HCT_VERSION_STRING, +- sizeof(HCT_VERSION_STRING)) < 0) { +- error_report("The hct.ko version is %s, please upgrade to version %s " +- "or higher.\n", +- ctrl.version, HCT_VERSION_STRING); ++ } else if (memcmp(ctrl.version, HCT_VERSION_STR_02, sizeof(HCT_VERSION_STR_02)) < 0) { ++ error_report("The hct.ko version is %s, please upgrade to version %s or higher.\n", ++ ctrl.version, HCT_VERSION_STR_02); + return -1; ++ } else if (memcmp(ctrl.version, HCT_VERSION_STRING, sizeof(HCT_VERSION_STRING)) != 0) { ++ info_report("The hct.ko version is %s, please upgrade to version %s.\n", ++ ctrl.version, HCT_VERSION_STRING); + } + ++ if (memcmp(ctrl.version, HCT_VERSION_STR_05, sizeof(HCT_VERSION_STR_05)) < 0) ++ hct_data.hct_shared_size = PAGE_SIZE * DEF_CCP_CNT_MAX; ++ else ++ hct_data.hct_shared_size = HCT_SHARED_MEMORY_SIZE; ++ + return 0; + } + +@@ -340,9 +349,9 @@ static int hct_shared_memory_init(void) + { + int ret = 0; + +- hct_data.hct_shared_memory = +- mmap(NULL, HCT_SHARED_MEMORY_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, +- hct_data.hct_fd, 0); ++ hct_data.hct_shared_memory = mmap(NULL, hct_data.hct_shared_size, ++ PROT_READ | PROT_WRITE, MAP_SHARED, ++ hct_data.hct_fd, 0); + if (hct_data.hct_shared_memory == MAP_FAILED) { + ret = -errno; + error_report("map hct shared memory fail\n"); +@@ -442,7 +451,7 @@ static void hct_data_uninit(HCTDevState *state) + } + + if (hct_data.hct_shared_memory) { +- munmap((void *)hct_data.hct_shared_memory, HCT_SHARED_MEMORY_SIZE); ++ munmap((void *)hct_data.hct_shared_memory, hct_data.hct_shared_size); + hct_data.hct_shared_memory = NULL; + } + +@@ -495,7 +504,7 @@ unmap_pasid_memory_exit: + munmap(hct_data.pasid_memory, PAGE_SIZE); + + unmap_shared_memory_exit: +- munmap((void *)hct_data.hct_shared_memory, HCT_SHARED_MEMORY_SIZE); ++ munmap((void *)hct_data.hct_shared_memory, hct_data.hct_shared_size); + + out: + return ret; +-- +2.39.3 + diff --git a/0521-hw-vfio-hct-fix-ccp-index-error-caused-by-uninitiali.patch b/0521-hw-vfio-hct-fix-ccp-index-error-caused-by-uninitiali.patch new file mode 100644 index 0000000..b4bd6c6 --- /dev/null +++ b/0521-hw-vfio-hct-fix-ccp-index-error-caused-by-uninitiali.patch @@ -0,0 +1,36 @@ +From 381c7da605a60f85ece78aacc779e93f4cfe12aa Mon Sep 17 00:00:00 2001 +From: yangdepei +Date: Tue, 27 Aug 2024 13:58:35 +0800 +Subject: [PATCH] hw/vfio/hct: fix ccp index error caused by uninitialized buf + +Signed-off-by: liyabin +Signed-off-by: yangdepei +--- + hw/vfio/hct.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/hw/vfio/hct.c b/hw/vfio/hct.c +index 83e15e18d3..f6724a38fb 100644 +--- a/hw/vfio/hct.c ++++ b/hw/vfio/hct.c +@@ -114,7 +114,7 @@ struct hct_dev_ctrl { + static int hct_get_sysfs_value(const char *path, int *val) + { + FILE *fp = NULL; +- char buf[CCP_INDEX_BYTES]; ++ char buf[CCP_INDEX_BYTES] = {0}; + unsigned long v; + + fp = fopen(path, "r"); +@@ -301,7 +301,7 @@ static int hct_check_duplicated_index(int index) + + static int hct_get_ccp_index(HCTDevState *state) + { +- char path[PATH_MAX]; ++ char path[PATH_MAX] = {0}; + int index; + + snprintf(path, PATH_MAX, "%s/vendor/id", state->vdev.sysfsdev); +-- +2.39.3 + diff --git a/0522-hw-vfio-hct-remove-the-operation-of-reading-the-valu.patch b/0522-hw-vfio-hct-remove-the-operation-of-reading-the-valu.patch new file mode 100644 index 0000000..c8fd46a --- /dev/null +++ b/0522-hw-vfio-hct-remove-the-operation-of-reading-the-valu.patch @@ -0,0 +1,131 @@ +From c1d44b21fdcdf3a1d693e33794c160e34cd84057 Mon Sep 17 00:00:00 2001 +From: Yabin Li +Date: Wed, 4 Sep 2024 20:55:42 +0800 +Subject: [PATCH] hw/vfio/hct: remove the operation of reading the value of + mdev index in qemu. + +Signed-off-by: liyabin +Signed-off-by: yangdepei +--- + hw/vfio/hct.c | 45 ++++++++++++++++++++++++--------------------- + 1 file changed, 24 insertions(+), 21 deletions(-) + +diff --git a/hw/vfio/hct.c b/hw/vfio/hct.c +index f6724a38fb..953d7b03a8 100644 +--- a/hw/vfio/hct.c ++++ b/hw/vfio/hct.c +@@ -44,10 +44,10 @@ + + #define HCT_SHARE_DEV "/dev/hct_share" + +-#define HCT_VERSION_STRING "0.6" + #define DEF_VERSION_STRING "0.1" + #define HCT_VERSION_STR_02 "0.2" + #define HCT_VERSION_STR_05 "0.5" ++#define HCT_VERSION_STR_06 "0.6" + #define VERSION_SIZE 16 + + #define HCT_SHARE_IOC_TYPE 'C' +@@ -68,7 +68,6 @@ + + #define PASID_OFFSET 40 + #define HCT_PASID_MEM_GID_OFFSET 1024 +-#define HCT_PASID_MEM_MDEV_OFFSET 2048 + + static volatile struct hct_data { + int init; +@@ -77,6 +76,7 @@ static volatile struct hct_data { + unsigned long hct_shared_size; + uint8_t *pasid_memory; + uint8_t *hct_shared_memory; ++ uint8_t hct_version[VERSION_SIZE]; + uint8_t ccp_index[MAX_CCP_CNT]; + uint8_t ccp_cnt; + } hct_data; +@@ -110,6 +110,11 @@ struct hct_dev_ctrl { + }; + }; + ++enum MDEV_USED_TYPE { ++ MDEV_USED_FOR_HOST, ++ MDEV_USED_FOR_VM, ++ MDEV_USED_UNDEF ++}; + + static int hct_get_sysfs_value(const char *path, int *val) + { +@@ -141,17 +146,14 @@ static int hct_get_sysfs_value(const char *path, int *val) + + /* + * the memory layout of pasid_memory is as follows: +- * offset -- 0 1024 2048 4096 +- * a page -- |pasid(8B) --- |gid(8B) --- |mdev_idx(8B) --- | ++ * offset -- 0 1024 4096 ++ * a page -- |pasid(8B) --- |gid(8B) --- | + */ + static int pasid_get_and_init(HCTDevState *state) + { + void *base = (void *)hct_data.pasid_memory; + struct hct_dev_ctrl ctrl; + unsigned long *gid = NULL; +- unsigned long *mdev_idx = NULL; +- char path[PATH_MAX]; +- int index; + int ret; + + ctrl.op = HCT_SHARE_OP_GET_PASID; +@@ -176,16 +178,6 @@ static int pasid_get_and_init(HCTDevState *state) + gid = (unsigned long *)((unsigned long)base + HCT_PASID_MEM_GID_OFFSET); + *(unsigned long *)gid = (unsigned long)ctrl.id; + +- snprintf(path, PATH_MAX, "%s/vendor/idx", state->vdev.sysfsdev); +- if (hct_get_sysfs_value(path, &index)) { +- ret = -EINVAL; +- error_report("get %s sysfs value fail.\n", path); +- goto out; +- } +- +- mdev_idx = (unsigned long *)((unsigned long)base + HCT_PASID_MEM_MDEV_OFFSET); +- *(unsigned long *)mdev_idx = (unsigned long)index; +- + out: + return ret; + } +@@ -302,7 +294,20 @@ static int hct_check_duplicated_index(int index) + static int hct_get_ccp_index(HCTDevState *state) + { + char path[PATH_MAX] = {0}; +- int index; ++ int mdev_used, index; ++ ++ if (memcmp((void *)hct_data.hct_version, HCT_VERSION_STR_06, ++ sizeof(HCT_VERSION_STR_06)) >= 0) { ++ snprintf(path, PATH_MAX, "%s/vendor/use", state->vdev.sysfsdev); ++ if (hct_get_sysfs_value(path, &mdev_used)) { ++ error_report("get %s sysfs value fail.\n", path); ++ return -1; ++ } else if (mdev_used != MDEV_USED_FOR_VM) { ++ error_report("The value of file node(%s) is %d, should be MDEV_USED_FOR_VM(%d), pls check.\n", ++ path, mdev_used, MDEV_USED_FOR_VM); ++ return -1; ++ } ++ } + + snprintf(path, PATH_MAX, "%s/vendor/id", state->vdev.sysfsdev); + if (hct_get_sysfs_value(path, &index)) { +@@ -332,11 +337,9 @@ static int hct_api_version_check(void) + error_report("The hct.ko version is %s, please upgrade to version %s or higher.\n", + ctrl.version, HCT_VERSION_STR_02); + return -1; +- } else if (memcmp(ctrl.version, HCT_VERSION_STRING, sizeof(HCT_VERSION_STRING)) != 0) { +- info_report("The hct.ko version is %s, please upgrade to version %s.\n", +- ctrl.version, HCT_VERSION_STRING); + } + ++ memcpy((void *)hct_data.hct_version, (void *)ctrl.version, sizeof(hct_data.hct_version)); + if (memcmp(ctrl.version, HCT_VERSION_STR_05, sizeof(HCT_VERSION_STR_05)) < 0) + hct_data.hct_shared_size = PAGE_SIZE * DEF_CCP_CNT_MAX; + else +-- +2.39.3 + diff --git a/qemu.spec b/qemu.spec index 1363326..832e2a3 100644 --- a/qemu.spec +++ b/qemu.spec @@ -1,4 +1,4 @@ -%define anolis_release 34 +%define anolis_release 35 %bcond_with check %global all_system_emu_support 0 @@ -783,6 +783,31 @@ Patch0494: 0494-hw-usb-hcd-ohci-fix-1510-303-pid-not-in-or-out.patch Patch0495: 0495-target-riscv-kvm-c-fix-the-hart-bit-setting-of-aia.patch Patch0496: 0496-target-riscv-kvm-c-remove-group-setting-of-kvm-aia-i.patch Patch0497: 0497-target-riscv-kvm-fix-the-group-bit-setting-of-aia.patch +Patch0498: 0498-hw-arm-virt-acpi-build-c-migrate-fw-cfg-creation-to-.patch +Patch0499: 0499-hw-arm-virt-acpi-build-c-migrate-virtio-creation-to-.patch +Patch0500: 0500-hw-i386-acpi-microvm-c-use-common-function-to-add-vi.patch +Patch0501: 0501-hw-riscv-virt-make-few-imsic-macros-and-functions-pu.patch +Patch0502: 0502-hw-riscv-virt-acpi-build-c-add-aia-support-in-rintc.patch +Patch0503: 0503-hw-riscv-virt-acpi-build-c-add-imsic-in-the-madt.patch +Patch0504: 0504-hw-riscv-virt-acpi-build-c-add-aplic-in-the-madt.patch +Patch0505: 0505-hw-riscv-virt-acpi-build-c-add-cmo-information-in-rh.patch +Patch0506: 0506-hw-riscv-virt-acpi-build-c-add-mmu-node-in-rhct.patch +Patch0507: 0507-hw-pci-host-gpex-define-properties-for-mmio-ranges.patch +Patch0508: 0508-hw-riscv-virt-update-gpex-mmio-related-properties.patch +Patch0509: 0509-hw-riscv-virt-acpi-build-c-add-io-controllers-and-de.patch +Patch0510: 0510-hw-riscv-virt-acpi-build-c-add-plic-in-madt.patch +Patch0511: 0511-hw-riscv-virt-c-fix-the-interrupts-extended-property.patch +Patch0512: 0512-hw-riscv-virt-acpi-build-c-add-namespace-devices-for.patch +Patch0513: 0513-hw-riscv-virt-acpi-build-c-update-the-hid-of-risc-v-.patch +Patch0514: 0514-acpi-gpex-create-pci-link-devices-outside-pci-root-b.patch +Patch0515: 0515-hw-arm-virt-acpi-build-c-migrate-spcr-creation-to-co.patch +Patch0516: 0516-hw-riscv-virt-acpi-build-c-generate-spcr-table.patch +Patch0517: 0517-meson-mitigate-against-rop-exploits-with-fzero-call-.patch +Patch0518: 0518-meson-mitigate-against-use-of-uninitialize-stack-for.patch +Patch0519: 0519-hw-vfio-hct-sharing-ccp-resources-between-host-and-v.patch +Patch0520: 0520-hw-vfio-hct-compatible-with-hct-ko-modules-in-versio.patch +Patch0521: 0521-hw-vfio-hct-fix-ccp-index-error-caused-by-uninitiali.patch +Patch0522: 0522-hw-vfio-hct-remove-the-operation-of-reading-the-valu.patch ExclusiveArch: x86_64 aarch64 loongarch64 riscv64 @@ -2347,6 +2372,10 @@ useradd -r -u 107 -g qemu -G kvm -d / -s /sbin/nologin \ %endif %changelog +* Thu Oct 09 2025 wh02252983 - 2:8.2.0-35 +- RISC-V: ACPI: Enable AIA and update RHCT +- update hct device, to support latest HCT version (HCT2.1) + * Mon Sep 15 2025 wh02252983 - 2:8.2.0-34 - block: Parse filenames only when explicitly requested - hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or OUT -- Gitee