diff --git a/ChangeLog.md b/ChangeLog.md index 7b3e87e373c8bc5683465bb803d6e63166f55f0d..8ac4fc2ab89b6eb87adecfa758709c09cb4cf8f3 100644 --- a/ChangeLog.md +++ b/ChangeLog.md @@ -1,3 +1,155 @@ +# RT-Thread v4.0.2 Change Log + +Change log since v4.0.1 + +## Kernel + +* Split the component automatic initialization to component automatic initialization and main funciton; +* Add spin lock API in SMP mode; +* Fix RT_IDLE_HOOK spelling issue; +* Add thread waiting for message queue when queue is full; +* Fix the issue of delete mq in `rt_mq_create` in some abnormal case; +* Remove the C++ keywords in the`rt_console_set_device`function; +* Remove the `suspend_thread_count` member from memory_pool structure; +* Fix the issue when block = NULL in rt_mp_free; +* Fix the issue of incorrect scheduling task sequence caused by rt_thread_yeild in system scheduling; +* Fix the issue that the interrupt is opened too late and cause the signal handling delayed; +* When disable SMP, `cpu.c` will not be added into project by default; +* Fix the issue that `rt_thread_exit` turned on the interrupt prematurely in the SMP mode, so other cores might delete this task, causing the issue in subsequent function stacks; +* Fix the issue of critical protection when `rt_thread_delete` change the status of thread; + +## Components + +* Fix the issue of mPool size in C++ / Queue; +* Add the error status return in C++ / Thread task join/wait function; +* Fix compilation warning in DFS/ELM FatFS; +* Add support for Linux NFS Server in DFS/NFS; +* Fix mkfs issue in DFS/UFFS; +* Add ftruncate, flock, getuid, umask APIs; +* Fix the display issue of fd with offset in list_fd command; +* Add `dfs_mount_device` API to mount a file system on a device which is already in mount_table; +* Rename the C++ keywords in DFS/rename function; +* Connnect dfs/poll, select with RT_USING_POSIX in Kconfig; +* Optimize the part of the code of finsh to make it more simple; +* When RT_USING_DEVICE is not used, finsh can use the `rt_hw_console_getchar()` function which is simple to implement and not using the device framework; +* Increase the line length of the finsh shell to more than 256 characters; +* utest can support clang compiler and C++ compiler; +* Fix possible cross-boundary issues in ulog; +* Fix compilation warning in `ulog/ulog_console_backend_output`; +* Add support for file sending and receiving feature in YModem; +* CRC16 can be calculated without the lookup talbe to reduce code size in YModem component; +* Fix the issue that stack may be wrongly released during pthread/destory; +* Fix the possible memory leaks issue which caused by pthread_create abnormal case; +* The timer-related APIs under different compiler of libc are moved to the `libc\compilers\common` folder; +* Remove redundant definitions in `dlib/sys/unistd.h` (which will cause compilation warnings); +* Add `sys/errno.h` and`sys/signal.h` header files under dlib; +* Freemodbus is no longer in the kernel, and split it as a standalone softwre package; +* AT socket updated to v1.3.0: + - Add multi-client and multi-device function support in AT Socket, and improve the dirty data handling when AT device hardware module reboot; + - Support netdev network card feature, which can manage and control AT device network connection through the network card interface; +* Improve AT Server function support in AT components, add AT Server data sending and receiving interfaces `at_server_send ()` and `at_server_recv ()`; +* Fix the issue of `closesocket()` in SAL component when socket closing failure after `shutdown()`; +* Improve `sal_bind ()` network card binding related function in SAL component; +* Add IPV6 related options configuration and function support to SAL and netdev; +* Improve ping command error handling and log display in the netdev; +* Add hostname configuration options and functions in lwIP component; +* Fix the assertion issue of `sys_arch_mbox_fetch()` in lwIP which may occur when a socket is closed; +* Add network card uninstallation function and support for dhcpd service stop function to the lwip component; +* Fix lwIP component compilation failure caused by closing FinSH component; +* Fix the issue that the socket may not be closed during the DHCPD task in the lwIP DHCP server; +* Add `dhcpd_stop()` interface; +* Change log in device driver framework: + * Refactor audio driver framework; + * Fix the issue that the receiving length is 0 in CAN and the issue of returning wrong values; + * Add hardware encryption and decryption driver framework; + * Fix the flag handling issue of `rt_i2c_master_send/rt_i2c_master_recv`; + * Add input capture and pulse encoding driver framework; + * Fix the issue that partition lock is deleted when `rt_mmcsd_blk_remove`; + * Fix the issue that the enumerated capacity of the large-capacity card in MMC/SD exceeded the data range; + * When the SDIO device is initialized, the function's manufacturer and product can also use the information in CIS; + * Improve the interrupt mode handling in the sensor framework, and fix the issue that the memory is not released when registering the sensor; + * More information are provided in command line of sensor framework; + * Add the checking for Rx buffer size in the serial port framework, and provide a notification when RX buffer full; + * Remove the old Nor SPI Flash driver in SPI framework, and replace with SFUD component; + * Fix some judgements issue in the return value of SFUD; + * Fix the definition warning of `SFUD_FLASH_DEVICE_TABLE` in SFUD; + * Add support for W25Q64DW devices in SFUD; + * Fix FiFo creation failure handling when creating a pipe; + * Fix the issue of releasing RBB in advance in `rt_rbb_destroy()` function; + * Rename the new keyword using of C++ in `rt_rbb_blk_alloc` function; + * Unify the `struct rt_delayed_work` in workqueue to `struct rt_work`; + * Add touch driver framework; + * Add USB Audio class; + * Fix RNDIS plug-in/out issue in USB device stack; + * Add the interface callback function in USB device stack; + * Improve wlan framework, including command line functions, handling of AP name, password length, support for netdev, better configurability, etc. + +## BSP and CPU porting + +* Add Clang compiler support in ARM-related CPU porting; +* Fix SCB_AIRCR definition issue in ARM Cortex-M0; +* Add ARM Cortex-M33 porting; +* Add DMB/DSB related operations for cache operations in ARM Cortex-A porting; +* Add FPU support in ARM Cortex-A porting; +* Re-organize MIPS port. And XBurst related porting are moved to X1000 BSP; +* The porting of loongson 1B and 1C CPU are combined into one GS232 porting; +* Add support for RISC-V Hummingbird processor porting; +* The context switch exit operation of risc-v is forced back to machine mode; +* Fix the issue of switch interruption during TI C28x DSP porting; +* Add _ffs like implementation in the TI C28x DSP porting; +* Unify the .data .bss section to 8bytes alignment in GCC tool chain; +* The es32f0334 BSP is moved to `bsp/essemi/es32f0334`; +* Add `bsp/essemi/es8p508x` BSP, including UART and GPIO drivers; +* Add GD32VF103V-EVAL (RISC-V MCU) BSP, including UART driver; +* Rerange NXP i.MXRT BSP and add related BSP documents; +* Add i.MXRT1052 ATK Commander, Fire Pro BSP and i.MXRT1064 EVK BSP to the new i.MXRT BSP; +* Add BSP for NXP LPC55S6X series, and increase support for NXP official development board LPC55S69-EVK; +* Fix I2C operation (master_xfer) in LPC54114-lite BSP; +* Add Audio driver in LPC54114-lite BSP; +* Update Loongson 1B BSP and use automatic component initialization in default; +* Add Kconfig configuration for Loongson 1B BSP; +* Add QEMU/mipssim BSP for simulate RT-Thread/MIPS without MIPS hardware; +* Refactor qemu-vexpress-a9's Audio driver and fix the issue of OS Tick accuracy; +* Add LPUART driver to RV32M1 VEGA BSP; +* Remove old STM32 BSP: stm32f4xx-HAL, stm32f10x, stm32f10x-HAL, stm32f429-apollo, stm32f429-disco, stm32h743-nucleo; +* Fix the issue of `rt_hw_sci_init()` for opening the global interrupt in tms320f28379d BSP; +* Add support of soft I2C and hardware encryption module to WinnerMicro W60x BSP（AES/DES/3DES/RC/SHA1/MD3/CRC); +* Add oneshot WiFi configuration support in WinnerMicro W60x BSP; +* Add more STM32 BSP based on new STM32 BSP framework: + * stm32f072-st-nucleo + * stm32f103-gizwits-gokitv21 + * stm32f103-yf-ufun + * stm32f412-st-nucleo + * stm32f427-robomaster-a + * stm32f429-st-disco + * stm32f769-st-disco + * stm32g431-st-nucleo + * stm32h743-st-nucleo + * stm32h750-armfly-h7-tool + * stm32l4r5-st-nucleo + * stm32l452-st-nucleo +* For the new STM32 BSP framework: + * Add DMAMUX support to stm32l4+; + * Update F7 HAL library SConscript; + * Open the SWD port configuration on cubemx in stm32f103-atk-warshipv3 BSP; + * Add support for SD card in stm32f427-robomaster-a BSP; + * Add USBFS driver to stm32f412-nucleo BSP; + * Remove use of device user data on uart driver; + * Add QSPI FLASH support in stm32h743-atk-apollo BSP; + * Optimized Ethernet driver; + * Add hardware encryption and decryption driver; + * Add MIPI LCD driver; + * Add pulse encoding driver; + * Optimize hardware timer driver; + * Add support for UART 7/8 in serial driver; + * Optimize WDT driver; + +## Tools + +* Optimize scons script for eclipse in order to generate eclipse project better; +* Improve rtconfig.h generator, PATH type configuration can be generated correctly; +* Fix gcc path detection issue when using the default cross toolchain of the Linux distribution; + # RT-Thread v4.0.1 Change Log ## Kernel @@ -674,7 +826,7 @@ RT-Thread v2.0.1是2.0这个系列的bug修正版，而v2.1.0 alpha则是当前 * 修正USB host代码的编译错误； * 修正sensor框架回调函数的问题； * 修正pin设备注册时的设备名称问题； - + 而v2.1.0 alpha这个技术预览版则沿着最初设定的roadmap技术路线进行，这其中主要包括： * lwip更深度的集成：把它集成到RT-Thread的文件系统接口中，这样Linux/Unix下的一些socket网络应用能够更顺利的移植到RT-Thread上，也为以后可以应用到更多地方的select接口铺路。 @@ -687,7 +839,7 @@ RT-Thread v2.0.1是2.0这个系列的bug修正版，而v2.1.0 alpha则是当前 以下是自v2.0.0 RC版本以来的详细更改记录。后续我还会给出v2.0.0版本自v1.2.x版本的主要不同、看点，以及给出下一个版本的roadmap规划。 ## 内核 - + * console以RT_DEVICE_FLAG_STREAM参数打开字符设备； * 在rt_memheap_free中加入更多的断言检查； @@ -707,7 +859,7 @@ RT-Thread v2.0.1是2.0这个系列的bug修正版，而v2.1.0 alpha则是当前 * 添加VBUS组件用于Linux与RT-Thread系统之间，RT-Thread与RT-Thread系统之间通信（睿赛德服务公司捐赠）； * 增加lwIP/NAT组件，可以做多个网口间的地址转换（Hicard）； * 增加lwIP/DHCP服务端，用于向客户端分配IP地址（睿赛德服务公司提供）； - + ## BSP * 修正LPC4357串口驱动初始化时过早打开中断的问题（nongxiaoming）； @@ -738,487 +890,4 @@ RT-Thread做为一个开源组织参与的CSDN开源夏令营结出了丰硕的 由wzyy2参与的GDB stub实现，也完美的支持BeagleBoneBlack开发板和STM32F4平台； CSDN开源夏令营其他的成果，例如bluedroid移植也有了初步的成果，希望能够在后续的版本（可能会是2.1.0系列版本？）包含进来。CSDN开源夏令营是一次非常棒的活动，能够让学生提前进入实战，了解软件开发的初步知识。对开源社区来说，也是一次非常有益的社区互动活动。希望明年这个活动可以继续，关注RT-Thread、嵌入式开发的同学可以关注明年的动向。 -当前智能化设备是一个备受关注的领域，针对这一领域的特点，RT-Thread也相应的做出了积极的响应，所以这个版本开始加入sensor的应用框架（APP/算法 <--> sensor framework <--> RT-Thread device driver <--> 硬件外设）。希望在小型化的RT-Thread操作系统基础上融合智能化相关的技术，让RT-Thread成为这方面可选的OS系统之一。RT-Thread操作系统的sensor框架也尝试新的实现方式，即采用C++的方式来实现（当然也会考虑C方面的兼容，无疑C++的面向对象特性会更好，所以最终选择了C++），在这个基础上也可能融合其他的一些生态技术，例如ARM mbed平台上的一些社区组件技术。所以这个发布版本中既包括sensor框架，也包括了C++底层的一些基础支撑。 - -这个版本是RT-Thread 2.0.0系列正式版本的候选版本，正式版本预计会在年底正式发布，距离正式版本还会加入更完善的一些支撑（例如各种传感器驱动）。也计划2014年11月22日，在上海浦东举行RT-Thread嵌入式系统沙龙活动，欢迎大家关注并参与进行RT-Thread方方面面的技术交流。 - -以下是这个版本的更改记录: - -## 内核 - -* 修正当采用高级别优化编译时，idle任务中查询是否有僵尸线程的潜在bug； - -* 修正memory pool中的竞争问题； - -* 在console中打开设备时，加入流标志进行打开； - -## 组件 - -* 加入C++基础支撑组件。C++组件依赖于RT_USING_LIBC库，当使用GCC编译器时请注意查看其中的说明文档并更改ld script； -* 修正DFS中NFS打开目录的bug； -* 更改DFS ROMFS默认romfs_root为弱化符号； -* 添加DFS中dfs_file_lseek接口中关于fs的检查； -* 移除I2C core中无用的core lock锁； -* 添加sensor framework（采用C++的方式支持各种sensor）； -* 修正serial框架中DMA发送的bug（heyuanjie87）； -* 移除SPI框架中不必要的device初始化代码； -* 完善SPI Wi-Fi网卡RW009驱动并提供RSSI相关的命令； -* 修正MSH中未定义DFS_USING_WORKDIR时更改当前目录的bug； -* 修正MSH中未定义RT_LWIP_TCP时依然定义了netstat命令的bug； -* 修正MSH中未定义RT_USING_HEAP时依然定义了free命令的bug； -* 修正finsh中FINSH_USING_HISTORY相关的裁剪； -* 加入gdb stub组件，当前支持ARM Cortex-A8和Cortex-M3/4（wzyy2）； -* 统一不同编译器下使用LIBC的宏为RT_USING_LIBC，原有的宏定义RT_USING_NEWLIB/RT_USING_ARM_LIBC需要从rtconfig.h中移除，并替换成RT_USING_LIBC； -* 加入最新的lwIP分支：lwip-head，以提供IPv4/v6双栈的功能（hduffddybz）； -* YMode中打开串口设备时，添加open flag（armink）； - -## bsp - -* 加入北京京微雅格的M7（华山）低功耗FPGA的ARM Cortex-M3移植（aozima）； -* 加入北京京微雅格的M7 EMAC以太网驱动（aozima）； -* AT91SAM9260分支中更改RT_USING_NEWLIB为RT_USING_LIBC； -* BeagleBoneBlack分支中加入gdb stub支持（wzyy2）； -* LPC176x分支中加入C++支持； -* LPC176x分支中修正SD卡驱动返回卡信息的bug； -* 修正LPC408x分支中GCC编译时的问题； -* LPC408x分支中加入C++支持； -* 龙芯1B分支中加入UART3驱动； -* 加入飞索半导体的MB9BF568 FM4分支移植（yangfasheng）； -* mini2440分支中更改RT_USING_NEWLIB为 RT_USING_LIBC； -* stm32f0x分支中移除不同编译器下的LIBC定义，统一更改为RT_USING_LIBC； -* stm32f0x分支中加入串口接收溢出中断处理（armink）； -* stm32f40x分支中加入gdb stub支持并添加UART6驱动（wzzy2）； -* zynq7000分支中更改RT_USING_NEWLIB为RT_USING_LIBC； -* 加入ARM Cortex-M4芯片指令级的ffs实现； -* 修正MB0BF618S分支中缺少timer初始化的bug（mike mao）； - -## 工具 - -* 移除Python 2.6中未支持的语法（xfguo）； -* 移除Windows平台中的startupinfo信息（对Python版本兼容性更好）； -* 修正CPPPATH被打乱的bug； - -# RT-Thread 2.0.0 Beta更改说明 - -发布时间:2014/8/1 - -v2.0.0这个版本系列是RT-Thread当前的开发分支，如果要上新项目，建议使用这个版本来进行，预计这个版本的正式版会在年底发布。欢迎对这个版本进行测试、并反馈问题，能够早日进入到稳定版。 - -v2.0.0版本的开发相对活跃些，开源社区提供了强有力的支持：如Arda贡献的TM4C129x移植，Romeo贡献的frdm-k64f移植，xiaonong的LPC4300移植等，以及睿赛德服务公司捐赠的Zynq7000移植，MB9BF618S移植，以及SPI WiFi网卡的驱动代码等。 - -更改记录 - -## 内核 - -* 移除rt_device_init_all()函数：在系统启动时不需要再调用这个函数来初始化驱动，而是由上层应用执行rt_device_open时自动进行设备初始化； -* 修正设备对象引用计数在打开设备失败依然递增的问题； -* 增加WEAK宏用于定义/声明弱符号； -* 在执行静态内存块分配前，重置线程的errno； -* 修正timer未打开调试选项时，无用的静态函数定义（导致编译警告）； -* 启动timer前，对timer进行强制移除； -* 在执行soft timer超时函数时，打开调度器锁； -* 新增块设备的自动刷新参数，RT_DEVICE_CTRL_BLK_AUTOREFRESH； - -## 工具 - -* 修正scons命令编译时，选择keil mdk (armcc)编译器时，命令行太长编译失败的问题； - -## 移植 - -* 移除rt_device_init_all()相关的调用； -* 根据串口框架调整相关的驱动代码； -* 新增frdm-k64f移植（FreeScale K64芯片）； -* 移除K60Fxxxx移植； -* 新增LPC43xx移植（NXP LPC4357芯片）； -* 移除LPC176x中的组件初始化配置； -* 修正龙芯1B移植（ls1bdev）中链接脚本关于组件初始化部分的配置； -* 修正STM32F40x中UART3的配置； -* 修正STM32F40x中GNU GCC连接脚本中ROM/RAM大小的配置； -* 移除STM32F107中的组件初始化配置； -* 增强STM32F107 EMAC驱动性能，同时加入自动查找PHY芯片地址功能； -* 重写xplorer4330（NXP LPC4330芯片）移植（xiaonong完成）； -* 新增Zynq7000 ARM Dual Cortex-A9移植； -* 新增MB9BF618S移植； -* 新增tm4c129x移植，并加入相应的EMAC以太网驱动； - -## 组件 - -* DFS: 新增根据设备对象获得其上装载文件系统路径的函数：dfs_filesystem_get_mounted_path(struct rt_device* device); -* DFS: 修正readdir在GNU GCC下的编译警告； -* DeviceDrivers：新增workqueue实现； -* DeviceDrivers: 修正USB Device栈中的一些拼写错误； -* DeviceDrivers: 重写serial框架，能够让串口设备驱动同时支持三种模式：poll、interrupt、DMA。模式选择需要在执行rt_device_open时，由open flags指定； -* DeviceDrivers: 加入更多的SPI设备驱动，例如RW009的SPI WiFi网口驱动（2.4G 802.11 b/g/n，WEP/WPA/WPA2，SoftAP/Station），SPI NorFlash块设备驱动，ENC28J60以太网网卡驱动； -* Finsh: list_device()命令中增加refcount的信息； -* Finsh: 修正'0'零常量无法识别的错误； -* Finsh: mv命令，实现把一个文件移动到一个目录中； -* Finsh: ifconfig命令支持对一个网络接口的基本配置； -* Finsh: 新增netstat命令，用于显示当前系统中TCP连接的状态； -* Finsh: 修正当命令行太长导致的缓冲区移除的问题； -* libc: 修正arm libc中未使用DFS时的编译警告； -* libc: 修正newlib中使用DFS时的系统调用编译警告（GNU GCC下）； -* lwIP 1.4.1: 默认打开LWIP_SO_SNDTIMEO以支持连接发送超时； -* lwIP 1.4.1: 修正MEMP_NUM_TCP_SEG定义错误的问题； -* lwIP 1.4.1: 加入RT_LWIP_REASSEMBLY_FRAG选项定义以支持IP分组及合并； -* lwIP 1.4.1: ethnet网络接口支持定义LWIP_NO_TX_THREAD/LWIP_NO_RX_THREAD，以关闭etx/erx线程； -* lwIP 1.4.1: 用户可以重新定义RT_LWIP_ETH_MTU，以修改网络中的MTU值； -* lwIP 1.4.1: 修正LWIP_NETIF_LINK_CALLBACK条件编译的问题； -* lwIP 1.4.1: 完善移植相关的注释； -* log trace: 增加log_session_lvl接口； -* log trace: log trace中的session引用更改成常量形式； -* ymodem: 增强数据接收的稳定性； - -# RT-Thread 2.0.0 Alpha更改说明 - -发布时间:2014/4/8 - -RT-Thread 2.0.0分支的第一个技术预览版本，仅用于展示2.0.0发展分支的演化动向(按照roadmap，2.0.0这个分支会有一部分RT-Thread和Linux互补性的技术，为Linux增加更好的实时性，为RT-Thread增加更多的功能性，这份技术预览版正是朝着这个目标而努力)，欢迎反馈建议和问题。 - -## 组件 - -* msh： bugfix 和功能性增强。新的 msh 在调用外部模块方面更加方便。 -* DFS： nfs 的 bugfix 和内置命令的增强。ELM FatFS加入对扇区不匹配情况下的信息输出，这样能够及时定位问题。 -* JS：新添了轻量级Javascript引擎，可以在RT-Thread中直接运行javascript脚本。 -* VMM：可以在qemu中运行的 Virtual Machine Module 组件。暂时只支持 realview-pb-a8 的 bsp。 -* CMSIS：版本更新至 3.20 -* drivers：USB 协议栈的重构。新的框架中编写驱动变得更加容易了。 - -## BSP - -* beaglebone：串口驱动更新 -* realview-a8：添加了 VMM 组件 - -## 工具 - -* 固件加入scons --target=ua -s，用于准备用户应用环境； - -[发布后记] - -RT-Thread 2.0.0. Alpha版本相比于RT-Thread 1.2.1，新的特性主要有两部分： -- RT-Thread + Linux双系统，这部分以RealView-A8处理器(ARM Cortex-A8单核)为蓝本，给出一个简单的双系统并行运行的demo；在没有硬件的环境下，可以使用QEMU软件虚拟方式的执行。这个链接中包含一个编译好的Linux及RT-Thread二进制包，可以直接下载进行体验。 - -目录中有 Linux 的内核镜像 zImage，ramdisk rootfs.cpio.gz。可以用 -qemu-system-arm -M realview-pb-a8 -kernel zImage -initrd rootfs.cpio.gz -serial vc -serial vc -来启动。启动之后 Linux 的控制台在第一个串口上(Atl + Ctrl + 3)，可以直接无密码以 root 用户登录。登录之后加载内核模块： -insmod rtvmm.ko -来启动 RT-Thread。RT-Thread 启动之后控制台在第二个串口上(Atl + Ctrl + 4)。第一个串口Linux shell依然可以使用，第二个串口则是RT-Thread的shell。 -- JavaScript解析器，这个是由牛头哥移植的，可以在一个非常小资料的MCU上以JavaScript脚本方式进行编程、开发。根据这种方式，也提供了RN001JS的以太网硬件模块：以JavaScript脚本语言作为二次开发，提供在线web(即WebIDE)进行编程并运行JavaScript程序。JavaScript作为一门轻量级、解释型的语言，更容易上手，配合WebIDE、及提供的一些example可以使得开发变得非常的轻松，也包括一些传感器的JavaScript例子，让做网页的人也可以玩硬件了！ - -# RT-Thread 1.2.1更改说明 - -发布时间: 2014/4/8 - -在原有的1.2.0版本的bug修正版本，也是1.2.0系列的第一个修正版本，原则上不添加任何的新功能，我们尽量会按照每个季度一个修订版本的方式推进。大家在使用的过程中有什么问题还请反馈给我们，这些问题很可能会在下个版本中修正！ - -以下是更改记录： - -## 内核 - -* 用户应用，增加用户应用命令行参数支持； -* 在挂起一个任务时，把相应的定时器也关闭； - -## BSP - -* BeagleBone，加入更多串口驱动支持； -* 移除BSP中rt_device_init_all函数调用，改成打开设备时自动进行初始化； -* LPC176x，移除components初始化管理器； -* LPC4088，修正LED驱动的问题； -* STM32F107，移除components初始化管理器； - -## 组件 - -* 文件系统，ELM FatFS加入对扇区不匹配情况下的信息输出，这样能够及时定位问题； -* 文件系统，NFS网络文件系统修正相关的一些编译警告信息； -* 文件系统，copy命令加入文件夹方式复制功能； -* 文件系统，RAMFS，加入到components初始化管理器中； -* 文件系统，ROMFS，用于转换文件的工具mkromfs.py，增加Linux主机的支持； -* CMSIS更新到3.2.0版本； -* 串口驱动框架加入serial->ops->control的调用； -* 命令行系统，优化msh，支持用户应用的命令行参数； -* 命令行系统，当使用msh时，默认使用msh >的命令行提示符； -* TCP/IP协议栈，导出更多的lwIP接口给用户应用； -* POSIX thread，修正了同时使用lwIP组件时的编译警告； -* 第三方组件，加入TJPGD的移植，加入libpng的移植； - -## 工具 - -* 固件加入scons --target=ua -s，用于准备用户应用环境； - -[发布后记] -* RT-Thread携带了众多的BSP，不一定能够一一保证每个分支上把RT-Thread上相应的功能使用起来。所以针对这种情况，我们有一款评估用的硬件开发板：RealBoard 4088，在上面力求把一些相关例程都添加上，这样在一个基本的BSP基础上，可以对照着把其他的组件、功能添加进去； -* RealBoard 4088使用的RT-Thread版本主要以RT-Thread 1.2.1版本为主。 - -# RT-Thread 1.2.0正式版本更改说明 - -发布时间: 2014/1/6 - -实现roadmap中提到的大部分内容 - -1，文档方面已完成《RT-Thread编程手册》，同时还有论坛上jiezhi童鞋的《一起来学RT-Thread系列连载教程》 -2，BSP分支方面新增cortext-A8(beaglebone)，cortext-R4(rm48x50)，UNITY-2(SEP6200),lpc408x的移植 -3，组件方面： -- 加入msh(类似linux shell的风格)，能够直接执行应用程序 -- 新增freemodbus 1.6.0的移植 -- 新增开源的嵌入式关系数据库SQLite 3.8.1的移植 -- 新增Ymodem协议 -- 默认使用lwIP 1.4.1 - -下面是自RT-Thread 1.2.0 RC版本发布以来具体的变更履历： - -## 内核 - -* timer.c - 使用跳跃表(skip list)实现系统定时器链表，并在bsp中的startup.c中重新加入定时器初始化函数rt_system_timer_init() -* rtdebug.h - 新增宏定义RT_DEBUG_IN_THREAD_CONTEXT -* idle.c - 在函数rt_thread_idle_excute()中一次清除所有的死线程 -* scheduler.c - 新增API rt_critical_level()返回调度器上锁次数 - -## 移植 - -* cortex-m0 - 修正 cortex-m0 GCC移植中hardfault的问题点 -* cortex-r4 - 在startup后释放IRQ堆栈空间 -* cortex-r4 - 按字节长度分配堆栈空间 - -## BSP分支 - -* 新增lpc408x移植 -* bsp/stm32f0x - 增加USART1，USART2驱动，支持finsh，支持组件初始化 -* bsp/simulator - 当RTGUI配置无效时打印错误信息 -* bsp/simulator - 默认情况下关闭RTGUI选项 -* bsp/simulator - 增加createdef.py文件来生成VS的def文件 -* bsp/simulator - 当使用VC++编译时去除_TIME_T_DEFINED的定义 -* bsp/xplorer4330 - 重命名文件Retarget.c为retarget.c,否则linux系统中编译会报错 -* bsp/xplorer4330 - 修正GCC编译链接时关于ENTRY的警告 -* bsp/rm48x50 - 新增GCC的移植 -* bsp/K60Fxxxx - 修正一个编译错误 - -## 组件 - -* dfs - 正确处理mkfs未实现的情况 -* dfs - 使用指针代替index变量 -* dfs - 在函数dfs_filesystem_lookup()将含义模糊的指针变量名称empty重命名为fs -* dfs - 修正dfs_unmount问题点 -* dfs - 在设备打开错误时令挂载失败 -* dfs/elmfat - 令elmfatfs每次都检查扇区大小 -* net - 新增freemodbus 1.6.0的移植 -* finsh - 新增FINSH_USING_MSH_ONLY选项 -* finsh - 只有当shell设备为空时调用rt_console_get_device() -* finsh - 修正FINSH_USING_SYMTAB未定义的错误 -* finsh - 重构control按键的处理 -* msh - 增加文件和路径名称自动补全的功能 -* msh - msh内增加执行module的功能 -* msh - msh内增加更多的命令 -* libc - 修正 _sys_read()/_sys_write()问题点 -* external - 增加开源的嵌入式关系数据库SQLite 3.8.1的移植 -* pthreads - 避免ESHUTDOWN重复定义 -* mtd_nand - 在MTD nand中增加更多的调试措施 -* mtd_nand - 修正操作MTD nand时起始块错误的问题 -* lwip-1.4.1 - 在lwIP内加入更多的RT-Thread选项设置 -* log_trace - 修正函数memmove()参数使用错误的问题 -* drivers/pipe - 增加一个control命令来获得pipe剩余的空间 -* drivers/serial - 如果读写长度为0，则立即返回 - -## 例程 - -* examples - 用rt_sem_control()中的RT_IPC_CMD_RESET命令rt_sem_trytake()来清除信号量 -* examples - 始终打印输出测试结果 -* examples - 在所有的测试结束后打印输出简报 -* examples - 在TC线程中清除变量_tc_stat的TC_STAT_RUNNING状态 -* examples - 重新实现loop功能，并新增finsh命令tc_loop -* examples - 在tc_stop中增加延时，由原来的延时RT_TICK_PER_SECOND/2调整为10 * RT_TICK_PER_SECOND -* examples - 在SConscript中判断TC如果被使能，在CPPPATH中增加TC路径 -* examples - 新增一个in-mem-log的例子 -* semaphore_priority.c - 在cleanup时释放信号量 -* heap_realloc.c - 检查调用realloc(ptr, 0)是否成功 -* thread_delete.c - tc线程的延时应该比tid2的延时长，保证其测试过程中正常运行 -* thread_delay.c - 放宽超时判断条件，因为当RT_TICK_PER_SECOND为1000时，容易产生1个tick的误差 -* semaphore_static.c - 放宽超时判断条件，因为当RT_TICK_PER_SECOND为1000时，容易产生1个tick的误差 -* semaphore_dynamic.c - 放宽超时判断条件，因为当RT_TICK_PER_SECOND为1000时，容易产生1个tick的误差 - -其他： -* 更新README.md - -# RT-Thread 1.2.0RC更改说明 - -发布时间: 2013/10/10/ 10:19 - -主要说明: 该版本新增ARM Cortex-A8的支持(BeagleBone)，新增UNITY-2内核的支持(SEP6200)，新增Ymodem协议。 - -变更履历 -======== - -[内核] - -* 修正rtdef.h中的拼写错误(_MSC_VER_ -> _MSC_VER) -* 修正scheduler.c中的调试打印输出错误 -* ipc - 在函数rt_event_recv()中增加对参数option有效性的检查 -* device - 增加统计设备引用次数的变量ref_count -* memheap - 修正内存块分割问题点 -* memheap - 优化函数rt_memheap_realloc() -* kservice - 函数声明使用rt_vsnprintf代替vsnprintf - - -[组件] - -* dfs - 修正dfs_file.c中一处变量参数类型错误的问题 -* dfs - 增加mount table -* dfs - 在building脚本中加入ramfs的支持 -* dfs - 修正ramfs中O_APPEND write的问题 -* dfs/elm - 在mkfs中加入device_open/close -* dfs/jffs2 - 修正jffs2_opn/opendir中的f_flag初始化问题 -* dfs/jffs2 - 修正jffs2卸载问题 -* pthread - 修正一处编译警告 -* drivers/pipe - 增加rt_pipe_init/rt_pipe_detach -* drivers/pipe - 增加非阻塞读写和强制写模式 -* drivers/pipe - 当恢复读的时候调用函数rx_indicate() -* drivers/pipe - 增加一个设备类型(pipe类型) -* drivers/portal - 实现portal设备类型 -* drivers/ringbuffer - 修改一些模糊不清的函数名称 -* drivers/ringbuffer - 新增put_force和putchar_force接口函数 -* finsh - 当set_device时增加设备检查 -* finsh - 在rx_ind中增加对shell设备的自动设置 -* finsh - 增加pipe和portal设备的描述 -* finsh - 在变量定义时使用别名 -* finsh - 当关闭设备时注销rx_indicate -* finsh - 修正命令行太长的问题 -* finsh/msh - 只有当DFS_USING_WORKDIR使能时才声明cd/pwd -* init - 为新的组件初始化机制更新连接脚本 -* init - 增加组件初始化调试代码 -* logtrace - 整理代码，去除编译警告 -* logtrace - 增加LOG_TRACE_VERBOSE -* logtrace - 调整log values -* logtrace - 只有当finsh使能的时候才声明cmd -* libc/minilibc - 在sys/time.h中增加gettimeofday的声明 -* utilities - 新增ymodem - -工具: - -* building.py - 增加clang静态缝隙器的支持 -* building.py - 为Keil MDK增加buildlib功能 -* building.py - 在clang-analyze中执行'clang -Wall -fsyntas-only' -* clang-analyze.py - 增加一个定制工具实现clang静态分析 - -分支: - -* 新增BeagleBone的移植 -* 新增SEP6200的移植 -* 新增K60Fxxxx的移植 -* 修正Linux中的编译错误(lm4f232, stm32f40x, xplorer4330) -* cortex-m3 - 加强hard fault的异常处理函数 -* at91sam9260 - 更新串口驱动，使用组件中的通用串口驱动 -* at91sam9260 - 更新工程目录结构 -* at91sam9260 - 修正编译错误 -* at91sam9260 - 内嵌GPLv2许可 -* stm32f10x - 删除无用的文件 -* stm32f10x - 更新工程目录结构 -* stm32f10x - 更新工程文件 -* stm32f10x - 为使用新的组件初始化更新连接脚本 -* stm32f10x - 为使用新的组件初始化更新SD card驱动 -* stm32f10x - 为使用新的组件初始化更新DM9000驱动 -* stm32f10x - 更新串口驱动，使用组件中的通用串口驱动 -* stm32f10x - 修正rtgui初始化问题 -* simulator - 为使用新的组件初始化更新代码，以便支持mingw -* simulator - 支持Linux系统 -* simulator - 修正Linux系统中的SDL初始化问题 -* simulator - 在rt_components_init之后初始化SDL -* simulator - 将对SDL设置的内容移入drivers/SConstruct -* simulator - 在env中获得CORSS_TOOL和EXEC_PATH的值 -* simulator - 支持clang-analyze -* simulator - 增加tap netif driver - -//---------------------------------------------------------------------------------------- - -//---------------------------------------------------------------------------------------- - -//---------------------------------------------------------------------------------------- - - -版本: RT-Thread 1.2.0 Beta 版本 - -发布时间: 2013/6/30 - -进过开发人员三个月的努力，RT-Thread 1.2.0 Beta 版本如期发布。 -该版本默认采用lwIP 1.4.1协议栈，USB device stack也进一步完善。加入 log_trace 子系统，加入组件初始化升级版本，加入 ARM Cortex-R 的移植。 - -主要变化： - -* 1，新增组件初始化功能 -- 详情请看论坛帖子[新功能] 组件初始化 -* 2，支持ARM Cortex-R系列处理器 -- Grissiom 完成 ARM Cortex-R 的移植，目前BSP中已有TI RM48x50分支（仅支持TI CCS开发环境） -* 3，文件系统中新增 RAMFS -* 4，加入 log_trace 子系统 -* 5，优化Cortex-M4线程上下文切换，使用了浮点运算的线程才保存及恢复FPU寄存器 -- 详情请看论坛帖子[优化]cortex-m4f线程切换，优化FPU寄存器 -* 6，新增API rt_memheap_realloc() -* 7，重新实现ringbuffer，采用镜像的方法区分“满”和“空”，同时支持任意大小的buffer -* 8，内核中加入RT_KERNEL_MALLOC/RT_KERNEL_FREE/RT_KERNEL_REALLOC宏。 -如果用户未定义这些宏，将默认指向rt_malloc/rt_free/rt_realloc。 -同时内核仅局限于使用这些宏来使用动态内存 -* 9，在 building.py 中新增生成 cscope database 的选项 -* 10，USB组件新增reset函数，支持热插拔 -* 11，scons编译系统支持CCS开发环境 -* 12，USB组件新增状态信息（USB_STATE_NOTATTACHED，USB_STATE_ATTACHED，USB_STATE_POWERED...） - -修复问题点： - -* 1，USB组件HOST可以挂起endpoints -* 2，simulator分支，修复 serial_write 问题 -* 3，udisk可以被弹出 -* 4，iar.py中修复绝对路径的问题 -* 5，dfs_fs.h内增加dfs_mkfs()函数的申明 -* 6，生成MDK工程文件的时候加入library文件 -* 7，当PC不再接受数据的时候，重置VCOM相应的状态 -* 8，USB组件：返回正确的LangID字符串长度给HOST -* 9，Cortex-M0，Cortex-M3，Cortex-M4上下文切换时，回收系统初始化时用到的栈空间 - -//---------------------------------------------------------------------------------------- - -//---------------------------------------------------------------------------------------- - -//---------------------------------------------------------------------------------------- - - - -版本: RT-Thread 1.2.0 Alpha版本 - -发布时间: 2013/4/10 - -遵循2013年RT-Thread roadmap，RT-Thread 1.2.0 Alpha版本发布，Alpha意味着此版本为技术预览版，仅用于展示RT-Thread 1.2.0未来的发展方向，并不适合于开发正式产品。RT-Thread 1.2.0版本是1.1.x系列的下一个分支，这个分支主要体现的是RT-Thread 1.x系列的文档情况。当然也有一些功能、代码方面的增强。 - -伴随着新版本的到来，RT-Thread有几个重大的转变： -1，代码托管从google code(SVN)迁移到github(GIT) -2，RT-Thread与RTGUI区分开来，并成为两个独立的开发分支 -3，重视文档，将文档建设作为1.2.0版本的首要任务来抓 - -内核主要变化： -1，加入__rt_ffs函数用于实现32位整数中获取第一个置1的位；同时调度器中位图相关算法直接使用__rt_ffs函数；CPU移植时，可定义RT_USING_CPU_FFS，使用芯片指令完成。 - -2，新的中断注册机制 -weety加入interrupt description功能，用于为interrupt增加更多的信息，同时中断服务例程也可以携带用户自定义的参数类型。 -* 这部分对ARM7、ARM9、MIPS等影响很大，需要对CPU移植做相应的一些修改。 -* 这部分对ARM Cortex-M系列芯片没有影响。 - -3，调整定时器插入位置，为相同超时定时的后面。 - -组件主要变化： -1，添加lwIP 1.4.1。 -2，在finsh shell中加入module shell功能。finsh shell本身是一个C语言表达式的shell命令行，而module shell更类似于一个传统的命令行，由命令，参数等方式构成。 - -分支主要变化： -1，完善simulator分支，支持RTGUI，支持应用模块。 -2，完善at91sam9260分支的移植及驱动更新。 - -编译系统主要变化： -1，开启省略编译时长命令特性，如果需要查看编译时命令行，可以使用scons --verbose查看。 -2，加入生成CodeBlocks工程特性。 -3，修正当系统安装使用Keil MDK 4.6+版本的问题。 - -github主要提交履历: -5646189b29: elm fatfs支持mkfs，并且无需提前执行dfs_mount; mount/umount/mkfs操作也不会引起reset -22786f8817: 允许用户自定义PID和VID -0001344105: 更明确的定时器运行机制，如果两个定时器在同一个时刻发生超时，那么先开始的定时器先处理 -5d68ef8ec1: 修正使用64位GCC时编译finsh过程中发生错误的问题 -a4d661dcf1: 修正dfs_elm.c中一处内存泄露，并且在mount fatfs失败时执行 umount fatfs操作 -43228aeb9c: 修正list_tcps问题：ipaddr_ntoa不是可重入的函数。 -3de4b92a68: 修正AT91SAM9260分支中PHY link状态错误的问题。 -1abaa0492d +当前智能化设备是一个备受关注的领域，针对这一领域的特点，RT-Thread也相 diff --git a/bsp/cypress/psoc6-pioneerkit_modus/.cproject b/bsp/cypress/psoc6-pioneerkit_modus/.cproject new file mode 100644 index 0000000000000000000000000000000000000000..fbb8aa3a9c4159edf489e3cbd1cf8e02ac875598 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/.cproject @@ -0,0 +1,157 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Attach (JLink).launch b/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Attach (JLink).launch new file mode 100644 index 0000000000000000000000000000000000000000..5a9b77907e272e4654b48dc544791bd38c8b5794 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Attach (JLink).launch @@ -0,0 +1,78 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Attach (KitProg3).launch b/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Attach (KitProg3).launch new file mode 100644 index 0000000000000000000000000000000000000000..63fbcc50a156134d5c5e0456d565287db49f0bf0 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Attach (KitProg3).launch @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Debug (JLink).launch b/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Debug (JLink).launch new file mode 100644 index 0000000000000000000000000000000000000000..5280966cf9d08023ed22ae7c1810f4f44beaf352 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Debug (JLink).launch @@ -0,0 +1,80 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Debug (KitProg3).launch b/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Debug (KitProg3).launch new file mode 100644 index 0000000000000000000000000000000000000000..8ca00070b2c0cb055ecf477ebf59b2513900a91c --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Debug (KitProg3).launch @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Erase (JLink).launch b/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Erase (JLink).launch new file mode 100644 index 0000000000000000000000000000000000000000..86a77fd13617ef030b415f86a1b2a801653345bf --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Erase (JLink).launch @@ -0,0 +1,78 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Erase (KitProg3).launch b/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Erase (KitProg3).launch new file mode 100644 index 0000000000000000000000000000000000000000..712c9743809254c8032b07239f4fc95de6f53f8e --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Erase (KitProg3).launch @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Program (JLink).launch b/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Program (JLink).launch new file mode 100644 index 0000000000000000000000000000000000000000..7469c742e92c0d18900f542f61f9528a06a9bf84 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Program (JLink).launch @@ -0,0 +1,80 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Program (KitProg3).launch b/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Program (KitProg3).launch new file mode 100644 index 0000000000000000000000000000000000000000..0e5bbc11ec1d61bc2bc7b74ca54b6c670ae827a7 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/.mtbLaunchConfigs/psoc6-pioneerkit_modus Program (KitProg3).launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/.project b/bsp/cypress/psoc6-pioneerkit_modus/.project new file mode 100644 index 0000000000000000000000000000000000000000..e9e2cefe654d93982b5c01546a0ef3dc78294eea --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/.project @@ -0,0 +1,28 @@ + + + psoc6-pioneerkit_modus + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + com.cypress.studio.app.cymodusnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/.settings/language.settings.xml b/bsp/cypress/psoc6-pioneerkit_modus/.settings/language.settings.xml new file mode 100644 index 0000000000000000000000000000000000000000..6fdfc52492554d4e6aa638d5bca4c4bdfa38d0a9 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/.settings/language.settings.xml @@ -0,0 +1,27 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/LICENSE b/bsp/cypress/psoc6-pioneerkit_modus/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..91c81ad20b740069cd5e098f7cd2674d75a933ee --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/LICENSE @@ -0,0 +1,210 @@ +CYPRESS END USER LICENSE AGREEMENT + +PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE +DOWNLOADING, INSTALLING, COPYING, OR USING THIS SOFTWARE AND ACCOMPANYING +DOCUMENTATION. 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You agree that information you provide through your +registration on Cypress IoT Community Forum or other Cypress websites, +including contact information or other personal information, may be collected +and used by Cypress consistent with its Data Privacy Policy +(www.cypress.com/privacy-policy), as updated or revised from time to time, and +may be provided to its third party sales representatives, distributors and +other entities conducting sales activities for Cypress for sales-related and +other business purposes. + +12. General. This Agreement will bind and inure to the benefit of each +party's successors and assigns, provided that you may not assign or transfer +this Agreement, in whole or in part, without Cypress' written consent. This +Agreement shall be governed by and construed in accordance with the laws of +the State of California, United States of America, as if performed wholly +within the state and without giving effect to the principles of conflict of +law. The parties consent to personal and exclusive jurisdiction of and venue +in, the state and federal courts within Santa Clara County, California; +provided however, that nothing in this Agreement will limit Cypress' right to +bring legal action in any venue in order to protect or enforce its +intellectual property rights. No failure of either party to exercise or +enforce any of its rights under this Agreement will act as a waiver of such +rights. If any portion of this Agreement is found to be void or +unenforceable, the remaining provisions of this Agreement shall remain in full +force and effect. This Agreement is the complete and exclusive agreement +between the parties with respect to the subject matter hereof, superseding and +replacing any and all prior agreements, communications, and understandings +(both written and oral) regarding such subject matter. Any notice to Cypress +will be deemed effective when actually received and must be sent to Cypress +Semiconductor Corporation, ATTN: Chief Legal Officer, 198 Champion Court, San +Jose, CA 95134 USA. diff --git a/bsp/cypress/psoc6-pioneerkit_modus/Makefile b/bsp/cypress/psoc6-pioneerkit_modus/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..61a750c0c12a64278c16a437b082e476f2bf215e --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/Makefile @@ -0,0 +1,183 @@ +################################################################################ +# \file Makefile +# \version 1.0 +# +# \brief +# Top-level application make file. +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + + +################################################################################ +# Basic Configuration +################################################################################ + +# Target board/hardware +TARGET=CY8CKIT-062-BLE +# Name of application (used to derive name of final linked file). +APPNAME=mtb-example-psoc6-empty-app + +# Name of toolchain to use. Options include: +# +# GCC_ARM -- GCC 7.2.1, provided with ModusToolbox IDE +# ARM -- ARM Compiler (must be installed separately) +# IAR -- IAR Compiler (must be installed separately) +# +# See also: CY_COMPILER_PATH below +TOOLCHAIN=GCC_ARM + +# Default build configuration. Options include: +# +# Debug -- build with minimal optimizations, focus on debugging. +# Release -- build with full optimizations +CONFIG=Debug + +# If set to "true" or "1", display full command-lines when building. +VERBOSE= + +# RT-Thread root directory +RTT_ROOT_DIR=../../../ + +################################################################################ +# Advanced Configuration +################################################################################ + +# Enable optional code that is ordinarily disabled by default. +# +# Available components depend on the specific targeted hardware and firmware +# in use. In general, if you have +# +# COMPONENTS=foo bar +# +# ... then code in directories named COMPONENT_foo and COMPONENT_bar will be +# added to the build +# +COMPONENTS= + +# Like COMPONENTS, but disable optional code that was enabled by default. +DISABLE_COMPONENTS= + +# By default the build system automatically looks in the Makefile's directory +# tree for source code and builds it. The SOURCES variable can be used to +# manually add source code to the build process from a location not searched +# by default, or otherwise not found by the build system. +SOURCES=$(wildcard $(RTT_ROOT_DIR)/libcpu/arm/cortex-m4/*.c) \ + $(wildcard $(RTT_ROOT_DIR)/libcpu/arm/common/*.c) \ + $(wildcard $(RTT_ROOT_DIR)/src/*.c) \ + $(wildcard $(RTT_ROOT_DIR)/components/drivers/src/*.c) \ + $(wildcard $(RTT_ROOT_DIR)/components/drivers/serial/*.c) \ + $(wildcard $(RTT_ROOT_DIR)/components/finsh/*.c) +ifeq ($(TOOLCHAIN),GCC_ARM) + SOURCES+=$(RTT_ROOT_DIR)/libcpu/arm/cortex-m4/context_gcc.S +else ifeq ($(TOOLCHAIN),ARM) + SOURCES+=$(RTT_ROOT_DIR)/libcpu/arm/cortex-m4/context_rvds.S +else + SOURCES+=$(RTT_ROOT_DIR)/libcpu/arm/cortex-m4/context_iar.S +endif + +# Like SOURCES, but for include directories. Value should be paths to +# directories (without a leading -I). +INCLUDES=$(RTT_ROOT_DIR)/include/ \ + $(RTT_ROOT_DIR)/components/finsh/ \ + $(RTT_ROOT_DIR)/components/drivers/include/ + +# Add additional defines to the build process (without a leading -D). +DEFINES=HAVE_SIGVAL HAVE_SIGEVENT HAVE_SIGINFO RT_USING_NEWLIB + +# Select softfp or hardfp floating point. Default is softfp. +VFP_SELECT=hardfp + +# Additional / custom C compiler flags. +# +# NOTE: Includes and defines should use the INCLUDES and DEFINES variable +# above. +CFLAGS= + +# Additional / custom C++ compiler flags. +# +# NOTE: Includes and defines should use the INCLUDES and DEFINES variable +# above. +CXXFLAGS= + +# Additional / custom assembler flags. +# +# NOTE: Includes and defines should use the INCLUDES and DEFINES variable +# above. +ASFLAGS=-mfloat-abi=hard -mfpu=fpv4-sp-d16 -Wa,-mimplicit-it=always + +# Additional / custom linker flags. +LDFLAGS= + +# Additional / custom libraries to link in to the application. +LDLIBS= + +# Path to the linker script to use (if empty, use the default linker script). +LINKER_SCRIPT= + +# Custom pre-build commands to run. +PREBUILD= + +# Custom post-build commands to run. +POSTBUILD= + + +################################################################################ +# Paths +################################################################################ + +# Relative path to the project directory (default is the Makefile's directory). +# +# This controls where automatic source code discovery looks for code. +CY_APP_PATH= + +# Relative path to the "base" library. It provides the core makefile build +# infrastructure. +CY_BASELIB_PATH=libs/psoc6make + +# Absolute path to the compiler's "bin" directory. +# +# The default depends on the selected TOOLCHAIN (GCC_ARM uses the ModusToolbox +# IDE provided compiler by default). +CY_COMPILER_PATH= + + +# Locate ModusToolbox IDE helper tools folders in default installation +# locations for Windows, Linux, and macOS. +CY_WIN_HOME=$(subst \,/,$(USERPROFILE)) +CY_TOOLS_PATHS ?= $(wildcard \ + $(CY_WIN_HOME)/ModusToolbox/tools_* \ + $(HOME)/ModusToolbox/tools_* \ + /Applications/ModusToolbox/tools_*) + +# If you install ModusToolbox IDE in a custom location, add the path to its +# "tools_X.Y" folder (where X and Y are the version number of the tools +# folder). +CY_TOOLS_PATHS+= + +# Default to the newest installed tools folder, or the users override (if it's +# found). +CY_TOOLS_DIR=$(lastword $(sort $(wildcard $(CY_TOOLS_PATHS)))) + +ifeq ($(CY_TOOLS_DIR),) +$(error Unable to find any of the available CY_TOOLS_PATHS -- $(CY_TOOLS_PATHS)) +endif + +$(info Tools Directory: $(CY_TOOLS_DIR)) + +include $(CY_TOOLS_DIR)/make/start.mk diff --git a/bsp/cypress/psoc6-pioneerkit_modus/README.md b/bsp/cypress/psoc6-pioneerkit_modus/README.md new file mode 100644 index 0000000000000000000000000000000000000000..bf886a707349138962bf4247237ad9cbdbebbefc --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/README.md @@ -0,0 +1,98 @@ +# Cypress CY8CKIT-062-BLE PSoC 6 BLE Pioneer Kit 说明 + +## 简介 + +本文档为Cypress为PSoC6 BLE Pioneer Kit开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +CY8CKIT-062-BLE PSoC6 BLE Pioneer Kit 是赛普拉斯推出的一款32位双核CPU子系统（ ARM Cortex-M4 和 ARM Cortex-M0）的开发板，具有单周期乘法的150-MHz Arm Cortex-M4F CPU (浮点和 +存储器保护单元)，100-MHz Cortex M0+ CPU，带单周期乘法和MPU，可以充分发挥 PSoC6 双核芯片性能。 + +开发板外观详细信息：https://www.cypress.com/file/390496/download + + +该开发板常用 **板载资源** 如下： + +- MCU：CY8C6347BZI-BLD53，Cortex-M4主频 150MHz，Cortex-M0主频 100MHz，1 MB 应用闪存，32 KB EEPROM 区域和32 KB 安全闪存 ，288 KB 集成SRAM + MCU手册更多详细信息请参考文档 https://www.cypress.com/file/457541/download + +- 开发环境：ModusToolbox 2.0 + PSoC® Creator™ 下载链接 https://www.cypress.com/products/modustoolbox-software-environment + +- 开发板：CY8CKIT-062-BLE PSoC 6 BLE Pioneer Kit + 开发板更多详细信息请参考文档 https://www.cypress.com/file/390496/download + + +## 外设支持 + +本 BSP 目前对外设的支持情况详细信息请参考文档 https://www.cypress.com/file/390496/download + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用赛普拉斯开发板资源的开发者准备的。 + + +### 快速上手 + +本 BSP 以 ModusToolbox 2.0开发环境（GCC），介绍如何将系统运行起来。 + +#### 硬件连接 + +使用Type-C数据线连接开发板到 PC. + +#### 编译下载 +1, 安装ModusToolbox 2.0时请使用默认路径 + +2, 打开ModusToolbox 2.0时workspace选择工程所在目录下（例如workspace: C:\Git\rt-thread\bsp\cypress） + +3, 在Project Explorer的空白处右键，点击import，General->Existing Projects into Workspace ->next，点击Browse选择 + 此BSP所在目录加载工程->Finish + +4, 下载lib：在左下角Quick Panel的Tools栏，点击library Manager-> BSPs下面勾选CY8CKIT-062-BLE (若已勾选可以不用再选) + -> Libraries里PSoC6 Base Libraries下面全部勾选core-lib,psoc6cm0p,psoc6hal,psoc6make,psoc6pdl -> 点击apply 进行下载 + +5, 编译此工程 + +6, 下载此工程 + + +工程默认配置使用 SWD方式下载程序，Type-C数据线连接开发板，编译之后直接点击下载按钮即可。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行。打开终端工具串口小助手，复位设备后，可以看到 RT-Thread 的输出信息: + +注：推荐使用串口调试助手如：sscom + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Jan 6 2020 + 2006 - 2019 Copyright by rt-thread team +hello rt-thread +msh >hello rt-thread +hello rt-thread +``` + +## 联系人信息 + +维护人: + +- [amyqian379](https://github.com/amyqian379) \ No newline at end of file diff --git a/bsp/cypress/psoc6-pioneerkit_modus/applications/main.c b/bsp/cypress/psoc6-pioneerkit_modus/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..56fc49240b1c39c9d0dfb64ff8a3f1981614f9ef --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/applications/main.c @@ -0,0 +1,67 @@ +/****************************************************************************** +* File Name: main.c +* +* Description: This is the source code for the Empty PSoC6 Application +* for ModusToolbox. +* +* Related Document: See Readme.md +* +* +******************************************************************************* +* (c) 2019, Cypress Semiconductor Corporation. All rights reserved. +******************************************************************************* +* This software, including source code, documentation and related materials +* ("Software"), is owned by Cypress Semiconductor Corporation or one of its +* subsidiaries ("Cypress") and is protected by and subject to worldwide patent +* protection (United States and foreign), United States copyright laws and +* international treaty provisions. Therefore, you may use this Software only +* as provided in the license agreement accompanying the software package from +* which you obtained this Software ("EULA"). +* +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, +* non-transferable license to copy, modify, and compile the Software source +* code solely for use in connection with Cypress's integrated circuit products. +* Any reproduction, modification, translation, compilation, or representation +* of this Software except as specified above is prohibited without the express +* written permission of Cypress. +* +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress +* reserves the right to make changes to the Software without notice. Cypress +* does not assume any liability arising out of the application or use of the +* Software or any product or circuit described in the Software. Cypress does +* not authorize its products for use in any products where a malfunction or +* failure of the Cypress product may reasonably be expected to result in +* significant property damage, injury or death ("High Risk Product"). By +* including Cypress's product in a High Risk Product, the manufacturer of such +* system or application assumes all risk of such use and in doing so agrees to +* indemnify Cypress against all liability. +*******************************************************************************/ + +#include "cy_pdl.h" +#include "cycfg.h" +#include "cy_device_headers.h" +#include "cycfg_peripherals.h" +#include +#include "board.h" +#include "cybsp.h" + +#ifdef RT_USING_FINSH +#include +#include +#endif + +int main(void) +{ + + for(;;) + { + rt_kprintf("hello rt-thread\n"); + rt_thread_mdelay(1000); + + + } +} + +/* [] END OF FILE */ diff --git a/bsp/cypress/psoc6-pioneerkit_modus/drivers/board.c b/bsp/cypress/psoc6-pioneerkit_modus/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..00b6607a7fa4b325e6d4a75cada5616403d5e8a1 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/drivers/board.c @@ -0,0 +1,51 @@ + +#include +#include +#include +#include "cy_device_headers.h" +#include "board.h" +#include "uart.h" +#include "cy_systick.h" +#include "cycfg.h" + +#define configTOTAL_HEAP_SIZE (24*1024) +/* Allocate the memory for the heap. */ +ALIGN(RT_ALIGN_SIZE) +static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler_CB(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + + +void rt_hw_board_init() +{ + /* init systick */ + init_cycfg_all(); + + SystemCoreClockUpdate(); + + Cy_SysTick_Init(CY_SYSTICK_CLOCK_SOURCE_CLK_CPU, SystemCoreClock/RT_TICK_PER_SECOND); + Cy_SysTick_SetCallback(0, SysTick_Handler_CB); + Cy_SysTick_EnableInterrupt(); + + rt_system_heap_init((void*)ucHeap, (void*)(ucHeap+configTOTAL_HEAP_SIZE)); + /* initialize UART device */ + rt_hw_uart_init(); + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} + +/*@}*/ diff --git a/bsp/cypress/psoc6-pioneerkit_modus/drivers/board.h b/bsp/cypress/psoc6-pioneerkit_modus/drivers/board.h new file mode 100644 index 0000000000000000000000000000000000000000..54fb261397c6d500a042a2e0e5534153c4de2f9f --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/drivers/board.h @@ -0,0 +1,21 @@ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern unsigned int __end__; +extern unsigned int __HeapLimit; +#define HEAP_BEGIN (void*)&__end__ +#define HEAP_END (void*)&__HeapLimit +#endif + +void rt_hw_board_init(void); + +#endif + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/drivers/uart.c b/bsp/cypress/psoc6-pioneerkit_modus/drivers/uart.c new file mode 100644 index 0000000000000000000000000000000000000000..54ba921ed9ce361059d688f9d42a25ba6b54176c --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/drivers/uart.c @@ -0,0 +1,350 @@ +#include +#include "uart.h" +#include "cycfg_peripherals.h" +/** + * @addtogroup + */ +/*@{*/ + +/* RT-Thread Device Interface */ +/** + * This function initializes uart + */ +static rt_err_t rt_uart_init (rt_device_t dev) +{ + struct uart_device* uart = (struct uart_device*) dev->user_data; + + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } + + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + + return RT_EOK; +} + +/* save a char to uart buffer */ +static void rt_uart_savechar(struct uart_device* uart, char ch) +{ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); +} + +static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct uart_device* uart; + oflag = oflag; + + RT_ASSERT(dev != RT_NULL); + uart = (struct uart_device*) dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable interrupt */ + UART_ENABLE_IRQ(uart->rx_irq); + } + + return RT_EOK; +} + +static rt_err_t rt_uart_close(rt_device_t dev) +{ + struct uart_device* uart; + + RT_ASSERT(dev != RT_NULL); + uart = (struct uart_device*) dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable interrupt */ + UART_DISABLE_IRQ(uart->rx_irq); + } + + return RT_EOK; +} + +static rt_size_t rt_uart_read (rt_device_t dev, rt_off_t pos, void* buffer, + rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct uart_device* uart; + pos = pos; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct uart_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; + + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (0UL != Cy_SCB_UART_GetNumInRxFifo(uart->scb_device)) + { + *ptr = Cy_SCB_UART_Get(uart->scb_device); + ptr ++; + } + } + } + + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_size_t rt_uart_write (rt_device_t dev, rt_off_t pos, + const void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct uart_device* uart; + pos = pos; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct uart_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; + + -- size; + + /* move to next position */ + uart->int_tx->save_index ++; + + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } + + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while(0 == Cy_SCB_UART_Put(uart->scb_device, '\r')); + } + while(0 == Cy_SCB_UART_Put(uart->scb_device, (*ptr & 0x1FF))); + + ++ptr; + --size; + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_err_t rt_uart_control (rt_device_t dev, int cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + args = args; + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } + + return RT_EOK; +} + +/* + * serial register + */ +rt_err_t rt_hw_uart_register(rt_device_t device, const char* name, + rt_uint32_t flag, struct uart_device *serial) +{ + RT_ASSERT(device != RT_NULL); + + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_uart_init; + device->open = rt_uart_open; + device->close = rt_uart_close; + device->read = rt_uart_read; + device->write = rt_uart_write; + device->control = rt_uart_control; + device->user_data = serial; + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); +} + +/* ISR for uart interrupt */ +void rt_hw_uart_isr(rt_device_t device) +{ + struct uart_device* uart = (struct uart_device*) device->user_data; + + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* Check for "RX fifo not empty interrupt" */ + if((uart->scb_device->INTR_RX_MASKED & SCB_INTR_RX_MASKED_NOT_EMPTY_Msk ) != 0) + { + /* Clear UART "RX fifo not empty interrupt" */ + uart->scb_device->INTR_RX = uart->scb_device->INTR_RX & SCB_INTR_RX_NOT_EMPTY_Msk; + /* Get the character from terminal */ + rt_uart_savechar(uart, Cy_SCB_UART_Get(uart->scb_device)); + } + + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; + + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; + + device->rx_indicate(device, rx_length); + } +} + +#ifdef RT_USING_UART0 +/* UART0 device driver structure */ +#define UART0_SCB_IRQ__INTC_NUMBER 46u +cy_stc_scb_uart_context_t UART0_context; +const cy_stc_sysint_t UART0_SCB_IRQ_cfg = +{ + .intrSrc = scb_5_interrupt_IRQn, + .intrPriority = 3u, +}; + +/* UART0 device driver structure */ +struct uart_int_rx uart0_int_rx; +struct uart_device uart0 = +{ + UART0_HW, + &UART0_config, + &UART0_context, + &UART0_SCB_IRQ_cfg, + (IRQn_Type)UART0_SCB_IRQ__INTC_NUMBER, + (IRQn_Type)UART0_SCB_IRQ__INTC_NUMBER, + &uart0_int_rx, + RT_NULL +}; +struct rt_device uart0_device; +/* UART0 Interrupt Hanlder */ +void uart0_isr_callback(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_uart_isr(&uart0_device); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + + +void rt_hw_uart_init(void) +{ + /* Start UART operation. */ + if(Cy_SCB_UART_Init(uart0.scb_device, uart0.uart_config, uart0.uart_context) != CY_SCB_UART_SUCCESS) + { + rt_assert_handler("UART0 init", __FUNCTION__, __LINE__); + } + Cy_SCB_UART_Enable(uart0.scb_device); + /* Unmasking only the RX fifo not empty interrupt bit */ + uart0.scb_device->INTR_RX_MASK = SCB_INTR_RX_MASK_NOT_EMPTY_Msk; + /* Interrupt Settings for UART */ + Cy_SysInt_Init(uart0.uart_int, uart0_isr_callback); + /* Enable the interrupt */ + NVIC_EnableIRQ(uart0.uart_int->intrSrc); + /* register UART0 device */ + rt_hw_uart_register(&uart0_device, + "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart0); + +} + +/*@}*/ diff --git a/bsp/cypress/psoc6-pioneerkit_modus/drivers/uart.h b/bsp/cypress/psoc6-pioneerkit_modus/drivers/uart.h new file mode 100644 index 0000000000000000000000000000000000000000..9a2c6dd3bf3129734828d930db70d102470aaf9d --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/drivers/uart.h @@ -0,0 +1,50 @@ + +#ifndef __UART_H__ +#define __UART_H__ + +#include +#include +#include "cy_device_headers.h" +#include "board.h" +#include "cy_pdl.h" + +#define UART_RX_BUFFER_SIZE 128u +#define UART_TX_BUFFER_SIZE 128u + +#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) +#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) + +struct uart_int_rx +{ + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; + +struct uart_int_tx +{ + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; +}; + +struct uart_device +{ + CySCB_Type* scb_device; + /* uart config */ + cy_stc_scb_uart_config_t const *uart_config; + /* uart context */ + cy_stc_scb_uart_context_t *uart_context; + /* uart interrupt */ + const cy_stc_sysint_t *uart_int; + /* irq number */ + IRQn_Type rx_irq; + IRQn_Type tx_irq; + + /* rx structure */ + struct uart_int_rx* int_rx; + /* tx structure */ + struct uart_int_tx* int_tx; +}; + +void rt_hw_uart_init(void); + +#endif diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE.lib b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE.lib new file mode 100644 index 0000000000000000000000000000000000000000..e144e75a2aaf70f5c3595e42dfd3179527421285 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE.lib @@ -0,0 +1 @@ +https://github.com/cypresssemiconductorco/TARGET_CY8CKIT-062-BLE/#latest-v1.X diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list new file mode 100644 index 0000000000000000000000000000000000000000..28210ff4663fd3b7bd99275b46b019b84c7ddfc0 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -0,0 +1,4 @@ +[Device=CY8C6347BZI-BLD53] + +[Blocks] +# Nothing needs to be reserved for this device diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense new file mode 100644 index 0000000000000000000000000000000000000000..43d6108110ef1f589154c962d54deeef30fc7ac1 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense @@ -0,0 +1,409 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi new file mode 100644 index 0000000000000000000000000000000000000000..3c5fbe94fb8be83c8bd7a567161ece0a531a8f92 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -0,0 +1,63 @@ + + + + PSoC 6.xml + + + 0 + S25FL512S-4byteaddr + true + None + 0x18000000 + 0x4000000 + 0x1BFFFFFF + true + false + QUAD_SPI_DATA_0_3 + S25FL512S-4byteaddr + true + + + 1 + Not used + false + None + 0x18010000 + 0x10000 + 0x1801FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + true + + + 2 + Not used + false + None + 0x18020000 + 0x10000 + 0x1802FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + true + + + 3 + Not used + false + None + 0x18030000 + 0x10000 + 0x1803FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + true + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus new file mode 100644 index 0000000000000000000000000000000000000000..839d49276bd84d5a4b2d2f6e56e580d01d4444dd --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -0,0 +1,288 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/CY8CKIT-062-BLE.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/CY8CKIT-062-BLE.mk new file mode 100644 index 0000000000000000000000000000000000000000..520a7087fac102e2d99b7c2b1d4334daefdb82a7 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/CY8CKIT-062-BLE.mk @@ -0,0 +1,37 @@ +################################################################################ +# \file CY8CKIT-062-BLE.mk +# \version 1.0 +# +# \brief +# Define the CY8CKIT-062-BLE target. +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + +# MCU device selection +DEVICE:=CY8C6347BZI-BLD53 + +# Additional components supported by the target +COMPONENTS+=CM0P_SLEEP BSP_DESIGN_MODUS + +# Use CyHAL +DEFINES+=CY_USING_HAL diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/EULA b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/EULA new file mode 100644 index 0000000000000000000000000000000000000000..f10c742b1023a8993a0a287d3afc221f20330147 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/EULA @@ -0,0 +1,55 @@ +CYPRESS END USER LICENSE AGREEMENT + +PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE DOWNLOADING, INSTALLING, COPYING, OR USING THIS SOFTWARE AND ACCOMPANYING DOCUMENTATION. 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Any notice to Cypress will be deemed effective when actually received and must be sent to Cypress Semiconductor Corporation, ATTN: Chief Legal Officer, 198 Champion Court, San Jose, CA 95134 USA. diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/LICENSE b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..59cd3f8a320657c5748e85f7b247eb838f39acfb --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/LICENSE @@ -0,0 +1,165 @@ +Apache License +Version 2.0, January 2004 +http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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Limitation of Liability. + +In no event and under no legal theory, whether in tort (including negligence), +contract, or otherwise, unless required by applicable law (such as deliberate +and grossly negligent acts) or agreed to in writing, shall any Contributor be +liable to You for damages, including any direct, indirect, special, incidental, +or consequential damages of any character arising as a result of this License or +out of the use or inability to use the Work (including but not limited to +damages for loss of goodwill, work stoppage, computer failure or malfunction, or +any and all other commercial damages or losses), even if such Contributor has +been advised of the possibility of such damages. + +9. Accepting Warranty or Additional Liability. + +While redistributing the Work or Derivative Works thereof, You may choose to +offer, and charge a fee for, acceptance of support, warranty, indemnity, or +other liability obligations and/or rights consistent with this License. However, +in accepting such obligations, You may act only on Your own behalf and on Your +sole responsibility, not on behalf of any other Contributor, and only if You +agree to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your +accepting any such warranty or additional liability. diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/README.md b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/README.md new file mode 100644 index 0000000000000000000000000000000000000000..36884311c740786dbf89f3cc3450abfb836dd2a6 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/README.md @@ -0,0 +1,57 @@ +# CY8CKIT-062-BLE BSP + +## Overview + +The PSoC 6 BLE Pioneer Kit is a low-cost hardware platform that enables design and debug of the PSoC 63 Line (CY8C6347BZI-BLD53). +![](docs/html/board.png) + +To use code from the BSP, simply include a reference to `cybsp.h`. + +## Features + +### Kit Features: + +* BLE v5.0 +* Serial memory interface +* PDM-PCM digital microphone interface +* Industry-leading CapSense + +### Kit Contents: + +* CY8CKIT-062-BLE evaluation board +* E-Ink display shield with an ultra-low-power 2.7" E-ink display, thermistor, 6-axis motion sensor, and digital microphone +* USB cable + +## BSP Configuration + +### Clock Configuration + +| Clock | Source | Output Frequency | +|----------|-----------|------------------| +| CLK_HF0 | CLK_PATH0 | 100 MHz | +| CLK_HF1 | CLK_PATH1 | 48 MHz | +| CLK_HF2 | CLK_PATH0 | 50 MHz | +| CLK_HF3 | CLK_PATH1 | 48 MHz | + +### Power Configuration + +* System Active Power Mode: LP +* System Idle Power Mode: Deep Sleep +* VDDA Voltage: 3300 mV +* VDDD Voltage: 3300 mV + +## API Reference Manual + +The CY8CKIT-062-BLE Board Support Package provides a set of APIs to configure, initialize and use the board resources. + +See the [BSP API Reference Manual][api] for the complete list of the provided interfaces. + +## More information +* [CY8CKIT-062-BLE BSP API Reference Manual][api] +* [CY8CKIT-062-BLE Documentation](http://www.cypress.com/documentation/development-kitsboards/psoc-6-ble-pioneer-kit) +* [Cypress Semiconductor](http://www.cypress.com) + +[api]: https://cypresssemiconductorco.github.io/TARGET_CY8CKIT-062-BLE/html/modules.html + +--- +© Cypress Semiconductor Corporation, 2019. \ No newline at end of file diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/RELEASE.md b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/RELEASE.md new file mode 100644 index 0000000000000000000000000000000000000000..2f6d7a9551ae5064adfe97ab99be01404e7d553f --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/RELEASE.md @@ -0,0 +1,35 @@ +### CY8CKIT-062-BLE BSP +The PSoC 6 BLE Pioneer Kit is a low-cost hardware platform that enables design and debug of the PSoC 63 Line (CY8C6347BZI-BLD53). + +### What's New In This Release? +* Added pin references for the board's J2 Header + +### What's Included? +The CY8CKIT-062-BLE library includes the following: +* BSP specific makefile to configure the build process for the board +* cybsp.c/h files to initialize the board and any system peripherals +* cybsp_types.h file describing basic board setup +* Linker script & startup code for GCC, IAR, ARM toolchains +* Configurator design files (and generated code) to setup board specific peripherals +* .lib file references for all dependent libraries +* API documentation + +### Supported Software and Tools +This version of the CY8CKIT-062-BLE BSP was validated for compatibility with the following Software and Tools: + +| Software and Tools | Version | +| :--- | :----: | +| ModusToolbox Software Environment | 2.0 | +| GCC Compiler | 7.4 | +| IAR Compiler | 8.32 | +| ARM Compiler | 6.11 | + +### More information +* [CY8CKIT-062-BLE BSP API Reference Manual][api] +* [CY8CKIT-062-BLE Documentation](http://www.cypress.com/documentation/development-kitsboards/psoc-6-ble-pioneer-kit) +* [Cypress Semiconductor](http://www.cypress.com) + +[api]: modules.html + +--- +© Cypress Semiconductor Corporation, 2019. \ No newline at end of file diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/cybsp.c b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/cybsp.c new file mode 100644 index 0000000000000000000000000000000000000000..30540962ab07dea262868333b2b0d60d1701d57f --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/cybsp.c @@ -0,0 +1,124 @@ +/***************************************************************************//** +* \file cybsp.c +* +* Description: +* Provides initialization code for starting up the hardware contained on the +* Cypress board. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cybsp.h" +#if defined(CY_USING_HAL) +#include "cyhal_hwmgr.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/* The sysclk deep sleep callback is recommended to be the last callback that +* is executed before entry into deep sleep mode and the first one upon +* exit the deep sleep mode. +* Doing so minimizes the time spent on low power mode entry and exit. +*/ +#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER + #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) +#endif + +#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) +static cyhal_sdio_t sdio_obj; + +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) +{ + return &sdio_obj; +} +#endif + +/** + * Registers a power management callback that prepares the clock system + * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. + * NOTE: This is called automatically as part of \ref cybsp_init + */ +static cy_rslt_t cybsp_register_sysclk_pm_callback(void) +{ + cy_rslt_t result = CY_RSLT_SUCCESS; + static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; + static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { + .callback = &Cy_SysClk_DeepSleepCallback, + .type = CY_SYSPM_DEEPSLEEP, + .callbackParams = &cybsp_sysclk_pm_callback_param, + .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER + }; + + if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) + { + result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; + } + return result; +} + +cy_rslt_t cybsp_init(void) +{ + /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ +#if defined(CY_USING_HAL) + cy_rslt_t result = cyhal_hwmgr_init(); +#else + cy_rslt_t result = CY_RSLT_SUCCESS; +#endif + + init_cycfg_all(); + + if (CY_RSLT_SUCCESS == result) + { + result = cybsp_register_sysclk_pm_callback(); + } + +#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) + /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require + * specific peripheral instances. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. + */ + if (CY_RSLT_SUCCESS == result) + { + /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 + * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. + */ + result = cyhal_sdio_init( + &sdio_obj, + CYBSP_WIFI_SDIO_CMD, + CYBSP_WIFI_SDIO_CLK, + CYBSP_WIFI_SDIO_D0, + CYBSP_WIFI_SDIO_D1, + CYBSP_WIFI_SDIO_D2, + CYBSP_WIFI_SDIO_D3); + } +#endif /* defined(CYBSP_WIFI_CAPABLE) */ + + /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by + * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list + * (cyreservedresources.list) to make sure no resources are reserved by both. + */ + return result; +} + +#if defined(__cplusplus) +} +#endif diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/cybsp.h b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/cybsp.h new file mode 100644 index 0000000000000000000000000000000000000000..80ab3c2a1d804b8799323a228e70a022604c1805 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/cybsp.h @@ -0,0 +1,74 @@ +/***************************************************************************//** +* \file cybsp.h +* +* \brief +* Basic API for setting up boards containing a Cypress MCU. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#include "cy_result.h" +#include "cybsp_types.h" +#include "cycfg.h" +#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) +#include "cyhal_sdio.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_bsp_macros Macros +* \{ +*/ + +/** Failed to configure sysclk power management callback */ +#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) + +/** \} group_bsp_macros */ + +/** +* \addtogroup group_bsp_functions Functions +* \{ +*/ + +/** + * \brief Initialize all hardware on the board + * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is + * a problem initializing any hardware it returns an error code specific + * to the hardware module that had a problem. + */ +cy_rslt_t cybsp_init(void); + +#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) +/** + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \note This function should only be called after cybsp_init(); + * \returns The initialized sdio object. + */ +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); +#endif /* defined(CYBSP_WIFI_CAPABLE) */ + +/** \} group_bsp_functions */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/cybsp_types.h b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/cybsp_types.h new file mode 100644 index 0000000000000000000000000000000000000000..89f543b1812ba9dae7b430a4fe1711a62589b2c4 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/cybsp_types.h @@ -0,0 +1,279 @@ +/***************************************************************************//** +* \file CY8CKIT-062-BLE/cybsp_types.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CKIT-062-BLE pioneer kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#if defined(CY_USING_HAL) +#include "cyhal_pin_package.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_bsp_settings BSP Settings +* \{ +* +*
Peripheral Default HAL Settings:
+* | Resource | Parameter | Value | Remarks | +* | :------: | :-------: | :---: | :------ | +* | ADC | VREF | 1.2 V | | +* | ^ | Measurement type | Single Ended | | +* | ^ | Input voltage range | 0 to 2.4 V (0 to 2*VREF) | | +* | ^ | Output range | 0x000 to 0x7FF | | +* | DAC | Reference source | VDDA | | +* | ^ | Input range | 0x000 to 0xFFF | | +* | ^ | Output range | 0 to VDDA | | +* | ^ | Output type | Unbuffered output | | +* | I2C | Role | Master | Configurable to slave mode through HAL function | +* | ^ | Data rate | 100 kbps | Configurable through HAL function | +* | ^ | Drive mode of SCL & SDA pins | Open Drain (drives low) | External pull-up resistors are required | +* | LpTimer | Uses WCO (32.768 kHz) as clock source & MCWDT as counter. 1 count = 1/32768 second or 32768 counts = 1 second. ||| +* | SPI | Data rate | 100 kpbs | Configurable through HAL function | +* | ^ | Slave select polarity | Active low | | +* | UART | Flow control | No flow control | Configurable through HAL function | +* | ^ | Data format | 8N1 | Configurable through HAL function | +* | ^ | Baud rate | 115200 | Configurable through HAL function | +*/ +/** \} group_bsp_settings */ + +/** +* \addtogroup group_bsp_pin_state Pin States +* \{ +*/ + +/** Pin state for the LED on. */ +#define CYBSP_LED_STATE_ON (0U) +/** Pin state for the LED off. */ +#define CYBSP_LED_STATE_OFF (1U) + +/** Pin state for when a button is pressed. */ +#define CYBSP_BTN_PRESSED (0U) +/** Pin state for when a button is released. */ +#define CYBSP_BTN_OFF (1U) + +/** \} group_bsp_pin_state */ + +#if defined(CY_USING_HAL) + +/** +* \addtogroup group_bsp_pins Pin Mappings +* \{ +*/ + +/** +* \addtogroup group_bsp_pins_led LED Pins +* \{ +*/ + +/** LED 8; User LED1 */ +#define CYBSP_LED8 (P1_5) +/** LED 9; User LED2 */ +#define CYBSP_LED9 (P13_7) +/** LED 5: RGB LED - Red; User LED3 */ +#define CYBSP_LED_RGB_RED (P0_3) +/** LED 5: RGB LED - Green; User LED4 */ +#define CYBSP_LED_RGB_GREEN (P1_1) +/** LED 5: RGB LED - Blue; User LED5 */ +#define CYBSP_LED_RGB_BLUE (P11_1) + +/** LED 8; User LED1 */ +#define CYBSP_USER_LED1 (CYBSP_LED8) +/** LED 9; User LED2 */ +#define CYBSP_USER_LED2 (CYBSP_LED9) +/** LED 5: RGB LED - Red; User LED3 */ +#define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED) +/** LED 5: RGB LED - Green; User LED4 */ +#define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN) +/** LED 5: RGB LED - Blue; User LED5 */ +#define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE) +/** LED 8; User LED1 */ +#define CYBSP_USER_LED (CYBSP_USER_LED1) + +/** \} group_bsp_pins_led */ + +/** +* \addtogroup group_bsp_pins_btn Button Pins +* \{ +*/ + +/** Switch 2; User Button 1 */ +#define CYBSP_SW2 (P0_4) + +/** Switch 2; User Button 1 */ +#define CYBSP_USER_BTN1 (CYBSP_SW2) +/** Switch 2; User Button 1 */ +#define CYBSP_USER_BTN (CYBSP_USER_BTN1) + +/** \} group_bsp_pins_btn */ + + +/** +* \addtogroup group_bsp_pins_comm Communication Pins +* \{ +*/ + +/** Pin: UART RX */ +#define CYBSP_DEBUG_UART_RX (P5_0) +/** Pin: UART TX */ +#define CYBSP_DEBUG_UART_TX (P5_1) + +/** Pin: I2C SCL */ +#define CYBSP_I2C_SCL (P6_0) +/** Pin: I2C SDA */ +#define CYBSP_I2C_SDA (P6_1) + +/** Pin: SWO */ +#define CYBSP_SWO (P6_4) +/** Pin: SWDIO */ +#define CYBSP_SWDIO (P6_6) +/** Pin: SWDCK */ +#define CYBSP_SWDCK (P6_7) + +/** Pin: QUAD SPI SS */ +#define CYBSP_QSPI_SS (P11_2) +/** Pin: QUAD SPI D3 */ +#define CYBSP_QSPI_D3 (P11_3) +/** Pin: QUAD SPI D2 */ +#define CYBSP_QSPI_D2 (P11_4) +/** Pin: QUAD SPI D1 */ +#define CYBSP_QSPI_D1 (P11_5) +/** Pin: QUAD SPI D0 */ +#define CYBSP_QSPI_D0 (P11_6) +/** Pin: QUAD SPI SCK */ +#define CYBSP_QSPI_SCK (P11_7) + +/** \} group_bsp_pins_comm */ + + +/** +* \addtogroup group_bsp_pins_arduino Arduino Header Pins +* \{ +*/ + +/** Arduino A0 */ +#define CYBSP_A0 (P10_0) +/** Arduino A1 */ +#define CYBSP_A1 (P10_1) +/** Arduino A2 */ +#define CYBSP_A2 (P10_2) +/** Arduino A3 */ +#define CYBSP_A3 (P10_3) +/** Arduino A4 */ +#define CYBSP_A4 (P10_4) +/** Arduino A5 */ +#define CYBSP_A5 (P10_5) +/** Arduino D0 */ +#define CYBSP_D0 (P5_0) +/** Arduino D1 */ +#define CYBSP_D1 (P5_1) +/** Arduino D2 */ +#define CYBSP_D2 (P5_2) +/** Arduino D3 */ +#define CYBSP_D3 (P5_3) +/** Arduino D4 */ +#define CYBSP_D4 (P5_4) +/** Arduino D5 */ +#define CYBSP_D5 (P5_5) +/** Arduino D6 */ +#define CYBSP_D6 (P5_6) +/** Arduino D7 */ +#define CYBSP_D7 (P0_2) +/** Arduino D8 */ +#define CYBSP_D8 (P13_0) +/** Arduino D9 */ +#define CYBSP_D9 (P13_1) +/** Arduino D10 */ +#define CYBSP_D10 (P12_3) +/** Arduino D11 */ +#define CYBSP_D11 (P12_0) +/** Arduino D12 */ +#define CYBSP_D12 (P12_1) +/** Arduino D13 */ +#define CYBSP_D13 (P12_2) +/** Arduino D14 */ +#define CYBSP_D14 (P6_1) +/** Arduino D15 */ +#define CYBSP_D15 (P6_0) + +/** \} group_bsp_pins_arduino */ + + +/** +* \addtogroup group_bsp_pins_j2 J2 Header Pins +* \{ +*/ + +/** Cypress J2 Header pin 1 */ +#define CYBSP_J2_1 (CYBSP_A0) +/** Cypress J2 Header pin 2 */ +#define CYBSP_J2_2 (P9_0) +/** Cypress J2 Header pin 3 */ +#define CYBSP_J2_3 (CYBSP_A1) +/** Cypress J2 Header pin 4 */ +#define CYBSP_J2_4 (P9_1) +/** Cypress J2 Header pin 5 */ +#define CYBSP_J2_5 (CYBSP_A2) +/** Cypress J2 Header pin 6 */ +#define CYBSP_J2_6 (P9_2) +/** Cypress J2 Header pin 7 */ +#define CYBSP_J2_7 (CYBSP_A3) +/** Cypress J2 Header pin 8 */ +#define CYBSP_J2_8 (P9_3) +/** Cypress J2 Header pin 9 */ +#define CYBSP_J2_9 (CYBSP_A4) +/** Cypress J2 Header pin 10 */ +#define CYBSP_J2_10 (P9_4) +/** Cypress J2 Header pin 11 */ +#define CYBSP_J2_11 (CYBSP_A5) +/** Cypress J2 Header pin 12 */ +#define CYBSP_J2_12 (P9_5) +/** Cypress J2 Header pin 13 */ +#define CYBSP_J2_13 (P10_6) +/** Cypress J2 Header pin 14 */ +#define CYBSP_J2_14 (NC) +/** Cypress J2 Header pin 15 */ +#define CYBSP_J2_15 (P6_2) +/** Cypress J2 Header pin 16 */ +#define CYBSP_J2_16 (P9_6) +/** Cypress J2 Header pin 17 */ +#define CYBSP_J2_17 (P6_3) +/** Cypress J2 Header pin 18 */ +#define CYBSP_J2_18 (P9_7) +/** Cypress J2 Header pin 19 */ +#define CYBSP_J2_19 (P13_6) +/** Cypress J2 Header pin 20 */ +#define CYBSP_J2_20 (P13_7) + +/** \} group_bsp_pins_j2 */ + +/** \} group_bsp_pins */ + +#endif /* defined(CY_USING_HAL) */ + +#if defined(__cplusplus) +} +#endif diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct new file mode 100644 index 0000000000000000000000000000000000000000..5af1eb206720af5358ae0010495d52c7c927df7f --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -0,0 +1,274 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm4_dual.sct +;* \version 2.60 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08002000 +#define RAM_SIZE 0x00045800 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00100000 + +; Size of the stack section at the end of CM4 SRAM +#define STACK_SIZE 0x00001000 + +; Size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM FLASH_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE) +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE) + { + } + + ; Stack region growing down + ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk new file mode 100644 index 0000000000000000000000000000000000000000..212b141d2c3ef45ebc8d524e0550816d5f797e0b --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_A_Clang/cy8c6xx7_cm4_dual.mk @@ -0,0 +1,85 @@ +################################################################################ +# \file cy8c6xx7_cm4_dual.mk +# \version 2.60 +# +# \brief +# Specifies the starting address and the size of the segments in the output +# file. +# +# \note The section definitions in this file are generic and handle all common +# use cases. +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +### CM0P ### +export HEAP_SIZE_CM0P := 0x400 +export VECT_BASE_CM0P := 0x10000000 +export RAM_VECT_BASE_CM0P := 0x08000000 +export VECT_SIZE_CM0P := 0x000000C0 +export TEXT_BASE_CM0P := 0x100000C0 +export TEXT_SIZE_CM0P := 0x00002000 +export RAM_BASE_CM0P := 0x080000C0 +export RAM_SIZE_CM0P := 0x00002000 +export CYMETA_BASE_CM0P := 0x90500000 +export STACK_SIZE_CM0P := 0x2000 + +STACK_ADDRESS_TOP_CM0P := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM0P) + $(RAM_SIZE_CM0P)))) +STACK_ADDRESS_BOTTOM_CM0P := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM0P) - $(STACK_SIZE_CM0P)))) +TOOLCHAIN_VECT_BASE_CM0 := $(VECT_BASE_CM0P) + +SECTIONS_CM0P := \ + -segaddr __VECT $(VECT_BASE_CM0P) \ + -segaddr __TEXT $(TEXT_BASE_CM0P) \ + -segaddr __DATA $(RAM_BASE_CM0P) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM0P) \ + -segaddr __CYMETA $(CYMETA_BASE_CM0P) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM0P) + +### CM4 ### +export HEAP_SIZE_CM4 := 0x400 +export VECT_BASE_CM4 := 0x10002000 +export RAM_VECT_BASE_CM4 := 0x08002000 +export VECT_SIZE_CM4 := 0x0000028C +export TEXT_BASE_CM4 := 0x1000228C +export TEXT_SIZE_CM4 := 0x000FE000 +export RAM_BASE_CM4 := 0x0800228C +export RAM_SIZE_CM4 := 0x00045800 +export CYMETA_BASE_CM4 := 0x90500000 +export STACK_SIZE_CM4 := 0x2000 +STACK_ADDRESS_TOP_CM4 := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM4) + $(RAM_SIZE_CM4)))) +STACK_ADDRESS_BOTTOM_CM4 := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM4) - $(STACK_SIZE_CM4)))) +TOOLCHAIN_VECT_BASE_CM4 := $(VECT_BASE_CM4) + +SECTIONS_CM4 := \ + -segaddr __CY_M0P_IMAGE $(VECT_BASE_CM0P) \ + -segaddr __VECT $(VECT_BASE_CM4) \ + -segaddr __TEXT $(TEXT_BASE_CM4) \ + -segaddr __DATA $(RAM_BASE_CM4) \ + -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM4) \ + -segaddr __CYMETA $(CYMETA_BASE_CM4) \ + -segaddr __STACK $(STACK_ADDRESS_TOP_CM4) + +# Pass section addresses to the linker +ifeq ($(CORE),CM4) +LDFLAGS += $(SECTIONS_CM4) +else ifeq ($(CORE),CM0P) +LDFLAGS += $(SECTIONS_CM0P) +endif + +# EOF diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld new file mode 100644 index 0000000000000000000000000000000000000000..012a379e70269854ad46d8517e8dc3a82b59c647 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -0,0 +1,459 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.ld +* \version 2.60 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* Size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = 0x1000; + +/* Size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(flash) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > flash + + /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */ + ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE") + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) + FLASH_CM0P_SIZE : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + /* setction information for finsh shell begin */ + FSymTab : + { + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + } > flash + VSymTab : + { + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + } > flash + rti_fn : + { + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } > flash + /* setction information for finsh shell end */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf new file mode 100644 index 0000000000000000000000000000000000000000..e30133713a85ee0957db57ccaa674262a742e307 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -0,0 +1,240 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.icf +* \version 2.60 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; + +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +/* Size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM1_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place in IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/TOOLCHAIN_ARM/startup_psoc6_01_cm4.s b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/TOOLCHAIN_ARM/startup_psoc6_01_cm4.s new file mode 100644 index 0000000000000000000000000000000000000000..dd04a07d304493584d1520b059b67a4985b82471 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/TOOLCHAIN_ARM/startup_psoc6_01_cm4.s @@ -0,0 +1,645 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack + + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT pass_interrupt_ctbs_IRQHandler [WEAK] + EXPORT bless_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT udb_interrupts_0_IRQHandler [WEAK] + EXPORT udb_interrupts_1_IRQHandler [WEAK] + EXPORT udb_interrupts_2_IRQHandler [WEAK] + EXPORT udb_interrupts_3_IRQHandler [WEAK] + EXPORT udb_interrupts_4_IRQHandler [WEAK] + EXPORT udb_interrupts_5_IRQHandler [WEAK] + EXPORT udb_interrupts_6_IRQHandler [WEAK] + EXPORT udb_interrupts_7_IRQHandler [WEAK] + EXPORT udb_interrupts_8_IRQHandler [WEAK] + EXPORT udb_interrupts_9_IRQHandler [WEAK] + EXPORT udb_interrupts_10_IRQHandler [WEAK] + EXPORT udb_interrupts_11_IRQHandler [WEAK] + EXPORT udb_interrupts_12_IRQHandler [WEAK] + EXPORT udb_interrupts_13_IRQHandler [WEAK] + EXPORT udb_interrupts_14_IRQHandler [WEAK] + EXPORT udb_interrupts_15_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_interrupt_pdm_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT pass_interrupt_dacs_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +pass_interrupt_ctbs_IRQHandler +bless_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +udb_interrupts_0_IRQHandler +udb_interrupts_1_IRQHandler +udb_interrupts_2_IRQHandler +udb_interrupts_3_IRQHandler +udb_interrupts_4_IRQHandler +udb_interrupts_5_IRQHandler +udb_interrupts_6_IRQHandler +udb_interrupts_7_IRQHandler +udb_interrupts_8_IRQHandler +udb_interrupts_9_IRQHandler +udb_interrupts_10_IRQHandler +udb_interrupts_11_IRQHandler +udb_interrupts_12_IRQHandler +udb_interrupts_13_IRQHandler +udb_interrupts_14_IRQHandler +udb_interrupts_15_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_interrupt_i2s_IRQHandler +audioss_interrupt_pdm_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +pass_interrupt_dacs_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + IMPORT __use_two_region_memory + + END + + +; [] END OF FILE diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/TOOLCHAIN_A_Clang/startup_psoc6_01_cm4.S b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/TOOLCHAIN_A_Clang/startup_psoc6_01_cm4.S new file mode 100644 index 0000000000000000000000000000000000000000..e641b3cc42c1cd588686198a46eed314762f6947 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/TOOLCHAIN_A_Clang/startup_psoc6_01_cm4.S @@ -0,0 +1,554 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + .syntax unified + .section __STACK , __stack + .align 3 + +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit + __StackLimit: + .space Stack_Size + .equ __StackTop, . - Stack_Size + + .section __HEAP, __heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + + .section __VECT, ___Vectors + .align 2 + .globl ___Vectors +___Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler+1 /* Reset Handler. Added +1, clang doesn't make lsb to 1 for thumb */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + .equ __VectorsSize, . - ___Vectors + + .section __RAMVECTORS, ___ramVectors + .align 2 + .globl ___ramVectors +___ramVectors: + .space __VectorsSize + + + /* Only .text, otherwise the linker is smart enough to treat .thumb_func as 2 byte aligned and the + * Reset handler vector + 1 in the vector table ends up at +2 and boot fails. Clang/LLVM issue. + */ + .text + /* Reset handler */ + .globl Reset_Handler + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + .equ __copy_table_start__, ___Vectors + .equ __data_start__, ___ramVectors + .equ __data_end__, __data_start__ + __VectorsSize + ldr r1, =__copy_table_start__ + ldr r2, =__data_start__ + ldr r3, =__data_end__ +.L_loop_copy_table: + subs r4, r3, r2 + ble .L_loop_copy_table_done + ldr r0, [r1,r4] + str r0, [r2,r4] + subs r3, #4 + bgt .L_loop_copy_table +.L_loop_copy_table_done: + ldr r1, =segment$end$__TEXT + ldr r2, =section$start$__DATA$__data + ldr r3, =section$end$__DATA$__data + mov r4, #3 + adds r1, #3 + mvn r4, r4 + and r1, r4 +.L_loop_copy_data: + subs r4, r3, r2 + ble .L_loop_copy_data_done + ldr r0, [r1,r4] + str r0, [r2,r4] + subs r3, #4 + bgt .L_loop_copy_data +.L_loop_copy_data_done: + ldr r2, =section$start$__DATA$__bss + ldr r3, =section$end$__DATA$__bss +.L_loop_bss: + subs r1, r3, r2 + ble .L_loop_bss_done + movs r0, #0 + str r0, [r2,r1] + subs r3, #4 + bgt .L_loop_bss +.L_loop_bss_done: + ldr r2, =section$start$__DATA$__zerofill + ldr r3, =section$end$__DATA$__zerofill +.L_loop_zerofill: + subs r1, r3, r2 + ble .L_loop_zerofill_done + movs r0, #0 + str r0, [r2,r1] + subs r3, #4 + bgt .L_loop_zerofill +.L_loop_zerofill_done: + + /* Update Vector Table Offset Register. */ + ldr r0, =___ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl _Cy_SystemInitFpuEnable + + bl _HeapInit +#ifndef __NO_SYSTEM_INIT + bl _SystemInit +#endif + + bl _main + + /* Should never get here */ + b . + + .pool + + .text + .thumb + .thumb_func + .align 2 + + /* Device startup customization */ + .weak_definition Cy_OnResetUser + .global Cy_OnResetUser, Cy_OnResetUser +Cy_OnResetUser: + bx lr + + .text + .align 1 + .thumb_func + .weak_reference Default_Handler + +Default_Handler: + b . + + .text + .thumb_func + .align 2 + .weak_definition Cy_SysLib_FaultHandler + +Cy_SysLib_FaultHandler: + b . + + .text + .thumb_func + .align 2 + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + +.macro def_fault_Handler fault_handler_name + .weak_definition \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak_definition \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + .end + + +/* [] END OF FILE */ diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S new file mode 100644 index 0000000000000000000000000000000000000000..2220eb3a06290a655a97913b806ab5ebc4a71d08 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S @@ -0,0 +1,656 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* OS-specific low-level initialization */ + .weak cy_toolchain_init + .func cy_toolchain_init, cy_toolchain_init + .type cy_toolchain_init, %function + +cy_toolchain_init: + bx lr + .size cy_toolchain_init, . - cy_toolchain_init + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + /* OS-specific low-level initialization */ + bl cy_toolchain_init + + /* Call C/C++ static constructors */ + bl __libc_init_array + + /* Execute main application */ + /*bl main */ + bl entry + + /* Call C/C++ static destructors */ + bl __libc_fini_array + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + .end + + +/* [] END OF FILE */ diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/TOOLCHAIN_IAR/startup_psoc6_01_cm4.s b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/TOOLCHAIN_IAR/startup_psoc6_01_cm4.s new file mode 100644 index 0000000000000000000000000000000000000000..2ce41f1064f252eb4fe6ccd02076bfbbea6ff3b9 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/TOOLCHAIN_IAR/startup_psoc6_01_cm4.s @@ -0,0 +1,1150 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for OS-specific customization +;; + PUBWEAK cy_toolchain_init + SECTION .text:CODE:REORDER:NOROOT(2) +cy_toolchain_init + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; OS-specific low-level initialization + LDR R0, =cy_toolchain_init + BLX R0 + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_1_IRQHandler + B ioss_interrupts_gpio_1_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_4_IRQHandler + B ioss_interrupts_gpio_4_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_13_IRQHandler + B ioss_interrupts_gpio_13_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_8_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_8_interrupt_IRQHandler + B scb_8_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK pass_interrupt_ctbs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_ctbs_IRQHandler + B pass_interrupt_ctbs_IRQHandler + + PUBWEAK bless_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +bless_interrupt_IRQHandler + B bless_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK scb_7_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_7_interrupt_IRQHandler + B scb_7_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_4_IRQHandler + B tcpwm_0_interrupts_4_IRQHandler + + PUBWEAK tcpwm_0_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_5_IRQHandler + B tcpwm_0_interrupts_5_IRQHandler + + PUBWEAK tcpwm_0_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_6_IRQHandler + B tcpwm_0_interrupts_6_IRQHandler + + PUBWEAK tcpwm_0_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_7_IRQHandler + B tcpwm_0_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_8_IRQHandler + B tcpwm_1_interrupts_8_IRQHandler + + PUBWEAK tcpwm_1_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_9_IRQHandler + B tcpwm_1_interrupts_9_IRQHandler + + PUBWEAK tcpwm_1_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_10_IRQHandler + B tcpwm_1_interrupts_10_IRQHandler + + PUBWEAK tcpwm_1_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_11_IRQHandler + B tcpwm_1_interrupts_11_IRQHandler + + PUBWEAK tcpwm_1_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_12_IRQHandler + B tcpwm_1_interrupts_12_IRQHandler + + PUBWEAK tcpwm_1_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_13_IRQHandler + B tcpwm_1_interrupts_13_IRQHandler + + PUBWEAK tcpwm_1_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_14_IRQHandler + B tcpwm_1_interrupts_14_IRQHandler + + PUBWEAK tcpwm_1_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_15_IRQHandler + B tcpwm_1_interrupts_15_IRQHandler + + PUBWEAK tcpwm_1_interrupts_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_16_IRQHandler + B tcpwm_1_interrupts_16_IRQHandler + + PUBWEAK tcpwm_1_interrupts_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_17_IRQHandler + B tcpwm_1_interrupts_17_IRQHandler + + PUBWEAK tcpwm_1_interrupts_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_18_IRQHandler + B tcpwm_1_interrupts_18_IRQHandler + + PUBWEAK tcpwm_1_interrupts_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_19_IRQHandler + B tcpwm_1_interrupts_19_IRQHandler + + PUBWEAK tcpwm_1_interrupts_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_20_IRQHandler + B tcpwm_1_interrupts_20_IRQHandler + + PUBWEAK tcpwm_1_interrupts_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_21_IRQHandler + B tcpwm_1_interrupts_21_IRQHandler + + PUBWEAK tcpwm_1_interrupts_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_22_IRQHandler + B tcpwm_1_interrupts_22_IRQHandler + + PUBWEAK tcpwm_1_interrupts_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_23_IRQHandler + B tcpwm_1_interrupts_23_IRQHandler + + PUBWEAK udb_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_0_IRQHandler + B udb_interrupts_0_IRQHandler + + PUBWEAK udb_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_1_IRQHandler + B udb_interrupts_1_IRQHandler + + PUBWEAK udb_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_2_IRQHandler + B udb_interrupts_2_IRQHandler + + PUBWEAK udb_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_3_IRQHandler + B udb_interrupts_3_IRQHandler + + PUBWEAK udb_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_4_IRQHandler + B udb_interrupts_4_IRQHandler + + PUBWEAK udb_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_5_IRQHandler + B udb_interrupts_5_IRQHandler + + PUBWEAK udb_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_6_IRQHandler + B udb_interrupts_6_IRQHandler + + PUBWEAK udb_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_7_IRQHandler + B udb_interrupts_7_IRQHandler + + PUBWEAK udb_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_8_IRQHandler + B udb_interrupts_8_IRQHandler + + PUBWEAK udb_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_9_IRQHandler + B udb_interrupts_9_IRQHandler + + PUBWEAK udb_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_10_IRQHandler + B udb_interrupts_10_IRQHandler + + PUBWEAK udb_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_11_IRQHandler + B udb_interrupts_11_IRQHandler + + PUBWEAK udb_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_12_IRQHandler + B udb_interrupts_12_IRQHandler + + PUBWEAK udb_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_13_IRQHandler + B udb_interrupts_13_IRQHandler + + PUBWEAK udb_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_14_IRQHandler + B udb_interrupts_14_IRQHandler + + PUBWEAK udb_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_15_IRQHandler + B udb_interrupts_15_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK audioss_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_i2s_IRQHandler + B audioss_interrupt_i2s_IRQHandler + + PUBWEAK audioss_interrupt_pdm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_pdm_IRQHandler + B audioss_interrupt_pdm_IRQHandler + + PUBWEAK profile_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +profile_interrupt_IRQHandler + B profile_interrupt_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK pass_interrupt_dacs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_dacs_IRQHandler + B pass_interrupt_dacs_IRQHandler + + + END + + +; [] END OF FILE diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/system_psoc6.h b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/system_psoc6.h new file mode 100644 index 0000000000000000000000000000000000000000..f0276e37948c9e426a1cf487c009dd30bb39bde5 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/system_psoc6.h @@ -0,0 +1,684 @@ +/***************************************************************************//** +* \file system_psoc6.h +* \version 2.60 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + + +#ifndef _SYSTEM_PSOC6_H_ +#define _SYSTEM_PSOC6_H_ + +/** +* \addtogroup group_system_config +* \{ +* Provides device startup, system configuration, and linker script files. +* The system startup provides the followings features: +* - See \ref group_system_config_device_initialization for the: +* * \ref group_system_config_dual_core_device_initialization +* * \ref group_system_config_single_core_device_initialization +* - \ref group_system_config_device_memory_definition +* - \ref group_system_config_heap_stack_config +* - \ref group_system_config_merge_apps +* - \ref group_system_config_default_handlers +* - \ref group_system_config_device_vector_table +* - \ref group_system_config_cm4_functions +* +* \section group_system_config_configuration Configuration Considerations +* +* \subsection group_system_config_device_memory_definition Device Memory Definition +* The flash and RAM allocation for each CPU is defined by the linker scripts. +* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. +* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. +* For Single-Core devices the system reserves additional 80 bytes of RAM. +* Using the reserved memory area for other purposes will lead to unexpected behavior. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see warnings during the build process. To eliminate build +* warnings in your project, you can simply comment out or remove the relevant +* code in the linker file. +* +* ARM GCC\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* \endcode +* - 'xx_cm4_dual.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's +* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this +* by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* ARM MDK\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see the warnings during the build process: +* L6314W (no section matches pattern) and/or L6329W +* (pattern only matches removed unused sections). In your project, you can +* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +* the linker. You can also comment out or remove the relevant code in the linker +* file. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08000000 +* #define RAM_SIZE 0x00024000 +* \endcode +* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10080000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08024000 +* #define RAM_SIZE 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START +* value in the 'xx_cm4_dual.scat' file, +* where 'xx' is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* IAR\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* \endcode +* - 'xx_cm4_dual.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' +* is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* \subsection group_system_config_device_initialization Device Initialization +* After a power-on-reset (POR), the boot process is handled by the boot code +* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot +* code passes the control to the Cortex-M0+ startup code located in flash. +* +* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices +* The Cortex-M0+ startup code performs the device initialization by a call to +* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled +* by default. Enable the core using the \ref Cy_SysEnableCM4() function. +* See \ref group_system_config_cm4_functions for more details. +* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. +* The function has a separate implementation on each core. +* Both function implementations unlock and disable the WDT. +* Therefore enable the WDT after both cores have been initialized. +* +* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices +* The Cortex-M0+ core is not user-accessible on these devices. In this case the +* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. +* +* \subsection group_system_config_heap_stack_config Heap and Stack Configuration +* There are two ways to adjust heap and stack configurations: +* -# Editing source code files +* -# Specifying via command line +* +* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* +* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* Change the heap and stack sizes by modifying the following lines:\n +* \code .equ Stack_Size, 0x00001000 \endcode +* \code .equ Heap_Size, 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the compiler:\n +* \code -D __STACK_SIZE=0x000000400 \endcode +* \code -D __HEAP_SIZE=0x000000100 \endcode +* +* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the assembler:\n +* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode +* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* +* \subsubsection group_system_config_heap_stack_config_iar IAR +* - Editing source code files\n +* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the +* linker (including quotation marks):\n +* \code --define_symbol __STACK_SIZE=0x000000400 \endcode +* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode +* +* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables +* The CM0+ project and linker script build the CM0+ application image. Similarly, +* the CM4 linker script builds the CM4 application image. Each specifies +* locations, sizes, and contents of sections in memory. See +* \ref group_system_config_device_memory_definition for the symbols and default +* values. +* +* The cymcuelftool is invoked by a post-build command. The precise project +* setting is IDE-specific. +* +* The cymcuelftool combines the two executables. The tool examines the +* executables to ensure that memory regions either do not overlap, or contain +* identical bytes (shared). If there are no problems, it creates a new ELF file +* with the merged image, without changing any of the addresses or data. +* +* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition +* The default interrupt handler functions are defined as weak functions to a dummy +* handler in the startup file. The naming convention for the interrupt handler names +* is \_IRQHandler. A default interrupt handler can be overwritten in +* user code by defining the handler function using the same name. For example: +* \code +* void scb_0_interrupt_IRQHandler(void) +*{ +* ... +*} +* \endcode +* +* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM +* This process uses memory sections defined in the linker script. The startup +* code actually defines the contents of the vector table and performs the copy. +* \subsubsection group_system_config_device_vector_table_gcc ARM GCC +* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* It defines sections and locations in memory.\n +* Copy interrupt vectors from flash to RAM: \n +* From: \code LONG (__Vectors) \endcode +* To: \code LONG (__ram_vectors_start__) \endcode +* Size: \code LONG (__Vectors_End - __Vectors) \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* The code in these files copies the vector table from Flash to RAM. +* \subsubsection group_system_config_device_vector_table_mdk ARM MDK +* The linker script file is 'xx_yy.scat', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and +* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* (RESET_RAM) shall be first in the RAM section.\n +* RESET_RAM represents the vector table. It is defined in the assembler startup +* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_iar IAR +* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* This file defines the .intvec_ram section and its location. +* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \section group_system_config_more_information More Information +* Refer to the PDL User Guide for the +* more details. +* +* \section group_system_config_MISRA MISRA Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
+* +* \section group_system_config_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.60Updated linker scripts.Provided support for new devices, updated usage of CM0p prebuilt image.
2.50Updated assembler files, C files, linker scripts.Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.
2.40Updated assembler files, C files, linker scripts.Added Arm Compiler 6 support.
2.30Added assembler files, linker scripts for Mbed OS.Added Arm Mbed OS embedded operating system support.
Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.Enhanced PDL usability.
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n +* Removed $Sub$$main symbol for ARM MDK compiler. +* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n +* Added note about WDT disabling by SystemInit() function. +* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. +* Single core device support. +*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n +* Renamed 'wflash' memory region to 'em_eeprom'. +* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
+* +* +* \defgroup group_system_config_macro Macro +* \{ +* \defgroup group_system_config_system_macro System +* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status +* \defgroup group_system_config_user_settings_macro User Settings +* \} +* \defgroup group_system_config_functions Functions +* \{ +* \defgroup group_system_config_system_functions System +* \defgroup group_system_config_cm4_functions Cortex-M4 Control +* \} +* \defgroup group_system_config_globals Global Variables +* +* \} +*/ + +/** +* \addtogroup group_system_config_system_functions +* \{ +* \details +* The following system functions implement CMSIS Core functions. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* \} +*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Include files +*******************************************************************************/ +#include + + +/******************************************************************************* +* Global preprocessor symbols/macros ('define') +*******************************************************************************/ +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + #define CY_SYSTEM_CPU_CM0P 1UL +#else + #define CY_SYSTEM_CPU_CM0P 0UL +#endif + +#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) + #include "cyfitter.h" +#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ + + + + +/******************************************************************************* +* +* START OF USER SETTINGS HERE +* =========================== +* +* All lines with '<<<' can be set by user. +* +*******************************************************************************/ + +/** +* \addtogroup group_system_config_user_settings_macro +* \{ +*/ + +#if defined (CYDEV_CLK_EXTCLK__HZ) + #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) +#else + /***************************************************************************//** + * External Clock Frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_EXTCLK__HZ) */ + + +#if defined (CYDEV_CLK_ECO__HZ) + #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) +#else + /***************************************************************************//** + * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled + * within PSoC Creator and the clock is enabled in the DWR, the value from DWR + * used. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_ECO__HZ) */ + + +#if defined (CYDEV_CLK_ALTHF__HZ) + #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) +#else + /***************************************************************************//** + * \brief Alternate high frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ +#endif /* (CYDEV_CLK_ALTHF__HZ) */ + + +/***************************************************************************//** +* \brief Start address of the Cortex-M4 application ([address]UL) +* (USER SETTING) +*******************************************************************************/ +#if !defined (CY_CORTEX_M4_APPL_ADDR) + #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */ +#endif /* (CY_CORTEX_M4_APPL_ADDR) */ + + +/***************************************************************************//** +* \brief IPC Semaphores allocation ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ + + +/***************************************************************************//** +* \brief IPC Pipe definitions ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ + + +/******************************************************************************* +* +* END OF USER SETTINGS HERE +* ========================= +* +*******************************************************************************/ + +/** \} group_system_config_user_settings_macro */ + + +/** +* \addtogroup group_system_config_system_macro +* \{ +*/ + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M0+ startup driver identifier */ + #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + +#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M4 startup driver identifier */ + #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ + +/** \} group_system_config_system_macro */ + + +/** +* \addtogroup group_system_config_system_functions +* \{ +*/ +#if defined(__ARMCC_VERSION) + extern void SystemInit(void) __attribute__((constructor)); +#else + extern void SystemInit(void); +#endif /* (__ARMCC_VERSION) */ + +extern void SystemCoreClockUpdate(void); +/** \} group_system_config_system_functions */ + + +/** +* \addtogroup group_system_config_cm4_functions +* \{ +*/ +extern uint32_t Cy_SysGetCM4Status(void); +extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); +extern void Cy_SysDisableCM4(void); +extern void Cy_SysRetainCM4(void); +extern void Cy_SysResetCM4(void); +/** \} group_system_config_cm4_functions */ + + +/** \cond */ +extern void Default_Handler (void); + +void Cy_SysIpcPipeIsrCm0(void); +void Cy_SysIpcPipeIsrCm4(void); + +extern void Cy_SystemInit(void); +extern void Cy_SystemInitFpuEnable(void); + +extern uint32_t cy_delayFreqHz; +extern uint32_t cy_delayFreqKhz; +extern uint8_t cy_delayFreqMhz; +extern uint32_t cy_delay32kMs; +/** \endcond */ + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/** +* \addtogroup group_system_config_cm4_status_macro +* \{ +*/ +#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ +#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ +#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ +#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ +/** \} group_system_config_cm4_status_macro */ + +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + + +/******************************************************************************* +* IPC Configuration +* ========================= +*******************************************************************************/ +/* IPC CY_PIPE default configuration */ +#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) + +#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ + +#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) + + +/******************************************************************************/ +/* + * The System pipe configuration defines the IPC channel number, interrupt + * number, and the pipe interrupt mask for the endpoint. + * + * The format of the endPoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ + +/* System Pipe addresses */ +/* CyPipe defines */ + +#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) + +#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) + +/******************************************************************************/ + + +/** \addtogroup group_system_config_globals +* \{ +*/ + +extern uint32_t SystemCoreClock; +extern uint32_t cy_BleEcoClockFreqHz; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; + +/** \} group_system_config_globals */ + + + +/** \cond INTERNAL */ +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ + +/* BWC defines for functions related to enter/exit critical section */ +#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection +#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection +#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) +#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) + +/** \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_PSOC6_H_ */ + + +/* [] END OF FILE */ diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/system_psoc6_cm4.c b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/system_psoc6_cm4.c new file mode 100644 index 0000000000000000000000000000000000000000..0a18f50a4d4ccf0d9c684c493c929103c66c1be1 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/startup/system_psoc6_cm4.c @@ -0,0 +1,552 @@ +/***************************************************************************//** +* \file system_psoc6_cm4.c +* \version 2.60 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) + +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ (8000000UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ (32000UL) + +/** PILO frequency in Hz */ +#define CY_CLK_PILO_FREQ_HZ (32768UL) + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ (32768UL) + +/** ALTLF frequency in Hz */ +#define CY_CLK_ALTLF_FREQ_HZ (32768UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ +#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ + +/* SCB->CPACR */ +#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* \cond +* Initializes the system: +* - Restores FLL registers to the default state for single core devices. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* \endcond +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Allocate and initialize semaphores for the system operations. */ + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + #else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); + #endif /* (__CM0P_PRESENT) */ +#else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); +#endif /* __CM0P_PRESENT */ + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 + }; + + if (cy_device->flashPipeRequired != 0u) + { + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); + } + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t fastClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if ((rootPath == 1UL) || (rootPath == 2UL)) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Fast Clock Divider */ + fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + cy_PeriClkFreqHz = pathFreqHz / periClkDiv; + + pathFreqHz = pathFreqHz / fastClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitFpuEnable +****************************************************************************//** +* +* Enables the FPU if it is used. The function is called from the startup file. +* +*******************************************************************************/ +void Cy_SystemInitFpuEnable(void) +{ + #if defined (__FPU_USED) && (__FPU_USED == 1U) + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; + __DSB(); + __ISB(); + Cy_SysLib_ExitCriticalSection(interruptState); + #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ +} + + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm4 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm4(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); +} +#endif + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ + + +/* [] END OF FILE */ diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/EULA b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/EULA new file mode 100644 index 0000000000000000000000000000000000000000..f10c742b1023a8993a0a287d3afc221f20330147 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/EULA @@ -0,0 +1,55 @@ +CYPRESS END USER LICENSE AGREEMENT + +PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE DOWNLOADING, INSTALLING, COPYING, OR USING THIS SOFTWARE AND ACCOMPANYING DOCUMENTATION. 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TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THE SOFTWARE, INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to the Software without notice. Cypress does not assume any liability arising out of the application or use of Software or any product or circuit described in the Software. It is the responsibility of the user of the Software to properly design, program, and test the functionality and safety of any application made of the Software and any resulting product. Cypress does not authorize its Software or products for use in any products where a malfunction or failure of the Software or Cypress product may reasonably be expected to result in significant property damage, injury or death ("High Risk Product"). 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IN NO EVENT SHALL CYPRESS' OR ITS SUPPLIERS', RESELLERS', OR DISTRIBUTORS' TOTAL LIABILITY TO YOU, WHETHER IN CONTRACT, TORT (INCLUDING NEGLIGENCE), OR OTHERWISE, EXCEED THE GREATER OF US$500 OR THE PRICE PAID BY YOU FOR THE SOFTWARE. THE FOREGOING LIMITATIONS SHALL APPLY EVEN IF THE ABOVE-STATED WARRANTY FAILS OF ITS ESSENTIAL PURPOSE. BECAUSE SOME STATES OR JURISDICTIONS DO NOT ALLOW LIMITATION OR EXCLUSION OF CONSEQUENTIAL OR INCIDENTAL DAMAGES, ALL OR PORTIONS OF THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + +10. Restricted Rights. The Software is commercial computer software as that term is described in 48 C.F.R. 252.227-7014(a)(1). If the Software is being acquired by or on behalf of the U.S. Government or by a U.S. Government prime contractor or subcontractor (at any tier), then the Government's rights in Software shall be only those set forth in this Agreement. + +11. Personal Information. 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Any notice to Cypress will be deemed effective when actually received and must be sent to Cypress Semiconductor Corporation, ATTN: Chief Legal Officer, 198 Champion Court, San Jose, CA 95134 USA. diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/LICENSE b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..59cd3f8a320657c5748e85f7b247eb838f39acfb --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/LICENSE @@ -0,0 +1,165 @@ +Apache License +Version 2.0, January 2004 +http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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However, +in accepting such obligations, You may act only on Your own behalf and on Your +sole responsibility, not on behalf of any other Contributor, and only if You +agree to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your +accepting any such warranty or additional liability. diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/README.md b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/README.md new file mode 100644 index 0000000000000000000000000000000000000000..17eac80954e583fcad5a1f0312c29cdf8da016b4 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/README.md @@ -0,0 +1,22 @@ +# PSoC 6 GNU make Build System + +## Overview + +This repo provides the build recipe make files and scripts for building and programming PSoC 6 applications. Builds can be run either through a command-line interface (CLI) or through the ModusToolbox Integrated Devlopment Environment (IDE). + +## Prerequisite + +Builds require that the ModusToolbox tools be installed on your machine. This comes with the ModusToolbox IDE install. On Windows machines, it is recommended that CLI builds be executed using the Cygwin.bat located in ModusToolBox/tools_x.y/modus-shell install directory. This guarantees a consistent shell environment for your builds. + +## Options + +To list the build options, run the "help" target by typing "make help" in CLI. For a verbose documentation on a specific subject type "make help CY_HELP={variable/target}", where "variable" or "target" is one of the listed make variables or targets. + + +## More information +* [Cypress Semiconductor](http://www.cypress.com) +* [Cypress Semiconductor GitHub](https://github.com/cypresssemiconductorco) +* [ModusToolbox](https://www.cypress.com/products/modustoolbox-software-environment) + +--- +© Cypress Semiconductor Corporation, 2019. diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/RELEASE.md b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/RELEASE.md new file mode 100644 index 0000000000000000000000000000000000000000..7aefc341c5bdc14bbe5570561f35abaf6f934533 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/RELEASE.md @@ -0,0 +1,39 @@ +### PSoC 6 GNU make Build System 1.0 +This repo provides the build recipe make files and scripts for building and programming PSoC 6 applications. Builds can be run either through a command-line interface (CLI) or through the ModusToolbox Integrated Devlopment Environment (IDE). + +### What's Included? +The this release of the PSoC 6 GNU make Build System includes complete support for building, programming, and debugging PSoC 6 application projects. It is expected that a code example contains a top level make file for itself and references a Board Support Package (BSP) that defines specifics items, like the PSoC 6 part, for the target board. This includes the following: +* Supported operations: + * Build + * Program + * Debug +* Supported toolchains: + * GCC + * IAR + * ARMv6 + +This also includes the getlibs.bash script that can be used directly, or via the make target to download additional git repo based libraries for the application. + +### Product/Asset Specific Instructions +Builds require that the ModusToolbox tools be installed on your machine. This comes with the ModusToolbox IDE install. On Windows machines, it is recommended that CLI builds be executed using the Cygwin.bat located in ModusToolBox/tools_x.y/modus-shell install directory. This guarantees a consistent shell environment for your builds. + +To list the build options, run the "help" target by typing "make help" in CLI. For a verbose documentation on a specific subject type "make help CY_HELP={variable/target}", where "variable" or "target" is one of the listed make variables or targets. + +### Supported Software and Tools +This version of the Cypress PSoC 6 Hardware Abstraction Layer was validated for compatibility with the following Software and Tools: + +| Software and Tools | Version | +| :--- | :----: | +| ModusToolbox Software Environment | 2.0 | +| GCC Compiler | 7.4 | +| IAR Compiler | 8.32 | +| ARM Compiler | 6.11 | + +### More information +Use the following links for more information, as needed: +* [Cypress Semiconductor](http://www.cypress.com) +* [Cypress Semiconductor GitHub](https://github.com/cypresssemiconductorco) +* [ModusToolbox](https://www.cypress.com/products/modustoolbox-software-environment) + +--- +© Cypress Semiconductor Corporation, 2019. \ No newline at end of file diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/build.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/build.mk new file mode 100644 index 0000000000000000000000000000000000000000..72a867e5545167c0f88d2662939a050d71bb3863 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/build.mk @@ -0,0 +1,694 @@ +################################################################################ +# \file build.mk +# \version 1.0 +# +# \brief +# Performs the compilation and linking steps. +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + + +################################################################################ +# Target output +################################################################################ + +ifneq ($(LIBNAME),) +CY_BUILD_TARGET=$(CY_CONFIG_DIR)/$(LIBNAME).$(CY_TOOLCHAIN_SUFFIX_ARCHIVE) +else +CY_BUILD_TARGET=$(CY_CONFIG_DIR)/$(APPNAME).$(CY_TOOLCHAIN_SUFFIX_TARGET) +endif +CY_BUILD_MAPFILE=$(CY_CONFIG_DIR)/$(APPNAME).$(CY_TOOLCHAIN_SUFFIX_MAP) + + +################################################################################ +# VPATH resolution +################################################################################ + +# +# Search for relative path patterns in source list +# $(1) : Pattern +# $(2) : Sources +# +CY_MACRO_VPATH_FIND=$(foreach level,$(1),$(if $(filter $(level)%,$(2)),$(level))) + +# +# Search for relative paths in user sources and include them in the VPATH +# +CY_BUILD_VPATH_PATTERN=./ ./../ ./../../ ./../../../ ./../../../../ ./../../../../../ ./../../../../../../ ./../../../../../../../ \ + ../ ../../ ../../../ ../../../../ ../../../../../ ../../../../../../ ../../../../../../../ +VPATH+=$(call CY_MACRO_VPATH_FIND,$(CY_BUILD_VPATH_PATTERN),$(SOURCES)) + + +############################################################################## +# +# Macro to construct recursive make for dependent lib apps +# +# Arguments: +# 1: The name of the target +# 2: The lib app directory +# +define CY_MACRO_SHAREDLIB_DEPENDENCIES + +$(1)_SED_PATTERN=$(subst /,\/,$(subst .,\.,$(2))) +ifeq ($(CY_BUILD_LOC),$(CY_APP_LOCATION)/build) +$(1)_SHAREDLIB_BUILD_LOCATION?=$(2)/build/$(TARGET)/$(CONFIG) +else +$(1)_SHAREDLIB_BUILD_LOCATION?=$(CY_INTERNAL_BUILD_LOCATION)/$(1)/$(TARGET)/$(CONFIG) +endif + +# Satisfy dependencies +$$($(1)_SHAREDLIB_BUILD_LOCATION)/inclist.rsp: | shared_libs +$$($(1)_SHAREDLIB_BUILD_LOCATION)/liblist.rsp: | shared_libs +$$($(1)_SHAREDLIB_BUILD_LOCATION)/artifact.rsp: | shared_libs +$(1)_shared_lib: | $$($(1)_SHAREDLIB_BUILD_LOCATION)/inclist.rsp $$($(1)_SHAREDLIB_BUILD_LOCATION)/liblist.rsp $$($(1)_SHAREDLIB_BUILD_LOCATION)/artifact.rsp + +$(1)_shared_lib: + @inclist_read=$$$$(cat $$($(1)_SHAREDLIB_BUILD_LOCATION)/inclist.rsp | sed -e "s/I\.\//I$$($(1)_SED_PATTERN)\//g" | tr " " "\n"); \ + if [ -f "$$($(1)_SHAREDLIB_BUILD_LOCATION)/inclist_export.rsp" ]; then \ + inclist_export_read=$$$$(cat $$($(1)_SHAREDLIB_BUILD_LOCATION)/inclist_export.rsp | tr " " "\n"); \ + else \ + echo $$$$inclist_read > $$($(1)_SHAREDLIB_BUILD_LOCATION)/inclist_export.rsp ;\ + fi;\ + if [[ "$$$$inclist_read" != "$$$$inclist_export_read" ]]; then \ + echo $$$$inclist_read > $$($(1)_SHAREDLIB_BUILD_LOCATION)/inclist_export.rsp ;\ + fi; \ + liblist_read=$$$$(cat $$($(1)_SHAREDLIB_BUILD_LOCATION)/liblist.rsp | sed -e "s/\.\//$$($(1)_SED_PATTERN)\//g" | tr " " "\n"); \ + if [ -f "$$($(1)_SHAREDLIB_BUILD_LOCATION)/liblist_export.rsp" ]; then \ + liblist_export_read=$$$$(cat $$($(1)_SHAREDLIB_BUILD_LOCATION)/liblist_export.rsp | tr " " "\n"); \ + else \ + echo $$$$liblist_read > $$($(1)_SHAREDLIB_BUILD_LOCATION)/liblist_export.rsp ;\ + fi;\ + if [[ "$$$$liblist_read" != "$$$$liblist_export_read" ]]; then \ + echo $$$$liblist_read > $$($(1)_SHAREDLIB_BUILD_LOCATION)/liblist_export.rsp ;\ + fi; \ + artifact_read=$$$$(sed '1s;^;$$($(1)_SHAREDLIB_BUILD_LOCATION)/;' $$($(1)_SHAREDLIB_BUILD_LOCATION)/artifact.rsp); \ + if [ -f "$$($(1)_SHAREDLIB_BUILD_LOCATION)/artifact_export.rsp" ]; then \ + artifact_export_read=$$$$(cat $$($(1)_SHAREDLIB_BUILD_LOCATION)/artifact_export.rsp); \ + else \ + echo $$$$artifact_read > $$($(1)_SHAREDLIB_BUILD_LOCATION)/artifact_export.rsp;\ + fi;\ + if [[ "$$$$artifact_read" -nt "$(CY_BUILD_TARGET)" ]] || [[ "$$$$artifact_read" != "$$$$artifact_export_read" ]]; then\ + echo $$$$artifact_read > $$($(1)_SHAREDLIB_BUILD_LOCATION)/artifact_export.rsp;\ + fi; + +# Satisfy dependencies +$$($(1)_SHAREDLIB_BUILD_LOCATION)/inclist_export.rsp: | $(1)_shared_lib +$$($(1)_SHAREDLIB_BUILD_LOCATION)/liblist_export.rsp: | $(1)_shared_lib +$$($(1)_SHAREDLIB_BUILD_LOCATION)/artifact_export.rsp: | $(1)_shared_lib + +endef + + +################################################################################ +# Shared libraries +################################################################################ + +ifneq ($(SEARCH_LIBS_AND_INCLUDES),) + +# Construct targets for all dependent lib apps +$(foreach lib,$(SEARCH_LIBS_AND_INCLUDES),$(eval $(call CY_MACRO_SHAREDLIB_DEPENDENCIES,$(notdir $(lib)),$(lib)))) + +CY_SHAREDLIB_LIST=$(foreach lib,$(SEARCH_LIBS_AND_INCLUDES),$(notdir $(lib)_shared_lib)) +CY_SHAREDLIB_ARTIFACT_LIST=$(foreach lib,$(SEARCH_LIBS_AND_INCLUDES),$($(notdir $(lib))_SHAREDLIB_BUILD_LOCATION)/artifact.rsp) + +CY_SHAREDLIB_INCLUDES_EXPORT_LIST=$(foreach lib,$(SEARCH_LIBS_AND_INCLUDES),$($(notdir $(lib))_SHAREDLIB_BUILD_LOCATION)/inclist_export.rsp) +CY_SHAREDLIB_LIBS_EXPORT_LIST=$(foreach lib,$(SEARCH_LIBS_AND_INCLUDES),$($(notdir $(lib))_SHAREDLIB_BUILD_LOCATION)/liblist_export.rsp) +CY_SHAREDLIB_ARTIFACT_EXPORT_LIST=$(foreach lib,$(SEARCH_LIBS_AND_INCLUDES),$($(notdir $(lib))_SHAREDLIB_BUILD_LOCATION)/artifact_export.rsp) + +CY_BUILD_SHAREDLIB_INCLIST=$(foreach inc,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST),$(addprefix $(CY_TOOLCHAIN_INCRSPFILE),$(inc))) +CY_BUILD_SHAREDLIB_LIBLIST=$(foreach lib,$(CY_SHAREDLIB_LIBS_EXPORT_LIST),$(addprefix $(CY_TOOLCHAIN_OBJRSPFILE),$(lib)))\ + $(foreach artifact,$(CY_SHAREDLIB_ARTIFACT_EXPORT_LIST),$(addprefix $(CY_TOOLCHAIN_OBJRSPFILE),$(artifact))) + +# Sentinel file to always trigger link step +CY_SHAREDLIB_TIMESTAMP=$(CY_CONFIG_DIR)/shared_libs.timestamp +$(shell touch $(CY_SHAREDLIB_TIMESTAMP)) + +endif + + +################################################################################ +# Build arguments +################################################################################ + +# +# The list of C and S source files that come from the application and generated source +# +CY_BUILD_SRC_S_FILES=$(patsubst $(CY_INTERNAL_APP_PATH)/%,/%,$(patsubst $(CY_INTERNAL_EXTAPP_PATH)/%,/%,\ + $(filter %.$(CY_TOOLCHAIN_SUFFIX_S),$(CY_RECIPE_SOURCE)))) +CY_BUILD_SRC_s_FILES=$(patsubst $(CY_INTERNAL_APP_PATH)/%,/%,$(patsubst $(CY_INTERNAL_EXTAPP_PATH)/%,/%,\ + $(filter %.$(CY_TOOLCHAIN_SUFFIX_s),$(CY_RECIPE_SOURCE)))) +CY_BUILD_SRC_C_FILES=$(patsubst $(CY_INTERNAL_APP_PATH)/%,/%,$(patsubst $(CY_INTERNAL_EXTAPP_PATH)/%,/%,\ + $(filter %.$(CY_TOOLCHAIN_SUFFIX_C),$(CY_RECIPE_SOURCE)))) +CY_BUILD_SRC_CPP_FILES=$(patsubst $(CY_INTERNAL_APP_PATH)/%,/%,$(patsubst $(CY_INTERNAL_EXTAPP_PATH)/%,/%,\ + $(filter %.$(CY_TOOLCHAIN_SUFFIX_CPP),$(CY_RECIPE_SOURCE)))) +CY_BUILD_GENSRC_S_FILES=$(filter %.$(CY_TOOLCHAIN_SUFFIX_S),$(CY_RECIPE_GENERATED)) +CY_BUILD_GENSRC_s_FILES=$(filter %.$(CY_TOOLCHAIN_SUFFIX_s),$(CY_RECIPE_GENERATED)) +CY_BUILD_GENSRC_C_FILES=$(filter %.$(CY_TOOLCHAIN_SUFFIX_C),$(CY_RECIPE_GENERATED)) +CY_BUILD_GENSRC_CPP_FILES=$(filter %.$(CY_TOOLCHAIN_SUFFIX_CPP),$(CY_RECIPE_GENERATED)) +CY_BUILD_EXTSRC_S_FILES=$(patsubst $(CY_INTERNAL_APP_PATH)/%,/%,$(subst ../,,$(filter %.$(CY_TOOLCHAIN_SUFFIX_S),$(SOURCES)))) +CY_BUILD_EXTSRC_s_FILES=$(patsubst $(CY_INTERNAL_APP_PATH)/%,/%,$(subst ../,,$(filter %.$(CY_TOOLCHAIN_SUFFIX_s),$(SOURCES)))) +CY_BUILD_EXTSRC_C_FILES=$(patsubst $(CY_INTERNAL_APP_PATH)/%,/%,$(subst ../,,$(filter %.$(CY_TOOLCHAIN_SUFFIX_C),$(SOURCES)))) +CY_BUILD_EXTSRC_CPP_FILES=$(patsubst $(CY_INTERNAL_APP_PATH)/%,/%,$(subst ../,,$(filter %.$(CY_TOOLCHAIN_SUFFIX_CPP),$(SOURCES)))) + +# +# The list of object files +# +CY_BUILD_SRC_S_OBJ_FILES=$(addprefix $(CY_CONFIG_DIR)/,$(CY_BUILD_SRC_S_FILES:%.$(CY_TOOLCHAIN_SUFFIX_S)=%.$(CY_TOOLCHAIN_SUFFIX_O))) +CY_BUILD_SRC_s_OBJ_FILES=$(addprefix $(CY_CONFIG_DIR)/,$(CY_BUILD_SRC_s_FILES:%.$(CY_TOOLCHAIN_SUFFIX_s)=%.$(CY_TOOLCHAIN_SUFFIX_O))) +CY_BUILD_SRC_C_OBJ_FILES=$(addprefix $(CY_CONFIG_DIR)/,$(CY_BUILD_SRC_C_FILES:%.$(CY_TOOLCHAIN_SUFFIX_C)=%.$(CY_TOOLCHAIN_SUFFIX_O))) +CY_BUILD_SRC_CPP_OBJ_FILES=$(addprefix $(CY_CONFIG_DIR)/,$(CY_BUILD_SRC_CPP_FILES:%.$(CY_TOOLCHAIN_SUFFIX_CPP)=%.$(CY_TOOLCHAIN_SUFFIX_O))) +CY_BUILD_GENSRC_S_OBJ_FILES=$(patsubst $(CY_BUILDTARGET_DIR)/%,$(CY_CONFIG_DIR)/%,$(CY_BUILD_GENSRC_S_FILES:%.$(CY_TOOLCHAIN_SUFFIX_S)=%.$(CY_TOOLCHAIN_SUFFIX_O))) +CY_BUILD_GENSRC_s_OBJ_FILES=$(patsubst $(CY_BUILDTARGET_DIR)/%,$(CY_CONFIG_DIR)/%,$(CY_BUILD_GENSRC_s_FILES:%.$(CY_TOOLCHAIN_SUFFIX_s)=%.$(CY_TOOLCHAIN_SUFFIX_O))) +CY_BUILD_GENSRC_C_OBJ_FILES=$(patsubst $(CY_BUILDTARGET_DIR)/%,$(CY_CONFIG_DIR)/%,$(CY_BUILD_GENSRC_C_FILES:%.$(CY_TOOLCHAIN_SUFFIX_C)=%.$(CY_TOOLCHAIN_SUFFIX_O))) +CY_BUILD_GENSRC_CPP_OBJ_FILES=$(patsubst $(CY_BUILDTARGET_DIR)/%,$(CY_CONFIG_DIR)/%,$(CY_BUILD_GENSRC_CPP_FILES:%.$(CY_TOOLCHAIN_SUFFIX_CPP)=%.$(CY_TOOLCHAIN_SUFFIX_O))) +CY_BUILD_EXTSRC_S_OBJ_FILES=$(addprefix $(CY_CONFIG_DIR)/user/,$(CY_BUILD_EXTSRC_S_FILES:%.$(CY_TOOLCHAIN_SUFFIX_S)=%.$(CY_TOOLCHAIN_SUFFIX_O))) +CY_BUILD_EXTSRC_s_OBJ_FILES=$(addprefix $(CY_CONFIG_DIR)/user/,$(CY_BUILD_EXTSRC_s_FILES:%.$(CY_TOOLCHAIN_SUFFIX_s)=%.$(CY_TOOLCHAIN_SUFFIX_O))) +CY_BUILD_EXTSRC_C_OBJ_FILES=$(addprefix $(CY_CONFIG_DIR)/user/,$(CY_BUILD_EXTSRC_C_FILES:%.$(CY_TOOLCHAIN_SUFFIX_C)=%.$(CY_TOOLCHAIN_SUFFIX_O))) +CY_BUILD_EXTSRC_CPP_OBJ_FILES=$(addprefix $(CY_CONFIG_DIR)/user/,$(CY_BUILD_EXTSRC_CPP_FILES:%.$(CY_TOOLCHAIN_SUFFIX_CPP)=%.$(CY_TOOLCHAIN_SUFFIX_O))) + +CY_BUILD_ALL_OBJ_FILES=\ + $(call CY_MACRO_REMOVE_DOUBLESLASH,\ + $(CY_BUILD_SRC_S_OBJ_FILES)\ + $(CY_BUILD_SRC_s_OBJ_FILES)\ + $(CY_BUILD_SRC_C_OBJ_FILES)\ + $(CY_BUILD_SRC_CPP_OBJ_FILES)\ + $(CY_BUILD_GENSRC_S_OBJ_FILES)\ + $(CY_BUILD_GENSRC_s_OBJ_FILES)\ + $(CY_BUILD_GENSRC_C_OBJ_FILES)\ + $(CY_BUILD_GENSRC_CPP_OBJ_FILES)\ + $(CY_BUILD_EXTSRC_S_OBJ_FILES)\ + $(CY_BUILD_EXTSRC_s_OBJ_FILES)\ + $(CY_BUILD_EXTSRC_C_OBJ_FILES)\ + $(CY_BUILD_EXTSRC_CPP_OBJ_FILES)) + +# +# Dependency files +# +CY_DEPENDENCY_FILES=$(CY_BUILD_ALL_OBJ_FILES:%.$(CY_TOOLCHAIN_SUFFIX_O)=%.$(CY_TOOLCHAIN_SUFFIX_D)) + +# +# The list of static libraries +# +CY_BUILD_ALL_LIB_FILES=$(CY_RECIPE_LIBS) + +# +# Output directories +# +CY_BUILD_DIRS=$(sort $(call CY_MACRO_DIR,$(CY_BUILD_ALL_OBJ_FILES)) $(call CY_MACRO_DIR,$(CY_BUILD_TARGET))) + +# +# Check Windows path length limit for build directories +# +ifeq ($(OS),Windows_NT) +CY_BUILD_CHECK_STRLEN:=$(shell \ + for directory in $(CY_BUILD_DIRS); do\ + if [ "$${\#directory}" -ge 260 ]; then\ + echo "$$directory";\ + fi;\ + done) + +ifneq ($(strip $(CY_BUILD_CHECK_STRLEN)),) +$(error Detected path(s) that exceed the Windows path length: $(CY_BUILD_CHECK_STRLEN)) +endif +endif + +# +# Prints full/shortened source name +# +ifneq (,$(filter $(VERBOSE),true 1)) +CY_COMPILE_PRINT=$< +else +CY_COMPILE_PRINT=$(notdir $<) +endif + +# +# Gather the includes in inclist_export.rsp files +# $(1) : List of inclist_export.rsp files +# +CY_MACRO_ECLIPSE_PRINT=$(shell \ + for incFile in $(1); do\ + incDirs="$$incDirs $$(cat $$incFile)";\ + done;\ + echo $$incDirs) + +# +# Construct the full list of flags +# +CY_BUILD_ALL_ASFLAGS_UC=\ + $(CY_RECIPE_ASFLAGS)\ + $(CY_RECIPE_DEFINES) + +CY_BUILD_ALL_ASFLAGS_LC=\ + $(CY_RECIPE_ASFLAGS) + +CY_BUILD_ALL_CFLAGS=\ + $(CY_RECIPE_CFLAGS)\ + $(CY_RECIPE_DEFINES) + +CY_BUILD_ALL_CXXFLAGS=\ + $(CY_RECIPE_CXXFLAGS)\ + $(CY_RECIPE_DEFINES) + +# +# Compiler arguments +# +CY_BUILD_COMPILE_AS_UC=$(AS) $(CY_BUILD_ALL_ASFLAGS_UC) $(CY_TOOLCHAIN_INCRSPFILE_ASM)$(CY_CONFIG_DIR)/inclist.rsp \ + $(CY_BUILD_SHAREDLIB_INCLIST) $(CY_TOOLCHAIN_OUTPUT_OPTION) +CY_BUILD_COMPILE_AS_LC=$(AS) $(CY_BUILD_ALL_ASFLAGS_LC) $(CY_TOOLCHAIN_INCRSPFILE_ASM)$(CY_CONFIG_DIR)/inclist.rsp \ + $(CY_BUILD_SHAREDLIB_INCLIST) $(CY_TOOLCHAIN_OUTPUT_OPTION) +CY_BUILD_COMPILE_C=$(CC) $(CY_BUILD_ALL_CFLAGS) $(CY_TOOLCHAIN_INCRSPFILE)$(CY_CONFIG_DIR)/inclist.rsp \ + $(CY_BUILD_SHAREDLIB_INCLIST) $(CY_TOOLCHAIN_DEPENDENCIES) $(CY_TOOLCHAIN_OUTPUT_OPTION) +CY_BUILD_COMPILE_CPP=$(CXX) $(CY_BUILD_ALL_CXXFLAGS) $(CY_TOOLCHAIN_INCRSPFILE)$(CY_CONFIG_DIR)/inclist.rsp \ + $(CY_BUILD_SHAREDLIB_INCLIST) $(CY_TOOLCHAIN_DEPENDENCIES) $(CY_TOOLCHAIN_OUTPUT_OPTION) + +# +# Linker arguments +# +CY_BUILD_LINK=$(LD) $(CY_RECIPE_LDFLAGS) $(CY_TOOLCHAIN_OUTPUT_OPTION) $@ $(CY_TOOLCHAIN_MAPFILE)$(CY_BUILD_MAPFILE) \ + $(CY_TOOLCHAIN_OBJRSPFILE)$(CY_CONFIG_DIR)/objlist.rsp \ + $(CY_TOOLCHAIN_STARTGROUP) $(CY_RECIPE_EXTRA_LIBS) $(CY_BUILD_ALL_LIB_FILES) $(CY_BUILD_SHAREDLIB_LIBLIST) $(CY_TOOLCHAIN_ENDGROUP) + +# +# Archiver arguments +# +CY_BUILD_ARCHIVE=$(AR) $(CY_RECIPE_ARFLAGS) $(CY_TOOLCHAIN_OUTPUT_OPTION) $@ $(CY_TOOLCHAIN_OBJRSPFILE)$(CY_CONFIG_DIR)/objlist.rsp + + +################################################################################ +# Dependency construction +################################################################################ + +# +# Dependency variables for compilation +# +CY_BUILD_COMPILER_DEPS=\ + $(CY_BUILD_COMPILE_AS_UC)\ + $(CY_BUILD_COMPILE_AS_LC)\ + $(CY_BUILD_COMPILE_C)\ + $(CY_BUILD_COMPILE_CPP)\ + $(CY_RECIPE_INCLUDES) + +# +# Dependency variables for link/archive +# +CY_BUILD_LINKER_DEPS=\ + $(CY_BUILD_LINK)\ + $(CY_BUILD_ARCHIVE)\ + $(CY_SHAREDLIB_ARTIFACT_EXPORT_LIST) + +# +# Read previous build's configuration if one exists +# +CY_BUILD_COMPILER_PREV=$(shell if [ -f "$(CY_CONFIG_DIR)/.cycompiler" ]; then cat $(CY_CONFIG_DIR)/.cycompiler; fi) +CY_BUILD_LINKER_PREV=$(shell if [ -f "$(CY_CONFIG_DIR)/.cylinker" ]; then cat $(CY_CONFIG_DIR)/.cylinker; fi) + +# +# Take care of the quotes for the echo command +# +CY_BUILD_COMPILER_DEPS_FORMATTED=$(subst ',,$(subst ",,$(CY_BUILD_COMPILER_DEPS))) +CY_BUILD_LINKER_DEPS_FORMATTED=$(subst ',,$(subst ",,$(CY_BUILD_LINKER_DEPS))) + +# +# Create compilation dependency file +# +ifneq ($(strip $(CY_BUILD_COMPILER_DEPS_FORMATTED)),$(strip $(CY_BUILD_COMPILER_PREV))) +ifeq ($(CY_BUILD_COMPILER_PREV),) +$(shell mkdir -p $(CY_CONFIG_DIR)) +endif +$(shell echo "$(CY_BUILD_COMPILER_DEPS_FORMATTED)" > $(CY_CONFIG_DIR)/.cycompiler) +endif + +# +# Create link dependency file +# +ifneq ($(strip $(CY_BUILD_LINKER_DEPS_FORMATTED)),$(strip $(CY_BUILD_LINKER_PREV))) +ifneq ($(CY_BUILD_LINKER_PREV),) +$(shell mkdir -p $(CY_CONFIG_DIR)) +endif +$(shell echo "$(CY_BUILD_LINKER_DEPS_FORMATTED)" > $(CY_CONFIG_DIR)/.cylinker) +endif + + +################################################################################ +# Application source Compilation +################################################################################ + +# Compile .S source +$(CY_CONFIG_DIR)/%.$(CY_TOOLCHAIN_SUFFIX_O) : $(CY_INTERNAL_APP_PATH)/%.$(CY_TOOLCHAIN_SUFFIX_S) +ifneq ($(CY_MAKE_IDE),eclipse) + $(info $(CY_INDENT)Compiling app file $(CY_COMPILE_PRINT)) +else + $(info Compiling $< $(CY_RECIPE_DEFINES) $(sort $(CY_RECIPE_INCLUDES) $(call CY_MACRO_ECLIPSE_PRINT,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST)))) +endif + $(CY_NOISE)$(CY_BUILD_COMPILE_AS_UC) $@ $< + +# Compile .s source +$(CY_CONFIG_DIR)/%.$(CY_TOOLCHAIN_SUFFIX_O) : $(CY_INTERNAL_APP_PATH)/%.$(CY_TOOLCHAIN_SUFFIX_s) +ifneq ($(CY_MAKE_IDE),eclipse) + $(info $(CY_INDENT)Compiling app file $(CY_COMPILE_PRINT)) +else + $(info Compiling $< $(CY_RECIPE_DEFINES) $(sort $(CY_RECIPE_INCLUDES) $(call CY_MACRO_ECLIPSE_PRINT,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST)))) +endif + $(CY_NOISE)$(CY_BUILD_COMPILE_AS_LC) $@ $< + +# Compile .c source +$(CY_CONFIG_DIR)/%.$(CY_TOOLCHAIN_SUFFIX_O) : $(CY_INTERNAL_APP_PATH)/%.$(CY_TOOLCHAIN_SUFFIX_C) +ifneq ($(CY_MAKE_IDE),eclipse) + $(info $(CY_INDENT)Compiling app file $(CY_COMPILE_PRINT)) +else + $(info Compiling $< $(CY_RECIPE_DEFINES) $(sort $(CY_RECIPE_INCLUDES) $(call CY_MACRO_ECLIPSE_PRINT,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST)))) +endif + $(CY_NOISE)$(CY_BUILD_COMPILE_C) $@ $< + +# Compile .cpp source +$(CY_CONFIG_DIR)/%.$(CY_TOOLCHAIN_SUFFIX_O) : $(CY_INTERNAL_APP_PATH)/%.$(CY_TOOLCHAIN_SUFFIX_CPP) +ifneq ($(CY_MAKE_IDE),eclipse) + $(info $(CY_INDENT)Compiling app file $(CY_COMPILE_PRINT)) +else + $(info Compiling $< $(CY_RECIPE_DEFINES) $(sort $(CY_RECIPE_INCLUDES) $(call CY_MACRO_ECLIPSE_PRINT,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST)))) +endif + $(CY_NOISE)$(CY_BUILD_COMPILE_CPP) $@ $< + + +################################################################################ +# ExtApp source Compilation +################################################################################ + +# Compile .S source +$(CY_CONFIG_DIR)/%.$(CY_TOOLCHAIN_SUFFIX_O) : $(CY_INTERNAL_EXTAPP_PATH)/%.$(CY_TOOLCHAIN_SUFFIX_S) +ifneq ($(CY_MAKE_IDE),eclipse) + $(info $(CY_INDENT)Compiling extapp file $(CY_COMPILE_PRINT)) +else + $(info Compiling $< $(CY_RECIPE_DEFINES) $(sort $(CY_RECIPE_INCLUDES) $(call CY_MACRO_ECLIPSE_PRINT,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST)))) +endif + $(CY_NOISE)$(CY_BUILD_COMPILE_AS_UC) $@ $< + +# Compile .s source +$(CY_CONFIG_DIR)/%.$(CY_TOOLCHAIN_SUFFIX_O) : $(CY_INTERNAL_EXTAPP_PATH)/%.$(CY_TOOLCHAIN_SUFFIX_s) +ifneq ($(CY_MAKE_IDE),eclipse) + $(info $(CY_INDENT)Compiling extapp file $(CY_COMPILE_PRINT)) +else + $(info Compiling $< $(CY_RECIPE_DEFINES) $(sort $(CY_RECIPE_INCLUDES) $(call CY_MACRO_ECLIPSE_PRINT,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST)))) +endif + $(CY_NOISE)$(CY_BUILD_COMPILE_AS_LC) $@ $< + +# Compile .c source +$(CY_CONFIG_DIR)/%.$(CY_TOOLCHAIN_SUFFIX_O) : $(CY_INTERNAL_EXTAPP_PATH)/%.$(CY_TOOLCHAIN_SUFFIX_C) +ifneq ($(CY_MAKE_IDE),eclipse) + $(info $(CY_INDENT)Compiling extapp file $(CY_COMPILE_PRINT)) +else + $(info Compiling $< $(CY_RECIPE_DEFINES) $(sort $(CY_RECIPE_INCLUDES) $(call CY_MACRO_ECLIPSE_PRINT,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST)))) +endif + $(CY_NOISE)$(CY_BUILD_COMPILE_C) $@ $< + +# Compile .cpp source +$(CY_CONFIG_DIR)/%.$(CY_TOOLCHAIN_SUFFIX_O) : $(CY_INTERNAL_EXTAPP_PATH)/%.$(CY_TOOLCHAIN_SUFFIX_CPP) +ifneq ($(CY_MAKE_IDE),eclipse) + $(info $(CY_INDENT)Compiling extapp file $(CY_COMPILE_PRINT)) +else + $(info Compiling $< $(CY_RECIPE_DEFINES) $(sort $(CY_RECIPE_INCLUDES) $(call CY_MACRO_ECLIPSE_PRINT,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST)))) +endif + $(CY_NOISE)$(CY_BUILD_COMPILE_CPP) $@ $< + + +################################################################################ +# Generated Source Compilation +################################################################################ + +# Compile .S source +$(CY_CONFIG_DIR)/generated/%.$(CY_TOOLCHAIN_SUFFIX_O) : $(CY_GENERATED_DIR)/%.$(CY_TOOLCHAIN_SUFFIX_S) +ifneq ($(CY_MAKE_IDE),eclipse) + $(info $(CY_INDENT)Compiling generated file $(CY_COMPILE_PRINT)) +else + $(info Compiling $< $(CY_RECIPE_DEFINES) $(sort $(CY_RECIPE_INCLUDES) $(call CY_MACRO_ECLIPSE_PRINT,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST)))) +endif + $(CY_NOISE)$(CY_BUILD_COMPILE_AS_UC) $@ $< + +# Compile .s source +$(CY_CONFIG_DIR)/generated/%.$(CY_TOOLCHAIN_SUFFIX_O) : $(CY_GENERATED_DIR)/%.$(CY_TOOLCHAIN_SUFFIX_s) +ifneq ($(CY_MAKE_IDE),eclipse) + $(info $(CY_INDENT)Compiling generated file $(CY_COMPILE_PRINT)) +else + $(info Compiling $< $(CY_RECIPE_DEFINES) $(sort $(CY_RECIPE_INCLUDES) $(call CY_MACRO_ECLIPSE_PRINT,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST)))) +endif + $(CY_NOISE)$(CY_BUILD_COMPILE_AS_LC) $@ $< + +# Compile .c source +$(CY_CONFIG_DIR)/generated/%.$(CY_TOOLCHAIN_SUFFIX_O) : $(CY_GENERATED_DIR)/%.$(CY_TOOLCHAIN_SUFFIX_C) +ifneq ($(CY_MAKE_IDE),eclipse) + $(info $(CY_INDENT)Compiling generated file $(CY_COMPILE_PRINT)) +else + $(info Compiling $< $(CY_RECIPE_DEFINES) $(sort $(CY_RECIPE_INCLUDES) $(call CY_MACRO_ECLIPSE_PRINT,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST)))) +endif + $(CY_NOISE)$(CY_BUILD_COMPILE_C) $@ $< + +# Compile .cpp source +$(CY_CONFIG_DIR)/generated/%.$(CY_TOOLCHAIN_SUFFIX_O) : $(CY_GENERATED_DIR)/%.$(CY_TOOLCHAIN_SUFFIX_CPP) +ifneq ($(CY_MAKE_IDE),eclipse) + $(info $(CY_INDENT)Compiling generated file $(CY_COMPILE_PRINT)) +else + $(info Compiling $< $(CY_RECIPE_DEFINES) $(sort $(CY_RECIPE_INCLUDES) $(call CY_MACRO_ECLIPSE_PRINT,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST)))) +endif + $(CY_NOISE)$(CY_BUILD_COMPILE_CPP) $@ $< + + +################################################################################ +# User source Compilation +################################################################################ + +# Compile .S source +$(CY_CONFIG_DIR)/user/%.$(CY_TOOLCHAIN_SUFFIX_O) : %.$(CY_TOOLCHAIN_SUFFIX_S) +ifneq ($(CY_MAKE_IDE),eclipse) + $(info $(CY_INDENT)Compiling user file $(CY_COMPILE_PRINT)) +else + $(info Compiling $< $(CY_RECIPE_DEFINES) $(sort $(CY_RECIPE_INCLUDES) $(call CY_MACRO_ECLIPSE_PRINT,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST)))) +endif + $(CY_NOISE)$(CY_BUILD_COMPILE_AS_UC) $@ $< + +# Compile .s source +$(CY_CONFIG_DIR)/user/%.$(CY_TOOLCHAIN_SUFFIX_O) : %.$(CY_TOOLCHAIN_SUFFIX_s) +ifneq ($(CY_MAKE_IDE),eclipse) + $(info $(CY_INDENT)Compiling user file $(CY_COMPILE_PRINT)) +else + $(info Compiling $< $(CY_RECIPE_DEFINES) $(sort $(CY_RECIPE_INCLUDES) $(call CY_MACRO_ECLIPSE_PRINT,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST)))) +endif + $(CY_NOISE)$(CY_BUILD_COMPILE_AS_LC) $@ $< + +# Compile .c source +$(CY_CONFIG_DIR)/user/%.$(CY_TOOLCHAIN_SUFFIX_O) : %.$(CY_TOOLCHAIN_SUFFIX_C) +ifneq ($(CY_MAKE_IDE),eclipse) + $(info $(CY_INDENT)Compiling user file $(CY_COMPILE_PRINT)) +else + $(info Compiling $< $(CY_RECIPE_DEFINES) $(sort $(CY_RECIPE_INCLUDES) $(call CY_MACRO_ECLIPSE_PRINT,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST)))) +endif + $(CY_NOISE)$(CY_BUILD_COMPILE_C) $@ $< + +# Compile .cpp source +$(CY_CONFIG_DIR)/user/%.$(CY_TOOLCHAIN_SUFFIX_O) : %.$(CY_TOOLCHAIN_SUFFIX_CPP) +ifneq ($(CY_MAKE_IDE),eclipse) + $(info $(CY_INDENT)Compiling user file $(CY_COMPILE_PRINT)) +else + $(info Compiling $< $(CY_RECIPE_DEFINES) $(sort $(CY_RECIPE_INCLUDES) $(call CY_MACRO_ECLIPSE_PRINT,$(CY_SHAREDLIB_INCLUDES_EXPORT_LIST)))) +endif + $(CY_NOISE)$(CY_BUILD_COMPILE_CPP) $@ $< + + +################################################################################ +# Prebuild, Postbuild and Link +################################################################################ + +# +# Top-level application dependency +# +app: CY_BUILD_sentinel + +# +# Print information before we start the build +# +CY_BUILD_preprint: | $(CY_SHAREDLIB_INCLUDES_EXPORT_LIST) $(CY_SHAREDLIB_LIBS_EXPORT_LIST) $(CY_SHAREDLIB_ARTIFACT_EXPORT_LIST) + $(info ) + $(info ==============================================================================) + $(info = Building application =) + $(info ==============================================================================) + +# +# Create the directories needed to do the build +# +CY_BUILD_mkdirs: CY_BUILD_preprint + $(CY_NOISE)mkdir -p $(CY_BUILD_DIRS) $(CY_CMD_TERM) +ifeq ($(CY_RECIPE_GENERATED_FLAG),TRUE) + $(CY_NOISE)mkdir -p $(CY_GENERATED_DIR) $(CY_CMD_TERM) +endif + +# +# Run BSP pre-build step +# +CY_BUILD_bsp_prebuild: CY_BUILD_mkdirs + $(CY_BSP_PREBUILD) + +# +# Run application pre-build step +# +CY_BUILD_app_prebuild: CY_BUILD_bsp_prebuild + $(PREBUILD) + +# +# Run generate source step +# +CY_BUILD_gensrc: CY_BUILD_app_prebuild +ifneq ($(CY_SEARCH_RESOURCE_FILES),) + @echo $(CY_RECIPE_RESOURCE_FILES) > $(CY_GENERATED_DIR)/resources.cyrsc +endif +ifeq ($(CY_RECIPE_GENERATED_FLAG),TRUE) + $(CY_NOISE)$(CY_RECIPE_GENSRC) $(CY_CMD_TERM) + $(info Generated $(words $(CY_RECIPE_GENERATED)) source file(s)) +endif + +# +# Add dependancy to support parallel builds +# +$(CY_BUILD_GENSRC_C_FILES): | CY_BUILD_gensrc + +# +# Run pre-build step +# +CY_BUILD_prebuild: CY_BUILD_gensrc + $(CY_NOISE)$(CY_RECIPE_PREBUILD) $(CY_CMD_TERM) + +# +# Print before compilation +# +CY_BUILD_precompile: CY_BUILD_prebuild + $(info Building $(words $(CY_BUILD_ALL_OBJ_FILES)) file(s)) + @echo $(CY_RECIPE_INCLUDES) | tr " " "\n" > $(CY_CONFIG_DIR)/inclist.rsp; \ + echo $(CY_BUILD_ALL_OBJ_FILES) | tr " " "\n" > $(CY_CONFIG_DIR)/objlist.rsp; \ + echo $(CY_BUILD_ALL_LIB_FILES) | tr " " "\n" > $(CY_CONFIG_DIR)/liblist.rsp; + +# +# Dependencies for compilation +# +$(CY_BUILD_ALL_OBJ_FILES): | CY_BUILD_precompile +$(CY_BUILD_ALL_OBJ_FILES): $(CY_CONFIG_DIR)/.cycompiler $(CY_SHAREDLIB_INCLUDES_EXPORT_LIST) + +# +# Dependencies for link +# +$(CY_BUILD_TARGET): | CY_BUILD_precompile +$(CY_BUILD_TARGET): $(CY_CONFIG_DIR)/.cylinker $(CY_SHAREDLIB_LIBS_EXPORT_LIST) $(CY_SHAREDLIB_ARTIFACT_EXPORT_LIST) + +# +# Link/archive the application +# +ifneq ($(LIBNAME),) +$(CY_BUILD_TARGET): $(CY_BUILD_ALL_OBJ_FILES) $(CY_BUILD_ALL_LIB_FILES) +ifneq ($(strip $(CY_BUILD_ALL_OBJ_FILES) $(CY_BUILD_ALL_LIB_FILES)),) + $(info $(CY_INDENT)Archiving output file $(notdir $@)) + $(CY_NOISE)$(CY_BUILD_ARCHIVE) $(CY_CMD_TERM) +endif +else +$(CY_BUILD_TARGET): $(CY_BUILD_ALL_OBJ_FILES) $(CY_BUILD_ALL_LIB_FILES) $(LINKER_SCRIPT) $(CY_SHAREDLIB_TIMESTAMP) +ifneq ($(SEARCH_LIBS_AND_INCLUDES),) + @libArray=($(CY_SHAREDLIB_LIBS_EXPORT_LIST)); \ + for libFile in "$${libArray[@]}"; do \ + if [ "$$libFile" -nt "$(CY_BUILD_TARGET)" ]; then \ + relink=true; \ + fi; \ + done; \ + artifactArray=($(CY_SHAREDLIB_ARTIFACT_EXPORT_LIST)); \ + for artifactFile in "$${artifactArray[@]}"; do \ + if [ "$$artifactFile" -nt "$(CY_BUILD_TARGET)" ]; then \ + relink=true; \ + fi; \ + done; \ + if [[ "$?" == *".$(CY_TOOLCHAIN_SUFFIX_O)"* ]] || [[ "$?" == *".$(CY_TOOLCHAIN_SUFFIX_A)"* ]]; then \ + relink=true; \ + fi; \ + if [ $$relink ]; then \ + echo " Linking output file $(notdir $@)"; \ + $(CY_BUILD_LINK); \ + fi +else + $(info $(CY_INDENT)Linking output file $(notdir $@)) + $(CY_NOISE)$(CY_BUILD_LINK) +endif +endif + +# +# Perform post-build step +# +CY_BUILD_postbuild: $(CY_BUILD_TARGET) + $(CY_NOISE)$(CY_RECIPE_POSTBUILD) $(CY_CMD_TERM) + +# +# Run BSP post-build step +# +CY_BUILD_bsp_postbuild: CY_BUILD_postbuild + $(CY_BSP_POSTBUILD) + +# +# Perform application post-build step +# +CY_BUILD_app_postbuild: CY_BUILD_bsp_postbuild + $(POSTBUILD) + +# +# Perform the post build print step, basically stating we are done +# +CY_BUILD_postprint: CY_BUILD_app_postbuild + $(info ==============================================================================) + $(info = Build complete =) + $(info ==============================================================================) + $(info ) + +# +# Create an artifact sentinel file for shared libs +# +ifneq ($(LIBNAME),) +CY_BUILD_sentinel: CY_BUILD_postprint +ifneq ($(strip $(CY_BUILD_ALL_OBJ_FILES) $(CY_BUILD_ALL_LIB_FILES)),) + @echo $(LIBNAME).$(CY_TOOLCHAIN_SUFFIX_ARCHIVE) > $(CY_CONFIG_DIR)/artifact.rsp +else + @touch $(CY_CONFIG_DIR)/artifact.rsp +endif +else +CY_BUILD_sentinel: CY_BUILD_postprint + +endif + +# +# Include generated dependency files (if rebuilding) +# +-include $(CY_DEPENDENCY_FILES) + +# +# Indicate all phony targets that should be built regardless +# +.PHONY: app $(CY_SHAREDLIB_LIST) +.PHONY: CY_BUILD_mkdirs +.PHONY: CY_BUILD_prebuild CY_BUILD_app_prebuild CY_BUILD_bsp_prebuild +.PHONY: CY_BUILD_postbuild CY_BUILD_app_postbuild CY_BUILD_bsp_postbuild +.PHONY: CY_BUILD_gensrc +.PHONY: CY_BUILD_genresource +.PHONY: CY_BUILD_preprint +.PHONY: CY_BUILD_postprint +.PHONY: CY_BUILD_sentinel diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/config.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/config.mk new file mode 100644 index 0000000000000000000000000000000000000000..dbfd07a6221c9f1dbb89279fa9df70cd31fa207d --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/config.mk @@ -0,0 +1,235 @@ +################################################################################ +# \file config.mk +# \version 1.0 +# +# \brief +# Configurator-related routines +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + +# +# Default file extension +# +CY_CONFIG_FILE_EXT?=modus + + +################################################################################ +# Search +################################################################################ + +CY_CONFIG_MODUS_EXT=modus +CY_CONFIG_CYBT_EXT=cybt +CY_CONFIG_CYUSBDEV_EXT=cyusbdev + +# +# Search for configuration files and filter +# +CY_CONFIG_MODUS_FILES:=$(call CY_MACRO_SEARCH,.$(CY_CONFIG_MODUS_EXT),$(CY_INTERNAL_APP_PATH))\ + $(if $(CY_INTERNAL_EXTAPP_PATH),$(call CY_MACRO_SEARCH,.$(CY_CONFIG_MODUS_EXT),$(CY_INTERNAL_EXTAPP_PATH)))\ + $(if $(SEARCH_LIBS_AND_INCLUDES),$(foreach d,$(SEARCH_LIBS_AND_INCLUDES),$(call CY_MACRO_SEARCH,.$(CY_CONFIG_MODUS_EXT),$(d)))) +CY_CONFIG_CYBT_FILES:=$(call CY_MACRO_SEARCH,.$(CY_CONFIG_CYBT_EXT),$(CY_INTERNAL_APP_PATH))\ + $(if $(CY_INTERNAL_EXTAPP_PATH),$(call CY_MACRO_SEARCH,.$(CY_CONFIG_CYBT_EXT),$(CY_INTERNAL_EXTAPP_PATH)))\ + $(if $(SEARCH_LIBS_AND_INCLUDES),$(foreach d,$(SEARCH_LIBS_AND_INCLUDES),$(call CY_MACRO_SEARCH,.$(CY_CONFIG_CYBT_EXT),$(d)))) +CY_CONFIG_CYUSBDEV_FILES:=$(call CY_MACRO_SEARCH,.$(CY_CONFIG_CYUSBDEV_EXT),$(CY_INTERNAL_APP_PATH))\ + $(if $(CY_INTERNAL_EXTAPP_PATH),$(call CY_MACRO_SEARCH,.$(CY_CONFIG_CYUSBDEV_EXT),$(CY_INTERNAL_EXTAPP_PATH)))\ + $(if $(SEARCH_LIBS_AND_INCLUDES),$(foreach d,$(SEARCH_LIBS_AND_INCLUDES),$(call CY_MACRO_SEARCH,.$(CY_CONFIG_CYUSBDEV_EXT),$(d)))) + +CY_SEARCH_PRUNED_MODUS_FILES:=$(filter-out $(foreach d,$(CY_IGNORE_DIRS),$(filter $(d)%,$(CY_CONFIG_MODUS_FILES))),$(CY_CONFIG_MODUS_FILES)) +CY_SEARCH_PRUNED_CYBT_FILES:=$(filter-out $(foreach d,$(CY_IGNORE_DIRS),$(filter $(d)%,$(CY_CONFIG_CYBT_FILES))),$(CY_CONFIG_CYBT_FILES)) +CY_SEARCH_PRUNED_CYUSBDEV_FILES:=$(filter-out $(foreach d,$(CY_IGNORE_DIRS),$(filter $(d)%,$(CY_CONFIG_CYUSBDEV_FILES))),$(CY_CONFIG_CYUSBDEV_FILES)) + +CY_SEARCH_AVAILABLE_MODUS_SOURCES=$(call CY_MACRO_FILTER_FILES,MODUS) +CY_SEARCH_AVAILABLE_CYBT_SOURCES=$(call CY_MACRO_FILTER_FILES,CYBT) +CY_SEARCH_AVAILABLE_CYUSBDEV_SOURCES=$(call CY_MACRO_FILTER_FILES,CYUSBDEV) + +ifneq ($(words $(CY_SEARCH_AVAILABLE_MODUS_SOURCES)),1) +ifneq ($(words $(CY_SEARCH_AVAILABLE_MODUS_SOURCES)),0) +$(call CY_MACRO_ERROR,Multiple device configuration files detected: $(CY_SEARCH_AVAILABLE_MODUS_SOURCES)) +endif +endif +ifneq ($(words $(CY_SEARCH_AVAILABLE_CYBT_SOURCES)),1) +ifneq ($(words $(CY_SEARCH_AVAILABLE_CYBT_SOURCES)),0) +$(call CY_MACRO_ERROR,Multiple BT configuration files detected: $(CY_SEARCH_AVAILABLE_CYBT_SOURCES)) +endif +endif +ifneq ($(words $(CY_SEARCH_AVAILABLE_CYUSBDEV_SOURCES)),1) +ifneq ($(words $(CY_SEARCH_AVAILABLE_CYUSBDEV_SOURCES)),0) +$(call CY_MACRO_ERROR,Multiple USBDEV configuration files detected: $(CY_SEARCH_AVAILABLE_CYUSBDEV_SOURCES)) +endif +endif + + +################################################################################ +# Arguments constructions +################################################################################ + +########################## +# .modus (HW) +########################## + +CY_CONFIG_MODUS_FILE?=$(CY_SEARCH_AVAILABLE_MODUS_SOURCES) +CY_CONFIG_MODUS_OUTPUT=$(call CY_MACRO_DIR,$(CY_CONFIG_MODUS_FILE))/GeneratedSource + +ifeq ($(CY_DEVICESUPPORT_PATH),) +CY_CONFIG_LIBFILE= +else +CY_CONFIG_LIBFILE=--library $(CY_INTERNAL_DEVICESUPPORT_PATH)/devicesupport.xml +endif + +CY_CONFIG_MODUS_EXEC=$(CY_CFG_BACKEND_CLI_DIR)/cfg-backend-cli +CY_CONFIG_MODUS_EXEC_FLAGS=\ + $(CY_CONFIG_LIBFILE)\ + --build $(CY_CONFIG_MODUS_FILE)\ + --set-device=$(subst $(CY_SPACE),$(CY_COMMA),$(DEVICE) $(ADDITIONAL_DEVICES)) + +CY_CONFIG_MODUS_GUI=$(CY_DEVICE_CONFIGURATOR_DIR)/device-configurator +CY_CONFIG_MODUS_GUI_FLAGS=\ + --design + +########################## +# .cybt (SW) +########################## + +CY_CONFIG_CYBT_FILE?=$(CY_SEARCH_AVAILABLE_CYBT_SOURCES) +CY_CONFIG_CYBT_OUTPUT=$(call CY_MACRO_DIR,$(CY_CONFIG_CYBT_FILE))/GeneratedSource + +CY_CONFIG_CYBT_EXEC=$(CY_BT_CONFIGURATOR_DIR)/bt-configurator-cli +CY_CONFIG_CYBT_EXEC_FLAGS=\ + --config $(CY_CONFIG_CYBT_FILE) + +CY_CONFIG_CYBT_GUI=$(CY_BT_CONFIGURATOR_DIR)/bt-configurator +CY_CONFIG_CYBT_GUI_FLAGS=\ + --config + +########################## +# .cyusbdev (SW) +########################## + +CY_CONFIG_CYUSBDEV_FILE?=$(CY_SEARCH_AVAILABLE_CYUSBDEV_SOURCES) +CY_CONFIG_CYUSBDEV_OUTPUT=$(call CY_MACRO_DIR,$(CY_CONFIG_CYUSBDEV_FILE))/GeneratedSource + +CY_CONFIG_CYUSBDEV_EXEC=$(CY_USBDEV_CONFIGURATOR_DIR)/usbdev-configurator-cli +CY_CONFIG_CYUSBDEV_EXEC_FLAGS=\ + --config $(CY_CONFIG_CYUSBDEV_FILE) + +CY_CONFIG_CYUSBDEV_GUI=$(CY_USBDEV_CONFIGURATOR_DIR)/usbdev-configurator +CY_CONFIG_CYUSBDEV_GUI_FLAGS=\ + --config + + +################################################################################ +# Source generation +################################################################################ + +ifeq ($(CY_COMMENCE_BUILD),true) + +########################## +# .modus +########################## + +# Check the timestamps and re-run the configurator if it's stale +ifneq ($(CY_CONFIG_MODUS_FILE),) +CY_CONFIG_MODUS_STATE=$(shell if [ "$(CY_CONFIG_MODUS_FILE)" -nt "$(CY_CONFIG_MODUS_OUTPUT)/cycfg.timestamp" ]; then echo 1; else echo 0; fi) +ifeq ($(CY_CONFIG_MODUS_STATE),1) +$(info $(CY_INDENT)Stale device files detected. Running device configurator to regenerate files...) +ifneq ($(shell $(CY_CONFIG_MODUS_EXEC) $(CY_CONFIG_MODUS_EXEC_FLAGS) 1> /dev/null; echo $$?),0) + $(error Error(s) encountered while running the configurator on $(CY_CONFIG_MODUS_FILE)) +endif +endif +endif + +########################## +# .cybt +########################## + +# Check the timestamps and re-run the configurator if it's stale +ifneq ($(CY_CONFIG_CYBT_FILE),) +CY_CONFIG_CYBT_STATE=$(shell if [ "$(CY_CONFIG_CYBT_FILE)" -nt "$(CY_CONFIG_CYBT_OUTPUT)/cycfg_bt.timestamp" ]; then echo 1; else echo 0; fi) +ifeq ($(CY_CONFIG_CYBT_STATE),1) +$(info $(CY_INDENT)Stale BT files detected. Running BT-configurator to regenerate files...) +ifneq ($(shell $(CY_CONFIG_CYBT_EXEC) $(CY_CONFIG_CYBT_EXEC_FLAGS) 1> /dev/null; echo $$?),0) + $(error Error(s) encountered while running the configurator on $(CY_CONFIG_CYBT_FILE)) +endif +endif +endif + +########################## +# .cyusbdev +########################## + +# Check the timestamps and re-run the configurator if it's stale +ifneq ($(CY_CONFIG_CYUSBDEV_FILE),) +CY_CONFIG_CYUSBDEV_STATE=$(shell if [ "$(CY_CONFIG_CYUSBDEV_FILE)" -nt "$(CY_CONFIG_CYUSBDEV_OUTPUT)/cycfg_usbdev.timestamp" ]; then echo 1; else echo 0; fi) +ifeq ($(CY_CONFIG_CYUSBDEV_STATE),1) +$(info $(CY_INDENT)Stale USBDEV files detected. Running USBDEV-configurator to regenerate files...) +ifneq ($(shell $(CY_CONFIG_CYUSBDEV_EXEC) $(CY_CONFIG_CYUSBDEV_EXEC_FLAGS) 1> /dev/null; echo $$?),0) + $(error Error(s) encountered while running the configurator on $(CY_CONFIG_CYUSBDEV_FILE)) +endif +endif +endif + +endif + + +################################################################################ +# Targets +################################################################################ + +# Extract the names for the variable name construction +CY_CONFIG_CONVERT=$(foreach ext,$(CY_CONFIG_FILE_EXT),$(call CY_MACRO_UC,$(ext))) + +# Gather the files. Find all files that match the extensions in the design.modus location +CY_CONFIG_FILES=$(sort $(foreach ext,$(CY_CONFIG_CONVERT),$(CY_CONFIG_$(ext)_FILE))\ + $(foreach ext,$(CY_CONFIG_FILE_EXT),$(wildcard $(call CY_MACRO_DIR,$(CY_CONFIG_MODUS_FILE))/*.$(ext)))) + +config: +ifeq ($(CY_CONFIG_MODUS_FILE),) + $(info $(CY_NEWLINE)Could not find any device configuration files) + $(info Launching device-configurator for a new configuration) + $(CY_NOISE) $(CY_CONFIG_MODUS_GUI) $(CY_CONFIG_LIBFILE) +else + $(info $(CY_NEWLINE)Launching device-configurator on $(CY_CONFIG_MODUS_FILE)) + $(CY_NOISE) $(CY_CONFIG_MODUS_GUI) $(CY_CONFIG_LIBFILE) $(CY_CONFIG_MODUS_GUI_FLAGS) $(CY_CONFIG_MODUS_FILE) +endif + +config_bt: +ifeq ($(CY_CONFIG_CYBT_FILE),) + $(info $(CY_NEWLINE)Could not find any bt-configuration files) + $(info Launching bt-configurator for a new configuration) + $(CY_NOISE) $(CY_CONFIG_CYBT_GUI) +else + $(info $(CY_NEWLINE)Launching bt-configurator on $(CY_CONFIG_CYBT_FILE)) + $(CY_NOISE) $(CY_CONFIG_CYBT_GUI) $(CY_CONFIG_CYBT_GUI_FLAGS) $(CY_CONFIG_CYBT_FILE) +endif + +config_usbdev: +ifeq ($(CY_CONFIG_CYUSBDEV_FILE),) + $(info $(CY_NEWLINE)Could not find any usbdev-configuration files) + $(info Launching usbdev-configurator for a new configuration) + $(CY_NOISE) $(CY_CONFIG_CYUSBDEV_GUI) +else + $(info $(CY_NEWLINE)Launching usbdev-configurator on $(CY_CONFIG_CYUSBDEV_FILE)) + $(CY_NOISE) $(CY_CONFIG_CYUSBDEV_GUI) $(CY_CONFIG_CYUSBDEV_GUI_FLAGS) $(CY_CONFIG_CYUSBDEV_FILE) +endif + +.PHONY: config config_bt config_usbdev diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/help.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/help.mk new file mode 100644 index 0000000000000000000000000000000000000000..ee62eac005b90be401ff708e1a361ae8525f4041 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/help.mk @@ -0,0 +1,374 @@ +################################################################################ +# \file help.mk +# \version 1.0 +# +# \brief +# Default help documentation +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + +# +# General Targets +# +CY_HELP_all_VERBOSE=This target is equivalent to the "build" target. +CY_HELP_getlibs_VERBOSE=The repos are cloned to the libs directory. By default, this directory is\ + created in the application directory. It may be directed to other locations using\ + the CY_GETLIBS_PATH variable. +CY_HELP_build_VERBOSE=The build process involves source auto-discovery, code generation, prebuilds, and postbuilds.\ + For faster incremental builds, use the "qbuild" target to skip the auto-generation step. +CY_HELP_qbuild_VERBOSE=When no other sources need to be auto-discovered, this target can be used to skip\ + the auto-discovery step for a faster incremental build. +CY_HELP_program_VERBOSE=The build process performs the same operations as the "build" target. Upon completion,\ + the artifact is programmed to the board. +CY_HELP_qprogram_VERBOSE=This target allows programming an existing artifact to the board without a build step. +CY_HELP_debug_VERBOSE=Once the GDB server is launched, another shell should be opened to launch a GDB client. +CY_HELP_qdebug_VERBOSE=Once the GDB server is launched, another shell should be opened to launch a GDB client. +CY_HELP_clean_VERBOSE=The directory and all its contents are deleted from disk. +CY_HELP_help_VERBOSE=Use the CY_HELP= to see the verbose documentation for a\ + particular target or a variable. + +# +# Configurator Targets +# +CY_HELP_open_VERBOSE=This target accepts two variables – CY_OPEN_TYPE and CY_OPEN_FILE. At least one of\ + these must be provided. The tool can be specified by setting the CY_OPEN_TYPE variable.\ + A specific file can also be passed using the CY_OPEN_FILE variable. If only CY_OPEN_FILE is given,\ + the build system will launch the default tool associated with the file’s extension. +CY_HELP_config_VERBOSE=If no existing device-configuration files are found, the configurator is launched to create one. +CY_HELP_config_bt_VERBOSE=If no existing bt-configuration files are found, the configurator is launched to create one. +CY_HELP_config_usbdev_VERBOSE=If no existing usbdev-configuration files are found, the configurator is launched to create one. + +# +# Utility Targets +# +CY_HELP_eclipse_VERBOSE=This target expects the CY_IDE_PRJNAME variable to be set to the name of the project\ + as defined in the eclipse IDE. E.g. "make eclipse CY_IDE_PRJNAME=AppV1". If this variable\ + is not defined, it will use the APPNAME for the launch configs. +CY_HELP_check_VERBOSE=Not all tools are necessary for every build recipe. This target allows the user\ + to get an idea of which tools are missing if a build fails in an unexpected way. +CY_HELP_get_app_info_VERBOSE=The file types can be specified by setting the\ + CY_CONFIG_FILE_EXT variable. E.g. "make get_app_info "CY_CONFIG_FILE_EXT=modus cybt cyusbdev"". +CY_HELP_get_env_info_VERBOSE=This allows a quick printout of the current app repo and the "make" and "git"\ + tool locations and versions. +CY_HELP_printlibs_VERBOSE=This target parses through the library repos and prints the SHA1 commit id for each library.\ + It also shows whether the repo is clean (no changes) or dirty (modified or new files). + +# +# Basic configuration +# +CY_HELP_TARGET=Specifies the target board/kit. E.g. CY8CPROTO-062-4343W. +CY_HELP_TARGET_VERBOSE=Currently available target(s) in this application is/are, [ $(CY_TARGET_AVAILABLE) ]. +CY_HELP_APPNAME=Specifies the name of the application. E.g. AppV1. +CY_HELP_APPNAME_VERBOSE=This variable signifies that the application will build an artifact that is\ + intended for a target board. For applications that need to build into an archive (library),\ + use the LIBNAME variable. +CY_HELP_LIBNAME=Specifies the name of the library application. E.g. LibV1. +CY_HELP_LIBNAME_VERBOSE=This variable signifies that the application will build an archive (library).\ + These library applications can be added as a dependency to an artifact producing application\ + using the SEARCH_LIBS_AND_INCLUDES variable. +CY_HELP_TOOLCHAIN=Specifies the toolchain for building the application. E.g. GCC_ARM. +CY_HELP_TOOLCHAIN_VERBOSE=Supported toolchains for this target are, [ $(CY_SUPPORTED_TOOLCHAINS) ]. +CY_HELP_CONFIG=Specifies the configuration option for the build [Debug Release]. +CY_HELP_CONFIG_VERBOSE=The CONFIG variable is not limited to Debug/Release. It can be\ + other values. However in those instances, the build system will not configure the optimization flags.\ + Debug=lowest optimization, Release=highest optimization. The optimization flags are toolchain-specific.\ + If you go with your custom config then you can manually set the optimization flag in the CFLAGS. +CY_HELP_VERBOSE=Specifies whether the build is silent [false] or verbose [true]. +CY_HELP_VERBOSE_VERBOSE=Setting VERBOSE to true may help in debuggging build errors/warnings. + +# +# Advanced configuration +# +CY_HELP_SOURCES=Specifies C/C++ and assembly files not under the working directory. +CY_HELP_SOURCES_VERBOSE=This can be used to include files external to the application directory. +CY_HELP_INCLUDES=Specifies include paths not under the working directory. +CY_HELP_INCLUDES_VERBOSE=Note: These MUST NOT have -I prepended. +CY_HELP_DEFINES=Specifies additional defines passed to the compiler. +CY_HELP_DEFINES_VERBOSE=Note: These MUST NOT have -D prepended. +CY_HELP_VFP_SELECT=Selects hard/soft ABI for floating-point operations [softfp hardfp]. +CY_HELP_VFP_SELECT_VERBOSE=If not defined, this value defaults to softfp. +CY_HELP_CFLAGS=Prepends additional C compiler flags. +CY_HELP_CFLAGS_VERBOSE=Note: If the entire C compiler flags list needs to be replaced, define the\ + CY_RECIPE_CFLAGS make variable with the desired C flags. +CY_HELP_CXXFLAGS=Prepends additional C++ compiler flags. +CY_HELP_CXXFLAGS_VERBOSE=Note: If the entire C++ compiler flags list needs to be replaced, define the\ + CY_RECIPE_CXXFLAGS make variable with the desired C++ flags. +CY_HELP_ASFLAGS=Prepends additional assembler flags. +CY_HELP_ASFLAGS_VERBOSE=Note: If the entire assembler flags list needs to be replaced, define the\ + CY_RECIPE_ASFLAGS make variable with the desired assembly flags. +CY_HELP_LDFLAGS=Prepends additional linker flags. +CY_HELP_LDFLAGS_VERBOSE=Note: If the entire linker flags list needs to be replaced, define the\ + CY_RECIPE_LDFLAGS make variable with the desired linker flags. +CY_HELP_LDLIBS=Includes application-specific prebuilt libraries. +CY_HELP_LDLIBS_VERBOSE=Note: If additional libraries need to be added using -l or -L, add to the\ + CY_RECIPE_EXTRA_LIBS make variable. +CY_HELP_LINKER_SCRIPT=Specifies a custom linker script location. +CY_HELP_LINKER_SCRIPT_VERBOSE=This linker script overrides the default. Note: Additional\ + linker scripts can be added for GCC via the LDFLAGS variable as a -L option. +CY_HELP_PREBUILD=Specifies the location of a custom prebuild step and its arguments. +CY_HELP_PREBUILD_VERBOSE=This operation runs before the build recipe's prebuild step.\ + $(CY_NEWLINE)Note: BSPs can also define a prebuild step. This runs before the\ + application prebuild step.\ + $(CY_NEWLINE)Note: If the default prebuild step needs to be replaced, define the\ + CY_RECIPE_PREBUILD make variable with the desired prebuild step. +CY_HELP_POSTBUILD=Specifies the location of a custom postbuild step and its arguments. +CY_HELP_POSTBUILD_VERBOSE=This operation runs after the build recipe's postbuild step.\ + $(CY_NEWLINE)Note: BSPs can also define a postbuild step. This runs before the\ + application postbuild step.\ + $(CY_NEWLINE)Note: If the default postbuild step needs to be replaced, define the\ + CY_RECIPE_POSTBUILD make variable with the desired postbuild step. +CY_HELP_COMPONENTS=Adds component-specific files to the build. +CY_HELP_COMPONENTS_VERBOSE=Create a directory named COMPONENT_ and place your files.\ + Then include the to this make variable to have that feature library\ + be included in the build. E.g. Create a directory named COMPONENT_ACCELEROMETER.\ + Then include it in the make variable. COMPONENT=ACCELEROMETER. If the make variable\ + does not include the , then that library will not be included in the build.\ + $(CY_NEWLINE)Note: If the default COMPONENT list must be overridden, defined the CY_COMPONENT_LIST\ + make variable with the list of component values. +CY_HELP_DISABLE_COMPONENTS=Removes component-specific files from the build. +CY_HELP_DISABLE_COMPONENTS_VERBOSE=Include a to this make variable to have that feature library\ + be excluded in the build. E.g. To exclude the contents of COMPONENT_BSP_DESIGN_MODUS\ + directory, set DISABLE_COMPONENTS=BSP_DESIGN_MODUS. +CY_HELP_SEARCH_LIBS_AND_INCLUDES=List of dependent library application paths. E.g. ../bspLib. +CY_HELP_SEARCH_LIBS_AND_INCLUDES_VERBOSE=An artifact producing application (Defined by setting APPNAME),\ + can have a dependency on library applications (Defined by setting LIBNAME). This variable\ + defines those dependencies for the artifact producing application. The actual build invocation\ + of those libraries are handled at the application level by defining the "shared_libs" target. E.g.\ + $(CY_NEWLINE)$(CY_NEWLINE)shared_libs: $(CY_NEWLINE)$(CY_INDENT)make -C ../bspLib build -j + +# +# Path variables +# +CY_HELP_CY_APP_PATH=Relative path to the top-level of application. E.g. ./ +CY_HELP_CY_APP_PATH_VERBOSE=Settings this path to other than ./ allows the auto-discovery mechanism\ + to search from a root directory location that is higher than the app directory.\ + E.g. CY_APP_PATH=../../ allows auto-discovery of files from a location that is\ + two directories above the location of ./Makefile. +CY_HELP_CY_BASELIB_PATH=Relative path to the base library. E.g. ./libs/psoc6make +CY_HELP_CY_BASELIB_PATH_VERBOSE=This directory must be relative to CY_APP_PATH. It defines the location\ + of the library containing the recipe make files, where the expected directory structure\ + is /make. All applications must set the location of the base library. +CY_HELP_CY_GETLIBS_PATH=Absolute path to the intended location of libs directory. +CY_HELP_CY_GETLIBS_PATH_VERBOSE=The library repos are cloned into a directory named, libs (Default: /libs).\ + Setting this variable allows specifying the location of the libs directory to elsewhere on disk. +CY_HELP_CY_GETLIBS_SEARCH_PATH=Relative path to the top directory for "getlibs" operation. +CY_HELP_CY_GETLIBS_SEARCH_PATH_VERBOSE=The getlibs operation by default executes at the location of the CY_APP_PATH. This can\ + be overridden by specifying this variable to point to a specific location. +CY_HELP_CY_DEVICESUPPORT_PATH=Relative path to the devicesupport.xml file. +CY_HELP_CY_DEVICESUPPORT_PATH_VERBOSE=This path specifies the location of the devicesupport.xml file for device-configurators.\ + It is used when the configurator needs to be run in a multi-app scenario. +CY_HELP_CY_SHARED_PATH=Relative path to the location of shared .lib files. +CY_HELP_CY_SHARED_PATH_VERBOSE=This variable is used in shared library applications to point to the location of external .lib files. +CY_HELP_CY_COMPILER_PATH=Absolute path to the compiler (Default: GCC_ARM in CY_TOOLS_DIR). +CY_HELP_CY_COMPILER_PATH_VERBOSE=Setting this path allows custom toolchains to be used instead of the defaults.\ + This should be the location of the /bin directory containing the compiler, assembler and\ + linker. E.g. CY_COMPILER_PATH="C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.2/arm/bin". +CY_HELP_CY_TOOLS_DIR=Absolute path to the tools root directory. +CY_HELP_CY_TOOLS_DIR_VERBOSE=Applications must specify the directory of the tools install, which contains the\ + root makefile and the necessary tools and scripts to build an application. Application Makefiles\ + are configured to automatically search in the standard locations for various platforms.\ + If the tools are not located in the standard location, you may explicitly set this. +CY_HELP_CY_BUILD_LOCATION=Absolute path to the build output directory (Default: pwd/build). +CY_HELP_CY_BUILD_LOCATION_VERBOSE=The build output directory is structured as /TARGET/CONFIG/. Setting this variable\ + allows the build artifacts to be located in the directory pointed to by this variable. +CY_HELP_CY_EXTAPP_PATH=Relative path to an external app directory. E.g. ../external +CY_HELP_CY_EXTAPP_PATH_VERBOSE=This directory must be relative to CY_APP_PATH. Setting this path\ + allows incorporating files external to CY_APP_PATH. E.g. CY_EXTAPP_PATH=../external\ + lets the auto-discovery to pull in the contents of ../external directory into the build.\ + $(CY_NEWLINE)Note: This variable is only supported in CLI. Use the shared_libs mechanism and\ + CY_HELP_SEARCH_LIBS_AND_INCLUDES for tools and IDE support. + +# +# Miscellaneous variables +# +CY_HELP_CY_IGNORE=Adds to the directory and file ignore list. E.g. ./file1.c ./inc1 +CY_HELP_CY_IGNORE_VERBOSE=Directories and files listed in this variable are ignored in the auto-discovery.\ + This mechanism works in combination with any existing .cyignore files in the application. +CY_HELP_CY_IDE_PRJNAME=Name of the eclipse IDE project. +CY_HELP_CY_IDE_PRJNAME_VERBOSE=This variable can be used to define the file and target project name when\ + generating eclipse launch configurations in the "eclipse" target. +CY_HELP_CY_CONFIG_FILE_EXT=Specifies the configurator file extension. E.g. modus +CY_HELP_CY_CONFIG_FILE_EXT_VERBOSE=This variable accepts a space-separated list of configurator file extensions\ + that should be searched for when running the "get_app_info" target. +CY_HELP_CY_SKIP_RECIPE=Skip including the recipe make files. +CY_HELP_CY_SKIP_RECIPE_VERBOSE=This allows the application to not include any recipe makefiles and only\ + include the start.mk file from the tools install. +CY_HELP_CY_SUPPORTED_TOOL_TYPES=Defines the supported tools for a BSP. +CY_HELP_CY_SUPPORTED_TOOL_TYPES_VERBOSE=BSPs can define the supported tools that can be launched using the\ + "open" target. The supported tool types are $(CY_OPEN_TYPE_LIST). +CY_HELP_CY_LIBS_SEARCH_DEPTH=Search depth for .lib files (Default: 5). +CY_HELP_CY_LIBS_SEARCH_DEPTH_VERBOSE=This variable controls how deep (directory) the search mechanism in getlibs looks for .lib files.\ + $(CY_NEWLINE)Note: Deeper searches take longer to process. +CY_HELP_CY_UTILS_SEARCH_DEPTH=Search depth for .cyignore and TARGET.mk files (Default: 5). +CY_HELP_CY_UTILS_SEARCH_DEPTH_VERBOSE=This variable controls how deep (directory) the search mechanism looks for .cyignore\ + and TARGET.mk files. Min=1, Max=9.\ + $(CY_NEWLINE)Note: Deeper searches take longer to process. +CY_HELP_CY_EXTRA_INCLUDES=Specifies additional makefiles to add to the build. +CY_HELP_CY_EXTRA_INCLUDES_VERBOSE=The application Makefile cannot add additional make files directly. Instead, use\ + this variable to include these in the build. E.g. CY_EXTRA_INCLUDES=./custom1.mk ./custom2.mk +CY_HELP_TOOLCHAIN_MK_PATH=Specifies the location of a custom TOOLCHAIN makefile. +CY_HELP_TOOLCHAIN_MK_PATH_VERBOSE=Defining this path allows the build system to use a custom TOOLCHAIN.mk\ + pointed to by this variable.\ + $(CY_NEWLINE)Note: The make variables in this file should match the\ + variables used in existing TOOLCHAIN.mk files. + +# Pass these to CY_HELP to get the full verbose info +CY_HELP_TARGETS_ALL=all getlibs build qbuild program qprogram debug qdebug clean help open config config_bt config_usbdev \ + eclipse check get_app_info get_env_info printlibs +CY_HELP_BASIC_CFG_ALL=TARGET APPNAME LIBNAME TOOLCHAIN CONFIG VERBOSE +CY_HELP_ADVANCED_CFG_ALL=SOURCES INCLUDES DEFINES VFP_SELECT CFLAGS CXXFLAGS ASFLAGS LDFLAGS LDLIBS LINKER_SCRIPT \ + PREBUILD POSTBUILD COMPONENTS DISABLE_COMPONENTS SEARCH_LIBS_AND_INCLUDES +CY_HELP_PATHS_ALL=CY_APP_PATH CY_BASELIB_PATH CY_EXTAPP_PATH CY_GETLIBS_PATH CY_GETLIBS_SEARCH_PATH CY_DEVICESUPPORT_PATH \ + CY_SHARED_PATH CY_COMPILER_PATH CY_TOOLS_DIR CY_BUILD_LOCATION +CY_HELP_MISC_ALL=CY_IGNORE CY_IDE_PRJNAME CY_CONFIG_FILE_EXT CY_SKIP_RECIPE CY_SUPPORTED_TOOL_TYPES CY_LIBS_SEARCH_DEPTH \ + CY_UTILS_SEARCH_DEPTH CY_EXTRA_INCLUDES TOOLCHAIN_MK_PATH +CY_HELP_PRINT_ALL=$(CY_HELP_TARGETS_ALL) $(CY_HELP_BASIC_CFG_ALL) $(CY_HELP_ADVANCED_CFG_ALL) $(CY_HELP_PATHS_ALL) $(CY_HELP_MISC_ALL) + + +help_default: +ifneq ($(CY_HELP),) + @echo + $(foreach topic,$(CY_HELP),\ + $(info $(CY_NEWLINE)Topic-specific help for "$(topic)")\ + $(info $(CY_SPACE)$(CY_SPACE)Brief: $(CY_HELP_$(topic)))\ + $(info $(CY_SPACE)$(CY_SPACE)Verbose: $(CY_HELP_$(topic)_VERBOSE))) +else + @echo + $(info ) + $(info ============================================================================== ) + $(info $(CY_SPACE)Cypress Build System ) + $(info ============================================================================== ) + $(info $(CY_SPACE)Copyright 2018-2019 Cypress Semiconductor Corporation ) + $(info $(CY_SPACE)SPDX-License-Identifier: Apache-2.0 ) + $(info ) + $(info $(CY_SPACE)Licensed under the Apache License, Version 2.0 (the "License"); ) + $(info $(CY_SPACE)you may not use this file except in compliance with the License. ) + $(info $(CY_SPACE)You may obtain a copy of the License at ) + $(info ) + $(info $(CY_SPACE)$(CY_SPACE) http://www.apache.org/licenses/LICENSE-2.0 ) + $(info ) + $(info $(CY_SPACE)Unless required by applicable law or agreed to in writing, software ) + $(info $(CY_SPACE)distributed under the License is distributed on an "AS IS" BASIS, ) + $(info $(CY_SPACE)WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.) + $(info $(CY_SPACE)See the License for the specific language governing permissions and ) + $(info $(CY_SPACE)limitations under the License. ) + $(info ============================================================================== ) + $(info ) + $(info $(CY_SPACE)This is the help documentation for the Cypress build system. ) + $(info $(CY_SPACE)It lists the supported make targets and make variables. ) + $(info ) + $(info $(CY_SPACE)Usage: make [target][variable] ) + $(info $(CY_SPACE)Example: make help CY_HELP=TOOLCHAIN ) + $(info ) + $(info ======================================= ) + $(info $(CY_SPACE)General make targets ) + $(info ======================================= ) + $(info $(CY_SPACE)all $(CY_HELP_all)) + $(info $(CY_SPACE)getlibs $(CY_HELP_getlibs)) + $(info $(CY_SPACE)build $(CY_HELP_build)) + $(info $(CY_SPACE)qbuild $(CY_HELP_qbuild)) + $(info $(CY_SPACE)program $(CY_HELP_program)) + $(info $(CY_SPACE)qprogram $(CY_HELP_qprogram)) + $(info $(CY_SPACE)debug $(CY_HELP_debug)) + $(info $(CY_SPACE)qdebug $(CY_HELP_qdebug)) + $(info $(CY_SPACE)clean $(CY_HELP_clean)) + $(info $(CY_SPACE)help $(CY_HELP_help)) + $(info ) + $(info ======================================= ) + $(info $(CY_SPACE)Tools make targets ) + $(info ======================================= ) + $(info $(CY_SPACE)open $(CY_HELP_open)) + $(info $(CY_SPACE)config $(CY_HELP_config)) + $(info $(CY_SPACE)config_bt $(CY_HELP_config_bt)) + $(info $(CY_SPACE)config_usbdev $(CY_HELP_config_usbdev)) + $(info ) + $(info ======================================= ) + $(info $(CY_SPACE)Utility make targets ) + $(info ======================================= ) + $(info $(CY_SPACE)eclipse $(CY_HELP_eclipse)) + $(info $(CY_SPACE)check $(CY_HELP_check)) + $(info $(CY_SPACE)get_app_info $(CY_HELP_get_app_info)) + $(info $(CY_SPACE)get_env_info $(CY_HELP_get_env_info)) + $(info $(CY_SPACE)printlibs $(CY_HELP_printlibs)) + $(info ) + $(info ======================================= ) + $(info $(CY_SPACE)Basic configuration make variables ) + $(info ======================================= ) + $(info $(CY_SPACE)TARGET $(CY_HELP_TARGET)) + $(info $(CY_SPACE)APPNAME $(CY_HELP_APPNAME)) + $(info $(CY_SPACE)LIBNAME $(CY_HELP_LIBNAME)) + $(info $(CY_SPACE)TOOLCHAIN $(CY_HELP_TOOLCHAIN)) + $(info $(CY_SPACE)CONFIG $(CY_HELP_CONFIG)) + $(info $(CY_SPACE)VERBOSE $(CY_HELP_VERBOSE)) + $(info ) + $(info ======================================= ) + $(info $(CY_SPACE)Advanced configuration make variables ) + $(info ======================================= ) + $(info $(CY_SPACE)SOURCES $(CY_HELP_SOURCES)) + $(info $(CY_SPACE)INCLUDES $(CY_HELP_INCLUDES)) + $(info $(CY_SPACE)DEFINES $(CY_HELP_DEFINES)) + $(info $(CY_SPACE)VFP_SELECT $(CY_HELP_VFP_SELECT)) + $(info $(CY_SPACE)CFLAGS $(CY_HELP_CFLAGS)) + $(info $(CY_SPACE)CXXFLAGS $(CY_HELP_CXXFLAGS)) + $(info $(CY_SPACE)ASFLAGS $(CY_HELP_ASFLAGS)) + $(info $(CY_SPACE)LDFLAGS $(CY_HELP_LDFLAGS)) + $(info $(CY_SPACE)LDLIBS $(CY_HELP_LDLIBS)) + $(info $(CY_SPACE)LINKER_SCRIPT $(CY_HELP_LINKER_SCRIPT)) + $(info $(CY_SPACE)PREBUILD $(CY_HELP_PREBUILD)) + $(info $(CY_SPACE)POSTBUILD $(CY_HELP_POSTBUILD)) + $(info $(CY_SPACE)COMPONENTS $(CY_HELP_COMPONENTS)) + $(info $(CY_SPACE)DISABLE_COMPONENTS $(CY_HELP_DISABLE_COMPONENTS)) + $(info $(CY_SPACE)SEARCH_LIBS_AND_INCLUDES $(CY_HELP_SEARCH_LIBS_AND_INCLUDES)) + $(info ) + $(info ======================================= ) + $(info $(CY_SPACE)Path make variables ) + $(info ======================================= ) + $(info $(CY_SPACE)CY_APP_PATH $(CY_HELP_CY_APP_PATH)) + $(info $(CY_SPACE)CY_BASELIB_PATH $(CY_HELP_CY_BASELIB_PATH)) + $(info $(CY_SPACE)CY_EXTAPP_PATH $(CY_HELP_CY_EXTAPP_PATH)) + $(info $(CY_SPACE)CY_GETLIBS_PATH $(CY_HELP_CY_GETLIBS_PATH)) + $(info $(CY_SPACE)CY_GETLIBS_SEARCH_PATH $(CY_HELP_CY_GETLIBS_SEARCH_PATH)) + $(info $(CY_SPACE)CY_DEVICESUPPORT_PATH $(CY_HELP_CY_DEVICESUPPORT_PATH)) + $(info $(CY_SPACE)CY_SHARED_PATH $(CY_HELP_CY_SHARED_PATH)) + $(info $(CY_SPACE)CY_COMPILER_PATH $(CY_HELP_CY_COMPILER_PATH)) + $(info $(CY_SPACE)CY_TOOLS_DIR $(CY_HELP_CY_TOOLS_DIR)) + $(info $(CY_SPACE)CY_BUILD_LOCATION $(CY_HELP_CY_BUILD_LOCATION)) + $(info ) + $(info ======================================= ) + $(info $(CY_SPACE)Miscellaneous make variables ) + $(info ======================================= ) + $(info $(CY_SPACE)CY_IGNORE $(CY_HELP_CY_IGNORE)) + $(info $(CY_SPACE)CY_IDE_PRJNAME $(CY_HELP_CY_IDE_PRJNAME)) + $(info $(CY_SPACE)CY_CONFIG_FILE_EXT $(CY_HELP_CY_CONFIG_FILE_EXT)) + $(info $(CY_SPACE)CY_SKIP_RECIPE $(CY_HELP_CY_SKIP_RECIPE)) + $(info $(CY_SPACE)CY_SUPPORTED_TOOL_TYPES $(CY_HELP_CY_SUPPORTED_TOOL_TYPES)) + $(info $(CY_SPACE)CY_LIBS_SEARCH_DEPTH $(CY_HELP_CY_LIBS_SEARCH_DEPTH)) + $(info $(CY_SPACE)CY_UTILS_SEARCH_DEPTH $(CY_HELP_CY_UTILS_SEARCH_DEPTH)) + $(info $(CY_SPACE)CY_EXTRA_INCLUDES $(CY_HELP_CY_EXTRA_INCLUDES)) + $(info $(CY_SPACE)TOOLCHAIN_MK_PATH $(CY_HELP_TOOLCHAIN_MK_PATH)) +endif + +# +# Identify the phony targets +# +.PHONY: help help_default diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/main.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/main.mk new file mode 100644 index 0000000000000000000000000000000000000000..3defc841a91dd994c1a50c4b3ec4b531a4e84aed --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/main.mk @@ -0,0 +1,317 @@ +################################################################################ +# \file main.mk +# \version 1.0 +# +# \brief +# Defines the public facing build targets common to all recipes and includes +# the core makefiles. +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + + +################################################################################ +# Paths +################################################################################ + +# +# Set the build location. Append app dir if CY_BUILD_LOCATION is defined +# +ifneq ($(CY_BUILD_LOCATION),) +CY_BUILD_LOC=$(CY_BUILD_LOCATION)/$(notdir $(CY_APP_LOCATION)) +else +CY_BUILD_LOC=$(CY_APP_LOCATION)/build +endif + +# +# Windows paths +# +ifeq ($(OS),Windows_NT) + +# +# CygWin/MSYS +# +ifneq ($(CY_WHICH_CYGPATH),) +CY_INTERNAL_BUILD_LOC:=$(shell cygpath -m --absolute $(subst \,/,$(CY_BUILD_LOC))) +ifneq ($(CY_BUILD_LOCATION),) +CY_INTERNAL_BUILD_LOCATION:=$(shell cygpath -m --absolute $(subst \,/,$(CY_BUILD_LOCATION))) +endif +ifneq ($(CY_DEVICESUPPORT_PATH),) +CY_INTERNAL_DEVICESUPPORT_PATH:=$(shell cygpath -m --absolute $(subst \,/,$(CY_DEVICESUPPORT_PATH))) +endif + +# +# Other Windows environments +# +else +CY_INTERNAL_BUILD_LOC:=$(subst \,/,$(CY_BUILD_LOC)) +CY_INTERNAL_BUILD_LOCATION:=$(subst \,/,$(CY_BUILD_LOCATION)) +CY_INTERNAL_DEVICESUPPORT_PATH:=$(abspath $(subst \,/,$(CY_DEVICESUPPORT_PATH))) +endif + +# +# Linux and macOS paths +# +else +CY_INTERNAL_BUILD_LOC:=$(CY_BUILD_LOC) +CY_INTERNAL_BUILD_LOCATION:=$(CY_BUILD_LOCATION) +CY_INTERNAL_DEVICESUPPORT_PATH:=$(abspath $(CY_DEVICESUPPORT_PATH)) +endif + +# +# Build directories +# +CY_RECIPE_DIR=$(CY_INTERNAL_BUILD_LOC) +CY_BUILDTARGET_DIR=$(CY_RECIPE_DIR)/$(TARGET) +CY_CONFIG_DIR=$(CY_BUILDTARGET_DIR)/$(CONFIG) +CY_GENERATED_DIR=$(CY_BUILDTARGET_DIR)/generated + +# +# Default toolchain locations +# +CY_COMPILER_GCC_ARM_DEFAULT_DIR=$(CY_COMPILER_DEFAULT_DIR) +CY_COMPILER_IAR_DEFAULT_DIR="C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.2/arm" +CY_COMPILER_ARM_DEFAULT_DIR="C:/Program Files/ARMCompiler6.11" +CY_COMPILER_A_Clang_DEFAULT_DIR=/Library/Developer/CommandLineTools/usr/lib/clang/10.0.0 + +# +# Toolchain locations +# +CY_COMPILER_GCC_ARM_DIR?=$(CY_COMPILER_GCC_ARM_DEFAULT_DIR) +CY_COMPILER_IAR_DIR?=$(CY_COMPILER_IAR_DEFAULT_DIR) +CY_COMPILER_ARM_DIR?=$(CY_COMPILER_ARM_DEFAULT_DIR) +CY_COMPILER_A_Clang_DIR?=$(CY_COMPILER_A_Clang_DEFAULT_DIR) + + +################################################################################ +# User-facing make targets +################################################################################ + +CY_HELP_all=Same as build. i.e. Builds the application. +all: build + +CY_HELP_getlibs=Clones the repositories, and checks out the identified commit. +getlibs: + +CY_HELP_build=Builds the application. +build: app memcalc + +CY_HELP_qbuild=Builds the application using the previous build's source list. +qbuild: app memcalc + +CY_HELP_program=Builds the application and programs it to the target device. +program: + +CY_HELP_qprogram=Programs a built application to the target device without rebuilding. +qprogram: + +CY_HELP_debug=Builds and programs. Then launches a GDB server. +debug: + +CY_HELP_qdebug=Skips the build and program step. Launches a GDB server. +qdebug: + +CY_HELP_clean=Cleans the /build/ directory. +clean: shared_libs + rm -rf $(CY_BUILDTARGET_DIR) + +# Note: Define the help target in BSP/recipe for custom help +CY_HELP_help=Prints the help documentation. +help: help_default + +CY_HELP_open=Opens/launches a specified tool. +open: + +CY_HELP_config=Runs the configurator on the target .modus file. +config: + +CY_HELP_config_bt=Runs the bt-configurator on the target .cybt file. +config_bt: + +CY_HELP_config_usbdev=Runs the usbdev-configurator on the target .cyusbdev file. +config_usbdev: + + +################################################################################ +# Include make files +################################################################################ + +# Make a decision on including logic pertinent to builds. +# If it's not any of these targets, then it's an actual build. +CY_COMMENCE_BUILD=false +ifneq ($(findstring clean,$(MAKECMDGOALS)),clean) +ifneq ($(findstring qprogram,$(MAKECMDGOALS)),qprogram) +ifneq ($(findstring qdebug,$(MAKECMDGOALS)),qdebug) +ifneq ($(findstring erase,$(MAKECMDGOALS)),erase) +ifneq ($(findstring attach,$(MAKECMDGOALS)),attach) +ifneq ($(findstring eclipse,$(MAKECMDGOALS)),eclipse) +ifneq ($(findstring check,$(MAKECMDGOALS)),check) +ifneq ($(findstring get_env_info,$(MAKECMDGOALS)),get_env_info) +ifneq ($(findstring get_app_info,$(MAKECMDGOALS)),get_app_info) +ifneq ($(findstring help,$(MAKECMDGOALS)),help) +# Note: covers config config_bt and config_usbdev +ifneq ($(findstring config,$(MAKECMDGOALS)),config) +ifneq ($(findstring open,$(MAKECMDGOALS)),open) +CY_COMMENCE_BUILD=true +endif +endif +endif +endif +endif +endif +endif +endif +endif +endif +endif +endif + +ifeq ($(CY_COMMENCE_BUILD),true) +$(info ) +$(info Initializing build: $(APPNAME)$(LIBNAME) $(CONFIG) $(TARGET) $(TOOLCHAIN)) +ifeq ($(wildcard $(CY_INTERNAL_BASELIB_PATH)),) +$(info ) +$(error Cannot find the base library. Run "make getlibs" and/or check\ +that the library location is correct in the CY_BASELIB_PATH variable) +endif +endif + +# +# Include utilities used by all make files +# +include $(CY_BASELIB_CORE_PATH)/make/core/utils.mk + +# +# Include any extra makefiles defined by app +# +include $(CY_EXTRA_INCLUDES) + +# +# Find the target and check that the device is valid +# +include $(CY_BASELIB_CORE_PATH)/make/core/target.mk +-include $(CY_INTERNAL_BASELIB_PATH)/make/udd/features.mk +include $(CY_INTERNAL_BASELIB_PATH)/make/recipe/defines.mk + +# +# Check if the user-data is correct +# +ifneq ($(APPNAME),) +ifneq ($(LIBNAME),) +$(error An application cannot define both APPNAME and LIBNAME. Define one or the other) +endif +endif +ifneq ($(findstring -I,$(INCLUDES)),) +$(error INCLUDES must be directories without -I prepended) +endif +ifneq ($(findstring -D,$(DEFINES)),) +$(error DEFINES must be specified without -D prepended) +endif +ifneq ($(findstring -I,$(CFLAGS)),) +$(error Include paths must be specified in the INCLUDES variable instead\ +of directly in CFLAGS. These must be directories without -I prepended) +endif +ifneq ($(findstring -D,$(CFLAGS)),) +$(error Defines must be specified in the DEFINES variable instead\ +of directly in CFLAGS. These must be specified without -D prepended) +endif +ifneq ($(findstring -I,$(CXXFLAGS)),) +$(error Include paths must be specified in the INCLUDES variable instead\ +of directly in CXXFLAGS. These must be directories without -I prepended) +endif +ifneq ($(findstring -D,$(CXXFLAGS)),) +$(error Defines must be specified in the DEFINES variable instead\ +of directly in CXXFLAGS. These must be specified without -D prepended) +endif +ifneq ($(findstring -I,$(ASFLAGS)),) +$(error Include paths must be specified in the INCLUDES variable instead\ +of directly in ASFLAGS. These must be directories without -I prepended) +endif +ifneq ($(findstring -D,$(ASFLAGS)),) +$(error Defines must be specified in the DEFINES variable instead\ +of directly in ASFLAGS. These must be specified without -D prepended) +endif + +# +# Choose local or default toolchain makefile +# +ifeq ($(TOOLCHAIN_MK_PATH),) +include $(CY_INTERNAL_BASELIB_PATH)/make/toolchains/$(TOOLCHAIN).mk +else +# Include the custom app-specific toolchain file +include $(TOOLCHAIN_MK_PATH) +endif + +# +# Configurator-related routines +# +ifeq ($(CY_SKIP_CONFIGURATOR),) +include $(CY_BASELIB_CORE_PATH)/make/core/config.mk +endif + +# +# Build-related routines +# +ifeq ($(CY_COMMENCE_BUILD),true) + +ifneq ($(findstring qbuild,$(MAKECMDGOALS)),qbuild) +include $(CY_BASELIB_CORE_PATH)/make/core/search.mk +else +# Skip the auto-discovery and re-use the last build's source list +-include $(CY_CONFIG_DIR)/cyqbuild.mk +CY_QBUILD=$(shell if [ -f $(CY_CONFIG_DIR)/cyqbuild.mk ]; then echo "true"; fi;) +ifneq ($(CY_QBUILD),true) +$(info WARNING: Cannot find the auto-discovery make file. Run "make build" to generate it.) +endif +endif + +include $(CY_INTERNAL_BASELIB_PATH)/make/recipe/recipe.mk + +ifneq ($(findstring vscode,$(MAKECMDGOALS)),vscode) +include $(CY_BASELIB_CORE_PATH)/make/core/build.mk +endif + +endif + +# +# Optional recipe-specific program routine +# +ifndef CY_BSP_PROGRAM +-include $(CY_INTERNAL_BASELIB_PATH)/make/recipe/program.mk +endif + +# +# Launch tools +# +-include $(CY_INTERNAL_TOOLS)/make/tools.mk +include $(CY_BASELIB_CORE_PATH)/make/core/open.mk + +# +# Help documentation +# +include $(CY_BASELIB_CORE_PATH)/make/core/help.mk + +# +# Identify the phony targets +# +.PHONY: all build qbuild getlibs clean program quickprogram help +.PHONY: app memcalc diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/open.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/open.mk new file mode 100644 index 0000000000000000000000000000000000000000..6be2460f2dabee2b4097cbbd1bd63dd790fcf3be --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/open.mk @@ -0,0 +1,126 @@ +################################################################################ +# \file open.mk +# \version 1.0 +# +# \brief +# Opens/launches a specified tool +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + + +# Verify that the tool is supported +ifneq ($(CY_OPEN_TYPE),) +ifeq ($(filter $(CY_OPEN_TYPE),$(CY_OPEN_TYPE_LIST)),) +$(error Unsupported tool type - $(CY_OPEN_TYPE). $(CY_NEWLINE)Supported types are: $(CY_OPEN_TYPE_LIST)) +endif +endif + +# Extension construction from given file +ifneq ($(CY_OPEN_FILE)),) +CY_OPEN_EXT=$(subst .,,$(suffix $(CY_OPEN_FILE))) +endif + + +################################################################################ +# New configurations +################################################################################ + +# Limit this as it can be a performance hit +ifneq ($(filter get_app_info open,$(MAKECMDGOALS)),) + +# Look for tools that DISALLOW new configurations +CY_OPEN_NEWCFG_XML_TYPES+=$(shell \ + xmlFileArray=($$(find $(CY_INTERNAL_TOOLS) -maxdepth 2 -name "configurator.xml" \ + -exec grep "false" {} +));\ + for xmlFile in "$${xmlFileArray[@]}"; do\ + if [[ "$$xmlFile" == *"configurator.xml"* ]]; then\ + toolNameDir="$${xmlFile%/*}";\ + toolName="$${toolNameDir\#\#*/}";\ + echo "$$toolName";\ + fi;\ + done;\ +) + +endif + +# Tools for existing files +CY_OPEN_NEWCFG_EXISTING_TYPES=$(foreach ext,$(subst .,,$(suffix $(CY_CONFIG_FILES))),$($(addsuffix _DEFAULT_TYPE,$(ext)))) +# Tools that do not have an existing file +CY_OPEN_NEWCFG_POSSIBLE_TYPES=$(filter-out $(CY_OPEN_NEWCFG_EXISTING_TYPES) $(CY_OPEN_NEWCFG_XML_TYPES),$(CY_SUPPORTED_TOOL_TYPES)) +# Complete list of supported files +CY_OPEN_FILTERED_SUPPORTED_TYPES=$(sort $(CY_OPEN_NEWCFG_POSSIBLE_TYPES) $(CY_OPEN_NEWCFG_EXISTING_TYPES)) + + +################################################################################ +# Prepare tool launch +################################################################################ + +# Only file is given. Use the default type for that file extension +ifneq ($(CY_OPEN_FILE),) +ifeq ($(CY_OPEN_TYPE),) +CY_OPEN_TYPE=$(firstword $($(CY_OPEN_EXT)_DEFAULT_TYPE)) +endif +endif + +# Set the tool and its arguments +CY_OPEN_TOOL_FILE=$(CY_OPEN_$(subst -,_,$(CY_OPEN_TYPE))_FILE) +CY_OPEN_TOOL_LAUNCH=$(CY_OPEN_$(subst -,_,$(CY_OPEN_TYPE))_TOOL) +CY_OPEN_TOOL_FLAGS=$(CY_OPEN_$(subst -,_,$(CY_OPEN_TYPE))_TOOL_FLAGS) +CY_OPEN_TOOL_ARGS=$(CY_OPEN_$(subst -,_,$(CY_OPEN_TYPE))_TOOL_ARGS) +CY_OPEN_TOOL_NEWCFG_FLAGS=$(CY_OPEN_$(subst -,_,$(CY_OPEN_TYPE))_TOOL_NEWCFG_FLAGS) + +# Use the file if provided +ifneq ($(CY_OPEN_FILE),) +CY_OPEN_TOOL_FILE=$(CY_OPEN_FILE) +endif + +ifneq ($(CY_MAKE_IDE),) +CY_OPEN_STDOUT=>& /dev/null +endif + + +################################################################################ +# Tool launch target +################################################################################ + +open: +ifeq ($(CY_OPEN_FILE),) +ifeq ($(CY_OPEN_TYPE),) + $(error Neither tool type or file specified to launch a tool) +endif +endif +ifeq ($(CY_OPEN_TOOL_LAUNCH),) + $(error Unable to find a default tool to launch .$(CY_OPEN_EXT) file extension) +endif +ifeq ($(CY_OPEN_TOOL_FILE),) + $(info Launching $(notdir $(CY_OPEN_TOOL_LAUNCH)) tool for a new configuration) + $(CY_NOISE) $(CY_OPEN_TOOL_LAUNCH) $(CY_OPEN_TOOL_ARGS) $(CY_OPEN_TOOL_NEWCFG_FLAGS) $(CY_OPEN_STDOUT) & +else + $(info $(CY_NEWLINE)Launching $(notdir $(CY_OPEN_TOOL_LAUNCH)) tool on $(CY_OPEN_TOOL_FILE)) + $(CY_NOISE) $(CY_OPEN_TOOL_LAUNCH) $(CY_OPEN_TOOL_ARGS) $(CY_OPEN_TOOL_FLAGS) $(CY_OPEN_TOOL_FILE) $(CY_OPEN_STDOUT) & +endif + +# +# Identify the phony targets +# +.PHONY: open diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/search.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/search.mk new file mode 100644 index 0000000000000000000000000000000000000000..5e11ec073bb467066e24a74b2a238e73a4dc0de1 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/search.mk @@ -0,0 +1,158 @@ +################################################################################ +# \file search.mk +# \version 1.0 +# +# \brief +# Performs auto-discovery of files in the project directories. +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + + +################################################################################ +# Search Files +################################################################################ + +$(info ) +$(info Auto-discovery in progress...) + +# +# Search for files. Use := assignment for better performance. Need to look in both project and shared lib. +# +CY_SEARCH_ALL_FILES:=$(sort $(shell $(CY_FIND) -L $(CY_INTERNAL_APP_PATH) $(CY_INTERNAL_EXTAPP_PATH) \ + \( $(CY_IGNORE_PRUNE) \) -prune \ + -o -type f -name "*.$(CY_TOOLCHAIN_SUFFIX_C)" -print \ + -o -type f -name "*.$(CY_TOOLCHAIN_SUFFIX_S)" -print \ + -o -type f -name "*.$(CY_TOOLCHAIN_SUFFIX_s)" -print \ + -o -type f -name "*.$(CY_TOOLCHAIN_SUFFIX_CPP)" -print \ + -o -type f -name "*.$(CY_TOOLCHAIN_SUFFIX_O)" -print \ + -o -type f -name "*.$(CY_TOOLCHAIN_SUFFIX_A)" -print \ + -o -type f -name "*.$(CY_TOOLCHAIN_SUFFIX_H)" -print \ + -o -type f -name "*.$(CY_TOOLCHAIN_SUFFIX_HPP)" -print \ + -o -type d -name "COMPONENT_RESOURCE" -print \ + -o -type d -name "* *" -print)) + +CY_SEARCH_C_FILES=$(filter %.$(CY_TOOLCHAIN_SUFFIX_C),$(CY_SEARCH_ALL_FILES)) +CY_SEARCH_S_FILES=$(filter %.$(CY_TOOLCHAIN_SUFFIX_S),$(CY_SEARCH_ALL_FILES)) +CY_SEARCH_s_FILES=$(filter %.$(CY_TOOLCHAIN_SUFFIX_s),$(CY_SEARCH_ALL_FILES)) +CY_SEARCH_CPP_FILES=$(filter %.$(CY_TOOLCHAIN_SUFFIX_CPP),$(CY_SEARCH_ALL_FILES)) +CY_SEARCH_O_FILES=$(filter %.$(CY_TOOLCHAIN_SUFFIX_O),$(CY_SEARCH_ALL_FILES)) +CY_SEARCH_A_FILES=$(filter %.$(CY_TOOLCHAIN_SUFFIX_A),$(CY_SEARCH_ALL_FILES)) +CY_SEARCH_H_FILES=$(filter %.$(CY_TOOLCHAIN_SUFFIX_H),$(CY_SEARCH_ALL_FILES)) +CY_SEARCH_HPP_FILES=$(filter %.$(CY_TOOLCHAIN_SUFFIX_HPP),$(CY_SEARCH_ALL_FILES)) + +# +# Search for resource directories and gather the files +# +CY_SEARCH_RESOURCE_DIR=$(filter %/COMPONENT_RESOURCE,$(CY_SEARCH_ALL_FILES)) +CY_SEARCH_RESOURCE_FILES=$(foreach dir,$(CY_SEARCH_RESOURCE_DIR),$(wildcard $(dir)/*)) + +# +# Check that the directories do not contain spaces +# +CY_SEARCH_EMPTY_DIRS=$(filter-out $(CY_SEARCH_C_FILES) $(CY_SEARCH_S_FILES) $(CY_SEARCH_s_FILES) $(CY_SEARCH_CPP_FILES)\ + $(CY_SEARCH_O_FILES) $(CY_SEARCH_A_FILES) $(CY_SEARCH_H_FILES) $(CY_SEARCH_HPP_FILES)\ + $(CY_SEARCH_RESOURCE_DIR),$(CY_SEARCH_ALL_FILES)) + +# +# Print the number of discovered files +# +ifneq ($(CY_SEARCH_EMPTY_DIRS),) +$(error The application must not contain spaces in the paths. Detected dir(s): $(CY_SEARCH_EMPTY_DIRS)) +else +$(info -> Found $(words $(CY_SEARCH_C_FILES)) .$(CY_TOOLCHAIN_SUFFIX_C) file(s)) +$(info -> Found $(words $(CY_SEARCH_S_FILES)) .$(CY_TOOLCHAIN_SUFFIX_S) file(s)) +$(info -> Found $(words $(CY_SEARCH_s_FILES)) .$(CY_TOOLCHAIN_SUFFIX_s) file(s)) +$(info -> Found $(words $(CY_SEARCH_CPP_FILES)) .$(CY_TOOLCHAIN_SUFFIX_CPP) file(s)) +$(info -> Found $(words $(CY_SEARCH_O_FILES)) .$(CY_TOOLCHAIN_SUFFIX_O) file(s)) +$(info -> Found $(words $(CY_SEARCH_A_FILES)) .$(CY_TOOLCHAIN_SUFFIX_A) file(s)) +$(info -> Found $(words $(CY_SEARCH_H_FILES)) .$(CY_TOOLCHAIN_SUFFIX_H) file(s)) +$(info -> Found $(words $(CY_SEARCH_HPP_FILES)) .$(CY_TOOLCHAIN_SUFFIX_HPP) file(s)) +$(info -> Found $(words $(CY_SEARCH_RESOURCE_FILES)) resource file(s)) +endif + + +################################################################################ +# Filter lists +################################################################################ + +$(info Applying filters...) + +# +# Apply the filtering for files in .cyignore +# +CY_SEARCH_PRUNED_C_FILES:=$(filter-out $(foreach d,$(CY_IGNORE_FILES),$(filter $(d)%,$(CY_SEARCH_C_FILES))),$(CY_SEARCH_C_FILES)) +CY_SEARCH_PRUNED_S_FILES:=$(filter-out $(foreach d,$(CY_IGNORE_FILES),$(filter $(d)%,$(CY_SEARCH_S_FILES))),$(CY_SEARCH_S_FILES)) +CY_SEARCH_PRUNED_s_FILES:=$(filter-out $(foreach d,$(CY_IGNORE_FILES),$(filter $(d)%,$(CY_SEARCH_s_FILES))),$(CY_SEARCH_s_FILES)) +CY_SEARCH_PRUNED_CPP_FILES:=$(filter-out $(foreach d,$(CY_IGNORE_FILES),$(filter $(d)%,$(CY_SEARCH_CPP_FILES))),$(CY_SEARCH_CPP_FILES)) +CY_SEARCH_PRUNED_O_FILES:=$(filter-out $(foreach d,$(CY_IGNORE_FILES),$(filter $(d)%,$(CY_SEARCH_O_FILES))),$(CY_SEARCH_O_FILES)) +CY_SEARCH_PRUNED_A_FILES:=$(filter-out $(foreach d,$(CY_IGNORE_FILES),$(filter $(d)%,$(CY_SEARCH_A_FILES))),$(CY_SEARCH_A_FILES)) +CY_SEARCH_PRUNED_H_FILES:=$(filter-out $(foreach d,$(CY_IGNORE_FILES),$(filter $(d)%,$(CY_SEARCH_H_FILES))),$(CY_SEARCH_H_FILES)) +CY_SEARCH_PRUNED_HPP_FILES:=$(filter-out $(foreach d,$(CY_IGNORE_FILES),$(filter $(d)%,$(CY_SEARCH_HPP_FILES))),$(CY_SEARCH_HPP_FILES)) + +# +# Apply the COMPONENT and configuration filtering +# +CY_SEARCH_AVAILABLE_C_SOURCES=$(call CY_MACRO_FILTER_FILES,C) +CY_SEARCH_AVAILABLE_S_SOURCES=$(call CY_MACRO_FILTER_FILES,S) +CY_SEARCH_AVAILABLE_s_SOURCES=$(call CY_MACRO_FILTER_FILES,s) +CY_SEARCH_AVAILABLE_CPP_SOURCES=$(call CY_MACRO_FILTER_FILES,CPP) +CY_SEARCH_AVAILABLE_O_SOURCES=$(call CY_MACRO_FILTER_FILES,O) +CY_SEARCH_AVAILABLE_A_LIBS=$(call CY_MACRO_FILTER_FILES,A) + +CY_SEARCH_AVAILABLE_H_INCLUDES=$(sort $(call CY_MACRO_DIR,$(call CY_MACRO_FILTER_FILES,H))) +CY_SEARCH_AVAILABLE_HPP_INCLUDES=$(sort $(call CY_MACRO_DIR,$(call CY_MACRO_FILTER_FILES,HPP))) + +# +# Combine the directories of the header files and its parent directories +# +CY_SEARCH_AVAILABLE_INCLUDES=\ + $(CY_SEARCH_AVAILABLE_H_INCLUDES)\ + $(call CY_MACRO_SEARCH_PARENT,$(CY_SEARCH_AVAILABLE_H_INCLUDES))\ + $(CY_SEARCH_AVAILABLE_HPP_INCLUDES)\ + $(call CY_MACRO_SEARCH_PARENT,$(CY_SEARCH_AVAILABLE_HPP_INCLUDES))\ + +# Conditionally add the generated source includes +ifneq ($(CY_SEARCH_RESOURCE_FILES),) +CY_SEARCH_AVAILABLE_INCLUDES+=$(CY_GENERATED_DIR) +endif + +# +# Add to the list +# +CY_SEARCH_APP_SOURCE=$(sort $(CY_SEARCH_AVAILABLE_S_SOURCES) $(CY_SEARCH_AVAILABLE_s_SOURCES)\ + $(CY_SEARCH_AVAILABLE_C_SOURCES) $(CY_SEARCH_AVAILABLE_CPP_SOURCES)) +CY_SEARCH_APP_LIBS=$(sort $(CY_SEARCH_AVAILABLE_O_SOURCES) $(CY_SEARCH_AVAILABLE_A_LIBS)) +CY_SEARCH_APP_INCLUDES=$(sort $(CY_SEARCH_AVAILABLE_INCLUDES)) + +# +# Create cyqbuild makefile +# +$(shell \ +mkdir -p $(CY_CONFIG_DIR); \ +echo "CY_COMPONENT_LIST:=$(CY_COMPONENT_LIST)" > $(CY_CONFIG_DIR)/cyqbuild.mk; \ +echo "CY_SEARCH_APP_SOURCE:=$(CY_SEARCH_APP_SOURCE)" >> $(CY_CONFIG_DIR)/cyqbuild.mk; \ +echo "CY_SEARCH_APP_LIBS:=$(CY_SEARCH_APP_LIBS)" >> $(CY_CONFIG_DIR)/cyqbuild.mk; \ +echo "CY_SEARCH_APP_INCLUDES:=$(CY_SEARCH_APP_INCLUDES)" >> $(CY_CONFIG_DIR)/cyqbuild.mk; \ +) + +$(info Auto-discovery complete) diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/target.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/target.mk new file mode 100644 index 0000000000000000000000000000000000000000..5c005cc1c05f34ef619e8666f4c6a0d825724bf1 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/target.mk @@ -0,0 +1,79 @@ +################################################################################ +# \file target.mk +# \version 1.0 +# +# \brief +# Finds available targets in the design. +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + + +# +# Search for target make files and BSPs. Use := assignment for better performance. +# +CY_TARGET_MAKEFILE_SEARCH:=$(call CY_MACRO_SEARCH,$(TARGET).mk,$(CY_INTERNAL_APP_PATH))\ + $(if $(CY_INTERNAL_EXTAPP_PATH),$(call CY_MACRO_SEARCH,$(TARGET).mk,$(CY_INTERNAL_EXTAPP_PATH)))\ + $(if $(SEARCH_LIBS_AND_INCLUDES),$(foreach d,$(SEARCH_LIBS_AND_INCLUDES),$(call CY_MACRO_SEARCH,$(TARGET).mk,$(d)))) +CY_TARGET_AVAILABLE_SEARCH:=$(call CY_MACRO_SEARCH,.mk,$(CY_INTERNAL_APP_PATH))\ + $(if $(CY_INTERNAL_EXTAPP_PATH),$(call CY_MACRO_SEARCH,.mk,$(CY_INTERNAL_EXTAPP_PATH)))\ + $(if $(SEARCH_LIBS_AND_INCLUDES),$(foreach d,$(SEARCH_LIBS_AND_INCLUDES),$(call CY_MACRO_SEARCH,.mk,$(d))))\ + +# Gather and filter the found files +CY_SEARCH_PRUNED_MAKE_FILES:=$(filter-out $(foreach d,$(CY_IGNORE_DIRS),$(filter $(d)%,$(CY_TARGET_MAKEFILE_SEARCH))),$(CY_TARGET_MAKEFILE_SEARCH)) +CY_SEARCH_PRUNED_AVAILABLEMAKE_FILES:=$(filter-out $(foreach d,$(CY_IGNORE_DIRS),$(filter $(d)%,$(CY_TARGET_AVAILABLE_SEARCH))),$(CY_TARGET_AVAILABLE_SEARCH)) + +# Target makefile +CY_TARGET_MAKEFILE=$(call CY_MACRO_FILTER_FILES,MAKE) + +# Check if the TARGET.mk was brought in through CY_EXTRA_INCLUDES or directly in the app makefile +CY_TARGET_EXTRA_INCLUDES=$(filter %/$(TARGET).mk,$(MAKEFILE_LIST)) +CY_TARGET_EXTRA_FILTERED=$(filter-out $(CY_TARGET_EXTRA_INCLUDES),$(CY_TARGET_MAKEFILE)) + +# Full list of available targets +CY_TARGET_AVAILABLE_DIRS=$(notdir $(call CY_MACRO_DIR,$(CY_SEARCH_PRUNED_AVAILABLEMAKE_FILES) $(CY_TARGET_EXTRA_INCLUDES))) +CY_TARGET_AVAILABLE=$(sort $(subst TARGET_,,$(foreach item,$(CY_TARGET_AVAILABLE_DIRS),$(if $(findstring /TARGET_,/$(item)),$(item),)))) + +# +# Set the target makefile and directory +# +ifneq ($(CY_TARGET_EXTRA_INCLUDES),) + +ifneq ($(CY_TARGET_EXTRA_FILTERED),) +$(call CY_MACRO_ERROR,Found multiple identical targets: $(CY_TARGET_EXTRA_INCLUDES) $(CY_TARGET_EXTRA_FILTERED)) +else +CY_TARGET_DIR=$(call CY_MACRO_DIR,$(CY_TARGET_EXTRA_INCLUDES)) +endif + +else + +ifeq ($(words $(CY_TARGET_MAKEFILE)),0) +$(info Available target(s): $(CY_TARGET_AVAILABLE)) +$(call CY_MACRO_ERROR,Target "$(TARGET)" not found) +else ifeq ($(words $(CY_TARGET_MAKEFILE)),1) +CY_TARGET_DIR=$(call CY_MACRO_DIR,$(CY_TARGET_MAKEFILE)$(CY_TARGET_MAKEFILE_SEARCH_LIBS)) +include $(CY_TARGET_MAKEFILE) $(CY_TARGET_MAKEFILE_SEARCH_LIBS) +else +$(call CY_MACRO_ERROR,Found multiple identical targets:$(CY_TARGET_MAKEFILE)) +endif + +endif diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/utils.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/utils.mk new file mode 100644 index 0000000000000000000000000000000000000000..16b3a6413ad0f5ee0a571899778178507272f9a7 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/core/utils.mk @@ -0,0 +1,358 @@ +################################################################################ +# \file utils.mk +# \version 1.0 +# +# \brief +# Global utilities used across the application recipes and BSPs +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + + +################################################################################ +# Components +################################################################################ + +# +# VFP-specific component +# +ifeq ($(VFP_SELECT),hardfp) +CY_COMPONENT_VFP=HARDFP +else +CY_COMPONENT_VFP=SOFTFP +endif + +# +# Component list +# +CY_COMPONENT_LIST_DEFAULT=$(CORE) $(CY_COMPONENT_VFP) $(COMPONENTS) +# Note: CY_DEFAULT_COMPONENT is needed as DISABLE_COMPONENTS cannot be empty +DISABLE_COMPONENTS+=CY_DEFAULT_COMPONENT +CY_COMPONENT_LIST?=$(sort $(filter-out $(DISABLE_COMPONENTS),$(CY_COMPONENT_LIST_DEFAULT))) + + +################################################################################ +# Utility variables +################################################################################ + +# Create a make variable that contains a space +CY_SPACE= +CY_SPACE+= + +# Create a make variable that contains a soft tab +CY_INDENT=$(CY_SPACE)$(CY_SPACE)$(CY_SPACE)$(CY_SPACE) + +# Create a make variable that contains a line break +define CY_NEWLINE + + +endef + +# Create a make variable that contains a comma +CY_COMMA=, + +# Displays/Hides the build steps +ifneq (,$(filter $(VERBOSE),true 1)) +CY_NOISE= +CY_CMD_TERM= +else +CY_NOISE=@ +CY_CMD_TERM= > /dev/null 2>&1 +endif + +# Set the location of the find utility (Avoid conflict with Windows system32/find.exe) +CY_QUERY_FIND=$(findstring /usr/bin/find,$(shell whereis find)) +ifeq ($(CY_QUERY_FIND),) +CY_FIND=find +else +CY_FIND=/usr/bin/find +endif + +# +# Prints for bypassing TARGET/DEVICE checks +# $(1) : String to print +# +ifeq ($(CY_COMMENCE_BUILD),true) +CY_MACRO_ERROR=$(error $(1)) +else +CY_MACRO_ERROR=$(info WARNING: $(1)) +endif + + +################################################################################ +# Search macros +################################################################################ + +# +# Macros to find all COMPONENTS not listed in the component list. +# Step 1: Find all COMPONENT directories in app +# Step 2: Process the list and get a list of all COMPONENTS +# Step 3: Compare the found COMPONENTS with the expected components list +# +# $(1): List of files of a certain file type +# +CY_MACRO_FIND_COMPONENTS=$(strip $(foreach item,$(1),$(if $(findstring /COMPONENT_,/$(item)),$(item),))) +CY_MACRO_PROCESS_COMPONENTS=\ +$(foreach item,$(1),\ + $(if $(findstring /COMPONENT_,/$(notdir $(item))),$(subst COMPONENT_,,$(notdir $(item))),)\ + $(if $(call CY_MACRO_EQUALITY,$(CY_INTERNAL_APP_PATH),$(item)),,$(call CY_MACRO_PROCESS_COMPONENTS,$(call CY_MACRO_DIR,$(item))))\ +) +CY_MACRO_COMPARE_COMPONENTS=$(filter-out $(CY_COMPONENT_LIST),$(sort $(call CY_MACRO_PROCESS_COMPONENTS,$(call CY_MACRO_FIND_COMPONENTS,$(1))))) + +# +# Filters for components. Iterates through CY_COMPONENT_LIST +# $(1) : List of files of a certain file type +# +CY_MACRO_MATCH_COMPONENT=$(sort $(foreach component,$(2),\ + $(foreach item,$(1),$(if $(findstring /COMPONENT_$(component)/,/$(item)/),$(item),)))) +CY_MACRO_GET_COMPONENT=$(filter-out \ + $(call CY_MACRO_MATCH_COMPONENT,$(1),$(call CY_MACRO_COMPARE_COMPONENTS,$(1))),\ + $(call CY_MACRO_MATCH_COMPONENT,$(1),$(CY_COMPONENT_LIST))) +CY_MACRO_REMOVE_COMPONENT=$(strip $(foreach item,$(1),$(if $(findstring /COMPONENT_,/$(item)),,$(item)))) +CY_MACRO_FILTER_COMPONENT=$(call CY_MACRO_REMOVE_COMPONENT,$(1)) $(call CY_MACRO_GET_COMPONENT,$(1)) + +# +# Filters for configurations +# $(1) : List of files of a certain file type +# $(2) : Filter string +# +CY_MACRO_MATCH_CONFIGURATION=$(strip $(foreach item,$(1),$(if $(findstring $(2),/$(item)/),$(item),))) +CY_MACRO_REMOVE_CONFIGURATION=$(strip $(foreach item,$(1),$(if $(findstring $(2),/$(item)),,$(item)))) +CY_MACRO_FILTER_CONFIGURATION=$(call CY_MACRO_REMOVE_CONFIGURATION,$(1),/$(strip $(2))_)\ + $(call CY_MACRO_MATCH_CONFIGURATION,$(1),/$(strip $(2))_$($(strip $(2)))/) + +# +# Filter for defined components and configurations +# $(1) : List of files of a certain file type +# +CY_MACRO_FILTER=\ + $(strip \ + $(call CY_MACRO_FILTER_COMPONENT,\ + $(call CY_MACRO_FILTER_CONFIGURATION,\ + $(call CY_MACRO_FILTER_CONFIGURATION,\ + $(call CY_MACRO_FILTER_CONFIGURATION,\ + $(1),\ + TOOLCHAIN),\ + TARGET),\ + CONFIG))) + +# +# Search for files +# $(1) : File type +# +CY_MACRO_FILTER_FILES=$(call CY_MACRO_FILTER,$(CY_SEARCH_PRUNED_$(1)_FILES)) + +# +# Test for equality +# $(1) : Base path +# $(2) : Directory containing header file +# +CY_MACRO_EQUALITY=$(if $(and $(findstring $1,$2),$(findstring $2,$1)),TRUE) + +# +# Recursively search for the parent directories up to the project root directory +# $(1) : Directories containing header files +# +CY_MACRO_SEARCH_PARENT=\ +$(foreach item,$(1),\ + $(if $(call CY_MACRO_EQUALITY,.,$(item)),\ + .\ + ,\ + $(call CY_MACRO_DIR,$(item))\ + $(call CY_MACRO_SEARCH_PARENT,$(call CY_MACRO_DIR,$(item)))\ + )\ +) + +# +# Convert to lower case +# $(1) : String to convert to lower case +# +CY_MACRO_LC=$(subst A,a,$(subst B,b,$(subst C,c,$(subst D,d,$(subst E,e,$(subst F,f,$(subst G,g,$(subst \ + H,h,$(subst I,i,$(subst J,j,$(subst K,k,$(subst L,l,$(subst M,m,$(subst N,n,$(subst O,o,$(subst P,p,$(subst \ + Q,q,$(subst R,r,$(subst S,s,$(subst T,t,$(subst U,u,$(subst V,v,$(subst \ + W,w,$(subst X,x,$(subst Y,y,$(subst Z,z,$1)))))))))))))))))))))))))) + +# +# Convert to upper case +# $(1) : String to convert to upper case +# +CY_MACRO_UC=$(subst a,A,$(subst b,B,$(subst c,C,$(subst d,D,$(subst e,E,$(subst f,F,$(subst g,G,$(subst \ + h,H,$(subst i,I,$(subst j,J,$(subst k,K,$(subst l,L,$(subst m,M,$(subst n,N,$(subst o,O,$(subst p,P,$(subst \ + q,Q,$(subst r,R,$(subst s,S,$(subst t,T,$(subst u,U,$(subst v,V,$(subst \ + w,W,$(subst x,X,$(subst y,Y,$(subst z,Z,$1)))))))))))))))))))))))))) + + +################################################################################ +# IDE-specifc targets +################################################################################ + +CY_VSCODE_OUT_PATH=$(CY_INTERNAL_APP_PATH)/.vscode +CY_VSCODE_OUT_TEMPLATE_PATH=$(CY_VSCODE_OUT_PATH)/cytemplates +CY_VSCODE_BACKUP_PATH=$(CY_VSCODE_OUT_PATH)/backup +CY_VSCODE_TEMPLATE_PATH=$(CY_INTERNAL_BASELIB_PATH)/make/scripts/vscode +CY_VSCODE_TEMPFILE=$(CY_CONFIG_DIR)/vscode_launch.temp + +CY_ECLIPSE_OUT_PATH=$(CY_INTERNAL_APP_PATH)/.mtbLaunchConfigs +CY_ECLIPSE_TEMPLATE_PATH=$(CY_INTERNAL_BASELIB_PATH)/make/scripts/eclipse +CY_ECLIPSE_TEMPFILE=$(CY_CONFIG_DIR)/eclipse_launch.temp +CY_ECLIPSE_TEMPLATES_WILDCARD?=* + +ifeq ($(CY_IDE_PRJNAME),) +CY_IDE_PRJNAME=$(APPNAME) +endif + +vscode: +ifeq ($(LIBNAME),) + @mkdir -p $(CY_CONFIG_DIR);\ + mkdir -p $(CY_VSCODE_OUT_TEMPLATE_PATH);\ + mkdir -p $(CY_VSCODE_BACKUP_PATH);\ + echo $(CY_VSCODE_ARGS) > $(CY_VSCODE_TEMPFILE);\ + echo "s|&&JSONINCLUDELIST&&|$(foreach onedef,$(subst -I,,$(CY_RECIPE_INCLUDES)),\"$(onedef)\",)|" >> $(CY_VSCODE_TEMPFILE);\ + echo "s|&&JSONDEFINELIST&&|$(foreach onedef,$(subst -D,,$(CY_RECIPE_DEFINES)),\"$(onedef)\",)|" >> $(CY_VSCODE_TEMPFILE);\ + for json in $(CY_VSCODE_TEMPLATE_PATH)/*; do\ + jsonFile="$${json##*/}";\ + if [[ $$jsonFile == *"c_cpp_properties"* ]] && [[ $$jsonFile != *"c_cpp_properties_$(TOOLCHAIN).json" ]]; then\ + continue;\ + fi;\ + sed -f $(CY_VSCODE_TEMPFILE) $(CY_VSCODE_TEMPLATE_PATH)/$$jsonFile > $(CY_VSCODE_OUT_TEMPLATE_PATH)/$$jsonFile;\ + jsonFiles="$$jsonFiles $$jsonFile";\ + if [ -f $(CY_VSCODE_OUT_PATH)/$$jsonFile ] && [[ $$jsonFile == *"settings.json" ]]; then\ + echo "Modifying existing settings.json file";\ + mv $(CY_VSCODE_OUT_PATH)/$$jsonFile $(CY_VSCODE_BACKUP_PATH)/$$jsonFile;\ + sed \ + -e /cortex-debug\\.armToolchainPath/s%:.*%:\ \"$(CY_COMPILER_DIR)/bin\",% \ + -e /cortex-debug\\.openocdPath/s%:.*%:\ \"$(CY_OPENOCD_DIR)/bin/openocd\",% \ + $(CY_VSCODE_BACKUP_PATH)/$$jsonFile > $(CY_VSCODE_OUT_PATH)/$$jsonFile;\ + else\ + cp $(CY_VSCODE_OUT_TEMPLATE_PATH)/$$jsonFile $(CY_VSCODE_OUT_PATH)/$$jsonFile;\ + fi;\ + done;\ + mv $(CY_VSCODE_OUT_PATH)/c_cpp_properties_$(TOOLCHAIN).json $(CY_VSCODE_OUT_PATH)/c_cpp_properties.json;\ + mv $(CY_VSCODE_OUT_PATH)/openocd.tcl $(CY_INTERNAL_APP_PATH)/openocd.tcl;\ + rm $(CY_VSCODE_TEMPFILE);\ + rm -rf $(CY_VSCODE_OUT_TEMPLATE_PATH);\ + echo;\ + echo Generated Visual Studio Code files: $$jsonFiles;\ + echo;\ + echo WARNING: The vscode target is preliminary... +else + @echo +endif + +CY_HELP_eclipse=Generates eclipse IDE launch configs. +eclipse: +ifeq ($(LIBNAME),) + @mkdir -p $(CY_CONFIG_DIR);\ + mkdir -p $(CY_ECLIPSE_OUT_PATH);\ + echo $(CY_ECLIPSE_ARGS) > $(CY_ECLIPSE_TEMPFILE);\ + for launch in $(CY_ECLIPSE_TEMPLATE_PATH)/$(CY_ECLIPSE_TEMPLATES_WILDCARD); do\ + launchFile="$${launch##*/}";\ + launchFileName="$${launchFile%.*}";\ + sed -f $(CY_ECLIPSE_TEMPFILE) "$(CY_ECLIPSE_TEMPLATE_PATH)/$$launchFileName.xml" > "$(CY_ECLIPSE_OUT_PATH)/$(CY_IDE_PRJNAME) $$launchFileName.launch";\ + launchConfigs="$$launchConfigs \"$(CY_IDE_PRJNAME) $$launchFileName.launch"\";\ + done;\ + rm $(CY_ECLIPSE_TEMPFILE);\ + echo;\ + echo Generated Eclipse launch config files: "$$launchConfigs" +else + @echo +endif + +ifneq ($(SEARCH_LIBS_AND_INCLUDES),) +CY_SHARED_ALL_LIB_FILES=$(call CY_MACRO_SEARCH,.lib,$(CY_SHARED_PATH)) +CY_SHARED_USED_LIB_NAMES=$(foreach item,$(SEARCH_LIBS_AND_INCLUDES),$(notdir $(item).lib)) +CY_SHARED_USED_LIB_FILES=$(foreach name,$(CY_SHARED_USED_LIB_NAMES),$(filter %/$(name),$(CY_SHARED_ALL_LIB_FILES))) +endif + +CY_HELP_get_app_info=Prints the app info for the eclipse IDE. +get_app_info: + @echo;\ + echo "APP_NAME=$(APPNAME)";\ + echo "LIB_NAME=$(LIBNAME)";\ + echo "TARGET=$(TARGET)";\ + echo "TARGET_DEVICE=$(DEVICE)";\ + echo "CONFIGURATOR_FILES=$(CY_CONFIG_FILES)";\ + echo "SUPPORTED_TOOL_TYPES=$(CY_OPEN_FILTERED_SUPPORTED_TYPES)";\ + echo "CY_TOOLS_PATH=$(CY_TOOLS_DIR)";\ + echo "CY_GETLIBS_PATH=$(CY_INTERNAL_GETLIBS_PATH)";\ + echo "SHAREDLIBS_ROOT=$(CY_SHARED_PATH)";\ + echo "SHAREDLIBS=$(SEARCH_LIBS_AND_INCLUDES)";\ + echo "SHAREDLIBS_FILES=$(CY_SHARED_USED_LIB_FILES)";\ + echo "CY_DEPENDENT_PROJECTS=$(CY_DEPENDENT_PROJECTS)" + + +################################################################################ +# Test/debug targets +################################################################################ + +CY_TOOLS_LIST+=bash git find ls cp mkdir rm cat sed awk perl file whereis + +CY_HELP_check=Checks for the necessary tools. +check: + $(info ) + $(foreach tool,$(CY_TOOLS_LIST),$(if $(shell which $(tool)),,$(error "$(tool) was not found in user's PATH"))) + @if [ ! -d $(CY_BT_CONFIGURATOR_DIR) ]; then toolsTest+=("bt-configurator could not be found"); fi;\ + if [ ! -d $(CY_CAPSENSE_CONFIGURATOR_DIR) ]; then toolsTest+=("capsense-configurator could not be found"); fi;\ + if [ ! -d $(CY_CFG_BACKEND_CLI_DIR) ]; then toolsTest+=("cfg-backend-cli could not be found"); fi;\ + if [ ! -d $(CY_MCUELFTOOL_DIR) ]; then toolsTest+=("cymcuelftool could not be found"); fi;\ + if [ ! -d $(CY_PE_TOOL_DIR) ]; then toolsTest+=("cype-tool could not be found"); fi;\ + if [ ! -d $(CY_DEVICE_CONFIGURATOR_DIR) ]; then toolsTest+=("device-configurator could not be found"); fi;\ + if [ ! -d $(CY_DFUH_TOOL_DIR) ]; then toolsTest+=("dfuh-tool could not be found"); fi;\ + if [ ! -d $(CY_FW_LOADER_DIR) ]; then toolsTest+=("fw-loader could not be found"); fi;\ + if [ ! -d $(CY_COMPILER_DIR) ]; then toolsTest+=("Default ARM GCC toolchain could not be found"); fi;\ + if [ ! -d $(CY_JRE_DIR) ]; then toolsTest+=("Java Runtime Environment tool could not be found"); fi;\ + if [ ! -d $(CY_LIBRARY_MANAGER_DIR) ]; then toolsTest+=("Library Manager could not be found"); fi;\ + if [ ! -d $(CY_MODUS_SHELL_DIR) ]; then toolsTest+=("modus-shell could not be found"); fi;\ + if [ ! -d $(CY_OPENOCD_DIR) ]; then toolsTest+=("openocd could not be found"); fi;\ + if [ ! -d $(CY_PROJECT_CREATOR_DIR) ]; then toolsTest+=("Project Creator could not be found"); fi;\ + if [ ! -d $(CY_QSPI_CONFIGURATOR_DIR) ]; then toolsTest+=("qspi-configurator could not be found"); fi;\ + if [ ! -d $(CY_SEGLCD_CONFIGURATOR_DIR) ]; then toolsTest+=("seglcd-configurator could not be found"); fi;\ + if [ ! -d $(CY_SMARTIO_CONFIGURATOR_DIR) ]; then toolsTest+=("smartio-configurator could not be found"); fi;\ + if [ ! -d $(CY_MAKEFILES_DIR) ]; then toolsTest+=("Tools make files could not be found"); fi;\ + if [ $${#toolsTest[@]} -eq 0 ]; then\ + printf "SUCCESS: All tools are present";\ + else\ + printf "FAILED: The following tools are missing\n";\ + printf ' %s\n' "$${toolsTest[@]}";\ + fi; + +CY_HELP_get_env_info=Prints the make, git, and app repo info. +get_env_info: + @echo;\ + echo "make location :" $$(which make);\ + echo "make version :" $(MAKE_VERSION);\ + echo "git location :" $$(which git);\ + echo "git version :" $$(git --version);\ + echo "git remote :";\ + git remote -v;\ + echo "git rev-parse :" $$(git rev-parse HEAD) + +# Empty libs on purpose. May be defined by the application +shared_libs: + +CY_HELP_printlibs=Prints the status of the library repos. +printlibs: + +# +# Identify the phony targets +# +.PHONY: help help_default vscode eclipse check shared_libs get_env_info get_app_info diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/recipe/defines.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/recipe/defines.mk new file mode 100644 index 0000000000000000000000000000000000000000..c57aca59927616065016e155ce29b610504f7031 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/recipe/defines.mk @@ -0,0 +1,295 @@ +################################################################################ +# \file defines.mk +# \version 1.0 +# +# \brief +# Defines, needed for the PSoC 6 build recipe. +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + + +# +# List the supported toolchains +# +CY_SUPPORTED_TOOLCHAINS=GCC_ARM IAR ARM A_Clang + +# +# Define the default core +# +CORE?=CM4 +CY_START_FLASH=0x10000000 +CY_START_SRAM=0x08000000 + +CY_OPEN_bt_configurator_DEVICE=--device PSoC6 +CY_OPENOCD_CHIP_NAME=psoc6 +CY_OPENOCD_SECOND_RESET_TYPE=run +CY_OPENOCD_OTHER_RUN_CMD=mon psoc6 reset_halt sysresetreq +CY_OPENOCD_OTHER_RUN_CMD_ECLIPSE=$(CY_OPENOCD_OTHER_RUN_CMD)\&\#13;\&\#10; + +# +# Core specifics +# +ifeq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_M0P))) +ifeq ($(CORE),CM0P) +$(call CY_MACRO_ERROR,$(DEVICE) does not have a CM0+ core) +endif +CY_LINKERSCRIPT_SUFFIX=cm4 +CY_OPENOCD_EXTRA_PORT_FLAG= +CY_OPENOCD_EXTRA_PORT_ECLIPSE= +CY_OPENOCD_CM0_DISABLE_FLAG=set ENABLE_CM0 0 +CY_OPENOCD_CM0_DISABLE_ECLIPSE=-c \"$(CY_OPENOCD_CM0_DISABLE_FLAG)\"\&\#13;\&\#10; +else +ifeq ($(CORE),CM0P) +CY_LINKERSCRIPT_SUFFIX=cm0plus +else +CY_LINKERSCRIPT_SUFFIX=cm4_dual +CY_OPENOCD_EXTRA_PORT_FLAG=gdb_port 3332 +CY_OPENOCD_EXTRA_PORT_ECLIPSE=-c \"$(CY_OPENOCD_EXTRA_PORT_FLAG)\"\&\#13;\&\#10; +CY_OPENOCD_CM0_DISABLE_FLAG= +CY_OPENOCD_CM0_DISABLE_ECLIPSE= +endif +endif + +# +# Architecure specifics +# +ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_DIE_PSOC6ABLE2))) + +CY_PSOC_ARCH=psoc6_01 +CY_PSOC_DIE_NAME=PSoC6ABLE2 +CY_OPENOCD_DEVICE_CFG=psoc6.cfg +CY_JLINK_DEVICE_CFG_PROGRAM=CY8C6xx7_CM0p_sect256KB_tm +CY_JLINK_DEVICE_CFG_DEBUG=CY8C6xx7_CM4_sect256KB +ifeq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_M0P))) +CY_JLINK_DEVICE_CFG_PROGRAM=CY8C6xx6_CM4_sect256KB +CY_JLINK_DEVICE_CFG_DEBUG=CY8C6xx6_CM4_sect256KB +endif +ifneq (,$(findstring CYB0,$(DEVICE))) +CY_PSOC_ARCH=psoc6_secure +CY_PSOC_DIE_NAME=PSoC6ABLE2Secure +CY_OPENOCD_CHIP_NAME=psoc64 +CY_OPENOCD_DEVICE_CFG=psoc6_secure.cfg +CY_OPENOCD_CM0_DISABLE_FLAG=set TARGET_AP cm4_ap +CY_OPENOCD_EXTRA_PORT_FLAG= +CY_OPENOCD_CM0_DISABLE_ECLIPSE=-c \"$(CY_OPENOCD_CM0_DISABLE_FLAG)\"\&\#13;\&\#10; +CY_OPENOCD_EXTRA_PORT_ECLIPSE= +CY_OPENOCD_SECOND_RESET_TYPE=init +CY_OPENOCD_OTHER_RUN_CMD= +CY_OPENOCD_OTHER_RUN_CMD_ECLIPSE= +CY_OPENOCD_SMIF_DISABLE=set DISABLE_SMIF 1 +CY_OPENOCD_SMIF_DISABLE_ECLIPSE=-c \"$(CY_OPENOCD_SMIF_DISABLE)\"\&\#13;\&\#10; +endif + +else ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_DIE_PSOC6A2M))) + +CY_PSOC_ARCH=psoc6_02 +CY_PSOC_DIE_NAME=PSoC6A2M +CY_OPENOCD_DEVICE_CFG=psoc6_2m.cfg +CY_JLINK_DEVICE_CFG_PROGRAM=CY8C6xxA_CM0p_sect256KB_tm +CY_JLINK_DEVICE_CFG_DEBUG=CY8C6xxA_CM4_sect256KB +ifneq (,$(findstring CYB0,$(DEVICE))) +CY_PSOC_ARCH=psoc6_2m_secure +CY_PSOC_DIE_NAME=PSoC6A2MSecure +CY_OPENOCD_CHIP_NAME=psoc64_2m +CY_OPENOCD_DEVICE_CFG=psoc6_2m_secure.cfg +CY_OPENOCD_CM0_DISABLE_FLAG=set TARGET_AP cm4_ap +CY_OPENOCD_EXTRA_PORT_FLAG= +CY_OPENOCD_CM0_DISABLE_ECLIPSE=-c \"$(CY_OPENOCD_CM0_DISABLE_FLAG)\"\&\#13;\&\#10; +CY_OPENOCD_EXTRA_PORT_ECLIPSE= +CY_OPENOCD_SECOND_RESET_TYPE=init +CY_OPENOCD_OTHER_RUN_CMD= +CY_OPENOCD_OTHER_RUN_CMD_ECLIPSE= +CY_OPENOCD_SMIF_DISABLE=set DISABLE_SMIF 1 +CY_OPENOCD_SMIF_DISABLE_ECLIPSE=-c \"$(CY_OPENOCD_SMIF_DISABLE)\"\&\#13;\&\#10; +endif + +else ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_DIE_PSOC6A512K))) + +CY_PSOC_ARCH=psoc6_03 +CY_PSOC_DIE_NAME=PSoC6A512K +CY_OPENOCD_DEVICE_CFG=psoc6_512k.cfg +CY_JLINK_DEVICE_CFG_PROGRAM=CY8C6xx5_CM0p_sect256KB_tm +CY_JLINK_DEVICE_CFG_DEBUG=CY8C6xx5_CM4_sect256KB + +else +$(call CY_MACRO_ERROR,Incorrect part number $(DEVICE). Check DEVICE variable.) +endif + +# +# Flash memory specifics +# +ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_FLASH_KB_512))) +CY_MEMORY_FLASH=524288 +else ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_FLASH_KB_832))) +CY_MEMORY_FLASH=850944 +else ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_FLASH_KB_1024))) +CY_MEMORY_FLASH=1048576 +else ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_FLASH_KB_1856))) +CY_MEMORY_FLASH=1899520 +else ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_FLASH_KB_2048))) +CY_MEMORY_FLASH=2097152 +else +$(call CY_MACRO_ERROR,No Flash memory size defined for $(DEVICE)) +endif + +# +# SRAM memory specifics +# +ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_SRAM_KB_128))) +CY_MEMORY_SRAM=129024 +else ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_SRAM_KB_256))) +CY_MEMORY_SRAM=260096 +else ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_SRAM_KB_288))) +CY_MEMORY_SRAM=292864 +else ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_SRAM_KB_512))) +CY_MEMORY_SRAM=522240 +else ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_SRAM_KB_1024))) +CY_MEMORY_SRAM=1046528 +else +$(call CY_MACRO_ERROR,No SRAM memory size defined for $(DEVICE)) +endif + +# +# linker scripts +# + +# Secure parts +ifneq (,$(findstring CYB06,$(DEVICE))) + +ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_DIE_PSOC6ABLE2))) +ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_FLASH_KB_832))) +CY_LINKER_SCRIPT_NAME=cyb06xx7 +endif +else ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_DIE_PSOC6A2M))) +ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_FLASH_KB_1856))) +CY_LINKER_SCRIPT_NAME=cyb06xxa +endif +endif + +# Non-secure part +else + +ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_DIE_PSOC6A512K))) +ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_FLASH_KB_512))) +CY_LINKER_SCRIPT_NAME=cy8c6xx5 +endif +else ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_DIE_PSOC6ABLE2))) +ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_FLASH_KB_512))) +CY_LINKER_SCRIPT_NAME=cy8c6xx6 +else ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_FLASH_KB_1024))) +CY_LINKER_SCRIPT_NAME=cy8c6xx7 +endif +else ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_DIE_PSOC6A2M))) +ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_FLASH_KB_1024))) +CY_LINKER_SCRIPT_NAME=cy8c6xx8 +else ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_FLASH_KB_2048))) +CY_LINKER_SCRIPT_NAME=cy8c6xxa +endif +endif + +endif + +ifeq ($(CY_LINKER_SCRIPT_NAME),) +$(call CY_MACRO_ERROR,Could not resolve device series for linker script) +endif + +# +# Paths used in program/debug +# +ifeq ($(CY_DEVICESUPPORT_PATH),) +CY_OPENOCD_SVD_PATH?= +else +CY_OPENOCD_SVD_PATH?= +endif +CY_OPENOCD_QSPI_CFG_PATH=$(CY_TARGET_DIR)/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource + +# +# Set the output file paths +# +ifneq ($(CY_BUILD_LOCATION),) +CY_SYM_FILE?=$(CY_INTERNAL_BUILD_LOCATION)/$(APPNAME)/$(TARGET)/$(CONFIG)/$(APPNAME).elf +CY_PROG_FILE?=$(CY_INTERNAL_BUILD_LOCATION)/$(APPNAME)/$(TARGET)/$(CONFIG)/$(APPNAME).hex +else +CY_SYM_FILE?=\$$\{cy_prj_path\}/$(notdir $(CY_INTERNAL_BUILD_LOC))/$(TARGET)/$(CONFIG)/$(APPNAME).elf +CY_PROG_FILE?=\$$\{cy_prj_path\}/$(notdir $(CY_INTERNAL_BUILD_LOC))/$(TARGET)/$(CONFIG)/$(APPNAME).hex +endif + +# +# IDE specifics +# +ifneq (,$(findstring CYB0,$(DEVICE))) +CY_ECLIPSE_TEMPLATES_WILDCARD=*KitProg3* +endif + +CY_VSCODE_ARGS="s|&&RELEASETARGET&&|build/$(TARGET)/Release/$(APPNAME).elf|g;"\ + "s|&&DEBUGTARGET&&|build/$(TARGET)/Debug/$(APPNAME).elf|g;"\ + "s|&&PSOCFAMILY&&|$(CY_PSOC_ARCH)|g;"\ + "s|&&MODUSSHELL&&|$(CY_MODUS_SHELL_DIR)|g;"\ + "s|&&OPENOCDFILE&&|$(CY_OPENOCD_DEVICE_CFG)|g;"\ + "s|&&SVDFILENAME&&|$(CY_OPENOCD_SVD_PATH)|g;"\ + "s|&&MODUSTOOLCHAIN&&|$(CY_COMPILER_DIR)|g;"\ + "s|&&MODUSTOOLCHAINVERSION&&|$(notdir $(CY_COMPILER_DIR))|g;"\ + "s|&&MODUSOPENCOD&&|$(CY_OPENOCD_DIR)|g;"\ + "s|&&MODUSLIBMANAGER&&|$(CY_LIBRARY_MANAGER_DIR)|g;"\ + +CY_ECLIPSE_ARGS="s|&&CY_OPENOCD_CFG&&|$(CY_OPENOCD_DEVICE_CFG)|;"\ + "s|&&CY_OPENOCD_CHIP&&|$(CY_OPENOCD_CHIP_NAME)|;"\ + "s|&&CY_OPENOCD_SECOND_RESET&&|$(CY_OPENOCD_SECOND_RESET_TYPE)|;"\ + "s|&&CY_OPENOCD_OTHER_RUN_CMD&&|$(CY_OPENOCD_OTHER_RUN_CMD_ECLIPSE)|;"\ + "s|&&CY_JLINK_CFG_PROGRAM&&|$(CY_JLINK_DEVICE_CFG_PROGRAM)|;"\ + "s|&&CY_JLINK_CFG_DEBUG&&|$(CY_JLINK_DEVICE_CFG_DEBUG)|;"\ + "s|&&CY_OPENOCD_PORT_SELECT&&|$(CY_OPENOCD_EXTRA_PORT_ECLIPSE)|;"\ + "s|&&CY_OPENOCD_CM0_FLAG&&|$(CY_OPENOCD_CM0_DISABLE_ECLIPSE)|;"\ + "s|&&CY_OPENOCD_SMIF_DISABLE&&|$(CY_OPENOCD_SMIF_DISABLE_ECLIPSE)|;"\ + "s|&&CY_APPNAME&&|$(CY_IDE_PRJNAME)|;"\ + "s|&&CY_CONFIG&&|$(CONFIG)|;"\ + "s|&&CY_QSPI_CFG_PATH&&|$(CY_OPENOCD_QSPI_CFG_PATH)|;"\ + "s|&&CY_SVD_PATH&&|$(CY_OPENOCD_SVD_PATH)|;"\ + "s|&&CY_SYM_FILE&&|$(CY_SYM_FILE)|;"\ + "s|&&CY_PROG_FILE&&|$(CY_PROG_FILE)|;" + +# +# Tools specifics +# +ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_CAPSENSE))) +CY_SUPPORTED_TOOL_TYPES+=capsense-configurator capsense-tuner +endif +ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_BLE))) +CY_SUPPORTED_TOOL_TYPES+=bt-configurator +endif +ifneq (,$(findstring $(DEVICE),$(CY_DEVICES_WITH_FS_USB))) +CY_SUPPORTED_TOOL_TYPES+=usbdev-configurator +endif +CY_SUPPORTED_TOOL_TYPES+=\ + device-configurator\ + qspi-configurator\ + seglcd-configurator\ + smartio-configurator\ + cype-tool\ + dfuh-tool + +# PSoC 6 smartio also uses the .modus extension +modus_DEFAULT_TYPE+=device-configurator smartio-configurator + +# PSoC 6 capsense-tuner shares its existence with capsense-configurator +CY_OPEN_NEWCFG_XML_TYPES+=capsense-tuner diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/recipe/program.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/recipe/program.mk new file mode 100644 index 0000000000000000000000000000000000000000..8697f3915259aa8f29ee9e7aa2066a10792fb19b --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/recipe/program.mk @@ -0,0 +1,104 @@ +################################################################################ +# \file program.mk +# \version 1.0 +# +# \brief +# This make file is called recursively and is used to build the +# resoures file system. It is expected to be run from the example directory. +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + + +CY_GDB_CLIENT=$(CY_COMPILER_DIR)/bin/arm-none-eabi-gdb +CY_GDB_ARGS=$(CY_INTERNAL_BASELIB_PATH)/make/scripts/gdbinit + +ifeq ($(TOOLCHAIN),A_Clang) +CY_OPENOCD_PROGRAM_IMG=$(CY_CONFIG_DIR)/$(APPNAME).bin $(TOOLCHAIN_VECT_BASE_CM4) +else +CY_OPENOCD_SYMBOL_IMG=$(CY_CONFIG_DIR)/$(APPNAME).elf +CY_OPENOCD_PROGRAM_IMG=$(CY_CONFIG_DIR)/$(APPNAME).hex +endif + +CY_OPENOCD_SCRIPTS=-s $(CY_OPENOCD_DIR)/scripts +CY_OPENOCD_QSPI=-s $(CY_OPENOCD_QSPI_CFG_PATH) +CY_OPENOCD_INTERFACE=source [find interface/kitprog3.cfg]; +CY_OPENOCD_TARGET=source [find target/$(CY_OPENOCD_DEVICE_CFG)]; +ifeq (,$(findstring CYB0,$(DEVICE))) +CY_OPENOCD_CUSTOM_COMMAND?=psoc6 allow_efuse_program off; +else +CY_GDB_ARGS=$(CY_INTERNAL_BASELIB_PATH)/make/scripts/gdbinit_secure +endif + +CY_OPENOCD_ERASE=init; reset init; psoc6 sflash_restrictions 1; erase_all; exit; +CY_OPENOCD_PROGRAM=psoc6 sflash_restrictions 1; program $(CY_OPENOCD_PROGRAM_IMG) verify reset exit; +CY_OPENOCD_DEBUG=$(CY_OPENOCD_CHIP_NAME).cpu.cm4 configure -rtos auto -rtos-wipe-on-reset-halt 1; $(CY_OPENOCD_EXTRA_PORT_FLAG); init; reset init; + +CY_OPENOCD_ERASE_ARGS=$(CY_OPENOCD_SCRIPTS) -c \ + "$(CY_OPENOCD_INTERFACE) $(CY_OPENOCD_CM0_DISABLE_FLAG); $(CY_OPENOCD_SMIF_DISABLE); $(CY_OPENOCD_TARGET) $(CY_OPENOCD_CUSTOM_COMMAND) $(CY_OPENOCD_ERASE)" +CY_OPENOCD_PROGRAM_ARGS=$(CY_OPENOCD_SCRIPTS) $(CY_OPENOCD_QSPI) -c \ + "$(CY_OPENOCD_INTERFACE) $(CY_OPENOCD_CM0_DISABLE_FLAG); $(CY_OPENOCD_TARGET) $(CY_OPENOCD_CUSTOM_COMMAND) $(CY_OPENOCD_PROGRAM)" +CY_OPENOCD_DEBUG_ARGS=$(CY_OPENOCD_SCRIPTS) $(CY_OPENOCD_QSPI) -c \ + "$(CY_OPENOCD_INTERFACE) $(CY_OPENOCD_CM0_DISABLE_FLAG); $(CY_OPENOCD_TARGET) $(CY_OPENOCD_CUSTOM_COMMAND) $(CY_OPENOCD_DEBUG)" + +erase: + @echo;\ + echo "Erasing target device... ";\ + $(CY_OPENOCD_DIR)/bin/openocd $(CY_OPENOCD_ERASE_ARGS) + +program: build qprogram + +qprogram: memcalc +ifeq ($(LIBNAME),) + @echo;\ + echo "Programming target device... ";\ + $(CY_OPENOCD_DIR)/bin/openocd $(CY_OPENOCD_PROGRAM_ARGS) +else + @echo "Library application detected. Skip programming... ";\ + echo +endif + +debug: program qdebug + +qdebug: qprogram +ifeq ($(LIBNAME),) + @echo;\ + echo ==============================================================================;\ + echo "Instruction:";\ + echo "Open a separate shell and run the attach target (make attach)";\ + echo "to start the GDB client. Then use the GDB commands to debug.";\ + echo ==============================================================================;\ + echo;\ + echo "Opening GDB port ... ";\ + $(CY_OPENOCD_DIR)/bin/openocd $(CY_OPENOCD_DEBUG_ARGS) +else + @echo "Library application detected. Skip debug... ";\ + echo +endif + +attach: + @echo;\ + echo "Starting GDB Client... ";\ + $(CY_GDB_CLIENT) $(CY_OPENOCD_SYMBOL_IMG) -x $(CY_GDB_ARGS) + + +.PHONY: erase program qprogram debug qdebug attach diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/recipe/recipe.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/recipe/recipe.mk new file mode 100644 index 0000000000000000000000000000000000000000..ed0f70866ee78bd41e74f8997213f430e0432f10 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/recipe/recipe.mk @@ -0,0 +1,202 @@ +################################################################################ +# \file recipe.mk +# \version 1.0 +# +# \brief +# Set up a set of defines, includes, software components, linker script, +# Pre and Post build steps and call a macro to create a specific ELF file. +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + + +# +# linker script construction +# +ifeq ($(LINKER_SCRIPT),) +LINKER_SCRIPT=$(CY_TARGET_DIR)/linker/TOOLCHAIN_$(TOOLCHAIN)/$(CY_LINKER_SCRIPT_NAME)_$(CY_LINKERSCRIPT_SUFFIX).$(CY_TOOLCHAIN_SUFFIX_LS) +endif + +ifeq ($(shell if [ -f $(LINKER_SCRIPT) ]; then echo 1; else echo 0; fi;),0) +$(error The specified linker script could not be found at $(LINKER_SCRIPT)) +endif + +ifeq ($(TOOLCHAIN),A_Clang) +include $(LINKER_SCRIPT) +else +CY_RECIPE_LSFLAG=$(CY_TOOLCHAIN_LSFLAGS)$(LINKER_SCRIPT) +endif + +# +# Flags construction +# +CY_RECIPE_CFLAGS?=\ + $(CFLAGS)\ + $(CY_TOOLCHAIN_CFLAGS) + +CY_RECIPE_CXXFLAGS?=\ + $(CXXFLAGS)\ + $(CY_TOOLCHAIN_CXXFLAGS) + +CY_RECIPE_ASFLAGS?=\ + $(ASFLAGS)\ + $(CY_TOOLCHAIN_ASFLAGS) + +CY_RECIPE_ARFLAGS?=\ + $(CY_TOOLCHAIN_ARFLAGS) + +CY_RECIPE_LDFLAGS?=\ + $(LDFLAGS)\ + $(CY_TOOLCHAIN_LDFLAGS)\ + $(CY_RECIPE_LSFLAG) + +# +# Defines construction +# +ifneq ($(DEFINES),) +CY_RECIPE_USER_DEFINES=$(addprefix -D,$(DEFINES)) +endif +ifneq ($(LIBNAME),) +CY_RECIPE_USER_NAME=-DCY_LIBNAME_$(subst -,_,$(LIBNAME)) +else +CY_RECIPE_USER_NAME=-DCY_APPNAME_$(subst -,_,$(APPNAME)) +endif + +CY_RECIPE_DEFINES=\ + $(CY_RECIPE_USER_DEFINES)\ + $(CY_RECIPE_USER_NAME)\ + -D$(subst -,_,$(DEVICE))\ + -DCY_TARGET_DEVICE=$(subst -,_,$(DEVICE))\ + -DTARGET_$(subst -,_,$(TARGET))\ + -DCY_TARGET_BOARD=$(subst -,_,$(TARGET))\ + $(foreach feature,$(CY_COMPONENT_LIST),-DCOMPONENT_$(subst -,_,$(feature)))\ + $(CY_TOOLCHAIN_DEBUG_FLAG)\ + $(CY_TOOLCHAIN_DEFINES) + +# +# Includes construction +# +CY_RECIPE_INCLUDES=\ + $(addprefix -I,$(INCLUDES))\ + $(addprefix -I,$(CY_SEARCH_APP_INCLUDES))\ + $(addprefix -I,$(CY_TOOLCHAIN_INCLUDES)) + +# +# Sources construction +# +CY_RECIPE_SOURCE=$(CY_SEARCH_APP_SOURCE) + +# +# Libraries construction +# +CY_RECIPE_LIBS=$(LDLIBS) $(CY_SEARCH_APP_LIBS) + +# +# Generate source step +# +ifneq ($(CY_SEARCH_RESOURCE_FILES),) +CY_RECIPE_RESOURCE_FILES=$(CY_SEARCH_RESOURCE_FILES) +CY_RECIPE_GENERATED_FLAG=TRUE + +# Define the generated source file. Use := for better performance +CY_RECIPE_GENERATED:=$(addprefix $(CY_GENERATED_DIR)/,$(addsuffix .$(CY_TOOLCHAIN_SUFFIX_C),\ + $(basename $(notdir $(subst .,_,$(CY_SEARCH_RESOURCE_FILES)))))) + +CY_RECIPE_GENSRC=\ + bash --norc --noprofile\ + $(CY_INTERNAL_BASELIB_PATH)/make/scripts/genresources.bash\ + $(CY_INTERNAL_BASELIB_PATH)/make/scripts\ + $(CY_GENERATED_DIR)/resources.cyrsc\ + $(CY_INTERNAL_APP_PATH)\ + $(CY_GENERATED_DIR)\ + "MEM" +endif + +# +# Prebuild step +# +CY_RECIPE_PREBUILD?= + +# +# Postbuild step +# +ifeq ($(LIBNAME),) + +ifeq ($(TOOLCHAIN),A_Clang) +CY_RECIPE_POSTBUILD?=\ + $(CY_TOOLCHAIN_M2BIN)\ + --verbose --vect $(VECT_BASE_CM4) --text $(TEXT_BASE_CM4) --data $(RAM_BASE_CM4) --size $(TEXT_SIZE_CM4)\ + $(CY_CONFIG_DIR)/$(APPNAME).mach_o\ + $(CY_CONFIG_DIR)/$(APPNAME).bin + +else ifeq ($(TOOLCHAIN),ARM) +ifeq ($(CY_COMPILER_PATH),) +CY_RECIPE_POSTBUILD?=$(CY_COMPILER_ARM_DIR)/bin/fromelf --output $(CY_CONFIG_DIR)/$(APPNAME).hex --i32combined $(CY_CONFIG_DIR)/$(APPNAME).elf +else +CY_RECIPE_POSTBUILD?=$(CY_COMPILER_PATH)/bin/fromelf --output $(CY_CONFIG_DIR)/$(APPNAME).hex --i32combined $(CY_CONFIG_DIR)/$(APPNAME).elf +endif + +else ifeq ($(TOOLCHAIN),IAR) +CY_RECIPE_POSTBUILD?=$(CY_COMPILER_GCC_ARM_DIR)/bin/arm-none-eabi-objcopy -O ihex $(CY_CONFIG_DIR)/$(APPNAME).elf $(CY_CONFIG_DIR)/$(APPNAME).hex + +else ifeq ($(TOOLCHAIN),GCC_ARM) +ifeq ($(CY_COMPILER_PATH),) +CY_RECIPE_POSTBUILD?=$(CY_COMPILER_GCC_ARM_DIR)/bin/arm-none-eabi-objcopy -O ihex $(CY_CONFIG_DIR)/$(APPNAME).elf $(CY_CONFIG_DIR)/$(APPNAME).hex +else +CY_RECIPE_POSTBUILD?=$(CY_COMPILER_PATH)/bin/arm-none-eabi-objcopy -O ihex $(CY_CONFIG_DIR)/$(APPNAME).elf $(CY_CONFIG_DIR)/$(APPNAME).hex +endif +endif + +endif + +################################################################################ +# Memory Consumption +################################################################################ + +ifeq ($(TOOLCHAIN),A_Clang) +CY_GEN_READELF= +CY_MEMORY_CALC= +else +CY_GEN_READELF=$(CY_COMPILER_DIR)/bin/arm-none-eabi-readelf -Sl $(CY_CONFIG_DIR)/$(APPNAME).elf > $(CY_CONFIG_DIR)/$(APPNAME).readelf +CY_MEM_CALC=\ + bash --norc --noprofile\ + $(CY_INTERNAL_BASELIB_PATH)/make/scripts/memcalc.bash\ + $(CY_CONFIG_DIR)/$(APPNAME).readelf\ + $(CY_MEMORY_FLASH)\ + $(CY_MEMORY_SRAM)\ + $(CY_START_FLASH)\ + $(CY_START_SRAM) +endif + +memcalc: app +ifneq ($(LIBNAME),) +else + @echo Calculating memory consumption: $(DEVICE) $(TOOLCHAIN) $(CY_TOOLCHAIN_OPTIMIZATION) + @echo + $(CY_NOISE)$(CY_GEN_READELF) + $(CY_NOISE)$(CY_MEM_CALC) +endif + +# +# Identify the phony targets +# +.PHONY: memcalc diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/bin_to_resource_c.pl b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/bin_to_resource_c.pl new file mode 100644 index 0000000000000000000000000000000000000000..20b6c767f08b403c4807fb20dac5c547c11fd595 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/bin_to_resource_c.pl @@ -0,0 +1,107 @@ +#!/usr/bin/perl + +# +# Copyright 2019, Cypress Semiconductor Corporation or a subsidiary of +# Cypress Semiconductor Corporation. All Rights Reserved. +# +# This software, including source code, documentation and related +# materials ("Software"), is owned by Cypress Semiconductor Corporation +# or one of its subsidiaries ("Cypress") and is protected by and subject to +# worldwide patent protection (United States and foreign), +# United States copyright laws and international treaty provisions. +# Therefore, you may use this Software only as provided in the license +# agreement accompanying the software package from which you +# obtained this Software ("EULA"). +# If no EULA applies, Cypress hereby grants you a personal, non-exclusive, +# non-transferable license to copy, modify, and compile the Software +# source code solely for use in connection with Cypress's +# integrated circuit products. Any reproduction, modification, translation, +# compilation, or representation of this Software except as specified +# above is prohibited without the express written permission of Cypress. +# +# Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO WARRANTY OF ANY KIND, +# EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress +# reserves the right to make changes to the Software without notice. Cypress +# does not assume any liability arising out of the application or use of the +# Software or any product or circuit described in the Software. Cypress does +# not authorize its products for use in any products where a malfunction or +# failure of the Cypress product may reasonably be expected to result in +# significant property damage, injury or death ("High Risk Product"). By +# including Cypress's product in a High Risk Product, the manufacturer +# of such system or application assumes all risk of such use and in doing +# so agrees to indemnify Cypress against all liability. +# + +if (! $ARGV[0] ) +{ + print "Usage ./bin_to_resource_c.pl "; + exit; +} + +# Print start of output +my $location = shift @ARGV; +my $variable_name = shift @ARGV; +my $original_variable_name = $variable_name; +my $file = shift @ARGV; + +#open the file +open INFILE, "<:raw", $file or die "cant open " . $file; +@file_cont_array = ; +close INFILE; +$file_cont = join('',@file_cont_array); + + +print "#include \"cy_abs_resource.h\"\n"; +print "\n"; +$name = $file; +$name=~s/^.+\/(.*?)/$1/; + +if ( $location ne "MEM" ) +{ + print "const cy_resource_handle_t ${variable_name} = { CY_RESOURCE_IN_FILESYSTEM, " . (length( $file_cont )) . ", {.fs = { 0, \"$name\" } }};\n"; + print "\n"; +} +else +{ + print "const uint8_t ${variable_name}_data[" . (length( $file_cont )) . "] = {\n"; + my @vals = unpack( "C*", $file_cont ); + + my $linepos; + my $firstval = 1; + + foreach $val (@vals) + { + my $valsize = 1; + if ( ( $val >= 10 ) && ( $val < 100 ) ) + { + $valsize = 2; + } + elsif ( $val >= 100 ) + { + $valsize = 3; + } + + if ( $firstval == 1 ) + { + print " $val"; + $linepos = 8 + $valsize; + $firstval = 0; + } + elsif ( $linepos + 5 >= 79 ) + { + print ",\n $val"; + $linepos = 8 + $valsize; + } + else + { + print ", $val"; + $linepos += 2 + $valsize; + } + } + + print "\n};\n"; + print "const cy_resource_handle_t ${variable_name} = { CY_RESOURCE_IN_MEMORY, " . (length( $file_cont )) . ", {.mem_data = ${variable_name}_data }};\n"; + print "\n"; +} + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Attach (JLink).xml b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Attach (JLink).xml new file mode 100644 index 0000000000000000000000000000000000000000..ca684385bd86b81c48f5cfdfb11ae83e2a062e44 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Attach (JLink).xml @@ -0,0 +1,78 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Attach (KitProg3).xml b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Attach (KitProg3).xml new file mode 100644 index 0000000000000000000000000000000000000000..f3ab745d535b4d4f3697790b6f617ebef9a0d727 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Attach (KitProg3).xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Debug (JLink).xml b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Debug (JLink).xml new file mode 100644 index 0000000000000000000000000000000000000000..5247c6f900f567ef5eeafd9694df67f77227c1d2 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Debug (JLink).xml @@ -0,0 +1,80 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Debug (KitProg3).xml b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Debug (KitProg3).xml new file mode 100644 index 0000000000000000000000000000000000000000..17516255644f9dc25ec6917a85cbdbb1cb814fca --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Debug (KitProg3).xml @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Erase (JLink).xml b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Erase (JLink).xml new file mode 100644 index 0000000000000000000000000000000000000000..ad502c569337a9d5b87bc3f6f66098a5f2a84eef --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Erase (JLink).xml @@ -0,0 +1,78 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Erase (KitProg3).xml b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Erase (KitProg3).xml new file mode 100644 index 0000000000000000000000000000000000000000..43f7970efd4e699720fa2498d4a36c33fda98d82 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Erase (KitProg3).xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Program (JLink).xml b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Program (JLink).xml new file mode 100644 index 0000000000000000000000000000000000000000..590852931aa120d687751abbba159e0ed10c8900 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Program (JLink).xml @@ -0,0 +1,80 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Program (KitProg3).xml b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Program (KitProg3).xml new file mode 100644 index 0000000000000000000000000000000000000000..d597267bf2e0429910f3c65b7b238f8ef28448dd --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/eclipse/Program (KitProg3).xml @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/gdbinit b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/gdbinit new file mode 100644 index 0000000000000000000000000000000000000000..03e0e87df88bf7c4c6771bf81638d4b34a052e1d --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/gdbinit @@ -0,0 +1,32 @@ +# CM4 port +target remote:3333 + +# Open all memory +set mem inaccessible-by-default off + +# Enable semihosting +monitor arm semihosting enable + +# Load the executable +# load + +# Reset device +monitor reset run + +# Halt device +monitor halt + +# Reset device via dedicated reset method +monitor psoc6 reset_halt sysresetreq +flushregs +mon gdb_sync +stepi + +# Set temporary breakpoint at main +tbreak main + +# Print registers +monitor reg + +# Continue program execution +continue \ No newline at end of file diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/gdbinit_secure b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/gdbinit_secure new file mode 100644 index 0000000000000000000000000000000000000000..c107ba49b344e8ae7bf9d4ec83a99e80eb793b8e --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/gdbinit_secure @@ -0,0 +1,34 @@ +# CM4 port +target remote:3333 + +# Open all memory +set mem inaccessible-by-default off + +# Target acquisition timeout +set remotetimeout 15 + +# Enable semihosting +monitor arm semihosting enable + +# Load the executable +# load + +# Reset device +monitor reset init + +# Halt device +monitor halt + +# Synchronize client and server +flushregs +mon gdb_sync +stepi + +# Set temporary breakpoint at main +tbreak main + +# Print registers +monitor reg + +# Continue program execution +continue \ No newline at end of file diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/genresources.bash b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/genresources.bash new file mode 100644 index 0000000000000000000000000000000000000000..3aa2083628c315d7c242fee1552eb4dd481abdc4 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/genresources.bash @@ -0,0 +1,177 @@ +#!/bin/bash +(set -o igncr) 2>/dev/null && set -o igncr; # this comment is required +set -$-ue${DEBUG+x} + +####################################################################################################################### +# This script is designed to process resource files that are necessary for a single component. It converts each +# resource file into a binary object and then stores that into an array in a .c file. The .c file can then be compiled +# with and linked into an application image. +# +# Once all resources files have been converted it will generate a header file that references each of them. +# +# usage: +# genresources.bash [s] +# +####################################################################################################################### + +RECIPE_DIR=$1 #eg: ./tools +RESOURCE_FILE=$2 #eg: ./generated/temp.cyrsc +PROJECT_DIR=$3 #eg: ./project_mainapp +TARGET_DIR=$4 #eg: ./project_resources +RESOURCE_TYPE=$5 #eg: FILESYSTEM or MEM + +echo Script: genresources.bash +echo " 1: Recipe Dir : '"$RECIPE_DIR"'" +echo " 3: Resource Files : '"$RESOURCE_FILE"'" +echo " 4: Project Dir : '"$PROJECT_DIR"'" +echo " 5: Target Dir : '"$TARGET_DIR"'" +echo " 6: Resource Type : '"$RESOURCE_TYPE"'" + +# +# File in the target directory +# +RES_FILE="$TARGET_DIR/cy_resources.h" + +# array of c source files parsed for declarations to generate resources.h +declare SOURCE_ARRAY=() + +# +# Print nice error messages +# +function error() { + echo "ERROR: $1" + shift + + while (( $# > 0 )); do + echo " : $1:" + shift + done + + echo "—ABORTING--" + exit 1 +} + +# +# Checks if the value $1 is in the array $element +# +array_contains () { + local seeking=$1; shift + local in=0 + for element; do + if [[ $element == $seeking ]]; then + in=1 + break + fi + done + echo $in +} + +# +# Prepares the resource file for outputing as c-file +# +convert_resource_name() { + local input=$1 + local result=${input//\//_DIR_} #replace '/' with '_DIR_' + result=${result//./_} #replace '.' with '_' + result=${result//-/_} #replace '-' with '_' + result=${result//resources_DIR/resources} #replace 'resources_DIR' with 'resources' + echo $result +} + +# +# Process the resources listed in the .cyrsc file by converting them to .c and creating +# a list of files for the resource header script +# +processResources() { + local TEXT_FILTERS=(html htm txt eml js css dat cer pem json xml py key) + local BINARY_FILTERS=(jpg jpeg png ico gif bin flac wav clm_blob gz mp3 wmfw) + + local TEXT_TO_RES="$RECIPE_DIR/text_to_resource_c.pl" + local BIN_TO_RES="$RECIPE_DIR/bin_to_resource_c.pl" + + local resourceList=($(<$1)) + + # Parse through each element in the .cyrsc file + for ((i = 0; i < ${#resourceList[@]}; i++)); do + + # Evaluate the file + local resourceFile="${resourceList[$i]}" + local filename="${resourceFile##*/}" + local extension="${filename##*.}" + + # only process the file if it exists + if [ -f "$resourceFile" ]; then + + local resourceName=$(convert_resource_name "$resourceFile") + local outputFile="$TARGET_DIR/$(convert_resource_name $filename).c" + + SOURCE_ARRAY+=("$TARGET_DIR/$(convert_resource_name $filename).c") + + local script + local isText=$(array_contains $extension "${TEXT_FILTERS[@]}") + if [ "1" == "$isText" ]; then + script=$TEXT_TO_RES + fi + + local isBinary=$(array_contains $extension "${BINARY_FILTERS[@]}") + if [ "1" == "$isBinary" ]; then + script=$BIN_TO_RES + fi + + local outputFileTmp="$TARGET_DIR/$(convert_resource_name $filename).c" + perl "$script" "$RESOURCE_TYPE" "$resourceName" "$resourceFile" > "$outputFileTmp" + else + error "Listed resource $resourceFile does not exist" + fi + done +} + +# +# Remove stale files from previous run +# +cleanStale() { + local staleList=($(find $TARGET_DIR -name "*.c")) + local resourceList=($(<$1)) + local fileFound=0 + + for ((j = 0; j < ${#staleList[@]}; j++)); do + for ((i = 0; i < ${#resourceList[@]}; i++)); do + local file="${resourceList[$i]}" + local filename="${file##*/}" + local outputFile="$TARGET_DIR/$(convert_resource_name $filename).c" + + if [[ $(basename $outputFile) == $(basename "${staleList[$j]}") ]]; then + fileFound=1 + fi + done + if [[ $fileFound == 0 ]]; then + rm -rf "${staleList[$j]}" + fi + fileFound=0 + done +} + +# +# Call the perl script that creates resources.h +# +generateResourceHeader() { + perl "$RECIPE_DIR/resources_header.pl" ${SOURCE_ARRAY[*]} > "$RES_FILE" +} + +####################################################################################################################### + +# +# Clean files from previous run that aren't in the current list +# +cleanStale $RESOURCE_FILE + +# +# Process all the resources in the cyrsc file +# +processResources $RESOURCE_FILE + +# +# Create the resource header +# +generateResourceHeader + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/memcalc.bash b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/memcalc.bash new file mode 100644 index 0000000000000000000000000000000000000000..47dac7b5554782904b3ccd39d544f49d50c29f88 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/memcalc.bash @@ -0,0 +1,78 @@ +#!/bin/bash +(set -o igncr) 2>/dev/null && set -o igncr; # this comment is required +set -$-ue${DEBUG+xv} + +####################################################################################################################### +# This script processes the memory consumption of an application and prints it out to the console. +# +# usage: +# memcalc.bash +# +####################################################################################################################### + +READELFFILE=$1 # file location of readelf output +AVAILABLEFLASH=$2 # Max available internal flash +AVAILABLESRAM=$3 # Max available internal SRAM +STARTFLASH=$4 # Start of internal flash +STARTSRAM=$5 # Start of internal SRAM + +ENDFLASH=$((STARTFLASH + AVAILABLEFLASH)) +ENDSRAM=$((STARTSRAM + AVAILABLESRAM)) + +# Gather the numbers +memcalc() { + local internalFlash=0 + local internalSram=0 + + printf " -------------------------------------------------- \n" + printf " | %-20s | %-10s | %-8s | \n" 'Section Name' 'Address' 'Size' + printf " -------------------------------------------------- \n" + + while IFS=$' \t\n\r' read -r line; do + local lineArray=($line) + local numElem=${#lineArray[@]} + + # Only look at potentially valid lines + if [[ $numElem -ge 6 ]]; then + # Section headers + if [[ ${lineArray[0]} == "["* ]]; then + local sectionElement=NULL + local addrElement=00000000 + local sizeElement=000000 + for (( idx = 0 ; idx <= $numElem-4 ; idx = $idx+1 )); + do + if [[ ${lineArray[$idx]} == *"]" ]]; then + sectionElement=${lineArray[$idx+1]} + fi + # Look for regions with SHF_ALLOC = A + if [[ ${#lineArray[idx]} -eq 8 ]] && [[ ${#lineArray[idx+1]} -eq 6 ]] && [[ ${#lineArray[idx+2]} -eq 6 ]] \ + && [[ ${lineArray[$idx+4]} == *"A"* ]] ; then + addrElement=${lineArray[$idx]} + sizeElement=${lineArray[$idx+2]} + fi + done + # Only consider non-zero size sections + if [[ $addrElement != "00000000" ]]; then + printf " | %-20s | 0x%-10s | %-8s | \n" $sectionElement $addrElement $((16#$sizeElement)) + # Use the section headers for SRAM tally + if [[ "0x$addrElement" -ge "$STARTSRAM" ]] && [[ "0x$addrElement" -lt "$ENDSRAM" ]]; then + internalSram=$((internalSram+$((16#$sizeElement)))) + fi + fi + # Program headers + elif [[ ${lineArray[1]} == "0x"* ]] && [[ ${lineArray[2]} == "0x"* ]] && [[ ${lineArray[3]} == "0x"* ]] && [[ ${lineArray[4]} == "0x"* ]]\ + && [[ ${lineArray[3]} -ge "$STARTFLASH" ]] && [[ ${lineArray[3]} -lt "$ENDFLASH" ]]; then + # Use the program headers for Flash tally + internalFlash=$((internalFlash+${lineArray[4]})) + fi + fi + done < "$READELFFILE" + + printf " -------------------------------------------------- \n\n" + printf " %-41s %-8s \n" 'Total Internal Flash (Available)' $AVAILABLEFLASH + printf " %-41s %-8s \n\n" 'Total Internal Flash (Utilized)' $internalFlash + printf " %-41s %-8s \n" 'Total Internal SRAM (Available)' $AVAILABLESRAM + printf " %-41s %-8s \n" 'Total Internal SRAM (Utilized)' $internalSram +} + +memcalc diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/resources_header.pl b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/resources_header.pl new file mode 100644 index 0000000000000000000000000000000000000000..85794778901621e26cea4a5538ed9c7b31f8ff82 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/resources_header.pl @@ -0,0 +1,83 @@ +#!/usr/bin/perl + +# +# Copyright 2019, Cypress Semiconductor Corporation or a subsidiary of +# Cypress Semiconductor Corporation. All Rights Reserved. +# +# This software, including source code, documentation and related +# materials ("Software"), is owned by Cypress Semiconductor Corporation +# or one of its subsidiaries ("Cypress") and is protected by and subject to +# worldwide patent protection (United States and foreign), +# United States copyright laws and international treaty provisions. +# Therefore, you may use this Software only as provided in the license +# agreement accompanying the software package from which you +# obtained this Software ("EULA"). +# If no EULA applies, Cypress hereby grants you a personal, non-exclusive, +# non-transferable license to copy, modify, and compile the Software +# source code solely for use in connection with Cypress's +# integrated circuit products. Any reproduction, modification, translation, +# compilation, or representation of this Software except as specified +# above is prohibited without the express written permission of Cypress. +# +# Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO WARRANTY OF ANY KIND, +# EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress +# reserves the right to make changes to the Software without notice. Cypress +# does not assume any liability arising out of the application or use of the +# Software or any product or circuit described in the Software. Cypress does +# not authorize its products for use in any products where a malfunction or +# failure of the Cypress product may reasonably be expected to result in +# significant property damage, injury or death ("High Risk Product"). By +# including Cypress's product in a High Risk Product, the manufacturer +# of such system or application assumes all risk of such use and in doing +# so agrees to indemnify Cypress against all liability. +# + +if (! $ARGV[0] ) +{ + print "Usage ./resources_header.pl ..."; + exit; +} + +print "/* Auto-generated header file. Do not edit */\n"; +print "\n"; +print "#pragma once\n"; +print "\n"; +print "#include \n"; +print "#include \"cy_abs_resource.h\"\n"; +print "\n"; +print "#ifdef __cplusplus\n"; +print "extern \"C\" {\n"; +print "#endif\n"; +print "\n"; + + +my $mem_resources = ""; +my $filesystem_resources = ""; + +foreach $file (@ARGV) +{ + #open the file + open INFILE, $file or die "cant open " . $file; + + @file_cont_array = ; + close INFILE; + $file_cont = join('',@file_cont_array); + + while ( $file_cont =~ m/(const cy_resource_handle_t \S+)/sgi ) + { + $resources .= "extern $1;\n"; + } + while ( $file_cont =~ m/(const uint8_t \S+\[\d+\])/sgi ) + { + $resources .= "extern $1;\n"; + } +} + +print "\n"; +print "$resources"; +print "\n"; +print "/* @} */\n"; +print "#ifdef __cplusplus\n"; +print "} /*extern \"C\" */\n"; +print "#endif\n"; diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/text_to_resource_c.pl b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/text_to_resource_c.pl new file mode 100644 index 0000000000000000000000000000000000000000..a9115aff83f106a266238a85d53ea5334e38acf2 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/text_to_resource_c.pl @@ -0,0 +1,132 @@ +#!/usr/bin/perl + +# +# Copyright 2019, Cypress Semiconductor Corporation or a subsidiary of +# Cypress Semiconductor Corporation. All Rights Reserved. +# +# This software, including source code, documentation and related +# materials ("Software"), is owned by Cypress Semiconductor Corporation +# or one of its subsidiaries ("Cypress") and is protected by and subject to +# worldwide patent protection (United States and foreign), +# United States copyright laws and international treaty provisions. +# Therefore, you may use this Software only as provided in the license +# agreement accompanying the software package from which you +# obtained this Software ("EULA"). +# If no EULA applies, Cypress hereby grants you a personal, non-exclusive, +# non-transferable license to copy, modify, and compile the Software +# source code solely for use in connection with Cypress's +# integrated circuit products. Any reproduction, modification, translation, +# compilation, or representation of this Software except as specified +# above is prohibited without the express written permission of Cypress. +# +# Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO WARRANTY OF ANY KIND, +# EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress +# reserves the right to make changes to the Software without notice. Cypress +# does not assume any liability arising out of the application or use of the +# Software or any product or circuit described in the Software. Cypress does +# not authorize its products for use in any products where a malfunction or +# failure of the Cypress product may reasonably be expected to result in +# significant property damage, injury or death ("High Risk Product"). By +# including Cypress's product in a High Risk Product, the manufacturer +# of such system or application assumes all risk of such use and in doing +# so agrees to indemnify Cypress against all liability. +# + +if (! $ARGV[0] ) +{ + print "Usage ./text_to_resource__c.pl "; + exit; +} + +# Print start of output +my $location = shift @ARGV; +my $variable_name = shift @ARGV; +my $original_variable_name = $variable_name; +my $file = shift @ARGV; + +#open the file +open INFILE, "<:raw", $file or die "cant open " . $file; +@file_cont_array = ; +close INFILE; +$file_cont = join('',@file_cont_array); + + +print "#include \"cy_abs_resource.h\"\n"; +print "\n"; + +my $pos = 0; + +if ( ( $file =~ m/\.html$/sgi ) || + ( $file =~ m/\.txt$/sgi ) ) +{ + while ( $file_cont =~ s/^(.*?)\r?\n?\\r?\n?(.*)$/$3/sgi ) + { + my $substr = $1; + my $variable_suffix = $2; + my $nextpos = $-[3]; + + print "\n"; + if ( $location ne "MEM" ) + { + $name = $file; + $name=~s/^.+\/(.*?)/$1/; + print "const cy_resource_handle_t ${variable_name} = { CY_RESOURCE_IN_FILESYSTEM, " . (length( $substr )) . ", { .fs = { $pos, \"$name\" }}};\n"; + print "\n"; + } + else + { + print "const uint8_t ${variable_name}_data[" . (length( $substr )+1) . "] = "; + my $section_length = length( $substr ); + while ( $substr =~ s/^(.*?\n)(.*)$/$2/sgi ) + { + print "\"" . escape_string( $1 ) . "\" \\\n"; + } + print "\"" . escape_string( $substr ) . "\";\n"; + + print "const cy_resource_handle_t ${variable_name} = { CY_RESOURCE_IN_MEMORY, $section_length, { .mem_data = ${variable_name}_data}};"; + print "\n"; + } + + $variable_name = $original_variable_name . $variable_suffix; + $pos += $nextpos; + } +} + +if ( $location ne "MEM" ) +{ + print "\n"; + $name = $file; + $name=~s/^.+\/(.*?)/$1/; + print "const cy_resource_handle_t ${variable_name} = { CY_RESOURCE_IN_FILESYSTEM, " . (length( $file_cont )) . ", { .fs = { $pos, \"$name\" }}};\n"; + print "\n"; +} +else +{ + print "const uint8_t ${variable_name}_data[" . (length( $file_cont ) + 1) . "] = "; + my $section_length = length( $file_cont ); + while ( $file_cont =~ s/^(.*?\n)(.*)$/$2/sgi ) + { + print "\"" . escape_string( $1 ) . "\" \\\n"; + } + print "\"" . escape_string( $file_cont ) . "\";\n"; + print "const cy_resource_handle_t ${variable_name} = { CY_RESOURCE_IN_MEMORY, $section_length, { .mem_data = ${variable_name}_data }};"; + print "\n"; +} + +sub escape_string( $escstring ) +{ + my $escstring = shift; + # Escape characters for C string + $escstring =~ s/\\/\\\\/sgi; # backslash + $escstring =~ s/\a/\\a/sgi; # bell + $escstring =~ s/\x8/\\b/sgi; # backspace + $escstring =~ s/\f/\\f/sgi; # formfeed + $escstring =~ s/\n/\\n/sgi; # linefeed + $escstring =~ s/\r/\\r/sgi; # carriage return + $escstring =~ s/\t/\\t/sgi; # tab + $escstring =~ s/\xB/\\v/sgi; # vertical tab + $escstring =~ s/\'/\\'/sgi; # single quote + $escstring =~ s/\"/\\"/sgi; # double quote + return $escstring; +} diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/vscode/c_cpp_properties_GCC_ARM.json b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/vscode/c_cpp_properties_GCC_ARM.json new file mode 100644 index 0000000000000000000000000000000000000000..3d2d96fd937e31bca4be837fa692028d93b252d5 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/vscode/c_cpp_properties_GCC_ARM.json @@ -0,0 +1,71 @@ +{ + "configurations": [ + { + "name": "Win32", + "includePath": [ + &&JSONINCLUDELIST&& + "&&MODUSTOOLCHAIN&&/lib/gcc/arm-none-eabi/&&MODUSTOOLCHAINVERSION&&/include", + "&&MODUSTOOLCHAIN&&/lib/gcc/arm-none-eabi/&&MODUSTOOLCHAINVERSION&&/include-fixed", + "&&MODUSTOOLCHAIN&&/arm-none-eabi/include", + "&&MODUSTOOLCHAIN&&/arm-none-eabi/include/c++/&&MODUSTOOLCHAINVERSION&&", + "&&MODUSTOOLCHAIN&&/arm-none-eabi/include/c++/&&MODUSTOOLCHAINVERSION&&/arm-none-eabi/thumb/v7e-m/fpv4-sp/hard", + "&&MODUSTOOLCHAIN&&/arm-none-eabi/include/c++/&&MODUSTOOLCHAINVERSION&&/backward" + ], + "browse": { + "path": [ + &&JSONINCLUDELIST&& + "&&MODUSTOOLCHAIN&&/lib/gcc/arm-none-eabi/&&MODUSTOOLCHAINVERSION&&/include", + "&&MODUSTOOLCHAIN&&/lib/gcc/arm-none-eabi/&&MODUSTOOLCHAINVERSION&&/include-fixed", + "&&MODUSTOOLCHAIN&&/arm-none-eabi/include", + "&&MODUSTOOLCHAIN&&/arm-none-eabi/include/c++/&&MODUSTOOLCHAINVERSION&&", + "&&MODUSTOOLCHAIN&&/arm-none-eabi/include/c++/&&MODUSTOOLCHAINVERSION&&/arm-none-eabi/thumb/v7e-m/fpv4-sp/hard", + "&&MODUSTOOLCHAIN&&/arm-none-eabi/include/c++/&&MODUSTOOLCHAINVERSION&&/backward" + ], + "limitSymbolsToIncludedHeaders": true, + "databaseFilename": "" + }, + "defines": [ + &&JSONDEFINELIST&& + "EMPTY_ENTRY" + ], + "intelliSenseMode": "clang-x64", + "compilerPath": "&&MODUSTOOLCHAIN&&/bin/arm-none-eabi-gcc.exe -mcpu=cortex-m4 -mthumb -mfloat-abi=soft", + "cStandard": "c99", + "cppStandard": "c++11" + }, + { + "name": "macOS", + "includePath": [ + &&JSONINCLUDELIST&& + "&&MODUSTOOLCHAIN&&/lib/gcc/arm-none-eabi/&&MODUSTOOLCHAINVERSION&&/include", + "&&MODUSTOOLCHAIN&&/lib/gcc/arm-none-eabi/&&MODUSTOOLCHAINVERSION&&/include-fixed", + "&&MODUSTOOLCHAIN&&/arm-none-eabi/include", + "&&MODUSTOOLCHAIN&&/arm-none-eabi/include/c++/&&MODUSTOOLCHAINVERSION&&", + "&&MODUSTOOLCHAIN&&/arm-none-eabi/include/c++/&&MODUSTOOLCHAINVERSION&&/arm-none-eabi/thumb/v7e-m/fpv4-sp/hard", + "&&MODUSTOOLCHAIN&&/arm-none-eabi/include/c++/&&MODUSTOOLCHAINVERSION&&/backward" + ], + "browse": { + "path": [ + &&JSONINCLUDELIST&& + "&&MODUSTOOLCHAIN&&/lib/gcc/arm-none-eabi/&&MODUSTOOLCHAINVERSION&&/include", + "&&MODUSTOOLCHAIN&&/lib/gcc/arm-none-eabi/&&MODUSTOOLCHAINVERSION&&/include-fixed", + "&&MODUSTOOLCHAIN&&/arm-none-eabi/include", + "&&MODUSTOOLCHAIN&&/arm-none-eabi/include/c++/&&MODUSTOOLCHAINVERSION&&", + "&&MODUSTOOLCHAIN&&/arm-none-eabi/include/c++/&&MODUSTOOLCHAINVERSION&&/arm-none-eabi/thumb/v7e-m/fpv4-sp/hard", + "&&MODUSTOOLCHAIN&&/arm-none-eabi/include/c++/&&MODUSTOOLCHAINVERSION&&/backward" + ], + "limitSymbolsToIncludedHeaders": true, + "databaseFilename": "" + }, + "defines": [ + &&JSONDEFINELIST&& + "EMPTY_ENTRY" + ], + "intelliSenseMode": "clang-x64", + "compilerPath": "&&MODUSTOOLCHAIN&&/bin/arm-none-eabi-gcc.exe -mcpu=cortex-m4 -mthumb -mfloat-abi=soft", + "cStandard": "c99", + "cppStandard": "c++11" + } + ], + "version": 4 +} diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/vscode/launch.json b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/vscode/launch.json new file mode 100644 index 0000000000000000000000000000000000000000..4ad1e853d71a3c69ca2ee31b9505df1ad5bff29b --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/vscode/launch.json @@ -0,0 +1,138 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Launch PSoC6 CM4 (OpenOCD)", + "type": "cortex-debug", + "request": "launch", + "cwd": "${workspaceRoot}", + "executable": "&&DEBUGTARGET&&", + "servertype": "openocd", + "searchDir": [ + "${workspaceRoot}", + "&&MODUSOPENCOD&&/scripts/" + ], + "configFiles": [ + "openocd.tcl" + ], + "overrideLaunchCommands": [ + "set mem inaccessible-by-default off", + "-enable-pretty-printing", + "monitor reset init", + "-target-download", // Comment this out if you don't want to reload program + "monitor reset run", + "monitor sleep 200", + "monitor psoc6 reset_halt sysresetreq" + ], + "postStartSessionCommands": [ // Needed if runToMain is false + /* + // Following two commands are needed to get gdb and openocd and HW all in sync. + // Or, execution context (PC, stack, registers, etc.) look like they are from before reset. + // The stepi, is a pretend instruction that does not actually do a stepi, but MUST be done + // Its a documented workaround in openocd. Do a 'monitor help' to see more info + // + // An alternative command to use is "continue" instead of the following two + */ + "monitor gdb_sync", + "stepi" + ], + "overrideRestartCommands": [ + "monitor reset init", + "monitor reset run", + "monitor sleep 200", + "monitor psoc6 reset_halt sysresetreq" + ], + "postRestartSessionCommands": [ + "monitor gdb_sync", + "stepi" + ], + // svdFile is optional, it can be very large. + "svdFile": "&&SVDFILENAME&&", + "runToMain": true, // if true, program will halt at main. Not used for a restart + "preLaunchTask": "", // Set this to run a task from tasks.json before starting a debug session + "showDevDebugOutput": false,// Shows output of GDB, helpful when something is not working right + }, + // When using 'attach', make sure your program is running on the board and that your executable matches + // the image in the chip exactly, or else strange things can happen with breakpoint, variables, etc. + { + "name": "Attach PSoC6 CM4 (OpenOCD)", + "type": "cortex-debug", + "request": "attach", + "cwd": "${workspaceRoot}", + "executable": "&&DEBUGTARGET&&", + "servertype": "openocd", + "searchDir": [ + "${workspaceRoot}", + "&&MODUSOPENCOD&&/scripts/" + ], + "openOCDPreConfigLaunchCommands": [ + "set ENABLE_ACQUIRE 0" + ], + "configFiles": [ + "openocd.tcl" + ], + "overrideAttachCommands": [ + "set mem inaccessible-by-default off", + "-enable-pretty-printing", + "monitor halt" + ], + "overrideRestartCommands": [ + "monitor reset init", + "monitor reset run", + "monitor sleep 200", + "monitor psoc6 reset_halt sysresetreq" + ], + "postRestartSessionCommands": [ + "monitor gdb_sync", + "stepi" + ], + // svdFile is optional, it can be very large. + "svdFile": "&&SVDFILENAME&&", + "showDevDebugOutput": false,// Shows output of GDB, helpful when something is not working right + }, + { + "name": "Erase (OpenOCD)", + "type": "cortex-debug", + "request": "launch", + "cwd": "${workspaceRoot}", + "executable": "&&DEBUGTARGET&&", + "servertype": "openocd", + "searchDir": [ + "${workspaceRoot}", + "&&MODUSOPENCOD&&/scripts/" + ], + "configFiles": [ + "openocd.tcl" + ], + "overrideLaunchCommands": [ + "monitor reset init", + "monitor psoc6 sflash_restrictions 1", + "monitor erase_all", + "-gdb-exit" + ] + }, + { + "name": "Program (OpenOCD)", + "type": "cortex-debug", + "request": "launch", + "cwd": "${workspaceRoot}", + "executable": "&&DEBUGTARGET&&", + "servertype": "openocd", + "searchDir": [ + "${workspaceRoot}", + "&&MODUSOPENCOD&&/scripts/" + ], + "configFiles": [ + "openocd.tcl" + ], + "overrideLaunchCommands": [ + "monitor psoc6 sflash_restrictions 1", + "monitor program {&&DEBUGTARGET&&}", + "monitor reset_config srst_only", + "monitor reset run", + "monitor psoc6.dap dpreg 0x04 0x00", + "-gdb-exit" + ], + } + ] +} diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/vscode/openocd.tcl b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/vscode/openocd.tcl new file mode 100644 index 0000000000000000000000000000000000000000..142b1bbd35fdcdcb8322a9ea09c1d671f4b73d60 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/vscode/openocd.tcl @@ -0,0 +1,4 @@ +source [find interface/kitprog3.cfg] +source [find target/&&OPENOCDFILE&&] +${TARGET}.cm0 configure -gdb-port disabled +${TARGET}.cm4 configure -rtos auto -rtos-wipe-on-reset-halt 1 diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/vscode/settings.json b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/vscode/settings.json new file mode 100644 index 0000000000000000000000000000000000000000..d612b0c4c3197aea61489fef9fa219dbedadbd56 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/vscode/settings.json @@ -0,0 +1,5 @@ +{ + "cortex-debug.armToolchainPath": "&&MODUSTOOLCHAIN&&/bin", + "cortex-debug.openocdPath": "&&MODUSOPENCOD&&/bin/openocd", + "cortex-debug.JLinkGDBServerPath": "", +} diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/vscode/tasks.json b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/vscode/tasks.json new file mode 100644 index 0000000000000000000000000000000000000000..034adfefc03dd5e2ae3edb5b001f4dedfe6b6274 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/scripts/vscode/tasks.json @@ -0,0 +1,325 @@ +{ + // See https://go.microsoft.com/fwlink/?LinkId=733558 + // for the documentation about the tasks.json format + "version": "2.0.0", + "tasks": [ + { + "label": "GetLibs", + "type": "shell", + "windows" : { + "command": "&&MODUSSHELL&&/bin/bash.exe" , + "args": [ + "--norc", + "-c", + "export PATH=/bin:/usr/bin ; &&MODUSSHELL&&/bin/make.exe getlibs" + ] + }, + "linux" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make getlibs" + ] + }, + "osx" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make getlibs" + ] + }, + "problemMatcher": [] + }, + { + "label": "Refresh", + "type": "shell", + "windows" : { + "command": "&&MODUSSHELL&&/bin/bash.exe" , + "args": [ + "--norc", + "-c", + "export PATH=/bin:/usr/bin ; &&MODUSSHELL&&/bin/make.exe vscode" + ] + }, + "linux" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make vscode" + ] + }, + "osx" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make vscode" + ] + }, + "problemMatcher": [] + }, + { + "label": "Build Debug", + "type": "shell", + + "windows" : { + "command": "&&MODUSSHELL&&/bin/bash.exe" , + "args": [ + "--norc", + "-c", + "export PATH=/bin:/usr/bin ; &&MODUSSHELL&&/bin/make.exe -j CONFIG=Debug build" + ] + }, + "linux" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make -j CONFIG=Debug build" + ] + }, + "osx" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make -j CONFIG=Debug build" + ] + }, + "problemMatcher": "$gcc", + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "Rebuild Debug", + "type": "shell", + + "windows" : { + "command": "&&MODUSSHELL&&/bin/bash.exe" , + "args": [ + "--norc", + "-c", + "export PATH=/bin:/usr/bin ; &&MODUSSHELL&&/bin/make.exe -j CONFIG=Debug clean ; &&MODUSSHELL&&/bin/make.exe -j CONFIG=Debug build" + ] + }, + "linux" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make -j CONFIG=Debug clean ; make -j CONFIG=Debug build" + ] + }, + "osx" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make -j CONFIG=Debug clean ; make -j CONFIG=Debug build" + ] + }, + "problemMatcher": "$gcc", + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "Clean Debug", + "type": "shell", + + "windows" : { + "command": "&&MODUSSHELL&&/bin/bash.exe" , + "args": [ + "--norc", + "-c", + "export PATH=/bin:/usr/bin ; &&MODUSSHELL&&/bin/make.exe -j CONFIG=Debug clean" + ] + }, + "linux" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make -j CONFIG=Debug clean" + ] + }, + "osx" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make -j CONFIG=Debug clean" + ] + }, + "problemMatcher": "$gcc", + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "Build Release", + "type": "shell", + "windows" : { + "command": "&&MODUSSHELL&&/bin/bash.exe" , + "args": [ + "--norc", + "-c", + "export PATH=/bin:/usr/bin ; &&MODUSSHELL&&/bin/make.exe -j CONFIG=Release build" + ] + }, + "linux" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make -j CONFIG=Release build" + ] + }, + "osx" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make -j CONFIG=Release build" + ] + }, + "problemMatcher": "$gcc", + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "Rebuild Release", + "type": "shell", + "windows" : { + "command": "&&MODUSSHELL&&/bin/bash.exe" , + "args": [ + "--norc", + "-c", + "export PATH=/bin:/usr/bin ; &&MODUSSHELL&&/bin/make.exe -j CONFIG=Release clean ; &&MODUSSHELL&&/bin/make.exe -j CONFIG=Release build" + ] + }, + "linux" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make -j CONFIG=Release clean ; make -j CONFIG=Release build" + ] + }, + "osx" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make -j CONFIG=Release clean ; make -j CONFIG=Release build" + ] + }, + "problemMatcher": "$gcc", + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "Clean Release", + "type": "shell", + "windows" : { + "command": "&&MODUSSHELL&&/bin/bash.exe" , + "args": [ + "--norc", + "-c", + "export PATH=/bin:/usr/bin ; &&MODUSSHELL&&/bin/make.exe -j CONFIG=Release clean" + ] + }, + "linux" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make -j CONFIG=Release clean" + ] + }, + "osx" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make -j CONFIG=Release clean" + ] + }, + "problemMatcher": "$gcc", + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "Base Configurator", + "type": "shell", + "windows" : { + "command": "&&MODUSSHELL&&/bin/bash.exe" , + "args": [ + "--norc", + "-c", + "export PATH=/bin:/usr/bin ; &&MODUSSHELL&&/bin/make.exe config" + ] + }, + "linux" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make config" + ] + }, + "osx" : { + "command": "bash", + "args": [ + "--norc", + "-c", + "make config" + ] + }, + "problemMatcher": "$gcc" + }, + { + "label": "Library Manager", + "type": "shell", + "windows" : { + "command": "&&MODUSLIBMANAGER&&/library-manager.exe", + "args" : [ + "-d", + "${workspaceRoot}" + ] + }, + "linux" : { + "command": "&&MODUSLIBMANAGER&&/library-manager", + "args" : [ + "-d", + "${workspaceRoot}" + ] + }, + "osx" : { + "command": "&&MODUSLIBMANAGER&&/library-manager -d ${workspaceRoot}", + "args" : [ + "-d", + "${workspaceRoot}" + ] + }, + "problemMatcher": "$gcc", + "group": { + "kind": "build", + "isDefault": true + } + } + ] +} diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/toolchains/ARM.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/toolchains/ARM.mk new file mode 100644 index 0000000000000000000000000000000000000000..7a2e9c2981f6123d16497cded0b9b9dd8a4caf97 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/toolchains/ARM.mk @@ -0,0 +1,168 @@ +############################################################################### +# \file ARM.mk +# \version 1.0 +# +# \brief +# ARM Compiler (Clang) toolchain configuration. +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + +# +# The base path to the ARM Compiler (Clang) cross compilation executables +# +ifeq ($(CY_COMPILER_PATH),) +CY_CROSSPATH=$(CY_COMPILER_ARM_DIR)/bin +else +CY_CROSSPATH=$(CY_COMPILER_PATH)/bin +endif + +# +# Build tools +# +CC=$(CY_CROSSPATH)/armclang +CXX=$(CC) +AS=$(CY_CROSSPATH)/armasm +AR=$(CY_CROSSPATH)/armar +LD=$(CY_CROSSPATH)/armlink + +# +# DEBUG/NDEBUG selection +# +ifeq ($(CONFIG),Debug) +CY_TOOLCHAIN_DEBUG_FLAG=-DDEBUG +CY_TOOLCHAIN_OPTIMIZATION=-O1 +else +ifeq ($(CONFIG),Release) +CY_TOOLCHAIN_DEBUG_FLAG=-DNDEBUG +CY_TOOLCHAIN_OPTIMIZATION=-Oz +else +CY_TOOLCHAIN_DEBUG_FLAG= +CY_TOOLCHAIN_OPTIMIZATION= +endif +endif + +# +# Flags common to compile and link +# +CY_TOOLCHAIN_COMMON_FLAGS=--target=arm-arm-none-eabi + +# +# CPU core specifics +# +ifeq ($(CORE),CM0P) +CY_TOOLCHAIN_CFLAGS_CORE=-mcpu=cortex-m0plus +CY_TOOLCHAIN_FLAGS_CORE=--cpu=Cortex-M0plus +CY_TOOLCHAIN_VFP_FLAGS= +else +CY_TOOLCHAIN_CFLAGS_CORE=-mcpu=cortex-m4 +CY_TOOLCHAIN_FLAGS_CORE=--cpu=Cortex-M4 +ifeq ($(VFP_SELECT),hardfp) +CY_TOOLCHAIN_VFP_CFLAGS=-mfloat-abi=hard -mfpu=fpv4-sp-d16 +CY_TOOLCHAIN_VFP_FLAGS=--fpu=FPv4-SP +else +CY_TOOLCHAIN_VFP_CFLAGS=-mfloat-abi=softfp -mfpu=fpv4-sp-d16 +CY_TOOLCHAIN_VFP_FLAGS=--fpu=SoftVFP+FPv4-SP +endif +endif + +# +# Command line flags for c-files +# +CY_TOOLCHAIN_CFLAGS=\ + -c\ + $(CY_TOOLCHAIN_CFLAGS_CORE)\ + $(CY_TOOLCHAIN_OPTIMIZATION)\ + $(CY_TOOLCHAIN_VFP_CFLAGS)\ + $(CY_TOOLCHAIN_COMMON_FLAGS)\ + -g\ + -fshort-enums\ + -fshort-wchar + +# +# Command line flags for cpp-files +# +CY_TOOLCHAIN_CXXFLAGS=$(CY_TOOLCHAIN_CFLAGS) + +# +# Command line flags for s-files +# +CY_TOOLCHAIN_ASFLAGS=\ + $(CY_TOOLCHAIN_FLAGS_CORE)\ + $(CY_TOOLCHAIN_VFP_FLAGS) + +# +# Command line flags for linking +# +CY_TOOLCHAIN_LDFLAGS=\ + $(CY_TOOLCHAIN_FLAGS_CORE)\ + $(CY_TOOLCHAIN_VFP_FLAGS)\ + --info=totals\ + --stdlib=libc++ + +# +# Command line flags for archiving +# +CY_TOOLCHAIN_ARFLAGS=-rvs + +# +# Toolchain-specific suffixes +# +CY_TOOLCHAIN_SUFFIX_S=S +CY_TOOLCHAIN_SUFFIX_s=s +CY_TOOLCHAIN_SUFFIX_C=c +CY_TOOLCHAIN_SUFFIX_H=h +CY_TOOLCHAIN_SUFFIX_CPP=cpp +CY_TOOLCHAIN_SUFFIX_HPP=hpp +CY_TOOLCHAIN_SUFFIX_O=o +CY_TOOLCHAIN_SUFFIX_A=ar +CY_TOOLCHAIN_SUFFIX_D=d +CY_TOOLCHAIN_SUFFIX_LS=sct +CY_TOOLCHAIN_SUFFIX_MAP=map +CY_TOOLCHAIN_SUFFIX_TARGET=elf +CY_TOOLCHAIN_SUFFIX_ARCHIVE=ar + +# +# Toolchain specific flags +# +CY_TOOLCHAIN_OUTPUT_OPTION=-o +CY_TOOLCHAIN_MAPFILE=--map --list +CY_TOOLCHAIN_LSFLAGS=--scatter +CY_TOOLCHAIN_INCRSPFILE=@ +CY_TOOLCHAIN_INCRSPFILE_ASM=--via +CY_TOOLCHAIN_OBJRSPFILE=--via + +# +# Produce a makefile dependency rule for each input file +# +CY_TOOLCHAIN_DEPENDENCIES=-MMD -MP -MF "$(subst .$(CY_TOOLCHAIN_SUFFIX_O),.$(CY_TOOLCHAIN_SUFFIX_D),$@)" -MT "$@" + +# +# Additional includes in the compilation process based on this +# toolchain +# +CY_TOOLCHAIN_INCLUDES= + +# +# Additional libraries in the link process based on this toolchain +# +CY_TOOLCHAIN_DEFINES= diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/toolchains/A_Clang.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/toolchains/A_Clang.mk new file mode 100644 index 0000000000000000000000000000000000000000..45bd0cc294f76549599f507c3c755d19bd3dc38d --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/toolchains/A_Clang.mk @@ -0,0 +1,218 @@ +################################################################################ +# \file AppleClang.mk +# \version 1.0 +# +# \brief +# Apple Clang toolchain configuration +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + +# +# The base path to the Clang cross compilation executables +# +ifeq ($(CY_COMPILER_PATH),) +CY_CROSSPATH=$(CY_COMPILER_A_Clang_DIR) +else +CY_CROSSPATH=$(CY_COMPILER_PATH) +endif + +# +# Build tools +# +CC=clang +CXX=$(CC) +AS=$(CC) +AR=libtool +LD=ld + +# +# DEBUG/NDEBUG selection +# +ifeq ($(CONFIG),Debug) +CY_TOOLCHAIN_DEBUG_FLAG=-DDEBUG +CY_TOOLCHAIN_OPTIMIZATION=-Og +else ifeq ($(CONFIG),Release) +CY_TOOLCHAIN_DEBUG_FLAG=-DNDEBUG +CY_TOOLCHAIN_OPTIMIZATION=-Os +else +CY_TOOLCHAIN_DEBUG_FLAG= +CY_TOOLCHAIN_OPTIMIZATION= +endif + +# +# Flags common to compile and link +# +CY_TOOLCHAIN_COMMON_FLAGS=\ + -mthumb\ + -ffunction-sections\ + -fdata-sections\ + -g\ + -Wall + +# +# CPU core specifics +# +ifeq ($(CORE),CM0P) +CY_TOOLCHAIN_FLAGS_CORE=\ + -arch armv6m\ + -mcpu=cortex-m0plus\ + --target=arm-none-macho +CY_TOOLCHAIN_LDFLAGS_CORE=\ + -arch armv6m\ + -lclang_rt.soft_static +CY_TOOLCHAIN_VFP_FLAGS= +else +ifeq ($(VFP_SELECT),hardfp) +CY_TOOLCHAIN_LD_VFP_FLAGS=-lclang_rt.hard_static +CY_TOOLCHAIN_VFP_FLAGS=-mfloat-abi=hard -mfpu=fpv4-sp-d16 +else +CY_TOOLCHAIN_LD_VFP_FLAGS=-lclang_rt.soft_static +CY_TOOLCHAIN_VFP_FLAGS=-mfloat-abi=softfp -mfpu=fpv4-sp-d16 +endif # ($(VFP_SELECT),hardfp) +CY_TOOLCHAIN_FLAGS_CORE=\ + -arch armv7em\ + -mcpu=cortex-m4\ + --target=armv7m-none-macho +CY_TOOLCHAIN_LDFLAGS_CORE=\ + -arch armv7em\ + $(CY_TOOLCHAIN_LD_VFP_FLAGS) +endif # ($(CORE),CM0P) + +# +# Command line flags for c-files +# +CY_TOOLCHAIN_CFLAGS=\ + -c\ + $(CY_TOOLCHAIN_FLAGS_CORE)\ + $(CY_TOOLCHAIN_OPTIMIZATION)\ + $(CY_TOOLCHAIN_VFP_FLAGS)\ + $(CY_TOOLCHAIN_COMMON_FLAGS)\ + --no-standard-includes\ + -fasm-blocks\ + -integrated-as\ + -Wall\ + -Wno-int-to-pointer-cast\ + -static\ + -fno-stack-protector\ + -fno-common\ + -ffreestanding\ + -mlong-calls + +# +# Command line flags for cpp-files +# +CY_TOOLCHAIN_CXXFLAGS=$(CY_TOOLCHAIN_CFLAGS) + +# +# Command line flags for s-files +# +CY_TOOLCHAIN_ASFLAGS=\ + -c\ + $(CY_TOOLCHAIN_FLAGS_CORE)\ + $(CY_TOOLCHAIN_COMMON_FLAGS)\ + -fasm-blocks\ + -integrated-as\ + -Wall\ + -Wno-int-to-pointer-cast\ + -static\ + -fno-stack-protector\ + -fno-common\ + -ffreestanding\ + -mlong-calls + +# +# Command line flags for linking +# +CY_TOOLCHAIN_LDFLAGS=\ + $(CY_TOOLCHAIN_LDFLAGS_CORE)\ + $(CY_TOOLCHAIN_LD_VFP_FLAGS)\ + -static\ + -segalign 4\ + -e Reset_Handler\ + -merge_zero_fill_sections\ + -pagezero_size 0\ + -ios_version_min 4.3\ + -preload\ + -v\ + -read_only_relocs suppress\ + -dead_strip\ + -dead_strip_dylibs\ + -no_branch_islands\ + -no_zero_fill_sections\ + -L$(CY_CROSSPATH)/lib/macho_embedded + +# +# Command line flags for archiving +# +CY_TOOLCHAIN_ARFLAGS=rvs + +# +# Toolchain-specific suffixes +# +CY_TOOLCHAIN_SUFFIX_S=S +CY_TOOLCHAIN_SUFFIX_s=s +CY_TOOLCHAIN_SUFFIX_C=c +CY_TOOLCHAIN_SUFFIX_H=h +CY_TOOLCHAIN_SUFFIX_CPP=cpp +CY_TOOLCHAIN_SUFFIX_HPP=hpp +CY_TOOLCHAIN_SUFFIX_O=o +CY_TOOLCHAIN_SUFFIX_A=a +CY_TOOLCHAIN_SUFFIX_D=d +CY_TOOLCHAIN_SUFFIX_LS=mk +CY_TOOLCHAIN_SUFFIX_MAP=map +CY_TOOLCHAIN_SUFFIX_TARGET=mach_o +CY_TOOLCHAIN_SUFFIX_ARCHIVE=a + +# +# Toolchain specific flags +# +CY_TOOLCHAIN_OUTPUT_OPTION=-o +CY_TOOLCHAIN_MAPFILE=-map +CY_TOOLCHAIN_LSFLAGS= +CY_TOOLCHAIN_INCRSPFILE=@ +CY_TOOLCHAIN_INCRSPFILE_ASM=@ +CY_TOOLCHAIN_OBJRSPFILE=-filelist + +# +# Produce a makefile dependency rule for each input file +# +CY_TOOLCHAIN_DEPENDENCIES=-MMD -MP -MF "$(subst .$(CY_TOOLCHAIN_SUFFIX_O),.$(CY_TOOLCHAIN_SUFFIX_D),$@)" -MT "$@" + +# +# Additional includes in the compilation process based on this +# toolchain +# +CY_TOOLCHAIN_INCLUDES=\ + $(CY_COMPILER_GCC_ARM_DIR)/arm-none-eabi/include\ + $(CY_COMPILER_GCC_ARM_DIR)/lib/gcc/arm-none-eabi/7.2.1/include\ + $(CY_COMPILER_GCC_ARM_DIR)/lib/gcc/arm-none-eabi/7.2.1/include-fixed + +# +# Additional libraries in the link process based on this toolchain +# +CY_TOOLCHAIN_DEFINES= + +# +# M2BIN tool is used to convert Mach-O to binary +# +CY_TOOLCHAIN_M2BIN=$(CY_BASELIB_PATH)/make/scripts/m2bin diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/toolchains/GCC_ARM.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/toolchains/GCC_ARM.mk new file mode 100644 index 0000000000000000000000000000000000000000..52ec8bcaa57562ee02348623a50646b8c292d54b --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/toolchains/GCC_ARM.mk @@ -0,0 +1,174 @@ +################################################################################ +# \file GCC_ARM.mk +# \version 1.0 +# +# \brief +# GCC ARM toolchain configuration. +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + +# +# The base path to the GCC cross compilation executables +# +ifeq ($(CY_COMPILER_PATH),) +CY_CROSSPATH=$(CY_COMPILER_GCC_ARM_DIR)/bin +else +CY_CROSSPATH=$(CY_COMPILER_PATH)/bin +endif + +# +# Build tools +# +CC=$(CY_CROSSPATH)/arm-none-eabi-gcc +CXX=$(CY_CROSSPATH)/arm-none-eabi-g++ +AS=$(CC) +AR=$(CY_CROSSPATH)/arm-none-eabi-ar +LD=$(CXX) + +# +# DEBUG/NDEBUG selection +# +ifeq ($(CONFIG),Debug) +CY_TOOLCHAIN_DEBUG_FLAG=-DDEBUG +CY_TOOLCHAIN_OPTIMIZATION=-Og +else ifeq ($(CONFIG),Release) +CY_TOOLCHAIN_DEBUG_FLAG=-DNDEBUG +CY_TOOLCHAIN_OPTIMIZATION=-Os +else +CY_TOOLCHAIN_DEBUG_FLAG= +CY_TOOLCHAIN_OPTIMIZATION= +endif + +# +# Flags common to compile and link +# +CY_TOOLCHAIN_COMMON_FLAGS=\ + -mthumb\ + -ffunction-sections\ + -fdata-sections\ + -ffat-lto-objects\ + -g\ + -Wall + +# +# CPU core specifics +# +ifeq ($(CORE),CM0P) +CY_TOOLCHAIN_FLAGS_CORE=-mcpu=cortex-m0plus +CY_TOOLCHAIN_VFP_FLAGS= +else +CY_TOOLCHAIN_FLAGS_CORE=-mcpu=cortex-m4 +ifeq ($(VFP_SELECT),hardfp) +CY_TOOLCHAIN_VFP_FLAGS=-mfloat-abi=hard -mfpu=fpv4-sp-d16 +else +CY_TOOLCHAIN_VFP_FLAGS=-mfloat-abi=softfp -mfpu=fpv4-sp-d16 +endif +endif + +# +# Command line flags for c-files +# +CY_TOOLCHAIN_CFLAGS=\ + -c\ + $(CY_TOOLCHAIN_FLAGS_CORE)\ + $(CY_TOOLCHAIN_OPTIMIZATION)\ + $(CY_TOOLCHAIN_VFP_FLAGS)\ + $(CY_TOOLCHAIN_COMMON_FLAGS) + +# +# Command line flags for cpp-files +# +CY_TOOLCHAIN_CXXFLAGS=\ + $(CY_TOOLCHAIN_CFLAGS)\ + -fno-rtti\ + -fno-exceptions + +# +# Command line flags for s-files +# +CY_TOOLCHAIN_ASFLAGS=\ + -c\ + $(CY_TOOLCHAIN_FLAGS_CORE)\ + $(CY_TOOLCHAIN_COMMON_FLAGS) + +# +# Command line flags for linking +# +CY_TOOLCHAIN_LDFLAGS=\ + $(CY_TOOLCHAIN_FLAGS_CORE)\ + $(CY_TOOLCHAIN_VFP_FLAGS)\ + $(CY_TOOLCHAIN_COMMON_FLAGS)\ + --enable-objc-gc\ + --specs=nano.specs\ + -Wl,--gc-sections + +# +# Command line flags for archiving +# +CY_TOOLCHAIN_ARFLAGS=rvs + +# +# Toolchain-specific suffixes +# +CY_TOOLCHAIN_SUFFIX_S=S +CY_TOOLCHAIN_SUFFIX_s=s +CY_TOOLCHAIN_SUFFIX_C=c +CY_TOOLCHAIN_SUFFIX_H=h +CY_TOOLCHAIN_SUFFIX_CPP=cpp +CY_TOOLCHAIN_SUFFIX_HPP=hpp +CY_TOOLCHAIN_SUFFIX_O=o +CY_TOOLCHAIN_SUFFIX_A=a +CY_TOOLCHAIN_SUFFIX_D=d +CY_TOOLCHAIN_SUFFIX_LS=ld +CY_TOOLCHAIN_SUFFIX_MAP=map +CY_TOOLCHAIN_SUFFIX_TARGET=elf +CY_TOOLCHAIN_SUFFIX_ARCHIVE=a + +# +# Toolchain specific flags +# +CY_TOOLCHAIN_OUTPUT_OPTION=-o +CY_TOOLCHAIN_MAPFILE=-Wl,-Map, +CY_TOOLCHAIN_STARTGROUP=-Wl,--start-group +CY_TOOLCHAIN_ENDGROUP=-Wl,--end-group +CY_TOOLCHAIN_LSFLAGS=-T +CY_TOOLCHAIN_INCRSPFILE=@ +CY_TOOLCHAIN_INCRSPFILE_ASM=@ +CY_TOOLCHAIN_OBJRSPFILE=@ + +# +# Produce a makefile dependency rule for each input file +# +CY_TOOLCHAIN_DEPENDENCIES=-MMD -MP -MF "$(subst .$(CY_TOOLCHAIN_SUFFIX_O),.$(CY_TOOLCHAIN_SUFFIX_D),$@)" -MT "$@" + +# +# Additional includes in the compilation process based on this +# toolchain +# +CY_TOOLCHAIN_INCLUDES= + +# +# Additional libraries in the link process based on this toolchain +# +CY_TOOLCHAIN_DEFINES= + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/toolchains/IAR.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/toolchains/IAR.mk new file mode 100644 index 0000000000000000000000000000000000000000..64c5155ee5c83e1c121a51b3ebd2f4ab462b06dd --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/toolchains/IAR.mk @@ -0,0 +1,187 @@ +################################################################################ +# \file IAR.mk +# \version 1.0 +# +# \brief +# IAR toolchain configuration. +# +################################################################################ +# \copyright +# Copyright 2018-2019 Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +################################################################################ + +ifeq ($(WHICHFILE),true) +$(info Processing $(lastword $(MAKEFILE_LIST))) +endif + +# +# The base path to the IAR cross compilation executables +# +ifeq ($(CY_COMPILER_PATH),) +CY_CROSSPATH=$(CY_COMPILER_IAR_DIR)/bin +else +CY_CROSSPATH=$(CY_COMPILER_PATH)/bin +endif + +# +# Build tools +# +CC=$(CY_CROSSPATH)/iccarm.exe +CXX=$(CC) +AS=$(CY_CROSSPATH)/iasmarm.exe +AR=$(CY_CROSSPATH)/iarchive.exe +LD=$(CY_CROSSPATH)/ilinkarm.exe + +# +# DEBUG/NDEBUG selection +# +ifeq ($(CONFIG),Debug) +CY_TOOLCHAIN_DEBUG_FLAG=-DDEBUG +CY_TOOLCHAIN_OPTIMIZATION=-Ol +else +ifeq ($(CONFIG),Release) +CY_TOOLCHAIN_DEBUG_FLAG=-DNDEBUG +CY_TOOLCHAIN_OPTIMIZATION=-Ohs +else +CY_TOOLCHAIN_DEBUG_FLAG= +CY_TOOLCHAIN_OPTIMIZATION= +endif +endif + +# +# Flags common to compile and link +# +ifneq ($(VERBOSE),) +CY_TOOLCHAIN_SILENT_CFLAGS= +CY_TOOLCHAIN_SILENT_SFLAGS= +else +CY_TOOLCHAIN_SILENT_CFLAGS=--silent +CY_TOOLCHAIN_SILENT_SFLAGS=-S +endif + +# +# CPU core specifics +# +ifeq ($(CORE),CM0P) +CY_TOOLCHAIN_FLAGS_CORE=--cpu Cortex-M0+ +CY_TOOLCHAIN_VFP_FLAGS= +else +CY_TOOLCHAIN_FLAGS_CORE=--cpu Cortex-M4 +CY_TOOLCHAIN_VFP_FLAGS=--fpu FPv4-SP +ifeq ($(VFP_SELECT),hardfp) +CY_TOOLCHAIN_VFP_CFLAGS=$(CY_TOOLCHAIN_VFP_FLAGS) --aapcs vfp +else +CY_TOOLCHAIN_VFP_CFLAGS=$(CY_TOOLCHAIN_VFP_FLAGS) --aapcs std +endif +endif + +# +# Command line flags for c-files +# +CY_TOOLCHAIN_CFLAGS=\ + -c\ + $(CY_TOOLCHAIN_FLAGS_CORE)\ + $(CY_TOOLCHAIN_OPTIMIZATION)\ + $(CY_TOOLCHAIN_VFP_CFLAGS)\ + $(CY_TOOLCHAIN_SILENT_CFLAGS)\ + --endian=little\ + -e\ + --enable_restrict\ + --no_wrap_diagnostics + +ifeq ($(CONFIG),Debug) +CY_TOOLCHAIN_CFLAGS+=--debug +endif + +# +# Command line flags for cpp-files +# +CY_TOOLCHAIN_CXXFLAGS=\ + $(CY_TOOLCHAIN_CFLAGS)\ + --c++\ + --no_rtti\ + --no_exceptions + +# +# Command line flags for s-files +# +CY_TOOLCHAIN_ASFLAGS=\ + -c\ + $(CY_TOOLCHAIN_FLAGS_CORE)\ + $(CY_TOOLCHAIN_VFP_FLAGS)\ + $(CY_TOOLCHAIN_SILENT_SFLAGS)\ + -s+\ + -w+\ + -r + +# +# Command line flags for linking +# +CY_TOOLCHAIN_LDFLAGS=\ + $(CY_TOOLCHAIN_FLAGS_CORE)\ + $(CY_TOOLCHAIN_VFP_FLAGS)\ + $(CY_TOOLCHAIN_SILENT_CFLAGS)\ + +# +# Command line flags for archiving +# +CY_TOOLCHAIN_ARFLAGS=\ + --create\ + --verbose + +# +# Toolchain-specific suffixes +# +CY_TOOLCHAIN_SUFFIX_S=S +CY_TOOLCHAIN_SUFFIX_s=s +CY_TOOLCHAIN_SUFFIX_C=c +CY_TOOLCHAIN_SUFFIX_H=h +CY_TOOLCHAIN_SUFFIX_CPP=cpp +CY_TOOLCHAIN_SUFFIX_HPP=hpp +CY_TOOLCHAIN_SUFFIX_O=o +CY_TOOLCHAIN_SUFFIX_A=a +CY_TOOLCHAIN_SUFFIX_D=d +CY_TOOLCHAIN_SUFFIX_LS=icf +CY_TOOLCHAIN_SUFFIX_MAP=map +CY_TOOLCHAIN_SUFFIX_TARGET=elf +CY_TOOLCHAIN_SUFFIX_ARCHIVE=a + +# +# Toolchain specific flags +# +CY_TOOLCHAIN_OUTPUT_OPTION=-o +CY_TOOLCHAIN_MAPFILE=--map= +CY_TOOLCHAIN_LSFLAGS=--config= +CY_TOOLCHAIN_INCRSPFILE=-f +CY_TOOLCHAIN_INCRSPFILE_ASM=-f +CY_TOOLCHAIN_OBJRSPFILE=-f + +# +# Produce a makefile dependency rule for each input file +# +CY_TOOLCHAIN_DEPENDENCIES=--dependencies=m "$(subst .$(CY_TOOLCHAIN_SUFFIX_O),.$(CY_TOOLCHAIN_SUFFIX_D),$@)" + +# +# Additional includes in the compilation process based on this +# toolchain +# +CY_TOOLCHAIN_INCLUDES= + +# +# Additional libraries in the link process based on this toolchain +# +CY_TOOLCHAIN_DEFINES= + diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/udd/features.mk b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/udd/features.mk new file mode 100644 index 0000000000000000000000000000000000000000..d5e95c02870a1a248d8166450aba50235a31b866 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/make/udd/features.mk @@ -0,0 +1,45 @@ +# This file defines variables for various sets of devices. Each variable is a +# list of the MPNs that have that capability or feature. + +# Major device capabilities. +CY_DEVICES_WITH_M0P=CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 +CY_DEVICES_WITH_BLE=CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 +CY_DEVICES_WITH_UDBS=CY8C6116BZI-F54 CY8C6136BZI-F34 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C6247FDI-D32 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6347LQI-BLD52 +CY_DEVICES_WITH_FS_USB=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 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CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 +CY_DEVICES_WITH_CAPSENSE=CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245W-S3D72 +CY_DEVICES_WITH_CRYPTO=CY8C6116BZI-F54 CY8C6137BZI-F54 CY8C6247BZI-D44 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6347BZI-BLD43 CY8C6347BZI-BLD53 CY8C6347FMI-BLD43 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6347BZI-BUD43 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD43 CY8C6137WI-F54 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245W-S3D72 + +# Different classifications of devices. +CY_DEVICES_WITH_DIE_PSOC6ABLE2=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 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CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 +CY_DEVICES_WITH_FLASH_KB_1024=CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CY8C6347LQI-BLD52 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 +CY_DEVICES_WITH_FLASH_KB_832=CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 +CY_DEVICES_WITH_FLASH_KB_2048=CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C624ALQI-D42 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 +CY_DEVICES_WITH_FLASH_KB_1856=CYB0644ABZI-S2D44 + +CY_DEVICES_WITH_SRAM_KB_128=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6246BZI-D04 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6336BZI-BUD13 CY8C6136FDI-F42 CY8C6136FTI-F42 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 +CY_DEVICES_WITH_SRAM_KB_288=CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6347LQI-BLD52 +CY_DEVICES_WITH_SRAM_KB_1024=CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 +CY_DEVICES_WITH_SRAM_KB_512=CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 +CY_DEVICES_WITH_SRAM_KB_256=CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 + +CY_DEVICES_WITH_MAX_SPEED_MHZ_150=CY8C6036BZI-F04 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLF03 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 +CY_DEVICES_WITH_MAX_SPEED_MHZ_50=CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6117BZI-F34 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6117FDI-F02 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6117WI-F34 + +CY_DEVICES_WITH_PACKAGE_124-BGA=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C637BZI-MD76 CY8C6247BZI-AUD54 CY8C6247BFI-D54 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C6248BZI-D44 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C6248BZI-S2D44 +CY_DEVICES_WITH_PACKAGE_116-BGA-BLE=CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C637BZI-BLD74 CY8C68237BZ-BLE CY8C6337BZI-BLF13 CYB06447BZI-BLD53 +CY_DEVICES_WITH_PACKAGE_104-M-CSP-BLE=CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637FMI-BLD73 CY8C68237FM-BLE +CY_DEVICES_WITH_PACKAGE_80-WLCSP=CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 +CY_DEVICES_WITH_PACKAGE_116-BGA-USB=CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 +CY_DEVICES_WITH_PACKAGE_124-BGA-SIP=CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CYB06447BZI-BLD54 +CY_DEVICES_WITH_PACKAGE_43-SMT=CYBLE-416045-02 +CY_DEVICES_WITH_PACKAGE_104-M-CSP-BLE-USB=CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 +CY_DEVICES_WITH_PACKAGE_68-QFN-BLE=CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 +CY_DEVICES_WITH_PACKAGE_128-TQFP=CY8C624AAZI-D44 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248AZI-D44 CY8C624AAZI-S2D44 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248AZI-S2D44 +CY_DEVICES_WITH_PACKAGE_100-WLCSP=CY8C624AFNI-D43 CY8C6248FNI-D43 CY8C624AFNI-S2D43 CY8C6248FNI-S2D43 +CY_DEVICES_WITH_PACKAGE_68-QFN=CY8C624ALQI-D42 CY8C6245LQI-S3D72 CY8C6245LQI-S3D62 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245LQI-S3D12 CY8C6245LQI-S3D02 +CY_DEVICES_WITH_PACKAGE_100-TQFP=CY8C6245AZI-S3D72 CY8C6245AZI-S3D62 CY8C6245AZI-S3D42 CY8C6245AZI-S3D12 CY8C6245AZI-S3D02 CY8C6245W-S3D72 +CY_DEVICES_WITH_PACKAGE_49-WLCSP=CY8C6245FNI-S3D71 CY8C6245FNI-S3D41 CY8C6245FNI-S3D11 diff --git a/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/version.xml b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/version.xml new file mode 100644 index 0000000000000000000000000000000000000000..0c4180cb3d29e2661db19ba50e457d46a696547d --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/libs/psoc6make/version.xml @@ -0,0 +1 @@ +1.0.1.8025 diff --git a/bsp/cypress/psoc6-pioneerkit_modus/makefile.init b/bsp/cypress/psoc6-pioneerkit_modus/makefile.init new file mode 100644 index 0000000000000000000000000000000000000000..6721bdc2e2c0c40e01e674209f49168f6597d7e1 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/makefile.init @@ -0,0 +1,2 @@ +export MAKE=make +export PATH:=/usr/bin:$(PATH) diff --git a/bsp/cypress/psoc6-pioneerkit_modus/rtconfig.h b/bsp/cypress/psoc6-pioneerkit_modus/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..def5a08afffaf873727cefad90540f037e9fb6b4 --- /dev/null +++ b/bsp/cypress/psoc6-pioneerkit_modus/rtconfig.h @@ -0,0 +1,156 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 16 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +#define RT_USING_SIGNALS + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_SMALL_MEM +#define RT_USING_MEMTRACE +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40000 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_USING_PIN + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define RT_USING_UART0 + +#endif diff --git a/bsp/es32f0654/drivers/drv_pm.c b/bsp/es32f0654/drivers/drv_pm.c deleted file mode 100644 index aa2f07ec68a101a94d15ecec51908d4c9ffbe2ad..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/drivers/drv_pm.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-04-01 wangyq the first version - * 2019-05-06 Zero-Free adapt to the new power management interface - */ - -#include -#include -#include "board.h" -#include "drv_pm.h" -#include - -#ifdef RT_USING_PM - -static void _drv_pm_enter(struct rt_pm *pm, uint8_t mode) -{ - switch (mode) - { - case PM_SLEEP_MODE_NONE: - break; - - case PM_SLEEP_MODE_IDLE: - __WFI(); - break; - - case PM_SLEEP_MODE_LIGHT: - break; - - case PM_SLEEP_MODE_DEEP: - pmu_stop2_enter(); - break; - - case PM_SLEEP_MODE_STANDBY: - pmu_standby_enter(PMU_STANDBY_PORT_NONE); - break; - - case PM_SLEEP_MODE_SHUTDOWN: - break; - - default: - RT_ASSERT(0); - break; - } -} - -static int drv_hw_pm_init(void) -{ - static const struct rt_pm_ops _ops = - { - _drv_pm_enter, - RT_NULL, - RT_NULL, - RT_NULL, - RT_NULL - }; - - rt_uint8_t timer_mask = 0; - - /* initialize timer mask(no need tickless) */ - timer_mask = 1UL << PM_SLEEP_MODE_DEEP; - - /* initialize system pm module */ - rt_system_pm_init(&_ops, timer_mask, RT_NULL); - - return 0; -} -INIT_BOARD_EXPORT(drv_hw_pm_init); - -#endif diff --git a/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h b/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h deleted file mode 100644 index 07ca77b338dcb29fe2f2ca80840169db4d92bfe3..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h +++ /dev/null @@ -1,6665 +0,0 @@ -/** - ********************************************************************************* - * - * @file es32f065x.h - * @brief ES32F065x Device Head File - * - * @version V1.0 - * @date 07 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ES32F0XX_H__ -#define __ES32F0XX_H__ - - -#define __I volatile const /* defines 'read only' permissions */ -#define __O volatile /* defines 'write only' permissions */ -#define __IO volatile /* defines 'read / write' permissions */ - -#define __NVIC_PRIO_BITS 2 - -typedef enum IRQn { - /* Cortex-M0 processor cxceptions index */ - Reset_IRQn = -15, - NMI_IRQn = -14, - HardFault_IRQn = -13, - SVCall_IRQn = -5, - DebugMonitor_IRQn = -4, - PendSV_IRQn = -2, - SysTick_IRQn = -1, - - /* es32f0xx specific interrupt index */ - WWDG_IWDG_IRQn = 0, - LVD_IRQn = 1, - RTC_TEMP_IRQn = 2, - CRYPT_TRNG_IRQn = 3, - CMU_IRQn = 4, - EXTI0_3_IRQn = 5, - EXTI4_7_IRQn = 6, - EXTI8_11_IRQn = 7, - EXTI12_15_IRQn = 8, - DMA_IRQn = 9, - CAN0_IRQn = 10, - LPTIM0_SPI2_IRQn = 11, - ADC_ACMP_IRQn = 12, - AD16C4T0_BRK_UP_TRIG_COM_IRQn = 13, - AD16C4T0_CC_IRQn = 14, - BS16T0_IRQn = 15, - GP16C2T0_IRQn = 17, - GP16C2T1_IRQn = 18, - BS16T1_UART2_IRQn = 19, - BS16T2_UART3_IRQn = 20, - GP16C4T0_LCD_IRQn = 21, - BS16T3_DAC0_IRQn = 22, - I2C0_IRQn = 23, - I2C1_IRQn = 24, - SPI0_IRQn = 25, - SPI1_IRQn = 26, - UART0_IRQn = 27, - UART1_IRQn = 28, - USART0_IRQn = 29, - USART1_IRQn = 30, - LPUART0_IRQn = 31, -} IRQn_Type; - - -#include -#include "core_cm0.h" - -#if defined (__CC_ARM) -#pragma anon_unions -#endif - -/* Peripheral register define */ - -/****************** Bit definition for SYSCFG_PROT register ************************/ - -#define SYSCFG_PROT_KEY_POSS 1U -#define SYSCFG_PROT_KEY_POSE 31U -#define SYSCFG_PROT_KEY_MSK BITS(SYSCFG_PROT_KEY_POSS,SYSCFG_PROT_KEY_POSE) - -#define SYSCFG_PROT_PROT_POS 0U -#define SYSCFG_PROT_PROT_MSK BIT(SYSCFG_PROT_PROT_POS) - -/****************** Bit definition for SYSCFG_MEMRMP register ************************/ - -#define SYSCFG_MEMRMP_VTOEN_POS 16U -#define SYSCFG_MEMRMP_VTOEN_MSK BIT(SYSCFG_MEMRMP_VTOEN_POS) - -#define SYSCFG_MEMRMP_BFRMPEN_POS 8U -#define SYSCFG_MEMRMP_BFRMPEN_MSK BIT(SYSCFG_MEMRMP_BFRMPEN_POS) - -#define SYSCFG_MEMRMP_BRRMPEN_POS 0U -#define SYSCFG_MEMRMP_BRRMPEN_MSK BIT(SYSCFG_MEMRMP_BRRMPEN_POS) - -/****************** Bit definition for SYSCFG_VTOR register ************************/ - -#define SYSCFG_VTOR_VTO_POSS 0U -#define SYSCFG_VTOR_VTO_POSE 29U -#define SYSCFG_VTOR_VTO_MSK BITS(SYSCFG_VTOR_VTO_POSS,SYSCFG_VTOR_VTO_POSE) - -typedef struct -{ - __IO uint32_t PROT; - __IO uint32_t MEMRMP; - __IO uint32_t VTOR; -} SYSCFG_TypeDef; - -/****************** Bit definition for MSC_FLASHKEY register ************************/ - -#define MSC_FLASHKEY_STATUS_POSS 0U -#define MSC_FLASHKEY_STATUS_POSE 1U -#define MSC_FLASHKEY_STATUS_MSK BITS(MSC_FLASHKEY_STATUS_POSS,MSC_FLASHKEY_STATUS_POSE) - -/****************** Bit definition for MSC_INFOKEY register ************************/ - -#define MSC_INFOKEY_STATUS_POSS 0U -#define MSC_INFOKEY_STATUS_POSE 1U -#define MSC_INFOKEY_STATUS_MSK BITS(MSC_INFOKEY_STATUS_POSS,MSC_INFOKEY_STATUS_POSE) - -/****************** Bit definition for MSC_FLASHADDR register ************************/ - -#define MSC_FLASHADDR_IFREN_POS 18U -#define MSC_FLASHADDR_IFREN_MSK BIT(MSC_FLASHADDR_IFREN_POS) - -#define MSC_FLASHADDR_ADDR_POSS 0U -#define MSC_FLASHADDR_ADDR_POSE 17U -#define MSC_FLASHADDR_ADDR_MSK BITS(MSC_FLASHADDR_ADDR_POSS,MSC_FLASHADDR_ADDR_POSE) - -/****************** Bit definition for MSC_FLASHFIFO register ************************/ - -#define MSC_FLASHFIFO_FIFO_POSS 0U -#define MSC_FLASHFIFO_FIFO_POSE 31U -#define MSC_FLASHFIFO_FIFO_MSK BITS(MSC_FLASHFIFO_FIFO_POSS,MSC_FLASHFIFO_FIFO_POSE) - -/****************** Bit definition for MSC_FLASHDL register ************************/ - -#define MSC_FLASHDL_DATAL_POSS 0U -#define MSC_FLASHDL_DATAL_POSE 31U -#define MSC_FLASHDL_DATAL_MSK BITS(MSC_FLASHDL_DATAL_POSS,MSC_FLASHDL_DATAL_POSE) - -/****************** Bit definition for MSC_FLASHDH register ************************/ - -#define MSC_FLASHDH_DATAH_POSS 0U -#define MSC_FLASHDH_DATAH_POSE 31U -#define MSC_FLASHDH_DATAH_MSK BITS(MSC_FLASHDH_DATAH_POSS,MSC_FLASHDH_DATAH_POSE) - -/****************** Bit definition for MSC_FLASHCMD register ************************/ - -#define MSC_FLASHCMD_CMD_POSS 0U -#define MSC_FLASHCMD_CMD_POSE 31U -#define MSC_FLASHCMD_CMD_MSK BITS(MSC_FLASHCMD_CMD_POSS,MSC_FLASHCMD_CMD_POSE) - -/****************** Bit definition for MSC_FLASHCR register ************************/ - -#define MSC_FLASHCR_FIFOEN_POS 5U -#define MSC_FLASHCR_FIFOEN_MSK BIT(MSC_FLASHCR_FIFOEN_POS) - -#define MSC_FLASHCR_FLASHREQ_POS 4U -#define MSC_FLASHCR_FLASHREQ_MSK BIT(MSC_FLASHCR_FLASHREQ_POS) - -#define MSC_FLASHCR_IAPRST_POS 1U -#define MSC_FLASHCR_IAPRST_MSK BIT(MSC_FLASHCR_IAPRST_POS) - -#define MSC_FLASHCR_IAPEN_POS 0U -#define MSC_FLASHCR_IAPEN_MSK BIT(MSC_FLASHCR_IAPEN_POS) - -/****************** Bit definition for MSC_FLASHSR register ************************/ - -#define MSC_FLASHSR_TIMEOUT_POS 7U -#define MSC_FLASHSR_TIMEOUT_MSK BIT(MSC_FLASHSR_TIMEOUT_POS) - -#define MSC_FLASHSR_PROG_POS 6U -#define MSC_FLASHSR_PROG_MSK BIT(MSC_FLASHSR_PROG_POS) - -#define MSC_FLASHSR_SERA_POS 5U -#define MSC_FLASHSR_SERA_MSK BIT(MSC_FLASHSR_SERA_POS) - -#define MSC_FLASHSR_MASE_POS 4U -#define MSC_FLASHSR_MASE_MSK BIT(MSC_FLASHSR_MASE_POS) - -#define MSC_FLASHSR_ADDR_OV_POS 3U -#define MSC_FLASHSR_ADDR_OV_MSK BIT(MSC_FLASHSR_ADDR_OV_POS) - -#define MSC_FLASHSR_WRP_FLAG_POS 2U -#define MSC_FLASHSR_WRP_FLAG_MSK BIT(MSC_FLASHSR_WRP_FLAG_POS) - -#define MSC_FLASHSR_BUSY_POS 1U -#define MSC_FLASHSR_BUSY_MSK BIT(MSC_FLASHSR_BUSY_POS) - -#define MSC_FLASHSR_FLASHACK_POS 0U -#define MSC_FLASHSR_FLASHACK_MSK BIT(MSC_FLASHSR_FLASHACK_POS) - -/****************** Bit definition for MSC_FLASHPL register ************************/ - -#define MSC_FLASHPL_PROG_LEN_POSS 0U -#define MSC_FLASHPL_PROG_LEN_POSE 15U -#define MSC_FLASHPL_PROG_LEN_MSK BITS(MSC_FLASHPL_PROG_LEN_POSS,MSC_FLASHPL_PROG_LEN_POSE) - -/****************** Bit definition for MSC_MEMWAIT register ************************/ - -#define MSC_MEMWAIT_SRAM_W_POSS 8U -#define MSC_MEMWAIT_SRAM_W_POSE 9U -#define MSC_MEMWAIT_SRAM_W_MSK BITS(MSC_MEMWAIT_SRAM_W_POSS,MSC_MEMWAIT_SRAM_W_POSE) - -#define MSC_MEMWAIT_FLASH_W_POSS 0U -#define MSC_MEMWAIT_FLASH_W_POSE 3U -#define MSC_MEMWAIT_FLASH_W_MSK BITS(MSC_MEMWAIT_FLASH_W_POSS,MSC_MEMWAIT_FLASH_W_POSE) - -typedef struct -{ - __IO uint32_t FLASHKEY; - __IO uint32_t INFOKEY; - __IO uint32_t FLASHADDR; - __O uint32_t FLASHFIFO; - __IO uint32_t FLASHDL; - __IO uint32_t FLASHDH; - __O uint32_t FLASHCMD; - __IO uint32_t FLASHCR; - __I uint32_t FLASHSR; - __IO uint32_t FLASHPL; - __IO uint32_t MEMWAIT; -} MSC_TypeDef; - -/****************** Bit definition for BKPC_PROT register ************************/ - -#define BKPC_PROT_KEY_POSS 1U -#define BKPC_PROT_KEY_POSE 31U -#define BKPC_PROT_KEY_MSK BITS(BKPC_PROT_KEY_POSS,BKPC_PROT_KEY_POSE) - -#define BKPC_PROT_PROT_POS 0U -#define BKPC_PROT_PROT_MSK BIT(BKPC_PROT_PROT_POS) - -/****************** Bit definition for BKPC_CR register ************************/ - -#define BKPC_CR_LDO_VSEL_POSS 24U -#define BKPC_CR_LDO_VSEL_POSE 26U -#define BKPC_CR_LDO_VSEL_MSK BITS(BKPC_CR_LDO_VSEL_POSS,BKPC_CR_LDO_VSEL_POSE) - -#define BKPC_CR_MT_STDB_POS 19U -#define BKPC_CR_MT_STDB_MSK BIT(BKPC_CR_MT_STDB_POS) - -#define BKPC_CR_VR1P5_VSEL_POSS 16U -#define BKPC_CR_VR1P5_VSEL_POSE 18U -#define BKPC_CR_VR1P5_VSEL_MSK BITS(BKPC_CR_VR1P5_VSEL_POSS,BKPC_CR_VR1P5_VSEL_POSE) - -#define BKPC_CR_TC_PWRDWN_POS 13U -#define BKPC_CR_TC_PWRDWN_MSK BIT(BKPC_CR_TC_PWRDWN_POS) - -#define BKPC_CR_WKPOL_POS 12U -#define BKPC_CR_WKPOL_MSK BIT(BKPC_CR_WKPOL_POS) - -#define BKPC_CR_WKPS_POSS 9U -#define BKPC_CR_WKPS_POSE 11U -#define BKPC_CR_WKPS_MSK BITS(BKPC_CR_WKPS_POSS,BKPC_CR_WKPS_POSE) - -#define BKPC_CR_WKPEN_POS 8U -#define BKPC_CR_WKPEN_MSK BIT(BKPC_CR_WKPEN_POS) - -#define BKPC_CR_LRCEN_POS 2U -#define BKPC_CR_LRCEN_MSK BIT(BKPC_CR_LRCEN_POS) - -#define BKPC_CR_LOSMEN_POS 1U -#define BKPC_CR_LOSMEN_MSK BIT(BKPC_CR_LOSMEN_POS) - -#define BKPC_CR_LOSCEN_POS 0U -#define BKPC_CR_LOSCEN_MSK BIT(BKPC_CR_LOSCEN_POS) - -/****************** Bit definition for BKPC_PCCR register ************************/ - -#define BKPC_PCCR_TEMPCS_POSS 4U -#define BKPC_PCCR_TEMPCS_POSE 5U -#define BKPC_PCCR_TEMPCS_MSK BITS(BKPC_PCCR_TEMPCS_POSS,BKPC_PCCR_TEMPCS_POSE) - -#define BKPC_PCCR_RTCCS_POSS 0U -#define BKPC_PCCR_RTCCS_POSE 1U -#define BKPC_PCCR_RTCCS_MSK BITS(BKPC_PCCR_RTCCS_POSS,BKPC_PCCR_RTCCS_POSE) - -/****************** Bit definition for BKPC_PCR register ************************/ - -#define BKPC_PCR_BORS_POSS 1U -#define BKPC_PCR_BORS_POSE 4U -#define BKPC_PCR_BORS_MSK BITS(BKPC_PCR_BORS_POSS,BKPC_PCR_BORS_POSE) - -#define BKPC_PCR_BOREN_POS 0U -#define BKPC_PCR_BOREN_MSK BIT(BKPC_PCR_BOREN_POS) - -typedef struct -{ - __IO uint32_t PROT; - __IO uint32_t CR; - __IO uint32_t PCCR; - __IO uint32_t PCR; -} BKPC_TypeDef; - -/****************** Bit definition for PMU_CR register ************************/ - -#define PMU_CR_MTSTOP_POS 21U -#define PMU_CR_MTSTOP_MSK BIT(PMU_CR_MTSTOP_POS) - -#define PMU_CR_LPSTOP_POS 20U -#define PMU_CR_LPSTOP_MSK BIT(PMU_CR_LPSTOP_POS) - -#define PMU_CR_LPRUN_POS 19U -#define PMU_CR_LPRUN_MSK BIT(PMU_CR_LPRUN_POS) - -#define PMU_CR_LPVS_POSS 16U -#define PMU_CR_LPVS_POSE 18U -#define PMU_CR_LPVS_MSK BITS(PMU_CR_LPVS_POSS,PMU_CR_LPVS_POSE) - -#define PMU_CR_WKPS_POSS 9U -#define PMU_CR_WKPS_POSE 11U -#define PMU_CR_WKPS_MSK BITS(PMU_CR_WKPS_POSS,PMU_CR_WKPS_POSE) - -#define PMU_CR_WKPEN_POS 8U -#define PMU_CR_WKPEN_MSK BIT(PMU_CR_WKPEN_POS) - -#define PMU_CR_CSTANDBYF_POS 3U -#define PMU_CR_CSTANDBYF_MSK BIT(PMU_CR_CSTANDBYF_POS) - -#define PMU_CR_CWUF_POS 2U -#define PMU_CR_CWUF_MSK BIT(PMU_CR_CWUF_POS) - -#define PMU_CR_LPM_POSS 0U -#define PMU_CR_LPM_POSE 1U -#define PMU_CR_LPM_MSK BITS(PMU_CR_LPM_POSS,PMU_CR_LPM_POSE) - -/****************** Bit definition for PMU_SR register ************************/ - -#define PMU_SR_STANDBYF_POS 1U -#define PMU_SR_STANDBYF_MSK BIT(PMU_SR_STANDBYF_POS) - -#define PMU_SR_WUF_POS 0U -#define PMU_SR_WUF_MSK BIT(PMU_SR_WUF_POS) - -/****************** Bit definition for PMU_LVDCR register ************************/ - -#define PMU_LVDCR_LVDO_POS 15U -#define PMU_LVDCR_LVDO_MSK BIT(PMU_LVDCR_LVDO_POS) - -#define PMU_LVDCR_LVDFLT_POS 11U -#define PMU_LVDCR_LVDFLT_MSK BIT(PMU_LVDCR_LVDFLT_POS) - -#define PMU_LVDCR_LVIFS_POSS 8U -#define PMU_LVDCR_LVIFS_POSE 10U -#define PMU_LVDCR_LVIFS_MSK BITS(PMU_LVDCR_LVIFS_POSS,PMU_LVDCR_LVIFS_POSE) - -#define PMU_LVDCR_LVDS_POSS 4U -#define PMU_LVDCR_LVDS_POSE 7U -#define PMU_LVDCR_LVDS_MSK BITS(PMU_LVDCR_LVDS_POSS,PMU_LVDCR_LVDS_POSE) - -#define PMU_LVDCR_LVDCIF_POS 3U -#define PMU_LVDCR_LVDCIF_MSK BIT(PMU_LVDCR_LVDCIF_POS) - -#define PMU_LVDCR_LVDIF_POS 2U -#define PMU_LVDCR_LVDIF_MSK BIT(PMU_LVDCR_LVDIF_POS) - -#define PMU_LVDCR_LVDIE_POS 1U -#define PMU_LVDCR_LVDIE_MSK BIT(PMU_LVDCR_LVDIE_POS) - -#define PMU_LVDCR_LVDEN_POS 0U -#define PMU_LVDCR_LVDEN_MSK BIT(PMU_LVDCR_LVDEN_POS) - -/****************** Bit definition for PMU_PWRCR register ************************/ - -#define PMU_PWRCR_BXCAN_POS 4U -#define PMU_PWRCR_BXCAN_MSK BIT(PMU_PWRCR_BXCAN_POS) - -#define PMU_PWRCR_SRAM_POSS 0U -#define PMU_PWRCR_SRAM_POSE 1U -#define PMU_PWRCR_SRAM_MSK BITS(PMU_PWRCR_SRAM_POSS,PMU_PWRCR_SRAM_POSE) - -/****************** Bit definition for PMU_TWUR register ************************/ - -#define PMU_TWUR_TWU_POSS 0U -#define PMU_TWUR_TWU_POSE 11U -#define PMU_TWUR_TWU_MSK BITS(PMU_TWUR_TWU_POSS,PMU_TWUR_TWU_POSE) - -/****************** Bit definition for PMU_VREFCR register ************************/ - -#define PMU_VREFCR_FLTS_POSS 13U -#define PMU_VREFCR_FLTS_POSE 14U -#define PMU_VREFCR_FLTS_MSK BITS(PMU_VREFCR_FLTS_POSS,PMU_VREFCR_FLTS_POSE) - -#define PMU_VREFCR_CHOPCS_POSS 10U -#define PMU_VREFCR_CHOPCS_POSE 12U -#define PMU_VREFCR_CHOPCS_MSK BITS(PMU_VREFCR_CHOPCS_POSS,PMU_VREFCR_CHOPCS_POSE) - -#define PMU_VREFCR_CHOP1EN_POS 9U -#define PMU_VREFCR_CHOP1EN_MSK BIT(PMU_VREFCR_CHOP1EN_POS) - -#define PMU_VREFCR_CHOPEN_POS 8U -#define PMU_VREFCR_CHOPEN_MSK BIT(PMU_VREFCR_CHOPEN_POS) - -#define PMU_VREFCR_VREFEN_POS 0U -#define PMU_VREFCR_VREFEN_MSK BIT(PMU_VREFCR_VREFEN_POS) - -typedef struct -{ - __IO uint32_t CR; - __I uint32_t SR; - __IO uint32_t LVDCR; - __IO uint32_t PWRCR; - __IO uint32_t TWUR; - __IO uint32_t VREFCR; -} PMU_TypeDef; - -/****************** Bit definition for RMU_CR register ************************/ - -#define RMU_CR_BORVS_POSS 4U -#define RMU_CR_BORVS_POSE 7U -#define RMU_CR_BORVS_MSK BITS(RMU_CR_BORVS_POSS,RMU_CR_BORVS_POSE) - -#define RMU_CR_BORFLT_POSS 1U -#define RMU_CR_BORFLT_POSE 3U -#define RMU_CR_BORFLT_MSK BITS(RMU_CR_BORFLT_POSS,RMU_CR_BORFLT_POSE) - -#define RMU_CR_BOREN_POS 0U -#define RMU_CR_BOREN_MSK BIT(RMU_CR_BOREN_POS) - -/****************** Bit definition for RMU_RSTSR register ************************/ - -#define RMU_RSTSR_CFGERR_POS 16U -#define RMU_RSTSR_CFGERR_MSK BIT(RMU_RSTSR_CFGERR_POS) - -#define RMU_RSTSR_CFG_POS 10U -#define RMU_RSTSR_CFG_MSK BIT(RMU_RSTSR_CFG_POS) - -#define RMU_RSTSR_CPU_POS 9U -#define RMU_RSTSR_CPU_MSK BIT(RMU_RSTSR_CPU_POS) - -#define RMU_RSTSR_MCU_POS 8U -#define RMU_RSTSR_MCU_MSK BIT(RMU_RSTSR_MCU_POS) - -#define RMU_RSTSR_CHIP_POS 7U -#define RMU_RSTSR_CHIP_MSK BIT(RMU_RSTSR_CHIP_POS) - -#define RMU_RSTSR_LOCKUP_POS 6U -#define RMU_RSTSR_LOCKUP_MSK BIT(RMU_RSTSR_LOCKUP_POS) - -#define RMU_RSTSR_WWDT_POS 5U -#define RMU_RSTSR_WWDT_MSK BIT(RMU_RSTSR_WWDT_POS) - -#define RMU_RSTSR_IWDT_POS 4U -#define RMU_RSTSR_IWDT_MSK BIT(RMU_RSTSR_IWDT_POS) - -#define RMU_RSTSR_NMRST_POS 3U -#define RMU_RSTSR_NMRST_MSK BIT(RMU_RSTSR_NMRST_POS) - -#define RMU_RSTSR_BOR_POS 2U -#define RMU_RSTSR_BOR_MSK BIT(RMU_RSTSR_BOR_POS) - -#define RMU_RSTSR_WAKEUP_POS 1U -#define RMU_RSTSR_WAKEUP_MSK BIT(RMU_RSTSR_WAKEUP_POS) - -#define RMU_RSTSR_POR_POS 0U -#define RMU_RSTSR_POR_MSK BIT(RMU_RSTSR_POR_POS) - -/****************** Bit definition for RMU_CRSTSR register ************************/ - -#define RMU_CRSTSR_CFG_POS 10U -#define RMU_CRSTSR_CFG_MSK BIT(RMU_CRSTSR_CFG_POS) - -#define RMU_CRSTSR_CPU_POS 9U -#define RMU_CRSTSR_CPU_MSK BIT(RMU_CRSTSR_CPU_POS) - -#define RMU_CRSTSR_MCU_POS 8U -#define RMU_CRSTSR_MCU_MSK BIT(RMU_CRSTSR_MCU_POS) - -#define RMU_CRSTSR_CHIP_POS 7U -#define RMU_CRSTSR_CHIP_MSK BIT(RMU_CRSTSR_CHIP_POS) - -#define RMU_CRSTSR_LOCKUP_POS 6U -#define RMU_CRSTSR_LOCKUP_MSK BIT(RMU_CRSTSR_LOCKUP_POS) - -#define RMU_CRSTSR_WWDT_POS 5U -#define RMU_CRSTSR_WWDT_MSK BIT(RMU_CRSTSR_WWDT_POS) - -#define RMU_CRSTSR_IWDT_POS 4U -#define RMU_CRSTSR_IWDT_MSK BIT(RMU_CRSTSR_IWDT_POS) - -#define RMU_CRSTSR_NMRST_POS 3U -#define RMU_CRSTSR_NMRST_MSK BIT(RMU_CRSTSR_NMRST_POS) - -#define RMU_CRSTSR_BOR_POS 2U -#define RMU_CRSTSR_BOR_MSK BIT(RMU_CRSTSR_BOR_POS) - -#define RMU_CRSTSR_WAKEUP_POS 1U -#define RMU_CRSTSR_WAKEUP_MSK BIT(RMU_CRSTSR_WAKEUP_POS) - -#define RMU_CRSTSR_POR_POS 0U -#define RMU_CRSTSR_POR_MSK BIT(RMU_CRSTSR_POR_POS) - -/****************** Bit definition for RMU_AHB1RSTR register ************************/ - -#define RMU_AHB1RSTR_PISRST_POS 5U -#define RMU_AHB1RSTR_PISRST_MSK BIT(RMU_AHB1RSTR_PISRST_POS) - -#define RMU_AHB1RSTR_TRNGRST_POS 4U -#define RMU_AHB1RSTR_TRNGRST_MSK BIT(RMU_AHB1RSTR_TRNGRST_POS) - -#define RMU_AHB1RSTR_CRYPTRST_POS 3U -#define RMU_AHB1RSTR_CRYPTRST_MSK BIT(RMU_AHB1RSTR_CRYPTRST_POS) - -#define RMU_AHB1RSTR_CALCRST_POS 2U -#define RMU_AHB1RSTR_CALCRST_MSK BIT(RMU_AHB1RSTR_CALCRST_POS) - -#define RMU_AHB1RSTR_CRCRST_POS 1U -#define RMU_AHB1RSTR_CRCRST_MSK BIT(RMU_AHB1RSTR_CRCRST_POS) - -#define RMU_AHB1RSTR_GPIORST_POS 0U -#define RMU_AHB1RSTR_GPIORST_MSK BIT(RMU_AHB1RSTR_GPIORST_POS) - -/****************** Bit definition for RMU_AHB2RSTR register ************************/ - -#define RMU_AHB2RSTR_CPURST_POS 1U -#define RMU_AHB2RSTR_CPURST_MSK BIT(RMU_AHB2RSTR_CPURST_POS) - -#define RMU_AHB2RSTR_CHIPRST_POS 0U -#define RMU_AHB2RSTR_CHIPRST_MSK BIT(RMU_AHB2RSTR_CHIPRST_POS) - -/****************** Bit definition for RMU_APB1RSTR register ************************/ - -#define RMU_APB1RSTR_CAN0RST_POS 24U -#define RMU_APB1RSTR_CAN0RST_MSK BIT(RMU_APB1RSTR_CAN0RST_POS) - -#define RMU_APB1RSTR_I2C1RST_POS 21U -#define RMU_APB1RSTR_I2C1RST_MSK BIT(RMU_APB1RSTR_I2C1RST_POS) - -#define RMU_APB1RSTR_I2C0RST_POS 20U -#define RMU_APB1RSTR_I2C0RST_MSK BIT(RMU_APB1RSTR_I2C0RST_POS) - -#define RMU_APB1RSTR_SPI2RST_POS 18U -#define RMU_APB1RSTR_SPI2RST_MSK BIT(RMU_APB1RSTR_SPI2RST_POS) - -#define RMU_APB1RSTR_SPI1RST_POS 17U -#define RMU_APB1RSTR_SPI1RST_MSK BIT(RMU_APB1RSTR_SPI1RST_POS) - -#define RMU_APB1RSTR_SPI0RST_POS 16U -#define RMU_APB1RSTR_SPI0RST_MSK BIT(RMU_APB1RSTR_SPI0RST_POS) - -#define RMU_APB1RSTR_USART1RST_POS 13U -#define RMU_APB1RSTR_USART1RST_MSK BIT(RMU_APB1RSTR_USART1RST_POS) - -#define RMU_APB1RSTR_USART0RST_POS 12U -#define RMU_APB1RSTR_USART0RST_MSK BIT(RMU_APB1RSTR_USART0RST_POS) - -#define RMU_APB1RSTR_UART3RST_POS 11U -#define RMU_APB1RSTR_UART3RST_MSK BIT(RMU_APB1RSTR_UART3RST_POS) - -#define RMU_APB1RSTR_UART2RST_POS 10U -#define RMU_APB1RSTR_UART2RST_MSK BIT(RMU_APB1RSTR_UART2RST_POS) - -#define RMU_APB1RSTR_UART1RST_POS 9U -#define RMU_APB1RSTR_UART1RST_MSK BIT(RMU_APB1RSTR_UART1RST_POS) - -#define RMU_APB1RSTR_UART0RST_POS 8U -#define RMU_APB1RSTR_UART0RST_MSK BIT(RMU_APB1RSTR_UART0RST_POS) - -#define RMU_APB1RSTR_TIM7RST_POS 7U -#define RMU_APB1RSTR_TIM7RST_MSK BIT(RMU_APB1RSTR_TIM7RST_POS) - -#define RMU_APB1RSTR_TIM6RST_POS 6U -#define RMU_APB1RSTR_TIM6RST_MSK BIT(RMU_APB1RSTR_TIM6RST_POS) - -#define RMU_APB1RSTR_TIM5RST_POS 5U -#define RMU_APB1RSTR_TIM5RST_MSK BIT(RMU_APB1RSTR_TIM5RST_POS) - -#define RMU_APB1RSTR_TIM4RST_POS 4U -#define RMU_APB1RSTR_TIM4RST_MSK BIT(RMU_APB1RSTR_TIM4RST_POS) - -#define RMU_APB1RSTR_TIM3RST_POS 3U -#define RMU_APB1RSTR_TIM3RST_MSK BIT(RMU_APB1RSTR_TIM3RST_POS) - -#define RMU_APB1RSTR_TIM2RST_POS 2U -#define RMU_APB1RSTR_TIM2RST_MSK BIT(RMU_APB1RSTR_TIM2RST_POS) - -#define RMU_APB1RSTR_TIM1RST_POS 1U -#define RMU_APB1RSTR_TIM1RST_MSK BIT(RMU_APB1RSTR_TIM1RST_POS) - -#define RMU_APB1RSTR_TIM0RST_POS 0U -#define RMU_APB1RSTR_TIM0RST_MSK BIT(RMU_APB1RSTR_TIM0RST_POS) - -/****************** Bit definition for RMU_APB2RSTR register ************************/ - -#define RMU_APB2RSTR_BKPRAMRST_POS 18U -#define RMU_APB2RSTR_BKPRAMRST_MSK BIT(RMU_APB2RSTR_BKPRAMRST_POS) - -#define RMU_APB2RSTR_BKPCRST_POS 17U -#define RMU_APB2RSTR_BKPCRST_MSK BIT(RMU_APB2RSTR_BKPCRST_POS) - -#define RMU_APB2RSTR_TEMPRST_POS 16U -#define RMU_APB2RSTR_TEMPRST_MSK BIT(RMU_APB2RSTR_TEMPRST_POS) - -#define RMU_APB2RSTR_RTCRST_POS 15U -#define RMU_APB2RSTR_RTCRST_MSK BIT(RMU_APB2RSTR_RTCRST_POS) - -#define RMU_APB2RSTR_IWDTRST_POS 14U -#define RMU_APB2RSTR_IWDTRST_MSK BIT(RMU_APB2RSTR_IWDTRST_POS) - -#define RMU_APB2RSTR_LCDRST_POS 13U -#define RMU_APB2RSTR_LCDRST_MSK BIT(RMU_APB2RSTR_LCDRST_POS) - -#define RMU_APB2RSTR_WWDTRST_POS 12U -#define RMU_APB2RSTR_WWDTRST_MSK BIT(RMU_APB2RSTR_WWDTRST_POS) - -#define RMU_APB2RSTR_OPAMPRST_POS 8U -#define RMU_APB2RSTR_OPAMPRST_MSK BIT(RMU_APB2RSTR_OPAMPRST_POS) - -#define RMU_APB2RSTR_ACMP1RST_POS 7U -#define RMU_APB2RSTR_ACMP1RST_MSK BIT(RMU_APB2RSTR_ACMP1RST_POS) - -#define RMU_APB2RSTR_ACMP0RST_POS 6U -#define RMU_APB2RSTR_ACMP0RST_MSK BIT(RMU_APB2RSTR_ACMP0RST_POS) - -#define RMU_APB2RSTR_ADC0RST_POS 4U -#define RMU_APB2RSTR_ADC0RST_MSK BIT(RMU_APB2RSTR_ADC0RST_POS) - -#define RMU_APB2RSTR_LPUART0RST_POS 2U -#define RMU_APB2RSTR_LPUART0RST_MSK BIT(RMU_APB2RSTR_LPUART0RST_POS) - -#define RMU_APB2RSTR_LPTIM0RST_POS 0U -#define RMU_APB2RSTR_LPTIM0RST_MSK BIT(RMU_APB2RSTR_LPTIM0RST_POS) - -typedef struct -{ - __IO uint32_t CR; - uint32_t RESERVED0[3] ; - __I uint32_t RSTSR; - __O uint32_t CRSTSR; - uint32_t RESERVED1[2] ; - __O uint32_t AHB1RSTR; - __O uint32_t AHB2RSTR; - uint32_t RESERVED2[2] ; - __O uint32_t APB1RSTR; - __O uint32_t APB2RSTR; -} RMU_TypeDef; - -/****************** Bit definition for CMU_CSR register ************************/ - -#define CMU_CSR_CFT_RDYN_POS 25U -#define CMU_CSR_CFT_RDYN_MSK BIT(CMU_CSR_CFT_RDYN_POS) - -#define CMU_CSR_CFT_STU_POS 24U -#define CMU_CSR_CFT_STU_MSK BIT(CMU_CSR_CFT_STU_POS) - -#define CMU_CSR_CFT_CMD_POSS 16U -#define CMU_CSR_CFT_CMD_POSE 23U -#define CMU_CSR_CFT_CMD_MSK BITS(CMU_CSR_CFT_CMD_POSS,CMU_CSR_CFT_CMD_POSE) - -#define CMU_CSR_SYS_RDYN_POS 12U -#define CMU_CSR_SYS_RDYN_MSK BIT(CMU_CSR_SYS_RDYN_POS) - -#define CMU_CSR_SYS_STU_POSS 8U -#define CMU_CSR_SYS_STU_POSE 10U -#define CMU_CSR_SYS_STU_MSK BITS(CMU_CSR_SYS_STU_POSS,CMU_CSR_SYS_STU_POSE) - -#define CMU_CSR_SYS_CMD_POSS 0U -#define CMU_CSR_SYS_CMD_POSE 2U -#define CMU_CSR_SYS_CMD_MSK BITS(CMU_CSR_SYS_CMD_POSS,CMU_CSR_SYS_CMD_POSE) - -/****************** Bit definition for CMU_CFGR register ************************/ - -#define CMU_CFGR_HRCFST_POS 25U -#define CMU_CFGR_HRCFST_MSK BIT(CMU_CFGR_HRCFST_POS) - -#define CMU_CFGR_HRCFSW_POS 24U -#define CMU_CFGR_HRCFSW_MSK BIT(CMU_CFGR_HRCFSW_POS) - -#define CMU_CFGR_PCLK2DIV_POSS 20U -#define CMU_CFGR_PCLK2DIV_POSE 23U -#define CMU_CFGR_PCLK2DIV_MSK BITS(CMU_CFGR_PCLK2DIV_POSS,CMU_CFGR_PCLK2DIV_POSE) - -#define CMU_CFGR_PCLK1DIV_POSS 16U -#define CMU_CFGR_PCLK1DIV_POSE 19U -#define CMU_CFGR_PCLK1DIV_MSK BITS(CMU_CFGR_PCLK1DIV_POSS,CMU_CFGR_PCLK1DIV_POSE) - -#define CMU_CFGR_SYSDIV_POSS 12U -#define CMU_CFGR_SYSDIV_POSE 15U -#define CMU_CFGR_SYSDIV_MSK BITS(CMU_CFGR_SYSDIV_POSS,CMU_CFGR_SYSDIV_POSE) - -#define CMU_CFGR_HCLK1DIV_POSS 0U -#define CMU_CFGR_HCLK1DIV_POSE 3U -#define CMU_CFGR_HCLK1DIV_MSK BITS(CMU_CFGR_HCLK1DIV_POSS,CMU_CFGR_HCLK1DIV_POSE) - -/****************** Bit definition for CMU_CLKENR register ************************/ - -#define CMU_CLKENR_PLL2EN_POS 9U -#define CMU_CLKENR_PLL2EN_MSK BIT(CMU_CLKENR_PLL2EN_POS) - -#define CMU_CLKENR_PLL1EN_POS 8U -#define CMU_CLKENR_PLL1EN_MSK BIT(CMU_CLKENR_PLL1EN_POS) - -#define CMU_CLKENR_ULRCEN_POS 4U -#define CMU_CLKENR_ULRCEN_MSK BIT(CMU_CLKENR_ULRCEN_POS) - -#define CMU_CLKENR_LRCEN_POS 3U -#define CMU_CLKENR_LRCEN_MSK BIT(CMU_CLKENR_LRCEN_POS) - -#define CMU_CLKENR_HRCEN_POS 2U -#define CMU_CLKENR_HRCEN_MSK BIT(CMU_CLKENR_HRCEN_POS) - -#define CMU_CLKENR_LOSCEN_POS 1U -#define CMU_CLKENR_LOSCEN_MSK BIT(CMU_CLKENR_LOSCEN_POS) - -#define CMU_CLKENR_HOSCEN_POS 0U -#define CMU_CLKENR_HOSCEN_MSK BIT(CMU_CLKENR_HOSCEN_POS) - -/****************** Bit definition for CMU_CLKSR register ************************/ - -#define CMU_CLKSR_PLL2RDY_POS 25U -#define CMU_CLKSR_PLL2RDY_MSK BIT(CMU_CLKSR_PLL2RDY_POS) - -#define CMU_CLKSR_PLL1RDY_POS 24U -#define CMU_CLKSR_PLL1RDY_MSK BIT(CMU_CLKSR_PLL1RDY_POS) - -#define CMU_CLKSR_LRCRDY_POS 19U -#define CMU_CLKSR_LRCRDY_MSK BIT(CMU_CLKSR_LRCRDY_POS) - -#define CMU_CLKSR_HRCRDY_POS 18U -#define CMU_CLKSR_HRCRDY_MSK BIT(CMU_CLKSR_HRCRDY_POS) - -#define CMU_CLKSR_LOSCRDY_POS 17U -#define CMU_CLKSR_LOSCRDY_MSK BIT(CMU_CLKSR_LOSCRDY_POS) - -#define CMU_CLKSR_HOSCRDY_POS 16U -#define CMU_CLKSR_HOSCRDY_MSK BIT(CMU_CLKSR_HOSCRDY_POS) - -#define CMU_CLKSR_PLL2ACT_POS 9U -#define CMU_CLKSR_PLL2ACT_MSK BIT(CMU_CLKSR_PLL2ACT_POS) - -#define CMU_CLKSR_PLL1ACT_POS 8U -#define CMU_CLKSR_PLL1ACT_MSK BIT(CMU_CLKSR_PLL1ACT_POS) - -#define CMU_CLKSR_ULRCACT_POS 4U -#define CMU_CLKSR_ULRCACT_MSK BIT(CMU_CLKSR_ULRCACT_POS) - -#define CMU_CLKSR_LRCACT_POS 3U -#define CMU_CLKSR_LRCACT_MSK BIT(CMU_CLKSR_LRCACT_POS) - -#define CMU_CLKSR_HRCACT_POS 2U -#define CMU_CLKSR_HRCACT_MSK BIT(CMU_CLKSR_HRCACT_POS) - -#define CMU_CLKSR_LOSCACT_POS 1U -#define CMU_CLKSR_LOSCACT_MSK BIT(CMU_CLKSR_LOSCACT_POS) - -#define CMU_CLKSR_HOSCACT_POS 0U -#define CMU_CLKSR_HOSCACT_MSK BIT(CMU_CLKSR_HOSCACT_POS) - -/****************** Bit definition for CMU_PLLCFG register ************************/ - -#define CMU_PLLCFG_PLL2LCKN_POS 17U -#define CMU_PLLCFG_PLL2LCKN_MSK BIT(CMU_PLLCFG_PLL2LCKN_POS) - -#define CMU_PLLCFG_PLL1LCKN_POS 16U -#define CMU_PLLCFG_PLL1LCKN_MSK BIT(CMU_PLLCFG_PLL1LCKN_POS) - -#define CMU_PLLCFG_PLL2RFS_POSS 8U -#define CMU_PLLCFG_PLL2RFS_POSE 9U -#define CMU_PLLCFG_PLL2RFS_MSK BITS(CMU_PLLCFG_PLL2RFS_POSS,CMU_PLLCFG_PLL2RFS_POSE) - -#define CMU_PLLCFG_PLL1OS_POS 4U -#define CMU_PLLCFG_PLL1OS_MSK BIT(CMU_PLLCFG_PLL1OS_POS) - -#define CMU_PLLCFG_PLL1RFS_POSS 0U -#define CMU_PLLCFG_PLL1RFS_POSE 2U -#define CMU_PLLCFG_PLL1RFS_MSK BITS(CMU_PLLCFG_PLL1RFS_POSS,CMU_PLLCFG_PLL1RFS_POSE) - -/****************** Bit definition for CMU_HOSCCFG register ************************/ - -#define CMU_HOSCCFG_FREQ_POSS 0U -#define CMU_HOSCCFG_FREQ_POSE 4U -#define CMU_HOSCCFG_FREQ_MSK BITS(CMU_HOSCCFG_FREQ_POSS,CMU_HOSCCFG_FREQ_POSE) - -/****************** Bit definition for CMU_HOSMCR register ************************/ - -#define CMU_HOSMCR_NMIE_POS 20U -#define CMU_HOSMCR_NMIE_MSK BIT(CMU_HOSMCR_NMIE_POS) - -#define CMU_HOSMCR_STPIF_POS 19U -#define CMU_HOSMCR_STPIF_MSK BIT(CMU_HOSMCR_STPIF_POS) - -#define CMU_HOSMCR_STRIF_POS 18U -#define CMU_HOSMCR_STRIF_MSK BIT(CMU_HOSMCR_STRIF_POS) - -#define CMU_HOSMCR_STPIE_POS 17U -#define CMU_HOSMCR_STPIE_MSK BIT(CMU_HOSMCR_STPIE_POS) - -#define CMU_HOSMCR_STRIE_POS 16U -#define CMU_HOSMCR_STRIE_MSK BIT(CMU_HOSMCR_STRIE_POS) - -#define CMU_HOSMCR_FRQS_POSS 8U -#define CMU_HOSMCR_FRQS_POSE 10U -#define CMU_HOSMCR_FRQS_MSK BITS(CMU_HOSMCR_FRQS_POSS,CMU_HOSMCR_FRQS_POSE) - -#define CMU_HOSMCR_CLKS_POS 1U -#define CMU_HOSMCR_CLKS_MSK BIT(CMU_HOSMCR_CLKS_POS) - -#define CMU_HOSMCR_EN_POS 0U -#define CMU_HOSMCR_EN_MSK BIT(CMU_HOSMCR_EN_POS) - -/****************** Bit definition for CMU_LOSMCR register ************************/ - -#define CMU_LOSMCR_NMIE_POS 20U -#define CMU_LOSMCR_NMIE_MSK BIT(CMU_LOSMCR_NMIE_POS) - -#define CMU_LOSMCR_STPIF_POS 19U -#define CMU_LOSMCR_STPIF_MSK BIT(CMU_LOSMCR_STPIF_POS) - -#define CMU_LOSMCR_STRIF_POS 18U -#define CMU_LOSMCR_STRIF_MSK BIT(CMU_LOSMCR_STRIF_POS) - -#define CMU_LOSMCR_STPIE_POS 17U -#define CMU_LOSMCR_STPIE_MSK BIT(CMU_LOSMCR_STPIE_POS) - -#define CMU_LOSMCR_STRIE_POS 16U -#define CMU_LOSMCR_STRIE_MSK BIT(CMU_LOSMCR_STRIE_POS) - -#define CMU_LOSMCR_CLKS_POS 1U -#define CMU_LOSMCR_CLKS_MSK BIT(CMU_LOSMCR_CLKS_POS) - -#define CMU_LOSMCR_EN_POS 0U -#define CMU_LOSMCR_EN_MSK BIT(CMU_LOSMCR_EN_POS) - -/****************** Bit definition for CMU_PULMCR register ************************/ - -#define CMU_PULMCR_NMIE_POS 20U -#define CMU_PULMCR_NMIE_MSK BIT(CMU_PULMCR_NMIE_POS) - -#define CMU_PULMCR_ULKIF_POS 19U -#define CMU_PULMCR_ULKIF_MSK BIT(CMU_PULMCR_ULKIF_POS) - -#define CMU_PULMCR_LCKIF_POS 18U -#define CMU_PULMCR_LCKIF_MSK BIT(CMU_PULMCR_LCKIF_POS) - -#define CMU_PULMCR_ULKIE_POS 17U -#define CMU_PULMCR_ULKIE_MSK BIT(CMU_PULMCR_ULKIE_POS) - -#define CMU_PULMCR_LCKIE_POS 16U -#define CMU_PULMCR_LCKIE_MSK BIT(CMU_PULMCR_LCKIE_POS) - -#define CMU_PULMCR_MODE_POSS 8U -#define CMU_PULMCR_MODE_POSE 9U -#define CMU_PULMCR_MODE_MSK BITS(CMU_PULMCR_MODE_POSS,CMU_PULMCR_MODE_POSE) - -#define CMU_PULMCR_CLKS_POS 1U -#define CMU_PULMCR_CLKS_MSK BIT(CMU_PULMCR_CLKS_POS) - -#define CMU_PULMCR_EN_POS 0U -#define CMU_PULMCR_EN_MSK BIT(CMU_PULMCR_EN_POS) - -/****************** Bit definition for CMU_CLKOCR register ************************/ - -#define CMU_CLKOCR_LSCOS_POSS 24U -#define CMU_CLKOCR_LSCOS_POSE 26U -#define CMU_CLKOCR_LSCOS_MSK BITS(CMU_CLKOCR_LSCOS_POSS,CMU_CLKOCR_LSCOS_POSE) - -#define CMU_CLKOCR_LSCOEN_POS 16U -#define CMU_CLKOCR_LSCOEN_MSK BIT(CMU_CLKOCR_LSCOEN_POS) - -#define CMU_CLKOCR_HSCODIV_POSS 12U -#define CMU_CLKOCR_HSCODIV_POSE 14U -#define CMU_CLKOCR_HSCODIV_MSK BITS(CMU_CLKOCR_HSCODIV_POSS,CMU_CLKOCR_HSCODIV_POSE) - -#define CMU_CLKOCR_HSCOS_POSS 8U -#define CMU_CLKOCR_HSCOS_POSE 10U -#define CMU_CLKOCR_HSCOS_MSK BITS(CMU_CLKOCR_HSCOS_POSS,CMU_CLKOCR_HSCOS_POSE) - -#define CMU_CLKOCR_HSCOEN_POS 0U -#define CMU_CLKOCR_HSCOEN_MSK BIT(CMU_CLKOCR_HSCOEN_POS) - -/****************** Bit definition for CMU_BUZZCR register ************************/ - -#define CMU_BUZZCR_DAT_POSS 16U -#define CMU_BUZZCR_DAT_POSE 31U -#define CMU_BUZZCR_DAT_MSK BITS(CMU_BUZZCR_DAT_POSS,CMU_BUZZCR_DAT_POSE) - -#define CMU_BUZZCR_DIV_POSS 8U -#define CMU_BUZZCR_DIV_POSE 10U -#define CMU_BUZZCR_DIV_MSK BITS(CMU_BUZZCR_DIV_POSS,CMU_BUZZCR_DIV_POSE) - -#define CMU_BUZZCR_EN_POS 0U -#define CMU_BUZZCR_EN_MSK BIT(CMU_BUZZCR_EN_POS) - -/****************** Bit definition for CMU_AHB1ENR register ************************/ - -#define CMU_AHB1ENR_PISEN_POS 5U -#define CMU_AHB1ENR_PISEN_MSK BIT(CMU_AHB1ENR_PISEN_POS) - -#define CMU_AHB1ENR_TRNGEN_POS 4U -#define CMU_AHB1ENR_TRNGEN_MSK BIT(CMU_AHB1ENR_TRNGEN_POS) - -#define CMU_AHB1ENR_CRYPTEN_POS 3U -#define CMU_AHB1ENR_CRYPTEN_MSK BIT(CMU_AHB1ENR_CRYPTEN_POS) - -#define CMU_AHB1ENR_CALCEN_POS 2U -#define CMU_AHB1ENR_CALCEN_MSK BIT(CMU_AHB1ENR_CALCEN_POS) - -#define CMU_AHB1ENR_CRCEN_POS 1U -#define CMU_AHB1ENR_CRCEN_MSK BIT(CMU_AHB1ENR_CRCEN_POS) - -#define CMU_AHB1ENR_GPIOEN_POS 0U -#define CMU_AHB1ENR_GPIOEN_MSK BIT(CMU_AHB1ENR_GPIOEN_POS) - -/****************** Bit definition for CMU_APB1ENR register ************************/ - -#define CMU_APB1ENR_CAN0EN_POS 24U -#define CMU_APB1ENR_CAN0EN_MSK BIT(CMU_APB1ENR_CAN0EN_POS) - -#define CMU_APB1ENR_I2C1EN_POS 21U -#define CMU_APB1ENR_I2C1EN_MSK BIT(CMU_APB1ENR_I2C1EN_POS) - -#define CMU_APB1ENR_I2C0EN_POS 20U -#define CMU_APB1ENR_I2C0EN_MSK BIT(CMU_APB1ENR_I2C0EN_POS) - -#define CMU_APB1ENR_SPI2EN_POS 18U -#define CMU_APB1ENR_SPI2EN_MSK BIT(CMU_APB1ENR_SPI2EN_POS) - -#define CMU_APB1ENR_SPI1EN_POS 17U -#define CMU_APB1ENR_SPI1EN_MSK BIT(CMU_APB1ENR_SPI1EN_POS) - -#define CMU_APB1ENR_SPI0EN_POS 16U -#define CMU_APB1ENR_SPI0EN_MSK BIT(CMU_APB1ENR_SPI0EN_POS) - -#define CMU_APB1ENR_USART1EN_POS 13U -#define CMU_APB1ENR_USART1EN_MSK BIT(CMU_APB1ENR_USART1EN_POS) - -#define CMU_APB1ENR_USART0EN_POS 12U -#define CMU_APB1ENR_USART0EN_MSK BIT(CMU_APB1ENR_USART0EN_POS) - -#define CMU_APB1ENR_UART3EN_POS 11U -#define CMU_APB1ENR_UART3EN_MSK BIT(CMU_APB1ENR_UART3EN_POS) - -#define CMU_APB1ENR_UART2EN_POS 10U -#define CMU_APB1ENR_UART2EN_MSK BIT(CMU_APB1ENR_UART2EN_POS) - -#define CMU_APB1ENR_UART1EN_POS 9U -#define CMU_APB1ENR_UART1EN_MSK BIT(CMU_APB1ENR_UART1EN_POS) - -#define CMU_APB1ENR_UART0EN_POS 8U -#define CMU_APB1ENR_UART0EN_MSK BIT(CMU_APB1ENR_UART0EN_POS) - -#define CMU_APB1ENR_TIM7EN_POS 7U -#define CMU_APB1ENR_TIM7EN_MSK BIT(CMU_APB1ENR_TIM7EN_POS) - -#define CMU_APB1ENR_TIM6EN_POS 6U -#define CMU_APB1ENR_TIM6EN_MSK BIT(CMU_APB1ENR_TIM6EN_POS) - -#define CMU_APB1ENR_TIM5EN_POS 5U -#define CMU_APB1ENR_TIM5EN_MSK BIT(CMU_APB1ENR_TIM5EN_POS) - -#define CMU_APB1ENR_TIM4EN_POS 4U -#define CMU_APB1ENR_TIM4EN_MSK BIT(CMU_APB1ENR_TIM4EN_POS) - -#define CMU_APB1ENR_TIM3EN_POS 3U -#define CMU_APB1ENR_TIM3EN_MSK BIT(CMU_APB1ENR_TIM3EN_POS) - -#define CMU_APB1ENR_TIM2EN_POS 2U -#define CMU_APB1ENR_TIM2EN_MSK BIT(CMU_APB1ENR_TIM2EN_POS) - -#define CMU_APB1ENR_TIM1EN_POS 1U -#define CMU_APB1ENR_TIM1EN_MSK BIT(CMU_APB1ENR_TIM1EN_POS) - -#define CMU_APB1ENR_TIM0EN_POS 0U -#define CMU_APB1ENR_TIM0EN_MSK BIT(CMU_APB1ENR_TIM0EN_POS) - -/****************** Bit definition for CMU_APB2ENR register ************************/ - -#define CMU_APB2ENR_DBGCEN_POS 19U -#define CMU_APB2ENR_DBGCEN_MSK BIT(CMU_APB2ENR_DBGCEN_POS) - -#define CMU_APB2ENR_BKPCEN_POS 17U -#define CMU_APB2ENR_BKPCEN_MSK BIT(CMU_APB2ENR_BKPCEN_POS) - -#define CMU_APB2ENR_TEMPEN_POS 16U -#define CMU_APB2ENR_TEMPEN_MSK BIT(CMU_APB2ENR_TEMPEN_POS) - -#define CMU_APB2ENR_RTCEN_POS 15U -#define CMU_APB2ENR_RTCEN_MSK BIT(CMU_APB2ENR_RTCEN_POS) - -#define CMU_APB2ENR_IWDTEN_POS 14U -#define CMU_APB2ENR_IWDTEN_MSK BIT(CMU_APB2ENR_IWDTEN_POS) - -#define CMU_APB2ENR_LCDEN_POS 13U -#define CMU_APB2ENR_LCDEN_MSK BIT(CMU_APB2ENR_LCDEN_POS) - -#define CMU_APB2ENR_WWDTEN_POS 12U -#define CMU_APB2ENR_WWDTEN_MSK BIT(CMU_APB2ENR_WWDTEN_POS) - -#define CMU_APB2ENR_OPAMPEN_POS 8U -#define CMU_APB2ENR_OPAMPEN_MSK BIT(CMU_APB2ENR_OPAMPEN_POS) - -#define CMU_APB2ENR_ACMP1EN_POS 7U -#define CMU_APB2ENR_ACMP1EN_MSK BIT(CMU_APB2ENR_ACMP1EN_POS) - -#define CMU_APB2ENR_ACMP0EN_POS 6U -#define CMU_APB2ENR_ACMP0EN_MSK BIT(CMU_APB2ENR_ACMP0EN_POS) - -#define CMU_APB2ENR_ADC0EN_POS 4U -#define CMU_APB2ENR_ADC0EN_MSK BIT(CMU_APB2ENR_ADC0EN_POS) - -#define CMU_APB2ENR_LPUART0EN_POS 2U -#define CMU_APB2ENR_LPUART0EN_MSK BIT(CMU_APB2ENR_LPUART0EN_POS) - -#define CMU_APB2ENR_LPTIM0EN_POS 0U -#define CMU_APB2ENR_LPTIM0EN_MSK BIT(CMU_APB2ENR_LPTIM0EN_POS) - -/****************** Bit definition for CMU_LPENR register ************************/ - -#define CMU_LPENR_HOSCEN_POS 3U -#define CMU_LPENR_HOSCEN_MSK BIT(CMU_LPENR_HOSCEN_POS) - -#define CMU_LPENR_HRCEN_POS 2U -#define CMU_LPENR_HRCEN_MSK BIT(CMU_LPENR_HRCEN_POS) - -#define CMU_LPENR_LOSCEN_POS 1U -#define CMU_LPENR_LOSCEN_MSK BIT(CMU_LPENR_LOSCEN_POS) - -#define CMU_LPENR_LRCEN_POS 0U -#define CMU_LPENR_LRCEN_MSK BIT(CMU_LPENR_LRCEN_POS) - -/****************** Bit definition for CMU_PERICR register ************************/ - -#define CMU_PERICR_LCD_POSS 16U -#define CMU_PERICR_LCD_POSE 18U -#define CMU_PERICR_LCD_MSK BITS(CMU_PERICR_LCD_POSS,CMU_PERICR_LCD_POSE) - -#define CMU_PERICR_LPUART0_POSS 8U -#define CMU_PERICR_LPUART0_POSE 11U -#define CMU_PERICR_LPUART0_MSK BITS(CMU_PERICR_LPUART0_POSS,CMU_PERICR_LPUART0_POSE) - -#define CMU_PERICR_LPTIM0_POSS 0U -#define CMU_PERICR_LPTIM0_POSE 3U -#define CMU_PERICR_LPTIM0_MSK BITS(CMU_PERICR_LPTIM0_POSS,CMU_PERICR_LPTIM0_POSE) - -/****************** Bit definition for CMU_HRCACR register ************************/ - -#define CMU_HRCACR_IB_POSS 28U -#define CMU_HRCACR_IB_POSE 29U -#define CMU_HRCACR_IB_MSK BITS(CMU_HRCACR_IB_POSS,CMU_HRCACR_IB_POSE) - -#define CMU_HRCACR_CAP_POSS 26U -#define CMU_HRCACR_CAP_POSE 27U -#define CMU_HRCACR_CAP_MSK BITS(CMU_HRCACR_CAP_POSS,CMU_HRCACR_CAP_POSE) - -#define CMU_HRCACR_CAL_POSS 16U -#define CMU_HRCACR_CAL_POSE 25U -#define CMU_HRCACR_CAL_MSK BITS(CMU_HRCACR_CAL_POSS,CMU_HRCACR_CAL_POSE) - -#define CMU_HRCACR_IBSET_POSS 14U -#define CMU_HRCACR_IBSET_POSE 15U -#define CMU_HRCACR_IBSET_MSK BITS(CMU_HRCACR_IBSET_POSS,CMU_HRCACR_IBSET_POSE) - -#define CMU_HRCACR_CAPSET_POSS 12U -#define CMU_HRCACR_CAPSET_POSE 13U -#define CMU_HRCACR_CAPSET_MSK BITS(CMU_HRCACR_CAPSET_POSS,CMU_HRCACR_CAPSET_POSE) - -#define CMU_HRCACR_STA_POSS 9U -#define CMU_HRCACR_STA_POSE 10U -#define CMU_HRCACR_STA_MSK BITS(CMU_HRCACR_STA_POSS,CMU_HRCACR_STA_POSE) - -#define CMU_HRCACR_BUSY_POS 8U -#define CMU_HRCACR_BUSY_MSK BIT(CMU_HRCACR_BUSY_POS) - -#define CMU_HRCACR_WRTRG_POS 7U -#define CMU_HRCACR_WRTRG_MSK BIT(CMU_HRCACR_WRTRG_POS) - -#define CMU_HRCACR_AC_POSS 4U -#define CMU_HRCACR_AC_POSE 6U -#define CMU_HRCACR_AC_MSK BITS(CMU_HRCACR_AC_POSS,CMU_HRCACR_AC_POSE) - -#define CMU_HRCACR_IBS_POS 3U -#define CMU_HRCACR_IBS_MSK BIT(CMU_HRCACR_IBS_POS) - -#define CMU_HRCACR_RFSEL_POS 2U -#define CMU_HRCACR_RFSEL_MSK BIT(CMU_HRCACR_RFSEL_POS) - -#define CMU_HRCACR_FREQ_POS 1U -#define CMU_HRCACR_FREQ_MSK BIT(CMU_HRCACR_FREQ_POS) - -#define CMU_HRCACR_EN_POS 0U -#define CMU_HRCACR_EN_MSK BIT(CMU_HRCACR_EN_POS) - -typedef struct -{ - __O uint32_t CSR; - __IO uint32_t CFGR; - uint32_t RESERVED0[2] ; - __IO uint32_t CLKENR; - __I uint32_t CLKSR; - __IO uint32_t PLLCFG; - __IO uint32_t HOSCCFG; - __IO uint32_t HOSMCR; - __IO uint32_t LOSMCR; - __IO uint32_t PULMCR; - uint32_t RESERVED1 ; - __IO uint32_t CLKOCR; - __IO uint32_t BUZZCR; - uint32_t RESERVED2[2] ; - __IO uint32_t AHB1ENR; - uint32_t RESERVED3[3] ; - __IO uint32_t APB1ENR; - __IO uint32_t APB2ENR; - uint32_t RESERVED4[2] ; - __IO uint32_t LPENR; - uint32_t RESERVED5[7] ; - __IO uint32_t PERICR; - uint32_t RESERVED6[3] ; - __IO uint32_t HRCACR; -} CMU_TypeDef; - -/****************** Bit definition for DMA_STATUS register ************************/ - -#define DMA_STATUS_STATUS_POSS 4U -#define DMA_STATUS_STATUS_POSE 7U -#define DMA_STATUS_STATUS_MSK BITS(DMA_STATUS_STATUS_POSS,DMA_STATUS_STATUS_POSE) - -#define DMA_STATUS_MASTER_ENABLE_POS 0U -#define DMA_STATUS_MASTER_ENABLE_MSK BIT(DMA_STATUS_MASTER_ENABLE_POS) - -/****************** Bit definition for DMA_CFG register ************************/ - -#define DMA_CFG_CHNL_PROT_CTRL_POSS 5U -#define DMA_CFG_CHNL_PROT_CTRL_POSE 7U -#define DMA_CFG_CHNL_PROT_CTRL_MSK BITS(DMA_CFG_CHNL_PROT_CTRL_POSS,DMA_CFG_CHNL_PROT_CTRL_POSE) - -#define DMA_CFG_MASTER_ENABLE_POS 0U -#define DMA_CFG_MASTER_ENABLE_MSK BIT(DMA_CFG_MASTER_ENABLE_POS) - -/****************** Bit definition for DMA_CTRLBASE register ************************/ - -#define DMA_CTRLBASE_CTRL_BASE_PTR_POSS 9U -#define DMA_CTRLBASE_CTRL_BASE_PTR_POSE 31U -#define DMA_CTRLBASE_CTRL_BASE_PTR_MSK BITS(DMA_CTRLBASE_CTRL_BASE_PTR_POSS,DMA_CTRLBASE_CTRL_BASE_PTR_POSE) - -/****************** Bit definition for DMA_ALTCTRLBASE register ************************/ - -#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSS 0U -#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSE 31U -#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_MSK BITS(DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSS,DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSE) - -/****************** Bit definition for DMA_CHWAITSTATUS register ************************/ - -#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS 0U -#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE 31U -#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_MSK BITS(DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS,DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE) - -/****************** Bit definition for DMA_CHSWREQ register ************************/ - -#define DMA_CHSWREQ_CHSWREQ_POSS 0U -#define DMA_CHSWREQ_CHSWREQ_POSE 31U -#define DMA_CHSWREQ_CHSWREQ_MSK BITS(DMA_CHSWREQ_CHSWREQ_POSS,DMA_CHSWREQ_CHSWREQ_POSE) - -/****************** Bit definition for DMA_CHUSEBURSTSET register ************************/ - -#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS 0U -#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE 31U -#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_MSK BITS(DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS,DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE) - -/****************** Bit definition for DMA_CHUSEBURSTCLR register ************************/ - -#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS 0U -#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE 31U -#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_MSK BITS(DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS,DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE) - -/****************** Bit definition for DMA_CHREQMASKSET register ************************/ - -#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS 0U -#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE 31U -#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_MSK BITS(DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS,DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE) - -/****************** Bit definition for DMA_CHREQMASKCLR register ************************/ - -#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS 0U -#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE 31U -#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_MSK BITS(DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS,DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE) - -/****************** Bit definition for DMA_CHENSET register ************************/ - -#define DMA_CHENSET_CHNL_ENABLE_SET_POSS 0U -#define DMA_CHENSET_CHNL_ENABLE_SET_POSE 31U -#define DMA_CHENSET_CHNL_ENABLE_SET_MSK BITS(DMA_CHENSET_CHNL_ENABLE_SET_POSS,DMA_CHENSET_CHNL_ENABLE_SET_POSE) - -/****************** Bit definition for DMA_CHENCLR register ************************/ - -#define DMA_CHENCLR_CHNL_ENABLE_CLR_POSS 0U -#define DMA_CHENCLR_CHNL_ENABLE_CLR_POSE 31U -#define DMA_CHENCLR_CHNL_ENABLE_CLR_MSK BITS(DMA_CHENCLR_CHNL_ENABLE_CLR_POSS,DMA_CHENCLR_CHNL_ENABLE_CLR_POSE) - -/****************** Bit definition for DMA_CHPRIALTSET register ************************/ - -#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS 0U -#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE 31U -#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_MSK BITS(DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS,DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE) - -/****************** Bit definition for DMA_CHPRIALTCLR register ************************/ - -#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS 0U -#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE 31U -#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_MSK BITS(DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS,DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE) - -/****************** Bit definition for DMA_CHPRSET register ************************/ - -#define DMA_CHPRSET_CHNL_PRIORITY_SET_POSS 0U -#define DMA_CHPRSET_CHNL_PRIORITY_SET_POSE 31U -#define DMA_CHPRSET_CHNL_PRIORITY_SET_MSK BITS(DMA_CHPRSET_CHNL_PRIORITY_SET_POSS,DMA_CHPRSET_CHNL_PRIORITY_SET_POSE) - -/****************** Bit definition for DMA_CHPRCLR register ************************/ - -#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS 0U -#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE 31U -#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_MSK BITS(DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS,DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE) - -/****************** Bit definition for DMA_ERRCLR register ************************/ - -#define DMA_ERRCLR_ERR_CLR_POS 0U -#define DMA_ERRCLR_ERR_CLR_MSK BIT(DMA_ERRCLR_ERR_CLR_POS) - -/****************** Bit definition for DMA_IFLAG register ************************/ - -#define DMA_IFLAG_DMAERRIF_POS 31U -#define DMA_IFLAG_DMAERRIF_MSK BIT(DMA_IFLAG_DMAERRIF_POS) - -#define DMA_IFLAG_CH5DONEIF_POS 5U -#define DMA_IFLAG_CH5DONEIF_MSK BIT(DMA_IFLAG_CH5DONEIF_POS) - -#define DMA_IFLAG_CH4DONEIF_POS 4U -#define DMA_IFLAG_CH4DONEIF_MSK BIT(DMA_IFLAG_CH4DONEIF_POS) - -#define DMA_IFLAG_CH3DONEIF_POS 3U -#define DMA_IFLAG_CH3DONEIF_MSK BIT(DMA_IFLAG_CH3DONEIF_POS) - -#define DMA_IFLAG_CH2DONEIF_POS 2U -#define DMA_IFLAG_CH2DONEIF_MSK BIT(DMA_IFLAG_CH2DONEIF_POS) - -#define DMA_IFLAG_CH1DONEIF_POS 1U -#define DMA_IFLAG_CH1DONEIF_MSK BIT(DMA_IFLAG_CH1DONEIF_POS) - -#define DMA_IFLAG_CH0DONEIF_POS 0U -#define DMA_IFLAG_CH0DONEIF_MSK BIT(DMA_IFLAG_CH0DONEIF_POS) - -/****************** Bit definition for DMA_ICFR register ************************/ - -#define DMA_ICFR_DMAERRC_POS 31U -#define DMA_ICFR_DMAERRC_MSK BIT(DMA_ICFR_DMAERRC_POS) - -#define DMA_ICFR_CH5DONEC_POS 5U -#define DMA_ICFR_CH5DONEC_MSK BIT(DMA_ICFR_CH5DONEC_POS) - -#define DMA_ICFR_CH4DONEC_POS 4U -#define DMA_ICFR_CH4DONEC_MSK BIT(DMA_ICFR_CH4DONEC_POS) - -#define DMA_ICFR_CH3DONEC_POS 3U -#define DMA_ICFR_CH3DONEC_MSK BIT(DMA_ICFR_CH3DONEC_POS) - -#define DMA_ICFR_CH2DONEC_POS 2U -#define DMA_ICFR_CH2DONEC_MSK BIT(DMA_ICFR_CH2DONEC_POS) - -#define DMA_ICFR_CH1DONEC_POS 1U -#define DMA_ICFR_CH1DONEC_MSK BIT(DMA_ICFR_CH1DONEC_POS) - -#define DMA_ICFR_CH0DONEC_POS 0U -#define DMA_ICFR_CH0DONEC_MSK BIT(DMA_ICFR_CH0DONEC_POS) - -/****************** Bit definition for DMA_IER register ************************/ - -#define DMA_IER_DMAERRIE_POS 31U -#define DMA_IER_DMAERRIE_MSK BIT(DMA_IER_DMAERRIE_POS) - -#define DMA_IER_CH5DONEIE_POS 5U -#define DMA_IER_CH5DONEIE_MSK BIT(DMA_IER_CH5DONEIE_POS) - -#define DMA_IER_CH4DONEIE_POS 4U -#define DMA_IER_CH4DONEIE_MSK BIT(DMA_IER_CH4DONEIE_POS) - -#define DMA_IER_CH3DONEIE_POS 3U -#define DMA_IER_CH3DONEIE_MSK BIT(DMA_IER_CH3DONEIE_POS) - -#define DMA_IER_CH2DONEIE_POS 2U -#define DMA_IER_CH2DONEIE_MSK BIT(DMA_IER_CH2DONEIE_POS) - -#define DMA_IER_CH1DONEIE_POS 1U -#define DMA_IER_CH1DONEIE_MSK BIT(DMA_IER_CH1DONEIE_POS) - -#define DMA_IER_CH0DONEIE_POS 0U -#define DMA_IER_CH0DONEIE_MSK BIT(DMA_IER_CH0DONEIE_POS) - -/****************** Bit definition for DMA_CH0_SELCON register ************************/ - -#define DMA_CH0_SELCON_MSEL_POSS 8U -#define DMA_CH0_SELCON_MSEL_POSE 13U -#define DMA_CH0_SELCON_MSEL_MSK BITS(DMA_CH0_SELCON_MSEL_POSS,DMA_CH0_SELCON_MSEL_POSE) - -#define DMA_CH0_SELCON_MSIGSEL_POSS 0U -#define DMA_CH0_SELCON_MSIGSEL_POSE 3U -#define DMA_CH0_SELCON_MSIGSEL_MSK BITS(DMA_CH0_SELCON_MSIGSEL_POSS,DMA_CH0_SELCON_MSIGSEL_POSE) - -typedef struct -{ - __I uint32_t STATUS; - __IO uint32_t CFG; - __IO uint32_t CTRLBASE; - __I uint32_t ALTCTRLBASE; - __I uint32_t CHWAITSTATUS; - __IO uint32_t CHSWREQ; - __IO uint32_t CHUSEBURSTSET; - __O uint32_t CHUSEBURSTCLR; - __IO uint32_t CHREQMASKSET; - __O uint32_t CHREQMASKCLR; - __IO uint32_t CHENSET; - __O uint32_t CHENCLR; - __IO uint32_t CHPRIALTSET; - __O uint32_t CHPRIALTCLR; - __IO uint32_t CHPRSET; - __O uint32_t CHPRCLR; - uint32_t RESERVED0[3] ; - __IO uint32_t ERRCLR; - uint32_t RESERVED1[1004] ; - __I uint32_t IFLAG; - uint32_t RESERVED2 ; - __O uint32_t ICFR; - __IO uint32_t IER; - uint32_t RESERVED3[60] ; - __IO uint32_t CH_SELCON[6]; -} DMA_TypeDef; - -/****************** Bit definition for PIS_CH0_CON register ************************/ - -#define PIS_CH0_CON_SYNCSEL_POSS 24U -#define PIS_CH0_CON_SYNCSEL_POSE 26U -#define PIS_CH0_CON_SYNCSEL_MSK BITS(PIS_CH0_CON_SYNCSEL_POSS,PIS_CH0_CON_SYNCSEL_POSE) - -#define PIS_CH0_CON_PULCK_POSS 18U -#define PIS_CH0_CON_PULCK_POSE 19U -#define PIS_CH0_CON_PULCK_MSK BITS(PIS_CH0_CON_PULCK_POSS,PIS_CH0_CON_PULCK_POSE) - -#define PIS_CH0_CON_EDGS_POSS 16U -#define PIS_CH0_CON_EDGS_POSE 17U -#define PIS_CH0_CON_EDGS_MSK BITS(PIS_CH0_CON_EDGS_POSS,PIS_CH0_CON_EDGS_POSE) - -#define PIS_CH0_CON_SRCS_POSS 8U -#define PIS_CH0_CON_SRCS_POSE 13U -#define PIS_CH0_CON_SRCS_MSK BITS(PIS_CH0_CON_SRCS_POSS,PIS_CH0_CON_SRCS_POSE) - -#define PIS_CH0_CON_MSIGS_POSS 0U -#define PIS_CH0_CON_MSIGS_POSE 3U -#define PIS_CH0_CON_MSIGS_MSK BITS(PIS_CH0_CON_MSIGS_POSS,PIS_CH0_CON_MSIGS_POSE) - -/****************** Bit definition for PIS_CH_OER register ************************/ - -#define PIS_CH_OER_CH3OE_POS 3U -#define PIS_CH_OER_CH3OE_MSK BIT(PIS_CH_OER_CH3OE_POS) - -#define PIS_CH_OER_CH2OE_POS 2U -#define PIS_CH_OER_CH2OE_MSK BIT(PIS_CH_OER_CH2OE_POS) - -#define PIS_CH_OER_CH1OE_POS 1U -#define PIS_CH_OER_CH1OE_MSK BIT(PIS_CH_OER_CH1OE_POS) - -#define PIS_CH_OER_CH0OE_POS 0U -#define PIS_CH_OER_CH0OE_MSK BIT(PIS_CH_OER_CH0OE_POS) - -/****************** Bit definition for PIS_TAR_CON0 register ************************/ - -#define PIS_TAR_CON0_TIM3_CH2IN_SEL_POS 25U -#define PIS_TAR_CON0_TIM3_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH2IN_SEL_POS) - -#define PIS_TAR_CON0_TIM3_CH1IN_SEL_POS 24U -#define PIS_TAR_CON0_TIM3_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH1IN_SEL_POS) - -#define PIS_TAR_CON0_TIM2_CH2IN_SEL_POS 17U -#define PIS_TAR_CON0_TIM2_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH2IN_SEL_POS) - -#define PIS_TAR_CON0_TIM2_CH1IN_SEL_POS 16U -#define PIS_TAR_CON0_TIM2_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH1IN_SEL_POS) - -#define PIS_TAR_CON0_TIM0_BRKIN_SEL_POS 4U -#define PIS_TAR_CON0_TIM0_BRKIN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_BRKIN_SEL_POS) - -#define PIS_TAR_CON0_TIM0_CH4IN_SEL_POS 3U -#define PIS_TAR_CON0_TIM0_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH4IN_SEL_POS) - -#define PIS_TAR_CON0_TIM0_CH3IN_SEL_POS 2U -#define PIS_TAR_CON0_TIM0_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH3IN_SEL_POS) - -#define PIS_TAR_CON0_TIM0_CH2IN_SEL_POS 1U -#define PIS_TAR_CON0_TIM0_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH2IN_SEL_POS) - -#define PIS_TAR_CON0_TIM0_CH1IN_SEL_POS 0U -#define PIS_TAR_CON0_TIM0_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH1IN_SEL_POS) - -/****************** Bit definition for PIS_TAR_CON1 register ************************/ - -#define PIS_TAR_CON1_SPI1_CLK_SEL_POS 15U -#define PIS_TAR_CON1_SPI1_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI1_CLK_SEL_POS) - -#define PIS_TAR_CON1_SPI1_RX_SEL_POS 14U -#define PIS_TAR_CON1_SPI1_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI1_RX_SEL_POS) - -#define PIS_TAR_CON1_SPI0_CLK_SEL_POS 13U -#define PIS_TAR_CON1_SPI0_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI0_CLK_SEL_POS) - -#define PIS_TAR_CON1_SPI0_RX_SEL_POS 12U -#define PIS_TAR_CON1_SPI0_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI0_RX_SEL_POS) - -#define PIS_TAR_CON1_LPUART0_RXD_SEL_POS 8U -#define PIS_TAR_CON1_LPUART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_LPUART0_RXD_SEL_POS) - -#define PIS_TAR_CON1_USART1_RXD_SEL_POS 7U -#define PIS_TAR_CON1_USART1_RXD_SEL_MSK BIT(PIS_TAR_CON1_USART1_RXD_SEL_POS) - -#define PIS_TAR_CON1_USART0_RXD_SEL_POS 6U -#define PIS_TAR_CON1_USART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_USART0_RXD_SEL_POS) - -#define PIS_TAR_CON1_UART3_RXD_SEL_POS 3U -#define PIS_TAR_CON1_UART3_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART3_RXD_SEL_POS) - -#define PIS_TAR_CON1_UART2_RXD_SEL_POS 2U -#define PIS_TAR_CON1_UART2_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART2_RXD_SEL_POS) - -#define PIS_TAR_CON1_UART1_RXD_SEL_POS 1U -#define PIS_TAR_CON1_UART1_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART1_RXD_SEL_POS) - -#define PIS_TAR_CON1_UART0_RXD_SEL_POS 0U -#define PIS_TAR_CON1_UART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART0_RXD_SEL_POS) - -/****************** Bit definition for PIS_TXMCR register ************************/ - -#define PIS_TXMCR_TXMLVLS_POS 8U -#define PIS_TXMCR_TXMLVLS_MSK BIT(PIS_TXMCR_TXMLVLS_POS) - -#define PIS_TXMCR_TXMSS_POSS 4U -#define PIS_TXMCR_TXMSS_POSE 7U -#define PIS_TXMCR_TXMSS_MSK BITS(PIS_TXMCR_TXMSS_POSS,PIS_TXMCR_TXMSS_POSE) - -#define PIS_TXMCR_TXSIGS_POSS 0U -#define PIS_TXMCR_TXSIGS_POSE 3U -#define PIS_TXMCR_TXSIGS_MSK BITS(PIS_TXMCR_TXSIGS_POSS,PIS_TXMCR_TXSIGS_POSE) - -typedef struct -{ - __IO uint32_t CH_CON[8]; - uint32_t RESERVED0[8] ; - __IO uint32_t CH_OER; - __IO uint32_t TAR_CON0; - __IO uint32_t TAR_CON1; - uint32_t RESERVED1[5] ; - __IO uint32_t UART0_TXMCR; - __IO uint32_t UART1_TXMCR; - __IO uint32_t UART2_TXMCR; - __IO uint32_t UART3_TXMCR; - __IO uint32_t LPUART0_TXMCR; -} PIS_TypeDef; - -/****************** Bit definition for GPIO_DIN register ************************/ - -#define GPIO_DIN_DIN_POSS 0U -#define GPIO_DIN_DIN_POSE 15U -#define GPIO_DIN_DIN_MSK BITS(GPIO_DIN_DIN_POSS,GPIO_DIN_DIN_POSE) - -/****************** Bit definition for GPIO_DOUT register ************************/ - -#define GPIO_DOUT_DOUT_POSS 0U -#define GPIO_DOUT_DOUT_POSE 15U -#define GPIO_DOUT_DOUT_MSK BITS(GPIO_DOUT_DOUT_POSS,GPIO_DOUT_DOUT_POSE) - -/****************** Bit definition for GPIO_BSRR register ************************/ - -#define GPIO_BSRR_BRR_POSS 16U -#define GPIO_BSRR_BRR_POSE 31U -#define GPIO_BSRR_BRR_MSK BITS(GPIO_BSRR_BRR_POSS,GPIO_BSRR_BRR_POSE) - -#define GPIO_BSRR_BSR_POSS 0U -#define GPIO_BSRR_BSR_POSE 15U -#define GPIO_BSRR_BSR_MSK BITS(GPIO_BSRR_BSR_POSS,GPIO_BSRR_BSR_POSE) - -/****************** Bit definition for GPIO_BIR register ************************/ - -#define GPIO_BIR_BIR_POSS 0U -#define GPIO_BIR_BIR_POSE 15U -#define GPIO_BIR_BIR_MSK BITS(GPIO_BIR_BIR_POSS,GPIO_BIR_BIR_POSE) - -/****************** Bit definition for GPIO_MODE register ************************/ - -#define GPIO_MODE_MODE_POSS 0U -#define GPIO_MODE_MODE_POSE 31U -#define GPIO_MODE_MODE_MSK BITS(GPIO_MODE_MODE_POSS,GPIO_MODE_MODE_POSE) - -/****************** Bit definition for GPIO_ODOS register ************************/ - -#define GPIO_ODOS_ODOS_POSS 0U -#define GPIO_ODOS_ODOS_POSE 31U -#define GPIO_ODOS_ODOS_MSK BITS(GPIO_ODOS_ODOS_POSS,GPIO_ODOS_ODOS_POSE) - -/****************** Bit definition for GPIO_PUPD register ************************/ - -#define GPIO_PUPD_PUPD_POSS 0U -#define GPIO_PUPD_PUPD_POSE 31U -#define GPIO_PUPD_PUPD_MSK BITS(GPIO_PUPD_PUPD_POSS,GPIO_PUPD_PUPD_POSE) - -/****************** Bit definition for GPIO_ODRV register ************************/ - -#define GPIO_ODRV_ODRV_POSS 0U -#define GPIO_ODRV_ODRV_POSE 31U -#define GPIO_ODRV_ODRV_MSK BITS(GPIO_ODRV_ODRV_POSS,GPIO_ODRV_ODRV_POSE) - -/****************** Bit definition for GPIO_FLT register ************************/ - -#define GPIO_FLT_FLT_POSS 0U -#define GPIO_FLT_FLT_POSE 15U -#define GPIO_FLT_FLT_MSK BITS(GPIO_FLT_FLT_POSS,GPIO_FLT_FLT_POSE) - -/****************** Bit definition for GPIO_TYPE register ************************/ - -#define GPIO_TYPE_TYPE_POSS 0U -#define GPIO_TYPE_TYPE_POSE 15U -#define GPIO_TYPE_TYPE_MSK BITS(GPIO_TYPE_TYPE_POSS,GPIO_TYPE_TYPE_POSE) - -/****************** Bit definition for GPIO_FUNC0 register ************************/ - -#define GPIO_FUNC0_FSEL_IO7_POSS 28U -#define GPIO_FUNC0_FSEL_IO7_POSE 31U -#define GPIO_FUNC0_FSEL_IO7_MSK BITS(GPIO_FUNC0_FSEL_IO7_POSS,GPIO_FUNC0_FSEL_IO7_POSE) - -#define GPIO_FUNC0_FSEL_IO6_POSS 24U -#define GPIO_FUNC0_FSEL_IO6_POSE 27U -#define GPIO_FUNC0_FSEL_IO6_MSK BITS(GPIO_FUNC0_FSEL_IO6_POSS,GPIO_FUNC0_FSEL_IO6_POSE) - -#define GPIO_FUNC0_FSEL_IO5_POSS 20U -#define GPIO_FUNC0_FSEL_IO5_POSE 23U -#define GPIO_FUNC0_FSEL_IO5_MSK BITS(GPIO_FUNC0_FSEL_IO5_POSS,GPIO_FUNC0_FSEL_IO5_POSE) - -#define GPIO_FUNC0_FSEL_IO4_POSS 16U -#define GPIO_FUNC0_FSEL_IO4_POSE 19U -#define GPIO_FUNC0_FSEL_IO4_MSK BITS(GPIO_FUNC0_FSEL_IO4_POSS,GPIO_FUNC0_FSEL_IO4_POSE) - -#define GPIO_FUNC0_FSEL_IO3_POSS 12U -#define GPIO_FUNC0_FSEL_IO3_POSE 15U -#define GPIO_FUNC0_FSEL_IO3_MSK BITS(GPIO_FUNC0_FSEL_IO3_POSS,GPIO_FUNC0_FSEL_IO3_POSE) - -#define GPIO_FUNC0_FSEL_IO2_POSS 8U -#define GPIO_FUNC0_FSEL_IO2_POSE 11U -#define GPIO_FUNC0_FSEL_IO2_MSK BITS(GPIO_FUNC0_FSEL_IO2_POSS,GPIO_FUNC0_FSEL_IO2_POSE) - -#define GPIO_FUNC0_FSEL_IO1_POSS 4U -#define GPIO_FUNC0_FSEL_IO1_POSE 7U -#define GPIO_FUNC0_FSEL_IO1_MSK BITS(GPIO_FUNC0_FSEL_IO1_POSS,GPIO_FUNC0_FSEL_IO1_POSE) - -#define GPIO_FUNC0_FSEL_IO0_POSS 0U -#define GPIO_FUNC0_FSEL_IO0_POSE 3U -#define GPIO_FUNC0_FSEL_IO0_MSK BITS(GPIO_FUNC0_FSEL_IO0_POSS,GPIO_FUNC0_FSEL_IO0_POSE) - -/****************** Bit definition for GPIO_FUNC1 register ************************/ - -#define GPIO_FUNC1_FSEL_IO15_POSS 28U -#define GPIO_FUNC1_FSEL_IO15_POSE 31U -#define GPIO_FUNC1_FSEL_IO15_MSK BITS(GPIO_FUNC1_FSEL_IO15_POSS,GPIO_FUNC1_FSEL_IO15_POSE) - -#define GPIO_FUNC1_FSEL_IO14_POSS 24U -#define GPIO_FUNC1_FSEL_IO14_POSE 27U -#define GPIO_FUNC1_FSEL_IO14_MSK BITS(GPIO_FUNC1_FSEL_IO14_POSS,GPIO_FUNC1_FSEL_IO14_POSE) - -#define GPIO_FUNC1_FSEL_IO13_POSS 20U -#define GPIO_FUNC1_FSEL_IO13_POSE 23U -#define GPIO_FUNC1_FSEL_IO13_MSK BITS(GPIO_FUNC1_FSEL_IO13_POSS,GPIO_FUNC1_FSEL_IO13_POSE) - -#define GPIO_FUNC1_FSEL_IO12_POSS 16U -#define GPIO_FUNC1_FSEL_IO12_POSE 19U -#define GPIO_FUNC1_FSEL_IO12_MSK BITS(GPIO_FUNC1_FSEL_IO12_POSS,GPIO_FUNC1_FSEL_IO12_POSE) - -#define GPIO_FUNC1_FSEL_IO11_POSS 12U -#define GPIO_FUNC1_FSEL_IO11_POSE 15U -#define GPIO_FUNC1_FSEL_IO11_MSK BITS(GPIO_FUNC1_FSEL_IO11_POSS,GPIO_FUNC1_FSEL_IO11_POSE) - -#define GPIO_FUNC1_FSEL_IO10_POSS 8U -#define GPIO_FUNC1_FSEL_IO10_POSE 11U -#define GPIO_FUNC1_FSEL_IO10_MSK BITS(GPIO_FUNC1_FSEL_IO10_POSS,GPIO_FUNC1_FSEL_IO10_POSE) - -#define GPIO_FUNC1_FSEL_IO9_POSS 4U -#define GPIO_FUNC1_FSEL_IO9_POSE 7U -#define GPIO_FUNC1_FSEL_IO9_MSK BITS(GPIO_FUNC1_FSEL_IO9_POSS,GPIO_FUNC1_FSEL_IO9_POSE) - -#define GPIO_FUNC1_FSEL_IO8_POSS 0U -#define GPIO_FUNC1_FSEL_IO8_POSE 3U -#define GPIO_FUNC1_FSEL_IO8_MSK BITS(GPIO_FUNC1_FSEL_IO8_POSS,GPIO_FUNC1_FSEL_IO8_POSE) - -/****************** Bit definition for GPIO_LOCK register ************************/ - -#define GPIO_LOCK_KEY_POSS 16U -#define GPIO_LOCK_KEY_POSE 31U -#define GPIO_LOCK_KEY_MSK BITS(GPIO_LOCK_KEY_POSS,GPIO_LOCK_KEY_POSE) - -#define GPIO_LOCK_LOCK_POSS 0U -#define GPIO_LOCK_LOCK_POSE 15U -#define GPIO_LOCK_LOCK_MSK BITS(GPIO_LOCK_LOCK_POSS,GPIO_LOCK_LOCK_POSE) - -typedef struct -{ - __I uint32_t DIN; - __IO uint32_t DOUT; - __O uint32_t BSRR; - __O uint32_t BIR; - __IO uint32_t MODE; - __IO uint32_t ODOS; - __IO uint32_t PUPD; - __IO uint32_t ODRV; - __IO uint32_t FLT; - __IO uint32_t TYPE; - __IO uint32_t FUNC0; - __IO uint32_t FUNC1; - __IO uint32_t LOCK; -} GPIO_TypeDef; - -/****************** Bit definition for GPIO_EXTIRER register ************************/ - -#define GPIO_EXTIRER_EXTIRER_POSS 0U -#define GPIO_EXTIRER_EXTIRER_POSE 15U -#define GPIO_EXTIRER_EXTIRER_MSK BITS(GPIO_EXTIRER_EXTIRER_POSS,GPIO_EXTIRER_EXTIRER_POSE) - -/****************** Bit definition for GPIO_EXTIFER register ************************/ - -#define GPIO_EXTIFER_EXTIFER_POSS 0U -#define GPIO_EXTIFER_EXTIFER_POSE 15U -#define GPIO_EXTIFER_EXTIFER_MSK BITS(GPIO_EXTIFER_EXTIFER_POSS,GPIO_EXTIFER_EXTIFER_POSE) - -/****************** Bit definition for GPIO_EXTIEN register ************************/ - -#define GPIO_EXTIEN_EXTIEN_POSS 0U -#define GPIO_EXTIEN_EXTIEN_POSE 15U -#define GPIO_EXTIEN_EXTIEN_MSK BITS(GPIO_EXTIEN_EXTIEN_POSS,GPIO_EXTIEN_EXTIEN_POSE) - -/****************** Bit definition for GPIO_EXTIFLAG register ************************/ - -#define GPIO_EXTIFLAG_EXTIFLAG_POSS 0U -#define GPIO_EXTIFLAG_EXTIFLAG_POSE 15U -#define GPIO_EXTIFLAG_EXTIFLAG_MSK BITS(GPIO_EXTIFLAG_EXTIFLAG_POSS,GPIO_EXTIFLAG_EXTIFLAG_POSE) - -/****************** Bit definition for GPIO_EXTISFR register ************************/ - -#define GPIO_EXTISFR_EXTISFR_POSS 0U -#define GPIO_EXTISFR_EXTISFR_POSE 15U -#define GPIO_EXTISFR_EXTISFR_MSK BITS(GPIO_EXTISFR_EXTISFR_POSS,GPIO_EXTISFR_EXTISFR_POSE) - -/****************** Bit definition for GPIO_EXTICFR register ************************/ - -#define GPIO_EXTICFR_EXTICFR_POSS 0U -#define GPIO_EXTICFR_EXTICFR_POSE 15U -#define GPIO_EXTICFR_EXTICFR_MSK BITS(GPIO_EXTICFR_EXTICFR_POSS,GPIO_EXTICFR_EXTICFR_POSE) - -/****************** Bit definition for GPIO_EXTIPSR0 register ************************/ - -#define GPIO_EXTIPSR0_EXTIS7_POSS 28U -#define GPIO_EXTIPSR0_EXTIS7_POSE 30U -#define GPIO_EXTIPSR0_EXTIS7_MSK BITS(GPIO_EXTIPSR0_EXTIS7_POSS,GPIO_EXTIPSR0_EXTIS7_POSE) - -#define GPIO_EXTIPSR0_EXTIS6_POSS 24U -#define GPIO_EXTIPSR0_EXTIS6_POSE 26U -#define GPIO_EXTIPSR0_EXTIS6_MSK BITS(GPIO_EXTIPSR0_EXTIS6_POSS,GPIO_EXTIPSR0_EXTIS6_POSE) - -#define GPIO_EXTIPSR0_EXTIS5_POSS 20U -#define GPIO_EXTIPSR0_EXTIS5_POSE 22U -#define GPIO_EXTIPSR0_EXTIS5_MSK BITS(GPIO_EXTIPSR0_EXTIS5_POSS,GPIO_EXTIPSR0_EXTIS5_POSE) - -#define GPIO_EXTIPSR0_EXTIS4_POSS 16U -#define GPIO_EXTIPSR0_EXTIS4_POSE 18U -#define GPIO_EXTIPSR0_EXTIS4_MSK BITS(GPIO_EXTIPSR0_EXTIS4_POSS,GPIO_EXTIPSR0_EXTIS4_POSE) - -#define GPIO_EXTIPSR0_EXTIS3_POSS 12U -#define GPIO_EXTIPSR0_EXTIS3_POSE 14U -#define GPIO_EXTIPSR0_EXTIS3_MSK BITS(GPIO_EXTIPSR0_EXTIS3_POSS,GPIO_EXTIPSR0_EXTIS3_POSE) - -#define GPIO_EXTIPSR0_EXTIS2_POSS 8U -#define GPIO_EXTIPSR0_EXTIS2_POSE 10U -#define GPIO_EXTIPSR0_EXTIS2_MSK BITS(GPIO_EXTIPSR0_EXTIS2_POSS,GPIO_EXTIPSR0_EXTIS2_POSE) - -#define GPIO_EXTIPSR0_EXTIS1_POSS 4U -#define GPIO_EXTIPSR0_EXTIS1_POSE 6U -#define GPIO_EXTIPSR0_EXTIS1_MSK BITS(GPIO_EXTIPSR0_EXTIS1_POSS,GPIO_EXTIPSR0_EXTIS1_POSE) - -#define GPIO_EXTIPSR0_EXTIS0_POSS 0U -#define GPIO_EXTIPSR0_EXTIS0_POSE 2U -#define GPIO_EXTIPSR0_EXTIS0_MSK BITS(GPIO_EXTIPSR0_EXTIS0_POSS,GPIO_EXTIPSR0_EXTIS0_POSE) - -/****************** Bit definition for GPIO_EXTIPSR1 register ************************/ - -#define GPIO_EXTIPSR1_EXTIS15_POSS 28U -#define GPIO_EXTIPSR1_EXTIS15_POSE 30U -#define GPIO_EXTIPSR1_EXTIS15_MSK BITS(GPIO_EXTIPSR1_EXTIS15_POSS,GPIO_EXTIPSR1_EXTIS15_POSE) - -#define GPIO_EXTIPSR1_EXTIS14_POSS 24U -#define GPIO_EXTIPSR1_EXTIS14_POSE 26U -#define GPIO_EXTIPSR1_EXTIS14_MSK BITS(GPIO_EXTIPSR1_EXTIS14_POSS,GPIO_EXTIPSR1_EXTIS14_POSE) - -#define GPIO_EXTIPSR1_EXTIS13_POSS 20U -#define GPIO_EXTIPSR1_EXTIS13_POSE 22U -#define GPIO_EXTIPSR1_EXTIS13_MSK BITS(GPIO_EXTIPSR1_EXTIS13_POSS,GPIO_EXTIPSR1_EXTIS13_POSE) - -#define GPIO_EXTIPSR1_EXTIS12_POSS 16U -#define GPIO_EXTIPSR1_EXTIS12_POSE 18U -#define GPIO_EXTIPSR1_EXTIS12_MSK BITS(GPIO_EXTIPSR1_EXTIS12_POSS,GPIO_EXTIPSR1_EXTIS12_POSE) - -#define GPIO_EXTIPSR1_EXTIS11_POSS 12U -#define GPIO_EXTIPSR1_EXTIS11_POSE 14U -#define GPIO_EXTIPSR1_EXTIS11_MSK BITS(GPIO_EXTIPSR1_EXTIS11_POSS,GPIO_EXTIPSR1_EXTIS11_POSE) - -#define GPIO_EXTIPSR1_EXTIS10_POSS 8U -#define GPIO_EXTIPSR1_EXTIS10_POSE 10U -#define GPIO_EXTIPSR1_EXTIS10_MSK BITS(GPIO_EXTIPSR1_EXTIS10_POSS,GPIO_EXTIPSR1_EXTIS10_POSE) - -#define GPIO_EXTIPSR1_EXTIS9_POSS 4U -#define GPIO_EXTIPSR1_EXTIS9_POSE 6U -#define GPIO_EXTIPSR1_EXTIS9_MSK BITS(GPIO_EXTIPSR1_EXTIS9_POSS,GPIO_EXTIPSR1_EXTIS9_POSE) - -#define GPIO_EXTIPSR1_EXTIS8_POSS 0U -#define GPIO_EXTIPSR1_EXTIS8_POSE 2U -#define GPIO_EXTIPSR1_EXTIS8_MSK BITS(GPIO_EXTIPSR1_EXTIS8_POSS,GPIO_EXTIPSR1_EXTIS8_POSE) - -/****************** Bit definition for GPIO_EXTIFLTCR register ************************/ - -#define GPIO_EXTIFLTCR_FLTCKS_POSS 24U -#define GPIO_EXTIFLTCR_FLTCKS_POSE 25U -#define GPIO_EXTIFLTCR_FLTCKS_MSK BITS(GPIO_EXTIFLTCR_FLTCKS_POSS,GPIO_EXTIFLTCR_FLTCKS_POSE) - -#define GPIO_EXTIFLTCR_FLTSEL_POSS 16U -#define GPIO_EXTIFLTCR_FLTSEL_POSE 23U -#define GPIO_EXTIFLTCR_FLTSEL_MSK BITS(GPIO_EXTIFLTCR_FLTSEL_POSS,GPIO_EXTIFLTCR_FLTSEL_POSE) - -#define GPIO_EXTIFLTCR_FLTEN_POSS 0U -#define GPIO_EXTIFLTCR_FLTEN_POSE 15U -#define GPIO_EXTIFLTCR_FLTEN_MSK BITS(GPIO_EXTIFLTCR_FLTEN_POSS,GPIO_EXTIFLTCR_FLTEN_POSE) - -typedef struct -{ - __IO uint32_t EXTIRER; - uint32_t RESERVED0 ; - __IO uint32_t EXTIFER; - uint32_t RESERVED1 ; - __IO uint32_t EXTIEN; - uint32_t RESERVED2 ; - __I uint32_t EXTIFLAG; - uint32_t RESERVED3 ; - __O uint32_t EXTISFR; - uint32_t RESERVED4 ; - __O uint32_t EXTICFR; - uint32_t RESERVED5 ; - __IO uint32_t EXTIPSR0; - __IO uint32_t EXTIPSR1; - uint32_t RESERVED6[2] ; - __IO uint32_t EXTIFLTCR; -} EXTI_TypeDef; - -/****************** Bit definition for RTC_WPR register ************************/ - -#define RTC_WPR_WP_POS 0U -#define RTC_WPR_WP_MSK BIT(RTC_WPR_WP_POS) - -/****************** Bit definition for RTC_CON register ************************/ - -#define RTC_CON_SSEC_POS 25U -#define RTC_CON_SSEC_MSK BIT(RTC_CON_SSEC_POS) - -#define RTC_CON_BUSY_POS 24U -#define RTC_CON_BUSY_MSK BIT(RTC_CON_BUSY_POS) - -#define RTC_CON_POL_POS 22U -#define RTC_CON_POL_MSK BIT(RTC_CON_POL_POS) - -#define RTC_CON_EOS_POSS 20U -#define RTC_CON_EOS_POSE 21U -#define RTC_CON_EOS_MSK BITS(RTC_CON_EOS_POSS,RTC_CON_EOS_POSE) - -#define RTC_CON_CKOS_POSS 17U -#define RTC_CON_CKOS_POSE 19U -#define RTC_CON_CKOS_MSK BITS(RTC_CON_CKOS_POSS,RTC_CON_CKOS_POSE) - -#define RTC_CON_CKOE_POS 16U -#define RTC_CON_CKOE_MSK BIT(RTC_CON_CKOE_POS) - -#define RTC_CON_WUCKS_POSS 13U -#define RTC_CON_WUCKS_POSE 15U -#define RTC_CON_WUCKS_MSK BITS(RTC_CON_WUCKS_POSS,RTC_CON_WUCKS_POSE) - -#define RTC_CON_WUTE_POS 12U -#define RTC_CON_WUTE_MSK BIT(RTC_CON_WUTE_POS) - -#define RTC_CON_DSTS_POS 10U -#define RTC_CON_DSTS_MSK BIT(RTC_CON_DSTS_POS) - -#define RTC_CON_SUB1H_POS 9U -#define RTC_CON_SUB1H_MSK BIT(RTC_CON_SUB1H_POS) - -#define RTC_CON_ADD1H_POS 8U -#define RTC_CON_ADD1H_MSK BIT(RTC_CON_ADD1H_POS) - -#define RTC_CON_TSPIN_POS 7U -#define RTC_CON_TSPIN_MSK BIT(RTC_CON_TSPIN_POS) - -#define RTC_CON_TSSEL_POS 6U -#define RTC_CON_TSSEL_MSK BIT(RTC_CON_TSSEL_POS) - -#define RTC_CON_TSEN_POS 5U -#define RTC_CON_TSEN_MSK BIT(RTC_CON_TSEN_POS) - -#define RTC_CON_SHDBP_POS 4U -#define RTC_CON_SHDBP_MSK BIT(RTC_CON_SHDBP_POS) - -#define RTC_CON_HFM_POS 3U -#define RTC_CON_HFM_MSK BIT(RTC_CON_HFM_POS) - -#define RTC_CON_ALMBEN_POS 2U -#define RTC_CON_ALMBEN_MSK BIT(RTC_CON_ALMBEN_POS) - -#define RTC_CON_ALMAEN_POS 1U -#define RTC_CON_ALMAEN_MSK BIT(RTC_CON_ALMAEN_POS) - -#define RTC_CON_GO_POS 0U -#define RTC_CON_GO_MSK BIT(RTC_CON_GO_POS) - -/****************** Bit definition for RTC_PSR register ************************/ - -#define RTC_PSR_APRS_POSS 16U -#define RTC_PSR_APRS_POSE 22U -#define RTC_PSR_APRS_MSK BITS(RTC_PSR_APRS_POSS,RTC_PSR_APRS_POSE) - -#define RTC_PSR_SPRS_POSS 0U -#define RTC_PSR_SPRS_POSE 14U -#define RTC_PSR_SPRS_MSK BITS(RTC_PSR_SPRS_POSS,RTC_PSR_SPRS_POSE) - -/****************** Bit definition for RTC_TAMPCON register ************************/ - -#define RTC_TAMPCON_TAMPFLT_POSS 20U -#define RTC_TAMPCON_TAMPFLT_POSE 21U -#define RTC_TAMPCON_TAMPFLT_MSK BITS(RTC_TAMPCON_TAMPFLT_POSS,RTC_TAMPCON_TAMPFLT_POSE) - -#define RTC_TAMPCON_TAMPCKS_POSS 17U -#define RTC_TAMPCON_TAMPCKS_POSE 19U -#define RTC_TAMPCON_TAMPCKS_MSK BITS(RTC_TAMPCON_TAMPCKS_POSS,RTC_TAMPCON_TAMPCKS_POSE) - -#define RTC_TAMPCON_TAMPTS_POS 16U -#define RTC_TAMPCON_TAMPTS_MSK BIT(RTC_TAMPCON_TAMPTS_POS) - -#define RTC_TAMPCON_TAMP2LV_POS 9U -#define RTC_TAMPCON_TAMP2LV_MSK BIT(RTC_TAMPCON_TAMP2LV_POS) - -#define RTC_TAMPCON_TAMP2EN_POS 8U -#define RTC_TAMPCON_TAMP2EN_MSK BIT(RTC_TAMPCON_TAMP2EN_POS) - -#define RTC_TAMPCON_TAMP1LV_POS 1U -#define RTC_TAMPCON_TAMP1LV_MSK BIT(RTC_TAMPCON_TAMP1LV_POS) - -#define RTC_TAMPCON_TAMP1EN_POS 0U -#define RTC_TAMPCON_TAMP1EN_MSK BIT(RTC_TAMPCON_TAMP1EN_POS) - -/****************** Bit definition for RTC_TIME register ************************/ - -#define RTC_TIME_PM_POS 22U -#define RTC_TIME_PM_MSK BIT(RTC_TIME_PM_POS) - -#define RTC_TIME_HRT_POSS 20U -#define RTC_TIME_HRT_POSE 21U -#define RTC_TIME_HRT_MSK BITS(RTC_TIME_HRT_POSS,RTC_TIME_HRT_POSE) - -#define RTC_TIME_HRU_POSS 16U -#define RTC_TIME_HRU_POSE 19U -#define RTC_TIME_HRU_MSK BITS(RTC_TIME_HRU_POSS,RTC_TIME_HRU_POSE) - -#define RTC_TIME_MINT_POSS 12U -#define RTC_TIME_MINT_POSE 14U -#define RTC_TIME_MINT_MSK BITS(RTC_TIME_MINT_POSS,RTC_TIME_MINT_POSE) - -#define RTC_TIME_MINU_POSS 8U -#define RTC_TIME_MINU_POSE 11U -#define RTC_TIME_MINU_MSK BITS(RTC_TIME_MINU_POSS,RTC_TIME_MINU_POSE) - -#define RTC_TIME_SECT_POSS 4U -#define RTC_TIME_SECT_POSE 6U -#define RTC_TIME_SECT_MSK BITS(RTC_TIME_SECT_POSS,RTC_TIME_SECT_POSE) - -#define RTC_TIME_SECU_POSS 0U -#define RTC_TIME_SECU_POSE 3U -#define RTC_TIME_SECU_MSK BITS(RTC_TIME_SECU_POSS,RTC_TIME_SECU_POSE) - -/****************** Bit definition for RTC_DATE register ************************/ - -#define RTC_DATE_WD_POSS 24U -#define RTC_DATE_WD_POSE 26U -#define RTC_DATE_WD_MSK BITS(RTC_DATE_WD_POSS,RTC_DATE_WD_POSE) - -#define RTC_DATE_YRT_POSS 20U -#define RTC_DATE_YRT_POSE 23U -#define RTC_DATE_YRT_MSK BITS(RTC_DATE_YRT_POSS,RTC_DATE_YRT_POSE) - -#define RTC_DATE_YRU_POSS 16U -#define RTC_DATE_YRU_POSE 19U -#define RTC_DATE_YRU_MSK BITS(RTC_DATE_YRU_POSS,RTC_DATE_YRU_POSE) - -#define RTC_DATE_MONT_POS 12U -#define RTC_DATE_MONT_MSK BIT(RTC_DATE_MONT_POS) - -#define RTC_DATE_MONU_POSS 8U -#define RTC_DATE_MONU_POSE 11U -#define RTC_DATE_MONU_MSK BITS(RTC_DATE_MONU_POSS,RTC_DATE_MONU_POSE) - -#define RTC_DATE_DAYT_POSS 4U -#define RTC_DATE_DAYT_POSE 5U -#define RTC_DATE_DAYT_MSK BITS(RTC_DATE_DAYT_POSS,RTC_DATE_DAYT_POSE) - -#define RTC_DATE_DAYU_POSS 0U -#define RTC_DATE_DAYU_POSE 3U -#define RTC_DATE_DAYU_MSK BITS(RTC_DATE_DAYU_POSS,RTC_DATE_DAYU_POSE) - -/****************** Bit definition for RTC_SSEC register ************************/ - -#define RTC_SSEC_VAL_POSS 0U -#define RTC_SSEC_VAL_POSE 15U -#define RTC_SSEC_VAL_MSK BITS(RTC_SSEC_VAL_POSS,RTC_SSEC_VAL_POSE) - -/****************** Bit definition for RTC_WUMAT register ************************/ - -#define RTC_WUMAT_VAL_POSS 0U -#define RTC_WUMAT_VAL_POSE 15U -#define RTC_WUMAT_VAL_MSK BITS(RTC_WUMAT_VAL_POSS,RTC_WUMAT_VAL_POSE) - -/****************** Bit definition for RTC_ALMA register ************************/ - -#define RTC_ALMA_WDS_POS 31U -#define RTC_ALMA_WDS_MSK BIT(RTC_ALMA_WDS_POS) - -#define RTC_ALMA_DAWD_POSS 24U -#define RTC_ALMA_DAWD_POSE 30U -#define RTC_ALMA_DAWD_MSK BITS(RTC_ALMA_DAWD_POSS,RTC_ALMA_DAWD_POSE) - -#define RTC_ALMA_DAYMSK_POS 30U -#define RTC_ALMA_DAYMSK_MSK BIT(RTC_ALMA_DAYMSK_POS) - -#define RTC_ALMA_DAWD_DAYT_POSS 28U -#define RTC_ALMA_DAWD_DAYT_POSE 29U -#define RTC_ALMA_DAWD_DAYT_MSK BITS(RTC_ALMA_DAWD_DAYT_POSS, RTC_ALMA_DAWD_DAYT_POSE) - -#define RTC_ALMA_DAWD_DAYU_POSS 24U -#define RTC_ALMA_DAWD_DAYU_POSE 27U -#define RTC_ALMA_DAWD_DAYU_MSK BITS(RTC_ALMA_DAWD_DAYU_POSS, RTC_ALMA_DAWD_DAYU_POSE) - -#define RTC_ALMA_HRMSK_POS 23U -#define RTC_ALMA_HRMSK_MSK BIT(RTC_ALMA_HRMSK_POS) - -#define RTC_ALMA_PM_POS 22U -#define RTC_ALMA_PM_MSK BIT(RTC_ALMA_PM_POS) - -#define RTC_ALMA_HRT_POSS 20U -#define RTC_ALMA_HRT_POSE 21U -#define RTC_ALMA_HRT_MSK BITS(RTC_ALMA_HRT_POSS,RTC_ALMA_HRT_POSE) - -#define RTC_ALMA_HRU_POSS 16U -#define RTC_ALMA_HRU_POSE 19U -#define RTC_ALMA_HRU_MSK BITS(RTC_ALMA_HRU_POSS,RTC_ALMA_HRU_POSE) - -#define RTC_ALMA_MINMSK_POS 15U -#define RTC_ALMA_MINMSK_MSK BIT(RTC_ALMA_MINMSK_POS) - -#define RTC_ALMA_MINT_POSS 12U -#define RTC_ALMA_MINT_POSE 14U -#define RTC_ALMA_MINT_MSK BITS(RTC_ALMA_MINT_POSS,RTC_ALMA_MINT_POSE) - -#define RTC_ALMA_MINU_POSS 8U -#define RTC_ALMA_MINU_POSE 11U -#define RTC_ALMA_MINU_MSK BITS(RTC_ALMA_MINU_POSS,RTC_ALMA_MINU_POSE) - -#define RTC_ALMA_SECMSK_POS 7U -#define RTC_ALMA_SECMSK_MSK BIT(RTC_ALMA_SECMSK_POS) - -#define RTC_ALMA_SECT_POSS 4U -#define RTC_ALMA_SECT_POSE 6U -#define RTC_ALMA_SECT_MSK BITS(RTC_ALMA_SECT_POSS,RTC_ALMA_SECT_POSE) - -#define RTC_ALMA_SECU_POSS 0U -#define RTC_ALMA_SECU_POSE 3U -#define RTC_ALMA_SECU_MSK BITS(RTC_ALMA_SECU_POSS,RTC_ALMA_SECU_POSE) - -/****************** Bit definition for RTC_ALMB register ************************/ - -#define RTC_ALMB_WDS_POS 31U -#define RTC_ALMB_WDS_MSK BIT(RTC_ALMB_WDS_POS) - -#define RTC_ALMB_DAWD_POSS 24U -#define RTC_ALMB_DAWD_POSE 30U -#define RTC_ALMB_DAWD_MSK BITS(RTC_ALMB_DAWD_POSS,RTC_ALMB_DAWD_POSE) - -#define RTC_ALMB_DAYMSK_POS 30U -#define RTC_ALMB_DAYMSK_MSK BIT(RTC_ALMB_DAYMSK_POS) - -#define RTC_ALMB_DAWD_DAYT_POSS 28U -#define RTC_ALMB_DAWD_DAYT_POSE 29U -#define RTC_ALMB_DAWD_DAYT_MSK BITS(RTC_ALMB_DAWD_DAYT_POSS, RTC_ALMB_DAWD_DAYT_POSE) - -#define RTC_ALMB_DAWD_DAYU_POSS 24U -#define RTC_ALMB_DAWD_DAYU_POSE 27U -#define RTC_ALMB_DAWD_DAYU_MSK BITS(RTC_ALMB_DAWD_DAYU_POSS, RTC_ALMB_DAWD_DAYU_POSE) - -#define RTC_ALMB_HRMSK_POS 23U -#define RTC_ALMB_HRMSK_MSK BIT(RTC_ALMB_HRMSK_POS) - -#define RTC_ALMB_PM_POS 22U -#define RTC_ALMB_PM_MSK BIT(RTC_ALMB_PM_POS) - -#define RTC_ALMB_HRT_POSS 20U -#define RTC_ALMB_HRT_POSE 21U -#define RTC_ALMB_HRT_MSK BITS(RTC_ALMB_HRT_POSS,RTC_ALMB_HRT_POSE) - -#define RTC_ALMB_HRU_POSS 16U -#define RTC_ALMB_HRU_POSE 19U -#define RTC_ALMB_HRU_MSK BITS(RTC_ALMB_HRU_POSS,RTC_ALMB_HRU_POSE) - -#define RTC_ALMB_MINMSK_POS 15U -#define RTC_ALMB_MINMSK_MSK BIT(RTC_ALMB_MINMSK_POS) - -#define RTC_ALMB_MINT_POSS 12U -#define RTC_ALMB_MINT_POSE 14U -#define RTC_ALMB_MINT_MSK BITS(RTC_ALMB_MINT_POSS,RTC_ALMB_MINT_POSE) - -#define RTC_ALMB_MINU_POSS 8U -#define RTC_ALMB_MINU_POSE 11U -#define RTC_ALMB_MINU_MSK BITS(RTC_ALMB_MINU_POSS,RTC_ALMB_MINU_POSE) - -#define RTC_ALMB_SECMSK_POS 7U -#define RTC_ALMB_SECMSK_MSK BIT(RTC_ALMB_SECMSK_POS) - -#define RTC_ALMB_SECT_POSS 4U -#define RTC_ALMB_SECT_POSE 6U -#define RTC_ALMB_SECT_MSK BITS(RTC_ALMB_SECT_POSS,RTC_ALMB_SECT_POSE) - -#define RTC_ALMB_SECU_POSS 0U -#define RTC_ALMB_SECU_POSE 3U -#define RTC_ALMB_SECU_MSK BITS(RTC_ALMB_SECU_POSS,RTC_ALMB_SECU_POSE) - -/****************** Bit definition for RTC_ALMASSEC register ************************/ - -#define RTC_ALMASSEC_SSECM_POSS 24U -#define RTC_ALMASSEC_SSECM_POSE 27U -#define RTC_ALMASSEC_SSECM_MSK BITS(RTC_ALMASSEC_SSECM_POSS,RTC_ALMASSEC_SSECM_POSE) - -#define RTC_ALMASSEC_SSEC_POSS 0U -#define RTC_ALMASSEC_SSEC_POSE 14U -#define RTC_ALMASSEC_SSEC_MSK BITS(RTC_ALMASSEC_SSEC_POSS,RTC_ALMASSEC_SSEC_POSE) - -/****************** Bit definition for RTC_ALMBSSEC register ************************/ - -#define RTC_ALMBSSEC_SSECM_POSS 24U -#define RTC_ALMBSSEC_SSECM_POSE 27U -#define RTC_ALMBSSEC_SSECM_MSK BITS(RTC_ALMBSSEC_SSECM_POSS,RTC_ALMBSSEC_SSECM_POSE) - -#define RTC_ALMBSSEC_SSEC_POSS 0U -#define RTC_ALMBSSEC_SSEC_POSE 14U -#define RTC_ALMBSSEC_SSEC_MSK BITS(RTC_ALMBSSEC_SSEC_POSS,RTC_ALMBSSEC_SSEC_POSE) - -/****************** Bit definition for RTC_TSTIME register ************************/ - -#define RTC_TSTIME_PM_POS 22U -#define RTC_TSTIME_PM_MSK BIT(RTC_TSTIME_PM_POS) - -#define RTC_TSTIME_HRT_POSS 20U -#define RTC_TSTIME_HRT_POSE 21U -#define RTC_TSTIME_HRT_MSK BITS(RTC_TSTIME_HRT_POSS,RTC_TSTIME_HRT_POSE) - -#define RTC_TSTIME_HRU_POSS 16U -#define RTC_TSTIME_HRU_POSE 19U -#define RTC_TSTIME_HRU_MSK BITS(RTC_TSTIME_HRU_POSS,RTC_TSTIME_HRU_POSE) - -#define RTC_TSTIME_MINT_POSS 12U -#define RTC_TSTIME_MINT_POSE 14U -#define RTC_TSTIME_MINT_MSK BITS(RTC_TSTIME_MINT_POSS,RTC_TSTIME_MINT_POSE) - -#define RTC_TSTIME_MINU_POSS 8U -#define RTC_TSTIME_MINU_POSE 11U -#define RTC_TSTIME_MINU_MSK BITS(RTC_TSTIME_MINU_POSS,RTC_TSTIME_MINU_POSE) - -#define RTC_TSTIME_SECT_POSS 4U -#define RTC_TSTIME_SECT_POSE 6U -#define RTC_TSTIME_SECT_MSK BITS(RTC_TSTIME_SECT_POSS,RTC_TSTIME_SECT_POSE) - -#define RTC_TSTIME_SECU_POSS 0U -#define RTC_TSTIME_SECU_POSE 3U -#define RTC_TSTIME_SECU_MSK BITS(RTC_TSTIME_SECU_POSS,RTC_TSTIME_SECU_POSE) - -/****************** Bit definition for RTC_TSDATE register ************************/ - -#define RTC_TSDATE_WD_POSS 24U -#define RTC_TSDATE_WD_POSE 26U -#define RTC_TSDATE_WD_MSK BITS(RTC_TSDATE_WD_POSS,RTC_TSDATE_WD_POSE) - -#define RTC_TSDATE_YRT_POSS 20U -#define RTC_TSDATE_YRT_POSE 23U -#define RTC_TSDATE_YRT_MSK BITS(RTC_TSDATE_YRT_POSS,RTC_TSDATE_YRT_POSE) - -#define RTC_TSDATE_YRU_POSS 16U -#define RTC_TSDATE_YRU_POSE 19U -#define RTC_TSDATE_YRU_MSK BITS(RTC_TSDATE_YRU_POSS,RTC_TSDATE_YRU_POSE) - -#define RTC_TSDATE_MONT_POS 12U -#define RTC_TSDATE_MONT_MSK BIT(RTC_TSDATE_MONT_POS) - -#define RTC_TSDATE_MONU_POSS 8U -#define RTC_TSDATE_MONU_POSE 11U -#define RTC_TSDATE_MONU_MSK BITS(RTC_TSDATE_MONU_POSS,RTC_TSDATE_MONU_POSE) - -#define RTC_TSDATE_DAYT_POSS 4U -#define RTC_TSDATE_DAYT_POSE 5U -#define RTC_TSDATE_DAYT_MSK BITS(RTC_TSDATE_DAYT_POSS,RTC_TSDATE_DAYT_POSE) - -#define RTC_TSDATE_DAYU_POSS 0U -#define RTC_TSDATE_DAYU_POSE 3U -#define RTC_TSDATE_DAYU_MSK BITS(RTC_TSDATE_DAYU_POSS,RTC_TSDATE_DAYU_POSE) - -/****************** Bit definition for RTC_TSSSEC register ************************/ - -#define RTC_TSSSEC_SSEC_POSS 0U -#define RTC_TSSSEC_SSEC_POSE 15U -#define RTC_TSSSEC_SSEC_MSK BITS(RTC_TSSSEC_SSEC_POSS,RTC_TSSSEC_SSEC_POSE) - -/****************** Bit definition for RTC_SSECTR register ************************/ - -#define RTC_SSECTR_INC_POS 31U -#define RTC_SSECTR_INC_MSK BIT(RTC_SSECTR_INC_POS) - -#define RTC_SSECTR_TRIM_POSS 0U -#define RTC_SSECTR_TRIM_POSE 14U -#define RTC_SSECTR_TRIM_MSK BITS(RTC_SSECTR_TRIM_POSS,RTC_SSECTR_TRIM_POSE) - -/****************** Bit definition for RTC_IER register ************************/ - -#define RTC_IER_TCE_POS 25U -#define RTC_IER_TCE_MSK BIT(RTC_IER_TCE_POS) - -#define RTC_IER_TCC_POS 24U -#define RTC_IER_TCC_MSK BIT(RTC_IER_TCC_POS) - -#define RTC_IER_WU_POS 18U -#define RTC_IER_WU_MSK BIT(RTC_IER_WU_POS) - -#define RTC_IER_SSTC_POS 17U -#define RTC_IER_SSTC_MSK BIT(RTC_IER_SSTC_POS) - -#define RTC_IER_RSC_POS 16U -#define RTC_IER_RSC_MSK BIT(RTC_IER_RSC_POS) - -#define RTC_IER_TAMP2_POS 13U -#define RTC_IER_TAMP2_MSK BIT(RTC_IER_TAMP2_POS) - -#define RTC_IER_TAMP1_POS 12U -#define RTC_IER_TAMP1_MSK BIT(RTC_IER_TAMP1_POS) - -#define RTC_IER_TSOV_POS 11U -#define RTC_IER_TSOV_MSK BIT(RTC_IER_TSOV_POS) - -#define RTC_IER_TS_POS 10U -#define RTC_IER_TS_MSK BIT(RTC_IER_TS_POS) - -#define RTC_IER_ALMB_POS 9U -#define RTC_IER_ALMB_MSK BIT(RTC_IER_ALMB_POS) - -#define RTC_IER_ALMA_POS 8U -#define RTC_IER_ALMA_MSK BIT(RTC_IER_ALMA_POS) - -#define RTC_IER_YR_POS 5U -#define RTC_IER_YR_MSK BIT(RTC_IER_YR_POS) - -#define RTC_IER_MON_POS 4U -#define RTC_IER_MON_MSK BIT(RTC_IER_MON_POS) - -#define RTC_IER_DAY_POS 3U -#define RTC_IER_DAY_MSK BIT(RTC_IER_DAY_POS) - -#define RTC_IER_HR_POS 2U -#define RTC_IER_HR_MSK BIT(RTC_IER_HR_POS) - -#define RTC_IER_MIN_POS 1U -#define RTC_IER_MIN_MSK BIT(RTC_IER_MIN_POS) - -#define RTC_IER_SEC_POS 0U -#define RTC_IER_SEC_MSK BIT(RTC_IER_SEC_POS) - -/****************** Bit definition for RTC_IFR register ************************/ - -#define RTC_IFR_TCEF_POS 25U -#define RTC_IFR_TCEF_MSK BIT(RTC_IFR_TCEF_POS) - -#define RTC_IFR_TCCF_POS 24U -#define RTC_IFR_TCCF_MSK BIT(RTC_IFR_TCCF_POS) - -#define RTC_IFR_WUF_POS 18U -#define RTC_IFR_WUF_MSK BIT(RTC_IFR_WUF_POS) - -#define RTC_IFR_SSTCF_POS 17U -#define RTC_IFR_SSTCF_MSK BIT(RTC_IFR_SSTCF_POS) - -#define RTC_IFR_RSCF_POS 16U -#define RTC_IFR_RSCF_MSK BIT(RTC_IFR_RSCF_POS) - -#define RTC_IFR_TAMP2F_POS 13U -#define RTC_IFR_TAMP2F_MSK BIT(RTC_IFR_TAMP2F_POS) - -#define RTC_IFR_TAMP1F_POS 12U -#define RTC_IFR_TAMP1F_MSK BIT(RTC_IFR_TAMP1F_POS) - -#define RTC_IFR_TSOVF_POS 11U -#define RTC_IFR_TSOVF_MSK BIT(RTC_IFR_TSOVF_POS) - -#define RTC_IFR_TSF_POS 10U -#define RTC_IFR_TSF_MSK BIT(RTC_IFR_TSF_POS) - -#define RTC_IFR_ALMBF_POS 9U -#define RTC_IFR_ALMBF_MSK BIT(RTC_IFR_ALMBF_POS) - -#define RTC_IFR_ALMAF_POS 8U -#define RTC_IFR_ALMAF_MSK BIT(RTC_IFR_ALMAF_POS) - -#define RTC_IFR_YRF_POS 5U -#define RTC_IFR_YRF_MSK BIT(RTC_IFR_YRF_POS) - -#define RTC_IFR_MONF_POS 4U -#define RTC_IFR_MONF_MSK BIT(RTC_IFR_MONF_POS) - -#define RTC_IFR_DAYF_POS 3U -#define RTC_IFR_DAYF_MSK BIT(RTC_IFR_DAYF_POS) - -#define RTC_IFR_HRF_POS 2U -#define RTC_IFR_HRF_MSK BIT(RTC_IFR_HRF_POS) - -#define RTC_IFR_MINF_POS 1U -#define RTC_IFR_MINF_MSK BIT(RTC_IFR_MINF_POS) - -#define RTC_IFR_SECF_POS 0U -#define RTC_IFR_SECF_MSK BIT(RTC_IFR_SECF_POS) - -/****************** Bit definition for RTC_IFCR register ************************/ - -#define RTC_IFCR_TCEFC_POS 25U -#define RTC_IFCR_TCEFC_MSK BIT(RTC_IFCR_TCEFC_POS) - -#define RTC_IFCR_TCCFC_POS 24U -#define RTC_IFCR_TCCFC_MSK BIT(RTC_IFCR_TCCFC_POS) - -#define RTC_IFCR_WUFC_POS 18U -#define RTC_IFCR_WUFC_MSK BIT(RTC_IFCR_WUFC_POS) - -#define RTC_IFCR_SSTCFC_POS 17U -#define RTC_IFCR_SSTCFC_MSK BIT(RTC_IFCR_SSTCFC_POS) - -#define RTC_IFCR_RSCFC_POS 16U -#define RTC_IFCR_RSCFC_MSK BIT(RTC_IFCR_RSCFC_POS) - -#define RTC_IFCR_TAMP2FC_POS 13U -#define RTC_IFCR_TAMP2FC_MSK BIT(RTC_IFCR_TAMP2FC_POS) - -#define RTC_IFCR_TAMP1FC_POS 12U -#define RTC_IFCR_TAMP1FC_MSK BIT(RTC_IFCR_TAMP1FC_POS) - -#define RTC_IFCR_TSOVFC_POS 11U -#define RTC_IFCR_TSOVFC_MSK BIT(RTC_IFCR_TSOVFC_POS) - -#define RTC_IFCR_TSSTC_POS 10U -#define RTC_IFCR_TSSTC_MSK BIT(RTC_IFCR_TSSTC_POS) - -#define RTC_IFCR_ALMBFC_POS 9U -#define RTC_IFCR_ALMBFC_MSK BIT(RTC_IFCR_ALMBFC_POS) - -#define RTC_IFCR_ALMAFC_POS 8U -#define RTC_IFCR_ALMAFC_MSK BIT(RTC_IFCR_ALMAFC_POS) - -#define RTC_IFCR_YRFC_POS 5U -#define RTC_IFCR_YRFC_MSK BIT(RTC_IFCR_YRFC_POS) - -#define RTC_IFCR_MONFC_POS 4U -#define RTC_IFCR_MONFC_MSK BIT(RTC_IFCR_MONFC_POS) - -#define RTC_IFCR_DAYFC_POS 3U -#define RTC_IFCR_DAYFC_MSK BIT(RTC_IFCR_DAYFC_POS) - -#define RTC_IFCR_HRFC_POS 2U -#define RTC_IFCR_HRFC_MSK BIT(RTC_IFCR_HRFC_POS) - -#define RTC_IFCR_MINFC_POS 1U -#define RTC_IFCR_MINFC_MSK BIT(RTC_IFCR_MINFC_POS) - -#define RTC_IFCR_SECFC_POS 0U -#define RTC_IFCR_SECFC_MSK BIT(RTC_IFCR_SECFC_POS) - -/****************** Bit definition for RTC_ISR register ************************/ - -#define RTC_ISR_TCEF_POS 25U -#define RTC_ISR_TCEF_MSK BIT(RTC_ISR_TCEF_POS) - -#define RTC_ISR_TCCF_POS 24U -#define RTC_ISR_TCCF_MSK BIT(RTC_ISR_TCCF_POS) - -#define RTC_ISR_WUF_POS 18U -#define RTC_ISR_WUF_MSK BIT(RTC_ISR_WUF_POS) - -#define RTC_ISR_SSTCF_POS 17U -#define RTC_ISR_SSTCF_MSK BIT(RTC_ISR_SSTCF_POS) - -#define RTC_ISR_RSCF_POS 16U -#define RTC_ISR_RSCF_MSK BIT(RTC_ISR_RSCF_POS) - -#define RTC_ISR_TAMP2F_POS 13U -#define RTC_ISR_TAMP2F_MSK BIT(RTC_ISR_TAMP2F_POS) - -#define RTC_ISR_TAMP1F_POS 12U -#define RTC_ISR_TAMP1F_MSK BIT(RTC_ISR_TAMP1F_POS) - -#define RTC_ISR_TSOVF_POS 11U -#define RTC_ISR_TSOVF_MSK BIT(RTC_ISR_TSOVF_POS) - -#define RTC_ISR_TSF_POS 10U -#define RTC_ISR_TSF_MSK BIT(RTC_ISR_TSF_POS) - -#define RTC_ISR_ALMBF_POS 9U -#define RTC_ISR_ALMBF_MSK BIT(RTC_ISR_ALMBF_POS) - -#define RTC_ISR_ALMAF_POS 8U -#define RTC_ISR_ALMAF_MSK BIT(RTC_ISR_ALMAF_POS) - -#define RTC_ISR_YRF_POS 5U -#define RTC_ISR_YRF_MSK BIT(RTC_ISR_YRF_POS) - -#define RTC_ISR_MONF_POS 4U -#define RTC_ISR_MONF_MSK BIT(RTC_ISR_MONF_POS) - -#define RTC_ISR_DAYF_POS 3U -#define RTC_ISR_DAYF_MSK BIT(RTC_ISR_DAYF_POS) - -#define RTC_ISR_HRF_POS 2U -#define RTC_ISR_HRF_MSK BIT(RTC_ISR_HRF_POS) - -#define RTC_ISR_MINF_POS 1U -#define RTC_ISR_MINF_MSK BIT(RTC_ISR_MINF_POS) - -#define RTC_ISR_SECF_POS 0U -#define RTC_ISR_SECF_MSK BIT(RTC_ISR_SECF_POS) - -/****************** Bit definition for RTC_CALWPR register ************************/ - -#define RTC_CALWPR_WP_POS 0U -#define RTC_CALWPR_WP_MSK BIT(RTC_CALWPR_WP_POS) - -/****************** Bit definition for RTC_CALCON register ************************/ - -#define RTC_CALCON_DCMACC_POS 24U -#define RTC_CALCON_DCMACC_MSK BIT(RTC_CALCON_DCMACC_POS) - -#define RTC_CALCON_ALG_POS 23U -#define RTC_CALCON_ALG_MSK BIT(RTC_CALCON_ALG_POS) - -#define RTC_CALCON_TCP_POSS 20U -#define RTC_CALCON_TCP_POSE 22U -#define RTC_CALCON_TCP_MSK BITS(RTC_CALCON_TCP_POSS,RTC_CALCON_TCP_POSE) - -#define RTC_CALCON_ERR_POS 19U -#define RTC_CALCON_ERR_MSK BIT(RTC_CALCON_ERR_POS) - -#define RTC_CALCON_BUSY_POS 18U -#define RTC_CALCON_BUSY_MSK BIT(RTC_CALCON_BUSY_POS) - -#define RTC_CALCON_TCM_POSS 16U -#define RTC_CALCON_TCM_POSE 17U -#define RTC_CALCON_TCM_MSK BITS(RTC_CALCON_TCM_POSS,RTC_CALCON_TCM_POSE) - -#define RTC_CALCON_CALP_POSS 1U -#define RTC_CALCON_CALP_POSE 3U -#define RTC_CALCON_CALP_MSK BITS(RTC_CALCON_CALP_POSS,RTC_CALCON_CALP_POSE) - -#define RTC_CALCON_CALEN_POS 0U -#define RTC_CALCON_CALEN_MSK BIT(RTC_CALCON_CALEN_POS) - -/****************** Bit definition for RTC_CALDR register ************************/ - -#define RTC_CALDR_DATA_POSS 16U -#define RTC_CALDR_DATA_POSE 31U -#define RTC_CALDR_DATA_MSK BITS(RTC_CALDR_DATA_POSS,RTC_CALDR_DATA_POSE) - -#define RTC_CALDR_VAL_POSS 0U -#define RTC_CALDR_VAL_POSE 15U -#define RTC_CALDR_VAL_MSK BITS(RTC_CALDR_VAL_POSS,RTC_CALDR_VAL_POSE) - -/****************** Bit definition for RTC_TEMPR register ************************/ - -#define RTC_TEMPR_DATA_POSS 16U -#define RTC_TEMPR_DATA_POSE 31U -#define RTC_TEMPR_DATA_MSK BITS(RTC_TEMPR_DATA_POSS,RTC_TEMPR_DATA_POSE) - -#define RTC_TEMPR_VAL_POSS 0U -#define RTC_TEMPR_VAL_POSE 15U -#define RTC_TEMPR_VAL_MSK BITS(RTC_TEMPR_VAL_POSS,RTC_TEMPR_VAL_POSE) - -/****************** Bit definition for RTC_TEMPBDR register ************************/ - -#define RTC_TEMPBDR_VAL_POSS 0U -#define RTC_TEMPBDR_VAL_POSE 15U -#define RTC_TEMPBDR_VAL_MSK BITS(RTC_TEMPBDR_VAL_POSS,RTC_TEMPBDR_VAL_POSE) - -/****************** Bit definition for RTC_BKP register ************************/ - -#define RTC_BKP_BKP_POSS 0U -#define RTC_BKP_BKP_POSE 31U -#define RTC_BKP_BKP_MSK BITS(RTC_BKP_BKP_POSS,RTC_BKP_BKP_POSE) - -typedef struct -{ - __IO uint32_t WPR; - __IO uint32_t CON; - __IO uint32_t PSR; - __IO uint32_t TAMPCON; - __IO uint32_t TIME; - __IO uint32_t DATE; - __IO uint32_t SSEC; - __IO uint32_t WUMAT; - __IO uint32_t ALMA; - __IO uint32_t ALMB; - __IO uint32_t ALMASSEC; - __IO uint32_t ALMBSSEC; - __I uint32_t TSTIME; - __I uint32_t TSDATE; - __I uint32_t TSSSEC; - __O uint32_t SSECTR; - __IO uint32_t IER; - __I uint32_t IFR; - __O uint32_t IFCR; - __I uint32_t ISR; - __IO uint32_t CALWPR; - __IO uint32_t CALCON; - __IO uint32_t CALDR; - __IO uint32_t TEMPR; - __IO uint32_t LTCAR; - __IO uint32_t LTCBR; - __IO uint32_t LTCCR; - __IO uint32_t LTCDR; - __IO uint32_t LTCER; - __IO uint32_t HTCAR; - __IO uint32_t HTCBR; - __IO uint32_t HTCCR; - __IO uint32_t HTCDR; - __IO uint32_t HTCER; - __IO uint32_t TEMPBDR; - uint32_t RESERVED0[29] ; - __IO uint32_t BKPR[32]; -} RTC_TypeDef; - -/****************** Bit definition for TIMER_CON1 register ************************/ - -#define TIMER_CON1_DFCKSEL_POSS 8U -#define TIMER_CON1_DFCKSEL_POSE 9U -#define TIMER_CON1_DFCKSEL_MSK BITS(TIMER_CON1_DFCKSEL_POSS,TIMER_CON1_DFCKSEL_POSE) - -#define TIMER_CON1_ARPEN_POS 7U -#define TIMER_CON1_ARPEN_MSK BIT(TIMER_CON1_ARPEN_POS) - -#define TIMER_CON1_CMSEL_POSS 5U -#define TIMER_CON1_CMSEL_POSE 6U -#define TIMER_CON1_CMSEL_MSK BITS(TIMER_CON1_CMSEL_POSS,TIMER_CON1_CMSEL_POSE) - -#define TIMER_CON1_DIRSEL_POS 4U -#define TIMER_CON1_DIRSEL_MSK BIT(TIMER_CON1_DIRSEL_POS) - -#define TIMER_CON1_SPMEN_POS 3U -#define TIMER_CON1_SPMEN_MSK BIT(TIMER_CON1_SPMEN_POS) - -#define TIMER_CON1_UERSEL_POS 2U -#define TIMER_CON1_UERSEL_MSK BIT(TIMER_CON1_UERSEL_POS) - -#define TIMER_CON1_DISUE_POS 1U -#define TIMER_CON1_DISUE_MSK BIT(TIMER_CON1_DISUE_POS) - -#define TIMER_CON1_CNTEN_POS 0U -#define TIMER_CON1_CNTEN_MSK BIT(TIMER_CON1_CNTEN_POS) - -/****************** Bit definition for TIMER_CON2 register ************************/ - -#define TIMER_CON2_OISS4_POS 14U -#define TIMER_CON2_OISS4_MSK BIT(TIMER_CON2_OISS4_POS) - -#define TIMER_CON2_OISS3N_POS 13U -#define TIMER_CON2_OISS3N_MSK BIT(TIMER_CON2_OISS3N_POS) - -#define TIMER_CON2_OISS3_POS 12U -#define TIMER_CON2_OISS3_MSK BIT(TIMER_CON2_OISS3_POS) - -#define TIMER_CON2_OISS2N_POS 11U -#define TIMER_CON2_OISS2N_MSK BIT(TIMER_CON2_OISS2N_POS) - -#define TIMER_CON2_OISS2_POS 10U -#define TIMER_CON2_OISS2_MSK BIT(TIMER_CON2_OISS2_POS) - -#define TIMER_CON2_OISS1N_POS 9U -#define TIMER_CON2_OISS1N_MSK BIT(TIMER_CON2_OISS1N_POS) - -#define TIMER_CON2_OISS1_POS 8U -#define TIMER_CON2_OISS1_MSK BIT(TIMER_CON2_OISS1_POS) - -#define TIMER_CON2_I1FSEL_POS 7U -#define TIMER_CON2_I1FSEL_MSK BIT(TIMER_CON2_I1FSEL_POS) - -#define TIMER_CON2_TRGOSEL_POSS 4U -#define TIMER_CON2_TRGOSEL_POSE 6U -#define TIMER_CON2_TRGOSEL_MSK BITS(TIMER_CON2_TRGOSEL_POSS,TIMER_CON2_TRGOSEL_POSE) - -#define TIMER_CON2_CCDMASEL_POS 3U -#define TIMER_CON2_CCDMASEL_MSK BIT(TIMER_CON2_CCDMASEL_POS) - -#define TIMER_CON2_CCUSEL_POS 2U -#define TIMER_CON2_CCUSEL_MSK BIT(TIMER_CON2_CCUSEL_POS) - -#define TIMER_CON2_CCPCEN_POS 0U -#define TIMER_CON2_CCPCEN_MSK BIT(TIMER_CON2_CCPCEN_POS) - -/****************** Bit definition for TIMER_SMCON register ************************/ - -#define TIMER_SMCON_ETPOL_POS 15U -#define TIMER_SMCON_ETPOL_MSK BIT(TIMER_SMCON_ETPOL_POS) - -#define TIMER_SMCON_ECM2EN_POS 14U -#define TIMER_SMCON_ECM2EN_MSK BIT(TIMER_SMCON_ECM2EN_POS) - -#define TIMER_SMCON_ETPSEL_POSS 12U -#define TIMER_SMCON_ETPSEL_POSE 13U -#define TIMER_SMCON_ETPSEL_MSK BITS(TIMER_SMCON_ETPSEL_POSS,TIMER_SMCON_ETPSEL_POSE) - -#define TIMER_SMCON_ETFLT_POSS 8U -#define TIMER_SMCON_ETFLT_POSE 11U -#define TIMER_SMCON_ETFLT_MSK BITS(TIMER_SMCON_ETFLT_POSS,TIMER_SMCON_ETFLT_POSE) - -#define TIMER_SMCON_MSCFG_POS 7U -#define TIMER_SMCON_MSCFG_MSK BIT(TIMER_SMCON_MSCFG_POS) - -#define TIMER_SMCON_TSSEL_POSS 4U -#define TIMER_SMCON_TSSEL_POSE 6U -#define TIMER_SMCON_TSSEL_MSK BITS(TIMER_SMCON_TSSEL_POSS,TIMER_SMCON_TSSEL_POSE) - -#define TIMER_SMCON_SMODS_POSS 0U -#define TIMER_SMCON_SMODS_POSE 2U -#define TIMER_SMCON_SMODS_MSK BITS(TIMER_SMCON_SMODS_POSS,TIMER_SMCON_SMODS_POSE) - -/****************** Bit definition for TIMER_DIER register ************************/ - -#define TIMER_DIER_TRGDMA_POS 14U -#define TIMER_DIER_TRGDMA_MSK BIT(TIMER_DIER_TRGDMA_POS) - -#define TIMER_DIER_COMDMA_POS 13U -#define TIMER_DIER_COMDMA_MSK BIT(TIMER_DIER_COMDMA_POS) - -#define TIMER_DIER_CC4DMA_POS 12U -#define TIMER_DIER_CC4DMA_MSK BIT(TIMER_DIER_CC4DMA_POS) - -#define TIMER_DIER_CC3DMA_POS 11U -#define TIMER_DIER_CC3DMA_MSK BIT(TIMER_DIER_CC3DMA_POS) - -#define TIMER_DIER_CC2DMA_POS 10U -#define TIMER_DIER_CC2DMA_MSK BIT(TIMER_DIER_CC2DMA_POS) - -#define TIMER_DIER_CC1DMA_POS 9U -#define TIMER_DIER_CC1DMA_MSK BIT(TIMER_DIER_CC1DMA_POS) - -#define TIMER_DIER_UDMA_POS 8U -#define TIMER_DIER_UDMA_MSK BIT(TIMER_DIER_UDMA_POS) - -#define TIMER_DIER_BRKIT_POS 7U -#define TIMER_DIER_BRKIT_MSK BIT(TIMER_DIER_BRKIT_POS) - -#define TIMER_DIER_TRGIT_POS 6U -#define TIMER_DIER_TRGIT_MSK BIT(TIMER_DIER_TRGIT_POS) - -#define TIMER_DIER_COMIT_POS 5U -#define TIMER_DIER_COMIT_MSK BIT(TIMER_DIER_COMIT_POS) - -#define TIMER_DIER_CC4IT_POS 4U -#define TIMER_DIER_CC4IT_MSK BIT(TIMER_DIER_CC4IT_POS) - -#define TIMER_DIER_CC3IT_POS 3U -#define TIMER_DIER_CC3IT_MSK BIT(TIMER_DIER_CC3IT_POS) - -#define TIMER_DIER_CC2IT_POS 2U -#define TIMER_DIER_CC2IT_MSK BIT(TIMER_DIER_CC2IT_POS) - -#define TIMER_DIER_CC1IT_POS 1U -#define TIMER_DIER_CC1IT_MSK BIT(TIMER_DIER_CC1IT_POS) - -#define TIMER_DIER_UIT_POS 0U -#define TIMER_DIER_UIT_MSK BIT(TIMER_DIER_UIT_POS) - -/****************** Bit definition for TIMER_DIDR register ************************/ - -#define TIMER_DIDR_TRGDMA_POS 14U -#define TIMER_DIDR_TRGDMA_MSK BIT(TIMER_DIDR_TRGDMA_POS) - -#define TIMER_DIDR_COMD_POS 13U -#define TIMER_DIDR_COMD_MSK BIT(TIMER_DIDR_COMD_POS) - -#define TIMER_DIDR_CC4D_POS 12U -#define TIMER_DIDR_CC4D_MSK BIT(TIMER_DIDR_CC4D_POS) - -#define TIMER_DIDR_CC3D_POS 11U -#define TIMER_DIDR_CC3D_MSK BIT(TIMER_DIDR_CC3D_POS) - -#define TIMER_DIDR_CC2D_POS 10U -#define TIMER_DIDR_CC2D_MSK BIT(TIMER_DIDR_CC2D_POS) - -#define TIMER_DIDR_CC1D_POS 9U -#define TIMER_DIDR_CC1D_MSK BIT(TIMER_DIDR_CC1D_POS) - -#define TIMER_DIDR_UD_POS 8U -#define TIMER_DIDR_UD_MSK BIT(TIMER_DIDR_UD_POS) - -#define TIMER_DIDR_BRKI_POS 7U -#define TIMER_DIDR_BRKI_MSK BIT(TIMER_DIDR_BRKI_POS) - -#define TIMER_DIDR_TRGI_POS 6U -#define TIMER_DIDR_TRGI_MSK BIT(TIMER_DIDR_TRGI_POS) - -#define TIMER_DIDR_COMI_POS 5U -#define TIMER_DIDR_COMI_MSK BIT(TIMER_DIDR_COMI_POS) - -#define TIMER_DIDR_CC4I_POS 4U -#define TIMER_DIDR_CC4I_MSK BIT(TIMER_DIDR_CC4I_POS) - -#define TIMER_DIDR_CC3I_POS 3U -#define TIMER_DIDR_CC3I_MSK BIT(TIMER_DIDR_CC3I_POS) - -#define TIMER_DIDR_CC2I_POS 2U -#define TIMER_DIDR_CC2I_MSK BIT(TIMER_DIDR_CC2I_POS) - -#define TIMER_DIDR_CC1I_POS 1U -#define TIMER_DIDR_CC1I_MSK BIT(TIMER_DIDR_CC1I_POS) - -#define TIMER_DIDR_UI_POS 0U -#define TIMER_DIDR_UI_MSK BIT(TIMER_DIDR_UI_POS) - -/****************** Bit definition for TIMER_DIVS register ************************/ - -#define TIMER_DIVS_TRGDMA_POS 14U -#define TIMER_DIVS_TRGDMA_MSK BIT(TIMER_DIVS_TRGDMA_POS) - -#define TIMER_DIVS_COMDMA_POS 13U -#define TIMER_DIVS_COMDMA_MSK BIT(TIMER_DIVS_COMDMA_POS) - -#define TIMER_DIVS_CC4DMA_POS 12U -#define TIMER_DIVS_CC4DMA_MSK BIT(TIMER_DIVS_CC4DMA_POS) - -#define TIMER_DIVS_CC3DMA_POS 11U -#define TIMER_DIVS_CC3DMA_MSK BIT(TIMER_DIVS_CC3DMA_POS) - -#define TIMER_DIVS_CC2DMA_POS 10U -#define TIMER_DIVS_CC2DMA_MSK BIT(TIMER_DIVS_CC2DMA_POS) - -#define TIMER_DIVS_CC1DMA_POS 9U -#define TIMER_DIVS_CC1DMA_MSK BIT(TIMER_DIVS_CC1DMA_POS) - -#define TIMER_DIVS_UEDTR_POS 8U -#define TIMER_DIVS_UEDTR_MSK BIT(TIMER_DIVS_UEDTR_POS) - -#define TIMER_DIVS_BKI_POS 7U -#define TIMER_DIVS_BKI_MSK BIT(TIMER_DIVS_BKI_POS) - -#define TIMER_DIVS_TRGI_POS 6U -#define TIMER_DIVS_TRGI_MSK BIT(TIMER_DIVS_TRGI_POS) - -#define TIMER_DIVS_COMI_POS 5U -#define TIMER_DIVS_COMI_MSK BIT(TIMER_DIVS_COMI_POS) - -#define TIMER_DIVS_CC4I_POS 4U -#define TIMER_DIVS_CC4I_MSK BIT(TIMER_DIVS_CC4I_POS) - -#define TIMER_DIVS_CC3I_POS 3U -#define TIMER_DIVS_CC3I_MSK BIT(TIMER_DIVS_CC3I_POS) - -#define TIMER_DIVS_CC2I_POS 2U -#define TIMER_DIVS_CC2I_MSK BIT(TIMER_DIVS_CC2I_POS) - -#define TIMER_DIVS_CC1I_POS 1U -#define TIMER_DIVS_CC1I_MSK BIT(TIMER_DIVS_CC1I_POS) - -#define TIMER_DIVS_UEI_POS 0U -#define TIMER_DIVS_UEI_MSK BIT(TIMER_DIVS_UEI_POS) - -/****************** Bit definition for TIMER_RIF register ************************/ - -#define TIMER_RIF_CH4OVIF_POS 12U -#define TIMER_RIF_CH4OVIF_MSK BIT(TIMER_RIF_CH4OVIF_POS) - -#define TIMER_RIF_CH3OVIF_POS 11U -#define TIMER_RIF_CH3OVIF_MSK BIT(TIMER_RIF_CH3OVIF_POS) - -#define TIMER_RIF_CH2OVIF_POS 10U -#define TIMER_RIF_CH2OVIF_MSK BIT(TIMER_RIF_CH2OVIF_POS) - -#define TIMER_RIF_CH1OVIF_POS 9U -#define TIMER_RIF_CH1OVIF_MSK BIT(TIMER_RIF_CH1OVIF_POS) - -#define TIMER_RIF_BRKIF_POS 7U -#define TIMER_RIF_BRKIF_MSK BIT(TIMER_RIF_BRKIF_POS) - -#define TIMER_RIF_TRGIF_POS 6U -#define TIMER_RIF_TRGIF_MSK BIT(TIMER_RIF_TRGIF_POS) - -#define TIMER_RIF_COMIF_POS 5U -#define TIMER_RIF_COMIF_MSK BIT(TIMER_RIF_COMIF_POS) - -#define TIMER_RIF_CH4IF_POS 4U -#define TIMER_RIF_CH4IF_MSK BIT(TIMER_RIF_CH4IF_POS) - -#define TIMER_RIF_CH3IF_POS 3U -#define TIMER_RIF_CH3IF_MSK BIT(TIMER_RIF_CH3IF_POS) - -#define TIMER_RIF_CH2IF_POS 2U -#define TIMER_RIF_CH2IF_MSK BIT(TIMER_RIF_CH2IF_POS) - -#define TIMER_RIF_CH1IF_POS 1U -#define TIMER_RIF_CH1IF_MSK BIT(TIMER_RIF_CH1IF_POS) - -#define TIMER_RIF_UEVTIF_POS 0U -#define TIMER_RIF_UEVTIF_MSK BIT(TIMER_RIF_UEVTIF_POS) - -/****************** Bit definition for TIMER_IFM register ************************/ - -#define TIMER_IFM_BRKIM_POS 7U -#define TIMER_IFM_BRKIM_MSK BIT(TIMER_IFM_BRKIM_POS) - -#define TIMER_IFM_TRGI_POS 6U -#define TIMER_IFM_TRGI_MSK BIT(TIMER_IFM_TRGI_POS) - -#define TIMER_IFM_COMI_POS 5U -#define TIMER_IFM_COMI_MSK BIT(TIMER_IFM_COMI_POS) - -#define TIMER_IFM_CH4CCI_POS 4U -#define TIMER_IFM_CH4CCI_MSK BIT(TIMER_IFM_CH4CCI_POS) - -#define TIMER_IFM_CH3CCI_POS 3U -#define TIMER_IFM_CH3CCI_MSK BIT(TIMER_IFM_CH3CCI_POS) - -#define TIMER_IFM_CH2CCI_POS 2U -#define TIMER_IFM_CH2CCI_MSK BIT(TIMER_IFM_CH2CCI_POS) - -#define TIMER_IFM_CH1CCI_POS 1U -#define TIMER_IFM_CH1CCI_MSK BIT(TIMER_IFM_CH1CCI_POS) - -#define TIMER_IFM_UEI_POS 0U -#define TIMER_IFM_UEI_MSK BIT(TIMER_IFM_UEI_POS) - -/****************** Bit definition for TIMER_ICR register ************************/ - -#define TIMER_ICR_BRKIC_POS 7U -#define TIMER_ICR_BRKIC_MSK BIT(TIMER_ICR_BRKIC_POS) - -#define TIMER_ICR_TRGIC_POS 6U -#define TIMER_ICR_TRGIC_MSK BIT(TIMER_ICR_TRGIC_POS) - -#define TIMER_ICR_COMIC_POS 5U -#define TIMER_ICR_COMIC_MSK BIT(TIMER_ICR_COMIC_POS) - -#define TIMER_ICR_CH4CCIC_POS 4U -#define TIMER_ICR_CH4CCIC_MSK BIT(TIMER_ICR_CH4CCIC_POS) - -#define TIMER_ICR_CH3CCIC_POS 3U -#define TIMER_ICR_CH3CCIC_MSK BIT(TIMER_ICR_CH3CCIC_POS) - -#define TIMER_ICR_CH2CCIC_POS 2U -#define TIMER_ICR_CH2CCIC_MSK BIT(TIMER_ICR_CH2CCIC_POS) - -#define TIMER_ICR_CH1CCIC_POS 1U -#define TIMER_ICR_CH1CCIC_MSK BIT(TIMER_ICR_CH1CCIC_POS) - -#define TIMER_ICR_UEIC_POS 0U -#define TIMER_ICR_UEIC_MSK BIT(TIMER_ICR_UEIC_POS) - -/****************** Bit definition for TIMER_SGE register ************************/ - -#define TIMER_SGE_SGBRK_POS 7U -#define TIMER_SGE_SGBRK_MSK BIT(TIMER_SGE_SGBRK_POS) - -#define TIMER_SGE_SGTRG_POS 6U -#define TIMER_SGE_SGTRG_MSK BIT(TIMER_SGE_SGTRG_POS) - -#define TIMER_SGE_SGCOM_POS 5U -#define TIMER_SGE_SGCOM_MSK BIT(TIMER_SGE_SGCOM_POS) - -#define TIMER_SGE_SGCC4E_POS 4U -#define TIMER_SGE_SGCC4E_MSK BIT(TIMER_SGE_SGCC4E_POS) - -#define TIMER_SGE_SGCC3E_POS 3U -#define TIMER_SGE_SGCC3E_MSK BIT(TIMER_SGE_SGCC3E_POS) - -#define TIMER_SGE_SGCC2E_POS 2U -#define TIMER_SGE_SGCC2E_MSK BIT(TIMER_SGE_SGCC2E_POS) - -#define TIMER_SGE_SGCC1E_POS 1U -#define TIMER_SGE_SGCC1E_MSK BIT(TIMER_SGE_SGCC1E_POS) - -#define TIMER_SGE_SGU_POS 0U -#define TIMER_SGE_SGU_MSK BIT(TIMER_SGE_SGU_POS) - -/****************** Bit definition for TIMER_CHMR1 register ************************/ -/* Output */ -#define TIMER_CHMR1_CH2OCLREN_POS 15U -#define TIMER_CHMR1_CH2OCLREN_MSK BIT(TIMER_CHMR1_CH2OCLREN_POS) - -#define TIMER_CHMR1_CH2OMOD_POSS 12U -#define TIMER_CHMR1_CH2OMOD_POSE 14U -#define TIMER_CHMR1_CH2OMOD_MSK BITS(TIMER_CHMR1_CH2OMOD_POSS,TIMER_CHMR1_CH2OMOD_POSE) - -#define TIMER_CHMR1_CH2OPEN_POS 11U -#define TIMER_CHMR1_CH2OPEN_MSK BIT(TIMER_CHMR1_CH2OPEN_POS) - -#define TIMER_CHMR1_CH2OFEN_POS 10U -#define TIMER_CHMR1_CH2OFEN_MSK BIT(TIMER_CHMR1_CH2OFEN_POS) - -#define TIMER_CHMR1_CC2SSEL_POSS 8U -#define TIMER_CHMR1_CC2SSEL_POSE 9U -#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) - -#define TIMER_CHMR1_CH1OCLREN_POS 7U -#define TIMER_CHMR1_CH1OCLREN_MSK BIT(TIMER_CHMR1_CH1OCLREN_POS) - -#define TIMER_CHMR1_CH1OMOD_POSS 4U -#define TIMER_CHMR1_CH1OMOD_POSE 6U -#define TIMER_CHMR1_CH1OMOD_MSK BITS(TIMER_CHMR1_CH1OMOD_POSS,TIMER_CHMR1_CH1OMOD_POSE) - -#define TIMER_CHMR1_CH1OPREN_POS 3U -#define TIMER_CHMR1_CH1OPREN_MSK BIT(TIMER_CHMR1_CH1OPREN_POS) - -#define TIMER_CHMR1_CH1OHSEN_POS 2U -#define TIMER_CHMR1_CH1OHSEN_MSK BIT(TIMER_CHMR1_CH1OHSEN_POS) - -#define TIMER_CHMR1_CC1SSEL_POSS 0U -#define TIMER_CHMR1_CC1SSEL_POSE 1U -#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) - -/* Input */ -#define TIMER_CHMR1_I2FLT_POSS 12U -#define TIMER_CHMR1_I2FLT_POSE 15U -#define TIMER_CHMR1_I2FLT_MSK BITS(TIMER_CHMR1_I2FLT_POSS,TIMER_CHMR1_I2FLT_POSE) - -#define TIMER_CHMR1_IC2PRES_POSS 10U -#define TIMER_CHMR1_IC2PRES_POSE 11U -#define TIMER_CHMR1_IC2PRES_MSK BITS(TIMER_CHMR1_IC2PRES_POSS,TIMER_CHMR1_IC2PRES_POSE) - -#define TIMER_CHMR1_CC2SSEL_POSS 8U -#define TIMER_CHMR1_CC2SSEL_POSE 9U -#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) - -#define TIMER_CHMR1_I1FLT_POSS 4U -#define TIMER_CHMR1_I1FLT_POSE 7U -#define TIMER_CHMR1_I1FLT_MSK BITS(TIMER_CHMR1_I1FLT_POSS,TIMER_CHMR1_I1FLT_POSE) - -#define TIMER_CHMR1_IC1PRES_POSS 2U -#define TIMER_CHMR1_IC1PRES_POSE 3U -#define TIMER_CHMR1_IC1PRES_MSK BITS(TIMER_CHMR1_IC1PRES_POSS,TIMER_CHMR1_IC1PRES_POSE) - -#define TIMER_CHMR1_CC1SSEL_POSS 0U -#define TIMER_CHMR1_CC1SSEL_POSE 1U -#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) - -/****************** Bit definition for TIMER_CHMR2 register ************************/ -/* Output */ -#define TIMER_CHMR2_CH4OCLREN_POS 15U -#define TIMER_CHMR2_CH4OCLREN_MSK BIT(TIMER_CHMR2_CH4OCLREN_POS) - -#define TIMER_CHMR2_CH4OMOD_POSS 12U -#define TIMER_CHMR2_CH4OMOD_POSE 14U -#define TIMER_CHMR2_CH4OMOD_MSK BITS(TIMER_CHMR2_CH4OMOD_POSS,TIMER_CHMR2_CH4OMOD_POSE) - -#define TIMER_CHMR2_CH4OPEN_POS 11U -#define TIMER_CHMR2_CH4OPEN_MSK BIT(TIMER_CHMR2_CH4OPEN_POS) - -#define TIMER_CHMR2_CH4OHSEN_POS 10U -#define TIMER_CHMR2_CH4OHSEN_MSK BIT(TIMER_CHMR2_CH4OHSEN_POS) - -#define TIMER_CHMR2_CC4SSEL_POSS 8U -#define TIMER_CHMR2_CC4SSEL_POSE 9U -#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) - -#define TIMER_CHMR2_CH3OCLREN_POS 7U -#define TIMER_CHMR2_CH3OCLREN_MSK BIT(TIMER_CHMR2_CH3OCLREN_POS) - -#define TIMER_CHMR2_CH3OMOD_POSS 4U -#define TIMER_CHMR2_CH3OMOD_POSE 6U -#define TIMER_CHMR2_CH3OMOD_MSK BITS(TIMER_CHMR2_CH3OMOD_POSS,TIMER_CHMR2_CH3OMOD_POSE) - -#define TIMER_CHMR2_CH3OPEN_POS 3U -#define TIMER_CHMR2_CH3OPEN_MSK BIT(TIMER_CHMR2_CH3OPEN_POS) - -#define TIMER_CHMR2_CH3OFEN_POS 2U -#define TIMER_CHMR2_CH3OFEN_MSK BIT(TIMER_CHMR2_CH3OFEN_POS) - -#define TIMER_CHMR2_CC3SSEL_POSS 0U -#define TIMER_CHMR2_CC3SSEL_POSE 1U -#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) - -/* Input */ -#define TIMER_CHMR2_I4FLT_POSS 12U -#define TIMER_CHMR2_I4FLT_POSE 15U -#define TIMER_CHMR2_I4FLT_MSK BITS(TIMER_CHMR2_I4FLT_POSS,TIMER_CHMR2_I4FLT_POSE) - -#define TIMER_CHMR2_IC4PRES_POSS 10U -#define TIMER_CHMR2_IC4PRES_POSE 11U -#define TIMER_CHMR2_IC4PRES_MSK BITS(TIMER_CHMR2_IC4PRES_POSS,TIMER_CHMR2_IC4PRES_POSE) - -#define TIMER_CHMR2_CC4SSEL_POSS 8U -#define TIMER_CHMR2_CC4SSEL_POSE 9U -#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) - -#define TIMER_CHMR2_I3FLT_POSS 4U -#define TIMER_CHMR2_I3FLT_POSE 7U -#define TIMER_CHMR2_I3FLT_MSK BITS(TIMER_CHMR2_I3FLT_POSS,TIMER_CHMR2_I3FLT_POSE) - -#define TIMER_CHMR2_IC3PRES_POSS 2U -#define TIMER_CHMR2_IC3PRES_POSE 3U -#define TIMER_CHMR2_IC3PRES_MSK BITS(TIMER_CHMR2_IC3PRES_POSS,TIMER_CHMR2_IC3PRES_POSE) - -#define TIMER_CHMR2_CC3SSEL_POSS 0U -#define TIMER_CHMR2_CC3SSEL_POSE 1U -#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) - -/****************** Bit definition for TIMER_CCEP register ************************/ - -#define TIMER_CCEP_CC4POL_POS 13U -#define TIMER_CCEP_CC4POL_MSK BIT(TIMER_CCEP_CC4POL_POS) - -#define TIMER_CCEP_CC4EN_POS 12U -#define TIMER_CCEP_CC4EN_MSK BIT(TIMER_CCEP_CC4EN_POS) - -#define TIMER_CCEP_CC3NPOL_POS 11U -#define TIMER_CCEP_CC3NPOL_MSK BIT(TIMER_CCEP_CC3NPOL_POS) - -#define TIMER_CCEP_CC3NEN_POS 10U -#define TIMER_CCEP_CC3NEN_MSK BIT(TIMER_CCEP_CC3NEN_POS) - -#define TIMER_CCEP_CC3POL_POS 9U -#define TIMER_CCEP_CC3POL_MSK BIT(TIMER_CCEP_CC3POL_POS) - -#define TIMER_CCEP_CC3EN_POS 8U -#define TIMER_CCEP_CC3EN_MSK BIT(TIMER_CCEP_CC3EN_POS) - -#define TIMER_CCEP_CC2NPOL_POS 7U -#define TIMER_CCEP_CC2NPOL_MSK BIT(TIMER_CCEP_CC2NPOL_POS) - -#define TIMER_CCEP_CC2NEN_POS 6U -#define TIMER_CCEP_CC2NEN_MSK BIT(TIMER_CCEP_CC2NEN_POS) - -#define TIMER_CCEP_CC2POL_POS 5U -#define TIMER_CCEP_CC2POL_MSK BIT(TIMER_CCEP_CC2POL_POS) - -#define TIMER_CCEP_CC2EN_POS 4U -#define TIMER_CCEP_CC2EN_MSK BIT(TIMER_CCEP_CC2EN_POS) - -#define TIMER_CCEP_CC1NPOL_POS 3U -#define TIMER_CCEP_CC1NPOL_MSK BIT(TIMER_CCEP_CC1NPOL_POS) - -#define TIMER_CCEP_CC1NEN_POS 2U -#define TIMER_CCEP_CC1NEN_MSK BIT(TIMER_CCEP_CC1NEN_POS) - -#define TIMER_CCEP_CC1POL_POS 1U -#define TIMER_CCEP_CC1POL_MSK BIT(TIMER_CCEP_CC1POL_POS) - -#define TIMER_CCEP_CC1EN_POS 0U -#define TIMER_CCEP_CC1EN_MSK BIT(TIMER_CCEP_CC1EN_POS) - -/****************** Bit definition for TIMER_COUNT register ************************/ - -#define TIMER_COUNT_CNTV_POSS 0U -#define TIMER_COUNT_CNTV_POSE 15U -#define TIMER_COUNT_CNTV_MSK BITS(TIMER_COUNT_CNTV_POSS,TIMER_COUNT_CNTV_POSE) - -/****************** Bit definition for TIMER_PRES register ************************/ - -#define TIMER_PRES_PSCV_POSS 0U -#define TIMER_PRES_PSCV_POSE 15U -#define TIMER_PRES_PSCV_MSK BITS(TIMER_PRES_PSCV_POSS,TIMER_PRES_PSCV_POSE) - -/****************** Bit definition for TIMER_AR register ************************/ - -#define TIMER_AR_ARRV_POSS 0U -#define TIMER_AR_ARRV_POSE 15U -#define TIMER_AR_ARRV_MSK BITS(TIMER_AR_ARRV_POSS,TIMER_AR_ARRV_POSE) - -/****************** Bit definition for TIMER_REPAR register ************************/ - -#define TIMER_REPAR_REPV_POSS 0U -#define TIMER_REPAR_REPV_POSE 7U -#define TIMER_REPAR_REPV_MSK BITS(TIMER_REPAR_REPV_POSS,TIMER_REPAR_REPV_POSE) - -/****************** Bit definition for TIMER_CCVAL1 register ************************/ - -#define TIMER_CCVAL1_CCRV1_POSS 0U -#define TIMER_CCVAL1_CCRV1_POSE 15U -#define TIMER_CCVAL1_CCRV1_MSK BITS(TIMER_CCVAL1_CCRV1_POSS,TIMER_CCVAL1_CCRV1_POSE) - -/****************** Bit definition for TIMER_CCVAL2 register ************************/ - -#define TIMER_CCVAL2_CCRV2_POSS 0U -#define TIMER_CCVAL2_CCRV2_POSE 15U -#define TIMER_CCVAL2_CCRV2_MSK BITS(TIMER_CCVAL2_CCRV2_POSS,TIMER_CCVAL2_CCRV2_POSE) - -/****************** Bit definition for TIMER_CCVAL3 register ************************/ - -#define TIMER_CCVAL3_CCRV3_POSS 0U -#define TIMER_CCVAL3_CCRV3_POSE 15U -#define TIMER_CCVAL3_CCRV3_MSK BITS(TIMER_CCVAL3_CCRV3_POSS,TIMER_CCVAL3_CCRV3_POSE) - -/****************** Bit definition for TIMER_CCVAL4 register ************************/ - -#define TIMER_CCVAL4_CCRV4_POSS 0U -#define TIMER_CCVAL4_CCRV4_POSE 15U -#define TIMER_CCVAL4_CCRV4_MSK BITS(TIMER_CCVAL4_CCRV4_POSS,TIMER_CCVAL4_CCRV4_POSE) - -/****************** Bit definition for TIMER_BDCFG register ************************/ - -#define TIMER_BDCFG_GOEN_POS 15U -#define TIMER_BDCFG_GOEN_MSK BIT(TIMER_BDCFG_GOEN_POS) - -#define TIMER_BDCFG_AOEN_POS 14U -#define TIMER_BDCFG_AOEN_MSK BIT(TIMER_BDCFG_AOEN_POS) - -#define TIMER_BDCFG_BRKP_POS 13U -#define TIMER_BDCFG_BRKP_MSK BIT(TIMER_BDCFG_BRKP_POS) - -#define TIMER_BDCFG_BRKEN_POS 12U -#define TIMER_BDCFG_BRKEN_MSK BIT(TIMER_BDCFG_BRKEN_POS) - -#define TIMER_BDCFG_OFFSSR_POS 11U -#define TIMER_BDCFG_OFFSSR_MSK BIT(TIMER_BDCFG_OFFSSR_POS) - -#define TIMER_BDCFG_OFFSSI_POS 10U -#define TIMER_BDCFG_OFFSSI_MSK BIT(TIMER_BDCFG_OFFSSI_POS) - -#define TIMER_BDCFG_LOCKLVL_POSS 8U -#define TIMER_BDCFG_LOCKLVL_POSE 9U -#define TIMER_BDCFG_LOCKLVL_MSK BITS(TIMER_BDCFG_LOCKLVL_POSS,TIMER_BDCFG_LOCKLVL_POSE) - -#define TIMER_BDCFG_DT_POSS 0U -#define TIMER_BDCFG_DT_POSE 7U -#define TIMER_BDCFG_DT_MSK BITS(TIMER_BDCFG_DT_POSS,TIMER_BDCFG_DT_POSE) - -typedef struct -{ - __IO uint32_t CON1; - __IO uint32_t CON2; - __IO uint32_t SMCON; - __O uint32_t DIER; - __O uint32_t DIDR; - __I uint32_t DIVS; - __I uint32_t RIF; - __I uint32_t IFM; - __O uint32_t ICR; - __O uint32_t SGE; - __IO uint32_t CHMR1; - __IO uint32_t CHMR2; - __IO uint32_t CCEP; - __IO uint32_t COUNT; - __IO uint32_t PRES; - __IO uint32_t AR; - __IO uint32_t REPAR; - __IO uint32_t CCVAL1; - __IO uint32_t CCVAL2; - __IO uint32_t CCVAL3; - __IO uint32_t CCVAL4; - __IO uint32_t BDCFG; -} TIMER_TypeDef; - -/****************** Bit definition for USART_STAT register ************************/ - -#define USART_STAT_CTSIF_POS 9U -#define USART_STAT_CTSIF_MSK BIT(USART_STAT_CTSIF_POS) - -#define USART_STAT_TXEMPIF_POS 7U -#define USART_STAT_TXEMPIF_MSK BIT(USART_STAT_TXEMPIF_POS) - -#define USART_STAT_TXCIF_POS 6U -#define USART_STAT_TXCIF_MSK BIT(USART_STAT_TXCIF_POS) - -#define USART_STAT_RXNEIF_POS 5U -#define USART_STAT_RXNEIF_MSK BIT(USART_STAT_RXNEIF_POS) - -#define USART_STAT_IDLEIF_POS 4U -#define USART_STAT_IDLEIF_MSK BIT(USART_STAT_IDLEIF_POS) - -#define USART_STAT_OVRIF_POS 3U -#define USART_STAT_OVRIF_MSK BIT(USART_STAT_OVRIF_POS) - -#define USART_STAT_NDETIF_POS 2U -#define USART_STAT_NDETIF_MSK BIT(USART_STAT_NDETIF_POS) - -#define USART_STAT_FERRIF_POS 1U -#define USART_STAT_FERRIF_MSK BIT(USART_STAT_FERRIF_POS) - -#define USART_STAT_PERRIF_POS 0U -#define USART_STAT_PERRIF_MSK BIT(USART_STAT_PERRIF_POS) - -/****************** Bit definition for USART_DATA register ************************/ - -#define USART_DATA_VAL_POSS 0U -#define USART_DATA_VAL_POSE 8U -#define USART_DATA_VAL_MSK BITS(USART_DATA_VAL_POSS,USART_DATA_VAL_POSE) - -/****************** Bit definition for USART_BAUDCON register ************************/ - -#define USART_BAUDCON_DIV_M_POSS 4U -#define USART_BAUDCON_DIV_M_POSE 15U -#define USART_BAUDCON_DIV_M_MSK BITS(USART_BAUDCON_DIV_M_POSS,USART_BAUDCON_DIV_M_POSE) - -#define USART_BAUDCON_DIV_F_POSS 0U -#define USART_BAUDCON_DIV_F_POSE 3U -#define USART_BAUDCON_DIV_F_MSK BITS(USART_BAUDCON_DIV_F_POSS,USART_BAUDCON_DIV_F_POSE) - -/****************** Bit definition for USART_CON0 register ************************/ - -#define USART_CON0_EN_POS 13U -#define USART_CON0_EN_MSK BIT(USART_CON0_EN_POS) - -#define USART_CON0_DLEN_POS 12U -#define USART_CON0_DLEN_MSK BIT(USART_CON0_DLEN_POS) - -#define USART_CON0_WKMOD_POS 11U -#define USART_CON0_WKMOD_MSK BIT(USART_CON0_WKMOD_POS) - -#define USART_CON0_PEN_POS 10U -#define USART_CON0_PEN_MSK BIT(USART_CON0_PEN_POS) - -#define USART_CON0_PSEL_POS 9U -#define USART_CON0_PSEL_MSK BIT(USART_CON0_PSEL_POS) - -#define USART_CON0_PERRIE_POS 8U -#define USART_CON0_PERRIE_MSK BIT(USART_CON0_PERRIE_POS) - -#define USART_CON0_TXEMPIE_POS 7U -#define USART_CON0_TXEMPIE_MSK BIT(USART_CON0_TXEMPIE_POS) - -#define USART_CON0_TXCIE_POS 6U -#define USART_CON0_TXCIE_MSK BIT(USART_CON0_TXCIE_POS) - -#define USART_CON0_RXNEIE_POS 5U -#define USART_CON0_RXNEIE_MSK BIT(USART_CON0_RXNEIE_POS) - -#define USART_CON0_IDLEIE_POS 4U -#define USART_CON0_IDLEIE_MSK BIT(USART_CON0_IDLEIE_POS) - -#define USART_CON0_TXEN_POS 3U -#define USART_CON0_TXEN_MSK BIT(USART_CON0_TXEN_POS) - -#define USART_CON0_RXEN_POS 2U -#define USART_CON0_RXEN_MSK BIT(USART_CON0_RXEN_POS) - -#define USART_CON0_RXWK_POS 1U -#define USART_CON0_RXWK_MSK BIT(USART_CON0_RXWK_POS) - -/****************** Bit definition for USART_CON1 register ************************/ - -#define USART_CON1_STPLEN_POSS 12U -#define USART_CON1_STPLEN_POSE 13U -#define USART_CON1_STPLEN_MSK BITS(USART_CON1_STPLEN_POSS,USART_CON1_STPLEN_POSE) - -#define USART_CON1_SCKEN_POS 11U -#define USART_CON1_SCKEN_MSK BIT(USART_CON1_SCKEN_POS) - -#define USART_CON1_SCKPOL_POS 10U -#define USART_CON1_SCKPOL_MSK BIT(USART_CON1_SCKPOL_POS) - -#define USART_CON1_SCKPHA_POS 9U -#define USART_CON1_SCKPHA_MSK BIT(USART_CON1_SCKPHA_POS) - -#define USART_CON1_LBCP_POS 8U -#define USART_CON1_LBCP_MSK BIT(USART_CON1_LBCP_POS) - -#define USART_CON1_ADDR_POSS 0U -#define USART_CON1_ADDR_POSE 3U -#define USART_CON1_ADDR_MSK BITS(USART_CON1_ADDR_POSS,USART_CON1_ADDR_POSE) - -/****************** Bit definition for USART_CON2 register ************************/ - -#define USART_CON2_CTSIE_POS 10U -#define USART_CON2_CTSIE_MSK BIT(USART_CON2_CTSIE_POS) - -#define USART_CON2_CTSEN_POS 9U -#define USART_CON2_CTSEN_MSK BIT(USART_CON2_CTSEN_POS) - -#define USART_CON2_RTSEN_POS 8U -#define USART_CON2_RTSEN_MSK BIT(USART_CON2_RTSEN_POS) - -#define USART_CON2_TXDMAEN_POS 7U -#define USART_CON2_TXDMAEN_MSK BIT(USART_CON2_TXDMAEN_POS) - -#define USART_CON2_RXDMAEN_POS 6U -#define USART_CON2_RXDMAEN_MSK BIT(USART_CON2_RXDMAEN_POS) - -#define USART_CON2_SMARTEN_POS 5U -#define USART_CON2_SMARTEN_MSK BIT(USART_CON2_SMARTEN_POS) - -#define USART_CON2_NACK_POS 4U -#define USART_CON2_NACK_MSK BIT(USART_CON2_NACK_POS) - -#define USART_CON2_HDPSEL_POS 3U -#define USART_CON2_HDPSEL_MSK BIT(USART_CON2_HDPSEL_POS) - -#define USART_CON2_IREN_POS 1U -#define USART_CON2_IREN_MSK BIT(USART_CON2_IREN_POS) - -#define USART_CON2_ERRIE_POS 0U -#define USART_CON2_ERRIE_MSK BIT(USART_CON2_ERRIE_POS) - -/****************** Bit definition for USART_GP register ************************/ - -#define USART_GP_GTVAL_POSS 8U -#define USART_GP_GTVAL_POSE 15U -#define USART_GP_GTVAL_MSK BITS(USART_GP_GTVAL_POSS,USART_GP_GTVAL_POSE) - -#define USART_GP_PSC_POSS 0U -#define USART_GP_PSC_POSE 7U -#define USART_GP_PSC_MSK BITS(USART_GP_PSC_POSS,USART_GP_PSC_POSE) - -typedef struct -{ - __IO uint32_t STAT; - __IO uint32_t DATA; - __IO uint32_t BAUDCON; - __IO uint32_t CON0; - __IO uint32_t CON1; - __IO uint32_t CON2; - __IO uint32_t GP; -} USART_TypeDef; - -/****************** Bit definition for UART_RBR register ************************/ - -#define UART_RBR_RBR_POSS 0U -#define UART_RBR_RBR_POSE 8U -#define UART_RBR_RBR_MSK BITS(UART_RBR_RBR_POSS,UART_RBR_RBR_POSE) - -/****************** Bit definition for UART_TBR register ************************/ - -#define UART_TBR_TBR_POSS 0U -#define UART_TBR_TBR_POSE 8U -#define UART_TBR_TBR_MSK BITS(UART_TBR_TBR_POSS,UART_TBR_TBR_POSE) - -/****************** Bit definition for UART_BRR register ************************/ - -#define UART_BRR_BRR_POSS 0U -#define UART_BRR_BRR_POSE 15U -#define UART_BRR_BRR_MSK BITS(UART_BRR_BRR_POSS,UART_BRR_BRR_POSE) - -/****************** Bit definition for UART_LCR register ************************/ - -#define UART_LCR_SWAP_POS 13U -#define UART_LCR_SWAP_MSK BIT(UART_LCR_SWAP_POS) - -#define UART_LCR_TXINV_POS 12U -#define UART_LCR_TXINV_MSK BIT(UART_LCR_TXINV_POS) - -#define UART_LCR_RXINV_POS 11U -#define UART_LCR_RXINV_MSK BIT(UART_LCR_RXINV_POS) - -#define UART_LCR_DATAINV_POS 10U -#define UART_LCR_DATAINV_MSK BIT(UART_LCR_DATAINV_POS) - -#define UART_LCR_MSBFIRST_POS 9U -#define UART_LCR_MSBFIRST_MSK BIT(UART_LCR_MSBFIRST_POS) - -#define UART_LCR_RTOEN_POS 8U -#define UART_LCR_RTOEN_MSK BIT(UART_LCR_RTOEN_POS) - -#define UART_LCR_BRWEN_POS 7U -#define UART_LCR_BRWEN_MSK BIT(UART_LCR_BRWEN_POS) - -#define UART_LCR_BC_POS 6U -#define UART_LCR_BC_MSK BIT(UART_LCR_BC_POS) - -#define UART_LCR_RXEN_POS 5U -#define UART_LCR_RXEN_MSK BIT(UART_LCR_RXEN_POS) - -#define UART_LCR_PS_POS 4U -#define UART_LCR_PS_MSK BIT(UART_LCR_PS_POS) - -#define UART_LCR_PEN_POS 3U -#define UART_LCR_PEN_MSK BIT(UART_LCR_PEN_POS) - -#define UART_LCR_STOP_POS 2U -#define UART_LCR_STOP_MSK BIT(UART_LCR_STOP_POS) - -#define UART_LCR_DLS_POSS 0U -#define UART_LCR_DLS_POSE 1U -#define UART_LCR_DLS_MSK BITS(UART_LCR_DLS_POSS,UART_LCR_DLS_POSE) - -/****************** Bit definition for UART_MCR register ************************/ - -#define UART_MCR_HDSEL_POS 22U -#define UART_MCR_HDSEL_MSK BIT(UART_MCR_HDSEL_POS) - -#define UART_MCR_ABRRS_POS 15U -#define UART_MCR_ABRRS_MSK BIT(UART_MCR_ABRRS_POS) - -#define UART_MCR_ABRMOD_POSS 13U -#define UART_MCR_ABRMOD_POSE 14U -#define UART_MCR_ABRMOD_MSK BITS(UART_MCR_ABRMOD_POSS,UART_MCR_ABRMOD_POSE) - -#define UART_MCR_ABREN_POS 12U -#define UART_MCR_ABREN_MSK BIT(UART_MCR_ABREN_POS) - -#define UART_MCR_DMAEN_POS 11U -#define UART_MCR_DMAEN_MSK BIT(UART_MCR_DMAEN_POS) - -#define UART_MCR_LINBDL_POS 10U -#define UART_MCR_LINBDL_MSK BIT(UART_MCR_LINBDL_POS) - -#define UART_MCR_BKREQ_POS 9U -#define UART_MCR_BKREQ_MSK BIT(UART_MCR_BKREQ_POS) - -#define UART_MCR_LINEN_POS 8U -#define UART_MCR_LINEN_MSK BIT(UART_MCR_LINEN_POS) - -#define UART_MCR_AADINV_POS 7U -#define UART_MCR_AADINV_MSK BIT(UART_MCR_AADINV_POS) - -#define UART_MCR_AADDIR_POS 6U -#define UART_MCR_AADDIR_MSK BIT(UART_MCR_AADDIR_POS) - -#define UART_MCR_AADNOR_POS 5U -#define UART_MCR_AADNOR_MSK BIT(UART_MCR_AADNOR_POS) - -#define UART_MCR_AADEN_POS 4U -#define UART_MCR_AADEN_MSK BIT(UART_MCR_AADEN_POS) - -#define UART_MCR_RTSCTRL_POS 3U -#define UART_MCR_RTSCTRL_MSK BIT(UART_MCR_RTSCTRL_POS) - -#define UART_MCR_AFCEN_POS 2U -#define UART_MCR_AFCEN_MSK BIT(UART_MCR_AFCEN_POS) - -#define UART_MCR_LBEN_POS 1U -#define UART_MCR_LBEN_MSK BIT(UART_MCR_LBEN_POS) - -#define UART_MCR_IREN_POS 0U -#define UART_MCR_IREN_MSK BIT(UART_MCR_IREN_POS) - -/****************** Bit definition for UART_CR register ************************/ - -#define UART_CR_PSC_POSS 16U -#define UART_CR_PSC_POSE 23U -#define UART_CR_PSC_MSK BITS(UART_CR_PSC_POSS,UART_CR_PSC_POSE) - -#define UART_CR_DLY_POSS 8U -#define UART_CR_DLY_POSE 15U -#define UART_CR_DLY_MSK BITS(UART_CR_DLY_POSS,UART_CR_DLY_POSE) - -#define UART_CR_ADDR_POSS 0U -#define UART_CR_ADDR_POSE 7U -#define UART_CR_ADDR_MSK BITS(UART_CR_ADDR_POSS,UART_CR_ADDR_POSE) - -/****************** Bit definition for UART_RTOR register ************************/ - -#define UART_RTOR_BLEN_POSS 24U -#define UART_RTOR_BLEN_POSE 31U -#define UART_RTOR_BLEN_MSK BITS(UART_RTOR_BLEN_POSS,UART_RTOR_BLEN_POSE) - -#define UART_RTOR_RTO_POSS 0U -#define UART_RTOR_RTO_POSE 23U -#define UART_RTOR_RTO_MSK BITS(UART_RTOR_RTO_POSS,UART_RTOR_RTO_POSE) - -/****************** Bit definition for UART_FCR register ************************/ - -#define UART_FCR_TXFL_POSS 12U -#define UART_FCR_TXFL_POSE 15U -#define UART_FCR_TXFL_MSK BITS(UART_FCR_TXFL_POSS,UART_FCR_TXFL_POSE) - -#define UART_FCR_RXFL_POSS 8U -#define UART_FCR_RXFL_POSE 11U -#define UART_FCR_RXFL_MSK BITS(UART_FCR_RXFL_POSS,UART_FCR_RXFL_POSE) - -#define UART_FCR_TXTL_POSS 6U -#define UART_FCR_TXTL_POSE 7U -#define UART_FCR_TXTL_MSK BITS(UART_FCR_TXTL_POSS,UART_FCR_TXTL_POSE) - -#define UART_FCR_RXTL_POSS 4U -#define UART_FCR_RXTL_POSE 5U -#define UART_FCR_RXTL_MSK BITS(UART_FCR_RXTL_POSS,UART_FCR_RXTL_POSE) - -#define UART_FCR_TFRST_POS 2U -#define UART_FCR_TFRST_MSK BIT(UART_FCR_TFRST_POS) - -#define UART_FCR_RFRST_POS 1U -#define UART_FCR_RFRST_MSK BIT(UART_FCR_RFRST_POS) - -#define UART_FCR_FIFOEN_POS 0U -#define UART_FCR_FIFOEN_MSK BIT(UART_FCR_FIFOEN_POS) - -/****************** Bit definition for UART_SR register ************************/ - -#define UART_SR_CTS_POS 14U -#define UART_SR_CTS_MSK BIT(UART_SR_CTS_POS) - -#define UART_SR_DCTS_POS 13U -#define UART_SR_DCTS_MSK BIT(UART_SR_DCTS_POS) - -#define UART_SR_RFF_POS 12U -#define UART_SR_RFF_MSK BIT(UART_SR_RFF_POS) - -#define UART_SR_RFNE_POS 11U -#define UART_SR_RFNE_MSK BIT(UART_SR_RFNE_POS) - -#define UART_SR_TFEM_POS 10U -#define UART_SR_TFEM_MSK BIT(UART_SR_TFEM_POS) - -#define UART_SR_TFNF_POS 9U -#define UART_SR_TFNF_MSK BIT(UART_SR_TFNF_POS) - -#define UART_SR_BUSY_POS 8U -#define UART_SR_BUSY_MSK BIT(UART_SR_BUSY_POS) - -#define UART_SR_RFE_POS 7U -#define UART_SR_RFE_MSK BIT(UART_SR_RFE_POS) - -#define UART_SR_TEM_POS 6U -#define UART_SR_TEM_MSK BIT(UART_SR_TEM_POS) - -#define UART_SR_TBEM_POS 5U -#define UART_SR_TBEM_MSK BIT(UART_SR_TBEM_POS) - -#define UART_SR_BF_POS 4U -#define UART_SR_BF_MSK BIT(UART_SR_BF_POS) - -#define UART_SR_FE_POS 3U -#define UART_SR_FE_MSK BIT(UART_SR_FE_POS) - -#define UART_SR_PE_POS 2U -#define UART_SR_PE_MSK BIT(UART_SR_PE_POS) - -#define UART_SR_OE_POS 1U -#define UART_SR_OE_MSK BIT(UART_SR_OE_POS) - -#define UART_SR_DR_POS 0U -#define UART_SR_DR_MSK BIT(UART_SR_DR_POS) - -/****************** Bit definition for UART_IER register ************************/ - -#define UART_IER_CMIE_POS 11U -#define UART_IER_CMIE_MSK BIT(UART_IER_CMIE_POS) - -#define UART_IER_EOBIE_POS 10U -#define UART_IER_EOBIE_MSK BIT(UART_IER_EOBIE_POS) - -#define UART_IER_TCIE_POS 9U -#define UART_IER_TCIE_MSK BIT(UART_IER_TCIE_POS) - -#define UART_IER_LINBKIE_POS 8U -#define UART_IER_LINBKIE_MSK BIT(UART_IER_LINBKIE_POS) - -#define UART_IER_ABTOIE_POS 7U -#define UART_IER_ABTOIE_MSK BIT(UART_IER_ABTOIE_POS) - -#define UART_IER_ABEIE_POS 6U -#define UART_IER_ABEIE_MSK BIT(UART_IER_ABEIE_POS) - -#define UART_IER_BZIE_POS 5U -#define UART_IER_BZIE_MSK BIT(UART_IER_BZIE_POS) - -#define UART_IER_RTOIE_POS 4U -#define UART_IER_RTOIE_MSK BIT(UART_IER_RTOIE_POS) - -#define UART_IER_MDSIE_POS 3U -#define UART_IER_MDSIE_MSK BIT(UART_IER_MDSIE_POS) - -#define UART_IER_RXSIE_POS 2U -#define UART_IER_RXSIE_MSK BIT(UART_IER_RXSIE_POS) - -#define UART_IER_TXSIE_POS 1U -#define UART_IER_TXSIE_MSK BIT(UART_IER_TXSIE_POS) - -#define UART_IER_RXRDIE_POS 0U -#define UART_IER_RXRDIE_MSK BIT(UART_IER_RXRDIE_POS) - -/****************** Bit definition for UART_IDR register ************************/ - -#define UART_IDR_CMID_POS 11U -#define UART_IDR_CMID_MSK BIT(UART_IDR_CMID_POS) - -#define UART_IDR_EOBID_POS 10U -#define UART_IDR_EOBID_MSK BIT(UART_IDR_EOBID_POS) - -#define UART_IDR_TCID_POS 9U -#define UART_IDR_TCID_MSK BIT(UART_IDR_TCID_POS) - -#define UART_IDR_LINBKID_POS 8U -#define UART_IDR_LINBKID_MSK BIT(UART_IDR_LINBKID_POS) - -#define UART_IDR_ABTOID_POS 7U -#define UART_IDR_ABTOID_MSK BIT(UART_IDR_ABTOID_POS) - -#define UART_IDR_ABEID_POS 6U -#define UART_IDR_ABEID_MSK BIT(UART_IDR_ABEID_POS) - -#define UART_IDR_BZID_POS 5U -#define UART_IDR_BZID_MSK BIT(UART_IDR_BZID_POS) - -#define UART_IDR_RTOID_POS 4U -#define UART_IDR_RTOID_MSK BIT(UART_IDR_RTOID_POS) - -#define UART_IDR_MDSID_POS 3U -#define UART_IDR_MDSID_MSK BIT(UART_IDR_MDSID_POS) - -#define UART_IDR_RXSID_POS 2U -#define UART_IDR_RXSID_MSK BIT(UART_IDR_RXSID_POS) - -#define UART_IDR_TXSID_POS 1U -#define UART_IDR_TXSID_MSK BIT(UART_IDR_TXSID_POS) - -#define UART_IDR_RXRDID_POS 0U -#define UART_IDR_RXRDID_MSK BIT(UART_IDR_RXRDID_POS) - -/****************** Bit definition for UART_IVS register ************************/ - -#define UART_IVS_CMIS_POS 11U -#define UART_IVS_CMIS_MSK BIT(UART_IVS_CMIS_POS) - -#define UART_IVS_EOBIS_POS 10U -#define UART_IVS_EOBIS_MSK BIT(UART_IVS_EOBIS_POS) - -#define UART_IVS_TCIS_POS 9U -#define UART_IVS_TCIS_MSK BIT(UART_IVS_TCIS_POS) - -#define UART_IVS_LINBKIS_POS 8U -#define UART_IVS_LINBKIS_MSK BIT(UART_IVS_LINBKIS_POS) - -#define UART_IVS_ABTOIS_POS 7U -#define UART_IVS_ABTOIS_MSK BIT(UART_IVS_ABTOIS_POS) - -#define UART_IVS_ABEIS_POS 6U -#define UART_IVS_ABEIS_MSK BIT(UART_IVS_ABEIS_POS) - -#define UART_IVS_BZIS_POS 5U -#define UART_IVS_BZIS_MSK BIT(UART_IVS_BZIS_POS) - -#define UART_IVS_RTOIS_POS 4U -#define UART_IVS_RTOIS_MSK BIT(UART_IVS_RTOIS_POS) - -#define UART_IVS_MDSIS_POS 3U -#define UART_IVS_MDSIS_MSK BIT(UART_IVS_MDSIS_POS) - -#define UART_IVS_RXSIS_POS 2U -#define UART_IVS_RXSIS_MSK BIT(UART_IVS_RXSIS_POS) - -#define UART_IVS_TXSIS_POS 1U -#define UART_IVS_TXSIS_MSK BIT(UART_IVS_TXSIS_POS) - -#define UART_IVS_RXRDIS_POS 0U -#define UART_IVS_RXRDIS_MSK BIT(UART_IVS_RXRDIS_POS) - -/****************** Bit definition for UART_RIF register ************************/ - -#define UART_RIF_CMIF_POS 11U -#define UART_RIF_CMIF_MSK BIT(UART_RIF_CMIF_POS) - -#define UART_RIF_EOBIF_POS 10U -#define UART_RIF_EOBIF_MSK BIT(UART_RIF_EOBIF_POS) - -#define UART_RIF_TCIF_POS 9U -#define UART_RIF_TCIF_MSK BIT(UART_RIF_TCIF_POS) - -#define UART_RIF_LINBKIF_POS 8U -#define UART_RIF_LINBKIF_MSK BIT(UART_RIF_LINBKIF_POS) - -#define UART_RIF_ABTOIF_POS 7U -#define UART_RIF_ABTOIF_MSK BIT(UART_RIF_ABTOIF_POS) - -#define UART_RIF_ABEIF_POS 6U -#define UART_RIF_ABEIF_MSK BIT(UART_RIF_ABEIF_POS) - -#define UART_RIF_BZIF_POS 5U -#define UART_RIF_BZIF_MSK BIT(UART_RIF_BZIF_POS) - -#define UART_RIF_RTOIF_POS 4U -#define UART_RIF_RTOIF_MSK BIT(UART_RIF_RTOIF_POS) - -#define UART_RIF_MDSIF_POS 3U -#define UART_RIF_MDSIF_MSK BIT(UART_RIF_MDSIF_POS) - -#define UART_RIF_RXSIF_POS 2U -#define UART_RIF_RXSIF_MSK BIT(UART_RIF_RXSIF_POS) - -#define UART_RIF_TXSIF_POS 1U -#define UART_RIF_TXSIF_MSK BIT(UART_RIF_TXSIF_POS) - -#define UART_RIF_RXRDIF_POS 0U -#define UART_RIF_RXRDIF_MSK BIT(UART_RIF_RXRDIF_POS) - -/****************** Bit definition for UART_IFM register ************************/ - -#define UART_IFM_CMIM_POS 11U -#define UART_IFM_CMIM_MSK BIT(UART_IFM_CMIM_POS) - -#define UART_IFM_EOBIM_POS 10U -#define UART_IFM_EOBIM_MSK BIT(UART_IFM_EOBIM_POS) - -#define UART_IFM_TCIM_POS 9U -#define UART_IFM_TCIM_MSK BIT(UART_IFM_TCIM_POS) - -#define UART_IFM_LINBKIM_POS 8U -#define UART_IFM_LINBKIM_MSK BIT(UART_IFM_LINBKIM_POS) - -#define UART_IFM_ABTOIM_POS 7U -#define UART_IFM_ABTOIM_MSK BIT(UART_IFM_ABTOIM_POS) - -#define UART_IFM_ABEIM_POS 6U -#define UART_IFM_ABEIM_MSK BIT(UART_IFM_ABEIM_POS) - -#define UART_IFM_BZIM_POS 5U -#define UART_IFM_BZIM_MSK BIT(UART_IFM_BZIM_POS) - -#define UART_IFM_RTOIM_POS 4U -#define UART_IFM_RTOIM_MSK BIT(UART_IFM_RTOIM_POS) - -#define UART_IFM_MDSIM_POS 3U -#define UART_IFM_MDSIM_MSK BIT(UART_IFM_MDSIM_POS) - -#define UART_IFM_RXSIM_POS 2U -#define UART_IFM_RXSIM_MSK BIT(UART_IFM_RXSIM_POS) - -#define UART_IFM_TXSIM_POS 1U -#define UART_IFM_TXSIM_MSK BIT(UART_IFM_TXSIM_POS) - -#define UART_IFM_RXRDIM_POS 0U -#define UART_IFM_RXRDIM_MSK BIT(UART_IFM_RXRDIM_POS) - -/****************** Bit definition for UART_ICR register ************************/ - -#define UART_ICR_CMIC_POS 11U -#define UART_ICR_CMIC_MSK BIT(UART_ICR_CMIC_POS) - -#define UART_ICR_EOBIC_POS 10U -#define UART_ICR_EOBIC_MSK BIT(UART_ICR_EOBIC_POS) - -#define UART_ICR_TCIC_POS 9U -#define UART_ICR_TCIC_MSK BIT(UART_ICR_TCIC_POS) - -#define UART_ICR_LINBKIC_POS 8U -#define UART_ICR_LINBKIC_MSK BIT(UART_ICR_LINBKIC_POS) - -#define UART_ICR_ABTOIC_POS 7U -#define UART_ICR_ABTOIC_MSK BIT(UART_ICR_ABTOIC_POS) - -#define UART_ICR_ABEIC_POS 6U -#define UART_ICR_ABEIC_MSK BIT(UART_ICR_ABEIC_POS) - -#define UART_ICR_BZIC_POS 5U -#define UART_ICR_BZIC_MSK BIT(UART_ICR_BZIC_POS) - -#define UART_ICR_CHTOIC_POS 4U -#define UART_ICR_CHTOIC_MSK BIT(UART_ICR_CHTOIC_POS) - -#define UART_ICR_MDSIC_POS 3U -#define UART_ICR_MDSIC_MSK BIT(UART_ICR_MDSIC_POS) - -#define UART_ICR_RXSIC_POS 2U -#define UART_ICR_RXSIC_MSK BIT(UART_ICR_RXSIC_POS) - -#define UART_ICR_TXSIC_POS 1U -#define UART_ICR_TXSIC_MSK BIT(UART_ICR_TXSIC_POS) - -#define UART_ICR_RXRDIC_POS 0U -#define UART_ICR_RXRDIC_MSK BIT(UART_ICR_RXRDIC_POS) - -typedef struct -{ - __I uint32_t RBR; - __IO uint32_t TBR; - __IO uint32_t BRR; - __IO uint32_t LCR; - __IO uint32_t MCR; - __IO uint32_t CR; - __IO uint32_t RTOR; - __IO uint32_t FCR; - __I uint32_t SR; - __O uint32_t IER; - __O uint32_t IDR; - __I uint32_t IVS; - __I uint32_t RIF; - __I uint32_t IFM; - __O uint32_t ICR; -} UART_TypeDef; - -/****************** Bit definition for LPUART_CON0 register ************************/ - -#define LPUART_CON0_MODESEL_POSS 30U -#define LPUART_CON0_MODESEL_POSE 31U -#define LPUART_CON0_MODESEL_MSK BITS(LPUART_CON0_MODESEL_POSS,LPUART_CON0_MODESEL_POSE) - -#define LPUART_CON0_TXDMAE_POS 29U -#define LPUART_CON0_TXDMAE_MSK BIT(LPUART_CON0_TXDMAE_POS) - -#define LPUART_CON0_RXDMAE_POS 28U -#define LPUART_CON0_RXDMAE_MSK BIT(LPUART_CON0_RXDMAE_POS) - -#define LPUART_CON0_INTERVAL_POSS 16U -#define LPUART_CON0_INTERVAL_POSE 23U -#define LPUART_CON0_INTERVAL_MSK BITS(LPUART_CON0_INTERVAL_POSS,LPUART_CON0_INTERVAL_POSE) - -#define LPUART_CON0_SYNCBP_POS 15U -#define LPUART_CON0_SYNCBP_MSK BIT(LPUART_CON0_SYNCBP_POS) - -#define LPUART_CON0_CTSPOL_POS 13U -#define LPUART_CON0_CTSPOL_MSK BIT(LPUART_CON0_CTSPOL_POS) - -#define LPUART_CON0_RTSPOL_POS 12U -#define LPUART_CON0_RTSPOL_MSK BIT(LPUART_CON0_RTSPOL_POS) - -#define LPUART_CON0_ATCTSE_POS 11U -#define LPUART_CON0_ATCTSE_MSK BIT(LPUART_CON0_ATCTSE_POS) - -#define LPUART_CON0_ATRTSE_POS 10U -#define LPUART_CON0_ATRTSE_MSK BIT(LPUART_CON0_ATRTSE_POS) - -#define LPUART_CON0_BRKCE_POS 8U -#define LPUART_CON0_BRKCE_MSK BIT(LPUART_CON0_BRKCE_POS) - -#define LPUART_CON0_LPBMOD_POS 7U -#define LPUART_CON0_LPBMOD_MSK BIT(LPUART_CON0_LPBMOD_POS) - -#define LPUART_CON0_STICKPARSEL_POS 6U -#define LPUART_CON0_STICKPARSEL_MSK BIT(LPUART_CON0_STICKPARSEL_POS) - -#define LPUART_CON0_EVENPARSEL_POS 5U -#define LPUART_CON0_EVENPARSEL_MSK BIT(LPUART_CON0_EVENPARSEL_POS) - -#define LPUART_CON0_PARCHKE_POS 4U -#define LPUART_CON0_PARCHKE_MSK BIT(LPUART_CON0_PARCHKE_POS) - -#define LPUART_CON0_STPLENTH_POS 3U -#define LPUART_CON0_STPLENTH_MSK BIT(LPUART_CON0_STPLENTH_POS) - -#define LPUART_CON0_DATLENTH_POSS 0U -#define LPUART_CON0_DATLENTH_POSE 2U -#define LPUART_CON0_DATLENTH_MSK BITS(LPUART_CON0_DATLENTH_POSS,LPUART_CON0_DATLENTH_POSE) - -/****************** Bit definition for LPUART_CON1 register ************************/ - -#define LPUART_CON1_ADDCMP_POSS 24U -#define LPUART_CON1_ADDCMP_POSE 31U -#define LPUART_CON1_ADDCMP_MSK BITS(LPUART_CON1_ADDCMP_POSS,LPUART_CON1_ADDCMP_POSE) - -#define LPUART_CON1_ADETE_POS 23U -#define LPUART_CON1_ADETE_MSK BIT(LPUART_CON1_ADETE_POS) - -#define LPUART_CON1_ATDIRM_POS 22U -#define LPUART_CON1_ATDIRM_MSK BIT(LPUART_CON1_ATDIRM_POS) - -#define LPUART_CON1_ATADETE_POS 21U -#define LPUART_CON1_ATADETE_MSK BIT(LPUART_CON1_ATADETE_POS) - -#define LPUART_CON1_NMPMOD_POS 20U -#define LPUART_CON1_NMPMOD_MSK BIT(LPUART_CON1_NMPMOD_POS) - -#define LPUART_CON1_IRWIDTH_POS 16U -#define LPUART_CON1_IRWIDTH_MSK BIT(LPUART_CON1_IRWIDTH_POS) - -#define LPUART_CON1_TOICMP_POSS 8U -#define LPUART_CON1_TOICMP_POSE 15U -#define LPUART_CON1_TOICMP_MSK BITS(LPUART_CON1_TOICMP_POSS,LPUART_CON1_TOICMP_POSE) - -#define LPUART_CON1_TOCNTE_POS 7U -#define LPUART_CON1_TOCNTE_MSK BIT(LPUART_CON1_TOCNTE_POS) - -#define LPUART_CON1_IRTXINV_POS 3U -#define LPUART_CON1_IRTXINV_MSK BIT(LPUART_CON1_IRTXINV_POS) - -#define LPUART_CON1_IRRXINV_POS 2U -#define LPUART_CON1_IRRXINV_MSK BIT(LPUART_CON1_IRRXINV_POS) - -#define LPUART_CON1_IRTXE_POS 1U -#define LPUART_CON1_IRTXE_MSK BIT(LPUART_CON1_IRTXE_POS) - -#define LPUART_CON1_RTS_POS 0U -#define LPUART_CON1_RTS_MSK BIT(LPUART_CON1_RTS_POS) - -/****************** Bit definition for LPUART_CLKDIV register ************************/ - -#define LPUART_CLKDIV_CLKDIV_POSS 0U -#define LPUART_CLKDIV_CLKDIV_POSE 19U -#define LPUART_CLKDIV_CLKDIV_MSK BITS(LPUART_CLKDIV_CLKDIV_POSS,LPUART_CLKDIV_CLKDIV_POSE) - -/****************** Bit definition for LPUART_FIFOCON register ************************/ - -#define LPUART_FIFOCON_RTSTRGLVL_POSS 12U -#define LPUART_FIFOCON_RTSTRGLVL_POSE 15U -#define LPUART_FIFOCON_RTSTRGLVL_MSK BITS(LPUART_FIFOCON_RTSTRGLVL_POSS,LPUART_FIFOCON_RTSTRGLVL_POSE) - -#define LPUART_FIFOCON_RXTRGLVL_POSS 8U -#define LPUART_FIFOCON_RXTRGLVL_POSE 11U -#define LPUART_FIFOCON_RXTRGLVL_MSK BITS(LPUART_FIFOCON_RXTRGLVL_POSS,LPUART_FIFOCON_RXTRGLVL_POSE) - -#define LPUART_FIFOCON_NMPMRXDIS_POS 2U -#define LPUART_FIFOCON_NMPMRXDIS_MSK BIT(LPUART_FIFOCON_NMPMRXDIS_POS) - -#define LPUART_FIFOCON_TXRESET_POS 1U -#define LPUART_FIFOCON_TXRESET_MSK BIT(LPUART_FIFOCON_TXRESET_POS) - -#define LPUART_FIFOCON_RXRESET_POS 0U -#define LPUART_FIFOCON_RXRESET_MSK BIT(LPUART_FIFOCON_RXRESET_POS) - -/****************** Bit definition for LPUART_RXDR register ************************/ - -#define LPUART_RXDR_FERR_POS 15U -#define LPUART_RXDR_FERR_MSK BIT(LPUART_RXDR_FERR_POS) - -#define LPUART_RXDR_PERR_POS 14U -#define LPUART_RXDR_PERR_MSK BIT(LPUART_RXDR_PERR_POS) - -#define LPUART_RXDR_RXDR_POSS 0U -#define LPUART_RXDR_RXDR_POSE 8U -#define LPUART_RXDR_RXDR_MSK BITS(LPUART_RXDR_RXDR_POSS,LPUART_RXDR_RXDR_POSE) - -/****************** Bit definition for LPUART_TXDR register ************************/ - -#define LPUART_TXDR_TXDR_POSS 0U -#define LPUART_TXDR_TXDR_POSE 8U -#define LPUART_TXDR_TXDR_MSK BITS(LPUART_TXDR_TXDR_POSS,LPUART_TXDR_TXDR_POSE) - -/****************** Bit definition for LPUART_STAT register ************************/ - -#define LPUART_STAT_RTSSTAT_POS 18U -#define LPUART_STAT_RTSSTAT_MSK BIT(LPUART_STAT_RTSSTAT_POS) - -#define LPUART_STAT_CTSSTAT_POS 17U -#define LPUART_STAT_CTSSTAT_MSK BIT(LPUART_STAT_CTSSTAT_POS) - -#define LPUART_STAT_TXIDLE_POS 16U -#define LPUART_STAT_TXIDLE_MSK BIT(LPUART_STAT_TXIDLE_POS) - -#define LPUART_STAT_TXFULL_POS 15U -#define LPUART_STAT_TXFULL_MSK BIT(LPUART_STAT_TXFULL_POS) - -#define LPUART_STAT_TXEMP_POS 14U -#define LPUART_STAT_TXEMP_MSK BIT(LPUART_STAT_TXEMP_POS) - -#define LPUART_STAT_TXPTR_POSS 8U -#define LPUART_STAT_TXPTR_POSE 13U -#define LPUART_STAT_TXPTR_MSK BITS(LPUART_STAT_TXPTR_POSS,LPUART_STAT_TXPTR_POSE) - -#define LPUART_STAT_RXFULL_POS 7U -#define LPUART_STAT_RXFULL_MSK BIT(LPUART_STAT_RXFULL_POS) - -#define LPUART_STAT_RXEMP_POS 6U -#define LPUART_STAT_RXEMP_MSK BIT(LPUART_STAT_RXEMP_POS) - -#define LPUART_STAT_RXPTR_POSS 0U -#define LPUART_STAT_RXPTR_POSE 5U -#define LPUART_STAT_RXPTR_MSK BITS(LPUART_STAT_RXPTR_POSS,LPUART_STAT_RXPTR_POSE) - -/****************** Bit definition for LPUART_IER register ************************/ - -#define LPUART_IER_TCIE_POS 15U -#define LPUART_IER_TCIE_MSK BIT(LPUART_IER_TCIE_POS) - -#define LPUART_IER_ADETIE_POS 12U -#define LPUART_IER_ADETIE_MSK BIT(LPUART_IER_ADETIE_POS) - -#define LPUART_IER_BRKERRIE_POS 11U -#define LPUART_IER_BRKERRIE_MSK BIT(LPUART_IER_BRKERRIE_POS) - -#define LPUART_IER_FERRIE_POS 10U -#define LPUART_IER_FERRIE_MSK BIT(LPUART_IER_FERRIE_POS) - -#define LPUART_IER_PERRIE_POS 9U -#define LPUART_IER_PERRIE_MSK BIT(LPUART_IER_PERRIE_POS) - -#define LPUART_IER_DATWKIE_POS 8U -#define LPUART_IER_DATWKIE_MSK BIT(LPUART_IER_DATWKIE_POS) - -#define LPUART_IER_CTSWKIE_POS 7U -#define LPUART_IER_CTSWKIE_MSK BIT(LPUART_IER_CTSWKIE_POS) - -#define LPUART_IER_TXOVIE_POS 5U -#define LPUART_IER_TXOVIE_MSK BIT(LPUART_IER_TXOVIE_POS) - -#define LPUART_IER_RXOVIE_POS 4U -#define LPUART_IER_RXOVIE_MSK BIT(LPUART_IER_RXOVIE_POS) - -#define LPUART_IER_RXTOIE_POS 3U -#define LPUART_IER_RXTOIE_MSK BIT(LPUART_IER_RXTOIE_POS) - -#define LPUART_IER_CTSDETIE_POS 2U -#define LPUART_IER_CTSDETIE_MSK BIT(LPUART_IER_CTSDETIE_POS) - -#define LPUART_IER_TBEMPIE_POS 1U -#define LPUART_IER_TBEMPIE_MSK BIT(LPUART_IER_TBEMPIE_POS) - -#define LPUART_IER_RBRIE_POS 0U -#define LPUART_IER_RBRIE_MSK BIT(LPUART_IER_RBRIE_POS) - -/****************** Bit definition for LPUART_IFLAG register ************************/ - -#define LPUART_IFLAG_TCIF_POS 15U -#define LPUART_IFLAG_TCIF_MSK BIT(LPUART_IFLAG_TCIF_POS) - -#define LPUART_IFLAG_ADETIF_POS 12U -#define LPUART_IFLAG_ADETIF_MSK BIT(LPUART_IFLAG_ADETIF_POS) - -#define LPUART_IFLAG_BRKERRIF_POS 11U -#define LPUART_IFLAG_BRKERRIF_MSK BIT(LPUART_IFLAG_BRKERRIF_POS) - -#define LPUART_IFLAG_FERRIF_POS 10U -#define LPUART_IFLAG_FERRIF_MSK BIT(LPUART_IFLAG_FERRIF_POS) - -#define LPUART_IFLAG_PERRIF_POS 9U -#define LPUART_IFLAG_PERRIF_MSK BIT(LPUART_IFLAG_PERRIF_POS) - -#define LPUART_IFLAG_DATWKIF_POS 8U -#define LPUART_IFLAG_DATWKIF_MSK BIT(LPUART_IFLAG_DATWKIF_POS) - -#define LPUART_IFLAG_CTSWKIF_POS 7U -#define LPUART_IFLAG_CTSWKIF_MSK BIT(LPUART_IFLAG_CTSWKIF_POS) - -#define LPUART_IFLAG_TXOVIF_POS 5U -#define LPUART_IFLAG_TXOVIF_MSK BIT(LPUART_IFLAG_TXOVIF_POS) - -#define LPUART_IFLAG_RXOVIF_POS 4U -#define LPUART_IFLAG_RXOVIF_MSK BIT(LPUART_IFLAG_RXOVIF_POS) - -#define LPUART_IFLAG_RXTOIF_POS 3U -#define LPUART_IFLAG_RXTOIF_MSK BIT(LPUART_IFLAG_RXTOIF_POS) - -#define LPUART_IFLAG_CTSDETIF_POS 2U -#define LPUART_IFLAG_CTSDETIF_MSK BIT(LPUART_IFLAG_CTSDETIF_POS) - -#define LPUART_IFLAG_TBEMPIF_POS 1U -#define LPUART_IFLAG_TBEMPIF_MSK BIT(LPUART_IFLAG_TBEMPIF_POS) - -#define LPUART_IFLAG_RBRIF_POS 0U -#define LPUART_IFLAG_RBRIF_MSK BIT(LPUART_IFLAG_RBRIF_POS) - -/****************** Bit definition for LPUART_IFC register ************************/ - -#define LPUART_IFC_TCIFC_POS 15U -#define LPUART_IFC_TCIFC_MSK BIT(LPUART_IFC_TCIFC_POS) - -#define LPUART_IFC_ADETIFC_POS 12U -#define LPUART_IFC_ADETIFC_MSK BIT(LPUART_IFC_ADETIFC_POS) - -#define LPUART_IFC_BRKERRIFC_POS 11U -#define LPUART_IFC_BRKERRIFC_MSK BIT(LPUART_IFC_BRKERRIFC_POS) - -#define LPUART_IFC_FERRIFC_POS 10U -#define LPUART_IFC_FERRIFC_MSK BIT(LPUART_IFC_FERRIFC_POS) - -#define LPUART_IFC_PERRIFC_POS 9U -#define LPUART_IFC_PERRIFC_MSK BIT(LPUART_IFC_PERRIFC_POS) - -#define LPUART_IFC_DATWKIFC_POS 8U -#define LPUART_IFC_DATWKIFC_MSK BIT(LPUART_IFC_DATWKIFC_POS) - -#define LPUART_IFC_CTSWKIFC_POS 7U -#define LPUART_IFC_CTSWKIFC_MSK BIT(LPUART_IFC_CTSWKIFC_POS) - -#define LPUART_IFC_TXOVIFC_POS 5U -#define LPUART_IFC_TXOVIFC_MSK BIT(LPUART_IFC_TXOVIFC_POS) - -#define LPUART_IFC_RXOVIFC_POS 4U -#define LPUART_IFC_RXOVIFC_MSK BIT(LPUART_IFC_RXOVIFC_POS) - -#define LPUART_IFC_CTSDETIFC_POS 2U -#define LPUART_IFC_CTSDETIFC_MSK BIT(LPUART_IFC_CTSDETIFC_POS) - -#define LPUART_IFC_TBEMPIFC_POS 1U -#define LPUART_IFC_TBEMPIFC_MSK BIT(LPUART_IFC_TBEMPIFC_POS) - -#define LPUART_IFC_RBRIFC_POS 0U -#define LPUART_IFC_RBRIFC_MSK BIT(LPUART_IFC_RBRIFC_POS) - -/****************** Bit definition for LPUART_ISTAT register ************************/ - -#define LPUART_ISTAT_TCINT_POS 15U -#define LPUART_ISTAT_TCINT_MSK BIT(LPUART_ISTAT_TCINT_POS) - -#define LPUART_ISTAT_RXSTATINT_POS 9U -#define LPUART_ISTAT_RXSTATINT_MSK BIT(LPUART_ISTAT_RXSTATINT_POS) - -#define LPUART_ISTAT_DATWKINT_POS 8U -#define LPUART_ISTAT_DATWKINT_MSK BIT(LPUART_ISTAT_DATWKINT_POS) - -#define LPUART_ISTAT_CTSWKINT_POS 7U -#define LPUART_ISTAT_CTSWKINT_MSK BIT(LPUART_ISTAT_CTSWKINT_POS) - -#define LPUART_ISTAT_BUFERRINT_POS 4U -#define LPUART_ISTAT_BUFERRINT_MSK BIT(LPUART_ISTAT_BUFERRINT_POS) - -#define LPUART_ISTAT_RXTOINT_POS 3U -#define LPUART_ISTAT_RXTOINT_MSK BIT(LPUART_ISTAT_RXTOINT_POS) - -#define LPUART_ISTAT_CTSDETINT_POS 2U -#define LPUART_ISTAT_CTSDETINT_MSK BIT(LPUART_ISTAT_CTSDETINT_POS) - -#define LPUART_ISTAT_TBEMPINT_POS 1U -#define LPUART_ISTAT_TBEMPINT_MSK BIT(LPUART_ISTAT_TBEMPINT_POS) - -#define LPUART_ISTAT_RBRINT_POS 0U -#define LPUART_ISTAT_RBRINT_MSK BIT(LPUART_ISTAT_RBRINT_POS) - -/****************** Bit definition for LPUART_UPDATE register ************************/ - -#define LPUART_UPDATE_UDIS_POS 0U -#define LPUART_UPDATE_UDIS_MSK BIT(LPUART_UPDATE_UDIS_POS) - -/****************** Bit definition for LPUART_SYNCSTAT register ************************/ - -#define LPUART_SYNCSTAT_FIFOCONWBSY_POS 3U -#define LPUART_SYNCSTAT_FIFOCONWBSY_MSK BIT(LPUART_SYNCSTAT_FIFOCONWBSY_POS) - -#define LPUART_SYNCSTAT_CLKDIVWBSY_POS 2U -#define LPUART_SYNCSTAT_CLKDIVWBSY_MSK BIT(LPUART_SYNCSTAT_CLKDIVWBSY_POS) - -#define LPUART_SYNCSTAT_CON1WBSY_POS 1U -#define LPUART_SYNCSTAT_CON1WBSY_MSK BIT(LPUART_SYNCSTAT_CON1WBSY_POS) - -#define LPUART_SYNCSTAT_CON0WBSY_POS 0U -#define LPUART_SYNCSTAT_CON0WBSY_MSK BIT(LPUART_SYNCSTAT_CON0WBSY_POS) - -typedef struct -{ - __IO uint32_t CON0; - __IO uint32_t CON1; - __IO uint32_t CLKDIV; - __IO uint32_t FIFOCON; - uint32_t RESERVED0 ; - __I uint32_t RXDR; - __O uint32_t TXDR; - __I uint32_t STAT; - __IO uint32_t IER; - __I uint32_t IFLAG; - __O uint32_t IFC; - __I uint32_t ISTAT; - uint32_t RESERVED1[2] ; - __IO uint32_t UPDATE; - __I uint32_t SYNCSTAT; -} LPUART_TypeDef; - -/****************** Bit definition for SPI_CON1 register ************************/ - -#define SPI_CON1_BIDEN_POS 15U -#define SPI_CON1_BIDEN_MSK BIT(SPI_CON1_BIDEN_POS) - -#define SPI_CON1_BIDOEN_POS 14U -#define SPI_CON1_BIDOEN_MSK BIT(SPI_CON1_BIDOEN_POS) - -#define SPI_CON1_CRCEN_POS 13U -#define SPI_CON1_CRCEN_MSK BIT(SPI_CON1_CRCEN_POS) - -#define SPI_CON1_NXTCRC_POS 12U -#define SPI_CON1_NXTCRC_MSK BIT(SPI_CON1_NXTCRC_POS) - -#define SPI_CON1_FLEN_POS 11U -#define SPI_CON1_FLEN_MSK BIT(SPI_CON1_FLEN_POS) - -#define SPI_CON1_RXO_POS 10U -#define SPI_CON1_RXO_MSK BIT(SPI_CON1_RXO_POS) - -#define SPI_CON1_SSEN_POS 9U -#define SPI_CON1_SSEN_MSK BIT(SPI_CON1_SSEN_POS) - -#define SPI_CON1_SSOUT_POS 8U -#define SPI_CON1_SSOUT_MSK BIT(SPI_CON1_SSOUT_POS) - -#define SPI_CON1_LSBFST_POS 7U -#define SPI_CON1_LSBFST_MSK BIT(SPI_CON1_LSBFST_POS) - -#define SPI_CON1_SPIEN_POS 6U -#define SPI_CON1_SPIEN_MSK BIT(SPI_CON1_SPIEN_POS) - -#define SPI_CON1_BAUD_POSS 3U -#define SPI_CON1_BAUD_POSE 5U -#define SPI_CON1_BAUD_MSK BITS(SPI_CON1_BAUD_POSS,SPI_CON1_BAUD_POSE) - -#define SPI_CON1_MSTREN_POS 2U -#define SPI_CON1_MSTREN_MSK BIT(SPI_CON1_MSTREN_POS) - -#define SPI_CON1_CPOL_POS 1U -#define SPI_CON1_CPOL_MSK BIT(SPI_CON1_CPOL_POS) - -#define SPI_CON1_CPHA_POS 0U -#define SPI_CON1_CPHA_MSK BIT(SPI_CON1_CPHA_POS) - -/****************** Bit definition for SPI_CON2 register ************************/ - -#define SPI_CON2_TXBEIE_POS 7U -#define SPI_CON2_TXBEIE_MSK BIT(SPI_CON2_TXBEIE_POS) - -#define SPI_CON2_RXBNEIE_POS 6U -#define SPI_CON2_RXBNEIE_MSK BIT(SPI_CON2_RXBNEIE_POS) - -#define SPI_CON2_ERRIE_POS 5U -#define SPI_CON2_ERRIE_MSK BIT(SPI_CON2_ERRIE_POS) - -#define SPI_CON2_NSSOE_POS 2U -#define SPI_CON2_NSSOE_MSK BIT(SPI_CON2_NSSOE_POS) - -#define SPI_CON2_TXDMA_POS 1U -#define SPI_CON2_TXDMA_MSK BIT(SPI_CON2_TXDMA_POS) - -#define SPI_CON2_RXDMA_POS 0U -#define SPI_CON2_RXDMA_MSK BIT(SPI_CON2_RXDMA_POS) - -/****************** Bit definition for SPI_STAT register ************************/ - -#define SPI_STAT_BUSY_POS 7U -#define SPI_STAT_BUSY_MSK BIT(SPI_STAT_BUSY_POS) - -#define SPI_STAT_OVERR_POS 6U -#define SPI_STAT_OVERR_MSK BIT(SPI_STAT_OVERR_POS) - -#define SPI_STAT_MODERR_POS 5U -#define SPI_STAT_MODERR_MSK BIT(SPI_STAT_MODERR_POS) - -#define SPI_STAT_CRCERR_POS 4U -#define SPI_STAT_CRCERR_MSK BIT(SPI_STAT_CRCERR_POS) - -#define SPI_STAT_TXBE_POS 1U -#define SPI_STAT_TXBE_MSK BIT(SPI_STAT_TXBE_POS) - -#define SPI_STAT_RXBNE_POS 0U -#define SPI_STAT_RXBNE_MSK BIT(SPI_STAT_RXBNE_POS) - -/****************** Bit definition for SPI_DATA register ************************/ - -#define SPI_DATA_VALUE_POSS 0U -#define SPI_DATA_VALUE_POSE 15U -#define SPI_DATA_VALUE_MSK BITS(SPI_DATA_VALUE_POSS,SPI_DATA_VALUE_POSE) - -/****************** Bit definition for SPI_CRCPOLY register ************************/ - -#define SPI_CRCPOLY_VALUE_POSS 0U -#define SPI_CRCPOLY_VALUE_POSE 15U -#define SPI_CRCPOLY_VALUE_MSK BITS(SPI_CRCPOLY_VALUE_POSS,SPI_CRCPOLY_VALUE_POSE) - -/****************** Bit definition for SPI_RXCRC register ************************/ - -#define SPI_RXCRC_CRCVAL_POSS 0U -#define SPI_RXCRC_CRCVAL_POSE 15U -#define SPI_RXCRC_CRCVAL_MSK BITS(SPI_RXCRC_CRCVAL_POSS,SPI_RXCRC_CRCVAL_POSE) - -/****************** Bit definition for SPI_TXCRC register ************************/ - -#define SPI_TXCRC_CRCVAL_POSS 0U -#define SPI_TXCRC_CRCVAL_POSE 15U -#define SPI_TXCRC_CRCVAL_MSK BITS(SPI_TXCRC_CRCVAL_POSS,SPI_TXCRC_CRCVAL_POSE) - -typedef struct -{ - __IO uint32_t CON1; - __IO uint32_t CON2; - __IO uint32_t STAT; - __IO uint32_t DATA; - __IO uint32_t CRCPOLY; - __I uint32_t RXCRC; - __I uint32_t TXCRC; -} SPI_TypeDef; - -/****************** Bit definition for I2C_CON1 register ************************/ - -#define I2C_CON1_SRST_POS 15U -#define I2C_CON1_SRST_MSK BIT(I2C_CON1_SRST_POS) - -#define I2C_CON1_ALARM_POS 13U -#define I2C_CON1_ALARM_MSK BIT(I2C_CON1_ALARM_POS) - -#define I2C_CON1_TRPEC_POS 12U -#define I2C_CON1_TRPEC_MSK BIT(I2C_CON1_TRPEC_POS) - -#define I2C_CON1_POSAP_POS 11U -#define I2C_CON1_POSAP_MSK BIT(I2C_CON1_POSAP_POS) - -#define I2C_CON1_ACKEN_POS 10U -#define I2C_CON1_ACKEN_MSK BIT(I2C_CON1_ACKEN_POS) - -#define I2C_CON1_STOP_POS 9U -#define I2C_CON1_STOP_MSK BIT(I2C_CON1_STOP_POS) - -#define I2C_CON1_START_POS 8U -#define I2C_CON1_START_MSK BIT(I2C_CON1_START_POS) - -#define I2C_CON1_DISCS_POS 7U -#define I2C_CON1_DISCS_MSK BIT(I2C_CON1_DISCS_POS) - -#define I2C_CON1_GCEN_POS 6U -#define I2C_CON1_GCEN_MSK BIT(I2C_CON1_GCEN_POS) - -#define I2C_CON1_PECEN_POS 5U -#define I2C_CON1_PECEN_MSK BIT(I2C_CON1_PECEN_POS) - -#define I2C_CON1_ARPEN_POS 4U -#define I2C_CON1_ARPEN_MSK BIT(I2C_CON1_ARPEN_POS) - -#define I2C_CON1_SMBMOD_POS 3U -#define I2C_CON1_SMBMOD_MSK BIT(I2C_CON1_SMBMOD_POS) - -#define I2C_CON1_PMOD_POS 1U -#define I2C_CON1_PMOD_MSK BIT(I2C_CON1_PMOD_POS) - -#define I2C_CON1_PEN_POS 0U -#define I2C_CON1_PEN_MSK BIT(I2C_CON1_PEN_POS) - -/****************** Bit definition for I2C_CON2 register ************************/ - -#define I2C_CON2_LDMA_POS 12U -#define I2C_CON2_LDMA_MSK BIT(I2C_CON2_LDMA_POS) - -#define I2C_CON2_DMAEN_POS 11U -#define I2C_CON2_DMAEN_MSK BIT(I2C_CON2_DMAEN_POS) - -#define I2C_CON2_BUFIE_POS 10U -#define I2C_CON2_BUFIE_MSK BIT(I2C_CON2_BUFIE_POS) - -#define I2C_CON2_EVTIE_POS 9U -#define I2C_CON2_EVTIE_MSK BIT(I2C_CON2_EVTIE_POS) - -#define I2C_CON2_ERRIE_POS 8U -#define I2C_CON2_ERRIE_MSK BIT(I2C_CON2_ERRIE_POS) - -#define I2C_CON2_CLKF_POSS 0U -#define I2C_CON2_CLKF_POSE 5U -#define I2C_CON2_CLKF_MSK BITS(I2C_CON2_CLKF_POSS,I2C_CON2_CLKF_POSE) - -/****************** Bit definition for I2C_ADDR1 register ************************/ - -#define I2C_ADDR1_ADDTYPE_POS 15U -#define I2C_ADDR1_ADDTYPE_MSK BIT(I2C_ADDR1_ADDTYPE_POS) - -#define I2C_ADDR1_ADDH_POSS 8U -#define I2C_ADDR1_ADDH_POSE 9U -#define I2C_ADDR1_ADDH_MSK BITS(I2C_ADDR1_ADDH_POSS,I2C_ADDR1_ADDH_POSE) - -#define I2C_ADDR1_ADD_POSS 1U -#define I2C_ADDR1_ADD_POSE 7U -#define I2C_ADDR1_ADD_MSK BITS(I2C_ADDR1_ADD_POSS,I2C_ADDR1_ADD_POSE) - -#define I2C_ADDR1_ADDLSB_POS 0U -#define I2C_ADDR1_ADDLSB_MSK BIT(I2C_ADDR1_ADDLSB_POS) - -/****************** Bit definition for I2C_ADDR2 register ************************/ - -#define I2C_ADDR2_ADD_POSS 1U -#define I2C_ADDR2_ADD_POSE 7U -#define I2C_ADDR2_ADD_MSK BITS(I2C_ADDR2_ADD_POSS,I2C_ADDR2_ADD_POSE) - -#define I2C_ADDR2_DUALEN_POS 0U -#define I2C_ADDR2_DUALEN_MSK BIT(I2C_ADDR2_DUALEN_POS) - -/****************** Bit definition for I2C_DATA register ************************/ - -#define I2C_DATA_TRBUF_POSS 0U -#define I2C_DATA_TRBUF_POSE 7U -#define I2C_DATA_TRBUF_MSK BITS(I2C_DATA_TRBUF_POSS,I2C_DATA_TRBUF_POSE) - -/****************** Bit definition for I2C_STAT1 register ************************/ - -#define I2C_STAT1_SMBALARM_POS 15U -#define I2C_STAT1_SMBALARM_MSK BIT(I2C_STAT1_SMBALARM_POS) - -#define I2C_STAT1_SMBTO_POS 14U -#define I2C_STAT1_SMBTO_MSK BIT(I2C_STAT1_SMBTO_POS) - -#define I2C_STAT1_PECERR_POS 12U -#define I2C_STAT1_PECERR_MSK BIT(I2C_STAT1_PECERR_POS) - -#define I2C_STAT1_ROUERR_POS 11U -#define I2C_STAT1_ROUERR_MSK BIT(I2C_STAT1_ROUERR_POS) - -#define I2C_STAT1_ACKERR_POS 10U -#define I2C_STAT1_ACKERR_MSK BIT(I2C_STAT1_ACKERR_POS) - -#define I2C_STAT1_LARB_POS 9U -#define I2C_STAT1_LARB_MSK BIT(I2C_STAT1_LARB_POS) - -#define I2C_STAT1_BUSERR_POS 8U -#define I2C_STAT1_BUSERR_MSK BIT(I2C_STAT1_BUSERR_POS) - -#define I2C_STAT1_TXBE_POS 7U -#define I2C_STAT1_TXBE_MSK BIT(I2C_STAT1_TXBE_POS) - -#define I2C_STAT1_RXBNE_POS 6U -#define I2C_STAT1_RXBNE_MSK BIT(I2C_STAT1_RXBNE_POS) - -#define I2C_STAT1_DETSTP_POS 4U -#define I2C_STAT1_DETSTP_MSK BIT(I2C_STAT1_DETSTP_POS) - -#define I2C_STAT1_SENDADD10_POS 3U -#define I2C_STAT1_SENDADD10_MSK BIT(I2C_STAT1_SENDADD10_POS) - -#define I2C_STAT1_BTC_POS 2U -#define I2C_STAT1_BTC_MSK BIT(I2C_STAT1_BTC_POS) - -#define I2C_STAT1_ADDR_POS 1U -#define I2C_STAT1_ADDR_MSK BIT(I2C_STAT1_ADDR_POS) - -#define I2C_STAT1_SENDSTR_POS 0U -#define I2C_STAT1_SENDSTR_MSK BIT(I2C_STAT1_SENDSTR_POS) - -/****************** Bit definition for I2C_STAT2 register ************************/ - -#define I2C_STAT2_PECV_POSS 8U -#define I2C_STAT2_PECV_POSE 15U -#define I2C_STAT2_PECV_MSK BITS(I2C_STAT2_PECV_POSS,I2C_STAT2_PECV_POSE) - -#define I2C_STAT2_DMF_POS 7U -#define I2C_STAT2_DMF_MSK BIT(I2C_STAT2_DMF_POS) - -#define I2C_STAT2_SMBHH_POS 6U -#define I2C_STAT2_SMBHH_MSK BIT(I2C_STAT2_SMBHH_POS) - -#define I2C_STAT2_SMBDEF_POS 5U -#define I2C_STAT2_SMBDEF_MSK BIT(I2C_STAT2_SMBDEF_POS) - -#define I2C_STAT2_RXGCF_POS 4U -#define I2C_STAT2_RXGCF_MSK BIT(I2C_STAT2_RXGCF_POS) - -#define I2C_STAT2_TRF_POS 2U -#define I2C_STAT2_TRF_MSK BIT(I2C_STAT2_TRF_POS) - -#define I2C_STAT2_BSYF_POS 1U -#define I2C_STAT2_BSYF_MSK BIT(I2C_STAT2_BSYF_POS) - -#define I2C_STAT2_MASTER_POS 0U -#define I2C_STAT2_MASTER_MSK BIT(I2C_STAT2_MASTER_POS) - -/****************** Bit definition for I2C_CKCFG register ************************/ - -#define I2C_CKCFG_CLKMOD_POS 15U -#define I2C_CKCFG_CLKMOD_MSK BIT(I2C_CKCFG_CLKMOD_POS) - -#define I2C_CKCFG_DUTY_POS 14U -#define I2C_CKCFG_DUTY_MSK BIT(I2C_CKCFG_DUTY_POS) - -#define I2C_CKCFG_CLKSET_POSS 0U -#define I2C_CKCFG_CLKSET_POSE 11U -#define I2C_CKCFG_CLKSET_MSK BITS(I2C_CKCFG_CLKSET_POSS,I2C_CKCFG_CLKSET_POSE) - -/****************** Bit definition for I2C_RT register ************************/ - -#define I2C_RT_RISET_POSS 0U -#define I2C_RT_RISET_POSE 5U -#define I2C_RT_RISET_MSK BITS(I2C_RT_RISET_POSS,I2C_RT_RISET_POSE) - -typedef struct -{ - __IO uint32_t CON1; - __IO uint32_t CON2; - __IO uint32_t ADDR1; - __IO uint32_t ADDR2; - __IO uint32_t DATA; - __IO uint32_t STAT1; - __I uint32_t STAT2; - __IO uint32_t CKCFG; - __IO uint32_t RT; -} I2C_TypeDef; - -/****************** Bit definition for CAN_CON register ************************/ - -#define CAN_CON_DBGSTP_POS 16U -#define CAN_CON_DBGSTP_MSK BIT(CAN_CON_DBGSTP_POS) - -#define CAN_CON_RST_POS 15U -#define CAN_CON_RST_MSK BIT(CAN_CON_RST_POS) - -#define CAN_CON_TTCEN_POS 7U -#define CAN_CON_TTCEN_MSK BIT(CAN_CON_TTCEN_POS) - -#define CAN_CON_ABOFFEN_POS 6U -#define CAN_CON_ABOFFEN_MSK BIT(CAN_CON_ABOFFEN_POS) - -#define CAN_CON_AWKEN_POS 5U -#define CAN_CON_AWKEN_MSK BIT(CAN_CON_AWKEN_POS) - -#define CAN_CON_ARTXDIS_POS 4U -#define CAN_CON_ARTXDIS_MSK BIT(CAN_CON_ARTXDIS_POS) - -#define CAN_CON_RXFOPM_POS 3U -#define CAN_CON_RXFOPM_MSK BIT(CAN_CON_RXFOPM_POS) - -#define CAN_CON_TXMP_POS 2U -#define CAN_CON_TXMP_MSK BIT(CAN_CON_TXMP_POS) - -#define CAN_CON_SLPREQ_POS 1U -#define CAN_CON_SLPREQ_MSK BIT(CAN_CON_SLPREQ_POS) - -#define CAN_CON_INIREQ_POS 0U -#define CAN_CON_INIREQ_MSK BIT(CAN_CON_INIREQ_POS) - -/****************** Bit definition for CAN_STAT register ************************/ - -#define CAN_STAT_RX_POS 11U -#define CAN_STAT_RX_MSK BIT(CAN_STAT_RX_POS) - -#define CAN_STAT_PRESMP_POS 10U -#define CAN_STAT_PRESMP_MSK BIT(CAN_STAT_PRESMP_POS) - -#define CAN_STAT_RXSTAT_POS 9U -#define CAN_STAT_RXSTAT_MSK BIT(CAN_STAT_RXSTAT_POS) - -#define CAN_STAT_TXSTAT_POS 8U -#define CAN_STAT_TXSTAT_MSK BIT(CAN_STAT_TXSTAT_POS) - -#define CAN_STAT_SLPIF_POS 4U -#define CAN_STAT_SLPIF_MSK BIT(CAN_STAT_SLPIF_POS) - -#define CAN_STAT_WKIF_POS 3U -#define CAN_STAT_WKIF_MSK BIT(CAN_STAT_WKIF_POS) - -#define CAN_STAT_ERRIF_POS 2U -#define CAN_STAT_ERRIF_MSK BIT(CAN_STAT_ERRIF_POS) - -#define CAN_STAT_SLPSTAT_POS 1U -#define CAN_STAT_SLPSTAT_MSK BIT(CAN_STAT_SLPSTAT_POS) - -#define CAN_STAT_INISTAT_POS 0U -#define CAN_STAT_INISTAT_MSK BIT(CAN_STAT_INISTAT_POS) - -/****************** Bit definition for CAN_IFC register ************************/ - -#define CAN_IFC_SLPIFC_POS 4U -#define CAN_IFC_SLPIFC_MSK BIT(CAN_IFC_SLPIFC_POS) - -#define CAN_IFC_WKIFC_POS 3U -#define CAN_IFC_WKIFC_MSK BIT(CAN_IFC_WKIFC_POS) - -#define CAN_IFC_ERRIFC_POS 2U -#define CAN_IFC_ERRIFC_MSK BIT(CAN_IFC_ERRIFC_POS) - -/****************** Bit definition for CAN_TXSTAT register ************************/ - -#define CAN_TXSTAT_TXM2LPF_POS 31U -#define CAN_TXSTAT_TXM2LPF_MSK BIT(CAN_TXSTAT_TXM2LPF_POS) - -#define CAN_TXSTAT_TXM1LPF_POS 30U -#define CAN_TXSTAT_TXM1LPF_MSK BIT(CAN_TXSTAT_TXM1LPF_POS) - -#define CAN_TXSTAT_TXM0LPF_POS 29U -#define CAN_TXSTAT_TXM0LPF_MSK BIT(CAN_TXSTAT_TXM0LPF_POS) - -#define CAN_TXSTAT_TXM2EF_POS 28U -#define CAN_TXSTAT_TXM2EF_MSK BIT(CAN_TXSTAT_TXM2EF_POS) - -#define CAN_TXSTAT_TXM1EF_POS 27U -#define CAN_TXSTAT_TXM1EF_MSK BIT(CAN_TXSTAT_TXM1EF_POS) - -#define CAN_TXSTAT_TXM0EF_POS 26U -#define CAN_TXSTAT_TXM0EF_MSK BIT(CAN_TXSTAT_TXM0EF_POS) - -#define CAN_TXSTAT_CODE_POSS 24U -#define CAN_TXSTAT_CODE_POSE 25U -#define CAN_TXSTAT_CODE_MSK BITS(CAN_TXSTAT_CODE_POSS,CAN_TXSTAT_CODE_POSE) - -#define CAN_TXSTAT_M2STPREQ_POS 23U -#define CAN_TXSTAT_M2STPREQ_MSK BIT(CAN_TXSTAT_M2STPREQ_POS) - -#define CAN_TXSTAT_M2TXERR_POS 19U -#define CAN_TXSTAT_M2TXERR_MSK BIT(CAN_TXSTAT_M2TXERR_POS) - -#define CAN_TXSTAT_M2ARBLST_POS 18U -#define CAN_TXSTAT_M2ARBLST_MSK BIT(CAN_TXSTAT_M2ARBLST_POS) - -#define CAN_TXSTAT_M2TXC_POS 17U -#define CAN_TXSTAT_M2TXC_MSK BIT(CAN_TXSTAT_M2TXC_POS) - -#define CAN_TXSTAT_M2REQC_POS 16U -#define CAN_TXSTAT_M2REQC_MSK BIT(CAN_TXSTAT_M2REQC_POS) - -#define CAN_TXSTAT_M1STPREQ_POS 15U -#define CAN_TXSTAT_M1STPREQ_MSK BIT(CAN_TXSTAT_M1STPREQ_POS) - -#define CAN_TXSTAT_M1TXERR_POS 11U -#define CAN_TXSTAT_M1TXERR_MSK BIT(CAN_TXSTAT_M1TXERR_POS) - -#define CAN_TXSTAT_M1ARBLST_POS 10U -#define CAN_TXSTAT_M1ARBLST_MSK BIT(CAN_TXSTAT_M1ARBLST_POS) - -#define CAN_TXSTAT_M1TXC_POS 9U -#define CAN_TXSTAT_M1TXC_MSK BIT(CAN_TXSTAT_M1TXC_POS) - -#define CAN_TXSTAT_M1REQC_POS 8U -#define CAN_TXSTAT_M1REQC_MSK BIT(CAN_TXSTAT_M1REQC_POS) - -#define CAN_TXSTAT_M0STPREQ_POS 7U -#define CAN_TXSTAT_M0STPREQ_MSK BIT(CAN_TXSTAT_M0STPREQ_POS) - -#define CAN_TXSTAT_M0TXERR_POS 3U -#define CAN_TXSTAT_M0TXERR_MSK BIT(CAN_TXSTAT_M0TXERR_POS) - -#define CAN_TXSTAT_M0ARBLST_POS 2U -#define CAN_TXSTAT_M0ARBLST_MSK BIT(CAN_TXSTAT_M0ARBLST_POS) - -#define CAN_TXSTAT_M0TXC_POS 1U -#define CAN_TXSTAT_M0TXC_MSK BIT(CAN_TXSTAT_M0TXC_POS) - -#define CAN_TXSTAT_M0REQC_POS 0U -#define CAN_TXSTAT_M0REQC_MSK BIT(CAN_TXSTAT_M0REQC_POS) - -/****************** Bit definition for CAN_TXSTATC register ************************/ - -#define CAN_TXSTATC_M2TXERR_POS 19U -#define CAN_TXSTATC_M2TXERR_MSK BIT(CAN_TXSTATC_M2TXERR_POS) - -#define CAN_TXSTATC_M2ARBLST_POS 18U -#define CAN_TXSTATC_M2ARBLST_MSK BIT(CAN_TXSTATC_M2ARBLST_POS) - -#define CAN_TXSTATC_M2TXC_POS 17U -#define CAN_TXSTATC_M2TXC_MSK BIT(CAN_TXSTATC_M2TXC_POS) - -#define CAN_TXSTATC_M2REQC_POS 16U -#define CAN_TXSTATC_M2REQC_MSK BIT(CAN_TXSTATC_M2REQC_POS) - -#define CAN_TXSTATC_M1TXERR_POS 11U -#define CAN_TXSTATC_M1TXERR_MSK BIT(CAN_TXSTATC_M1TXERR_POS) - -#define CAN_TXSTATC_M1ARBLST_POS 10U -#define CAN_TXSTATC_M1ARBLST_MSK BIT(CAN_TXSTATC_M1ARBLST_POS) - -#define CAN_TXSTATC_M1TXC_POS 9U -#define CAN_TXSTATC_M1TXC_MSK BIT(CAN_TXSTATC_M1TXC_POS) - -#define CAN_TXSTATC_M1REQC_POS 8U -#define CAN_TXSTATC_M1REQC_MSK BIT(CAN_TXSTATC_M1REQC_POS) - -#define CAN_TXSTATC_M0TXERR_POS 3U -#define CAN_TXSTATC_M0TXERR_MSK BIT(CAN_TXSTATC_M0TXERR_POS) - -#define CAN_TXSTATC_M0ARBLST_POS 2U -#define CAN_TXSTATC_M0ARBLST_MSK BIT(CAN_TXSTATC_M0ARBLST_POS) - -#define CAN_TXSTATC_M0TXC_POS 1U -#define CAN_TXSTATC_M0TXC_MSK BIT(CAN_TXSTATC_M0TXC_POS) - -#define CAN_TXSTATC_M0REQC_POS 0U -#define CAN_TXSTATC_M0REQC_MSK BIT(CAN_TXSTATC_M0REQC_POS) - -/****************** Bit definition for CAN_RXF0 register ************************/ - -#define CAN_RXF0_FREE_POS 5U -#define CAN_RXF0_FREE_MSK BIT(CAN_RXF0_FREE_POS) - -#define CAN_RXF0_OVR_POS 4U -#define CAN_RXF0_OVR_MSK BIT(CAN_RXF0_OVR_POS) - -#define CAN_RXF0_FULL_POS 3U -#define CAN_RXF0_FULL_MSK BIT(CAN_RXF0_FULL_POS) - -#define CAN_RXF0_PEND_POSS 0U -#define CAN_RXF0_PEND_POSE 1U -#define CAN_RXF0_PEND_MSK BITS(CAN_RXF0_PEND_POSS,CAN_RXF0_PEND_POSE) - -/****************** Bit definition for CAN_RXF0C register ************************/ - -#define CAN_RXF0C_OVRC_POS 4U -#define CAN_RXF0C_OVRC_MSK BIT(CAN_RXF0C_OVRC_POS) - -#define CAN_RXF0C_FULLC_POS 3U -#define CAN_RXF0C_FULLC_MSK BIT(CAN_RXF0C_FULLC_POS) - -/****************** Bit definition for CAN_RXF1 register ************************/ - -#define CAN_RXF1_FREE_POS 5U -#define CAN_RXF1_FREE_MSK BIT(CAN_RXF1_FREE_POS) - -#define CAN_RXF1_OVR_POS 4U -#define CAN_RXF1_OVR_MSK BIT(CAN_RXF1_OVR_POS) - -#define CAN_RXF1_FULL_POS 3U -#define CAN_RXF1_FULL_MSK BIT(CAN_RXF1_FULL_POS) - -#define CAN_RXF1_PEND_POSS 0U -#define CAN_RXF1_PEND_POSE 1U -#define CAN_RXF1_PEND_MSK BITS(CAN_RXF1_PEND_POSS,CAN_RXF1_PEND_POSE) - -/****************** Bit definition for CAN_RXF1C register ************************/ - -#define CAN_RXF1C_OVRC_POS 4U -#define CAN_RXF1C_OVRC_MSK BIT(CAN_RXF1C_OVRC_POS) - -#define CAN_RXF1C_FULLC_POS 3U -#define CAN_RXF1C_FULLC_MSK BIT(CAN_RXF1C_FULLC_POS) - -/****************** Bit definition for CAN_IE register ************************/ - -#define CAN_IE_SLPIE_POS 17U -#define CAN_IE_SLPIE_MSK BIT(CAN_IE_SLPIE_POS) - -#define CAN_IE_WKIE_POS 16U -#define CAN_IE_WKIE_MSK BIT(CAN_IE_WKIE_POS) - -#define CAN_IE_ERRIE_POS 15U -#define CAN_IE_ERRIE_MSK BIT(CAN_IE_ERRIE_POS) - -#define CAN_IE_PRERRIE_POS 11U -#define CAN_IE_PRERRIE_MSK BIT(CAN_IE_PRERRIE_POS) - -#define CAN_IE_BOFFIE_POS 10U -#define CAN_IE_BOFFIE_MSK BIT(CAN_IE_BOFFIE_POS) - -#define CAN_IE_PERRIE_POS 9U -#define CAN_IE_PERRIE_MSK BIT(CAN_IE_PERRIE_POS) - -#define CAN_IE_WARNIE_POS 8U -#define CAN_IE_WARNIE_MSK BIT(CAN_IE_WARNIE_POS) - -#define CAN_IE_F1OVRIE_POS 6U -#define CAN_IE_F1OVRIE_MSK BIT(CAN_IE_F1OVRIE_POS) - -#define CAN_IE_F1FULIE_POS 5U -#define CAN_IE_F1FULIE_MSK BIT(CAN_IE_F1FULIE_POS) - -#define CAN_IE_F1PIE_POS 4U -#define CAN_IE_F1PIE_MSK BIT(CAN_IE_F1PIE_POS) - -#define CAN_IE_F0OVRIE_POS 3U -#define CAN_IE_F0OVRIE_MSK BIT(CAN_IE_F0OVRIE_POS) - -#define CAN_IE_F0FULIE_POS 2U -#define CAN_IE_F0FULIE_MSK BIT(CAN_IE_F0FULIE_POS) - -#define CAN_IE_F0PIE_POS 1U -#define CAN_IE_F0PIE_MSK BIT(CAN_IE_F0PIE_POS) - -#define CAN_IE_TXMEIE_POS 0U -#define CAN_IE_TXMEIE_MSK BIT(CAN_IE_TXMEIE_POS) - -/****************** Bit definition for CAN_ERRSTAT register ************************/ - -#define CAN_ERRSTAT_RXERRC_POSS 24U -#define CAN_ERRSTAT_RXERRC_POSE 31U -#define CAN_ERRSTAT_RXERRC_MSK BITS(CAN_ERRSTAT_RXERRC_POSS,CAN_ERRSTAT_RXERRC_POSE) - -#define CAN_ERRSTAT_TXERRC_POSS 16U -#define CAN_ERRSTAT_TXERRC_POSE 23U -#define CAN_ERRSTAT_TXERRC_MSK BITS(CAN_ERRSTAT_TXERRC_POSS,CAN_ERRSTAT_TXERRC_POSE) - -#define CAN_ERRSTAT_PRERRF_POSS 4U -#define CAN_ERRSTAT_PRERRF_POSE 6U -#define CAN_ERRSTAT_PRERRF_MSK BITS(CAN_ERRSTAT_PRERRF_POSS,CAN_ERRSTAT_PRERRF_POSE) - -#define CAN_ERRSTAT_BOFF_POS 2U -#define CAN_ERRSTAT_BOFF_MSK BIT(CAN_ERRSTAT_BOFF_POS) - -#define CAN_ERRSTAT_PERRF_POS 1U -#define CAN_ERRSTAT_PERRF_MSK BIT(CAN_ERRSTAT_PERRF_POS) - -#define CAN_ERRSTAT_WARNF_POS 0U -#define CAN_ERRSTAT_WARNF_MSK BIT(CAN_ERRSTAT_WARNF_POS) - -/****************** Bit definition for CAN_BTIME register ************************/ - -#define CAN_BTIME_SILENT_POS 31U -#define CAN_BTIME_SILENT_MSK BIT(CAN_BTIME_SILENT_POS) - -#define CAN_BTIME_LOOP_POS 30U -#define CAN_BTIME_LOOP_MSK BIT(CAN_BTIME_LOOP_POS) - -#define CAN_BTIME_RESJW_POSS 24U -#define CAN_BTIME_RESJW_POSE 25U -#define CAN_BTIME_RESJW_MSK BITS(CAN_BTIME_RESJW_POSS,CAN_BTIME_RESJW_POSE) - -#define CAN_BTIME_SEG2_POSS 20U -#define CAN_BTIME_SEG2_POSE 22U -#define CAN_BTIME_SEG2_MSK BITS(CAN_BTIME_SEG2_POSS,CAN_BTIME_SEG2_POSE) - -#define CAN_BTIME_SEG1_POSS 16U -#define CAN_BTIME_SEG1_POSE 19U -#define CAN_BTIME_SEG1_MSK BITS(CAN_BTIME_SEG1_POSS,CAN_BTIME_SEG1_POSE) - -#define CAN_BTIME_BPSC_POSS 0U -#define CAN_BTIME_BPSC_POSE 9U -#define CAN_BTIME_BPSC_MSK BITS(CAN_BTIME_BPSC_POSS,CAN_BTIME_BPSC_POSE) - -/****************** Bit definition for CAN_TXID0 register ************************/ - -#define CAN_TXID0_STDID_POSS 21U -#define CAN_TXID0_STDID_POSE 31U -#define CAN_TXID0_STDID_MSK BITS(CAN_TXID0_STDID_POSS,CAN_TXID0_STDID_POSE) - -#define CAN_TXID0_EXID_POSS 3U -#define CAN_TXID0_EXID_POSE 20U -#define CAN_TXID0_EXID_MSK BITS(CAN_TXID0_EXID_POSS,CAN_TXID0_EXID_POSE) - -#define CAN_TXID0_IDE_POS 2U -#define CAN_TXID0_IDE_MSK BIT(CAN_TXID0_IDE_POS) - -#define CAN_TXID0_RTR_POS 1U -#define CAN_TXID0_RTR_MSK BIT(CAN_TXID0_RTR_POS) - -#define CAN_TXID0_TXMREQ_POS 0U -#define CAN_TXID0_TXMREQ_MSK BIT(CAN_TXID0_TXMREQ_POS) - -/****************** Bit definition for CAN_TXFCON0 register ************************/ - -#define CAN_TXFCON0_STAMP_POSS 16U -#define CAN_TXFCON0_STAMP_POSE 31U -#define CAN_TXFCON0_STAMP_MSK BITS(CAN_TXFCON0_STAMP_POSS,CAN_TXFCON0_STAMP_POSE) - -#define CAN_TXFCON0_TXGT_POS 8U -#define CAN_TXFCON0_TXGT_MSK BIT(CAN_TXFCON0_TXGT_POS) - -#define CAN_TXFCON0_DLEN_POSS 0U -#define CAN_TXFCON0_DLEN_POSE 3U -#define CAN_TXFCON0_DLEN_MSK BITS(CAN_TXFCON0_DLEN_POSS,CAN_TXFCON0_DLEN_POSE) - -/****************** Bit definition for CAN_TXDL0 register ************************/ - -#define CAN_TXDL0_BYTE3_POSS 24U -#define CAN_TXDL0_BYTE3_POSE 31U -#define CAN_TXDL0_BYTE3_MSK BITS(CAN_TXDL0_BYTE3_POSS,CAN_TXDL0_BYTE3_POSE) - -#define CAN_TXDL0_BYTE2_POSS 16U -#define CAN_TXDL0_BYTE2_POSE 23U -#define CAN_TXDL0_BYTE2_MSK BITS(CAN_TXDL0_BYTE2_POSS,CAN_TXDL0_BYTE2_POSE) - -#define CAN_TXDL0_BYTE1_POSS 8U -#define CAN_TXDL0_BYTE1_POSE 15U -#define CAN_TXDL0_BYTE1_MSK BITS(CAN_TXDL0_BYTE1_POSS,CAN_TXDL0_BYTE1_POSE) - -#define CAN_TXDL0_BYTE0_POSS 0U -#define CAN_TXDL0_BYTE0_POSE 7U -#define CAN_TXDL0_BYTE0_MSK BITS(CAN_TXDL0_BYTE0_POSS,CAN_TXDL0_BYTE0_POSE) - -/****************** Bit definition for CAN_TXDH0 register ************************/ - -#define CAN_TXDH0_BYTE7_POSS 24U -#define CAN_TXDH0_BYTE7_POSE 31U -#define CAN_TXDH0_BYTE7_MSK BITS(CAN_TXDH0_BYTE7_POSS,CAN_TXDH0_BYTE7_POSE) - -#define CAN_TXDH0_BYTE6_POSS 16U -#define CAN_TXDH0_BYTE6_POSE 23U -#define CAN_TXDH0_BYTE6_MSK BITS(CAN_TXDH0_BYTE6_POSS,CAN_TXDH0_BYTE6_POSE) - -#define CAN_TXDH0_BYTE5_POSS 8U -#define CAN_TXDH0_BYTE5_POSE 15U -#define CAN_TXDH0_BYTE5_MSK BITS(CAN_TXDH0_BYTE5_POSS,CAN_TXDH0_BYTE5_POSE) - -#define CAN_TXDH0_BYTE4_POSS 0U -#define CAN_TXDH0_BYTE4_POSE 7U -#define CAN_TXDH0_BYTE4_MSK BITS(CAN_TXDH0_BYTE4_POSS,CAN_TXDH0_BYTE4_POSE) - -/****************** Bit definition for CAN_TXID1 register ************************/ - -#define CAN_TXID1_STDID_POSS 21U -#define CAN_TXID1_STDID_POSE 31U -#define CAN_TXID1_STDID_MSK BITS(CAN_TXID1_STDID_POSS,CAN_TXID1_STDID_POSE) - -#define CAN_TXID1_EXID_POSS 3U -#define CAN_TXID1_EXID_POSE 20U -#define CAN_TXID1_EXID_MSK BITS(CAN_TXID1_EXID_POSS,CAN_TXID1_EXID_POSE) - -#define CAN_TXID1_IDE_POS 2U -#define CAN_TXID1_IDE_MSK BIT(CAN_TXID1_IDE_POS) - -#define CAN_TXID1_RTR_POS 1U -#define CAN_TXID1_RTR_MSK BIT(CAN_TXID1_RTR_POS) - -#define CAN_TXID1_TXMREQ_POS 0U -#define CAN_TXID1_TXMREQ_MSK BIT(CAN_TXID1_TXMREQ_POS) - -/****************** Bit definition for CAN_TXFCON1 register ************************/ - -#define CAN_TXFCON1_STAMP_POSS 16U -#define CAN_TXFCON1_STAMP_POSE 31U -#define CAN_TXFCON1_STAMP_MSK BITS(CAN_TXFCON1_STAMP_POSS,CAN_TXFCON1_STAMP_POSE) - -#define CAN_TXFCON1_TXGT_POS 8U -#define CAN_TXFCON1_TXGT_MSK BIT(CAN_TXFCON1_TXGT_POS) - -#define CAN_TXFCON1_DLEN_POSS 0U -#define CAN_TXFCON1_DLEN_POSE 3U -#define CAN_TXFCON1_DLEN_MSK BITS(CAN_TXFCON1_DLEN_POSS,CAN_TXFCON1_DLEN_POSE) - -/****************** Bit definition for CAN_TXDL1 register ************************/ - -#define CAN_TXDL1_BYTE3_POSS 24U -#define CAN_TXDL1_BYTE3_POSE 31U -#define CAN_TXDL1_BYTE3_MSK BITS(CAN_TXDL1_BYTE3_POSS,CAN_TXDL1_BYTE3_POSE) - -#define CAN_TXDL1_BYTE2_POSS 16U -#define CAN_TXDL1_BYTE2_POSE 23U -#define CAN_TXDL1_BYTE2_MSK BITS(CAN_TXDL1_BYTE2_POSS,CAN_TXDL1_BYTE2_POSE) - -#define CAN_TXDL1_BYTE1_POSS 8U -#define CAN_TXDL1_BYTE1_POSE 15U -#define CAN_TXDL1_BYTE1_MSK BITS(CAN_TXDL1_BYTE1_POSS,CAN_TXDL1_BYTE1_POSE) - -#define CAN_TXDL1_BYTE0_POSS 0U -#define CAN_TXDL1_BYTE0_POSE 7U -#define CAN_TXDL1_BYTE0_MSK BITS(CAN_TXDL1_BYTE0_POSS,CAN_TXDL1_BYTE0_POSE) - -/****************** Bit definition for CAN_TXDH1 register ************************/ - -#define CAN_TXDH1_BYTE7_POSS 24U -#define CAN_TXDH1_BYTE7_POSE 31U -#define CAN_TXDH1_BYTE7_MSK BITS(CAN_TXDH1_BYTE7_POSS,CAN_TXDH1_BYTE7_POSE) - -#define CAN_TXDH1_BYTE6_POSS 16U -#define CAN_TXDH1_BYTE6_POSE 23U -#define CAN_TXDH1_BYTE6_MSK BITS(CAN_TXDH1_BYTE6_POSS,CAN_TXDH1_BYTE6_POSE) - -#define CAN_TXDH1_BYTE5_POSS 8U -#define CAN_TXDH1_BYTE5_POSE 15U -#define CAN_TXDH1_BYTE5_MSK BITS(CAN_TXDH1_BYTE5_POSS,CAN_TXDH1_BYTE5_POSE) - -#define CAN_TXDH1_BYTE4_POSS 0U -#define CAN_TXDH1_BYTE4_POSE 7U -#define CAN_TXDH1_BYTE4_MSK BITS(CAN_TXDH1_BYTE4_POSS,CAN_TXDH1_BYTE4_POSE) - -/****************** Bit definition for CAN_TXID2 register ************************/ - -#define CAN_TXID2_STDID_POSS 21U -#define CAN_TXID2_STDID_POSE 31U -#define CAN_TXID2_STDID_MSK BITS(CAN_TXID2_STDID_POSS,CAN_TXID2_STDID_POSE) - -#define CAN_TXID2_EXID_POSS 3U -#define CAN_TXID2_EXID_POSE 20U -#define CAN_TXID2_EXID_MSK BITS(CAN_TXID2_EXID_POSS,CAN_TXID2_EXID_POSE) - -#define CAN_TXID2_IDE_POS 2U -#define CAN_TXID2_IDE_MSK BIT(CAN_TXID2_IDE_POS) - -#define CAN_TXID2_RTR_POS 1U -#define CAN_TXID2_RTR_MSK BIT(CAN_TXID2_RTR_POS) - -#define CAN_TXID2_TXMREQ_POS 0U -#define CAN_TXID2_TXMREQ_MSK BIT(CAN_TXID2_TXMREQ_POS) - -/****************** Bit definition for CAN_TXFCON2 register ************************/ - -#define CAN_TXFCON2_STAMP_POSS 16U -#define CAN_TXFCON2_STAMP_POSE 31U -#define CAN_TXFCON2_STAMP_MSK BITS(CAN_TXFCON2_STAMP_POSS,CAN_TXFCON2_STAMP_POSE) - -#define CAN_TXFCON2_TXGT_POS 8U -#define CAN_TXFCON2_TXGT_MSK BIT(CAN_TXFCON2_TXGT_POS) - -#define CAN_TXFCON2_DLEN_POSS 0U -#define CAN_TXFCON2_DLEN_POSE 3U -#define CAN_TXFCON2_DLEN_MSK BITS(CAN_TXFCON2_DLEN_POSS,CAN_TXFCON2_DLEN_POSE) - -/****************** Bit definition for CAN_TXDL2 register ************************/ - -#define CAN_TXDL2_BYTE3_POSS 24U -#define CAN_TXDL2_BYTE3_POSE 31U -#define CAN_TXDL2_BYTE3_MSK BITS(CAN_TXDL2_BYTE3_POSS,CAN_TXDL2_BYTE3_POSE) - -#define CAN_TXDL2_BYTE2_POSS 16U -#define CAN_TXDL2_BYTE2_POSE 23U -#define CAN_TXDL2_BYTE2_MSK BITS(CAN_TXDL2_BYTE2_POSS,CAN_TXDL2_BYTE2_POSE) - -#define CAN_TXDL2_BYTE1_POSS 8U -#define CAN_TXDL2_BYTE1_POSE 15U -#define CAN_TXDL2_BYTE1_MSK BITS(CAN_TXDL2_BYTE1_POSS,CAN_TXDL2_BYTE1_POSE) - -#define CAN_TXDL2_BYTE0_POSS 0U -#define CAN_TXDL2_BYTE0_POSE 7U -#define CAN_TXDL2_BYTE0_MSK BITS(CAN_TXDL2_BYTE0_POSS,CAN_TXDL2_BYTE0_POSE) - -/****************** Bit definition for CAN_TXDH2 register ************************/ - -#define CAN_TXDH2_BYTE7_POSS 24U -#define CAN_TXDH2_BYTE7_POSE 31U -#define CAN_TXDH2_BYTE7_MSK BITS(CAN_TXDH2_BYTE7_POSS,CAN_TXDH2_BYTE7_POSE) - -#define CAN_TXDH2_BYTE6_POSS 16U -#define CAN_TXDH2_BYTE6_POSE 23U -#define CAN_TXDH2_BYTE6_MSK BITS(CAN_TXDH2_BYTE6_POSS,CAN_TXDH2_BYTE6_POSE) - -#define CAN_TXDH2_BYTE5_POSS 8U -#define CAN_TXDH2_BYTE5_POSE 15U -#define CAN_TXDH2_BYTE5_MSK BITS(CAN_TXDH2_BYTE5_POSS,CAN_TXDH2_BYTE5_POSE) - -#define CAN_TXDH2_BYTE4_POSS 0U -#define CAN_TXDH2_BYTE4_POSE 7U -#define CAN_TXDH2_BYTE4_MSK BITS(CAN_TXDH2_BYTE4_POSS,CAN_TXDH2_BYTE4_POSE) - -/****************** Bit definition for CAN_RXF0ID register ************************/ - -#define CAN_RXF0ID_STDID_POSS 21U -#define CAN_RXF0ID_STDID_POSE 31U -#define CAN_RXF0ID_STDID_MSK BITS(CAN_RXF0ID_STDID_POSS,CAN_RXF0ID_STDID_POSE) - -#define CAN_RXF0ID_EXID_POSS 3U -#define CAN_RXF0ID_EXID_POSE 20U -#define CAN_RXF0ID_EXID_MSK BITS(CAN_RXF0ID_EXID_POSS,CAN_RXF0ID_EXID_POSE) - -#define CAN_RXF0ID_IDE_POS 2U -#define CAN_RXF0ID_IDE_MSK BIT(CAN_RXF0ID_IDE_POS) - -#define CAN_RXF0ID_RTR_POS 1U -#define CAN_RXF0ID_RTR_MSK BIT(CAN_RXF0ID_RTR_POS) - -/****************** Bit definition for CAN_RXF0INF register ************************/ - -#define CAN_RXF0INF_STAMP_POSS 16U -#define CAN_RXF0INF_STAMP_POSE 31U -#define CAN_RXF0INF_STAMP_MSK BITS(CAN_RXF0INF_STAMP_POSS,CAN_RXF0INF_STAMP_POSE) - -#define CAN_RXF0INF_FLTIDX_POSS 8U -#define CAN_RXF0INF_FLTIDX_POSE 15U -#define CAN_RXF0INF_FLTIDX_MSK BITS(CAN_RXF0INF_FLTIDX_POSS,CAN_RXF0INF_FLTIDX_POSE) - -#define CAN_RXF0INF_DLEN_POSS 0U -#define CAN_RXF0INF_DLEN_POSE 3U -#define CAN_RXF0INF_DLEN_MSK BITS(CAN_RXF0INF_DLEN_POSS,CAN_RXF0INF_DLEN_POSE) - -/****************** Bit definition for CAN_RXF0DL register ************************/ - -#define CAN_RXF0DL_BYTE3_POSS 24U -#define CAN_RXF0DL_BYTE3_POSE 31U -#define CAN_RXF0DL_BYTE3_MSK BITS(CAN_RXF0DL_BYTE3_POSS,CAN_RXF0DL_BYTE3_POSE) - -#define CAN_RXF0DL_BYTE2_POSS 16U -#define CAN_RXF0DL_BYTE2_POSE 23U -#define CAN_RXF0DL_BYTE2_MSK BITS(CAN_RXF0DL_BYTE2_POSS,CAN_RXF0DL_BYTE2_POSE) - -#define CAN_RXF0DL_BYTE1_POSS 8U -#define CAN_RXF0DL_BYTE1_POSE 15U -#define CAN_RXF0DL_BYTE1_MSK BITS(CAN_RXF0DL_BYTE1_POSS,CAN_RXF0DL_BYTE1_POSE) - -#define CAN_RXF0DL_BYTE0_POSS 0U -#define CAN_RXF0DL_BYTE0_POSE 7U -#define CAN_RXF0DL_BYTE0_MSK BITS(CAN_RXF0DL_BYTE0_POSS,CAN_RXF0DL_BYTE0_POSE) - -/****************** Bit definition for CAN_RXF0DH register ************************/ - -#define CAN_RXF0DH_BYTE7_POSS 24U -#define CAN_RXF0DH_BYTE7_POSE 31U -#define CAN_RXF0DH_BYTE7_MSK BITS(CAN_RXF0DH_BYTE7_POSS,CAN_RXF0DH_BYTE7_POSE) - -#define CAN_RXF0DH_BYTE6_POSS 16U -#define CAN_RXF0DH_BYTE6_POSE 23U -#define CAN_RXF0DH_BYTE6_MSK BITS(CAN_RXF0DH_BYTE6_POSS,CAN_RXF0DH_BYTE6_POSE) - -#define CAN_RXF0DH_BYTE5_POSS 8U -#define CAN_RXF0DH_BYTE5_POSE 15U -#define CAN_RXF0DH_BYTE5_MSK BITS(CAN_RXF0DH_BYTE5_POSS,CAN_RXF0DH_BYTE5_POSE) - -#define CAN_RXF0DH_BYTE4_POSS 0U -#define CAN_RXF0DH_BYTE4_POSE 7U -#define CAN_RXF0DH_BYTE4_MSK BITS(CAN_RXF0DH_BYTE4_POSS,CAN_RXF0DH_BYTE4_POSE) - -/****************** Bit definition for CAN_RXF1ID register ************************/ - -#define CAN_RXF1ID_STDID_POSS 21U -#define CAN_RXF1ID_STDID_POSE 31U -#define CAN_RXF1ID_STDID_MSK BITS(CAN_RXF1ID_STDID_POSS,CAN_RXF1ID_STDID_POSE) - -#define CAN_RXF1ID_EXID_POSS 3U -#define CAN_RXF1ID_EXID_POSE 20U -#define CAN_RXF1ID_EXID_MSK BITS(CAN_RXF1ID_EXID_POSS,CAN_RXF1ID_EXID_POSE) - -#define CAN_RXF1ID_IDE_POS 2U -#define CAN_RXF1ID_IDE_MSK BIT(CAN_RXF1ID_IDE_POS) - -#define CAN_RXF1ID_RTR_POS 1U -#define CAN_RXF1ID_RTR_MSK BIT(CAN_RXF1ID_RTR_POS) - -/****************** Bit definition for CAN_RXF1INF register ************************/ - -#define CAN_RXF1INF_STAMP_POSS 16U -#define CAN_RXF1INF_STAMP_POSE 31U -#define CAN_RXF1INF_STAMP_MSK BITS(CAN_RXF1INF_STAMP_POSS,CAN_RXF1INF_STAMP_POSE) - -#define CAN_RXF1INF_FLTIDX_POSS 8U -#define CAN_RXF1INF_FLTIDX_POSE 15U -#define CAN_RXF1INF_FLTIDX_MSK BITS(CAN_RXF1INF_FLTIDX_POSS,CAN_RXF1INF_FLTIDX_POSE) - -#define CAN_RXF1INF_DLEN_POSS 0U -#define CAN_RXF1INF_DLEN_POSE 3U -#define CAN_RXF1INF_DLEN_MSK BITS(CAN_RXF1INF_DLEN_POSS,CAN_RXF1INF_DLEN_POSE) - -/****************** Bit definition for CAN_RXF1DL register ************************/ - -#define CAN_RXF1DL_BYTE3_POSS 24U -#define CAN_RXF1DL_BYTE3_POSE 31U -#define CAN_RXF1DL_BYTE3_MSK BITS(CAN_RXF1DL_BYTE3_POSS,CAN_RXF1DL_BYTE3_POSE) - -#define CAN_RXF1DL_BYTE2_POSS 16U -#define CAN_RXF1DL_BYTE2_POSE 23U -#define CAN_RXF1DL_BYTE2_MSK BITS(CAN_RXF1DL_BYTE2_POSS,CAN_RXF1DL_BYTE2_POSE) - -#define CAN_RXF1DL_BYTE1_POSS 8U -#define CAN_RXF1DL_BYTE1_POSE 15U -#define CAN_RXF1DL_BYTE1_MSK BITS(CAN_RXF1DL_BYTE1_POSS,CAN_RXF1DL_BYTE1_POSE) - -#define CAN_RXF1DL_BYTE0_POSS 0U -#define CAN_RXF1DL_BYTE0_POSE 7U -#define CAN_RXF1DL_BYTE0_MSK BITS(CAN_RXF1DL_BYTE0_POSS,CAN_RXF1DL_BYTE0_POSE) - -/****************** Bit definition for CAN_RXF1DH register ************************/ - -#define CAN_RXF1DH_BYTE7_POSS 24U -#define CAN_RXF1DH_BYTE7_POSE 31U -#define CAN_RXF1DH_BYTE7_MSK BITS(CAN_RXF1DH_BYTE7_POSS,CAN_RXF1DH_BYTE7_POSE) - -#define CAN_RXF1DH_BYTE6_POSS 16U -#define CAN_RXF1DH_BYTE6_POSE 23U -#define CAN_RXF1DH_BYTE6_MSK BITS(CAN_RXF1DH_BYTE6_POSS,CAN_RXF1DH_BYTE6_POSE) - -#define CAN_RXF1DH_BYTE5_POSS 8U -#define CAN_RXF1DH_BYTE5_POSE 15U -#define CAN_RXF1DH_BYTE5_MSK BITS(CAN_RXF1DH_BYTE5_POSS,CAN_RXF1DH_BYTE5_POSE) - -#define CAN_RXF1DH_BYTE4_POSS 0U -#define CAN_RXF1DH_BYTE4_POSE 7U -#define CAN_RXF1DH_BYTE4_MSK BITS(CAN_RXF1DH_BYTE4_POSS,CAN_RXF1DH_BYTE4_POSE) - -/****************** Bit definition for CAN_FLTCON register ************************/ - -#define CAN_FLTCON_FLTINI_POS 0U -#define CAN_FLTCON_FLTINI_MSK BIT(CAN_FLTCON_FLTINI_POS) - -/****************** Bit definition for CAN_FLTM register ************************/ - -#define CAN_FLTM_MOD_POSS 0U -#define CAN_FLTM_MOD_POSE 13U -#define CAN_FLTM_MOD_MSK BITS(CAN_FLTM_MOD_POSS,CAN_FLTM_MOD_POSE) - -/****************** Bit definition for CAN_FLTWS register ************************/ - -#define CAN_FLTWS_SEL_POSS 0U -#define CAN_FLTWS_SEL_POSE 13U -#define CAN_FLTWS_SEL_MSK BITS(CAN_FLTWS_SEL_POSS,CAN_FLTWS_SEL_POSE) - -/****************** Bit definition for CAN_FLTAS register ************************/ - -#define CAN_FLTAS_ASSIGN_POSS 0U -#define CAN_FLTAS_ASSIGN_POSE 13U -#define CAN_FLTAS_ASSIGN_MSK BITS(CAN_FLTAS_ASSIGN_POSS,CAN_FLTAS_ASSIGN_POSE) - -/****************** Bit definition for CAN_FLTGO register ************************/ - -#define CAN_FLTGO_GO_POSS 0U -#define CAN_FLTGO_GO_POSE 13U -#define CAN_FLTGO_GO_MSK BITS(CAN_FLTGO_GO_POSS,CAN_FLTGO_GO_POSE) - -typedef struct { - __IO uint32_t TXID; - __IO uint32_t TXFCON; - __IO uint32_t TXDL; - __IO uint32_t TXDH; -} CAN_TxMailBox_Typedef; - -typedef struct { - __IO uint32_t RXFID; - __IO uint32_t RXFINF; - __IO uint32_t RXFDL; - __IO uint32_t RXFDH; -} CAN_RxFIFO_Typedef; - -typedef struct { - __IO uint32_t FLT1; - __IO uint32_t FLT2; -} CAN_Filter_Typedef; - -typedef struct -{ - __IO uint32_t CON; - __I uint32_t STAT; - __O uint32_t IFC; - __IO uint32_t TXSTAT; - __O uint32_t TXSTATC; - __IO uint32_t RXF0; - __O uint32_t RXF0C; - __IO uint32_t RXF1; - __O uint32_t RXF1C; - __IO uint32_t IE; - __IO uint32_t ERRSTAT; - __IO uint32_t BTIME; - uint32_t RESERVED0[84] ; - CAN_TxMailBox_Typedef TxMailBox[3]; - CAN_RxFIFO_Typedef RxFIFO[2]; - uint32_t RESERVED1[12] ; - __IO uint32_t FLTCON; - __IO uint32_t FLTM; - uint32_t RESERVED2 ; - __IO uint32_t FLTWS; - uint32_t RESERVED3 ; - __IO uint32_t FLTAS; - uint32_t RESERVED4 ; - __IO uint32_t FLTGO; - uint32_t RESERVED5[8] ; - CAN_Filter_Typedef Filter[14]; -} CAN_TypeDef; - -/****************** Bit definition for CRC_CR register ************************/ -#define CRC_CR_BYTORD_POS 24U -#define CRC_CR_BYTORD_MSK BIT(CRC_CR_BYTORD_POS) - -#define CRC_CR_DATLEN_POSS 22U -#define CRC_CR_DATLEN_POSE 23U -#define CRC_CR_DATLEN_MSK BITS(CRC_CR_DATLEN_POSS,CRC_CR_DATLEN_POSE) - -#define CRC_CR_MODE_POSS 20U -#define CRC_CR_MODE_POSE 21U -#define CRC_CR_MODE_MSK BITS(CRC_CR_MODE_POSS,CRC_CR_MODE_POSE) - -#define CRC_CR_CHSINV_POS 19U -#define CRC_CR_CHSINV_MSK BIT(CRC_CR_CHSINV_POS) - -#define CRC_CR_DATINV_POS 18U -#define CRC_CR_DATINV_MSK BIT(CRC_CR_DATINV_POS) - -#define CRC_CR_CHSREV_POS 17U -#define CRC_CR_CHSREV_MSK BIT(CRC_CR_CHSREV_POS) - -#define CRC_CR_DATREV_POS 16U -#define CRC_CR_DATREV_MSK BIT(CRC_CR_DATREV_POS) - -#define CRC_CR_DMAEN_POS 4U -#define CRC_CR_DMAEN_MSK BIT(CRC_CR_DMAEN_POS) - -#define CRC_CR_CWERR_POS 3U -#define CRC_CR_CWERR_MSK BIT(CRC_CR_CWERR_POS) - -#define CRC_CR_WERR_POS 2U -#define CRC_CR_WERR_MSK BIT(CRC_CR_WERR_POS) - -#define CRC_CR_RST_POS 1U -#define CRC_CR_RST_MSK BIT(CRC_CR_RST_POS) - -#define CRC_CR_EN_POS 0U -#define CRC_CR_EN_MSK BIT(CRC_CR_EN_POS) - -/****************** Bit definition for CRC_DATA register ************************/ - -#define CRC_DATA_DATA_POSS 0U -#define CRC_DATA_DATA_POSE 31U -#define CRC_DATA_DATA_MSK BITS(CRC_DATA_DATA_POSS,CRC_DATA_DATA_POSE) - -/****************** Bit definition for CRC_SEED register ************************/ - -#define CRC_SEED_SEED_POSS 0U -#define CRC_SEED_SEED_POSE 31U -#define CRC_SEED_SEED_MSK BITS(CRC_SEED_SEED_POSS,CRC_SEED_SEED_POSE) - -/****************** Bit definition for CRC_CHECKSUM register ************************/ - -#define CRC_CHECKSUM_CHECKSUM_POSS 0U -#define CRC_CHECKSUM_CHECKSUM_POSE 31U -#define CRC_CHECKSUM_CHECKSUM_MSK BITS(CRC_CHECKSUM_CHECKSUM_POSS,CRC_CHECKSUM_CHECKSUM_POSE) - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t DATA; - __IO uint32_t SEED; - __I uint32_t CHECKSUM; -} CRC_TypeDef; - -/****************** Bit definition for CRYPT_CON register ************************/ - -#define CRYPT_CON_CRYSEL_POS 31U -#define CRYPT_CON_CRYSEL_MSK BIT(CRYPT_CON_CRYSEL_POS) - -#define CRYPT_CON_RESCLR_POS 15U -#define CRYPT_CON_RESCLR_MSK BIT(CRYPT_CON_RESCLR_POS) - -#define CRYPT_CON_DMAEN_POS 14U -#define CRYPT_CON_DMAEN_MSK BIT(CRYPT_CON_DMAEN_POS) - -#define CRYPT_CON_FIFOODR_POS 13U -#define CRYPT_CON_FIFOODR_MSK BIT(CRYPT_CON_FIFOODR_POS) - -#define CRYPT_CON_FIFOEN_POS 12U -#define CRYPT_CON_FIFOEN_MSK BIT(CRYPT_CON_FIFOEN_POS) - -#define CRYPT_CON_DESKS_POS 11U -#define CRYPT_CON_DESKS_MSK BIT(CRYPT_CON_DESKS_POS) - -#define CRYPT_CON_TDES_POS 10U -#define CRYPT_CON_TDES_MSK BIT(CRYPT_CON_TDES_POS) - -#define CRYPT_CON_TYPE_POSS 8U -#define CRYPT_CON_TYPE_POSE 9U -#define CRYPT_CON_TYPE_MSK BITS(CRYPT_CON_TYPE_POSS,CRYPT_CON_TYPE_POSE) - -#define CRYPT_CON_IE_POS 7U -#define CRYPT_CON_IE_MSK BIT(CRYPT_CON_IE_POS) - -#define CRYPT_CON_IVEN_POS 6U -#define CRYPT_CON_IVEN_MSK BIT(CRYPT_CON_IVEN_POS) - -#define CRYPT_CON_MODE_POSS 4U -#define CRYPT_CON_MODE_POSE 5U -#define CRYPT_CON_MODE_MSK BITS(CRYPT_CON_MODE_POSS,CRYPT_CON_MODE_POSE) - -#define CRYPT_CON_AESKS_POSS 2U -#define CRYPT_CON_AESKS_POSE 3U -#define CRYPT_CON_AESKS_MSK BITS(CRYPT_CON_AESKS_POSS,CRYPT_CON_AESKS_POSE) - -#define CRYPT_CON_ENCS_POS 1U -#define CRYPT_CON_ENCS_MSK BIT(CRYPT_CON_ENCS_POS) - -#define CRYPT_CON_GO_POS 0U -#define CRYPT_CON_GO_MSK BIT(CRYPT_CON_GO_POS) - -/****************** Bit definition for CRYPT_IF register ************************/ - -#define CRYPT_IF_DONE_POS 8U -#define CRYPT_IF_DONE_MSK BIT(CRYPT_IF_DONE_POS) - -#define CRYPT_IF_MULTHIF_POS 2U -#define CRYPT_IF_MULTHIF_MSK BIT(CRYPT_IF_MULTHIF_POS) - -#define CRYPT_IF_DESIF_POS 1U -#define CRYPT_IF_DESIF_MSK BIT(CRYPT_IF_DESIF_POS) - -#define CRYPT_IF_AESIF_POS 0U -#define CRYPT_IF_AESIF_MSK BIT(CRYPT_IF_AESIF_POS) - -/****************** Bit definition for CRYPT_IFC register ************************/ - -#define CRYPT_IFC_MULTHIFC_POS 2U -#define CRYPT_IFC_MULTHIFC_MSK BIT(CRYPT_IFC_MULTHIFC_POS) - -#define CRYPT_IFC_DESIFC_POS 1U -#define CRYPT_IFC_DESIFC_MSK BIT(CRYPT_IFC_DESIFC_POS) - -#define CRYPT_IFC_AESIFC_POS 0U -#define CRYPT_IFC_AESIFC_MSK BIT(CRYPT_IFC_AESIFC_POS) - -/****************** Bit definition for CRYPT_FIFO register ************************/ - -#define CRYPT_FIFO_FIFO_POSS 0U -#define CRYPT_FIFO_FIFO_POSE 31U -#define CRYPT_FIFO_FIFO_MSK BITS(CRYPT_FIFO_FIFO_POSS,CRYPT_FIFO_FIFO_POSE) - -typedef struct -{ - __IO uint32_t DATA[4]; - __IO uint32_t KEY[8]; - __IO uint32_t IV[4]; - __I uint32_t RES[4]; - __IO uint32_t CON; - __I uint32_t IF; - __O uint32_t IFC; - __IO uint32_t FIFO; -} CRYPT_TypeDef; - -/****************** Bit definition for LCD_CR register ************************/ - -#define LCD_CR_VCHPS_POSS 24U -#define LCD_CR_VCHPS_POSE 25U -#define LCD_CR_VCHPS_MSK BITS(LCD_CR_VCHPS_POSS,LCD_CR_VCHPS_POSE) - -#define LCD_CR_DSLD_POSS 20U -#define LCD_CR_DSLD_POSE 23U -#define LCD_CR_DSLD_MSK BITS(LCD_CR_DSLD_POSS,LCD_CR_DSLD_POSE) - -#define LCD_CR_DSHD_POSS 16U -#define LCD_CR_DSHD_POSE 19U -#define LCD_CR_DSHD_MSK BITS(LCD_CR_DSHD_POSS,LCD_CR_DSHD_POSE) - -#define LCD_CR_VBUFLD_POS 15U -#define LCD_CR_VBUFLD_MSK BIT(LCD_CR_VBUFLD_POS) - -#define LCD_CR_VBUFHD_POS 14U -#define LCD_CR_VBUFHD_MSK BIT(LCD_CR_VBUFHD_POS) - -#define LCD_CR_RESLD_POSS 12U -#define LCD_CR_RESLD_POSE 13U -#define LCD_CR_RESLD_MSK BITS(LCD_CR_RESLD_POSS,LCD_CR_RESLD_POSE) - -#define LCD_CR_RESHD_POSS 10U -#define LCD_CR_RESHD_POSE 11U -#define LCD_CR_RESHD_MSK BITS(LCD_CR_RESHD_POSS,LCD_CR_RESHD_POSE) - -#define LCD_CR_BIAS_POSS 8U -#define LCD_CR_BIAS_POSE 9U -#define LCD_CR_BIAS_MSK BITS(LCD_CR_BIAS_POSS,LCD_CR_BIAS_POSE) - -#define LCD_CR_DUTY_POSS 4U -#define LCD_CR_DUTY_POSE 6U -#define LCD_CR_DUTY_MSK BITS(LCD_CR_DUTY_POSS,LCD_CR_DUTY_POSE) - -#define LCD_CR_OE_POS 3U -#define LCD_CR_OE_MSK BIT(LCD_CR_OE_POS) - -#define LCD_CR_VSEL_POSS 1U -#define LCD_CR_VSEL_POSE 2U -#define LCD_CR_VSEL_MSK BITS(LCD_CR_VSEL_POSS,LCD_CR_VSEL_POSE) - -#define LCD_CR_EN_POS 0U -#define LCD_CR_EN_MSK BIT(LCD_CR_EN_POS) - -/****************** Bit definition for LCD_FCR register ************************/ - -#define LCD_FCR_WFS_POS 31U -#define LCD_FCR_WFS_MSK BIT(LCD_FCR_WFS_POS) - -#define LCD_FCR_PRS_POSS 24U -#define LCD_FCR_PRS_POSE 27U -#define LCD_FCR_PRS_MSK BITS(LCD_FCR_PRS_POSS,LCD_FCR_PRS_POSE) - -#define LCD_FCR_DIV_POSS 20U -#define LCD_FCR_DIV_POSE 23U -#define LCD_FCR_DIV_MSK BITS(LCD_FCR_DIV_POSS,LCD_FCR_DIV_POSE) - -#define LCD_FCR_BLMOD_POSS 16U -#define LCD_FCR_BLMOD_POSE 17U -#define LCD_FCR_BLMOD_MSK BITS(LCD_FCR_BLMOD_POSS,LCD_FCR_BLMOD_POSE) - -#define LCD_FCR_BLFRQ_POSS 12U -#define LCD_FCR_BLFRQ_POSE 14U -#define LCD_FCR_BLFRQ_MSK BITS(LCD_FCR_BLFRQ_POSS,LCD_FCR_BLFRQ_POSE) - -#define LCD_FCR_DEAD_POSS 8U -#define LCD_FCR_DEAD_POSE 10U -#define LCD_FCR_DEAD_MSK BITS(LCD_FCR_DEAD_POSS,LCD_FCR_DEAD_POSE) - -#define LCD_FCR_HD_POS 7U -#define LCD_FCR_HD_MSK BIT(LCD_FCR_HD_POS) - -#define LCD_FCR_PON_POSS 4U -#define LCD_FCR_PON_POSE 6U -#define LCD_FCR_PON_MSK BITS(LCD_FCR_PON_POSS,LCD_FCR_PON_POSE) - -#define LCD_FCR_VGS_POSS 0U -#define LCD_FCR_VGS_POSE 3U -#define LCD_FCR_VGS_MSK BITS(LCD_FCR_VGS_POSS,LCD_FCR_VGS_POSE) - -/****************** Bit definition for LCD_SEGCR0 register ************************/ - -#define LCD_SEGCR0_SEG_OE_POSS 0U -#define LCD_SEGCR0_SEG_OE_POSE 31U -#define LCD_SEGCR0_SEG_OE_MSK BITS(LCD_SEGCR0_SEG_OE_POSS,LCD_SEGCR0_SEG_OE_POSE) - -/****************** Bit definition for LCD_SEGCR1 register ************************/ - -#define LCD_SEGCR1_SEG_OE_POSS 0U -#define LCD_SEGCR1_SEG_OE_POSE 11U -#define LCD_SEGCR1_SEG_OE_MSK BITS(LCD_SEGCR1_SEG_OE_POSS,LCD_SEGCR1_SEG_OE_POSE) - -/****************** Bit definition for LCD_IE register ************************/ - -#define LCD_IE_UDDIE_POS 1U -#define LCD_IE_UDDIE_MSK BIT(LCD_IE_UDDIE_POS) - -#define LCD_IE_SOFIE_POS 0U -#define LCD_IE_SOFIE_MSK BIT(LCD_IE_SOFIE_POS) - -/****************** Bit definition for LCD_IF register ************************/ - -#define LCD_IF_UDDIF_POS 1U -#define LCD_IF_UDDIF_MSK BIT(LCD_IF_UDDIF_POS) - -#define LCD_IF_SOFIF_POS 0U -#define LCD_IF_SOFIF_MSK BIT(LCD_IF_SOFIF_POS) - -/****************** Bit definition for LCD_IFCR register ************************/ - -#define LCD_IFCR_UDDIFC_POS 1U -#define LCD_IFCR_UDDIFC_MSK BIT(LCD_IFCR_UDDIFC_POS) - -#define LCD_IFCR_SOFIFC_POS 0U -#define LCD_IFCR_SOFIFC_MSK BIT(LCD_IFCR_SOFIFC_POS) - -/****************** Bit definition for LCD_SR register ************************/ - -#define LCD_SR_FCRSF_POS 3U -#define LCD_SR_FCRSF_MSK BIT(LCD_SR_FCRSF_POS) - -#define LCD_SR_UDR_POS 2U -#define LCD_SR_UDR_MSK BIT(LCD_SR_UDR_POS) - -#define LCD_SR_ENS_POS 1U -#define LCD_SR_ENS_MSK BIT(LCD_SR_ENS_POS) - -#define LCD_SR_RDY_POS 0U -#define LCD_SR_RDY_MSK BIT(LCD_SR_RDY_POS) - -/****************** Bit definition for LCD_BUF register ************************/ - -#define LCD_BUF_SEG_DATA_POSS 0U -#define LCD_BUF_SEG_DATA_POSE 31U -#define LCD_BUF_SEG_DATA_MSK BITS(LCD_BUF_SEG_DATA_POSS,LCD_BUF_SEG_DATA_POSE) - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t FCR; - __IO uint32_t SEGCR0; - __IO uint32_t SEGCR1; - __IO uint32_t IE; - __I uint32_t IF; - __O uint32_t IFCR; - __I uint32_t SR; - uint32_t RESERVED0[8] ; - __IO uint32_t BUF[16]; -} LCD_TypeDef; - -/****************** Bit definition for ADC_STAT register ************************/ - -#define ADC_STAT_ICHS_POS 9U -#define ADC_STAT_ICHS_MSK BIT(ADC_STAT_ICHS_POS) - -#define ADC_STAT_NCHS_POS 8U -#define ADC_STAT_NCHS_MSK BIT(ADC_STAT_NCHS_POS) - -#define ADC_STAT_OVR_POS 3U -#define ADC_STAT_OVR_MSK BIT(ADC_STAT_OVR_POS) - -#define ADC_STAT_ICHE_POS 2U -#define ADC_STAT_ICHE_MSK BIT(ADC_STAT_ICHE_POS) - -#define ADC_STAT_NCHE_POS 1U -#define ADC_STAT_NCHE_MSK BIT(ADC_STAT_NCHE_POS) - -#define ADC_STAT_AWDF_POS 0U -#define ADC_STAT_AWDF_MSK BIT(ADC_STAT_AWDF_POS) - -/****************** Bit definition for ADC_CLR register ************************/ - -#define ADC_CLR_ICHS_POS 9U -#define ADC_CLR_ICHS_MSK BIT(ADC_CLR_ICHS_POS) - -#define ADC_CLR_NCHS_POS 8U -#define ADC_CLR_NCHS_MSK BIT(ADC_CLR_NCHS_POS) - -#define ADC_CLR_OVR_POS 3U -#define ADC_CLR_OVR_MSK BIT(ADC_CLR_OVR_POS) - -#define ADC_CLR_ICHE_POS 2U -#define ADC_CLR_ICHE_MSK BIT(ADC_CLR_ICHE_POS) - -#define ADC_CLR_NCHE_POS 1U -#define ADC_CLR_NCHE_MSK BIT(ADC_CLR_NCHE_POS) - -#define ADC_CLR_AWDF_POS 0U -#define ADC_CLR_AWDF_MSK BIT(ADC_CLR_AWDF_POS) - -/****************** Bit definition for ADC_CON0 register ************************/ - -#define ADC_CON0_OVRIE_POS 26U -#define ADC_CON0_OVRIE_MSK BIT(ADC_CON0_OVRIE_POS) - -#define ADC_CON0_RSEL_POSS 24U -#define ADC_CON0_RSEL_POSE 25U -#define ADC_CON0_RSEL_MSK BITS(ADC_CON0_RSEL_POSS,ADC_CON0_RSEL_POSE) - -#define ADC_CON0_NCHWDEN_POS 23U -#define ADC_CON0_NCHWDEN_MSK BIT(ADC_CON0_NCHWDEN_POS) - -#define ADC_CON0_ICHWDTEN_POS 22U -#define ADC_CON0_ICHWDTEN_MSK BIT(ADC_CON0_ICHWDTEN_POS) - -#define ADC_CON0_ETRGN_POSS 13U -#define ADC_CON0_ETRGN_POSE 15U -#define ADC_CON0_ETRGN_MSK BITS(ADC_CON0_ETRGN_POSS,ADC_CON0_ETRGN_POSE) - -#define ADC_CON0_ICHDCEN_POS 12U -#define ADC_CON0_ICHDCEN_MSK BIT(ADC_CON0_ICHDCEN_POS) - -#define ADC_CON0_NCHDCEN_POS 11U -#define ADC_CON0_NCHDCEN_MSK BIT(ADC_CON0_NCHDCEN_POS) - -#define ADC_CON0_IAUTO_POS 10U -#define ADC_CON0_IAUTO_MSK BIT(ADC_CON0_IAUTO_POS) - -#define ADC_CON0_AWDSGL_POS 9U -#define ADC_CON0_AWDSGL_MSK BIT(ADC_CON0_AWDSGL_POS) - -#define ADC_CON0_SCANEN_POS 8U -#define ADC_CON0_SCANEN_MSK BIT(ADC_CON0_SCANEN_POS) - -#define ADC_CON0_ICHEIE_POS 7U -#define ADC_CON0_ICHEIE_MSK BIT(ADC_CON0_ICHEIE_POS) - -#define ADC_CON0_AWDIE_POS 6U -#define ADC_CON0_AWDIE_MSK BIT(ADC_CON0_AWDIE_POS) - -#define ADC_CON0_NCHEIE_POS 5U -#define ADC_CON0_NCHEIE_MSK BIT(ADC_CON0_NCHEIE_POS) - -#define ADC_CON0_AWDCH_POSS 0U -#define ADC_CON0_AWDCH_POSE 4U -#define ADC_CON0_AWDCH_MSK BITS(ADC_CON0_AWDCH_POSS,ADC_CON0_AWDCH_POSE) - -/****************** Bit definition for ADC_CON1 register ************************/ - -#define ADC_CON1_NCHTRG_POS 30U -#define ADC_CON1_NCHTRG_MSK BIT(ADC_CON1_NCHTRG_POS) - -#define ADC_CON1_ICHTRG_POS 22U -#define ADC_CON1_ICHTRG_MSK BIT(ADC_CON1_ICHTRG_POS) - -#define ADC_CON1_ALIGN_POS 11U -#define ADC_CON1_ALIGN_MSK BIT(ADC_CON1_ALIGN_POS) - -#define ADC_CON1_NCHESEL_POS 10U -#define ADC_CON1_NCHESEL_MSK BIT(ADC_CON1_NCHESEL_POS) - -#define ADC_CON1_OVRDIS_POS 8U -#define ADC_CON1_OVRDIS_MSK BIT(ADC_CON1_OVRDIS_POS) - -#define ADC_CON1_CM_POS 1U -#define ADC_CON1_CM_MSK BIT(ADC_CON1_CM_POS) - -#define ADC_CON1_ADCEN_POS 0U -#define ADC_CON1_ADCEN_MSK BIT(ADC_CON1_ADCEN_POS) - -/****************** Bit definition for ADC_SMPT1 register ************************/ - -#define ADC_SMPT1_CHT_POSS 0U -#define ADC_SMPT1_CHT_POSE 31U -#define ADC_SMPT1_CHT_MSK BITS(ADC_SMPT1_CHT_POSS,ADC_SMPT1_CHT_POSE) - -/****************** Bit definition for ADC_SMPT2 register ************************/ - -#define ADC_SMPT2_CHT_POSS 0U -#define ADC_SMPT2_CHT_POSE 7U -#define ADC_SMPT2_CHT_MSK BITS(ADC_SMPT2_CHT_POSS,ADC_SMPT2_CHT_POSE) - -/****************** Bit definition for ADC_ICHOFF1 register ************************/ - -#define ADC_ICHOFF1_IOFF_POSS 0U -#define ADC_ICHOFF1_IOFF_POSE 11U -#define ADC_ICHOFF1_IOFF_MSK BITS(ADC_ICHOFF1_IOFF_POSS,ADC_ICHOFF1_IOFF_POSE) - -/****************** Bit definition for ADC_ICHOFF2 register ************************/ - -#define ADC_ICHOFF2_IOFF_POSS 0U -#define ADC_ICHOFF2_IOFF_POSE 11U -#define ADC_ICHOFF2_IOFF_MSK BITS(ADC_ICHOFF2_IOFF_POSS,ADC_ICHOFF2_IOFF_POSE) - -/****************** Bit definition for ADC_ICHOFF3 register ************************/ - -#define ADC_ICHOFF3_IOFF_POSS 0U -#define ADC_ICHOFF3_IOFF_POSE 11U -#define ADC_ICHOFF3_IOFF_MSK BITS(ADC_ICHOFF3_IOFF_POSS,ADC_ICHOFF3_IOFF_POSE) - -/****************** Bit definition for ADC_ICHOFF4 register ************************/ - -#define ADC_ICHOFF4_IOFF_POSS 0U -#define ADC_ICHOFF4_IOFF_POSE 11U -#define ADC_ICHOFF4_IOFF_MSK BITS(ADC_ICHOFF4_IOFF_POSS,ADC_ICHOFF4_IOFF_POSE) - -/****************** Bit definition for ADC_WDTH register ************************/ - -#define ADC_WDTH_HT_POSS 0U -#define ADC_WDTH_HT_POSE 11U -#define ADC_WDTH_HT_MSK BITS(ADC_WDTH_HT_POSS,ADC_WDTH_HT_POSE) - -/****************** Bit definition for ADC_WDTL register ************************/ - -#define ADC_WDTL_LT_POSS 0U -#define ADC_WDTL_LT_POSE 11U -#define ADC_WDTL_LT_MSK BITS(ADC_WDTL_LT_POSS,ADC_WDTL_LT_POSE) - -/****************** Bit definition for ADC_NCHS1 register ************************/ - -#define ADC_NCHS1_NS4_POSS 24U -#define ADC_NCHS1_NS4_POSE 28U -#define ADC_NCHS1_NS4_MSK BITS(ADC_NCHS1_NS4_POSS,ADC_NCHS1_NS4_POSE) - -#define ADC_NCHS1_NS3_POSS 16U -#define ADC_NCHS1_NS3_POSE 20U -#define ADC_NCHS1_NS3_MSK BITS(ADC_NCHS1_NS3_POSS,ADC_NCHS1_NS3_POSE) - -#define ADC_NCHS1_NS2_POSS 8U -#define ADC_NCHS1_NS2_POSE 12U -#define ADC_NCHS1_NS2_MSK BITS(ADC_NCHS1_NS2_POSS,ADC_NCHS1_NS2_POSE) - -#define ADC_NCHS1_NS1_POSS 0U -#define ADC_NCHS1_NS1_POSE 4U -#define ADC_NCHS1_NS1_MSK BITS(ADC_NCHS1_NS1_POSS,ADC_NCHS1_NS1_POSE) - -/****************** Bit definition for ADC_NCHS2 register ************************/ - -#define ADC_NCHS2_NS8_POSS 24U -#define ADC_NCHS2_NS8_POSE 28U -#define ADC_NCHS2_NS8_MSK BITS(ADC_NCHS2_NS8_POSS,ADC_NCHS2_NS8_POSE) - -#define ADC_NCHS2_NS7_POSS 16U -#define ADC_NCHS2_NS7_POSE 20U -#define ADC_NCHS2_NS7_MSK BITS(ADC_NCHS2_NS7_POSS,ADC_NCHS2_NS7_POSE) - -#define ADC_NCHS2_NS6_POSS 8U -#define ADC_NCHS2_NS6_POSE 12U -#define ADC_NCHS2_NS6_MSK BITS(ADC_NCHS2_NS6_POSS,ADC_NCHS2_NS6_POSE) - -#define ADC_NCHS2_NS5_POSS 0U -#define ADC_NCHS2_NS5_POSE 4U -#define ADC_NCHS2_NS5_MSK BITS(ADC_NCHS2_NS5_POSS,ADC_NCHS2_NS5_POSE) - -/****************** Bit definition for ADC_NCHS3 register ************************/ - -#define ADC_NCHS3_NS12_POSS 24U -#define ADC_NCHS3_NS12_POSE 28U -#define ADC_NCHS3_NS12_MSK BITS(ADC_NCHS3_NS12_POSS,ADC_NCHS3_NS12_POSE) - -#define ADC_NCHS3_NS11_POSS 16U -#define ADC_NCHS3_NS11_POSE 20U -#define ADC_NCHS3_NS11_MSK BITS(ADC_NCHS3_NS11_POSS,ADC_NCHS3_NS11_POSE) - -#define ADC_NCHS3_NS10_POSS 8U -#define ADC_NCHS3_NS10_POSE 12U -#define ADC_NCHS3_NS10_MSK BITS(ADC_NCHS3_NS10_POSS,ADC_NCHS3_NS10_POSE) - -#define ADC_NCHS3_NS9_POSS 0U -#define ADC_NCHS3_NS9_POSE 4U -#define ADC_NCHS3_NS9_MSK BITS(ADC_NCHS3_NS9_POSS,ADC_NCHS3_NS9_POSE) - -/****************** Bit definition for ADC_NCHS4 register ************************/ - -#define ADC_NCHS4_NS16_POSS 24U -#define ADC_NCHS4_NS16_POSE 28U -#define ADC_NCHS4_NS16_MSK BITS(ADC_NCHS4_NS16_POSS,ADC_NCHS4_NS16_POSE) - -#define ADC_NCHS4_NS15_POSS 16U -#define ADC_NCHS4_NS15_POSE 20U -#define ADC_NCHS4_NS15_MSK BITS(ADC_NCHS4_NS15_POSS,ADC_NCHS4_NS15_POSE) - -#define ADC_NCHS4_NS14_POSS 8U -#define ADC_NCHS4_NS14_POSE 12U -#define ADC_NCHS4_NS14_MSK BITS(ADC_NCHS4_NS14_POSS,ADC_NCHS4_NS14_POSE) - -#define ADC_NCHS4_NS13_POSS 0U -#define ADC_NCHS4_NS13_POSE 4U -#define ADC_NCHS4_NS13_MSK BITS(ADC_NCHS4_NS13_POSS,ADC_NCHS4_NS13_POSE) - -/****************** Bit definition for ADC_ICHS register ************************/ - -#define ADC_ICHS_IS4_POSS 24U -#define ADC_ICHS_IS4_POSE 28U -#define ADC_ICHS_IS4_MSK BITS(ADC_ICHS_IS4_POSS,ADC_ICHS_IS4_POSE) - -#define ADC_ICHS_IS3_POSS 16U -#define ADC_ICHS_IS3_POSE 20U -#define ADC_ICHS_IS3_MSK BITS(ADC_ICHS_IS3_POSS,ADC_ICHS_IS3_POSE) - -#define ADC_ICHS_IS2_POSS 8U -#define ADC_ICHS_IS2_POSE 12U -#define ADC_ICHS_IS2_MSK BITS(ADC_ICHS_IS2_POSS,ADC_ICHS_IS2_POSE) - -#define ADC_ICHS_IS1_POSS 0U -#define ADC_ICHS_IS1_POSE 4U -#define ADC_ICHS_IS1_MSK BITS(ADC_ICHS_IS1_POSS,ADC_ICHS_IS1_POSE) - -/****************** Bit definition for ADC_CHSL register ************************/ - -#define ADC_CHSL_ISL_POSS 8U -#define ADC_CHSL_ISL_POSE 9U -#define ADC_CHSL_ISL_MSK BITS(ADC_CHSL_ISL_POSS,ADC_CHSL_ISL_POSE) - -#define ADC_CHSL_NSL_POSS 0U -#define ADC_CHSL_NSL_POSE 3U -#define ADC_CHSL_NSL_MSK BITS(ADC_CHSL_NSL_POSS,ADC_CHSL_NSL_POSE) - -/****************** Bit definition for ADC_ICHDR1 register ************************/ - -#define ADC_ICHDR1_VAL_POSS 0U -#define ADC_ICHDR1_VAL_POSE 15U -#define ADC_ICHDR1_VAL_MSK BITS(ADC_ICHDR1_VAL_POSS,ADC_ICHDR1_VAL_POSE) - -/****************** Bit definition for ADC_ICHDR2 register ************************/ - -#define ADC_ICHDR2_VAL_POSS 0U -#define ADC_ICHDR2_VAL_POSE 15U -#define ADC_ICHDR2_VAL_MSK BITS(ADC_ICHDR2_VAL_POSS,ADC_ICHDR2_VAL_POSE) - -/****************** Bit definition for ADC_ICHDR3 register ************************/ - -#define ADC_ICHDR3_VAL_POSS 0U -#define ADC_ICHDR3_VAL_POSE 15U -#define ADC_ICHDR3_VAL_MSK BITS(ADC_ICHDR3_VAL_POSS,ADC_ICHDR3_VAL_POSE) - -/****************** Bit definition for ADC_ICHDR4 register ************************/ - -#define ADC_ICHDR4_VAL_POSS 0U -#define ADC_ICHDR4_VAL_POSE 15U -#define ADC_ICHDR4_VAL_MSK BITS(ADC_ICHDR4_VAL_POSS,ADC_ICHDR4_VAL_POSE) - -/****************** Bit definition for ADC_NCHDR register ************************/ - -#define ADC_NCHDR_VAL_POSS 0U -#define ADC_NCHDR_VAL_POSE 15U -#define ADC_NCHDR_VAL_MSK BITS(ADC_NCHDR_VAL_POSS,ADC_NCHDR_VAL_POSE) - -/****************** Bit definition for ADC_CCR register ************************/ - -#define ADC_CCR_TRMEN_POS 28U -#define ADC_CCR_TRMEN_MSK BIT(ADC_CCR_TRMEN_POS) - -#define ADC_CCR_GAINCALEN_POS 25U -#define ADC_CCR_GAINCALEN_MSK BIT(ADC_CCR_GAINCALEN_POS) - -#define ADC_CCR_OFFCALEN_POS 24U -#define ADC_CCR_OFFCALEN_MSK BIT(ADC_CCR_OFFCALEN_POS) - -#define ADC_CCR_VREFOEN_POS 19U -#define ADC_CCR_VREFOEN_MSK BIT(ADC_CCR_VREFOEN_POS) - -#define ADC_CCR_VRNSEL_POS 18U -#define ADC_CCR_VRNSEL_MSK BIT(ADC_CCR_VRNSEL_POS) - -#define ADC_CCR_VRPSEL_POSS 16U -#define ADC_CCR_VRPSEL_POSE 17U -#define ADC_CCR_VRPSEL_MSK BITS(ADC_CCR_VRPSEL_POSS,ADC_CCR_VRPSEL_POSE) - -#define ADC_CCR_PWRMODSEL_POS 15U -#define ADC_CCR_PWRMODSEL_MSK BIT(ADC_CCR_PWRMODSEL_POS) - -#define ADC_CCR_DIFFEN_POS 12U -#define ADC_CCR_DIFFEN_MSK BIT(ADC_CCR_DIFFEN_POS) - -#define ADC_CCR_IREFEN_POS 11U -#define ADC_CCR_IREFEN_MSK BIT(ADC_CCR_IREFEN_POS) - -#define ADC_CCR_VRBUFEN_POS 10U -#define ADC_CCR_VRBUFEN_MSK BIT(ADC_CCR_VRBUFEN_POS) - -#define ADC_CCR_VCMBUFEN_POS 9U -#define ADC_CCR_VCMBUFEN_MSK BIT(ADC_CCR_VCMBUFEN_POS) - -#define ADC_CCR_VREFEN_POS 8U -#define ADC_CCR_VREFEN_MSK BIT(ADC_CCR_VREFEN_POS) - -#define ADC_CCR_CKDIV_POSS 0U -#define ADC_CCR_CKDIV_POSE 2U -#define ADC_CCR_CKDIV_MSK BITS(ADC_CCR_CKDIV_POSS,ADC_CCR_CKDIV_POSE) - -typedef struct -{ - __I uint32_t STAT; - __O uint32_t CLR; - __IO uint32_t CON0; - __IO uint32_t CON1; - __IO uint32_t SMPT1; - __IO uint32_t SMPT2; - __IO uint32_t ICHOFF[4]; - __IO uint32_t WDTH; - __IO uint32_t WDTL; - __IO uint32_t NCHS1; - __IO uint32_t NCHS2; - __IO uint32_t NCHS3; - __IO uint32_t NCHS4; - __IO uint32_t ICHS; - __IO uint32_t CHSL; - __I uint32_t ICHDR[4]; - __I uint32_t NCHDR; - __IO uint32_t CCR; -} ADC_TypeDef; - -/****************** Bit definition for ACMP_CON register ************************/ - -#define ACMP_CON_FALLEN_POS 17U -#define ACMP_CON_FALLEN_MSK BIT(ACMP_CON_FALLEN_POS) - -#define ACMP_CON_RISEEN_POS 16U -#define ACMP_CON_RISEEN_MSK BIT(ACMP_CON_RISEEN_POS) - -#define ACMP_CON_MODSEL_POSS 14U -#define ACMP_CON_MODSEL_POSE 15U -#define ACMP_CON_MODSEL_MSK BITS(ACMP_CON_MODSEL_POSS,ACMP_CON_MODSEL_POSE) - -#define ACMP_CON_WARMUPT_POSS 8U -#define ACMP_CON_WARMUPT_POSE 10U -#define ACMP_CON_WARMUPT_MSK BITS(ACMP_CON_WARMUPT_POSS,ACMP_CON_WARMUPT_POSE) - -#define ACMP_CON_HYSTSEL_POSS 4U -#define ACMP_CON_HYSTSEL_POSE 6U -#define ACMP_CON_HYSTSEL_MSK BITS(ACMP_CON_HYSTSEL_POSS,ACMP_CON_HYSTSEL_POSE) - -#define ACMP_CON_OUTINV_POS 3U -#define ACMP_CON_OUTINV_MSK BIT(ACMP_CON_OUTINV_POS) - -#define ACMP_CON_INACTV_POS 2U -#define ACMP_CON_INACTV_MSK BIT(ACMP_CON_INACTV_POS) - -#define ACMP_CON_EN_POS 0U -#define ACMP_CON_EN_MSK BIT(ACMP_CON_EN_POS) - -/****************** Bit definition for ACMP_INPUTSEL register ************************/ - -#define ACMP_INPUTSEL_VDDLVL_POSS 8U -#define ACMP_INPUTSEL_VDDLVL_POSE 13U -#define ACMP_INPUTSEL_VDDLVL_MSK BITS(ACMP_INPUTSEL_VDDLVL_POSS,ACMP_INPUTSEL_VDDLVL_POSE) - -#define ACMP_INPUTSEL_NSEL_POSS 4U -#define ACMP_INPUTSEL_NSEL_POSE 7U -#define ACMP_INPUTSEL_NSEL_MSK BITS(ACMP_INPUTSEL_NSEL_POSS,ACMP_INPUTSEL_NSEL_POSE) - -#define ACMP_INPUTSEL_PSEL_POSS 0U -#define ACMP_INPUTSEL_PSEL_POSE 2U -#define ACMP_INPUTSEL_PSEL_MSK BITS(ACMP_INPUTSEL_PSEL_POSS,ACMP_INPUTSEL_PSEL_POSE) - -/****************** Bit definition for ACMP_STAT register ************************/ - -#define ACMP_STAT_OUT_POS 1U -#define ACMP_STAT_OUT_MSK BIT(ACMP_STAT_OUT_POS) - -#define ACMP_STAT_ACT_POS 0U -#define ACMP_STAT_ACT_MSK BIT(ACMP_STAT_ACT_POS) - -/****************** Bit definition for ACMP_IES register ************************/ - -#define ACMP_IES_WARMUP_POS 1U -#define ACMP_IES_WARMUP_MSK BIT(ACMP_IES_WARMUP_POS) - -#define ACMP_IES_EDGE_POS 0U -#define ACMP_IES_EDGE_MSK BIT(ACMP_IES_EDGE_POS) - -/****************** Bit definition for ACMP_IEV register ************************/ - -#define ACMP_IEV_WARMUP_POS 1U -#define ACMP_IEV_WARMUP_MSK BIT(ACMP_IEV_WARMUP_POS) - -#define ACMP_IEV_EDGE_POS 0U -#define ACMP_IEV_EDGE_MSK BIT(ACMP_IEV_EDGE_POS) - -/****************** Bit definition for ACMP_IEC register ************************/ - -#define ACMP_IEC_WARMUP_POS 1U -#define ACMP_IEC_WARMUP_MSK BIT(ACMP_IEC_WARMUP_POS) - -#define ACMP_IEC_EDGE_POS 0U -#define ACMP_IEC_EDGE_MSK BIT(ACMP_IEC_EDGE_POS) - -/****************** Bit definition for ACMP_RIF register ************************/ - -#define ACMP_RIF_WARMUP_POS 1U -#define ACMP_RIF_WARMUP_MSK BIT(ACMP_RIF_WARMUP_POS) - -#define ACMP_RIF_EDGE_POS 0U -#define ACMP_RIF_EDGE_MSK BIT(ACMP_RIF_EDGE_POS) - -/****************** Bit definition for ACMP_IFM register ************************/ - -#define ACMP_IFM_WARMUP_POS 1U -#define ACMP_IFM_WARMUP_MSK BIT(ACMP_IFM_WARMUP_POS) - -#define ACMP_IFM_EDGE_POS 0U -#define ACMP_IFM_EDGE_MSK BIT(ACMP_IFM_EDGE_POS) - -/****************** Bit definition for ACMP_IFC register ************************/ - -#define ACMP_IFC_WARMUP_POS 1U -#define ACMP_IFC_WARMUP_MSK BIT(ACMP_IFC_WARMUP_POS) - -#define ACMP_IFC_EDGE_POS 0U -#define ACMP_IFC_EDGE_MSK BIT(ACMP_IFC_EDGE_POS) - -/****************** Bit definition for ACMP_PORT register ************************/ - -#define ACMP_PORT_PEN_POS 0U -#define ACMP_PORT_PEN_MSK BIT(ACMP_PORT_PEN_POS) - -typedef struct -{ - __IO uint32_t CON; - __IO uint32_t INPUTSEL; - __I uint32_t STAT; - __O uint32_t IES; - __I uint32_t IEV; - __O uint32_t IEC; - __I uint32_t RIF; - __O uint32_t IFM; - __O uint32_t IFC; - __IO uint32_t PORT; -} ACMP_TypeDef; - -/****************** Bit definition for CALC_SQRTSR register ************************/ - -#define CALC_SQRTSR_BUSY_POS 0U -#define CALC_SQRTSR_BUSY_MSK BIT(CALC_SQRTSR_BUSY_POS) - -/****************** Bit definition for CALC_RDCND register ************************/ - -#define CALC_RDCND_RADICAND_POSS 0U -#define CALC_RDCND_RADICAND_POSE 31U -#define CALC_RDCND_RADICAND_MSK BITS(CALC_RDCND_RADICAND_POSS,CALC_RDCND_RADICAND_POSE) - -/****************** Bit definition for CALC_SQRTRES register ************************/ - -#define CALC_SQRTRES_RESULT_POSS 0U -#define CALC_SQRTRES_RESULT_POSE 15U -#define CALC_SQRTRES_RESULT_MSK BITS(CALC_SQRTRES_RESULT_POSS,CALC_SQRTRES_RESULT_POSE) - -/****************** Bit definition for CALC_DIVDR register ************************/ - -#define CALC_DIVDR_DIVD_POSS 0U -#define CALC_DIVDR_DIVD_POSE 31U -#define CALC_DIVDR_DIVD_MSK BITS(CALC_DIVDR_DIVD_POSS,CALC_DIVDR_DIVD_POSE) - -/****************** Bit definition for CALC_DIVSR register ************************/ - -#define CALC_DIVSR_DIVS_POSS 0U -#define CALC_DIVSR_DIVS_POSE 31U -#define CALC_DIVSR_DIVS_MSK BITS(CALC_DIVSR_DIVS_POSS,CALC_DIVSR_DIVS_POSE) - -/****************** Bit definition for CALC_DIVQR register ************************/ - -#define CALC_DIVQR_DIVQ_POSS 0U -#define CALC_DIVQR_DIVQ_POSE 31U -#define CALC_DIVQR_DIVQ_MSK BITS(CALC_DIVQR_DIVQ_POSS,CALC_DIVQR_DIVQ_POSE) - -/****************** Bit definition for CALC_DIVRR register ************************/ - -#define CALC_DIVRR_DIVS_POSS 0U -#define CALC_DIVRR_DIVS_POSE 31U -#define CALC_DIVRR_DIVS_MSK BITS(CALC_DIVRR_DIVS_POSS,CALC_DIVRR_DIVS_POSE) - -/****************** Bit definition for CALC_DIVCSR register ************************/ - -#define CALC_DIVCSR_TRM_POS 9U -#define CALC_DIVCSR_TRM_MSK BIT(CALC_DIVCSR_TRM_POS) - -#define CALC_DIVCSR_SIGN_POS 8U -#define CALC_DIVCSR_SIGN_MSK BIT(CALC_DIVCSR_SIGN_POS) - -#define CALC_DIVCSR_DZ_POS 1U -#define CALC_DIVCSR_DZ_MSK BIT(CALC_DIVCSR_DZ_POS) - -#define CALC_DIVCSR_BUSY_POS 0U -#define CALC_DIVCSR_BUSY_MSK BIT(CALC_DIVCSR_BUSY_POS) - -typedef struct -{ - __I uint32_t SQRTSR; - __IO uint32_t RDCND; - __I uint32_t SQRTRES; - uint32_t RESERVED0[5] ; - __IO uint32_t DIVDR; - __IO uint32_t DIVSR; - __I uint32_t DIVQR; - __I uint32_t DIVRR; - __IO uint32_t DIVCSR; -} CALC_TypeDef; - -/****************** Bit definition for TRNG_CR register ************************/ - -#define TRNG_CR_ADJC_POSS 16U -#define TRNG_CR_ADJC_POSE 17U -#define TRNG_CR_ADJC_MSK BITS(TRNG_CR_ADJC_POSS,TRNG_CR_ADJC_POSE) - -#define TRNG_CR_SDSEL_POSS 10U -#define TRNG_CR_SDSEL_POSE 11U -#define TRNG_CR_SDSEL_MSK BITS(TRNG_CR_SDSEL_POSS,TRNG_CR_SDSEL_POSE) - -#define TRNG_CR_DSEL_POSS 8U -#define TRNG_CR_DSEL_POSE 9U -#define TRNG_CR_DSEL_MSK BITS(TRNG_CR_DSEL_POSS,TRNG_CR_DSEL_POSE) - -#define TRNG_CR_POSTEN_POS 3U -#define TRNG_CR_POSTEN_MSK BIT(TRNG_CR_POSTEN_POS) - -#define TRNG_CR_TRNGSEL_POS 2U -#define TRNG_CR_TRNGSEL_MSK BIT(TRNG_CR_TRNGSEL_POS) - -#define TRNG_CR_ADJM_POS 1U -#define TRNG_CR_ADJM_MSK BIT(TRNG_CR_ADJM_POS) - -#define TRNG_CR_TRNGEN_POS 0U -#define TRNG_CR_TRNGEN_MSK BIT(TRNG_CR_TRNGEN_POS) - -/****************** Bit definition for TRNG_SR register ************************/ - -#define TRNG_SR_OVER_POS 3U -#define TRNG_SR_OVER_MSK BIT(TRNG_SR_OVER_POS) - -#define TRNG_SR_SERR_POS 2U -#define TRNG_SR_SERR_MSK BIT(TRNG_SR_SERR_POS) - -#define TRNG_SR_DAVLD_POS 1U -#define TRNG_SR_DAVLD_MSK BIT(TRNG_SR_DAVLD_POS) - -#define TRNG_SR_START_POS 0U -#define TRNG_SR_START_MSK BIT(TRNG_SR_START_POS) - -/****************** Bit definition for TRNG_DR register ************************/ - -#define TRNG_DR_DATA_POSS 0U -#define TRNG_DR_DATA_POSE 31U -#define TRNG_DR_DATA_MSK BITS(TRNG_DR_DATA_POSS,TRNG_DR_DATA_POSE) - -/****************** Bit definition for TRNG_SEED register ************************/ - -#define TRNG_SEED_SEED_POSS 0U -#define TRNG_SEED_SEED_POSE 31U -#define TRNG_SEED_SEED_MSK BITS(TRNG_SEED_SEED_POSS,TRNG_SEED_SEED_POSE) - -/****************** Bit definition for TRNG_CFGR register ************************/ - -#define TRNG_CFGR_TOPLMT_POSS 16U -#define TRNG_CFGR_TOPLMT_POSE 24U -#define TRNG_CFGR_TOPLMT_MSK BITS(TRNG_CFGR_TOPLMT_POSS,TRNG_CFGR_TOPLMT_POSE) - -#define TRNG_CFGR_CKDIV_POSS 8U -#define TRNG_CFGR_CKDIV_POSE 11U -#define TRNG_CFGR_CKDIV_MSK BITS(TRNG_CFGR_CKDIV_POSS,TRNG_CFGR_CKDIV_POSE) - -#define TRNG_CFGR_TSTART_POSS 0U -#define TRNG_CFGR_TSTART_POSE 2U -#define TRNG_CFGR_TSTART_MSK BITS(TRNG_CFGR_TSTART_POSS,TRNG_CFGR_TSTART_POSE) - -/****************** Bit definition for TRNG_IER register ************************/ - -#define TRNG_IER_SERR_POS 2U -#define TRNG_IER_SERR_MSK BIT(TRNG_IER_SERR_POS) - -#define TRNG_IER_DAVLD_POS 1U -#define TRNG_IER_DAVLD_MSK BIT(TRNG_IER_DAVLD_POS) - -#define TRNG_IER_START_POS 0U -#define TRNG_IER_START_MSK BIT(TRNG_IER_START_POS) - -/****************** Bit definition for TRNG_IFR register ************************/ - -#define TRNG_IFR_SERR_POS 2U -#define TRNG_IFR_SERR_MSK BIT(TRNG_IFR_SERR_POS) - -#define TRNG_IFR_DAVLD_POS 1U -#define TRNG_IFR_DAVLD_MSK BIT(TRNG_IFR_DAVLD_POS) - -#define TRNG_IFR_START_POS 0U -#define TRNG_IFR_START_MSK BIT(TRNG_IFR_START_POS) - -/****************** Bit definition for TRNG_IFCR register ************************/ - -#define TRNG_IFCR_SERRC_POS 2U -#define TRNG_IFCR_SERRC_MSK BIT(TRNG_IFCR_SERRC_POS) - -#define TRNG_IFCR_DAVLDC_POS 1U -#define TRNG_IFCR_DAVLDC_MSK BIT(TRNG_IFCR_DAVLDC_POS) - -#define TRNG_IFCR_STARTC_POS 0U -#define TRNG_IFCR_STARTC_MSK BIT(TRNG_IFCR_STARTC_POS) - -/****************** Bit definition for TRNG_ISR register ************************/ - -#define TRNG_ISR_SERR_POS 2U -#define TRNG_ISR_SERR_MSK BIT(TRNG_ISR_SERR_POS) - -#define TRNG_ISR_DAVLD_POS 1U -#define TRNG_ISR_DAVLD_MSK BIT(TRNG_ISR_DAVLD_POS) - -#define TRNG_ISR_START_POS 0U -#define TRNG_ISR_START_MSK BIT(TRNG_ISR_START_POS) - -typedef struct -{ - __IO uint32_t CR; - __I uint32_t SR; - __I uint32_t DR; - __IO uint32_t SEED; - __IO uint32_t CFGR; - __IO uint32_t IER; - __I uint32_t IFR; - __O uint32_t IFCR; - __I uint32_t ISR; -} TRNG_TypeDef; - -/****************** Bit definition for TEMP_WPR register ************************/ - -#define TEMP_WPR_WP_POS 0U -#define TEMP_WPR_WP_MSK BIT(TEMP_WPR_WP_POS) - -/****************** Bit definition for TEMP_CR register ************************/ - -#define TEMP_CR_TSU_POSS 12U -#define TEMP_CR_TSU_POSE 14U -#define TEMP_CR_TSU_MSK BITS(TEMP_CR_TSU_POSS,TEMP_CR_TSU_POSE) - -#define TEMP_CR_TOM_POSS 8U -#define TEMP_CR_TOM_POSE 10U -#define TEMP_CR_TOM_MSK BITS(TEMP_CR_TOM_POSS,TEMP_CR_TOM_POSE) - -#define TEMP_CR_CTN_POS 4U -#define TEMP_CR_CTN_MSK BIT(TEMP_CR_CTN_POS) - -#define TEMP_CR_RST_POS 3U -#define TEMP_CR_RST_MSK BIT(TEMP_CR_RST_POS) - -#define TEMP_CR_ENS_POS 2U -#define TEMP_CR_ENS_MSK BIT(TEMP_CR_ENS_POS) - -#define TEMP_CR_REQEN_POS 1U -#define TEMP_CR_REQEN_MSK BIT(TEMP_CR_REQEN_POS) - -#define TEMP_CR_EN_POS 0U -#define TEMP_CR_EN_MSK BIT(TEMP_CR_EN_POS) - -/****************** Bit definition for TEMP_DR register ************************/ - -#define TEMP_DR_ERR_POS 31U -#define TEMP_DR_ERR_MSK BIT(TEMP_DR_ERR_POS) - -#define TEMP_DR_DATA_POSS 0U -#define TEMP_DR_DATA_POSE 15U -#define TEMP_DR_DATA_MSK BITS(TEMP_DR_DATA_POSS,TEMP_DR_DATA_POSE) - -/****************** Bit definition for TEMP_PSR register ************************/ - -#define TEMP_PSR_PRS_POSS 0U -#define TEMP_PSR_PRS_POSE 7U -#define TEMP_PSR_PRS_MSK BITS(TEMP_PSR_PRS_POSS,TEMP_PSR_PRS_POSE) - -/****************** Bit definition for TEMP_IE register ************************/ - -#define TEMP_IE_TEMP_POS 0U -#define TEMP_IE_TEMP_MSK BIT(TEMP_IE_TEMP_POS) - -/****************** Bit definition for TEMP_IF register ************************/ - -#define TEMP_IF_TEMP_POS 0U -#define TEMP_IF_TEMP_MSK BIT(TEMP_IF_TEMP_POS) - -/****************** Bit definition for TEMP_IFCR register ************************/ - -#define TEMP_IFCR_TEMP_POS 0U -#define TEMP_IFCR_TEMP_MSK BIT(TEMP_IFCR_TEMP_POS) - -/****************** Bit definition for TEMP_LTGR register ************************/ - -#define TEMP_LTGR_LTG_POSS 0U -#define TEMP_LTGR_LTG_POSE 20U -#define TEMP_LTGR_LTG_MSK BITS(TEMP_LTGR_LTG_POSS,TEMP_LTGR_LTG_POSE) - -/****************** Bit definition for TEMP_HTGR register ************************/ - -#define TEMP_HTGR_HTG_POSS 0U -#define TEMP_HTGR_HTG_POSE 20U -#define TEMP_HTGR_HTG_MSK BITS(TEMP_HTGR_HTG_POSS,TEMP_HTGR_HTG_POSE) - -/****************** Bit definition for TEMP_TBDR register ************************/ - -#define TEMP_TBDR_TBD_POSS 0U -#define TEMP_TBDR_TBD_POSE 15U -#define TEMP_TBDR_TBD_MSK BITS(TEMP_TBDR_TBD_POSS,TEMP_TBDR_TBD_POSE) - -/****************** Bit definition for TEMP_TCALBDR register ************************/ - -#define TEMP_TCALBDR_TCAL_POSS 0U -#define TEMP_TCALBDR_TCAL_POSE 16U -#define TEMP_TCALBDR_TCAL_MSK BITS(TEMP_TCALBDR_TCAL_POSS,TEMP_TCALBDR_TCAL_POSE) - -/****************** Bit definition for TEMP_SR register ************************/ - -#define TEMP_SR_TSOUT_POS 31U -#define TEMP_SR_TSOUT_MSK BIT(TEMP_SR_TSOUT_POS) - -#define TEMP_SR_NVLD_POS 25U -#define TEMP_SR_NVLD_MSK BIT(TEMP_SR_NVLD_POS) - -#define TEMP_SR_TCAL_POSS 0U -#define TEMP_SR_TCAL_POSE 24U -#define TEMP_SR_TCAL_MSK BITS(TEMP_SR_TCAL_POSS,TEMP_SR_TCAL_POSE) - -typedef struct -{ - __IO uint32_t WPR; - __IO uint32_t CR; - __I uint32_t DR; - __IO uint32_t PSR; - __IO uint32_t IE; - __I uint32_t IF; - __IO uint32_t IFCR; - __IO uint32_t LTGR; - __IO uint32_t HTGR; - __IO uint32_t TBDR; - __IO uint32_t TCALBDR; - __I uint32_t SR; -} TEMP_TypeDef; - -/****************** Bit definition for IWDT_LOAD register ************************/ - -#define IWDT_LOAD_LOAD_POSS 0U -#define IWDT_LOAD_LOAD_POSE 31U -#define IWDT_LOAD_LOAD_MSK BITS(IWDT_LOAD_LOAD_POSS,IWDT_LOAD_LOAD_POSE) - -/****************** Bit definition for IWDT_VALUE register ************************/ - -#define IWDT_VALUE_VALUE_POSS 0U -#define IWDT_VALUE_VALUE_POSE 31U -#define IWDT_VALUE_VALUE_MSK BITS(IWDT_VALUE_VALUE_POSS,IWDT_VALUE_VALUE_POSE) - -/****************** Bit definition for IWDT_CON register ************************/ - -#define IWDT_CON_CLKS_POS 3U -#define IWDT_CON_CLKS_MSK BIT(IWDT_CON_CLKS_POS) - -#define IWDT_CON_RSTEN_POS 2U -#define IWDT_CON_RSTEN_MSK BIT(IWDT_CON_RSTEN_POS) - -#define IWDT_CON_IE_POS 1U -#define IWDT_CON_IE_MSK BIT(IWDT_CON_IE_POS) - -#define IWDT_CON_EN_POS 0U -#define IWDT_CON_EN_MSK BIT(IWDT_CON_EN_POS) - -/****************** Bit definition for IWDT_INTCLR register ************************/ - -#define IWDT_INTCLR_INTCLR_POSS 0U -#define IWDT_INTCLR_INTCLR_POSE 31U -#define IWDT_INTCLR_INTCLR_MSK BITS(IWDT_INTCLR_INTCLR_POSS,IWDT_INTCLR_INTCLR_POSE) - -/****************** Bit definition for IWDT_RIS register ************************/ - -#define IWDT_RIS_WDTIF_POS 0U -#define IWDT_RIS_WDTIF_MSK BIT(IWDT_RIS_WDTIF_POS) - -/****************** Bit definition for IWDT_LOCK register ************************/ - -#define IWDT_LOCK_LOCK_POS 0U -#define IWDT_LOCK_LOCK_MSK BIT(IWDT_LOCK_LOCK_POS) - -typedef struct -{ - __O uint32_t LOAD; - __I uint32_t VALUE; - __IO uint32_t CON; - __O uint32_t INTCLR; - __I uint32_t RIS; - uint32_t RESERVED0[59] ; - __IO uint32_t LOCK; -} IWDT_TypeDef; - -/****************** Bit definition for WWDT_LOAD register ************************/ - -#define WWDT_LOAD_LOAD_POSS 0U -#define WWDT_LOAD_LOAD_POSE 31U -#define WWDT_LOAD_LOAD_MSK BITS(WWDT_LOAD_LOAD_POSS,WWDT_LOAD_LOAD_POSE) - -/****************** Bit definition for WWDT_VALUE register ************************/ - -#define WWDT_VALUE_VALUE_POSS 0U -#define WWDT_VALUE_VALUE_POSE 31U -#define WWDT_VALUE_VALUE_MSK BITS(WWDT_VALUE_VALUE_POSS,WWDT_VALUE_VALUE_POSE) - -/****************** Bit definition for WWDT_CON register ************************/ - -#define WWDT_CON_WWDTWIN_POSS 4U -#define WWDT_CON_WWDTWIN_POSE 5U -#define WWDT_CON_WWDTWIN_MSK BITS(WWDT_CON_WWDTWIN_POSS,WWDT_CON_WWDTWIN_POSE) - -#define WWDT_CON_CLKS_POS 3U -#define WWDT_CON_CLKS_MSK BIT(WWDT_CON_CLKS_POS) - -#define WWDT_CON_RSTEN_POS 2U -#define WWDT_CON_RSTEN_MSK BIT(WWDT_CON_RSTEN_POS) - -#define WWDT_CON_IE_POS 1U -#define WWDT_CON_IE_MSK BIT(WWDT_CON_IE_POS) - -#define WWDT_CON_EN_POS 0U -#define WWDT_CON_EN_MSK BIT(WWDT_CON_EN_POS) - -/****************** Bit definition for WWDT_INTCLR register ************************/ - -#define WWDT_INTCLR_INTCLR_POSS 0U -#define WWDT_INTCLR_INTCLR_POSE 31U -#define WWDT_INTCLR_INTCLR_MSK BITS(WWDT_INTCLR_INTCLR_POSS,WWDT_INTCLR_INTCLR_POSE) - -/****************** Bit definition for WWDT_RIS register ************************/ - -#define WWDT_RIS_WWDTIF_POS 0U -#define WWDT_RIS_WWDTIF_MSK BIT(WWDT_RIS_WWDTIF_POS) - -/****************** Bit definition for WWDT_LOCK register ************************/ - -#define WWDT_LOCK_LOCK_POS 0U -#define WWDT_LOCK_LOCK_MSK BIT(WWDT_LOCK_LOCK_POS) - -typedef struct -{ - __O uint32_t LOAD; - __I uint32_t VALUE; - __IO uint32_t CON; - __O uint32_t INTCLR; - __I uint32_t RIS; - uint32_t RESERVED0[59]; - __IO uint32_t LOCK; -} WWDT_TypeDef; - -/****************** Bit definition for LP16T_CON0 register ************************/ - -#define LP16T_CON0_PRELOAD_POS 22U -#define LP16T_CON0_PRELOAD_MSK BIT(LP16T_CON0_PRELOAD_POS) - -#define LP16T_CON0_WAVEPOL_POS 21U -#define LP16T_CON0_WAVEPOL_MSK BIT(LP16T_CON0_WAVEPOL_POS) - -#define LP16T_CON0_WAVE_POSS 19U -#define LP16T_CON0_WAVE_POSE 20U -#define LP16T_CON0_WAVE_MSK BITS(LP16T_CON0_WAVE_POSS,LP16T_CON0_WAVE_POSE) - -#define LP16T_CON0_TRIGEN_POSS 17U -#define LP16T_CON0_TRIGEN_POSE 18U -#define LP16T_CON0_TRIGEN_MSK BITS(LP16T_CON0_TRIGEN_POSS,LP16T_CON0_TRIGEN_POSE) - -#define LP16T_CON0_TRIGSEL_POSS 13U -#define LP16T_CON0_TRIGSEL_POSE 15U -#define LP16T_CON0_TRIGSEL_MSK BITS(LP16T_CON0_TRIGSEL_POSS,LP16T_CON0_TRIGSEL_POSE) - -#define LP16T_CON0_PRESC_POSS 9U -#define LP16T_CON0_PRESC_POSE 11U -#define LP16T_CON0_PRESC_MSK BITS(LP16T_CON0_PRESC_POSS,LP16T_CON0_PRESC_POSE) - -#define LP16T_CON0_TRGFLT_POSS 6U -#define LP16T_CON0_TRGFLT_POSE 7U -#define LP16T_CON0_TRGFLT_MSK BITS(LP16T_CON0_TRGFLT_POSS,LP16T_CON0_TRGFLT_POSE) - -#define LP16T_CON0_CKFLT_POSS 3U -#define LP16T_CON0_CKFLT_POSE 4U -#define LP16T_CON0_CKFLT_MSK BITS(LP16T_CON0_CKFLT_POSS,LP16T_CON0_CKFLT_POSE) - -#define LP16T_CON0_CKPOL_POS 1U -#define LP16T_CON0_CKPOL_MSK BIT(LP16T_CON0_CKPOL_POS) - -#define LP16T_CON0_CKSEL_POS 0U -#define LP16T_CON0_CKSEL_MSK BIT(LP16T_CON0_CKSEL_POS) - -/****************** Bit definition for LP16T_CON1 register ************************/ - -#define LP16T_CON1_CNTSTRT_POS 2U -#define LP16T_CON1_CNTSTRT_MSK BIT(LP16T_CON1_CNTSTRT_POS) - -#define LP16T_CON1_SNGSTRT_POS 1U -#define LP16T_CON1_SNGSTRT_MSK BIT(LP16T_CON1_SNGSTRT_POS) - -#define LP16T_CON1_ENABLE_POS 0U -#define LP16T_CON1_ENABLE_MSK BIT(LP16T_CON1_ENABLE_POS) - -/****************** Bit definition for LP16T_ARR register ************************/ - -#define LP16T_ARR_ARR_POSS 0U -#define LP16T_ARR_ARR_POSE 15U -#define LP16T_ARR_ARR_MSK BITS(LP16T_ARR_ARR_POSS,LP16T_ARR_ARR_POSE) - -/****************** Bit definition for LP16T_CNT register ************************/ - -#define LP16T_CNT_CNT_POSS 0U -#define LP16T_CNT_CNT_POSE 15U -#define LP16T_CNT_CNT_MSK BITS(LP16T_CNT_CNT_POSS,LP16T_CNT_CNT_POSE) - -/****************** Bit definition for LP16T_CMP register ************************/ - -#define LP16T_CMP_CMP_POSS 0U -#define LP16T_CMP_CMP_POSE 15U -#define LP16T_CMP_CMP_MSK BITS(LP16T_CMP_CMP_POSS,LP16T_CMP_CMP_POSE) - -/****************** Bit definition for LP16T_IER register ************************/ - -#define LP16T_IER_EXTTRIGIE_POS 2U -#define LP16T_IER_EXTTRIGIE_MSK BIT(LP16T_IER_EXTTRIGIE_POS) - -#define LP16T_IER_ARRMIE_POS 1U -#define LP16T_IER_ARRMIE_MSK BIT(LP16T_IER_ARRMIE_POS) - -#define LP16T_IER_CMPMIE_POS 0U -#define LP16T_IER_CMPMIE_MSK BIT(LP16T_IER_CMPMIE_POS) - -/****************** Bit definition for LP16T_ISR register ************************/ - -#define LP16T_ISR_EXTTRIG_POS 2U -#define LP16T_ISR_EXTTRIG_MSK BIT(LP16T_ISR_EXTTRIG_POS) - -#define LP16T_ISR_ARRM_POS 1U -#define LP16T_ISR_ARRM_MSK BIT(LP16T_ISR_ARRM_POS) - -#define LP16T_ISR_CMPM_POS 0U -#define LP16T_ISR_CMPM_MSK BIT(LP16T_ISR_CMPM_POS) - -/****************** Bit definition for LP16T_IFC register ************************/ - -#define LP16T_IFC_EXTTRIG_POS 2U -#define LP16T_IFC_EXTTRIG_MSK BIT(LP16T_IFC_EXTTRIG_POS) - -#define LP16T_IFC_ARRM_POS 1U -#define LP16T_IFC_ARRM_MSK BIT(LP16T_IFC_ARRM_POS) - -#define LP16T_IFC_CMPM_POS 0U -#define LP16T_IFC_CMPM_MSK BIT(LP16T_IFC_CMPM_POS) - -/****************** Bit definition for LP16T_UPDATE register ************************/ - -#define LP16T_UPDATE_UDIS_POS 0U -#define LP16T_UPDATE_UDIS_MSK BIT(LP16T_UPDATE_UDIS_POS) - -/****************** Bit definition for LP16T_SYNCSTAT register ************************/ - -#define LP16T_SYNCSTAT_CMPWBSY_POS 3U -#define LP16T_SYNCSTAT_CMPWBSY_MSK BIT(LP16T_SYNCSTAT_CMPWBSY_POS) - -#define LP16T_SYNCSTAT_ARRWBSY_POS 2U -#define LP16T_SYNCSTAT_ARRWBSY_MSK BIT(LP16T_SYNCSTAT_ARRWBSY_POS) - -#define LP16T_SYNCSTAT_CON1WBSY_POS 1U -#define LP16T_SYNCSTAT_CON1WBSY_MSK BIT(LP16T_SYNCSTAT_CON1WBSY_POS) - -typedef struct -{ - __IO uint32_t CON0; - __IO uint32_t CON1; - __IO uint32_t ARR; - __I uint32_t CNT; - __IO uint32_t CMP; - uint32_t RESERVED0 ; - __IO uint32_t IER; - __I uint32_t ISR; - __O uint32_t IFC; - uint32_t RESERVED1[3] ; - __IO uint32_t UPDATE; - __I uint32_t SYNCSTAT; -} LPTIM_TypeDef; - -/****************** Bit definition for DBGC_IDCODE register ************************/ - -#define DBGC_IDCODE_REV_ID_POSS 16U -#define DBGC_IDCODE_REV_ID_POSE 31U -#define DBGC_IDCODE_REV_ID_MSK BITS(DBGC_IDCODE_REV_ID_POSS,DBGC_IDCODE_REV_ID_POSE) - -#define DBGC_IDCODE_CORE_ID_POSS 12U -#define DBGC_IDCODE_CORE_ID_POSE 15U -#define DBGC_IDCODE_CORE_ID_MSK BITS(DBGC_IDCODE_CORE_ID_POSS,DBGC_IDCODE_CORE_ID_POSE) - -#define DBGC_IDCODE_DEV_ID_POSS 0U -#define DBGC_IDCODE_DEV_ID_POSE 11U -#define DBGC_IDCODE_DEV_ID_MSK BITS(DBGC_IDCODE_DEV_ID_POSS,DBGC_IDCODE_DEV_ID_POSE) - -/****************** Bit definition for DBGC_CR register ************************/ - -#define DBGC_CR_DBG_STANDBY_POS 3U -#define DBGC_CR_DBG_STANDBY_MSK BIT(DBGC_CR_DBG_STANDBY_POS) - -#define DBGC_CR_DBG_STOP2_POS 2U -#define DBGC_CR_DBG_STOP2_MSK BIT(DBGC_CR_DBG_STOP2_POS) - -#define DBGC_CR_DBG_STOP1_POS 1U -#define DBGC_CR_DBG_STOP1_MSK BIT(DBGC_CR_DBG_STOP1_POS) - -#define DBGC_CR_DBG_SLEEP_POS 0U -#define DBGC_CR_DBG_SLEEP_MSK BIT(DBGC_CR_DBG_SLEEP_POS) - -/****************** Bit definition for DBGC_APB1FZ register ************************/ - -#define DBGC_APB1FZ_CAN_STOP_POS 12U -#define DBGC_APB1FZ_CAN_STOP_MSK BIT(DBGC_APB1FZ_CAN_STOP_POS) - -#define DBGC_APB1FZ_I2C1_SMBUS_TO_POS 9U -#define DBGC_APB1FZ_I2C1_SMBUS_TO_MSK BIT(DBGC_APB1FZ_I2C1_SMBUS_TO_POS) - -#define DBGC_APB1FZ_I2C0_SMBUS_TO_POS 8U -#define DBGC_APB1FZ_I2C0_SMBUS_TO_MSK BIT(DBGC_APB1FZ_I2C0_SMBUS_TO_POS) - -#define DBGC_APB1FZ_TIM7_STOP_POS 7U -#define DBGC_APB1FZ_TIM7_STOP_MSK BIT(DBGC_APB1FZ_TIM7_STOP_POS) - -#define DBGC_APB1FZ_TIM6_STOP_POS 6U -#define DBGC_APB1FZ_TIM6_STOP_MSK BIT(DBGC_APB1FZ_TIM6_STOP_POS) - -#define DBGC_APB1FZ_TIM5_STOP_POS 5U -#define DBGC_APB1FZ_TIM5_STOP_MSK BIT(DBGC_APB1FZ_TIM5_STOP_POS) - -#define DBGC_APB1FZ_TIM4_STOP_POS 4U -#define DBGC_APB1FZ_TIM4_STOP_MSK BIT(DBGC_APB1FZ_TIM4_STOP_POS) - -#define DBGC_APB1FZ_TIM3_STOP_POS 3U -#define DBGC_APB1FZ_TIM3_STOP_MSK BIT(DBGC_APB1FZ_TIM3_STOP_POS) - -#define DBGC_APB1FZ_TIM2_STOP_POS 2U -#define DBGC_APB1FZ_TIM2_STOP_MSK BIT(DBGC_APB1FZ_TIM2_STOP_POS) - -#define DBGC_APB1FZ_TIM1_STOP_POS 1U -#define DBGC_APB1FZ_TIM1_STOP_MSK BIT(DBGC_APB1FZ_TIM1_STOP_POS) - -#define DBGC_APB1FZ_TIM0_STOP_POS 0U -#define DBGC_APB1FZ_TIM0_STOP_MSK BIT(DBGC_APB1FZ_TIM0_STOP_POS) - -/****************** Bit definition for DBGC_APB2FZ register ************************/ - -#define DBGC_APB2FZ_RTC_STOP_POS 10U -#define DBGC_APB2FZ_RTC_STOP_MSK BIT(DBGC_APB2FZ_RTC_STOP_POS) - -#define DBGC_APB2FZ_WWDT_STOP_POS 9U -#define DBGC_APB2FZ_WWDT_STOP_MSK BIT(DBGC_APB2FZ_WWDT_STOP_POS) - -#define DBGC_APB2FZ_IWDT_STOP_POS 8U -#define DBGC_APB2FZ_IWDT_STOP_MSK BIT(DBGC_APB2FZ_IWDT_STOP_POS) - -#define DBGC_APB2FZ_LPTIM0_STOP_POS 0U -#define DBGC_APB2FZ_LPTIM0_STOP_MSK BIT(DBGC_APB2FZ_LPTIM0_STOP_POS) - -typedef struct -{ - __I uint32_t IDCODE; - __IO uint32_t CR; - __IO uint32_t APB1FZ; - __IO uint32_t APB2FZ; -} DBGC_TypeDef; - - -/* Base addresses */ -#define SRAM_BASE (0x20000000UL) -#define APB1_BASE (0x40000000UL) -#define APB2_BASE (0x40040000UL) -#define AHB_BASE (0x40080000UL) - -/* Timer memory map */ -#define TIMER0_BASE (APB1_BASE + 0x0000) -#define TIMER1_BASE (APB1_BASE + 0x0400) -#define TIMER2_BASE (APB1_BASE + 0x0800) -#define TIMER3_BASE (APB1_BASE + 0x0C00) -#define TIMER4_BASE (APB1_BASE + 0x1000) -#define TIMER5_BASE (APB1_BASE + 0x1400) -#define TIMER6_BASE (APB1_BASE + 0x1800) -#define TIMER7_BASE (APB1_BASE + 0x1C00) - -/* SPI memory map */ -#define SPI0_BASE (APB1_BASE + 0x6000) -#define SPI1_BASE (APB1_BASE + 0x6400) -#define SPI2_BASE (APB1_BASE + 0x6800) - -/* I2C memory map */ -#define I2C0_BASE (APB1_BASE + 0x8000) -#define I2C1_BASE (APB1_BASE + 0x8400) - -/* AHB peripherals */ -#define SYSTEM_BASE (AHB_BASE + 0x0000) -#define GPIOA_BASE (AHB_BASE + 0x4000) -#define GPIOB_BASE (AHB_BASE + 0x4040) -#define GPIOC_BASE (AHB_BASE + 0x4080) -#define GPIOD_BASE (AHB_BASE + 0x40C0) -#define GPIOE_BASE (AHB_BASE + 0x4100) -#define GPIOF_BASE (AHB_BASE + 0x4140) -#define GPIOG_BASE (AHB_BASE + 0x4180) -#define GPIOH_BASE (AHB_BASE + 0x41C0) -#define EXTI_BASE (AHB_BASE + 0x4300) -#define CRC_BASE (AHB_BASE + 0x5000) -#define CALC_BASE (AHB_BASE + 0x5400) -#define TRNG_BASE (AHB_BASE + 0x5C00) -#define CRYPT_BASE (AHB_BASE + 0x5800) - -#define SYSCFG_BASE (SYSTEM_BASE + 0x0000) -#define CMU_BASE (SYSTEM_BASE + 0x0400) -#define RMU_BASE (SYSTEM_BASE + 0x0800) -#define PMU_BASE (SYSTEM_BASE + 0x0C00) -#define MSC_BASE (SYSTEM_BASE + 0x1000) -#define PIS_BASE (SYSTEM_BASE + 0x6000) - -/* APB1 peripherals */ -#define CAN0_BASE (APB1_BASE + 0xB000) -#define USART0_BASE (APB1_BASE + 0x5000) -#define USART1_BASE (APB1_BASE + 0x5400) -#define UART0_BASE (APB1_BASE + 0x4000) -#define UART1_BASE (APB1_BASE + 0x4400) -#define UART2_BASE (APB1_BASE + 0x4800) -#define UART3_BASE (APB1_BASE + 0x4C00) -#define DMA0_BASE (APB1_BASE + 0xC000) - -/* APB2 peripherals */ -#define LPTIM0_BASE (APB2_BASE + 0x0000) -#define LPUART0_BASE (APB2_BASE + 0x1000) -#define DBGC_BASE (APB2_BASE + 0xA000) -#define WWDT_BASE (APB2_BASE + 0x6000) -#define IWDT_BASE (APB2_BASE + 0x6400) -#define RTC_BASE (APB2_BASE + 0x8400) -#define LCD_BASE (APB2_BASE + 0x7000) -#define ADC0_BASE (APB2_BASE + 0x2000) -#define ADC1_BASE (APB2_BASE + 0x2400) -#define ACMP0_BASE (APB2_BASE + 0x3000) -#define ACMP1_BASE (APB2_BASE + 0x3400) -#define OPAMP_BASE (APB2_BASE + 0x4000) -#define DAC0_BASE (APB2_BASE + 0x5000) -#define BKPC_BASE (APB2_BASE + 0x8000) -#define TEMP_BASE (APB2_BASE + 0x8800) - -/* RTC Peripheral declaration */ -#define RTC ((RTC_TypeDef *)RTC_BASE) - -/* GPIO Peripheral_declaration */ -#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *)GPIOH_BASE) -#define EXTI ((EXTI_TypeDef *)EXTI_BASE) - -#define CRC ((CRC_TypeDef *)CRC_BASE) -#define TRNG ((TRNG_TypeDef *)TRNG_BASE) -#define CALC ((CALC_TypeDef *)CALC_BASE) -#define CRYPT ((CRYPT_TypeDef *)CRYPT_BASE) -#define PIS ((PIS_TypeDef *)PIS_BASE) - -/* LCD Peripheral declaration */ -#define LCD ((LCD_TypeDef *)LCD_BASE) -/* ADC Peripheral declaration */ -#define ADC0 ((ADC_TypeDef *)ADC0_BASE) -#define ADC1 ((ADC_TypeDef *)ADC1_BASE) -/* ACMP Peripheral declaration */ -#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) -#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) -/* OPAMP Peripheral declaration */ -#define OPAMP ((OPAMP_TypeDef *)OPAMP_BASE) -/* DAC Peripheral declaration */ -#define DAC0 ((DAC_TypeDef *)DAC0_BASE) -/* TEMP Peripheral declaration */ -#define TEMP ((TEMP_TypeDef *)TEMP_BASE) -/* BKPC Peripheral declaration */ -#define BKPC ((BKPC_TypeDef *)BKPC_BASE) - -/* Timer Peripheral_declaration */ -#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) -#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) -#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) -#define TIMER3 ((TIMER_TypeDef *)TIMER3_BASE) -#define TIMER4 ((TIMER_TypeDef *)TIMER4_BASE) -#define TIMER5 ((TIMER_TypeDef *)TIMER5_BASE) -#define TIMER6 ((TIMER_TypeDef *)TIMER6_BASE) -#define TIMER7 ((TIMER_TypeDef *)TIMER7_BASE) - -#define AD16C4T0 TIMER0 -#define GP16C4T0 TIMER6 -#define GP16C2T0 TIMER2 -#define GP16C2T1 TIMER3 -#define BS16T0 TIMER1 -#define BS16T1 TIMER4 -#define BS16T2 TIMER5 -#define BS16T3 TIMER7 - -/* SPI Peripheral_declaration */ -#define SPI0 ((SPI_TypeDef *)SPI0_BASE) -#define SPI1 ((SPI_TypeDef *)SPI1_BASE) -#define SPI2 ((SPI_TypeDef *)SPI2_BASE) - -/* I2C Peripheral_declaration */ -#define I2C0 ((I2C_TypeDef *)I2C0_BASE) -#define I2C1 ((I2C_TypeDef *)I2C1_BASE) - -/* CAN Peripheral_declaration */ -#define CAN0 ((CAN_TypeDef *)CAN0_BASE) - -/* DMA Peripheral_declaration */ -#define DMA0 ((DMA_TypeDef *)DMA0_BASE) - -/* UART Peripheral_declaration */ -#define USART0 ((USART_TypeDef *)USART0_BASE) -#define USART1 ((USART_TypeDef *)USART1_BASE) -#define UART0 ((UART_TypeDef *)UART0_BASE) -#define UART1 ((UART_TypeDef *)UART1_BASE) -#define UART2 ((UART_TypeDef *)UART2_BASE) -#define UART3 ((UART_TypeDef *)UART3_BASE) -#define LPTIM0 ((LPTIM_TypeDef *)LPTIM0_BASE) -#define LPUART0 ((LPUART_TypeDef *)LPUART0_BASE) -#define DBGC ((DBGC_TypeDef *)DBGC_BASE) -#define WWDT ((WWDT_TypeDef *)WWDT_BASE) -#define IWDT ((IWDT_TypeDef *)IWDT_BASE) - -#define SYSCFG ((SYSCFG_TypeDef *)SYSCFG_BASE) -#define CMU ((CMU_TypeDef *)CMU_BASE) -#define RMU ((RMU_TypeDef *)RMU_BASE) -#define PMU ((PMU_TypeDef *)PMU_BASE) -#define MSC ((MSC_TypeDef *)MSC_BASE) - -#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h deleted file mode 100644 index 8c39f28af2e318c32c2f04789b94e86565fc83eb..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h +++ /dev/null @@ -1,374 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_acmp.h - * @brief Header file of ACMP module driver. - * - * @version V1.0 - * @date 13 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_ACMP_H__ -#define __ALD_ACMP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup ACMP - * @{ - */ - -/** @defgroup ACMP_Public_Types ACMP Public Types - * @{ - */ - -/** - * @brief Acmp interrupt - */ -typedef enum -{ - ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */ - ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */ -} acmp_it_t; - -/** - * @brief Acmp interrupt - */ -typedef enum -{ - ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */ - ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */ -} acmp_flag_t; - -/** - * @brief Acmp interrupt flag - */ -typedef enum -{ - ACMP_STATUS_EDGE = (1U << 0), /**< Edge interrupt flag */ - ACMP_STATUS_WARMUP = (1U << 1), /**< Warm up interrupt flag */ -} acmp_status_t; - -/** - * @brief Acmp positive input - */ -typedef enum -{ - ACMP_POS_CH0 = 0, /**< Channel 0 as positive input */ - ACMP_POS_CH1 = 1, /**< Channel 1 as positive input */ - ACMP_POS_CH2 = 2, /**< Channel 2 as positive input */ - ACMP_POS_CH3 = 3, /**< Channel 3 as positive input */ - ACMP_POS_CH4 = 4, /**< Channel 4 as positive input */ - ACMP_POS_CH5 = 5, /**< Channel 5 as positive input */ - ACMP_POS_CH6 = 6, /**< Channel 6 as positive input */ - ACMP_POS_CH7 = 7, /**< Channel 7 as positive input */ -} acmp_pos_input_t; - -/** - * @brief Acmp negative input - */ -typedef enum -{ - ACMP_NEG_CH0 = 0, /**< Channel 0 as negative input */ - ACMP_NEG_CH1 = 1, /**< Channel 1 as negative input */ - ACMP_NEG_CH2 = 2, /**< Channel 2 as negative input */ - ACMP_NEG_CH3 = 3, /**< Channel 3 as negative input */ - ACMP_NEG_CH4 = 4, /**< Channel 4 as negative input */ - ACMP_NEG_CH5 = 5, /**< Channel 5 as negative input */ - ACMP_NEG_CH6 = 6, /**< Channel 6 as negative input */ - ACMP_NEG_CH7 = 7, /**< Channel 7 as negative input */ - ACMP_NEG_1V25 = 8, /**< 1.25v as negative input */ - ACMP_NEG_2V5 = 9, /**< 2.5v as negative input */ - ACMP_NEG_VDD = 10, /**< VDD as negative input */ - ACMP_NEG_CAP = 11, /**< Capacitive as negative input */ - ACMP_NEG_DAC0_CH0 = 12, /**< DAC0 channel 0 as negative input */ - ACMP_NEG_DAC0_CH1 = 13, /**< DAC0 channel 1 as negative input */ -} acmp_neg_input_t; - -/** - * @brief Acmp mode - */ -typedef enum -{ - ACMP_ULTRA_LOW_POWER = 0, /**< Ultra low power mode */ - ACMP_LOW_POWER = 1, /**< Low power mode */ - ACMP_MIDDLE_POWER = 2, /**< Middle power mode */ - ACMP_HIGH_POWER = 3, /**< High power mode */ -} acmp_mode_t; - -/** - * @brief Acmp warm-up time - */ -typedef enum -{ - ACMP_4_PCLK = 0, /**< 4 hfperclk cycles */ - ACMP_8_PCLK = 1, /**< 4 hfperclk cycles */ - ACMP_16_PCLK = 2, /**< 4 hfperclk cycles */ - ACMP_32_PCLK = 3, /**< 4 hfperclk cycles */ - ACMP_64_PCLK = 4, /**< 4 hfperclk cycles */ - ACMP_128_PCLK = 5, /**< 4 hfperclk cycles */ - ACMP_256_PCLK = 6, /**< 4 hfperclk cycles */ - ACMP_512_PCLK = 7, /**< 4 hfperclk cycles */ -} acmp_warm_time_t; - -/** - * @brief Acmp hysteresis level - */ -typedef enum -{ - ACMP_HYST_0 = 0, /**< No hysteresis */ - ACMP_HYST_15 = 1, /**< 15mV hysteresis */ - ACMP_HYST_22 = 2, /**< 22mV hysteresis */ - ACMP_HYST_29 = 3, /**< 29mV hysteresis */ - ACMP_HYST_36 = 4, /**< 36mV hysteresis */ - ACMP_HYST_43 = 5, /**< 43mV hysteresis */ - ACMP_HYST_50 = 6, /**< 50mV hysteresis */ - ACMP_HYST_57 = 7, /**< 57mV hysteresis */ -} acmp_hystsel_t; - -/** - * @brief Acmp inactive state - */ -typedef enum -{ - ACMP_INACTVAL_LOW = 0, /**< The inactive value is 0 */ - ACMP_INACTVAL_HIGH = 1, /**< The inactive value is 1 */ -} acmp_inactval_t; - -/** - * @brief which edges set up interrupt - */ -typedef enum -{ - ACMP_EDGE_NONE = 0, /**< Disable EDGE interrupt */ - ACMP_EDGE_FALL = 1, /**< Falling edges set EDGE interrupt */ - ACMP_EDGE_RISE = 2, /**< rise edges set EDGE interrupt */ - ACMP_EDGE_ALL = 3, /**< Falling edges and rise edges set EDGE interrupt */ -} acmp_edge_t; - -/** - * @brief Acmp output function - */ -typedef enum -{ - ACMP_OUT_DISABLE = 0, /**< Disable acmp output */ - ACMP_OUT_ENABLE = 1, /**< Enable acmp output */ -} acmp_out_func_t; - -/** - * @brief Acmp warm-up interrupt function - */ -typedef enum -{ - ACMP_WARM_DISABLE = 0, /**< Disable acmp warm-up interrupt */ - ACMP_WARM_ENABLE = 1, /**< Enable acmp warm-up interrupt */ -} acmp_warm_it_func; - -/** - * @brief Acmp gpio output invert - */ -typedef enum -{ - ACMP_GPIO_NO_INV = 0, /**< Acmp output to gpio is not inverted */ - ACMP_GPIO_INV = 1, /**< Acmp output to gpio is inverted */ -} acmp_invert_t; - -/** - * @brief The location of the acmp i/o pin - */ -typedef enum -{ - ACMP_LOCATION_O = 0, /**< Location 0 */ - ACMP_LOCATION_1 = 1, /**< Location 1 */ - ACMP_LOCATION_2 = 2, /**< Location 2 */ -} acmp_location_t; - -/** - * @brief Acmp output config structure definition - */ -typedef struct -{ - acmp_out_func_t out_func; /**< Acmp output function */ - acmp_invert_t gpio_inv; /**< If invert gpio output */ - acmp_location_t location; /**< The location of acmp I/0 pin */ -} acmp_output_config_t; - -/** - * @brief Acmp init structure definition - */ -typedef struct -{ - acmp_mode_t mode; /**< Acmp operation mode */ - acmp_warm_time_t warm_time; /**< Acmp warm up time */ - acmp_hystsel_t hystsel; /**< Acmp hysteresis level */ - acmp_warm_it_func warm_func; /**< Acmp warm-up interrupt enable/disable */ - acmp_pos_input_t pos_port; /**< Acmp positive port select */ - acmp_neg_input_t neg_port; /**< Acmp negative port select */ - acmp_inactval_t inactval; /**< Acmp inavtive output value */ - acmp_edge_t edge; /** Select edges to set interrupt flag */ - uint8_t vdd_level; /** Select scaling factor for CDD reference level, MAX is 63 */ -} acmp_init_t; - -/** - * @brief ACMP Handle Structure definition - */ -typedef struct acmp_handle_s -{ - ACMP_TypeDef *perh; /**< Register base address */ - acmp_init_t init; /**< ACMP required parameters */ - lock_state_t lock; /**< Locking object */ - - void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp warm-up complete callback */ - void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp edge trigger callback */ -} acmp_handle_t; -/** - * @} - */ - -/** @defgroup ACMP_Public_Macros ACMP Public Macros - * @{ - */ -#define ACMP_ENABLE(handle) (SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK)) -#define ACMP_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK)) -/** - * @} - */ - -/** @defgroup ACMP_Private_Macros ACMP Private Macros - * @{ - */ -#define IS_ACMP_TYPE(x) (((x) == ACMP0) || \ - ((x) == ACMP1)) -#define IS_ACMP_MODE_TYPE(x) (((x) == ACMP_ULTRA_LOW_POWER) || \ - ((x) == ACMP_LOW_POWER) || \ - ((x) == ACMP_MIDDLE_POWER) || \ - ((x) == ACMP_HIGH_POWER)) -#define IS_ACMP_IT_TYPE(x) (((x) == ACMP_IT_EDGE) || \ - ((x) == ACMP_IT_WARMUP)) -#define IS_ACMP_FLAG_TYPE(x) (((x) == ACMP_FLAG_EDGE) || \ - ((x) == ACMP_FLAG_WARMUP)) -#define IS_ACMP_STATUS_TYPE(x) (((x) == ACMP_STATUS_EDGE) || \ - ((x) == ACMP_STATUS_WARMUP)) -#define IS_ACMP_POS_INPUT_TYPE(x) (((x) == ACMP_POS_CH0) || \ - ((x) == ACMP_POS_CH1) || \ - ((x) == ACMP_POS_CH2) || \ - ((x) == ACMP_POS_CH3) || \ - ((x) == ACMP_POS_CH4) || \ - ((x) == ACMP_POS_CH5) || \ - ((x) == ACMP_POS_CH6) || \ - ((x) == ACMP_POS_CH7)) -#define IS_ACMP_NEG_INPUT_TYPE(x) (((x) == ACMP_NEG_CH0) || \ - ((x) == ACMP_NEG_CH1) || \ - ((x) == ACMP_NEG_CH2) || \ - ((x) == ACMP_NEG_CH3) || \ - ((x) == ACMP_NEG_CH4) || \ - ((x) == ACMP_NEG_CH5) || \ - ((x) == ACMP_NEG_CH6) || \ - ((x) == ACMP_NEG_CH7) || \ - ((x) == ACMP_NEG_1V25) || \ - ((x) == ACMP_NEG_2V5) || \ - ((x) == ACMP_NEG_VDD) || \ - ((x) == ACMP_NEG_CAP) || \ - ((x) == ACMP_NEG_DAC0_CH0) || \ - ((x) == ACMP_NEG_DAC0_CH1)) -#define IS_ACMP_WARM_UP_TIME_TYPE(x) (((x) == ACMP_4_PCLK) || \ - ((x) == ACMP_8_PCLK) || \ - ((x) == ACMP_16_PCLK) || \ - ((x) == ACMP_32_PCLK) || \ - ((x) == ACMP_64_PCLK) || \ - ((x) == ACMP_128_PCLK) || \ - ((x) == ACMP_256_PCLK) || \ - ((x) == ACMP_512_PCLK)) -#define IS_ACMP_HYSTSEL_TYPE(x) (((x) == ACMP_HYST_0) || \ - ((x) == ACMP_HYST_15) || \ - ((x) == ACMP_HYST_22) || \ - ((x) == ACMP_HYST_29) || \ - ((x) == ACMP_HYST_36) || \ - ((x) == ACMP_HYST_43) || \ - ((x) == ACMP_HYST_50) || \ - ((x) == ACMP_HYST_57)) -#define IS_ACMP_INACTVAL_TYPE(x) (((x) == ACMP_INACTVAL_LOW) || \ - ((x) == ACMP_INACTVAL_HIGH)) -#define IS_ACMP_EDGE_TYPE(x) (((x) == ACMP_EDGE_NONE) || \ - ((x) == ACMP_EDGE_FALL) || \ - ((x) == ACMP_EDGE_RISE) || \ - ((x) == ACMP_EDGE_ALL)) -#define IS_ACMP_OUT_FUNC_TYPE(x) (((x) == ACMP_OUT_DISABLE) || \ - ((x) == ACMP_OUT_ENABLE)) -#define IS_ACMP_INVERT_TYPE(x) (((x) == ACMP_GPIO_NO_INV) || \ - ((x) == ACMP_GPIO_INV)) -#define IS_ACMP_LOCATION_TYPE(x) (((x) == ACMP_LOCATION_O) || \ - ((x) == ACMP_LOCATION_1) || \ - ((x) == ACMP_LOCATION_2)) -#define IS_ACMP_WARM_FUNC_TYPE(x) (((x) == ACMP_WARM_DISABLE) || \ - ((x) == ACMP_WARM_ENABLE)) -/** - * @} - */ - -/** @addtogroup ACMP_Public_Functions - * @{ - */ - -/** @addtogroup ACMP_Public_Functions_Group1 - * @{ - */ -ald_status_t acmp_init(acmp_handle_t *hperh); - -/** - * @} - */ - -/** @addtogroup ACMP_Public_Functions_Group2 - * @{ - */ -ald_status_t acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state); -ald_status_t acmp_set_interrupt_mask(acmp_handle_t *hperh, acmp_it_t it); -it_status_t acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t it); -ald_status_t acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t it); -flag_status_t acmp_get_status(acmp_handle_t *hperh, acmp_status_t flag); - -/** - * @} - */ - -/** @addtogroup ACMP_Public_Functions_Group3 - * @{ - */ -void acmp_irq_handle(acmp_handle_t *hperh); -ald_status_t acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config); -uint8_t acmp_out_result(acmp_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -extern "C" -} -#endif - -#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h deleted file mode 100644 index b4f4f029d13e737bc324e90837a3d1b42d197697..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h +++ /dev/null @@ -1,585 +0,0 @@ -/** - ****************************************************************************** - * @file ald_adc.h - * @brief Header file of ADC Module library. - * - * @version V1.0 - * @date 15 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ****************************************************************************** - */ - -#ifndef __ALD_ADC_H__ -#define __ALD_ADC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" -#include "ald_pis.h" -#include "ald_timer.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/** @defgroup ADC_Pubulic_Types ADC Pubulic Types - * @{ - */ - -/** - * @brief ADC State structures definition - */ -typedef enum -{ - ADC_STATE_RESET = 0x0, /**< ADC not yet initialized or disabled */ - ADC_STATE_READY = 0x1, /**< ADC peripheral ready for use */ - ADC_STATE_BUSY_INTERNAL = 0x2, /**< ADC is busy to internal process */ - ADC_STATE_TIMEOUT = 0x4, /**< TimeOut occurrence */ - ADC_STATE_ERROR = 0x10, /**< Internal error occurrence */ - ADC_STATE_NM_BUSY = 0x100, /**< Conversion on group normal is ongoing or can occur */ - ADC_STATE_NM_EOC = 0x200, /**< Conversion data available on group normal */ - ADC_STATE_IST_BUSY = 0x1000, /**< Conversion on group insert is ongoing or can occur */ - ADC_STATE_IST_EOC = 0x2000, /**< Conversion data available on group insert */ - ADC_STATE_AWD = 0x10000, /**< Out-of-window occurrence of analog watchdog */ -} adc_state_t; - -/** - *@brief ADC Error Code - */ -typedef enum -{ - ADC_ERROR_NONE = 0x0, /**< No error */ - ADC_ERROR_INTERNAL = 0x1, /**< ADC IP internal error*/ - ADC_ERROR_OVR = 0x2, /**< Overrun error */ - ADC_ERROR_DMA = 0x4, /**< DMA transfer error */ -} adc_error_t; - -/** - *@brief ADC data alignment - */ -typedef enum -{ - ADC_DATAALIGN_RIGHT = 0x0, /**< ADC data alignment right */ - ADC_DATAALIGN_LEFT = 0x1, /**< ADC data alignment left */ -} adc_align_t; - -/** - *@brief ADC scan mode - */ -typedef enum -{ - ADC_SCAN_DISABLE = 0x0, /**< ADC scan disable */ - ADC_SCAN_ENABLE = 0x1, /**< ADC scan enable */ -} adc_scan_t; - -/** - *@brief ADC config hannal trigger the EOC IT mode - */ -typedef enum -{ - ADC_NCHESEL_MODE_ALL = 0x0, /**< ADC set RCHE after convert sequence finish */ - ADC_NCHESEL_MODE_ONE = 0x1, /**< ADC set RCHE after one convert finish */ -} adc_nchesel_t; - -/** - *@brief ADC channels - */ -typedef enum -{ - ADC_CHANNEL_0 = 0x0, /**< ADC channel 0 */ - ADC_CHANNEL_1 = 0x1, /**< ADC channel 1 */ - ADC_CHANNEL_2 = 0x2, /**< ADC channel 2 */ - ADC_CHANNEL_3 = 0x3, /**< ADC channel 3 */ - ADC_CHANNEL_4 = 0x4, /**< ADC channel 4 */ - ADC_CHANNEL_5 = 0x5, /**< ADC channel 5 */ - ADC_CHANNEL_6 = 0x6, /**< ADC channel 6 */ - ADC_CHANNEL_7 = 0x7, /**< ADC channel 7 */ - ADC_CHANNEL_8 = 0x8, /**< ADC channel 8 */ - ADC_CHANNEL_9 = 0x9, /**< ADC channel 9 */ - ADC_CHANNEL_10 = 0xA, /**< ADC channel 10 */ - ADC_CHANNEL_11 = 0xB, /**< ADC channel 11 */ - ADC_CHANNEL_12 = 0xC, /**< ADC channel 12 */ - ADC_CHANNEL_13 = 0xD, /**< ADC channel 13 */ - ADC_CHANNEL_14 = 0xE, /**< ADC channel 14 */ - ADC_CHANNEL_15 = 0xF, /**< ADC channel 15 */ - ADC_CHANNEL_16 = 0x10, /**< ADC channel 16 */ - ADC_CHANNEL_17 = 0x11, /**< ADC channel 17 */ - ADC_CHANNEL_18 = 0x12, /**< ADC channel 18 */ - ADC_CHANNEL_19 = 0x13, /**< ADC channel 19 */ -} adc_channel_t; - -/** - *@brief ADC sampling times - */ -typedef enum -{ - ADC_SAMPLETIME_1 = 0x0, /**< ADC sampling times 1 clk */ - ADC_SAMPLETIME_2 = 0x1, /**< ADC sampling times 2 clk */ - ADC_SAMPLETIME_4 = 0x2, /**< ADC sampling times 4 clk */ - ADC_SAMPLETIME_15 = 0x3, /**< ADC sampling times 15 clk */ -} adc_samp_t; - -/** - *@brief ADC rank into normal group - */ -typedef enum -{ - ADC_NC_RANK_1 = 0x1, /**< ADC normal channel rank 1 */ - ADC_NC_RANK_2 = 0x2, /**< ADC normal channel rank 2 */ - ADC_NC_RANK_3 = 0x3, /**< ADC normal channel rank 3 */ - ADC_NC_RANK_4 = 0x4, /**< ADC normal channel rank 4 */ - ADC_NC_RANK_5 = 0x5, /**< ADC normal channel rank 5 */ - ADC_NC_RANK_6 = 0x6, /**< ADC normal channel rank 6 */ - ADC_NC_RANK_7 = 0x7, /**< ADC normal channel rank 7 */ - ADC_NC_RANK_8 = 0x8, /**< ADC normal channel rank 8 */ - ADC_NC_RANK_9 = 0x9, /**< ADC normal channel rank 9 */ - ADC_NC_RANK_10 = 0xA, /**< ADC normal channel rank 10 */ - ADC_NC_RANK_11 = 0xB, /**< ADC normal channel rank 11 */ - ADC_NC_RANK_12 = 0xC, /**< ADC normal channel rank 12 */ - ADC_NC_RANK_13 = 0xD, /**< ADC normal channel rank 13 */ - ADC_NC_RANK_14 = 0xE, /**< ADC normal channel rank 14 */ - ADC_NC_RANK_15 = 0xF, /**< ADC normal channel rank 15 */ - ADC_NC_RANK_16 = 0x10, /**< ADC normal channel rank 16 */ -} adc_nc_rank_t; - -/** - * @brief ADC rank into insert group - */ -typedef enum -{ - ADC_IH_RANK_1 = 0x1, /**< ADC insert channel rank 1 */ - ADC_IH_RANK_2 = 0x2, /**< ADC insert channel rank 2 */ - ADC_IH_RANK_3 = 0x3, /**< ADC insert channel rank 3 */ - ADC_IH_RANK_4 = 0x4, /**< ADC insert channel rank 4 */ -} adc_ih_rank_t; - -/** - * @brief ADC analog watchdog mode - */ -typedef enum -{ - ADC_ANAWTD_NONE = 0x0, /**< No watch dog */ - ADC_ANAWTD_SING_NM = 0x800200, /**< One normal channel watch dog */ - ADC_ANAWTD_SING_IST = 0x400200, /**< One inset channel Injec watch dog */ - ADC_ANAWTD_SING_NMIST = 0xC00200, /**< One normal and inset channel watch dog */ - ADC_ANAWTD_ALL_NM = 0x800000, /**< All normal channel watch dog */ - ADC_ANAWTD_ALL_IST = 0x400000, /**< All inset channel watch dog */ - ADC_ANAWTD_ALL_NMIST = 0xC00000, /**< All normal and inset channel watch dog */ -} adc_ana_wtd_t; - -/** - * @brief ADC Event type - */ -typedef enum -{ - ADC_AWD_EVENT = (1U << 0), /**< ADC analog watch dog event */ -} adc_event_type_t; - -/** - * @brief ADC interrupts definition - */ -typedef enum -{ - ADC_IT_NH = (1U << 5), /**< ADC it normal */ - ADC_IT_AWD = (1U << 6), /**< ADC it awd */ - ADC_IT_IH = (1U << 7), /**< ADC it insert */ - ADC_IT_OVR = (1U << 26), /**< ADC it overring */ -} adc_it_t; - -/** - * @brief ADC flags definition - */ -typedef enum -{ - ADC_FLAG_AWD = (1U << 0), /**perh->CON1, ADC_CON1_ADCEN_MSK)) -#define ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) -#define ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK)) -#define ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK)) -#define ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET) -#define ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) -#define ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) -/** - * @} - */ - -/** @defgroup ADC_Private_Macros ADC Private Macros - * @{ - */ -#define IS_ADC_IH_RANK_TYPE(x) ((x) <= ADC_IH_RANK_4) -#define IS_ADC_NC_RANK_TYPE(x) ((x) <= ADC_NC_RANK_16) -#define IS_ADC_SAMPLING_TIMES_TYPE(x) (((x) == ADC_SAMPLETIME_1) || \ - ((x) == ADC_SAMPLETIME_2) || \ - ((x) == ADC_SAMPLETIME_4) || \ - ((x) == ADC_SAMPLETIME_15)) -#define IS_ADC_CHANNELS_TYPE(x) ((x) <= ADC_CHANNEL_19) -#define IS_ADC_SCAN_MODE_TYPE(x) (((x) == ADC_SCAN_DISABLE) || \ - ((x) == ADC_SCAN_ENABLE) ) -#define IS_ADC_DATA_ALIGN_TYPE(x) (((x) == ADC_DATAALIGN_RIGHT) || \ - ((x) == ADC_DATAALIGN_LEFT)) -#define IS_ADC_ANALOG_WTD_MODE_TYPE(x) (((x) == ADC_ANAWTD_NONE) || \ - ((x) == ADC_ANAWTD_SING_NM) || \ - ((x) == ADC_ANAWTD_SING_IST) || \ - ((x) == ADC_ANAWTD_SING_NMIST) || \ - ((x) == ADC_ANAWTD_ALL_NM) || \ - ((x) == ADC_ANAWTD_ALL_IST) || \ - ((x) == ADC_ANAWTD_ALL_NMIST)) -#define IS_ADC_IT_TYPE(x) (((x) == ADC_IT_NH) || \ - ((x) == ADC_IT_AWD) || \ - ((x) == ADC_IT_IH) || \ - ((x) == ADC_IT_OVR )) -#define IS_ADC_FLAGS_TYPE(x) (((x) == ADC_FLAG_AWD) || \ - ((x) == ADC_FLAG_NH) || \ - ((x) == ADC_FLAG_IH) || \ - ((x) == ADC_FLAG_OVR) || \ - ((x) == ADC_FLAG_NHS) || \ - ((x) == ADC_FLAG_IHS)) -#define IS_ADC_CLK_DIV_TYPE(x) (((x) == ADC_CKDIV_1) || \ - ((x) == ADC_CKDIV_2) || \ - ((x) == ADC_CKDIV_4) || \ - ((x) == ADC_CKDIV_8) || \ - ((x) == ADC_CKDIV_16) || \ - ((x) == ADC_CKDIV_32) || \ - ((x) == ADC_CKDIV_64) || \ - ((x) == ADC_CKDIV_128)) -#define IS_ADC_NEG_REF_VOLTAGE_TYPE(x) (((x) == ADC_NEG_REF_VSS ) || \ - ((x) == ADC_NEG_REF_VREFN )) -#define IS_POS_REF_VOLTAGE_TYPE(x) (((x) == ADC_POS_REF_VDD) || \ - ((x) == ADC_POS_REF_2V) || \ - ((x) == ADC_POS_REF_VREEFP) || \ - ((x) == ADC_POS_REF_VREEFP_BUF)) -#define IS_ADC_NBR_OF_NM_TYPE(x) ((x) <= ADC_NM_NBR_16) -#define IS_ADC_NBR_OF_IST_TYPE(x) ((x) <= ADC_IST_NBR_4) -#define IS_ADC_DISC_NBR_TYPE(x) ((x) <= ADC_DISC_NBR_8) -#define IS_ADC_CONV_RES_TYPE(x) (((x) == ADC_CONV_RES_12) || \ - ((x) == ADC_CONV_RES_6) || \ - ((x) == ADC_CONV_RES_8) || \ - ((x) == ADC_CONV_RES_10)) -#define IS_ADC_TRIG_MODE_TYPE(x) (((x) == ADC_TRIG_SOFT) || \ - ((x) == ADC_TRIG_PIS) || \ - ((x) == ADC_TRIG_PIS_SOFT)) -#define IS_ADC_TYPE(x) (((x) == ADC0) || \ - ((x) == ADC1)) -#define IS_ADC_NCHESEL_MODE_TYPE(x) (((x) == ADC_NCHESEL_MODE_ALL) || \ - ((x) == ADC_NCHESEL_MODE_ONE)) -#define IS_ADC_EVENT_TYPE(x) ((x) == ADC_AWD_EVENT) -#define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xfff) -#define IS_HTR_TYPE(x) ((x) <= 0xfff) -#define IS_LTR_TYPE(x) ((x) <= 0xfff) -/** - * @} - */ - -/** @addtogroup ADC_Public_Functions - * @{ - */ - -/** @addtogroup ADC_Public_Functions_Group1 - * @{ - */ -ald_status_t adc_init(adc_handle_t *hperh); -ald_status_t adc_reset(adc_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup ADC_Public_Functions_Group2 - * @{ - */ -ald_status_t adc_normal_start(adc_handle_t *hperh); -ald_status_t adc_normal_stop(adc_handle_t *hperh); -ald_status_t adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); -ald_status_t adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout); -ald_status_t adc_normal_start_by_it(adc_handle_t *hperh); -ald_status_t adc_normal_stop_by_it(adc_handle_t *hperh); -#ifdef ALD_DMA -ald_status_t adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); -ald_status_t adc_stop_by_dma(adc_handle_t *hperh); -ald_status_t adc_timer_trigger_adc_by_dma(adc_timer_config_t *config); -#endif -uint32_t adc_normal_get_value(adc_handle_t *hperh); -ald_status_t adc_insert_start(adc_handle_t *hperh); -ald_status_t adc_insert_stop(adc_handle_t *hperh); -ald_status_t adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); -ald_status_t adc_insert_start_by_it(adc_handle_t *hperh); -ald_status_t adc_insert_stop_by_it(adc_handle_t *hperh); -uint32_t adc_insert_get_value(adc_handle_t *hperh, adc_ih_rank_t ih_rank); -void adc_irq_handler(adc_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup ADC_Public_Functions_Group3 - * @{ - */ -ald_status_t adc_normal_channel_config(adc_handle_t *hperh, adc_channel_conf_t *config); -ald_status_t adc_insert_channel_config(adc_handle_t *hperh, adc_ih_conf_t *config); -ald_status_t adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config); -void adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state); -it_status_t adc_get_it_status(adc_handle_t *hperh, adc_it_t it); -flag_status_t adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag); -void adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag); -/** - * @} - */ - -/** @addtogroup ADC_Public_Functions_Group4 - * @{ - */ -uint32_t adc_get_state(adc_handle_t *hperh); -uint32_t adc_get_error(adc_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -extern "C" -} -#endif - -#endif /* __ALD_ADC_H */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h deleted file mode 100644 index ebe2e2a479e6c5b0ad29bf96dea38c45cd3e6b27..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h +++ /dev/null @@ -1,485 +0,0 @@ -/** - ****************************************************************************** - * @file ald_can.h - * @brief Header file of CAN Module driver. - * - * @version V1.0 - * @date 16 Apr 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ****************************************************************************** - */ - -#ifndef __ALD_CAN_H -#define __ALD_CAN_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup CAN - * @{ - */ - -/** @defgroup CAN_Public_Types CAN Public Types - * @{ - */ -/** - * @brief ALD State structures definition - */ -typedef enum -{ - CAN_STATE_RESET = 0x00, /**< CAN not yet initialized or disabled */ - CAN_STATE_READY = 0x01, /**< CAN initialized and ready for use */ - CAN_STATE_BUSY = 0x02, /**< CAN process is ongoing */ - CAN_STATE_BUSY_TX = 0x11, /**< CAN process is ongoing */ - CAN_STATE_BUSY_RX = 0x21, /**< CAN process is ongoing */ - CAN_STATE_BUSY_TX_RX = 0x31, /**< CAN process is ongoing */ - CAN_STATE_TIMEOUT = 0x03, /**< CAN in Timeout state */ - CAN_STATE_ERROR = 0x04, /**< CAN error state */ -} can_state_t; - -/** - * @brief CAN Error Code - */ -typedef enum -{ - CAN_ERROR_NONE = 0x00, /**< No error */ - CAN_ERROR_EWG = 0x01, /**< EWG error */ - CAN_ERROR_EPV = 0x02, /**< EPV error */ - CAN_ERROR_BOF = 0x04, /**< BOF error */ - CAN_ERROR_STF = 0x08, /**< Stuff error */ - CAN_ERROR_FOR = 0x10, /**< Form error */ - CAN_ERROR_ACK = 0x20, /**< Acknowledgment error */ - CAN_ERROR_BR = 0x40, /**< Bit recessive */ - CAN_ERROR_BD = 0x80, /**< LEC dominant */ - CAN_ERROR_CRC = 0x100, /**< LEC transfer error */ -} can_error_t; - -/** - * @brief CAN Operating Mode - */ -typedef enum -{ - CAN_MODE_NORMAL = 0x00, /**< Normal mode */ - CAN_MODE_LOOPBACK = 0x01, /**< Loopback mode */ - CAN_MODE_SILENT = 0x02, /**< Silent mode */ - CAN_MODE_SILENT_LOOPBACK = 0x03, /**< Loopback combined with silent mode */ -} can_operate_mode_t; - -/** - * @brief CAN Synchronization Jump Width - */ -typedef enum -{ - CAN_SJW_1 = 0x0, /**< 1 time quantum */ - CAN_SJW_2 = 0x1, /**< 2 time quantum */ - CAN_SJW_3 = 0x2, /**< 3 time quantum */ - CAN_SJW_4 = 0x3, /**< 4 time quantum */ -} can_sjw_t; - -/** - * @brief CAN Time Quantum in Bit Segment 1 - */ -typedef enum -{ - CAN_SEG1_1 = 0x0, /**< 1 time quantum */ - CAN_SEG1_2 = 0x1, /**< 2 time quantum */ - CAN_SEG1_3 = 0x2, /**< 3 time quantum */ - CAN_SEG1_4 = 0x3, /**< 4 time quantum */ - CAN_SEG1_5 = 0x4, /**< 5 time quantum */ - CAN_SEG1_6 = 0x5, /**< 6 time quantum */ - CAN_SEG1_7 = 0x6, /**< 7 time quantum */ - CAN_SEG1_8 = 0x7, /**< 8 time quantum */ - CAN_SEG1_9 = 0x8, /**< 9 time quantum */ - CAN_SEG1_10 = 0x9, /**< 10 time quantum */ - CAN_SEG1_11 = 0xA, /**< 11 time quantum */ - CAN_SEG1_12 = 0xB, /**< 12 time quantum */ - CAN_SEG1_13 = 0xC, /**< 13 time quantum */ - CAN_SEG1_14 = 0xD, /**< 14 time quantum */ - CAN_SEG1_15 = 0xE, /**< 15 time quantum */ - CAN_SEG1_16 = 0xF, /**< 16 time quantum */ -} can_seg1_t; - -/** - * @brief CAN Time Quantum in Bit Segment 2 - */ -typedef enum -{ - CAN_SEG2_1 = 0x0, /**< 1 time quantum */ - CAN_SEG2_2 = 0x1, /**< 2 time quantum */ - CAN_SEG2_3 = 0x2, /**< 3 time quantum */ - CAN_SEG2_4 = 0x3, /**< 4 time quantum */ - CAN_SEG2_5 = 0x4, /**< 5 time quantum */ - CAN_SEG2_6 = 0x5, /**< 6 time quantum */ - CAN_SEG2_7 = 0x6, /**< 7 time quantum */ - CAN_SEG2_8 = 0x7, /**< 8 time quantum */ -} can_seg2_t; - -/** - * @brief CAN Filter Mode - */ -typedef enum -{ - CAN_FILTER_MODE_MASK = 0x0, /**< Identifier mask mode */ - CAN_FILTER_MODE_LIST = 0x1, /**< Identifier list mode */ -} can_filter_mode_t; - -/** - * @brief CAN Filter Scale - */ -typedef enum -{ - CAN_FILTER_SCALE_16 = 0x0, /**< Two 16-bit filters */ - CAN_FILTER_SCALE_32 = 0x1, /**< One 32-bit filter */ -} can_filter_scale_t; - -/** - * @brief CAN Filter fifo - */ -typedef enum -{ - CAN_FILTER_FIFO0 = 0x0, /**< FIFO 0 assignment for filter */ - CAN_FILTER_FIFO1 = 0x1, /**< FIFO 1 assignment for filter */ -} can_filter_fifo_t; - -/** - * @brief CAN Identifier Type - */ -typedef enum -{ - CAN_ID_STD = 0x0, /**< Standard Id */ - CAN_ID_EXT = 0x1, /**< Extended Id */ -} can_id_type_t; - -/** - * @brief CAN Remote Transmission Request - */ -typedef enum -{ - CAN_RTR_DATA = 0x0, /**< Data frame */ - CAN_RTR_REMOTE = 0x1, /**< Remote frame */ -} can_remote_req_t; - -/** - * @brief CAN Transmit Constants - */ -typedef enum -{ - CAN_TX_MAILBOX_0 = 0x0, /**< TX mailbox index 0 */ - CAN_TX_MAILBOX_1 = 0x1, /**< TX mailbox index 1 */ - CAN_TX_MAILBOX_2 = 0x2, /**< TX mailbox index 2 */ - CAN_TX_MAILBOX_NONE = 0x3, /**< MailBox can't be used */ -} can_tx_mailbox_t; - -/** - * @brief CAN Receive fifo Number - */ -typedef enum -{ - CAN_RX_FIFO0 = 0x0, /**< CAN fifo 0 used to receive */ - CAN_RX_FIFO1 = 0x1, /**< CAN fifo 1 used to receive */ -} can_rx_fifo_t; - -/** - * @brief CAN Flags - */ -typedef enum -{ - CAN_FLAG_SLAK = (1U << 1), /**< Sleep acknowledge flag */ - CAN_FLAG_WKU = (1U << 3), /**< Wake up flag */ - CAN_FLAG_SLAKI = (1U << 4), /**< Sleep acknowledge flag */ - CAN_FLAG_RQCP0 = (1U << 20) | (1U << 0), /**< Request MailBox0 flag */ - CAN_FLAG_TXOK0 = (1U << 20) | (1U << 1), /**< Transmission OK MailBox0 flag */ - CAN_FLAG_RQCP1 = (1U << 20) | (1U << 8), /**< Request MailBox1 flag */ - CAN_FLAG_TXOK1 = (1U << 20) | (1U << 9), /**< Transmission OK MailBox1 flag */ - CAN_FLAG_RQCP2 = (1U << 20) | (1U << 16), /**< Request MailBox2 flag */ - CAN_FLAG_TXOK2 = (1U << 20) | (1U << 17), /**< Transmission OK MailBox2 flag */ - CAN_FLAG_TME0 = (1U << 20) | (1U << 26), /**< Transmit mailbox 0 empty flag */ - CAN_FLAG_TME1 = (1U << 20) | (1U << 27), /**< Transmit mailbox 1 empty flag */ - CAN_FLAG_TME2 = (1U << 20) | (1U << 28), /**< Transmit mailbox 2 empty flag */ - CAN_FLAG_FF0 = (2U << 20) | (1U << 3), /**< FIFO 0 Full flag */ - CAN_FLAG_FOV0 = (2U << 20) | (1U << 4), /**< FIFO 0 Overrun flag */ - CAN_FLAG_FF1 = (3U << 20) | (1U << 3), /**< FIFO 1 Full flag */ - CAN_FLAG_FOV1 = (3U << 20) | (1U << 4), /**< FIFO 1 Overrun flag */ - CAN_FLAG_EWG = (4U << 20) | (1U << 0), /**< Error warning flag */ - CAN_FLAG_EPV = (4U << 20) | (1U << 1), /**< Error passive flag */ - CAN_FLAG_BOF = (4U << 20) | (1U << 2), /**< Bus-Off flag */ -} can_flag_t; - -/** - * @brief CAN Interrupts - */ -typedef enum -{ - CAN_IT_TME = (1U << 0), /**< Transmit mailbox empty interrupt bit */ - CAN_IT_FMP0 = (1U << 1), /**< FIFO0 message pending interrupt bit */ - CAN_IT_FF0 = (1U << 2), /**< FIFO0 full interrupt bit */ - CAN_IT_FOV0 = (1U << 3), /**< FIFO0 overrun interrupt bit */ - CAN_IT_FMP1 = (1U << 4), /**< FIFO1 message pending interrupt bit */ - CAN_IT_FF1 = (1U << 5), /**< FIFO1 full interrupt bit */ - CAN_IT_FOV1 = (1U << 6), /**< FIFO1 overrun interrupt bit */ - CAN_IT_EWG = (1U << 8), /**< Error warning interrupt bit */ - CAN_IT_EPV = (1U << 9), /**< Error passive interrupt bit */ - CAN_IT_BOF = (1U << 10), /**< Bus-off interrupt bit */ - CAN_IT_LEC = (1U << 11), /**< Last error code interrupt bit */ - CAN_IT_ERR = (1U << 15), /**< Error interrupt bit */ - CAN_IT_WKU = (1U << 16), /**< wake-up interrupt bit */ - CAN_IT_SLK = (1U << 17), /**< sleep interrupt bit */ -} can_it_t; - -/** - * @brief CAN filter configuration structure definition - */ -typedef struct -{ - uint32_t id_high; /**< Specifies the filter identification number */ - uint32_t id_low; /**< Specifies the filter identification number */ - uint32_t mask_id_high; /**< Specifies the filter mask number or identification number */ - uint32_t mask_id_low; /**< Specifies the filter mask number or identification number */ - can_filter_fifo_t fifo; /**< Specifies the fifo (0 or 1) which will be assigned to the filter. */ - uint32_t number; /**< Specifies the filter which will be initialized. */ - can_filter_mode_t mode; /**< Specifies the filter mode to be initialized. */ - can_filter_scale_t scale; /**< Specifies the filter scale. */ - type_func_t active; /**< Enable or disable the filter. */ - uint32_t bank_number; /**< Select the start slave bank filter. */ -} can_filter_t; - -/** - * @brief CAN init structure definition - */ -typedef struct -{ - uint32_t psc; /**< Specifies the length of a time quantum. */ - can_operate_mode_t mode; /**< Specifies the CAN operating mode. */ - can_sjw_t sjw; /**< Specifies the maximum number of time quanta the CAN hardware is - allowed to lengthen or shorten a bit to perform resynchronization. */ - can_seg1_t seg1; /**< Specifies the number of time quanta in Bit Segment 1. */ - can_seg2_t seg2; /**< Specifies the number of time quanta in Bit Segment 2. */ - type_func_t ttcm; /**< Enable or disable the time triggered communication mode. */ - type_func_t abom; /**< Enable or disable the automatic bus-off management. */ - type_func_t awk; /**< Enable or disable the automatic wake-up mode. */ - type_func_t artx; /**< Enable or disable the non-automatic retransmission mode. */ - type_func_t rfom; /**< Enable or disable the Receive fifo Locked mode. */ - type_func_t txmp; /**< Enable or disable the transmit fifo priority. */ -} can_init_t; - -/** - * @brief CAN Tx message structure definition - */ -typedef struct -{ - uint32_t std; /**< Specifies the standard identifier. */ - uint32_t ext; /**< Specifies the extended identifier. */ - can_id_type_t type; /**< Specifies the type of identifier for the message that will be transmitted. */ - can_remote_req_t rtr; /**< Specifies the type of frame for the message that will be transmitted. */ - uint32_t len; /**< Specifies the length of the frame that will be transmitted. */ - uint8_t data[8]; /**< Contains the data to be transmitted. */ -} can_tx_msg_t; - -/** - * @brief CAN Rx message structure definition - */ -typedef struct -{ - uint32_t std; /**< Specifies the standard identifier. */ - uint32_t ext; /**< Specifies the extended identifier. */ - can_id_type_t type; /**< Specifies the type of identifier for the message that will be received. */ - can_remote_req_t rtr; /**< Specifies the type of frame for the received message. */ - uint32_t len; /**< Specifies the length of the frame that will be received. */ - uint8_t data[8]; /**< Contains the data to be received. */ - uint32_t fmi; /**< Specifies the index of the filter the message stored in the mailbox passes through. */ - can_rx_fifo_t num; /**< Specifies the receive fifo number. */ -} can_rx_msg_t; - -/** - * @brief CAN handle Structure definition - */ -typedef struct can_handle_s -{ - CAN_TypeDef *perh; /**< Register base address */ - can_init_t init; /**< CAN required parameters */ - can_rx_msg_t *rx_msg; /**< Pointer to receive message */ - lock_state_t lock; /**< CAN locking object */ - can_state_t state; /**< CAN communication state */ - can_error_t err; /**< CAN Error code */ - - void (*tx_cplt_cbk)(struct can_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct can_handle_s *arg); /**< Rx completed callback */ - void (*error_cbk)(struct can_handle_s *arg); /**< error callback */ -} can_handle_t; -/** - * @} - */ - -/** @defgroup CAN_Public_Macro CAN Public Macros - * @{ - */ -#define CAN_RESET_HANDLE_STATE(x) ((x)->state = CAN_STATE_RESET) -#define CAN_RX_MSG_PENDING(x, y) (((y) == CAN_RX_FIFO0) ? \ - (READ_BIT((x)->perh->RXF0, CAN_RXF0_PEND_MSK)) : (READ_BIT((x)->perh->RXF1, CAN_RXF1_PEND_MSK))) -#define CAN_DBG_FREEZE(x, y) (MODIFY_REG((x)->perh->CON, CAN_CON_DBGSTP_MSK, (y) << CAN_CON_DBGSTP_POS)) -/** - * @} - */ - -/** @defgroup CAN_Private_Macros CAN Private Macros - * @{ - */ -#define IS_CAN_ALL(x) ((x) == CAN0) -#define IS_CAN_FILTER_NUMBER(x) ((x) <= 13) -#define IS_CAN_MODE(x) (((x) == CAN_MODE_NORMAL) || \ - ((x) == CAN_MODE_LOOPBACK) || \ - ((x) == CAN_MODE_SILENT) || \ - ((x) == CAN_MODE_SILENT_LOOPBACK)) -#define IS_CAN_SJW(x) (((x) == CAN_SJW_1) || \ - ((x) == CAN_SJW_2) || \ - ((x) == CAN_SJW_3) || \ - ((x) == CAN_SJW_4)) -#define IS_CAN_BS1(x) ((x) <= CAN_SEG1_16) -#define IS_CAN_BS2(x) ((x) <= CAN_SEG2_8) -#define IS_CAN_FILTER_MODE(x) (((x) == CAN_FILTER_MODE_MASK) || \ - ((x) == CAN_FILTER_MODE_LIST)) -#define IS_CAN_FILTER_SCALE(x) (((x) == CAN_FILTER_SCALE_16) || \ - ((x) == CAN_FILTER_SCALE_32)) -#define IS_CAN_FILTER_FIFO(x) (((x) == CAN_FILTER_FIFO0) || \ - ((x) == CAN_FILTER_FIFO1)) -#define IS_CAN_IDTYPE(x) (((x) == CAN_ID_STD) || \ - ((x) == CAN_ID_EXT)) -#define IS_CAN_RTR(x) (((x) == CAN_RTR_DATA) || ((x) == CAN_RTR_REMOTE)) -#define IS_CAN_FIFO(x) (((x) == CAN_RX_FIFO0) || ((x) == CAN_RX_FIFO1)) -#define IS_CAN_BANKNUMBER(x) ((x) <= 28) -#define IS_CAN_TX_MAILBOX(x) ((x) <= CAN_TX_MAILBOX_NONE) -#define IS_CAN_STDID(x) ((x) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(x) ((x) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DATA_LEN(x) ((x) <= ((uint8_t)0x08)) -#define IS_CAN_PRESCALER(x) (((x) >= 1) && ((x) <= 1024)) -#define IS_CAN_GET_FLAG(x) (((x) == CAN_FLAG_SLAK) || \ - ((x) == CAN_FLAG_WKU) || \ - ((x) == CAN_FLAG_SLAKI) || \ - ((x) == CAN_FLAG_RQCP0) || \ - ((x) == CAN_FLAG_TXOK0) || \ - ((x) == CAN_FLAG_RQCP1) || \ - ((x) == CAN_FLAG_TXOK1) || \ - ((x) == CAN_FLAG_RQCP2) || \ - ((x) == CAN_FLAG_TXOK2) || \ - ((x) == CAN_FLAG_TME0) || \ - ((x) == CAN_FLAG_TME1) || \ - ((x) == CAN_FLAG_TME2) || \ - ((x) == CAN_FLAG_FF0) || \ - ((x) == CAN_FLAG_FOV0) || \ - ((x) == CAN_FLAG_FF1) || \ - ((x) == CAN_FLAG_FOV1) || \ - ((x) == CAN_FLAG_EWG) || \ - ((x) == CAN_FLAG_EPV) || \ - ((x) == CAN_FLAG_BOF)) -#define IS_CAN_CLEAR_FLAG(x) (((x) == CAN_FLAG_WKU) || \ - ((x) == CAN_FLAG_SLAKI) || \ - ((x) == CAN_FLAG_RQCP0) || \ - ((x) == CAN_FLAG_RQCP1) || \ - ((x) == CAN_FLAG_RQCP2) || \ - ((x) == CAN_FLAG_FF0) || \ - ((x) == CAN_FLAG_FOV0) || \ - ((x) == CAN_FLAG_FF1) || \ - ((x) == CAN_FLAG_FOV1)) -#define IS_CAN_IT(x) (((x) == CAN_IT_TME) || \ - ((x) == CAN_IT_FMP0) || \ - ((x) == CAN_IT_FF0) || \ - ((x) == CAN_IT_FOV0) || \ - ((x) == CAN_IT_FMP1) || \ - ((x) == CAN_IT_FF1) || \ - ((x) == CAN_IT_FOV1) || \ - ((x) == CAN_IT_EWG) || \ - ((x) == CAN_IT_EPV) || \ - ((x) == CAN_IT_BOF) || \ - ((x) == CAN_IT_LEC) || \ - ((x) == CAN_IT_ERR) || \ - ((x) == CAN_IT_WKU) || \ - ((x) == CAN_IT_SLK)) -#define CAN_TIMEOUT_VALUE 100 -#define CAN_STATE_TX_MASK (1U << 4) -#define CAN_STATE_RX_MASK (1U << 5) -/** - * @} - */ - -/** @addtogroup CAN_Public_Functions - * @{ - */ - -/** @addtogroup CAN_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -void can_reset(can_handle_t *hperh); -ald_status_t can_init(can_handle_t *hperh); -ald_status_t can_filter_config(can_handle_t *hperh, can_filter_t *config); -/** - * @} - */ - -/** @addtogroup CAN_Public_Functions_Group2 - * @{ - */ -/* IO operation functions */ -ald_status_t can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout); -ald_status_t can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg); -ald_status_t can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout); -ald_status_t can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg); -/** - * @} - */ - -/** @addtogroup CAN_Public_Functions_Group3 - * @{ - */ -/* Control function */ -ald_status_t can_sleep(can_handle_t *hperh); -ald_status_t can_wake_up(can_handle_t *hperh); -void can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box); -void can_irq_handler(can_handle_t *hperh); -type_bool_t can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box); -void can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state); -it_status_t can_get_it_status(can_handle_t *hperh, can_it_t it); -flag_status_t can_get_flag_status(can_handle_t *hperh, can_flag_t flag); -void can_clear_flag_status(can_handle_t *hperh, can_flag_t flag); -/** - * @} - */ - -/** @addtogroup CAN_Public_Functions_Group4 - * @{ - */ -/* State and Error functions */ -can_state_t can_get_state(can_handle_t *hperh); -can_error_t can_get_error(can_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_CAN_H */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h deleted file mode 100644 index 646ae02a67a21be1f3361f1ab35c924625fed973..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h +++ /dev/null @@ -1,389 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_dma.h - * @brief DMA module Library. - * - * @version V1.0 - * @date 09 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_DMA_H__ -#define __ALD_DMA_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/** - * @defgroup DMA_Public_Macros DMA Public Macros - * @{ - */ -#define DMA_CH_COUNT 6 -#define DMA_ERR 31 -/** - * @} - */ - -/** - * @defgroup DMA_Public_Types DMA Public Types - * @{ - */ - -/** - * @brief Input source to DMA channel - */ -typedef enum -{ - DMA_MSEL_NONE = 0x0, /**< NONE */ - DMA_MSEL_GPIO = 0x1, /**< GPIO */ - DMA_MSEL_CRYPT = 0x2, /**< CRYPT */ - DMA_MSEL_ACMP = 0x3, /**< ACMP */ - DMA_MSEL_DAC0 = 0x4, /**< DAC0 */ - DMA_MSEL_ADC0 = 0x6, /**< ADC0 */ - DMA_MSEL_CRC = 0x7, /**< CRC */ - DMA_MSEL_UART0 = 0x8, /**< UART0 */ - DMA_MSEL_UART1 = 0x9, /**< UART1 */ - DMA_MSEL_UART2 = 0xA, /**< UART2 */ - DMA_MSEL_UART3 = 0xB, /**< UART3 */ - DMA_MSEL_USART0 = 0xC, /**< USART0 */ - DMA_MSEL_USART1 = 0xD, /**< USART1 */ - DMA_MSEL_SPI0 = 0xE, /**< SPI0 */ - DMA_MSEL_SPI1 = 0xF, /**< SPI1 */ - DMA_MSEL_I2C0 = 0x10, /**< I2C0 */ - DMA_MSEL_I2C1 = 0x11, /**< I2C1 */ - DMA_MSEL_TIMER0 = 0x12, /**< TIMER0 */ - DMA_MSEL_TIMER1 = 0x13, /**< TIMER1 */ - DMA_MSEL_TIMER2 = 0x14, /**< TIMER2 */ - DMA_MSEL_TIMER3 = 0x15, /**< TIMER3 */ - DMA_MSEL_RTC = 0x16, /**< RTC */ - DMA_MSEL_LPTIM0 = 0x17, /**< LPTIM0 */ - DMA_MSEL_LPUART0 = 0x18, /**< LPUART0 */ - DMA_MSEL_DMA = 0x19, /**< DMA */ - DMA_MSEL_SPI2 = 0x1A, /**< SPI2 */ - DMA_MSEL_TIMER4 = 0x1B, /**< TIMER4 */ - DMA_MSEL_TIMER5 = 0x1C, /**< TIMER5 */ - DMA_MSEL_TIMER6 = 0x1D, /**< TIMER6 */ - DMA_MSEL_TIMER7 = 0x1E, /**< TIMER7 */ - DMA_MSEL_ADC1 = 0x1F, /**< ADC1 */ - DMA_MSEL_PIS = 0x20, /**< PIS */ - DMA_MSEL_TRNG = 0x21, /**< TRNG */ -} dma_msel_t; - -/** - * @brief Input signal to DMA channel - */ -typedef enum -{ - DMA_MSIGSEL_NONE = 0x0, /**< NONE */ - DMA_MSIGSEL_EXTI_0 = 0x0, /**< External interrupt 0 */ - DMA_MSIGSEL_EXTI_1 = 0x1, /**< External interrupt 1 */ - DMA_MSIGSEL_EXTI_2 = 0x2, /**< External interrupt 2 */ - DMA_MSIGSEL_EXTI_3 = 0x3, /**< External interrupt 3 */ - DMA_MSIGSEL_EXTI_4 = 0x4, /**< External interrupt 4 */ - DMA_MSIGSEL_EXTI_5 = 0x5, /**< External interrupt 5 */ - DMA_MSIGSEL_EXTI_6 = 0x6, /**< External interrupt 6 */ - DMA_MSIGSEL_EXTI_7 = 0x7, /**< External interrupt 7 */ - DMA_MSIGSEL_EXTI_8 = 0x8, /**< External interrupt 8 */ - DMA_MSIGSEL_EXTI_9 = 0x9, /**< External interrupt 9 */ - DMA_MSIGSEL_EXTI_10 = 0xA, /**< External interrupt 10 */ - DMA_MSIGSEL_EXTI_11 = 0xB, /**< External interrupt 11 */ - DMA_MSIGSEL_EXTI_12 = 0xC, /**< External interrupt 12 */ - DMA_MSIGSEL_EXTI_13 = 0xD, /**< External interrupt 13 */ - DMA_MSIGSEL_EXTI_14 = 0xE, /**< External interrupt 14 */ - DMA_MSIGSEL_EXTI_15 = 0xF, /**< External interrupt 15 */ - DMA_MSIGSEL_CRYPT_WRITE = 0x0, /**< CRYPT write mode */ - DMA_MSIGSEL_CRYPT_READ = 0x1, /**< CRYPT read mode */ - DMA_MSIGSEL_CALC_WRITE = 0x0, /**< CALC write mode */ - DMA_MSIGSEL_CALC_READ = 0x1, /**< CALC read mode */ - DMA_MSIGSEL_DAC0_CH0 = 0x0, /**< DAC0 channel 0 complete */ - DMA_MSIGSEL_DAC0_CH1 = 0x1, /**< DAC0 channel 1 complete */ - DMA_MSIGSEL_ADC = 0x0, /**< ADC mode */ - DMA_MSIGSEL_UART_TXEMPTY = 0x0, /**< UART transmit */ - DMA_MSIGSEL_UART_RNR = 0x1, /**< UART receive */ - DMA_MSIGSEL_USART_RNR = 0x0, /**< USART reveive */ - DMA_MSIGSEL_USART_TXEMPTY = 0x1, /**< USART transmit */ - DMA_MSIGSEL_SPI_RNR = 0x0, /**< SPI receive */ - DMA_MSIGSEL_SPI_TXEMPTY = 0x1, /**< SPI transmit */ - DMA_MSIGSEL_I2C_RNR = 0x0, /**< I2C receive */ - DMA_MSIGSEL_I2C_TXEMPTY = 0x1, /**< I2C transmit */ - DMA_MSIGSEL_TIMER_CH1 = 0x0, /**< TIM channal 1 */ - DMA_MSIGSEL_TIMER_CH2 = 0x1, /**< TIM channal 2 */ - DMA_MSIGSEL_TIMER_CH3 = 0x2, /**< TIM channal 3 */ - DMA_MSIGSEL_TIMER_CH4 = 0x3, /**< TIM channal 4 */ - DMA_MSIGSEL_TIMER_TRI = 0x4, /**< TIM trigger */ - DMA_MSIGSEL_TIMER_COMP = 0x5, /**< TIM compare */ - DMA_MSIGSEL_TIMER_UPDATE = 0x6, /**< TIM update */ - DMA_MSIGSEL_LPUART_RNR = 0x0, /**< LPUART receive */ - DMA_MSIGSEL_LPUART_TXEMPTY = 0x1, /**< LPUART transmit */ - DMA_MSIGSEL_PIS_CH0 = 0x0, /**< PIS channal 0 */ - DMA_MSIGSEL_PIS_CH1 = 0x1, /**< PIS channal 1 */ - DMA_MSIGSEL_PIS_CH2 = 0x2, /**< PIS channal 2 */ - DMA_MSIGSEL_PIS_CH3 = 0x3, /**< PIS channal 3 */ - DMA_MSIGSEL_PIS_CH4 = 0x4, /**< PIS channal 4 */ - DMA_MSIGSEL_PIS_CH5 = 0x5, /**< PIS channal 5 */ - DMA_MSIGSEL_PIS_CH6 = 0x6, /**< PIS channal 6 */ - DMA_MSIGSEL_PIS_CH7 = 0x7, /**< PIS channal 7 */ - DMA_MSIGSEL_PIS_CH8 = 0x8, /**< PIS channal 8 */ - DMA_MSIGSEL_PIS_CH9 = 0x9, /**< PIS channal 9 */ - DMA_MSIGSEL_PIS_CH10 = 0xA, /**< PIS channal 10 */ - DMA_MSIGSEL_PIS_CH11 = 0xB, /**< PIS channal 11 */ - DMA_MSIGSEL_PIS_CH12 = 0xC, /**< PIS channal 12 */ - DMA_MSIGSEL_PIS_CH13 = 0xD, /**< PIS channal 13 */ - DMA_MSIGSEL_PIS_CH14 = 0xE, /**< PIS channal 14 */ - DMA_MSIGSEL_PIS_CH15 = 0xF, /**< PIS channal 15 */ -} dma_msigsel_t; - -/** - * @brief DMA Descriptor control type - */ -typedef union -{ - struct - { - uint32_t cycle_ctrl : 3; /**< DMA operating mode @ref dma_cycle_ctrl_t */ - uint32_t next_useburst : 1; /**< Uses the alternate data structure when complete a DMA cycle */ - uint32_t n_minus_1 : 10; /**< Represent the total number of DMA transfers that DMA cycle contains. */ - uint32_t R_power : 4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ - uint32_t src_prot_ctrl : 3; /**< Control the state of HPROT when reads the source data. */ - uint32_t dst_prot_ctrl : 3; /**< Control the state of HPROT when writes the destination data */ - uint32_t src_size : 2; /**< Source data size @ref dma_data_size_t */ - uint32_t src_inc : 2; /**< Control the source address increment. @ref dma_data_inc_t */ - uint32_t dst_size : 2; /**< Destination data size. @ref dma_data_size_t */ - uint32_t dst_inc : 2; /**< Destination address increment. @ref dma_data_inc_t */ - }; - uint32_t word; -} dma_ctrl_t; - -/** - * @brief Channel control data structure - */ -typedef struct -{ - void *src; /**< Source data end pointer */ - void *dst; /**< Destination data end pointer */ - dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */ - uint32_t use; /**< Reserve for user */ -} dma_descriptor_t; - -/** - * @brief data increment - */ -typedef enum -{ - DMA_DATA_INC_BYTE = 0x0, /**< Address increment by byte */ - DMA_DATA_INC_HALFWORD = 0x1, /**< Address increment by halfword */ - DMA_DATA_INC_WORD = 0x2, /**< Address increment by word */ - DMA_DATA_INC_NONE = 0x3, /**< No increment */ -} dma_data_inc_t; - -/** - * @brief Data size - */ -typedef enum -{ - DMA_DATA_SIZE_BYTE = 0x0, /**< Byte */ - DMA_DATA_SIZE_HALFWORD = 0x1, /**< Halfword */ - DMA_DATA_SIZE_WORD = 0x2, /**< Word */ -} dma_data_size_t; - -/** - * @brief The operating mode of the DMA cycle - */ -typedef enum -{ - DMA_CYCLE_CTRL_NONE = 0x0, /**< Stop */ - DMA_CYCLE_CTRL_BASIC = 0x1, /**< Basic */ - DMA_CYCLE_CTRL_AUTO = 0x2, /**< Auto-request */ - DMA_CYCLE_CTRL_PINGPONG = 0x3, /**< Ping-pong */ - DMA_CYCLE_CTRL_MEM_SCATTER_GATHER = 0x4, /**< Memory scatter/gather */ - DMA_CYCLE_CTRL_PER_SCATTER_GATHER = 0x6, /**< Peripheral scatter/gather */ -} dma_cycle_ctrl_t; - -/** - * @brief Control how many DMA transfers can occur - * before the controller re-arbitrates - */ -typedef enum -{ - DMA_R_POWER_1 = 0x0, /**< Arbitrates after each DMA transfer */ - DMA_R_POWER_2 = 0x1, /**< Arbitrates after 2 DMA transfer */ - DMA_R_POWER_4 = 0x2, /**< Arbitrates after 4 DMA transfer */ - DMA_R_POWER_8 = 0x3, /**< Arbitrates after 8 DMA transfer */ - DMA_R_POWER_16 = 0x4, /**< Arbitrates after 16 DMA transfer */ - DMA_R_POWER_32 = 0x5, /**< Arbitrates after 32 DMA transfer */ - DMA_R_POWER_64 = 0x6, /**< Arbitrates after 64 DMA transfer */ - DMA_R_POWER_128 = 0x7, /**< Arbitrates after 128 DMA transfer */ - DMA_R_POWER_256 = 0x8, /**< Arbitrates after 256 DMA transfer */ - DMA_R_POWER_512 = 0x9, /**< Arbitrates after 512 DMA transfer */ - DMA_R_POWER_1024 = 0xA, /**< Arbitrates after 1024 DMA transfer */ -} dma_arbiter_config_t; - -/** - * @brief Callback function pointer and param - */ -typedef struct -{ - void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ - void (*err_cbk)(void *arg); /**< DMA occurs error callback */ - void *cplt_arg; /**< The parameter of cplt_cbk() */ - void *err_arg; /**< The parameter of err_cbk() */ -} dma_call_back_t; - -/** - * @brief DMA channal configure structure - */ -typedef struct -{ - void *src; /**< Source data begin pointer */ - void *dst; /**< Destination data begin pointer */ - uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ - dma_data_size_t data_width; /**< Data width, @ref dma_data_size_t */ - dma_data_inc_t src_inc; /**< Source increment type. @ref dma_data_inc_t */ - dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */ - dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ - type_func_t primary; /**< Use primary descriptor or alternate descriptor */ - type_func_t burst; /**< Uses the alternate data structure when complete a DMA cycle */ - type_func_t high_prio; /**< High priority or default priority */ - type_func_t iterrupt; /**< Enable/disable interrupt */ - dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */ - dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */ - uint8_t channel; /**< Channel index */ -} dma_config_t; - -/** - * @brief DMA handle structure definition - */ -typedef struct -{ - DMA_TypeDef *perh; /**< DMA registers base address */ - dma_config_t config; /**< Channel configure structure. @ref dma_config_t */ - void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ - void (*err_cbk)(void *arg); /**< DMA bus occurs error callback */ - void *cplt_arg; /**< The parameter of cplt_cbk() */ - void *err_arg; /**< The parameter of err_cbk() */ -} dma_handle_t; -/** - * @} - */ - -/** - * @defgroup DMA_Private_Macros DMA Private Macros - * @{ - */ -#define IS_DMA_MSEL_TYPE(x) ((x) <= DMA_MSEL_TRNG) -#define IS_DMA_MSIGSEL_TYPE(x) ((x) <= 0xF) -#define IS_DMA_DATAINC_TYPE(x) (((x) == DMA_DATA_INC_BYTE) || \ - ((x) == DMA_DATA_INC_HALFWORD) || \ - ((x) == DMA_DATA_INC_WORD) || \ - ((x) == DMA_DATA_INC_NONE)) -#define IS_DMA_DATASIZE_TYPE(x) (((x) == DMA_DATA_SIZE_BYTE) || \ - ((x) == DMA_DATA_SIZE_HALFWORD) || \ - ((x) == DMA_DATA_SIZE_WORD)) -#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \ - ((x) == DMA_CYCLE_CTRL_BASIC) || \ - ((x) == DMA_CYCLE_CTRL_AUTO) || \ - ((x) == DMA_CYCLE_CTRL_PINGPONG) || \ - ((x) == DMA_CYCLE_CTRL_MEM_SCATTER_GATHER) || \ - ((x) == DMA_CYCLE_CTRL_PER_SCATTER_GATHER)) -#define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \ - ((x) == DMA_R_POWER_2) || \ - ((x) == DMA_R_POWER_4) || \ - ((x) == DMA_R_POWER_8) || \ - ((x) == DMA_R_POWER_16) || \ - ((x) == DMA_R_POWER_32) || \ - ((x) == DMA_R_POWER_64) || \ - ((x) == DMA_R_POWER_128) || \ - ((x) == DMA_R_POWER_256) || \ - ((x) == DMA_R_POWER_512) || \ - ((x) == DMA_R_POWER_1024)) -#define IS_DMA(x) ((x) == DMA0) -#define IS_DMA_CHANNEL(x) ((x) <= 5) -#define IS_DMA_DATA_SIZE(x) ((x) <= 1024) -#define IS_DMA_IT_TYPE(x) (((x) <= 5) || ((x) == 31)) -/** - * @} - */ - -/** - * @addtogroup DMA_Public_Functions - * @{ - */ - -/** @addtogroup DMA_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -extern void dma_reset(DMA_TypeDef *DMAx); -extern void dma_init(DMA_TypeDef *DMAx); -extern void dma_config_struct(dma_config_t *p); -/** - * @} - */ - - -/** @addtogroup DMA_Public_Functions_Group2 - * @{ - */ -/* Configure DMA channel functions */ -extern void dma_config_auto(dma_handle_t *hperh); -extern void dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size); -extern void dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, - uint16_t size, uint8_t channel, void (*cbk)(void *arg)); -extern void dma_config_basic(dma_handle_t *hperh); -extern void dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size); -extern void dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, - dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); -/** - * @} - */ - -/** @addtogroup DMA_Public_Functions_Group3 - * @{ - */ -/* DMA control functions */ -extern void dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); -extern void dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); -extern it_status_t dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel); -extern flag_status_t dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel); -extern void dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel); -void dma0_irq_cbk(void); -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__ALD_DMA_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h deleted file mode 100644 index f20384d7e194684a56a110b97ed5834af6776d46..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h +++ /dev/null @@ -1,534 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_i2c.h - * @brief Header file of I2C driver - * - * @version V1.0 - * @date 15 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_I2C_H__ -#define __ALD_I2C_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" -#include "ald_cmu.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/** @defgroup I2C_Public_Types I2C Public Types - * @{ - */ -/** - * @brief I2C Error Code - */ -typedef enum -{ - I2C_ERROR_NONE = 0x0, /**< No error */ - I2C_ERROR_BERR = 0x1, /**< Berr error */ - I2C_ERROR_ARLO = 0x2, /**< Arlo error */ - I2C_ERROR_AF = 0x4, /**< Af error */ - I2C_ERROR_OVR = 0x8, /**< Ovr error */ - I2C_ERROR_DMA = 0x10, /**< Dma error */ - I2C_ERROR_TIMEOUT = 0x20, /**< Timeout error */ -} i2c_error_t; - -/** - * @brief I2C state structure definition - */ -typedef enum -{ - I2C_STATE_RESET = 0x0, /**< Peripheral is not yet Initialized */ - I2C_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - I2C_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - I2C_STATE_BUSY_TX = 0x3, /**< Data Transmission process is ongoing */ - I2C_STATE_BUSY_RX = 0x4, /**< Data Reception process is ongoing */ - I2C_STATE_TIMEOUT = 0x5, /**< timeout state */ - I2C_STATE_ERROR = 0x6, /**< Error */ -} i2c_state_t; - -/** - * @brief I2C Duty Cycle - */ -typedef enum -{ - I2C_DUTYCYCLE_2 = 0x0, /**< duty cycle is 2 */ - I2C_DUTYCYCLE_16_9 = 0x4000, /**< duty cycle is 16/9 */ -} i2c_duty_t; - -/** - * @brief I2C Addressing Mode - */ -typedef enum -{ - I2C_ADDR_7BIT = 0x1, /**< 7 bit address */ - I2C_ADDR_10BIT = 0x2, /**< 10 bit address */ -} i2c_addr_t; - -/** - * @brief I2C Dual Addressing Mode - */ -typedef enum -{ - I2C_DUALADDR_DISABLE = 0x0, /**< dual address is disable */ - I2C_DUALADDR_ENABLE = 0x1, /**< dual address is enable */ -} i2c_dual_addr_t; - -/** - * @brief I2C General Call Addressing mode - */ -typedef enum -{ - I2C_GENERALCALL_DISABLE = 0x0, /**< feneral call address is disable */ - I2C_GENERALCALL_ENABLE = 0x40, /**< feneral call address is enable */ -} i2c_general_addr_t; - -/** - * @brief I2C Nostretch Mode - */ -typedef enum -{ - I2C_NOSTRETCH_DISABLE = 0x0, /**< Nostretch disable */ - I2C_NOSTRETCH_ENABLE = 0x80, /**< Nostretch enable */ -} i2c_nostretch_t; - -/** - * @brief I2C Memory Address Size - */ -typedef enum -{ - I2C_MEMADD_SIZE_8BIT = 0x1, /**< 8 bit memory address size */ - I2C_MEMADD_SIZE_16BIT = 0x10 /**< 10 bit memory address size */ -} i2c_addr_size_t; - -/** - * @brief I2C Flag Definition - */ -typedef enum -{ - I2C_FLAG_SB = (1U << 0), - I2C_FLAG_ADDR = (1U << 1), - I2C_FLAG_BTF = (1U << 2), - I2C_FLAG_ADD10 = (1U << 3), - I2C_FLAG_STOPF = (1U << 4), - I2C_FLAG_RXNE = (1U << 6), - I2C_FLAG_TXE = (1U << 7), - I2C_FLAG_BERR = (1U << 8), - I2C_FLAG_ARLO = (1U << 9), - I2C_FLAG_AF = (1U << 10), - I2C_FLAG_OVR = (1U << 11), - I2C_FLAG_PECERR = (1U << 12), - I2C_FLAG_TIMEOUT = (1U << 14), - I2C_FLAG_SMBALERT = (1U << 15), - I2C_FLAG_MSL = (1U << 16), - I2C_FLAG_BUSY = (1U << 17), - I2C_FLAG_TRA = (1U << 18), - I2C_FLAG_GENCALL = (1U << 20), - I2C_FLAG_SMBDEFAULT = (1U << 21), - I2C_FLAG_SMBHOST = (1U << 22), - I2C_FLAG_DUALF = (1U << 23), -} i2c_flag_t; - -/** - * @brief I2C mode structure definition - */ -typedef enum -{ - I2C_MODE_NONE = 0x0, /**< No I2C communication on going */ - I2C_MODE_MASTER = 0x10, /**< I2C communication is in Master mode */ - I2C_MODE_SLAVE = 0x20, /**< I2C communication is in Slave mode */ - I2C_MODE_MEM = 0x40, /**< I2C communication is in Memory mode */ -} i2c_mode_t; - -/** - * @brief I2C Clock - */ -typedef enum -{ - I2C_STANDARD_MODE_MAX_CLK = 100000, /**< Standard mode clock */ - I2C_FAST_MODE_MAX_CLK = 400000, /**< Fast mode clock */ -} i2c_clock_t; - -/** - * @brief Interrupt Configuration Definition - */ -typedef enum -{ - I2C_IT_BUF = (1U << 10), /**< Buffer interrupt */ - I2C_IT_EVT = (1U << 9), /**< Event interrupt */ - I2C_IT_ERR = (1U << 8), /**< Error interrupt */ -} i2c_interrupt_t; - -/** - * @brief I2C CON1 Register - */ -typedef enum -{ - I2C_CON1_PEN = (1U << 0), /**< PEN BIT */ - I2C_CON1_PMOD = (1U << 1), /**< PMOD BIT */ - I2C_CON1_SMBMOD = (1U << 3), /**< SMBMOD BIT */ - I2C_CON1_ARPEN = (1U << 4), /**< ARPEN BIT */ - I2C_CON1_PECEN = (1U << 5), /**< PECEN BIT */ - I2C_CON1_GCEN = (1U << 6), /**< GCEN BIT */ - I2C_CON1_DISCS = (1U << 7), /**< DISCS BIT */ - I2C_CON1_START = (1U << 8), /**< START BIT */ - I2C_CON1_STOP = (1U << 9), /**< STOP BIT */ - I2C_CON1_ACKEN = (1U << 10), /**< ACKEN BIT */ - I2C_CON1_POSAP = (1U << 11), /**< POSAP BIT */ - I2C_CON1_TRPEC = (1U << 12), /**< TRPEC BIT */ - I2C_CON1_ALARM = (1U << 13), /**< ALARM BIT */ - I2C_CON1_SRST = (1U << 15), /**< SRST BIT */ -} i2c_con1_t; - -/** - * @brief I2C CON2 Register - */ -typedef enum -{ - I2C_CON2_CLKF = 0x3F, /**< CLKF BITS */ - I2C_CON2_CLKF_0 = (1U << 0), /**< CLKF_0 BIT */ - I2C_CON2_CLKF_1 = (1U << 1), /**< CLKF_1 BIT */ - I2C_CON2_CLKF_2 = (1U << 2), /**< CLKF_2 BIT */ - I2C_CON2_CLKF_3 = (1U << 3), /**< CLKF_3 BIT */ - I2C_CON2_CLKF_4 = (1U << 4), /**< CLKF_4 BIT */ - I2C_CON2_CLKF_5 = (1U << 5), /**< CLKF_5 BIT */ - I2C_CON2_ERRIE = (1U << 8), /**< ERRIE BIT */ - I2C_CON2_EVTIE = (1U << 9), /**< EVTIE BIT */ - I2C_CON2_BUFIE = (1U << 10), /**< BUFIE BIT */ - I2C_CON2_DMAEN = (1U << 11), /**< DMAEN BIT */ - I2C_CON2_LDMA = (1U << 12), /**< LDMA BIT */ -} i2c_con2_t; - -/** - * @brief I2C ADDR1 Register - */ -typedef enum -{ - I2C_ADDR1_ADDH0 = (1U << 0), /**< ADDH0 BIT */ - I2C_ADDR1_ADDH1 = (1U << 1), /**< ADDH1 BIT */ - I2C_ADDR1_ADDH2 = (1U << 2), /**< ADDH2 BIT */ - I2C_ADDR1_ADDH3 = (1U << 3), /**< ADDH3 BIT */ - I2C_ADDR1_ADDH4 = (1U << 4), /**< ADDH4 BIT */ - I2C_ADDR1_ADDH5 = (1U << 5), /**< ADDH5 BIT */ - I2C_ADDR1_ADDH6 = (1U << 6), /**< ADDH6 BIT */ - I2C_ADDR1_ADDH7 = (1U << 7), /**< ADDH7 BIT */ - I2C_ADDR1_ADDH8 = (1U << 8), /**< ADDH8 BIT */ - I2C_ADDR1_ADDH9 = (1U << 9), /**< ADDH9 BIT */ - I2C_ADDR1_ADDTYPE = (1U << 15), /**< ADDTYPE BIT */ -} i2c_addr1_t; - -/** - * @brief I2C ADDR2 Register - */ -typedef enum -{ - I2C_ADDR2_DUALEN = (1U << 0), /**< DUALEN BIT */ - I2C_ADDR2_ADD = (1U << 1), /**< ADD BIT */ -} i2c_addr2_t; - -/** - * @brief I2C STAT1 Register - */ -typedef enum -{ - I2C_STAT1_SB = (1U << 0), /**< SB BIT */ - I2C_STAT1_ADDR = (1U << 1), /**< ADDR BIT */ - I2C_STAT1_BTC = (1U << 2), /**< BTC BIT */ - I2C_STAT1_SENDADD10 = (1U << 3), /**< SENDADD10 BIT */ - I2C_STAT1_DETSTP = (1U << 4), /**< DETSTP BIT */ - I2C_STAT1_RXBNE = (1U << 6), /**< RXBNE BIT */ - I2C_STAT1_TXBE = (1U << 7), /**< TXBE BIT */ - I2C_STAT1_BUSERR = (1U << 8), /**< BUSERR BIT */ - I2C_STAT1_LARB = (1U << 9), /**< LARB BIT */ - I2C_STAT1_ACKERR = (1U << 10), /**< ACKERR BIT */ - I2C_STAT1_ROUERR = (1U << 11), /**< ROUERR BIT */ - I2C_STAT1_PECERR = (1U << 12), /**< PECERR BIT */ - I2C_STAT1_SMBTO = (1U << 14), /**< SMBTO BIT */ - I2C_STAT1_SMBALARM = (1U << 15), /**< SMBALARM BIT */ -} i2c_stat1_t; - -/** - * @brief I2C STAT2 Register - */ -typedef enum -{ - I2C_STAT2_MASTER = (1U << 0), /**< MASTER BIT */ - I2C_STAT2_BSYF = (1U << 1), /**< BSYF BIT */ - I2C_STAT2_TRF = (1U << 2), /**< TRF BIT */ - I2C_STAT2_RXGCF = (1U << 4), /**< RXGCF BIT */ - I2C_STAT2_SMBDEF = (1U << 5), /**< SMBDEF BIT */ - I2C_STAT2_SMBHH = (1U << 6), /**< SMBHH BIT */ - I2C_STAT2_DUALF = (1U << 7), /**< DMF BIT */ - I2C_STAT2_PECV = (1U << 8), /**< PECV BIT */ -} i2c_stat2_t; - -/** - * @brief I2C CKCFG Register - */ -typedef enum -{ - I2C_CKCFG_CLKSET = 0xFFF, /**< CLKSET BITS */ - I2C_CKCFG_DUTY = (1U << 14), /**< DUTY BIT */ - I2C_CKCFG_CLKMOD = (1U << 15), /**< CLKMOD BIT */ -} i2c_ckcfg_t; - -/** - * @brief I2C RT Register - */ -typedef enum -{ - I2C_RT_RISET = 0x3F, /**< RISET BITS */ -} i2c_trise_t; - -/** - * @brief I2C Configuration Structure definition - */ -typedef struct -{ - uint32_t clk_speed; /**< Specifies the clock frequency */ - i2c_duty_t duty; /**< Specifies the I2C fast mode duty cycle */ - uint32_t own_addr1; /**< Specifies the first device own address */ - i2c_addr_t addr_mode; /**< Specifies addressing mode */ - i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ - uint32_t own_addr2; /**< Specifies the second device own address */ - i2c_general_addr_t general_call; /**< Specifies if general call mode is selected */ - i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ -} i2c_init_t; - -/** - * @brief I2C handle Structure definition - */ -typedef struct i2c_handle_s -{ - I2C_TypeDef *perh; /**< I2C registers base address */ - i2c_init_t init; /**< I2C communication parameters */ - uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ - uint16_t xfer_size; /**< I2C transfer size */ - __IO uint16_t xfer_count; /**< I2C transfer counter */ -#ifdef ALD_DMA - dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ - dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ -#endif - lock_state_t lock; /**< I2C locking object */ - __IO i2c_state_t state; /**< I2C communication state */ - __IO i2c_mode_t mode; /**< I2C communication mode */ - __IO uint32_t error_code; /**< I2C Error code */ - - void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Tx completed callback */ - void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Rx completed callback */ - void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Tx completed callback */ - void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Rx completed callback */ - void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Tx to Memory completed callback */ - void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Rx from Memory completed callback */ - void (*error_callback)(struct i2c_handle_s *arg); /**< Error callback */ -} i2c_handle_t; - -/** - * @} - */ - -/** @defgroup I2C_Public_Macro I2C Public Macros - * @{ - */ -#define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET) -#define I2C_CLEAR_ADDRFLAG(x) \ -do { \ - __IO uint32_t tmpreg; \ - tmpreg = (x)->perh->STAT1; \ - tmpreg = (x)->perh->STAT2; \ - UNUSED(tmpreg); \ -} while (0) -#define __I2C_CLEAR_STOPFLAG(x) \ -do { \ - __IO uint32_t tmpreg; \ - tmpreg = (x)->perh->STAT1; \ - tmpreg = SET_BIT((x)->perh->CON1, I2C_CON1_PEN); \ - UNUSED(tmpreg); \ -} while (0) -#define I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) -#define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) -/** - * @} - */ - -/** @defgroup I2C_Private_Macro I2C Private Macros - * @{ - */ -#define IS_I2C_TYPE(x) (((x) == I2C0) || \ - ((x) == I2C1)) -#define IS_I2C_ADDRESSING_MODE(x) (((x) == I2C_ADDR_7BIT) || \ - ((x) == I2C_ADDR_10BIT)) -#define IS_I2C_DUAL_ADDRESS(x) (((x) == I2C_DUALADDR_DISABLE) || \ - ((x) == I2C_DUALADDR_ENABLE)) -#define IS_I2C_GENERAL_CALL(x) (((x) == I2C_GENERALCALL_DISABLE) || \ - ((x) == I2C_GENERALCALL_ENABLE)) -#define IS_I2C_MEMADD_size(x) (((x) == I2C_MEMADD_SIZE_8BIT) || \ - ((x) == I2C_MEMADD_SIZE_16BIT)) -#define IS_I2C_NO_STRETCH(x) (((x) == I2C_NOSTRETCH_DISABLE) || \ - ((x) == I2C_NOSTRETCH_ENABLE)) -#define IS_I2C_OWN_ADDRESS1(x) (((x) & (uint32_t)(0xFFFFFC00)) == 0) -#define IS_I2C_OWN_ADDRESS2(x) (((x) & (uint32_t)(0xFFFFFF01)) == 0) -#define IS_I2C_CLOCK_SPEED(x) (((x) > 0) && ((x) <= I2C_FAST_MODE_MAX_CLK)) -#define IS_I2C_DUTY_CYCLE(x) (((x) == I2C_DUTYCYCLE_2) || \ - ((x) == I2C_DUTYCYCLE_16_9)) -#define IS_I2C_IT_TYPE(x) (((x) == I2C_IT_BUF) || \ - ((x) == I2C_IT_EVT) || \ - ((x) == I2C_IT_ERR)) -#define IS_I2C_FLAG(x) (((x) == I2C_FLAG_SB) || \ - ((x) == I2C_FLAG_ADDR) || \ - ((x) == I2C_FLAG_BTF) || \ - ((x) == I2C_FLAG_ADD10) || \ - ((x) == I2C_FLAG_STOPF) || \ - ((x) == I2C_FLAG_RXNE) || \ - ((x) == I2C_FLAG_TXE) || \ - ((x) == I2C_FLAG_BERR) || \ - ((x) == I2C_FLAG_ARLO) || \ - ((x) == I2C_FLAG_AF) || \ - ((x) == I2C_FLAG_OVR) || \ - ((x) == I2C_FLAG_PECERR) || \ - ((x) == I2C_FLAG_TIMEOUT) || \ - ((x) == I2C_FLAG_SMBALERT) || \ - ((x) == I2C_FLAG_MSL) || \ - ((x) == I2C_FLAG_BUSY) || \ - ((x) == I2C_FLAG_TRA) || \ - ((x) == I2C_FLAG_GENCALL) || \ - ((x) == I2C_FLAG_SMBDEFAULT) || \ - ((x) == I2C_FLAG_SMBHOST) || \ - ((x) == I2C_FLAG_DUALF)) - -#define I2C_FREQ_RANGE(x) ((x) / 1000000) -#define I2C_RISE_TIME(x, u) (((u) <= I2C_STANDARD_MODE_MAX_CLK) ? ((x) + 1) :\ - ((((x) * 300) / 1000) + 1)) -#define I2C_SPEED_STANDARD(x, y) (((((x) / ((y) << 1)) & I2C_CKCFG_CLKSET) < 4) ? 4:\ - ((x) / ((y) << 1))) -#define I2C_SPEED_FAST(x, y, z) (((z) == I2C_DUTYCYCLE_2) ? ((x) / ((y) * 3)) :\ - (((x) / ((y) * 25)) | I2C_DUTYCYCLE_16_9)) -#define I2C_SPEED(x, y, z) (((y) <= 100000) ? (I2C_SPEED_STANDARD((x), (y))) :\ - ((I2C_SPEED_FAST((x), (y), (z)) & I2C_CKCFG_CLKSET) == 0) ? 1 : \ - ((I2C_SPEED_FAST((x), (y), (z))) | I2C_CKCFG_CLKMOD)) -#define I2C_MEM_ADD_MSB(x) ((uint8_t)((uint16_t)(((uint16_t)((x) &\ - (uint16_t)(0xFF00))) >> 8))) -#define I2C_MEM_ADD_LSB(x) ((uint8_t)((uint16_t)((x) & (uint16_t)(0x00FF)))) -#define I2C_7BIT_ADD_WRITE(x) ((uint8_t)((x) & (~I2C_ADDR1_ADDH0))) -#define I2C_7BIT_ADD_READ(x) ((uint8_t)((x) | I2C_ADDR1_ADDH0)) -#define I2C_10BIT_ADDRESS(x) ((uint8_t)((uint16_t)((x) & (uint16_t)(0x00FF)))) -#define I2C_10BIT_HEADER_WRITE(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ - (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) -#define I2C_10BIT_HEADER_READ(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ - (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) -/** - * @} - */ - -/** @addtogroup I2C_Public_Functions - * @{ - */ - -/** @addtogroup I2C_Public_Functions_Group1 - * @{ - */ -ald_status_t i2c_init(i2c_handle_t *hperh); -ald_status_t i2c_reset(i2c_handle_t *hperh); - -/** - * @} - */ - -/** @addtogroup I2C_Public_Functions_Group2 - * @{ - */ -/** Blocking mode: Polling */ -ald_status_t i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout); - -/** Non-Blocking mode: Interrupt */ -ald_status_t i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); -ald_status_t i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); -ald_status_t i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); -ald_status_t i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); - -#ifdef ALD_DMA -/** Non-Blocking mode: DMA */ -ald_status_t i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, - uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel); -#endif -/** - * @} - */ - -/** @addtogroup I2C_Public_Functions_Group3 - * @{ - */ -i2c_state_t i2c_get_state(i2c_handle_t *hperh); -uint32_t i2c_get_error(i2c_handle_t *hperh); -flag_status_t i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag); -flag_status_t i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it); -void i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag); -/** - * @} - */ - -/** @addtogroup I2C_Public_Functions_Group4 - * @{ - */ -void i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state); -void i2c_ev_irq_handler(i2c_handle_t *hperh); -void i2c_er_irq_handler(i2c_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_I2C_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h deleted file mode 100644 index 3b7c12cf0f9fe75de5a6703d335d4fd32ab77f66..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h +++ /dev/null @@ -1,633 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_pis.h - * @brief Header file of PIS driver. - * - * @version V1.0 - * @date 27 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_PIS_H__ -#define __ALD_PIS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup PIS - * @{ - */ - -/** @defgroup PIS_Public_Types PIS Public Types - * @{ - */ - -/** - * @brief Producer entry - */ -typedef enum -{ - PIS_NON = 0x0, /**< No async */ - PIS_GPIO_PIN0 = 0x10, /**< Pin0, level,support async */ - PIS_GPIO_PIN1 = 0x11, /**< Pin1, level,support async */ - PIS_GPIO_PIN2 = 0x12, /**< Pin2, level,support async */ - PIS_GPIO_PIN3 = 0x13, /**< Pin3, level,support async */ - PIS_GPIO_PIN4 = 0x14, /**< Pin4, level,support async */ - PIS_GPIO_PIN5 = 0x15, /**< Pin5, level,support async */ - PIS_GPIO_PIN6 = 0x16, /**< Pin6, level,support async */ - PIS_GPIO_PIN7 = 0x17, /**< Pin7, level,support async */ - PIS_GPIO_PIN8 = 0x18, /**< Pin8, level,support async */ - PIS_GPIO_PIN9 = 0x19, /**< Pin9, level,support async */ - PIS_GPIO_PIN10 = 0x1a, /**< Pin10, level,support async */ - PIS_GPIO_PIN11 = 0x1b, /**< Pin11, level,support async */ - PIS_GPIO_PIN12 = 0x1c, /**< Pin12, level,support async */ - PIS_GPIO_PIN13 = 0x1d, /**< Pin13, level,support async */ - PIS_GPIO_PIN14 = 0x1e, /**< Pin14, level,support async */ - PIS_GPIO_PIN15 = 0x1f, /**< Pin15, level,support async */ - PIS_ACMP_OUT0 = 0x30, /**< Acmp0 output, level,support async */ - PIS_ACMP_OUT1 = 0x31, /**< Acmp1 output, level,support async */ - PIS_DAC0_CH0 = 0x40, /**< Dac0 channel 0, pclk2 pulse,support async */ - PIS_DAC0_CH1 = 0x41, /**< Dac0 channel 1, pclk2 pulse,support async */ - PIS_ADC0_INJECT = 0x60, /**< Adc0 inject, pclk2 pulse,support async */ - PIS_ADC0_REGULAT = 0x61, /**< Adc0 regulat, pclk2 pulse,support async */ - PIS_ADC0_WINDOW = 0x62, /**< Adc0 window, no have */ - PIS_LVD = 0x70, /**< Lvd, level,support async */ - PIS_UART0_ASY_SEND = 0x80, /**< Uart0 asy send, pulse,support async */ - PIS_UART0_ASY_RECV = 0x81, /**< Uart0 asy recv, pulse,support async */ - PIS_UART0_IRDAOUT = 0x82, /**< Uart0 irdaout, level,support async */ - PIS_UART0_RTSOUT = 0x83, /**< Uart0 rtsout, level,support async */ - PIS_UART0_TXOUT = 0x84, /**< Uart0 txout, level,support async */ - PIS_UART0_SYN_SEND = 0x85, /**< Uart0 syn send, pulse,support async */ - PIS_UART0_SYN_RECV = 0x86, /**< Uart0 syn recv, pulse,support async */ - PIS_UART1_ASY_SEND = 0x90, /**< Uart1 asy send, pulse,support async */ - PIS_UART1_ASY_RECV = 0x91, /**< Uart1 asy recv, pulse,support async */ - PIS_UART1_IRDA = 0x92, /**< Uart1 irdaout, level,support async */ - PIS_UART1_RTS = 0x93, /**< Uart1 rtsout, level,support async */ - PIS_UART1_TXOUT = 0x94, /**< Uart1 txout, level,support async */ - PIS_UART1_SYN_SEND = 0x95, /**< Uart1 syn send, pulse,support async */ - PIS_UART1_SYN_RECV = 0x96, /**< Uart1 syn recv, pulse,support async */ - PIS_UART2_ASY_SEND = 0xa0, /**< Uart2 asy send, pulse,support async */ - PIS_UART2_ASY_RECV = 0xa1, /**< Uart2 asy recv, pulse,support async */ - PIS_UART2_IRDA = 0xa2, /**< Uart2 irdaout, level,support async */ - PIS_UART2_RTS = 0xa3, /**< Uart2 rtsout, level,support async */ - PIS_UART2_TXOUT = 0xa4, /**< Uart2 txout, level,support async */ - PIS_UART2_SYN_SEND = 0xa5, /**< Uart2 syn send, pulse,support async */ - PIS_UART2_SYN_RECV = 0xa6, /**< Uart2 syn recv, pulse,support async */ - PIS_UART3_ASY_SEND = 0xb1, /**< Uart3 asy send, pulse,support async */ - PIS_UART3_ASY_RECV = 0xb2, /**< Uart3 asy recv, pulse,support async */ - PIS_UART3_IRDA = 0xb3, /**< Uart3 irdaout, level,support async */ - PIS_UART3_RTS = 0xb4, /**< Uart3 rtsout, level,support async */ - PIS_UART3_TXOUT = 0xb5, /**< Uart3 txout, level,support async */ - PIS_UART3_SYN_SEND = 0xb6, /**< Uart3 syn send, pulse,support async */ - PIS_UART3_SYN_RECV = 0xb7, /**< Uart3 syn recv, pulse,support async */ - PIS_EUART0_RECV = 0xc0, /**< Euart0 recv, plck1 pulse */ - PIS_EUART0_SEND = 0xc1, /**< Euart0 send, plck1 pulse */ - PIS_EUART0_TXOUT = 0xc2, /**< Euart0 txout, plck1 level */ - PIS_EUART1_RECV = 0xd0, /**< Euart1 recv, plck1 pulse */ - PIS_EUART1_SEND = 0xd1, /**< Euart1 send, plck1 pulse */ - PIS_EUART1_TXOUT = 0xd2, /**< Euart1 txout, plck1 level */ - PIS_SPI0_RECV = 0xe0, /**< Spi0 recv, plck1 pulse */ - PIS_SPI0_SEND = 0xe1, /**< Spi0 send, plck1 pulse */ - PIS_SPI0_NE = 0xe2, /**< Spi0 ne, plck1 level */ - PIS_SPI1_RECV = 0xf0, /**< Spi1 recv, plck1 pulse */ - PIS_SPI1_SEND = 0xf1, /**< Spi1 send, plck1 pulse */ - PIS_SPI1_NE = 0xf2, /**< Spi1 ne, plck1 level */ - PIS_I2C0_RECV = 0x100, /**< I2c0 recv, plck1 level */ - PIS_I2C0_SEND = 0x101, /**< I2c0 send, plck1 level */ - PIS_I2C1_RECV = 0x110, /**< I2c1 recv, plck1 level */ - PIS_I2C1_SEND = 0x111, /**< I2c1 send, plck1 level */ - PIS_TIMER0_UPDATA = 0x120, /**< Timer0 updata, plck1 pulse */ - PIS_TIMER0_TRIG = 0x121, /**< Timer0 trig, plck1 pulse */ - PIS_TIMER0_INPUT = 0x122, /**< Timer0 input, plck1 pulse */ - PIS_TIMER0_OUTPUT = 0x123, /**< Timer0 output, plck1 pulse */ - PIS_TIMER1_UPDATA = 0x130, /**< Timer1 updata, plck1 pulse */ - PIS_TIMER1_TRIG = 0x131, /**< Timer1 trig, plck1 pulse */ - PIS_TIMER1_INPUT = 0x132, /**< Timer1 input, plck1 pulse */ - PIS_TIMER1_OUTPUT = 0x133, /**< Timer1 output, plck1 pulse */ - PIS_TIMER2_UPDATA = 0x140, /**< Timer2 updata, plck1 pulse */ - PIS_TIMER2_TRIG = 0x141, /**< Timer2 trig, plck1 pulse */ - PIS_TIMER2_INPUT = 0x142, /**< Timer2 input, plck1 pulse */ - PIS_TIMER2_OUTPUT = 0x143, /**< Timer2 output, plck1 pulse */ - PIS_TIMER3_UPDATA = 0x150, /**< Timer0 updata, plck1 pulse */ - PIS_TIMER3_TRIG = 0x151, /**< Timer0 trig, plck1 pulse */ - PIS_TIMER3_INPUT = 0x152, /**< Timer0 input, plck1 pulse */ - PIS_TIMER3_OUTPUT = 0x153, /**< Timer0 output, plck1 pulse */ - PIS_RTC_CLOCK = 0x160, /**< Rtc clock, pulse,support async */ - PIS_RTC_ALARM = 0x161, /**< Rtc alarm, pulse,support async */ - PIS_LPTIM0_SYN_UPDATA = 0x170, /**< Lptimer0 syn updata, pulse,support async */ - PIS_LPTIM0_ASY_UPDATA = 0x171, /**< Lptimer0 asy updata, pulse,support async */ - PIS_LPUART0_ASY_RECV = 0x180, /**< Lpuart0 asy recv, pulse,support async */ - PIS_LPUART0_ASY_SEND = 0x181, /**< Lpuart0 asy send, pulse,support async */ - PIS_LPUART0_SYN_RECV = 0x182, /**< Lpuart0 syn recv, pulse,support async */ - PIS_LPUART0_SYN_SEND = 0x183, /**< Lpuart0 syn recv, pulse,support async */ - PIS_DMA = 0x190, /**< Dma, pulse,support async */ - PIS_ADC1_INJECT = 0x1a0, /**< Adc1 inject, pclk2 pulse,support async */ - PIS_ADC1_REGULAT = 0x1a1, /**< Adc1 regulat, pclk2 pulse,support async */ - PIS_ADC1_WINDOW = 0x1a2, /**< Adc1 window, no have */ -} pis_src_t; - -/** - * @brief Consumer entry - */ -typedef enum -{ - PIS_CH0_TIMER0_BRKIN = 0x4000, /**< Timer0 brkin */ - PIS_CH0_SPI1_CLK = 0xF010, /**< Spi1 clk */ - PIS_CH0_LPTIM0_EXT0 = 0x0030, /**< Lptimer0 ext0 */ - PIS_CH0_ADC1_NORMAL = 0x0030, /**< Adc1 normal */ - PIS_CH1_TIMER0_CH1IN = 0x0001, /**< Timer0 ch1in */ - PIS_CH1_TIMER2_CH1IN = 0x0101, /**< Timer2 ch1in */ - PIS_CH1_TIMER3_CH1IN = 0x8101, /**< Timer3 ch1in */ - PIS_CH1_LPTIM0_EXT1 = 0x0031, /**< Lptime0 ext1 */ - PIS_CH1_UART0_RX_IRDA = 0x0011, /**< Uart0 rx irda */ - PIS_CH1_ADC1_INSERT = 0x0031, /**< Adc1 insert */ - PIS_CH2_TIMER0_CH2IN = 0x1002, /**< Timer0 ch2in */ - PIS_CH2_TIMER2_CH2IN = 0x1102, /**< Timer2 ch2in */ - PIS_CH2_TIMER3_CH2IN = 0x9102, /**< Timer3 ch2in */ - PIS_CH2_LPTIM0_EXT2 = 0x0032, /**< Lptime0 ext2 */ - PIS_CH2_UART1_RX_IRDA = 0x1012, /**< Uart1 rx irda */ - PIS_CH3_TIMER0_CH3IN = 0x2003, /**< Timer0 ch3in */ - PIS_CH3_LPTIM0_EXT3 = 0x0033, /**< Lptime0 ext3 */ - PIS_CH3_UART2_RX_IRDA = 0x2013, /**< Uart2 rx irda */ - PIS_CH4_TIMER0_CH4IN = 0x0004, /**< Timer0 ch4in */ - PIS_CH4_TIMER0_ITR0 = 0x0034, /**< Timer0 itr0 */ - PIS_CH4_TIMER2_ITR0 = 0x0034, /**< Timer2 itr0 */ - PIS_CH4_TIMER3_ITR0 = 0x0034, /**< Timer3 itr0 */ - PIS_CH4_LPTIM0_EXT4 = 0x4034, /**< Lptime0 ext4 */ - PIS_CH4_UART3_RX_IRDA = 0x3014, /**< Uart3 rx irda */ - PIS_CH5_SPI0_RX = 0xC015, /**< Spi0 rx */ - PIS_CH5_LPTIM0_EXT5 = 0x0035, /**< Lptime0 ext5 */ - PIS_CH5_EUART0_RX = 0x6015, /**< Euart0 rx */ - PIS_CH5_TIMER0_ITR1 = 0x0035, /**< Timer0 itr1 */ - PIS_CH5_TIMER2_ITR1 = 0x0035, /**< Timer2 itr1 */ - PIS_CH5_TIMER3_ITR1 = 0x0035, /**< Timer3 itr1 */ - PIS_CH6_SPI0_CLK = 0xD016, /**< Spi0 clk */ - PIS_CH6_ADC0_NORMAL = 0x0036, /**< Adc0 normal */ - PIS_CH6_LPTIM0_EXT6 = 0x0036, /**< Lptime0 ext6 */ - PIS_CH6_EUART1_RX = 0x7016, /**< Euart1 rx */ - PIS_CH6_TIMER0_ITR2 = 0x0036, /**< Timer0 itr2 */ - PIS_CH6_TIMER2_ITR2 = 0x0036, /**< Timer2 itr2 */ - PIS_CH6_TIMER3_ITR2 = 0x0036, /**< Timer3 itr2 */ - PIS_CH6_DAC_CH1 = 0x0036, /**< Dac channel 1 */ - PIS_CH7_SPI1_RX = 0xE017, /**< Spi1 rx */ - PIS_CH7_ADC0_INSERT = 0x0037, /**< Adc0 insert */ - PIS_CH7_LPTIM0_EXT7 = 0x0037, /**< Lptime0 ext7 */ - PIS_CH7_DMA = 0x0037, /**< Dma */ - PIS_CH7_TIMER0_ITR3 = 0x0037, /**< Timer0 itr3 */ - PIS_CH7_TIMER2_ITR3 = 0x0037, /**< Timer2 itr3 */ - PIS_CH7_TIMER3_ITR3 = 0x0037, /**< Timer3 itr3 */ - PIS_CH7_LPUART_RX = 0x8017, /**< Lpuart rx */ - PIS_CH7_DAC_CH0 = 0x0037, /**< Dac channel 0 */ -} pis_trig_t; - -/** - * @brief Clock select - */ -typedef enum -{ - PIS_CLK_PCLK1 = 0, /**< Pclock1 */ - PIS_CLK_PCLK2 = 1, /**< Pclock2 */ - PIS_CLK_SYS = 2, /**< Sys clock */ - PIS_CLK_LP = 3, /**< Low power clock */ -} pis_clock_t; - -/** - * @brief Level select - */ -typedef enum -{ - PIS_EDGE_NONE = 0, /**< None edge */ - PIS_EDGE_UP = 1, /**< Up edge */ - PIS_EDGE_DOWN = 2, /**< Down edge */ - PIS_EDGE_UP_DOWN = 3, /**< Up and down edge */ -} pis_edge_t; - -/** - * @brief Output style - */ -typedef enum -{ - PIS_OUT_LEVEL = 0, /**< Level */ - PIS_OUT_PULSE = 1, /**< Pulse */ -} pis_output_t; -/** - * @brief Sync select - */ -typedef enum -{ - PIS_SYN_DIRECT = 0, /**< Direct */ - PIS_SYN_ASY_PCLK1 = 1, /**< Asy pclk1 */ - PIS_SYN_ASY_PCLK2 = 2, /**< Asy pclk2 */ - PIS_SYN_ASY_PCLK = 3, /**< Asy pclk */ - PIS_SYN_PCLK2_PCLK1 = 4, /**< Pclk2 to pclk1 */ - PIS_SYN_PCLK1_PCLK2 = 5, /**< Pclk1 to pclk2 */ - PIS_SYN_PCLK12_SYS = 6, /**< Pclk1 or pclk2 to sysclk */ -} pis_syncsel_t; - -/** - * @brief Pis channel - */ -typedef enum -{ - PIS_CH_0 = 0, /**< Channel 0 */ - PIS_CH_1 = 1, /**< Channel 1 */ - PIS_CH_2 = 2, /**< Channel 2 */ - PIS_CH_3 = 3, /**< Channel 3 */ - PIS_CH_4 = 4, /**< Channel 4 */ - PIS_CH_5 = 5, /**< Channel 5 */ - PIS_CH_6 = 6, /**< Channel 6 */ - PIS_CH_7 = 7, /**< Channel 7 */ -} pis_ch_t; - -/** - * @brief Pis output channel - */ -typedef enum -{ - PIS_OUT_CH_0 = 0, /**< Channel 0 */ - PIS_OUT_CH_1 = 1, /**< Channel 1 */ - PIS_OUT_CH_2 = 2, /**< Channel 2 */ - PIS_OUT_CH_3 = 3, /**< Channel 3 */ -} pis_out_ch_t; - -/** - * @brief Indirect value,no care of it. - */ -typedef enum -{ - PIS_CON_0 = 0, /**< Con 0 */ - PIS_CON_1 = 1, /**< Con 1 */ - PIS_CON_NONE = 2, /**< None */ -} pis_con_t; - -/** - * @brief Indirect value,no care of it. - */ -typedef union -{ - struct - { - uint8_t ch : 4; /**< Channel */ - uint8_t con : 4; /**< Contorl */ - uint8_t shift : 8; /**< Shift */ - }; - uint16_t HalfWord; -} pis_divide_t; - -/** - * @brief PIS state structures definition - */ -typedef enum -{ - PIS_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - PIS_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - PIS_STATE_BUSY = 0x02, /**< An internal process is ongoing */ - PIS_STATE_TIMEOUT = 0x03, /**< Timeout state */ - PIS_STATE_ERROR = 0x04, /**< Error */ -} pis_state_t; - -/** - * @brief PIS modulate target - */ -typedef enum -{ - PIS_UART0_TX = 0, /**< Modulate uart0 tx */ - PIS_UART1_TX = 1, /**< Modulate uart1 tx */ - PIS_UART2_TX = 2, /**< Modulate uart2 tx */ - PIS_UART3_TX = 3, /**< Modulate uart3 tx */ - PIS_LPUART0_TX = 4, /**< Modulate lpuart0 tx */ -} pis_modu_targ_t; - -/** - * @brief PIS modulate level - */ -typedef enum -{ - PIS_LOW_LEVEL = 0, /**< Modulate low level */ - PIS_HIGH_LEVEL = 1, /**< Modulate high level */ -} pis_modu_level_t; - -/** - * @brief PIS modulate source - */ -typedef enum -{ - PIS_SRC_NONE = 0, /**< Stop modulate */ - PIS_SRC_TIMER0 = 1, /**< Modulate source is TIMER0 */ - PIS_SRC_TIMER1 = 2, /**< Modulate source is TIMER1 */ - PIS_SRC_TIMER2 = 3, /**< Modulate source is TIMER2 */ - PIS_SRC_TIMER3 = 4, /**< Modulate source is TIMER3 */ - PIS_SRC_TIMER6 = 5, /**< Modulate source is TIMER6 */ - PIS_SRC_TIMER7 = 6, /**< Modulate source is TIMER7 */ - PIS_SRC_LPTIM0 = 7, /**< Modulate source is LPTIM0 */ - PIS_SRC_BUZ = 8, /**< Modulate source is buz */ -} pis_modu_src_t; - -/** - * @brief PIS modulate channel - */ -typedef enum -{ - PIS_TIMER_CH1 = 0, /**< Src is TIMERx and choose channel 1 */ - PIS_TIMER_CH2 = 1, /**< Src is TIMERx and choose channel 2 */ - PIS_TIMER_CH3 = 2, /**< Src is TIMERx and choose channel 3 */ - PIS_TIMER_CH4 = 3, /**< Src is TIMERx and choose channel 4 */ -} pis_modu_channel_t; - -/** - * @brief PIS init structure definition - */ -typedef struct -{ - pis_src_t producer_src; /**< Producer entry */ - pis_clock_t producer_clk; /**< Producer module clock */ - pis_edge_t producer_edge; /**< Producer module pin output edge */ - pis_trig_t consumer_trig; /**< Consumer entry */ - pis_clock_t consumer_clk; /**< Consumer clock */ -} pis_init_t; - -/** - * @brief PIS modulate config structure definition - */ -typedef struct -{ - pis_modu_targ_t target; /**< Modulate target */ - pis_modu_level_t level; /**< Modulate level */ - pis_modu_src_t src; /**< Modulate src */ - pis_modu_channel_t channel; /**< Modulate channel */ -} pis_modulate_config_t; - -/** - * @brief PIS Handle Structure definition - */ -typedef struct pis_handle_s -{ - PIS_TypeDef *perh; /**< Register base address */ - pis_init_t init; /**< PIS required parameters */ - pis_ch_t consumer_ch; /**< Indirect value, no care of it */ - pis_con_t consumer_con; /**< Indirect value, no care of it */ - uint8_t consumer_pos; /**< Indirect value, no care of it */ - uint32_t check_info; /**< When destroy a handle ,user need check whether is right that ready to destroy */ - lock_state_t lock; /**< Locking object */ - pis_state_t state; /**< PIS operation state */ -} pis_handle_t; -/** - * @} - */ - - -/** @defgroup PIS_Private_Macros PIS Private Macros - * @{ - */ -#define IS_PIS(x) (((x) == PIS)) -#define IS_PIS_SRC(x) (((x) == PIS_NON) || \ - ((x) == PIS_GPIO_PIN0) || \ - ((x) == PIS_GPIO_PIN1) || \ - ((x) == PIS_GPIO_PIN2) || \ - ((x) == PIS_GPIO_PIN3) || \ - ((x) == PIS_GPIO_PIN4) || \ - ((x) == PIS_GPIO_PIN5) || \ - ((x) == PIS_GPIO_PIN6) || \ - ((x) == PIS_GPIO_PIN7) || \ - ((x) == PIS_GPIO_PIN8) || \ - ((x) == PIS_GPIO_PIN9) || \ - ((x) == PIS_GPIO_PIN10) || \ - ((x) == PIS_GPIO_PIN11) || \ - ((x) == PIS_GPIO_PIN12) || \ - ((x) == PIS_GPIO_PIN13) || \ - ((x) == PIS_GPIO_PIN14) || \ - ((x) == PIS_GPIO_PIN15) || \ - ((x) == PIS_ACMP_OUT0) || \ - ((x) == PIS_ACMP_OUT1) || \ - ((x) == PIS_DAC0_CH1) || \ - ((x) == PIS_ACMP_OUT1) || \ - ((x) == PIS_ADC0_INJECT) || \ - ((x) == PIS_ADC0_REGULAT) || \ - ((x) == PIS_ADC0_WINDOW) || \ - ((x) == PIS_LVD) || \ - ((x) == PIS_UART0_ASY_SEND) || \ - ((x) == PIS_UART0_ASY_RECV) || \ - ((x) == PIS_UART0_IRDAOUT) || \ - ((x) == PIS_UART0_RTSOUT) || \ - ((x) == PIS_UART0_TXOUT) || \ - ((x) == PIS_UART0_SYN_SEND) || \ - ((x) == PIS_UART0_SYN_RECV) || \ - ((x) == PIS_UART1_ASY_SEND) || \ - ((x) == PIS_UART1_ASY_RECV) || \ - ((x) == PIS_UART1_IRDA) || \ - ((x) == PIS_UART1_RTS) || \ - ((x) == PIS_UART1_TXOUT) || \ - ((x) == PIS_UART1_SYN_SEND) || \ - ((x) == PIS_UART1_SYN_RECV) || \ - ((x) == PIS_UART2_ASY_SEND) || \ - ((x) == PIS_UART2_ASY_RECV) || \ - ((x) == PIS_UART2_IRDA) || \ - ((x) == PIS_UART2_RTS) || \ - ((x) == PIS_UART2_TXOUT) || \ - ((x) == PIS_UART2_SYN_SEND) || \ - ((x) == PIS_UART2_SYN_RECV) || \ - ((x) == PIS_UART3_ASY_SEND) || \ - ((x) == PIS_UART3_ASY_RECV) || \ - ((x) == PIS_UART3_IRDA) || \ - ((x) == PIS_UART3_RTS) || \ - ((x) == PIS_UART3_TXOUT) || \ - ((x) == PIS_UART3_SYN_SEND) || \ - ((x) == PIS_UART3_SYN_RECV) || \ - ((x) == PIS_EUART0_RECV) || \ - ((x) == PIS_EUART0_SEND) || \ - ((x) == PIS_EUART0_TXOUT) || \ - ((x) == PIS_EUART1_RECV) || \ - ((x) == PIS_EUART1_SEND) || \ - ((x) == PIS_EUART1_TXOUT) || \ - ((x) == PIS_SPI0_RECV) || \ - ((x) == PIS_SPI0_SEND) || \ - ((x) == PIS_SPI0_NE) || \ - ((x) == PIS_SPI1_RECV) || \ - ((x) == PIS_SPI1_SEND) || \ - ((x) == PIS_SPI1_NE) || \ - ((x) == PIS_I2C0_RECV) || \ - ((x) == PIS_I2C0_SEND) || \ - ((x) == PIS_I2C1_RECV) || \ - ((x) == PIS_I2C1_SEND) || \ - ((x) == PIS_TIMER0_UPDATA) || \ - ((x) == PIS_TIMER0_TRIG) || \ - ((x) == PIS_TIMER0_INPUT) || \ - ((x) == PIS_TIMER0_OUTPUT) || \ - ((x) == PIS_TIMER1_UPDATA) || \ - ((x) == PIS_TIMER1_TRIG) || \ - ((x) == PIS_TIMER1_INPUT) || \ - ((x) == PIS_TIMER1_OUTPUT) || \ - ((x) == PIS_TIMER2_UPDATA) || \ - ((x) == PIS_TIMER2_TRIG) || \ - ((x) == PIS_TIMER2_INPUT) || \ - ((x) == PIS_TIMER2_OUTPUT) || \ - ((x) == PIS_TIMER3_UPDATA) || \ - ((x) == PIS_TIMER3_TRIG) || \ - ((x) == PIS_TIMER3_INPUT) || \ - ((x) == PIS_TIMER3_OUTPUT) || \ - ((x) == PIS_RTC_CLOCK) || \ - ((x) == PIS_RTC_ALARM) || \ - ((x) == PIS_LPTIM0_SYN_UPDATA) || \ - ((x) == PIS_LPTIM0_ASY_UPDATA) || \ - ((x) == PIS_LPUART0_ASY_RECV) || \ - ((x) == PIS_LPUART0_ASY_SEND) || \ - ((x) == PIS_LPUART0_SYN_RECV) || \ - ((x) == PIS_LPUART0_SYN_SEND) || \ - ((x) == PIS_DMA) || \ - ((x) == PIS_ADC1_INJECT) || \ - ((x) == PIS_ADC1_REGULAT) || \ - ((x) == PIS_ADC1_WINDOW)) -#define IS_PIS_TRIG(x) (((x) == PIS_CH0_TIMER0_BRKIN) || \ - ((x) == PIS_CH0_SPI1_CLK) || \ - ((x) == PIS_CH0_LPTIM0_EXT0) || \ - ((x) == PIS_CH0_ADC1_NORMAL) || \ - ((x) == PIS_CH1_TIMER0_CH1IN) || \ - ((x) == PIS_CH1_TIMER2_CH1IN) || \ - ((x) == PIS_CH1_TIMER3_CH1IN) || \ - ((x) == PIS_CH1_UART0_RX_IRDA) || \ - ((x) == PIS_CH1_LPTIM0_EXT1) || \ - ((x) == PIS_CH1_ADC1_INSERT) || \ - ((x) == PIS_CH2_TIMER0_CH2IN) || \ - ((x) == PIS_CH2_TIMER2_CH2IN) || \ - ((x) == PIS_CH2_TIMER3_CH2IN) || \ - ((x) == PIS_CH2_LPTIM0_EXT2) || \ - ((x) == PIS_CH2_UART1_RX_IRDA) || \ - ((x) == PIS_CH3_TIMER0_CH3IN) || \ - ((x) == PIS_CH3_LPTIM0_EXT3) || \ - ((x) == PIS_CH3_UART2_RX_IRDA) || \ - ((x) == PIS_CH4_TIMER0_CH4IN) || \ - ((x) == PIS_CH4_TIMER0_ITR0) || \ - ((x) == PIS_CH4_TIMER2_ITR0) || \ - ((x) == PIS_CH4_TIMER3_ITR0) || \ - ((x) == PIS_CH4_LPTIM0_EXT4) || \ - ((x) == PIS_CH4_UART3_RX_IRDA) || \ - ((x) == PIS_CH5_SPI0_RX) || \ - ((x) == PIS_CH5_LPTIM0_EXT5) || \ - ((x) == PIS_CH5_EUART0_RX) || \ - ((x) == PIS_CH5_TIMER0_ITR1) || \ - ((x) == PIS_CH5_TIMER2_ITR1) || \ - ((x) == PIS_CH5_TIMER3_ITR1) || \ - ((x) == PIS_CH6_SPI0_CLK) || \ - ((x) == PIS_CH6_ADC0_NORMAL) || \ - ((x) == PIS_CH6_LPTIM0_EXT6) || \ - ((x) == PIS_CH6_EUART1_RX) || \ - ((x) == PIS_CH6_TIMER0_ITR2) || \ - ((x) == PIS_CH6_TIMER2_ITR2) || \ - ((x) == PIS_CH6_TIMER3_ITR2) || \ - ((x) == PIS_CH6_DAC_CH1) || \ - ((x) == PIS_CH7_SPI1_RX) || \ - ((x) == PIS_CH7_ADC0_INSERT) || \ - ((x) == PIS_CH7_LPTIM0_EXT7) || \ - ((x) == PIS_CH7_DMA) || \ - ((x) == PIS_CH7_TIMER0_ITR3) || \ - ((x) == PIS_CH7_TIMER2_ITR3) || \ - ((x) == PIS_CH7_TIMER3_ITR3) || \ - ((x) == PIS_CH7_DAC_CH0) || \ - ((x) == PIS_CH7_LPUART_RX)) -#define IS_PIS_CLOCK(x) (((x) == PIS_CLK_PCLK1) || \ - ((x) == PIS_CLK_PCLK2) || \ - ((x) == PIS_CLK_SYS) || \ - ((x) == PIS_CLK_LP)) -#define IS_PIS_EDGE(x) (((x) == PIS_EDGE_NONE) || \ - ((x) == PIS_EDGE_UP) || \ - ((x) == PIS_EDGE_DOWN) || \ - ((x) == PIS_EDGE_UP_DOWN)) -#define IS_PIS_OUTPUT(x) (((x) == PIS_OUT_LEVEL) || \ - ((x) == PIS_OUT_PULSE)) -#define IS_PIS_OUPUT_CH(x) (((x) == PIS_OUT_CH_0) || \ - ((x) == PIS_OUT_CH_1) || \ - ((x) == PIS_OUT_CH_2) || \ - ((x) == PIS_OUT_CH_3)) -#define IS_PIS_MODU_TARGET(x) (((x) == PIS_UART0_TX) || \ - ((x) == PIS_UART1_TX) || \ - ((x) == PIS_UART2_TX) || \ - ((x) == PIS_UART3_TX) || \ - ((x) == PIS_LPUART0_TX)) -#define IS_PIS_MODU_LEVEL(x) (((x) == PIS_LOW_LEVEL) || \ - ((x) == PIS_HIGH_LEVEL)) -#define IS_PIS_MODU_SRC(x) (((x) == PIS_SRC_NONE) || \ - ((x) == PIS_SRC_TIMER0) || \ - ((x) == PIS_SRC_TIMER1) || \ - ((x) == PIS_SRC_TIMER2) || \ - ((x) == PIS_SRC_TIMER3) || \ - ((x) == PIS_SRC_TIMER6) || \ - ((x) == PIS_SRC_TIMER7) || \ - ((x) == PIS_SRC_LPTIM0) || \ - ((x) == PIS_SRC_BUZ)) -#define IS_PIS_MODU_CHANNEL(x) (((x) == PIS_TIMER_CH1) || \ - ((x) == PIS_TIMER_CH2) || \ - ((x) == PIS_TIMER_CH3) || \ - ((x) == PIS_TIMER_CH4)) -/** - * @} - */ - -/** @addtogroup PIS_Public_Functions - * @{ - */ - -/** @addtogroup PIS_Public_Functions_Group1 - * @{ - */ -ald_status_t pis_create(pis_handle_t *hperh); -ald_status_t pis_destroy(pis_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup PIS_Public_Functions_Group2 - * @{ - */ -ald_status_t pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch); -ald_status_t pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch); -/** - * @} - */ - -/** @addtogroup PIS_Public_Functions_Group3 - * @{ - */ -pis_state_t pis_get_state(pis_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup PIS_Public_Functions_Group4 - * @{ - */ -ald_status_t pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_PIS_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h deleted file mode 100644 index 467e92b07fc8b94673ca111179b7ebb7757772e3..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h +++ /dev/null @@ -1,377 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_spi.c - * @brief Header file of SPI module driver. - * - * @version V1.0 - * @date 13 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_SPI_H__ -#define __ALD_SPI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/** @defgroup SPI_Public_Types SPI Public Types - * @{ - */ - -/** - * @brief clock phase - */ -typedef enum -{ - SPI_CPHA_FIRST = 0, /**< Transiting data in the first edge */ - SPI_CPHA_SECOND = 1, /**< Transiting data in the seconde edge */ -} spi_cpha_t; - -/** - * @brief clock polarity - */ -typedef enum -{ - SPI_CPOL_LOW = 0, /**< Polarity hold low when spi-bus is idle */ - SPI_CPOL_HIGH = 1, /**< Polarity hold high when spi-bus is idle */ -} spi_cpol_t; - -/** - * @brief master selection - */ -typedef enum -{ - SPI_MODE_SLAVER = 0, /**< Slave mode */ - SPI_MODE_MASTER = 1, /**< Master mode */ -} spi_mode_t; - -/** - * @brief baud rate control - */ -typedef enum -{ - SPI_BAUD_2 = 0, /**< fpclk/2 */ - SPI_BAUD_4 = 1, /**< fpclk/4 */ - SPI_BAUD_8 = 2, /**< fpclk/8 */ - SPI_BAUD_16 = 3, /**< fpclk/16 */ - SPI_BAUD_32 = 4, /**< fpclk/32 */ - SPI_BAUD_64 = 5, /**< fpclk/64 */ - SPI_BAUD_128 = 6, /**< fpclk/128 */ - SPI_BAUD_256 = 7, /**< fpclk/256 */ -} spi_baud_t; - -/** - * @brief frame format - */ -typedef enum -{ - SPI_FIRSTBIT_MSB = 0, /**< MSB transmitted first */ - SPI_FIRSTBIT_LSB = 1, /**< LSB transmitted first */ -} spi_firstbit_t; - -/** - * @brief data frame format - */ -typedef enum -{ - SPI_DATA_SIZE_8 = 0, /**< 8-bit data frame format is selected for transmission/reception */ - SPI_DATA_SIZE_16 = 1, /**< 16-bit data frame format is selected for transmission/reception */ -} spi_datasize_t; - -/** - * @brief interrupt control - */ -typedef enum -{ - SPI_IT_ERR = (1U << 5), /**< error interrupt */ - SPI_IT_RXBNE = (1U << 6), /**< rx buffer not empty interrupt */ - SPI_IT_TXBE = (1U << 7), /**< tx buffer empty interrupt */ -} spi_it_t; - -/** - * @brief interrupt flag - */ -typedef enum -{ - SPI_IF_RXBNE = (1U << 0), /**< receive buffer not empty */ - SPI_IF_TXBE = (1U << 1), /**< transmit buffer empty */ - SPI_IF_CRCERR = (1U << 4), /**< crc error flag */ - SPI_IF_MODF = (1U << 5), /**< mode fault */ - SPI_IF_OVE = (1U << 6), /**< overrun flag */ - SPI_IF_BUSY = (1U << 7), /**< busy flag */ -} spi_flag_t; - -/** - * @brief SPI error status - */ -typedef enum -{ - SPI_ERROR_NONE = 0, /**< none */ - SPI_ERROR_MODF = 1, /**< mode fault */ - SPI_ERROR_CRC = 2, /**< crc error */ - SPI_ERROR_OVE = 4, /**< overrun error */ - SPI_ERROR_DMA = 8, /**< dma error */ - SPI_ERROR_FLAG = 0x10, /**< interrupt flag error */ -} spi_error_t; - - - -/** - * @brief SPI state structures definition - */ -typedef enum -{ - SPI_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - SPI_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - SPI_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - SPI_STATE_BUSY_TX = 0x11, /**< transmit is ongoing */ - SPI_STATE_BUSY_RX = 0x21, /**< receive is ongoing */ - SPI_STATE_BUSY_TX_RX = 0x31, /**< transmit and receive are ongoing */ - SPI_STATE_TIMEOUT = 0x03, /**< Timeout state */ - SPI_STATE_ERROR = 0x04, /**< Error */ -} spi_state_t; - - -/** - * @brief SPI direction definition - */ -typedef enum -{ - SPI_DIRECTION_2LINES = 0, /**< 2 lines */ - SPI_DIRECTION_2LINES_RXONLY = 1, /**< 2 lines only rx */ - SPI_DIRECTION_1LINE = 2, /**< 1 line */ - SPI_DIRECTION_1LINE_RX = 3, /**< 1 line only rx */ -} spi_direction_t; - -/** - * @brief SPI dma request definition - */ -typedef enum -{ - SPI_DMA_REQ_TX = 0, /**< TX dma request */ - SPI_DMA_REQ_RX = 1, /**< RX dma request */ -} spi_dma_req_t; - -/** - * @brief SPI TXE/RXNE status definition - */ -typedef enum -{ - SPI_SR_TXBE = 0, /**< SR.TXE set */ - SPI_SR_RXBNE = 1, /**< SR.RXNE set */ - SPI_SR_TXBE_RXBNE = 2, /**< SR.TXE and SR.RXNE set */ -} spi_sr_status_t; - -/** - * @brief SPI init structure definition - */ -typedef struct -{ - spi_mode_t mode; /**< SPI mode */ - spi_direction_t dir; /**< SPI direction */ - spi_datasize_t data_size; /**< SPI data size */ - spi_baud_t baud; /**< SPI baudrate prescaler */ - spi_cpha_t phase; /**< SPI clock phase */ - spi_cpol_t polarity; /**< SPI clock polarity */ - spi_firstbit_t first_bit; /**< SPI first bit */ - type_func_t ss_en; /**< SPI ssm enable or disable */ - type_func_t crc_calc; /**< SPI crc calculation */ - uint16_t crc_poly; /**< SPI crc polynomial */ -} spi_init_t; - -/** - * @brief SPI handle structure definition - */ -typedef struct spi_handle_s -{ - SPI_TypeDef *perh; /**< SPI registers base address */ - spi_init_t init; /**< SPI communication parameters */ - uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */ - uint16_t tx_size; /**< SPI Tx transfer size */ - uint16_t tx_count; /**< SPI Tx transfer counter */ - uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */ - uint16_t rx_size; /**< SPI Rx Transfer size */ - uint16_t rx_count; /**< SPI Rx Transfer Counter */ -#ifdef ALD_DMA - dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */ - dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */ -#endif - lock_state_t lock; /**< Locking object */ - spi_state_t state; /**< SPI communication state */ - uint32_t err_code; /**< SPI error code */ - - void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */ - void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */ - void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */ -} spi_handle_t; -/** - * @} - */ - -/** @defgroup SPI_Public_Macros SPI Public Macros - * @{ - */ -#define SPI_RESET_HANDLE_STATE(x) ((x)->state = SPI_STATE_RESET) -#define SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS)) -#define SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS)) -#define SPI_CRC_RESET(x) \ -do { \ - CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ - SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ -} while (0) -#define SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) -#define SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) -#define SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) -#define SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) -#define SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) -#define SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) -#define SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) -#define SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) -#define SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) -#define SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) -/** - * @} - */ - -/** @defgroup SPI_Private_Macros SPI Private Macros - * @{ - */ -#define IS_SPI(x) (((x) == SPI0) || \ - ((x) == SPI1) || \ - ((x) == SPI2)) -#define IS_SPI_CPHA(x) (((x) == SPI_CPHA_FIRST) || \ - ((x) == SPI_CPHA_SECOND)) -#define IS_SPI_CPOL(x) (((x) == SPI_CPOL_LOW) || \ - ((x) == SPI_CPOL_HIGH)) -#define IS_SPI_MODE(x) (((x) == SPI_MODE_SLAVER) || \ - ((x) == SPI_MODE_MASTER)) -#define IS_SPI_BAUD(x) (((x) == SPI_BAUD_2) || \ - ((x) == SPI_BAUD_4) || \ - ((x) == SPI_BAUD_8) || \ - ((x) == SPI_BAUD_16) || \ - ((x) == SPI_BAUD_32) || \ - ((x) == SPI_BAUD_64) || \ - ((x) == SPI_BAUD_128) || \ - ((x) == SPI_BAUD_256)) -#define IS_SPI_DATASIZE(x) (((x) == SPI_DATA_SIZE_8) || \ - ((x) == SPI_DATA_SIZE_16)) -#define IS_SPI_BIDOE(x) (((x) == SPI_BID_RX) || \ - ((x) == SPI_BID_TX)) -#define IS_SPI_BIDMODE(x) (((x) == SPI_BIDMODE_DUAL) || \ - ((x) == SPI_BIDMODE_SOLE)) -#define IS_SPI_DIRECTION(x) (((x) == SPI_DIRECTION_2LINES) || \ - ((x) == SPI_DIRECTION_2LINES_RXONLY) || \ - ((x) == SPI_DIRECTION_1LINE) || \ - ((x) == SPI_DIRECTION_1LINE_RX)) -#define IS_SPI_DMA_REQ(x) (((x) == SPI_DMA_REQ_TX) || \ - ((x) == SPI_DMA_REQ_RX)) -#define IS_SPI_SR_STATUS(x) (((x) == SPI_SR_TXBE) || \ - ((x) == SPI_SR_RXBNE) || \ - ((x) == SPI_SR_TXBE_RXBNE)) -#define IS_SPI_IT(x) (((x) == SPI_IT_ERR) || \ - ((x) == SPI_IT_RXBNE) || \ - ((x) == SPI_IT_TXBE)) -#define IS_SPI_IF(x) (((x) == SPI_IF_RXBNE) || \ - ((x) == SPI_IF_TXBE) || \ - ((x) == SPI_IF_CRCERR) || \ - ((x) == SPI_IF_MODF) || \ - ((x) == SPI_IF_OVE) || \ - ((x) == SPI_IF_BUSY)) -/** - * @} - */ - -/** @addtogroup SPI_Public_Functions - * @{ - */ - -/** @addtogroup SPI_Public_Functions_Group1 - * @{ - */ - -ald_status_t spi_init(spi_handle_t *hperh); -void spi_reset(spi_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup SPI_Public_Functions_Group2 - * @{ - */ -int32_t spi_send_byte_fast(spi_handle_t *hperh, uint8_t data); -uint8_t spi_recv_byte_fast(spi_handle_t *hperh); -ald_status_t spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); -ald_status_t spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size); -#ifdef ALD_DMA -ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); -ald_status_t spi_dma_pause(spi_handle_t *hperh); -ald_status_t spi_dma_resume(spi_handle_t *hperh); -ald_status_t spi_dma_stop(spi_handle_t *hperh); -#endif -/** - * @} - */ - -/** @addtogroup SPI_Public_Functions_Group3 - * @{ - */ -void spi_irq_handle(spi_handle_t *hperh); -void spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state); -void spi_speed_config(spi_handle_t *hperh, spi_baud_t speed); -void spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state); -it_status_t spi_get_it_status(spi_handle_t *hperh, spi_it_t it); -flag_status_t spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag); -void spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag); -/** - * @} - */ - -/** @addtogroup SPI_Public_Functions_Group4 - * @{ - */ -spi_state_t spi_get_state(spi_handle_t *hperh); -uint32_t spi_get_error(spi_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_temp.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_temp.h deleted file mode 100644 index b9d5c15d15141e54860ea79a606d82e06eca64fb..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_temp.h +++ /dev/null @@ -1,203 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_temp.h - * @brief Header file of TEMP module driver. - * - * @version V1.0 - * @date 15 Dec 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ******************************************************************************** - */ - -#ifndef __ALD_TEMP_H__ -#define __ALD_TEMP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup TEMP - * @{ - */ - -/** @defgroup TEMP_Public_Macros TEMP Public Macros - * @{ - */ -#define TEMP_LOCK() (WRITE_REG(TEMP->WPR, 0x0)) -#define TEMP_UNLOCK() (WRITE_REG(TEMP->WPR, 0xA55A9669)) -#define TEMP_ENABLE() \ -do { \ - TEMP_UNLOCK(); \ - SET_BIT(TEMP->CR, TEMP_CR_EN_MSK); \ - TEMP_LOCK(); \ -} while (0) -#define TEMP_DISABLE() \ -do { \ - TEMP_UNLOCK(); \ - CLEAR_BIT(TEMP->CR, TEMP_CR_EN_MSK); \ - TEMP_LOCK(); \ -} while (0) -#define TEMP_REQ_ENABLE() \ -do { \ - TEMP_UNLOCK(); \ - SET_BIT(TEMP->CR, TEMP_CR_REQEN_MSK); \ - TEMP_LOCK(); \ -} while (0) -#define TEMP_REQ_DISABLE() \ -do { \ - TEMP_UNLOCK(); \ - CLEAR_BIT(TEMP->CR, TEMP_CR_REQEN_MSK); \ - TEMP_LOCK(); \ -} while (0) -#define TEMP_CTN_ENABLE() \ -do { \ - TEMP_UNLOCK(); \ - SET_BIT(TEMP->CR, TEMP_CR_CTN_MSK); \ - TEMP_LOCK(); \ -} while (0) -#define TEMP_CTN_DISABLE() \ -do { \ - TEMP_UNLOCK(); \ - CLEAR_BIT(TEMP->CR, TEMP_CR_CTN_MSK); \ - TEMP_LOCK(); \ -} while (0) -#define TEMP_RESET() \ -do { \ - TEMP_UNLOCK(); \ - SET_BIT(TEMP->CR, TEMP_CR_RST_MSK); \ - TEMP_LOCK(); \ -} while (0) -/** - * @} - */ - -/** @defgroup TEMP_Public_Types TEMP Public Types - * @{ - */ -/** - * @brief Temperature update time - */ -typedef enum -{ - TEMP_UPDATE_CYCLE_3 = 0x3, /**< 3 Cycles */ - TEMP_UPDATE_CYCLE_4 = 0x4, /**< 4 Cycles */ - TEMP_UPDATE_CYCLE_5 = 0x5, /**< 5 Cycles */ - TEMP_UPDATE_CYCLE_6 = 0x6, /**< 6 Cycles */ - TEMP_UPDATE_CYCLE_7 = 0x7, /**< 7 Cycles */ -} temp_update_cycle_t; - -/** - * @brief Temperature output mode - */ -typedef enum -{ - TEMP_OUTPUT_MODE_200 = 0x0, /**< 200 cycles update one temperature */ - TEMP_OUTPUT_MODE_400 = 0x1, /**< 400 cycles update one temperature */ - TEMP_OUTPUT_MODE_800 = 0x2, /**< 800 cycles update one temperature */ - TEMP_OUTPUT_MODE_1600 = 0x3, /**< 1600 cycles update one temperature */ - TEMP_OUTPUT_MODE_3200 = 0x4, /**< 3200 cycles update one temperature */ -} temp_output_mode_t; - -/** - * @brief Source select - */ -typedef enum -{ - TEMP_SOURCE_LOSC = 0x0, /**< LOSC */ - TEMP_SOURCE_LRC = 0x1, /**< LRC */ - TEMP_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */ - TEMP_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */ -} temp_source_sel_t; - - -/** - * @brief TEMP init structure definition - */ -typedef struct -{ - temp_update_cycle_t cycle; /**< Temperature update time */ - temp_output_mode_t mode; /**< Temperature output mode */ - uint8_t ctn; /**< Continue mode */ - uint8_t psc; /**< Perscaler */ -} temp_init_t; - -/** - * @brief Define callback function type - */ -typedef void (*temp_cbk)(uint16_t value, ald_status_t status); -/** - * @} - */ - -/** - * @defgroup TEMP_Private_Macros TEMP Private Macros - * @{ - */ -#define IS_TEMP_UPDATE_CYCLE(x) (((x) == TEMP_UPDATE_CYCLE_3) || \ - ((x) == TEMP_UPDATE_CYCLE_4) || \ - ((x) == TEMP_UPDATE_CYCLE_5) || \ - ((x) == TEMP_UPDATE_CYCLE_6) || \ - ((x) == TEMP_UPDATE_CYCLE_7)) -#define IS_TEMP_OUTPUT_MODE(x) (((x) == TEMP_OUTPUT_MODE_200) || \ - ((x) == TEMP_OUTPUT_MODE_400) || \ - ((x) == TEMP_OUTPUT_MODE_800) || \ - ((x) == TEMP_OUTPUT_MODE_1600) || \ - ((x) == TEMP_OUTPUT_MODE_3200)) -#define IS_TEMP_SOURCE_SEL(x) (((x) == TEMP_SOURCE_LOSC) || \ - ((x) == TEMP_SOURCE_LRC) || \ - ((x) == TEMP_SOURCE_HRC_DIV_1M ) || \ - ((x) == TEMP_SOURCE_HOSC_DIV_1M)) -/** - * @} - */ - -/** @addtogroup TEMP_Public_Functions - * @{ - */ -/** @addtogroup TEMP_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -extern void temp_init(temp_init_t *init); -extern void temp_source_selcet(temp_source_sel_t sel); -/** - * @} - */ -/** @addtogroup TEMP_Public_Functions_Group2 - * @{ - */ -/* Control functions */ -extern ald_status_t temp_get_value(uint16_t *temp); -extern void temp_get_value_by_it(temp_cbk cbk); -void temp_irq_handle(void); -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_TEMP_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h b/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h deleted file mode 100644 index 0d8b1899318a382fdfaf77b7bbeebce63a5a094e..0000000000000000000000000000000000000000 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h +++ /dev/null @@ -1,478 +0,0 @@ -/** - ********************************************************************************* - * - * @file ald_uart.h - * @brief Header file of UART module library. - * - * @version V1.0 - * @date 21 Nov 2017 - * @author AE Team - * @note - * - * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. - * - ********************************************************************************* - */ - -#ifndef __ALD_UART_H__ -#define __ALD_UART_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "utils.h" -#include "ald_dma.h" - - -/** @addtogroup ES32FXXX_ALD - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/** - * @defgroup UART_Public_Macros UART Public Macros - * @{ - */ -#define UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK)) -#define UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK)) -#define UART_BRR_WRITE_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK)) -#define UART_BRR_WRITE_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK)) -#define UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK)) -#define UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK)) -#define UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK)) -#define UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK)) -#define UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK)) -#define UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK)) -#define UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK)) -#define UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK)) -#define UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK)) -#define UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK)) -#define UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK)) -#define UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK)) -#define UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK)) -#define UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK)) -#define UART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_TFRST_MSK)) -#define UART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_RFRST_MSK)) -#define UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK)) -#define UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK)) -#define UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK)) -#define UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK)) -#define UART_AUTOBR_RESTART(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABRRS_MSK)) -#define UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR)) -#define UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS)) -/** - * @} - */ - -/** @defgroup UART_Public_Types UART Public Types - * @{ - */ -/** - * @brief UART word length - */ -typedef enum -{ - UART_WORD_LENGTH_5B = 0x0, /**< 5-bits */ - UART_WORD_LENGTH_6B = 0x1, /**< 6-bits */ - UART_WORD_LENGTH_7B = 0x2, /**< 7-bits */ - UART_WORD_LENGTH_8B = 0x3, /**< 8-bits */ -} uart_word_length_t; - -/** - * @brief UART stop bits - */ -typedef enum -{ - UART_STOP_BITS_1 = 0x0, /**< 1-bits */ - UART_STOP_BITS_2 = 0x1, /**< 2-bits */ - UART_STOP_BITS_0_5 = 0x0, /**< 0.5-bits, using smartcard mode */ - UART_STOP_BITS_1_5 = 0x1, /**< 1.5-bits, using smartcard mode */ -} uart_stop_bits_t; - -/** - * @brief UART parity - */ -typedef enum -{ - UART_PARITY_NONE = 0x0, /**< Not parity */ - UART_PARITY_ODD = 0x1, /**< Odd parity */ - UART_PARITY_EVEN = 0x3, /**< Even parity */ -} uart_parity_t; - -/** - * @brief UART mode - */ -typedef enum -{ - UART_MODE_UART = 0x0, /**< UART */ - UART_MODE_LIN = 0x1, /**< LIN */ - UART_MODE_IrDA = 0x2, /**< IrDA */ - UART_MODE_RS485 = 0x3, /**< RS485 */ - UART_MODE_HDSEL = 0x4, /**< Single-wire half-duplex */ -} uart_mode_t; - -/** - * @brief UART hardware flow control - */ -typedef enum -{ - UART_HW_FLOW_CTL_DISABLE = 0x0, /**< Auto-flow-control disable */ - UART_HW_FLOW_CTL_ENABLE = 0x1, /**< Auto-flow-control enable */ -} uart_hw_flow_ctl_t; - -/** - * @brief ALD UART state - */ -typedef enum -{ - UART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - UART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - UART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - UART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ - UART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ - UART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ - UART_STATE_TIMEOUT = 0x03, /**< Timeout state */ - UART_STATE_ERROR = 0x04, /**< Error */ -} uart_state_t; - -/** - * @brief UART error codes - */ -typedef enum -{ - UART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ - UART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ - UART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ - UART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ - UART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ - UART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ -} uart_error_t; - -/** - * @brief UART init structure definition - */ -typedef struct -{ - uint32_t baud; /**< Specifies the uart communication baud rate */ - uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ - uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ - uart_parity_t parity; /**< Specifies the parity mode */ - uart_mode_t mode; /**< Specifies uart mode */ - uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ -} uart_init_t; - -/** - * @brief UART handle structure definition - */ -typedef struct uart_handle_s -{ - UART_TypeDef *perh; /**< UART registers base address */ - uart_init_t init; /**< UART communication parameters */ - uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */ - uint16_t tx_size; /**< UART Tx Transfer size */ - uint16_t tx_count; /**< UART Tx Transfer Counter */ - uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */ - uint16_t rx_size; /**< UART Rx Transfer size */ - uint16_t rx_count; /**< UART Rx Transfer Counter */ -#ifdef ALD_DMA - dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */ - dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */ -#endif - lock_state_t lock; /**< Locking object */ - uart_state_t state; /**< UART communication state */ - uart_error_t err_code; /**< UART Error code */ - - void (*tx_cplt_cbk)(struct uart_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct uart_handle_s *arg); /**< Rx completed callback */ - void (*error_cbk)(struct uart_handle_s *arg); /**< error callback */ -} uart_handle_t; - -/** - * @brief UART RS485 configure structure definition - */ -typedef struct -{ - type_func_t normal; /**< Normal mode */ - type_func_t dir; /**< Auto-direction mode */ - type_func_t invert; /**< Address detection invert */ - uint8_t addr; /**< Address for compare */ -} uart_rs485_config_t; - -/** - * @brief LIN detection break length - */ -typedef enum -{ - LIN_BREAK_LEN_10B = 0x0, /**< 10-bit break */ - LIN_BREAK_LEN_11B = 0x1, /**< 11-bit break */ -} uart_lin_break_len_t; - -/** - * @brief UART TXFIFO size - */ -typedef enum -{ - UART_TXFIFO_EMPTY = 0x0, /**< Empty */ - UART_TXFIFO_2BYTE = 0x1, /**< 2-Bytes */ - UART_TXFIFO_4BYTE = 0x2, /**< 4-Bytes */ - UART_TXFIFO_8BYTE = 0x3, /**< 8-Bytes */ -} uart_txfifo_t; - -/** - * @brief UART RXFIFO size - */ -typedef enum -{ - UART_RXFIFO_1BYTE = 0x0, /**< 1-Byte */ - UART_RXFIFO_4BYTE = 0x1, /**< 4-Bytes */ - UART_RXFIFO_8BYTE = 0x2, /**< 8-Bytes */ - UART_RXFIFO_14BYTE = 0x3, /**< 14-Bytes */ -} uart_rxfifo_t; - -/** - * @brief UART auto-baud mode - */ -typedef enum -{ - UART_ABRMOD_1_TO_0 = 0x0, /**< Detect bit0:1, bit1:0 */ - UART_ABRMOD_1 = 0x1, /**< Detect bit0:1 */ - UART_ABRMOD_0_TO_1 = 0x2, /**< Detect bit0:0, bit1:1 */ -} uart_auto_baud_mode_t; - -/** - * @brief UART status types - */ -typedef enum -{ - UART_STATUS_DR = (1U << 0), /**< Data ready */ - UART_STATUS_OE = (1U << 1), /**< Overrun error */ - UART_STATUS_PE = (1U << 2), /**< Parity error */ - UART_STATUS_FE = (1U << 3), /**< Framing error */ - UART_STATUS_BI = (1U << 4), /**< Break interrupt */ - UART_STATUS_TBEM = (1U << 5), /**< Transmit buffer empty */ - UART_STATUS_TEM = (1U << 6), /**< Transmitter empty */ - UART_STATUS_RFE = (1U << 7), /**< Reveiver FIFO data error */ - UART_STATUS_BUSY = (1U << 8), /**< UART busy */ - UART_STATUS_TFNF = (1U << 9), /**< Transmit FIFO not full */ - UART_STATUS_TFEM = (1U << 10), /**< Transmit FIFO not empty */ - UART_STATUS_RFNE = (1U << 11), /**< Receive FIFO not empty */ - UART_STATUS_RFF = (1U << 12), /**< Receive FIFO full */ - UART_STATUS_DCTS = (1U << 14), /**< Delta clear to send */ - UART_STATUS_CTS = (1U << 15), /**< Clear to send */ -} uart_status_t; - -/** - * @brief UART interrupt types - */ -typedef enum -{ - UART_IT_RXRD = (1U << 0), /**< Receive data available */ - UART_IT_TXS = (1U << 1), /**< Tx empty status */ - UART_IT_RXS = (1U << 2), /**< Rx line status */ - UART_IT_MDS = (1U << 3), /**< Modem status */ - UART_IT_RTO = (1U << 4), /**< Receiver timeout */ - UART_IT_BZ = (1U << 5), /**< Busy status */ - UART_IT_ABE = (1U << 6), /**< Auto-baud rate detection end */ - UART_IT_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ - UART_IT_LINBK = (1U << 8), /**< Lin break detection */ - UART_IT_TC = (1U << 9), /**< Transmission complete */ - UART_IT_EOB = (1U << 10), /**< End of block */ - UART_IT_CM = (1U << 11), /**< Character match */ -} uart_it_t; - -/** - * @brief UART flags types - */ -typedef enum -{ - UART_IF_RXRD = (1U << 0), /**< Receive data available */ - UART_IF_TXS = (1U << 1), /**< Tx empty status */ - UART_IF_RXS = (1U << 2), /**< Rx line status */ - UART_IF_MDS = (1U << 3), /**< Modem status */ - UART_IF_RTO = (1U << 4), /**< Receiver timeout */ - UART_IF_BZ = (1U << 5), /**< Busy status */ - UART_IF_ABE = (1U << 6), /**< Auto-baud rate detection end */ - UART_IF_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ - UART_IF_LINBK = (1U << 8), /**< Lin break detection */ - UART_IF_TC = (1U << 9), /**< Transmission complete */ - UART_IF_EOB = (1U << 10), /**< End of block */ - UART_IF_CM = (1U << 11), /**< Character match */ -} uart_flag_t; -/** - * @} - */ - -/** @defgroup UART_Private_Macros UART Private Macros - * @{ - */ -#define IS_UART_ALL(x) (((x) == UART0) || \ - ((x) == UART1) || \ - ((x) == UART2) || \ - ((x) == UART3)) -#define IS_UART_WORD_LENGTH(x) (((x) == UART_WORD_LENGTH_5B) || \ - ((x) == UART_WORD_LENGTH_6B) || \ - ((x) == UART_WORD_LENGTH_7B) || \ - ((x) == UART_WORD_LENGTH_8B)) -#define IS_UART_STOPBITS(x) (((x) == UART_STOP_BITS_1) || \ - ((x) == UART_STOP_BITS_2) || \ - ((x) == UART_STOP_BITS_0_5) || \ - ((x) == UART_STOP_BITS_1_5)) -#define IS_UART_PARITY(x) (((x) == UART_PARITY_NONE) || \ - ((x) == UART_PARITY_ODD) || \ - ((x) == UART_PARITY_EVEN)) -#define IS_UART_MODE(x) (((x) == UART_MODE_UART) || \ - ((x) == UART_MODE_LIN) || \ - ((x) == UART_MODE_IrDA) || \ - ((x) == UART_MODE_RS485) || \ - ((x) == UART_MODE_HDSEL)) -#define IS_UART_HARDWARE_FLOW_CONTROL(x) \ - (((x) == UART_HW_FLOW_CTL_DISABLE) || \ - ((x) == UART_HW_FLOW_CTL_ENABLE)) -#define IS_UART_LIN_BREAK_LEN(x) (((x) == LIN_BREAK_LEN_10B) || \ - ((x) == LIN_BREAK_LEN_11B)) -#define IS_UART_TXFIFO_TYPE(x) (((x) == UART_TXFIFO_EMPTY) || \ - ((x) == UART_TXFIFO_2BYTE) || \ - ((x) == UART_TXFIFO_4BYTE) || \ - ((x) == UART_TXFIFO_8BYTE)) -#define IS_UART_RXFIFO_TYPE(x) (((x) == UART_RXFIFO_1BYTE) || \ - ((x) == UART_RXFIFO_4BYTE) || \ - ((x) == UART_RXFIFO_8BYTE) || \ - ((x) == UART_RXFIFO_14BYTE)) -#define IS_UART_AUTO_BAUD_MODE(x) (((x) == UART_ABRMOD_1_TO_0) || \ - ((x) == UART_ABRMOD_1) || \ - ((x) == UART_ABRMOD_0_TO_1)) -#define IS_UART_STATUS(x) (((x) == UART_STATUS_DR) || \ - ((x) == UART_STATUS_OE) || \ - ((x) == UART_STATUS_PE) || \ - ((x) == UART_STATUS_FE) || \ - ((x) == UART_STATUS_BI) || \ - ((x) == UART_STATUS_TBEM) || \ - ((x) == UART_STATUS_TEM) || \ - ((x) == UART_STATUS_RFE) || \ - ((x) == UART_STATUS_BUSY) || \ - ((x) == UART_STATUS_TFNF) || \ - ((x) == UART_STATUS_TFEM) || \ - ((x) == UART_STATUS_RFNE) || \ - ((x) == UART_STATUS_RFF) || \ - ((x) == UART_STATUS_DCTS) || \ - ((x) == UART_STATUS_CTS)) -#define IS_UART_IT(x) (((x) == UART_IT_RXRD) || \ - ((x) == UART_IT_TXS) || \ - ((x) == UART_IT_RXS) || \ - ((x) == UART_IT_MDS) || \ - ((x) == UART_IT_RTO) || \ - ((x) == UART_IT_BZ) || \ - ((x) == UART_IT_ABE) || \ - ((x) == UART_IT_ABTO) || \ - ((x) == UART_IT_LINBK) || \ - ((x) == UART_IT_TC) || \ - ((x) == UART_IT_EOB) || \ - ((x) == UART_IT_CM)) -#define IS_UART_IF(x) (((x) == UART_IF_RXRD) || \ - ((x) == UART_IF_TXS) || \ - ((x) == UART_IF_RXS) || \ - ((x) == UART_IF_MDS) || \ - ((x) == UART_IF_RTO) || \ - ((x) == UART_IF_BZ) || \ - ((x) == UART_IF_ABE) || \ - ((x) == UART_IF_ABTO) || \ - ((x) == UART_IF_LINBK) || \ - ((x) == UART_IF_TC) || \ - ((x) == UART_IF_EOB) || \ - ((x) == UART_IF_CM)) -#define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21)) -#define IS_UART_DATA(x) ((x) <= 0x1FF) - -#define UART_STATE_TX_MASK (1U << 4) -#define UART_STATE_RX_MASK (1U << 5) -/** - * @} - */ - -/** @addtogroup UART_Public_Functions - * @{ - */ - -/** @addtogroup UART_Public_Functions_Group1 - * @{ - */ -/* Initialization functions */ -void uart_init(uart_handle_t *hperh); -void uart_reset(uart_handle_t *hperh); -void uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config); -/** - * @} - */ - -/** @addtogroup UART_Public_Functions_Group2 - * @{ - */ -/* IO operation functions */ -ald_status_t uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); -#ifdef ALD_DMA -ald_status_t uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t uart_dma_pause(uart_handle_t *hperh); -ald_status_t uart_dma_resume(uart_handle_t *hperh); -ald_status_t uart_dma_stop(uart_handle_t *hperh); -#endif -void uart_irq_handle(uart_handle_t *hperh); -/** - * @} - */ - -/** @addtogroup UART_Public_Functions_Group3 - * @{ - */ -/* Peripheral Control functions */ -void uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state); -void uart_dma_req_config(uart_handle_t *hperh, type_func_t state); -void uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level); -void uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level); -void uart_lin_send_break(uart_handle_t *hperh); -void uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len); -void uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode); -ald_status_t uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout); -it_status_t uart_get_it_status(uart_handle_t *hperh, uart_it_t it); -flag_status_t uart_get_status(uart_handle_t *hperh, uart_status_t status); -flag_status_t uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag); -flag_status_t uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag); -void uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag); -/** - * @} - */ - -/** @addtogroup UART_Public_Functions_Group4 - * @{ - */ -/* Peripheral State and Errors functions */ -uart_state_t uart_get_state(uart_handle_t *hperh); -uint32_t uart_get_error(uart_handle_t *hperh); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALD_UART_H__ */ diff --git a/bsp/essemi/es32f0271/.config b/bsp/essemi/es32f0271/.config new file mode 100644 index 0000000000000000000000000000000000000000..15ed9fadcdeec8cb13ace64af79a459d4f28e721 --- /dev/null +++ b/bsp/essemi/es32f0271/.config @@ -0,0 +1,439 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40002 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=2048 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_LIBC_USING_TIME is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_LCD_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +CONFIG_SOC_ES32F0271LT=y + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# + +# +# PIN Drivers +# +CONFIG_BSP_USING_GPIO=y + +# +# UART Drivers +# +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set + +# +# SPI Drivers +# +# CONFIG_BSP_USING_SPI1 is not set +# CONFIG_BSP_USING_SPI2 is not set + +# +# I2C Drivers +# +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_I2C2 is not set + +# +# HWtimer Drivers +# +# CONFIG_BSP_USING_HWTIMER1 is not set + +# +# PWM Drivers +# +# CONFIG_BSP_USING_PWM_GP16C2T1 is not set +# CONFIG_BSP_USING_PWM_GP16C2T4 is not set + +# +# RTC Drivers +# +# CONFIG_BSP_USING_RTC is not set + +# +# ADC Drivers +# +# CONFIG_BSP_USING_ADC is not set + +# +# Onboard Peripheral Drivers +# + +# +# Offboard Peripheral Drivers +# diff --git a/bsp/essemi/es32f0271/Kconfig b/bsp/essemi/es32f0271/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..20657830420ecf9c45d5ba7615ce9dbae0837d2e --- /dev/null +++ b/bsp/essemi/es32f0271/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_ES32F0271LT + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "drivers/Kconfig" diff --git a/bsp/essemi/es32f0271/README.md b/bsp/essemi/es32f0271/README.md new file mode 100644 index 0000000000000000000000000000000000000000..c50443466b595e0d80c7bb507e4b36ed50dc2d1e --- /dev/null +++ b/bsp/essemi/es32f0271/README.md @@ -0,0 +1,95 @@ +# ES-PDS-ES32F0271 开发板 BSP 说明 +标签： EastSoft、国产MCU、Cortex-M0、ES32F0271LT + +## 1. 简介 + +本文档为上海东软载波微电子开发团队为 ES-PDS-ES32F0271 开发板提供的 BSP (板级支持包) 说明。 +通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +### 1.1 开发板介绍 + +主要内容如下： +ES-PDS-ES32F0271 是东软载波微电子官方推出的一款基于 ARM Cortex-M0 内核的开发板，最高主频为 48MHz，可满足基础功能测试及高端功能扩展等开发需求。 + +ES-PDS-ES32F0271-V1.1 + +该开发板常用 **板载资源** 如下： + +- MCU：ES32F0271LT，主频 48MHz，8KB SRAM，64KB FLASH +- 外部模块：SPI FLASH (MX25L64，8MB)、I2C EEPROM (M24C04，512B) +- 常用外设 + - 可调电阻：1个，(PC03) + - LED：2个，(PD03/PB08) + - 五轴按键： +- 常用接口：GPIO、UART、SPI、I2C +- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载 + +外设支持: + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :---------------- | :----------: | :------------------------------------| +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | GPIOs | +| UART | 支持 | UART1/2/3 | +| SPI | 支持 | SPI1/2 | +| I2C | 支持 | I2C1/2 | +| PWM | 支持 | PWM1/2 | +| TIMER | 支持 | TIMER1 | +| RTC | 支持 | RTC | +| ADC | 支持 | ADC | + +### 1.2 注意事项 + +- 本BSP中，SPI2和PWM2不能同时使用 + +更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/) + +## 2. 快速上手 + +本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +### 硬件连接 + +使用 ESLinkⅡ (自带 CDC 串口)或 Jlink 等调试工具连接开发板到 PC端，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 UART1_TX(PB06)、UART1_RX(PB07)、GND 接到串口工具上。 + +ESLinkⅡ(mini) + ES-PDS-ES32F0271-V1.1 + +### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。 + +### 运行结果 + +下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。 + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build Oct 31 2019 + 2006 - 2019 Copyright by rt-thread team +msh > +``` +## 3. 进阶使用 + +此 BSP 默认只开启了 GPIO 和 uart1 的功能，如果需使用 Flash 等更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/) + +## 4. 联系人信息 + +- [yuzr](https://github.com/essemi-yuzr) + +## 5. 参考 + +- [ EastSoft 官网](http://www.essemi.com) + diff --git a/bsp/es32f0654/SConscript b/bsp/essemi/es32f0271/SConscript similarity index 100% rename from bsp/es32f0654/SConscript rename to bsp/essemi/es32f0271/SConscript diff --git a/bsp/essemi/es32f0271/SConstruct b/bsp/essemi/es32f0271/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..164265293da6f0f0240d637f812532529b46881b --- /dev/null +++ b/bsp/essemi/es32f0271/SConstruct @@ -0,0 +1,39 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/es32f0654/applications/SConscript b/bsp/essemi/es32f0271/applications/SConscript similarity index 100% rename from bsp/es32f0654/applications/SConscript rename to bsp/essemi/es32f0271/applications/SConscript diff --git a/bsp/essemi/es32f0271/applications/main.c b/bsp/essemi/es32f0271/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..31e31d355d224ddbbb20a84752b06d6733581492 --- /dev/null +++ b/bsp/essemi/es32f0271/applications/main.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#include +#include + +#define LED_PIN 61 + +int main(void) +{ + /* LED pin configuration */ + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(1000); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(1000); + } +} diff --git a/bsp/essemi/es32f0271/drivers/Kconfig b/bsp/essemi/es32f0271/drivers/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..37265a5ba811e1cec537e98bc0efb68e4b3ef250 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/Kconfig @@ -0,0 +1,102 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + menu "PIN Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + endmenu + + menu "UART Drivers" + config BSP_USING_UART1 + bool "Enable UART1 PB06/PB07(T/R)" + select RT_USING_SERIAL + default y + + config BSP_USING_UART2 + bool "Enable UART2 PA02/PA03(T/R)" + select RT_USING_SERIAL + default n + + config BSP_USING_UART3 + bool "Enable UART3 PC06/PC07(T/R)" + select RT_USING_SERIAL + default n + endmenu + + menu "SPI Drivers" + config BSP_USING_SPI1 + bool "Enable SPI1 BUS PB03/PB04/PB05(CLK/MISO/MOSI)" + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS PB13/PB14/PB15(CLK/MISO/MOSI)" + select RT_USING_SPI + select RT_USING_PIN + default n + depends on !BSP_USING_PWM_GP16C2T4 + endmenu + + menu "I2C Drivers" + config BSP_USING_I2C1 + bool "Enable I2C1 BUS PC12/PD02(SCL/SDA)" + select RT_USING_I2C + default n + + config BSP_USING_I2C2 + bool "Enable I2C2 BUS PB10/PB11(SCL/SDA)" + select RT_USING_I2C + default n + endmenu + + menu "HWtimer Drivers" + + config BSP_USING_HWTIMER1 + bool "Using timer1" + select RT_USING_HWTIMER + default n + endmenu + + menu "PWM Drivers" + + config BSP_USING_PWM_GP16C2T1 + bool "Using PWM_1(GP16C2T1) PB01/PB02" + select RT_USING_PWM + default n + + config BSP_USING_PWM_GP16C2T4 + bool "Using PWM2(GP16C2T4) PB12/PB14" + select RT_USING_PWM + default n + depends on !BSP_USING_SPI2 + + endmenu + + menu "RTC Drivers" + config BSP_USING_RTC + bool "Using RTC" + select RT_USING_RTC + default n + endmenu + + menu "ADC Drivers" + config BSP_USING_ADC + bool "Using ADC" + select RT_USING_ADC + default n + endmenu + + endmenu + + menu "Onboard Peripheral Drivers" + + endmenu + + menu "Offboard Peripheral Drivers" + + endmenu + +endmenu diff --git a/bsp/essemi/es32f0271/drivers/SConscript b/bsp/essemi/es32f0271/drivers/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..3be3df80c59c61bd23f3d02f367d0a9463b598c9 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/SConscript @@ -0,0 +1,45 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(''' +board.c +''') + +# add gpio code +if GetDepend('RT_USING_PIN'): + src += ['drv_gpio.c'] + +# add serial driver code +if GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'): + src += ['drv_uart.c'] + +# add spi driver code +if GetDepend('BSP_USING_SPI1') or GetDepend('BSP_USING_SPI2'): + src += ['drv_spi.c'] + +# add i2c driver code +if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2'): + src += ['drv_i2c.c'] + +# add pwm driver code +if GetDepend('BSP_USING_PWM1') or GetDepend('BSP_USING_PWM2') or GetDepend('BSP_USING_PWM3') or GetDepend('BSP_USING_PWM4') or GetDepend('BSP_USING_PWM_GP16C2T1') or GetDepend('BSP_USING_PWM_GP16C2T4'): + src += ['drv_pwm.c'] + +# add hwtimer driver code +if GetDepend('BSP_USING_HWTIMER1'): + src += ['drv_hwtimer.c'] + +# add rtc driver code +if GetDepend(['BSP_USING_RTC']): + src += ['drv_rtc.c'] + +# add adc driver code +if GetDepend(['BSP_USING_ADC']): + src += ['drv_adc.c'] + +CPPPATH = [cwd] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/essemi/es32f0271/drivers/board.c b/bsp/essemi/es32f0271/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..8ebc351ff1922c195befbd24629a557c95a098f1 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/board.c @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#include +#include +#include "board.h" +#include "drv_uart.h" +#include "drv_gpio.h" +#include "md_gpio.h" + +/** + * @addtogroup es32f0 + */ + +/*@{*/ + +/******************************************************************************* +* Function Name : NVIC_Configuration +* Description : Configures Vector Table base location. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_Configuration(void) +{ +} + +/******************************************************************************* + * Function Name : SystemClock_Configuration + * Description : Configures the System Clock. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SystemClock_Config(void) +{ + /*-------------------------Clock Config-------------------------/ + * Config system clock to 48MHz of which the clock source + * is PLL0. + */ + + // + // Open PLL0/HRC then wait it ready. + // + SET_BIT(RCU->CON, RCU_CON_PLL0ON_MSK); + SET_BIT(RCU->CON, RCU_CON_HRCON_MSK); + + /* Wait HRC clock steady. */ + while (!READ_BIT(RCU->CON, RCU_CON_HRCRDY_MSK)); + + // + // Change system clock source,PLL0,48MHz. + // + /* Chose PLL0 as system clock. */ + MODIFY_REG(RCU->CFG, RCU_CFG_SW_MSK, (0x4 << RCU_CFG_SW_POSS)); + /* Config mul of PLL0. */ + MODIFY_REG(RCU->CFG, RCU_CFG_PLLMUL_MSK, (11 << RCU_CFG_PLLMUL_POSS)); + + // + // Start to change system clock and wait it ready. + // + /* Config flash read wait time. */ + MODIFY_REG(FC->CON, FC_CON_WAIT_MSK, (0X2 << FC_CON_WAIT_POSS)); + /* Start to change. */ + SET_BIT(RCU->CFG, RCU_CFG_CKCFG_MSK); + + /* Wait system clock ready. */ + while (!READ_BIT(RCU->CON, RCU_CON_SWRDY_MSK)); + + // + // Remember the system clock. + // + SystemCoreClock = 48000000; +} + +/******************************************************************************* + * Function Name : SysTick_Configuration + * Description : Configures the SysTick for OS tick. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SysTick_Configuration(void) +{ + /* ticks = sysclk / RT_TICK_PER_SECOND */ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/*@}*/ +/** + * This function will initial ES32F0 board. + */ +void rt_hw_board_init(void) +{ + /* NVIC Configuration */ + NVIC_Configuration(); + + /*System Clock Configuration */ + SystemClock_Config(); + + /* Configure the SysTick */ + SysTick_Configuration(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} + diff --git a/bsp/essemi/es32f0271/drivers/board.h b/bsp/essemi/es32f0271/drivers/board.h new file mode 100644 index 0000000000000000000000000000000000000000..b1cb44890d2d77bc21a950af016385f833d90a96 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/board.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "es32f0271.h" + +#define ES32F0_SRAM_SIZE 0x2000 +#define ES32F0_SRAM_END (0x20000000 + ES32F0_SRAM_SIZE) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ + #pragma section="HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern int __bss_end; + #define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END ES32F0_SRAM_END + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_adc.c b/bsp/essemi/es32f0271/drivers/drv_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..d111b54f22bbdd263b3fe2df08c7300e91f758df --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_adc.c @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#include +#include +#include +#include "board.h" +#include "drv_adc.h" +#include "md_gpio.h" +#include "md_adc.h" +#include "md_rcu.h" +#include "md_syscfg.h" + +#ifdef RT_USING_ADC + +#define BSP_ADC_CHANNEL_NUM 8 + +/* define adc instance */ +static struct rt_adc_device _device_adc0; + +/* enable or disable adc */ +static rt_err_t es32f0_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +{ + RT_ASSERT(device != RT_NULL); + + if (enabled) + { + md_adc_enable_ssen_ss0en(ADC); + } + else + { + md_adc_disable_ssen_ss0en(ADC); + } + + return RT_EOK; +} + +static void _adc_channel_config(rt_uint32_t channel) +{ + /* select gpio pin as adc function */ + switch (channel) + { + case 0: + md_gpio_set_mode(GPIOA, MD_GPIO_PIN_0, MD_GPIO_MODE_ANALOG); + break; + case 1: + md_gpio_set_mode(GPIOA, MD_GPIO_PIN_1, MD_GPIO_MODE_ANALOG); + break; + case 2: + md_gpio_set_mode(GPIOA, MD_GPIO_PIN_2, MD_GPIO_MODE_ANALOG); + break; + case 3: + md_gpio_set_mode(GPIOA, MD_GPIO_PIN_3, MD_GPIO_MODE_ANALOG); + break; + case 4: + md_gpio_set_mode(GPIOA, MD_GPIO_PIN_4, MD_GPIO_MODE_ANALOG); + break; + case 5: + md_gpio_set_mode(GPIOA, MD_GPIO_PIN_5, MD_GPIO_MODE_ANALOG); + break; + case 6: + md_gpio_set_mode(GPIOA, MD_GPIO_PIN_6, MD_GPIO_MODE_ANALOG); + break; + case 7: + md_gpio_set_mode(GPIOA, MD_GPIO_PIN_7, MD_GPIO_MODE_ANALOG); + break; + default: + break; + } +} + +static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + rt_uint32_t chn_data[BSP_ADC_CHANNEL_NUM]; + rt_uint32_t i; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(value != RT_NULL); + + /* config adc channel */ + _adc_channel_config(channel); + + md_adc_set_swtri_ss0(ADC); + + while ((ADC->RIF & ADC_RIF_SS0RIF_MSK) == 0); + + for (i=0; i +#include +#include "board.h" +#include "drv_gpio.h" + +#ifdef RT_USING_PIN + +#define __ES32F0_PIN(index, gpio, gpio_index) {index, GPIO##gpio, gpio_index} +#define __ES32F0_PIN_DEFAULT {-1, 0, 0} + +/* ES32F0 GPIO driver */ +struct pin_index +{ + int index; + GPIO_TypeDef *gpio; + uint32_t pin; +}; + +static const struct pin_index pins[] = +{ + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(2, C, 13), + __ES32F0_PIN(3, C, 14), + __ES32F0_PIN(4, C, 15), + __ES32F0_PIN(5, D, 14), + __ES32F0_PIN(6, D, 15), + __ES32F0_PIN(7, D, 13), + __ES32F0_PIN(8, C, 0), + __ES32F0_PIN(9, C, 1), + __ES32F0_PIN(10, C, 2), + __ES32F0_PIN(11, C, 3), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(14, A, 0), + __ES32F0_PIN(15, A, 1), + __ES32F0_PIN(16, A, 2), + __ES32F0_PIN(17, A, 3), + __ES32F0_PIN(18, D, 0), + __ES32F0_PIN(19, D, 1), + __ES32F0_PIN(20, A, 4), + __ES32F0_PIN(21, A, 5), + __ES32F0_PIN(22, A, 6), + __ES32F0_PIN(23, A, 7), + __ES32F0_PIN(24, C, 4), + __ES32F0_PIN(25, C, 5), + __ES32F0_PIN(26, B, 0), + __ES32F0_PIN(27, B, 1), + __ES32F0_PIN(28, B, 2), + __ES32F0_PIN(29, B, 10), + __ES32F0_PIN(30, B, 11), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(33, B, 12), + __ES32F0_PIN(34, B, 13), + __ES32F0_PIN(35, B, 14), + __ES32F0_PIN(36, B, 15), + __ES32F0_PIN(37, C, 6), + __ES32F0_PIN(38, C, 7), + __ES32F0_PIN(39, C, 8), + __ES32F0_PIN(40, C, 9), + __ES32F0_PIN(41, A, 8), + __ES32F0_PIN(42, A, 9), + __ES32F0_PIN(43, A, 10), + __ES32F0_PIN(44, A, 11), + __ES32F0_PIN(45, A, 12), + __ES32F0_PIN(46, A, 13), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(49, A, 14), + __ES32F0_PIN(50, A, 15), + __ES32F0_PIN(51, C, 10), + __ES32F0_PIN(52, C, 11), + __ES32F0_PIN(53, C, 12), + __ES32F0_PIN(54, D, 2), + __ES32F0_PIN(55, B, 3), + __ES32F0_PIN(56, B, 4), + __ES32F0_PIN(57, B, 5), + __ES32F0_PIN(58, B, 6), + __ES32F0_PIN(59, B, 7), + __ES32F0_PIN(60, D, 3), + __ES32F0_PIN(61, B, 8), + __ES32F0_PIN(62, B, 9), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; +static const struct pin_irq_map pin_irq_map[] = +{ + {0, EXTI_0to1_IRQn}, + {1, EXTI_0to1_IRQn}, + {2, EXTI_2to3_IRQn}, + {3, EXTI_2to3_IRQn}, + {4, EXTI_4to15_IRQn}, + {5, EXTI_4to15_IRQn}, + {6, EXTI_4to15_IRQn}, + {7, EXTI_4to15_IRQn}, + {8, EXTI_4to15_IRQn}, + {9, EXTI_4to15_IRQn}, + {10, EXTI_4to15_IRQn}, + {11, EXTI_4to15_IRQn}, + {12, EXTI_4to15_IRQn}, + {13, EXTI_4to15_IRQn}, + {14, EXTI_4to15_IRQn}, + {15, EXTI_4to15_IRQn}, +}; + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, +}; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + return index; +}; + +void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* Write GPIO */ + if (value == 0) + SET_BIT(index->gpio->BSBR, 0x1<<(index->pin+16)); + else + SET_BIT(index->gpio->BSBR, 0x1<pin); +} + +int es32f0_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + value = PIN_LOW; + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + + /* Read the GPIO value with the spcified index */ + value = (index->gpio->IDATA & (0x1<pin)) != 0; + + return value; +} + +void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + GPIO_TypeDef *gpiox; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* Get the IO port */ + gpiox = index->gpio; + + /* Config GPIO */ + switch(mode) + { + case PIN_MODE_OUTPUT: + { + /* pushpull & output & 16mA */ + MODIFY_REG(gpiox->MOD, (0x3<<(index->pin*2)), (0x1<<(index->pin*2))); + CLEAR_BIT(gpiox->OT, (0x1<pin)); + CLEAR_BIT(gpiox->DS, (0x1<pin)); + break; + } + case PIN_MODE_OUTPUT_OD: + { + /* opendrain & output & 16mA */ + MODIFY_REG(gpiox->MOD, (0x3<pin), (0x1<pin)); + SET_BIT(gpiox->OT, (0x1<pin)); + CLEAR_BIT(gpiox->DS, (0x1<pin)); + break; + } + case PIN_MODE_INPUT: + { + /* input & no pull & CMOS & filter */ + MODIFY_REG(gpiox->MOD, (0x3<pin), (0x0<pin)); + MODIFY_REG(gpiox->PUD, (0x3<pin), (0x0<pin)); + SET_BIT(gpiox->IST, (0x1<pin)); + SET_BIT(gpiox->FIR, (0x1<pin)); + break; + } + case PIN_MODE_INPUT_PULLUP: + { + /* input & pull up & CMOS & filter */ + MODIFY_REG(gpiox->MOD, (0x3<pin), (0x0<pin)); + MODIFY_REG(gpiox->PUD, (0x3<pin), (0x1<pin)); + SET_BIT(gpiox->IST, (0x1<pin)); + SET_BIT(gpiox->FIR, (0x1<pin)); + break; + } + case PIN_MODE_INPUT_PULLDOWN: + { + /* input & pull down & CMOS & filter */ + MODIFY_REG(gpiox->MOD, (0x3<pin), (0x0<pin)); + MODIFY_REG(gpiox->PUD, (0x3<pin), (0x2<pin)); + SET_BIT(gpiox->IST, (0x1<pin)); + SET_BIT(gpiox->FIR, (0x1<pin)); + break; + } + default: + { + /* output */ + MODIFY_REG(gpiox->MOD, (0x3<pin), (0x1<pin)); + } + } +} + +rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin) +{ + rt_int32_t mapindex = gpio_pin & 0x00FF; + if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; + +rt_err_t es32f0_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + /* pin no. convert to dec no. */ + for (irqindex = 0; irqindex < 16; irqindex++) + { + if ((0x01 << irqindex) == index->pin) + { + break; + } + } + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +rt_err_t es32f0_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = index->pin & 0x00FF; + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + GPIO_TypeDef *gpiox; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + + /* Get the IO port */ + gpiox = index->gpio; + + if (enabled == PIN_IRQ_ENABLE) + { + /* pin no. convert to dec no. */ + for (irqindex = 0; irqindex < 16; irqindex++) + { + if ((0x01 << irqindex) == index->pin) + { + break; + } + } + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + irqmap = &pin_irq_map[irqindex]; + + /* Config EXTI */ + MODIFY_REG(gpiox->MOD, (0x3<pin), (0x0<pin)); + SET_BIT(gpiox->FIR, index->pin); + SET_BIT(gpiox->IST, index->pin); + MODIFY_REG(((uint32_t *)(&EXTI->ICFG1))[index->pin/8], + 0xF<<(index->pin%8), + (((uint32_t)(index->gpio) - AHB2_BASE)/0x400)<<(index->pin%8)); + SET_BIT(EXTI->DB, 0x1<pin); + + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + { + /* pull down the pin */ + MODIFY_REG(gpiox->PUD, (0x3<pin), (0x2<pin)); + /* Enable EXTI rising interrupt and disable falling interrupt */ + SET_BIT(EXTI->RTS, (0x1<pin)); + CLEAR_BIT(EXTI->FTS, (0x1<pin)); + break; + } + case PIN_IRQ_MODE_FALLING: + { + /* pull up the pin */ + MODIFY_REG(gpiox->PUD, (0x3<pin), (0x1<pin)); + /* Enable EXTI falling interrupt and disable rising interrupt */ + CLEAR_BIT(EXTI->RTS, (0x1<pin)); + SET_BIT(EXTI->FTS, (0x1<pin)); + break; + } + case PIN_IRQ_MODE_RISING_FALLING: + { + /* pull up the pin */ + MODIFY_REG(gpiox->PUD, (0x3<pin), (0x1<pin)); + /* Enable EXTI falling interrupt and enable rising interrupt */ + SET_BIT(EXTI->RTS, (0x1<pin)); + SET_BIT(EXTI->FTS, (0x1<pin)); + break; + } + } + + /* Enable EXTI interrupt */ + SET_BIT(EXTI->IER, (0x1<pin)); + NVIC_EnableIRQ(irqmap->irqno); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return RT_ENOSYS; + } + NVIC_DisableIRQ(irqmap->irqno); + } + else + { + return RT_ENOSYS; + } + return RT_EOK; +} + +const static struct rt_pin_ops _es32f0_pin_ops = +{ + es32f0_pin_mode, + es32f0_pin_write, + es32f0_pin_read, + es32f0_pin_attach_irq, + es32f0_pin_detach_irq, + es32f0_pin_irq_enable, +}; + +int rt_hw_pin_init(void) +{ + int result; + + /* Open IO clock */ + SET_BIT(RCU->AHBEN, RCU_AHBEN_GPDEN_MSK|RCU_AHBEN_GPCEN_MSK \ + |RCU_AHBEN_GPBEN_MSK|RCU_AHBEN_GPAEN_MSK); + + /* register IO device */ + result = rt_device_pin_register("pin", &_es32f0_pin_ops, RT_NULL); + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +rt_inline void pin_irq_hdr(uint16_t GPIO_Pin) +{ + uint16_t irqno; + /* pin no. convert to dec no. */ + for (irqno = 0; irqno < 16; irqno++) + { + if ((0x01 << irqno) == GPIO_Pin) + { + break; + } + } + if (irqno == 16) + return; + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +void GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Read the exti interrupt then clear the flag */ + if ((EXTI->RIF & (0x1<ICR, 0x1< +#include +#include +#include +#include +#include "md_ad16c4t.h" +#include "md_rcu.h" + +#ifdef RT_USING_HWTIMER + +/* Defien the hardware timer control struct */ +struct es32f0_hwtimer_dev +{ + rt_hwtimer_t parent; + AD16C4T_TypeDef *hwtimer_periph; + IRQn_Type IRQn; +}; + +#ifdef BSP_USING_HWTIMER1 +static struct es32f0_hwtimer_dev hwtimer1; + +void BS16T1_IRQHandler(void) +{ + /* if BS16T1 IT */ + if (BS16T1->IFM & AD16C4T_RIF_UI_MSK) + { + SET_BIT(BS16T1->ICR, AD16C4T_ICR_UI_MSK); + rt_device_hwtimer_isr(&hwtimer1.parent); + + if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode) + { + CLEAR_BIT(BS16T1->CON1, AD16C4T_CON1_CNTEN_MSK); + } + } +} +#endif + +static struct rt_hwtimer_info es32f0_hwtimer_info = +{ + 48000000, /* maximum count frequency */ + 1, /* minimum count frequency */ + 65535, /* counter maximum value */ + HWTIMER_CNTMODE_UP +}; + +static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) +{ + struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; + + RT_ASSERT(hwtimer != RT_NULL); + + if (1 == state) + { + /* Set frequency */ + WRITE_REG(hwtimer->hwtimer_periph->PRES, (SystemCoreClock/hwtimer->parent.freq - 1)); + /* Enable timer IT */ + SET_BIT(hwtimer->hwtimer_periph->IER, AD16C4T_IER_UI_MSK); + NVIC_EnableIRQ(hwtimer->IRQn); + } + else + { + /* Dsiable timer IT */ + SET_BIT(hwtimer->hwtimer_periph->IDR, AD16C4T_IER_UI_MSK); + } +} + +static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer, + rt_uint32_t cnt, + rt_hwtimer_mode_t mode) +{ + struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; + + RT_ASSERT(hwtimer != RT_NULL); + + WRITE_REG(hwtimer->hwtimer_periph->AR, cnt); + SET_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK); + + return RT_EOK; +} + +static void es32f0_hwtimer_stop(rt_hwtimer_t *timer) +{ + struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; + + RT_ASSERT(hwtimer != RT_NULL); + + CLEAR_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK); +} + +static rt_uint32_t es32f0_hwtimer_count_get(rt_hwtimer_t *timer) +{ + struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; + uint32_t hwtimer_count = 0; + + RT_ASSERT(hwtimer != RT_NULL); + + hwtimer_count = READ_REG(hwtimer->hwtimer_periph->COUNT); + + return hwtimer_count; +} + +static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer, + rt_uint32_t cmd, + void *args) +{ + rt_err_t ret = RT_EOK; + rt_uint32_t freq = 0; + struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; + + RT_ASSERT(hwtimer != RT_NULL); + + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + freq = *(rt_uint32_t *)args; + if ((freq < hwtimer->parent.info->minfreq) || (freq > hwtimer->parent.info->maxfreq)) + { + ret = RT_EINVAL; + } + /* Set frequency */ + WRITE_REG(hwtimer->hwtimer_periph->PRES, (SystemCoreClock/freq - 1)); + break; + + case HWTIMER_CTRL_STOP: + CLEAR_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK); + break; + + default: + ret = RT_EINVAL; + break; + } + + return ret; +} + +static struct rt_hwtimer_ops es32f0_hwtimer_ops = +{ + es32f0_hwtimer_init, + es32f0_hwtimer_start, + es32f0_hwtimer_stop, + es32f0_hwtimer_count_get, + es32f0_hwtimer_control +}; + +int rt_hw_hwtimer_init(void) +{ + rt_err_t ret = RT_EOK; + +#ifdef BSP_USING_HWTIMER1 + /*Open clock*/ + SET_BIT(RCU->APB1EN, RCU_APB1EN_BS16T1EN_MSK); + + hwtimer1.hwtimer_periph = BS16T1; + hwtimer1.IRQn = BS16T1_IRQn; + hwtimer1.parent.info = &es32f0_hwtimer_info; + hwtimer1.parent.ops = &es32f0_hwtimer_ops; + ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1); +#endif + + return ret; +} +INIT_BOARD_EXPORT(rt_hw_hwtimer_init); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_hwtimer.h b/bsp/essemi/es32f0271/drivers/drv_hwtimer.h new file mode 100644 index 0000000000000000000000000000000000000000..576671e73537d41c6b8b000b7434e2bbe48fbe68 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_hwtimer.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#ifndef DRV_HWTIMER_H__ +#define DRV_HWTIMER_H__ + +int rt_hw_hwtimer_init(void); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_i2c.c b/bsp/essemi/es32f0271/drivers/drv_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..5d863fc447617652b6e93716375231c992cf8d6d --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_i2c.c @@ -0,0 +1,275 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#include +#include +#include +#include "board.h" +#include "drv_i2c.h" +#include "md_i2c.h" +#include "md_gpio.h" + +#ifdef RT_USING_I2C + +#define TIMEOUT 0xF +/* Define I2C hardware SCL timeout */ +#define I2C_TIMING_48MHZ_CLK100KHZ ((0xBU<<28)|(4<<20)|(2<<16)|(0xF<<8)|(0x13)) + +/** + * @brief: I2C receive. + * @param: i2cx, pointer to the I2Cx + * @param: addr, address + * @param: buf, send data buffer + * @param: len, the length of buf + * @param: timout, timeout + * @retval: rt_err_t + */ +static rt_err_t __i2c_master_recv(I2C_TypeDef *i2cx, rt_uint16_t addr, + rt_uint8_t *buf, rt_uint16_t len, rt_uint32_t timout) +{ + rt_uint32_t rt_timout; + + // + // Config I2C transfer mode + // + md_i2c_set_con2_add10(i2cx, MD_I2C_ADDRESSINGMODE_7BIT); + /* Config slaver address */ + md_i2c_set_con2_sadd(i2cx, addr); + /* Config data size */ + md_i2c_set_con2_nbytes(i2cx, len); + /* Reset TX FIFO */ + md_i2c_set_fcon_txfrst(i2cx, MD_I2C_TXFIFO_RESET); + /* Config mode */ + md_i2c_set_con2_rd_wrn(i2cx, MD_I2C_MASTER_READ); + /* Config auto-reload */ + md_i2c_set_con2_reload(i2cx, MD_I2C_NORELOAD_MODE); + /* When NBYTES is matched, the communication will be automatically stop */ + md_i2c_set_con2_autoend(i2cx, MD_I2C_AUTOEND_MODE); + /* Start the I2C communication */ + md_i2c_set_con2_start(i2cx, MD_I2C_START_GENERATION); + + while (len > 0) + { + /* Wait Rx FIFO non-empty */ + rt_timout = timout; + while (md_i2c_is_active_stat_rxe(i2cx) && (--rt_timout)); + if (rt_timout == 0) + return RT_ETIMEOUT; + + *buf++ = md_i2c_recv(i2cx); + len--; + } + + return RT_EOK; +} + +/** + * @brief: I2C send. + * @param: i2cx, pointer to the I2Cx + * @param: addr, address + * @param: buf, send data buffer + * @param: len, the length of buf + * @param: timout, timeout + * @retval: rt_err_t + */ +static rt_err_t __i2c_master_send(I2C_TypeDef *i2cx, rt_uint16_t addr, + rt_uint8_t *buf, rt_uint16_t len, rt_uint32_t timout) +{ + rt_uint32_t rt_timout; + rt_uint8_t index; + + // + // Config I2C transfer mode + // + md_i2c_set_con2_add10(i2cx, MD_I2C_ADDRESSINGMODE_7BIT); + /* Config slaver address */ + md_i2c_set_con2_sadd(i2cx, addr); + /* Config data size */ + md_i2c_set_con2_nbytes(i2cx, len); + /* Reset TX FIFO */ + md_i2c_set_fcon_txfrst(i2cx, MD_I2C_TXFIFO_RESET); + /* Config mode */ + md_i2c_set_con2_rd_wrn(i2cx, MD_I2C_MASTER_WRITE); + /* Enable auto-end */ + md_i2c_set_con2_autoend(i2cx, MD_I2C_AUTOEND_MODE); + + // + // Check if the bus is busy + // + /* Wait bus to be ready */ + rt_timout = timout; + while ((READ_BIT(i2cx->STAT, I2C_STAT_BUSY_MSK) == I2C_STAT_BUSY_MSK) && (--rt_timout)); + if (rt_timout == 0) + return RT_EBUSY; + + // + // Start to send + // + if (len <= 8) + { + for (index = 0; index < len; index++) + md_i2c_send(i2cx, *buf++); + + len = 0; + } + else + { + for (index = 0; index < 8; index++) + md_i2c_send(i2cx, *buf++); + + len -= 8; + } + + /* Start the I2C communication */ + md_i2c_set_con2_start(i2cx, MD_I2C_START_GENERATION); + + while (len > 0) + { + rt_timout = timout; + while (md_i2c_is_active_stat_txf(i2cx) && (--rt_timout)); + if (rt_timout == 0) + return RT_ETIMEOUT; + + md_i2c_send(i2cx, *buf++); + len--; + } + + return RT_EOK; +} + +static rt_size_t es32f0_master_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + struct rt_i2c_msg *msg; + rt_uint32_t i; + rt_err_t ret = RT_ERROR; + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + if (msg->flags & RT_I2C_RD) + { + if (__i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) + { + i2c_dbg("i2c bus write failed,i2c bus stop!\n"); + goto out; + } + } + else + { + if (__i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) + { + i2c_dbg("i2c bus write failed,i2c bus stop!\n"); + goto out; + } + } + } + + ret = i; + +out: + i2c_dbg("send stop condition\n"); + + return ret; +} + +const struct rt_i2c_bus_device_ops es32f0_i2c_ops = +{ + es32f0_master_xfer, + RT_NULL, + RT_NULL, +}; + +static void _i2c_init(void) +{ + md_i2c_inittypedef I2C_Init = + { + .Timing = CLK100kHz48M, + .Address1 = 0x55 << 1, + .AddrSize = MD_I2C_ADDRESSINGMODE_7BIT, + .DualAddressMode = MD_I2C_DUALADDRESS_DISABLE, + .Address2 = 0xAA, + .Address2Masks = MD_I2C_ADDR2_NOMASK + }; + +#ifdef BSP_USING_I2C1 + /* Open I2C clock */ + SET_BIT(RCU->APB1EN, RCU_APB1EN_I2C1EN_MSK); + + /* GPIO configuration */ + md_gpio_set_pull (GPIOC, MD_GPIO_PIN_12, MD_GPIO_PULL_UP); + md_gpio_set_pull (GPIOD, MD_GPIO_PIN_2, MD_GPIO_PULL_UP); + md_gpio_set_output_type (GPIOC, MD_GPIO_PIN_12, MD_GPIO_OUTPUT_OPENDRAIN); + md_gpio_set_output_type (GPIOD, MD_GPIO_PIN_2, MD_GPIO_OUTPUT_OPENDRAIN); + md_gpio_set_mode (GPIOC, MD_GPIO_PIN_12, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOD, MD_GPIO_PIN_2, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function8_15(GPIOC, MD_GPIO_PIN_12, MD_GPIO_AF1); + md_gpio_set_function0_7 (GPIOD, MD_GPIO_PIN_2, MD_GPIO_AF1); + + // + // Config I2C + // + md_i2c_init(I2C1, &I2C_Init); +#endif + +#ifdef BSP_USING_I2C2 + /* Open I2C clock */ + SET_BIT(RCU->APB1EN, RCU_APB1EN_I2C2EN_MSK); + + /* GPIO configuration */ + md_gpio_set_pull (GPIOB, MD_GPIO_PIN_10, MD_GPIO_PULL_UP); + md_gpio_set_pull (GPIOB, MD_GPIO_PIN_11, MD_GPIO_PULL_UP); + md_gpio_set_output_type (GPIOB, MD_GPIO_PIN_10, MD_GPIO_OUTPUT_OPENDRAIN); + md_gpio_set_output_type (GPIOB, MD_GPIO_PIN_11, MD_GPIO_OUTPUT_OPENDRAIN); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_10, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_11, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_10, MD_GPIO_AF1); + md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_11, MD_GPIO_AF1); + + // + // Config I2C + // + md_i2c_init(I2C2, &I2C_Init); +#endif +} + +#ifdef BSP_USING_I2C2 +static struct rt_i2c_bus_device i2c_device2; +#endif + +#ifdef BSP_USING_I2C1 +static struct rt_i2c_bus_device i2c_device1; +#endif +int rt_hw_i2c_init(void) +{ + _i2c_init(); + +#ifdef BSP_USING_I2C2 + /* define i2c Instance */ + rt_memset((void *)&i2c_device2, 0, sizeof(struct rt_i2c_bus_device)); + i2c_device2.ops = &es32f0_i2c_ops; + i2c_device2.priv = I2C2; + rt_i2c_bus_device_register(&i2c_device2, "i2c2"); +#endif + +#ifdef BSP_USING_I2C1 + /* define i2c Instance */ + rt_memset((void *)&i2c_device1, 0, sizeof(struct rt_i2c_bus_device)); + i2c_device1.ops = &es32f0_i2c_ops; + i2c_device1.priv = I2C1; + rt_i2c_bus_device_register(&i2c_device1, "i2c1"); +#endif + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_i2c.h b/bsp/essemi/es32f0271/drivers/drv_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..7af06805f70c18188f37725c999eadf1715585cb --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_i2c.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#ifndef DRV_I2C_H__ +#define DRV_I2C_H__ + +int rt_hw_i2c_init(void); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_pwm.c b/bsp/essemi/es32f0271/drivers/drv_pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..768fcd04cd6b943c5e285e0a87368a202dbd18ed --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_pwm.c @@ -0,0 +1,208 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#include +#include +#include +#include +#include "md_gpio.h" + +/* PWM device control struct */ +struct pwm_dev_ctrl { + AD16C4T_TypeDef *timx; + rt_uint8_t chnm; /* Cannel number */ + struct rt_pwm_configuration *cfg; +}; + +#ifdef BSP_USING_PWM_GP16C2T1 + +/* Remember channel configuration */ +static struct rt_pwm_configuration pwm_ch_cfg_gp16c2t1[2] = { + [0] = { + .channel = 1, + .period = 0, + .pulse = 0 + }, + [1] = { + .channel = 2, + .period = 0, + .pulse = 0 + } +}; + +/* Define static device */ +static struct rt_device_pwm pwm_dev_gp16c2t1; +static struct pwm_dev_ctrl pwm_dev_gp16c2t1_ctrl; +#endif +#ifdef BSP_USING_PWM_GP16C2T4 + +/* Remember channel configuration */ +static struct rt_pwm_configuration pwm_ch_cfg_gp16c2t4[2] = { + [0] = { + .channel = 1, + .period = 0, + .pulse = 0 + }, + [1] = { + .channel = 2, + .period = 0, + .pulse = 0 + } +}; + +/* Define static device */ +static struct rt_device_pwm pwm_dev_gp16c2t4; +static struct pwm_dev_ctrl pwm_dev_gp16c2t4_ctrl; +#endif + +static void pwm_auto_config_freq(AD16C4T_TypeDef *timerx, uint32_t ns) +{ + uint32_t temp_ar; + uint32_t temp_pres = timerx->PRES & 0xFFFF; + uint32_t err_cnt = 0; + + /* Automatic setting frequency division ratio */ + while (err_cnt++ < 65536) + { + temp_ar = (uint64_t)SystemCoreClock * ns / 1000000000 / (temp_pres + 1); + if (temp_ar <= 0xFFFF) + break; + temp_pres++; + } + + /* Write back to PRES */ + timerx->PRES = (uint16_t)(temp_pres & 0xFFFF); + timerx->AR = temp_ar; +} + +static void pwm_set_duty(AD16C4T_TypeDef *timerx, uint8_t ch, uint32_t ns) +{ + uint32_t temp_pres = timerx->PRES & 0xFFFF; + uint64_t tmp = (uint64_t)SystemCoreClock * ns / 1000000000 / (temp_pres + 1); + + if (ch == 1) + WRITE_REG(timerx->CCVAL1, (uint32_t)tmp); + else if (ch == 2) + WRITE_REG(timerx->CCVAL2, (uint32_t)tmp); +} + +static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + rt_err_t ret = RT_EOK; + struct pwm_dev_ctrl *dev_ctrl + = (struct pwm_dev_ctrl *)device->parent.user_data; + struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg; + AD16C4T_TypeDef *timerx = (AD16C4T_TypeDef *)dev_ctrl->timx; + + switch (cmd) + { + case PWM_CMD_ENABLE: + { + if (cfg->channel == 1) + SET_BIT(timerx->CCEP, AD16C4T_CCEP_CC1EN_MSK); + else if (cfg->channel == 2) + SET_BIT(timerx->CCEP, AD16C4T_CCEP_CC2EN_MSK); + break; + } + case PWM_CMD_DISABLE: + { + if (cfg->channel == 1) + CLEAR_BIT(timerx->CCEP, AD16C4T_CCEP_CC1EN_MSK); + else if (cfg->channel == 2) + CLEAR_BIT(timerx->CCEP, AD16C4T_CCEP_CC2EN_MSK); + break; + } + case PWM_CMD_SET: + { + /* count registers max 0xFFFF, auto adjust prescaler */ + pwm_auto_config_freq(timerx, cfg->period); + pwm_set_duty(timerx, cfg->channel, cfg->pulse); + /* Remember configuration */ + dev_ctrl->cfg[cfg->channel-1].period = cfg->period; + dev_ctrl->cfg[cfg->channel-1].pulse = cfg->pulse; + break; + } + case PWM_CMD_GET: + { + cfg->period = dev_ctrl->cfg[cfg->channel-1].period; + cfg->pulse = dev_ctrl->cfg[cfg->channel-1].pulse; + break; + } + + default: + break; + } + return ret; +} + +const static struct rt_pwm_ops es32f0_pwm_ops = +{ + es32f0_pwm_control +}; + +int rt_hw_pwm_init(void) +{ + rt_err_t ret = RT_EOK; + +#ifdef BSP_USING_PWM_GP16C2T1 /* 2 channels */ + /* Open clock */ + SET_BIT(RCU->APB2EN, RCU_APB2EN_GP16C2T1EN_MSK); + + /* GPIO configuration */ + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_1, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_2, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_1, MD_GPIO_AF5); + md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_2, MD_GPIO_AF5); + + /* Timer configuration */ + MODIFY_REG(GP16C2T1->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK, + (6 << AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS)); + MODIFY_REG(GP16C2T1->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK, + (6 << AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS)); + SET_BIT(GP16C2T1->BDCFG, AD16C4T_BDCFG_GOEN_MSK); + SET_BIT(GP16C2T1->CON1, AD16C4T_CON1_CNTEN_MSK); + + pwm_dev_gp16c2t1_ctrl.chnm = 2; + pwm_dev_gp16c2t1_ctrl.timx = GP16C2T1; + pwm_dev_gp16c2t1_ctrl.cfg = pwm_ch_cfg_gp16c2t1; + /* Register PWM device */ + ret = rt_device_pwm_register(&pwm_dev_gp16c2t1, + "pwm1", &es32f0_pwm_ops, &pwm_dev_gp16c2t1_ctrl); +#endif + +#ifdef BSP_USING_PWM_GP16C2T4 /* 2 channels */ + /* Open clock */ + SET_BIT(RCU->APB2EN, RCU_APB2EN_GP16C2T4EN_MSK); + + /* GPIO configuration */ + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_12, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_14, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_12, MD_GPIO_AF5); + md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_14, MD_GPIO_AF5); + + /* Timer configuration */ + MODIFY_REG(GP16C2T4->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK, + (6 << AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS)); + MODIFY_REG(GP16C2T4->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK, + (6 << AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS)); + SET_BIT(GP16C2T4->BDCFG, AD16C4T_BDCFG_GOEN_MSK); + SET_BIT(GP16C2T4->CON1, AD16C4T_CON1_CNTEN_MSK); + + pwm_dev_gp16c2t4_ctrl.chnm = 2; + pwm_dev_gp16c2t4_ctrl.timx = GP16C2T4; + pwm_dev_gp16c2t4_ctrl.cfg = pwm_ch_cfg_gp16c2t4; + /* Register PWM device */ + ret = rt_device_pwm_register(&pwm_dev_gp16c2t4, + "pwm2", &es32f0_pwm_ops, &pwm_dev_gp16c2t4_ctrl); +#endif + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_pwm_init); diff --git a/bsp/essemi/es32f0271/drivers/drv_pwm.h b/bsp/essemi/es32f0271/drivers/drv_pwm.h new file mode 100644 index 0000000000000000000000000000000000000000..12c0364563a16688e71def91ca1c7b89cc8d903d --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_pwm.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#ifndef DRV_PWM_H__ +#define DRV_PWM_H__ + +int rt_hw_pwm_init(void); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_rtc.c b/bsp/essemi/es32f0271/drivers/drv_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..23bab4dc16bb58e5e64720118c9adb4c99c41769 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_rtc.c @@ -0,0 +1,252 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#include +#include +#include +#include +#include "board.h" +#include "drv_rtc.h" + +#ifdef RT_USING_RTC + +/** + * @brief Time structure + */ +typedef struct +{ + uint8_t hour; /**< Hours */ + uint8_t minute; /**< Minutes */ + uint8_t second; /**< Seconds */ + uint16_t sub_sec; /**< Sub-seconds */ +} rtc_time_t; + +/** + * @brief Date structure + */ +typedef struct +{ + uint8_t week; /**< Weeks */ + uint8_t day; /**< days */ + uint8_t month; /**< months */ + uint8_t year; /**< years */ +} rtc_date_t; + +static rt_uint32_t bcd_to_dec(rt_uint32_t bcd) +{ + return ((bcd & 0xF) + ((bcd >> 4) & 0xF) * 10); +} + +static void rtc_get_time(rtc_time_t *time) +{ + rt_uint32_t tmp = RTC->TIME; + + time->second = bcd_to_dec(tmp & 0x7F); + time->minute = bcd_to_dec((tmp >> 8) & 0x7F); + time->hour = bcd_to_dec((tmp >> 16) & 0x7F); + + return; +} + +static void rtc_get_date(rtc_date_t *date) +{ + uint32_t tmp = RTC->CAL; + + date->day = bcd_to_dec(tmp & 0x3F); + date->month = bcd_to_dec((tmp >> 8) & 0x1F); + date->year = bcd_to_dec((tmp >> 16) & 0xFF); + date->week = bcd_to_dec((RTC->TIME >> 24) & 0x7); + + return; +} + +static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t result = RT_EOK; + + struct tm time_temp; + struct tm *pNow; + rt_uint16_t timout = 0xFFF; + rtc_time_t *time = rt_malloc(sizeof(rtc_time_t)); + rtc_date_t *date = rt_malloc(sizeof(rtc_date_t)); + + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + { + /* Wait RTC data ready then read */ + while ((--timout)&&((RTC->STAT & RTC_STAT_SYNDONE_MSK) != RTC_STAT_SYNDONE_MSK)); + if (timout == 0) + result = RT_ERROR; + /* Read */ + rtc_get_time(time); + rtc_get_date(date); + + time_temp.tm_sec = time->second; + time_temp.tm_min = time->minute; + time_temp.tm_hour = time->hour; + time_temp.tm_wday = date->week - 1; + time_temp.tm_mday = date->day; + time_temp.tm_mon = date->month - 1; + time_temp.tm_year = date->year - 1900 + 2000; + *((time_t *)args) = mktime(&time_temp); + break; + } + case RT_DEVICE_CTRL_RTC_SET_TIME: + { + rt_enter_critical(); + /* converts calendar time time into local time. */ + pNow = localtime((const time_t *)args); + /* copy the statically located variable */ + memcpy(&time_temp, pNow, sizeof(struct tm)); + /* unlock scheduler. */ + rt_exit_critical(); + + time->hour = time_temp.tm_hour; + time->minute = time_temp.tm_min; + time->second = time_temp.tm_sec; + date->year = time_temp.tm_year + 1900 - 2000; + date->month = time_temp.tm_mon + 1; + date->day = time_temp.tm_mday; + /* Stop RTC */ + CLEAR_BIT(RTC->CON, RTC_CON_RTCEN_MSK); + WRITE_REG(RTC->TIME, ((time->hour/10)<hour%10)<minute/10)<minute%10)<second/10)<second%10)<CAL, ((date->year/10)<year%10)<month/10)<month%10)<day/10)<day%10)<CON, RTC_CON_RTCEN_MSK); + break; + } + case RT_DEVICE_CTRL_RTC_GET_ALARM: + break; + + case RT_DEVICE_CTRL_RTC_SET_ALARM: + break; + + default: + break; + } + + rt_free(time); + rt_free(date); + + return result; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops es32f0_rtc_ops = +{ + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + es32f0_rtc_control +}; +#endif + +static struct rt_device rtc_dev; +#define RTC_SOURCE_LOSC 0x1 +#define RTC_SOURCE_LRC 0x2 +int rt_hw_rtc_init(void) +{ + rt_err_t ret = RT_EOK; + rt_uint16_t timout = 0xFFFF; + rt_uint32_t rtc_clk = 32768-1; + rt_uint8_t rtc_src = RTC_SOURCE_LOSC; + + /* + * Config RTC clock + * We config the external 32.768K crystal as RTC clock source for the first + * choice. If external 32.768K crystal is not ready, we will choose LRC. + */ + /* Enable LOSC then wait it ready */ + if ((RCU->CON & RCU_CON_LOSCON_MSK) != RCU_CON_LOSCON_MSK) + SET_BIT(RCU->CON, RCU_CON_LOSCON_MSK); + + /* Wait external 32.768K crystal ready */ + while (((RCU->CON & RCU_CON_LOSCRDY_MSK) != RCU_CON_LOSCRDY_MSK)&&(--timout)); + if (timout == 0) + { + /* We use LRC if external 32.768K crystal is not ready */ + if ((RCU->CON & RCU_CON_LRCON_MSK) != RCU_CON_LRCON_MSK) + SET_BIT(RCU->CON, RCU_CON_LRCON_MSK); + /* Wait LRC ready */ + timout = 0xFF; + while (((RCU->CON & RCU_CON_LRCRDY_MSK) != RCU_CON_LRCRDY_MSK)&&(--timout)); + rtc_clk = 32000-1; + rtc_src = RTC_SOURCE_LRC; + } + + /* Open RTC clock */ + SET_BIT(RCU->AHBEN, RCU_AHBEN_RTCEN_MSK); + + /* Reset RTC */ + SET_BIT(RCU->AHBRST, RCU_AHBRST_RTCEN_MSK); + CLEAR_BIT(RCU->AHBRST, RCU_AHBRST_RTCEN_MSK); + CLEAR_BIT(RTC->CON, RTC_CON_RTCEN_MSK); + + /* Config RTC clock source */ + MODIFY_REG(RTC->CON, RTC_CON_CKSEL_MSK, rtc_src<CON, RTC_CON_PSCALE_MSK|RTC_CON_SCALE_MSK, + ((rtc_clk&0x7F)<>7)&0xFF)<TIME, (0x3<CAL, (0x1<CON, RTC_CON_RTCEN_MSK); + + rtc_dev.type = RT_Device_Class_RTC; + rtc_dev.rx_indicate = RT_NULL; + rtc_dev.tx_complete = RT_NULL; + +#ifdef RT_USING_DEVICE_OPS + rtc_dev.ops = &es32f0_rtc_ops; +#else + rtc_dev.init = RT_NULL; + rtc_dev.open = RT_NULL; + rtc_dev.close = RT_NULL; + rtc_dev.read = RT_NULL; + rtc_dev.write = RT_NULL; + rtc_dev.control = es32f0_rtc_control; +#endif + + rtc_dev.user_data = RTC; + + ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR); + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_rtc_init); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_rtc.h b/bsp/essemi/es32f0271/drivers/drv_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..0fd0661026b7974e3d680cf30965912a7803421b --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_rtc.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#ifndef DRV_RTC_H__ +#define DRV_RTC_H__ + +int rt_hw_rtc_init(void); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_spi.c b/bsp/essemi/es32f0271/drivers/drv_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..9a7fc3ab7064fc4462b3a0ac01cb1e33448bb600 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_spi.c @@ -0,0 +1,439 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#include +#include +#include +#include +#include "board.h" +#include "drv_spi.h" +#include "md_spi.h" +#include "md_gpio.h" + +#ifdef RT_USING_SPI + +#define SPITIMEOUT 0x0FFF + +static rt_err_t __spi_send(struct rt_spi_device *device, rt_uint8_t *buf, + rt_int32_t len, rt_uint32_t tmout); +static rt_err_t __spi_recv(struct rt_spi_device *device, rt_uint8_t *buf, + rt_int32_t len, rt_uint32_t tmout); +static rt_err_t __spi_send_recv(struct rt_spi_device *device, rt_uint8_t *tbuf, + rt_uint8_t *rbuf, rt_int32_t len, rt_uint32_t tmout); + +/** + * @brief: SPI single line send. + * @param: device, pointer to the SPI device + * @param: buf, send data buffer + * @param: len, the length of buf + * @param: tmout, timeout + * @retval: rt_err_t + */ +static rt_err_t __spi_send(struct rt_spi_device *device, rt_uint8_t *buf, + rt_int32_t len, rt_uint32_t tmout) +{ + SPI_TypeDef *hspi; + rt_uint32_t rt_timout; + rt_uint8_t temp_data; + + /* Get the SPI port */ + hspi = (SPI_TypeDef *)device->bus->parent.user_data; + + /* Open SPI if it is disabled */ + if (READ_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK) != SPI_CON1_SPIEN_MSK) + SET_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK); + + while (len > 0) + { + /* Confirm that no data is being transmitted */ + rt_timout = tmout; + while (((hspi->STAT & SPI_STAT_TXE_MSK) == 0) && (--rt_timout)); + if (rt_timout == 0) + return RT_ETIMEOUT; + + /* Send data */ + if (device->config.data_width == 8) + { + hspi->DATA = *(rt_uint8_t *)buf; + buf++; + len--; + } + else if (device->config.data_width == 16) + { + hspi->DATA = *(rt_uint16_t *)buf; + buf += 2; + len -= 2; + } + else + return RT_EINVAL; + } + + /* At here, we have transmitted all the data. + * The next step is to clear the IT flag. + */ + for (rt_uint8_t i = 0; i < md_spi_get_stat_rxflv(hspi); i++) + temp_data = hspi->DATA; + UNUSED(temp_data); + hspi->ICR = hspi->RIF; + + return RT_EOK; +} + +/** + * @brief: SPI single line receive. + * @param: device, pointer to the SPI device + * @param: buf, receive data buffer + * @param: len, the length of buf + * @param: tmout, timeout + * @retval: rt_err_t + */ +static rt_err_t __spi_recv(struct rt_spi_device *device, rt_uint8_t *buf, + rt_int32_t len, rt_uint32_t tmout) +{ + SPI_TypeDef *hspi; + rt_uint32_t rt_timout; + + /* Get the SPI port */ + hspi = (SPI_TypeDef *)device->bus->parent.user_data; + + /* Open SPI if it is disabled */ + if (READ_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK) != SPI_CON1_SPIEN_MSK) + SET_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK); + + /* Handle data in __spi_send_recv() function */ + if (((device->config.mode & RT_SPI_SLAVE) == 0) + && ((device->config.mode & RT_SPI_3WIRE) == 0)) + __spi_send_recv(device, buf, buf, len, tmout); + + while (len > 0) + { + /* Waiting for data */ + rt_timout = tmout; + while (((hspi->STAT & SPI_STAT_RXTH_MSK) == 0) && (--rt_timout)); + if (rt_timout == 0) + return RT_ETIMEOUT; + + /* Send data */ + if (device->config.data_width == 8) + { + *(rt_uint8_t *)buf = hspi->DATA; + buf++; + len--; + } + else if (device->config.data_width == 16) + { + *(rt_uint16_t *)buf = hspi->DATA; + buf += 2; + len -= 2; + } + else + return RT_EINVAL; + } + + /* At here, we have transmitted all the data. + * The next step is to clear the IT flag. + */ + hspi->ICR = hspi->RIF; + + return RT_EOK; +} + +/** + * @brief: SPI two line transmission. + * @param: device, pointer to the SPI device + * @param: tbuf, send data buffer + * @param: rbuf, receive data buffer + * @param: len, the length of buf + * @param: tmout, timeout + * @retval: rt_err_t + */ +static rt_err_t __spi_send_recv(struct rt_spi_device *device, rt_uint8_t *tbuf, + rt_uint8_t *rbuf, rt_int32_t len, rt_uint32_t tmout) +{ + SPI_TypeDef *hspi; + rt_uint32_t rt_timout; + + /* Get the SPI port */ + hspi = (SPI_TypeDef *)device->bus->parent.user_data; + + /* Open SPI if it is disabled */ + if (READ_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK) != SPI_CON1_SPIEN_MSK) + SET_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK); + + /* return error if SPI is in 1-line mode */ + if ((device->config.mode & RT_SPI_3WIRE) == RT_SPI_3WIRE) + return RT_ERROR; + + while (len > 0) + { + /* Confirm that no data is being transmitted */ + rt_timout = tmout; + while (((hspi->STAT & SPI_STAT_TXE_MSK) == 0) && (--rt_timout)); + if (rt_timout == 0) + return RT_ETIMEOUT; + + /* Send data */ + if (device->config.data_width == 8) + { + hspi->DATA = *(rt_uint8_t *)tbuf; + tbuf++; + len--; + } + else if (device->config.data_width == 16) + { + hspi->DATA = *(rt_uint16_t *)tbuf; + tbuf += 2; + len -= 2; + } + else + return RT_EINVAL; + + /* Waiting for data */ + rt_timout = tmout; + while (((hspi->STAT & SPI_STAT_RXTH_MSK) == 0) && (--rt_timout)); + if (rt_timout == 0) + return RT_ETIMEOUT; + + /* Send data */ + if (device->config.data_width == 8) + { + *(rt_uint8_t *)rbuf = hspi->DATA; + rbuf++; + } + else if (device->config.data_width == 16) + { + *(rt_uint16_t *)rbuf = hspi->DATA; + rbuf += 2; + } + } + + /* At here, we have transmitted all the data. + * The next step is to clear the IT flag. + */ + hspi->ICR = hspi->RIF; + + return RT_EOK; +} + +rt_err_t spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *cfg) +{ + SPI_TypeDef *hspi; + hspi = (SPI_TypeDef *)device->bus->parent.user_data; + + /* Close SPI temporarily */ + md_spi_disable_con1_spien(hspi); + + /* config spi mode */ + if (cfg->mode & RT_SPI_SLAVE) + md_spi_set_con1_mstren(hspi, MD_SPI_MODE_SLAVE); + else + md_spi_set_con1_mstren(hspi, MD_SPI_MODE_MASTER); + + /* Config data mode */ + if (cfg->mode & RT_SPI_3WIRE) + md_spi_set_con1_bidimode(hspi, MD_SPI_HALF_DUPLEX); + else + md_spi_set_con1_bidimode(hspi, MD_SPI_FULL_DUPLEX); + + /* Config data width */ + if (cfg->data_width == 8) + md_spi_set_con1_flen(hspi, MD_SPI_FRAME_FORMAT_8BIT); + else if (cfg->data_width == 16) + md_spi_set_con1_flen(hspi, SPI_CON1_FLEN_MSK); + + /* Config phase */ + if (cfg->mode & RT_SPI_CPHA) + md_spi_set_con1_cpha(hspi, MD_SPI_PHASE_2EDGE); + else + md_spi_set_con1_cpha(hspi, MD_SPI_PHASE_1EDGE); + + /* Config polarity */ + if (cfg->mode & RT_SPI_CPOL) + md_spi_set_con1_cpol(hspi, MD_SPI_POLARITY_HIGH); + else + md_spi_set_con1_cpol(hspi, MD_SPI_POLARITY_LOW); + + /* Config if NSS pin is managed by software */ + md_spi_disable_con1_ssen(hspi); + + /* config spi clock */ + if (cfg->max_hz >= SystemCoreClock / 2) + { + /* pclk1 max speed 48MHz, spi master max speed 10MHz */ + if (SystemCoreClock / 2 <= 10000000) + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV2); + else if (SystemCoreClock / 4 <= 10000000) + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV4); + else + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV8); + } + else if (cfg->max_hz >= SystemCoreClock / 4) + { + /* pclk1 max speed 48MHz, spi master max speed 10MHz */ + if (SystemCoreClock / 4 <= 10000000) + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV4); + else + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV8); + } + else if (cfg->max_hz >= SystemCoreClock / 8) + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV8); + else if (cfg->max_hz >= SystemCoreClock / 16) + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV16); + else if (cfg->max_hz >= SystemCoreClock / 32) + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV32); + else if (cfg->max_hz >= SystemCoreClock / 64) + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV64); + else if (cfg->max_hz >= SystemCoreClock / 128) + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV128); + else + md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV256); + + /* Enable SPI */ + md_spi_enable_con1_spien(hspi); + + return RT_EOK; +} + +static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + rt_err_t res; + rt_uint32_t *cs; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL); + + cs = (rt_uint32_t *)device->parent.user_data; + + /* only send data */ + if (message->recv_buf == RT_NULL) + { + if (message->cs_take) + { + rt_pin_write(*cs, 0); + } + res = __spi_send(device, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); + if (message->cs_release) + { + rt_pin_write(*cs, 1); + } + if (res != RT_EOK) + return RT_ERROR; + } + + /* only receive data */ + if (message->send_buf == RT_NULL) + { + if (message->cs_take) + { + rt_pin_write(*cs, 0); + } + res = __spi_recv(device, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); + if (message->cs_release) + { + rt_pin_write(*cs, 1); + } + if (res != RT_EOK) + return RT_ERROR; + } + + /* send & receive */ + else + { + if (message->cs_take) + { + rt_pin_write(*cs, 0); + } + res = __spi_send_recv(device, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, + (rt_int32_t)message->length, SPITIMEOUT); + if (message->cs_release) + { + rt_pin_write(*cs, 1); + } + if (res != RT_EOK) + return RT_ERROR; + } + + return message->length; +} + +const struct rt_spi_ops es32f0_spi_ops = +{ + spi_configure, + spixfer, +}; + +static struct rt_spi_bus _spi_bus1, _spi_bus2; +int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name) +{ + struct rt_spi_bus *spi_bus; + + if (SPIx == SPI2) + { + /* Open GPIO and SPI clock */ + SET_BIT(RCU->APB1EN, RCU_APB1EN_SPI2EN_MSK); + SET_BIT(RCU->AHBEN, RCU_AHBEN_GPBEN_MSK); + + /* Config SPI2 GPIO */ + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_13, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_14, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_15, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function8_15 (GPIOB, MD_GPIO_PIN_13, MD_GPIO_AF0); + md_gpio_set_function8_15 (GPIOB, MD_GPIO_PIN_14, MD_GPIO_AF0); + md_gpio_set_function8_15 (GPIOB, MD_GPIO_PIN_15, MD_GPIO_AF0); + + /* Remember SPI bus2 */ + spi_bus = &_spi_bus2; + } + else if (SPIx == SPI1) + { + /* Open GPIO and SPI clock */ + SET_BIT(RCU->APB2EN, RCU_APB2EN_SPI1EN_MSK); + SET_BIT(RCU->AHBEN, RCU_AHBEN_GPBEN_MSK); + + /* Config SPI1 GPIO */ + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_3, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_4, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_5, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_3, MD_GPIO_AF0); + md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_4, MD_GPIO_AF0); + md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_5, MD_GPIO_AF0); + + /* Remember SPI bus1 */ + spi_bus = &_spi_bus1; + } + else + { + return -1; + } + spi_bus->parent.user_data = SPIx; + + return rt_spi_bus_register(spi_bus, name, &es32f0_spi_ops); +} + +int rt_hw_spi_init(void) +{ + int result = 0; + +#ifdef BSP_USING_SPI2 + result = es32f0_spi_register_bus(SPI2, "spi2"); +#endif + +#ifdef BSP_USING_SPI1 + result = es32f0_spi_register_bus(SPI1, "spi1"); +#endif + + return result; +} +INIT_BOARD_EXPORT(rt_hw_spi_init); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_spi.h b/bsp/essemi/es32f0271/drivers/drv_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..c7c8a13b4ad287e69804fa81dff9b7565a714e78 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_spi.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#ifndef DRV_SPI_H__ +#define DRV_SPI_H__ + +#include +#include +#include + +///* cannot be used before completion init */ +//rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name); +int rt_hw_spi_init(void); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_uart.c b/bsp/essemi/es32f0271/drivers/drv_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..f860c2df91e2c0200212e13c7613fb40e8167f38 --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_uart.c @@ -0,0 +1,296 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#include +#include +#include +#include "board.h" +#include "drv_uart.h" +#include "md_gpio.h" +#include "md_uart.h" + +#ifdef RT_USING_SERIAL + +/* es32 uart driver */ +struct es32_uart +{ + UART_TypeDef *huart; + IRQn_Type irq; +}; + +static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + /* Close TX/RX temporarily */ + md_uart_disable_lcon_txen(uart->huart); + md_uart_disable_lcon_rxen(uart->huart); + +#ifdef BSP_USING_UART1 + /* Open UART1 clock */ + SET_BIT(RCU->APB2EN, RCU_APB2EN_UART1EN_MSK); + + /* Config UART1 GPIO pin */ + md_gpio_set_pull (GPIOB, MD_GPIO_PIN_7, MD_GPIO_PULL_UP); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_6, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOB, MD_GPIO_PIN_7, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_6, MD_GPIO_AF2); + md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_7, MD_GPIO_AF2); +#endif /* uart2 gpio init */ + +#ifdef BSP_USING_UART2 + /* Open UART2 clock */ + SET_BIT(RCU->APB1EN, RCU_APB1EN_UART2EN_MSK); + + /* Config UART2 GPIO pin */ + md_gpio_set_pull (GPIOA, MD_GPIO_PIN_3, MD_GPIO_PULL_UP); + md_gpio_set_mode (GPIOA, MD_GPIO_PIN_2, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOA, MD_GPIO_PIN_3, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function0_7 (GPIOA, MD_GPIO_PIN_2, MD_GPIO_AF2); + md_gpio_set_function0_7 (GPIOA, MD_GPIO_PIN_3, MD_GPIO_AF2); +#endif /* uart1 gpio init */ + +#ifdef BSP_USING_UART3 + /* Open UART3 clock */ + SET_BIT(RCU->APB1EN, RCU_APB1EN_UART3EN_MSK); + + /* Config UART3 GPIO pin */ + md_gpio_set_pull (GPIOC, MD_GPIO_PIN_7, MD_GPIO_PULL_UP); + md_gpio_set_mode (GPIOC, MD_GPIO_PIN_6, MD_GPIO_MODE_FUNCTION); + md_gpio_set_mode (GPIOC, MD_GPIO_PIN_7, MD_GPIO_MODE_FUNCTION); + md_gpio_set_function0_7 (GPIOC, MD_GPIO_PIN_6, MD_GPIO_AF2); + md_gpio_set_function0_7 (GPIOC, MD_GPIO_PIN_7, MD_GPIO_AF2); +#endif /* uart3 gpio init */ + + if (cfg->bit_order == BIT_ORDER_MSB) + { + md_uart_set_lcon_msb(uart->huart, MD_UART_LCON_MSB_FIRST); + } + else + { + md_uart_set_lcon_msb(uart->huart, MD_UART_LCON_LSB_FIRST); + } + + if (cfg->invert == NRZ_INVERTED) + { + md_uart_enable_lcon_datainv(uart->huart); + } + else + { + md_uart_disable_lcon_datainv(uart->huart); + } + + /* Config buadrate */ + md_uart_set_brr(uart->huart, SystemCoreClock/cfg->baud_rate); + /* Config data width */ + md_uart_set_lcon_dls(uart->huart, 8-cfg->data_bits); + /* Config stop bits */ + md_uart_set_lcon_stop(uart->huart, cfg->stop_bits); + /* Config parity */ + if (cfg->parity > PARITY_NONE) + { + md_uart_set_lcon_ps(uart->huart, cfg->parity-1); + md_uart_enable_lcon_pe(uart->huart); + } + else + md_uart_disable_lcon_pe(uart->huart); + + /* enable rx int */ + md_uart_set_fcon_rxth(uart->huart, MD_UART_FCON_RXTH_1); + md_uart_enable_ier_rfth(uart->huart); + md_uart_enable_lcon_txen(uart->huart); + md_uart_enable_lcon_rxen(uart->huart); + + return RT_EOK; +} + +static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = (struct es32_uart *)serial->parent.user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irq); + /* disable interrupt */ + md_uart_disable_idr_rfth(uart->huart); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irq); + /* enable interrupt */ + md_uart_enable_ier_rfth(uart->huart); + break; + } + + return RT_EOK; +} + +static int es32f0x_putc(struct rt_serial_device *serial, char c) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + while (uart->huart->STAT & UART_STAT_TSBUSY_MSK); + WRITE_REG(uart->huart->TXBUF, c); + + return 1; +} + +static int es32f0x_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct es32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + if (uart->huart->STAT & UART_STAT_RFTH_MSK) + { + ch = (uint8_t)(uart->huart->RXBUF & 0xFF); + } + + return ch; +} + +static const struct rt_uart_ops es32f0x_uart_ops = +{ + es32f0x_configure, + es32f0x_control, + es32f0x_putc, + es32f0x_getc, +}; + +#ifdef BSP_USING_UART1 +/* UART1 device driver structure */ +struct es32_uart uart1 = +{ + UART1, + UART1_IRQn +}; + +struct rt_serial_device serial1; + +void UART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (md_uart_is_active_flag_rif_rfth(UART1) == 1) + { + rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); + md_uart_clear_flag_rfth(UART1); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 +/* UART2 device driver structure */ +struct es32_uart uart2 = +{ + UART2, + UART2_IRQn +}; + +struct rt_serial_device serial2; + +void UART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (md_uart_is_active_flag_rif_rfth(UART2) == 1) + { + rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); + md_uart_clear_flag_rfth(UART2); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#ifdef BSP_USING_UART3 +/* UART3 device driver structure */ +struct es32_uart uart3 = +{ + UART3, + UART3_IRQn +}; + +struct rt_serial_device serial3; + +void UART3_AES_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (md_uart_is_active_flag_rif_rfth(UART3) == 1) + { + rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); + md_uart_clear_flag_rfth(UART3); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +int rt_hw_uart_init(void) +{ + struct es32_uart *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + +#ifdef BSP_USING_UART1 + uart = &uart1; + serial1.ops = &es32f0x_uart_ops; + serial1.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 + uart = &uart2; + serial2.ops = &es32f0x_uart_ops; + serial2.config = config; + + /* register UART2 device */ + rt_hw_serial_register(&serial2, "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART2 */ + +#ifdef BSP_USING_UART3 + uart = &uart3; + serial3.ops = &es32f0x_uart_ops; + serial3.config = config; + + /* register UART3 device */ + rt_hw_serial_register(&serial3, "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART3 */ + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/drv_uart.h b/bsp/essemi/es32f0271/drivers/drv_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..7d3755d0a6db211c8f28cee324a5dbfb168ec97f --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/drv_uart.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-23 yuzrain the first version + */ + +#ifndef DRV_UART_H__ +#define DRV_UART_H__ + +int rt_hw_uart_init(void); + +#endif diff --git a/bsp/essemi/es32f0271/drivers/linker_scripts/link.sct b/bsp/essemi/es32f0271/drivers/linker_scripts/link.sct new file mode 100644 index 0000000000000000000000000000000000000000..4ee8d1e3fc8b0d721151fcb3200a6732c50f765d --- /dev/null +++ b/bsp/essemi/es32f0271/drivers/linker_scripts/link.sct @@ -0,0 +1,14 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x10000 { ; load region size_region + ER_IROM1 0x00000000 0x10000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x2000{ ; RW data + .ANY (+RW +ZI) + } +} diff --git a/bsp/es32f0654/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf b/bsp/essemi/es32f0271/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf rename to bsp/essemi/es32f0271/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf diff --git a/bsp/es32f0654/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf b/bsp/essemi/es32f0271/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf rename to bsp/essemi/es32f0271/libraries/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_ad16c4t.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_ad16c4t.h new file mode 100644 index 0000000000000000000000000000000000000000..f70a10e35c1b006af73d87098ae17e362f310b6c --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_ad16c4t.h @@ -0,0 +1,683 @@ +/** + ************************************************************************************** + * @file reg_AD16C4T.h + * @brief AD16C4T Head File + * + * @version V0.01 + * @date 3/12/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __REG_AD16C4T_H__ +#define __REG_AD16C4T_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for AD16C4T_CON1 register ************************/ + +#define AD16C4T_CON1_DBGSEL_POS 15U +#define AD16C4T_CON1_DBGSEL_MSK BIT(AD16C4T_CON1_DBGSEL_POS) + +#define AD16C4T_CON1_CMPSEL_POSS 11U +#define AD16C4T_CON1_CMPSEL_POSE 13U +#define AD16C4T_CON1_CMPSEL_MSK BITS(AD16C4T_CON1_CMPSEL_POSS,AD16C4T_CON1_CMPSEL_POSE) + +#define AD16C4T_CON1_CMPSELP_POS 10U +#define AD16C4T_CON1_CMPSELP_MSK BIT(AD16C4T_CON1_CMPSELP_POS) + +#define AD16C4T_CON1_DFCKSEL_POSS 8U +#define AD16C4T_CON1_DFCKSEL_POSE 9U +#define AD16C4T_CON1_DFCKSEL_MSK BITS(AD16C4T_CON1_DFCKSEL_POSS,AD16C4T_CON1_DFCKSEL_POSE) + +#define AD16C4T_CON1_ARPEN_POS 7U +#define AD16C4T_CON1_ARPEN_MSK BIT(AD16C4T_CON1_ARPEN_POS) + +#define AD16C4T_CON1_CMSEL_POSS 5U +#define AD16C4T_CON1_CMSEL_POSE 6U +#define AD16C4T_CON1_CMSEL_MSK BITS(AD16C4T_CON1_CMSEL_POSS,AD16C4T_CON1_CMSEL_POSE) + +#define AD16C4T_CON1_DIRSEL_POS 4U +#define AD16C4T_CON1_DIRSEL_MSK BIT(AD16C4T_CON1_DIRSEL_POS) + +#define AD16C4T_CON1_SPMEN_POS 3U +#define AD16C4T_CON1_SPMEN_MSK BIT(AD16C4T_CON1_SPMEN_POS) + +#define AD16C4T_CON1_UERSEL_POS 2U +#define AD16C4T_CON1_UERSEL_MSK BIT(AD16C4T_CON1_UERSEL_POS) + +#define AD16C4T_CON1_DISUE_POS 1U +#define AD16C4T_CON1_DISUE_MSK BIT(AD16C4T_CON1_DISUE_POS) + +#define AD16C4T_CON1_CNTEN_POS 0U +#define AD16C4T_CON1_CNTEN_MSK BIT(AD16C4T_CON1_CNTEN_POS) + +/****************** Bit definition for AD16C4T_CON2 register ************************/ + +#define AD16C4T_CON2_OISS4_POS 14U +#define AD16C4T_CON2_OISS4_MSK BIT(AD16C4T_CON2_OISS4_POS) + +#define AD16C4T_CON2_OISS3N_POS 13U +#define AD16C4T_CON2_OISS3N_MSK BIT(AD16C4T_CON2_OISS3N_POS) + +#define AD16C4T_CON2_OISS3_POS 12U +#define AD16C4T_CON2_OISS3_MSK BIT(AD16C4T_CON2_OISS3_POS) + +#define AD16C4T_CON2_OISS2N_POS 11U +#define AD16C4T_CON2_OISS2N_MSK BIT(AD16C4T_CON2_OISS2N_POS) + +#define AD16C4T_CON2_OISS2_POS 10U +#define AD16C4T_CON2_OISS2_MSK BIT(AD16C4T_CON2_OISS2_POS) + +#define AD16C4T_CON2_OISS1N_POS 9U +#define AD16C4T_CON2_OISS1N_MSK BIT(AD16C4T_CON2_OISS1N_POS) + +#define AD16C4T_CON2_OISS1_POS 8U +#define AD16C4T_CON2_OISS1_MSK BIT(AD16C4T_CON2_OISS1_POS) + +#define AD16C4T_CON2_I1SEL_POS 7U +#define AD16C4T_CON2_I1SEL_MSK BIT(AD16C4T_CON2_I1SEL_POS) + +#define AD16C4T_CON2_MMSEL_POSS 4U +#define AD16C4T_CON2_MMSEL_POSE 6U +#define AD16C4T_CON2_MMSEL_MSK BITS(AD16C4T_CON2_MMSEL_POSS,AD16C4T_CON2_MMSEL_POSE) + +#define AD16C4T_CON2_CCDMASEL_POS 3U +#define AD16C4T_CON2_CCDMASEL_MSK BIT(AD16C4T_CON2_CCDMASEL_POS) + +#define AD16C4T_CON2_CCUSEL_POS 2U +#define AD16C4T_CON2_CCUSEL_MSK BIT(AD16C4T_CON2_CCUSEL_POS) + +#define AD16C4T_CON2_CCPCEN_POS 0U +#define AD16C4T_CON2_CCPCEN_MSK BIT(AD16C4T_CON2_CCPCEN_POS) + +/****************** Bit definition for AD16C4T_SMCON register ************************/ + +#define AD16C4T_SMCON_ETPOL_POS 15U +#define AD16C4T_SMCON_ETPOL_MSK BIT(AD16C4T_SMCON_ETPOL_POS) + +#define AD16C4T_SMCON_ECM2EN_POS 14U +#define AD16C4T_SMCON_ECM2EN_MSK BIT(AD16C4T_SMCON_ECM2EN_POS) + +#define AD16C4T_SMCON_ETFLT_POSS 8U +#define AD16C4T_SMCON_ETFLT_POSE 11U +#define AD16C4T_SMCON_ETFLT_MSK BITS(AD16C4T_SMCON_ETFLT_POSS,AD16C4T_SMCON_ETFLT_POSE) + +#define AD16C4T_SMCON_MSCFG_POS 7U +#define AD16C4T_SMCON_MSCFG_MSK BIT(AD16C4T_SMCON_MSCFG_POS) + +#define AD16C4T_SMCON_TSSEL_POSS 4U +#define AD16C4T_SMCON_TSSEL_POSE 6U +#define AD16C4T_SMCON_TSSEL_MSK BITS(AD16C4T_SMCON_TSSEL_POSS,AD16C4T_SMCON_TSSEL_POSE) + +#define AD16C4T_SMCON_CHCSEL_POS 3U +#define AD16C4T_SMCON_CHCSEL_MSK BIT(AD16C4T_SMCON_CHCSEL_POS) + +#define AD16C4T_SMCON_SMODS_POSS 0U +#define AD16C4T_SMCON_SMODS_POSE 2U +#define AD16C4T_SMCON_SMODS_MSK BITS(AD16C4T_SMCON_SMODS_POSS,AD16C4T_SMCON_SMODS_POSE) + +/****************** Bit definition for AD16C4T_IER register ************************/ + +#define AD16C4T_IER_CH4OVI_POS 12U +#define AD16C4T_IER_CH4OVI_MSK BIT(AD16C4T_IER_CH4OVI_POS) + +#define AD16C4T_IER_CH3OVI_POS 11U +#define AD16C4T_IER_CH3OVI_MSK BIT(AD16C4T_IER_CH3OVI_POS) + +#define AD16C4T_IER_CH2OVI_POS 10U +#define AD16C4T_IER_CH2OVI_MSK BIT(AD16C4T_IER_CH2OVI_POS) + +#define AD16C4T_IER_CH1OVI_POS 9U +#define AD16C4T_IER_CH1OVI_MSK BIT(AD16C4T_IER_CH1OVI_POS) + +#define AD16C4T_IER_BRKI_POS 7U +#define AD16C4T_IER_BRKI_MSK BIT(AD16C4T_IER_BRKI_POS) + +#define AD16C4T_IER_TRGI_POS 6U +#define AD16C4T_IER_TRGI_MSK BIT(AD16C4T_IER_TRGI_POS) + +#define AD16C4T_IER_COMI_POS 5U +#define AD16C4T_IER_COMI_MSK BIT(AD16C4T_IER_COMI_POS) + +#define AD16C4T_IER_CH4I_POS 4U +#define AD16C4T_IER_CH4I_MSK BIT(AD16C4T_IER_CH4I_POS) + +#define AD16C4T_IER_CH3I_POS 3U +#define AD16C4T_IER_CH3I_MSK BIT(AD16C4T_IER_CH3I_POS) + +#define AD16C4T_IER_CH2I_POS 2U +#define AD16C4T_IER_CH2I_MSK BIT(AD16C4T_IER_CH2I_POS) + +#define AD16C4T_IER_CH1I_POS 1U +#define AD16C4T_IER_CH1I_MSK BIT(AD16C4T_IER_CH1I_POS) + +#define AD16C4T_IER_UI_POS 0U +#define AD16C4T_IER_UI_MSK BIT(AD16C4T_IER_UI_POS) + +/****************** Bit definition for AD16C4T_IDR register ************************/ + +#define AD16C4T_IDR_CH4OVI_POS 12U +#define AD16C4T_IDR_CH4OVI_MSK BIT(AD16C4T_IDR_CH4OVI_POS) + +#define AD16C4T_IDR_CH3OVI_POS 11U +#define AD16C4T_IDR_CH3OVI_MSK BIT(AD16C4T_IDR_CH3OVI_POS) + +#define AD16C4T_IDR_CH2OVI_POS 10U +#define AD16C4T_IDR_CH2OVI_MSK BIT(AD16C4T_IDR_CH2OVI_POS) + +#define AD16C4T_IDR_CH1OVI_POS 9U +#define AD16C4T_IDR_CH1OVI_MSK BIT(AD16C4T_IDR_CH1OVI_POS) + +#define AD16C4T_IDR_BRKI_POS 7U +#define AD16C4T_IDR_BRKI_MSK BIT(AD16C4T_IDR_BRKI_POS) + +#define AD16C4T_IDR_TRGI_POS 6U +#define AD16C4T_IDR_TRGI_MSK BIT(AD16C4T_IDR_TRGI_POS) + +#define AD16C4T_IDR_COMI_POS 5U +#define AD16C4T_IDR_COMI_MSK BIT(AD16C4T_IDR_COMI_POS) + +#define AD16C4T_IDR_CH4I_POS 4U +#define AD16C4T_IDR_CH4I_MSK BIT(AD16C4T_IDR_CH4I_POS) + +#define AD16C4T_IDR_CH3I_POS 3U +#define AD16C4T_IDR_CH3I_MSK BIT(AD16C4T_IDR_CH3I_POS) + +#define AD16C4T_IDR_CH2I_POS 2U +#define AD16C4T_IDR_CH2I_MSK BIT(AD16C4T_IDR_CH2I_POS) + +#define AD16C4T_IDR_CH1I_POS 1U +#define AD16C4T_IDR_CH1I_MSK BIT(AD16C4T_IDR_CH1I_POS) + +#define AD16C4T_IDR_UI_POS 0U +#define AD16C4T_IDR_UI_MSK BIT(AD16C4T_IDR_UI_POS) + +/****************** Bit definition for AD16C4T_IVS register ************************/ + +#define AD16C4T_IVS_CH4OVI_POS 12U +#define AD16C4T_IVS_CH4OVI_MSK BIT(AD16C4T_IVS_CH4OVI_POS) + +#define AD16C4T_IVS_CH3OVI_POS 11U +#define AD16C4T_IVS_CH3OVI_MSK BIT(AD16C4T_IVS_CH3OVI_POS) + +#define AD16C4T_IVS_CH2OVI_POS 10U +#define AD16C4T_IVS_CH2OVI_MSK BIT(AD16C4T_IVS_CH2OVI_POS) + +#define AD16C4T_IVS_CH1OVI_POS 9U +#define AD16C4T_IVS_CH1OVI_MSK BIT(AD16C4T_IVS_CH1OVI_POS) + +#define AD16C4T_IVS_BRKI_POS 7U +#define AD16C4T_IVS_BRKI_MSK BIT(AD16C4T_IVS_BRKI_POS) + +#define AD16C4T_IVS_TRGI_POS 6U +#define AD16C4T_IVS_TRGI_MSK BIT(AD16C4T_IVS_TRGI_POS) + +#define AD16C4T_IVS_COMI_POS 5U +#define AD16C4T_IVS_COMI_MSK BIT(AD16C4T_IVS_COMI_POS) + +#define AD16C4T_IVS_CH4I_POS 4U +#define AD16C4T_IVS_CH4I_MSK BIT(AD16C4T_IVS_CH4I_POS) + +#define AD16C4T_IVS_CH3I_POS 3U +#define AD16C4T_IVS_CH3I_MSK BIT(AD16C4T_IVS_CH3I_POS) + +#define AD16C4T_IVS_CH2I_POS 2U +#define AD16C4T_IVS_CH2I_MSK BIT(AD16C4T_IVS_CH2I_POS) + +#define AD16C4T_IVS_CH1I_POS 1U +#define AD16C4T_IVS_CH1I_MSK BIT(AD16C4T_IVS_CH1I_POS) + +#define AD16C4T_IVS_UI_POS 0U +#define AD16C4T_IVS_UI_MSK BIT(AD16C4T_IVS_UI_POS) + +/****************** Bit definition for AD16C4T_RIF register ************************/ + +#define AD16C4T_RIF_CH4OVI_POS 12U +#define AD16C4T_RIF_CH4OVI_MSK BIT(AD16C4T_RIF_CH4OVI_POS) + +#define AD16C4T_RIF_CH3OVI_POS 11U +#define AD16C4T_RIF_CH3OVI_MSK BIT(AD16C4T_RIF_CH3OVI_POS) + +#define AD16C4T_RIF_CH2OVI_POS 10U +#define AD16C4T_RIF_CH2OVI_MSK BIT(AD16C4T_RIF_CH2OVI_POS) + +#define AD16C4T_RIF_CH1OVI_POS 9U +#define AD16C4T_RIF_CH1OVI_MSK BIT(AD16C4T_RIF_CH1OVI_POS) + +#define AD16C4T_RIF_BRKI_POS 7U +#define AD16C4T_RIF_BRKI_MSK BIT(AD16C4T_RIF_BRKI_POS) + +#define AD16C4T_RIF_TRGI_POS 6U +#define AD16C4T_RIF_TRGI_MSK BIT(AD16C4T_RIF_TRGI_POS) + +#define AD16C4T_RIF_COMI_POS 5U +#define AD16C4T_RIF_COMI_MSK BIT(AD16C4T_RIF_COMI_POS) + +#define AD16C4T_RIF_CH4I_POS 4U +#define AD16C4T_RIF_CH4I_MSK BIT(AD16C4T_RIF_CH4I_POS) + +#define AD16C4T_RIF_CH3I_POS 3U +#define AD16C4T_RIF_CH3I_MSK BIT(AD16C4T_RIF_CH3I_POS) + +#define AD16C4T_RIF_CH2I_POS 2U +#define AD16C4T_RIF_CH2I_MSK BIT(AD16C4T_RIF_CH2I_POS) + +#define AD16C4T_RIF_CH1I_POS 1U +#define AD16C4T_RIF_CH1I_MSK BIT(AD16C4T_RIF_CH1I_POS) + +#define AD16C4T_RIF_UI_POS 0U +#define AD16C4T_RIF_UI_MSK BIT(AD16C4T_RIF_UI_POS) + +/****************** Bit definition for AD16C4T_IFM register ************************/ + +#define AD16C4T_IFM_CH4OVI_POS 12U +#define AD16C4T_IFM_CH4OVI_MSK BIT(AD16C4T_IFM_CH4OVI_POS) + +#define AD16C4T_IFM_CH3OVI_POS 11U +#define AD16C4T_IFM_CH3OVI_MSK BIT(AD16C4T_IFM_CH3OVI_POS) + +#define AD16C4T_IFM_CH2OVI_POS 10U +#define AD16C4T_IFM_CH2OVI_MSK BIT(AD16C4T_IFM_CH2OVI_POS) + +#define AD16C4T_IFM_CH1OVI_POS 9U +#define AD16C4T_IFM_CH1OVI_MSK BIT(AD16C4T_IFM_CH1OVI_POS) + +#define AD16C4T_IFM_BRKI_POS 7U +#define AD16C4T_IFM_BRKI_MSK BIT(AD16C4T_IFM_BRKI_POS) + +#define AD16C4T_IFM_TRGI_POS 6U +#define AD16C4T_IFM_TRGI_MSK BIT(AD16C4T_IFM_TRGI_POS) + +#define AD16C4T_IFM_COMI_POS 5U +#define AD16C4T_IFM_COMI_MSK BIT(AD16C4T_IFM_COMI_POS) + +#define AD16C4T_IFM_CH4I_POS 4U +#define AD16C4T_IFM_CH4I_MSK BIT(AD16C4T_IFM_CH4I_POS) + +#define AD16C4T_IFM_CH3I_POS 3U +#define AD16C4T_IFM_CH3I_MSK BIT(AD16C4T_IFM_CH3I_POS) + +#define AD16C4T_IFM_CH2I_POS 2U +#define AD16C4T_IFM_CH2I_MSK BIT(AD16C4T_IFM_CH2I_POS) + +#define AD16C4T_IFM_CH1I_POS 1U +#define AD16C4T_IFM_CH1I_MSK BIT(AD16C4T_IFM_CH1I_POS) + +#define AD16C4T_IFM_UI_POS 0U +#define AD16C4T_IFM_UI_MSK BIT(AD16C4T_IFM_UI_POS) + +/****************** Bit definition for AD16C4T_ICR register ************************/ + +#define AD16C4T_ICR_CH4OVI_POS 12U +#define AD16C4T_ICR_CH4OVI_MSK BIT(AD16C4T_ICR_CH4OVI_POS) + +#define AD16C4T_ICR_CH3OVI_POS 11U +#define AD16C4T_ICR_CH3OVI_MSK BIT(AD16C4T_ICR_CH3OVI_POS) + +#define AD16C4T_ICR_CH2OVI_POS 10U +#define AD16C4T_ICR_CH2OVI_MSK BIT(AD16C4T_ICR_CH2OVI_POS) + +#define AD16C4T_ICR_CH1OVI_POS 9U +#define AD16C4T_ICR_CH1OVI_MSK BIT(AD16C4T_ICR_CH1OVI_POS) + +#define AD16C4T_ICR_BRKI_POS 7U +#define AD16C4T_ICR_BRKI_MSK BIT(AD16C4T_ICR_BRKI_POS) + +#define AD16C4T_ICR_TRGI_POS 6U +#define AD16C4T_ICR_TRGI_MSK BIT(AD16C4T_ICR_TRGI_POS) + +#define AD16C4T_ICR_COMI_POS 5U +#define AD16C4T_ICR_COMI_MSK BIT(AD16C4T_ICR_COMI_POS) + +#define AD16C4T_ICR_CH4I_POS 4U +#define AD16C4T_ICR_CH4I_MSK BIT(AD16C4T_ICR_CH4I_POS) + +#define AD16C4T_ICR_CH3I_POS 3U +#define AD16C4T_ICR_CH3I_MSK BIT(AD16C4T_ICR_CH3I_POS) + +#define AD16C4T_ICR_CH2I_POS 2U +#define AD16C4T_ICR_CH2I_MSK BIT(AD16C4T_ICR_CH2I_POS) + +#define AD16C4T_ICR_CH1I_POS 1U +#define AD16C4T_ICR_CH1I_MSK BIT(AD16C4T_ICR_CH1I_POS) + +#define AD16C4T_ICR_UI_POS 0U +#define AD16C4T_ICR_UI_MSK BIT(AD16C4T_ICR_UI_POS) + +/****************** Bit definition for AD16C4T_SGE register ************************/ + +#define AD16C4T_SGE_SGBRK_POS 7U +#define AD16C4T_SGE_SGBRK_MSK BIT(AD16C4T_SGE_SGBRK_POS) + +#define AD16C4T_SGE_SGTRG_POS 6U +#define AD16C4T_SGE_SGTRG_MSK BIT(AD16C4T_SGE_SGTRG_POS) + +#define AD16C4T_SGE_SGCOM_POS 5U +#define AD16C4T_SGE_SGCOM_MSK BIT(AD16C4T_SGE_SGCOM_POS) + +#define AD16C4T_SGE_SGCH4_POS 4U +#define AD16C4T_SGE_SGCH4_MSK BIT(AD16C4T_SGE_SGCH4_POS) + +#define AD16C4T_SGE_SGCH3_POS 3U +#define AD16C4T_SGE_SGCH3_MSK BIT(AD16C4T_SGE_SGCH3_POS) + +#define AD16C4T_SGE_SGCH2_POS 2U +#define AD16C4T_SGE_SGCH2_MSK BIT(AD16C4T_SGE_SGCH2_POS) + +#define AD16C4T_SGE_SGCH1_POS 1U +#define AD16C4T_SGE_SGCH1_MSK BIT(AD16C4T_SGE_SGCH1_POS) + +#define AD16C4T_SGE_SGU_POS 0U +#define AD16C4T_SGE_SGU_MSK BIT(AD16C4T_SGE_SGU_POS) + +/****************** Bit definition for AD16C4T_CHMR1_OUTPUT register ************************/ + +#define AD16C4T_CHMR1_OUTPUT_CH2OCLREN_POS 15U +#define AD16C4T_CHMR1_OUTPUT_CH2OCLREN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH2OCLREN_POS) + +#define AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS 12U +#define AD16C4T_CHMR1_OUTPUT_CH2MOD_POSE 14U +#define AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK BITS(AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS,AD16C4T_CHMR1_OUTPUT_CH2MOD_POSE) + +#define AD16C4T_CHMR1_OUTPUT_CH2PEN_POS 11U +#define AD16C4T_CHMR1_OUTPUT_CH2PEN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH2PEN_POS) + +#define AD16C4T_CHMR1_OUTPUT_CH2FEN_POS 10U +#define AD16C4T_CHMR1_OUTPUT_CH2FEN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH2FEN_POS) + +#define AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSS 8U +#define AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSE 9U +#define AD16C4T_CHMR1_OUTPUT_CC2SSEL_MSK BITS(AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSS,AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSE) + +#define AD16C4T_CHMR1_OUTPUT_CH1OCLREN_POS 7U +#define AD16C4T_CHMR1_OUTPUT_CH1OCLREN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH1OCLREN_POS) + +#define AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS 4U +#define AD16C4T_CHMR1_OUTPUT_CH1MOD_POSE 6U +#define AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK BITS(AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS,AD16C4T_CHMR1_OUTPUT_CH1MOD_POSE) + +#define AD16C4T_CHMR1_OUTPUT_CH1PEN_POS 3U +#define AD16C4T_CHMR1_OUTPUT_CH1PEN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH1PEN_POS) + +#define AD16C4T_CHMR1_OUTPUT_CH1FEN_POS 2U +#define AD16C4T_CHMR1_OUTPUT_CH1FEN_MSK BIT(AD16C4T_CHMR1_OUTPUT_CH1FEN_POS) + +#define AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSS 0U +#define AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSE 1U +#define AD16C4T_CHMR1_OUTPUT_CC1SSEL_MSK BITS(AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSS,AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSE) + +/****************** Bit definition for AD16C4T_CHMR1_INPUT register ************************/ + +#define AD16C4T_CHMR1_INPUT_I2FLT_POSS 12U +#define AD16C4T_CHMR1_INPUT_I2FLT_POSE 15U +#define AD16C4T_CHMR1_INPUT_I2FLT_MSK BITS(AD16C4T_CHMR1_INPUT_I2FLT_POSS,AD16C4T_CHMR1_INPUT_I2FLT_POSE) + +#define AD16C4T_CHMR1_INPUT_I2PRES_POSS 10U +#define AD16C4T_CHMR1_INPUT_I2PRES_POSE 11U +#define AD16C4T_CHMR1_INPUT_I2PRES_MSK BITS(AD16C4T_CHMR1_INPUT_I2PRES_POSS,AD16C4T_CHMR1_INPUT_I2PRES_POSE) + +#define AD16C4T_CHMR1_INPUT_CC2SSEL_POSS 8U +#define AD16C4T_CHMR1_INPUT_CC2SSEL_POSE 9U +#define AD16C4T_CHMR1_INPUT_CC2SSEL_MSK BITS(AD16C4T_CHMR1_INPUT_CC2SSEL_POSS,AD16C4T_CHMR1_INPUT_CC2SSEL_POSE) + +#define AD16C4T_CHMR1_INPUT_I1FLT_POSS 4U +#define AD16C4T_CHMR1_INPUT_I1FLT_POSE 7U +#define AD16C4T_CHMR1_INPUT_I1FLT_MSK BITS(AD16C4T_CHMR1_INPUT_I1FLT_POSS,AD16C4T_CHMR1_INPUT_I1FLT_POSE) + +#define AD16C4T_CHMR1_INPUT_I1PRES_POSS 2U +#define AD16C4T_CHMR1_INPUT_I1PRES_POSE 3U +#define AD16C4T_CHMR1_INPUT_I1PRES_MSK BITS(AD16C4T_CHMR1_INPUT_I1PRES_POSS,AD16C4T_CHMR1_INPUT_I1PRES_POSE) + +#define AD16C4T_CHMR1_INPUT_CC1SSEL_POSS 0U +#define AD16C4T_CHMR1_INPUT_CC1SSEL_POSE 1U +#define AD16C4T_CHMR1_INPUT_CC1SSEL_MSK BITS(AD16C4T_CHMR1_INPUT_CC1SSEL_POSS,AD16C4T_CHMR1_INPUT_CC1SSEL_POSE) + +/****************** Bit definition for AD16C4T_CHMR2_OUTPUT register ************************/ + +#define AD16C4T_CHMR2_OUTPUT_CH4OCLREN_POS 15U +#define AD16C4T_CHMR2_OUTPUT_CH4OCLREN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH4OCLREN_POS) + +#define AD16C4T_CHMR2_OUTPUT_CH4MOD_POSS 12U +#define AD16C4T_CHMR2_OUTPUT_CH4MOD_POSE 14U +#define AD16C4T_CHMR2_OUTPUT_CH4MOD_MSK BITS(AD16C4T_CHMR2_OUTPUT_CH4MOD_POSS,AD16C4T_CHMR2_OUTPUT_CH4MOD_POSE) + +#define AD16C4T_CHMR2_OUTPUT_CH4PEN_POS 11U +#define AD16C4T_CHMR2_OUTPUT_CH4PEN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH4PEN_POS) + +#define AD16C4T_CHMR2_OUTPUT_CH4FEN_POS 10U +#define AD16C4T_CHMR2_OUTPUT_CH4FEN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH4FEN_POS) + +#define AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSS 8U +#define AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSE 9U +#define AD16C4T_CHMR2_OUTPUT_CC4SSEL_MSK BITS(AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSS,AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSE) + +#define AD16C4T_CHMR2_OUTPUT_CH3OCLREN_POS 7U +#define AD16C4T_CHMR2_OUTPUT_CH3OCLREN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH3OCLREN_POS) + +#define AD16C4T_CHMR2_OUTPUT_CH3MOD_POSS 4U +#define AD16C4T_CHMR2_OUTPUT_CH3MOD_POSE 6U +#define AD16C4T_CHMR2_OUTPUT_CH3MOD_MSK BITS(AD16C4T_CHMR2_OUTPUT_CH3MOD_POSS,AD16C4T_CHMR2_OUTPUT_CH3MOD_POSE) + +#define AD16C4T_CHMR2_OUTPUT_CH3PEN_POS 3U +#define AD16C4T_CHMR2_OUTPUT_CH3PEN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH3PEN_POS) + +#define AD16C4T_CHMR2_OUTPUT_CH3FEN_POS 2U +#define AD16C4T_CHMR2_OUTPUT_CH3FEN_MSK BIT(AD16C4T_CHMR2_OUTPUT_CH3FEN_POS) + +#define AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSS 0U +#define AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSE 1U +#define AD16C4T_CHMR2_OUTPUT_CC3SSEL_MSK BITS(AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSS,AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSE) + +/****************** Bit definition for AD16C4T_CHMR2_INPUT register ************************/ + +#define AD16C4T_CHMR2_INPUT_I4FLT_POSS 12U +#define AD16C4T_CHMR2_INPUT_I4FLT_POSE 15U +#define AD16C4T_CHMR2_INPUT_I4FLT_MSK BITS(AD16C4T_CHMR2_INPUT_I4FLT_POSS,AD16C4T_CHMR2_INPUT_I4FLT_POSE) + +#define AD16C4T_CHMR2_INPUT_I4PRES_POSS 10U +#define AD16C4T_CHMR2_INPUT_I4PRES_POSE 11U +#define AD16C4T_CHMR2_INPUT_I4PRES_MSK BITS(AD16C4T_CHMR2_INPUT_I4PRES_POSS,AD16C4T_CHMR2_INPUT_I4PRES_POSE) + +#define AD16C4T_CHMR2_INPUT_CC4SSEL_POSS 8U +#define AD16C4T_CHMR2_INPUT_CC4SSEL_POSE 9U +#define AD16C4T_CHMR2_INPUT_CC4SSEL_MSK BITS(AD16C4T_CHMR2_INPUT_CC4SSEL_POSS,AD16C4T_CHMR2_INPUT_CC4SSEL_POSE) + +#define AD16C4T_CHMR2_INPUT_I3FLT_POSS 4U +#define AD16C4T_CHMR2_INPUT_I3FLT_POSE 7U +#define AD16C4T_CHMR2_INPUT_I3FLT_MSK BITS(AD16C4T_CHMR2_INPUT_I3FLT_POSS,AD16C4T_CHMR2_INPUT_I3FLT_POSE) + +#define AD16C4T_CHMR2_INPUT_I3PRES_POSS 2U +#define AD16C4T_CHMR2_INPUT_I3PRES_POSE 3U +#define AD16C4T_CHMR2_INPUT_I3PRES_MSK BITS(AD16C4T_CHMR2_INPUT_I3PRES_POSS,AD16C4T_CHMR2_INPUT_I3PRES_POSE) + +#define AD16C4T_CHMR2_INPUT_CC3SSEL_POSS 0U +#define AD16C4T_CHMR2_INPUT_CC3SSEL_POSE 1U +#define AD16C4T_CHMR2_INPUT_CC3SSEL_MSK BITS(AD16C4T_CHMR2_INPUT_CC3SSEL_POSS,AD16C4T_CHMR2_INPUT_CC3SSEL_POSE) + +/****************** Bit definition for AD16C4T_CCEP register ************************/ + +#define AD16C4T_CCEP_CC4NPOL_POS 15U +#define AD16C4T_CCEP_CC4NPOL_MSK BIT(AD16C4T_CCEP_CC4NPOL_POS) + +#define AD16C4T_CCEP_CC4POL_POS 13U +#define AD16C4T_CCEP_CC4POL_MSK BIT(AD16C4T_CCEP_CC4POL_POS) + +#define AD16C4T_CCEP_CC4EN_POS 12U +#define AD16C4T_CCEP_CC4EN_MSK BIT(AD16C4T_CCEP_CC4EN_POS) + +#define AD16C4T_CCEP_CC3NPOL_POS 11U +#define AD16C4T_CCEP_CC3NPOL_MSK BIT(AD16C4T_CCEP_CC3NPOL_POS) + +#define AD16C4T_CCEP_CC3NEN_POS 10U +#define AD16C4T_CCEP_CC3NEN_MSK BIT(AD16C4T_CCEP_CC3NEN_POS) + +#define AD16C4T_CCEP_CC3POL_POS 9U +#define AD16C4T_CCEP_CC3POL_MSK BIT(AD16C4T_CCEP_CC3POL_POS) + +#define AD16C4T_CCEP_CC3EN_POS 8U +#define AD16C4T_CCEP_CC3EN_MSK BIT(AD16C4T_CCEP_CC3EN_POS) + +#define AD16C4T_CCEP_CC2NPOL_POS 7U +#define AD16C4T_CCEP_CC2NPOL_MSK BIT(AD16C4T_CCEP_CC2NPOL_POS) + +#define AD16C4T_CCEP_CC2NEN_POS 6U +#define AD16C4T_CCEP_CC2NEN_MSK BIT(AD16C4T_CCEP_CC2NEN_POS) + +#define AD16C4T_CCEP_CC2POL_POS 5U +#define AD16C4T_CCEP_CC2POL_MSK BIT(AD16C4T_CCEP_CC2POL_POS) + +#define AD16C4T_CCEP_CC2EN_POS 4U +#define AD16C4T_CCEP_CC2EN_MSK BIT(AD16C4T_CCEP_CC2EN_POS) + +#define AD16C4T_CCEP_CC1NPOL_POS 3U +#define AD16C4T_CCEP_CC1NPOL_MSK BIT(AD16C4T_CCEP_CC1NPOL_POS) + +#define AD16C4T_CCEP_CC1NEN_POS 2U +#define AD16C4T_CCEP_CC1NEN_MSK BIT(AD16C4T_CCEP_CC1NEN_POS) + +#define AD16C4T_CCEP_CC1POL_POS 1U +#define AD16C4T_CCEP_CC1POL_MSK BIT(AD16C4T_CCEP_CC1POL_POS) + +#define AD16C4T_CCEP_CC1EN_POS 0U +#define AD16C4T_CCEP_CC1EN_MSK BIT(AD16C4T_CCEP_CC1EN_POS) + +/****************** Bit definition for AD16C4T_COUNT register ************************/ + +#define AD16C4T_COUNT_CNTV_POSS 0U +#define AD16C4T_COUNT_CNTV_POSE 15U +#define AD16C4T_COUNT_CNTV_MSK BITS(AD16C4T_COUNT_CNTV_POSS,AD16C4T_COUNT_CNTV_POSE) + +/****************** Bit definition for AD16C4T_PRES register ************************/ + +#define AD16C4T_PRES_PSCV_POSS 0U +#define AD16C4T_PRES_PSCV_POSE 15U +#define AD16C4T_PRES_PSCV_MSK BITS(AD16C4T_PRES_PSCV_POSS,AD16C4T_PRES_PSCV_POSE) + +/****************** Bit definition for AD16C4T_AR register ************************/ + +#define AD16C4T_AR_ARV_POSS 0U +#define AD16C4T_AR_ARV_POSE 15U +#define AD16C4T_AR_ARV_MSK BITS(AD16C4T_AR_ARV_POSS,AD16C4T_AR_ARV_POSE) + +/****************** Bit definition for AD16C4T_REPAR register ************************/ + +#define AD16C4T_REPAR_REPV_POSS 0U +#define AD16C4T_REPAR_REPV_POSE 7U +#define AD16C4T_REPAR_REPV_MSK BITS(AD16C4T_REPAR_REPV_POSS,AD16C4T_REPAR_REPV_POSE) + +/****************** Bit definition for AD16C4T_CCVAL1 register ************************/ + +#define AD16C4T_CCVAL1_CCRV1_POSS 0U +#define AD16C4T_CCVAL1_CCRV1_POSE 15U +#define AD16C4T_CCVAL1_CCRV1_MSK BITS(AD16C4T_CCVAL1_CCRV1_POSS,AD16C4T_CCVAL1_CCRV1_POSE) + +/****************** Bit definition for AD16C4T_CCVAL2 register ************************/ + +#define AD16C4T_CCVAL2_CCRV2_POSS 0U +#define AD16C4T_CCVAL2_CCRV2_POSE 15U +#define AD16C4T_CCVAL2_CCRV2_MSK BITS(AD16C4T_CCVAL2_CCRV2_POSS,AD16C4T_CCVAL2_CCRV2_POSE) + +/****************** Bit definition for AD16C4T_CCVAL3 register ************************/ + +#define AD16C4T_CCVAL3_CCRV3_POSS 0U +#define AD16C4T_CCVAL3_CCRV3_POSE 15U +#define AD16C4T_CCVAL3_CCRV3_MSK BITS(AD16C4T_CCVAL3_CCRV3_POSS,AD16C4T_CCVAL3_CCRV3_POSE) + +/****************** Bit definition for AD16C4T_CCVAL4 register ************************/ + +#define AD16C4T_CCVAL4_CCRV4_POSS 0U +#define AD16C4T_CCVAL4_CCRV4_POSE 15U +#define AD16C4T_CCVAL4_CCRV4_MSK BITS(AD16C4T_CCVAL4_CCRV4_POSS,AD16C4T_CCVAL4_CCRV4_POSE) + +/****************** Bit definition for AD16C4T_BDCFG register ************************/ + +#define AD16C4T_BDCFG_GOEN_POS 15U +#define AD16C4T_BDCFG_GOEN_MSK BIT(AD16C4T_BDCFG_GOEN_POS) + +#define AD16C4T_BDCFG_AOEN_POS 14U +#define AD16C4T_BDCFG_AOEN_MSK BIT(AD16C4T_BDCFG_AOEN_POS) + +#define AD16C4T_BDCFG_BRKP_POS 13U +#define AD16C4T_BDCFG_BRKP_MSK BIT(AD16C4T_BDCFG_BRKP_POS) + +#define AD16C4T_BDCFG_BRKEN_POS 12U +#define AD16C4T_BDCFG_BRKEN_MSK BIT(AD16C4T_BDCFG_BRKEN_POS) + +#define AD16C4T_BDCFG_OFFSSR_POS 11U +#define AD16C4T_BDCFG_OFFSSR_MSK BIT(AD16C4T_BDCFG_OFFSSR_POS) + +#define AD16C4T_BDCFG_OFFSSI_POS 10U +#define AD16C4T_BDCFG_OFFSSI_MSK BIT(AD16C4T_BDCFG_OFFSSI_POS) + +#define AD16C4T_BDCFG_LOCKLVL_POSS 8U +#define AD16C4T_BDCFG_LOCKLVL_POSE 9U +#define AD16C4T_BDCFG_LOCKLVL_MSK BITS(AD16C4T_BDCFG_LOCKLVL_POSS,AD16C4T_BDCFG_LOCKLVL_POSE) + +#define AD16C4T_BDCFG_DT_POSS 0U +#define AD16C4T_BDCFG_DT_POSE 7U +#define AD16C4T_BDCFG_DT_MSK BITS(AD16C4T_BDCFG_DT_POSS,AD16C4T_BDCFG_DT_POSE) + +/****************** Bit definition for AD16C4T_DMAEN register ************************/ + +#define AD16C4T_DMAEN_TRGIDE_POS 6U +#define AD16C4T_DMAEN_TRGIDE_MSK BIT(AD16C4T_DMAEN_TRGIDE_POS) + +#define AD16C4T_DMAEN_COMDE_POS 5U +#define AD16C4T_DMAEN_COMDE_MSK BIT(AD16C4T_DMAEN_COMDE_POS) + +#define AD16C4T_DMAEN_CH4DE_POS 4U +#define AD16C4T_DMAEN_CH4DE_MSK BIT(AD16C4T_DMAEN_CH4DE_POS) + +#define AD16C4T_DMAEN_CH3DE_POS 3U +#define AD16C4T_DMAEN_CH3DE_MSK BIT(AD16C4T_DMAEN_CH3DE_POS) + +#define AD16C4T_DMAEN_CH2DE_POS 2U +#define AD16C4T_DMAEN_CH2DE_MSK BIT(AD16C4T_DMAEN_CH2DE_POS) + +#define AD16C4T_DMAEN_CH1DE_POS 1U +#define AD16C4T_DMAEN_CH1DE_MSK BIT(AD16C4T_DMAEN_CH1DE_POS) + +#define AD16C4T_DMAEN_UDE_POS 0U +#define AD16C4T_DMAEN_UDE_MSK BIT(AD16C4T_DMAEN_UDE_POS) + +typedef struct +{ + __IO uint32_t CON1; /* 0x000 AD16C4T_CON1 Control register 1 */ + __IO uint32_t CON2; /* 0x004 AD16C4T_CON2 Control register 2 */ + __IO uint32_t SMCON; /* 0x008 AD16C4T_SMCON Slave mode control register */ + __O uint32_t IER; /* 0x00C AD16C4T_IER Interrupt Enable register */ + __O uint32_t IDR; /* 0x010 AD16C4T_IDR Interrupt Disable register */ + __I uint32_t IVS; /* 0x014 AD16C4T_IVS Interrupt Valid status register */ + __I uint32_t RIF; /* 0x018 AD16C4T_RIF Interrupt Raw interrupt Flag */ + __I uint32_t IFM; /* 0x01C AD16C4T_IFM Interrupt Masked interrupt Flag */ + __O uint32_t ICR; /* 0x020 AD16C4T_ICR Interrupt Clear status register */ + __O uint32_t SGE; /* 0x024 AD16C4T_SGE Event generation register */ + __IO uint32_t CHMR1; /* 0x028 AD16C4T_CHMR1 Capture/compare mode register 1 */ + __IO uint32_t CHMR2; /* 0x02C AD16C4T_CHMR2 Capture/compare mode register 2 */ + __IO uint32_t CCEP; /* 0x030 AD16C4T_CCEP Capture/compare enable register */ + __IO uint32_t COUNT; /* 0x034 AD16C4T_COUNT Timer Counter */ + __IO uint32_t PRES; /* 0x038 AD16C4T_PRES Prescaler */ + __IO uint32_t AR; /* 0x03C AD16C4T_AR Auto-reload register */ + __IO uint32_t REPAR; /* 0x040 AD16C4T_REPAR Repetition counter register */ + __IO uint32_t CCVAL1; /* 0x044 AD16C4T_CCVAL1 Capture/compare register 1 */ + __IO uint32_t CCVAL2; /* 0x048 AD16C4T_CCVAL2 Capture/compare register 2 */ + __IO uint32_t CCVAL3; /* 0x04C AD16C4T_CCVAL3 Capture/compare register 3 */ + __IO uint32_t CCVAL4; /* 0x050 AD16C4T_CCVAL4 Capture/compare register 4 */ + __IO uint32_t BDCFG; /* 0x054 AD16C4T_BDCFG Break and dead-time register */ + __IO uint32_t DMAEN; /* 0x058 AD16C4T_DMAEN DMA trigger event enable */ +} AD16C4T_TypeDef; + +#endif +/******************* (C) COPYRIGHT Eastsoft Microelectronics END OF REG_AD16C4T.H****/ + diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_adc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..e1b57e2773c6fb7b4f19160047f8c1f75aaf12aa --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_adc.h @@ -0,0 +1,795 @@ +/** + ************************************************************************************** + * @file REG_ADC.h + * @brief ADC Header File + * + * @version V1.00.01 + * @date 04/12/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __ADC_H__ +#define __ADC_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for ADC_CFG register ************************/ + +#define ADC_CFG_TESTEN_POSS 8U +#define ADC_CFG_TESTEN_POSE 15U +#define ADC_CFG_TESTEN_MSK BITS(ADC_CFG_TESTEN_POSS,ADC_CFG_TESTEN_POSE) + +#define ADC_CFG_MODE_POS 0U +#define ADC_CFG_MODE_MSK BIT(ADC_CFG_MODE_POS) + +/****************** Bit definition for ADC_SRATE register ************************/ + +#define ADC_SRATE_CNT_POSS 16U +#define ADC_SRATE_CNT_POSE 23U +#define ADC_SRATE_CNT_MSK BITS(ADC_SRATE_CNT_POSS,ADC_SRATE_CNT_POSE) + +#define ADC_SRATE_CNTINI_POSS 8U +#define ADC_SRATE_CNTINI_POSE 15U +#define ADC_SRATE_CNTINI_MSK BITS(ADC_SRATE_CNTINI_POSS,ADC_SRATE_CNTINI_POSE) + +#define ADC_SRATE_CKDIV_POSS 1U +#define ADC_SRATE_CKDIV_POSE 4U +#define ADC_SRATE_CKDIV_MSK BITS(ADC_SRATE_CKDIV_POSS,ADC_SRATE_CKDIV_POSE) + +#define ADC_SRATE_CKEN_POS 0U +#define ADC_SRATE_CKEN_MSK BIT(ADC_SRATE_CKEN_POS) + +/****************** Bit definition for ADC_CHINV register ************************/ + +#define ADC_CHINV_CH15INV_POS 15U +#define ADC_CHINV_CH15INV_MSK BIT(ADC_CHINV_CH15INV_POS) + +#define ADC_CHINV_CH14INV_POS 14U +#define ADC_CHINV_CH14INV_MSK BIT(ADC_CHINV_CH14INV_POS) + +#define ADC_CHINV_CH13INV_POS 13U +#define ADC_CHINV_CH13INV_MSK BIT(ADC_CHINV_CH13INV_POS) + +#define ADC_CHINV_CH12INV_POS 12U +#define ADC_CHINV_CH12INV_MSK BIT(ADC_CHINV_CH12INV_POS) + +#define ADC_CHINV_CH11INV_POS 11U +#define ADC_CHINV_CH11INV_MSK BIT(ADC_CHINV_CH11INV_POS) + +#define ADC_CHINV_CH10INV_POS 10U +#define ADC_CHINV_CH10INV_MSK BIT(ADC_CHINV_CH10INV_POS) + +#define ADC_CHINV_CH9INV_POS 9U +#define ADC_CHINV_CH9INV_MSK BIT(ADC_CHINV_CH9INV_POS) + +#define ADC_CHINV_CH8INV_POS 8U +#define ADC_CHINV_CH8INV_MSK BIT(ADC_CHINV_CH8INV_POS) + +#define ADC_CHINV_CH7INV_POS 7U +#define ADC_CHINV_CH7INV_MSK BIT(ADC_CHINV_CH7INV_POS) + +#define ADC_CHINV_CH6INV_POS 6U +#define ADC_CHINV_CH6INV_MSK BIT(ADC_CHINV_CH6INV_POS) + +#define ADC_CHINV_CH5INV_POS 5U +#define ADC_CHINV_CH5INV_MSK BIT(ADC_CHINV_CH5INV_POS) + +#define ADC_CHINV_CH4INV_POS 4U +#define ADC_CHINV_CH4INV_MSK BIT(ADC_CHINV_CH4INV_POS) + +#define ADC_CHINV_CH3INV_POS 3U +#define ADC_CHINV_CH3INV_MSK BIT(ADC_CHINV_CH3INV_POS) + +#define ADC_CHINV_CH2INV_POS 2U +#define ADC_CHINV_CH2INV_MSK BIT(ADC_CHINV_CH2INV_POS) + +#define ADC_CHINV_CH1INV_POS 1U +#define ADC_CHINV_CH1INV_MSK BIT(ADC_CHINV_CH1INV_POS) + +#define ADC_CHINV_CH0INV_POS 0U +#define ADC_CHINV_CH0INV_MSK BIT(ADC_CHINV_CH0INV_POS) + +/****************** Bit definition for ADC_GAINL register ************************/ + +#define ADC_GAINL_CH7PGA_POSS 21U +#define ADC_GAINL_CH7PGA_POSE 23U +#define ADC_GAINL_CH7PGA_MSK BITS(ADC_GAINL_CH7PGA_POSS,ADC_GAINL_CH7PGA_POSE) + +#define ADC_GAINL_CH6PGA_POSS 18U +#define ADC_GAINL_CH6PGA_POSE 20U +#define ADC_GAINL_CH6PGA_MSK BITS(ADC_GAINL_CH6PGA_POSS,ADC_GAINL_CH6PGA_POSE) + +#define ADC_GAINL_CH5PGA_POSS 15U +#define ADC_GAINL_CH5PGA_POSE 17U +#define ADC_GAINL_CH5PGA_MSK BITS(ADC_GAINL_CH5PGA_POSS,ADC_GAINL_CH5PGA_POSE) + +#define ADC_GAINL_CH4PGA_POSS 12U +#define ADC_GAINL_CH4PGA_POSE 14U +#define ADC_GAINL_CH4PGA_MSK BITS(ADC_GAINL_CH4PGA_POSS,ADC_GAINL_CH4PGA_POSE) + +#define ADC_GAINL_CH3PGA_POSS 9U +#define ADC_GAINL_CH3PGA_POSE 11U +#define ADC_GAINL_CH3PGA_MSK BITS(ADC_GAINL_CH3PGA_POSS,ADC_GAINL_CH3PGA_POSE) + +#define ADC_GAINL_CH2PGA_POSS 6U +#define ADC_GAINL_CH2PGA_POSE 8U +#define ADC_GAINL_CH2PGA_MSK BITS(ADC_GAINL_CH2PGA_POSS,ADC_GAINL_CH2PGA_POSE) + +#define ADC_GAINL_CH1PGA_POSS 3U +#define ADC_GAINL_CH1PGA_POSE 5U +#define ADC_GAINL_CH1PGA_MSK BITS(ADC_GAINL_CH1PGA_POSS,ADC_GAINL_CH1PGA_POSE) + +#define ADC_GAINL_CH0PGA_POSS 0U +#define ADC_GAINL_CH0PGA_POSE 2U +#define ADC_GAINL_CH0PGA_MSK BITS(ADC_GAINL_CH0PGA_POSS,ADC_GAINL_CH0PGA_POSE) + +/****************** Bit definition for ADC_GAINH register ************************/ + +#define ADC_GAINH_CH15PGA_POSS 21U +#define ADC_GAINH_CH15PGA_POSE 23U +#define ADC_GAINH_CH15PGA_MSK BITS(ADC_GAINH_CH15PGA_POSS,ADC_GAINH_CH15PGA_POSE) + +#define ADC_GAINH_CH14PGA_POSS 18U +#define ADC_GAINH_CH14PGA_POSE 20U +#define ADC_GAINH_CH14PGA_MSK BITS(ADC_GAINH_CH14PGA_POSS,ADC_GAINH_CH14PGA_POSE) + +#define ADC_GAINH_CH13PGA_POSS 15U +#define ADC_GAINH_CH13PGA_POSE 17U +#define ADC_GAINH_CH13PGA_MSK BITS(ADC_GAINH_CH13PGA_POSS,ADC_GAINH_CH13PGA_POSE) + +#define ADC_GAINH_CH12PGA_POSS 12U +#define ADC_GAINH_CH12PGA_POSE 14U +#define ADC_GAINH_CH12PGA_MSK BITS(ADC_GAINH_CH12PGA_POSS,ADC_GAINH_CH12PGA_POSE) + +#define ADC_GAINH_CH11PGA_POSS 9U +#define ADC_GAINH_CH11PGA_POSE 11U +#define ADC_GAINH_CH11PGA_MSK BITS(ADC_GAINH_CH11PGA_POSS,ADC_GAINH_CH11PGA_POSE) + +#define ADC_GAINH_CH10PGA_POSS 6U +#define ADC_GAINH_CH10PGA_POSE 8U +#define ADC_GAINH_CH10PGA_MSK BITS(ADC_GAINH_CH10PGA_POSS,ADC_GAINH_CH10PGA_POSE) + +#define ADC_GAINH_CH9PGA_POSS 3U +#define ADC_GAINH_CH9PGA_POSE 5U +#define ADC_GAINH_CH9PGA_MSK BITS(ADC_GAINH_CH9PGA_POSS,ADC_GAINH_CH9PGA_POSE) + +#define ADC_GAINH_CH8PGA_POSS 0U +#define ADC_GAINH_CH8PGA_POSE 2U +#define ADC_GAINH_CH8PGA_MSK BITS(ADC_GAINH_CH8PGA_POSS,ADC_GAINH_CH8PGA_POSE) + +/****************** Bit definition for ADC_FRF register ************************/ + +#define ADC_FRF_FFRST_POS 4U +#define ADC_FRF_FFRST_MSK BIT(ADC_FRF_FFRST_POS) + +#define ADC_FRF_SS3RF_POS 3U +#define ADC_FRF_SS3RF_MSK BIT(ADC_FRF_SS3RF_POS) + +#define ADC_FRF_SS2RF_POS 2U +#define ADC_FRF_SS2RF_MSK BIT(ADC_FRF_SS2RF_POS) + +#define ADC_FRF_SS1RF_POS 1U +#define ADC_FRF_SS1RF_MSK BIT(ADC_FRF_SS1RF_POS) + +#define ADC_FRF_SS0RF_POS 0U +#define ADC_FRF_SS0RF_MSK BIT(ADC_FRF_SS0RF_POS) + +/****************** Bit definition for ADC_SSEN register ************************/ + +#define ADC_SSEN_IDLE_POS 4U +#define ADC_SSEN_IDLE_MSK BIT(ADC_SSEN_IDLE_POS) + +#define ADC_SSEN_SS3EN_POS 3U +#define ADC_SSEN_SS3EN_MSK BIT(ADC_SSEN_SS3EN_POS) + +#define ADC_SSEN_SS2EN_POS 2U +#define ADC_SSEN_SS2EN_MSK BIT(ADC_SSEN_SS2EN_POS) + +#define ADC_SSEN_SS1EN_POS 1U +#define ADC_SSEN_SS1EN_MSK BIT(ADC_SSEN_SS1EN_POS) + +#define ADC_SSEN_SS0EN_POS 0U +#define ADC_SSEN_SS0EN_MSK BIT(ADC_SSEN_SS0EN_POS) + +/****************** Bit definition for ADC_SWTRI register ************************/ + +#define ADC_SWTRI_SS3_POS 3U +#define ADC_SWTRI_SS3_MSK BIT(ADC_SWTRI_SS3_POS) + +#define ADC_SWTRI_SS2_POS 2U +#define ADC_SWTRI_SS2_MSK BIT(ADC_SWTRI_SS2_POS) + +#define ADC_SWTRI_SS1_POS 1U +#define ADC_SWTRI_SS1_MSK BIT(ADC_SWTRI_SS1_POS) + +#define ADC_SWTRI_SS0_POS 0U +#define ADC_SWTRI_SS0_MSK BIT(ADC_SWTRI_SS0_POS) + +/****************** Bit definition for ADC_IER register ************************/ + +#define ADC_IER_TOIE_POS 4U +#define ADC_IER_TOIE_MSK BIT(ADC_IER_TOIE_POS) + +#define ADC_IER_SS3IE_POS 3U +#define ADC_IER_SS3IE_MSK BIT(ADC_IER_SS3IE_POS) + +#define ADC_IER_SS2IE_POS 2U +#define ADC_IER_SS2IE_MSK BIT(ADC_IER_SS2IE_POS) + +#define ADC_IER_SS1IE_POS 1U +#define ADC_IER_SS1IE_MSK BIT(ADC_IER_SS1IE_POS) + +#define ADC_IER_SS0IE_POS 0U +#define ADC_IER_SS0IE_MSK BIT(ADC_IER_SS0IE_POS) + +/****************** Bit definition for ADC_IDR register ************************/ + +#define ADC_IDR_TOID_POS 4U +#define ADC_IDR_TOID_MSK BIT(ADC_IDR_TOID_POS) + +#define ADC_IDR_SS3ID_POS 3U +#define ADC_IDR_SS3ID_MSK BIT(ADC_IDR_SS3ID_POS) + +#define ADC_IDR_SS2ID_POS 2U +#define ADC_IDR_SS2ID_MSK BIT(ADC_IDR_SS2ID_POS) + +#define ADC_IDR_SS1ID_POS 1U +#define ADC_IDR_SS1ID_MSK BIT(ADC_IDR_SS1ID_POS) + +#define ADC_IDR_SS0ID_POS 0U +#define ADC_IDR_SS0ID_MSK BIT(ADC_IDR_SS0ID_POS) + +/****************** Bit definition for ADC_IVS register ************************/ + +#define ADC_IVS_TOIVS_POS 4U +#define ADC_IVS_TOIVS_MSK BIT(ADC_IVS_TOIVS_POS) + +#define ADC_IVS_SS3IVS_POS 3U +#define ADC_IVS_SS3IVS_MSK BIT(ADC_IVS_SS3IVS_POS) + +#define ADC_IVS_SS2IVS_POS 2U +#define ADC_IVS_SS2IVS_MSK BIT(ADC_IVS_SS2IVS_POS) + +#define ADC_IVS_SS1IVS_POS 1U +#define ADC_IVS_SS1IVS_MSK BIT(ADC_IVS_SS1IVS_POS) + +#define ADC_IVS_SS0IVS_POS 0U +#define ADC_IVS_SS0IVS_MSK BIT(ADC_IVS_SS0IVS_POS) + +/****************** Bit definition for ADC_RIF register ************************/ + +#define ADC_RIF_TORIF_POS 4U +#define ADC_RIF_TORIF_MSK BIT(ADC_RIF_TORIF_POS) + +#define ADC_RIF_SS3RIF_POS 3U +#define ADC_RIF_SS3RIF_MSK BIT(ADC_RIF_SS3RIF_POS) + +#define ADC_RIF_SS2RIF_POS 2U +#define ADC_RIF_SS2RIF_MSK BIT(ADC_RIF_SS2RIF_POS) + +#define ADC_RIF_SS1RIF_POS 1U +#define ADC_RIF_SS1RIF_MSK BIT(ADC_RIF_SS1RIF_POS) + +#define ADC_RIF_SS0RIF_POS 0U +#define ADC_RIF_SS0RIF_MSK BIT(ADC_RIF_SS0RIF_POS) + +/****************** Bit definition for ADC_IFM register ************************/ + +#define ADC_IFM_TOIFM_POS 4U +#define ADC_IFM_TOIFM_MSK BIT(ADC_IFM_TOIFM_POS) + +#define ADC_IFM_SS3IFM_POS 3U +#define ADC_IFM_SS3IFM_MSK BIT(ADC_IFM_SS3IFM_POS) + +#define ADC_IFM_SS2IFM_POS 2U +#define ADC_IFM_SS2IFM_MSK BIT(ADC_IFM_SS2IFM_POS) + +#define ADC_IFM_SS1IFM_POS 1U +#define ADC_IFM_SS1IFM_MSK BIT(ADC_IFM_SS1IFM_POS) + +#define ADC_IFM_SS0IFM_POS 0U +#define ADC_IFM_SS0IFM_MSK BIT(ADC_IFM_SS0IFM_POS) + +/****************** Bit definition for ADC_ICR register ************************/ + +#define ADC_ICR_TOICR_POS 4U +#define ADC_ICR_TOICR_MSK BIT(ADC_ICR_TOICR_POS) + +#define ADC_ICR_SS3ICR_POS 3U +#define ADC_ICR_SS3ICR_MSK BIT(ADC_ICR_SS3ICR_POS) + +#define ADC_ICR_SS2ICR_POS 2U +#define ADC_ICR_SS2ICR_MSK BIT(ADC_ICR_SS2ICR_POS) + +#define ADC_ICR_SS1ICR_POS 1U +#define ADC_ICR_SS1ICR_MSK BIT(ADC_ICR_SS1ICR_POS) + +#define ADC_ICR_SS0ICR_POS 0U +#define ADC_ICR_SS0ICR_MSK BIT(ADC_ICR_SS0ICR_POS) + +/****************** Bit definition for ADC_DMA register ************************/ + +#define ADC_DMA_SS3_DMAEN_POS 3U +#define ADC_DMA_SS3_DMAEN_MSK BIT(ADC_DMA_SS3_DMAEN_POS) + +#define ADC_DMA_SS2_DMAEN_POS 2U +#define ADC_DMA_SS2_DMAEN_MSK BIT(ADC_DMA_SS2_DMAEN_POS) + +#define ADC_DMA_SS1_DMAEN_POS 1U +#define ADC_DMA_SS1_DMAEN_MSK BIT(ADC_DMA_SS1_DMAEN_POS) + +#define ADC_DMA_SS0_DMAEN_POS 0U +#define ADC_DMA_SS0_DMAEN_MSK BIT(ADC_DMA_SS0_DMAEN_POS) + +/****************** Bit definition for ADC_SS0_CON register ************************/ + +#define ADC_SS0_CON_SEL_POSS 11U +#define ADC_SS0_CON_SEL_POSE 15U +#define ADC_SS0_CON_SEL_MSK BITS(ADC_SS0_CON_SEL_POSS,ADC_SS0_CON_SEL_POSE) + +#define ADC_SS0_CON_TYP_POS 8U +#define ADC_SS0_CON_TYP_MSK BIT(ADC_SS0_CON_TYP_POS) + +#define ADC_SS0_CON_PRI_POSS 4U +#define ADC_SS0_CON_PRI_POSE 5U +#define ADC_SS0_CON_PRI_MSK BITS(ADC_SS0_CON_PRI_POSS,ADC_SS0_CON_PRI_POSE) + +#define ADC_SS0_CON_ONE_POS 0U +#define ADC_SS0_CON_ONE_MSK BIT(ADC_SS0_CON_ONE_POS) + +/****************** Bit definition for ADC_SS0_MUX0 register ************************/ + +#define ADC_SS0_MUX0_MUX7_POSS 28U +#define ADC_SS0_MUX0_MUX7_POSE 31U +#define ADC_SS0_MUX0_MUX7_MSK BITS(ADC_SS0_MUX0_MUX7_POSS,ADC_SS0_MUX0_MUX7_POSE) + +#define ADC_SS0_MUX0_MUX6_POSS 24U +#define ADC_SS0_MUX0_MUX6_POSE 27U +#define ADC_SS0_MUX0_MUX6_MSK BITS(ADC_SS0_MUX0_MUX6_POSS,ADC_SS0_MUX0_MUX6_POSE) + +#define ADC_SS0_MUX0_MUX5_POSS 20U +#define ADC_SS0_MUX0_MUX5_POSE 23U +#define ADC_SS0_MUX0_MUX5_MSK BITS(ADC_SS0_MUX0_MUX5_POSS,ADC_SS0_MUX0_MUX5_POSE) + +#define ADC_SS0_MUX0_MUX4_POSS 16U +#define ADC_SS0_MUX0_MUX4_POSE 19U +#define ADC_SS0_MUX0_MUX4_MSK BITS(ADC_SS0_MUX0_MUX4_POSS,ADC_SS0_MUX0_MUX4_POSE) + +#define ADC_SS0_MUX0_MUX3_POSS 12U +#define ADC_SS0_MUX0_MUX3_POSE 15U +#define ADC_SS0_MUX0_MUX3_MSK BITS(ADC_SS0_MUX0_MUX3_POSS,ADC_SS0_MUX0_MUX3_POSE) + +#define ADC_SS0_MUX0_MUX2_POSS 8U +#define ADC_SS0_MUX0_MUX2_POSE 11U +#define ADC_SS0_MUX0_MUX2_MSK BITS(ADC_SS0_MUX0_MUX2_POSS,ADC_SS0_MUX0_MUX2_POSE) + +#define ADC_SS0_MUX0_MUX1_POSS 4U +#define ADC_SS0_MUX0_MUX1_POSE 7U +#define ADC_SS0_MUX0_MUX1_MSK BITS(ADC_SS0_MUX0_MUX1_POSS,ADC_SS0_MUX0_MUX1_POSE) + +#define ADC_SS0_MUX0_MUX0_POSS 0U +#define ADC_SS0_MUX0_MUX0_POSE 3U +#define ADC_SS0_MUX0_MUX0_MSK BITS(ADC_SS0_MUX0_MUX0_POSS,ADC_SS0_MUX0_MUX0_POSE) + +/****************** Bit definition for ADC_SS0_MUX1 register ************************/ + +#define ADC_SS0_MUX1_MUX15_POSS 28U +#define ADC_SS0_MUX1_MUX15_POSE 31U +#define ADC_SS0_MUX1_MUX15_MSK BITS(ADC_SS0_MUX1_MUX15_POSS,ADC_SS0_MUX1_MUX15_POSE) + +#define ADC_SS0_MUX1_MUX14_POSS 24U +#define ADC_SS0_MUX1_MUX14_POSE 27U +#define ADC_SS0_MUX1_MUX14_MSK BITS(ADC_SS0_MUX1_MUX14_POSS,ADC_SS0_MUX1_MUX14_POSE) + +#define ADC_SS0_MUX1_MUX13_POSS 20U +#define ADC_SS0_MUX1_MUX13_POSE 23U +#define ADC_SS0_MUX1_MUX13_MSK BITS(ADC_SS0_MUX1_MUX13_POSS,ADC_SS0_MUX1_MUX13_POSE) + +#define ADC_SS0_MUX1_MUX12_POSS 16U +#define ADC_SS0_MUX1_MUX12_POSE 19U +#define ADC_SS0_MUX1_MUX12_MSK BITS(ADC_SS0_MUX1_MUX12_POSS,ADC_SS0_MUX1_MUX12_POSE) + +#define ADC_SS0_MUX1_MUX11_POSS 12U +#define ADC_SS0_MUX1_MUX11_POSE 15U +#define ADC_SS0_MUX1_MUX11_MSK BITS(ADC_SS0_MUX1_MUX11_POSS,ADC_SS0_MUX1_MUX11_POSE) + +#define ADC_SS0_MUX1_MUX10_POSS 8U +#define ADC_SS0_MUX1_MUX10_POSE 11U +#define ADC_SS0_MUX1_MUX10_MSK BITS(ADC_SS0_MUX1_MUX10_POSS,ADC_SS0_MUX1_MUX10_POSE) + +#define ADC_SS0_MUX1_MUX9_POSS 4U +#define ADC_SS0_MUX1_MUX9_POSE 7U +#define ADC_SS0_MUX1_MUX9_MSK BITS(ADC_SS0_MUX1_MUX9_POSS,ADC_SS0_MUX1_MUX9_POSE) + +#define ADC_SS0_MUX1_MUX8_POSS 0U +#define ADC_SS0_MUX1_MUX8_POSE 3U +#define ADC_SS0_MUX1_MUX8_MSK BITS(ADC_SS0_MUX1_MUX8_POSS,ADC_SS0_MUX1_MUX8_POSE) + +/****************** Bit definition for ADC_SS0_END register ************************/ + +#define ADC_SS0_END_IE15_POS 23U +#define ADC_SS0_END_IE15_MSK BIT(ADC_SS0_END_IE15_POS) + +#define ADC_SS0_END_IE14_POS 22U +#define ADC_SS0_END_IE14_MSK BIT(ADC_SS0_END_IE14_POS) + +#define ADC_SS0_END_IE13_POS 21U +#define ADC_SS0_END_IE13_MSK BIT(ADC_SS0_END_IE13_POS) + +#define ADC_SS0_END_IE12_POS 20U +#define ADC_SS0_END_IE12_MSK BIT(ADC_SS0_END_IE12_POS) + +#define ADC_SS0_END_IE11_POS 19U +#define ADC_SS0_END_IE11_MSK BIT(ADC_SS0_END_IE11_POS) + +#define ADC_SS0_END_IE10_POS 18U +#define ADC_SS0_END_IE10_MSK BIT(ADC_SS0_END_IE10_POS) + +#define ADC_SS0_END_IE9_POS 17U +#define ADC_SS0_END_IE9_MSK BIT(ADC_SS0_END_IE9_POS) + +#define ADC_SS0_END_IE8_POS 16U +#define ADC_SS0_END_IE8_MSK BIT(ADC_SS0_END_IE8_POS) + +#define ADC_SS0_END_IE7_POS 15U +#define ADC_SS0_END_IE7_MSK BIT(ADC_SS0_END_IE7_POS) + +#define ADC_SS0_END_IE6_POS 14U +#define ADC_SS0_END_IE6_MSK BIT(ADC_SS0_END_IE6_POS) + +#define ADC_SS0_END_IE5_POS 13U +#define ADC_SS0_END_IE5_MSK BIT(ADC_SS0_END_IE5_POS) + +#define ADC_SS0_END_IE4_POS 12U +#define ADC_SS0_END_IE4_MSK BIT(ADC_SS0_END_IE4_POS) + +#define ADC_SS0_END_IE3_POS 11U +#define ADC_SS0_END_IE3_MSK BIT(ADC_SS0_END_IE3_POS) + +#define ADC_SS0_END_IE2_POS 10U +#define ADC_SS0_END_IE2_MSK BIT(ADC_SS0_END_IE2_POS) + +#define ADC_SS0_END_IE1_POS 9U +#define ADC_SS0_END_IE1_MSK BIT(ADC_SS0_END_IE1_POS) + +#define ADC_SS0_END_IE0_POS 8U +#define ADC_SS0_END_IE0_MSK BIT(ADC_SS0_END_IE0_POS) + +#define ADC_SS0_END_END_POSS 0U +#define ADC_SS0_END_END_POSE 3U +#define ADC_SS0_END_END_MSK BITS(ADC_SS0_END_END_POSS,ADC_SS0_END_END_POSE) + +/****************** Bit definition for ADC_SS0_FSTAT register ************************/ + +#define ADC_SS0_FSTAT_OV_POS 11U +#define ADC_SS0_FSTAT_OV_MSK BIT(ADC_SS0_FSTAT_OV_POS) + +#define ADC_SS0_FSTAT_FULL_POS 10U +#define ADC_SS0_FSTAT_FULL_MSK BIT(ADC_SS0_FSTAT_FULL_POS) + +#define ADC_SS0_FSTAT_UV_POS 9U +#define ADC_SS0_FSTAT_UV_MSK BIT(ADC_SS0_FSTAT_UV_POS) + +#define ADC_SS0_FSTAT_EMPTY_POS 8U +#define ADC_SS0_FSTAT_EMPTY_MSK BIT(ADC_SS0_FSTAT_EMPTY_POS) + +#define ADC_SS0_FSTAT_HPTR_POSS 4U +#define ADC_SS0_FSTAT_HPTR_POSE 7U +#define ADC_SS0_FSTAT_HPTR_MSK BITS(ADC_SS0_FSTAT_HPTR_POSS,ADC_SS0_FSTAT_HPTR_POSE) + +#define ADC_SS0_FSTAT_TPTR_POSS 0U +#define ADC_SS0_FSTAT_TPTR_POSE 3U +#define ADC_SS0_FSTAT_TPTR_MSK BITS(ADC_SS0_FSTAT_TPTR_POSS,ADC_SS0_FSTAT_TPTR_POSE) + +/****************** Bit definition for ADC_SS0_DATA register ************************/ + +#define ADC_SS0_DATA_DATA_POSS 0U +#define ADC_SS0_DATA_DATA_POSE 11U +#define ADC_SS0_DATA_DATA_MSK BITS(ADC_SS0_DATA_DATA_POSS,ADC_SS0_DATA_DATA_POSE) + +/****************** Bit definition for ADC_SS1_CON register ************************/ + +#define ADC_SS1_CON_SEL_POSS 11U +#define ADC_SS1_CON_SEL_POSE 15U +#define ADC_SS1_CON_SEL_MSK BITS(ADC_SS1_CON_SEL_POSS,ADC_SS1_CON_SEL_POSE) + +#define ADC_SS1_CON_TYP_POS 8U +#define ADC_SS1_CON_TYP_MSK BIT(ADC_SS1_CON_TYP_POS) + +#define ADC_SS1_CON_PRI_POSS 4U +#define ADC_SS1_CON_PRI_POSE 5U +#define ADC_SS1_CON_PRI_MSK BITS(ADC_SS1_CON_PRI_POSS,ADC_SS1_CON_PRI_POSE) + +#define ADC_SS1_CON_ONE_POS 0U +#define ADC_SS1_CON_ONE_MSK BIT(ADC_SS1_CON_ONE_POS) + +/****************** Bit definition for ADC_SS1_MUX0 register ************************/ + +#define ADC_SS1_MUX0_MUX7_POSS 28U +#define ADC_SS1_MUX0_MUX7_POSE 31U +#define ADC_SS1_MUX0_MUX7_MSK BITS(ADC_SS1_MUX0_MUX7_POSS,ADC_SS1_MUX0_MUX7_POSE) + +#define ADC_SS1_MUX0_MUX6_POSS 24U +#define ADC_SS1_MUX0_MUX6_POSE 27U +#define ADC_SS1_MUX0_MUX6_MSK BITS(ADC_SS1_MUX0_MUX6_POSS,ADC_SS1_MUX0_MUX6_POSE) + +#define ADC_SS1_MUX0_MUX5_POSS 20U +#define ADC_SS1_MUX0_MUX5_POSE 23U +#define ADC_SS1_MUX0_MUX5_MSK BITS(ADC_SS1_MUX0_MUX5_POSS,ADC_SS1_MUX0_MUX5_POSE) + +#define ADC_SS1_MUX0_MUX4_POSS 16U +#define ADC_SS1_MUX0_MUX4_POSE 19U +#define ADC_SS1_MUX0_MUX4_MSK BITS(ADC_SS1_MUX0_MUX4_POSS,ADC_SS1_MUX0_MUX4_POSE) + +#define ADC_SS1_MUX0_MUX3_POSS 12U +#define ADC_SS1_MUX0_MUX3_POSE 15U +#define ADC_SS1_MUX0_MUX3_MSK BITS(ADC_SS1_MUX0_MUX3_POSS,ADC_SS1_MUX0_MUX3_POSE) + +#define ADC_SS1_MUX0_MUX2_POSS 8U +#define ADC_SS1_MUX0_MUX2_POSE 11U +#define ADC_SS1_MUX0_MUX2_MSK BITS(ADC_SS1_MUX0_MUX2_POSS,ADC_SS1_MUX0_MUX2_POSE) + +#define ADC_SS1_MUX0_MUX1_POSS 4U +#define ADC_SS1_MUX0_MUX1_POSE 7U +#define ADC_SS1_MUX0_MUX1_MSK BITS(ADC_SS1_MUX0_MUX1_POSS,ADC_SS1_MUX0_MUX1_POSE) + +#define ADC_SS1_MUX0_MUX0_POSS 0U +#define ADC_SS1_MUX0_MUX0_POSE 3U +#define ADC_SS1_MUX0_MUX0_MSK BITS(ADC_SS1_MUX0_MUX0_POSS,ADC_SS1_MUX0_MUX0_POSE) + +/****************** Bit definition for ADC_SS1_END register ************************/ + +#define ADC_SS1_END_IE7_POS 15U +#define ADC_SS1_END_IE7_MSK BIT(ADC_SS1_END_IE7_POS) + +#define ADC_SS1_END_IE6_POS 14U +#define ADC_SS1_END_IE6_MSK BIT(ADC_SS1_END_IE6_POS) + +#define ADC_SS1_END_IE5_POS 13U +#define ADC_SS1_END_IE5_MSK BIT(ADC_SS1_END_IE5_POS) + +#define ADC_SS1_END_IE4_POS 12U +#define ADC_SS1_END_IE4_MSK BIT(ADC_SS1_END_IE4_POS) + +#define ADC_SS1_END_IE3_POS 11U +#define ADC_SS1_END_IE3_MSK BIT(ADC_SS1_END_IE3_POS) + +#define ADC_SS1_END_IE2_POS 10U +#define ADC_SS1_END_IE2_MSK BIT(ADC_SS1_END_IE2_POS) + +#define ADC_SS1_END_IE1_POS 9U +#define ADC_SS1_END_IE1_MSK BIT(ADC_SS1_END_IE1_POS) + +#define ADC_SS1_END_IE0_POS 8U +#define ADC_SS1_END_IE0_MSK BIT(ADC_SS1_END_IE0_POS) + +#define ADC_SS1_END_END_POSS 0U +#define ADC_SS1_END_END_POSE 2U +#define ADC_SS1_END_END_MSK BITS(ADC_SS1_END_END_POSS,ADC_SS1_END_END_POSE) + +/****************** Bit definition for ADC_SS1_FSTAT register ************************/ + +#define ADC_SS1_FSTAT_OV_POS 11U +#define ADC_SS1_FSTAT_OV_MSK BIT(ADC_SS1_FSTAT_OV_POS) + +#define ADC_SS1_FSTAT_FULL_POS 10U +#define ADC_SS1_FSTAT_FULL_MSK BIT(ADC_SS1_FSTAT_FULL_POS) + +#define ADC_SS1_FSTAT_UV_POS 9U +#define ADC_SS1_FSTAT_UV_MSK BIT(ADC_SS1_FSTAT_UV_POS) + +#define ADC_SS1_FSTAT_EMPTY_POS 8U +#define ADC_SS1_FSTAT_EMPTY_MSK BIT(ADC_SS1_FSTAT_EMPTY_POS) + +#define ADC_SS1_FSTAT_HPTR_POSS 4U +#define ADC_SS1_FSTAT_HPTR_POSE 7U +#define ADC_SS1_FSTAT_HPTR_MSK BITS(ADC_SS1_FSTAT_HPTR_POSS,ADC_SS1_FSTAT_HPTR_POSE) + +#define ADC_SS1_FSTAT_TPTR_POSS 0U +#define ADC_SS1_FSTAT_TPTR_POSE 3U +#define ADC_SS1_FSTAT_TPTR_MSK BITS(ADC_SS1_FSTAT_TPTR_POSS,ADC_SS1_FSTAT_TPTR_POSE) + +/****************** Bit definition for ADC_SS1_DATA register ************************/ + +#define ADC_SS1_DATA_DATA_POSS 0U +#define ADC_SS1_DATA_DATA_POSE 11U +#define ADC_SS1_DATA_DATA_MSK BITS(ADC_SS1_DATA_DATA_POSS,ADC_SS1_DATA_DATA_POSE) + +/****************** Bit definition for ADC_SS2_CON register ************************/ + +#define ADC_SS2_CON_SEL_POSS 11U +#define ADC_SS2_CON_SEL_POSE 15U +#define ADC_SS2_CON_SEL_MSK BITS(ADC_SS2_CON_SEL_POSS,ADC_SS2_CON_SEL_POSE) + +#define ADC_SS2_CON_TYP_POS 8U +#define ADC_SS2_CON_TYP_MSK BIT(ADC_SS2_CON_TYP_POS) + +#define ADC_SS2_CON_PRI_POSS 4U +#define ADC_SS2_CON_PRI_POSE 5U +#define ADC_SS2_CON_PRI_MSK BITS(ADC_SS2_CON_PRI_POSS,ADC_SS2_CON_PRI_POSE) + +#define ADC_SS2_CON_ONE_POS 0U +#define ADC_SS2_CON_ONE_MSK BIT(ADC_SS2_CON_ONE_POS) + +/****************** Bit definition for ADC_SS2_MUX0 register ************************/ + +#define ADC_SS2_MUX0_MUX3_POSS 12U +#define ADC_SS2_MUX0_MUX3_POSE 15U +#define ADC_SS2_MUX0_MUX3_MSK BITS(ADC_SS2_MUX0_MUX3_POSS,ADC_SS2_MUX0_MUX3_POSE) + +#define ADC_SS2_MUX0_MUX2_POSS 8U +#define ADC_SS2_MUX0_MUX2_POSE 11U +#define ADC_SS2_MUX0_MUX2_MSK BITS(ADC_SS2_MUX0_MUX2_POSS,ADC_SS2_MUX0_MUX2_POSE) + +#define ADC_SS2_MUX0_MUX1_POSS 4U +#define ADC_SS2_MUX0_MUX1_POSE 7U +#define ADC_SS2_MUX0_MUX1_MSK BITS(ADC_SS2_MUX0_MUX1_POSS,ADC_SS2_MUX0_MUX1_POSE) + +#define ADC_SS2_MUX0_MUX0_POSS 0U +#define ADC_SS2_MUX0_MUX0_POSE 3U +#define ADC_SS2_MUX0_MUX0_MSK BITS(ADC_SS2_MUX0_MUX0_POSS,ADC_SS2_MUX0_MUX0_POSE) + +/****************** Bit definition for ADC_SS2_END register ************************/ + +#define ADC_SS2_END_IE3_POS 11U +#define ADC_SS2_END_IE3_MSK BIT(ADC_SS2_END_IE3_POS) + +#define ADC_SS2_END_IE2_POS 10U +#define ADC_SS2_END_IE2_MSK BIT(ADC_SS2_END_IE2_POS) + +#define ADC_SS2_END_IE1_POS 9U +#define ADC_SS2_END_IE1_MSK BIT(ADC_SS2_END_IE1_POS) + +#define ADC_SS2_END_IE0_POS 8U +#define ADC_SS2_END_IE0_MSK BIT(ADC_SS2_END_IE0_POS) + +#define ADC_SS2_END_END_POSS 0U +#define ADC_SS2_END_END_POSE 1U +#define ADC_SS2_END_END_MSK BITS(ADC_SS2_END_END_POSS,ADC_SS2_END_END_POSE) + +/****************** Bit definition for ADC_SS2_FSTAT register ************************/ + +#define ADC_SS2_FSTAT_OV_POS 11U +#define ADC_SS2_FSTAT_OV_MSK BIT(ADC_SS2_FSTAT_OV_POS) + +#define ADC_SS2_FSTAT_FULL_POS 10U +#define ADC_SS2_FSTAT_FULL_MSK BIT(ADC_SS2_FSTAT_FULL_POS) + +#define ADC_SS2_FSTAT_UV_POS 9U +#define ADC_SS2_FSTAT_UV_MSK BIT(ADC_SS2_FSTAT_UV_POS) + +#define ADC_SS2_FSTAT_EMPTY_POS 8U +#define ADC_SS2_FSTAT_EMPTY_MSK BIT(ADC_SS2_FSTAT_EMPTY_POS) + +#define ADC_SS2_FSTAT_HPTR_POSS 4U +#define ADC_SS2_FSTAT_HPTR_POSE 7U +#define ADC_SS2_FSTAT_HPTR_MSK BITS(ADC_SS2_FSTAT_HPTR_POSS,ADC_SS2_FSTAT_HPTR_POSE) + +#define ADC_SS2_FSTAT_TPTR_POSS 0U +#define ADC_SS2_FSTAT_TPTR_POSE 3U +#define ADC_SS2_FSTAT_TPTR_MSK BITS(ADC_SS2_FSTAT_TPTR_POSS,ADC_SS2_FSTAT_TPTR_POSE) + +/****************** Bit definition for ADC_SS2_DATA register ************************/ + +#define ADC_SS2_DATA_DATA_POSS 0U +#define ADC_SS2_DATA_DATA_POSE 11U +#define ADC_SS2_DATA_DATA_MSK BITS(ADC_SS2_DATA_DATA_POSS,ADC_SS2_DATA_DATA_POSE) + +/****************** Bit definition for ADC_SS3_CON register ************************/ + +#define ADC_SS3_CON_SEL_POSS 11U +#define ADC_SS3_CON_SEL_POSE 15U +#define ADC_SS3_CON_SEL_MSK BITS(ADC_SS3_CON_SEL_POSS,ADC_SS3_CON_SEL_POSE) + +#define ADC_SS3_CON_TYP_POS 8U +#define ADC_SS3_CON_TYP_MSK BIT(ADC_SS3_CON_TYP_POS) + +#define ADC_SS3_CON_PRI_POSS 4U +#define ADC_SS3_CON_PRI_POSE 5U +#define ADC_SS3_CON_PRI_MSK BITS(ADC_SS3_CON_PRI_POSS,ADC_SS3_CON_PRI_POSE) + +#define ADC_SS3_CON_ONE_POS 0U +#define ADC_SS3_CON_ONE_MSK BIT(ADC_SS3_CON_ONE_POS) + +/****************** Bit definition for ADC_SS3_MUX0 register ************************/ + +#define ADC_SS3_MUX0_MUX0_POSS 0U +#define ADC_SS3_MUX0_MUX0_POSE 3U +#define ADC_SS3_MUX0_MUX0_MSK BITS(ADC_SS3_MUX0_MUX0_POSS,ADC_SS3_MUX0_MUX0_POSE) + +/****************** Bit definition for ADC_SS3_END register ************************/ + +#define ADC_SS3_END_IE0_POS 8U +#define ADC_SS3_END_IE0_MSK BIT(ADC_SS3_END_IE0_POS) + +#define ADC_SS3_END_END_POS 0U +#define ADC_SS3_END_END_MSK BIT(ADC_SS3_END_END_POS) + +/****************** Bit definition for ADC_SS3_FSTAT register ************************/ + +#define ADC_SS3_FSTAT_OV_POS 11U +#define ADC_SS3_FSTAT_OV_MSK BIT(ADC_SS3_FSTAT_OV_POS) + +#define ADC_SS3_FSTAT_FULL_POS 10U +#define ADC_SS3_FSTAT_FULL_MSK BIT(ADC_SS3_FSTAT_FULL_POS) + +#define ADC_SS3_FSTAT_UV_POS 9U +#define ADC_SS3_FSTAT_UV_MSK BIT(ADC_SS3_FSTAT_UV_POS) + +#define ADC_SS3_FSTAT_EMPTY_POS 8U +#define ADC_SS3_FSTAT_EMPTY_MSK BIT(ADC_SS3_FSTAT_EMPTY_POS) + +#define ADC_SS3_FSTAT_HPTR_POSS 4U +#define ADC_SS3_FSTAT_HPTR_POSE 7U +#define ADC_SS3_FSTAT_HPTR_MSK BITS(ADC_SS3_FSTAT_HPTR_POSS,ADC_SS3_FSTAT_HPTR_POSE) + +#define ADC_SS3_FSTAT_TPTR_POSS 0U +#define ADC_SS3_FSTAT_TPTR_POSE 3U +#define ADC_SS3_FSTAT_TPTR_MSK BITS(ADC_SS3_FSTAT_TPTR_POSS,ADC_SS3_FSTAT_TPTR_POSE) + +/****************** Bit definition for ADC_SS3_DATA register ************************/ + +#define ADC_SS3_DATA_DATA_POSS 0U +#define ADC_SS3_DATA_DATA_POSE 11U +#define ADC_SS3_DATA_DATA_MSK BITS(ADC_SS3_DATA_DATA_POSS,ADC_SS3_DATA_DATA_POSE) + +typedef struct +{ + __IO uint32_t CFG; + __IO uint32_t SRATE; + __IO uint32_t CHINV; + __IO uint32_t GAINL; + __IO uint32_t GAINH; + __O uint32_t FRF; + __IO uint32_t SSEN; + __IO uint32_t SWTRI; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + __IO uint32_t DMA; + uint32_t RESERVED0 ; + __IO uint32_t SS0_CON; + __IO uint32_t SS0_MUX0; + __IO uint32_t SS0_MUX1; + __IO uint32_t SS0_END; + __I uint32_t SS0_FSTAT; + __IO uint32_t SS0_DATA; + uint32_t RESERVED1[2] ; + __IO uint32_t SS1_CON; + __IO uint32_t SS1_MUX0; + __IO uint32_t SS1_END; + __I uint32_t SS1_FSTAT; + __IO uint32_t SS1_DATA; + uint32_t RESERVED2 ; + __IO uint32_t SS2_CON; + __IO uint32_t SS2_MUX0; + __IO uint32_t SS2_END; + __I uint32_t SS2_FSTAT; + __IO uint32_t SS2_DATA; + uint32_t RESERVED3 ; + __IO uint32_t SS3_CON; + __IO uint32_t SS3_MUX0; + __IO uint32_t SS3_END; + __I uint32_t SS3_FSTAT; + __IO uint32_t SS3_DATA; +} ADC_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_aes.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_aes.h new file mode 100644 index 0000000000000000000000000000000000000000..dd47cdea101d554d024022e839c8710e02f2e3a9 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_aes.h @@ -0,0 +1,193 @@ +/** + ************************************************************************************** + * @file REG_AES.h + * @brief AES Head File + * + * @version V0.01 + * @data 11/16/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __AES_H__ +#define __AES_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for AES_CON register ************************/ + +#define AES_CON_READY_POS 22U +#define AES_CON_READY_MSK BIT(AES_CON_READY_POS) + +#define AES_CON_OT_DMA_ST_POS 21U +#define AES_CON_OT_DMA_ST_MSK BIT(AES_CON_OT_DMA_ST_POS) + +#define AES_CON_IT_DMA_ST_POS 20U +#define AES_CON_IT_DMA_ST_MSK BIT(AES_CON_IT_DMA_ST_POS) + +#define AES_CON_OT_DEPTH_POSS 18U +#define AES_CON_OT_DEPTH_POSE 19U +#define AES_CON_OT_DEPTH_MSK BITS(AES_CON_OT_DEPTH_POSS,AES_CON_OT_DEPTH_POSE) + +#define AES_CON_IT_DEPTH_POSS 16U +#define AES_CON_IT_DEPTH_POSE 17U +#define AES_CON_IT_DEPTH_MSK BITS(AES_CON_IT_DEPTH_POSS,AES_CON_IT_DEPTH_POSE) + +#define AES_CON_RE_INIT_POS 8U +#define AES_CON_RE_INIT_MSK BIT(AES_CON_RE_INIT_POS) + +#define AES_CON_DMA_EN_POSS 6U +#define AES_CON_DMA_EN_POSE 7U +#define AES_CON_DMA_EN_MSK BITS(AES_CON_DMA_EN_POSS,AES_CON_DMA_EN_POSE) + +#define AES_CON_BL_POSS 3U +#define AES_CON_BL_POSE 5U +#define AES_CON_BL_MSK BITS(AES_CON_BL_POSS,AES_CON_BL_POSE) + +#define AES_CON_REV_POS 2U +#define AES_CON_REV_MSK BIT(AES_CON_REV_POS) + +#define AES_CON_MODE_POS 1U +#define AES_CON_MODE_MSK BIT(AES_CON_MODE_POS) + +#define AES_CON_START_POS 0U +#define AES_CON_START_MSK BIT(AES_CON_START_POS) + +/****************** Bit definition for AES_IER register ************************/ + +#define AES_IER_DECIE_POS 1U +#define AES_IER_DECIE_MSK BIT(AES_IER_DECIE_POS) + +#define AES_IER_ENCIE_POS 0U +#define AES_IER_ENCIE_MSK BIT(AES_IER_ENCIE_POS) + +/****************** Bit definition for AES_IDR register ************************/ + +#define AES_IDR_DECID_POS 1U +#define AES_IDR_DECID_MSK BIT(AES_IDR_DECID_POS) + +#define AES_IDR_ENCID_POS 0U +#define AES_IDR_ENCID_MSK BIT(AES_IDR_ENCID_POS) + +/****************** Bit definition for AES_IVS register ************************/ + +#define AES_IVS_DECIVS_POS 1U +#define AES_IVS_DECIVS_MSK BIT(AES_IVS_DECIVS_POS) + +#define AES_IVS_ENCIVS_POS 0U +#define AES_IVS_ENCIVS_MSK BIT(AES_IVS_ENCIVS_POS) + +/****************** Bit definition for AES_RIF register ************************/ + +#define AES_RIF_DECRIF_POS 1U +#define AES_RIF_DECRIF_MSK BIT(AES_RIF_DECRIF_POS) + +#define AES_RIF_ENCRIF_POS 0U +#define AES_RIF_ENCRIF_MSK BIT(AES_RIF_ENCRIF_POS) + +/****************** Bit definition for AES_IFM register ************************/ + +#define AES_IFM_DECIFM_POS 1U +#define AES_IFM_DECIFM_MSK BIT(AES_IFM_DECIFM_POS) + +#define AES_IFM_ENCIFM_POS 0U +#define AES_IFM_ENCIFM_MSK BIT(AES_IFM_ENCIFM_POS) + +/****************** Bit definition for AES_ICR register ************************/ + +#define AES_ICR_DECICR_POS 1U +#define AES_ICR_DECICR_MSK BIT(AES_ICR_DECICR_POS) + +#define AES_ICR_ENCICR_POS 0U +#define AES_ICR_ENCICR_MSK BIT(AES_ICR_ENCICR_POS) + +/****************** Bit definition for AES_DIO register ************************/ + +#define AES_DIO_DIO_POSS 0U +#define AES_DIO_DIO_POSE 31U +#define AES_DIO_DIO_MSK BITS(AES_DIO_DIO_POSS,AES_DIO_DIO_POSE) + +/****************** Bit definition for AES_KEY0 register ************************/ + +#define AES_KEY0_KEY0_POSS 0U +#define AES_KEY0_KEY0_POSE 31U +#define AES_KEY0_KEY0_MSK BITS(AES_KEY0_KEY0_POSS,AES_KEY0_KEY0_POSE) + +/****************** Bit definition for AES_KEY1 register ************************/ + +#define AES_KEY1_KEY1_POSS 0U +#define AES_KEY1_KEY1_POSE 31U +#define AES_KEY1_KEY1_MSK BITS(AES_KEY1_KEY1_POSS,AES_KEY1_KEY1_POSE) + +/****************** Bit definition for AES_KEY2 register ************************/ + +#define AES_KEY2_KEY2_POSS 0U +#define AES_KEY2_KEY2_POSE 31U +#define AES_KEY2_KEY2_MSK BITS(AES_KEY2_KEY2_POSS,AES_KEY2_KEY2_POSE) + +/****************** Bit definition for AES_KEY3 register ************************/ + +#define AES_KEY3_KEY3_POSS 0U +#define AES_KEY3_KEY3_POSE 31U +#define AES_KEY3_KEY3_MSK BITS(AES_KEY3_KEY3_POSS,AES_KEY3_KEY3_POSE) + +/****************** Bit definition for AES_IV0 register ************************/ + +#define AES_IV0_IV0_POSS 0U +#define AES_IV0_IV0_POSE 31U +#define AES_IV0_IV0_MSK BITS(AES_IV0_IV0_POSS,AES_IV0_IV0_POSE) + +/****************** Bit definition for AES_IV1 register ************************/ + +#define AES_IV1_IV1_POSS 0U +#define AES_IV1_IV1_POSE 31U +#define AES_IV1_IV1_MSK BITS(AES_IV1_IV1_POSS,AES_IV1_IV1_POSE) + +/****************** Bit definition for AES_IV2 register ************************/ + +#define AES_IV2_IV2_POSS 0U +#define AES_IV2_IV2_POSE 31U +#define AES_IV2_IV2_MSK BITS(AES_IV2_IV2_POSS,AES_IV2_IV2_POSE) + +/****************** Bit definition for AES_IV3 register ************************/ + +#define AES_IV3_IV3_POSS 0U +#define AES_IV3_IV3_POSE 31U +#define AES_IV3_IV3_MSK BITS(AES_IV3_IV3_POSS,AES_IV3_IV3_POSE) + +typedef struct +{ + __IO uint32_t CON; /* 0x000 AES_CON AES Control Register */ + __O uint32_t IER; /* 0x004 AES_IER AES Interrupt Enable Register */ + __O uint32_t IDR; /* 0x008 AES_IDR AES Interrupt Disable Register */ + __I uint32_t IVS; /* 0x00C AES_IVS AES Interrupt Valid Status Register */ + __I uint32_t RIF; /* 0x010 AES_RIF AES Raw Interrupt Flag Status Register */ + __I uint32_t IFM; /* 0x014 AES_IFM AES Interrupt Flag Masked Register */ + __O uint32_t ICR; /* 0x018 AES_ICR AES Interrupt Clear Register */ + __IO uint32_t DIO; /* 0x01C AES_DIO AES 128-bit Input/Output Data Register */ + __IO uint32_t KEY0; /* 0x020 AES_KEY0 AES 256-bit Keyword Register 0 */ + __IO uint32_t KEY1; /* 0x024 AES_KEY1 AES 256-bit Keyword Register 1 */ + __IO uint32_t KEY2; /* 0x028 AES_KEY2 AES 256-bit Keyword Register 2 */ + __IO uint32_t KEY3; /* 0x02C AES_KEY3 AES 256-bit Keyword Register 3 */ + uint32_t RESERVED0[4] ; + __IO uint32_t IV0; /* 0x040 AES_IV0 AES 128-bit Initial Vector Register 0 */ + __IO uint32_t IV1; /* 0x044 AES_IV1 AES 128-bit Initial Vector Register 1 */ + __IO uint32_t IV2; /* 0x048 AES_IV2 AES 128-bit Initial Vector Register 2 */ + __IO uint32_t IV3; /* 0x04C AES_IV3 AES 128-bit Initial Vector Register 3 */ +} AES_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_cmp.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_cmp.h new file mode 100644 index 0000000000000000000000000000000000000000..8b1f4e5de6c77fcc89d6e9209e7296175de09446 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_cmp.h @@ -0,0 +1,95 @@ +/** + ************************************************************************************** + * @file REG_CMP.h + * @brief CMP Head File + * + * @version V0.01 + * @data 12/3/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __CMP_H__ +#define __CMP_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for CMP_CON register ************************/ + +#define CMP_CON_REFON_POS 4U +#define CMP_CON_REFON_MSK BIT(CMP_CON_REFON_POS) + +#define CMP_CON_CMPON2_POS 1U +#define CMP_CON_CMPON2_MSK BIT(CMP_CON_CMPON2_POS) + +#define CMP_CON_CMPON1_POS 0U +#define CMP_CON_CMPON1_MSK BIT(CMP_CON_CMPON1_POS) + +/****************** Bit definition for CMP_CFG1 register ************************/ + +#define CMP_CFG1_RS_POSS 4U +#define CMP_CFG1_RS_POSE 5U +#define CMP_CFG1_RS_MSK BITS(CMP_CFG1_RS_POSS,CMP_CFG1_RS_POSE) + +#define CMP_CFG1_FEN_POS 3U +#define CMP_CFG1_FEN_MSK BIT(CMP_CFG1_FEN_POS) + +#define CMP_CFG1_PSEN_POS 2U +#define CMP_CFG1_PSEN_MSK BIT(CMP_CFG1_PSEN_POS) + +#define CMP_CFG1_INSEL_POS 1U +#define CMP_CFG1_INSEL_MSK BIT(CMP_CFG1_INSEL_POS) + +#define CMP_CFG1_IPSEL_POS 0U +#define CMP_CFG1_IPSEL_MSK BIT(CMP_CFG1_IPSEL_POS) + +/****************** Bit definition for CMP_CFG2 register ************************/ + +#define CMP_CFG2_RS_POSS 4U +#define CMP_CFG2_RS_POSE 5U +#define CMP_CFG2_RS_MSK BITS(CMP_CFG2_RS_POSS,CMP_CFG2_RS_POSE) + +#define CMP_CFG2_FEN_POS 3U +#define CMP_CFG2_FEN_MSK BIT(CMP_CFG1_FEN_POS) + +#define CMP_CFG2_PSEN_POS 2U +#define CMP_CFG2_PSEN_MSK BIT(CMP_CFG1_PSEN_POS) + +#define CMP_CFG2_INSEL_POS 1U +#define CMP_CFG2_INSEL_MSK BIT(CMP_CFG1_INSEL_POS) + +#define CMP_CFG2_IPSEL_POS 0U +#define CMP_CFG2_IPSEL_MSK BIT(CMP_CFG1_IPSEL_POS) + +/****************** Bit definition for CMP_RULT register ************************/ + +#define CMP_RULT_CMPO2_POS 1U +#define CMP_RULT_CMPO2_MSK BIT(CMP_RULT_CMPO2_POS) + +#define CMP_RULT_CMPO1_POS 0U +#define CMP_RULT_CMPO1_MSK BIT(CMP_RULT_CMPO1_POS) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t CFG1; + __IO uint32_t CFG2; + uint32_t RESERVED0[2] ; + __I uint32_t RULT; +} CMP_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_crc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..cdbb00b45c61c7d5d4e3e94bf1c28b67474583c7 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_crc.h @@ -0,0 +1,125 @@ +/** + ************************************************************************************** + * @file REG_CRC.h + * @brief CRC Head File + * + * @version V0.01 + * @data 11/16/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __CRC_H__ +#define __CRC_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for CRC_INIT register ************************/ + +#define CRC_INIT_INIT_POSS 0U +#define CRC_INIT_INIT_POSE 31U +#define CRC_INIT_INIT_MSK BITS(CRC_INIT_INIT_POSS,CRC_INIT_INIT_POSE) + +/****************** Bit definition for CRC_POLY register ************************/ + +#define CRC_POLY_POLY_POSS 0U +#define CRC_POLY_POLY_POSE 31U +#define CRC_POLY_POLY_MSK BITS(CRC_POLY_POLY_POSS,CRC_POLY_POLY_POSE) + +/****************** Bit definition for CRC_DATA register ************************/ + +#define CRC_DATA_DATA_POSS 0U +#define CRC_DATA_DATA_POSE 31U +#define CRC_DATA_DATA_MSK BITS(CRC_DATA_DATA_POSS,CRC_DATA_DATA_POSE) + +/****************** Bit definition for CRC_COMP register ************************/ + +#define CRC_COMP_COMP_POSS 0U +#define CRC_COMP_COMP_POSE 31U +#define CRC_COMP_COMP_MSK BITS(CRC_COMP_COMP_POSS,CRC_COMP_COMP_POSE) + +/****************** Bit definition for CRC_REMA register ************************/ + +#define CRC_REMA_REMA_POSS 0U +#define CRC_REMA_REMA_POSE 31U +#define CRC_REMA_REMA_MSK BITS(CRC_REMA_REMA_POSS,CRC_REMA_REMA_POSE) + +/****************** Bit definition for CRC_CON register ************************/ + +#define CRC_CON_DMA_POS 16U +#define CRC_CON_DMA_MSK BIT(CRC_CON_DMA_POS) + +#define CRC_CON_MSB_POS 12U +#define CRC_CON_MSB_MSK BIT(CRC_CON_MSB_POS) + +#define CRC_CON_REOUT_POS 10U +#define CRC_CON_REOUT_MSK BIT(CRC_CON_REOUT_POS) + +#define CRC_CON_REIN_POS 8U +#define CRC_CON_REIN_MSK BIT(CRC_CON_REIN_POS) + +#define CRC_CON_SIZE_POSS 4U +#define CRC_CON_SIZE_POSE 5U +#define CRC_CON_SIZE_MSK BITS(CRC_CON_SIZE_POSS,CRC_CON_SIZE_POSE) + +#define CRC_CON_MODE_POSS 2U +#define CRC_CON_MODE_POSE 3U +#define CRC_CON_MODE_MSK BITS(CRC_CON_MODE_POSS,CRC_CON_MODE_POSE) + +#define CRC_CON_RESET_POS 0U +#define CRC_CON_RESET_MSK BIT(CRC_CON_RESET_POS) + +/****************** Bit definition for CRC_DOUT register ************************/ + +#define CRC_DOUT_DOUT_POSS 0U +#define CRC_DOUT_DOUT_POSE 31U +#define CRC_DOUT_DOUT_MSK BITS(CRC_DOUT_DOUT_POSS,CRC_DOUT_DOUT_POSE) + +/****************** Bit definition for CRC_DOUT_XOR register ************************/ + +#define CRC_DOUT_XOR_DOUT_XOR_POSS 0U +#define CRC_DOUT_XOR_DOUT_XOR_POSE 31U +#define CRC_DOUT_XOR_DOUT_XOR_MSK BITS(CRC_DOUT_XOR_DOUT_XOR_POSS,CRC_DOUT_XOR_DOUT_XOR_POSE) + +/****************** Bit definition for CRC_STAT register ************************/ + +#define CRC_STAT_FAIL_POS 8U +#define CRC_STAT_FAIL_MSK BIT(CRC_STAT_FAIL_POS) + +#define CRC_STAT_EMPTY_POS 2U +#define CRC_STAT_EMPTY_MSK BIT(CRC_STAT_EMPTY_POS) + +#define CRC_STAT_BUSY_POS 1U +#define CRC_STAT_BUSY_MSK BIT(CRC_STAT_BUSY_POS) + +#define CRC_STAT_DONE_POS 0U +#define CRC_STAT_DONE_MSK BIT(CRC_STAT_DONE_POS) + +typedef struct +{ + __IO uint32_t INIT; /* 0x000 CRC_INIT CRC Iintial Value Register */ + __IO uint32_t POLY; /* 0x004 CRC_POLY CRC Polynomial Register */ + __IO uint32_t DATA; /* 0x008 CRC_DATA CRC Input Data Register */ + __IO uint32_t COMP; /* 0x00C CRC_COMP CRC Compare Data Register */ + __IO uint32_t REMA; /* 0x010 CRC_REMA CRC Remainder Register */ + __IO uint32_t CON; /* 0x014 CRC_CTRL CRC Control Register */ + __I uint32_t DOUT; /* 0x018 CRC_DOUT CRC Output Data Register */ + __I uint32_t DOUT_XOR; /* 0x01C CRC_DOUT_XOR CRC Output Data Register */ + __I uint32_t STAT; /* 0x020 CRC_STA CRC Status Register */ +} CRC_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dac.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dac.h new file mode 100644 index 0000000000000000000000000000000000000000..73a409e5eb2fd81d6006d211030ffc1fb265a6da --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dac.h @@ -0,0 +1,97 @@ +/** + ************************************************************************************** + * @file REG_DAC.h + * @brief DAC Head File + * + * @version V0.01 + * @data 1/14/2019 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __DAC_H__ +#define __DAC_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for DAC_CON register ************************/ + +#define DAC_CON_T_SEL_POSS 9U +#define DAC_CON_T_SEL_POSE 13U +#define DAC_CON_T_SEL_MSK BITS(DAC_CON_T_SEL_POSS,DAC_CON_T_SEL_POSE) + +#define DAC_CON_TRIEN_POS 8U +#define DAC_CON_TRIEN_MSK BIT(DAC_CON_TRIEN_POS) + +#define DAC_CON_MAMP_POSS 3U +#define DAC_CON_MAMP_POSE 6U +#define DAC_CON_MAMP_MSK BITS(DAC_CON_MAMP_POSS,DAC_CON_MAMP_POSE) + +#define DAC_CON_WAVE_POSS 1U +#define DAC_CON_WAVE_POSE 2U +#define DAC_CON_WAVE_MSK BITS(DAC_CON_WAVE_POSS,DAC_CON_WAVE_POSE) + +#define DAC_CON_INVREN_POS 0U +#define DAC_CON_INVREN_MSK BIT(DAC_CON_INVREN_POS) + +/****************** Bit definition for DAC_DIV register ************************/ + +#define DAC_DIV_DIV_VALUE_POSS 0U +#define DAC_DIV_DIV_VALUE_POSE 15U +#define DAC_DIV_DIV_VALUE_MSK BITS(DAC_DIV_DIV_VALUE_POSS,DAC_DIV_DIV_VALUE_POSE) + +/****************** Bit definition for DAC_STAT register ************************/ + +#define DAC_STAT_TX_FULL_POS 1U +#define DAC_STAT_TX_FULL_MSK BIT(DAC_STAT_TX_FULL_POS) + +#define DAC_STAT_BUSY_POS 0U +#define DAC_STAT_BUSY_MSK BIT(DAC_STAT_BUSY_POS) + +/****************** Bit definition for DAC_EN register ************************/ + +#define DAC_EN_DAC_EN_POS 0U +#define DAC_EN_DAC_EN_MSK BIT(DAC_EN_DAC_EN_POS) + +/****************** Bit definition for DAC_DMAC register ************************/ + +#define DAC_DMAC_TXDMAEN_POS 0U +#define DAC_DMAC_TXDMAEN_MSK BIT(DAC_DMAC_TXDMAEN_POS) + +/****************** Bit definition for DAC_TRIG register ************************/ + +#define DAC_TRIG_S_TRIG_POS 0U +#define DAC_TRIG_S_TRIG_MSK BIT(DAC_TRIG_S_TRIG_POS) + +/****************** Bit definition for DAC_DATA register ************************/ + +#define DAC_DATA_TXDATA_POSS 0U +#define DAC_DATA_TXDATA_POSE 11U +#define DAC_DATA_TXDATA_MSK BITS(DAC_DATA_TXDATA_POSS,DAC_DATA_TXDATA_POSE) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t DIV; + __I uint32_t STAT; + __IO uint32_t EN; + __IO uint32_t DMAC; + __O uint32_t TRIG; + __IO uint32_t DATA; +} DAC_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dma.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..bead8afcdb5e0180745897fda692a1b6b35ffae3 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_dma.h @@ -0,0 +1,825 @@ +/** + ************************************************************************************** + * @file REG_DMA.h + * @brief DMA Head File + * + * @version V0.01 + * @date 12/5/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __DMA_H__ +#define __DMA_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for DMA_IER register ************************/ + +#define DMA_IER_CH5TABIE_POS 11U +#define DMA_IER_CH5TABIE_MSK BIT(DMA_IER_CH5TABIE_POS) + +#define DMA_IER_CH5BTDIE_POS 10U +#define DMA_IER_CH5BTDIE_MSK BIT(DMA_IER_CH5BTDIE_POS) + +#define DMA_IER_CH4TABIE_POS 9U +#define DMA_IER_CH4TABIE_MSK BIT(DMA_IER_CH4TABIE_POS) + +#define DMA_IER_CH4BTDIE_POS 8U +#define DMA_IER_CH4BTDIE_MSK BIT(DMA_IER_CH4BTDIE_POS) + +#define DMA_IER_CH3TABIE_POS 7U +#define DMA_IER_CH3TABIE_MSK BIT(DMA_IER_CH3TABIE_POS) + +#define DMA_IER_CH3BTDIE_POS 6U +#define DMA_IER_CH3BTDIE_MSK BIT(DMA_IER_CH3BTDIE_POS) + +#define DMA_IER_CH2TABIE_POS 5U +#define DMA_IER_CH2TABIE_MSK BIT(DMA_IER_CH2TABIE_POS) + +#define DMA_IER_CH2BTDIE_POS 4U +#define DMA_IER_CH2BTDIE_MSK BIT(DMA_IER_CH2BTDIE_POS) + +#define DMA_IER_CH1TABIE_POS 3U +#define DMA_IER_CH1TABIE_MSK BIT(DMA_IER_CH1TABIE_POS) + +#define DMA_IER_CH1BTDIE_POS 2U +#define DMA_IER_CH1BTDIE_MSK BIT(DMA_IER_CH1BTDIE_POS) + +#define DMA_IER_CH0TABIE_POS 1U +#define DMA_IER_CH0TABIE_MSK BIT(DMA_IER_CH0TABIE_POS) + +#define DMA_IER_CH0BTDIE_POS 0U +#define DMA_IER_CH0BTDIE_MSK BIT(DMA_IER_CH0BTDIE_POS) + +/****************** Bit definition for DMA_IDR register ************************/ + +#define DMA_IDR_CH5TABID_POS 11U +#define DMA_IDR_CH5TABID_MSK BIT(DMA_IDR_CH5TABID_POS) + +#define DMA_IDR_CH5BTDID_POS 10U +#define DMA_IDR_CH5BTDID_MSK BIT(DMA_IDR_CH5BTDID_POS) + +#define DMA_IDR_CH4TABID_POS 9U +#define DMA_IDR_CH4TABID_MSK BIT(DMA_IDR_CH4TABID_POS) + +#define DMA_IDR_CH4BTDID_POS 8U +#define DMA_IDR_CH4BTDID_MSK BIT(DMA_IDR_CH4BTDID_POS) + +#define DMA_IDR_CH3TABID_POS 7U +#define DMA_IDR_CH3TABID_MSK BIT(DMA_IDR_CH3TABID_POS) + +#define DMA_IDR_CH3BTDID_POS 6U +#define DMA_IDR_CH3BTDID_MSK BIT(DMA_IDR_CH3BTDID_POS) + +#define DMA_IDR_CH2TABID_POS 5U +#define DMA_IDR_CH2TABID_MSK BIT(DMA_IDR_CH2TABID_POS) + +#define DMA_IDR_CH2BTDID_POS 4U +#define DMA_IDR_CH2BTDID_MSK BIT(DMA_IDR_CH2BTDID_POS) + +#define DMA_IDR_CH1TABID_POS 3U +#define DMA_IDR_CH1TABID_MSK BIT(DMA_IDR_CH1TABID_POS) + +#define DMA_IDR_CH1BTDID_POS 2U +#define DMA_IDR_CH1BTDID_MSK BIT(DMA_IDR_CH1BTDID_POS) + +#define DMA_IDR_CH0TABID_POS 1U +#define DMA_IDR_CH0TABID_MSK BIT(DMA_IDR_CH0TABID_POS) + +#define DMA_IDR_CH0BTDID_POS 0U +#define DMA_IDR_CH0BTDID_MSK BIT(DMA_IDR_CH0BTDID_POS) + +/****************** Bit definition for DMA_IVS register ************************/ + +#define DMA_IVS_CH5TABIVS_POS 11U +#define DMA_IVS_CH5TABIVS_MSK BIT(DMA_IVS_CH5TABIVS_POS) + +#define DMA_IVS_CH5BTDIVS_POS 10U +#define DMA_IVS_CH5BTDIVS_MSK BIT(DMA_IVS_CH5BTDIVS_POS) + +#define DMA_IVS_CH4TABIVS_POS 9U +#define DMA_IVS_CH4TABIVS_MSK BIT(DMA_IVS_CH4TABIVS_POS) + +#define DMA_IVS_CH4BTDIVS_POS 8U +#define DMA_IVS_CH4BTDIVS_MSK BIT(DMA_IVS_CH4BTDIVS_POS) + +#define DMA_IVS_CH3TABIVS_POS 7U +#define DMA_IVS_CH3TABIVS_MSK BIT(DMA_IVS_CH3TABIVS_POS) + +#define DMA_IVS_CH3BTDIVS_POS 6U +#define DMA_IVS_CH3BTDIVS_MSK BIT(DMA_IVS_CH3BTDIVS_POS) + +#define DMA_IVS_CH2TABIVS_POS 5U +#define DMA_IVS_CH2TABIVS_MSK BIT(DMA_IVS_CH2TABIVS_POS) + +#define DMA_IVS_CH2BTDIVS_POS 4U +#define DMA_IVS_CH2BTDIVS_MSK BIT(DMA_IVS_CH2BTDIVS_POS) + +#define DMA_IVS_CH1TABIVS_POS 3U +#define DMA_IVS_CH1TABIVS_MSK BIT(DMA_IVS_CH1TABIVS_POS) + +#define DMA_IVS_CH1BTDIVS_POS 2U +#define DMA_IVS_CH1BTDIVS_MSK BIT(DMA_IVS_CH1BTDIVS_POS) + +#define DMA_IVS_CH0TABIVS_POS 1U +#define DMA_IVS_CH0TABIVS_MSK BIT(DMA_IVS_CH0TABIVS_POS) + +#define DMA_IVS_CH0BTDIVS_POS 0U +#define DMA_IVS_CH0BTDIVS_MSK BIT(DMA_IVS_CH0BTDIVS_POS) + +/****************** Bit definition for DMA_RIF register ************************/ + +#define DMA_RIF_CH5TABRIF_POS 11U +#define DMA_RIF_CH5TABRIF_MSK BIT(DMA_RIF_CH5TABRIF_POS) + +#define DMA_RIF_CH5BTDRIF_POS 10U +#define DMA_RIF_CH5BTDRIF_MSK BIT(DMA_RIF_CH5BTDRIF_POS) + +#define DMA_RIF_CH4TABRIF_POS 9U +#define DMA_RIF_CH4TABRIF_MSK BIT(DMA_RIF_CH4TABRIF_POS) + +#define DMA_RIF_CH4BTDRIF_POS 8U +#define DMA_RIF_CH4BTDRIF_MSK BIT(DMA_RIF_CH4BTDRIF_POS) + +#define DMA_RIF_CH3TABRIF_POS 7U +#define DMA_RIF_CH3TABRIF_MSK BIT(DMA_RIF_CH3TABRIF_POS) + +#define DMA_RIF_CH3BTDRIF_POS 6U +#define DMA_RIF_CH3BTDRIF_MSK BIT(DMA_RIF_CH3BTDRIF_POS) + +#define DMA_RIF_CH2TABRIF_POS 5U +#define DMA_RIF_CH2TABRIF_MSK BIT(DMA_RIF_CH2TABRIF_POS) + +#define DMA_RIF_CH2BTDRIF_POS 4U +#define DMA_RIF_CH2BTDRIF_MSK BIT(DMA_RIF_CH2BTDRIF_POS) + +#define DMA_RIF_CH1TABRIF_POS 3U +#define DMA_RIF_CH1TABRIF_MSK BIT(DMA_RIF_CH1TABRIF_POS) + +#define DMA_RIF_CH1BTDRIF_POS 2U +#define DMA_RIF_CH1BTDRIF_MSK BIT(DMA_RIF_CH1BTDRIF_POS) + +#define DMA_RIF_CH0TABRIF_POS 1U +#define DMA_RIF_CH0TABRIF_MSK BIT(DMA_RIF_CH0TABRIF_POS) + +#define DMA_RIF_CH0BTDRIF_POS 0U +#define DMA_RIF_CH0BTDRIF_MSK BIT(DMA_RIF_CH0BTDRIF_POS) + +/****************** Bit definition for DMA_IFM register ************************/ + +#define DMA_IFM_CH5TABIFM_POS 11U +#define DMA_IFM_CH5TABIFM_MSK BIT(DMA_IFM_CH5TABIFM_POS) + +#define DMA_IFM_CH5BTDIFM_POS 10U +#define DMA_IFM_CH5BTDIFM_MSK BIT(DMA_IFM_CH5BTDIFM_POS) + +#define DMA_IFM_CH4TABIFM_POS 9U +#define DMA_IFM_CH4TABIFM_MSK BIT(DMA_IFM_CH4TABIFM_POS) + +#define DMA_IFM_CH4BTDIFM_POS 8U +#define DMA_IFM_CH4BTDIFM_MSK BIT(DMA_IFM_CH4BTDIFM_POS) + +#define DMA_IFM_CH3TABIFM_POS 7U +#define DMA_IFM_CH3TABIFM_MSK BIT(DMA_IFM_CH3TABIFM_POS) + +#define DMA_IFM_CH3BTDIFM_POS 6U +#define DMA_IFM_CH3BTDIFM_MSK BIT(DMA_IFM_CH3BTDIFM_POS) + +#define DMA_IFM_CH2TABIFM_POS 5U +#define DMA_IFM_CH2TABIFM_MSK BIT(DMA_IFM_CH2TABIFM_POS) + +#define DMA_IFM_CH2BTDIFM_POS 4U +#define DMA_IFM_CH2BTDIFM_MSK BIT(DMA_IFM_CH2BTDIFM_POS) + +#define DMA_IFM_CH1TABIFM_POS 3U +#define DMA_IFM_CH1TABIFM_MSK BIT(DMA_IFM_CH1TABIFM_POS) + +#define DMA_IFM_CH1BTDIFM_POS 2U +#define DMA_IFM_CH1BTDIFM_MSK BIT(DMA_IFM_CH1BTDIFM_POS) + +#define DMA_IFM_CH0TABIFM_POS 1U +#define DMA_IFM_CH0TABIFM_MSK BIT(DMA_IFM_CH0TABIFM_POS) + +#define DMA_IFM_CH0BTDIFM_POS 0U +#define DMA_IFM_CH0BTDIFM_MSK BIT(DMA_IFM_CH0BTDIFM_POS) + +/****************** Bit definition for DMA_ICR register ************************/ + +#define DMA_ICR_CH5TABICR_POS 11U +#define DMA_ICR_CH5TABICR_MSK BIT(DMA_ICR_CH5TABICR_POS) + +#define DMA_ICR_CH5BTDICR_POS 10U +#define DMA_ICR_CH5BTDICR_MSK BIT(DMA_ICR_CH5BTDICR_POS) + +#define DMA_ICR_CH4TABICR_POS 9U +#define DMA_ICR_CH4TABICR_MSK BIT(DMA_ICR_CH4TABICR_POS) + +#define DMA_ICR_CH4BTDICR_POS 8U +#define DMA_ICR_CH4BTDICR_MSK BIT(DMA_ICR_CH4BTDICR_POS) + +#define DMA_ICR_CH3TABICR_POS 7U +#define DMA_ICR_CH3TABICR_MSK BIT(DMA_ICR_CH3TABICR_POS) + +#define DMA_ICR_CH3BTDICR_POS 6U +#define DMA_ICR_CH3BTDICR_MSK BIT(DMA_ICR_CH3BTDICR_POS) + +#define DMA_ICR_CH2TABICR_POS 5U +#define DMA_ICR_CH2TABICR_MSK BIT(DMA_ICR_CH2TABICR_POS) + +#define DMA_ICR_CH2BTDICR_POS 4U +#define DMA_ICR_CH2BTDICR_MSK BIT(DMA_ICR_CH2BTDICR_POS) + +#define DMA_ICR_CH1TABICR_POS 3U +#define DMA_ICR_CH1TABICR_MSK BIT(DMA_ICR_CH1TABICR_POS) + +#define DMA_ICR_CH1BTDICR_POS 2U +#define DMA_ICR_CH1BTDICR_MSK BIT(DMA_ICR_CH1BTDICR_POS) + +#define DMA_ICR_CH0TABICR_POS 1U +#define DMA_ICR_CH0TABICR_MSK BIT(DMA_ICR_CH0TABICR_POS) + +#define DMA_ICR_CH0BTDICR_POS 0U +#define DMA_ICR_CH0BTDICR_MSK BIT(DMA_ICR_CH0BTDICR_POS) + +/****************** Bit definition for DMA_EMSG register ************************/ + +#define DMA_EMSG_CH5PFSER_POS 23U +#define DMA_EMSG_CH5PFSER_MSK BIT(DMA_EMSG_CH5PFSER_POS) + +#define DMA_EMSG_CH5PFOV_POS 22U +#define DMA_EMSG_CH5PFOV_MSK BIT(DMA_EMSG_CH5PFOV_POS) + +#define DMA_EMSG_CH5SETBUER_POS 21U +#define DMA_EMSG_CH5SETBUER_MSK BIT(DMA_EMSG_CH5SETBUER_POS) + +#define DMA_EMSG_CH5SETBCER_POS 20U +#define DMA_EMSG_CH5SETBCER_MSK BIT(DMA_EMSG_CH5SETBCER_POS) + +#define DMA_EMSG_CH4PFSER_POS 19U +#define DMA_EMSG_CH4PFSER_MSK BIT(DMA_EMSG_CH4PFSER_POS) + +#define DMA_EMSG_CH4PFOV_POS 18U +#define DMA_EMSG_CH4PFOV_MSK BIT(DMA_EMSG_CH4PFOV_POS) + +#define DMA_EMSG_CH4SETBUER_POS 17U +#define DMA_EMSG_CH4SETBUER_MSK BIT(DMA_EMSG_CH4SETBUER_POS) + +#define DMA_EMSG_CH4SETBCER_POS 16U +#define DMA_EMSG_CH4SETBCER_MSK BIT(DMA_EMSG_CH4SETBCER_POS) + +#define DMA_EMSG_CH3PFSER_POS 15U +#define DMA_EMSG_CH3PFSER_MSK BIT(DMA_EMSG_CH3PFSER_POS) + +#define DMA_EMSG_CH3PFOV_POS 14U +#define DMA_EMSG_CH3PFOV_MSK BIT(DMA_EMSG_CH3PFOV_POS) + +#define DMA_EMSG_CH3SETBUER_POS 13U +#define DMA_EMSG_CH3SETBUER_MSK BIT(DMA_EMSG_CH3SETBUER_POS) + +#define DMA_EMSG_CH3SETBCER_POS 12U +#define DMA_EMSG_CH3SETBCER_MSK BIT(DMA_EMSG_CH3SETBCER_POS) + +#define DMA_EMSG_CH2PFSER_POS 11U +#define DMA_EMSG_CH2PFSER_MSK BIT(DMA_EMSG_CH2PFSER_POS) + +#define DMA_EMSG_CH2PFOV_POS 10U +#define DMA_EMSG_CH2PFOV_MSK BIT(DMA_EMSG_CH2PFOV_POS) + +#define DMA_EMSG_CH2SETBUER_POS 9U +#define DMA_EMSG_CH2SETBUER_MSK BIT(DMA_EMSG_CH2SETBUER_POS) + +#define DMA_EMSG_CH2SETBCER_POS 8U +#define DMA_EMSG_CH2SETBCER_MSK BIT(DMA_EMSG_CH2SETBCER_POS) + +#define DMA_EMSG_CH1PFSER_POS 7U +#define DMA_EMSG_CH1PFSER_MSK BIT(DMA_EMSG_CH1PFSER_POS) + +#define DMA_EMSG_CH1PFOV_POS 6U +#define DMA_EMSG_CH1PFOV_MSK BIT(DMA_EMSG_CH1PFOV_POS) + +#define DMA_EMSG_CH1SETBUER_POS 5U +#define DMA_EMSG_CH1SETBUER_MSK BIT(DMA_EMSG_CH1SETBUER_POS) + +#define DMA_EMSG_CH1SETBCER_POS 4U +#define DMA_EMSG_CH1SETBCER_MSK BIT(DMA_EMSG_CH1SETBCER_POS) + +#define DMA_EMSG_CH0PFSER_POS 3U +#define DMA_EMSG_CH0PFSER_MSK BIT(DMA_EMSG_CH0PFSER_POS) + +#define DMA_EMSG_CH0PFOV_POS 2U +#define DMA_EMSG_CH0PFOV_MSK BIT(DMA_EMSG_CH0PFOV_POS) + +#define DMA_EMSG_CH0SETBUER_POS 1U +#define DMA_EMSG_CH0SETBUER_MSK BIT(DMA_EMSG_CH0SETBUER_POS) + +#define DMA_EMSG_CH0SETBCER_POS 0U +#define DMA_EMSG_CH0SETBCER_MSK BIT(DMA_EMSG_CH0SETBCER_POS) + +/****************** Bit definition for DMA_CSR0 register ************************/ + +#define DMA_CSR0_DINCOS_POS 30U +#define DMA_CSR0_DINCOS_MSK BIT(DMA_CSR0_DINCOS_POS) + +#define DMA_CSR0_DBUSEL_POSS 27U +#define DMA_CSR0_DBUSEL_POSE 29U +#define DMA_CSR0_DBUSEL_MSK BITS(DMA_CSR0_DBUSEL_POSS,DMA_CSR0_DBUSEL_POSE) + +#define DMA_CSR0_DDWSEL_POSS 25U +#define DMA_CSR0_DDWSEL_POSE 26U +#define DMA_CSR0_DDWSEL_MSK BITS(DMA_CSR0_DDWSEL_POSS,DMA_CSR0_DDWSEL_POSE) + +#define DMA_CSR0_DINC_POS 24U +#define DMA_CSR0_DINC_MSK BIT(DMA_CSR0_DINC_POS) + +#define DMA_CSR0_SINCOS_POS 22U +#define DMA_CSR0_SINCOS_MSK BIT(DMA_CSR0_SINCOS_POS) + +#define DMA_CSR0_SBUSEL_POSS 19U +#define DMA_CSR0_SBUSEL_POSE 21U +#define DMA_CSR0_SBUSEL_MSK BITS(DMA_CSR0_SBUSEL_POSS,DMA_CSR0_SBUSEL_POSE) + +#define DMA_CSR0_SDWSEL_POSS 17U +#define DMA_CSR0_SDWSEL_POSE 18U +#define DMA_CSR0_SDWSEL_MSK BITS(DMA_CSR0_SDWSEL_POSS,DMA_CSR0_SDWSEL_POSE) + +#define DMA_CSR0_SINC_POS 16U +#define DMA_CSR0_SINC_MSK BIT(DMA_CSR0_SINC_POS) + +#define DMA_CSR0_PHSS_POSS 9U +#define DMA_CSR0_PHSS_POSE 15U +#define DMA_CSR0_PHSS_MSK BITS(DMA_CSR0_PHSS_POSS,DMA_CSR0_PHSS_POSE) + +#define DMA_CSR0_CHPRI_POSS 6U +#define DMA_CSR0_CHPRI_POSE 8U +#define DMA_CSR0_CHPRI_MSK BITS(DMA_CSR0_CHPRI_POSS,DMA_CSR0_CHPRI_POSE) + +#define DMA_CSR0_MODESEL_POSS 4U +#define DMA_CSR0_MODESEL_POSE 5U +#define DMA_CSR0_MODESEL_MSK BITS(DMA_CSR0_MODESEL_POSS,DMA_CSR0_MODESEL_POSE) + +#define DMA_CSR0_DIRMDEN_POS 3U +#define DMA_CSR0_DIRMDEN_MSK BIT(DMA_CSR0_DIRMDEN_POS) + +#define DMA_CSR0_PFCTRL_POS 2U +#define DMA_CSR0_PFCTRL_MSK BIT(DMA_CSR0_PFCTRL_POS) + +#define DMA_CSR0_CIRC_POS 1U +#define DMA_CSR0_CIRC_MSK BIT(DMA_CSR0_CIRC_POS) + +#define DMA_CSR0_CHEN_POS 0U +#define DMA_CSR0_CHEN_MSK BIT(DMA_CSR0_CHEN_POS) + +/****************** Bit definition for DMA_SAR0 register ************************/ + +#define DMA_SAR0_SAR_POSS 0U +#define DMA_SAR0_SAR_POSE 31U +#define DMA_SAR0_SAR_MSK BITS(DMA_SAR0_SAR_POSS,DMA_SAR0_SAR_POSE) + +/****************** Bit definition for DMA_DAR0 register ************************/ + +#define DMA_DAR0_DAR_POSS 0U +#define DMA_DAR0_DAR_POSE 31U +#define DMA_DAR0_DAR_MSK BITS(DMA_DAR0_DAR_POSS,DMA_DAR0_DAR_POSE) + +/****************** Bit definition for DMA_BCR0 register ************************/ + +#define DMA_BCR0_CBCR_POSS 16U +#define DMA_BCR0_CBCR_POSE 31U +#define DMA_BCR0_CBCR_MSK BITS(DMA_BCR0_CBCR_POSS,DMA_BCR0_CBCR_POSE) + +#define DMA_BCR0_BCR_POSS 0U +#define DMA_BCR0_BCR_POSE 15U +#define DMA_BCR0_BCR_MSK BITS(DMA_BCR0_BCR_POSS,DMA_BCR0_BCR_POSE) + +/****************** Bit definition for DMA_CSR1 register ************************/ + +#define DMA_CSR1_DINCOS_POS 30U +#define DMA_CSR1_DINCOS_MSK BIT(DMA_CSR1_DINCOS_POS) + +#define DMA_CSR1_DBUSEL_POSS 27U +#define DMA_CSR1_DBUSEL_POSE 29U +#define DMA_CSR1_DBUSEL_MSK BITS(DMA_CSR1_DBUSEL_POSS,DMA_CSR1_DBUSEL_POSE) + +#define DMA_CSR1_DDWSEL_POSS 25U +#define DMA_CSR1_DDWSEL_POSE 26U +#define DMA_CSR1_DDWSEL_MSK BITS(DMA_CSR1_DDWSEL_POSS,DMA_CSR1_DDWSEL_POSE) + +#define DMA_CSR1_DINC_POS 24U +#define DMA_CSR1_DINC_MSK BIT(DMA_CSR1_DINC_POS) + +#define DMA_CSR1_SINCOS_POS 22U +#define DMA_CSR1_SINCOS_MSK BIT(DMA_CSR1_SINCOS_POS) + +#define DMA_CSR1_SBUSEL_POSS 19U +#define DMA_CSR1_SBUSEL_POSE 21U +#define DMA_CSR1_SBUSEL_MSK BITS(DMA_CSR1_SBUSEL_POSS,DMA_CSR1_SBUSEL_POSE) + +#define DMA_CSR1_SDWSEL_POSS 17U +#define DMA_CSR1_SDWSEL_POSE 18U +#define DMA_CSR1_SDWSEL_MSK BITS(DMA_CSR1_SDWSEL_POSS,DMA_CSR1_SDWSEL_POSE) + +#define DMA_CSR1_SINC_POS 16U +#define DMA_CSR1_SINC_MSK BIT(DMA_CSR1_SINC_POS) + +#define DMA_CSR1_PHSS_POSS 9U +#define DMA_CSR1_PHSS_POSE 15U +#define DMA_CSR1_PHSS_MSK BITS(DMA_CSR1_PHSS_POSS,DMA_CSR1_PHSS_POSE) + +#define DMA_CSR1_CHPRI_POSS 6U +#define DMA_CSR1_CHPRI_POSE 8U +#define DMA_CSR1_CHPRI_MSK BITS(DMA_CSR1_CHPRI_POSS,DMA_CSR1_CHPRI_POSE) + +#define DMA_CSR1_MODESEL_POSS 4U +#define DMA_CSR1_MODESEL_POSE 5U +#define DMA_CSR1_MODESEL_MSK BITS(DMA_CSR1_MODESEL_POSS,DMA_CSR1_MODESEL_POSE) + +#define DMA_CSR1_DIRMDEN_POS 3U +#define DMA_CSR1_DIRMDEN_MSK BIT(DMA_CSR1_DIRMDEN_POS) + +#define DMA_CSR1_PFCTRL_POS 2U +#define DMA_CSR1_PFCTRL_MSK BIT(DMA_CSR1_PFCTRL_POS) + +#define DMA_CSR1_CIRC_POS 1U +#define DMA_CSR1_CIRC_MSK BIT(DMA_CSR1_CIRC_POS) + +#define DMA_CSR1_CHEN_POS 0U +#define DMA_CSR1_CHEN_MSK BIT(DMA_CSR1_CHEN_POS) + +/****************** Bit definition for DMA_SAR1 register ************************/ + +#define DMA_SAR1_SAR_POSS 0U +#define DMA_SAR1_SAR_POSE 31U +#define DMA_SAR1_SAR_MSK BITS(DMA_SAR1_SAR_POSS,DMA_SAR1_SAR_POSE) + +/****************** Bit definition for DMA_DAR1 register ************************/ + +#define DMA_DAR1_DAR_POSS 0U +#define DMA_DAR1_DAR_POSE 31U +#define DMA_DAR1_DAR_MSK BITS(DMA_DAR1_DAR_POSS,DMA_DAR1_DAR_POSE) + +/****************** Bit definition for DMA_BCR1 register ************************/ + +#define DMA_BCR1_CBCR_POSS 16U +#define DMA_BCR1_CBCR_POSE 31U +#define DMA_BCR1_CBCR_MSK BITS(DMA_BCR1_CBCR_POSS,DMA_BCR1_CBCR_POSE) + +#define DMA_BCR1_BCR_POSS 0U +#define DMA_BCR1_BCR_POSE 15U +#define DMA_BCR1_BCR_MSK BITS(DMA_BCR1_BCR_POSS,DMA_BCR1_BCR_POSE) + +/****************** Bit definition for DMA_CSR2 register ************************/ + +#define DMA_CSR2_DINCOS_POS 30U +#define DMA_CSR2_DINCOS_MSK BIT(DMA_CSR2_DINCOS_POS) + +#define DMA_CSR2_DBUSEL_POSS 27U +#define DMA_CSR2_DBUSEL_POSE 29U +#define DMA_CSR2_DBUSEL_MSK BITS(DMA_CSR2_DBUSEL_POSS,DMA_CSR2_DBUSEL_POSE) + +#define DMA_CSR2_DDWSEL_POSS 25U +#define DMA_CSR2_DDWSEL_POSE 26U +#define DMA_CSR2_DDWSEL_MSK BITS(DMA_CSR2_DDWSEL_POSS,DMA_CSR2_DDWSEL_POSE) + +#define DMA_CSR2_DINC_POS 24U +#define DMA_CSR2_DINC_MSK BIT(DMA_CSR2_DINC_POS) + +#define DMA_CSR2_SINCOS_POS 22U +#define DMA_CSR2_SINCOS_MSK BIT(DMA_CSR2_SINCOS_POS) + +#define DMA_CSR2_SBUSEL_POSS 19U +#define DMA_CSR2_SBUSEL_POSE 21U +#define DMA_CSR2_SBUSEL_MSK BITS(DMA_CSR2_SBUSEL_POSS,DMA_CSR2_SBUSEL_POSE) + +#define DMA_CSR2_SDWSEL_POSS 17U +#define DMA_CSR2_SDWSEL_POSE 18U +#define DMA_CSR2_SDWSEL_MSK BITS(DMA_CSR2_SDWSEL_POSS,DMA_CSR2_SDWSEL_POSE) + +#define DMA_CSR2_SINC_POS 16U +#define DMA_CSR2_SINC_MSK BIT(DMA_CSR2_SINC_POS) + +#define DMA_CSR2_PHSS_POSS 9U +#define DMA_CSR2_PHSS_POSE 15U +#define DMA_CSR2_PHSS_MSK BITS(DMA_CSR2_PHSS_POSS,DMA_CSR2_PHSS_POSE) + +#define DMA_CSR2_CHPRI_POSS 6U +#define DMA_CSR2_CHPRI_POSE 8U +#define DMA_CSR2_CHPRI_MSK BITS(DMA_CSR2_CHPRI_POSS,DMA_CSR2_CHPRI_POSE) + +#define DMA_CSR2_MODESEL_POSS 4U +#define DMA_CSR2_MODESEL_POSE 5U +#define DMA_CSR2_MODESEL_MSK BITS(DMA_CSR2_MODESEL_POSS,DMA_CSR2_MODESEL_POSE) + +#define DMA_CSR2_DIRMDEN_POS 3U +#define DMA_CSR2_DIRMDEN_MSK BIT(DMA_CSR2_DIRMDEN_POS) + +#define DMA_CSR2_PFCTRL_POS 2U +#define DMA_CSR2_PFCTRL_MSK BIT(DMA_CSR2_PFCTRL_POS) + +#define DMA_CSR2_CIRC_POS 1U +#define DMA_CSR2_CIRC_MSK BIT(DMA_CSR2_CIRC_POS) + +#define DMA_CSR2_CHEN_POS 0U +#define DMA_CSR2_CHEN_MSK BIT(DMA_CSR2_CHEN_POS) + +/****************** Bit definition for DMA_SAR2 register ************************/ + +#define DMA_SAR2_SAR_POSS 0U +#define DMA_SAR2_SAR_POSE 31U +#define DMA_SAR2_SAR_MSK BITS(DMA_SAR2_SAR_POSS,DMA_SAR2_SAR_POSE) + +/****************** Bit definition for DMA_DAR2 register ************************/ + +#define DMA_DAR2_DAR_POSS 0U +#define DMA_DAR2_DAR_POSE 31U +#define DMA_DAR2_DAR_MSK BITS(DMA_DAR2_DAR_POSS,DMA_DAR2_DAR_POSE) + +/****************** Bit definition for DMA_BCR2 register ************************/ + +#define DMA_BCR2_CBCR_POSS 16U +#define DMA_BCR2_CBCR_POSE 31U +#define DMA_BCR2_CBCR_MSK BITS(DMA_BCR2_CBCR_POSS,DMA_BCR2_CBCR_POSE) + +#define DMA_BCR2_BCR_POSS 0U +#define DMA_BCR2_BCR_POSE 15U +#define DMA_BCR2_BCR_MSK BITS(DMA_BCR2_BCR_POSS,DMA_BCR2_BCR_POSE) + +/****************** Bit definition for DMA_CSR3 register ************************/ + +#define DMA_CSR3_DINCOS_POS 30U +#define DMA_CSR3_DINCOS_MSK BIT(DMA_CSR3_DINCOS_POS) + +#define DMA_CSR3_DBUSEL_POSS 27U +#define DMA_CSR3_DBUSEL_POSE 29U +#define DMA_CSR3_DBUSEL_MSK BITS(DMA_CSR3_DBUSEL_POSS,DMA_CSR3_DBUSEL_POSE) + +#define DMA_CSR3_DDWSEL_POSS 25U +#define DMA_CSR3_DDWSEL_POSE 26U +#define DMA_CSR3_DDWSEL_MSK BITS(DMA_CSR3_DDWSEL_POSS,DMA_CSR3_DDWSEL_POSE) + +#define DMA_CSR3_DINC_POS 24U +#define DMA_CSR3_DINC_MSK BIT(DMA_CSR3_DINC_POS) + +#define DMA_CSR3_SINCOS_POS 22U +#define DMA_CSR3_SINCOS_MSK BIT(DMA_CSR3_SINCOS_POS) + +#define DMA_CSR3_SBUSEL_POSS 19U +#define DMA_CSR3_SBUSEL_POSE 21U +#define DMA_CSR3_SBUSEL_MSK BITS(DMA_CSR3_SBUSEL_POSS,DMA_CSR3_SBUSEL_POSE) + +#define DMA_CSR3_SDWSEL_POSS 17U +#define DMA_CSR3_SDWSEL_POSE 18U +#define DMA_CSR3_SDWSEL_MSK BITS(DMA_CSR3_SDWSEL_POSS,DMA_CSR3_SDWSEL_POSE) + +#define DMA_CSR3_SINC_POS 16U +#define DMA_CSR3_SINC_MSK BIT(DMA_CSR3_SINC_POS) + +#define DMA_CSR3_PHSS_POSS 9U +#define DMA_CSR3_PHSS_POSE 15U +#define DMA_CSR3_PHSS_MSK BITS(DMA_CSR3_PHSS_POSS,DMA_CSR3_PHSS_POSE) + +#define DMA_CSR3_CHPRI_POSS 6U +#define DMA_CSR3_CHPRI_POSE 8U +#define DMA_CSR3_CHPRI_MSK BITS(DMA_CSR3_CHPRI_POSS,DMA_CSR3_CHPRI_POSE) + +#define DMA_CSR3_MODESEL_POSS 4U +#define DMA_CSR3_MODESEL_POSE 5U +#define DMA_CSR3_MODESEL_MSK BITS(DMA_CSR3_MODESEL_POSS,DMA_CSR3_MODESEL_POSE) + +#define DMA_CSR3_DIRMDEN_POS 3U +#define DMA_CSR3_DIRMDEN_MSK BIT(DMA_CSR3_DIRMDEN_POS) + +#define DMA_CSR3_PFCTRL_POS 2U +#define DMA_CSR3_PFCTRL_MSK BIT(DMA_CSR3_PFCTRL_POS) + +#define DMA_CSR3_CIRC_POS 1U +#define DMA_CSR3_CIRC_MSK BIT(DMA_CSR3_CIRC_POS) + +#define DMA_CSR3_CHEN_POS 0U +#define DMA_CSR3_CHEN_MSK BIT(DMA_CSR3_CHEN_POS) + +/****************** Bit definition for DMA_SAR3 register ************************/ + +#define DMA_SAR3_SAR_POSS 0U +#define DMA_SAR3_SAR_POSE 31U +#define DMA_SAR3_SAR_MSK BITS(DMA_SAR3_SAR_POSS,DMA_SAR3_SAR_POSE) + +/****************** Bit definition for DMA_DAR3 register ************************/ + +#define DMA_DAR3_DAR_POSS 0U +#define DMA_DAR3_DAR_POSE 31U +#define DMA_DAR3_DAR_MSK BITS(DMA_DAR3_DAR_POSS,DMA_DAR3_DAR_POSE) + +/****************** Bit definition for DMA_BCR3 register ************************/ + +#define DMA_BCR3_CBCR_POSS 16U +#define DMA_BCR3_CBCR_POSE 31U +#define DMA_BCR3_CBCR_MSK BITS(DMA_BCR3_CBCR_POSS,DMA_BCR3_CBCR_POSE) + +#define DMA_BCR3_BCR_POSS 0U +#define DMA_BCR3_BCR_POSE 15U +#define DMA_BCR3_BCR_MSK BITS(DMA_BCR3_BCR_POSS,DMA_BCR3_BCR_POSE) + +/****************** Bit definition for DMA_CSR4 register ************************/ + +#define DMA_CSR4_DINCOS_POS 30U +#define DMA_CSR4_DINCOS_MSK BIT(DMA_CSR4_DINCOS_POS) + +#define DMA_CSR4_DBUSEL_POSS 27U +#define DMA_CSR4_DBUSEL_POSE 29U +#define DMA_CSR4_DBUSEL_MSK BITS(DMA_CSR4_DBUSEL_POSS,DMA_CSR4_DBUSEL_POSE) + +#define DMA_CSR4_DDWSEL_POSS 25U +#define DMA_CSR4_DDWSEL_POSE 26U +#define DMA_CSR4_DDWSEL_MSK BITS(DMA_CSR4_DDWSEL_POSS,DMA_CSR4_DDWSEL_POSE) + +#define DMA_CSR4_DINC_POS 24U +#define DMA_CSR4_DINC_MSK BIT(DMA_CSR4_DINC_POS) + +#define DMA_CSR4_SINCOS_POS 22U +#define DMA_CSR4_SINCOS_MSK BIT(DMA_CSR4_SINCOS_POS) + +#define DMA_CSR4_SBUSEL_POSS 19U +#define DMA_CSR4_SBUSEL_POSE 21U +#define DMA_CSR4_SBUSEL_MSK BITS(DMA_CSR4_SBUSEL_POSS,DMA_CSR4_SBUSEL_POSE) + +#define DMA_CSR4_SDWSEL_POSS 17U +#define DMA_CSR4_SDWSEL_POSE 18U +#define DMA_CSR4_SDWSEL_MSK BITS(DMA_CSR4_SDWSEL_POSS,DMA_CSR4_SDWSEL_POSE) + +#define DMA_CSR4_SINC_POS 16U +#define DMA_CSR4_SINC_MSK BIT(DMA_CSR4_SINC_POS) + +#define DMA_CSR4_PHSS_POSS 9U +#define DMA_CSR4_PHSS_POSE 15U +#define DMA_CSR4_PHSS_MSK BITS(DMA_CSR4_PHSS_POSS,DMA_CSR4_PHSS_POSE) + +#define DMA_CSR4_CHPRI_POSS 6U +#define DMA_CSR4_CHPRI_POSE 8U +#define DMA_CSR4_CHPRI_MSK BITS(DMA_CSR4_CHPRI_POSS,DMA_CSR4_CHPRI_POSE) + +#define DMA_CSR4_MODESEL_POSS 4U +#define DMA_CSR4_MODESEL_POSE 5U +#define DMA_CSR4_MODESEL_MSK BITS(DMA_CSR4_MODESEL_POSS,DMA_CSR4_MODESEL_POSE) + +#define DMA_CSR4_DIRMDEN_POS 3U +#define DMA_CSR4_DIRMDEN_MSK BIT(DMA_CSR4_DIRMDEN_POS) + +#define DMA_CSR4_PFCTRL_POS 2U +#define DMA_CSR4_PFCTRL_MSK BIT(DMA_CSR4_PFCTRL_POS) + +#define DMA_CSR4_CIRC_POS 1U +#define DMA_CSR4_CIRC_MSK BIT(DMA_CSR4_CIRC_POS) + +#define DMA_CSR4_CHEN_POS 0U +#define DMA_CSR4_CHEN_MSK BIT(DMA_CSR4_CHEN_POS) + +/****************** Bit definition for DMA_SAR4 register ************************/ + +#define DMA_SAR4_SAR_POSS 0U +#define DMA_SAR4_SAR_POSE 31U +#define DMA_SAR4_SAR_MSK BITS(DMA_SAR4_SAR_POSS,DMA_SAR4_SAR_POSE) + +/****************** Bit definition for DMA_DAR4 register ************************/ + +#define DMA_DAR4_DAR_POSS 0U +#define DMA_DAR4_DAR_POSE 31U +#define DMA_DAR4_DAR_MSK BITS(DMA_DAR4_DAR_POSS,DMA_DAR4_DAR_POSE) + +/****************** Bit definition for DMA_BCR4 register ************************/ + +#define DMA_BCR4_CBCR_POSS 16U +#define DMA_BCR4_CBCR_POSE 31U +#define DMA_BCR4_CBCR_MSK BITS(DMA_BCR4_CBCR_POSS,DMA_BCR4_CBCR_POSE) + +#define DMA_BCR4_BCR_POSS 0U +#define DMA_BCR4_BCR_POSE 15U +#define DMA_BCR4_BCR_MSK BITS(DMA_BCR4_BCR_POSS,DMA_BCR4_BCR_POSE) + +/****************** Bit definition for DMA_CSR5 register ************************/ + +#define DMA_CSR5_DINCOS_POS 30U +#define DMA_CSR5_DINCOS_MSK BIT(DMA_CSR5_DINCOS_POS) + +#define DMA_CSR5_DBUSEL_POSS 27U +#define DMA_CSR5_DBUSEL_POSE 29U +#define DMA_CSR5_DBUSEL_MSK BITS(DMA_CSR5_DBUSEL_POSS,DMA_CSR5_DBUSEL_POSE) + +#define DMA_CSR5_DDWSEL_POSS 25U +#define DMA_CSR5_DDWSEL_POSE 26U +#define DMA_CSR5_DDWSEL_MSK BITS(DMA_CSR5_DDWSEL_POSS,DMA_CSR5_DDWSEL_POSE) + +#define DMA_CSR5_DINC_POS 24U +#define DMA_CSR5_DINC_MSK BIT(DMA_CSR5_DINC_POS) + +#define DMA_CSR5_SINCOS_POS 22U +#define DMA_CSR5_SINCOS_MSK BIT(DMA_CSR5_SINCOS_POS) + +#define DMA_CSR5_SBUSEL_POSS 19U +#define DMA_CSR5_SBUSEL_POSE 21U +#define DMA_CSR5_SBUSEL_MSK BITS(DMA_CSR5_SBUSEL_POSS,DMA_CSR5_SBUSEL_POSE) + +#define DMA_CSR5_SDWSEL_POSS 17U +#define DMA_CSR5_SDWSEL_POSE 18U +#define DMA_CSR5_SDWSEL_MSK BITS(DMA_CSR5_SDWSEL_POSS,DMA_CSR5_SDWSEL_POSE) + +#define DMA_CSR5_SINC_POS 16U +#define DMA_CSR5_SINC_MSK BIT(DMA_CSR5_SINC_POS) + +#define DMA_CSR5_PHSS_POSS 9U +#define DMA_CSR5_PHSS_POSE 15U +#define DMA_CSR5_PHSS_MSK BITS(DMA_CSR5_PHSS_POSS,DMA_CSR5_PHSS_POSE) + +#define DMA_CSR5_CHPRI_POSS 6U +#define DMA_CSR5_CHPRI_POSE 8U +#define DMA_CSR5_CHPRI_MSK BITS(DMA_CSR5_CHPRI_POSS,DMA_CSR5_CHPRI_POSE) + +#define DMA_CSR5_MODESEL_POSS 4U +#define DMA_CSR5_MODESEL_POSE 5U +#define DMA_CSR5_MODESEL_MSK BITS(DMA_CSR5_MODESEL_POSS,DMA_CSR5_MODESEL_POSE) + +#define DMA_CSR5_DIRMDEN_POS 3U +#define DMA_CSR5_DIRMDEN_MSK BIT(DMA_CSR5_DIRMDEN_POS) + +#define DMA_CSR5_PFCTRL_POS 2U +#define DMA_CSR5_PFCTRL_MSK BIT(DMA_CSR5_PFCTRL_POS) + +#define DMA_CSR5_CIRC_POS 1U +#define DMA_CSR5_CIRC_MSK BIT(DMA_CSR5_CIRC_POS) + +#define DMA_CSR5_CHEN_POS 0U +#define DMA_CSR5_CHEN_MSK BIT(DMA_CSR5_CHEN_POS) + +/****************** Bit definition for DMA_SAR5 register ************************/ + +#define DMA_SAR5_SAR_POSS 0U +#define DMA_SAR5_SAR_POSE 31U +#define DMA_SAR5_SAR_MSK BITS(DMA_SAR5_SAR_POSS,DMA_SAR5_SAR_POSE) + +/****************** Bit definition for DMA_DAR5 register ************************/ + +#define DMA_DAR5_DAR_POSS 0U +#define DMA_DAR5_DAR_POSE 31U +#define DMA_DAR5_DAR_MSK BITS(DMA_DAR5_DAR_POSS,DMA_DAR5_DAR_POSE) + +/****************** Bit definition for DMA_BCR5 register ************************/ + +#define DMA_BCR5_CBCR_POSS 16U +#define DMA_BCR5_CBCR_POSE 31U +#define DMA_BCR5_CBCR_MSK BITS(DMA_BCR5_CBCR_POSS,DMA_BCR5_CBCR_POSE) + +#define DMA_BCR5_BCR_POSS 0U +#define DMA_BCR5_BCR_POSE 15U +#define DMA_BCR5_BCR_MSK BITS(DMA_BCR5_BCR_POSS,DMA_BCR5_BCR_POSE) + +typedef struct +{ + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + __I uint32_t EMSG; + uint32_t RESERVED0 ; + __IO uint32_t CSR0; + __IO uint32_t SAR0; + __IO uint32_t DAR0; + __IO uint32_t BCR0; + __IO uint32_t CSR1; + __IO uint32_t SAR1; + __IO uint32_t DAR1; + __IO uint32_t BCR1; + __IO uint32_t CSR2; + __IO uint32_t SAR2; + __IO uint32_t DAR2; + __IO uint32_t BCR2; + __IO uint32_t CSR3; + __IO uint32_t SAR3; + __IO uint32_t DAR3; + __IO uint32_t BCR3; + __IO uint32_t CSR4; + __IO uint32_t SAR4; + __IO uint32_t DAR4; + __IO uint32_t BCR4; + __IO uint32_t CSR5; + __IO uint32_t SAR5; + __IO uint32_t DAR5; + __IO uint32_t BCR5; +} DMA_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_exti.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_exti.h new file mode 100644 index 0000000000000000000000000000000000000000..92a82288896dd5704158831876e5bb2329851e2c --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_exti.h @@ -0,0 +1,809 @@ +/** + ************************************************************************************** + * @file REG_EXTI.h + * @brief EXTI Head File + * + * @version V0.01 + * @data 12/3/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __EXTI_H__ +#define __EXTI_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for EXTI_IER register ************************/ + +#define EXTI_IER_WAKEUP_POS 21U +#define EXTI_IER_WAKEUP_MSK BIT(EXTI_IER_WAKEUP_POS) + +#define EXTI_IER_PVD0_POS 20U +#define EXTI_IER_PVD0_MSK BIT(EXTI_IER_PVD0_POS) + +#define EXTI_IER_CMP2_POS 17U +#define EXTI_IER_CMP2_MSK BIT(EXTI_IER_CMP2_POS) + +#define EXTI_IER_CMP1_POS 16U +#define EXTI_IER_CMP1_MSK BIT(EXTI_IER_CMP1_POS) + +#define EXTI_IER_GPIO15_POS 15U +#define EXTI_IER_GPIO15_MSK BIT(EXTI_IER_GPIO15_POS) + +#define EXTI_IER_GPIO14_POS 14U +#define EXTI_IER_GPIO14_MSK BIT(EXTI_IER_GPIO14_POS) + +#define EXTI_IER_GPIO13_POS 13U +#define EXTI_IER_GPIO13_MSK BIT(EXTI_IER_GPIO13_POS) + +#define EXTI_IER_GPIO12_POS 12U +#define EXTI_IER_GPIO12_MSK BIT(EXTI_IER_GPIO12_POS) + +#define EXTI_IER_GPIO11_POS 11U +#define EXTI_IER_GPIO11_MSK BIT(EXTI_IER_GPIO11_POS) + +#define EXTI_IER_GPIO10_POS 10U +#define EXTI_IER_GPIO10_MSK BIT(EXTI_IER_GPIO10_POS) + +#define EXTI_IER_GPIO9_POS 9U +#define EXTI_IER_GPIO9_MSK BIT(EXTI_IER_GPIO9_POS) + +#define EXTI_IER_GPIO8_POS 8U +#define EXTI_IER_GPIO8_MSK BIT(EXTI_IER_GPIO8_POS) + +#define EXTI_IER_GPIO7_POS 7U +#define EXTI_IER_GPIO7_MSK BIT(EXTI_IER_GPIO7_POS) + +#define EXTI_IER_GPIO6_POS 6U +#define EXTI_IER_GPIO6_MSK BIT(EXTI_IER_GPIO6_POS) + +#define EXTI_IER_GPIO5_POS 5U +#define EXTI_IER_GPIO5_MSK BIT(EXTI_IER_GPIO5_POS) + +#define EXTI_IER_GPIO4_POS 4U +#define EXTI_IER_GPIO4_MSK BIT(EXTI_IER_GPIO4_POS) + +#define EXTI_IER_GPIO3_POS 3U +#define EXTI_IER_GPIO3_MSK BIT(EXTI_IER_GPIO3_POS) + +#define EXTI_IER_GPIO2_POS 2U +#define EXTI_IER_GPIO2_MSK BIT(EXTI_IER_GPIO2_POS) + +#define EXTI_IER_GPIO1_POS 1U +#define EXTI_IER_GPIO1_MSK BIT(EXTI_IER_GPIO1_POS) + +#define EXTI_IER_GPIO0_POS 0U +#define EXTI_IER_GPIO0_MSK BIT(EXTI_IER_GPIO0_POS) + +/****************** Bit definition for EXTI_IDR register ************************/ + +#define EXTI_IDR_WAKEUP_POS 21U +#define EXTI_IDR_WAKEUP_MSK BIT(EXTI_IDR_WAKEUP_POS) + +#define EXTI_IDR_PVD0_POS 20U +#define EXTI_IDR_PVD0_MSK BIT(EXTI_IDR_PVD0_POS) + +#define EXTI_IDR_CMP2_POS 17U +#define EXTI_IDR_CMP2_MSK BIT(EXTI_IDR_CMP2_POS) + +#define EXTI_IDR_CMP1_POS 16U +#define EXTI_IDR_CMP1_MSK BIT(EXTI_IDR_CMP1_POS) + +#define EXTI_IDR_GPIO15_POS 15U +#define EXTI_IDR_GPIO15_MSK BIT(EXTI_IDR_GPIO15_POS) + +#define EXTI_IDR_GPIO14_POS 14U +#define EXTI_IDR_GPIO14_MSK BIT(EXTI_IDR_GPIO14_POS) + +#define EXTI_IDR_GPIO13_POS 13U +#define EXTI_IDR_GPIO13_MSK BIT(EXTI_IDR_GPIO13_POS) + +#define EXTI_IDR_GPIO12_POS 12U +#define EXTI_IDR_GPIO12_MSK BIT(EXTI_IDR_GPIO12_POS) + +#define EXTI_IDR_GPIO11_POS 11U +#define EXTI_IDR_GPIO11_MSK BIT(EXTI_IDR_GPIO11_POS) + +#define EXTI_IDR_GPIO10_POS 10U +#define EXTI_IDR_GPIO10_MSK BIT(EXTI_IDR_GPIO10_POS) + +#define EXTI_IDR_GPIO9_POS 9U +#define EXTI_IDR_GPIO9_MSK BIT(EXTI_IDR_GPIO9_POS) + +#define EXTI_IDR_GPIO8_POS 8U +#define EXTI_IDR_GPIO8_MSK BIT(EXTI_IDR_GPIO8_POS) + +#define EXTI_IDR_GPIO7_POS 7U +#define EXTI_IDR_GPIO7_MSK BIT(EXTI_IDR_GPIO7_POS) + +#define EXTI_IDR_GPIO6_POS 6U +#define EXTI_IDR_GPIO6_MSK BIT(EXTI_IDR_GPIO6_POS) + +#define EXTI_IDR_GPIO5_POS 5U +#define EXTI_IDR_GPIO5_MSK BIT(EXTI_IDR_GPIO5_POS) + +#define EXTI_IDR_GPIO4_POS 4U +#define EXTI_IDR_GPIO4_MSK BIT(EXTI_IDR_GPIO4_POS) + +#define EXTI_IDR_GPIO3_POS 3U +#define EXTI_IDR_GPIO3_MSK BIT(EXTI_IDR_GPIO3_POS) + +#define EXTI_IDR_GPIO2_POS 2U +#define EXTI_IDR_GPIO2_MSK BIT(EXTI_IDR_GPIO2_POS) + +#define EXTI_IDR_GPIO1_POS 1U +#define EXTI_IDR_GPIO1_MSK BIT(EXTI_IDR_GPIO1_POS) + +#define EXTI_IDR_GPIO0_POS 0U +#define EXTI_IDR_GPIO0_MSK BIT(EXTI_IDR_GPIO0_POS) + +/****************** Bit definition for EXTI_IVS register ************************/ + +#define EXTI_IVS_WAKEUP_POS 21U +#define EXTI_IVS_WAKEUP_MSK BIT(EXTI_IVS_WAKEUP_POS) + +#define EXTI_IVS_PVD0_POS 20U +#define EXTI_IVS_PVD0_MSK BIT(EXTI_IVS_PVD0_POS) + +#define EXTI_IVS_CMP2_POS 17U +#define EXTI_IVS_CMP2_MSK BIT(EXTI_IVS_CMP2_POS) + +#define EXTI_IVS_CMP1_POS 16U +#define EXTI_IVS_CMP1_MSK BIT(EXTI_IVS_CMP1_POS) + +#define EXTI_IVS_GPIO15_POS 15U +#define EXTI_IVS_GPIO15_MSK BIT(EXTI_IVS_GPIO15_POS) + +#define EXTI_IVS_GPIO14_POS 14U +#define EXTI_IVS_GPIO14_MSK BIT(EXTI_IVS_GPIO14_POS) + +#define EXTI_IVS_GPIO13_POS 13U +#define EXTI_IVS_GPIO13_MSK BIT(EXTI_IVS_GPIO13_POS) + +#define EXTI_IVS_GPIO12_POS 12U +#define EXTI_IVS_GPIO12_MSK BIT(EXTI_IVS_GPIO12_POS) + +#define EXTI_IVS_GPIO11_POS 11U +#define EXTI_IVS_GPIO11_MSK BIT(EXTI_IVS_GPIO11_POS) + +#define EXTI_IVS_GPIO10_POS 10U +#define EXTI_IVS_GPIO10_MSK BIT(EXTI_IVS_GPIO10_POS) + +#define EXTI_IVS_GPIO9_POS 9U +#define EXTI_IVS_GPIO9_MSK BIT(EXTI_IVS_GPIO9_POS) + +#define EXTI_IVS_GPIO8_POS 8U +#define EXTI_IVS_GPIO8_MSK BIT(EXTI_IVS_GPIO8_POS) + +#define EXTI_IVS_GPIO7_POS 7U +#define EXTI_IVS_GPIO7_MSK BIT(EXTI_IVS_GPIO7_POS) + +#define EXTI_IVS_GPIO6_POS 6U +#define EXTI_IVS_GPIO6_MSK BIT(EXTI_IVS_GPIO6_POS) + +#define EXTI_IVS_GPIO5_POS 5U +#define EXTI_IVS_GPIO5_MSK BIT(EXTI_IVS_GPIO5_POS) + +#define EXTI_IVS_GPIO4_POS 4U +#define EXTI_IVS_GPIO4_MSK BIT(EXTI_IVS_GPIO4_POS) + +#define EXTI_IVS_GPIO3_POS 3U +#define EXTI_IVS_GPIO3_MSK BIT(EXTI_IVS_GPIO3_POS) + +#define EXTI_IVS_GPIO2_POS 2U +#define EXTI_IVS_GPIO2_MSK BIT(EXTI_IVS_GPIO2_POS) + +#define EXTI_IVS_GPIO1_POS 1U +#define EXTI_IVS_GPIO1_MSK BIT(EXTI_IVS_GPIO1_POS) + +#define EXTI_IVS_GPIO0_POS 0U +#define EXTI_IVS_GPIO0_MSK BIT(EXTI_IVS_GPIO0_POS) + +/****************** Bit definition for EXTI_RIF register ************************/ + +#define EXTI_RIF_WAKEUP_POS 21U +#define EXTI_RIF_WAKEUP_MSK BIT(EXTI_RIF_WAKEUP_POS) + +#define EXTI_RIF_PVD0_POS 20U +#define EXTI_RIF_PVD0_MSK BIT(EXTI_RIF_PVD0_POS) + +#define EXTI_RIF_CMP2_POS 17U +#define EXTI_RIF_CMP2_MSK BIT(EXTI_RIF_CMP2_POS) + +#define EXTI_RIF_CMP1_POS 16U +#define EXTI_RIF_CMP1_MSK BIT(EXTI_RIF_CMP1_POS) + +#define EXTI_RIF_GPIO15_POS 15U +#define EXTI_RIF_GPIO15_MSK BIT(EXTI_RIF_GPIO15_POS) + +#define EXTI_RIF_GPIO14_POS 14U +#define EXTI_RIF_GPIO14_MSK BIT(EXTI_RIF_GPIO14_POS) + +#define EXTI_RIF_GPIO13_POS 13U +#define EXTI_RIF_GPIO13_MSK BIT(EXTI_RIF_GPIO13_POS) + +#define EXTI_RIF_GPIO12_POS 12U +#define EXTI_RIF_GPIO12_MSK BIT(EXTI_RIF_GPIO12_POS) + +#define EXTI_RIF_GPIO11_POS 11U +#define EXTI_RIF_GPIO11_MSK BIT(EXTI_RIF_GPIO11_POS) + +#define EXTI_RIF_GPIO10_POS 10U +#define EXTI_RIF_GPIO10_MSK BIT(EXTI_RIF_GPIO10_POS) + +#define EXTI_RIF_GPIO9_POS 9U +#define EXTI_RIF_GPIO9_MSK BIT(EXTI_RIF_GPIO9_POS) + +#define EXTI_RIF_GPIO8_POS 8U +#define EXTI_RIF_GPIO8_MSK BIT(EXTI_RIF_GPIO8_POS) + +#define EXTI_RIF_GPIO7_POS 7U +#define EXTI_RIF_GPIO7_MSK BIT(EXTI_RIF_GPIO7_POS) + +#define EXTI_RIF_GPIO6_POS 6U +#define EXTI_RIF_GPIO6_MSK BIT(EXTI_RIF_GPIO6_POS) + +#define EXTI_RIF_GPIO5_POS 5U +#define EXTI_RIF_GPIO5_MSK BIT(EXTI_RIF_GPIO5_POS) + +#define EXTI_RIF_GPIO4_POS 4U +#define EXTI_RIF_GPIO4_MSK BIT(EXTI_RIF_GPIO4_POS) + +#define EXTI_RIF_GPIO3_POS 3U +#define EXTI_RIF_GPIO3_MSK BIT(EXTI_RIF_GPIO3_POS) + +#define EXTI_RIF_GPIO2_POS 2U +#define EXTI_RIF_GPIO2_MSK BIT(EXTI_RIF_GPIO2_POS) + +#define EXTI_RIF_GPIO1_POS 1U +#define EXTI_RIF_GPIO1_MSK BIT(EXTI_RIF_GPIO1_POS) + +#define EXTI_RIF_GPIO0_POS 0U +#define EXTI_RIF_GPIO0_MSK BIT(EXTI_RIF_GPIO0_POS) + +/****************** Bit definition for EXTI_IFM register ************************/ + +#define EXTI_IFM_WAKEUP_POS 21U +#define EXTI_IFM_WAKEUP_MSK BIT(EXTI_IFM_WAKEUP_POS) + +#define EXTI_IFM_PVD0_POS 20U +#define EXTI_IFM_PVD0_MSK BIT(EXTI_IFM_PVD0_POS) + +#define EXTI_IFM_CMP2_POS 17U +#define EXTI_IFM_CMP2_MSK BIT(EXTI_IFM_CMP2_POS) + +#define EXTI_IFM_CMP1_POS 16U +#define EXTI_IFM_CMP1_MSK BIT(EXTI_IFM_CMP1_POS) + +#define EXTI_IFM_GPIO15_POS 15U +#define EXTI_IFM_GPIO15_MSK BIT(EXTI_IFM_GPIO15_POS) + +#define EXTI_IFM_GPIO14_POS 14U +#define EXTI_IFM_GPIO14_MSK BIT(EXTI_IFM_GPIO14_POS) + +#define EXTI_IFM_GPIO13_POS 13U +#define EXTI_IFM_GPIO13_MSK BIT(EXTI_IFM_GPIO13_POS) + +#define EXTI_IFM_GPIO12_POS 12U +#define EXTI_IFM_GPIO12_MSK BIT(EXTI_IFM_GPIO12_POS) + +#define EXTI_IFM_GPIO11_POS 11U +#define EXTI_IFM_GPIO11_MSK BIT(EXTI_IFM_GPIO11_POS) + +#define EXTI_IFM_GPIO10_POS 10U +#define EXTI_IFM_GPIO10_MSK BIT(EXTI_IFM_GPIO10_POS) + +#define EXTI_IFM_GPIO9_POS 9U +#define EXTI_IFM_GPIO9_MSK BIT(EXTI_IFM_GPIO9_POS) + +#define EXTI_IFM_GPIO8_POS 8U +#define EXTI_IFM_GPIO8_MSK BIT(EXTI_IFM_GPIO8_POS) + +#define EXTI_IFM_GPIO7_POS 7U +#define EXTI_IFM_GPIO7_MSK BIT(EXTI_IFM_GPIO7_POS) + +#define EXTI_IFM_GPIO6_POS 6U +#define EXTI_IFM_GPIO6_MSK BIT(EXTI_IFM_GPIO6_POS) + +#define EXTI_IFM_GPIO5_POS 5U +#define EXTI_IFM_GPIO5_MSK BIT(EXTI_IFM_GPIO5_POS) + +#define EXTI_IFM_GPIO4_POS 4U +#define EXTI_IFM_GPIO4_MSK BIT(EXTI_IFM_GPIO4_POS) + +#define EXTI_IFM_GPIO3_POS 3U +#define EXTI_IFM_GPIO3_MSK BIT(EXTI_IFM_GPIO3_POS) + +#define EXTI_IFM_GPIO2_POS 2U +#define EXTI_IFM_GPIO2_MSK BIT(EXTI_IFM_GPIO2_POS) + +#define EXTI_IFM_GPIO1_POS 1U +#define EXTI_IFM_GPIO1_MSK BIT(EXTI_IFM_GPIO1_POS) + +#define EXTI_IFM_GPIO0_POS 0U +#define EXTI_IFM_GPIO0_MSK BIT(EXTI_IFM_GPIO0_POS) + +/****************** Bit definition for EXTI_ICR register ************************/ + +#define EXTI_ICR_WAKEUP_POS 21U +#define EXTI_ICR_WAKEUP_MSK BIT(EXTI_ICR_WAKEUP_POS) + +#define EXTI_ICR_PVD0_POS 20U +#define EXTI_ICR_PVD0_MSK BIT(EXTI_ICR_PVD0_POS) + +#define EXTI_ICR_CMP2_POS 17U +#define EXTI_ICR_CMP2_MSK BIT(EXTI_ICR_CMP2_POS) + +#define EXTI_ICR_CMP1_POS 16U +#define EXTI_ICR_CMP1_MSK BIT(EXTI_ICR_CMP1_POS) + +#define EXTI_ICR_GPIO15_POS 15U +#define EXTI_ICR_GPIO15_MSK BIT(EXTI_ICR_GPIO15_POS) + +#define EXTI_ICR_GPIO14_POS 14U +#define EXTI_ICR_GPIO14_MSK BIT(EXTI_ICR_GPIO14_POS) + +#define EXTI_ICR_GPIO13_POS 13U +#define EXTI_ICR_GPIO13_MSK BIT(EXTI_ICR_GPIO13_POS) + +#define EXTI_ICR_GPIO12_POS 12U +#define EXTI_ICR_GPIO12_MSK BIT(EXTI_ICR_GPIO12_POS) + +#define EXTI_ICR_GPIO11_POS 11U +#define EXTI_ICR_GPIO11_MSK BIT(EXTI_ICR_GPIO11_POS) + +#define EXTI_ICR_GPIO10_POS 10U +#define EXTI_ICR_GPIO10_MSK BIT(EXTI_ICR_GPIO10_POS) + +#define EXTI_ICR_GPIO9_POS 9U +#define EXTI_ICR_GPIO9_MSK BIT(EXTI_ICR_GPIO9_POS) + +#define EXTI_ICR_GPIO8_POS 8U +#define EXTI_ICR_GPIO8_MSK BIT(EXTI_ICR_GPIO8_POS) + +#define EXTI_ICR_GPIO7_POS 7U +#define EXTI_ICR_GPIO7_MSK BIT(EXTI_ICR_GPIO7_POS) + +#define EXTI_ICR_GPIO6_POS 6U +#define EXTI_ICR_GPIO6_MSK BIT(EXTI_ICR_GPIO6_POS) + +#define EXTI_ICR_GPIO5_POS 5U +#define EXTI_ICR_GPIO5_MSK BIT(EXTI_ICR_GPIO5_POS) + +#define EXTI_ICR_GPIO4_POS 4U +#define EXTI_ICR_GPIO4_MSK BIT(EXTI_ICR_GPIO4_POS) + +#define EXTI_ICR_GPIO3_POS 3U +#define EXTI_ICR_GPIO3_MSK BIT(EXTI_ICR_GPIO3_POS) + +#define EXTI_ICR_GPIO2_POS 2U +#define EXTI_ICR_GPIO2_MSK BIT(EXTI_ICR_GPIO2_POS) + +#define EXTI_ICR_GPIO1_POS 1U +#define EXTI_ICR_GPIO1_MSK BIT(EXTI_ICR_GPIO1_POS) + +#define EXTI_ICR_GPIO0_POS 0U +#define EXTI_ICR_GPIO0_MSK BIT(EXTI_ICR_GPIO0_POS) + +/****************** Bit definition for EXTI_RTS register ************************/ + +#define EXTI_RTS_WAKEUP_POS 21U +#define EXTI_RTS_WAKEUP_MSK BIT(EXTI_RTS_WAKEUP_POS) + +#define EXTI_RTS_PVD0_POS 20U +#define EXTI_RTS_PVD0_MSK BIT(EXTI_RTS_PVD0_POS) + +#define EXTI_RTS_CMP2_POS 17U +#define EXTI_RTS_CMP2_MSK BIT(EXTI_RTS_CMP2_POS) + +#define EXTI_RTS_CMP1_POS 16U +#define EXTI_RTS_CMP1_MSK BIT(EXTI_RTS_CMP1_POS) + +#define EXTI_RTS_GPIO15_POS 15U +#define EXTI_RTS_GPIO15_MSK BIT(EXTI_RTS_GPIO15_POS) + +#define EXTI_RTS_GPIO14_POS 14U +#define EXTI_RTS_GPIO14_MSK BIT(EXTI_RTS_GPIO14_POS) + +#define EXTI_RTS_GPIO13_POS 13U +#define EXTI_RTS_GPIO13_MSK BIT(EXTI_RTS_GPIO13_POS) + +#define EXTI_RTS_GPIO12_POS 12U +#define EXTI_RTS_GPIO12_MSK BIT(EXTI_RTS_GPIO12_POS) + +#define EXTI_RTS_GPIO11_POS 11U +#define EXTI_RTS_GPIO11_MSK BIT(EXTI_RTS_GPIO11_POS) + +#define EXTI_RTS_GPIO10_POS 10U +#define EXTI_RTS_GPIO10_MSK BIT(EXTI_RTS_GPIO10_POS) + +#define EXTI_RTS_GPIO9_POS 9U +#define EXTI_RTS_GPIO9_MSK BIT(EXTI_RTS_GPIO9_POS) + +#define EXTI_RTS_GPIO8_POS 8U +#define EXTI_RTS_GPIO8_MSK BIT(EXTI_RTS_GPIO8_POS) + +#define EXTI_RTS_GPIO7_POS 7U +#define EXTI_RTS_GPIO7_MSK BIT(EXTI_RTS_GPIO7_POS) + +#define EXTI_RTS_GPIO6_POS 6U +#define EXTI_RTS_GPIO6_MSK BIT(EXTI_RTS_GPIO6_POS) + +#define EXTI_RTS_GPIO5_POS 5U +#define EXTI_RTS_GPIO5_MSK BIT(EXTI_RTS_GPIO5_POS) + +#define EXTI_RTS_GPIO4_POS 4U +#define EXTI_RTS_GPIO4_MSK BIT(EXTI_RTS_GPIO4_POS) + +#define EXTI_RTS_GPIO3_POS 3U +#define EXTI_RTS_GPIO3_MSK BIT(EXTI_RTS_GPIO3_POS) + +#define EXTI_RTS_GPIO2_POS 2U +#define EXTI_RTS_GPIO2_MSK BIT(EXTI_RTS_GPIO2_POS) + +#define EXTI_RTS_GPIO1_POS 1U +#define EXTI_RTS_GPIO1_MSK BIT(EXTI_RTS_GPIO1_POS) + +#define EXTI_RTS_GPIO0_POS 0U +#define EXTI_RTS_GPIO0_MSK BIT(EXTI_RTS_GPIO0_POS) + +/****************** Bit definition for EXTI_FTS register ************************/ + +#define EXTI_FTS_WAKEUP_POS 21U +#define EXTI_FTS_WAKEUP_MSK BIT(EXTI_FTS_WAKEUP_POS) + +#define EXTI_FTS_PVD0_POS 20U +#define EXTI_FTS_PVD0_MSK BIT(EXTI_FTS_PVD0_POS) + +#define EXTI_FTS_CMP2_POS 17U +#define EXTI_FTS_CMP2_MSK BIT(EXTI_FTS_CMP2_POS) + +#define EXTI_FTS_CMP1_POS 16U +#define EXTI_FTS_CMP1_MSK BIT(EXTI_FTS_CMP1_POS) + +#define EXTI_FTS_GPIO15_POS 15U +#define EXTI_FTS_GPIO15_MSK BIT(EXTI_FTS_GPIO15_POS) + +#define EXTI_FTS_GPIO14_POS 14U +#define EXTI_FTS_GPIO14_MSK BIT(EXTI_FTS_GPIO14_POS) + +#define EXTI_FTS_GPIO13_POS 13U +#define EXTI_FTS_GPIO13_MSK BIT(EXTI_FTS_GPIO13_POS) + +#define EXTI_FTS_GPIO12_POS 12U +#define EXTI_FTS_GPIO12_MSK BIT(EXTI_FTS_GPIO12_POS) + +#define EXTI_FTS_GPIO11_POS 11U +#define EXTI_FTS_GPIO11_MSK BIT(EXTI_FTS_GPIO11_POS) + +#define EXTI_FTS_GPIO10_POS 10U +#define EXTI_FTS_GPIO10_MSK BIT(EXTI_FTS_GPIO10_POS) + +#define EXTI_FTS_GPIO9_POS 9U +#define EXTI_FTS_GPIO9_MSK BIT(EXTI_FTS_GPIO9_POS) + +#define EXTI_FTS_GPIO8_POS 8U +#define EXTI_FTS_GPIO8_MSK BIT(EXTI_FTS_GPIO8_POS) + +#define EXTI_FTS_GPIO7_POS 7U +#define EXTI_FTS_GPIO7_MSK BIT(EXTI_FTS_GPIO7_POS) + +#define EXTI_FTS_GPIO6_POS 6U +#define EXTI_FTS_GPIO6_MSK BIT(EXTI_FTS_GPIO6_POS) + +#define EXTI_FTS_GPIO5_POS 5U +#define EXTI_FTS_GPIO5_MSK BIT(EXTI_FTS_GPIO5_POS) + +#define EXTI_FTS_GPIO4_POS 4U +#define EXTI_FTS_GPIO4_MSK BIT(EXTI_FTS_GPIO4_POS) + +#define EXTI_FTS_GPIO3_POS 3U +#define EXTI_FTS_GPIO3_MSK BIT(EXTI_FTS_GPIO3_POS) + +#define EXTI_FTS_GPIO2_POS 2U +#define EXTI_FTS_GPIO2_MSK BIT(EXTI_FTS_GPIO2_POS) + +#define EXTI_FTS_GPIO1_POS 1U +#define EXTI_FTS_GPIO1_MSK BIT(EXTI_FTS_GPIO1_POS) + +#define EXTI_FTS_GPIO0_POS 0U +#define EXTI_FTS_GPIO0_MSK BIT(EXTI_FTS_GPIO0_POS) + +/****************** Bit definition for EXTI_SWI register ************************/ + +#define EXTI_SWI_WAKEUP_POS 21U +#define EXTI_SWI_WAKEUP_MSK BIT(EXTI_SWI_WAKEUP_POS) + +#define EXTI_SWI_PVD0_POS 20U +#define EXTI_SWI_PVD0_MSK BIT(EXTI_SWI_PVD0_POS) + +#define EXTI_SWI_CMP2_POS 17U +#define EXTI_SWI_CMP2_MSK BIT(EXTI_SWI_CMP2_POS) + +#define EXTI_SWI_CMP1_POS 16U +#define EXTI_SWI_CMP1_MSK BIT(EXTI_SWI_CMP1_POS) + +#define EXTI_SWI_GPIO15_POS 15U +#define EXTI_SWI_GPIO15_MSK BIT(EXTI_SWI_GPIO15_POS) + +#define EXTI_SWI_GPIO14_POS 14U +#define EXTI_SWI_GPIO14_MSK BIT(EXTI_SWI_GPIO14_POS) + +#define EXTI_SWI_GPIO13_POS 13U +#define EXTI_SWI_GPIO13_MSK BIT(EXTI_SWI_GPIO13_POS) + +#define EXTI_SWI_GPIO12_POS 12U +#define EXTI_SWI_GPIO12_MSK BIT(EXTI_SWI_GPIO12_POS) + +#define EXTI_SWI_GPIO11_POS 11U +#define EXTI_SWI_GPIO11_MSK BIT(EXTI_SWI_GPIO11_POS) + +#define EXTI_SWI_GPIO10_POS 10U +#define EXTI_SWI_GPIO10_MSK BIT(EXTI_SWI_GPIO10_POS) + +#define EXTI_SWI_GPIO9_POS 9U +#define EXTI_SWI_GPIO9_MSK BIT(EXTI_SWI_GPIO9_POS) + +#define EXTI_SWI_GPIO8_POS 8U +#define EXTI_SWI_GPIO8_MSK BIT(EXTI_SWI_GPIO8_POS) + +#define EXTI_SWI_GPIO7_POS 7U +#define EXTI_SWI_GPIO7_MSK BIT(EXTI_SWI_GPIO7_POS) + +#define EXTI_SWI_GPIO6_POS 6U +#define EXTI_SWI_GPIO6_MSK BIT(EXTI_SWI_GPIO6_POS) + +#define EXTI_SWI_GPIO5_POS 5U +#define EXTI_SWI_GPIO5_MSK BIT(EXTI_SWI_GPIO5_POS) + +#define EXTI_SWI_GPIO4_POS 4U +#define EXTI_SWI_GPIO4_MSK BIT(EXTI_SWI_GPIO4_POS) + +#define EXTI_SWI_GPIO3_POS 3U +#define EXTI_SWI_GPIO3_MSK BIT(EXTI_SWI_GPIO3_POS) + +#define EXTI_SWI_GPIO2_POS 2U +#define EXTI_SWI_GPIO2_MSK BIT(EXTI_SWI_GPIO2_POS) + +#define EXTI_SWI_GPIO1_POS 1U +#define EXTI_SWI_GPIO1_MSK BIT(EXTI_SWI_GPIO1_POS) + +#define EXTI_SWI_GPIO0_POS 0U +#define EXTI_SWI_GPIO0_MSK BIT(EXTI_SWI_GPIO0_POS) + +/****************** Bit definition for EXTI_ADTE register ************************/ + +#define EXTI_ADTE_WAKEUP_POS 21U +#define EXTI_ADTE_WAKEUP_MSK BIT(EXTI_ADTE_WAKEUP_POS) + +#define EXTI_ADTE_PVD0_POS 20U +#define EXTI_ADTE_PVD0_MSK BIT(EXTI_ADTE_PVD0_POS) + +#define EXTI_ADTE_CMP2_POS 17U +#define EXTI_ADTE_CMP2_MSK BIT(EXTI_ADTE_CMP2_POS) + +#define EXTI_ADTE_CMP1_POS 16U +#define EXTI_ADTE_CMP1_MSK BIT(EXTI_ADTE_CMP1_POS) + +#define EXTI_ADTE_GPIO15_POS 15U +#define EXTI_ADTE_GPIO15_MSK BIT(EXTI_ADTE_GPIO15_POS) + +#define EXTI_ADTE_GPIO14_POS 14U +#define EXTI_ADTE_GPIO14_MSK BIT(EXTI_ADTE_GPIO14_POS) + +#define EXTI_ADTE_GPIO13_POS 13U +#define EXTI_ADTE_GPIO13_MSK BIT(EXTI_ADTE_GPIO13_POS) + +#define EXTI_ADTE_GPIO12_POS 12U +#define EXTI_ADTE_GPIO12_MSK BIT(EXTI_ADTE_GPIO12_POS) + +#define EXTI_ADTE_GPIO11_POS 11U +#define EXTI_ADTE_GPIO11_MSK BIT(EXTI_ADTE_GPIO11_POS) + +#define EXTI_ADTE_GPIO10_POS 10U +#define EXTI_ADTE_GPIO10_MSK BIT(EXTI_ADTE_GPIO10_POS) + +#define EXTI_ADTE_GPIO9_POS 9U +#define EXTI_ADTE_GPIO9_MSK BIT(EXTI_ADTE_GPIO9_POS) + +#define EXTI_ADTE_GPIO8_POS 8U +#define EXTI_ADTE_GPIO8_MSK BIT(EXTI_ADTE_GPIO8_POS) + +#define EXTI_ADTE_GPIO7_POS 7U +#define EXTI_ADTE_GPIO7_MSK BIT(EXTI_ADTE_GPIO7_POS) + +#define EXTI_ADTE_GPIO6_POS 6U +#define EXTI_ADTE_GPIO6_MSK BIT(EXTI_ADTE_GPIO6_POS) + +#define EXTI_ADTE_GPIO5_POS 5U +#define EXTI_ADTE_GPIO5_MSK BIT(EXTI_ADTE_GPIO5_POS) + +#define EXTI_ADTE_GPIO4_POS 4U +#define EXTI_ADTE_GPIO4_MSK BIT(EXTI_ADTE_GPIO4_POS) + +#define EXTI_ADTE_GPIO3_POS 3U +#define EXTI_ADTE_GPIO3_MSK BIT(EXTI_ADTE_GPIO3_POS) + +#define EXTI_ADTE_GPIO2_POS 2U +#define EXTI_ADTE_GPIO2_MSK BIT(EXTI_ADTE_GPIO2_POS) + +#define EXTI_ADTE_GPIO1_POS 1U +#define EXTI_ADTE_GPIO1_MSK BIT(EXTI_ADTE_GPIO1_POS) + +#define EXTI_ADTE_GPIO0_POS 0U +#define EXTI_ADTE_GPIO0_MSK BIT(EXTI_ADTE_GPIO0_POS) + +/****************** Bit definition for EXTI_DB register ************************/ + +#define EXTI_DB_WAKEUP_POS 21U +#define EXTI_DB_WAKEUP_MSK BIT(EXTI_DB_WAKEUP_POS) + +#define EXTI_DB_PVD0_POS 20U +#define EXTI_DB_PVD0_MSK BIT(EXTI_DB_PVD0_POS) + +#define EXTI_DB_CMP2_POS 17U +#define EXTI_DB_CMP2_MSK BIT(EXTI_DB_CMP2_POS) + +#define EXTI_DB_CMP1_POS 16U +#define EXTI_DB_CMP1_MSK BIT(EXTI_DB_CMP1_POS) + +#define EXTI_DB_GPIO15_POS 15U +#define EXTI_DB_GPIO15_MSK BIT(EXTI_DB_GPIO15_POS) + +#define EXTI_DB_GPIO14_POS 14U +#define EXTI_DB_GPIO14_MSK BIT(EXTI_DB_GPIO14_POS) + +#define EXTI_DB_GPIO13_POS 13U +#define EXTI_DB_GPIO13_MSK BIT(EXTI_DB_GPIO13_POS) + +#define EXTI_DB_GPIO12_POS 12U +#define EXTI_DB_GPIO12_MSK BIT(EXTI_DB_GPIO12_POS) + +#define EXTI_DB_GPIO11_POS 11U +#define EXTI_DB_GPIO11_MSK BIT(EXTI_DB_GPIO11_POS) + +#define EXTI_DB_GPIO10_POS 10U +#define EXTI_DB_GPIO10_MSK BIT(EXTI_DB_GPIO10_POS) + +#define EXTI_DB_GPIO9_POS 9U +#define EXTI_DB_GPIO9_MSK BIT(EXTI_DB_GPIO9_POS) + +#define EXTI_DB_GPIO8_POS 8U +#define EXTI_DB_GPIO8_MSK BIT(EXTI_DB_GPIO8_POS) + +#define EXTI_DB_GPIO7_POS 7U +#define EXTI_DB_GPIO7_MSK BIT(EXTI_DB_GPIO7_POS) + +#define EXTI_DB_GPIO6_POS 6U +#define EXTI_DB_GPIO6_MSK BIT(EXTI_DB_GPIO6_POS) + +#define EXTI_DB_GPIO5_POS 5U +#define EXTI_DB_GPIO5_MSK BIT(EXTI_DB_GPIO5_POS) + +#define EXTI_DB_GPIO4_POS 4U +#define EXTI_DB_GPIO4_MSK BIT(EXTI_DB_GPIO4_POS) + +#define EXTI_DB_GPIO3_POS 3U +#define EXTI_DB_GPIO3_MSK BIT(EXTI_DB_GPIO3_POS) + +#define EXTI_DB_GPIO2_POS 2U +#define EXTI_DB_GPIO2_MSK BIT(EXTI_DB_GPIO2_POS) + +#define EXTI_DB_GPIO1_POS 1U +#define EXTI_DB_GPIO1_MSK BIT(EXTI_DB_GPIO1_POS) + +#define EXTI_DB_GPIO0_POS 0U +#define EXTI_DB_GPIO0_MSK BIT(EXTI_DB_GPIO0_POS) + +/****************** Bit definition for EXTI_DBCON register ************************/ + +#define EXTI_DBCON_DBPRE_POSS 8U +#define EXTI_DBCON_DBPRE_POSE 15U +#define EXTI_DBCON_DBPRE_MSK BITS(EXTI_DBCON_DBPRE_POSS,EXTI_DBCON_DBPRE_POSE) + +#define EXTI_DBCON_DBCNT_POSS 0U +#define EXTI_DBCON_DBCNT_POSE 2U +#define EXTI_DBCON_DBCNT_MSK BITS(EXTI_DBCON_DBCNT_POSS,EXTI_DBCON_DBCNT_POSE) + +/****************** Bit definition for EXTI_ICFG1 register ************************/ + +#define EXTI_ICFG1_GPIO7_POSS 28U +#define EXTI_ICFG1_GPIO7_POSE 31U +#define EXTI_ICFG1_GPIO7_MSK BITS(EXTI_ICFG1_GPIO7_POSS,EXTI_ICFG1_GPIO7_POSE) + +#define EXTI_ICFG1_GPIO6_POSS 24U +#define EXTI_ICFG1_GPIO6_POSE 27U +#define EXTI_ICFG1_GPIO6_MSK BITS(EXTI_ICFG1_GPIO6_POSS,EXTI_ICFG1_GPIO6_POSE) + +#define EXTI_ICFG1_GPIO5_POSS 20U +#define EXTI_ICFG1_GPIO5_POSE 23U +#define EXTI_ICFG1_GPIO5_MSK BITS(EXTI_ICFG1_GPIO5_POSS,EXTI_ICFG1_GPIO5_POSE) + +#define EXTI_ICFG1_GPIO4_POSS 16U +#define EXTI_ICFG1_GPIO4_POSE 19U +#define EXTI_ICFG1_GPIO4_MSK BITS(EXTI_ICFG1_GPIO4_POSS,EXTI_ICFG1_GPIO4_POSE) + +#define EXTI_ICFG1_GPIO3_POSS 12U +#define EXTI_ICFG1_GPIO3_POSE 15U +#define EXTI_ICFG1_GPIO3_MSK BITS(EXTI_ICFG1_GPIO3_POSS,EXTI_ICFG1_GPIO3_POSE) + +#define EXTI_ICFG1_GPIO2_POSS 8U +#define EXTI_ICFG1_GPIO2_POSE 11U +#define EXTI_ICFG1_GPIO2_MSK BITS(EXTI_ICFG1_GPIO2_POSS,EXTI_ICFG1_GPIO2_POSE) + +#define EXTI_ICFG1_GPIO1_POSS 4U +#define EXTI_ICFG1_GPIO1_POSE 7U +#define EXTI_ICFG1_GPIO1_MSK BITS(EXTI_ICFG1_GPIO1_POSS,EXTI_ICFG1_GPIO1_POSE) + +#define EXTI_ICFG1_GPIO0_POSS 0U +#define EXTI_ICFG1_GPIO0_POSE 3U +#define EXTI_ICFG1_GPIO0_MSK BITS(EXTI_ICFG1_GPIO0_POSS,EXTI_ICFG1_GPIO0_POSE) + +/****************** Bit definition for EXTI_ICFG2 register ************************/ + +#define EXTI_ICFG2_GPIO15_POSS 28U +#define EXTI_ICFG2_GPIO15_POSE 31U +#define EXTI_ICFG2_GPIO15_MSK BITS(EXTI_ICFG2_GPIO15_POSS,EXTI_ICFG2_GPIO15_POSE) + +#define EXTI_ICFG2_GPIO14_POSS 24U +#define EXTI_ICFG2_GPIO14_POSE 27U +#define EXTI_ICFG2_GPIO14_MSK BITS(EXTI_ICFG2_GPIO14_POSS,EXTI_ICFG2_GPIO14_POSE) + +#define EXTI_ICFG2_GPIO13_POSS 20U +#define EXTI_ICFG2_GPIO13_POSE 23U +#define EXTI_ICFG2_GPIO13_MSK BITS(EXTI_ICFG2_GPIO13_POSS,EXTI_ICFG2_GPIO13_POSE) + +#define EXTI_ICFG2_GPIO12_POSS 16U +#define EXTI_ICFG2_GPIO12_POSE 19U +#define EXTI_ICFG2_GPIO12_MSK BITS(EXTI_ICFG2_GPIO12_POSS,EXTI_ICFG2_GPIO12_POSE) + +#define EXTI_ICFG2_GPIO11_POSS 12U +#define EXTI_ICFG2_GPIO11_POSE 15U +#define EXTI_ICFG2_GPIO11_MSK BITS(EXTI_ICFG2_GPIO11_POSS,EXTI_ICFG2_GPIO11_POSE) + +#define EXTI_ICFG2_GPIO10_POSS 8U +#define EXTI_ICFG2_GPIO10_POSE 11U +#define EXTI_ICFG2_GPIO10_MSK BITS(EXTI_ICFG2_GPIO10_POSS,EXTI_ICFG2_GPIO10_POSE) + +#define EXTI_ICFG2_GPIO9_POSS 4U +#define EXTI_ICFG2_GPIO9_POSE 7U +#define EXTI_ICFG2_GPIO9_MSK BITS(EXTI_ICFG2_GPIO9_POSS,EXTI_ICFG2_GPIO9_POSE) + +#define EXTI_ICFG2_GPIO8_POSS 0U +#define EXTI_ICFG2_GPIO8_POSE 3U +#define EXTI_ICFG2_GPIO8_MSK BITS(EXTI_ICFG2_GPIO8_POSS,EXTI_ICFG2_GPIO8_POSE) + +typedef struct +{ + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + __IO uint32_t RTS; + __IO uint32_t FTS; + __O uint32_t SWI; + __IO uint32_t ADTE; + __IO uint32_t DB; + __IO uint32_t DBCON; + __IO uint32_t ICFG1; + __IO uint32_t ICFG2; +} EXTI_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_fc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_fc.h new file mode 100644 index 0000000000000000000000000000000000000000..0b9850cb4e68986ba97ad2ab20b6669da69f4f89 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_fc.h @@ -0,0 +1,181 @@ +/** + ************************************************************************************** + * @file REG_FC.h + * @brief FC Head File + * + * @version V0.01 + * @data 12/3/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __fc_H__ +#define __fc_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for FC_CMD register ************************/ + +#define FC_CMD_FC_CMD_POSS 0U +#define FC_CMD_FC_CMD_POSE 7U +#define FC_CMD_FC_CMD_MSK BITS(FC_CMD_FC_CMD_POSS,FC_CMD_FC_CMD_POSE) + +/****************** Bit definition for FC_PA register ************************/ + +#define FC_PA_PCNT_POSS 25U +#define FC_PA_PCNT_POSE 31U +#define FC_PA_PCNT_MSK BITS(FC_PA_PCNT_POSS,FC_PA_PCNT_POSE) + +#define FC_PA_IFREN_POS 24U +#define FC_PA_IFREN_MSK BIT(FC_PA_IFREN_POS) + +#define FC_PA_PROG_ADDR_POSS 0U +#define FC_PA_PROG_ADDR_POSE 23U +#define FC_PA_PROG_ADDR_MSK BITS(FC_PA_PROG_ADDR_POSS,FC_PA_PROG_ADDR_POSE) + +/****************** Bit definition for FC_PLD register ************************/ + +#define FC_PLD_PROG_DATA_L_POSS 0U +#define FC_PLD_PROG_DATA_L_POSE 31U +#define FC_PLD_PROG_DATA_L_MSK BITS(FC_PLD_PROG_DATA_L_POSS,FC_PLD_PROG_DATA_L_POSE) + +/****************** Bit definition for FC_PHD register ************************/ + +#define FC_PHD_PROG_DATA_H_POSS 0U +#define FC_PHD_PROG_DATA_H_POSE 31U +#define FC_PHD_PROG_DATA_H_MSK BITS(FC_PHD_PROG_DATA_H_POSS,FC_PHD_PROG_DATA_H_POSE) + +/****************** Bit definition for FC_CON register ************************/ + +#define FC_CON_SLEEP_POS 9U +#define FC_CON_SLEEP_MSK BIT(FC_CON_SLEEP_POS) + +#define FC_CON_PFEN_POS 8U +#define FC_CON_PFEN_MSK BIT(FC_CON_PFEN_POS) + +#define FC_CON_WAIT_POSS 0U +#define FC_CON_WAIT_POSE 1U +#define FC_CON_WAIT_MSK BITS(FC_CON_WAIT_POSS,FC_CON_WAIT_POSE) + +/****************** Bit definition for FC_STAT register ************************/ + +#define FC_STAT_OPVD_POS 2U +#define FC_STAT_OPVD_MSK BIT(FC_STAT_OPVD_POS) + +#define FC_STAT_MUNP2_POS 1U +#define FC_STAT_MUNP2_MSK BIT(FC_STAT_MUNP2_POS) + +#define FC_STAT_MUNP1_POS 0U +#define FC_STAT_MUNP1_MSK BIT(FC_STAT_MUNP1_POS) + +/****************** Bit definition for FC_UPL register ************************/ + +#define FC_UPL_UPL_POSS 0U +#define FC_UPL_UPL_POSE 31U +#define FC_UPL_UPL_MSK BITS(FC_UPL_UPL_POSS,FC_UPL_UPL_POSE) + +/****************** Bit definition for FC_UPH register ************************/ + +#define FC_UPH_UPH_POSS 0U +#define FC_UPH_UPH_POSE 31U +#define FC_UPH_UPH_MSK BITS(FC_UPH_UPH_POSS,FC_UPH_UPH_POSE) + +/****************** Bit definition for FC_OP_TRIM register ************************/ + +#define FC_OP_TRIM_BGTRIMVD_POSS 24U +#define FC_OP_TRIM_BGTRIMVD_POSE 31U +#define FC_OP_TRIM_BGTRIMVD_MSK BITS(FC_OP_TRIM_BGTRIMVD_POSS,FC_OP_TRIM_BGTRIMVD_POSE) + +#define FC_OP_TRIM_BGTRIM_POSS 16U +#define FC_OP_TRIM_BGTRIM_POSE 23U +#define FC_OP_TRIM_BGTRIM_MSK BITS(FC_OP_TRIM_BGTRIM_POSS,FC_OP_TRIM_BGTRIM_POSE) + +#define FC_OP_TRIM_HRCTRIMVD_POSS 8U +#define FC_OP_TRIM_HRCTRIMVD_POSE 15U +#define FC_OP_TRIM_HRCTRIMVD_MSK BITS(FC_OP_TRIM_HRCTRIMVD_POSS,FC_OP_TRIM_HRCTRIMVD_POSE) + +#define FC_OP_TRIM_HRCTRIM_POSS 0U +#define FC_OP_TRIM_HRCTRIM_POSE 7U +#define FC_OP_TRIM_HRCTRIM_MSK BITS(FC_OP_TRIM_HRCTRIM_POSS,FC_OP_TRIM_HRCTRIM_POSE) + +/****************** Bit definition for FC_OP_PRT2L register ************************/ + +#define FC_OP_PRT2L_PRTLV2L_POSS 0U +#define FC_OP_PRT2L_PRTLV2L_POSE 31U +#define FC_OP_PRT2L_PRTLV2L_MSK BITS(FC_OP_PRT2L_PRTLV2L_POSS,FC_OP_PRT2L_PRTLV2L_POSE) + +/****************** Bit definition for FC_OP_PRT2H register ************************/ + +#define FC_OP_PRT2H_PRTLV2H_POSS 0U +#define FC_OP_PRT2H_PRTLV2H_POSE 31U +#define FC_OP_PRT2H_PRTLV2H_MSK BITS(FC_OP_PRT2H_PRTLV2H_POSS,FC_OP_PRT2H_PRTLV2H_POSE) + +/****************** Bit definition for FC_OP_PRT1L register ************************/ + +#define FC_OP_PRT1L_PRTLV1L_POSS 0U +#define FC_OP_PRT1L_PRTLV1L_POSE 31U +#define FC_OP_PRT1L_PRTLV1L_MSK BITS(FC_OP_PRT1L_PRTLV1L_POSS,FC_OP_PRT1L_PRTLV1L_POSE) + +/****************** Bit definition for FC_OP_PRT1H register ************************/ + +#define FC_OP_PRT1H_PRTLV1H_POSS 0U +#define FC_OP_PRT1H_PRTLV1H_POSE 31U +#define FC_OP_PRT1H_PRTLV1H_MSK BITS(FC_OP_PRT1H_PRTLV1H_POSS,FC_OP_PRT1H_PRTLV1H_POSE) + +/****************** Bit definition for FC_OP_REMAP register ************************/ + +#define FC_OP_REMAP_HREMAP_POSS 8U +#define FC_OP_REMAP_HREMAP_POSE 15U +#define FC_OP_REMAP_HREMAP_MSK BITS(FC_OP_REMAP_HREMAP_POSS,FC_OP_REMAP_HREMAP_POSE) + +#define FC_OP_REMAP_SREMAP_POSS 4U +#define FC_OP_REMAP_SREMAP_POSE 5U +#define FC_OP_REMAP_SREMAP_MSK BITS(FC_OP_REMAP_SREMAP_POSS,FC_OP_REMAP_SREMAP_POSE) + +#define FC_OP_REMAP_SEFBASE_POSS 0U +#define FC_OP_REMAP_SEFBASE_POSE 3U +#define FC_OP_REMAP_SEFBASE_MSK BITS(FC_OP_REMAP_SEFBASE_POSS,FC_OP_REMAP_SEFBASE_POSE) + +typedef struct +{ + __IO uint32_t CMD; + __IO uint32_t PA; + __IO uint32_t PLD; + __IO uint32_t PHD; + __IO uint32_t CON; + __I uint32_t STAT; + uint32_t RESERVED0[2] ; + __IO uint32_t UPL; + __IO uint32_t UPH; + uint32_t RESERVED1[2] ; + __I uint32_t OP_TRIM; + uint32_t RESERVED2[4] ; +// uint32_t ADCTRIM_1V; +// uint32_t ADCTRIM_2V; +// uint32_t RESERVED3; + + uint32_t ADCTRIM_VDD5V_VREF5V; + uint32_t ADCTRIM_VDD3V3_VREF3V3; + uint32_t ADCTRIM_VDD5V_VREF2V5; + __I uint32_t OP_PRT2L; + __I uint32_t OP_PRT2H; + __I uint32_t OP_PRT1L; + __I uint32_t OP_PRT1H; + __I uint32_t OP_REMAP; +} FC_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_gpio.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..d965ef3b94aa8abf8a88ede1ede6a8eaeceb1e58 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_gpio.h @@ -0,0 +1,710 @@ +/** + ************************************************************************************** + * @file REG_GPIO.h + * @brief GPIO Head File + * + * @version V0.01 + * @date 12/5/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __GPIO_H__ +#define __GPIO_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for GPIO_IDATA register ************************/ + +#define GPIO_IDATA_ID15_POS 15U +#define GPIO_IDATA_ID15_MSK BIT(GPIO_IDATA_ID15_POS) + +#define GPIO_IDATA_ID14_POS 14U +#define GPIO_IDATA_ID14_MSK BIT(GPIO_IDATA_ID14_POS) + +#define GPIO_IDATA_ID13_POS 13U +#define GPIO_IDATA_ID13_MSK BIT(GPIO_IDATA_ID13_POS) + +#define GPIO_IDATA_ID12_POS 12U +#define GPIO_IDATA_ID12_MSK BIT(GPIO_IDATA_ID12_POS) + +#define GPIO_IDATA_ID11_POS 11U +#define GPIO_IDATA_ID11_MSK BIT(GPIO_IDATA_ID11_POS) + +#define GPIO_IDATA_ID10_POS 10U +#define GPIO_IDATA_ID10_MSK BIT(GPIO_IDATA_ID10_POS) + +#define GPIO_IDATA_ID9_POS 9U +#define GPIO_IDATA_ID9_MSK BIT(GPIO_IDATA_ID9_POS) + +#define GPIO_IDATA_ID8_POS 8U +#define GPIO_IDATA_ID8_MSK BIT(GPIO_IDATA_ID8_POS) + +#define GPIO_IDATA_ID7_POS 7U +#define GPIO_IDATA_ID7_MSK BIT(GPIO_IDATA_ID7_POS) + +#define GPIO_IDATA_ID6_POS 6U +#define GPIO_IDATA_ID6_MSK BIT(GPIO_IDATA_ID6_POS) + +#define GPIO_IDATA_ID5_POS 5U +#define GPIO_IDATA_ID5_MSK BIT(GPIO_IDATA_ID5_POS) + +#define GPIO_IDATA_ID4_POS 4U +#define GPIO_IDATA_ID4_MSK BIT(GPIO_IDATA_ID4_POS) + +#define GPIO_IDATA_ID3_POS 3U +#define GPIO_IDATA_ID3_MSK BIT(GPIO_IDATA_ID3_POS) + +#define GPIO_IDATA_ID2_POS 2U +#define GPIO_IDATA_ID2_MSK BIT(GPIO_IDATA_ID2_POS) + +#define GPIO_IDATA_ID1_POS 1U +#define GPIO_IDATA_ID1_MSK BIT(GPIO_IDATA_ID1_POS) + +#define GPIO_IDATA_ID0_POS 0U +#define GPIO_IDATA_ID0_MSK BIT(GPIO_IDATA_ID0_POS) + +/****************** Bit definition for GPIO_ODATA register ************************/ + +#define GPIO_ODATA_OD15_POS 15U +#define GPIO_ODATA_OD15_MSK BIT(GPIO_ODATA_OD15_POS) + +#define GPIO_ODATA_OD14_POS 14U +#define GPIO_ODATA_OD14_MSK BIT(GPIO_ODATA_OD14_POS) + +#define GPIO_ODATA_OD13_POS 13U +#define GPIO_ODATA_OD13_MSK BIT(GPIO_ODATA_OD13_POS) + +#define GPIO_ODATA_OD12_POS 12U +#define GPIO_ODATA_OD12_MSK BIT(GPIO_ODATA_OD12_POS) + +#define GPIO_ODATA_OD11_POS 11U +#define GPIO_ODATA_OD11_MSK BIT(GPIO_ODATA_OD11_POS) + +#define GPIO_ODATA_OD10_POS 10U +#define GPIO_ODATA_OD10_MSK BIT(GPIO_ODATA_OD10_POS) + +#define GPIO_ODATA_OD9_POS 9U +#define GPIO_ODATA_OD9_MSK BIT(GPIO_ODATA_OD9_POS) + +#define GPIO_ODATA_OD8_POS 8U +#define GPIO_ODATA_OD8_MSK BIT(GPIO_ODATA_OD8_POS) + +#define GPIO_ODATA_OD7_POS 7U +#define GPIO_ODATA_OD7_MSK BIT(GPIO_ODATA_OD7_POS) + +#define GPIO_ODATA_OD6_POS 6U +#define GPIO_ODATA_OD6_MSK BIT(GPIO_ODATA_OD6_POS) + +#define GPIO_ODATA_OD5_POS 5U +#define GPIO_ODATA_OD5_MSK BIT(GPIO_ODATA_OD5_POS) + +#define GPIO_ODATA_OD4_POS 4U +#define GPIO_ODATA_OD4_MSK BIT(GPIO_ODATA_OD4_POS) + +#define GPIO_ODATA_OD3_POS 3U +#define GPIO_ODATA_OD3_MSK BIT(GPIO_ODATA_OD3_POS) + +#define GPIO_ODATA_OD2_POS 2U +#define GPIO_ODATA_OD2_MSK BIT(GPIO_ODATA_OD2_POS) + +#define GPIO_ODATA_OD1_POS 1U +#define GPIO_ODATA_OD1_MSK BIT(GPIO_ODATA_OD1_POS) + +#define GPIO_ODATA_OD0_POS 0U +#define GPIO_ODATA_OD0_MSK BIT(GPIO_ODATA_OD0_POS) + +/****************** Bit definition for GPIO_BSBR register ************************/ + +#define GPIO_BSBR_BR15_POS 31U +#define GPIO_BSBR_BR15_MSK BIT(GPIO_BSBR_BR15_POS) + +#define GPIO_BSBR_BR14_POS 30U +#define GPIO_BSBR_BR14_MSK BIT(GPIO_BSBR_BR14_POS) + +#define GPIO_BSBR_BR13_POS 29U +#define GPIO_BSBR_BR13_MSK BIT(GPIO_BSBR_BR13_POS) + +#define GPIO_BSBR_BR12_POS 28U +#define GPIO_BSBR_BR12_MSK BIT(GPIO_BSBR_BR12_POS) + +#define GPIO_BSBR_BR11_POS 27U +#define GPIO_BSBR_BR11_MSK BIT(GPIO_BSBR_BR11_POS) + +#define GPIO_BSBR_BR10_POS 26U +#define GPIO_BSBR_BR10_MSK BIT(GPIO_BSBR_BR10_POS) + +#define GPIO_BSBR_BR9_POS 25U +#define GPIO_BSBR_BR9_MSK BIT(GPIO_BSBR_BR9_POS) + +#define GPIO_BSBR_BR8_POS 24U +#define GPIO_BSBR_BR8_MSK BIT(GPIO_BSBR_BR8_POS) + +#define GPIO_BSBR_BR7_POS 23U +#define GPIO_BSBR_BR7_MSK BIT(GPIO_BSBR_BR7_POS) + +#define GPIO_BSBR_BR6_POS 22U +#define GPIO_BSBR_BR6_MSK BIT(GPIO_BSBR_BR6_POS) + +#define GPIO_BSBR_BR5_POS 21U +#define GPIO_BSBR_BR5_MSK BIT(GPIO_BSBR_BR5_POS) + +#define GPIO_BSBR_BR4_POS 20U +#define GPIO_BSBR_BR4_MSK BIT(GPIO_BSBR_BR4_POS) + +#define GPIO_BSBR_BR3_POS 19U +#define GPIO_BSBR_BR3_MSK BIT(GPIO_BSBR_BR3_POS) + +#define GPIO_BSBR_BR2_POS 18U +#define GPIO_BSBR_BR2_MSK BIT(GPIO_BSBR_BR2_POS) + +#define GPIO_BSBR_BR1_POS 17U +#define GPIO_BSBR_BR1_MSK BIT(GPIO_BSBR_BR1_POS) + +#define GPIO_BSBR_BR0_POS 16U +#define GPIO_BSBR_BR0_MSK BIT(GPIO_BSBR_BR0_POS) + +#define GPIO_BSBR_BS15_POS 15U +#define GPIO_BSBR_BS15_MSK BIT(GPIO_BSBR_BS15_POS) + +#define GPIO_BSBR_BS14_POS 14U +#define GPIO_BSBR_BS14_MSK BIT(GPIO_BSBR_BS14_POS) + +#define GPIO_BSBR_BS13_POS 13U +#define GPIO_BSBR_BS13_MSK BIT(GPIO_BSBR_BS13_POS) + +#define GPIO_BSBR_BS12_POS 12U +#define GPIO_BSBR_BS12_MSK BIT(GPIO_BSBR_BS12_POS) + +#define GPIO_BSBR_BS11_POS 11U +#define GPIO_BSBR_BS11_MSK BIT(GPIO_BSBR_BS11_POS) + +#define GPIO_BSBR_BS10_POS 10U +#define GPIO_BSBR_BS10_MSK BIT(GPIO_BSBR_BS10_POS) + +#define GPIO_BSBR_BS9_POS 9U +#define GPIO_BSBR_BS9_MSK BIT(GPIO_BSBR_BS9_POS) + +#define GPIO_BSBR_BS8_POS 8U +#define GPIO_BSBR_BS8_MSK BIT(GPIO_BSBR_BS8_POS) + +#define GPIO_BSBR_BS7_POS 7U +#define GPIO_BSBR_BS7_MSK BIT(GPIO_BSBR_BS7_POS) + +#define GPIO_BSBR_BS6_POS 6U +#define GPIO_BSBR_BS6_MSK BIT(GPIO_BSBR_BS6_POS) + +#define GPIO_BSBR_BS5_POS 5U +#define GPIO_BSBR_BS5_MSK BIT(GPIO_BSBR_BS5_POS) + +#define GPIO_BSBR_BS4_POS 4U +#define GPIO_BSBR_BS4_MSK BIT(GPIO_BSBR_BS4_POS) + +#define GPIO_BSBR_BS3_POS 3U +#define GPIO_BSBR_BS3_MSK BIT(GPIO_BSBR_BS3_POS) + +#define GPIO_BSBR_BS2_POS 2U +#define GPIO_BSBR_BS2_MSK BIT(GPIO_BSBR_BS2_POS) + +#define GPIO_BSBR_BS1_POS 1U +#define GPIO_BSBR_BS1_MSK BIT(GPIO_BSBR_BS1_POS) + +#define GPIO_BSBR_BS0_POS 0U +#define GPIO_BSBR_BS0_MSK BIT(GPIO_BSBR_BS0_POS) + +/****************** Bit definition for GPIO_LCK register ************************/ + +#define GPIO_LCK_LCKK_POS 16U +#define GPIO_LCK_LCKK_MSK BIT(GPIO_LCK_LCKK_POS) + +#define GPIO_LCK_LCK15_POS 15U +#define GPIO_LCK_LCK15_MSK BIT(GPIO_LCK_LCK15_POS) + +#define GPIO_LCK_LCK14_POS 14U +#define GPIO_LCK_LCK14_MSK BIT(GPIO_LCK_LCK14_POS) + +#define GPIO_LCK_LCK13_POS 13U +#define GPIO_LCK_LCK13_MSK BIT(GPIO_LCK_LCK13_POS) + +#define GPIO_LCK_LCK12_POS 12U +#define GPIO_LCK_LCK12_MSK BIT(GPIO_LCK_LCK12_POS) + +#define GPIO_LCK_LCK11_POS 11U +#define GPIO_LCK_LCK11_MSK BIT(GPIO_LCK_LCK11_POS) + +#define GPIO_LCK_LCK10_POS 10U +#define GPIO_LCK_LCK10_MSK BIT(GPIO_LCK_LCK10_POS) + +#define GPIO_LCK_LCK9_POS 9U +#define GPIO_LCK_LCK9_MSK BIT(GPIO_LCK_LCK9_POS) + +#define GPIO_LCK_LCK8_POS 8U +#define GPIO_LCK_LCK8_MSK BIT(GPIO_LCK_LCK8_POS) + +#define GPIO_LCK_LCK7_POS 7U +#define GPIO_LCK_LCK7_MSK BIT(GPIO_LCK_LCK7_POS) + +#define GPIO_LCK_LCK6_POS 6U +#define GPIO_LCK_LCK6_MSK BIT(GPIO_LCK_LCK6_POS) + +#define GPIO_LCK_LCK5_POS 5U +#define GPIO_LCK_LCK5_MSK BIT(GPIO_LCK_LCK5_POS) + +#define GPIO_LCK_LCK4_POS 4U +#define GPIO_LCK_LCK4_MSK BIT(GPIO_LCK_LCK4_POS) + +#define GPIO_LCK_LCK3_POS 3U +#define GPIO_LCK_LCK3_MSK BIT(GPIO_LCK_LCK3_POS) + +#define GPIO_LCK_LCK2_POS 2U +#define GPIO_LCK_LCK2_MSK BIT(GPIO_LCK_LCK2_POS) + +#define GPIO_LCK_LCK1_POS 1U +#define GPIO_LCK_LCK1_MSK BIT(GPIO_LCK_LCK1_POS) + +#define GPIO_LCK_LCK0_POS 0U +#define GPIO_LCK_LCK0_MSK BIT(GPIO_LCK_LCK0_POS) + +/****************** Bit definition for GPIO_MOD register ************************/ + +#define GPIO_MOD_MOD15_POSS 30U +#define GPIO_MOD_MOD15_POSE 31U +#define GPIO_MOD_MOD15_MSK BITS(GPIO_MOD_MOD15_POSS,GPIO_MOD_MOD15_POSE) + +#define GPIO_MOD_MOD14_POSS 28U +#define GPIO_MOD_MOD14_POSE 29U +#define GPIO_MOD_MOD14_MSK BITS(GPIO_MOD_MOD14_POSS,GPIO_MOD_MOD14_POSE) + +#define GPIO_MOD_MOD13_POSS 26U +#define GPIO_MOD_MOD13_POSE 27U +#define GPIO_MOD_MOD13_MSK BITS(GPIO_MOD_MOD13_POSS,GPIO_MOD_MOD13_POSE) + +#define GPIO_MOD_MOD12_POSS 24U +#define GPIO_MOD_MOD12_POSE 25U +#define GPIO_MOD_MOD12_MSK BITS(GPIO_MOD_MOD12_POSS,GPIO_MOD_MOD12_POSE) + +#define GPIO_MOD_MOD11_POSS 22U +#define GPIO_MOD_MOD11_POSE 23U +#define GPIO_MOD_MOD11_MSK BITS(GPIO_MOD_MOD11_POSS,GPIO_MOD_MOD11_POSE) + +#define GPIO_MOD_MOD10_POSS 20U +#define GPIO_MOD_MOD10_POSE 21U +#define GPIO_MOD_MOD10_MSK BITS(GPIO_MOD_MOD10_POSS,GPIO_MOD_MOD10_POSE) + +#define GPIO_MOD_MOD9_POSS 18U +#define GPIO_MOD_MOD9_POSE 19U +#define GPIO_MOD_MOD9_MSK BITS(GPIO_MOD_MOD9_POSS,GPIO_MOD_MOD9_POSE) + +#define GPIO_MOD_MOD8_POSS 16U +#define GPIO_MOD_MOD8_POSE 17U +#define GPIO_MOD_MOD8_MSK BITS(GPIO_MOD_MOD8_POSS,GPIO_MOD_MOD8_POSE) + +#define GPIO_MOD_MOD7_POSS 14U +#define GPIO_MOD_MOD7_POSE 15U +#define GPIO_MOD_MOD7_MSK BITS(GPIO_MOD_MOD7_POSS,GPIO_MOD_MOD7_POSE) + +#define GPIO_MOD_MOD6_POSS 12U +#define GPIO_MOD_MOD6_POSE 13U +#define GPIO_MOD_MOD6_MSK BITS(GPIO_MOD_MOD6_POSS,GPIO_MOD_MOD6_POSE) + +#define GPIO_MOD_MOD5_POSS 10U +#define GPIO_MOD_MOD5_POSE 11U +#define GPIO_MOD_MOD5_MSK BITS(GPIO_MOD_MOD5_POSS,GPIO_MOD_MOD5_POSE) + +#define GPIO_MOD_MOD4_POSS 8U +#define GPIO_MOD_MOD4_POSE 9U +#define GPIO_MOD_MOD4_MSK BITS(GPIO_MOD_MOD4_POSS,GPIO_MOD_MOD4_POSE) + +#define GPIO_MOD_MOD3_POSS 6U +#define GPIO_MOD_MOD3_POSE 7U +#define GPIO_MOD_MOD3_MSK BITS(GPIO_MOD_MOD3_POSS,GPIO_MOD_MOD3_POSE) + +#define GPIO_MOD_MOD2_POSS 4U +#define GPIO_MOD_MOD2_POSE 5U +#define GPIO_MOD_MOD2_MSK BITS(GPIO_MOD_MOD2_POSS,GPIO_MOD_MOD2_POSE) + +#define GPIO_MOD_MOD1_POSS 2U +#define GPIO_MOD_MOD1_POSE 3U +#define GPIO_MOD_MOD1_MSK BITS(GPIO_MOD_MOD1_POSS,GPIO_MOD_MOD1_POSE) + +#define GPIO_MOD_MOD0_POSS 0U +#define GPIO_MOD_MOD0_POSE 1U +#define GPIO_MOD_MOD0_MSK BITS(GPIO_MOD_MOD0_POSS,GPIO_MOD_MOD0_POSE) + +/****************** Bit definition for GPIO_PUD register ************************/ + +#define GPIO_PUD_PUD15_POSS 30U +#define GPIO_PUD_PUD15_POSE 31U +#define GPIO_PUD_PUD15_MSK BITS(GPIO_PUD_PUD15_POSS,GPIO_PUD_PUD15_POSE) + +#define GPIO_PUD_PUD14_POSS 28U +#define GPIO_PUD_PUD14_POSE 29U +#define GPIO_PUD_PUD14_MSK BITS(GPIO_PUD_PUD14_POSS,GPIO_PUD_PUD14_POSE) + +#define GPIO_PUD_PUD13_POSS 26U +#define GPIO_PUD_PUD13_POSE 27U +#define GPIO_PUD_PUD13_MSK BITS(GPIO_PUD_PUD13_POSS,GPIO_PUD_PUD13_POSE) + +#define GPIO_PUD_PUD12_POSS 24U +#define GPIO_PUD_PUD12_POSE 25U +#define GPIO_PUD_PUD12_MSK BITS(GPIO_PUD_PUD12_POSS,GPIO_PUD_PUD12_POSE) + +#define GPIO_PUD_PUD11_POSS 22U +#define GPIO_PUD_PUD11_POSE 23U +#define GPIO_PUD_PUD11_MSK BITS(GPIO_PUD_PUD11_POSS,GPIO_PUD_PUD11_POSE) + +#define GPIO_PUD_PUD10_POSS 20U +#define GPIO_PUD_PUD10_POSE 21U +#define GPIO_PUD_PUD10_MSK BITS(GPIO_PUD_PUD10_POSS,GPIO_PUD_PUD10_POSE) + +#define GPIO_PUD_PUD9_POSS 18U +#define GPIO_PUD_PUD9_POSE 19U +#define GPIO_PUD_PUD9_MSK BITS(GPIO_PUD_PUD9_POSS,GPIO_PUD_PUD9_POSE) + +#define GPIO_PUD_PUD8_POSS 16U +#define GPIO_PUD_PUD8_POSE 17U +#define GPIO_PUD_PUD8_MSK BITS(GPIO_PUD_PUD8_POSS,GPIO_PUD_PUD8_POSE) + +#define GPIO_PUD_PUD7_POSS 14U +#define GPIO_PUD_PUD7_POSE 15U +#define GPIO_PUD_PUD7_MSK BITS(GPIO_PUD_PUD7_POSS,GPIO_PUD_PUD7_POSE) + +#define GPIO_PUD_PUD6_POSS 12U +#define GPIO_PUD_PUD6_POSE 13U +#define GPIO_PUD_PUD6_MSK BITS(GPIO_PUD_PUD6_POSS,GPIO_PUD_PUD6_POSE) + +#define GPIO_PUD_PUD5_POSS 10U +#define GPIO_PUD_PUD5_POSE 11U +#define GPIO_PUD_PUD5_MSK BITS(GPIO_PUD_PUD5_POSS,GPIO_PUD_PUD5_POSE) + +#define GPIO_PUD_PUD4_POSS 8U +#define GPIO_PUD_PUD4_POSE 9U +#define GPIO_PUD_PUD4_MSK BITS(GPIO_PUD_PUD4_POSS,GPIO_PUD_PUD4_POSE) + +#define GPIO_PUD_PUD3_POSS 6U +#define GPIO_PUD_PUD3_POSE 7U +#define GPIO_PUD_PUD3_MSK BITS(GPIO_PUD_PUD3_POSS,GPIO_PUD_PUD3_POSE) + +#define GPIO_PUD_PUD2_POSS 4U +#define GPIO_PUD_PUD2_POSE 5U +#define GPIO_PUD_PUD2_MSK BITS(GPIO_PUD_PUD2_POSS,GPIO_PUD_PUD2_POSE) + +#define GPIO_PUD_PUD1_POSS 2U +#define GPIO_PUD_PUD1_POSE 3U +#define GPIO_PUD_PUD1_MSK BITS(GPIO_PUD_PUD1_POSS,GPIO_PUD_PUD1_POSE) + +#define GPIO_PUD_PUD0_POSS 0U +#define GPIO_PUD_PUD0_POSE 1U +#define GPIO_PUD_PUD0_MSK BITS(GPIO_PUD_PUD0_POSS,GPIO_PUD_PUD0_POSE) + +/****************** Bit definition for GPIO_OT register ************************/ + +#define GPIO_OT_OT15_POS 15U +#define GPIO_OT_OT15_MSK BIT(GPIO_OT_OT15_POS) + +#define GPIO_OT_OT14_POS 14U +#define GPIO_OT_OT14_MSK BIT(GPIO_OT_OT14_POS) + +#define GPIO_OT_OT13_POS 13U +#define GPIO_OT_OT13_MSK BIT(GPIO_OT_OT13_POS) + +#define GPIO_OT_OT12_POS 12U +#define GPIO_OT_OT12_MSK BIT(GPIO_OT_OT12_POS) + +#define GPIO_OT_OT11_POS 11U +#define GPIO_OT_OT11_MSK BIT(GPIO_OT_OT11_POS) + +#define GPIO_OT_OT10_POS 10U +#define GPIO_OT_OT10_MSK BIT(GPIO_OT_OT10_POS) + +#define GPIO_OT_OT9_POS 9U +#define GPIO_OT_OT9_MSK BIT(GPIO_OT_OT9_POS) + +#define GPIO_OT_OT8_POS 8U +#define GPIO_OT_OT8_MSK BIT(GPIO_OT_OT8_POS) + +#define GPIO_OT_OT7_POS 7U +#define GPIO_OT_OT7_MSK BIT(GPIO_OT_OT7_POS) + +#define GPIO_OT_OT6_POS 6U +#define GPIO_OT_OT6_MSK BIT(GPIO_OT_OT6_POS) + +#define GPIO_OT_OT5_POS 5U +#define GPIO_OT_OT5_MSK BIT(GPIO_OT_OT5_POS) + +#define GPIO_OT_OT4_POS 4U +#define GPIO_OT_OT4_MSK BIT(GPIO_OT_OT4_POS) + +#define GPIO_OT_OT3_POS 3U +#define GPIO_OT_OT3_MSK BIT(GPIO_OT_OT3_POS) + +#define GPIO_OT_OT2_POS 2U +#define GPIO_OT_OT2_MSK BIT(GPIO_OT_OT2_POS) + +#define GPIO_OT_OT1_POS 1U +#define GPIO_OT_OT1_MSK BIT(GPIO_OT_OT1_POS) + +#define GPIO_OT_OT0_POS 0U +#define GPIO_OT_OT0_MSK BIT(GPIO_OT_OT0_POS) + +#define GPIO_OT_OT_POSS 0U +#define GPIO_OT_OT_POSE 15U +#define GPIO_OT_OT_MSK BITS(GPIO_OT_OT_POSS,GPIO_OT_OT_POSE) + +/****************** Bit definition for GPIO_DS register ************************/ + +#define GPIO_DS_DS15_POS 15U +#define GPIO_DS_DS15_MSK BIT(GPIO_DS_DS15_POS) + +#define GPIO_DS_DS14_POS 14U +#define GPIO_DS_DS14_MSK BIT(GPIO_DS_DS14_POS) + +#define GPIO_DS_DS13_POS 13U +#define GPIO_DS_DS13_MSK BIT(GPIO_DS_DS13_POS) + +#define GPIO_DS_DS12_POS 12U +#define GPIO_DS_DS12_MSK BIT(GPIO_DS_DS12_POS) + +#define GPIO_DS_DS11_POS 11U +#define GPIO_DS_DS11_MSK BIT(GPIO_DS_DS11_POS) + +#define GPIO_DS_DS10_POS 10U +#define GPIO_DS_DS10_MSK BIT(GPIO_DS_DS10_POS) + +#define GPIO_DS_DS9_POS 9U +#define GPIO_DS_DS9_MSK BIT(GPIO_DS_DS9_POS) + +#define GPIO_DS_DS8_POS 8U +#define GPIO_DS_DS8_MSK BIT(GPIO_DS_DS8_POS) + +#define GPIO_DS_DS7_POS 7U +#define GPIO_DS_DS7_MSK BIT(GPIO_DS_DS7_POS) + +#define GPIO_DS_DS6_POS 6U +#define GPIO_DS_DS6_MSK BIT(GPIO_DS_DS6_POS) + +#define GPIO_DS_DS5_POS 5U +#define GPIO_DS_DS5_MSK BIT(GPIO_DS_DS5_POS) + +#define GPIO_DS_DS4_POS 4U +#define GPIO_DS_DS4_MSK BIT(GPIO_DS_DS4_POS) + +#define GPIO_DS_DS3_POS 3U +#define GPIO_DS_DS3_MSK BIT(GPIO_DS_DS3_POS) + +#define GPIO_DS_DS2_POS 2U +#define GPIO_DS_DS2_MSK BIT(GPIO_DS_DS2_POS) + +#define GPIO_DS_DS1_POS 1U +#define GPIO_DS_DS1_MSK BIT(GPIO_DS_DS1_POS) + +#define GPIO_DS_DS0_POS 0U +#define GPIO_DS_DS0_MSK BIT(GPIO_DS_DS0_POS) + +#define GPIO_DS_DS_POSS 0U +#define GPIO_DS_DS_POSE 15U +#define GPIO_DS_DS_MSK BITS(GPIO_DS_DS_POSS,GPIO_DS_DS_POSE) + +/****************** Bit definition for GPIO_FIR register ************************/ + +#define GPIO_FIR_FIR15_POS 15U +#define GPIO_FIR_FIR15_MSK BIT(GPIO_FIR_FIR15_POS) + +#define GPIO_FIR_FIR14_POS 14U +#define GPIO_FIR_FIR14_MSK BIT(GPIO_FIR_FIR14_POS) + +#define GPIO_FIR_FIR13_POS 13U +#define GPIO_FIR_FIR13_MSK BIT(GPIO_FIR_FIR13_POS) + +#define GPIO_FIR_FIR12_POS 12U +#define GPIO_FIR_FIR12_MSK BIT(GPIO_FIR_FIR12_POS) + +#define GPIO_FIR_FIR11_POS 11U +#define GPIO_FIR_FIR11_MSK BIT(GPIO_FIR_FIR11_POS) + +#define GPIO_FIR_FIR10_POS 10U +#define GPIO_FIR_FIR10_MSK BIT(GPIO_FIR_FIR10_POS) + +#define GPIO_FIR_FIR9_POS 9U +#define GPIO_FIR_FIR9_MSK BIT(GPIO_FIR_FIR9_POS) + +#define GPIO_FIR_FIR8_POS 8U +#define GPIO_FIR_FIR8_MSK BIT(GPIO_FIR_FIR8_POS) + +#define GPIO_FIR_FIR7_POS 7U +#define GPIO_FIR_FIR7_MSK BIT(GPIO_FIR_FIR7_POS) + +#define GPIO_FIR_FIR6_POS 6U +#define GPIO_FIR_FIR6_MSK BIT(GPIO_FIR_FIR6_POS) + +#define GPIO_FIR_FIR5_POS 5U +#define GPIO_FIR_FIR5_MSK BIT(GPIO_FIR_FIR5_POS) + +#define GPIO_FIR_FIR4_POS 4U +#define GPIO_FIR_FIR4_MSK BIT(GPIO_FIR_FIR4_POS) + +#define GPIO_FIR_FIR3_POS 3U +#define GPIO_FIR_FIR3_MSK BIT(GPIO_FIR_FIR3_POS) + +#define GPIO_FIR_FIR2_POS 2U +#define GPIO_FIR_FIR2_MSK BIT(GPIO_FIR_FIR2_POS) + +#define GPIO_FIR_FIR1_POS 1U +#define GPIO_FIR_FIR1_MSK BIT(GPIO_FIR_FIR1_POS) + +#define GPIO_FIR_FIR0_POS 0U +#define GPIO_FIR_FIR0_MSK BIT(GPIO_FIR_FIR0_POS) + +/****************** Bit definition for GPIO_IST register ************************/ + +#define GPIO_IST_IST15_POS 15U +#define GPIO_IST_IST15_MSK BIT(GPIO_IST_IST15_POS) + +#define GPIO_IST_IST14_POS 14U +#define GPIO_IST_IST14_MSK BIT(GPIO_IST_IST14_POS) + +#define GPIO_IST_IST13_POS 13U +#define GPIO_IST_IST13_MSK BIT(GPIO_IST_IST13_POS) + +#define GPIO_IST_IST12_POS 12U +#define GPIO_IST_IST12_MSK BIT(GPIO_IST_IST12_POS) + +#define GPIO_IST_IST11_POS 11U +#define GPIO_IST_IST11_MSK BIT(GPIO_IST_IST11_POS) + +#define GPIO_IST_IST10_POS 10U +#define GPIO_IST_IST10_MSK BIT(GPIO_IST_IST10_POS) + +#define GPIO_IST_IST9_POS 9U +#define GPIO_IST_IST9_MSK BIT(GPIO_IST_IST9_POS) + +#define GPIO_IST_IST8_POS 8U +#define GPIO_IST_IST8_MSK BIT(GPIO_IST_IST8_POS) + +#define GPIO_IST_IST7_POS 7U +#define GPIO_IST_IST7_MSK BIT(GPIO_IST_IST7_POS) + +#define GPIO_IST_IST6_POS 6U +#define GPIO_IST_IST6_MSK BIT(GPIO_IST_IST6_POS) + +#define GPIO_IST_IST5_POS 5U +#define GPIO_IST_IST5_MSK BIT(GPIO_IST_IST5_POS) + +#define GPIO_IST_IST4_POS 4U +#define GPIO_IST_IST4_MSK BIT(GPIO_IST_IST4_POS) + +#define GPIO_IST_IST3_POS 3U +#define GPIO_IST_IST3_MSK BIT(GPIO_IST_IST3_POS) + +#define GPIO_IST_IST2_POS 2U +#define GPIO_IST_IST2_MSK BIT(GPIO_IST_IST2_POS) + +#define GPIO_IST_IST1_POS 1U +#define GPIO_IST_IST1_MSK BIT(GPIO_IST_IST1_POS) + +#define GPIO_IST_IST0_POS 0U +#define GPIO_IST_IST0_MSK BIT(GPIO_IST_IST0_POS) + +#define GPIO_IST_IST_POSS 0U +#define GPIO_IST_IST_POSE 15U +#define GPIO_IST_IST_MSK BITS(GPIO_IST_IST_POSS, GPIO_IST_IST_POSE) + +/****************** Bit definition for GPIO_AFL register ************************/ + +#define GPIO_AFL_AF7_POSS 28U +#define GPIO_AFL_AF7_POSE 31U +#define GPIO_AFL_AF7_MSK BITS(GPIO_AFL_AF7_POSS,GPIO_AFL_AF7_POSE) + +#define GPIO_AFL_AF6_POSS 24U +#define GPIO_AFL_AF6_POSE 27U +#define GPIO_AFL_AF6_MSK BITS(GPIO_AFL_AF6_POSS,GPIO_AFL_AF6_POSE) + +#define GPIO_AFL_AF5_POSS 20U +#define GPIO_AFL_AF5_POSE 23U +#define GPIO_AFL_AF5_MSK BITS(GPIO_AFL_AF5_POSS,GPIO_AFL_AF5_POSE) + +#define GPIO_AFL_AF4_POSS 16U +#define GPIO_AFL_AF4_POSE 19U +#define GPIO_AFL_AF4_MSK BITS(GPIO_AFL_AF4_POSS,GPIO_AFL_AF4_POSE) + +#define GPIO_AFL_AF3_POSS 12U +#define GPIO_AFL_AF3_POSE 15U +#define GPIO_AFL_AF3_MSK BITS(GPIO_AFL_AF3_POSS,GPIO_AFL_AF3_POSE) + +#define GPIO_AFL_AF2_POSS 8U +#define GPIO_AFL_AF2_POSE 11U +#define GPIO_AFL_AF2_MSK BITS(GPIO_AFL_AF2_POSS,GPIO_AFL_AF2_POSE) + +#define GPIO_AFL_AF1_POSS 4U +#define GPIO_AFL_AF1_POSE 7U +#define GPIO_AFL_AF1_MSK BITS(GPIO_AFL_AF1_POSS,GPIO_AFL_AF1_POSE) + +#define GPIO_AFL_AF0_POSS 0U +#define GPIO_AFL_AF0_POSE 3U +#define GPIO_AFL_AF0_MSK BITS(GPIO_AFL_AF0_POSS,GPIO_AFL_AF0_POSE) + +/****************** Bit definition for GPIO_AFH register ************************/ + +#define GPIO_AFH_AF15_POSS 28U +#define GPIO_AFH_AF15_POSE 31U +#define GPIO_AFH_AF15_MSK BITS(GPIO_AFH_AF15_POSS,GPIO_AFH_AF15_POSE) + +#define GPIO_AFH_AF14_POSS 24U +#define GPIO_AFH_AF14_POSE 27U +#define GPIO_AFH_AF14_MSK BITS(GPIO_AFH_AF14_POSS,GPIO_AFH_AF14_POSE) + +#define GPIO_AFH_AF13_POSS 20U +#define GPIO_AFH_AF13_POSE 23U +#define GPIO_AFH_AF13_MSK BITS(GPIO_AFH_AF13_POSS,GPIO_AFH_AF13_POSE) + +#define GPIO_AFH_AF12_POSS 16U +#define GPIO_AFH_AF12_POSE 19U +#define GPIO_AFH_AF12_MSK BITS(GPIO_AFH_AF12_POSS,GPIO_AFH_AF12_POSE) + +#define GPIO_AFH_AF11_POSS 12U +#define GPIO_AFH_AF11_POSE 15U +#define GPIO_AFH_AF11_MSK BITS(GPIO_AFH_AF11_POSS,GPIO_AFH_AF11_POSE) + +#define GPIO_AFH_AF10_POSS 8U +#define GPIO_AFH_AF10_POSE 11U +#define GPIO_AFH_AF10_MSK BITS(GPIO_AFH_AF10_POSS,GPIO_AFH_AF10_POSE) + +#define GPIO_AFH_AF9_POSS 4U +#define GPIO_AFH_AF9_POSE 7U +#define GPIO_AFH_AF9_MSK BITS(GPIO_AFH_AF9_POSS,GPIO_AFH_AF9_POSE) + +#define GPIO_AFH_AF8_POSS 0U +#define GPIO_AFH_AF8_POSE 3U +#define GPIO_AFH_AF8_MSK BITS(GPIO_AFH_AF8_POSS,GPIO_AFH_AF8_POSE) + +typedef struct +{ + __I uint32_t IDATA; + __IO uint32_t ODATA; + __O uint32_t BSBR; + __IO uint32_t LCK; + __IO uint32_t MOD; + __IO uint32_t PUD; + __IO uint32_t OT; + __IO uint32_t DS; + __IO uint32_t FIR; + __IO uint32_t IST; + __IO uint32_t AFL; + __IO uint32_t AFH; +} GPIO_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_hdiv.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_hdiv.h new file mode 100644 index 0000000000000000000000000000000000000000..d1ffd0d102ecff98692b9b2f6a9ad493c35896eb --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_hdiv.h @@ -0,0 +1,75 @@ +/** + ************************************************************************************** + * @file REG_HDIV.h + * @brief HDIV Head File + * + * @version V0.01 + * @data 12/3/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __hdiv_H__ +#define __hdiv_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for HDIV_DIVDR register ************************/ + +#define HDIV_DIVDR_DIVS_POSS 0U +#define HDIV_DIVDR_DIVS_POSE 31U +#define HDIV_DIVDR_DIVD_MSK BITS(HDIV_DIVDR_DIVD_POSS,HDIV_DIVDR_DIVD_POSE) + +/****************** Bit definition for HDIV_DIVSR register ************************/ + +#define HDIV_DIVSR_DIVS_POSS 0U +#define HDIV_DIVSR_DIVS_POSE 31U +#define HDIV_DIVSR_DIVS_MSK BITS(HDIV_DIVSR_DIVS_POSS,HDIV_DIVSR_DIVS_POSE) + +/****************** Bit definition for HDIV_DIVQR register ************************/ + +#define HDIV_DIVQR_DIVQ_POSS 0U +#define HDIV_DIVQR_DIVQ_POSE 31U +#define HDIV_DIVQR_DIVQ_MSK BITS(HDIV_DIVQR_DIVQ_POSS,HDIV_DIVQR_DIVQ_POSE) + +/****************** Bit definition for HDIV_DIVRR register ************************/ + +#define HDIV_DIVRR_DIVR_POSS 0U +#define HDIV_DIVRR_DIVR_POSE 31U +#define HDIV_DIVRR_DIVR_MSK BITS(HDIV_DIVRR_DIVR_POSS,HDIV_DIVRR_DIVR_POSE) + +/****************** Bit definition for HDIV_DIVSTAT register ************************/ + +#define HDIV_DIVSTAT_SIGN_POS 2U +#define HDIV_DIVSTAT_SIGN_MSK BIT(HDIV_DIVSTAT_SIGN_POS) + +#define HDIV_DIVSTAT_DIV0_POS 1U +#define HDIV_DIVSTAT_DIV0_MSK BIT(HDIV_DIVSTAT_DIV0_POS) + +#define HDIV_DIVSTAT_BUSY_POS 0U +#define HDIV_DIVSTAT_BUSY_MSK BIT(HDIV_DIVSTAT_BUSY_POS) + +typedef struct +{ + __IO uint32_t DIVDR; + __IO uint32_t DIVSR; + __I uint32_t DIVQR; + __I uint32_t DIVRR; + __I uint32_t DIVSTAT; +} HDIV_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_i2c.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..887eb01e0363751a70792031988f9c99770a1bb0 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_i2c.h @@ -0,0 +1,623 @@ +/** + ************************************************************************************** + * @file REG_I2C.h + * @brief I2C Head File + * + * @version V0.01 + * @date 4/12/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __REG_I2C_H__ +#define __REG_I2C_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for I2C_CON1 register ************************/ + +#define I2C_CON1_PECEN_POS 23U +#define I2C_CON1_PECEN_MSK BIT(I2C_CON1_PECEN_POS) + +#define I2C_CON1_ALERTEN_POS 22U +#define I2C_CON1_ALERTEN_MSK BIT(I2C_CON1_ALERTEN_POS) + +#define I2C_CON1_SMBDEN_POS 21U +#define I2C_CON1_SMBDEN_MSK BIT(I2C_CON1_SMBDEN_POS) + +#define I2C_CON1_SMBHEN_POS 20U +#define I2C_CON1_SMBHEN_MSK BIT(I2C_CON1_SMBHEN_POS) + +#define I2C_CON1_GCEN_POS 19U +#define I2C_CON1_GCEN_MSK BIT(I2C_CON1_GCEN_POS) + +#define I2C_CON1_NOSTRETCH_POS 17U +#define I2C_CON1_NOSTRETCH_MSK BIT(I2C_CON1_NOSTRETCH_POS) + +#define I2C_CON1_SBC_POS 16U +#define I2C_CON1_SBC_MSK BIT(I2C_CON1_SBC_POS) + +#define I2C_CON1_RXDMAEN_POS 15U +#define I2C_CON1_RXDMAEN_MSK BIT(I2C_CON1_RXDMAEN_POS) + +#define I2C_CON1_TXDMAEN_POS 14U +#define I2C_CON1_TXDMAEN_MSK BIT(I2C_CON1_TXDMAEN_POS) + +#define I2C_CON1_DNF_POSS 8U +#define I2C_CON1_DNF_POSE 11U +#define I2C_CON1_DNF_MSK BITS(I2C_CON1_DNF_POSS,I2C_CON1_DNF_POSE) + +#define I2C_CON1_PE_POS 0U +#define I2C_CON1_PE_MSK BIT(I2C_CON1_PE_POS) + +/****************** Bit definition for I2C_CON2 register ************************/ + +#define I2C_CON2_ACK_UPD_POS 29U +#define I2C_CON2_ACK_UPD_MSK BIT(I2C_CON2_ACK_UPD_POS) + +#define I2C_CON2_HOLDACK_POS 28U +#define I2C_CON2_HOLDACK_MSK BIT(I2C_CON2_HOLDACK_POS) + +#define I2C_CON2_PECBYTE_POS 26U +#define I2C_CON2_PECBYTE_MSK BIT(I2C_CON2_PECBYTE_POS) + +#define I2C_CON2_AUTOEND_POS 25U +#define I2C_CON2_AUTOEND_MSK BIT(I2C_CON2_AUTOEND_POS) + +#define I2C_CON2_RELOAD_POS 24U +#define I2C_CON2_RELOAD_MSK BIT(I2C_CON2_RELOAD_POS) + +#define I2C_CON2_NBYTES_POSS 16U +#define I2C_CON2_NBYTES_POSE 23U +#define I2C_CON2_NBYTES_MSK BITS(I2C_CON2_NBYTES_POSS,I2C_CON2_NBYTES_POSE) + +#define I2C_CON2_NACK_POS 15U +#define I2C_CON2_NACK_MSK BIT(I2C_CON2_NACK_POS) + +#define I2C_CON2_STOP_POS 14U +#define I2C_CON2_STOP_MSK BIT(I2C_CON2_STOP_POS) + +#define I2C_CON2_START_POS 13U +#define I2C_CON2_START_MSK BIT(I2C_CON2_START_POS) + +#define I2C_CON2_HEAD10R_POS 12U +#define I2C_CON2_HEAD10R_MSK BIT(I2C_CON2_HEAD10R_POS) + +#define I2C_CON2_ADD10_POS 11U +#define I2C_CON2_ADD10_MSK BIT(I2C_CON2_ADD10_POS) + +#define I2C_CON2_RD_WRN_POS 10U +#define I2C_CON2_RD_WRN_MSK BIT(I2C_CON2_RD_WRN_POS) + +#define I2C_CON2_SADD_POSS 0U +#define I2C_CON2_SADD_POSE 9U +#define I2C_CON2_SADD_MSK BITS(I2C_CON2_SADD_POSS,I2C_CON2_SADD_POSE) + +/****************** Bit definition for I2C_ADDR1 register ************************/ + +#define I2C_ADDR1_OA1EN_POS 15U +#define I2C_ADDR1_OA1EN_MSK BIT(I2C_ADDR1_OA1EN_POS) + +#define I2C_ADDR1_OA1MODE_POS 10U +#define I2C_ADDR1_OA1MODE_MSK BIT(I2C_ADDR1_OA1MODE_POS) + +#define I2C_ADDR1_OA1_POSS 0U +#define I2C_ADDR1_OA1_POSE 9U +#define I2C_ADDR1_OA1_MSK BITS(I2C_ADDR1_OA1_POSS,I2C_ADDR1_OA1_POSE) + +/****************** Bit definition for I2C_ADDR2 register ************************/ + +#define I2C_ADDR2_OA2EN_POS 15U +#define I2C_ADDR2_OA2EN_MSK BIT(I2C_ADDR2_OA2EN_POS) + +#define I2C_ADDR2_OA2MSK_POSS 8U +#define I2C_ADDR2_OA2MSK_POSE 10U +#define I2C_ADDR2_OA2MSK_MSK BITS(I2C_ADDR2_OA2MSK_POSS,I2C_ADDR2_OA2MSK_POSE) + +#define I2C_ADDR2_OA2_POSS 1U +#define I2C_ADDR2_OA2_POSE 7U +#define I2C_ADDR2_OA2_MSK BITS(I2C_ADDR2_OA2_POSS,I2C_ADDR2_OA2_POSE) + +/****************** Bit definition for I2C_TIMINGR register ************************/ + +#define I2C_TIMINGR_PRESC_POSS 28U +#define I2C_TIMINGR_PRESC_POSE 31U +#define I2C_TIMINGR_PRESC_MSK BITS(I2C_TIMINGR_PRESC_POSS,I2C_TIMINGR_PRESC_POSE) + +#define I2C_TIMINGR_SCLDEL_POSS 20U +#define I2C_TIMINGR_SCLDEL_POSE 23U +#define I2C_TIMINGR_SCLDEL_MSK BITS(I2C_TIMINGR_SCLDEL_POSS,I2C_TIMINGR_SCLDEL_POSE) + +#define I2C_TIMINGR_SDADEL_POSS 16U +#define I2C_TIMINGR_SDADEL_POSE 19U +#define I2C_TIMINGR_SDADEL_MSK BITS(I2C_TIMINGR_SDADEL_POSS,I2C_TIMINGR_SDADEL_POSE) + +#define I2C_TIMINGR_SCLH_POSS 8U +#define I2C_TIMINGR_SCLH_POSE 15U +#define I2C_TIMINGR_SCLH_MSK BITS(I2C_TIMINGR_SCLH_POSS,I2C_TIMINGR_SCLH_POSE) + +#define I2C_TIMINGR_SCLL_POSS 0U +#define I2C_TIMINGR_SCLL_POSE 7U +#define I2C_TIMINGR_SCLL_MSK BITS(I2C_TIMINGR_SCLL_POSS,I2C_TIMINGR_SCLL_POSE) + +/****************** Bit definition for I2C_TIMEOUTR register ************************/ + +#define I2C_TIMEOUTR_TEXTEN_POS 31U +#define I2C_TIMEOUTR_TEXTEN_MSK BIT(I2C_TIMEOUTR_TEXTEN_POS) + +#define I2C_TIMEOUTR_TIMEOUTB_POSS 16U +#define I2C_TIMEOUTR_TIMEOUTB_POSE 27U +#define I2C_TIMEOUTR_TIMEOUTB_MSK BITS(I2C_TIMEOUTR_TIMEOUTB_POSS,I2C_TIMEOUTR_TIMEOUTB_POSE) + +#define I2C_TIMEOUTR_TIMEOUTEN_POS 15U +#define I2C_TIMEOUTR_TIMEOUTEN_MSK BIT(I2C_TIMEOUTR_TIMEOUTEN_POS) + +#define I2C_TIMEOUTR_TIDLE_POS 12U +#define I2C_TIMEOUTR_TIDLE_MSK BIT(I2C_TIMEOUTR_TIDLE_POS) + +#define I2C_TIMEOUTR_TIMEOUTA_POSS 0U +#define I2C_TIMEOUTR_TIMEOUTA_POSE 11U +#define I2C_TIMEOUTR_TIMEOUTA_MSK BITS(I2C_TIMEOUTR_TIMEOUTA_POSS,I2C_TIMEOUTR_TIMEOUTA_POSE) + +/****************** Bit definition for I2C_STAT register ************************/ + +#define I2C_STAT_ADDCODE_POSS 17U +#define I2C_STAT_ADDCODE_POSE 23U +#define I2C_STAT_ADDCODE_MSK BITS(I2C_STAT_ADDCODE_POSS,I2C_STAT_ADDCODE_POSE) + +#define I2C_STAT_DIR_POS 16U +#define I2C_STAT_DIR_MSK BIT(I2C_STAT_DIR_POS) + +#define I2C_STAT_BUSY_POS 15U +#define I2C_STAT_BUSY_MSK BIT(I2C_STAT_BUSY_POS) + +#define I2C_STAT_TCR_POS 11U +#define I2C_STAT_TCR_MSK BIT(I2C_STAT_TCR_POS) + +#define I2C_STAT_TC_POS 10U +#define I2C_STAT_TC_MSK BIT(I2C_STAT_TC_POS) + +#define I2C_STAT_RXTH_POS 9U +#define I2C_STAT_RXTH_MSK BIT(I2C_STAT_RXTH_POS) + +#define I2C_STAT_RXUD_POS 8U +#define I2C_STAT_RXUD_MSK BIT(I2C_STAT_RXUD_POS) + +#define I2C_STAT_RXOV_POS 7U +#define I2C_STAT_RXOV_MSK BIT(I2C_STAT_RXOV_POS) + +#define I2C_STAT_RXF_POS 6U +#define I2C_STAT_RXF_MSK BIT(I2C_STAT_RXF_POS) + +#define I2C_STAT_RXE_POS 5U +#define I2C_STAT_RXE_MSK BIT(I2C_STAT_RXE_POS) + +#define I2C_STAT_TXTH_POS 4U +#define I2C_STAT_TXTH_MSK BIT(I2C_STAT_TXTH_POS) + +#define I2C_STAT_TXUD_POS 3U +#define I2C_STAT_TXUD_MSK BIT(I2C_STAT_TXUD_POS) + +#define I2C_STAT_TXOV_POS 2U +#define I2C_STAT_TXOV_MSK BIT(I2C_STAT_TXOV_POS) + +#define I2C_STAT_TXF_POS 1U +#define I2C_STAT_TXF_MSK BIT(I2C_STAT_TXF_POS) + +#define I2C_STAT_TXE_POS 0U +#define I2C_STAT_TXE_MSK BIT(I2C_STAT_TXE_POS) + +/****************** Bit definition for I2C_FCON register ************************/ + +#define I2C_FCON_RXFTH_POSS 14U +#define I2C_FCON_RXFTH_POSE 15U +#define I2C_FCON_RXFTH_MSK BITS(I2C_FCON_RXFTH_POSS,I2C_FCON_RXFTH_POSE) + +#define I2C_FCON_RXFRST_POS 13U +#define I2C_FCON_RXFRST_MSK BIT(I2C_FCON_RXFRST_POS) + +#define I2C_FCON_RXFLV_POSS 8U +#define I2C_FCON_RXFLV_POSE 12U +#define I2C_FCON_RXFLV_MSK BITS(I2C_FCON_RXFLV_POSS,I2C_FCON_RXFLV_POSE) + +#define I2C_FCON_TXFTH_POSS 6U +#define I2C_FCON_TXFTH_POSE 7U +#define I2C_FCON_TXFTH_MSK BITS(I2C_FCON_TXFTH_POSS,I2C_FCON_TXFTH_POSE) + +#define I2C_FCON_TXFRST_POS 5U +#define I2C_FCON_TXFRST_MSK BIT(I2C_FCON_TXFRST_POS) + +#define I2C_FCON_TXFLV_POSS 0U +#define I2C_FCON_TXFLV_POSE 4U +#define I2C_FCON_TXFLV_MSK BITS(I2C_FCON_TXFLV_POSS,I2C_FCON_TXFLV_POSE) + +/****************** Bit definition for I2C_PECR register ************************/ + +#define I2C_PECR_PEC_POSS 0U +#define I2C_PECR_PEC_POSE 7U +#define I2C_PECR_PEC_MSK BITS(I2C_PECR_PEC_POSS,I2C_PECR_PEC_POSE) + +/****************** Bit definition for I2C_RXDATA register ************************/ + +#define I2C_RXDATA_RXDATA_POSS 0U +#define I2C_RXDATA_RXDATA_POSE 7U +#define I2C_RXDATA_RXDATA_MSK BITS(I2C_RXDATA_RXDATA_POSS,I2C_RXDATA_RXDATA_POSE) + +/****************** Bit definition for I2C_TXDATA register ************************/ + +#define I2C_TXDATA_TXDATA_POSS 0U +#define I2C_TXDATA_TXDATA_POSE 7U +#define I2C_TXDATA_TXDATA_MSK BITS(I2C_TXDATA_TXDATA_POSS,I2C_TXDATA_TXDATA_POSE) + +/****************** Bit definition for I2C_IER register ************************/ + +#define I2C_IER_ALERTIE_POS 20U +#define I2C_IER_ALERTIE_MSK BIT(I2C_IER_ALERTIE_POS) + +#define I2C_IER_TOUTIE_POS 19U +#define I2C_IER_TOUTIE_MSK BIT(I2C_IER_TOUTIE_POS) + +#define I2C_IER_PECEIE_POS 18U +#define I2C_IER_PECEIE_MSK BIT(I2C_IER_PECEIE_POS) + +#define I2C_IER_ARLOIE_POS 17U +#define I2C_IER_ARLOIE_MSK BIT(I2C_IER_ARLOIE_POS) + +#define I2C_IER_BERRIE_POS 16U +#define I2C_IER_BERRIE_MSK BIT(I2C_IER_BERRIE_POS) + +#define I2C_IER_STOPIE_POS 14U +#define I2C_IER_STOPIE_MSK BIT(I2C_IER_STOPIE_POS) + +#define I2C_IER_NACKIE_POS 13U +#define I2C_IER_NACKIE_MSK BIT(I2C_IER_NACKIE_POS) + +#define I2C_IER_ADDRIE_POS 12U +#define I2C_IER_ADDRIE_MSK BIT(I2C_IER_ADDRIE_POS) + +#define I2C_IER_TCRIE_POS 11U +#define I2C_IER_TCRIE_MSK BIT(I2C_IER_TCRIE_POS) + +#define I2C_IER_TCIE_POS 10U +#define I2C_IER_TCIE_MSK BIT(I2C_IER_TCIE_POS) + +#define I2C_IER_RXTHIE_POS 9U +#define I2C_IER_RXTHIE_MSK BIT(I2C_IER_RXTHIE_POS) + +#define I2C_IER_RXUDIE_POS 8U +#define I2C_IER_RXUDIE_MSK BIT(I2C_IER_RXUDIE_POS) + +#define I2C_IER_RXOVIE_POS 7U +#define I2C_IER_RXOVIE_MSK BIT(I2C_IER_RXOVIE_POS) + +#define I2C_IER_RXFIE_POS 6U +#define I2C_IER_RXFIE_MSK BIT(I2C_IER_RXFIE_POS) + +#define I2C_IER_TXTHIE_POS 4U +#define I2C_IER_TXTHIE_MSK BIT(I2C_IER_TXTHIE_POS) + +#define I2C_IER_TXUDIE_POS 3U +#define I2C_IER_TXUDIE_MSK BIT(I2C_IER_TXUDIE_POS) + +#define I2C_IER_TXOVIE_POS 2U +#define I2C_IER_TXOVIE_MSK BIT(I2C_IER_TXOVIE_POS) + +#define I2C_IER_TXEIE_POS 0U +#define I2C_IER_TXEIE_MSK BIT(I2C_IER_TXEIE_POS) + +/****************** Bit definition for I2C_IDR register ************************/ + +#define I2C_IDR_ALERTID_POS 20U +#define I2C_IDR_ALERTID_MSK BIT(I2C_IDR_ALERTID_POS) + +#define I2C_IDR_TOUTID_POS 19U +#define I2C_IDR_TOUTID_MSK BIT(I2C_IDR_TOUTID_POS) + +#define I2C_IDR_PECEID_POS 18U +#define I2C_IDR_PECEID_MSK BIT(I2C_IDR_PECEID_POS) + +#define I2C_IDR_ARLOID_POS 17U +#define I2C_IDR_ARLOID_MSK BIT(I2C_IDR_ARLOID_POS) + +#define I2C_IDR_BERRID_POS 16U +#define I2C_IDR_BERRID_MSK BIT(I2C_IDR_BERRID_POS) + +#define I2C_IDR_STOPID_POS 14U +#define I2C_IDR_STOPID_MSK BIT(I2C_IDR_STOPID_POS) + +#define I2C_IDR_NACKID_POS 13U +#define I2C_IDR_NACKID_MSK BIT(I2C_IDR_NACKID_POS) + +#define I2C_IDR_ADDRID_POS 12U +#define I2C_IDR_ADDRID_MSK BIT(I2C_IDR_ADDRID_POS) + +#define I2C_IDR_TCRID_POS 11U +#define I2C_IDR_TCRID_MSK BIT(I2C_IDR_TCRID_POS) + +#define I2C_IDR_TCID_POS 10U +#define I2C_IDR_TCID_MSK BIT(I2C_IDR_TCID_POS) + +#define I2C_IDR_RXTHID_POS 9U +#define I2C_IDR_RXTHID_MSK BIT(I2C_IDR_RXTHID_POS) + +#define I2C_IDR_RXUDID_POS 8U +#define I2C_IDR_RXUDID_MSK BIT(I2C_IDR_RXUDID_POS) + +#define I2C_IDR_RXOVID_POS 7U +#define I2C_IDR_RXOVID_MSK BIT(I2C_IDR_RXOVID_POS) + +#define I2C_IDR_RXFID_POS 6U +#define I2C_IDR_RXFID_MSK BIT(I2C_IDR_RXFID_POS) + +#define I2C_IDR_TXTHID_POS 4U +#define I2C_IDR_TXTHID_MSK BIT(I2C_IDR_TXTHID_POS) + +#define I2C_IDR_TXUDID_POS 3U +#define I2C_IDR_TXUDID_MSK BIT(I2C_IDR_TXUDID_POS) + +#define I2C_IDR_TXOVID_POS 2U +#define I2C_IDR_TXOVID_MSK BIT(I2C_IDR_TXOVID_POS) + +#define I2C_IDR_TXEID_POS 0U +#define I2C_IDR_TXEID_MSK BIT(I2C_IDR_TXEID_POS) + +/****************** Bit definition for I2C_IVS register ************************/ + +#define I2C_IVS_ALERTIV_POS 20U +#define I2C_IVS_ALERTIV_MSK BIT(I2C_IVS_ALERTIV_POS) + +#define I2C_IVS_TOUTIV_POS 19U +#define I2C_IVS_TOUTIV_MSK BIT(I2C_IVS_TOUTIV_POS) + +#define I2C_IVS_PECEIV_POS 18U +#define I2C_IVS_PECEIV_MSK BIT(I2C_IVS_PECEIV_POS) + +#define I2C_IVS_ARLOIV_POS 17U +#define I2C_IVS_ARLOIV_MSK BIT(I2C_IVS_ARLOIV_POS) + +#define I2C_IVS_BERRIV_POS 16U +#define I2C_IVS_BERRIV_MSK BIT(I2C_IVS_BERRIV_POS) + +#define I2C_IVS_STOPIV_POS 14U +#define I2C_IVS_STOPIV_MSK BIT(I2C_IVS_STOPIV_POS) + +#define I2C_IVS_NACKIV_POS 13U +#define I2C_IVS_NACKIV_MSK BIT(I2C_IVS_NACKIV_POS) + +#define I2C_IVS_ADDRIV_POS 12U +#define I2C_IVS_ADDRIV_MSK BIT(I2C_IVS_ADDRIV_POS) + +#define I2C_IVS_TCRIV_POS 11U +#define I2C_IVS_TCRIV_MSK BIT(I2C_IVS_TCRIV_POS) + +#define I2C_IVS_TCIV_POS 10U +#define I2C_IVS_TCIV_MSK BIT(I2C_IVS_TCIV_POS) + +#define I2C_IVS_RXTHIV_POS 9U +#define I2C_IVS_RXTHIV_MSK BIT(I2C_IVS_RXTHIV_POS) + +#define I2C_IVS_RXUDIV_POS 8U +#define I2C_IVS_RXUDIV_MSK BIT(I2C_IVS_RXUDIV_POS) + +#define I2C_IVS_RXOVIV_POS 7U +#define I2C_IVS_RXOVIV_MSK BIT(I2C_IVS_RXOVIV_POS) + +#define I2C_IVS_RXFIV_POS 6U +#define I2C_IVS_RXFIV_MSK BIT(I2C_IVS_RXFIV_POS) + +#define I2C_IVS_TXTHIV_POS 4U +#define I2C_IVS_TXTHIV_MSK BIT(I2C_IVS_TXTHIV_POS) + +#define I2C_IVS_TXUDIV_POS 3U +#define I2C_IVS_TXUDIV_MSK BIT(I2C_IVS_TXUDIV_POS) + +#define I2C_IVS_TXOVIV_POS 2U +#define I2C_IVS_TXOVIV_MSK BIT(I2C_IVS_TXOVIV_POS) + +#define I2C_IVS_TXEIV_POS 0U +#define I2C_IVS_TXEIV_MSK BIT(I2C_IVS_TXEIV_POS) + +/****************** Bit definition for I2C_RIF register ************************/ + +#define I2C_RIF_ALERTRI_POS 20U +#define I2C_RIF_ALERTRI_MSK BIT(I2C_RIF_ALERTRI_POS) + +#define I2C_RIF_TOUTRI_POS 19U +#define I2C_RIF_TOUTRI_MSK BIT(I2C_RIF_TOUTRI_POS) + +#define I2C_RIF_PECERI_POS 18U +#define I2C_RIF_PECERI_MSK BIT(I2C_RIF_PECERI_POS) + +#define I2C_RIF_ARLORI_POS 17U +#define I2C_RIF_ARLORI_MSK BIT(I2C_RIF_ARLORI_POS) + +#define I2C_RIF_BERRRI_POS 16U +#define I2C_RIF_BERRRI_MSK BIT(I2C_RIF_BERRRI_POS) + +#define I2C_RIF_STOPRI_POS 14U +#define I2C_RIF_STOPRI_MSK BIT(I2C_RIF_STOPRI_POS) + +#define I2C_RIF_NACKRI_POS 13U +#define I2C_RIF_NACKRI_MSK BIT(I2C_RIF_NACKRI_POS) + +#define I2C_RIF_ADDRRI_POS 12U +#define I2C_RIF_ADDRRI_MSK BIT(I2C_RIF_ADDRRI_POS) + +#define I2C_RIF_TCRRI_POS 11U +#define I2C_RIF_TCRRI_MSK BIT(I2C_RIF_TCRRI_POS) + +#define I2C_RIF_TCRI_POS 10U +#define I2C_RIF_TCRI_MSK BIT(I2C_RIF_TCRI_POS) + +#define I2C_RIF_RXTHRI_POS 9U +#define I2C_RIF_RXTHRI_MSK BIT(I2C_RIF_RXTHRI_POS) + +#define I2C_RIF_RXUDRI_POS 8U +#define I2C_RIF_RXUDRI_MSK BIT(I2C_RIF_RXUDRI_POS) + +#define I2C_RIF_RXOVRI_POS 7U +#define I2C_RIF_RXOVRI_MSK BIT(I2C_RIF_RXOVRI_POS) + +#define I2C_RIF_RXFRI_POS 6U +#define I2C_RIF_RXFRI_MSK BIT(I2C_RIF_RXFRI_POS) + +#define I2C_RIF_TXTHRI_POS 4U +#define I2C_RIF_TXTHRI_MSK BIT(I2C_RIF_TXTHRI_POS) + +#define I2C_RIF_TXUDRI_POS 3U +#define I2C_RIF_TXUDRI_MSK BIT(I2C_RIF_TXUDRI_POS) + +#define I2C_RIF_TXOVRI_POS 2U +#define I2C_RIF_TXOVRI_MSK BIT(I2C_RIF_TXOVRI_POS) + +#define I2C_RIF_TXERI_POS 0U +#define I2C_RIF_TXERI_MSK BIT(I2C_RIF_TXERI_POS) + +/****************** Bit definition for I2C_IFM register ************************/ + +#define I2C_IFM_ALERTFM_POS 20U +#define I2C_IFM_ALERTFM_MSK BIT(I2C_IFM_ALERTFM_POS) + +#define I2C_IFM_TOUTFM_POS 19U +#define I2C_IFM_TOUTFM_MSK BIT(I2C_IFM_TOUTFM_POS) + +#define I2C_IFM_PECEFM_POS 18U +#define I2C_IFM_PECEFM_MSK BIT(I2C_IFM_PECEFM_POS) + +#define I2C_IFM_ARLOFM_POS 17U +#define I2C_IFM_ARLOFM_MSK BIT(I2C_IFM_ARLOFM_POS) + +#define I2C_IFM_BERRFM_POS 16U +#define I2C_IFM_BERRFM_MSK BIT(I2C_IFM_BERRFM_POS) + +#define I2C_IFM_STOPFM_POS 14U +#define I2C_IFM_STOPFM_MSK BIT(I2C_IFM_STOPFM_POS) + +#define I2C_IFM_NACKFM_POS 13U +#define I2C_IFM_NACKFM_MSK BIT(I2C_IFM_NACKFM_POS) + +#define I2C_IFM_ADDRFM_POS 12U +#define I2C_IFM_ADDRFM_MSK BIT(I2C_IFM_ADDRFM_POS) + +#define I2C_IFM_TCRFM_POS 11U +#define I2C_IFM_TCRFM_MSK BIT(I2C_IFM_TCRFM_POS) + +#define I2C_IFM_TCFM_POS 10U +#define I2C_IFM_TCFM_MSK BIT(I2C_IFM_TCFM_POS) + +#define I2C_IFM_RXTHFM_POS 9U +#define I2C_IFM_RXTHFM_MSK BIT(I2C_IFM_RXTHFM_POS) + +#define I2C_IFM_RXUDFM_POS 8U +#define I2C_IFM_RXUDFM_MSK BIT(I2C_IFM_RXUDFM_POS) + +#define I2C_IFM_RXOVFM_POS 7U +#define I2C_IFM_RXOVFM_MSK BIT(I2C_IFM_RXOVFM_POS) + +#define I2C_IFM_RXFFM_POS 6U +#define I2C_IFM_RXFFM_MSK BIT(I2C_IFM_RXFFM_POS) + +#define I2C_IFM_TXTHFM_POS 4U +#define I2C_IFM_TXTHFM_MSK BIT(I2C_IFM_TXTHFM_POS) + +#define I2C_IFM_TXUDFM_POS 3U +#define I2C_IFM_TXUDFM_MSK BIT(I2C_IFM_TXUDFM_POS) + +#define I2C_IFM_TXOVFM_POS 2U +#define I2C_IFM_TXOVFM_MSK BIT(I2C_IFM_TXOVFM_POS) + +#define I2C_IFM_TXEFM_POS 0U +#define I2C_IFM_TXEFM_MSK BIT(I2C_IFM_TXEFM_POS) + +/****************** Bit definition for I2C_ICR register ************************/ + +#define I2C_ICR_ALERTIC_POS 20U +#define I2C_ICR_ALERTIC_MSK BIT(I2C_ICR_ALERTIC_POS) + +#define I2C_ICR_TOUTIC_POS 19U +#define I2C_ICR_TOUTIC_MSK BIT(I2C_ICR_TOUTIC_POS) + +#define I2C_ICR_PECEIC_POS 18U +#define I2C_ICR_PECEIC_MSK BIT(I2C_ICR_PECEIC_POS) + +#define I2C_ICR_ARLOIC_POS 17U +#define I2C_ICR_ARLOIC_MSK BIT(I2C_ICR_ARLOIC_POS) + +#define I2C_ICR_BERRIC_POS 16U +#define I2C_ICR_BERRIC_MSK BIT(I2C_ICR_BERRIC_POS) + +#define I2C_ICR_STOPIC_POS 14U +#define I2C_ICR_STOPIC_MSK BIT(I2C_ICR_STOPIC_POS) + +#define I2C_ICR_NACKIC_POS 13U +#define I2C_ICR_NACKIC_MSK BIT(I2C_ICR_NACKIC_POS) + +#define I2C_ICR_ADDRIC_POS 12U +#define I2C_ICR_ADDRIC_MSK BIT(I2C_ICR_ADDRIC_POS) + +#define I2C_ICR_TCRIC_POS 11U +#define I2C_ICR_TCRIC_MSK BIT(I2C_ICR_TCRIC_POS) + +#define I2C_ICR_TCIC_POS 10U +#define I2C_ICR_TCIC_MSK BIT(I2C_ICR_TCIC_POS) + +#define I2C_ICR_RXTHIC_POS 9U +#define I2C_ICR_RXTHIC_MSK BIT(I2C_ICR_RXTHIC_POS) + +#define I2C_ICR_RXUDIC_POS 8U +#define I2C_ICR_RXUDIC_MSK BIT(I2C_ICR_RXUDIC_POS) + +#define I2C_ICR_RXOVIC_POS 7U +#define I2C_ICR_RXOVIC_MSK BIT(I2C_ICR_RXOVIC_POS) + +#define I2C_ICR_RXFIC_POS 6U +#define I2C_ICR_RXFIC_MSK BIT(I2C_ICR_RXFIC_POS) + +#define I2C_ICR_TXTHIC_POS 4U +#define I2C_ICR_TXTHIC_MSK BIT(I2C_ICR_TXTHIC_POS) + +#define I2C_ICR_TXUDIC_POS 3U +#define I2C_ICR_TXUDIC_MSK BIT(I2C_ICR_TXUDIC_POS) + +#define I2C_ICR_TXOVIC_POS 2U +#define I2C_ICR_TXOVIC_MSK BIT(I2C_ICR_TXOVIC_POS) + +#define I2C_ICR_TXEIC_POS 0U +#define I2C_ICR_TXEIC_MSK BIT(I2C_ICR_TXEIC_POS) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t ADDR1; + __IO uint32_t ADDR2; + __IO uint32_t TIMINGR; + __IO uint32_t TIMEOUTR; + __I uint32_t STAT; + __IO uint32_t FCON; + __I uint32_t PECR; + __I uint32_t RXDATA; + __O uint32_t TXDATA; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} I2C_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_iwdg.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_iwdg.h new file mode 100644 index 0000000000000000000000000000000000000000..a5c657c89a200c9a6ab8be6ae356e261aefe558b --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_iwdg.h @@ -0,0 +1,73 @@ +/** + ************************************************************************************** + * @file reg_IWDG.h + * @brief IWDG Head File + * + * @version V1.00.01 + * @data 19/10/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __IWDG_H__ +#define __IWDG_H__ + +typedef struct +{ + __O uint32_t KR ; /* 0x00 IWDG_KR - Key register */ + __IO uint32_t PR ; /* 0x04 IWDG_PR - Prescaler register */ + __IO uint32_t RLR ; /* 0x08 IWDG_RLR - Reload register */ + __I uint32_t FR ; /* 0x0C IWDG_SR - Status register */ + __IO uint32_t WINR; /* 0x10 IWDG_WINR - Window register */ +} IWDG_TypeDef; + +/******************************************************************************/ +/* Ȧs줸wq */ +/******************************************************************************/ + +/* #pragma anon_unions */ + +/****************** Bit definition for IWDG_KR register ************************/ + +#define IWDG_KR_KEY_POSS 0U +#define IWDG_KR_KEY_POSE 15U +#define IWDG_KR_KEY_MSK BITS(IWDG_KR_KEY_POSS,IWDG_KR_KEY_POSE) + +/****************** Bit definition for IWDG_PR register ************************/ + +#define IWDG_PR_PR_POSS 0U +#define IWDG_PR_PR_POSE 2U +#define IWDG_PR_PR_MSK BITS(IWDG_PR_PR_POSS,IWDG_PR_PR_POSE) + +/****************** Bit definition for IWDG_RLR register ************************/ + +#define IWDG_RLR_RL_POSS 0U +#define IWDG_RLR_RL_POSE 12U +#define IWDG_RLR_RL_MSK BITS(IWDG_RLR_RL_POSS,IWDG_RLR_RL_POSE) + +/****************** Bit definition for IWDG_FR register ************************/ + +#define IWDG_FR_BUSY_POS 15U +#define IWDG_FR_BUSY_MSK BIT(IWDG_FR_BUSY_POS) + +#define IWDG_FR_STR_POS 12U +#define IWDG_FR_STR_MSK BIT(IWDG_FR_STR_POS) + +#define IWDG_FR_CNT_POSS 0U +#define IWDG_FR_CNT_POSE 11U +#define IWDG_FR_CNT_MSK BITS(IWDG_FR_CNT_POSS,IWDG_FR_CNT_POSE) + +/****************** Bit definition for IWDG_WINR register ************************/ + +#define IWDG_WINR_WIN_POSS 0U +#define IWDG_WINR_WIN_POSE 31U +#define IWDG_WINR_WIN_MSK BITS(IWDG_WINR_WIN_POSS,IWDG_WINR_WIN_POSE) + + +#else +/* */ +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mcm.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mcm.h new file mode 100644 index 0000000000000000000000000000000000000000..ebb675dafe20efdc33ca6bb903ee45352c59c7f3 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mcm.h @@ -0,0 +1,211 @@ +/** + ************************************************************************************** + * @file reg_MCM.h + * @brief MCM Head File + * + * @version V1.00.01 + * @data 19/10/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __MCM_H__ +#define __MCM_H__ + +typedef struct +{ + __IO uint32_t RAMP_INI; // 0x00 MCM Ramp Generator Initialization Register + __IO uint32_t RAMP_IDATA; // 0x04 MCM Ramp Generator Initial Data Register + __IO uint32_t RAMP_DIV; // 0x08 MCM Ramp Clock Divider Register + __IO uint32_t RAMP_SCALE; // 0x0C MCM Ramp Generator Output Scale Register + __IO uint32_t RAMP_STEP; // 0x10 MCM Step Increment of the Ramp Output Register + __IO uint32_t RAMP_SET; // 0x14 MCM Ramp Generator Reference Data Register + __IO uint32_t RAMP_EN; // 0x18 MCM Ramp Generator Enable Register + __I uint32_t RAMP_DO; // 0x1C MCM Ramp Generator Output Register + __IO uint32_t RMAP_CON; // 0x20 MCM Connect Ramp Generator to PI control Register + __IO uint32_t IX_UPD; // 0x24 MCM Inverse Transform Update Register + __IO uint32_t IX_VQ; // 0x28 MCM Inverse Park Transform Vq Input Register + __IO uint32_t IX_VD; // 0x2C MCM Inverse Park Transform Vd Input Register + __I uint32_t IX_VA; // 0x30 MCM Inverse Clarke Transform Va Output Register + __I uint32_t IX_VB; // 0x34 MCM Inverse Clarke Transform Vb Output Register + __I uint32_t IX_VC; // 0x38 MCM Inverse Clarke Transform Vc Output Register + __I uint32_t IX_VALPHA; // 0x3C MCM Inverse Clarke Transform Valpha Output Register + __I uint32_t IX_VBETA; // 0x40 MCM Inverse Clarke Transform Vbeta Output Register + __I uint32_t IX_SVMVA; // 0x44 MCM Inverse Clarke Transform SVPWM Va Output Register + __I uint32_t IX_SVMVB; // 0x48 MCM Inverse Clarke Transform SVPWM Vb Output Register + __I uint32_t IX_SVMVC; // 0x4C MCM Inverse Clarke Transform SVPWM Vc Output Register + __I uint32_t IX_DONE; // 0x50 MCM Inverse Transform Processing Status Register + __I uint32_t IX_SDONE; // 0x54 MCM Inverse SVPWM Process Status Register + __IO uint32_t IX_CON; // 0x58 MCM Connect PI Control To The Inverse Transform Register + __IO uint32_t IX_NORMAL; // 0x5C MCM Normal Clarke Inverse Transform Register + __IO uint32_t X_UPD; // 0x60 MCM Transform Function Update Register + __IO uint32_t X_IA; // 0x64 MCM Clarke Transform Ia Input Register + __IO uint32_t X_IB; // 0x68 MCM Clarke Transform Ib Input Register + __IO uint32_t X_IC; // 0x6C MCM Clarke Transform Ic Input Register + __I uint32_t X_IALPHA; // 0x70 MCM Clarke Transform Ialpha Output Register + __I uint32_t X_IBETA; // 0x74 MCM Clarke Transform Ibeta Output Register + __I uint32_t X_ID; // 0x78 MCM Park Transform Id Output Register + __I uint32_t X_IQ; // 0x7C MCM Park Transform Iq Output Register + __I uint32_t X_DONE; // 0x80 MCM Transform Process Status Register + __IO uint32_t X_CON; // 0x84 MCM Forward Transform Input Source Selection Register + uint32_t REV88; // 0x88 RESERVED + __IO uint32_t PI0_UPD; // 0x8C MCM PI Control 0 Update Register + __IO uint32_t PI0_INI; // 0x90 MCM Initialize PI Control 0 Register + __IO uint32_t PI0_IDATA; // 0x94 MCM PI Control 0 Initial Data Register + __IO uint32_t PI0_ELIMIT; // 0x98 MCM PI Control 0 Error Limit Register + __IO uint32_t PI0_KP; // 0x9C MCM PI Control 0 Kp Coefficient Register + __IO uint32_t PI0_KI; // 0xA0 MCM PI Control 0 Ki Coefficient Register + __IO uint32_t PI0_REF; // 0xA4 MCM PI Control 0 Reference Value Register + __IO uint32_t PI0_ACTUAL; // 0xA8 MCM PI Control 0 Actual Value Register + __IO uint32_t PI0_MIN; // 0xAC MCM PI Control 0 Minimum Output Register + __IO uint32_t PI0_MAX; // 0xB0 MCM PI Control 0 Maximum Output Register + __I uint32_t PI0_DO; // 0xB4 MCM PI Control 0 Data Out Register + __IO uint32_t PI0_OSCALE; // 0xB8 MCM PI Control 0 Data Output Scale Register + __I uint32_t PI_DONE; // 0xBC MCM PI Control Processing Status Register + __IO uint32_t PI1_UPD; // 0xC0 MCM PI Control 1 Update Register + __IO uint32_t PI1_INI; // 0xC4 MCM Initialize PI Control 1 Register + __IO uint32_t PI1_IDATA; // 0xC8 MCM PI Control 1 Initial Data Register + __IO uint32_t PI1_ELIMIT; // 0xCC MCM PI Control 1 Error Limit Register + __IO uint32_t PI1_KP; // 0xD0 MCM PI Control 1 Kp Coefficient Register + __IO uint32_t PI1_KI; // 0xD4 MCM PI Control 1 Ki Coefficient Register + __IO uint32_t PI1_REF; // 0xD8 MCM PI Control 1 Reference Value Register + __IO uint32_t PI1_ACTUAL; // 0xDC MCM PI Control 1 Actual Value Register + __IO uint32_t PI1_MIN; // 0xE0 MCM PI Control 1 Minimum Output Register + __IO uint32_t PI1_MAX; // 0xE4 MCM PI Control 1 Maximum Output Register + __I uint32_t PI1_DO; // 0xE8 MCM PI Control 1 Data Out Register + __IO uint32_t PI1_OSCALE; // 0xEC MCM PI Control 1 Data Output Scale Register + __IO uint32_t PI2_UPD; // 0xF0 MCM PI Control 2 Update Register + __IO uint32_t PI2_INI; // 0xF4 MCM Initialize PI Control 2 Register + __IO uint32_t PI2_IDATA; // 0xF8 MCM PI Control 2 Initial Data Register + __IO uint32_t PI2_ELIMIT; // 0xFC MCM PI Control 2 Error Limit Register + __IO uint32_t PI2_KP; // 0x100 MCM PI Control 2 Kp Coefficient Register + __IO uint32_t PI2_KI; // 0x104 MCM PI Control 2 Ki Coefficient Register + __IO uint32_t PI2_REF; // 0x108 MCM PI Control 2 Reference Value Register + __IO uint32_t PI2_ACTUAL; // 0x10C MCM PI Control 2 Actual Value Register + __IO uint32_t PI2_MIN; // 0x110 MCM PI Control 2 Minimum Output Register + __IO uint32_t PI2_MAX; // 0x114 MCM PI Control 2 Maximum Output Register + __I uint32_t PI2_DO; // 0x118 MCM PI Control 2 Data Out Register + __IO uint32_t PI2_OSCALE; // 0x11C MCM PI Control 2 Data Output Scale Register + __IO uint32_t COR_START; // 0x120 MCM Start CORDIC Calculation Register + __IO uint32_t COR_X; // 0x124 MCM CORDIC X Input Register + __IO uint32_t COR_Y; // 0x128 MCM CORDIC Y Input Register + __I uint32_t COR_RES; // 0x12C MCM CORDIC Result Register + __I uint32_t COR_DONE; // 0x130 MCM CORDIC Processing Status Register + __IO uint32_t COR_CON; // 0x134 MCM CORDIC Input Selection Register + uint32_t REV138; // 0x138 RESERVED + uint32_t REV13C; // 0x13C RESERVED + __IO uint32_t LPFA_INI; // 0x140 MCM LPF A Channel Initialize Register + __IO uint32_t LPFA_UPD; // 0x144 MCM LPF A Channel Update Register + __IO uint32_t LPFA_DIN; // 0x148 MCM LPF A Input Register + __IO uint32_t LPFA_A0; // 0x14C MCM LPF A a0 Coefficient Register + __IO uint32_t LPFA_B0; // 0x150 MCM LPF A b0 Coefficient Register + __IO uint32_t LPFA_B1; // 0x154 MCM LPF A b1 Coefficient Register + + __IO uint32_t LPFA_A0SCALE; // 0x158 MCM LPF A a0 Coefficient Scale Register + __IO uint32_t LPFA_B0SCALE; // 0x15C MCM LPF A b0 Coefficient Scale Register + __IO uint32_t LPFA_B1SCALE; // 0x160 MCM LPF A b1 Coefficient Scale Register + + __I uint32_t LPFA_DO; // 0x164 MCM LPF A Data Output Register + __I uint32_t LPFA_DONE; // 0x168 MCM LPF A Process Status Register + __IO uint32_t LPFB_INI; // 0x16C MCM LPF B Channel Initialize Register + __IO uint32_t LPFB_UPD; // 0x170 MCM LPF B Channel Update Register + __IO uint32_t LPFB_DIN; // 0x174 MCM LPF B Input Register + __IO uint32_t LPFB_A0; // 0x178 MCM LPF B a0 Coefficient Register + __IO uint32_t LPFB_B0; // 0x17C MCM LPF B b0 Coefficient Register + __IO uint32_t LPFB_B1; // 0x180 MCM LPF B b1 Coefficient Register + + __IO uint32_t LPFB_A0SCALE; // 0x184 MCM LPF B a0 Coefficient Scale Register + __IO uint32_t LPFB_B0SCALE; // 0x188 MCM LPF B b0 Coefficient Scale Register + __IO uint32_t LPFB_B1SCALE; // 0x18C MCM LPF B b1 Coefficient Scale Register + + __I uint32_t LPFB_DO; // 0x190 MCM LPF B Data Output Register + __I uint32_t LPFB_DONE; // 0x194 MCM LPF B Process Status Register + __IO uint32_t LPFC_INI; // 0x198 MCM LPF C Channel Initialize Register + __IO uint32_t LPFC_UPD; // 0x19C MCM LPF C Channel Update Register + __IO uint32_t LPFC_DIN; // 0x1A0 MCM LPF C Input Register + __IO uint32_t LPFC_A0; // 0x1A4 MCM LPF C a0 Coefficient Register + __IO uint32_t LPFC_B0; // 0x1A8 MCM LPF C b0 Coefficient Register + __IO uint32_t LPFC_B1; // 0x1AC MCM LPF C b1 Coefficient Register + + __IO uint32_t LPFC_A0SCALE; // 0x1B0 MCM LPF C a0 Coefficient Scale Register + __IO uint32_t LPFC_B0SCALE; // 0x1B4 MCM LPF C b0 Coefficient Scale Register + __IO uint32_t LPFC_B1SCALE; // 0x1B8 MCM LPF C b1 Coefficient Scale Register + + __I uint32_t LPFC_DO; // 0x1BC MCM LPF C Data Output Register + __I uint32_t LPFC_DONE; // 0x1C0 MCM LPF C Process Status Register + __IO uint32_t GL_UPD; // 0x1C4 MCM Global Update Register + __IO uint32_t GL_STAT; // 0x1C8 MCM Global Status Register + __IO uint32_t THETA_SIN; // 0x1CC MCM Sine Angle Register + __IO uint32_t THETA_COS; // 0x1D0 MCM Cosine Angle Register + __IO uint32_t PI_TYPE; // 0x1D4 MCM PI Control Type Register + __IO uint32_t MOTOR_DIR; // 0x1D8 MCM Motor Direction Register + __I uint32_t MCM_VER; // 0x1DC MCM Version Register + __IO uint32_t SMC_UPD; // 0x1E0 MCM Slide Mode Controller Update Register + __IO uint32_t SMC_INI; // 0x1E4 MCM Slide Mode Controller Initialization Register + __IO uint32_t SMC_ALPHAINI; // 0x1E8 MCM Slide Mode Controller Alpha Initial Data Register + __IO uint32_t SMC_BETAINI; // 0x1EC MCM Slide Mode Controller Beta Initial Data Register + __IO uint32_t SMC_A0; // 0x1F0 MCM Slide Mode Controller Dynamic LPF coefficient Register + __IO uint32_t SMC_ELIMIT; // 0x1F4 MCM Slide Mode Controller Error Limit Register + __IO uint32_t SMC_KSLIDE; // 0x1F8 MCM Slide Mode Controller Z Factor Error Amplification Register + __I uint32_t SMC_DONE; // 0x1FC MCM Slide Mode Controller Process Status Register + __IO uint32_t SMC_IEALPHA; // 0x200 MCM SMC Estimated Current Alpha Register + __IO uint32_t SMC_IEBETA; // 0x204 MCM SMC Estimated Current Beta Register + __IO uint32_t SMC_IALPHA; // 0x208 MCM SMC Measured Current Alpha Register + __IO uint32_t SMC_IBETA; // 0x20C MCM SMC Measured Current Beta Register + __IO uint32_t SMC_DISI; // 0x210 MCM SMC Estimated Current Input Selection Register + __I uint32_t SMC_ZALPHA; // 0x214 MCM SMC Z Factor Alpha Register + __I uint32_t SMC_ZBETA; // 0x218 MCM SMC Z Factor Beta Register + __I uint32_t SMC_BEMF1A; // 0x21C MCM SMC Estimated BEMF Alpha Register + __I uint32_t SMC_BEMF1B; // 0x220 MCM SMC Estimated BEMF Beta Register + __I uint32_t SMC_BEMF2A; // 0x224 MCM SMC BEMF Filtered Alpha Register + __I uint32_t SMC_BEMF2B; // 0x228 MCM SMC BEMF Filtered Beta Register + __IO uint32_t SMC_LPFSCALE; // 0x22C MCM SMC LPF Coefficient Scale Factor Register + uint32_t REV230; // 0x230 RESERVED + __IO uint32_t VM_UPD; // 0x234 MCM Virtual Motor Update Register + __IO uint32_t VM_INI; // 0x238 MCM Virtual Motor Initialization Register + __IO uint32_t VM_ALPHAINI; // 0x23C MCM Virtual Motor Initial Data Alpha Register + __IO uint32_t VM_BETAINI; // 0x240 MCM Virtual Motor Initial Data Beta Register + __IO uint32_t VM_KF; // 0x244 MCM Virtual Motor F Constant Register + __IO uint32_t VM_KG; // 0x248 MCM Virtual Motor G Constant Register + __IO uint32_t VM_VALPHA; // 0x24C MCM Virtual Motor Voltage Vector Alpha Register + __IO uint32_t VM_VBETA; // 0x250 MCM Virtual Motor Voltage Vector BETA Register + __IO uint32_t VM_BEMFA; // 0x254 MCM Virtual Motor BEMF Vector Alpha Register + __IO uint32_t VM_BEMFB; // 0x258 MCM Virtual Motor BEMF Vector BETA Register + __IO uint32_t VM_ZALPHA; // 0x25C MCM Virtual Motor Z Vector Alpha Register + __IO uint32_t VM_ZBETA; // 0x260 MCM Virtual Motor Z Vector BETA Register + __IO uint32_t VM_DISZ; // 0x264 MCM Virtual Motor Z Factor Input Selection Register + __I uint32_t VM_DONE; // 0x268 MCM Virtual Motor Process Status Register + __I uint32_t VM_IEALPHA; // 0x26C MCM Virtual Motor Estimated IS Result Alpha Register + __I uint32_t VM_IEBETA; // 0x270 MCM Virtual Motor Estimated IS Result BETA Register + __IO uint32_t VM_CON; // 0x274 MCM Virtual Motor Connect Register + + __IO uint32_t VM_KFSCALE; // 0x278 MCM Virtual Motor F Constant Scale Register + __IO uint32_t VM_KGSCALE; // 0x27C MCM Virtual Motor G Constant Scale Register + __IO uint32_t VM_CONVS; // 0x280 MCM Virtual Motor Voltage Connect Register + + uint32_t REV284; // 0x284 RESERVED + __IO uint32_t SVM_UPD; // 0x288 MCM SVM Update Register + __IO uint32_t SVM_CON; // 0x28C MCM SVM Source Input Select Register + __IO uint32_t SVM_DINA; // 0x290 MCM SVM Phase A Register + __IO uint32_t SVM_DINB; // 0x294 MCM SVM Phase B Register + __IO uint32_t SVM_DINC; // 0x298 MCM SVM Phase C Register +} MCM_TypeDef; + +/******************************************************************************/ +/* Ȧs줸wq */ +/******************************************************************************/ + +/* #pragma anon_unions */ + +/****************** Bit definition for WWDG_CR register ************************/ + + + + +#else +/* */ +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mswd.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mswd.h new file mode 100644 index 0000000000000000000000000000000000000000..3a7d2f5dcf7ae1db494b2e6fb746d1ed20a096b6 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_mswd.h @@ -0,0 +1,58 @@ +/** + ************************************************************************************** + * @file reg_MSWD.h + * @brief WWDG Head File + * + * @version V1.00.01 + * @data 19/10/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __MSWD_H__ +#define __MSWD_H__ + +typedef struct +{ + __IO uint32_t CFG; // 0x00 SW_CFG Serial Wire Configure Register + __IO uint32_t JTAG2SWD; // 0x04 SW_JTAG2SW Serial Wire JTAG2SWD Register + __IO uint32_t LINERESET; // 0x08 SW_LINERESET Serial Wire LINERESET Resister + __O uint32_t STS; // 0x0C SW_STS Serial Wire STATUS Register + __IO uint32_t DP_IDR_ABORT; // 0x10 SW_DP_IDR_ABORT Serial Wire DP R-IDR W-ABORT Register + __IO uint32_t DP_CSR_WCR; // 0x14 SW_DP_CSR_WCR Serial Wire DP R-CSR W-WCR Register + __IO uint32_t DP_RESEND_SELECT; // 0x18 SW_DP_RESEND_SELECT Serial Wire DP R-RESEND W-SELECT Register + __IO uint32_t DP_RDBUF_ROUTESEL; // 0x1C SW_DP_RDBUF_ROUTESEL Serial Wire DP R-RDBUF W-ROUTESEL Register + __IO uint32_t AP_CSW; // 0x20 SW_AP_CSW Serial Wire AP CSW Register + __IO uint32_t AP_TAR; // 0x24 SW_AP_TAR Serial Wire AP TAR Register + __IO uint32_t AP_DRW; // 0x28 SW_AP_DRW Serial Wire AP DRW Register + __IO uint32_t AP_BD0; // 0x2C SW_AP_BD0 Serial Wire AP BD0 Register + __IO uint32_t AP_BD1; // 0x30 SW_AP_BD1 Serial Wire AP BD1 Register + __IO uint32_t AP_BD2; // 0x34 SW_AP_BD2 Serial Wire AP BD2 Register + __IO uint32_t AP_BD3; // 0x38 SW_AP_BD3 Serial Wire AP BD3 Register + __IO uint32_t AP_CFG; // 0x3C SW_AP_CFG Serial Wire AP CFG Register + __IO uint32_t AP_BASE; // 0x40 SW_AP_BASE Serial Wire AP BASE Register + __IO uint32_t AP_IDR; // 0x44 SW_AP_IDR Serial Wire AP IDR Register + uint32_t RES0; // 0x48 + uint32_t RES1; // 0x4C + __IO uint32_t ISP_CMD; // 0x50 SW_ISP_CMD Serial Wire ISP Command Register + __IO uint32_t ISP_DAT; // 0x54 SW_ISP_DAT Serial Wire ISP Data Register +} MSWD_TypeDef; + +/******************************************************************************/ +/* Ȧs줸wq */ +/******************************************************************************/ + +/* #pragma anon_unions */ + +/****************** Bit definition for WWDG_CR register ************************/ + + + + +#else +/* */ +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rcu.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rcu.h new file mode 100644 index 0000000000000000000000000000000000000000..af6a59c419c117717c4c78a7b020e59a70d2461e --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rcu.h @@ -0,0 +1,585 @@ +/** + ************************************************************************************** + * @file REG_RCU.h + * @brief RCU Head File + * + * @version V0.01 + * @date 12/5/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __RCU_H__ +#define __RCU_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for RCU_CON register ************************/ + +#define RCU_CON_SWRDY_POS 24U +#define RCU_CON_SWRDY_MSK BIT(RCU_CON_SWRDY_POS) + +#define RCU_CON_CSSFLG_POS 23U +#define RCU_CON_CSSFLG_MSK BIT(RCU_CON_CSSFLG_POS) + +#define RCU_CON_PLL1RDY_POS 21U +#define RCU_CON_PLL1RDY_MSK BIT(RCU_CON_PLL1RDY_POS) + +#define RCU_CON_PLL0RDY_POS 20U +#define RCU_CON_PLL0RDY_MSK BIT(RCU_CON_PLL0RDY_POS) + +#define RCU_CON_LOSCRDY_POS 19U +#define RCU_CON_LOSCRDY_MSK BIT(RCU_CON_LOSCRDY_POS) + +#define RCU_CON_LRCRDY_POS 18U +#define RCU_CON_LRCRDY_MSK BIT(RCU_CON_LRCRDY_POS) + +#define RCU_CON_HOSCRDY_POS 17U +#define RCU_CON_HOSCRDY_MSK BIT(RCU_CON_HOSCRDY_POS) + +#define RCU_CON_HRCRDY_POS 16U +#define RCU_CON_HRCRDY_MSK BIT(RCU_CON_HRCRDY_POS) + +#define RCU_CON_CSSON_POS 7U +#define RCU_CON_CSSON_MSK BIT(RCU_CON_CSSON_POS) + +#define RCU_CON_PLL1ON_POS 5U +#define RCU_CON_PLL1ON_MSK BIT(RCU_CON_PLL1ON_POS) + +#define RCU_CON_PLL0ON_POS 4U +#define RCU_CON_PLL0ON_MSK BIT(RCU_CON_PLL0ON_POS) + +#define RCU_CON_LOSCON_POS 3U +#define RCU_CON_LOSCON_MSK BIT(RCU_CON_LOSCON_POS) + +#define RCU_CON_LRCON_POS 2U +#define RCU_CON_LRCON_MSK BIT(RCU_CON_LRCON_POS) + +#define RCU_CON_HOSCON_POS 1U +#define RCU_CON_HOSCON_MSK BIT(RCU_CON_HOSCON_POS) + +#define RCU_CON_HRCON_POS 0U +#define RCU_CON_HRCON_MSK BIT(RCU_CON_HRCON_POS) + +/****************** Bit definition for RCU_CFG register ************************/ + +#define RCU_CFG_CKCFG_POS 31U +#define RCU_CFG_CKCFG_MSK BIT(RCU_CFG_CKCFG_POS) + +#define RCU_CFG_MPRE_POSS 28U +#define RCU_CFG_MPRE_POSE 30U +#define RCU_CFG_MPRE_MSK BITS(RCU_CFG_MPRE_POSS,RCU_CFG_MPRE_POSE) + +#define RCU_CFG_MSW_POSS 24U +#define RCU_CFG_MSW_POSE 27U +#define RCU_CFG_MSW_MSK BITS(RCU_CFG_MSW_POSS,RCU_CFG_MSW_POSE) + +#define RCU_CFG_PLLMUL_POSS 17U +#define RCU_CFG_PLLMUL_POSE 21U +#define RCU_CFG_PLLMUL_MSK BITS(RCU_CFG_PLLMUL_POSS,RCU_CFG_PLLMUL_POSE) + +#define RCU_CFG_PLLSRC_POS 16U +#define RCU_CFG_PLLSRC_MSK BIT(RCU_CFG_PLLSRC_POS) + +#define RCU_CFG_HOSCDIV_POSS 12U +#define RCU_CFG_HOSCDIV_POSE 14U +#define RCU_CFG_HOSCDIV_MSK BITS(RCU_CFG_HOSCDIV_POSS,RCU_CFG_HOSCDIV_POSE) + +#define RCU_CFG_PPRE_POSS 8U +#define RCU_CFG_PPRE_POSE 10U +#define RCU_CFG_PPRE_MSK BITS(RCU_CFG_PPRE_POSS,RCU_CFG_PPRE_POSE) + +#define RCU_CFG_HPRE_POSS 4U +#define RCU_CFG_HPRE_POSE 7U +#define RCU_CFG_HPRE_MSK BITS(RCU_CFG_HPRE_POSS,RCU_CFG_HPRE_POSE) + +#define RCU_CFG_SW_POSS 0U +#define RCU_CFG_SW_POSE 2U +#define RCU_CFG_SW_MSK BITS(RCU_CFG_SW_POSS,RCU_CFG_SW_POSE) + +/****************** Bit definition for RCU_STCALIB register ************************/ + +#define RCU_STCALIB_SKEW_POS 30U +#define RCU_STCALIB_SKEW_MSK BIT(RCU_STCALIB_SKEW_POS) + +#define RCU_STCALIB_TENMS_POSS 0U +#define RCU_STCALIB_TENMS_POSE 23U +#define RCU_STCALIB_TENMS_MSK BITS(RCU_STCALIB_TENMS_POSS,RCU_STCALIB_TENMS_POSE) + +/****************** Bit definition for RCU_PSCK register ************************/ + +#define RCU_PSCK_I2S2CKSL_POSS 2U +#define RCU_PSCK_I2S2CKSL_POSE 3U +#define RCU_PSCK_I2S2CKSL_MSK BITS(RCU_PSCK_I2S2CKSL_POSS,RCU_PSCK_I2S2CKSL_POSE) + +#define RCU_PSCK_I2S1CKSL_POSS 0U +#define RCU_PSCK_I2S1CKSL_POSE 1U +#define RCU_PSCK_I2S1CKSL_MSK BITS(RCU_PSCK_I2S1CKSL_POSS,RCU_PSCK_I2S1CKSL_POSE) + +/****************** Bit definition for RCU_AHBRST register ************************/ + +#define RCU_AHBRST_GPDEN_POS 19U +#define RCU_AHBRST_GPDEN_MSK BIT(RCU_AHBRST_GPDEN_POS) + +#define RCU_AHBRST_GPCEN_POS 18U +#define RCU_AHBRST_GPCEN_MSK BIT(RCU_AHBRST_GPCEN_POS) + +#define RCU_AHBRST_GPBEN_POS 17U +#define RCU_AHBRST_GPBEN_MSK BIT(RCU_AHBRST_GPBEN_POS) + +#define RCU_AHBRST_GPAEN_POS 16U +#define RCU_AHBRST_GPAEN_MSK BIT(RCU_AHBRST_GPAEN_POS) + +#define RCU_AHBRST_HDIVEN_POS 15U +#define RCU_AHBRST_HDIVEN_MSK BIT(RCU_AHBRST_HDIVEN_POS) + +#define RCU_AHBRST_USBEN_POS 14U +#define RCU_AHBRST_USBEN_MSK BIT(RCU_AHBRST_USBEN_POS) + +#define RCU_AHBRST_AESEN_POS 13U +#define RCU_AHBRST_AESEN_MSK BIT(RCU_AHBRST_AESEN_POS) + +#define RCU_AHBRST_CRCEN_POS 12U +#define RCU_AHBRST_CRCEN_MSK BIT(RCU_AHBRST_CRCEN_POS) + +#define RCU_AHBRST_RTCEN_POS 6U +#define RCU_AHBRST_RTCEN_MSK BIT(RCU_AHBRST_RTCEN_POS) + +#define RCU_AHBRST_DMA1EN_POS 0U +#define RCU_AHBRST_DMA1EN_MSK BIT(RCU_AHBRST_DMA1EN_POS) + +/****************** Bit definition for RCU_APB1RST register ************************/ + +#define RCU_APB1RST_DACEN_POS 23U +#define RCU_APB1RST_DACEN_MSK BIT(RCU_APB1RST_DACEN_POS) + +#define RCU_APB1RST_I2C2EN_POS 22U +#define RCU_APB1RST_I2C2EN_MSK BIT(RCU_APB1RST_I2C2EN_POS) + +#define RCU_APB1RST_I2C1EN_POS 21U +#define RCU_APB1RST_I2C1EN_MSK BIT(RCU_APB1RST_I2C1EN_POS) + +#define RCU_APB1RST_SUART2EN_POS 20U +#define RCU_APB1RST_SUART2EN_MSK BIT(RCU_APB1RST_SUART2EN_POS) + +#define RCU_APB1RST_SUART1EN_POS 19U +#define RCU_APB1RST_SUART1EN_MSK BIT(RCU_APB1RST_SUART1EN_POS) + +#define RCU_APB1RST_UART3EN_POS 18U +#define RCU_APB1RST_UART3EN_MSK BIT(RCU_APB1RST_UART3EN_POS) + +#define RCU_APB1RST_UART2EN_POS 17U +#define RCU_APB1RST_UART2EN_MSK BIT(RCU_APB1RST_UART2EN_POS) + +#define RCU_APB1RST_SPI2EN_POS 14U +#define RCU_APB1RST_SPI2EN_MSK BIT(RCU_APB1RST_SPI2EN_POS) + +#define RCU_APB1RST_IWDTEN_POS 12U +#define RCU_APB1RST_IWDTEN_MSK BIT(RCU_APB1RST_IWDTEN_POS) + +#define RCU_APB1RST_WWDTEN_POS 11U +#define RCU_APB1RST_WWDTEN_MSK BIT(RCU_APB1RST_WWDTEN_POS) + +#define RCU_APB1RST_BS16T1EN_POS 4U +#define RCU_APB1RST_BS16T1EN_MSK BIT(RCU_APB1RST_BS16T1EN_POS) + +#define RCU_APB1RST_GP16C4T3EN_POS 3U +#define RCU_APB1RST_GP16C4T3EN_MSK BIT(RCU_APB1RST_GP16C4T3EN_POS) + +#define RCU_APB1RST_GP16C4T2EN_POS 2U +#define RCU_APB1RST_GP16C4T2EN_MSK BIT(RCU_APB1RST_GP16C4T2EN_POS) + +#define RCU_APB1RST_GP16C4T1EN_POS 1U +#define RCU_APB1RST_GP16C4T1EN_MSK BIT(RCU_APB1RST_GP16C4T1EN_POS) + +#define RCU_APB1RST_GP32C4T1EN_POS 0U +#define RCU_APB1RST_GP32C4T1EN_MSK BIT(RCU_APB1RST_GP32C4T1EN_POS) + +/****************** Bit definition for RCU_APB2RST register ************************/ + +#define RCU_APB2RST_CMPEN_POS 23U +#define RCU_APB2RST_CMPEN_MSK BIT(RCU_APB2RST_CMPEN_POS) + +#define RCU_APB2RST_GP16C2T4EN_POS 19U +#define RCU_APB2RST_GP16C2T4EN_MSK BIT(RCU_APB2RST_GP16C2T4EN_POS) + +#define RCU_APB2RST_GP16C2T3EN_POS 18U +#define RCU_APB2RST_GP16C2T3EN_MSK BIT(RCU_APB2RST_GP16C2T3EN_POS) + +#define RCU_APB2RST_GP16C2T2EN_POS 17U +#define RCU_APB2RST_GP16C2T2EN_MSK BIT(RCU_APB2RST_GP16C2T2EN_POS) + +#define RCU_APB2RST_GP16C2T1EN_POS 16U +#define RCU_APB2RST_GP16C2T1EN_MSK BIT(RCU_APB2RST_GP16C2T1EN_POS) + +#define RCU_APB2RST_UART1EN_POS 14U +#define RCU_APB2RST_UART1EN_MSK BIT(RCU_APB2RST_UART1EN_POS) + +#define RCU_APB2RST_SPI1EN_POS 12U +#define RCU_APB2RST_SPI1EN_MSK BIT(RCU_APB2RST_SPI1EN_POS) + +#define RCU_APB2RST_AD16C4T1EN_POS 11U +#define RCU_APB2RST_AD16C4T1EN_MSK BIT(RCU_APB2RST_AD16C4T1EN_POS) + +#define RCU_APB2RST_ADCEN_POS 9U +#define RCU_APB2RST_ADCEN_MSK BIT(RCU_APB2RST_ADCEN_POS) + +/****************** Bit definition for RCU_AHBEN register ************************/ + +#define RCU_AHBEN_GPDEN_POS 19U +#define RCU_AHBEN_GPDEN_MSK BIT(RCU_AHBEN_GPDEN_POS) + +#define RCU_AHBEN_GPCEN_POS 18U +#define RCU_AHBEN_GPCEN_MSK BIT(RCU_AHBEN_GPCEN_POS) + +#define RCU_AHBEN_GPBEN_POS 17U +#define RCU_AHBEN_GPBEN_MSK BIT(RCU_AHBEN_GPBEN_POS) + +#define RCU_AHBEN_GPAEN_POS 16U +#define RCU_AHBEN_GPAEN_MSK BIT(RCU_AHBEN_GPAEN_POS) + +#define RCU_AHBEN_HDIVEN_POS 15U +#define RCU_AHBEN_HDIVEN_MSK BIT(RCU_AHBEN_HDIVEN_POS) + +#define RCU_AHBEN_USBEN_POS 14U +#define RCU_AHBEN_USBEN_MSK BIT(RCU_AHBEN_USBEN_POS) + +#define RCU_AHBEN_AESEN_POS 13U +#define RCU_AHBEN_AESEN_MSK BIT(RCU_AHBEN_AESEN_POS) + +#define RCU_AHBEN_CRCEN_POS 12U +#define RCU_AHBEN_CRCEN_MSK BIT(RCU_AHBEN_CRCEN_POS) + +#define RCU_AHBEN_RTCEN_POS 6U +#define RCU_AHBEN_RTCEN_MSK BIT(RCU_AHBEN_RTCEN_POS) + +#define RCU_AHBEN_DMA1EN_POS 0U +#define RCU_AHBEN_DMA1EN_MSK BIT(RCU_AHBEN_DMA1EN_POS) + +/****************** Bit definition for RCU_APB1EN register ************************/ + +#define RCU_APB1EN_DACEN_POS 23U +#define RCU_APB1EN_DACEN_MSK BIT(RCU_APB1EN_DACEN_POS) + +#define RCU_APB1EN_I2C2EN_POS 22U +#define RCU_APB1EN_I2C2EN_MSK BIT(RCU_APB1EN_I2C2EN_POS) + +#define RCU_APB1EN_I2C1EN_POS 21U +#define RCU_APB1EN_I2C1EN_MSK BIT(RCU_APB1EN_I2C1EN_POS) + +#define RCU_APB1EN_SUART2EN_POS 20U +#define RCU_APB1EN_SUART2EN_MSK BIT(RCU_APB1EN_SUART2EN_POS) + +#define RCU_APB1EN_SUART1EN_POS 19U +#define RCU_APB1EN_SUART1EN_MSK BIT(RCU_APB1EN_SUART1EN_POS) + +#define RCU_APB1EN_UART3EN_POS 18U +#define RCU_APB1EN_UART3EN_MSK BIT(RCU_APB1EN_UART3EN_POS) + +#define RCU_APB1EN_UART2EN_POS 17U +#define RCU_APB1EN_UART2EN_MSK BIT(RCU_APB1EN_UART2EN_POS) + +#define RCU_APB1EN_SPI2EN_POS 14U +#define RCU_APB1EN_SPI2EN_MSK BIT(RCU_APB1EN_SPI2EN_POS) + +#define RCU_APB1EN_IWDTEN_POS 12U +#define RCU_APB1EN_IWDTEN_MSK BIT(RCU_APB1EN_IWDTEN_POS) + +#define RCU_APB1EN_WWDTEN_POS 11U +#define RCU_APB1EN_WWDTEN_MSK BIT(RCU_APB1EN_WWDTEN_POS) + +#define RCU_APB1EN_BS16T1EN_POS 4U +#define RCU_APB1EN_BS16T1EN_MSK BIT(RCU_APB1EN_BS16T1EN_POS) + +#define RCU_APB1EN_GP16C4T3EN_POS 3U +#define RCU_APB1EN_GP16C4T3EN_MSK BIT(RCU_APB1EN_GP16C4T3EN_POS) + +#define RCU_APB1EN_GP16C4T2EN_POS 2U +#define RCU_APB1EN_GP16C4T2EN_MSK BIT(RCU_APB1EN_GP16C4T2EN_POS) + +#define RCU_APB1EN_GP16C4T1EN_POS 1U +#define RCU_APB1EN_GP16C4T1EN_MSK BIT(RCU_APB1EN_GP16C4T1EN_POS) + +#define RCU_APB1EN_GP32C4T1EN_POS 0U +#define RCU_APB1EN_GP32C4T1EN_MSK BIT(RCU_APB1EN_GP32C4T1EN_POS) + +/****************** Bit definition for RCU_APB2EN register ************************/ + +#define RCU_APB2EN_CMPEN_POS 23U +#define RCU_APB2EN_CMPEN_MSK BIT(RCU_APB2EN_CMPEN_POS) + +#define RCU_APB2EN_GP16C2T4EN_POS 19U +#define RCU_APB2EN_GP16C2T4EN_MSK BIT(RCU_APB2EN_GP16C2T4EN_POS) + +#define RCU_APB2EN_GP16C2T3EN_POS 18U +#define RCU_APB2EN_GP16C2T3EN_MSK BIT(RCU_APB2EN_GP16C2T3EN_POS) + +#define RCU_APB2EN_GP16C2T2EN_POS 17U +#define RCU_APB2EN_GP16C2T2EN_MSK BIT(RCU_APB2EN_GP16C2T2EN_POS) + +#define RCU_APB2EN_GP16C2T1EN_POS 16U +#define RCU_APB2EN_GP16C2T1EN_MSK BIT(RCU_APB2EN_GP16C2T1EN_POS) + +#define RCU_APB2EN_UART1EN_POS 14U +#define RCU_APB2EN_UART1EN_MSK BIT(RCU_APB2EN_UART1EN_POS) + +#define RCU_APB2EN_SPI1EN_POS 12U +#define RCU_APB2EN_SPI1EN_MSK BIT(RCU_APB2EN_SPI1EN_POS) + +#define RCU_APB2EN_AD16C4T1EN_POS 11U +#define RCU_APB2EN_AD16C4T1EN_MSK BIT(RCU_APB2EN_AD16C4T1EN_POS) + +#define RCU_APB2EN_ADCEN_POS 9U +#define RCU_APB2EN_ADCEN_MSK BIT(RCU_APB2EN_ADCEN_POS) + +/****************** Bit definition for RCU_AHBSL register ************************/ + +#define RCU_AHBSL_GPDEN_POS 19U +#define RCU_AHBSL_GPDEN_MSK BIT(RCU_AHBSL_GPDEN_POS) + +#define RCU_AHBSL_GPCEN_POS 18U +#define RCU_AHBSL_GPCEN_MSK BIT(RCU_AHBSL_GPCEN_POS) + +#define RCU_AHBSL_GPBEN_POS 17U +#define RCU_AHBSL_GPBEN_MSK BIT(RCU_AHBSL_GPBEN_POS) + +#define RCU_AHBSL_GPAEN_POS 16U +#define RCU_AHBSL_GPAEN_MSK BIT(RCU_AHBSL_GPAEN_POS) + +#define RCU_AHBSL_HDIVEN_POS 15U +#define RCU_AHBSL_HDIVEN_MSK BIT(RCU_AHBSL_HDIVEN_POS) + +#define RCU_AHBSL_USBEN_POS 14U +#define RCU_AHBSL_USBEN_MSK BIT(RCU_AHBSL_USBEN_POS) + +#define RCU_AHBSL_AESEN_POS 13U +#define RCU_AHBSL_AESEN_MSK BIT(RCU_AHBSL_AESEN_POS) + +#define RCU_AHBSL_CRCEN_POS 12U +#define RCU_AHBSL_CRCEN_MSK BIT(RCU_AHBSL_CRCEN_POS) + +#define RCU_AHBSL_RTCEN_POS 6U +#define RCU_AHBSL_RTCEN_MSK BIT(RCU_AHBSL_RTCEN_POS) + +#define RCU_AHBSL_DMA1EN_POS 0U +#define RCU_AHBSL_DMA1EN_MSK BIT(RCU_AHBSL_DMA1EN_POS) + +/****************** Bit definition for RCU_APB1SL register ************************/ + +#define RCU_APB1SL_DACEN_POS 23U +#define RCU_APB1SL_DACEN_MSK BIT(RCU_APB1SL_DACEN_POS) + +#define RCU_APB1SL_I2C2EN_POS 22U +#define RCU_APB1SL_I2C2EN_MSK BIT(RCU_APB1SL_I2C2EN_POS) + +#define RCU_APB1SL_I2C1EN_POS 21U +#define RCU_APB1SL_I2C1EN_MSK BIT(RCU_APB1SL_I2C1EN_POS) + +#define RCU_APB1SL_SUART2EN_POS 20U +#define RCU_APB1SL_SUART2EN_MSK BIT(RCU_APB1SL_SUART2EN_POS) + +#define RCU_APB1SL_SUART1EN_POS 19U +#define RCU_APB1SL_SUART1EN_MSK BIT(RCU_APB1SL_SUART1EN_POS) + +#define RCU_APB1SL_UART3EN_POS 18U +#define RCU_APB1SL_UART3EN_MSK BIT(RCU_APB1SL_UART3EN_POS) + +#define RCU_APB1SL_UART2EN_POS 17U +#define RCU_APB1SL_UART2EN_MSK BIT(RCU_APB1SL_UART2EN_POS) + +#define RCU_APB1SL_SPI2EN_POS 14U +#define RCU_APB1SL_SPI2EN_MSK BIT(RCU_APB1SL_SPI2EN_POS) + +#define RCU_APB1SL_IWDTEN_POS 12U +#define RCU_APB1SL_IWDTEN_MSK BIT(RCU_APB1SL_IWDTEN_POS) + +#define RCU_APB1SL_WWDTEN_POS 11U +#define RCU_APB1SL_WWDTEN_MSK BIT(RCU_APB1SL_WWDTEN_POS) + +#define RCU_APB1SL_BS16T1EN_POS 4U +#define RCU_APB1SL_BS16T1EN_MSK BIT(RCU_APB1SL_BS16T1EN_POS) + +#define RCU_APB1SL_GP16C4T3EN_POS 3U +#define RCU_APB1SL_GP16C4T3EN_MSK BIT(RCU_APB1SL_GP16C4T3EN_POS) + +#define RCU_APB1SL_GP16C4T2EN_POS 2U +#define RCU_APB1SL_GP16C4T2EN_MSK BIT(RCU_APB1SL_GP16C4T2EN_POS) + +#define RCU_APB1SL_GP16C4T1EN_POS 1U +#define RCU_APB1SL_GP16C4T1EN_MSK BIT(RCU_APB1SL_GP16C4T1EN_POS) + +#define RCU_APB1SL_GP32C4T1EN_POS 0U +#define RCU_APB1SL_GP32C4T1EN_MSK BIT(RCU_APB1SL_GP32C4T1EN_POS) + +/****************** Bit definition for RCU_APB2SL register ************************/ + +#define RCU_APB2SL_CMPEN_POS 23U +#define RCU_APB2SL_CMPEN_MSK BIT(RCU_APB2SL_CMPEN_POS) + +#define RCU_APB2SL_GP16C2T4EN_POS 19U +#define RCU_APB2SL_GP16C2T4EN_MSK BIT(RCU_APB2SL_GP16C2T4EN_POS) + +#define RCU_APB2SL_GP16C2T3EN_POS 18U +#define RCU_APB2SL_GP16C2T3EN_MSK BIT(RCU_APB2SL_GP16C2T3EN_POS) + +#define RCU_APB2SL_GP16C2T2EN_POS 17U +#define RCU_APB2SL_GP16C2T2EN_MSK BIT(RCU_APB2SL_GP16C2T2EN_POS) + +#define RCU_APB2SL_GP16C2T1EN_POS 16U +#define RCU_APB2SL_GP16C2T1EN_MSK BIT(RCU_APB2SL_GP16C2T1EN_POS) + +#define RCU_APB2SL_UART1EN_POS 14U +#define RCU_APB2SL_UART1EN_MSK BIT(RCU_APB2SL_UART1EN_POS) + +#define RCU_APB2SL_SPI1EN_POS 12U +#define RCU_APB2SL_SPI1EN_MSK BIT(RCU_APB2SL_SPI1EN_POS) + +#define RCU_APB2SL_AD16C4T1EN_POS 11U +#define RCU_APB2SL_AD16C4T1EN_MSK BIT(RCU_APB2SL_AD16C4T1EN_POS) + +#define RCU_APB2SL_ADCEN_POS 9U +#define RCU_APB2SL_ADCEN_MSK BIT(RCU_APB2SL_ADCEN_POS) + +/****************** Bit definition for RCU_AHBDSL register ************************/ + +#define RCU_AHBDSL_GPDEN_POS 19U +#define RCU_AHBDSL_GPDEN_MSK BIT(RCU_AHBDSL_GPDEN_POS) + +#define RCU_AHBDSL_GPCEN_POS 18U +#define RCU_AHBDSL_GPCEN_MSK BIT(RCU_AHBDSL_GPCEN_POS) + +#define RCU_AHBDSL_GPBEN_POS 17U +#define RCU_AHBDSL_GPBEN_MSK BIT(RCU_AHBDSL_GPBEN_POS) + +#define RCU_AHBDSL_GPAEN_POS 16U +#define RCU_AHBDSL_GPAEN_MSK BIT(RCU_AHBDSL_GPAEN_POS) + +#define RCU_AHBDSL_HDIVEN_POS 15U +#define RCU_AHBDSL_HDIVEN_MSK BIT(RCU_AHBDSL_HDIVEN_POS) + +#define RCU_AHBDSL_USBEN_POS 14U +#define RCU_AHBDSL_USBEN_MSK BIT(RCU_AHBDSL_USBEN_POS) + +#define RCU_AHBDSL_AESEN_POS 13U +#define RCU_AHBDSL_AESEN_MSK BIT(RCU_AHBDSL_AESEN_POS) + +#define RCU_AHBDSL_CRCEN_POS 12U +#define RCU_AHBDSL_CRCEN_MSK BIT(RCU_AHBDSL_CRCEN_POS) + +#define RCU_AHBDSL_RTCEN_POS 6U +#define RCU_AHBDSL_RTCEN_MSK BIT(RCU_AHBDSL_RTCEN_POS) + +#define RCU_AHBDSL_DMA1EN_POS 0U +#define RCU_AHBDSL_DMA1EN_MSK BIT(RCU_AHBDSL_DMA1EN_POS) + +/****************** Bit definition for RCU_APB1DSL register ************************/ + +#define RCU_APB1DSL_DACEN_POS 23U +#define RCU_APB1DSL_DACEN_MSK BIT(RCU_APB1DSL_DACEN_POS) + +#define RCU_APB1DSL_I2C2EN_POS 22U +#define RCU_APB1DSL_I2C2EN_MSK BIT(RCU_APB1DSL_I2C2EN_POS) + +#define RCU_APB1DSL_I2C1EN_POS 21U +#define RCU_APB1DSL_I2C1EN_MSK BIT(RCU_APB1DSL_I2C1EN_POS) + +#define RCU_APB1DSL_SUART2EN_POS 20U +#define RCU_APB1DSL_SUART2EN_MSK BIT(RCU_APB1DSL_SUART2EN_POS) + +#define RCU_APB1DSL_SUART1EN_POS 19U +#define RCU_APB1DSL_SUART1EN_MSK BIT(RCU_APB1DSL_SUART1EN_POS) + +#define RCU_APB1DSL_UART3EN_POS 18U +#define RCU_APB1DSL_UART3EN_MSK BIT(RCU_APB1DSL_UART3EN_POS) + +#define RCU_APB1DSL_UART2EN_POS 17U +#define RCU_APB1DSL_UART2EN_MSK BIT(RCU_APB1DSL_UART2EN_POS) + +#define RCU_APB1DSL_SPI2EN_POS 14U +#define RCU_APB1DSL_SPI2EN_MSK BIT(RCU_APB1DSL_SPI2EN_POS) + +#define RCU_APB1DSL_IWDTEN_POS 12U +#define RCU_APB1DSL_IWDTEN_MSK BIT(RCU_APB1DSL_IWDTEN_POS) + +#define RCU_APB1DSL_WWDTEN_POS 11U +#define RCU_APB1DSL_WWDTEN_MSK BIT(RCU_APB1DSL_WWDTEN_POS) + +#define RCU_APB1DSL_BS16T1EN_POS 4U +#define RCU_APB1DSL_BS16T1EN_MSK BIT(RCU_APB1DSL_BS16T1EN_POS) + +#define RCU_APB1DSL_GP16C4T3EN_POS 3U +#define RCU_APB1DSL_GP16C4T3EN_MSK BIT(RCU_APB1DSL_GP16C4T3EN_POS) + +#define RCU_APB1DSL_GP16C4T2EN_POS 2U +#define RCU_APB1DSL_GP16C4T2EN_MSK BIT(RCU_APB1DSL_GP16C4T2EN_POS) + +#define RCU_APB1DSL_GP16C4T1EN_POS 1U +#define RCU_APB1DSL_GP16C4T1EN_MSK BIT(RCU_APB1DSL_GP16C4T1EN_POS) + +#define RCU_APB1DSL_GP32C4T1EN_POS 0U +#define RCU_APB1DSL_GP32C4T1EN_MSK BIT(RCU_APB1DSL_GP32C4T1EN_POS) + +/****************** Bit definition for RCU_APB2DSL register ************************/ + +#define RCU_APB2DSL_CMPEN_POS 23U +#define RCU_APB2DSL_CMPEN_MSK BIT(RCU_APB2DSL_CMPEN_POS) + +#define RCU_APB2DSL_GP16C2T4EN_POS 19U +#define RCU_APB2DSL_GP16C2T4EN_MSK BIT(RCU_APB2DSL_GP16C2T4EN_POS) + +#define RCU_APB2DSL_GP16C2T3EN_POS 18U +#define RCU_APB2DSL_GP16C2T3EN_MSK BIT(RCU_APB2DSL_GP16C2T3EN_POS) + +#define RCU_APB2DSL_GP16C2T2EN_POS 17U +#define RCU_APB2DSL_GP16C2T2EN_MSK BIT(RCU_APB2DSL_GP16C2T2EN_POS) + +#define RCU_APB2DSL_GP16C2T1EN_POS 16U +#define RCU_APB2DSL_GP16C2T1EN_MSK BIT(RCU_APB2DSL_GP16C2T1EN_POS) + +#define RCU_APB2DSL_UART1EN_POS 14U +#define RCU_APB2DSL_UART1EN_MSK BIT(RCU_APB2DSL_UART1EN_POS) + +#define RCU_APB2DSL_SPI1EN_POS 12U +#define RCU_APB2DSL_SPI1EN_MSK BIT(RCU_APB2DSL_SPI1EN_POS) + +#define RCU_APB2DSL_AD16C4T1EN_POS 11U +#define RCU_APB2DSL_AD16C4T1EN_MSK BIT(RCU_APB2DSL_AD16C4T1EN_POS) + +#define RCU_APB2DSL_ADCEN_POS 9U +#define RCU_APB2DSL_ADCEN_MSK BIT(RCU_APB2DSL_ADCEN_POS) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t CFG; + __IO uint32_t STCALIB; + __IO uint32_t PSCK; + __IO uint32_t AHBRST; + __IO uint32_t APB1RST; + __IO uint32_t APB2RST; + __IO uint32_t AHBEN; + __IO uint32_t APB1EN; + __IO uint32_t APB2EN; + __IO uint32_t AHBSL; + __IO uint32_t APB1SL; + __IO uint32_t APB2SL; + __IO uint32_t AHBDSL; + __IO uint32_t APB1DSL; + __IO uint32_t APB2DSL; +} RCU_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rtc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..a22674f22ba6a7731f234366828397339c10ab1d --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_rtc.h @@ -0,0 +1,613 @@ +/** + ************************************************************************************** + * @file REG_RTC.h + * @brief RTC Head File + * + * @version V0.01 + * @date 12/5/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __RTC_H__ +#define __RTC_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for RTC_CON register ************************/ + +#define RTC_CON_MODE_POS 30U +#define RTC_CON_MODE_MSK BIT(RTC_CON_MODE_POS) + +#define RTC_CON_CALVAL_POSS 24U +#define RTC_CON_CALVAL_POSE 29U +#define RTC_CON_CALVAL_MSK BITS(RTC_CON_CALVAL_POSS,RTC_CON_CALVAL_POSE) + +#define RTC_CON_SCALE_POSS 16U +#define RTC_CON_SCALE_POSE 23U +#define RTC_CON_SCALE_MSK BITS(RTC_CON_SCALE_POSS,RTC_CON_SCALE_POSE) + +#define RTC_CON_PSCALE_POSS 8U +#define RTC_CON_PSCALE_POSE 14U +#define RTC_CON_PSCALE_MSK BITS(RTC_CON_PSCALE_POSS,RTC_CON_PSCALE_POSE) + +#define RTC_CON_CYCLE_POS 5U +#define RTC_CON_CYCLE_MSK BIT(RTC_CON_CYCLE_POS) + +#define RTC_CON_CALIB_POS 4U +#define RTC_CON_CALIB_MSK BIT(RTC_CON_CALIB_POS) + +#define RTC_CON_CKSEL_POSS 2U +#define RTC_CON_CKSEL_POSE 3U +#define RTC_CON_CKSEL_MSK BITS(RTC_CON_CKSEL_POSS,RTC_CON_CKSEL_POSE) + +#define RTC_CON_RTCEN_POS 0U +#define RTC_CON_RTCEN_MSK BIT(RTC_CON_RTCEN_POS) + +/****************** Bit definition for RTC_WKUP register ************************/ + +#define RTC_WKUP_WKSCAL_POSS 26U +#define RTC_WKUP_WKSCAL_POSE 29U +#define RTC_WKUP_WKSCAL_MSK BITS(RTC_WKUP_WKSCAL_POSS,RTC_WKUP_WKSCAL_POSE) + +#define RTC_WKUP_WKSEL_POSS 24U +#define RTC_WKUP_WKSEL_POSE 25U +#define RTC_WKUP_WKSEL_MSK BITS(RTC_WKUP_WKSEL_POSS,RTC_WKUP_WKSEL_POSE) + +#define RTC_WKUP_WKCAL_POSS 0U +#define RTC_WKUP_WKCAL_POSE 23U +#define RTC_WKUP_WKCAL_MSK BITS(RTC_WKUP_WKCAL_POSS,RTC_WKUP_WKCAL_POSE) + +/****************** Bit definition for RTC_TIME register ************************/ + +#define RTC_TIME_WEEK_POSS 24U +#define RTC_TIME_WEEK_POSE 26U +#define RTC_TIME_WEEK_MSK BITS(RTC_TIME_WEEK_POSS,RTC_TIME_WEEK_POSE) + +#define RTC_TIME_HOUR_T_POSS 20U +#define RTC_TIME_HOUR_T_POSE 21U +#define RTC_TIME_HOUR_T_MSK BITS(RTC_TIME_HOUR_T_POSS,RTC_TIME_HOUR_T_POSE) + +#define RTC_TIME_HOUR_U_POSS 16U +#define RTC_TIME_HOUR_U_POSE 19U +#define RTC_TIME_HOUR_U_MSK BITS(RTC_TIME_HOUR_U_POSS,RTC_TIME_HOUR_U_POSE) + +#define RTC_TIME_MIN_T_POSS 12U +#define RTC_TIME_MIN_T_POSE 14U +#define RTC_TIME_MIN_T_MSK BITS(RTC_TIME_MIN_T_POSS,RTC_TIME_MIN_T_POSE) + +#define RTC_TIME_MIN_U_POSS 8U +#define RTC_TIME_MIN_U_POSE 11U +#define RTC_TIME_MIN_U_MSK BITS(RTC_TIME_MIN_U_POSS,RTC_TIME_MIN_U_POSE) + +#define RTC_TIME_SEC_T_POSS 4U +#define RTC_TIME_SEC_T_POSE 6U +#define RTC_TIME_SEC_T_MSK BITS(RTC_TIME_SEC_T_POSS,RTC_TIME_SEC_T_POSE) + +#define RTC_TIME_SEC_U_POSS 0U +#define RTC_TIME_SEC_U_POSE 3U +#define RTC_TIME_SEC_U_MSK BITS(RTC_TIME_SEC_U_POSS,RTC_TIME_SEC_U_POSE) + +/****************** Bit definition for RTC_CAL register ************************/ + +#define RTC_CAL_YEAR_T_POSS 20U +#define RTC_CAL_YEAR_T_POSE 23U +#define RTC_CAL_YEAR_T_MSK BITS(RTC_CAL_YEAR_T_POSS,RTC_CAL_YEAR_T_POSE) + +#define RTC_CAL_YEAR_U_POSS 16U +#define RTC_CAL_YEAR_U_POSE 19U +#define RTC_CAL_YEAR_U_MSK BITS(RTC_CAL_YEAR_U_POSS,RTC_CAL_YEAR_U_POSE) + +#define RTC_CAL_MON_T_POS 12U +#define RTC_CAL_MON_T_MSK BIT(RTC_CAL_MON_T_POS) + +#define RTC_CAL_MON_U_POSS 8U +#define RTC_CAL_MON_U_POSE 11U +#define RTC_CAL_MON_U_MSK BITS(RTC_CAL_MON_U_POSS,RTC_CAL_MON_U_POSE) + +#define RTC_CAL_DATE_T_POSS 4U +#define RTC_CAL_DATE_T_POSE 5U +#define RTC_CAL_DATE_T_MSK BITS(RTC_CAL_DATE_T_POSS,RTC_CAL_DATE_T_POSE) + +#define RTC_CAL_DATE_U_POSS 0U +#define RTC_CAL_DATE_U_POSE 3U +#define RTC_CAL_DATE_U_MSK BITS(RTC_CAL_DATE_U_POSS,RTC_CAL_DATE_U_POSE) + +/****************** Bit definition for RTC_ALTIME register ************************/ + +#define RTC_ALTIME_WEEK_POSS 24U +#define RTC_ALTIME_WEEK_POSE 26U +#define RTC_ALTIME_WEEK_MSK BITS(RTC_ALTIME_WEEK_POSS,RTC_ALTIME_WEEK_POSE) + +#define RTC_ALTIME_HOUR_T_POSS 20U +#define RTC_ALTIME_HOUR_T_POSE 21U +#define RTC_ALTIME_HOUR_T_MSK BITS(RTC_ALTIME_HOUR_T_POSS,RTC_ALTIME_HOUR_T_POSE) + +#define RTC_ALTIME_HOUR_U_POSS 16U +#define RTC_ALTIME_HOUR_U_POSE 19U +#define RTC_ALTIME_HOUR_U_MSK BITS(RTC_ALTIME_HOUR_U_POSS,RTC_ALTIME_HOUR_U_POSE) + +#define RTC_ALTIME_MIN_T_POSS 12U +#define RTC_ALTIME_MIN_T_POSE 14U +#define RTC_ALTIME_MIN_T_MSK BITS(RTC_ALTIME_MIN_T_POSS,RTC_ALTIME_MIN_T_POSE) + +#define RTC_ALTIME_MIN_U_POSS 8U +#define RTC_ALTIME_MIN_U_POSE 11U +#define RTC_ALTIME_MIN_U_MSK BITS(RTC_ALTIME_MIN_U_POSS,RTC_ALTIME_MIN_U_POSE) + +#define RTC_ALTIME_SEC_T_POSS 4U +#define RTC_ALTIME_SEC_T_POSE 6U +#define RTC_ALTIME_SEC_T_MSK BITS(RTC_ALTIME_SEC_T_POSS,RTC_ALTIME_SEC_T_POSE) + +#define RTC_ALTIME_SEC_U_POSS 0U +#define RTC_ALTIME_SEC_U_POSE 3U +#define RTC_ALTIME_SEC_U_MSK BITS(RTC_ALTIME_SEC_U_POSS,RTC_ALTIME_SEC_U_POSE) + +/****************** Bit definition for RTC_ALCAL register ************************/ + +#define RTC_ALCAL_YEAR_T_POSS 20U +#define RTC_ALCAL_YEAR_T_POSE 23U +#define RTC_ALCAL_YEAR_T_MSK BITS(RTC_ALCAL_YEAR_T_POSS,RTC_ALCAL_YEAR_T_POSE) + +#define RTC_ALCAL_YEAR_U_POSS 16U +#define RTC_ALCAL_YEAR_U_POSE 19U +#define RTC_ALCAL_YEAR_U_MSK BITS(RTC_ALCAL_YEAR_U_POSS,RTC_ALCAL_YEAR_U_POSE) + +#define RTC_ALCAL_MON_T_POS 12U +#define RTC_ALCAL_MON_T_MSK BIT(RTC_ALCAL_MON_T_POS) + +#define RTC_ALCAL_MON_U_POSS 8U +#define RTC_ALCAL_MON_U_POSE 11U +#define RTC_ALCAL_MON_U_MSK BITS(RTC_ALCAL_MON_U_POSS,RTC_ALCAL_MON_U_POSE) + +#define RTC_ALCAL_DATE_T_POSS 4U +#define RTC_ALCAL_DATE_T_POSE 5U +#define RTC_ALCAL_DATE_T_MSK BITS(RTC_ALCAL_DATE_T_POSS,RTC_ALCAL_DATE_T_POSE) + +#define RTC_ALCAL_DATE_U_POSS 0U +#define RTC_ALCAL_DATE_U_POSE 3U +#define RTC_ALCAL_DATE_U_MSK BITS(RTC_ALCAL_DATE_U_POSS,RTC_ALCAL_DATE_U_POSE) + +/****************** Bit definition for RTC_ALEN register ************************/ + +#define RTC_ALEN_YEAR_POS 6U +#define RTC_ALEN_YEAR_MSK BIT(RTC_ALEN_YEAR_POS) + +#define RTC_ALEN_MONTH_POS 5U +#define RTC_ALEN_MONTH_MSK BIT(RTC_ALEN_MONTH_POS) + +#define RTC_ALEN_DATE_POS 4U +#define RTC_ALEN_DATE_MSK BIT(RTC_ALEN_DATE_POS) + +#define RTC_ALEN_WEEK_POS 3U +#define RTC_ALEN_WEEK_MSK BIT(RTC_ALEN_WEEK_POS) + +#define RTC_ALEN_HOUR_POS 2U +#define RTC_ALEN_HOUR_MSK BIT(RTC_ALEN_HOUR_POS) + +#define RTC_ALEN_MIN_POS 1U +#define RTC_ALEN_MIN_MSK BIT(RTC_ALEN_MIN_POS) + +#define RTC_ALEN_SEC_POS 0U +#define RTC_ALEN_SEC_MSK BIT(RTC_ALEN_SEC_POS) + +/****************** Bit definition for RTC_TRIG register ************************/ + +#define RTC_TRIG_WKTM_POS 16U +#define RTC_TRIG_WKTM_MSK BIT(RTC_TRIG_WKTM_POS) + +#define RTC_TRIG_F1HZ_POS 15U +#define RTC_TRIG_F1HZ_MSK BIT(RTC_TRIG_F1HZ_POS) + +#define RTC_TRIG_RYEAR_POS 14U +#define RTC_TRIG_RYEAR_MSK BIT(RTC_TRIG_RYEAR_POS) + +#define RTC_TRIG_RMON_POS 13U +#define RTC_TRIG_RMON_MSK BIT(RTC_TRIG_RMON_POS) + +#define RTC_TRIG_RDATE_POS 12U +#define RTC_TRIG_RDATE_MSK BIT(RTC_TRIG_RDATE_POS) + +#define RTC_TRIG_RWEEK_POS 11U +#define RTC_TRIG_RWEEK_MSK BIT(RTC_TRIG_RWEEK_POS) + +#define RTC_TRIG_RHOUR_POS 10U +#define RTC_TRIG_RHOUR_MSK BIT(RTC_TRIG_RHOUR_POS) + +#define RTC_TRIG_RMIN_POS 9U +#define RTC_TRIG_RMIN_MSK BIT(RTC_TRIG_RMIN_POS) + +#define RTC_TRIG_RSEC_POS 8U +#define RTC_TRIG_RSEC_MSK BIT(RTC_TRIG_RSEC_POS) + +#define RTC_TRIG_AMALL_POS 7U +#define RTC_TRIG_AMALL_MSK BIT(RTC_TRIG_AMALL_POS) + +#define RTC_TRIG_AYEAR_POS 6U +#define RTC_TRIG_AYEAR_MSK BIT(RTC_TRIG_AYEAR_POS) + +#define RTC_TRIG_AMON_POS 5U +#define RTC_TRIG_AMON_MSK BIT(RTC_TRIG_AMON_POS) + +#define RTC_TRIG_ADTAE_POS 4U +#define RTC_TRIG_ADTAE_MSK BIT(RTC_TRIG_ADTAE_POS) + +#define RTC_TRIG_AWEEK_POS 3U +#define RTC_TRIG_AWEEK_MSK BIT(RTC_TRIG_AWEEK_POS) + +#define RTC_TRIG_AHOUR_POS 2U +#define RTC_TRIG_AHOUR_MSK BIT(RTC_TRIG_AHOUR_POS) + +#define RTC_TRIG_AMIN_POS 1U +#define RTC_TRIG_AMIN_MSK BIT(RTC_TRIG_AMIN_POS) + +#define RTC_TRIG_ASEC_POS 0U +#define RTC_TRIG_ASEC_MSK BIT(RTC_TRIG_ASEC_POS) + +/****************** Bit definition for RTC_IER register ************************/ + +#define RTC_IER_WKTM_POS 16U +#define RTC_IER_WKTM_MSK BIT(RTC_IER_WKTM_POS) + +#define RTC_IER_F1HZ_POS 15U +#define RTC_IER_F1HZ_MSK BIT(RTC_IER_F1HZ_POS) + +#define RTC_IER_RYEAR_POS 14U +#define RTC_IER_RYEAR_MSK BIT(RTC_IER_RYEAR_POS) + +#define RTC_IER_RMON_POS 13U +#define RTC_IER_RMON_MSK BIT(RTC_IER_RMON_POS) + +#define RTC_IER_RDATE_POS 12U +#define RTC_IER_RDATE_MSK BIT(RTC_IER_RDATE_POS) + +#define RTC_IER_RWEEK_POS 11U +#define RTC_IER_RWEEK_MSK BIT(RTC_IER_RWEEK_POS) + +#define RTC_IER_RHOUR_POS 10U +#define RTC_IER_RHOUR_MSK BIT(RTC_IER_RHOUR_POS) + +#define RTC_IER_RMIN_POS 9U +#define RTC_IER_RMIN_MSK BIT(RTC_IER_RMIN_POS) + +#define RTC_IER_RSEC_POS 8U +#define RTC_IER_RSEC_MSK BIT(RTC_IER_RSEC_POS) + +#define RTC_IER_AMALL_POS 7U +#define RTC_IER_AMALL_MSK BIT(RTC_IER_AMALL_POS) + +#define RTC_IER_AYEAR_POS 6U +#define RTC_IER_AYEAR_MSK BIT(RTC_IER_AYEAR_POS) + +#define RTC_IER_AMON_POS 5U +#define RTC_IER_AMON_MSK BIT(RTC_IER_AMON_POS) + +#define RTC_IER_ADTAE_POS 4U +#define RTC_IER_ADTAE_MSK BIT(RTC_IER_ADTAE_POS) + +#define RTC_IER_AWEEK_POS 3U +#define RTC_IER_AWEEK_MSK BIT(RTC_IER_AWEEK_POS) + +#define RTC_IER_AHOUR_POS 2U +#define RTC_IER_AHOUR_MSK BIT(RTC_IER_AHOUR_POS) + +#define RTC_IER_AMIN_POS 1U +#define RTC_IER_AMIN_MSK BIT(RTC_IER_AMIN_POS) + +#define RTC_IER_ASEC_POS 0U +#define RTC_IER_ASEC_MSK BIT(RTC_IER_ASEC_POS) + +/****************** Bit definition for RTC_IDR register ************************/ + +#define RTC_IDR_WKTM_POS 16U +#define RTC_IDR_WKTM_MSK BIT(RTC_IDR_WKTM_POS) + +#define RTC_IDR_F1HZ_POS 15U +#define RTC_IDR_F1HZ_MSK BIT(RTC_IDR_F1HZ_POS) + +#define RTC_IDR_RYEAR_POS 14U +#define RTC_IDR_RYEAR_MSK BIT(RTC_IDR_RYEAR_POS) + +#define RTC_IDR_RMON_POS 13U +#define RTC_IDR_RMON_MSK BIT(RTC_IDR_RMON_POS) + +#define RTC_IDR_RDATE_POS 12U +#define RTC_IDR_RDATE_MSK BIT(RTC_IDR_RDATE_POS) + +#define RTC_IDR_RWEEK_POS 11U +#define RTC_IDR_RWEEK_MSK BIT(RTC_IDR_RWEEK_POS) + +#define RTC_IDR_RHOUR_POS 10U +#define RTC_IDR_RHOUR_MSK BIT(RTC_IDR_RHOUR_POS) + +#define RTC_IDR_RMIN_POS 9U +#define RTC_IDR_RMIN_MSK BIT(RTC_IDR_RMIN_POS) + +#define RTC_IDR_RSEC_POS 8U +#define RTC_IDR_RSEC_MSK BIT(RTC_IDR_RSEC_POS) + +#define RTC_IDR_AMALL_POS 7U +#define RTC_IDR_AMALL_MSK BIT(RTC_IDR_AMALL_POS) + +#define RTC_IDR_AYEAR_POS 6U +#define RTC_IDR_AYEAR_MSK BIT(RTC_IDR_AYEAR_POS) + +#define RTC_IDR_AMON_POS 5U +#define RTC_IDR_AMON_MSK BIT(RTC_IDR_AMON_POS) + +#define RTC_IDR_ADTAE_POS 4U +#define RTC_IDR_ADTAE_MSK BIT(RTC_IDR_ADTAE_POS) + +#define RTC_IDR_AWEEK_POS 3U +#define RTC_IDR_AWEEK_MSK BIT(RTC_IDR_AWEEK_POS) + +#define RTC_IDR_AHOUR_POS 2U +#define RTC_IDR_AHOUR_MSK BIT(RTC_IDR_AHOUR_POS) + +#define RTC_IDR_AMIN_POS 1U +#define RTC_IDR_AMIN_MSK BIT(RTC_IDR_AMIN_POS) + +#define RTC_IDR_ASEC_POS 0U +#define RTC_IDR_ASEC_MSK BIT(RTC_IDR_ASEC_POS) + +/****************** Bit definition for RTC_IVS register ************************/ + +#define RTC_IVS_WKTM_POS 16U +#define RTC_IVS_WKTM_MSK BIT(RTC_IVS_WKTM_POS) + +#define RTC_IVS_F1HZ_POS 15U +#define RTC_IVS_F1HZ_MSK BIT(RTC_IVS_F1HZ_POS) + +#define RTC_IVS_RYEAR_POS 14U +#define RTC_IVS_RYEAR_MSK BIT(RTC_IVS_RYEAR_POS) + +#define RTC_IVS_RMON_POS 13U +#define RTC_IVS_RMON_MSK BIT(RTC_IVS_RMON_POS) + +#define RTC_IVS_RDATE_POS 12U +#define RTC_IVS_RDATE_MSK BIT(RTC_IVS_RDATE_POS) + +#define RTC_IVS_RWEEK_POS 11U +#define RTC_IVS_RWEEK_MSK BIT(RTC_IVS_RWEEK_POS) + +#define RTC_IVS_RHOUR_POS 10U +#define RTC_IVS_RHOUR_MSK BIT(RTC_IVS_RHOUR_POS) + +#define RTC_IVS_RMIN_POS 9U +#define RTC_IVS_RMIN_MSK BIT(RTC_IVS_RMIN_POS) + +#define RTC_IVS_RSEC_POS 8U +#define RTC_IVS_RSEC_MSK BIT(RTC_IVS_RSEC_POS) + +#define RTC_IVS_AMALL_POS 7U +#define RTC_IVS_AMALL_MSK BIT(RTC_IVS_AMALL_POS) + +#define RTC_IVS_AYEAR_POS 6U +#define RTC_IVS_AYEAR_MSK BIT(RTC_IVS_AYEAR_POS) + +#define RTC_IVS_AMON_POS 5U +#define RTC_IVS_AMON_MSK BIT(RTC_IVS_AMON_POS) + +#define RTC_IVS_ADTAE_POS 4U +#define RTC_IVS_ADTAE_MSK BIT(RTC_IVS_ADTAE_POS) + +#define RTC_IVS_AWEEK_POS 3U +#define RTC_IVS_AWEEK_MSK BIT(RTC_IVS_AWEEK_POS) + +#define RTC_IVS_AHOUR_POS 2U +#define RTC_IVS_AHOUR_MSK BIT(RTC_IVS_AHOUR_POS) + +#define RTC_IVS_AMIN_POS 1U +#define RTC_IVS_AMIN_MSK BIT(RTC_IVS_AMIN_POS) + +#define RTC_IVS_ASEC_POS 0U +#define RTC_IVS_ASEC_MSK BIT(RTC_IVS_ASEC_POS) + +/****************** Bit definition for RTC_RIF register ************************/ + +#define RTC_RIF_WKTM_POS 16U +#define RTC_RIF_WKTM_MSK BIT(RTC_RIF_WKTM_POS) + +#define RTC_RIF_F1HZ_POS 15U +#define RTC_RIF_F1HZ_MSK BIT(RTC_RIF_F1HZ_POS) + +#define RTC_RIF_RYEAR_POS 14U +#define RTC_RIF_RYEAR_MSK BIT(RTC_RIF_RYEAR_POS) + +#define RTC_RIF_RMON_POS 13U +#define RTC_RIF_RMON_MSK BIT(RTC_RIF_RMON_POS) + +#define RTC_RIF_RDATE_POS 12U +#define RTC_RIF_RDATE_MSK BIT(RTC_RIF_RDATE_POS) + +#define RTC_RIF_RWEEK_POS 11U +#define RTC_RIF_RWEEK_MSK BIT(RTC_RIF_RWEEK_POS) + +#define RTC_RIF_RHOUR_POS 10U +#define RTC_RIF_RHOUR_MSK BIT(RTC_RIF_RHOUR_POS) + +#define RTC_RIF_RMIN_POS 9U +#define RTC_RIF_RMIN_MSK BIT(RTC_RIF_RMIN_POS) + +#define RTC_RIF_RSEC_POS 8U +#define RTC_RIF_RSEC_MSK BIT(RTC_RIF_RSEC_POS) + +#define RTC_RIF_AMALL_POS 7U +#define RTC_RIF_AMALL_MSK BIT(RTC_RIF_AMALL_POS) + +#define RTC_RIF_AYEAR_POS 6U +#define RTC_RIF_AYEAR_MSK BIT(RTC_RIF_AYEAR_POS) + +#define RTC_RIF_AMON_POS 5U +#define RTC_RIF_AMON_MSK BIT(RTC_RIF_AMON_POS) + +#define RTC_RIF_ADTAE_POS 4U +#define RTC_RIF_ADTAE_MSK BIT(RTC_RIF_ADTAE_POS) + +#define RTC_RIF_AWEEK_POS 3U +#define RTC_RIF_AWEEK_MSK BIT(RTC_RIF_AWEEK_POS) + +#define RTC_RIF_AHOUR_POS 2U +#define RTC_RIF_AHOUR_MSK BIT(RTC_RIF_AHOUR_POS) + +#define RTC_RIF_AMIN_POS 1U +#define RTC_RIF_AMIN_MSK BIT(RTC_RIF_AMIN_POS) + +#define RTC_RIF_ASEC_POS 0U +#define RTC_RIF_ASEC_MSK BIT(RTC_RIF_ASEC_POS) + +/****************** Bit definition for RTC_IFM register ************************/ + +#define RTC_IFM_WKTM_POS 16U +#define RTC_IFM_WKTM_MSK BIT(RTC_IFM_WKTM_POS) + +#define RTC_IFM_F1HZ_POS 15U +#define RTC_IFM_F1HZ_MSK BIT(RTC_IFM_F1HZ_POS) + +#define RTC_IFM_RYEAR_POS 14U +#define RTC_IFM_RYEAR_MSK BIT(RTC_IFM_RYEAR_POS) + +#define RTC_IFM_RMON_POS 13U +#define RTC_IFM_RMON_MSK BIT(RTC_IFM_RMON_POS) + +#define RTC_IFM_RDATE_POS 12U +#define RTC_IFM_RDATE_MSK BIT(RTC_IFM_RDATE_POS) + +#define RTC_IFM_RWEEK_POS 11U +#define RTC_IFM_RWEEK_MSK BIT(RTC_IFM_RWEEK_POS) + +#define RTC_IFM_RHOUR_POS 10U +#define RTC_IFM_RHOUR_MSK BIT(RTC_IFM_RHOUR_POS) + +#define RTC_IFM_RMIN_POS 9U +#define RTC_IFM_RMIN_MSK BIT(RTC_IFM_RMIN_POS) + +#define RTC_IFM_RSEC_POS 8U +#define RTC_IFM_RSEC_MSK BIT(RTC_IFM_RSEC_POS) + +#define RTC_IFM_AMALL_POS 7U +#define RTC_IFM_AMALL_MSK BIT(RTC_IFM_AMALL_POS) + +#define RTC_IFM_AYEAR_POS 6U +#define RTC_IFM_AYEAR_MSK BIT(RTC_IFM_AYEAR_POS) + +#define RTC_IFM_AMON_POS 5U +#define RTC_IFM_AMON_MSK BIT(RTC_IFM_AMON_POS) + +#define RTC_IFM_ADTAE_POS 4U +#define RTC_IFM_ADTAE_MSK BIT(RTC_IFM_ADTAE_POS) + +#define RTC_IFM_AWEEK_POS 3U +#define RTC_IFM_AWEEK_MSK BIT(RTC_IFM_AWEEK_POS) + +#define RTC_IFM_AHOUR_POS 2U +#define RTC_IFM_AHOUR_MSK BIT(RTC_IFM_AHOUR_POS) + +#define RTC_IFM_AMIN_POS 1U +#define RTC_IFM_AMIN_MSK BIT(RTC_IFM_AMIN_POS) + +#define RTC_IFM_ASEC_POS 0U +#define RTC_IFM_ASEC_MSK BIT(RTC_IFM_ASEC_POS) + +/****************** Bit definition for RTC_ICR register ************************/ + +#define RTC_ICR_WKTM_POS 16U +#define RTC_ICR_WKTM_MSK BIT(RTC_ICR_WKTM_POS) + +#define RTC_ICR_F1HZ_POS 15U +#define RTC_ICR_F1HZ_MSK BIT(RTC_ICR_F1HZ_POS) + +#define RTC_ICR_RYEAR_POS 14U +#define RTC_ICR_RYEAR_MSK BIT(RTC_ICR_RYEAR_POS) + +#define RTC_ICR_RMON_POS 13U +#define RTC_ICR_RMON_MSK BIT(RTC_ICR_RMON_POS) + +#define RTC_ICR_RDATE_POS 12U +#define RTC_ICR_RDATE_MSK BIT(RTC_ICR_RDATE_POS) + +#define RTC_ICR_RWEEK_POS 11U +#define RTC_ICR_RWEEK_MSK BIT(RTC_ICR_RWEEK_POS) + +#define RTC_ICR_RHOUR_POS 10U +#define RTC_ICR_RHOUR_MSK BIT(RTC_ICR_RHOUR_POS) + +#define RTC_ICR_RMIN_POS 9U +#define RTC_ICR_RMIN_MSK BIT(RTC_ICR_RMIN_POS) + +#define RTC_ICR_RSEC_POS 8U +#define RTC_ICR_RSEC_MSK BIT(RTC_ICR_RSEC_POS) + +#define RTC_ICR_AMALL_POS 7U +#define RTC_ICR_AMALL_MSK BIT(RTC_ICR_AMALL_POS) + +#define RTC_ICR_AYEAR_POS 6U +#define RTC_ICR_AYEAR_MSK BIT(RTC_ICR_AYEAR_POS) + +#define RTC_ICR_AMON_POS 5U +#define RTC_ICR_AMON_MSK BIT(RTC_ICR_AMON_POS) + +#define RTC_ICR_ADTAE_POS 4U +#define RTC_ICR_ADTAE_MSK BIT(RTC_ICR_ADTAE_POS) + +#define RTC_ICR_AWEEK_POS 3U +#define RTC_ICR_AWEEK_MSK BIT(RTC_ICR_AWEEK_POS) + +#define RTC_ICR_AHOUR_POS 2U +#define RTC_ICR_AHOUR_MSK BIT(RTC_ICR_AHOUR_POS) + +#define RTC_ICR_AMIN_POS 1U +#define RTC_ICR_AMIN_MSK BIT(RTC_ICR_AMIN_POS) + +#define RTC_ICR_ASEC_POS 0U +#define RTC_ICR_ASEC_MSK BIT(RTC_ICR_ASEC_POS) + +/****************** Bit definition for RTC_STAT register ************************/ + +#define RTC_STAT_SYNDONE_POS 1U +#define RTC_STAT_SYNDONE_MSK BIT(RTC_STAT_SYNDONE_POS) + +#define RTC_STAT_EMPTY_POS 0U +#define RTC_STAT_EMPTY_MSK BIT(RTC_STAT_EMPTY_POS) + +/****************** Bit definition for RTC_BKEN register ************************/ + +#define RTC_BKEN_BKEN_POS 0U +#define RTC_BKEN_BKEN_MSK BIT(RTC_BKEN_BKEN_POS) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t WKUP; + __IO uint32_t TIME; + __IO uint32_t CAL; + __IO uint32_t ALTIME; + __IO uint32_t ALCAL; + __IO uint32_t ALEN; + __IO uint32_t TRIG; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + uint32_t RESERVED0[2] ; + __I uint32_t STAT; + __IO uint32_t BKEN; +} RTC_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_spi.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..0d7fbf6ccccea2d1d756f952a0416f5a88d9ede4 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_spi.h @@ -0,0 +1,444 @@ +/** + ************************************************************************************** + * @file REG_SPI.h + * @brief SPI Head File + * + * @version V0.01 + * @data 12/3/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __SPI_H__ +#define __SPI_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for SPI_CON1 register ************************/ + +#define SPI_CON1_BIDEN_POS 15U +#define SPI_CON1_BIDEN_MSK BIT(SPI_CON1_BIDEN_POS) + +#define SPI_CON1_BIDOEN_POS 14U +#define SPI_CON1_BIDOEN_MSK BIT(SPI_CON1_BIDOEN_POS) + +#define SPI_CON1_CRCEN_POS 13U +#define SPI_CON1_CRCEN_MSK BIT(SPI_CON1_CRCEN_POS) + +#define SPI_CON1_NXTCRC_POS 12U +#define SPI_CON1_NXTCRC_MSK BIT(SPI_CON1_NXTCRC_POS) + +#define SPI_CON1_FLEN_POS 11U +#define SPI_CON1_FLEN_MSK BIT(SPI_CON1_FLEN_POS) + +#define SPI_CON1_RXO_POS 10U +#define SPI_CON1_RXO_MSK BIT(SPI_CON1_RXO_POS) + +#define SPI_CON1_SSEN_POS 9U +#define SPI_CON1_SSEN_MSK BIT(SPI_CON1_SSEN_POS) + +#define SPI_CON1_SSOUT_POS 8U +#define SPI_CON1_SSOUT_MSK BIT(SPI_CON1_SSOUT_POS) + +#define SPI_CON1_LSBFST_POS 7U +#define SPI_CON1_LSBFST_MSK BIT(SPI_CON1_LSBFST_POS) + +#define SPI_CON1_SPIEN_POS 6U +#define SPI_CON1_SPIEN_MSK BIT(SPI_CON1_SPIEN_POS) + +#define SPI_CON1_BAUD_POSS 3U +#define SPI_CON1_BAUD_POSE 5U +#define SPI_CON1_BAUD_MSK BITS(SPI_CON1_BAUD_POSS,SPI_CON1_BAUD_POSE) + +#define SPI_CON1_MSTREN_POS 2U +#define SPI_CON1_MSTREN_MSK BIT(SPI_CON1_MSTREN_POS) + +#define SPI_CON1_CPOL_POS 1U +#define SPI_CON1_CPOL_MSK BIT(SPI_CON1_CPOL_POS) + +#define SPI_CON1_CPHA_POS 0U +#define SPI_CON1_CPHA_MSK BIT(SPI_CON1_CPHA_POS) + +/****************** Bit definition for SPI_CON2 register ************************/ + +#define SPI_CON2_RXFTH_POSS 14U +#define SPI_CON2_RXFTH_POSE 15U +#define SPI_CON2_RXFTH_MSK BITS(SPI_CON2_RXFTH_POSS,SPI_CON2_RXFTH_POSE) + +#define SPI_CON2_TXFTH_POSS 12U +#define SPI_CON2_TXFTH_POSE 13U +#define SPI_CON2_TXFTH_MSK BITS(SPI_CON2_TXFTH_POSS,SPI_CON2_TXFTH_POSE) + +#define SPI_CON2_FRF_POS 4U +#define SPI_CON2_FRF_MSK BIT(SPI_CON2_FRF_POS) + +#define SPI_CON2_NSSP_POS 3U +#define SPI_CON2_NSSP_MSK BIT(SPI_CON2_NSSP_POS) + +#define SPI_CON2_NSSOE_POS 2U +#define SPI_CON2_NSSOE_MSK BIT(SPI_CON2_NSSOE_POS) + +#define SPI_CON2_TXDMA_POS 1U +#define SPI_CON2_TXDMA_MSK BIT(SPI_CON2_TXDMA_POS) + +#define SPI_CON2_RXDMA_POS 0U +#define SPI_CON2_RXDMA_MSK BIT(SPI_CON2_RXDMA_POS) + +/****************** Bit definition for SPI_STAT register ************************/ + +#define SPI_STAT_RXFLV_POSS 24U +#define SPI_STAT_RXFLV_POSE 28U +#define SPI_STAT_RXFLV_MSK BITS(SPI_STAT_RXFLV_POSS,SPI_STAT_RXFLV_POSE) + +#define SPI_STAT_TXFLV_POSS 16U +#define SPI_STAT_TXFLV_POSE 20U +#define SPI_STAT_TXFLV_MSK BITS(SPI_STAT_TXFLV_POSS,SPI_STAT_TXFLV_POSE) + +#define SPI_STAT_BUSY_POS 15U +#define SPI_STAT_BUSY_MSK BIT(SPI_STAT_BUSY_POS) + +#define SPI_STAT_CHSIDE_POS 14U +#define SPI_STAT_CHSIDE_MSK BIT(SPI_STAT_CHSIDE_POS) + +#define SPI_STAT_RXTH_POS 12U +#define SPI_STAT_RXTH_MSK BIT(SPI_STAT_RXTH_POS) + +#define SPI_STAT_RXUD_POS 11U +#define SPI_STAT_RXUD_MSK BIT(SPI_STAT_RXUD_POS) + +#define SPI_STAT_RXOV_POS 10U +#define SPI_STAT_RXOV_MSK BIT(SPI_STAT_RXOV_POS) + +#define SPI_STAT_RXF_POS 9U +#define SPI_STAT_RXF_MSK BIT(SPI_STAT_RXF_POS) + +#define SPI_STAT_RXE_POS 8U +#define SPI_STAT_RXE_MSK BIT(SPI_STAT_RXE_POS) + +#define SPI_STAT_TXTH_POS 4U +#define SPI_STAT_TXTH_MSK BIT(SPI_STAT_TXTH_POS) + +#define SPI_STAT_TXUD_POS 3U +#define SPI_STAT_TXUD_MSK BIT(SPI_STAT_TXUD_POS) + +#define SPI_STAT_TXOV_POS 2U +#define SPI_STAT_TXOV_MSK BIT(SPI_STAT_TXOV_POS) + +#define SPI_STAT_TXF_POS 1U +#define SPI_STAT_TXF_MSK BIT(SPI_STAT_TXF_POS) + +#define SPI_STAT_TXE_POS 0U +#define SPI_STAT_TXE_MSK BIT(SPI_STAT_TXE_POS) + +/****************** Bit definition for SPI_DATA register ************************/ + +#define SPI_DATA_DATA_POSS 0U +#define SPI_DATA_DATA_POSE 15U +#define SPI_DATA_DATA_MSK BITS(SPI_DATA_DATA_POSS,SPI_DATA_DATA_POSE) + +/****************** Bit definition for SPI_CRCPOLY register ************************/ + +#define SPI_CRCPOLY_CRCPOLY_POSS 0U +#define SPI_CRCPOLY_CRCPOLY_POSE 15U +#define SPI_CRCPOLY_CRCPOLY_MSK BITS(SPI_CRCPOLY_CRCPOLY_POSS,SPI_CRCPOLY_CRCPOLY_POSE) + +/****************** Bit definition for SPI_RXCRC register ************************/ + +#define SPI_RXCRC_RXCRC_POSS 0U +#define SPI_RXCRC_RXCRC_POSE 15U +#define SPI_RXCRC_RXCRC_MSK BITS(SPI_RXCRC_RXCRC_POSS,SPI_RXCRC_RXCRC_POSE) + +/****************** Bit definition for SPI_TXCRC register ************************/ + +#define SPI_TXCRC_TXCRC_POSS 0U +#define SPI_TXCRC_TXCRC_POSE 15U +#define SPI_TXCRC_TXCRC_MSK BITS(SPI_TXCRC_TXCRC_POSS,SPI_TXCRC_TXCRC_POSE) + +/****************** Bit definition for SPI_I2SCFG register ************************/ + +#define SPI_I2SCFG_I2SMOD_POS 11U +#define SPI_I2SCFG_I2SMOD_MSK BIT(SPI_I2SCFG_I2SMOD_POS) + +#define SPI_I2SCFG_I2SE_POS 10U +#define SPI_I2SCFG_I2SE_MSK BIT(SPI_I2SCFG_I2SE_POS) + +#define SPI_I2SCFG_I2SCFG_POSS 8U +#define SPI_I2SCFG_I2SCFG_POSE 9U +#define SPI_I2SCFG_I2SCFG_MSK BITS(SPI_I2SCFG_I2SCFG_POSS,SPI_I2SCFG_I2SCFG_POSE) + +#define SPI_I2SCFG_PCMSYNC_POS 7U +#define SPI_I2SCFG_PCMSYNC_MSK BIT(SPI_I2SCFG_PCMSYNC_POS) + +#define SPI_I2SCFG_I2SSTD_POSS 4U +#define SPI_I2SCFG_I2SSTD_POSE 5U +#define SPI_I2SCFG_I2SSTD_MSK BITS(SPI_I2SCFG_I2SSTD_POSS,SPI_I2SCFG_I2SSTD_POSE) + +#define SPI_I2SCFG_CKPOL_POS 3U +#define SPI_I2SCFG_CKPOL_MSK BIT(SPI_I2SCFG_CKPOL_POS) + +#define SPI_I2SCFG_DATLEN_POSS 1U +#define SPI_I2SCFG_DATLEN_POSE 2U +#define SPI_I2SCFG_DATLEN_MSK BITS(SPI_I2SCFG_DATLEN_POSS,SPI_I2SCFG_DATLEN_POSE) + +#define SPI_I2SCFG_CHLEN_POS 0U +#define SPI_I2SCFG_CHLEN_MSK BIT(SPI_I2SCFG_CHLEN_POS) + +/****************** Bit definition for SPI_I2SPR register ************************/ + +#define SPI_I2SPR_EXTCKEN_POS 10U +#define SPI_I2SPR_EXTCKEN_MSK BIT(SPI_I2SPR_EXTCKEN_POS) + +#define SPI_I2SPR_MCKOE_POS 9U +#define SPI_I2SPR_MCKOE_MSK BIT(SPI_I2SPR_MCKOE_POS) + +#define SPI_I2SPR_ODD_POS 8U +#define SPI_I2SPR_ODD_MSK BIT(SPI_I2SPR_ODD_POS) + +#define SPI_I2SPR_I2SDIV_POSS 0U +#define SPI_I2SPR_I2SDIV_POSE 7U +#define SPI_I2SPR_I2SDIV_MSK BITS(SPI_I2SPR_I2SDIV_POSS,SPI_I2SPR_I2SDIV_POSE) + +/****************** Bit definition for SPI_IER register ************************/ + +#define SPI_IER_FREIE_POS 18U +#define SPI_IER_FREIE_MSK BIT(SPI_IER_FREIE_POS) + +#define SPI_IER_MODFIE_POS 17U +#define SPI_IER_MODFIE_MSK BIT(SPI_IER_MODFIE_POS) + +#define SPI_IER_CRCERRIE_POS 16U +#define SPI_IER_CRCERRIE_MSK BIT(SPI_IER_CRCERRIE_POS) + +#define SPI_IER_RXTHIE_POS 12U +#define SPI_IER_RXTHIE_MSK BIT(SPI_IER_RXTHIE_POS) + +#define SPI_IER_RXUDIE_POS 11U +#define SPI_IER_RXUDIE_MSK BIT(SPI_IER_RXUDIE_POS) + +#define SPI_IER_RXOVIE_POS 10U +#define SPI_IER_RXOVIE_MSK BIT(SPI_IER_RXOVIE_POS) + +#define SPI_IER_RXFIE_POS 9U +#define SPI_IER_RXFIE_MSK BIT(SPI_IER_RXFIE_POS) + +#define SPI_IER_TXTHIE_POS 4U +#define SPI_IER_TXTHIE_MSK BIT(SPI_IER_TXTHIE_POS) + +#define SPI_IER_TXUDIE_POS 3U +#define SPI_IER_TXUDIE_MSK BIT(SPI_IER_TXUDIE_POS) + +#define SPI_IER_TXOVIE_POS 2U +#define SPI_IER_TXOVIE_MSK BIT(SPI_IER_TXOVIE_POS) + +#define SPI_IER_TXEIE_POS 0U +#define SPI_IER_TXEIE_MSK BIT(SPI_IER_TXEIE_POS) + +/****************** Bit definition for SPI_IDR register ************************/ + +#define SPI_IDR_FREID_POS 18U +#define SPI_IDR_FREID_MSK BIT(SPI_IDR_FREID_POS) + +#define SPI_IDR_MODFID_POS 17U +#define SPI_IDR_MODFID_MSK BIT(SPI_IDR_MODFID_POS) + +#define SPI_IDR_CRCERRID_POS 16U +#define SPI_IDR_CRCERRID_MSK BIT(SPI_IDR_CRCERRID_POS) + +#define SPI_IDR_RXTHID_POS 12U +#define SPI_IDR_RXTHID_MSK BIT(SPI_IDR_RXTHID_POS) + +#define SPI_IDR_RXUDID_POS 11U +#define SPI_IDR_RXUDID_MSK BIT(SPI_IDR_RXUDID_POS) + +#define SPI_IDR_RXOVID_POS 10U +#define SPI_IDR_RXOVID_MSK BIT(SPI_IDR_RXOVID_POS) + +#define SPI_IDR_RXFID_POS 9U +#define SPI_IDR_RXFID_MSK BIT(SPI_IDR_RXFID_POS) + +#define SPI_IDR_TXTHID_POS 4U +#define SPI_IDR_TXTHID_MSK BIT(SPI_IDR_TXTHID_POS) + +#define SPI_IDR_TXUDID_POS 3U +#define SPI_IDR_TXUDID_MSK BIT(SPI_IDR_TXUDID_POS) + +#define SPI_IDR_TXOVID_POS 2U +#define SPI_IDR_TXOVID_MSK BIT(SPI_IDR_TXOVID_POS) + +#define SPI_IDR_TXEID_POS 0U +#define SPI_IDR_TXEID_MSK BIT(SPI_IDR_TXEID_POS) + +/****************** Bit definition for SPI_IVS register ************************/ + +#define SPI_IVS_FREIV_POS 18U +#define SPI_IVS_FREIV_MSK BIT(SPI_IVS_FREIV_POS) + +#define SPI_IVS_MODFIV_POS 17U +#define SPI_IVS_MODFIV_MSK BIT(SPI_IVS_MODFIV_POS) + +#define SPI_IVS_CRCERRIV_POS 16U +#define SPI_IVS_CRCERRIV_MSK BIT(SPI_IVS_CRCERRIV_POS) + +#define SPI_IVS_RXTHIV_POS 12U +#define SPI_IVS_RXTHIV_MSK BIT(SPI_IVS_RXTHIV_POS) + +#define SPI_IVS_RXUDIV_POS 11U +#define SPI_IVS_RXUDIV_MSK BIT(SPI_IVS_RXUDIV_POS) + +#define SPI_IVS_RXOVIV_POS 10U +#define SPI_IVS_RXOVIV_MSK BIT(SPI_IVS_RXOVIV_POS) + +#define SPI_IVS_RXFIV_POS 9U +#define SPI_IVS_RXFIV_MSK BIT(SPI_IVS_RXFIV_POS) + +#define SPI_IVS_TXTHIV_POS 4U +#define SPI_IVS_TXTHIV_MSK BIT(SPI_IVS_TXTHIV_POS) + +#define SPI_IVS_TXUDIV_POS 3U +#define SPI_IVS_TXUDIV_MSK BIT(SPI_IVS_TXUDIV_POS) + +#define SPI_IVS_TXOVIV_POS 2U +#define SPI_IVS_TXOVIV_MSK BIT(SPI_IVS_TXOVIV_POS) + +#define SPI_IVS_TXEIV_POS 0U +#define SPI_IVS_TXEIV_MSK BIT(SPI_IVS_TXEIV_POS) + +/****************** Bit definition for SPI_RIF register ************************/ + +#define SPI_RIF_FRERI_POS 18U +#define SPI_RIF_FRERI_MSK BIT(SPI_RIF_FRERI_POS) + +#define SPI_RIF_MODFRI_POS 17U +#define SPI_RIF_MODFRI_MSK BIT(SPI_RIF_MODFRI_POS) + +#define SPI_RIF_CRCERRRI_POS 16U +#define SPI_RIF_CRCERRRI_MSK BIT(SPI_RIF_CRCERRRI_POS) + +#define SPI_RIF_RXTHRI_POS 12U +#define SPI_RIF_RXTHRI_MSK BIT(SPI_RIF_RXTHRI_POS) + +#define SPI_RIF_RXUDRI_POS 11U +#define SPI_RIF_RXUDRI_MSK BIT(SPI_RIF_RXUDRI_POS) + +#define SPI_RIF_RXOVRI_POS 10U +#define SPI_RIF_RXOVRI_MSK BIT(SPI_RIF_RXOVRI_POS) + +#define SPI_RIF_RXFRI_POS 9U +#define SPI_RIF_RXFRI_MSK BIT(SPI_RIF_RXFRI_POS) + +#define SPI_RIF_TXTHRI_POS 4U +#define SPI_RIF_TXTHRI_MSK BIT(SPI_RIF_TXTHRI_POS) + +#define SPI_RIF_TXUDRI_POS 3U +#define SPI_RIF_TXUDRI_MSK BIT(SPI_RIF_TXUDRI_POS) + +#define SPI_RIF_TXOVRI_POS 2U +#define SPI_RIF_TXOVRI_MSK BIT(SPI_RIF_TXOVRI_POS) + +#define SPI_RIF_TXERI_POS 0U +#define SPI_RIF_TXERI_MSK BIT(SPI_RIF_TXERI_POS) + +/****************** Bit definition for SPI_IFM register ************************/ + +#define SPI_IFM_FREFM_POS 18U +#define SPI_IFM_FREFM_MSK BIT(SPI_IFM_FREFM_POS) + +#define SPI_IFM_MODFFM_POS 17U +#define SPI_IFM_MODFFM_MSK BIT(SPI_IFM_MODFFM_POS) + +#define SPI_IFM_CRCERRFM_POS 16U +#define SPI_IFM_CRCERRFM_MSK BIT(SPI_IFM_CRCERRFM_POS) + +#define SPI_IFM_RXTHFM_POS 12U +#define SPI_IFM_RXTHFM_MSK BIT(SPI_IFM_RXTHFM_POS) + +#define SPI_IFM_RXUDFM_POS 11U +#define SPI_IFM_RXUDFM_MSK BIT(SPI_IFM_RXUDFM_POS) + +#define SPI_IFM_RXOVFM_POS 10U +#define SPI_IFM_RXOVFM_MSK BIT(SPI_IFM_RXOVFM_POS) + +#define SPI_IFM_RXFFM_POS 9U +#define SPI_IFM_RXFFM_MSK BIT(SPI_IFM_RXFFM_POS) + +#define SPI_IFM_TXTHFM_POS 4U +#define SPI_IFM_TXTHFM_MSK BIT(SPI_IFM_TXTHFM_POS) + +#define SPI_IFM_TXUDFM_POS 3U +#define SPI_IFM_TXUDFM_MSK BIT(SPI_IFM_TXUDFM_POS) + +#define SPI_IFM_TXOVFM_POS 2U +#define SPI_IFM_TXOVFM_MSK BIT(SPI_IFM_TXOVFM_POS) + +#define SPI_IFM_TXEFM_POS 0U +#define SPI_IFM_TXEFM_MSK BIT(SPI_IFM_TXEFM_POS) + +/****************** Bit definition for SPI_ICR register ************************/ + +#define SPI_ICR_FREIC_POS 18U +#define SPI_ICR_FREIC_MSK BIT(SPI_ICR_FREIC_POS) + +#define SPI_ICR_MODFIC_POS 17U +#define SPI_ICR_MODFIC_MSK BIT(SPI_ICR_MODFIC_POS) + +#define SPI_ICR_CRCERRIC_POS 16U +#define SPI_ICR_CRCERRIC_MSK BIT(SPI_ICR_CRCERRIC_POS) + +#define SPI_ICR_RXTHIC_POS 12U +#define SPI_ICR_RXTHIC_MSK BIT(SPI_ICR_RXTHIC_POS) + +#define SPI_ICR_RXUDIC_POS 11U +#define SPI_ICR_RXUDIC_MSK BIT(SPI_ICR_RXUDIC_POS) + +#define SPI_ICR_RXOVIC_POS 10U +#define SPI_ICR_RXOVIC_MSK BIT(SPI_ICR_RXOVIC_POS) + +#define SPI_ICR_RXFIC_POS 9U +#define SPI_ICR_RXFIC_MSK BIT(SPI_ICR_RXFIC_POS) + +#define SPI_ICR_TXTHIC_POS 4U +#define SPI_ICR_TXTHIC_MSK BIT(SPI_ICR_TXTHIC_POS) + +#define SPI_ICR_TXUDIC_POS 3U +#define SPI_ICR_TXUDIC_MSK BIT(SPI_ICR_TXUDIC_POS) + +#define SPI_ICR_TXOVIC_POS 2U +#define SPI_ICR_TXOVIC_MSK BIT(SPI_ICR_TXOVIC_POS) + +#define SPI_ICR_TXEIC_POS 0U +#define SPI_ICR_TXEIC_MSK BIT(SPI_ICR_TXEIC_POS) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __I uint32_t STAT; + __IO uint32_t DATA; + __IO uint32_t CRCPOLY; + __I uint32_t RXCRC; + __I uint32_t TXCRC; + __IO uint32_t I2SCFG; + __IO uint32_t I2SPR; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} SPI_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_syscfg.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_syscfg.h new file mode 100644 index 0000000000000000000000000000000000000000..675d9484c9841ad57b31a1f37ddeef6c85b4e8c8 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_syscfg.h @@ -0,0 +1,215 @@ +/** + ************************************************************************************** + * @file REG_SYSCFG.h + * @brief SYSCFG Head File + * + * @version V0.01 + * @date 12/5/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __SYSCFG_H__ +#define __SYSCFG_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for SYSCFG_REMAP register ************************/ + +#define SYSCFG_REMAP_REALMOD_POSS 10U +#define SYSCFG_REMAP_REALMOD_POSE 11U +#define SYSCFG_REMAP_REALMOD_MSK BITS(SYSCFG_REMAP_REALMOD_POSS,SYSCFG_REMAP_REALMOD_POSE) + +#define SYSCFG_REMAP_EFBASE_POSS 4U +#define SYSCFG_REMAP_EFBASE_POSE 7U +#define SYSCFG_REMAP_EFBASE_MSK BITS(SYSCFG_REMAP_EFBASE_POSS,SYSCFG_REMAP_EFBASE_POSE) + +#define SYSCFG_REMAP_MEMMOD_POSS 2U +#define SYSCFG_REMAP_MEMMOD_POSE 3U +#define SYSCFG_REMAP_MEMMOD_MSK BITS(SYSCFG_REMAP_MEMMOD_POSS,SYSCFG_REMAP_MEMMOD_POSE) + +#define SYSCFG_REMAP_REMAP_POS 0U +#define SYSCFG_REMAP_REMAP_MSK BIT(SYSCFG_REMAP_REMAP_POS) + +/****************** Bit definition for SYSCFG_TRIM register ************************/ + +#define SYSCFG_TRIM_CNT_POSS 20U +#define SYSCFG_TRIM_CNT_POSE 31U +#define SYSCFG_TRIM_CNT_MSK BITS(SYSCFG_TRIM_CNT_POSS,SYSCFG_TRIM_CNT_POSE) + +#define SYSCFG_TRIM_FAIL_POS 18U +#define SYSCFG_TRIM_FAIL_MSK BIT(SYSCFG_TRIM_FAIL_POS) + +#define SYSCFG_TRIM_NOEQU_POS 17U +#define SYSCFG_TRIM_NOEQU_MSK BIT(SYSCFG_TRIM_NOEQU_POS) + +#define SYSCFG_TRIM_BUSY_POS 16U +#define SYSCFG_TRIM_BUSY_MSK BIT(SYSCFG_TRIM_BUSY_POS) + +#define SYSCFG_TRIM_HRCTRIM_POSS 8U +#define SYSCFG_TRIM_HRCTRIM_POSE 15U +#define SYSCFG_TRIM_HRCTRIM_MSK BITS(SYSCFG_TRIM_HRCTRIM_POSS,SYSCFG_TRIM_HRCTRIM_POSE) + +#define SYSCFG_TRIM_TSRC_POS 1U +#define SYSCFG_TRIM_TSRC_MSK BIT(SYSCFG_TRIM_TSRC_POS) + +#define SYSCFG_TRIM_TRIM_POS 0U +#define SYSCFG_TRIM_TRIM_MSK BIT(SYSCFG_TRIM_TRIM_POS) + +/****************** Bit definition for SYSCFG_IRSEL register ************************/ + +#define SYSCFG_IRSEL_PLR_POS 8U +#define SYSCFG_IRSEL_PLR_MSK BIT(SYSCFG_IRSEL_PLR_POS) + +#define SYSCFG_IRSEL_SEL2_POSS 4U +#define SYSCFG_IRSEL_SEL2_POSE 7U +#define SYSCFG_IRSEL_SEL2_MSK BITS(SYSCFG_IRSEL_SEL2_POSS,SYSCFG_IRSEL_SEL2_POSE) + +#define SYSCFG_IRSEL_SEL1_POSS 0U +#define SYSCFG_IRSEL_SEL1_POSE 3U +#define SYSCFG_IRSEL_SEL1_MSK BITS(SYSCFG_IRSEL_SEL1_POSS,SYSCFG_IRSEL_SEL1_POSE) + +/****************** Bit definition for SYSCFG_CFG register ************************/ + +#define SYSCFG_CFG_DBGH_EN_POSS 16U +#define SYSCFG_CFG_DBGH_EN_POSE 31U +#define SYSCFG_CFG_DBGH_EN_MSK BITS(SYSCFG_CFG_DBGH_EN_POSS,SYSCFG_CFG_DBGH_EN_POSE) + +#define SYSCFG_CFG_PVD_LCK_POS 14U +#define SYSCFG_CFG_PVD_LCK_MSK BIT(SYSCFG_CFG_PVD_LCK_POS) + +#define SYSCFG_CFG_CSS_LCK_POS 13U +#define SYSCFG_CFG_CSS_LCK_MSK BIT(SYSCFG_CFG_CSS_LCK_POS) + +#define SYSCFG_CFG_CPU_LCK_POS 12U +#define SYSCFG_CFG_CPU_LCK_MSK BIT(SYSCFG_CFG_CPU_LCK_POS) + +#define SYSCFG_CFG_VTST_POSS 8U +#define SYSCFG_CFG_VTST_POSE 9U +#define SYSCFG_CFG_VTST_MSK BITS(SYSCFG_CFG_VTST_POSS,SYSCFG_CFG_VTST_POSE) + +#define SYSCFG_CFG_NRSTREQ_POS 7U +#define SYSCFG_CFG_NRSTREQ_MSK BIT(SYSCFG_CFG_NRSTREQ_POS) + +#define SYSCFG_CFG_CURRGEN_POS 5U +#define SYSCFG_CFG_CURRGEN_MSK BIT(SYSCFG_CFG_CURRGEN_POS) + +#define SYSCFG_CFG_TEMPEN_POS 4U +#define SYSCFG_CFG_TEMPEN_MSK BIT(SYSCFG_CFG_TEMPEN_POS) + +#define SYSCFG_CFG_VREFEN_POS 3U +#define SYSCFG_CFG_VREFEN_MSK BIT(SYSCFG_CFG_VREFEN_POS) + +#define SYSCFG_CFG_VRLS_POSS 0U +#define SYSCFG_CFG_VRLS_POSE 2U +#define SYSCFG_CFG_VRLS_MSK BITS(SYSCFG_CFG_VRLS_POSS,SYSCFG_CFG_VRLS_POSE) + +/****************** Bit definition for SYSCFG_PWCON register ************************/ + +#define SYSCFG_PWCON_IOLOCK_POS 23U +#define SYSCFG_PWCON_IOLOCK_MSK BIT(SYSCFG_PWCON_IOLOCK_POS) + +#define SYSCFG_PWCON_BGTRIM_POSS 17U +#define SYSCFG_PWCON_BGTRIM_POSE 20U +#define SYSCFG_PWCON_BGTRIM_MSK BITS(SYSCFG_PWCON_BGTRIM_POSS,SYSCFG_PWCON_BGTRIM_POSE) + +#define SYSCFG_PWCON_HRCLOCK_POS 16U +#define SYSCFG_PWCON_HRCLOCK_MSK BIT(SYSCFG_PWCON_HRCLOCK_POS) + +#define SYSCFG_PWCON_HRCTRIM_POSS 8U +#define SYSCFG_PWCON_HRCTRIM_POSE 15U +#define SYSCFG_PWCON_HRCTRIM_MSK BITS(SYSCFG_PWCON_HRCTRIM_POSS,SYSCFG_PWCON_HRCTRIM_POSE) + +#define SYSCFG_PWCON_LOSCDRV_POSS 5U +#define SYSCFG_PWCON_LOSCDRV_POSE 7U +#define SYSCFG_PWCON_LOSCDRV_MSK BITS(SYSCFG_PWCON_LOSCDRV_POSS,SYSCFG_PWCON_LOSCDRV_POSE) + +#define SYSCFG_PWCON_PVDEN_POS 4U +#define SYSCFG_PWCON_PVDEN_MSK BIT(SYSCFG_PWCON_PVDEN_POS) + +#define SYSCFG_PWCON_PVLS_POSS 0U +#define SYSCFG_PWCON_PVLS_POSE 3U +#define SYSCFG_PWCON_PVLS_MSK BITS(SYSCFG_PWCON_PVLS_POSS,SYSCFG_PWCON_PVLS_POSE) + +/****************** Bit definition for SYSCFG_WKCON register ************************/ + +#define SYSCFG_WKCON_WKCLR_POS 31U +#define SYSCFG_WKCON_WKCLR_MSK BIT(SYSCFG_WKCON_WKCLR_POS) + +#define SYSCFG_WKCON_LPLS_POSS 28U +#define SYSCFG_WKCON_LPLS_POSE 30U +#define SYSCFG_WKCON_LPLS_MSK BITS(SYSCFG_WKCON_LPLS_POSS,SYSCFG_WKCON_LPLS_POSE) + +#define SYSCFG_WKCON_WKEG_POSS 16U +#define SYSCFG_WKCON_WKEG_POSE 27U +#define SYSCFG_WKCON_WKEG_MSK BITS(SYSCFG_WKCON_WKEG_POSS,SYSCFG_WKCON_WKEG_POSE) + +#define SYSCFG_WKCON_WKEN_POSS 0U +#define SYSCFG_WKCON_WKEN_POSE 11U +#define SYSCFG_WKCON_WKEN_MSK BITS(SYSCFG_WKCON_WKEN_POSS,SYSCFG_WKCON_WKEN_POSE) + +/****************** Bit definition for SYSCFG_WKSTAT register ************************/ + +#define SYSCFG_WKSTAT_FLAG_POS 16U +#define SYSCFG_WKSTAT_FLAG_MSK BIT(SYSCFG_WKSTAT_FLAG_POS) + +#define SYSCFG_WKSTAT_FG_POSS 0U +#define SYSCFG_WKSTAT_FG_POSE 11U +#define SYSCFG_WKSTAT_FG_MSK BITS(SYSCFG_WKSTAT_FG_POSS,SYSCFG_WKSTAT_FG_POSE) + +/****************** Bit definition for SYSCFG_BKREG0 register ************************/ + +#define SYSCFG_BKREG0_BKREG0_POSS 0U +#define SYSCFG_BKREG0_BKREG0_POSE 31U +#define SYSCFG_BKREG0_BKREG0_MSK BITS(SYSCFG_BKREG0_BKREG0_POSS,SYSCFG_BKREG0_BKREG0_POSE) + +/****************** Bit definition for SYSCFG_BKREG1 register ************************/ + +#define SYSCFG_BKREG1_BKREG1_POSS 0U +#define SYSCFG_BKREG1_BKREG1_POSE 31U +#define SYSCFG_BKREG1_BKREG1_MSK BITS(SYSCFG_BKREG1_BKREG1_POSS,SYSCFG_BKREG1_BKREG1_POSE) + +/****************** Bit definition for SYSCFG_BKREG2 register ************************/ + +#define SYSCFG_BKREG2_BKREG2_POSS 0U +#define SYSCFG_BKREG2_BKREG2_POSE 31U +#define SYSCFG_BKREG2_BKREG2_MSK BITS(SYSCFG_BKREG2_BKREG2_POSS,SYSCFG_BKREG2_BKREG2_POSE) + +/****************** Bit definition for SYSCFG_BKREG3 register ************************/ + +#define SYSCFG_BKREG3_BKREG3_POSS 0U +#define SYSCFG_BKREG3_BKREG3_POSE 29U +#define SYSCFG_BKREG3_BKREG3_MSK BITS(SYSCFG_BKREG3_BKREG3_POSS,SYSCFG_BKREG3_BKREG3_POSE) + +typedef struct +{ + __O uint32_t REMAP; + __O uint32_t TRIM; + __IO uint32_t IRSEL; + uint32_t RESERVED0[12] ; + __IO uint32_t CFG; + __IO uint32_t PWCON; + uint32_t RESERVED1 ; + __IO uint32_t WKCON; + __I uint32_t WKSTAT; + __IO uint32_t BKREG0; + __IO uint32_t BKREG1; + __IO uint32_t BKREG2; + __IO uint32_t BKREG3; +} SYSCFG_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_tick.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_tick.h new file mode 100644 index 0000000000000000000000000000000000000000..13122aef46b42f4f92ed933d9b8a77f921cc83a3 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_tick.h @@ -0,0 +1,113 @@ +/** + ************************************************************************************** + * @file reg_TICK.h + * @brief TICK Head File + * + * @version V1.00.01 + * @date 19/10/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __TICK_H__ +#define __TICK_H__ + +/******************************************************************************/ +/* Ȧs줸wq */ +/******************************************************************************/ + +/* #pragma anon_unions */ + +/****************** Bit definition for TICK_CSR register ************************/ + +#define TICK_CSR_ENABLE_POS 0U +#define TICK_CSR_ENABLE_MSK BIT(TICK_CSR_ENABLE_POS) + +#define TICK_CSR_TICKINT_POS 1U +#define TICK_CSR_TICKINT_MSK BIT(TICK_CSR_TICKINT_POS) + +#define TICK_CSR_CLKSOURCE_POS 2U +#define TICK_CSR_CLKSOURCE_MSK BIT(TICK_CSR_CLKSOURCE_POS) + +#define TICK_CSR_COUNTFLAG_POS 16U +#define TICK_CSR_COUNTFLAG_MSK BIT(TICK_CSR_COUNTFLAG_POS) + +/****************** Bit definition for TICK_RVR register ************************/ + +#define TICK_RVR_RELOAD_POSS 0U +#define TICK_RVR_RELOAD_POSE 23U +#define TICK_RVR_RELOAD_MSK BITS(TICK_RVR_RELOAD_POSS,TICK_RVR_RELOAD_POSE) + +/****************** Bit definition for TICK_CVR register ************************/ + +#define TICK_CVR_CURRENT_POSS 0U +#define TICK_CVR_CURRENT_POSE 23U +#define TICK_CVR_CURRENT_MSK BITS(TICK_CVR_CURRENT_POSS,TICK_CVR_CURRENT_POSE) + + +/****************** Bit definition for TICK_CALIB register ************************/ + +#define TICK_CALIB_TENMS_POSS 0U +#define TICK_CALIB_TENMS_POSE 23U +#define TICK_CALIB_TENMS_MSK BITS(TICK_CALIB_TENMS_POSS,TICK_CALIB_TENMS_POSE) + +#define TICK_CALIB_SKEW_POS 30U +#define TICK_CALIB_SKEW_MSK BIT(TICK_CALIB_SKEW_POS) + +#define TICK_CALIB_NOREF_POS 31U +#define TICK_CALIB_NOREF_MSK BIT(TICK_CALIB_NOREF_POS) + + +/* TICK Register */ +#define pTICK TICK + +/* TICK CSR Register(TICK_CSR) */ +#define CSR_COUNTFLAG(x) (x<<16) /* Indicates whether the counter has counted to 0 since the last read of this register + 0 timer has not counted to 0 + 1 timer has counted to 0 */ +#define CSR_CLKSOURCE(x) (x<<2) /* Indicates the SysTick clock source: + 0 SysTick uses the optional external reference clock + 1 SysTick uses the processor clock */ +#define CSR_TICKINT(x) (x<<1) /* Indicates whether counting to 0 causes the status of the SysTick exception to change to pending: + 0 count to 0 does not affect the SysTick exception status + 1 count to 0 changes the SysTick exception status to pending */ +#define CSR_ENABLE(x) (x<<0) /* /Indicates the enabled status of the SysTick counter: + 0 counter is disabled + 1 counter is operating */ + + +/* TICK RVR Register(TICK_RVR) */ +#define RVR_RELOAD(x) (x<<0) /* The value to load into the SYST_CVR register when the counter reaches 0 */ + + +/* TICK CVR Register(TICK_CVR) */ +#define CVR_CURRENT(x) (x<<0) /* Current counter value + This is the value of the counter at the time it is sampled */ + + +/* TICK CALIB Register(TICK_CALIB) */ +#define CALIB_NOREF(x) (x<<31) /* Indicates whether the IMPLEMENTATION DEFINED reference clock is provided: + 0 the reference clock is implemented + 1 the reference clock is not implemented + When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to 1 and cannot be cleared to 0 */ +#define CALIB_SKEW(x) (x<<30) /* Indicates whether the 10ms calibration value is exact: + 0 10ms calibration value is exact + 1 10ms calibration value is inexact, because of the clock frequency */ +#define CALIB_TENMS(x) (x<<0) /* Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. + If this field is zero, the calibration value is not known */ +typedef struct +{ + __IO uint32_t CSR; /* 0x0, Control and Status */ + __IO uint32_t RVR; /* 0x4, Reload Value */ + __IO uint32_t CVR; /* 0x8, Current Value */ + __I uint32_t CALIB; /* 0xC, Calibration */ +} TICK_TypeDef; + + +#else +/* */ +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_uart.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..1cd5670f8edf067178451720645f2d19d1478944 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_uart.h @@ -0,0 +1,606 @@ +/** + ************************************************************************************** + * @file REG_UART.h + * @brief UART Head File + * + * @version V0.01 + * @data 12/3/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __UART_H__ +#define __UART_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for UART_RXBUF register ************************/ + +#define UART_RXBUF_RXBUF_POSS 0U +#define UART_RXBUF_RXBUF_POSE 8U +#define UART_RXBUF_RXBUF_MSK BITS(UART_RXBUF_RXBUF_POSS,UART_RXBUF_RXBUF_POSE) + +/****************** Bit definition for UART_TXBUF register ************************/ + +#define UART_TXBUF_TXBUF_POSS 0U +#define UART_TXBUF_TXBUF_POSE 8U +#define UART_TXBUF_TXBUF_MSK BITS(UART_TXBUF_TXBUF_POSS,UART_TXBUF_TXBUF_POSE) + +/****************** Bit definition for UART_BRR register ************************/ + +#define UART_BRR_BRR_POSS 0U +#define UART_BRR_BRR_POSE 15U +#define UART_BRR_BRR_MSK BITS(UART_BRR_BRR_POSS,UART_BRR_BRR_POSE) + +/****************** Bit definition for UART_LCON register ************************/ + +#define UART_LCON_TXEN_POS 15U +#define UART_LCON_TXEN_MSK BIT(UART_LCON_TXEN_POS) + +#define UART_LCON_RXEN_POS 14U +#define UART_LCON_RXEN_MSK BIT(UART_LCON_RXEN_POS) + +#define UART_LCON_DBCEN_POS 13U +#define UART_LCON_DBCEN_MSK BIT(UART_LCON_DBCEN_POS) + +#define UART_LCON_BREAK_POS 10U +#define UART_LCON_BREAK_MSK BIT(UART_LCON_BREAK_POS) + +#define UART_LCON_SWAP_POS 9U +#define UART_LCON_SWAP_MSK BIT(UART_LCON_SWAP_POS) + +#define UART_LCON_TXINV_POS 8U +#define UART_LCON_TXINV_MSK BIT(UART_LCON_TXINV_POS) + +#define UART_LCON_RXINV_POS 7U +#define UART_LCON_RXINV_MSK BIT(UART_LCON_RXINV_POS) + +#define UART_LCON_DATAINV_POS 6U +#define UART_LCON_DATAINV_MSK BIT(UART_LCON_DATAINV_POS) + +#define UART_LCON_MSB_POS 5U +#define UART_LCON_MSB_MSK BIT(UART_LCON_MSB_POS) + +#define UART_LCON_PS_POS 4U +#define UART_LCON_PS_MSK BIT(UART_LCON_PS_POS) + +#define UART_LCON_PE_POS 3U +#define UART_LCON_PE_MSK BIT(UART_LCON_PE_POS) + +#define UART_LCON_STOP_POS 2U +#define UART_LCON_STOP_MSK BIT(UART_LCON_STOP_POS) + +#define UART_LCON_DLS_POSS 0U +#define UART_LCON_DLS_POSE 1U +#define UART_LCON_DLS_MSK BITS(UART_LCON_DLS_POSS,UART_LCON_DLS_POSE) + +/****************** Bit definition for UART_MCON register ************************/ + +#define UART_MCON_TXDMAEN_POS 15U +#define UART_MCON_TXDMAEN_MSK BIT(UART_MCON_TXDMAEN_POS) + +#define UART_MCON_RXDMAEN_POS 14U +#define UART_MCON_RXDMAEN_MSK BIT(UART_MCON_RXDMAEN_POS) + +#define UART_MCON_ABRREPT_POS 11U +#define UART_MCON_ABRREPT_MSK BIT(UART_MCON_ABRREPT_POS) + +#define UART_MCON_ABRMOD_POSS 9U +#define UART_MCON_ABRMOD_POSE 10U +#define UART_MCON_ABRMOD_MSK BITS(UART_MCON_ABRMOD_POSS,UART_MCON_ABRMOD_POSE) + +#define UART_MCON_ABREN_POS 8U +#define UART_MCON_ABREN_MSK BIT(UART_MCON_ABREN_POS) + +#define UART_MCON_BKREQ_POS 5U +#define UART_MCON_BKREQ_MSK BIT(UART_MCON_BKREQ_POS) + +#define UART_MCON_HDEN_POS 4U +#define UART_MCON_HDEN_MSK BIT(UART_MCON_HDEN_POS) + +#define UART_MCON_IREN_POS 3U +#define UART_MCON_IREN_MSK BIT(UART_MCON_IREN_POS) + +#define UART_MCON_AFCEN_POS 2U +#define UART_MCON_AFCEN_MSK BIT(UART_MCON_AFCEN_POS) + +#define UART_MCON_RTSSET_POS 1U +#define UART_MCON_RTSSET_MSK BIT(UART_MCON_RTSSET_POS) + +#define UART_MCON_LPBKEN_POS 0U +#define UART_MCON_LPBKEN_MSK BIT(UART_MCON_LPBKEN_POS) + +/****************** Bit definition for UART_RS485 register ************************/ + +#define UART_RS485_DLY_POSS 16U +#define UART_RS485_DLY_POSE 23U +#define UART_RS485_DLY_MSK BITS(UART_RS485_DLY_POSS,UART_RS485_DLY_POSE) + +#define UART_RS485_ADDR_POSS 8U +#define UART_RS485_ADDR_POSE 15U +#define UART_RS485_ADDR_MSK BITS(UART_RS485_ADDR_POSS,UART_RS485_ADDR_POSE) + +#define UART_RS485_AADINV_POS 3U +#define UART_RS485_AADINV_MSK BIT(UART_RS485_AADINV_POS) + +#define UART_RS485_AADACEN_POS 2U +#define UART_RS485_AADACEN_MSK BIT(UART_RS485_AADACEN_POS) + +#define UART_RS485_AADNEN_POS 1U +#define UART_RS485_AADNEN_MSK BIT(UART_RS485_AADNEN_POS) + +#define UART_RS485_AADEN_POS 0U +#define UART_RS485_AADEN_MSK BIT(UART_RS485_AADEN_POS) + +/****************** Bit definition for UART_SCARD register ************************/ + +#define UART_SCARD_BLEN_POSS 24U +#define UART_SCARD_BLEN_POSE 31U +#define UART_SCARD_BLEN_MSK BITS(UART_SCARD_BLEN_POSS,UART_SCARD_BLEN_POSE) + +#define UART_SCARD_GT_POSS 16U +#define UART_SCARD_GT_POSE 23U +#define UART_SCARD_GT_MSK BITS(UART_SCARD_GT_POSS,UART_SCARD_GT_POSE) + +#define UART_SCARD_PSC_POSS 8U +#define UART_SCARD_PSC_POSE 15U +#define UART_SCARD_PSC_MSK BITS(UART_SCARD_PSC_POSS,UART_SCARD_PSC_POSE) + +#define UART_SCARD_SCCNT_POSS 3U +#define UART_SCARD_SCCNT_POSE 5U +#define UART_SCARD_SCCNT_MSK BITS(UART_SCARD_SCCNT_POSS,UART_SCARD_SCCNT_POSE) + +#define UART_SCARD_SCLKEN_POS 2U +#define UART_SCARD_SCLKEN_MSK BIT(UART_SCARD_SCLKEN_POS) + +#define UART_SCARD_SCNACK_POS 1U +#define UART_SCARD_SCNACK_MSK BIT(UART_SCARD_SCNACK_POS) + +#define UART_SCARD_SCEN_POS 0U +#define UART_SCARD_SCEN_MSK BIT(UART_SCARD_SCEN_POS) + +/****************** Bit definition for UART_LIN register ************************/ + +#define UART_LIN_LINBKREQ_POS 2U +#define UART_LIN_LINBKREQ_MSK BIT(UART_LIN_LINBKREQ_POS) + +#define UART_LIN_LINBDL_POS 1U +#define UART_LIN_LINBDL_MSK BIT(UART_LIN_LINBDL_POS) + +#define UART_LIN_LINEN_POS 0U +#define UART_LIN_LINEN_MSK BIT(UART_LIN_LINEN_POS) + +/****************** Bit definition for UART_RTOR register ************************/ + +#define UART_RTOR_RTOEN_POS 24U +#define UART_RTOR_RTOEN_MSK BIT(UART_RTOR_RTOEN_POS) + +#define UART_RTOR_RTO_POSS 0U +#define UART_RTOR_RTO_POSE 23U +#define UART_RTOR_RTO_MSK BITS(UART_RTOR_RTO_POSS,UART_RTOR_RTO_POSE) + +/****************** Bit definition for UART_FCON register ************************/ + +#define UART_FCON_TXFL_POSS 11U +#define UART_FCON_TXFL_POSE 15U +#define UART_FCON_TXFL_MSK BITS(UART_FCON_TXFL_POSS,UART_FCON_TXFL_POSE) + +#define UART_FCON_TXTH_POSS 9U +#define UART_FCON_TXTH_POSE 10U +#define UART_FCON_TXTH_MSK BITS(UART_FCON_TXTH_POSS,UART_FCON_TXTH_POSE) + +#define UART_FCON_TFRST_POS 8U +#define UART_FCON_TFRST_MSK BIT(UART_FCON_TFRST_POS) + +#define UART_FCON_RXFL_POSS 3U +#define UART_FCON_RXFL_POSE 7U +#define UART_FCON_RXFL_MSK BITS(UART_FCON_RXFL_POSS,UART_FCON_RXFL_POSE) + +#define UART_FCON_RXTH_POSS 1U +#define UART_FCON_RXTH_POSE 2U +#define UART_FCON_RXTH_MSK BITS(UART_FCON_RXTH_POSS,UART_FCON_RXTH_POSE) + +#define UART_FCON_RFRST_POS 0U +#define UART_FCON_RFRST_MSK BIT(UART_FCON_RFRST_POS) + +/****************** Bit definition for UART_STAT register ************************/ + +#define UART_STAT_TFOERR_POS 18U +#define UART_STAT_TFOERR_MSK BIT(UART_STAT_TFOERR_POS) + +#define UART_STAT_TFFULL_POS 17U +#define UART_STAT_TFFULL_MSK BIT(UART_STAT_TFFULL_POS) + +#define UART_STAT_TFEMPTY_POS 16U +#define UART_STAT_TFEMPTY_MSK BIT(UART_STAT_TFEMPTY_POS) + +#define UART_STAT_TFTH_POS 15U +#define UART_STAT_TFTH_MSK BIT(UART_STAT_TFTH_POS) + +#define UART_STAT_TSBUSY_POS 14U +#define UART_STAT_TSBUSY_MSK BIT(UART_STAT_TSBUSY_POS) + +#define UART_STAT_RFUERR_POS 13U +#define UART_STAT_RFUERR_MSK BIT(UART_STAT_RFUERR_POS) + +#define UART_STAT_RFOERR_POS 12U +#define UART_STAT_RFOERR_MSK BIT(UART_STAT_RFOERR_POS) + +#define UART_STAT_RFFULL_POS 11U +#define UART_STAT_RFFULL_MSK BIT(UART_STAT_RFFULL_POS) + +#define UART_STAT_RFEMPTY_POS 10U +#define UART_STAT_RFEMPTY_MSK BIT(UART_STAT_RFEMPTY_POS) + +#define UART_STAT_RFTH_POS 9U +#define UART_STAT_RFTH_MSK BIT(UART_STAT_RFTH_POS) + +#define UART_STAT_RSBUSY_POS 8U +#define UART_STAT_RSBUSY_MSK BIT(UART_STAT_RSBUSY_POS) + +#define UART_STAT_CTSSTA_POS 3U +#define UART_STAT_CTSSTA_MSK BIT(UART_STAT_CTSSTA_POS) + +#define UART_STAT_BKERR_POS 2U +#define UART_STAT_BKERR_MSK BIT(UART_STAT_BKERR_POS) + +#define UART_STAT_FERR_POS 1U +#define UART_STAT_FERR_MSK BIT(UART_STAT_FERR_POS) + +#define UART_STAT_PERR_POS 0U +#define UART_STAT_PERR_MSK BIT(UART_STAT_PERR_POS) + +/****************** Bit definition for UART_IER register ************************/ + +#define UART_IER_TFOVER_POS 18U +#define UART_IER_TFOVER_MSK BIT(UART_IER_TFOVER_POS) + +#define UART_IER_TFEMPTY_POS 16U +#define UART_IER_TFEMPTY_MSK BIT(UART_IER_TFEMPTY_POS) + +#define UART_IER_TFTH_POS 15U +#define UART_IER_TFTH_MSK BIT(UART_IER_TFTH_POS) + +#define UART_IER_TBC_POS 14U +#define UART_IER_TBC_MSK BIT(UART_IER_TBC_POS) + +#define UART_IER_RFUERR_POS 13U +#define UART_IER_RFUERR_MSK BIT(UART_IER_RFUERR_POS) + +#define UART_IER_RFOERR_POS 12U +#define UART_IER_RFOERR_MSK BIT(UART_IER_RFOERR_POS) + +#define UART_IER_RFFULL_POS 11U +#define UART_IER_RFFULL_MSK BIT(UART_IER_RFFULL_POS) + +#define UART_IER_RFTH_POS 9U +#define UART_IER_RFTH_MSK BIT(UART_IER_RFTH_POS) + +#define UART_IER_NOISE_POS 8U +#define UART_IER_NOISE_MSK BIT(UART_IER_NOISE_POS) + +#define UART_IER_EOB_POS 7U +#define UART_IER_EOB_MSK BIT(UART_IER_EOB_POS) + +#define UART_IER_LINBK_POS 6U +#define UART_IER_LINBK_MSK BIT(UART_IER_LINBK_POS) + +#define UART_IER_ADDRM_POS 5U +#define UART_IER_ADDRM_MSK BIT(UART_IER_ADDRM_POS) + +#define UART_IER_RXTO_POS 4U +#define UART_IER_RXTO_MSK BIT(UART_IER_RXTO_POS) + +#define UART_IER_DCTS_POS 3U +#define UART_IER_DCTS_MSK BIT(UART_IER_DCTS_POS) + +#define UART_IER_ABTO_POS 2U +#define UART_IER_ABTO_MSK BIT(UART_IER_ABTO_POS) + +#define UART_IER_ABEND_POS 1U +#define UART_IER_ABEND_MSK BIT(UART_IER_ABEND_POS) + +#define UART_IER_RXBERR_POS 0U +#define UART_IER_RXBERR_MSK BIT(UART_IER_RXBERR_POS) + +/****************** Bit definition for UART_IDR register ************************/ + +#define UART_IDR_TFOVER_POS 18U +#define UART_IDR_TFOVER_MSK BIT(UART_IDR_TFOVER_POS) + +#define UART_IDR_TFEMPTY_POS 16U +#define UART_IDR_TFEMPTY_MSK BIT(UART_IDR_TFEMPTY_POS) + +#define UART_IDR_TFTH_POS 15U +#define UART_IDR_TFTH_MSK BIT(UART_IDR_TFTH_POS) + +#define UART_IDR_TBC_POS 14U +#define UART_IDR_TBC_MSK BIT(UART_IDR_TBC_POS) + +#define UART_IDR_RFUERR_POS 13U +#define UART_IDR_RFUERR_MSK BIT(UART_IDR_RFUERR_POS) + +#define UART_IDR_RFOERR_POS 12U +#define UART_IDR_RFOERR_MSK BIT(UART_IDR_RFOERR_POS) + +#define UART_IDR_RFFULL_POS 11U +#define UART_IDR_RFFULL_MSK BIT(UART_IDR_RFFULL_POS) + +#define UART_IDR_RFTH_POS 9U +#define UART_IDR_RFTH_MSK BIT(UART_IDR_RFTH_POS) + +#define UART_IDR_NOISE_POS 8U +#define UART_IDR_NOISE_MSK BIT(UART_IDR_NOISE_POS) + +#define UART_IDR_EOB_POS 7U +#define UART_IDR_EOB_MSK BIT(UART_IDR_EOB_POS) + +#define UART_IDR_LINBK_POS 6U +#define UART_IDR_LINBK_MSK BIT(UART_IDR_LINBK_POS) + +#define UART_IDR_ADDRM_POS 5U +#define UART_IDR_ADDRM_MSK BIT(UART_IDR_ADDRM_POS) + +#define UART_IDR_RXTO_POS 4U +#define UART_IDR_RXTO_MSK BIT(UART_IDR_RXTO_POS) + +#define UART_IDR_DCTS_POS 3U +#define UART_IDR_DCTS_MSK BIT(UART_IDR_DCTS_POS) + +#define UART_IDR_ABTO_POS 2U +#define UART_IDR_ABTO_MSK BIT(UART_IDR_ABTO_POS) + +#define UART_IDR_ABEND_POS 1U +#define UART_IDR_ABEND_MSK BIT(UART_IDR_ABEND_POS) + +#define UART_IDR_RXBERR_POS 0U +#define UART_IDR_RXBERR_MSK BIT(UART_IDR_RXBERR_POS) + +/****************** Bit definition for UART_IVS register ************************/ + +#define UART_IVS_TFOVER_POS 18U +#define UART_IVS_TFOVER_MSK BIT(UART_IVS_TFOVER_POS) + +#define UART_IVS_TFEMPTY_POS 16U +#define UART_IVS_TFEMPTY_MSK BIT(UART_IVS_TFEMPTY_POS) + +#define UART_IVS_TFTH_POS 15U +#define UART_IVS_TFTH_MSK BIT(UART_IVS_TFTH_POS) + +#define UART_IVS_TBC_POS 14U +#define UART_IVS_TBC_MSK BIT(UART_IVS_TBC_POS) + +#define UART_IVS_RFUERR_POS 13U +#define UART_IVS_RFUERR_MSK BIT(UART_IVS_RFUERR_POS) + +#define UART_IVS_RFOERR_POS 12U +#define UART_IVS_RFOERR_MSK BIT(UART_IVS_RFOERR_POS) + +#define UART_IVS_RFFULL_POS 11U +#define UART_IVS_RFFULL_MSK BIT(UART_IVS_RFFULL_POS) + +#define UART_IVS_RFTH_POS 9U +#define UART_IVS_RFTH_MSK BIT(UART_IVS_RFTH_POS) + +#define UART_IVS_NOISE_POS 8U +#define UART_IVS_NOISE_MSK BIT(UART_IVS_NOISE_POS) + +#define UART_IVS_EOB_POS 7U +#define UART_IVS_EOB_MSK BIT(UART_IVS_EOB_POS) + +#define UART_IVS_LINBK_POS 6U +#define UART_IVS_LINBK_MSK BIT(UART_IVS_LINBK_POS) + +#define UART_IVS_ADDRM_POS 5U +#define UART_IVS_ADDRM_MSK BIT(UART_IVS_ADDRM_POS) + +#define UART_IVS_RXTO_POS 4U +#define UART_IVS_RXTO_MSK BIT(UART_IVS_RXTO_POS) + +#define UART_IVS_DCTS_POS 3U +#define UART_IVS_DCTS_MSK BIT(UART_IVS_DCTS_POS) + +#define UART_IVS_ABTO_POS 2U +#define UART_IVS_ABTO_MSK BIT(UART_IVS_ABTO_POS) + +#define UART_IVS_ABEND_POS 1U +#define UART_IVS_ABEND_MSK BIT(UART_IVS_ABEND_POS) + +#define UART_IVS_RXBERR_POS 0U +#define UART_IVS_RXBERR_MSK BIT(UART_IVS_RXBERR_POS) + +/****************** Bit definition for UART_RIF register ************************/ + +#define UART_RIF_TFOVER_POS 18U +#define UART_RIF_TFOVER_MSK BIT(UART_RIF_TFOVER_POS) + +#define UART_RIF_TFEMPTY_POS 16U +#define UART_RIF_TFEMPTY_MSK BIT(UART_RIF_TFEMPTY_POS) + +#define UART_RIF_TFTH_POS 15U +#define UART_RIF_TFTH_MSK BIT(UART_RIF_TFTH_POS) + +#define UART_RIF_TBC_POS 14U +#define UART_RIF_TBC_MSK BIT(UART_RIF_TBC_POS) + +#define UART_RIF_RFUERR_POS 13U +#define UART_RIF_RFUERR_MSK BIT(UART_RIF_RFUERR_POS) + +#define UART_RIF_RFOERR_POS 12U +#define UART_RIF_RFOERR_MSK BIT(UART_RIF_RFOERR_POS) + +#define UART_RIF_RFFULL_POS 11U +#define UART_RIF_RFFULL_MSK BIT(UART_RIF_RFFULL_POS) + +#define UART_RIF_RFTH_POS 9U +#define UART_RIF_RFTH_MSK BIT(UART_RIF_RFTH_POS) + +#define UART_RIF_NOISE_POS 8U +#define UART_RIF_NOISE_MSK BIT(UART_RIF_NOISE_POS) + +#define UART_RIF_EOB_POS 7U +#define UART_RIF_EOB_MSK BIT(UART_RIF_EOB_POS) + +#define UART_RIF_LINBK_POS 6U +#define UART_RIF_LINBK_MSK BIT(UART_RIF_LINBK_POS) + +#define UART_RIF_ADDRM_POS 5U +#define UART_RIF_ADDRM_MSK BIT(UART_RIF_ADDRM_POS) + +#define UART_RIF_RXTO_POS 4U +#define UART_RIF_RXTO_MSK BIT(UART_RIF_RXTO_POS) + +#define UART_RIF_DCTS_POS 3U +#define UART_RIF_DCTS_MSK BIT(UART_RIF_DCTS_POS) + +#define UART_RIF_ABTO_POS 2U +#define UART_RIF_ABTO_MSK BIT(UART_RIF_ABTO_POS) + +#define UART_RIF_ABEND_POS 1U +#define UART_RIF_ABEND_MSK BIT(UART_RIF_ABEND_POS) + +#define UART_RIF_RXBERR_POS 0U +#define UART_RIF_RXBERR_MSK BIT(UART_RIF_RXBERR_POS) + +/****************** Bit definition for UART_IFM register ************************/ + +#define UART_IFM_TFOVER_POS 18U +#define UART_IFM_TFOVER_MSK BIT(UART_IFM_TFOVER_POS) + +#define UART_IFM_TFEMPTY_POS 16U +#define UART_IFM_TFEMPTY_MSK BIT(UART_IFM_TFEMPTY_POS) + +#define UART_IFM_TFTH_POS 15U +#define UART_IFM_TFTH_MSK BIT(UART_IFM_TFTH_POS) + +#define UART_IFM_TBC_POS 14U +#define UART_IFM_TBC_MSK BIT(UART_IFM_TBC_POS) + +#define UART_IFM_RFUERR_POS 13U +#define UART_IFM_RFUERR_MSK BIT(UART_IFM_RFUERR_POS) + +#define UART_IFM_RFOERR_POS 12U +#define UART_IFM_RFOERR_MSK BIT(UART_IFM_RFOERR_POS) + +#define UART_IFM_RFFULL_POS 11U +#define UART_IFM_RFFULL_MSK BIT(UART_IFM_RFFULL_POS) + +#define UART_IFM_RFTH_POS 9U +#define UART_IFM_RFTH_MSK BIT(UART_IFM_RFTH_POS) + +#define UART_IFM_NOISE_POS 8U +#define UART_IFM_NOISE_MSK BIT(UART_IFM_NOISE_POS) + +#define UART_IFM_EOB_POS 7U +#define UART_IFM_EOB_MSK BIT(UART_IFM_EOB_POS) + +#define UART_IFM_LINBK_POS 6U +#define UART_IFM_LINBK_MSK BIT(UART_IFM_LINBK_POS) + +#define UART_IFM_ADDRM_POS 5U +#define UART_IFM_ADDRM_MSK BIT(UART_IFM_ADDRM_POS) + +#define UART_IFM_RXTO_POS 4U +#define UART_IFM_RXTO_MSK BIT(UART_IFM_RXTO_POS) + +#define UART_IFM_DCTS_POS 3U +#define UART_IFM_DCTS_MSK BIT(UART_IFM_DCTS_POS) + +#define UART_IFM_ABTO_POS 2U +#define UART_IFM_ABTO_MSK BIT(UART_IFM_ABTO_POS) + +#define UART_IFM_ABEND_POS 1U +#define UART_IFM_ABEND_MSK BIT(UART_IFM_ABEND_POS) + +#define UART_IFM_RXBERR_POS 0U +#define UART_IFM_RXBERR_MSK BIT(UART_IFM_RXBERR_POS) + +/****************** Bit definition for UART_ICR register ************************/ + +#define UART_ICR_TFOVER_POS 18U +#define UART_ICR_TFOVER_MSK BIT(UART_ICR_TFOVER_POS) + +#define UART_ICR_TFEMPTY_POS 16U +#define UART_ICR_TFEMPTY_MSK BIT(UART_ICR_TFEMPTY_POS) + +#define UART_ICR_TFTH_POS 15U +#define UART_ICR_TFTH_MSK BIT(UART_ICR_TFTH_POS) + +#define UART_ICR_TBC_POS 14U +#define UART_ICR_TBC_MSK BIT(UART_ICR_TBC_POS) + +#define UART_ICR_RFUERR_POS 13U +#define UART_ICR_RFUERR_MSK BIT(UART_ICR_RFUERR_POS) + +#define UART_ICR_RFOERR_POS 12U +#define UART_ICR_RFOERR_MSK BIT(UART_ICR_RFOERR_POS) + +#define UART_ICR_RFFULL_POS 11U +#define UART_ICR_RFFULL_MSK BIT(UART_ICR_RFFULL_POS) + +#define UART_ICR_RFTH_POS 9U +#define UART_ICR_RFTH_MSK BIT(UART_ICR_RFTH_POS) + +#define UART_ICR_NOISE_POS 8U +#define UART_ICR_NOISE_MSK BIT(UART_ICR_NOISE_POS) + +#define UART_ICR_EOB_POS 7U +#define UART_ICR_EOB_MSK BIT(UART_ICR_EOB_POS) + +#define UART_ICR_LINBK_POS 6U +#define UART_ICR_LINBK_MSK BIT(UART_ICR_LINBK_POS) + +#define UART_ICR_ADDRM_POS 5U +#define UART_ICR_ADDRM_MSK BIT(UART_ICR_ADDRM_POS) + +#define UART_ICR_RXTO_POS 4U +#define UART_ICR_RXTO_MSK BIT(UART_ICR_RXTO_POS) + +#define UART_ICR_DCTS_POS 3U +#define UART_ICR_DCTS_MSK BIT(UART_ICR_DCTS_POS) + +#define UART_ICR_ABTO_POS 2U +#define UART_ICR_ABTO_MSK BIT(UART_ICR_ABTO_POS) + +#define UART_ICR_ABEND_POS 1U +#define UART_ICR_ABEND_MSK BIT(UART_ICR_ABEND_POS) + +#define UART_ICR_RXBERR_POS 0U +#define UART_ICR_RXBERR_MSK BIT(UART_ICR_RXBERR_POS) + +typedef struct +{ + __I uint32_t RXBUF; + __IO uint32_t TXBUF; + __IO uint32_t BRR; + __IO uint32_t LCON; + __IO uint32_t MCON; + __IO uint32_t RS485; + __IO uint32_t SCARD; + __IO uint32_t LIN; + __IO uint32_t RTOR; + __O uint32_t FCON; + __I uint32_t STAT; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} UART_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_usb.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_usb.h new file mode 100644 index 0000000000000000000000000000000000000000..96858065519d45137f8841acf4c2c9d63247eb8a --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_usb.h @@ -0,0 +1,873 @@ +/** + ************************************************************************************** + * @file reg_usb.h + * @brief USB Head File + * @data 5/22/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __REG_USB_H__ +#define __REG_USB_H__ + + +/******************************************************************************/ +/* ṹ嶨 */ +/******************************************************************************/ + +/* ṹ */ +/* #pragma anon_unions */ + +/****************** Bit definition for USB_FADDR register ************************/ + +#define USB_FADDR_ADDR_POSS 0U +#define USB_FADDR_ADDR_POSE 6U +#define USB_FADDR_ADDR_MSK BITS(USB_FADDR_ADDR_POSS,USB_FADDR_ADDR_POSE) + +/****************** Bit definition for USB_POWER register ************************/ + +#define USB_POWER_ISOUDT_POSS 7U +#define USB_POWER_ISOUDT_MSK BIT(USB_POWER_ISOUDT_POSS) + +#define USB_POWER_RESET_POSS 3U +#define USB_POWER_RESET_MSK BIT(USB_POWER_RESET_POSS) + +#define USB_POWER_RESUME_POSS 2U +#define USB_POWER_RESUME_MSK BIT(USB_POWER_RESUME_POSS) + +#define USB_POWER_SUSPEND_POSS 1U +#define USB_POWER_SUSPEND_MSK BIT(USB_POWER_SUSPEND_POSS) + +#define USB_POWER_SUSPENDEN_POSS 0U +#define USB_POWER_SUSPENDEN_MSK BIT(USB_POWER_SUSPENDEN_POSS) + +/****************** Bit definition for USB_DPDMCTL register ************************/ + +#define USB_DPDMCTL_DPPUD_POSS 3U +#define USB_DPDMCTL_DPPUD_POSE 4U +#define USB_DPDMCTL_DPPUD_MSK BITS(USB_DPDMCTL_DPPUD_POSS,USB_DPDMCTL_DPPUD_POSE) + +#define USB_DPDMCTL_DMPUD_POSS 1U +#define USB_DPDMCTL_DMPUD_POSE 2U +#define USB_DPDMCTL_DMPUD_MSK BITS(USB_DPDMCTL_DMPUD_POSS,USB_DPDMCTL_DMPUD_POSE) + +#define USB_DPDMCTL_PHYPWREN_POS 0U +#define USB_DPDMCTL_PHYPWREN_MSK BIT(USB_DPDMCTL_PHYPWREN_POS) + +/****************** Bit definition for USB_SWCID register ************************/ + +#define USB_SWCID_HOST_POSS 1U +#define USB_SWCID_HOST_MSK BIT(USB_SWCID_HOST_POSS) + +#define USB_SWCID_CIDCTRL_POSS 0U +#define USB_SWCID_CIDCTRL_MSK BIT(USB_SWCID_CIDCTRL_POSS) + +/****************** Bit definition for USB_SWVBUS register ************************/ + +#define USB_SWVBUS_VALTH_POS 3U +#define USB_SWVBUS_VALTH_MSK BIT(USB_SWVBUS_VALTH_POS) + +#define USB_SWVBUS_SESVALTH_POS 2U +#define USB_SWVBUS_SESVALTH_MSK BIT(USB_SWVBUS_SESVALTH_POS) + +#define USB_SWVBUS_SESENDTH_POS 1U +#define USB_SWVBUS_SESENDTH_MSK BIT(USB_SWVBUS_SESENDTH_POS) + +#define USB_SWVBUS_SIGCTRL_POS 0U +#define USB_SWVBUS_SIGCTRL_MSK BIT(USB_SWVBUS_SIGCTRL_POS) + +/****************** Bit definition for USB_TMODE register ************************/ + +#define USB_TMODE_PROTECT_POSS 1U +#define USB_TMODE_PROTECT_POSE 7U +#define USB_TMODE_PROTECT_MSK BITS(USB_TMODE_PROTECT_POSS,USB_TMODE_PROTECT_POSE) + +#define USB_TMODE_ENABLE_POS 0U +#define USB_TMODE_ENABLE_MSK BIT(USB_TMODE_ENABLE_POS) + +/****************** Bit definition for USB_FRAME1 register ************************/ + +#define USB_FRAME1_LOWFRAME_POSS 0U +#define USB_FRAME1_LOWFRAME_POSE 7U +#define USB_FRAME1_LOWFRAME_MSK BITS(USB_FRAME1_LOWFRAME_POSS,USB_FRAME1_LOWFRAME_POSE) + +/****************** Bit definition for USB_FRAME2 register ************************/ + +#define USB_FRAME2_UPFRAME_POSS 0U +#define USB_FRAME2_UPFRAME_POSE 2U +#define USB_FRAME2_UPFRAME_MSK BITS(USB_FRAME2_UPFRAME_POSS,USB_FRAME2_UPFRAME_POSE) + +/****************** Bit definition for USB_INDEX register ************************/ + +#define USB_INDEX_EPTIDX_POSS 0U +#define USB_INDEX_EPTIDX_POSE 3U +#define USB_INDEX_EPTIDX_MSK BITS(USB_INDEX_EPTIDX_POSS,USB_INDEX_EPTIDX_POSE) + +/****************** Bit definition for USB_DEVCTRL register ************************/ + +#define USB_DEVCTRL_FSDEV_POS 6U +#define USB_DEVCTRL_FSDEV_MSK BIT(USB_DEVCTRL_FSDEV_POS) + +#define USB_DEVCTRL_LSDEV_POS 5U +#define USB_DEVCTRL_LSDEV_MSK BIT(USB_DEVCTRL_LSDEV_POS) + +#define USB_DEVCTRL_HOST_POS 2U +#define USB_DEVCTRL_HOST_MSK BIT(USB_DEVCTRL_HOST_POS) + +#define USB_DEVCTRL_HOSTREQ_POS 1U +#define USB_DEVCTRL_HOSTREQ_MSK BIT(USB_DEVCTRL_HOSTREQ_POS) + +#define USB_DEVCTRL_SESSION_POS 0U +#define USB_DEVCTRL_SESSION_MSK BIT(USB_DEVCTRL_SESSION_POS) + +/****************** Bit definition for USB_TXMAXP register ************************/ + +#define USB_TXMAXP_MAXSIZE_POSS 0U +#define USB_TXMAXP_MAXSIZE_POSE 7U +#define USB_TXMAXP_MAXSIZE_MSK BITS(USB_TXMAXP_MAXSIZE_POSS,USB_TXMAXP_MAXSIZE_POSE) + +/****************** Bit definition for USB_CSR0L_TXCSRL register ************************/ + +// +//Endpoint 0 +// +/* host mode */ +#define USB_CSR0L_TXCSRL_NAKTO_POS 7U +#define USB_CSR0L_TXCSRL_NAKTO_MSK BIT(USB_CSR0L_TXCSRL_NAKTO_POS) + +#define USB_CSR0L_TXCSRL_STATUSPKT_POS 6U +#define USB_CSR0L_TXCSRL_STATUSPKT_MSK BIT(USB_CSR0L_TXCSRL_STATUSPKT_POS) + +#define USB_CSR0L_TXCSRL_REQPKT_POS 5U +#define USB_CSR0L_TXCSRL_REQPKT_MSK BIT(USB_CSR0L_TXCSRL_REQPKT_POS) + +#define USB_CSR0L_TXCSRL_ERROR_POS 4U +#define USB_CSR0L_TXCSRL_ERROR_MSK BIT(USB_CSR0L_TXCSRL_ERROR_POS) + +#define USB_CSR0L_TXCSRL_SETUPPKT_POS 3U +#define USB_CSR0L_TXCSRL_SETUPPKT_MSK BIT(USB_CSR0L_TXCSRL_SETUPPKT_POS) + +/* device mode */ +#define USB_CSR0L_TXCSRL_SETENDC_POS 7U +#define USB_CSR0L_TXCSRL_SETENDC_MSK BIT(USB_CSR0L_TXCSRL_SETENDC_POS) + +#define USB_CSR0L_TXCSRL_RXRDYC_POS 6U +#define USB_CSR0L_TXCSRL_RXRDYC_MSK BIT(USB_CSR0L_TXCSRL_RXRDYC_POS) + +#define USB_CSR0L_TXCSRL_STALL_POS 5U +#define USB_CSR0L_TXCSRL_STALL_MSK BIT(USB_CSR0L_TXCSRL_STALL_POS) + +#define USB_CSR0L_TXCSRL_SETEND_POS 4U +#define USB_CSR0L_TXCSRL_SETEND_MSK BIT(USB_CSR0L_TXCSRL_SETEND_POS) + +#define USB_CSR0L_TXCSRL_DATAEND_POS 3U +#define USB_CSR0L_TXCSRL_DATAEND_MSK BIT(USB_CSR0L_TXCSRL_DATAEND_POS) + +#define USB_CSR0L_TXCSRL_STALLED_POS 2U +#define USB_CSR0L_TXCSRL_STALLED_MSK BIT(USB_CSR0L_TXCSRL_STALLED_POS) + +#define USB_CSR0L_TXCSRL_TXRDY_POS 1U +#define USB_CSR0L_TXCSRL_TXRDY_MSK BIT(USB_CSR0L_TXCSRL_TXRDY_POS) + +#define USB_CSR0L_TXCSRL_RXRDY_POS 0U +#define USB_CSR0L_TXCSRL_RXRDY_MSK BIT(USB_CSR0L_TXCSRL_RXRDY_POS) + +// +//Endpoint 1-6 +// +/* host mode */ +#define USB_CSR0L_TXCSRL_NACKOUT_POS 7U +#define USB_CSR0L_TXCSRL_NACKOUT_MSK BIT(USB_CSR0L_TXCSRL_NACKOUT_POS) + +#define USB_CSR0L_TXCSRL_CLRDATAT_POS 6U +#define USB_CSR0L_TXCSRL_CLRDATAT_MSK BIT(USB_CSR0L_TXCSRL_CLRDATAT_POS) + +#define USB_CSR0L_TXCSRL_RXSTALL_POS 5U +#define USB_CSR0L_TXCSRL_RXSTALL_MSK BIT(USB_CSR0L_TXCSRL_RXSTALL_POS) + +#define USB_CSR0L_TXCSRL_TXPKTRDY_POS 0U +#define USB_CSR0L_TXCSRL_TXPKTRDY_MSK BIT(USB_CSR0L_TXCSRL_TXPKTRDY_POS) + +/* device mode */ +#define USB_CSR0L_TXCSRL_INCOMPTX_POS 7U +#define USB_CSR0L_TXCSRL_INCOMPTX_MSK BIT(USB_CSR0L_TXCSRL_INCOMPTX_POS) + +#define USB_CSR0L_TXCSRL_CLRDATAT_POS 6U +#define USB_CSR0L_TXCSRL_CLRDATAT_MSK BIT(USB_CSR0L_TXCSRL_CLRDATAT_POS) + +#define USB_CSR0L_TXCSRL_SENTSTALL_POS 5U +#define USB_CSR0L_TXCSRL_SENTSTALL_MSK BIT(USB_CSR0L_TXCSRL_SENTSTALL_POS) + +#define USB_CSR0L_TXCSRL_SENDSTALL_POS 4U +#define USB_CSR0L_TXCSRL_SENDSTALL_MSK BIT(USB_CSR0L_TXCSRL_SENDSTALL_POS) + +#define USB_CSR0L_TXCSRL_FLUSHFIFO_POS 3U +#define USB_CSR0L_TXCSRL_FLUSHFIFO_MSK BIT(USB_CSR0L_TXCSRL_FLUSHFIFO_POS) + +#define USB_CSR0L_TXCSRL_UNDERRUN_POS 2U +#define USB_CSR0L_TXCSRL_UNDERRUN_MSK BIT(USB_CSR0L_TXCSRL_UNDERRUN_POS) + +#define USB_CSR0L_TXCSRL_FIFONE_POS 1U +#define USB_CSR0L_TXCSRL_FIFONE_MSK BIT(USB_CSR0L_TXCSRL_FIFONE_POS) + +#define USB_CSR0L_TXCSRL_TXPKTRDY_POS 0U +#define USB_CSR0L_TXCSRL_TXPKTRDY_MSK BIT(USB_CSR0L_TXCSRL_TXPKTRDY_POS) + +/****************** Bit definition for USB_CSR0H_TXCSRH register ************************/ +// +//For endpoint 0 +// +#define USB_CSR0H_TXCSRH_FLUSH_POS 0U +#define USB_CSR0H_TXCSRH_FLUSH_MSK BIT(USB_CSR0H_TXCSRH_FLUSH_POS) + +// +//For endpoint 1-6 +// +#define USB_CSR0H_TXCSRH_AUTOSET_POS 7U +#define USB_CSR0H_TXCSRH_AUTOSET_MSK BIT(USB_CSR0H_TXCSRH_AUTOSET_POS) + +#define USB_CSR0H_TXCSRH_ISO_POS 6U +#define USB_CSR0H_TXCSRH_ISO_MSK BIT(USB_CSR0H_TXCSRH_ISO_POS) + +#define USB_CSR0H_TXCSRH_MODE_POS 5U +#define USB_CSR0H_TXCSRH_MODE_MSK BIT(USB_CSR0H_TXCSRH_MODE_POS) + +#define USB_CSR0H_TXCSRH_FDT_POS 3U +#define USB_CSR0H_TXCSRH_FDT_MSK BIT(USB_CSR0H_TXCSRH_FDT_POS) + +/****************** Bit definition for USB_RXMAXP register ************************/ + +#define USB_RXMAXP_MAXSIZE_POSS 0U +#define USB_RXMAXP_MAXSIZE_POSE 7U +#define USB_RXMAXP_MAXSIZE_MSK BITS(USB_RXMAXP_MAXSIZE_POSS,USB_RXMAXP_MAXSIZE_POSE) + +/****************** Bit definition for USB_RXCSRL register ************************/ + +#define USB_RXCSRL_CLRDT_POS 7U +#define USB_RXCSRL_CLRDT_MSK BIT(USB_RXCSRL_CLRDT_POS) + +#define USB_RXCSRL_STALLED_POS 6U +#define USB_RXCSRL_STALLED_MSK BIT(USB_RXCSRL_STALLED_POS) + +#define USB_RXCSRL_REQPKT_POS 5U +#define USB_RXCSRL_REQPKT_MSK BIT(USB_RXCSRL_REQPKT_POS) + +#define USB_RXCSRL_STALL_POS 5U +#define USB_RXCSRL_STALL_MSK BIT(USB_RXCSRL_STALL_POS) + +#define USB_RXCSRL_FLUSH_POS 4U +#define USB_RXCSRL_FLUSH_MSK BIT(USB_RXCSRL_FLUSH_POS) + +#define USB_RXCSRL_DATAERR_NAKTO_POS 3U +#define USB_RXCSRL_DATAERR_NAKTO_MSK BIT(USB_RXCSRL_DATAERR_NAKTO_POS) + +#define USB_RXCSRL_ERROR_POS 2U +#define USB_RXCSRL_ERROR_MSK BIT(USB_RXCSRL_ERROR_POS) + +#define USB_RXCSRL_OVERRUN_POS 2U +#define USB_RXCSRL_OVERRUN_MSK BIT(USB_RXCSRL_OVERRUN_POS) + +#define USB_RXCSRL_FULL_POS 1U +#define USB_RXCSRL_FULL_MSK BIT(USB_RXCSRL_FULL_POS) + +#define USB_RXCSRL_RXRDY_POS 0U +#define USB_RXCSRL_RXRDY_MSK BIT(USB_RXCSRL_RXRDY_POS) + +/****************** Bit definition for USB_RXCSRH register ************************/ + +#define USB_RXCSRH_AUTOCLR_POS 7U +#define USB_RXCSRH_AUTOCLR_MSK BIT(USB_RXCSRH_AUTOCLR_POS) + +#define USB_RXCSRH_AUTOREQ_POS 6U +#define USB_RXCSRH_AUTOREQ_MSK BIT(USB_RXCSRH_AUTOREQ_POS) + +#define USB_RXCSRH_ISO_POS 6U +#define USB_RXCSRH_ISO_MSK BIT(USB_RXCSRH_ISO_POS) + +/****************** Bit definition for USB_RXCOUNT1 register ************************/ + +#define USB_RXCOUNT1_COUNT_POSS 0U +#define USB_RXCOUNT1_COUNT_POSE 6U +#define USB_RXCOUNT1_COUNT_MSK BITS(USB_RXCOUNT1_COUNT_POSS,USB_RXCOUNT1_COUNT_POSE) + +#define USB_RXCOUNT1_PKTLOW_POSS 0U +#define USB_RXCOUNT1_PKTLOW_POSE 7U +#define USB_RXCOUNT1_PKTLOW_MSK BITS(USB_RXCOUNT1_PKTLOW_POSS,USB_RXCOUNT1_PKTLOW_POSE) + +/****************** Bit definition for USB_RXCOUNT2 register ************************/ + +#define USB_RXCOUNT2_PKTHIGH_POSS 0U +#define USB_RXCOUNT2_PKTHIGH_POSE 2U +#define USB_RXCOUNT2_PKTHIGH_MSK BITS(USB_RXCOUNT2_PKTHIGH_POSS,USB_RXCOUNT2_PKTHIGH_POSE) + +/****************** Bit definition for USB_TXTYPE register ************************/ + +#define USB_TXTYPE_PROTOCOL_POSS 4U +#define USB_TXTYPE_PROTOCOL_POSE 5U +#define USB_TXTYPE_PROTOCOL_MSK BITS(USB_TXTYPE_PROTOCOL_POSS,USB_TXTYPE_PROTOCOL_POSE) + +#define USB_TXTYPE_TEPN_POSS 0U +#define USB_TXTYPE_TEPN_POSE 3U +#define USB_TXTYPE_TEPN_MSK BITS(USB_TXTYPE_TEPN_POSS,USB_TXTYPE_TEPN_POSE) + +/****************** Bit definition for USB_NAKLIMIT0_TXINTERVAL register ************************/ + +#define USB_NAKLIMIT0_TXINTERVAL_NAKLMT_POSS 0U +#define USB_NAKLIMIT0_TXINTERVAL_NAKLMT_POSE 7U +#define USB_NAKLIMIT0_TXINTERVAL_NAKLMT_MSK BITS(USB_NAKLIMIT0_TXINTERVAL_NAKLMT_POSS,USB_NAKLIMIT0_TXINTERVAL_NAKLMT_POSE) + +/****************** Bit definition for USB_RXTYPE register ************************/ + +#define USB_RXTYPE_PROTOCOL_POSS 4U +#define USB_RXTYPE_PROTOCOL_POSE 5U +#define USB_RXTYPE_PROTOCOL_MSK BITS(USB_RXTYPE_PROTOCOL_POSS,USB_RXTYPE_PROTOCOL_POSE) + +#define USB_RXTYPE_TEPN_POSS 0U +#define USB_RXTYPE_TEPN_POSE 3U +#define USB_RXTYPE_TEPN_MSK BITS(USB_RXTYPE_TEPN_POSS,USB_RXTYPE_TEPN_POSE) + +/****************** Bit definition for USB_RXINTERVAL register ************************/ + +#define USB_RXINTERVAL_NAKLMT_POSS 0U +#define USB_RXINTERVAL_NAKLMT_POSE 7U +#define USB_RXINTERVAL_NAKLMT_MSK BITS(USB_RXINTERVAL_NAKLMT_POSS,USB_RXINTERVAL_NAKLMT_POSE) + +/****************** Bit definition for USB_TXFIFO1 register ************************/ + +#define USB_TXFIFO1_ADDRL_POSS 0U +#define USB_TXFIFO1_ADDRL_POSE 7U +#define USB_TXFIFO1_ADDRL_MSK BITS(USB_TXFIFO1_ADDRL_POSS,USB_TXFIFO1_ADDRL_POSE) + +/****************** Bit definition for USB_TXFIFO2 register ************************/ + +#define USB_TXFIFO2_MAXPKTSIZE_POSS 5U +#define USB_TXFIFO2_MAXPKTSIZE_POSE 7U +#define USB_TXFIFO2_MAXPKTSIZE_MSK BITS(USB_TXFIFO2_MAXPKTSIZE_POSS,USB_TXFIFO2_MAXPKTSIZE_POSE) + +#define USB_TXFIFO2_DPB_POS 4U +#define USB_TXFIFO2_DPB_MSK BIT(USB_TXFIFO2_DPB_POS) + +#define USB_TXFIFO2_ADDRH_POSS 0U +#define USB_TXFIFO2_ADDRH_POSE 3U +#define USB_TXFIFO2_ADDRH_MSK BITS(USB_TXFIFO2_ADDRH_POSS,USB_TXFIFO2_ADDRH_POSE) + +/****************** Bit definition for USB_RXFIFO1 register ************************/ + +#define USB_RXFIFO1_ADDRL_POSS 0U +#define USB_RXFIFO1_ADDRL_POSE 7U +#define USB_RXFIFO1_ADDRL_MSK BITS(USB_RXFIFO1_ADDRL_POSS,USB_RXFIFO1_ADDRL_POSE) + +/****************** Bit definition for USB_RXFIFO2 register ************************/ + +#define USB_RXFIFO2_MAXPKTSIZE_POSS 5U +#define USB_RXFIFO2_MAXPKTSIZE_POSE 7U +#define USB_RXFIFO2_MAXPKTSIZE_MSK BITS(USB_RXFIFO2_MAXPKTSIZE_POSS,USB_RXFIFO2_MAXPKTSIZE_POSE) + +#define USB_RXFIFO2_DPB_POS 4U +#define USB_RXFIFO2_DPB_MSK BIT(USB_RXFIFO2_DPB_POS) + +#define USB_RXFIFO2_ADDRH_POSS 0U +#define USB_RXFIFO2_ADDRH_POSE 3U +#define USB_RXFIFO2_ADDRH_MSK BITS(USB_RXFIFO2_ADDRH_POSS,USB_RXFIFO2_ADDRH_POSE) + +/************* Bit definition for USB_EP0FIFO/USB_EPxFIFO register *****************/ + +#define USB_EPxFIFO_FIFO_POSS 0U +#define USB_EPxFIFO_FIFO_POSE 7U +#define USB_EPxFIFO_FIFO_MSK BITS(USB_EPxFIFO_FIFO_POSS,USB_EPxFIFO_FIFO_POSE) + +/****************** Bit definition for USB_TXIER register ************************/ + +#define USB_TXIER_EP6IE_POS 6U +#define USB_TXIER_EP6IE_MSK BIT(USB_TXIER_EP6IE_POS) + +#define USB_TXIER_EP5IE_POS 5U +#define USB_TXIER_EP5IE_MSK BIT(USB_TXIER_EP5IE_POS) + +#define USB_TXIER_EP4IE_POS 4U +#define USB_TXIER_EP4IE_MSK BIT(USB_TXIER_EP4IE_POS) + +#define USB_TXIER_EP3IE_POS 3U +#define USB_TXIER_EP3IE_MSK BIT(USB_TXIER_EP3IE_POS) + +#define USB_TXIER_EP2IE_POS 2U +#define USB_TXIER_EP2IE_MSK BIT(USB_TXIER_EP2IE_POS) + +#define USB_TXIER_EP1IE_POS 1U +#define USB_TXIER_EP1IE_MSK BIT(USB_TXIER_EP1IE_POS) + +#define USB_TXIER_EP0IE_POS 0U +#define USB_TXIER_EP0IE_MSK BIT(USB_TXIER_EP0IE_POS) + +/****************** Bit definition for USB_RXIER register ************************/ + +#define USB_RXIER_EP6IE_POS 6U +#define USB_RXIER_EP6IE_MSK BIT(USB_RXIER_EP6IE_POS) + +#define USB_RXIER_EP5IE_POS 5U +#define USB_RXIER_EP5IE_MSK BIT(USB_RXIER_EP5IE_POS) + +#define USB_RXIER_EP4IE_POS 4U +#define USB_RXIER_EP4IE_MSK BIT(USB_RXIER_EP4IE_POS) + +#define USB_RXIER_EP3IE_POS 3U +#define USB_RXIER_EP3IE_MSK BIT(USB_RXIER_EP3IE_POS) + +#define USB_RXIER_EP2IE_POS 2U +#define USB_RXIER_EP2IE_MSK BIT(USB_RXIER_EP2IE_POS) + +#define USB_RXIER_EP1IE_POS 1U +#define USB_RXIER_EP1IE_MSK BIT(USB_RXIER_EP1IE_POS) + +/****************** Bit definition for USB_TXIDR register ************************/ + +#define USB_TXIDR_EP6ID_POS 6U +#define USB_TXIDR_EP6ID_MSK BIT(USB_TXIDR_EP6ID_POS) + +#define USB_TXIDR_EP5ID_POS 5U +#define USB_TXIDR_EP5ID_MSK BIT(USB_TXIDR_EP5ID_POS) + +#define USB_TXIDR_EP4ID_POS 4U +#define USB_TXIDR_EP4ID_MSK BIT(USB_TXIDR_EP4ID_POS) + +#define USB_TXIDR_EP3ID_POS 3U +#define USB_TXIDR_EP3ID_MSK BIT(USB_TXIDR_EP3ID_POS) + +#define USB_TXIDR_EP2ID_POS 2U +#define USB_TXIDR_EP2ID_MSK BIT(USB_TXIDR_EP2ID_POS) + +#define USB_TXIDR_EP1ID_POS 1U +#define USB_TXIDR_EP1ID_MSK BIT(USB_TXIDR_EP1ID_POS) + +#define USB_TXIDR_EP0ID_POS 0U +#define USB_TXIDR_EP0ID_MSK BIT(USB_TXIDR_EP0ID_POS) + +/****************** Bit definition for USB_RXIDR register ************************/ + +#define USB_RXIDR_EP6ID_POS 6U +#define USB_RXIDR_EP6ID_MSK BIT(USB_RXIDR_EP6ID_POS) + +#define USB_RXIDR_EP5ID_POS 5U +#define USB_RXIDR_EP5ID_MSK BIT(USB_RXIDR_EP5ID_POS) + +#define USB_RXIDR_EP4ID_POS 4U +#define USB_RXIDR_EP4ID_MSK BIT(USB_RXIDR_EP4ID_POS) + +#define USB_RXIDR_EP3ID_POS 3U +#define USB_RXIDR_EP3ID_MSK BIT(USB_RXIDR_EP3ID_POS) + +#define USB_RXIDR_EP2ID_POS 2U +#define USB_RXIDR_EP2ID_MSK BIT(USB_RXIDR_EP2ID_POS) + +#define USB_RXIDR_EP1ID_POS 1U +#define USB_RXIDR_EP1ID_MSK BIT(USB_RXIDR_EP1ID_POS) + +/****************** Bit definition for USB_TXIVS register ************************/ + +#define USB_TXIVS_EP6IVS_POS 6U +#define USB_TXIVS_EP6IVS_MSK BIT(USB_TXIVS_EP6IVS_POS) + +#define USB_TXIVS_EP5IVS_POS 5U +#define USB_TXIVS_EP5IVS_MSK BIT(USB_TXIVS_EP5IVS_POS) + +#define USB_TXIVS_EP4IVS_POS 4U +#define USB_TXIVS_EP4IVS_MSK BIT(USB_TXIVS_EP4IVS_POS) + +#define USB_TXIVS_EP3IVS_POS 3U +#define USB_TXIVS_EP3IVS_MSK BIT(USB_TXIVS_EP3IVS_POS) + +#define USB_TXIVS_EP2IVS_POS 2U +#define USB_TXIVS_EP2IVS_MSK BIT(USB_TXIVS_EP2IVS_POS) + +#define USB_TXIVS_EP1IVS_POS 1U +#define USB_TXIVS_EP1IVS_MSK BIT(USB_TXIVS_EP1IVS_POS) + +#define USB_TXIVS_EP0IVS_POS 0U +#define USB_TXIVS_EP0IVS_MSK BIT(USB_TXIVS_EP0IVS_POS) + +/****************** Bit definition for USB_RXIVS register ************************/ + +#define USB_RXIVS_EP6IVS_POS 6U +#define USB_RXIVS_EP6IVS_MSK BIT(USB_RXIVS_EP6IVS_POS) + +#define USB_RXIVS_EP5IVS_POS 5U +#define USB_RXIVS_EP5IVS_MSK BIT(USB_RXIVS_EP5IVS_POS) + +#define USB_RXIVS_EP4IVS_POS 4U +#define USB_RXIVS_EP4IVS_MSK BIT(USB_RXIVS_EP4IVS_POS) + +#define USB_RXIVS_EP3IVS_POS 3U +#define USB_RXIVS_EP3IVS_MSK BIT(USB_RXIVS_EP3IVS_POS) + +#define USB_RXIVS_EP2IVS_POS 2U +#define USB_RXIVS_EP2IVS_MSK BIT(USB_RXIVS_EP2IVS_POS) + +#define USB_RXIVS_EP1IVS_POS 1U +#define USB_RXIVS_EP1IVS_MSK BIT(USB_RXIVS_EP1IVS_POS) + +/****************** Bit definition for USB_TXRIF register ************************/ + +#define USB_TXRIF_EP6RIF_POS 6U +#define USB_TXRIF_EP6RIF_MSK BIT(USB_TXRIF_EP6RIF_POS) + +#define USB_TXRIF_EP5RIF_POS 5U +#define USB_TXRIF_EP5RIF_MSK BIT(USB_TXRIF_EP5RIF_POS) + +#define USB_TXRIF_EP4RIF_POS 4U +#define USB_TXRIF_EP4RIF_MSK BIT(USB_TXRIF_EP4RIF_POS) + +#define USB_TXRIF_EP3RIF_POS 3U +#define USB_TXRIF_EP3RIF_MSK BIT(USB_TXRIF_EP3RIF_POS) + +#define USB_TXRIF_EP2RIF_POS 2U +#define USB_TXRIF_EP2RIF_MSK BIT(USB_TXRIF_EP2RIF_POS) + +#define USB_TXRIF_EP1RIF_POS 1U +#define USB_TXRIF_EP1RIF_MSK BIT(USB_TXRIF_EP1RIF_POS) + +#define USB_TXRIF_EP0RIF_POS 0U +#define USB_TXRIF_EP0RIF_MSK BIT(USB_TXRIF_EP0RIF_POS) + +/****************** Bit definition for USB_RXRIF register ************************/ + +#define USB_RXRIF_EP6RIF_POS 6U +#define USB_RXRIF_EP6RIF_MSK BIT(USB_RXRIF_EP6RIF_POS) + +#define USB_RXRIF_EP5RIF_POS 5U +#define USB_RXRIF_EP5RIF_MSK BIT(USB_RXRIF_EP5RIF_POS) + +#define USB_RXRIF_EP4RIF_POS 4U +#define USB_RXRIF_EP4RIF_MSK BIT(USB_RXRIF_EP4RIF_POS) + +#define USB_RXRIF_EP3RIF_POS 3U +#define USB_RXRIF_EP3RIF_MSK BIT(USB_RXRIF_EP3RIF_POS) + +#define USB_RXRIF_EP2RIF_POS 2U +#define USB_RXRIF_EP2RIF_MSK BIT(USB_RXRIF_EP2RIF_POS) + +#define USB_RXRIF_EP1RIF_POS 1U +#define USB_RXRIF_EP1RIF_MSK BIT(USB_RXRIF_EP1RIF_POS) + +/****************** Bit definition for USB_TXIFM register ************************/ + +#define USB_TXIFM_EP6IFM_POS 6U +#define USB_TXIFM_EP6IFM_MSK BIT(USB_TXIFM_EP6IFM_POS) + +#define USB_TXIFM_EP5IFM_POS 5U +#define USB_TXIFM_EP5IFM_MSK BIT(USB_TXIFM_EP5IFM_POS) + +#define USB_TXIFM_EP4IFM_POS 4U +#define USB_TXIFM_EP4IFM_MSK BIT(USB_TXIFM_EP4IFM_POS) + +#define USB_TXIFM_EP3IFM_POS 3U +#define USB_TXIFM_EP3IFM_MSK BIT(USB_TXIFM_EP3IFM_POS) + +#define USB_TXIFM_EP2IFM_POS 2U +#define USB_TXIFM_EP2IFM_MSK BIT(USB_TXIFM_EP2IFM_POS) + +#define USB_TXIFM_EP1IFM_POS 1U +#define USB_TXIFM_EP1IFM_MSK BIT(USB_TXIFM_EP1IFM_POS) + +#define USB_TXIFM_EP0IFM_POS 0U +#define USB_TXIFM_EP0IFM_MSK BIT(USB_TXIFM_EP0IFM_POS) + +/****************** Bit definition for USB_RXIFM register ************************/ + +#define USB_RXIFM_EP6IFM_POS 6U +#define USB_RXIFM_EP6IFM_MSK BIT(USB_RXIFM_EP6IFM_POS) + +#define USB_RXIFM_EP5IFM_POS 5U +#define USB_RXIFM_EP5IFM_MSK BIT(USB_RXIFM_EP5IFM_POS) + +#define USB_RXIFM_EP4IFM_POS 4U +#define USB_RXIFM_EP4IFM_MSK BIT(USB_RXIFM_EP4IFM_POS) + +#define USB_RXIFM_EP3IFM_POS 3U +#define USB_RXIFM_EP3IFM_MSK BIT(USB_RXIFM_EP3IFM_POS) + +#define USB_RXIFM_EP2IFM_POS 2U +#define USB_RXIFM_EP2IFM_MSK BIT(USB_RXIFM_EP2IFM_POS) + +#define USB_RXIFM_EP1IFM_POS 1U +#define USB_RXIFM_EP1IFM_MSK BIT(USB_RXIFM_EP1IFM_POS) + +/****************** Bit definition for USB_TXICR register ************************/ + +#define USB_TXICR_EP6ICR_POS 6U +#define USB_TXICR_EP6ICR_MSK BIT(USB_TXICR_EP6ICR_POS) + +#define USB_TXICR_EP5ICR_POS 5U +#define USB_TXICR_EP5ICR_MSK BIT(USB_TXICR_EP5ICR_POS) + +#define USB_TXICR_EP4ICR_POS 4U +#define USB_TXICR_EP4ICR_MSK BIT(USB_TXICR_EP4ICR_POS) + +#define USB_TXICR_EP3ICR_POS 3U +#define USB_TXICR_EP3ICR_MSK BIT(USB_TXICR_EP3ICR_POS) + +#define USB_TXICR_EP2ICR_POS 2U +#define USB_TXICR_EP2ICR_MSK BIT(USB_TXICR_EP2ICR_POS) + +#define USB_TXICR_EP1ICR_POS 1U +#define USB_TXICR_EP1ICR_MSK BIT(USB_TXICR_EP1ICR_POS) + +#define USB_TXICR_EP0ICR_POS 0U +#define USB_TXICR_EP0ICR_MSK BIT(USB_TXICR_EP0ICR_POS) + +/****************** Bit definition for USB_RXICR register ************************/ + +#define USB_RXICR_EP6ICR_POS 6U +#define USB_RXICR_EP6ICR_MSK BIT(USB_RXICR_EP6ICR_POS) + +#define USB_RXICR_EP5ICR_POS 5U +#define USB_RXICR_EP5ICR_MSK BIT(USB_RXICR_EP5ICR_POS) + +#define USB_RXICR_EP4ICR_POS 4U +#define USB_RXICR_EP4ICR_MSK BIT(USB_RXICR_EP4ICR_POS) + +#define USB_RXICR_EP3ICR_POS 3U +#define USB_RXICR_EP3ICR_MSK BIT(USB_RXICR_EP3ICR_POS) + +#define USB_RXICR_EP2ICR_POS 2U +#define USB_RXICR_EP2ICR_MSK BIT(USB_RXICR_EP2ICR_POS) + +#define USB_RXICR_EP1ICR_POS 1U +#define USB_RXICR_EP1ICR_MSK BIT(USB_RXICR_EP1ICR_POS) + +/****************** Bit definition for USB_IER register ************************/ + +#define USB_IER_SESREQIE_POS 6U +#define USB_IER_SESREQIE_MSK BIT(USB_IER_SESREQIE_POS) + +#define USB_IER_DISCONIE_POS 5U +#define USB_IER_DISCONIE_MSK BIT(USB_IER_DISCONIE_POS) + +#define USB_IER_CONIE_POS 4U +#define USB_IER_CONIE_MSK BIT(USB_IER_CONIE_POS) + +#define USB_IER_SOFIE_POS 3U +#define USB_IER_SOFIE_MSK BIT(USB_IER_SOFIE_POS) + +#define USB_IER_BABIE_POS 2U +#define USB_IER_BABIE_MSK BIT(USB_IER_BABIE_POS) + +#define USB_IER_RESTIE_POS 2U +#define USB_IER_RESTIE_MSK BIT(USB_IER_RESTIE_POS) + +#define USB_IER_RESIE_POS 1U +#define USB_IER_RESIE_MSK BIT(USB_IER_RESIE_POS) + +#define USB_IER_SUSPDIE_POS 0U +#define USB_IER_SUSPDIE_MSK BIT(USB_IER_SUSPDIE_POS) + +/****************** Bit definition for USB_IDR register ************************/ + +#define USB_IDR_SESREQID_POS 6U +#define USB_IDR_SESREQID_MSK BIT(USB_IDR_SESREQID_POS) + +#define USB_IDR_DISCONID_POS 5U +#define USB_IDR_DISCONID_MSK BIT(USB_IDR_DISCONID_POS) + +#define USB_IDR_CONID_POS 4U +#define USB_IDR_CONID_MSK BIT(USB_IDR_CONID_POS) + +#define USB_IDR_SOFID_POS 3U +#define USB_IDR_SOFID_MSK BIT(USB_IDR_SOFID_POS) + +#define USB_IDR_BABID_POS 2U +#define USB_IDR_BABID_MSK BIT(USB_IDR_BABID_POS) + +#define USB_IDR_RESTID_POS 2U +#define USB_IDR_RESTID_MSK BIT(USB_IDR_RESTID_POS) + +#define USB_IDR_RESID_POS 1U +#define USB_IDR_RESID_MSK BIT(USB_IDR_RESID_POS) + +#define USB_IDR_SUSPDID_POS 0U +#define USB_IDR_SUSPDID_MSK BIT(USB_IDR_SUSPDID_POS) + +/****************** Bit definition for USB_IVS register ************************/ + +#define USB_IVS_SESREQIVS_POS 6U +#define USB_IVS_SESREQIVS_MSK BIT(USB_IVS_SESREQIVS_POS) + +#define USB_IVS_DISCONIVS_POS 5U +#define USB_IVS_DISCONIVS_MSK BIT(USB_IVS_DISCONIVS_POS) + +#define USB_IVS_CONIVS_POS 4U +#define USB_IVS_CONIVS_MSK BIT(USB_IVS_CONIVS_POS) + +#define USB_IVS_SOFIVS_POS 3U +#define USB_IVS_SOFIVS_MSK BIT(USB_IVS_SOFIVS_POS) + +#define USB_IVS_BABIVS_POS 2U +#define USB_IVS_BABIVS_MSK BIT(USB_IVS_BABIVS_POS) + +#define USB_IVS_RESTIVS_POS 2U +#define USB_IVS_RESTIVS_MSK BIT(USB_IVS_RESTIVS_POS) + +#define USB_IVS_RESIVS_POS 1U +#define USB_IVS_RESIVS_MSK BIT(USB_IVS_RESIVS_POS) + +#define USB_IVS_SUSPDIVS_POS 0U +#define USB_IVS_SUSPDIVS_MSK BIT(USB_IVS_SUSPDIVS_POS) + +/****************** Bit definition for USB_RIF register ************************/ + +#define USB_RIF_SESREQRIF_POS 6U +#define USB_RIF_SESREQRIF_MSK BIT(USB_RIF_SESREQRIF_POS) + +#define USB_RIF_DISCONRIF_POS 5U +#define USB_RIF_DISCONRIF_MSK BIT(USB_RIF_DISCONRIF_POS) + +#define USB_RIF_CONRIF_POS 4U +#define USB_RIF_CONRIF_MSK BIT(USB_RIF_CONRIF_POS) + +#define USB_RIF_SOFRIF_POS 3U +#define USB_RIF_SOFRIF_MSK BIT(USB_RIF_SOFRIF_POS) + +#define USB_RIF_BABRIF_POS 2U +#define USB_RIF_BABRIF_MSK BIT(USB_RIF_BABRIF_POS) + +#define USB_RIF_RESTRIF_POS 2U +#define USB_RIF_RESTRIF_MSK BIT(USB_RIF_RESTRIF_POS) + +#define USB_RIF_RESRIF_POS 1U +#define USB_RIF_RESRIF_MSK BIT(USB_RIF_RESRIF_POS) + +#define USB_RIF_SUSPDRIF_POS 0U +#define USB_RIF_SUSPDRIF_MSK BIT(USB_RIF_SUSPDRIF_POS) + +/****************** Bit definition for USB_IFM register ************************/ + +#define USB_IFM_SESREQIFM_POS 6U +#define USB_IFM_SESREQIFM_MSK BIT(USB_IFM_SESREQIFM_POS) + +#define USB_IFM_DISCONIFM_POS 5U +#define USB_IFM_DISCONIFM_MSK BIT(USB_IFM_DISCONIFM_POS) + +#define USB_IFM_CONIFM_POS 4U +#define USB_IFM_CONIFM_MSK BIT(USB_IFM_CONIFM_POS) + +#define USB_IFM_SOFIFM_POS 3U +#define USB_IFM_SOFIFM_MSK BIT(USB_IFM_SOFIFM_POS) + +#define USB_IFM_BABIFM_POS 2U +#define USB_IFM_BABIFM_MSK BIT(USB_IFM_BABIFM_POS) + +#define USB_IFM_RESTIFM_POS 2U +#define USB_IFM_RESTIFM_MSK BIT(USB_IFM_RESTIFM_POS) + +#define USB_IFM_RESIFM_POS 1U +#define USB_IFM_RESIFM_MSK BIT(USB_IFM_RESIFM_POS) + +#define USB_IFM_SUSPDIFM_POS 0U +#define USB_IFM_SUSPDIFM_MSK BIT(USB_IFM_SUSPDIFM_POS) + +/****************** Bit definition for USB_ICR register ************************/ + +#define USB_ICR_SESREQICR_POS 6U +#define USB_ICR_SESREQICR_MSK BIT(USB_ICR_SESREQICR_POS) + +#define USB_ICR_DISCONICR_POS 5U +#define USB_ICR_DISCONICR_MSK BIT(USB_ICR_DISCONICR_POS) + +#define USB_ICR_CONICR_POS 4U +#define USB_ICR_CONICR_MSK BIT(USB_ICR_CONICR_POS) + +#define USB_ICR_SOFICR_POS 3U +#define USB_ICR_SOFICR_MSK BIT(USB_ICR_SOFICR_POS) + +#define USB_ICR_BABICR_POS 2U +#define USB_ICR_BABICR_MSK BIT(USB_ICR_BABICR_POS) + +#define USB_ICR_RESTICR_POS 2U +#define USB_ICR_RESTICR_MSK BIT(USB_ICR_RESTICR_POS) + +#define USB_ICR_RESICR_POS 1U +#define USB_ICR_RESICR_MSK BIT(USB_ICR_RESICR_POS) + +#define USB_ICR_SUSPDICR_POS 0U +#define USB_ICR_SUSPDICR_MSK BIT(USB_ICR_SUSPDICR_POS) + +typedef struct +{ + __IO uint8_t FADDR ; //0x0000 Function address register. + __IO uint8_t POWER ; //0x0001 Power management register. + __IO uint8_t DPDMCTRL ; //0x0002 DP DM Control register. + __IO uint8_t SWCID ; //0x0003 Softwave CID register. + __IO uint8_t SWVBUS ; //0x0004 Softwave VBUS register. + __IO uint8_t TMODE ; //0x0005 Test Mode register. + __IO uint8_t RES002[6] ; //0x0006~0x0B, Reserved + __IO uint8_t FRAME1 ; //0x000C, Frame number bits 0 to 7. + __IO uint8_t FRAME2 ; //0x000D, Frame number bits 8 to 10. + __IO uint8_t INDEX ; //0x000E, Index register for selecting the endp + __IO uint8_t DEVCTRL ; //0x000F, USB device control register. + __IO uint8_t TXMAXP ; //0x0010, Peripheral mode - Maximum packet size + __IO uint8_t CSR0L_TXCSRL ;//0x0011, Peripheral mode - Control Status regi + __IO uint8_t CSR0H_TXCSRH ;//0x0012, Peripheral mode - Control Status regi + __IO uint8_t RXMAXP ; //0x0013, Peripheral mode - Maximum packet size + __IO uint8_t RXCSR1 ; //0x0014, Peripheral mode - Control Status regi + __IO uint8_t RXCSR2 ; //0x0015, Peripheral mode - Control Status regi + __IO uint8_t RXCOUNT1 ; //0x0016, Peripheral mode - Number of bytes in + __IO uint8_t RXCOUNT2 ; //0x0017, Peripheral mode - Number of bytes in + __IO uint8_t TXTYPE ; //0x0018, Peripheral mode - // + __IO uint8_t NAKLIMIT0_TXINTERVAL ; //0x0019, Peripheral mode - // + __IO uint8_t RXTYPE ; //0x001A, Peripheral mode - // + __IO uint8_t RXINTERVAL ; //0x001B, Peripheral mode - // + __IO uint8_t TXFIFO1 ; //0x001C, Tx Endpoint FIFO details + __IO uint8_t TXFIFO2 ; //0x001D, Tx Endpoint FIFO details + __IO uint8_t RXFIFO1 ; //0x001E, Rx Endpoint FIFO details + __IO uint8_t RXFIFO2 ; //0x001F, Rx Endpoint FIFO details + __IO uint8_t EP0FIFO ; //0x0020, FIFOs for Endpoints 0. + __IO uint8_t RES021[3] ; //0x0021~0x23, Reserved + __IO uint8_t EP1FIFO ; //0x0024, FIFOs for Endpoints 1. + __IO uint8_t RES025[3] ; //0x0025~0x27, Reserved + __IO uint8_t EP2FIFO ; //0x0028, FIFOs for Endpoints 2. + __IO uint8_t RES029[3] ; //0x0029~0x2B, Reserved + __IO uint8_t EP3FIFO ; //0x002C, FIFOs for Endpoints 3. + __IO uint8_t RES02D[3] ; //0x002D~0x2F, Reserved + __IO uint8_t EP4FIFO ; //0x0030, FIFOs for Endpoints 4. + __IO uint8_t RES031[3] ; //0x0031~0x33, Reserved + __IO uint8_t EP5FIFO ; //0x0034, FIFOs for Endpoints 5. + __IO uint8_t RES035[3] ; //0x0035~0x37, Reserved + __IO uint8_t EP6FIFO ; //0x0038, FIFOs for Endpoints 6. + __IO uint8_t RES039[71] ; //0x0039~0x7C, Reserved + __IO uint8_t TXIER ; //0x0080, TX Endpoint 0~6 Interrupt Enable + __IO uint8_t RES081 ; //0x0081, Reserved + __IO uint8_t RXIER ; //0x0082, RX Endpoint 0~6 Interrupt Enable + __IO uint8_t RES083 ; //0x0083, Reserved + __IO uint8_t TXIDR ; //0x0084, TX Endpoint 0~6 Interrupt Disable + __IO uint8_t RES085 ; //0x0085, Reserved + __IO uint8_t RXIDR ; //0x0086, RX Endpoint 0~6 Interrupt Disable + __IO uint8_t RES087 ; //0x0087, Reserved + __IO uint8_t TXIVS ; //0x0088, TX Endpoint 0~6 Interrupt Valid Status + __IO uint8_t RES089 ; //0x0089, Reserved + __IO uint8_t RXIVS ; //0x008A, RX Endpoint 0~6 Interrupt Valid Status + __IO uint8_t RES08B ; //0x008B, Reserved + __IO uint8_t TXRIF ; //0x008C, TX Endpoint 0~6 Raw Interrupt Flag Status + __IO uint8_t RES08D ; //0x008D, Reserved + __IO uint8_t RXRIF ; //0x008E, RX Endpoint 0~6 Raw Interrupt Flag Status + __IO uint8_t RES08F ; //0x008F, Reserved + __IO uint8_t TXIFM ; //0x0090, TX Endpoint 0~6 Interrupt Flag Masked Status + __IO uint8_t RES091 ; //0x0091, Reserved + __IO uint8_t RXIFM ; //0x0092, RX Endpoint 0~6 Interrupt Flag Masked Status + __IO uint8_t RES093 ; //0x0093, Reserved + __IO uint8_t TXICR ; //0x0094, TX Endpoint 0~6 Interrupt Clear Register + __IO uint8_t RES095 ; //0x0095, Reserved + __IO uint8_t RXICR ; //0x0096, RX Endpoint 0~6 Interrupt Clear Register + __IO uint8_t RES097[9] ; //0x0097~0x9C, Reserved + __O uint32_t IER ; //0x00A0, USB Interrupt Enable Register + __O uint32_t IDR ; //0x00A4, USB Interrupt Disable Register + __I uint32_t IVS ; //0x00A8, USB Interrupt Valid Register + __I uint32_t RIF ; //0x00AC, USB Raw Interrupt Flag Status Register + __I uint32_t IFM ; //0x00B0, USB Interrupt Flag Masked Status + __O uint32_t ICR ; //0x00B4, USB Interrupt Clear Register +} USBCTRL_TypeDef; + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdg.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdg.h new file mode 100644 index 0000000000000000000000000000000000000000..0c64ea3d43ccf9f6d141e5ffe7cfb960fd51549b --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdg.h @@ -0,0 +1,88 @@ +/** + ************************************************************************************** + * @file reg_WWDG.h + * @brief WWDG Head File + * + * @version V1.00.01 + * @data 19/10/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __WWDG_H__ +#define __WWDG_H__ + +typedef struct +{ + __IO uint32_t CR; /* 0x00 WWDG_CR Control register */ + __IO uint32_t CFR; /* 0x04 WWDG_CFR Configuration register */ + __O uint32_t IER; /* 0x08 WWDG_IER Interrupt enable register */ + __O uint32_t IDR; /* 0x0C WWDG_IDR Interrupt disable register */ + __I uint32_t IVS; /* 0x10 WWDG_IVS Interrupt valid status */ + __I uint32_t RIF; /* 0x14 WWDG_RIF Raw interrupt flag */ + __I uint32_t IFM; /* 0x18 WWDG_IFM Interrupt flag masked */ + __O uint32_t ICR; /* 0x1C WWDG_ICR Interrupt clear register */ +} WWDG_TypeDef; + +/******************************************************************************/ +/* Ȧs줸wq */ +/******************************************************************************/ + +/* #pragma anon_unions */ + +/****************** Bit definition for WWDG_CR register ************************/ + +#define WWDG_CR_WDGA_POS 7U +#define WWDG_CR_WDGA_MSK BIT(WWDG_CR_WDGA_POS) + +#define WWDG_CR_T_POSS 0U +#define WWDG_CR_T_POSE 6U +#define WWDG_CR_T_MSK BITS(WWDG_CR_T_POSS,WWDG_CR_T_POSE) + +/****************** Bit definition for WWDG_CFR register ************************/ + +#define WWDG_CFR_WDGTB_POS 7U +#define WWDG_CFR_WDGTB_MSK BIT(WWDG_CFR_WDGTB_POS) + +#define WWDG_CFR_W_POSS 0U +#define WWDG_CFR_W_POSE 6U +#define WWDG_CFR_W_MSK BITS(WWDG_CFR_W_POSS,WWDG_CFR_W_POSE) + +/****************** Bit definition for WWDG_IER register ************************/ + +#define WWDG_IER_EWIS_POS 7U +#define WWDG_IER_EWIS_MSK BIT(WWDG_IER_EWIS_POS) + +/****************** Bit definition for WWDG_IDR register ************************/ + +#define WWDG_IDR_EWIS_POS 7U +#define WWDG_IDR_EWIS_MSK BIT(WWDG_IER_EWIS_POS) + +/****************** Bit definition for WWDG_IVS register ************************/ + +#define WWDG_IVS_EWIS_POS 7U +#define WWDG_IVS_EWIS_MSK BIT(WWDG_IER_EWIS_POS) + +/****************** Bit definition for WWDG_RIF register ************************/ + +#define WWDG_RIF_EWIS_POS 7U +#define WWDG_RIF_EWIS_MSK BIT(WWDG_IER_EWIS_POS) + +/****************** Bit definition for WWDG_IFM register ************************/ + +#define WWDG_IFM_EWIS_POS 7U +#define WWDG_IFM_EWIS_MSK BIT(WWDG_IER_EWIS_POS) + +/****************** Bit definition for WWDG_ICR register ************************/ + +#define WWDG_ICR_EWIS_POS 7U +#define WWDG_ICR_EWIS_MSK BIT(WWDG_IER_EWIS_POS) + + +#else +/* */ +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdt.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdt.h new file mode 100644 index 0000000000000000000000000000000000000000..b1ee6dcf18ad887719577641ab7d07ce9d9a9800 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271/reg_wwdt.h @@ -0,0 +1,92 @@ +/** + ************************************************************************************** + * @file REG_WWDT.h + * @brief WWDT Head File + * + * @version V0.01 + * @date 4/12/2018 + * @author Eastsoft MCU Software Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __REG_WWDT_H__ +#define __REG_WWDT_H__ + + +/******************************************************************************/ +/* 设备特殊寄存器结构定义 */ +/******************************************************************************/ + +/* 允许匿名结构和匿名联合 */ +/* #pragma anon_unions */ + +/****************** Bit definition for WWDT_CON register ************************/ + +#define WWDT_CON_WDGA_POS 7U +#define WWDT_CON_WDGA_MSK BIT(WWDT_CON_WDGA_POS) + +#define WWDT_CON_T_POSS 0U +#define WWDT_CON_T_POSE 6U +#define WWDT_CON_T_MSK BITS(WWDT_CON_T_POSS,WWDT_CON_T_POSE) + +/****************** Bit definition for WWDT_CFG register ************************/ + +#define WWDT_CFG_WDGTB_POSS 7U +#define WWDT_CFG_WDGTB_POSE 8U +#define WWDT_CFG_WDGTB_MSK BITS(WWDT_CFG_WDGTB_POSS,WWDT_CFG_WDGTB_POSE) + +#define WWDT_CFG_W_POSS 0U +#define WWDT_CFG_W_POSE 6U +#define WWDT_CFG_W_MSK BITS(WWDT_CFG_W_POSS,WWDT_CFG_W_POSE) + +/****************** Bit definition for WWDT_IER register ************************/ + +#define WWDT_IER_EWIS_POS 0U +#define WWDT_IER_EWIS_MSK BIT(WWDT_IER_EWIS_POS) + +/****************** Bit definition for WWDT_IDR register ************************/ + +#define WWDT_IDR_EWIS_POS 0U +#define WWDT_IDR_EWIS_MSK BIT(WWDT_IDR_EWIS_POS) + +/****************** Bit definition for WWDT_IVS register ************************/ + +#define WWDT_IVS_EWIS_POS 0U +#define WWDT_IVS_EWIS_MSK BIT(WWDT_IVS_EWIS_POS) + +/****************** Bit definition for WWDT_RIF register ************************/ + +#define WWDT_RIF_EWIF_POS 0U +#define WWDT_RIF_EWIF_MSK BIT(WWDT_RIF_EWIF_POS) + +/****************** Bit definition for WWDT_IFM register ************************/ + +#define WWDT_IFM_EWIM_POS 0U +#define WWDT_IFM_EWIM_MSK BIT(WWDT_IFM_EWIM_POS) + +/****************** Bit definition for WWDT_ICR register ************************/ + +#define WWDT_ICR_EWIC_POS 0U +#define WWDT_ICR_EWIC_MSK BIT(WWDT_ICR_EWIC_POS) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t CFG; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} WWDT_TypeDef; + + + + + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/es32f0271.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/es32f0271.h new file mode 100644 index 0000000000000000000000000000000000000000..2810051370a15c4781e0de78dd79f3167a566811 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/es32f0271.h @@ -0,0 +1,389 @@ +/******************************************************************* +* *file : ES32F0271_sub.h +* *description: ES32F0271 Device Head File +* *author : Eastsoft AE Team +* *version : V1.00.01 +* *data : 4/10/2018 +* +* *Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. +*******************************************************************/ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup ES32F0271_SUB1 + * @{ + */ + +#ifndef __ES32F0271_SUB_H__ +#define __ES32F0271_SUB_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +/** + * @brief defines 'read only' 、'write only'、 'read / write' permissions. + */ +#define __I volatile const /* defines 'read only' permissions */ +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief configuration of the cortex-M3 processor and core peripherals. + */ + +#define __MPU_PRESENT 0 /*!< cm0ikmcu does not provide a MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< cm0ikmcu Supports 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** + * @} + */ + +/** @addtogroup peripherals_interrupt_number_definition + * @{ + */ + +typedef enum IRQn +{ + + /****** ES32 Processor Exceptions Numbers ******************************************************/ + + /*************** Cortex-M0 Processor Exceptions Numbers **************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + + /**************** ES32F0271_SUB specific Exceptions Numbers **************************/ + WWDT_IRQn = 0, /* 0 | WWDT Interrupt */ + PVD_IRQn = 1, /* 1 | PVD Interrupt EXTI[20] */ + RTC_IRQn = 2, /* 2 | RTC Interrupt */ + WAKEUP_IRQn = 3, /* 3 | WAKEUP Interrupt EXTI[21] */ + CM0IKMCU_IRQ04_IRQn = 4, /* 4 | Interrupt */ + EXTI_0to1_IRQn = 5, /* 5 | EXTI[1:0] Interrupt GPIOx[1:0] */ + EXTI_2to3_IRQn = 6, /* 6 | EXTI[3:2] Interrupt GPIOx[3:2] */ + EXTI_4to15_IRQn = 7, /* 7 | EXTI[15:4] Interrupt GPIOx[15:4] */ + CM0IKMCU_IRQ08_IRQn = 8, /* 8 | Interrupt */ + DMA1_CH0_IRQn = 9, /* 9 | DMA1_CH0 Interrupt */ + DMA1_CH12_IRQn = 10, /* 10 | DMA1_CH12 Interrupt */ + DMA1_CH345_IRQn = 11, /* 11 | DMA1_CH345 Interrupt */ + ADC_CMP_IRQn = 12, /* 12 | ADC/COMP0-3 Interrupt EXTI[19:16]) */ + AD16C4T1_IRQn = 13, /* 13 | AD16C4T1 Interrupt */ + BS16T1_IRQn = 14, /* 14 | BS16T1 Interrupt */ + GP32C4T1_IRQn = 15, /* 15 | GP32C4T1 Interrupt */ + GP16C4T1_IRQn = 16, /* 16 | GP16C4T1 Interrupt */ + GP16C4T2_IRQn = 17, /* 17 | GP16C4T2 Interrupt */ + GP16C4T3_IRQn = 18, /* 18 | GP16C4T3 Interrupt */ + GP16C2T1_IRQn = 19, /* 19 | GP16C2T1 Interrupt */ + GP16C2T2_IRQn = 20, /* 20 | GP16C2T2 Interrupt */ + GP16C2T3_IRQn = 21, /* 21 | GP16C2T3 Interrupt */ + GP16C2T4_IRQn = 22, /* 22 | GP16C2T4 Interrupt */ + I2C1_IRQn = 23, /* 23 | I2C1 Interrupt */ + I2C2_IRQn = 24, /* 24 | I2C2 Interrupt */ + SPI1_IRQn = 25, /* 25 | SPI1 Interrupt */ + SPI2_IRQn = 26, /* 26 | SPI2 Interrupt */ + UART1_IRQn = 27, /* 27 | UART1 Interrupt */ + UART2_IRQn = 28, /* 28 | UART2 Interrupt */ + UART3_IRQn = 29, /* 29 | UART3 Interrupt */ + SUART12_IRQn = 30, /* 30 | SUART1/2 Interrupt */ + USB_IRQn = 31 /* 31 | USB Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +/* Includes-------------------------------------------------------------------------------*/ + +#include "core_cm0.h" +#include +#include +#include "system_es32f027x.h" +/** + * @brief these files declare Peripheral register bit_definition. + */ +#include "reg_rcu.h" +#include "reg_syscfg.h" +#include "reg_fc.h" +#include "reg_dma.h" +#include "reg_gpio.h" +#include "reg_i2c.h" +#include "reg_uart.h" +#include "reg_adc.h" +#include "reg_cmp.h" +#include "reg_dac.h" +#include "reg_spi.h" +#include "reg_crc.h" +#include "reg_ad16c4t.h" +#include "reg_hdiv.h" +#include "reg_aes.h" +#include "reg_wwdt.h" +#include "reg_rtc.h" +#include "reg_mswd.h" +#include "reg_mcm.h" +#include "reg_exti.h" +#include "reg_usb.h" + +/******************************************************************************/ +/* Peripheral register */ +/******************************************************************************/ + +/* allow anonymous structures and anonymous enumeration */ +/* #pragma anon_unions */ + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ + +/********************* Base addresses *************************/ +#define FLASH_BASE (0x08000000UL) +#define FLASH_INFO_BASE (0x1FFFE000UL) /* EFLASH Info ( 6K Bytes) - Boot Loader Memory */ +#define SRAM_BASE (0x20000000UL) +#define APB1_BASE (0x40000000UL) +#define APB2_BASE (0x40010000UL) +#define AHB1_BASE (0x40020000UL) +#define AHB2_BASE (0x48000000UL) +#define CM0IN_BASE (0xE0000000UL) + +/* Cortex簧-M0 internal Peripherals - CM0IN_BASE: 0xE0000000*/ +#define TICK_BASE (CM0IN_BASE + 0xE010) + +#define SRAM1_BASE (SRAM_BASE + 0x0000) // SRAM1 Memory ( 4K Bytes) +#define SRAM2_BASE (SRAM_BASE + 0x1000) // SRAM2 Memory ( 4K Bytes) for Rev.B +#define STACK_SIZE 0x00000400>>2 // Stack size (in Words) +#define SRAMTOP 0x1000//0x2000 // Jackey 2018.9.5 + +/***************** peripherals base addresses ********************/ +/* APB1 */ +#define GP32C4T1_BASE (APB1_BASE + 0x0000) +#define GP16C4T1_BASE (APB1_BASE + 0x0400) +#define GP16C4T2_BASE (APB1_BASE + 0x0800) +#define GP16C4T3_BASE (APB1_BASE + 0x0C00) +#define BS16T1_BASE (APB1_BASE + 0x1000) +#define WWDT_BASE (APB1_BASE + 0x2C00) +#define IWDT_BASE (APB1_BASE + 0x3000) +#define SPI2_BASE (APB1_BASE + 0x3800) +#define UART2_BASE (APB1_BASE + 0x4400) +#define UART3_BASE (APB1_BASE + 0x4800) +#define SUART1_BASE (APB1_BASE + 0x4C00) +#define SUART2_BASE (APB1_BASE + 0x5000) +#define I2C1_BASE (APB1_BASE + 0x5400) +#define I2C2_BASE (APB1_BASE + 0x5800) +#define DAC_BASE (APB1_BASE + 0x5C00) +#define PWR_BASE (APB1_BASE + 0x7000) +/* APB2 */ +#define EXTI_BASE (APB2_BASE + 0x0400) +#define ADC_BASE (APB2_BASE + 0x2400) +#define AD16C4T1_BASE (APB2_BASE + 0x2C00) +#define SPI1_BASE (APB2_BASE + 0x3000) +#define UART1_BASE (APB2_BASE + 0x3800) +#define GP16C2T1_BASE (APB2_BASE + 0x4000) +#define GP16C2T2_BASE (APB2_BASE + 0x4400) +#define GP16C2T3_BASE (APB2_BASE + 0x4800) +#define GP16C2T4_BASE (APB2_BASE + 0x4C00) +#define MCM_BASE (APB2_BASE + 0x5400) +#define DBGMCU_BASE (APB2_BASE + 0x5800) +#define COMP_BASE (APB2_BASE + 0x5C00) +/* AHB1 */ +#define DMA1_BASE (AHB1_BASE + 0x0000) +#define RCU_BASE (AHB1_BASE + 0x1000) +#define SYSCFG_BASE (AHB1_BASE + 0x1400) +#define RTC_BASE (AHB1_BASE + 0x1800) +#define EFLASH_BASE (AHB1_BASE + 0x2000) +#define MSWD_BASE (AHB1_BASE + 0x2C00) +#define CRC_BASE (AHB1_BASE + 0x3000) +#define AES_BASE (AHB1_BASE + 0x3400) +#define USB_BASE (AHB1_BASE + 0x3800) +#define HDIV_BASE (AHB1_BASE + 0x3C00) +/* AHB2 */ +#define GPIOA_BASE (AHB2_BASE + 0x0000) +#define GPIOB_BASE (AHB2_BASE + 0x0400) +#define GPIOC_BASE (AHB2_BASE + 0x0800) +#define GPIOD_BASE (AHB2_BASE + 0x0C00) +#define GPIOE_BASE (AHB2_BASE + 0x1000) +#define GPIOF_BASE (AHB2_BASE + 0x1400) + +/********************* Peripheral declaration *************************/ +#define TICK (( TICK_TypeDef *) TICK_BASE) +#define GPIOA (( GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB (( GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC (( GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD (( GPIO_TypeDef *) GPIOD_BASE) +#define DMA1 (( DMA_TypeDef *) DMA1_BASE) +#define RCU (( RCU_TypeDef *) RCU_BASE) +#define SYSCFG (( SYSCFG_TypeDef *) SYSCFG_BASE) +#define FC (( FC_TypeDef *) EFLASH_BASE) +#define CRC (( CRC_TypeDef *) CRC_BASE) +#define AES (( AES_TypeDef *) AES_BASE) +#define HDIV (( HDIV_TypeDef *) HDIV_BASE) +#define MSWD (( MSWD_TypeDef *) MSWD_BASE) +#define USB (( USBCTRL_TypeDef *) USB_BASE) +#define USBH (( USBCTRL_TypeDef *) USB_BASE) +#define USBD (( USBCTRL_TypeDef *) USB_BASE) +#define IWDT (( IWDT_TypeDef *) IWDT_BASE) +#define WWDT (( WWDT_TypeDef *) WWDT_BASE) +#define ADC (( ADC_TypeDef *) ADC_BASE) +#define AD16C4T1 (( AD16C4T_TypeDef *) AD16C4T1_BASE) +#define GP32C4T1 (( AD16C4T_TypeDef *) GP32C4T1_BASE) +#define GP16C4T1 (( AD16C4T_TypeDef *) GP16C4T1_BASE) +#define GP16C4T2 (( AD16C4T_TypeDef *) GP16C4T2_BASE) +#define GP16C4T3 (( AD16C4T_TypeDef *) GP16C4T3_BASE) +#define GP16C2T1 (( AD16C4T_TypeDef *) GP16C2T1_BASE) +#define GP16C2T2 (( AD16C4T_TypeDef *) GP16C2T2_BASE) +#define GP16C2T3 (( AD16C4T_TypeDef *) GP16C2T3_BASE) +#define GP16C2T4 (( AD16C4T_TypeDef *) GP16C2T4_BASE) +#define BS16T1 (( AD16C4T_TypeDef *) BS16T1_BASE) +#define SPI1 (( SPI_TypeDef *) SPI1_BASE) +#define SPI2 (( SPI_TypeDef *) SPI2_BASE) +#define I2C1 (( I2C_TypeDef *) I2C1_BASE) +#define I2C2 (( I2C_TypeDef *) I2C2_BASE) +#define DAC (( DAC_TypeDef *) DAC_BASE) +#define CMP (( CMP_TypeDef *) COMP_BASE) +#define UART1 (( UART_TypeDef *) UART1_BASE) +#define UART2 (( UART_TypeDef *) UART2_BASE) +#define UART3 (( UART_TypeDef *) UART3_BASE) +#define SUART1 (( UART_TypeDef *) SUART1_BASE) +#define SUART2 (( UART_TypeDef *) SUART2_BASE) +#define EXTI (( EXTI_TypeDef *) EXTI_BASE) +#define RTC (( RTC_TypeDef *) RTC_BASE) +#define MCM (( MCM_TypeDef *) MCM_BASE) +/* Special stuff */ +#define MSG_INCR ( __IO uint8_t *) (DBGMCU_BASE + 0x50) +#define MSG_WR ( __IO uint32_t *) (DBGMCU_BASE + 0x54) +#define MSG_END ( __IO uint32_t *) (DBGMCU_BASE + 0x58) +#define MSG_INCR_S ( __IO uint32_t *) (DBGMCU_BASE + 0x5C) +#define MSG_INCR_X ( __IO uint32_t *) (DBGMCU_BASE + 0x60) +#define MSG_INCR_B ( __IO uint32_t *) (DBGMCU_BASE + 0x64) +#define MSG_PTR ( __IO uint8_t **) (DBGMCU_BASE + 0x68) +#define MSG_INCR_D ( __IO uint32_t *) (DBGMCU_BASE + 0x78) +#define INCR_ERR_CNT ( __IO uint32_t *) (DBGMCU_BASE + 0x6C) + +#define END_SIM *MSG_END +#define SIM_FAIL 0xFFFFAAAA +#define SIM_PASS 0xFFFF5555 +/******************************************************************************/ +/* macros */ +/******************************************************************************/ + +/** @addtogroup Public_macros + * @{ + */ +#if defined (__CC_ARM) +#define __INLINE__ __inline +#else +#define __INLINE__ inline +#endif + +#define __isr__ + +#define UNUSED(x) ((void)(x)) + +#ifdef USE_ASSERT +#define assert_param(x) \ +do \ +{ \ + if (!(x)) \ + { \ + __disable_irq(); \ + while (1) \ + ; \ + } \ +} while (0) +#else +#define assert_param(x) +#endif + +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) + +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) &\ + (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) + +#define SET_BIT(REG, SETMASK) ((REG) |= (SETMASK)) + +#define CLEAR_BIT(REG, SETMASK) ((REG) &= ~(SETMASK)) + +#define READ_BIT(REG, SETMASK) ((REG) & (SETMASK)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + +/** + * @} + */ + +/******************************************************************************/ +/* types */ +/******************************************************************************/ +/** @addtogroup Public_types + * @{ + */ +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} TypeFunc,FuncState; +#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) + +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus, PinStatus; + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +typedef enum +{ + BIT_RESET = 0x0, + BIT_SET = 0x1, +} BitStatus; + +typedef enum +{ + FALSE = 0x0, + TRUE = 0x1, +} TypeBool; + +typedef enum +{ + UNLOCK = 0x0, + LOCK = 0x1, +} LockState; +#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) + +/** + * @} Public_types + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/** + * @} ES32F0271_SUB + */ + +/** + * @} CMSIS + */ + +/************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/rt_misc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/rt_misc.h new file mode 100644 index 0000000000000000000000000000000000000000..71a3270c6e3093d4ddb0dd5b793dc0c72ca6d82f --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Include/rt_misc.h @@ -0,0 +1,183 @@ +/* rt_misc.h: definitions for miscellaneous retargetable functions + * + * Copyright 1999,2013-2014 ARM Limited. All rights reserved. + * + * RCS $Revision$ + * Checkin $Date$ + * Revising $Author$ + */ + +#ifndef __RT_MISC_H +#define __RT_MISC_H +#define __ARMCLIB_VERSION 5060019 + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/* + * This will be called during startup if it's defined, in order to + * allow a user reimplementation of getenv() to initialise itself. + */ +extern void _getenv_init(void); + +/* + * This will be called during startup if it's defined, in order to + * allow a user reimplementation of clock() to initialise itself. + */ +extern void _clock_init(void); + +/* + * This must return a pointer to __USER_LIBSPACE_SIZE bytes of + * zero-initialised space, used to store vital static data such as + * errno, the heap state, and the FP status word. + */ +#define __USER_LIBSPACE_SIZE 96 +extern void *__user_libspace(void); + +/* + * This is the library init function itself, provided just in case + * a user needs to call it directly. It is called just after + * __rt_stackheap_init(), and passed an initial chunk of memory to + * use as a heap. It returns argc and argv ready to be passed to + * main(). (The __argc_argv structure contains four words rather + * than just two, in case you need to pass anything else to main() + * such as the Unix envp. For AArch64 struct __argc_argv is 8 words + * (4 registers) and explicit padding is used to ensure argc is in w0.) + */ +struct __argc_argv { +#if (defined(__ARM_64BIT_STATE) || defined(__TARGET_ARCH_AARCH64)) && \ + (defined(__ARM_BIG_ENDIAN) || defined(__BIG_ENDIAN)) + int padding; +#endif + int argc; +#if (defined(__ARM_64BIT_STATE) || defined(__TARGET_ARCH_AARCH64)) && \ + !(defined(__ARM_BIG_ENDIAN) || defined(__BIG_ENDIAN)) + int padding; +#endif + char **argv; + void *r2; + void *r3; +}; +extern __value_in_regs struct __argc_argv +__rt_lib_init(unsigned /*heapbase*/, unsigned /*heaptop*/); + +/* + * This function is responsible for constructing argc and argv to + * be passed to main(). Normally it works by calling + * _sys_command_string() and then splitting up the returned command + * line. If you define main() without arguments, the compiler also + * defines an empty version of this function to save time. In + * special circumstances, you might need to redefine this function + * explicitly yourself. + */ +__value_in_regs struct __argc_argv __ARM_get_argv(void */*internal use only*/); + +/* + * This is the library shutdown function, analogous to + * __rt_lib_init(). + */ +extern void __rt_lib_shutdown(void); + +/* + * The medium-level exit function. exit() calls atexit()-registered + * functions and shuts down the library; _sys_exit() does neither + * of those things; __rt_exit() shuts down the library but doesn't + * call atexit() functions. + */ +extern void __rt_exit(int /*returncode*/); /* never returns */ + +/* + * This can be defined to override the standard memory models' way + * of determining where to put the initial stack and heap. + * + * The input parameters R0 and R2 contain nothing useful. The input + * parameters SP and SL are the values that were in SP and SL when + * the program began execution (so you can return them if you want + * to keep that stack). + * + * The two `limit' fields in the return structure are ignored if + * you are using the one-region memory model: the memory region is + * taken to be all the space between heap_base and stack_base. + */ +struct __initial_stackheap { + unsigned heap_base; /* low-address end of initial heap */ + unsigned stack_base; /* high-address end of initial stack */ + unsigned heap_limit; /* high-address end of initial heap */ + unsigned stack_limit; /* low-address end of initial stack */ +}; +extern __value_in_regs struct __initial_stackheap +__user_initial_stackheap(unsigned /*R0*/, unsigned /*SP*/, + unsigned /*R2*/, unsigned /*SL*/); + +/* + * This can be defined to give bounds on the address space the heap + * will ever use. + */ +struct __heap_extent { + uintptr_t base; + size_t range; +}; +extern __value_in_regs struct __heap_extent +__user_heap_extent(uintptr_t /*ignore*/, size_t /*ignore*/); + +/* + * This can be defined to specify how much spare stack is needed + * below SL in addition to the 256 bytes required by ATPCS: + * `always' gives the number of bytes of extra stack required at + * all instants (so that an interrupt handler has space to run in, + * for example), while `cleanup' gives the number of bytes of extra + * stack required to be available after a stack overflow has + * occurred, so that the stack overflow routine (e.g. SIGSTAK + * handler) has room to tidy up. + */ +struct __stack_slop { + unsigned always, cleanup; +}; +extern __value_in_regs struct __stack_slop +__user_stack_slop(unsigned /*ignore*/, unsigned /*ignore*/); + +/* + * This can be defined to return extra blocks of memory, separate + * from the initial one, to be used by the heap. It should place a + * pointer to a block of at least the requested size in `*base', + * and return the size of the block. It should return 0 if no such + * block can be returned, in which case the value stored at `*base' + * is never used. + */ +extern size_t __user_heap_extend(int /*ignore*/, + void ** /*base*/, + size_t /*requestedsize*/); + +/* + * Redefine this to completely override the C handling of signals + * (bypassing the signal() mechanism). Return values are 0 to + * continue execution, or a non-zero value to cause an exit with + * that return code. + */ +int __raise(int /*sig*/, intptr_t /*type*/); + +/* + * Redefine this to change the default handling of signals. The + * interface is the same as __raise(), but this function will only + * get called after the C signal handling mechanism has declined to + * process the signal. + */ +int __default_signal_handler(int /*sig*/, intptr_t /*type*/); + +/* + * Redefine this to replace the library's entire signal handling + * mechanism in the most efficient possible way. The default + * implementation of this is what calls __raise (above). + */ +void __rt_raise(int /*sig*/, intptr_t /*type*/); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/ReleaseNote.html b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/ReleaseNote.html similarity index 47% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/ReleaseNote.html rename to bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/ReleaseNote.html index a57c58046d66d43f9d1161783c33531f4309db61..dce80ba62c72cc960649193235529b61a0068b3d 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/ReleaseNote.html +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/ReleaseNote.html @@ -3,10 +3,12 @@ ReleaseNote -

ES32F065x MD Release Note

-

V1.00 2018-12-26

-
    -
  1. First release
    2. +

    ES32F0271 Device Release Note

    +

    V1.00 2019-1-4

    +

    初版发布

    +

    V1.03 2019-09-23

    +
      +
    1. Drivers\CMSIS\Device\EastSoft\ES32F0271\Startup\iar\ : 增加startup_es32f027x.s

     

    diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/iar/startup_es32f027x.s b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/iar/startup_es32f027x.s new file mode 100644 index 0000000000000000000000000000000000000000..bda1ad6ecd778a0e18ec55a0d832913d1221060a --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/iar/startup_es32f027x.s @@ -0,0 +1,256 @@ +;******************************************************************************* +; file : startup_ES32f027x.s +; description: ES32F027x Device Startup File +; author : Eastsoft MCU Software Team +; data : 10 Dec 2018 +; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. +;******************************************************************************* + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ;0, load top of stack + DCD Reset_Handler ;1, reset handler + DCD NMI_Handler ;2, nmi handler + DCD HardFault_Handler ;3, hard fault handler + DCD 0 ;4, MPU Fault Handler + DCD 0 ;5, Bus Fault Handler + DCD 0 ;6, Usage Fault Handler + DCD 0 ;7, Reserved + DCD 0 ;8, Reserved + DCD 0 ;9, Reserved + DCD 0 ;10, Reserved + DCD SVC_Handler ;11, svcall handler + DCD 0 ;12, Reserved + DCD 0 ;13, Reserved + DCD PENDSV_Handler ;14, PENDSV Handler + DCD SYSTICK_Handler ;15, SYSTICK Handler + DCD WWDT_IRQHandler ;16, WWDT IRQHandler + DCD PVD_IRQHandler ;17, PVD IRQHandler + DCD RTC_IRQHandler ;18, RTC IRQHandler + DCD LowPowerWakeup_IRQHandler ;19, LowPowerWakeup IRQHandler + DCD 0 ;20, Reserved + DCD EXTI0_1_IRQHandler ;21, EXTI01_1 IRQHandler + DCD EXTI2_3_IRQHandler ;22, EXTI2_3 IRQHandler + DCD EXTI4_15_IRQHandler ;23, EXTI4_15 IRQHandler + DCD 0 ;24, Reserved + DCD DMA1_CH0_IRQHandler ;25, DMA1_CH1 IRQHandler + DCD DMA1_CH1_2_IRQHandler ;26, DMA1_CH2_3 IRQHandler + DCD DMA1_CH3_5_IRQHandler ;27, DMA1_CH4_7 IRQHandler + DCD ADC_CMP_IRQHandler ;28, ADC_CMP IRQHandler + DCD AD16C4T1_IRQHandler ;29, AD16C4T1 IRQHandler + DCD BS16T1_IRQHandler ;30, BS16T1 IRQHandler + DCD GP32C4T1_IRQHandler ;31, GP32C4T1 IRQHandler + DCD GP16C4T1_IRQHandler ;32, GP16C4T1 IRQHandler + DCD GP16C4T2_IRQHandler ;33, GP16C4T2 IRQHandler + DCD GP16C4T3_IRQHandler ;34, GP16C4T3 IRQHandler + DCD GP16C2T1_IRQHandler ;35, GP16C2T1 IRQHandler + DCD GP16C2T2_IRQHandler ;36, GP16C2T2 IRQHandler + DCD GP16C2T3_IRQHandler ;37, GP16C2T3 IRQHandler + DCD GP16C2T4_IRQHandler ;38, GP16C2T4 IRQHandler + DCD I2C1_IRQHandler ;39, I2C1 IRQHandler + DCD I2C2_IRQHandler ;40, I2C2 IRQHandler + DCD SPI1_IRQHandler ;41, SPI1 IRQHandler + DCD SPI2_IRQHandler ;42, SPI2 IRQHandler + DCD UART1_IRQHandler ;43, UART1 IRQHandler + DCD UART2_IRQHandler ;44, UART2 IRQHandler + DCD UART3_AES_IRQHandler ;45, UART3_AES IRQHandler + DCD SUART1_SUART2_IRQHandler ;46, SUART1_SUART2 IRQHandler + DCD USB_IRQHandler ;47, USB IRQHandler + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PENDSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PENDSV_Handler + B PENDSV_Handler + + PUBWEAK SYSTICK_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SYSTICK_Handler + B SYSTICK_Handler + + PUBWEAK WWDT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDT_IRQHandler + B WWDT_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK LowPowerWakeup_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LowPowerWakeup_IRQHandler + B LowPowerWakeup_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK DMA1_CH0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH0_IRQHandler + B DMA1_CH0_IRQHandler + + PUBWEAK DMA1_CH1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH1_2_IRQHandler + B DMA1_CH1_2_IRQHandler + + PUBWEAK DMA1_CH3_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH3_5_IRQHandler + B DMA1_CH3_5_IRQHandler + + PUBWEAK ADC_CMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_CMP_IRQHandler + B ADC_CMP_IRQHandler + + PUBWEAK AD16C4T1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T1_IRQHandler + B AD16C4T1_IRQHandler + + PUBWEAK BS16T1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BS16T1_IRQHandler + B BS16T1_IRQHandler + + PUBWEAK GP32C4T1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GP32C4T1_IRQHandler + B GP32C4T1_IRQHandler + + PUBWEAK GP16C4T1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C4T1_IRQHandler + B GP16C4T1_IRQHandler + + PUBWEAK GP16C4T2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C4T2_IRQHandler + B GP16C4T2_IRQHandler + + PUBWEAK GP16C4T3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C4T3_IRQHandler + B GP16C4T3_IRQHandler + + PUBWEAK GP16C2T1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C2T1_IRQHandler + B GP16C2T1_IRQHandler + + PUBWEAK GP16C2T2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C2T2_IRQHandler + B GP16C2T2_IRQHandler + + PUBWEAK GP16C2T3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C2T3_IRQHandler + B GP16C2T3_IRQHandler + + PUBWEAK GP16C2T4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C2T4_IRQHandler + B GP16C2T4_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_IRQHandler + B UART1_IRQHandler + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_IRQHandler + B UART2_IRQHandler + + PUBWEAK UART3_AES_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_AES_IRQHandler + B UART3_AES_IRQHandler + + PUBWEAK SUART1_SUART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SUART1_SUART2_IRQHandler + B SUART1_SUART2_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + END diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/boot.c b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/boot.c new file mode 100644 index 0000000000000000000000000000000000000000..4c4e15ee4c80c85604ce452f8a092d678f6212cc --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/boot.c @@ -0,0 +1,321 @@ + +// +// Boot (vectors) file for Cortex-M0 Integration Kit +// + +#include +#include +#include +#include "es32F0271_sub.h" + +// +// Build a stand-alone image +// + +#pragma import(__use_no_semihosting) + + +/*----------------------------------------------------------------------*/ +/*-------------- Interrupt Handlers --------------*/ +/*----------------------------------------------------------------------*/ +// The following functions are defined weakly to allow the user +// to override them at link time simply by declaring their own +// function of the same name. +// +// If no user function is provided, the weak function is used. +// +//------------------------------------ IRQ NMI Handler +__weak void NMI_Handler(void) +{ + while(1); +} +//------------------------------------ IRQ Hard Fault Handler +__weak void HardFault_Handler(void) +{ + //printf("Hard Fault\r\n"); + while(1); +} +//------------------------------------ IRQ SVCall Handler +__weak void SVC_Handler(void) +{ + while(1); +} +//------------------------------------ IRQ PendSV Handler +__weak void PendSV_Handler(void) +{ + while(1); +} +//------------------------------------ IRQ SysTick Handler +__weak void SysTick_Handler(void) +{ + while(1); +} +//------------------------------------ IRQ 31 +__weak void USB_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 30 +__weak void SUART12_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 29 +__weak void UART3_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 28 +__weak void UART2_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 27 +__weak void UART1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 26 +__weak void SPI2_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 25 +__weak void SPI1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 24 +__weak void I2C2_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 23 +__weak void I2C1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 22 +__weak void GPTIMC4_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 21 +__weak void GPTIMC3_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 20 +__weak void GPTIMC2_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 19 +__weak void GPTIMC1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 18 +__weak void GPTIMB3_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 17 +__weak void GPTIMB2_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 16 +__weak void GPTIMB1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 15 +__weak void GPTIMA1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 14 +__weak void BSTIM1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 13 +__weak void ADTIM1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 12 +__weak void ADC_COMP_IRQHandler(void) +{ + // while(1); +} +//------------------------------------ IRQ 11 +__weak void DMA1_CH345_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 10 +__weak void DMA1_CH12_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 9 +__weak void DMA1_CH0_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 8 +//------------------------------------ IRQ 7 +__weak void EXTI_4to15_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 6 +__weak void EXTI_2to3_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 5 +__weak void EXTI_0to1_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 4 +//------------------------------------ IRQ 3 +__weak void WAKEUP_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 2 +__weak void RTC_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 1 +__weak void PVD_IRQHandler(void) +{ + while(1); +} +//------------------------------------ IRQ 0 +__weak void WWDT_IRQHandler(void) +{ + while(1); +} + + +/*----------------------------------------------------------------------*/ +/*-------------- Defined Handler --------------*/ +/*----------------------------------------------------------------------*/ +__weak void Default_IRQHandler(void) +{ + while(1); +} + +/*----------------------------------------------------------------------*/ +/*-------------- Symbols defined in linker script ---------*/ +/*----------------------------------------------------------------------*/ + +extern void __main(void); + +/*----------------------------------------------------------------------*/ +/*-------------- Reset Handler --------------*/ +/*----------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __main(); + while(1) {;} // In case main() fails +} + +/*----------------------------------------------------------------------*/ +/*-------------- Set up Vector Table --------------*/ +/*----------------------------------------------------------------------*/ +typedef void (*const vect_t)(void) __irq; + +vect_t __Vectors[] +__attribute__ ((section("vectors"))) = { + (vect_t)(SRAM1_BASE+SRAMTOP),//(vect_t)(0x20000F80), // Top of Stack - Allowing 4 words for DEBUGDRIVERDATA + (vect_t)Reset_Handler, // Reset Handler + (vect_t)NMI_Handler, // NMI Handler + (vect_t)HardFault_Handler,// Hard Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + (vect_t)SVC_Handler, // SVCall Handler + 0, // Reserved + 0, // Reserved + (vect_t)PendSV_Handler, // PendSV Handler + (vect_t)SysTick_Handler, // SysTick Handler + /*----------External Exceptions---------------------------------------------*/ + // External Interrupts 0 - 31 + // These are essentially unused, so will all + // take the same default handler if invoked. + // External Interrupts + //|=========================================| + //| IRQ NO. | M621 | + //|-----------------------------------------| + (vect_t)WWDT_IRQHandler, //| 0 | WWDG | | + (vect_t)PVD_IRQHandler, //| 1 | PVD | EXTI[20] | + (vect_t)RTC_IRQHandler, //| 2 | RTC | | + (vect_t)WAKEUP_IRQHandler, //| 3 | WAKEUP | EXTI[21] | + (vect_t)Default_IRQHandler, //| 4 | | | + (vect_t)EXTI_0to1_IRQHandler, //| 5 | EXTI[1:0] | GPIOx[1:0] | + (vect_t)EXTI_2to3_IRQHandler, //| 6 | EXTI[3:2] | GPIOx[3:2] | + (vect_t)EXTI_4to15_IRQHandler, //| 7 | EXTI[15:4] | GPIOx[15:4] | + (vect_t)Default_IRQHandler, //| 8 | | | + (vect_t)DMA1_CH0_IRQHandler, //| 9 | DMA1_CH0 | | + (vect_t)DMA1_CH12_IRQHandler, //| 10 | DMA1_CH12 | | + (vect_t)DMA1_CH345_IRQHandler, //| 11 | DMA1_CH345 | | + (vect_t)ADC_COMP_IRQHandler, //| 12 | ADC/COMP0-3 | EXTI[19:16] | + (vect_t)ADTIM1_IRQHandler, //| 13 | ADTIM1 | | + (vect_t)BSTIM1_IRQHandler, //| 14 | BSTIM1 | | + (vect_t)GPTIMA1_IRQHandler, //| 15 | GPTIMA1 | | + (vect_t)GPTIMB1_IRQHandler, //| 16 | GPTIMB1 | | + (vect_t)GPTIMB2_IRQHandler, //| 17 | GPTIMB2 | | + (vect_t)GPTIMB3_IRQHandler, //| 18 | GPTIMB3 | | + (vect_t)GPTIMC1_IRQHandler, //| 19 | GPTIMC1 | | + (vect_t)GPTIMC2_IRQHandler, //| 20 | GPTIMC2 | | + (vect_t)GPTIMC3_IRQHandler, //| 21 | GPTIMC3 | | + (vect_t)GPTIMC4_IRQHandler, //| 22 | GPTIMC4 | | + (vect_t)I2C1_IRQHandler, //| 23 | I2C1 | | + (vect_t)I2C2_IRQHandler, //| 24 | I2C2 | | + (vect_t)SPI1_IRQHandler, //| 25 | SPI1 | | + (vect_t)SPI2_IRQHandler, //| 26 | SPI2 | | + (vect_t)UART1_IRQHandler, //| 27 | UART1 | | + (vect_t)UART2_IRQHandler, //| 28 | UART2 | | + (vect_t)UART3_IRQHandler, //| 29 | UART3 | | + (vect_t)SUART12_IRQHandler, //| 30 | SUART1/2 | | + (vect_t)USB_IRQHandler //| 31 | USB | | + //==========================================| +}; + + +/*----------------------------------------------------------------------*/ +/*-------------- Set up initial stack and heap --------------*/ +/*----------------------------------------------------------------------*/ +__value_in_regs struct __initial_stackheap +__user_initial_stackheap(unsigned hb, unsigned sb, unsigned hl, unsigned sl) +{ + struct __initial_stackheap s; + + s.heap_base = hb; + s.stack_base = sb; + s.heap_limit = s.stack_base; + s.stack_limit = s.heap_base; + return s; +} + +/*----------------------------------------------------------------------*/ +/*------ Set test status bits in testbench when main() exits -------*/ +/*----------------------------------------------------------------------*/ +void _sys_exit(int return_code) +{ + while(1); +} + + + diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/startup_es32f027x.s b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/startup_es32f027x.s new file mode 100644 index 0000000000000000000000000000000000000000..78c14566c3787dae557b46ee5b30a2a393c69e17 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/Startup/keil/startup_es32f027x.s @@ -0,0 +1,244 @@ +;******************************************************************************* +; *file : startup_ES32F027x.s +; *description: ES32F027x Device Startup File +; *author : Eastsoft MCU Software Team +; *version : V0.01 +; *data : 12/10/2018 +; +; *Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +;******************************************************************************* + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + ; External Interrupts + DCD Reset_Handler ;1, Reset Handler + DCD NMI_Handler ;2, NMI Handler + DCD HardFault_Handler ;3, HARDFAULT Handler + DCD 0 ;4, Reserved + DCD 0 ;5, Reserved + DCD 0 ;6, Reserved + DCD 0 ;7, Reserved + DCD 0 ;8, Reserved + DCD 0 ;9, Reserved + DCD 0 ;10, Reserved + DCD SVC_Handler ;11, SVC Handler + DCD 0 ;12, Reserved + DCD 0 ;13, Reserved + DCD PendSV_Handler ;14, PENDSV Handler + DCD SysTick_Handler ;15, SYSTICK Handler + DCD WWDT_IRQHandler ;16, WWDT IRQHandler + DCD PVD_IRQHandler ;17, PVD IRQHandler + DCD RTC_IRQHandler ;18, RTC IRQHandler + DCD LowPowerWakeup_IRQHandler ;19, LowPowerWakeup IRQHandler + DCD 0 ;20, Reserved + DCD EXTI0_1_IRQHandler ;21, EXTI01_1 IRQHandler + DCD EXTI2_3_IRQHandler ;22, EXTI2_3 IRQHandler + DCD EXTI4_15_IRQHandler ;23, EXTI4_15 IRQHandler + DCD 0 ;24, Reserved + DCD DMA1_CH0_IRQHandler ;25, DMA1_CH0 IRQHandler + DCD DMA1_CH1_2_IRQHandler ;26, DMA1_CH1_2 IRQHandler + DCD DMA1_CH3_5_IRQHandler ;27, DMA1_CH3_5 IRQHandler + DCD ADC_CMP_IRQHandler ;28, ADC_CMP IRQHandler + DCD AD16C4T1_IRQHandler ;29, AD16C4T1 IRQHandler + DCD BS16T1_IRQHandler ;30, BS16T1 IRQHandler + DCD GP32C4T1_IRQHandler ;31, GP32C4T1 IRQHandler + DCD GP16C4T1_IRQHandler ;32, GP16C4T1 IRQHandler + DCD GP16C4T2_IRQHandler ;33, GP16C4T2 IRQHandler + DCD GP16C4T3_IRQHandler ;34, GP16C4T3 IRQHandler + DCD GP16C2T1_IRQHandler ;35, GP16C2T1 IRQHandler + DCD GP16C2T2_IRQHandler ;36, GP16C2T2 IRQHandler + DCD GP16C2T3_IRQHandler ;37, GP16C2T3 IRQHandler + DCD GP16C2T4_IRQHandler ;38, GP16C2T4 IRQHandler + DCD I2C1_IRQHandler ;39, I2C1 IRQHandler + DCD I2C2_IRQHandler ;40, I2C2 IRQHandler + DCD SPI1_IRQHandler ;41, SPI1 IRQHandler + DCD SPI2_IRQHandler ;42, SPI2 IRQHandler + DCD UART1_IRQHandler ;43, UART1 IRQHandler + DCD UART2_IRQHandler ;44, UART2 IRQHandler + DCD UART3_AES_IRQHandler ;45, UART3_AES IRQHandler + DCD SUART1_SUART2_IRQHandler ;46, SUART1_SUART2 IRQHandler + DCD USB_IRQHandler ;47, USB IRQHandler + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception IRQHandlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + + + EXPORT WWDT_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT LowPowerWakeup_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_CH0_IRQHandler [WEAK] + EXPORT DMA1_CH1_2_IRQHandler [WEAK] + EXPORT DMA1_CH3_5_IRQHandler [WEAK] + EXPORT ADC_CMP_IRQHandler [WEAK] + EXPORT AD16C4T1_IRQHandler [WEAK] + EXPORT BS16T1_IRQHandler [WEAK] + EXPORT GP32C4T1_IRQHandler [WEAK] + EXPORT GP16C4T1_IRQHandler [WEAK] + EXPORT GP16C4T2_IRQHandler [WEAK] + EXPORT GP16C4T3_IRQHandler [WEAK] + EXPORT GP16C2T1_IRQHandler [WEAK] + EXPORT GP16C2T2_IRQHandler [WEAK] + EXPORT GP16C2T3_IRQHandler [WEAK] + EXPORT GP16C2T4_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_AES_IRQHandler [WEAK] + EXPORT SUART1_SUART2_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + + + +WWDT_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +LowPowerWakeup_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_CH0_IRQHandler +DMA1_CH1_2_IRQHandler +DMA1_CH3_5_IRQHandler +ADC_CMP_IRQHandler +AD16C4T1_IRQHandler +BS16T1_IRQHandler +GP32C4T1_IRQHandler +GP16C4T1_IRQHandler +GP16C4T2_IRQHandler +GP16C4T3_IRQHandler +GP16C2T1_IRQHandler +GP16C2T2_IRQHandler +GP16C2T3_IRQHandler +GP16C2T4_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_AES_IRQHandler +SUART1_SUART2_IRQHandler +USB_IRQHandler + + + B . + + ENDP + + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + + diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/core_cm0.c b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/core_cm0.c new file mode 100644 index 0000000000000000000000000000000000000000..e8a1ed21c0235902bbece97627636b693fd2dc45 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/core_cm0.c @@ -0,0 +1,472 @@ +/* + *----------------------------------------------------------------------------- + * The confidential and proprietary information contained in this file may + * only be used by a person authorised under and to the extent permitted + * by a subsisting licensing agreement from ARM Limited. + * + * (C) COPYRIGHT 2009-2010 ARM Limited. + * ALL RIGHTS RESERVED + * + * This entire notice must be reproduced on all copies of this file + * and copies of this file may only be made by a person if such person is + * permitted to do so under the terms of a subsisting license agreement + * from ARM Limited. + * + * SVN Information + * + * Checked In : $Date: 2008-12-31 10:59:44 +0000 (Wed, 31 Dec 2008) $ + * + * Revision : $Revision: 97564 $ + * + * Release Information : Cortex-M0-AT510-r0p0-03rel0 + *----------------------------------------------------------------------------- + */ + + +#include + + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for armcc */ + #define __INLINE __inline /*!< inline keyword for armcc */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for iarcc */ + #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */ + #define __nop __no_operation /*!< no operation intrinsic in iarcc */ + +#elif defined ( __GNUC__ ) + #define __ASM asm /*!< asm keyword for gcc */ + #define __INLINE inline /*!< inline keyword for gcc */ +#endif + + + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ + +/** + * @brief Return the Process Stack Pointer + * + * @param none + * @return uint32_t ProcessStackPointer + * + * Return the actual process stack pointer + */ +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} + +/** + * @brief Set the Process Stack Pointer + * + * @param uint32_t Process Stack Pointer + * @return none + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} + +/** + * @brief Return the Main Stack Pointer + * + * @param none + * @return uint32_t Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} + +/** + * @brief Set the Main Stack Pointer + * + * @param uint32_t Main Stack Pointer + * @return none + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param uint16_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in unsigned short value + */ +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param int16_t value to reverse + * @return int32_t reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__ARMCC_VERSION < 400000) + + +/** + * @brief Return the Priority Mask value + * + * @param none + * @return uint32_t PriMask + * + * Return the state of the priority mask bit from the priority mask + * register + */ +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} + +/** + * @brief Set the Priority Mask value + * + * @param uint32_t PriMask + * @return none + * + * Set the priority mask bit in the priority mask register + */ +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} + + +/** + * @brief Return the Control Register value + * + * @param none + * @return uint32_t Control value + * + * Return the content of the control register + */ +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} + +/** + * @brief Set the Control Register value + * + * @param uint32_t Control value + * @return none + * + * Set the control register + */ +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} + +#endif /* __ARMCC_VERSION */ + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +#pragma diag_suppress=Pe940 + +/** + * @brief Return the Process Stack Pointer + * + * @param none + * @return uint32_t ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param uint32_t Process Stack Pointer + * @return none + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @param none + * @return uint32_t Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param uint32_t Main Stack Pointer + * @return none + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param uint16_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); + __ASM("bx lr"); +} + + +#pragma diag_default=Pe940 + + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ + +/** + * @brief Return the Process Stack Pointer + * + * @param none + * @return uint32_t ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param uint32_t Process Stack Pointer + * @return none + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @param none + * @return uint32_t Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param uint32_t Main Stack Pointer + * @return none + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) ); +} + + +/** + * @brief Return the Priority Mask value + * + * @param none + * @return uint32_t PriMask + * + * Return the state of the priority mask bit from the priority mask + * register + */ +uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param uint32_t PriMask + * @return none + * + * Set the priority mask bit in the priority mask register + */ +void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +/** + * @brief Reverse byte order in integer value + * + * @param uint32_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in integer value + */ +uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param uint16_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param int32_t value to reverse + * @return int32_t reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** + * @brief Return the Control Register value + * + * @param none + * @return uint32_t Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param uint32_t Control value + * @return none + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + +#endif + + + + + + + + + + + + + + + + + diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/retarget.c b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/retarget.c new file mode 100644 index 0000000000000000000000000000000000000000..1303e0765e88b926081916b00540f1aab56218e7 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/retarget.c @@ -0,0 +1,55 @@ +/******************************************************************************/ +/* RETARGET.C: 'Retarget' layer for target-dependent low level functions */ +/******************************************************************************/ +/* This file is part of the uVision/ARM development tools. */ +/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */ +/* This software may only be used under the terms of a valid, current, */ +/* end user licence from KEIL for a compatible version of KEIL software */ +/* development tools. Nothing else gives you the right to use this software. */ +/******************************************************************************/ + +#include +#include + +//#pragma import(__use_no_semihosting_swi) + +__weak uint8_t sendchar(uint8_t ui8char) +{ + (void) ui8char; + return 0; +} + + +int ITM_fputc(int ch); /* ITM debug */ + +struct __FILE +{ +int handle; /* Add whatever you need here */ +}; +FILE __stdout; + + +int fputc(int ch, FILE *f) +{ + return (sendchar(ch)); +} + + +int ferror(FILE *f) +{ + /* Your implementation of ferror */ + return EOF; +} + + +void _ttywrch(int ch) +{ + sendchar(ch); +} + + +void _sys_exit(int return_code) +{ +label: + goto label; /* endless loop */ +} diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.c b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.c new file mode 100644 index 0000000000000000000000000000000000000000..6112c52bb4ca5f2292919972f8b23029367bbfb1 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.c @@ -0,0 +1,79 @@ +/** + ************************************************************************************** + * @file system_es32f027x.c + * @brief System File. + * + * @version V0.01 + * @data 5/17/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +/* Incudes--------------------------------------------------------*/ +#include "system_es32f027x.h" + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup System_ES32F027X + * @{ + */ + +/* Public Functions -----------------------------------------------------------*/ +/* Public Init Structure ------------------------------------------------------*/ +/* Public Macros --------------------------------------------------------------*/ +/* Public Constants -----------------------------------------------------------*/ +/* Private Macros -------------------------------------------------------------*/ +/* Private Constants-----------------------------------------------------------*/ + +/* Private Variables ----------------------------------------------------------*/ +/** @addtogroup Private_Variables + * @{ + */ + +/** + * @brief update the value of SystemCoreClock after changing the system clock. + */ +unsigned int SystemCoreClock = 4000000; +unsigned int SystemFrequency_SysClk = 4000000; +unsigned int SystemFrequency_AHBClk = 4000000; +unsigned int SystemFrequency_APBClk = 4000000; +unsigned int PLL1Frequency = 48000000; +unsigned int PLL0Frequency = 4000000; + +/** + * @} Private_Variables + */ + +/* Private Functions ----------------------------------------------------------*/ +/** @addtogroup Private_Functions + * @{ + */ + +/** + * @brief:SystemInit. + * @param:none + * @retval:none + */ +void SystemInit (void) +{ +} + +/** + * @} Private_Functions + */ + +/** + * @} System_ES32F072X + */ + +/** + * @} CMSIS + */ +/********** (C) COPYRIGHT Eastsoft Microelectronics END OF FILE SYSTEM_ES32F027X.H **********/ + diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.h b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.h new file mode 100644 index 0000000000000000000000000000000000000000..d2cee80354f455407f220592ef5f73702946ec02 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.h @@ -0,0 +1,83 @@ +/** + ************************************************************************************** + * @file SYSTEM_ES32F027x.H + * @brief es32f0271 system head file. + * + * @version V0.01 + * @data 5/17/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __SYSTEM_ES32F027x_H__ +#define __SYSTEM_ES32F027x_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes -------------------------------------------------------*/ +#include + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup System_ES32F027x + * @{ + */ + +/* Public Functions -----------------------------------------------------------*/ +/* Public Init Structure ------------------------------------------------------*/ +/* Public Macros --------------------------------------------------------------*/ +/* Public Constants -----------------------------------------------------------*/ +/* Private Variables ----------------------------------------------------------*/ +/* Private Macros -------------------------------------------------------------*/ +/* Private Constants-----------------------------------------------------------*/ + +/* Public Types ---------------------------------------------------------------*/ +/** @addtogroup Public_Types + * @{ + */ +extern unsigned int SystemCoreClock; +extern unsigned int SystemFrequency_SysClk; +extern unsigned int SystemFrequency_AHBClk; +extern unsigned int SystemFrequency_APBClk; +extern unsigned int PLL1Frequency; +extern unsigned int PLL0Frequency; + +/* Exported function -------------------------------------------------*/ +/** @addtogroup Public_Functions + * @{ + */ + +extern void SystemInit (void); + +#ifdef __cplusplus +} +#endif + +#endif + +/** + * @} Public_Functions + */ + +/** + * @} Public_Types + */ + +/** + * @} System_ES32F027x + */ + +/** + * @} CMSIS + */ +/********** (C) COPYRIGHT Eastsoft Microelectronics END OF FILE SYSTEM_ES32F027x.H **********/ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_common_tables.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000000000000000000000000000000000000..dfea7460e9a79e5b20670d947e6a52a894b29801 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_const_structs.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_const_structs.h new file mode 100644 index 0000000000000000000000000000000000000000..80a3e8bbe72b8c54f34a0f40aa1e01f2bfb3308f --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_math.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_math.h new file mode 100644 index 0000000000000000000000000000000000000000..ea9dd26aa8110a0a90babc7b297c5bc6d5eb4216 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/arm_math.h @@ -0,0 +1,7157 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP LibraryU + * @version V1.5.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library + * on Armv8-M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * + *
    + * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
    + * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 Arm Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
    + *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
    + * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
    + *     pData[i*numCols + j]
+ *
    + * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
    + * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
    + * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
    + *     ARM_MATH_SIZE_MISMATCH
+ *
    + * Otherwise the functions return + * 
    + *     ARM_MATH_SUCCESS
+ *
    + * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
    + *     ARM_MATH_MATRIX_CHECK
+ *
    + * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
    +   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
    + * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
    +   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
    + * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
    +   *      x1 = x0 - f(x0)/f'(x0)
+   *
    + * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
    +   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
    + */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
    +   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
    + * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
    +   *     XF = floor(x)
+   *     YF = floor(y)
+   *
    + * \par + * The interpolated output point is computed as: + * 
    +   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
    + * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armcc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000000000000000000000000000000000..093d35b9e5cfe6477ce7a71c842af5f35dabf5c8 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,870 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armclang.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000000000000000000000000000000000000..5c4c20e8777bf1177e03acbb6fca4b80f9b61362 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1877 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_compiler.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000000000000000000000000000000000000..94212eb87a94d11bb8346c6fff99d5fbf838c0ac --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_gcc.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..5d0f07e8accbfdd00dbace8fdf02f98825cfb6f9 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2088 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.3 + * @date 16. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_iccarm.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000000000000000000000000000000000000..edcaee3d4ab1e4026b53858e06930dd53d71f038 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,913 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.5 + * @date 10. January 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_version.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000000000000000000000000000000000000..660f612aa31fe2a71cc786af5cac407e41fdd144 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mbl.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000000000000000000000000000000000000..47a39893aced51da4790b504c92a3bde53204a19 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1896 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mml.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000000000000000000000000000000000000..0951a1f78126b48bf8279a71ecdafbbe4fc50f11 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2960 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000000000000000000000000000000000..a3f1b9ac33045732b0ccef9bf592fbc544ccfb10 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0plus.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000000000000000000000000000000000..f8f30c3496a16d62409066e4ded26c404e7ae813 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1023 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm23.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000000000000000000000000000000000000..7d1d478af2a958f21304ecc743b4ee6bd5a0eb02 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm23.h @@ -0,0 +1,1899 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cm3.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm3.h similarity index 85% rename from bsp/es32f0654/libraries/CMSIS/Include/core_cm3.h rename to bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm3.h index b4ac4c7b05a799590575c0b5c8e24c51748ee20b..a2c0d0805729739413b170af6a47410f89d854de 100644 --- a/bsp/es32f0654/libraries/CMSIS/Include/core_cm3.h +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm3.h @@ -1,40 +1,30 @@ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 + * @version V5.0.5 + * @date 08. January 2018 ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -70,53 +60,15 @@ @{ */ +#include "cmsis_version.h" + /* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif +#define __CORTEX_M (3U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all @@ -128,7 +80,7 @@ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif @@ -143,7 +95,7 @@ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif -#elif defined ( __TMS470__ ) +#elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif @@ -160,8 +112,8 @@ #endif -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + #ifdef __cplusplus } @@ -191,7 +143,7 @@ #endif #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U + #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif @@ -308,9 +260,11 @@ typedef union struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ @@ -336,12 +290,15 @@ typedef union #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ @@ -487,7 +444,7 @@ typedef struct #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201U) /* core r2p1 */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ @@ -602,6 +559,60 @@ typedef struct #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ @@ -645,7 +656,7 @@ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ #else uint32_t RESERVED1[1U]; @@ -770,7 +781,7 @@ typedef struct /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ @@ -1011,8 +1022,11 @@ typedef struct } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -1127,7 +1141,7 @@ typedef struct /*@}*/ /* end of group CMSIS_TPI */ -#if (__MPU_PRESENT == 1U) +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) @@ -1153,6 +1167,8 @@ typedef struct __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; +#define MPU_TYPE_RALIASES 4U + /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ @@ -1337,18 +1353,18 @@ typedef struct /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. - \param[in] value Value of register. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ @@ -1360,7 +1376,7 @@ typedef struct @{ */ -/* Memory mapping of Cortex-M3 Hardware */ +/* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ @@ -1379,7 +1395,7 @@ typedef struct #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ -#if (__MPU_PRESENT == 1U) +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif @@ -1410,6 +1426,40 @@ typedef struct @{ */ +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. @@ -1419,7 +1469,7 @@ typedef struct priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ @@ -1428,7 +1478,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } @@ -1438,121 +1488,178 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } } /** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } } /** \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. + \note IRQn must not be negative. */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } } /** \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } } /** \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } } /** \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. + \note IRQn must not be negative. */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } } /** \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if ((int32_t)(IRQn) < 0) + if ((int32_t)(IRQn) >= 0) { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { - if ((int32_t)(IRQn) < 0) + if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } @@ -1609,11 +1716,42 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr } +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void NVIC_SystemReset(void) +__STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ @@ -1630,6 +1768,38 @@ __STATIC_INLINE void NVIC_SystemReset(void) /*@} end of CMSIS_Core_NVICFunctions */ +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + /* ################################## SysTick function ############################################ */ @@ -1640,7 +1810,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) @{ */ -#if (__Vendor_SysTickConfig == 0U) +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration @@ -1683,8 +1853,8 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) @{ */ -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm33.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000000000000000000000000000000000000..b1efbcae7c733a636cfb4e043b6c4858e84ac6b6 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm33.h @@ -0,0 +1,2963 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cm4.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm4.h similarity index 85% rename from bsp/es32f0654/libraries/CMSIS/Include/core_cm4.h rename to bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm4.h index dc840ebf2221382b8ca8e9ed8ce72b99e4027ad1..a11a3817a23491db120b26564d07c7cb1257b59e 100644 --- a/bsp/es32f0654/libraries/CMSIS/Include/core_cm4.h +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm4.h @@ -1,40 +1,30 @@ /**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 + * @version V5.0.5 + * @date 08. January 2018 ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -70,60 +60,22 @@ @{ */ -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ -#else - #error Unknown compiler -#endif +#define __CORTEX_M (4U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -133,9 +85,9 @@ #define __FPU_USED 0U #endif -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -147,7 +99,7 @@ #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -159,7 +111,7 @@ #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -169,9 +121,9 @@ #define __FPU_USED 0U #endif -#elif defined ( __TMS470__ ) +#elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -183,7 +135,7 @@ #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -195,7 +147,7 @@ #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -207,9 +159,8 @@ #endif -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + #ifdef __cplusplus } @@ -244,7 +195,7 @@ #endif #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U + #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif @@ -367,11 +318,12 @@ typedef union struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ @@ -397,8 +349,8 @@ typedef union #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ @@ -406,6 +358,9 @@ typedef union #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ @@ -662,6 +617,66 @@ typedef struct #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ @@ -831,7 +846,7 @@ typedef struct /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ @@ -1072,8 +1087,11 @@ typedef struct } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -1188,7 +1206,7 @@ typedef struct /*@}*/ /* end of group CMSIS_TPI */ -#if (__MPU_PRESENT == 1U) +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) @@ -1214,6 +1232,8 @@ typedef struct __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; +#define MPU_TYPE_RALIASES 4U + /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ @@ -1280,10 +1300,9 @@ typedef struct #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ -#endif +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ -#if (__FPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) @@ -1388,7 +1407,6 @@ typedef struct #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ -#endif /** @@ -1506,18 +1524,18 @@ typedef struct /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. - \param[in] value Value of register. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ @@ -1529,7 +1547,7 @@ typedef struct @{ */ -/* Memory mapping of Cortex-M4 Hardware */ +/* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ @@ -1548,15 +1566,13 @@ typedef struct #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ -#if (__MPU_PRESENT == 1U) +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ /*@} */ @@ -1584,6 +1600,40 @@ typedef struct @{ */ +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. @@ -1593,7 +1643,7 @@ typedef struct priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ @@ -1602,7 +1652,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } @@ -1612,121 +1662,178 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } } /** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } } /** \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. + \note IRQn must not be negative. */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } } /** \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } } /** \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } } /** \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. + \note IRQn must not be negative. */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } } /** \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if ((int32_t)(IRQn) < 0) + if ((int32_t)(IRQn) >= 0) { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { - if ((int32_t)(IRQn) < 0) + if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } @@ -1783,11 +1890,42 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr } +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void NVIC_SystemReset(void) +__STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ @@ -1804,6 +1942,49 @@ __STATIC_INLINE void NVIC_SystemReset(void) /*@} end of CMSIS_Core_NVICFunctions */ +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + /* ################################## SysTick function ############################################ */ @@ -1814,7 +1995,7 @@ __STATIC_INLINE void NVIC_SystemReset(void) @{ */ -#if (__Vendor_SysTickConfig == 0U) +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration @@ -1857,8 +2038,8 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) @{ */ -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cm7.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm7.h similarity index 87% rename from bsp/es32f0654/libraries/CMSIS/Include/core_cm7.h rename to bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm7.h index 3b7530ad505b57d283cc6f07e7f51b9a54be9a0b..1fe53bf012f4345356dd119fa0f03162f4d04dc6 100644 --- a/bsp/es32f0654/libraries/CMSIS/Include/core_cm7.h +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_cm7.h @@ -1,40 +1,30 @@ /**************************************************************************//** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 + * @version V5.0.5 + * @date 08. January 2018 ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif @@ -70,60 +60,22 @@ @{ */ +#include "cmsis_version.h" + /* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif +#define __CORTEX_M (7U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -133,9 +85,9 @@ #define __FPU_USED 0U #endif -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -147,7 +99,7 @@ #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -159,7 +111,7 @@ #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -169,9 +121,9 @@ #define __FPU_USED 0U #endif -#elif defined ( __TMS470__ ) +#elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -183,7 +135,7 @@ #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -195,7 +147,7 @@ #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" @@ -207,9 +159,8 @@ #endif -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + #ifdef __cplusplus } @@ -382,11 +333,12 @@ typedef union struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ @@ -412,8 +364,8 @@ typedef union #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ @@ -421,6 +373,9 @@ typedef union #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ @@ -529,7 +484,7 @@ typedef struct uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; @@ -715,6 +670,66 @@ typedef struct #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ @@ -1033,7 +1048,7 @@ typedef struct /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ @@ -1277,8 +1292,11 @@ typedef struct } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -1393,7 +1411,7 @@ typedef struct /*@}*/ /* end of group CMSIS_TPI */ -#if (__MPU_PRESENT == 1U) +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) @@ -1419,6 +1437,8 @@ typedef struct __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; +#define MPU_TYPE_RALIASES 4U + /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ @@ -1485,10 +1505,9 @@ typedef struct #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ -#endif +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ -#if (__FPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) @@ -1596,7 +1615,6 @@ typedef struct /* Media and FP Feature Register 2 Definitions */ /*@} end of group CMSIS_FPU */ -#endif /** @@ -1714,18 +1732,18 @@ typedef struct /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. - \param[in] value Value of register. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ @@ -1737,7 +1755,7 @@ typedef struct @{ */ -/* Memory mapping of Cortex-M4 Hardware */ +/* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ @@ -1756,15 +1774,13 @@ typedef struct #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ -#if (__MPU_PRESENT == 1U) +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ /*@} */ @@ -1792,6 +1808,40 @@ typedef struct @{ */ +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. @@ -1801,7 +1851,7 @@ typedef struct priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ @@ -1810,7 +1860,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } @@ -1820,121 +1870,178 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } } /** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } } /** \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. + \note IRQn must not be negative. */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } } /** \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } } /** \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } } /** \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. + \note IRQn must not be negative. */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } } /** \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if ((int32_t)(IRQn) < 0) + if ((int32_t)(IRQn) >= 0) { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { - if ((int32_t)(IRQn) < 0) + if ((int32_t)(IRQn) >= 0) { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } @@ -1991,11 +2098,42 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr } +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void NVIC_SystemReset(void) +__STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ @@ -2012,6 +2150,13 @@ __STATIC_INLINE void NVIC_SystemReset(void) /*@} end of CMSIS_Core_NVICFunctions */ +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif /* ########################## FPU functions #################################### */ /** @@ -2034,17 +2179,17 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void) uint32_t mvfr0; mvfr0 = SCB->MVFR0; - if ((mvfr0 & 0x00000FF0UL) == 0x220UL) + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { - return 2UL; /* Double + Single precision FPU */ + return 2U; /* Double + Single precision FPU */ } - else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { - return 1UL; /* Single precision FPU */ + return 1U; /* Single precision FPU */ } else { - return 0UL; /* No FPU */ + return 0U; /* No FPU */ } } @@ -2072,10 +2217,12 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void) */ __STATIC_INLINE void SCB_EnableICache (void) { - #if (__ICACHE_PRESENT == 1U) + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ __DSB(); __ISB(); @@ -2089,7 +2236,7 @@ __STATIC_INLINE void SCB_EnableICache (void) */ __STATIC_INLINE void SCB_DisableICache (void) { - #if (__ICACHE_PRESENT == 1U) + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ @@ -2106,7 +2253,7 @@ __STATIC_INLINE void SCB_DisableICache (void) */ __STATIC_INLINE void SCB_InvalidateICache (void) { - #if (__ICACHE_PRESENT == 1U) + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->ICIALLU = 0UL; @@ -2122,12 +2269,12 @@ __STATIC_INLINE void SCB_InvalidateICache (void) */ __STATIC_INLINE void SCB_EnableDCache (void) { - #if (__DCACHE_PRESENT == 1U) + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; @@ -2142,8 +2289,8 @@ __STATIC_INLINE void SCB_EnableDCache (void) #if defined ( __CC_ARM ) __schedule_barrier(); #endif - } while (ways--); - } while(sets--); + } while (ways-- != 0U); + } while(sets-- != 0U); __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ @@ -2160,17 +2307,18 @@ __STATIC_INLINE void SCB_EnableDCache (void) */ __STATIC_INLINE void SCB_DisableDCache (void) { - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); - ccsidr = SCB->CCSIDR; - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; /* clean & invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); @@ -2182,8 +2330,8 @@ __STATIC_INLINE void SCB_DisableDCache (void) #if defined ( __CC_ARM ) __schedule_barrier(); #endif - } while (ways--); - } while(sets--); + } while (ways-- != 0U); + } while(sets-- != 0U); __DSB(); __ISB(); @@ -2197,12 +2345,12 @@ __STATIC_INLINE void SCB_DisableDCache (void) */ __STATIC_INLINE void SCB_InvalidateDCache (void) { - #if (__DCACHE_PRESENT == 1U) + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; @@ -2217,8 +2365,8 @@ __STATIC_INLINE void SCB_InvalidateDCache (void) #if defined ( __CC_ARM ) __schedule_barrier(); #endif - } while (ways--); - } while(sets--); + } while (ways-- != 0U); + } while(sets-- != 0U); __DSB(); __ISB(); @@ -2232,13 +2380,13 @@ __STATIC_INLINE void SCB_InvalidateDCache (void) */ __STATIC_INLINE void SCB_CleanDCache (void) { - #if (__DCACHE_PRESENT == 1U) + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); ccsidr = SCB->CCSIDR; @@ -2252,8 +2400,8 @@ __STATIC_INLINE void SCB_CleanDCache (void) #if defined ( __CC_ARM ) __schedule_barrier(); #endif - } while (ways--); - } while(sets--); + } while (ways-- != 0U); + } while(sets-- != 0U); __DSB(); __ISB(); @@ -2267,12 +2415,12 @@ __STATIC_INLINE void SCB_CleanDCache (void) */ __STATIC_INLINE void SCB_CleanInvalidateDCache (void) { - #if (__DCACHE_PRESENT == 1U) + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; @@ -2287,8 +2435,8 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache (void) #if defined ( __CC_ARM ) __schedule_barrier(); #endif - } while (ways--); - } while(sets--); + } while (ways-- != 0U); + } while(sets-- != 0U); __DSB(); __ISB(); @@ -2304,17 +2452,17 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache (void) */ __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) { - #if (__DCACHE_PRESENT == 1U) + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) int32_t op_size = dsize; uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ __DSB(); while (op_size > 0) { SCB->DCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; + op_addr += (uint32_t)linesize; + op_size -= linesize; } __DSB(); @@ -2331,17 +2479,17 @@ __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize */ __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) { - #if (__DCACHE_PRESENT == 1) + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) int32_t op_size = dsize; uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ __DSB(); while (op_size > 0) { SCB->DCCMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; + op_addr += (uint32_t)linesize; + op_size -= linesize; } __DSB(); @@ -2358,17 +2506,17 @@ __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) */ __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) { - #if (__DCACHE_PRESENT == 1U) + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) int32_t op_size = dsize; uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ __DSB(); while (op_size > 0) { SCB->DCCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; + op_addr += (uint32_t)linesize; + op_size -= linesize; } __DSB(); @@ -2389,7 +2537,7 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t @{ */ -#if (__Vendor_SysTickConfig == 0U) +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration @@ -2432,8 +2580,8 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) @{ */ -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc000.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000000000000000000000000000000000000..9aab5e5b3ea5330bb524038aec36100126a59be5 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc000.h @@ -0,0 +1,1016 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc300.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000000000000000000000000000000000000..a569ef2acec4a2966777053c6c51498b21aadbbd --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/core_sc300.h @@ -0,0 +1,1903 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv7.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000000000000000000000000000000000000..aa180c9e5967841134fa5b37a488fa3e5e3f2f2f --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,197 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) + +#define ARM_MPU_AP_NONE 0U +#define ARM_MPU_AP_PRIV 1U +#define ARM_MPU_AP_URO 2U +#define ARM_MPU_AP_FULL 3U +#define ARM_MPU_AP_PRO 5U +#define ARM_MPU_AP_RO 6U + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (MPU_RASR_ENABLE_Msk)) + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv8.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000000000000000000000000000000000000..0ccfc74fe5b640ec5703495996872a5b6bcf1270 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Pos) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/essemi/es32f0271/libraries/CMSIS/Include/tz_context.h b/bsp/essemi/es32f0271/libraries/CMSIS/Include/tz_context.h new file mode 100644 index 0000000000000000000000000000000000000000..0d09749f3a5066f0e061783a1e67972b72ab61a7 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/es32f0654/libraries/CMSIS/RTOS/Template/cmsis_os.h b/bsp/essemi/es32f0271/libraries/CMSIS/RTOS/Template/cmsis_os.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/RTOS/Template/cmsis_os.h rename to bsp/essemi/es32f0271/libraries/CMSIS/RTOS/Template/cmsis_os.h diff --git a/bsp/es32f0654/libraries/CMSIS/index.html b/bsp/essemi/es32f0271/libraries/CMSIS/index.html similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/index.html rename to bsp/essemi/es32f0271/libraries/CMSIS/index.html diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_ad16c4t.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_ad16c4t.h new file mode 100644 index 0000000000000000000000000000000000000000..672719a20b634e7f99bf34050fbc0689a0f1a342 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_ad16c4t.h @@ -0,0 +1,4484 @@ +/** + ************************************************************************************** + * @file md_AD16C4T.h + * @brief ES32F0271 Header file of MD AD16C4T module. + * + * @version V0.01 + * @date 3/12/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. AMD rights reserved. + * + ************************************************************************************** + */ + /* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_AD16C4T_H__ +#define __MD_AD16C4T_H__ + +#ifdef __cplusplus +extern "C"{ +#endif + +/* Includes -------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_ad16c4t.h" + + +/** @addtogroup Micro_Driver + * @{ + */ +#if defined (AD16C4T1) + +/** @defgroup AD16C4T AD16C4T + * @brief AD16C4T module driver + * @{ + */ + + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private Macros ----------------------------------------------------------*/ + + + +/* Public Constants -----------------------------------------------------------*/ + +/** @defgroup MD_AD16C4T_Public_Constants Public Constants + * @brief AD16C4T module driver + * @{ + */ +/* AD16C4T_CON1 macros define*/ +#define MD_AD16C4T_DEBUGSELECT_INPUT (0 << AD16C4T_CON1_DBGSEL_POS) /*!< Channel input*/ +#define MD_AD16C4T_DEBUGSELECT_OUTPUT (1 << AD16C4T_CON1_DBGSEL_POS) /*!< Channel output*/ + +#define MD_AD16C4T_COMPAREINPUT_DISABLE (0 << AD16C4T_CON1_CMPSEL_POSS) /*!< Compare input is disabled*/ +#define MD_AD16C4T_COMPAREINPUT_0 (1 << AD16C4T_CON1_CMPSEL_POSS) /*!< Compare input(CMP_IN)=Compare output 0*/ +#define MD_AD16C4T_COMPAREINPUT_1 (2 << AD16C4T_CON1_CMPSEL_POSS) /*!< Compare input(CMP_IN)=Compare output 1*/ +#define MD_AD16C4T_COMPAREINPUT_2 (3 << AD16C4T_CON1_CMPSEL_POSS) /*!< Compare input(CMP_IN)=Compare output 2*/ +#define MD_AD16C4T_COMPAREINPUT_3 (4 << AD16C4T_CON1_CMPSEL_POSS) /*!< Compare input(CMP_IN)=Compare output 3*/ + +#define MD_AD16C4T_COMPAREPOLARITY_LOW (0 << AD16C4T_CON1_CMPSELP_POS) /*!< Compare input is active low*/ +#define MD_AD16C4T_COMPAREPOLARITY_HIGH (1 << AD16C4T_CON1_CMPSELP_POS) /*!< Compare input is active high*/ + +#define MD_AD16C4T_CLOCKDIVSION_DIV1 (0 << AD16C4T_CON1_DFCKSEL_POSS) /*!< tDTS=tCK_INT*/ +#define MD_AD16C4T_CLOCKDIVSION_DIV2 (1 << AD16C4T_CON1_DFCKSEL_POSS) /*!< tDTS=2*tCK_INT*/ +#define MD_AD16C4T_CLOCKDIVSION_DIV4 (2 << AD16C4T_CON1_DFCKSEL_POSS) /*!< tDTS=4*tCK_INT*/ + +#define MD_AD16C4T_CENTERALIGNED_DISABLE (0 << AD16C4T_CON1_CMSEL_POSS) /*!< Edge-aligned mode*/ +#define MD_AD16C4T_CENTERALIGNED_DOWN (1 << AD16C4T_CON1_CMSEL_POSS) /*!< Center-aligned mode 1*/ +#define MD_AD16C4T_CENTERALIGNED_UP (2 << AD16C4T_CON1_CMSEL_POSS) /*!< Center-aligned mode 2*/ +#define MD_AD16C4T_CENTERALIGNED_BOTH (3 << AD16C4T_CON1_CMSEL_POSS) /*!< Center-aligned mode 3*/ + +#define MD_AD16C4T_UPCOUNTER (0 << AD16C4T_CON1_DIRSEL_POS) /*!< Counter used as upcounter*/ +#define MD_AD16C4T_DOWNCOUNTER (1 << AD16C4T_CON1_DIRSEL_POS) /*!< Counter used as downcounter*/ + +#define MD_AD16C4T_ONEPULSEMODE_DISABLE (0 << AD16C4T_CON1_SPMEN_POS) /*!< Counter is not stopped at update event*/ +#define MD_AD16C4T_ONEPULSEMODE_ENABLE (1 << AD16C4T_CON1_SPMEN_POS) /*!< Counter stops counting at the next update event*/ + +#define MD_AD16C4T_UPDATESOURCE_NORMAL (0 << AD16C4T_CON1_UERSEL_POS) /*!< Counter overflow/underflow, Setting the UG bit, Update generation through the slave mode controller generate an update interrupt*/ +#define MD_AD16C4T_UPDATESOURCE_COUNTER (1 << AD16C4T_CON1_UERSEL_POS) /*!< Only counter overflow/underflow generates an update interrupt or DMA request if Enabled*/ + +/* AD16C4T_CON2 macros define*/ +#define MD_AD16C4T_IDLEOUTPUT_LOW 0 /*!< OC1=0 (after a dead-time if OC1N is implemented) when MOE=0*/ +#define MD_AD16C4T_IDLEOUTPUT_HIGH 1 /*!< OC1=1 (after a dead-time if OC1N is implemented) when MOE=0*/ + +#define MD_AD16C4T_TI1INPUT_CH1 (0 << AD16C4T_CON2_I1SEL_POS) /*!< The TIMx_CH1 pin is connected to TI1 input*/ +#define MD_AD16C4T_TI1INPUT_XOR (1 << AD16C4T_CON2_I1SEL_POS) /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)*/ + +#define MD_AD16C4T_MASTERMODE_RESET (0 << AD16C4T_CON2_MMSEL_POSS) /*!< Reset mode*/ +#define MD_AD16C4T_MASTERMODE_ENABLE (1 << AD16C4T_CON2_MMSEL_POSS) /*!< Enable mode*/ +#define MD_AD16C4T_MASTERMODE_UPDATE (2 << AD16C4T_CON2_MMSEL_POSS) /*!< Update mode*/ +#define MD_AD16C4T_MASTERMODE_COMPAREPULSE (3 << AD16C4T_CON2_MMSEL_POSS) /*!< Compare Pulse mode*/ +#define MD_AD16C4T_MASTERMODE_COMPARE1 (4 << AD16C4T_CON2_MMSEL_POSS) /*!< Compare 1 mode*/ +#define MD_AD16C4T_MASTERMODE_COMPARE2 (5 << AD16C4T_CON2_MMSEL_POSS) /*!< Compare 2 mode*/ +#define MD_AD16C4T_MASTERMODE_COMPARE3 (6 << AD16C4T_CON2_MMSEL_POSS) /*!< Compare 3 mode*/ +#define MD_AD16C4T_MASTERMODE_COMPARE4 (7 << AD16C4T_CON2_MMSEL_POSS) /*!< Compare 4 mode*/ + +#define MD_AD16C4T_DMASELECTION_COMPARE (0 << AD16C4T_CON2_CCDMASEL_POS) /*!< CCx DMA request sent when CCx event occurs*/ +#define MD_AD16C4T_DMASELECTION_UPDATE (1 << AD16C4T_CON2_CCDMASEL_POS) /*!< CCx DMA requests sent when update event occurs*/ + +#define MD_AD16C4T_UPDATESELECTION_COMG (0 << AD16C4T_CON2_CCUSEL_POS) /*!< When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only*/ +#define MD_AD16C4T_UPDATESELECTION_BOTH (1 << AD16C4T_CON2_CCUSEL_POS) /*!< When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI*/ + +#define MD_AD16C4T_CCPRELOAD_DISABLE (0 << AD16C4T_CON2_CCPCEN_POS) /*!< CCxE, CCxNE and OCxM bits are not preloaded*/ +#define MD_AD16C4T_CCPRELOAD_ENABLE (1 << AD16C4T_CON2_CCPCEN_POS) /*!< CCxE, CCxNE and OCxM bits are preloaded*/ + +/* AD16C4T_SMCON macros define*/ +#define MD_AD16C4T_ETRPOLARITY_NONINVERTED (0 << AD16C4T_SMCON_ETPOL_POS) /*!< ETR is non-inverted*/ +#define MD_AD16C4T_ETRPOLARITY_INVERTED (1 << AD16C4T_SMCON_ETPOL_POS) /*!< ETR is inverted*/ + +#define MD_AD16C4T_ETRFILTER_FDIV1 (0 << AD16C4T_SMCON_ETFLT_POSS) /*!< No filter*/ +#define MD_AD16C4T_ETRFILTER_FDIV1N2 (1 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fCK_INT, N = 2*/ +#define MD_AD16C4T_ETRFILTER_FDIV1N4 (2 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fCK_INT, N = 4*/ +#define MD_AD16C4T_ETRFILTER_FDIV1N8 (3 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fCK_INT, N = 8*/ +#define MD_AD16C4T_ETRFILTER_FDIV2N6 (4 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 2, N = 6*/ +#define MD_AD16C4T_ETRFILTER_FDIV2N8 (5 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 2, N = 8*/ +#define MD_AD16C4T_ETRFILTER_FDIV4N6 (6 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 4, N = 6*/ +#define MD_AD16C4T_ETRFILTER_FDIV4N8 (7 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 4, N = 8*/ +#define MD_AD16C4T_ETRFILTER_FDIV8N6 (8 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 8, N = 6*/ +#define MD_AD16C4T_ETRFILTER_FDIV8N8 (9 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 8, N = 8*/ +#define MD_AD16C4T_ETRFILTER_FDIV16N5 (10 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 16, N = 5*/ +#define MD_AD16C4T_ETRFILTER_FDIV16N6 (11 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 16, N = 6*/ +#define MD_AD16C4T_ETRFILTER_FDIV16N8 (12 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 16, N = 8*/ +#define MD_AD16C4T_ETRFILTER_FDIV32N5 (13 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 32, N = 5*/ +#define MD_AD16C4T_ETRFILTER_FDIV32N6 (14 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 32, N = 6*/ +#define MD_AD16C4T_ETRFILTER_FDIV32N8 (15 << AD16C4T_SMCON_ETFLT_POSS) /*!< fSAMPLING = fDTS / 32, N = 8*/ + +#define MD_AD16C4T_MASTERSLAVE_NODELAY (0 << AD16C4T_SMCON_MSCFG_POS) /*!< No action*/ +#define MD_AD16C4T_MASTERSLAVE_DELAY (1 << AD16C4T_SMCON_MSCFG_POS) /*!< The effect of an event on the trigger input (TRGI) is delayed to allow a perfect*/ + +#define MD_AD16C4T_TRIGGERSELECT_ITR0 (0 << AD16C4T_SMCON_TSSEL_POSS) /*!< Internal Trigger 0*/ +#define MD_AD16C4T_TRIGGERSELECT_ITR1 (1 << AD16C4T_SMCON_TSSEL_POSS) /*!< Internal Trigger 1*/ +#define MD_AD16C4T_TRIGGERSELECT_ITR2 (2 << AD16C4T_SMCON_TSSEL_POSS) /*!< Internal Trigger 2*/ +#define MD_AD16C4T_TRIGGERSELECT_ITR3 (3 << AD16C4T_SMCON_TSSEL_POSS) /*!< Internal Trigger 3*/ +#define MD_AD16C4T_TRIGGERSELECT_TI1FED (4 << AD16C4T_SMCON_TSSEL_POSS) /*!< TI1 Edge Detector*/ +#define MD_AD16C4T_TRIGGERSELECT_TI1FP1 (5 << AD16C4T_SMCON_TSSEL_POSS) /*!< Filtered Timer Input 1*/ +#define MD_AD16C4T_TRIGGERSELECT_TI2FP2 (6 << AD16C4T_SMCON_TSSEL_POSS) /*!< Filtered Timer Input 2*/ +#define MD_AD16C4T_TRIGGERSELECT_ETRF (7 << AD16C4T_SMCON_TSSEL_POSS) /*!< External Trigger input*/ + +#define MD_AD16C4T_OCREFCLEAR_CMP (0 << AD16C4T_SMCON_CHCSEL_POS) /*!< OCREF_CLR is connected to the CMP_IN input*/ +#define MD_AD16C4T_OCREFCLEAR_ETRF (1 << AD16C4T_SMCON_CHCSEL_POS) /*!< OCREF_CLR is connected to ETRF*/ + +#define MD_AD16C4T_SLAVEMODE_DISABLE (0 << AD16C4T_SMCON_SMODS_POSS) /*!< Slave mode disabled*/ +#define MD_AD16C4T_SLAVEMODE_ENCODER1 (1 << AD16C4T_SMCON_SMODS_POSS) /*!< Encoder mode 1*/ +#define MD_AD16C4T_SLAVEMODE_ENCODER2 (2 << AD16C4T_SMCON_SMODS_POSS) /*!< Encoder mode 2*/ +#define MD_AD16C4T_SLAVEMODE_ENCODER3 (3 << AD16C4T_SMCON_SMODS_POSS) /*!< Encoder mode 3*/ +#define MD_AD16C4T_SLAVEMODE_RESET (4 << AD16C4T_SMCON_SMODS_POSS) /*!< Reset Mode*/ +#define MD_AD16C4T_SLAVEMODE_GATED (5 << AD16C4T_SMCON_SMODS_POSS) /*!< Gated Mode*/ +#define MD_AD16C4T_SLAVEMODE_TRIGGER (6 << AD16C4T_SMCON_SMODS_POSS) /*!< Trigger Mode*/ +#define MD_AD16C4T_SLAVEMODE_EXTERNALCLOCK (7 << AD16C4T_SMCON_SMODS_POSS) /*!< External Clock Mode 1*/ + +/* AD16C4T_IER IDR IVS RIF IFM ICR macros define*/ +#define MD_AD16C4T_INTERRUPTFALG_CC4OI (1 << AD16C4T_IER_CH4OVI_POS) /*!< Capture/Compare 4 overcapture interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_CC3OI (1 << AD16C4T_IER_CH3OVI_POS) /*!< Capture/Compare 3 overcapture interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_CC2OI (1 << AD16C4T_IER_CH2OVI_POS) /*!< Capture/Compare 2 overcapture interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_CC1OI (1 << AD16C4T_IER_CH1OVI_POS) /*!< Capture/Compare 1 overcapture interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_BI (1 << AD16C4T_IER_BRKI_POS) /*!< Break interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_TI (1 << AD16C4T_IER_TRGI_POS) /*!< Trigger interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_COMI (1 << AD16C4T_IER_COMI_POS) /*!< COM interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_CC4I (1 << AD16C4T_IER_CH4I_POS) /*!< Capture/Compare 4 interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_CC3I (1 << AD16C4T_IER_CH3I_POS) /*!< Capture/Compare 3 interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_CC2I (1 << AD16C4T_IER_CH2I_POS) /*!< Capture/Compare 2 interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_CC1I (1 << AD16C4T_IER_CH1I_POS) /*!< Capture/Compare 1 interrupt*/ +#define MD_AD16C4T_INTERRUPTFALG_UI (1 << AD16C4T_IER_UI_POS) /*!< Update interrupt*/ + +/* AD16C4T_SGE macros define*/ +#define MD_AD16C4T_EVENTGENERATION_BG (1 << AD16C4T_SGE_SGBRK_POS) /*!< Break generation*/ +#define MD_AD16C4T_EVENTGENERATION_TG (1 << AD16C4T_SGE_SGTRG_POS) /*!< Trigger generation*/ +#define MD_AD16C4T_EVENTGENERATION_COMG (1 << AD16C4T_SGE_SGCOM_POS) /*!< Capture/Compare control update generation*/ +#define MD_AD16C4T_EVENTGENERATION_CC4G (1 << AD16C4T_SGE_SGCH4_POS) /*!< Capture/Compare 4 generation*/ +#define MD_AD16C4T_EVENTGENERATION_CC3G (1 << AD16C4T_SGE_SGCH3_POS) /*!< Capture/Compare 3 generation*/ +#define MD_AD16C4T_EVENTGENERATION_CC2G (1 << AD16C4T_SGE_SGCH2_POS) /*!< Capture/Compare 2 generation*/ +#define MD_AD16C4T_EVENTGENERATION_CC1G (1 << AD16C4T_SGE_SGCH1_POS) /*!< Capture/Compare 1 generation*/ +#define MD_AD16C4T_EVENTGENERATION_UG (1 << AD16C4T_SGE_SGU_POS) /*!< Update generation*/ + +/* AD16C4T_CHMR1 CHMR2 output macros define*/ +#define MD_AD16C4T_OUTPUTMODE_DISABLE 0 /*!< Frozen*/ +#define MD_AD16C4T_OUTPUTMODE_HIGHONMSTCH 1 /*!< Set channel 1 to active level on match*/ +#define MD_AD16C4T_OUTPUTMODE_LOWONMSTCH 2 /*!< Set channel 1 to inactive level on match*/ +#define MD_AD16C4T_OUTPUTMODE_TOGGLE 3 /*!< Toggle*/ +#define MD_AD16C4T_OUTPUTMODE_FORCELOW 4 /*!< Force inactive level*/ +#define MD_AD16C4T_OUTPUTMODE_FORCEHIGH 5 /*!< Force active level*/ +#define MD_AD16C4T_OUTPUTMODE_PWMMODE1 6 /*!< PWM mode 1*/ +#define MD_AD16C4T_OUTPUTMODE_PWMMODE2 7 /*!< PWM mode 2*/ + +#define MD_AD16C4T_CHMODE_OUTPUT 0 /*!< CCx channel is configured as output*/ +#define MD_AD16C4T_CHMODE_INPUT_DIRECT 1 /*!< CCx channel is configured as input, ICx is mapped direct*/ +#define MD_AD16C4T_CHMODE_INPUT_INDIRECT 2 /*!< CCx channel is configured as input, ICx is mapped indirect*/ +#define MD_AD16C4T_CHMODE_INPUT_TRC 3 /*!< CCx channel is configured as input, ICx is mapped TRC*/ + +/* AD16C4T_CHMR1 CHMR2 input macros define*/ +#define MD_AD16C4T_INPUTFILTER_FDIV1 0 /*!< No filter*/ +#define MD_AD16C4T_INPUTFILTER_FDIV1N2 1 /*!< fSAMPLING = fCK_INT, N = 2*/ +#define MD_AD16C4T_INPUTFILTER_FDIV1N4 2 /*!< fSAMPLING = fCK_INT, N = 4*/ +#define MD_AD16C4T_INPUTFILTER_FDIV1N8 3 /*!< fSAMPLING = fCK_INT, N = 8*/ +#define MD_AD16C4T_INPUTFILTER_FDIV2N6 4 /*!< fSAMPLING = fDTS / 2, N = 6*/ +#define MD_AD16C4T_INPUTFILTER_FDIV2N8 5 /*!< fSAMPLING = fDTS / 2, N = 8*/ +#define MD_AD16C4T_INPUTFILTER_FDIV4N6 6 /*!< fSAMPLING = fDTS / 4, N = 6*/ +#define MD_AD16C4T_INPUTFILTER_FDIV4N8 7 /*!< fSAMPLING = fDTS / 4, N = 8*/ +#define MD_AD16C4T_INPUTFILTER_FDIV8N6 8 /*!< fSAMPLING = fDTS / 8, N = 6*/ +#define MD_AD16C4T_INPUTFILTER_FDIV8N8 9 /*!< fSAMPLING = fDTS / 8, N = 8*/ +#define MD_AD16C4T_INPUTFILTER_FDIV16N5 10 /*!< fSAMPLING = fDTS / 16, N = 5*/ +#define MD_AD16C4T_INPUTFILTER_FDIV16N6 11 /*!< fSAMPLING = fDTS / 16, N = 6*/ +#define MD_AD16C4T_INPUTFILTER_FDIV16N8 12 /*!< fSAMPLING = fDTS / 16, N = 8*/ +#define MD_AD16C4T_INPUTFILTER_FDIV32N5 13 /*!< fSAMPLING = fDTS / 32, N = 5*/ +#define MD_AD16C4T_INPUTFILTER_FDIV32N6 14 /*!< fSAMPLING = fDTS / 32, N = 6*/ +#define MD_AD16C4T_INPUTFILTER_FDIV32N8 15 /*!< fSAMPLING = fDTS / 32, N = 8*/ + +#define MD_AD16C4T_INPUTPRESCALE_DIV1 0 /*!< no prescaler*/ +#define MD_AD16C4T_INPUTPRESCALE_DIV2 1 /*!< capture is done once every 2 events*/ +#define MD_AD16C4T_INPUTPRESCALE_DIV4 2 /*!< capture is done once every 4 events*/ +#define MD_AD16C4T_INPUTPRESCALE_DIV8 3 /*!< capture is done once every 8 events*/ + +/* AD16C4T_CCEP input macros define*/ +#define MD_AD16C4T_OUTPUTPOLARITY_HIGH 0 /*!< active high*/ +#define MD_AD16C4T_OUTPUTPOLARITY_LOW 1 /*!< active low*/ + +/* AD16C4T_BDCFG input macros define*/ +#define MD_AD16C4T_BREAKPOLARITY_LOW (0 << AD16C4T_BDCFG_BRKP_POS) /*!< Break input BRK is active low*/ +#define MD_AD16C4T_BREAKPOLARITY_HIGH (1 << AD16C4T_BDCFG_BRKP_POS) /*!< Break input BRK is active high */ + +#define MD_AD16C4T_OFFSTATERUN_DISABLE (0 << AD16C4T_BDCFG_OFFSSR_POS) /*!< This bit is used when MOE=1, when inactive, OC/OCN outputs are disabled*/ +#define MD_AD16C4T_OFFSTATERUN_ENABLE (1 << AD16C4T_BDCFG_OFFSSR_POS) /*!< This bit is used when MOE=1, when inactive, OC/OCN outputs are enabled*/ + +#define MD_AD16C4T_OFFSTATEIDLE_DISABLE (0 << AD16C4T_BDCFG_OFFSSI_POS) /*!< This bit is used when MOE=0, when inactive, OC/OCN outputs are disabled*/ +#define MD_AD16C4T_OFFSTATEIDLE_ENABLE (1 << AD16C4T_BDCFG_OFFSSI_POS) /*!< This bit is used when MOE=0, when inactive, OC/OCN outputs are forced*/ + +#define MD_AD16C4T_LOCKLEVEL_0 (0 << AD16C4T_BDCFG_LOCKLVL_POSS) /*!< LOCK OFF*/ +#define MD_AD16C4T_LOCKLEVEL_1 (1 << AD16C4T_BDCFG_LOCKLVL_POSS) /*!< LOCK Level 1*/ +#define MD_AD16C4T_LOCKLEVEL_2 (2 << AD16C4T_BDCFG_LOCKLVL_POSS) /*!< LOCK Level 2*/ +#define MD_AD16C4T_LOCKLEVEL_3 (3 << AD16C4T_BDCFG_LOCKLVL_POSS) /*!< LOCK Level 3*/ + +/** + * @} MD_AD16C4T_Public_Constants + */ + +/* Public Macro ------------------------------------------------------------*/ +/** @defgroup MD_AD16C4T_Public_Macro Public Macro + * @brief AD16C4T module driver + * @{ + */ + +/** + * @brief Timer CON1 setup. + * @param timx AD16C4T instance + * @param value (DBGSEL | CMPSEL | CMPSELP | DFCKSEL | ARPEN | CMSEL | DIRSEL | SPMEN | UERSEL | DISUE | CNTEN) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con1(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CON1, value); +} + +/** + * @brief GET Timer CON1 register value. + * @param timx AD16C4T instance + * @retval Timer CON1 register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con1(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CON1)); +} + +/** + * @brief Timer debug mode select. + * @param timx AD16C4T instance + * @param DebugSelect Debug mode output select + @arg @ref MD_AD16C4T_DEBUGSELECT_INPUT + @arg @ref MD_AD16C4T_DEBUGSELECT_OUTPUT + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con1_dbgsel(AD16C4T_TypeDef *timx, uint32_t DebugSelect) +{ + MODIFY_REG(timx->CON1, AD16C4T_CON1_DBGSEL_MSK, DebugSelect); +} + +/** + * @brief Get timer debug mode select. + * @param timx AD16C4T instance + * @retval Timer debug mode select. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con1_dbgsel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_DBGSEL_MSK) >> AD16C4T_CON1_DBGSEL_POS); +} + +/** + * @brief Timer compare input selection. + * @param timx AD16C4T instance + * @param CompareSelection Compare input selection + @arg @ref MD_AD16C4T_COMPAREINPUT_DISABLE + @arg @ref MD_AD16C4T_COMPAREINPUT_0 + @arg @ref MD_AD16C4T_COMPAREINPUT_1 + @arg @ref MD_AD16C4T_COMPAREINPUT_2 + @arg @ref MD_AD16C4T_COMPAREINPUT_3 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con1_cmpsel(AD16C4T_TypeDef *timx, uint32_t CompareSelection) +{ + MODIFY_REG(timx->CON1, AD16C4T_CON1_CMPSEL_MSK, CompareSelection); +} + +/** + * @brief Get timer compare input selection. + * @param timx AD16C4T instance + * @retval Timer compare input selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con1_cmpsel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_CMPSEL_MSK) >> AD16C4T_CON1_CMPSEL_POSS); +} + +/** + * @brief Timer compare input selection polarity setup. + * @param timx AD16C4T instance + * @param ComparePolarity compare input selection polarity + @arg @ref MD_AD16C4T_COMPAREPOLARITY_LOW + @arg @ref MD_AD16C4T_COMPAREPOLARITY_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con1_cmpselp(AD16C4T_TypeDef *timx, uint32_t ComparePolarity) +{ + MODIFY_REG(timx->CON1, AD16C4T_CON1_CMPSELP_MSK, ComparePolarity); +} + +/** + * @brief Get timer compare input selection polarity. + * @param timx AD16C4T instance + * @retval Timer compare input selection polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con1_cmpselp(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_CMPSELP_MSK) >> AD16C4T_CON1_CMPSELP_POS); +} + +/** + * @brief Timer clock division setup. + * @param timx AD16C4T instance + * @param ClockDivision Clock division + @arg @ref MD_AD16C4T_CLOCKDIVSION_DIV1 + @arg @ref MD_AD16C4T_CLOCKDIVSION_DIV2 + @arg @ref MD_AD16C4T_CLOCKDIVSION_DIV4 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con1_dfcksel(AD16C4T_TypeDef *timx, uint32_t ClockDivision) +{ + MODIFY_REG(timx->CON1, AD16C4T_CON1_DFCKSEL_MSK, ClockDivision); +} + +/** + * @brief Get timer Clock division. + * @param timx AD16C4T instance + * @retval Timer Clock division. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con1_dfcksel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_DFCKSEL_MSK) >> AD16C4T_CON1_DFCKSEL_POSS); +} + +/** + * @brief Timer auto-reload preload enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_con1_arpen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CON1, AD16C4T_CON1_ARPEN_MSK); +} + +/** + * @brief Timer auto-reload preload disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_con1_arpen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CON1, AD16C4T_CON1_ARPEN_MSK); +} + +/** + * @brief Indicates whether the timer auto-reload preload is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_con1_arpen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_ARPEN_MSK) == (AD16C4T_CON1_ARPEN_MSK)); +} + +/** + * @brief Timer center-aligned mode selection setup. + * @param timx AD16C4T instance + * @param CenterAlignedMode center-aligned mode selection + @arg @ref MD_AD16C4T_CENTERALIGNED_DISABLE + @arg @ref MD_AD16C4T_CENTERALIGNED_DOWN + @arg @ref MD_AD16C4T_CENTERALIGNED_UP + @arg @ref MD_AD16C4T_CENTERALIGNED_BOTH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con1_cmsel(AD16C4T_TypeDef *timx, uint32_t CenterAlignedMode) +{ + MODIFY_REG(timx->CON1, AD16C4T_CON1_CMSEL_MSK, CenterAlignedMode); +} + +/** + * @brief Get timer center-aligned mode selection. + * @param timx AD16C4T instance + * @retval Timer center-aligned mode selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con1_cmsel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_CMSEL_MSK) >> AD16C4T_CON1_CMSEL_POSS); +} + +/** + * @brief Timer counting direction setup. + * @param timx AD16C4T instance + * @param direction Counting direction + @arg @ref MD_AD16C4T_UPCOUNTER + @arg @ref MD_AD16C4T_DOWNCOUNTER + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con1_dirsel(AD16C4T_TypeDef *timx, uint32_t direction) +{ + MODIFY_REG(timx->CON1, AD16C4T_CON1_DIRSEL_MSK, direction); +} + +/** + * @brief Get timer counting direction. + * @param timx AD16C4T instance + * @retval Timer counting direction. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con1_dirsel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_DIRSEL_MSK) >> AD16C4T_CON1_DIRSEL_POS); +} + +/** + * @brief Timer one pulse mode enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_con1_spmen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CON1, AD16C4T_CON1_SPMEN_MSK); +} + +/** + * @brief Timer one pulse mode disable. + * @param timx AD16C4T instance + * @retval None. + */ + +__STATIC_INLINE void md_ad16c4t_disable_con1_spmen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CON1, AD16C4T_CON1_SPMEN_MSK); +} + +/** + * @brief Indicates whether the timer one pulse mode is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_con1_spmen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_SPMEN_MSK) == (AD16C4T_CON1_SPMEN_MSK)); +} + +/** + * @brief Timer update request source setup. + * @param timx AD16C4T instance + * @param UpdateSource Update request source select + @arg @ref MD_AD16C4T_UPDATESOURCE_NORMAL + @arg @ref MD_AD16C4T_UPDATESOURCE_COUNTER + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con1_uersel(AD16C4T_TypeDef *timx, uint32_t UpdateSource) +{ + MODIFY_REG(timx->CON1, AD16C4T_CON1_UERSEL_MSK, UpdateSource); +} + +/** + * @brief Get timer update request source. + * @param timx AD16C4T instance + * @retval Timer update request source. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con1_uersel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_UERSEL_MSK) >> AD16C4T_CON1_UERSEL_POS); +} + +/** + * @brief Timer update event enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_con1_disue(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CON1, AD16C4T_CON1_DISUE_MSK); +} + +/** + * @brief Timer update event disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disble_con1_disue(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CON1, AD16C4T_CON1_DISUE_MSK); +} + +/** + * @brief Indicates whether the timer update event is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_con1_disue(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_DISUE_MSK) == (AD16C4T_CON1_DISUE_MSK)); +} + +/** + * @brief Timer counter enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_con1_cnten(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CON1, AD16C4T_CON1_CNTEN_MSK); +} + + +/** + * @brief Timer counter disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_con1_cnten(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CON1, AD16C4T_CON1_CNTEN_MSK); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_con1_cnten(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON1, AD16C4T_CON1_CNTEN_MSK) == (AD16C4T_CON1_CNTEN_MSK)); +} + +/** + * @brief Timer CON2 setup. + * @param timx AD16C4T instance + * @param value (OISS4 | OISS3N | OISS3 | OISS2N | OISS2 | OISS1N | OISS1 | I1SEL | MMSEL | CCDMASEL | CCUSEL | CCPCEN) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CON2, value); +} + +/** + * @brief GET Timer CON2 register value. + * @param timx AD16C4T instance + * @retval Timer CON2 register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CON2)); +} + +/** + * @brief Timer output idle state 4 setup. + * @param timx AD16C4T instance + * @param IdleOutput Output idle state + @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW + @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_oiss4(AD16C4T_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS4_MSK, (IdleOutput << AD16C4T_CON2_OISS4_POS)); +} + +/** + * @brief Get timer output idle state 4. + * @param timx AD16C4T instance + * @retval Timer output idle state 4. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss4(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS4_MSK) >> AD16C4T_CON2_OISS4_POS); +} + +/** + * @brief Timer output idle state 3N setup. + * @param timx AD16C4T instance + * @param IdleOutput Output idle state + @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW + @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_oiss3n(AD16C4T_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS3N_MSK, (IdleOutput << AD16C4T_CON2_OISS3N_POS)); +} + +/** + * @brief Get timer output idle state 3N. + * @param timx AD16C4T instance + * @retval Timer output idle state 3N. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss3n(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS3N_MSK) >> AD16C4T_CON2_OISS3N_POS); +} + +/** + * @brief Timer output idle state 3 setup. + * @param timx AD16C4T instance + * @param IdleOutput Output idle state + @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW + @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_oiss3(AD16C4T_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS3_MSK, (IdleOutput << AD16C4T_CON2_OISS3_POS)); +} + +/** + * @brief Get timer output idle state 3. + * @param timx AD16C4T instance + * @retval Timer output idle state 3. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss3(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS3_MSK) >> AD16C4T_CON2_OISS3_POS); +} + +/** + * @brief Timer output idle state 2N setup. + * @param timx AD16C4T instance + * @param IdleOutput Output idle state + @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW + @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_oiss2n(AD16C4T_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS2N_MSK, (IdleOutput << AD16C4T_CON2_OISS2N_POS)); +} + +/** + * @brief Get timer output idle state 2N. + * @param timx AD16C4T instance + * @retval Timer output idle state 2N. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss2n(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS2N_MSK) >> AD16C4T_CON2_OISS2N_POS); +} + +/** + * @brief Timer output idle state 2 setup. + * @param timx AD16C4T instance + * @param IdleOutput Output idle state + @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW + @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_oiss2(AD16C4T_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS2_MSK, (IdleOutput << AD16C4T_CON2_OISS2_POS)); +} + +/** + * @brief Get timer output idle state 2. + * @param timx AD16C4T instance + * @retval Timer output idle state 2. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss2(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS2_MSK) >> AD16C4T_CON2_OISS2_POS); +} + +/** + * @brief Timer output idle state 1N setup. + * @param timx AD16C4T instance + * @param IdleOutput Output idle state + @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW + @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_oiss1n(AD16C4T_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS1N_MSK, (IdleOutput << AD16C4T_CON2_OISS1N_POS)); +} + +/** + * @brief Get timer output idle state 1N. + * @param timx AD16C4T instance + * @retval Timer output idle state 1N. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss1n(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS1N_MSK) >> AD16C4T_CON2_OISS1N_POS); +} + +/** + * @brief Timer output idle state 1 setup. + * @param timx AD16C4T instance + * @param IdleOutput Output idle state + @arg @ref MD_AD16C4T_IDLEOUTPUT_LOW + @arg @ref MD_AD16C4T_IDLEOUTPUT_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_oiss1(AD16C4T_TypeDef *timx, uint32_t IdleOutput) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_OISS1_MSK, (IdleOutput << AD16C4T_CON2_OISS1_POS)); +} + +/** + * @brief Get timer output idle state 1. + * @param timx AD16C4T instance + * @retval Timer output idle state 1. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_oiss1(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_OISS1_MSK) >> AD16C4T_CON2_OISS1_POS); +} + +/** + * @brief Timer TI1 selection setup. + * @param timx AD16C4T instance + * @param TI1Input TI1 input select + @arg @ref MD_AD16C4T_TI1INPUT_CH1 + @arg @ref MD_AD16C4T_TI1INPUT_XOR + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_i1sel(AD16C4T_TypeDef *timx, uint32_t TI1Input) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_I1SEL_MSK, TI1Input); +} + +/** + * @brief Get timer TI1 selection. + * @param timx AD16C4T instance + * @retval Timer TI1 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_i1sel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_I1SEL_MSK) >> AD16C4T_CON2_I1SEL_POS); +} + +/** + * @brief Timer master mode selection setup. + * @param timx AD16C4T instance + * @param MasterMode Master mode selection + @arg @ref MD_AD16C4T_MASTERMODE_RESET + @arg @ref MD_AD16C4T_MASTERMODE_ENABLE + @arg @ref MD_AD16C4T_MASTERMODE_UPDATE + @arg @ref MD_AD16C4T_MASTERMODE_COMPAREPULSE + @arg @ref MD_AD16C4T_MASTERMODE_COMPARE1 + @arg @ref MD_AD16C4T_MASTERMODE_COMPARE2 + @arg @ref MD_AD16C4T_MASTERMODE_COMPARE3 + @arg @ref MD_AD16C4T_MASTERMODE_COMPARE4 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_mmsel(AD16C4T_TypeDef *timx, uint32_t MasterMode) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_MMSEL_MSK, MasterMode); +} + +/** + * @brief Get timer master mode selection. + * @param timx AD16C4T instance + * @retval Timer master mode selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_mmsel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_MMSEL_MSK) >> AD16C4T_CON2_MMSEL_POSS); +} + +/** + * @brief Timer capture/compare DMA selection setup. + * @param timx AD16C4T instance + * @param DMASelection Capture/compare DMA selection + @arg @ref MD_AD16C4T_DMASELECTION_COMPARE + @arg @ref MD_AD16C4T_DMASELECTION_UPDATE + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_ccdmasel(AD16C4T_TypeDef *timx, uint32_t DMASelection) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_CCDMASEL_MSK, DMASelection); +} + +/** + * @brief Get timer capture/compare DMA selection. + * @param timx AD16C4T instance + * @retval Timer capture/compare DMA selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_ccdmasel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_CCDMASEL_MSK) >> AD16C4T_CON2_CCDMASEL_POS); +} + +/** + * @brief Timer capture/compare control update selection setup. + * @param timx AD16C4T instance + * @param UpdateSelection Capture/compare control update selection + @arg @ref MD_AD16C4T_UPDATESELECTION_COMG + @arg @ref MD_AD16C4T_UPDATESELECTION_BOTH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_con2_ccusel(AD16C4T_TypeDef *timx, uint32_t UpdateSelection) +{ + MODIFY_REG(timx->CON2, AD16C4T_CON2_CCUSEL_MSK, UpdateSelection); +} + +/** + * @brief Get timer capture/compare control update selection. + * @param timx AD16C4T instance + * @retval Timer capture/compare control update selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_con2_ccusel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_CCUSEL_MSK) >> AD16C4T_CON2_CCUSEL_POS); +} + +/** + * @brief Timer capture/compare preloaded control enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_con2_ccpcen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CON2, AD16C4T_CON2_CCPCEN_MSK); +} + +/** + * @brief Timer capture/compare preloaded control disable. + * @param timx AD16C4T instance + * @retval None. + */ + +__STATIC_INLINE void md_ad16c4t_disable_con2_ccpcen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CON2, AD16C4T_CON2_CCPCEN_MSK); +} + +/** + * @brief Indicates whether the timer capture/compare preloaded control is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_con2_ccpcen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CON2, AD16C4T_CON2_CCPCEN_MSK) == (AD16C4T_CON2_CCPCEN_MSK)); +} + +/** + * @brief Timer SMCON setup. + * @param timx AD16C4T instance + * @param value (ETPOL | ECM2EN | ETFLT | MSCFG | TSSEL | CHCSEL | SMODS) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_smcon(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->SMCON, value); +} + +/** + * @brief GET Timer SMCON register value. + * @param timx AD16C4T instance + * @retval Timer SMCON register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_smcon(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->SMCON)); +} + +/** + * @brief Timer external trigger polarity setup. + * @param timx AD16C4T instance + * @param ETRPolarity External trigger polarity + @arg @ref MD_AD16C4T_ETRPOLARITY_NONINVERTED + @arg @ref MD_AD16C4T_ETRPOLARITY_INVERTED + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_smcon_etpol(AD16C4T_TypeDef *timx, uint32_t ETRPolarity) +{ + MODIFY_REG(timx->SMCON, AD16C4T_SMCON_ETPOL_MSK, ETRPolarity); +} + +/** + * @brief Get timer external trigger polarity. + * @param timx AD16C4T instance + * @retval Timer external trigger polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_etpol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->SMCON, AD16C4T_SMCON_ETPOL_MSK) >> AD16C4T_SMCON_ETPOL_POS); +} + +/** + * @brief Timer external clock enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_smcon_ecm2en(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SMCON, AD16C4T_SMCON_ECM2EN_MSK); +} + + +/** + * @brief Timer external clock disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_smcon_ecm2en(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->SMCON, AD16C4T_SMCON_ECM2EN_MSK); +} + +/** + * @brief Indicates whether the timer external clock is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_smcon_ecm2en(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->SMCON, AD16C4T_SMCON_ECM2EN_MSK) == (AD16C4T_SMCON_ECM2EN_MSK)); +} + +/** + * @brief Timer external trigger filter setup. + * @param timx AD16C4T instance + * @param ETRFilter External trigger filter + @arg @ref MD_AD16C4T_ETRFILTER_FDIV1 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV1N2 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV1N4 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV1N8 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV2N6 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV2N8 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV4N6 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV4N8 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV8N6 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV8N8 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV16N5 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV16N6 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV16N8 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV32N5 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV32N6 + @arg @ref MD_AD16C4T_ETRFILTER_FDIV32N8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_smcon_etflt(AD16C4T_TypeDef *timx, uint32_t ETRFilter) +{ + MODIFY_REG(timx->SMCON, AD16C4T_SMCON_ETFLT_MSK, ETRFilter); +} + +/** + * @brief Get timer external trigger filter. + * @param timx AD16C4T instance + * @retval Timer external trigger filter. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_etflt(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->SMCON, AD16C4T_SMCON_ETFLT_MSK) >> AD16C4T_SMCON_ETFLT_POSS); +} + +/** + * @brief Timer master/slave mode setup. + * @param timx AD16C4T instance + * @param MSMode master/slave mode + @arg @ref MD_AD16C4T_MASTERSLAVE_NODELAY + @arg @ref MD_AD16C4T_MASTERSLAVE_DELAY + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_smcon_mscfg(AD16C4T_TypeDef *timx, uint32_t MSMode) +{ + MODIFY_REG(timx->SMCON, AD16C4T_SMCON_MSCFG_MSK, MSMode); +} + +/** + * @brief Get timer master/slave mode. + * @param timx AD16C4T instance + * @retval Timer master/slave mode. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_mscfg(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->SMCON, AD16C4T_SMCON_MSCFG_MSK) >> AD16C4T_SMCON_MSCFG_POS); +} + +/** + * @brief Timer trigger selection setup. + * @param timx AD16C4T instance + * @param TriggerSelect Trigger selection + @arg @ref MD_AD16C4T_TRIGGERSELECT_ITR0 + @arg @ref MD_AD16C4T_TRIGGERSELECT_ITR1 + @arg @ref MD_AD16C4T_TRIGGERSELECT_ITR2 + @arg @ref MD_AD16C4T_TRIGGERSELECT_ITR3 + @arg @ref MD_AD16C4T_TRIGGERSELECT_TI1FED + @arg @ref MD_AD16C4T_TRIGGERSELECT_TI1FP1 + @arg @ref MD_AD16C4T_TRIGGERSELECT_TI2FP2 + @arg @ref MD_AD16C4T_TRIGGERSELECT_ETRF + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_smcon_tssel(AD16C4T_TypeDef *timx, uint32_t TriggerSelect) +{ + MODIFY_REG(timx->SMCON, AD16C4T_SMCON_TSSEL_MSK, TriggerSelect); +} + +/** + * @brief Get timer trigger selection. + * @param timx AD16C4T instance + * @retval Timer trigger selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_tssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->SMCON, AD16C4T_SMCON_TSSEL_MSK) >> AD16C4T_SMCON_TSSEL_POSS); +} + +/** + * @brief Timer OCREF clear selection setup. + * @param timx AD16C4T instance + * @param OCREFSelect OCREF clear selection + @arg @ref MD_AD16C4T_OCREFCLEAR_CMP + @arg @ref MD_AD16C4T_OCREFCLEAR_ETRF + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_smcon_chcsel(AD16C4T_TypeDef *timx, uint32_t OCREFSelect) +{ + MODIFY_REG(timx->SMCON, AD16C4T_SMCON_CHCSEL_MSK, OCREFSelect); +} + +/** + * @brief Get timer OCREF clear selection. + * @param timx AD16C4T instance + * @retval Timer OCREF clear selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_chcsel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->SMCON, AD16C4T_SMCON_CHCSEL_MSK) >> AD16C4T_SMCON_CHCSEL_POS); +} + +/** + * @brief Timer slave mode selection setup. + * @param timx AD16C4T instance + * @param SlaveMode Slave mode selection + @arg @ref MD_AD16C4T_SLAVEMODE_DISABLE + @arg @ref MD_AD16C4T_SLAVEMODE_ENCODER1 + @arg @ref MD_AD16C4T_SLAVEMODE_ENCODER2 + @arg @ref MD_AD16C4T_SLAVEMODE_ENCODER3 + @arg @ref MD_AD16C4T_SLAVEMODE_RESET + @arg @ref MD_AD16C4T_SLAVEMODE_GATED + @arg @ref MD_AD16C4T_SLAVEMODE_TRIGGER + @arg @ref MD_AD16C4T_SLAVEMODE_EXTERNALCLOCK + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_smcon_smods(AD16C4T_TypeDef *timx, uint32_t SlaveMode) +{ + MODIFY_REG(timx->SMCON, AD16C4T_SMCON_SMODS_MSK, SlaveMode); +} + +/** + * @brief Get timer slave mode selection. + * @param timx AD16C4T instance + * @retval Timer slave mode selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_smcon_smods(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->SMCON, AD16C4T_SMCON_SMODS_MSK) >> AD16C4T_SMCON_SMODS_POSS); +} + +/** + * @brief Timer IER setup. + * @param timx AD16C4T instance + * @param value (CH4OVI | CH3OVI | CH2OVI | CH1OVI | BRKI | TRGI | COMI | CH4I | CH3I | CH2I | CH1I | UI) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ier(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->IER, value); +} + +/** + * @brief Timer cpture/compare 4 overcapture interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ch4ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_CH4OVI_MSK); +} + +/** + * @brief Timer cpture/compare 3 overcapture interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ch3ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_CH3OVI_MSK); +} + +/** + * @brief Timer cpture/compare 2 overcapture interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ch2ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_CH2OVI_MSK); +} + +/** + * @brief Timer cpture/compare 1 overcapture interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ch1ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_CH1OVI_MSK); +} + +/** + * @brief Timer break interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_brki(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_BRKI_MSK); +} + +/** + * @brief Timer trigger interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_trgi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_TRGI_MSK); +} + +/** + * @brief Timer COM interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_comi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_COMI_MSK); +} + +/** + * @brief Timer capture/compare 4 interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ch4i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_CH4I_MSK); +} + +/** + * @brief Timer capture/compare 3 interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ch3i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_CH3I_MSK); +} + +/** + * @brief Timer capture/compare 2 interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ch2i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_CH2I_MSK); +} + +/** + * @brief Timer capture/compare 1 interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ch1i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_CH1I_MSK); +} + +/** + * @brief Timer update interrupt enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ier_ui(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IER, AD16C4T_IER_UI_MSK); +} + +/** + * @brief Timer IDR setup. + * @param timx AD16C4T instance + * @param value (CH4OVI | CH3OVI | CH2OVI | CH1OVI | BRKI | TRGI | COMI | CH4I | CH3I | CH2I | CH1I | UI) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_idr(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->IDR, value); +} + +/** + * @brief Timer cpture/compare 4 overcapture interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ch4ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_CH4OVI_MSK); +} + +/** + * @brief Timer cpture/compare 3 overcapture interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ch3ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_CH3OVI_MSK); +} + +/** + * @brief Timer cpture/compare 2 overcapture interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ch2ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_CH2OVI_MSK); +} + +/** + * @brief Timer cpture/compare 1 overcapture interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ch1ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_CH1OVI_MSK); +} + +/** + * @brief Timer break interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_brki(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_BRKI_MSK); +} + +/** + * @brief Timer trigger interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_trgi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_TRGI_MSK); +} + +/** + * @brief Timer COM interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_comi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_COMI_MSK); +} + +/** + * @brief Timer capture/compare 4 interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ch4i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_CH4I_MSK); +} + +/** + * @brief Timer capture/compare 3 interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ch3i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_CH3I_MSK); +} + +/** + * @brief Timer capture/compare 2 interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ch2i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_CH2I_MSK); +} + +/** + * @brief Timer capture/compare 1 interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ch1i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_CH1I_MSK); +} + +/** + * @brief Timer update interrupt disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_idr_ui(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->IDR, AD16C4T_IDR_UI_MSK); +} + +/** + * @brief Get timer IVS setup. + * @param timx AD16C4T instance + * @retval Timer IVS setup. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ivs(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->IVS)); +} + +/** + * @brief Indicates whether the timer capture/compare 4 overcapture interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch4ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_CH4OVI_MSK) == (AD16C4T_IVS_CH4OVI_MSK)); +} + +/** + * @brief Indicates whether the timer capture/compare 3 overcapture interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch3ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_CH3OVI_MSK) == (AD16C4T_IVS_CH3OVI_MSK)); +} + +/** + * @brief Indicates whether the timer cpture/compare 2 overcapture interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch2ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_CH2OVI_MSK) == (AD16C4T_IVS_CH2OVI_MSK)); +} + +/** + * @brief Indicates whether the timer capture/compare 1 overcapture interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch1ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_CH1OVI_MSK) == (AD16C4T_IVS_CH1OVI_MSK)); +} + +/** + * @brief Indicates whether the timer break interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_brki(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_BRKI_MSK) == (AD16C4T_IVS_BRKI_MSK)); +} + +/** + * @brief Indicates whether the timer trigger interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_trgi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_TRGI_MSK) == (AD16C4T_IVS_TRGI_MSK)); +} + +/** + * @brief Indicates whether the timer COM interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_comi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_COMI_MSK) == (AD16C4T_IVS_COMI_MSK)); +} + +/** + * @brief Indicates whether the timer Capture/Compare 4 interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch4i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_CH4I_MSK) == (AD16C4T_IVS_CH4I_MSK)); +} + +/** + * @brief Indicates whether the timer Capture/Compare 3 interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch3i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_CH3I_MSK) == (AD16C4T_IVS_CH3I_MSK)); +} + +/** + * @brief Indicates whether the timer Capture/Compare 2 interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch2i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_CH2I_MSK) == (AD16C4T_IVS_CH2I_MSK)); +} + +/** + * @brief Indicates whether the timer Capture/Compare 1 interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ch1i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_CH1I_MSK) == (AD16C4T_IVS_CH1I_MSK)); +} + +/** + * @brief Indicates whether the timer update interrupt is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ivs_ui(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IVS, AD16C4T_IVS_UI_MSK) == (AD16C4T_IVS_UI_MSK)); +} + +/** + * @brief Get timer RIF flag. + * @param timx AD16C4T instance + * @retval Timer RIF flag. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_rif(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->RIF)); +} + +/** + * @brief Get timer capture/compare 4 overcapture interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch4ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_CH4OVI_MSK) == (AD16C4T_RIF_CH4OVI_MSK)); +} + +/** + * @brief Get timer capture/compare 3 overcapture interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch3ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_CH3OVI_MSK) == (AD16C4T_RIF_CH3OVI_MSK)); +} + +/** + * @brief Get timer capture/compare 2 overcapture interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch2ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_CH2OVI_MSK) == (AD16C4T_RIF_CH2OVI_MSK)); +} + +/** + * @brief Get timer capture/compare 1 overcapture interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch1ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_CH1OVI_MSK) == (AD16C4T_RIF_CH1OVI_MSK)); +} + +/** + * @brief Get timer break interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_brki(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_BRKI_MSK) == (AD16C4T_RIF_BRKI_MSK)); +} + +/** + * @brief Get timer trigger interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_trgi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_TRGI_MSK) == (AD16C4T_RIF_TRGI_MSK)); +} + +/** + * @brief Get timer COM interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_comi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_COMI_MSK) == (AD16C4T_RIF_COMI_MSK)); +} + +/** + * @brief Get timer capture/compare 4 interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch4i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_CH4I_MSK) == (AD16C4T_RIF_CH4I_MSK)); +} + +/** + * @brief Get timer capture/compare 3 interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch3i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_CH3I_MSK) == (AD16C4T_RIF_CH3I_MSK)); +} + +/** + * @brief Get timer capture/compare 2 interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch2i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_CH2I_MSK) == (AD16C4T_RIF_CH2I_MSK)); +} + +/** + * @brief Get timer capture/compare 1 interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ch1i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_CH1I_MSK) == (AD16C4T_RIF_CH1I_MSK)); +} + +/** + * @brief Get timer update interrupt flag. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_rif_ui(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->RIF, AD16C4T_RIF_UI_MSK) == (AD16C4T_RIF_UI_MSK)); +} + +/** + * @brief Get timer IFM flag. + * @param timx AD16C4T instance + * @retval Timer IFM flag. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ifm(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->IFM)); +} + +/** + * @brief Get timer capture/compare 4 overcapture interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch4ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_CH4OVI_MSK) == (AD16C4T_IFM_CH4OVI_MSK)); +} + +/** + * @brief Get timer capture/compare 3 overcapture interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch3ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_CH3OVI_MSK) == (AD16C4T_IFM_CH3OVI_MSK)); +} + +/** + * @brief Get timer capture/compare 2 overcapture interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch2ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_CH2OVI_MSK) == (AD16C4T_IFM_CH2OVI_MSK)); +} + +/** + * @brief Get timer capture/compare 1 overcapture interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch1ovi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_CH1OVI_MSK) == (AD16C4T_IFM_CH1OVI_MSK)); +} + +/** + * @brief Get timer break interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_brki(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_BRKI_MSK) == (AD16C4T_IFM_BRKI_MSK)); +} + +/** + * @brief Get timer trigger interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_trgi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_TRGI_MSK) == (AD16C4T_IFM_TRGI_MSK)); +} + +/** + * @brief Get timer COM interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_comi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_COMI_MSK) == (AD16C4T_IFM_COMI_MSK)); +} + +/** + * @brief Get timer capture/compare 4 interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch4i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_CH4I_MSK) == (AD16C4T_IFM_CH4I_MSK)); +} + +/** + * @brief Get timer capture/compare 3 interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch3i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_CH3I_MSK) == (AD16C4T_IFM_CH3I_MSK)); +} + +/** + * @brief Get timer capture/compare 2 interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch2i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_CH2I_MSK) == (AD16C4T_IFM_CH2I_MSK)); +} + +/** + * @brief Get timer capture/compare 1 interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ch1i(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_CH1I_MSK) == (AD16C4T_IFM_CH1I_MSK)); +} + +/** + * @brief Get timer update interrupt flag masked. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_ad16c4t_is_active_flag_ifm_ui(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->IFM, AD16C4T_IFM_UI_MSK) == (AD16C4T_IFM_UI_MSK)); +} + +/** + * @brief Timer ICR setup. + * @param timx AD16C4T instance + * @param value (CC4OI | CC3OI | CC2OI | CC1OI | BI | TI | COMI | CC4I | CC3I | CC2I | CC1I | UI) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_icr(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->ICR, value); +} + +/** + * @brief Clear timer cpture/compare 4 overcapture interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch4ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_CH4OVI_MSK); +} + +/** + * @brief Clear timer cpture/compare 3 overcapture interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch3ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_CH3OVI_MSK); +} + +/** + * @brief Clear timer cpture/compare 2 overcapture interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch2ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_CH2OVI_MSK); +} + +/** + * @brief Clear timer cpture/compare 1 overcapture interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch1ovi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_CH1OVI_MSK); +} + +/** + * @brief Clear timer break interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_brki(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_BRKI_MSK); +} + +/** + * @brief Clear timer trigger interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_trgi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_TRGI_MSK); +} + +/** + * @brief Clear timer COM interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_comi(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_COMI_MSK); +} + +/** + * @brief Clear timer capture/compare 4 interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch4i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_CH4I_MSK); +} + +/** + * @brief Clear timer capture/compare 3 interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch3i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_CH3I_MSK); +} + +/** + * @brief Clear timer capture/compare 2 interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch2i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_CH2I_MSK); +} + +/** + * @brief Clear timer capture/compare 1 interrupt flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ch1i(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_CH1I_MSK); +} + +/** + * @brief Clear timer upadte flag. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_clear_flag_icr_ui(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->ICR, AD16C4T_ICR_UI_MSK); +} + +/** + * @brief Timer SGE setup. + * @param timx AD16C4T instance + * @param value (SGBRK | SGTRG | SGCOM | SGCH4 | SGCH3 | SGCH2 | SGCH1 | SGU) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->SGE, value); +} + +/** + * @brief Timer break generation. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge_sgbrk(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SGE, AD16C4T_SGE_SGBRK_MSK); +} + +/** + * @brief Timer trigger generation. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge_sgtrg(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SGE, AD16C4T_SGE_SGTRG_MSK); +} + +/** + * @brief Timer COM generation. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge_sgcom(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SGE, AD16C4T_SGE_SGCOM_MSK); +} + +/** + * @brief Timer Capture/Compare 4 generation. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge_sgch4(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SGE, AD16C4T_SGE_SGCH4_MSK); +} + +/** + * @brief Timer Capture/Compare 3 generation. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge_sgch3(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SGE, AD16C4T_SGE_SGCH3_MSK); +} + +/** + * @brief Timer Capture/Compare 2 generation. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge_sgch2(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SGE, AD16C4T_SGE_SGCH2_MSK); +} + +/** + * @brief Timer Capture/Compare 1 generation. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge_sgch1(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SGE, AD16C4T_SGE_SGCH1_MSK); +} + +/** + * @brief Timer update generation. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_sge_sgu(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->SGE, AD16C4T_SGE_SGU_MSK); +} + +/** + * @brief Timer CHMR1 setup. + * @param timx AD16C4T instance + * @param value output (CH2OCLREN | CH2MOD | CH2PEN | CH2FEN | CC2SSEL | CH1OCLREN | CH1MOD | CH1PEN | CH1FEN | CC1SSEL) + * input (I2FLT | I2PRES | CC2SSEL | I1FLT | I1PRES | CC1SSEL) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CHMR1, value); +} + +/** + * @brief GET Timer CHMR1 register value. + * @param timx AD16C4T instance + * @retval Timer CHMR1 register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CHMR1)); +} + +/** + * @brief Timer output compare 2 clear enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch2oclren(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2OCLREN_MSK); +} + +/** + * @brief Timer output compare 2 clear disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch2oclren(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2OCLREN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 2 clear is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch2oclren(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2OCLREN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH2OCLREN_MSK)); +} + +/** + * @brief Timer output compare 2 mode setup. + * @param timx AD16C4T instance + * @param OutputMode Output compare mode + @arg @ref MD_AD16C4T_OUTPUTMODE_DISABLE + @arg @ref MD_AD16C4T_OUTPUTMODE_HIGHONMSTCH + @arg @ref MD_AD16C4T_OUTPUTMODE_LOWONMSTCH + @arg @ref MD_AD16C4T_OUTPUTMODE_TOGGLE + @arg @ref MD_AD16C4T_OUTPUTMODE_FORCELOW + @arg @ref MD_AD16C4T_OUTPUTMODE_FORCEHIGH + @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE1 + @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE2 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_output_ch2mod(AD16C4T_TypeDef *timx, uint32_t OutputMode) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK, (OutputMode << AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS)); +} + +/** + * @brief Get timer output compare 2 mode. + * @param timx AD16C4T instance + * @retval Timer output compare 2 mode. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_output_ch2mod(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK) >> AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS); +} + +/** + * @brief Timer output compare 2 preload enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch2pen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2PEN_MSK); +} + +/** + * @brief Timer output compare 2 preload disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch2pen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2PEN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 2 preload is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch2pen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2PEN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH2PEN_MSK)); +} + +/** + * @brief Timer output compare 2 fast enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch2fen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2FEN_MSK); +} + +/** + * @brief Timer output compare 2 fast disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch2fen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2FEN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 2 fast is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch2fen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2FEN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH2FEN_MSK)); +} + +/** + * @brief Timer cpture/compare 2 selection setup. + * @param timx AD16C4T instance + * @param ChannelMode Channel mode selection + @arg @ref MD_AD16C4T_CHMODE_OUTPUT + @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_output_cc2ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CC2SSEL_MSK, (ChannelMode << AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 2 selection. + * @param timx AD16C4T instance + * @retval Timer cpture/compare 2 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_output_cc2ssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CC2SSEL_MSK) >> AD16C4T_CHMR1_OUTPUT_CC2SSEL_POSS); +} + +/** + * @brief Timer output compare 1 clear enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch1oclren(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1OCLREN_MSK); +} + +/** + * @brief Timer output compare 1 clear disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch1oclren(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1OCLREN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 1 clear is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch1oclren(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1OCLREN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH1OCLREN_MSK)); +} + +/** + * @brief Timer output compare 1 mode setup. + * @param timx AD16C4T instance + * @param OutputMode Output compare mode + @arg @ref MD_AD16C4T_OUTPUTMODE_DISABLE + @arg @ref MD_AD16C4T_OUTPUTMODE_HIGHONMSTCH + @arg @ref MD_AD16C4T_OUTPUTMODE_LOWONMSTCH + @arg @ref MD_AD16C4T_OUTPUTMODE_TOGGLE + @arg @ref MD_AD16C4T_OUTPUTMODE_FORCELOW + @arg @ref MD_AD16C4T_OUTPUTMODE_FORCEHIGH + @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE1 + @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE2 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_output_ch1mod(AD16C4T_TypeDef *timx, uint32_t OutputMode) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK, (OutputMode << AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS)); +} + +/** + * @brief Get timer output compare 1 mode. + * @param timx AD16C4T instance + * @retval Timer output compare 1 mode. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_output_ch1mod(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK) >> AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS); +} + +/** + * @brief Timer output compare 1 preload enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch1pen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1PEN_MSK); +} + +/** + * @brief Timer output compare 1 preload disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch1pen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1PEN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 1 preload is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch1pen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1PEN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH1PEN_MSK)); +} + +/** + * @brief Timer output compare 1 fast enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr1_output_ch1fen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1FEN_MSK); +} + +/** + * @brief Timer output compare 1 fast disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr1_output_ch1fen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1FEN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 1 fast is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr1_output_ch1fen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1FEN_MSK) == (AD16C4T_CHMR1_OUTPUT_CH1FEN_MSK)); +} + +/** + * @brief Timer cpture/compare 1 selection setup. + * @param timx AD16C4T instance + * @param ChannelMode Channel mode selection + @arg @ref MD_AD16C4T_CHMODE_OUTPUT + @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_output_cc1ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CC1SSEL_MSK, (ChannelMode << AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 1 selection. + * @param timx AD16C4T instance + * @retval Timer cpture/compare 1 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_output_cc1ssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_OUTPUT_CC1SSEL_MSK) >> AD16C4T_CHMR1_OUTPUT_CC1SSEL_POSS); +} + +/** + * @brief Timer input capture 2 filter setup. + * @param timx AD16C4T instance + * @param InputFliter Input capture filter + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N2 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N4 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N5 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N5 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_input_i2flt(AD16C4T_TypeDef *timx, uint32_t InputFliter) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_I2FLT_MSK, (InputFliter << AD16C4T_CHMR1_INPUT_I2FLT_POSS)); +} + +/** + * @brief Get timer input capture 2 filter. + * @param timx AD16C4T instance + * @retval Timer input capture 2 filter. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_i2flt(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_I2FLT_MSK) >> AD16C4T_CHMR1_INPUT_I2FLT_POSS); +} + +/** + * @brief Timer input capture 2 prescaler setup. + * @param timx AD16C4T instance + * @param InputPrescale Input capture prescaler + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV1 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV2 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV4 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_input_i2pres(AD16C4T_TypeDef *timx, uint32_t InputPrescale) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_I2PRES_MSK, (InputPrescale << AD16C4T_CHMR1_INPUT_I2PRES_POSS)); +} + +/** + * @brief Get timer input capture 2 prescaler. + * @param timx AD16C4T instance + * @retval Timer input capture 2 prescaler. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_i2pres(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_I2PRES_MSK) >> AD16C4T_CHMR1_INPUT_I2PRES_POSS); +} + +/** + * @brief Timer cpture/compare 2 selection setup. + * @param timx AD16C4T instance + * @param ChannelMode Channel mode selection + @arg @ref MD_AD16C4T_CHMODE_OUTPUT + @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_input_cc2ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_CC2SSEL_MSK, (ChannelMode << AD16C4T_CHMR1_INPUT_CC2SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 2 selection. + * @param timx AD16C4T instance + * @retval Timer cpture/compare 2 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_cc2ssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_CC2SSEL_MSK) >> AD16C4T_CHMR1_INPUT_CC2SSEL_POSS); +} + +/** + * @brief Timer input capture 1 filter setup. + * @param timx AD16C4T instance + * @param InputFliter Input capture filter + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N2 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N4 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N5 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N5 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_input_i1flt(AD16C4T_TypeDef *timx, uint32_t InputFliter) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_I1FLT_MSK, (InputFliter << AD16C4T_CHMR1_INPUT_I1FLT_POSS)); +} + +/** + * @brief Get timer input capture 1 filter. + * @param timx AD16C4T instance + * @retval Timer input capture 1 filter. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_i1flt(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_I1FLT_MSK) >> AD16C4T_CHMR1_INPUT_I1FLT_POSS); +} + +/** + * @brief Timer input capture 1 prescaler setup. + * @param timx AD16C4T instance + * @param InputPrescale Input capture prescaler + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV1 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV2 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV4 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_input_i1pres(AD16C4T_TypeDef *timx, uint32_t InputPrescale) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_I1PRES_MSK, (InputPrescale << AD16C4T_CHMR1_INPUT_I1PRES_POSS)); +} + +/** + * @brief Get timer input capture 1 prescaler. + * @param timx AD16C4T instance + * @retval Timer input capture 1 prescaler. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_i1pres(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_I1PRES_MSK) >> AD16C4T_CHMR1_INPUT_I1PRES_POSS); +} + +/** + * @brief Timer cpture/compare 1 selection setup. + * @param timx AD16C4T instance + * @param ChannelMode Channel mode selection + @arg @ref MD_AD16C4T_CHMODE_OUTPUT + @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr1_input_cc1ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR1, AD16C4T_CHMR1_INPUT_CC1SSEL_MSK, (ChannelMode << AD16C4T_CHMR1_INPUT_CC1SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 1 selection. + * @param timx AD16C4T instance + * @retval Timer cpture/compare 1 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr1_input_cc1ssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR1, AD16C4T_CHMR1_INPUT_CC1SSEL_MSK) >> AD16C4T_CHMR1_INPUT_CC1SSEL_POSS); +} + +/** + * @brief Timer CHMR2 setup. + + * @param timx AD16C4T instance + * @param value output (CH4OCLREN | CH4MOD | CH4PEN | CH4FEN | CC4SSEL | CH3OCLREN | CH3MOD | CH3PEN | CH3FEN | CC3SSEL) + * input (I4FLT | I4PRES | CC4SSEL | I3FLT | I3PRES | CC3SSEL) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CHMR2, value); +} + +/** + * @brief GET Timer CHMR2 register value. + * @param timx AD16C4T instance + * @retval Timer CHMR2 register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CHMR2)); +} + +/** + * @brief Timer output compare 4 clear enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch4oclren(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4OCLREN_MSK); +} + +/** + * @brief Timer output compare 4 clear disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch4oclren(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4OCLREN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 4 clear is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch4oclren(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4OCLREN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH4OCLREN_MSK)); +} + +/** + * @brief Timer output compare 4 mode setup. + * @param timx AD16C4T instance + * @param OutputMode Output compare mode + @arg @ref MD_AD16C4T_OUTPUTMODE_DISABLE + @arg @ref MD_AD16C4T_OUTPUTMODE_HIGHONMSTCH + @arg @ref MD_AD16C4T_OUTPUTMODE_LOWONMSTCH + @arg @ref MD_AD16C4T_OUTPUTMODE_TOGGLE + @arg @ref MD_AD16C4T_OUTPUTMODE_FORCELOW + @arg @ref MD_AD16C4T_OUTPUTMODE_FORCEHIGH + @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE1 + @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE2 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_output_ch4mod(AD16C4T_TypeDef *timx, uint32_t OutputMode) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4MOD_MSK, (OutputMode << AD16C4T_CHMR2_OUTPUT_CH4MOD_POSS)); +} + +/** + * @brief Get timer output compare 4 mode. + * @param timx AD16C4T instance + * @retval Timer output compare 4 mode. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_output_ch4mod(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4MOD_MSK) >> AD16C4T_CHMR2_OUTPUT_CH4MOD_POSS); +} + +/** + * @brief Timer output compare 4 preload enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch4pen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4PEN_MSK); +} + +/** + * @brief Timer output compare 4 preload disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch4pen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4PEN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 4 preload is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch4pen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4PEN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH4PEN_MSK)); +} + +/** + * @brief Timer output compare 4 fast enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch4fen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4FEN_MSK); +} + +/** + * @brief Timer output compare 4 fast disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch4fen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4FEN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 4 fast is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch4fen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH4FEN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH4FEN_MSK)); +} + +/** + * @brief Timer cpture/compare 4 selection setup. + * @param timx AD16C4T instance + * @param ChannelMode Channel mode selection + @arg @ref MD_AD16C4T_CHMODE_OUTPUT + @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_output_cc4ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CC4SSEL_MSK, (ChannelMode << AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 4 selection. + * @param timx AD16C4T instance + * @retval Timer cpture/compare 4 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_output_cc4ssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CC4SSEL_MSK) >> AD16C4T_CHMR2_OUTPUT_CC4SSEL_POSS); +} + +/** + * @brief Timer output compare 3 clear enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch3oclren(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3OCLREN_MSK); +} + +/** + * @brief Timer output compare 3 clear disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch3oclren(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3OCLREN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 3 clear is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch3oclren(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3OCLREN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH3OCLREN_MSK)); +} + +/** + * @brief Timer output compare 3 mode setup. + * @param timx AD16C4T instance + * @param OutputMode Output compare mode + @arg @ref MD_AD16C4T_OUTPUTMODE_DISABLE + @arg @ref MD_AD16C4T_OUTPUTMODE_HIGHONMSTCH + @arg @ref MD_AD16C4T_OUTPUTMODE_LOWONMSTCH + @arg @ref MD_AD16C4T_OUTPUTMODE_TOGGLE + @arg @ref MD_AD16C4T_OUTPUTMODE_FORCELOW + @arg @ref MD_AD16C4T_OUTPUTMODE_FORCEHIGH + @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE1 + @arg @ref MD_AD16C4T_OUTPUTMODE_PWMMODE2 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_output_ch3mod(AD16C4T_TypeDef *timx, uint32_t OutputMode) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3MOD_MSK, (OutputMode << AD16C4T_CHMR2_OUTPUT_CH3MOD_POSS)); +} + +/** + * @brief Get timer output compare 3 mode. + * @param timx AD16C4T instance + * @retval Timer output compare 3 mode. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_output_ch3mod(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3MOD_MSK) >> AD16C4T_CHMR2_OUTPUT_CH3MOD_POSS); +} + +/** + * @brief Timer output compare 3 preload enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch3pen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3PEN_MSK); +} + +/** + * @brief Timer output compare 3 preload disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch3pen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3PEN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 3 preload is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch3pen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3PEN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH3PEN_MSK)); +} + +/** + * @brief Timer output compare 3 fast enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_chmr2_output_ch3fen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3FEN_MSK); +} + +/** + * @brief Timer output compare 3 fast disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_chmr2_output_ch3fen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3FEN_MSK); +} + +/** + * @brief Indicates whether the timer output compare 3 fast is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_chmr2_output_ch3fen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CH3FEN_MSK) == (AD16C4T_CHMR2_OUTPUT_CH3FEN_MSK)); +} + +/** + * @brief Timer cpture/compare 3 selection setup. + * @param timx AD16C4T instance + * @param ChannelMode Channel mode selection + @arg @ref MD_AD16C4T_CHMODE_OUTPUT + @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_output_cc3ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CC3SSEL_MSK, (ChannelMode << AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 3 selection. + * @param timx AD16C4T instance + * @retval Timer cpture/compare 3 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_output_cc3ssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_OUTPUT_CC3SSEL_MSK) >> AD16C4T_CHMR2_OUTPUT_CC3SSEL_POSS); +} + +/** + * @brief Timer input capture 4 filter setup. + * @param timx AD16C4T instance + * @param InputFliter Input capture filter + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N2 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N4 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N5 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N5 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_input_i4flt(AD16C4T_TypeDef *timx, uint32_t InputFliter) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_I4FLT_MSK, (InputFliter << AD16C4T_CHMR2_INPUT_I4FLT_POSS)); +} + +/** + * @brief Get timer input capture 4 filter. + * @param timx AD16C4T instance + * @retval Timer input capture 4 filter. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_i4flt(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_I4FLT_MSK) >> AD16C4T_CHMR2_INPUT_I4FLT_POSS); +} + +/** + * @brief Timer input capture 4 prescaler setup. + * @param timx AD16C4T instance + * @param InputPrescale Input capture prescaler + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV1 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV2 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV4 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_input_i4pres(AD16C4T_TypeDef *timx, uint32_t InputPrescale) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_I4PRES_MSK, (InputPrescale << AD16C4T_CHMR2_INPUT_I4PRES_POSS)); +} + +/** + * @brief Get timer input capture 4 prescaler. + * @param timx AD16C4T instance + * @retval Timer input capture 4 prescaler. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_i4pres(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_I4PRES_MSK) >> AD16C4T_CHMR2_INPUT_I4PRES_POSS); +} + +/** + * @brief Timer cpture/compare 4 selection setup. + * @param timx AD16C4T instance + * @param ChannelMode Channel mode selection + @arg @ref MD_AD16C4T_CHMODE_OUTPUT + @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_input_cc4ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_CC4SSEL_MSK, (ChannelMode << AD16C4T_CHMR2_INPUT_CC4SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 4 selection. + * @param timx AD16C4T instance + * @retval Timer cpture/compare 4 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_cc4ssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_CC4SSEL_MSK) >> AD16C4T_CHMR2_INPUT_CC4SSEL_POSS); +} + +/** + * @brief Timer input capture 3 filter setup. + * @param timx AD16C4T instance + * @param InputFliter Input capture filter + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N2 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N4 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV1N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV2N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV4N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV8N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N5 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV16N8 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N5 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N6 + @arg @ref MD_AD16C4T_INPUTFILTER_FDIV32N8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_input_i3flt(AD16C4T_TypeDef *timx, uint32_t InputFliter) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_I3FLT_MSK, (InputFliter << AD16C4T_CHMR2_INPUT_I3FLT_POSS)); +} + +/** + * @brief Get timer input capture 3 filter. + * @param timx AD16C4T instance + * @retval Timer input capture 3 filter. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_i3flt(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_I3FLT_MSK) >> AD16C4T_CHMR2_INPUT_I3FLT_POSS); +} + +/** + * @brief Timer input capture 3 prescaler setup. + * @param timx AD16C4T instance + * @param InputPrescale Input capture prescaler + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV1 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV2 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV4 + @arg @ref MD_AD16C4T_INPUTPRESCALE_DIV8 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_input_i3pres(AD16C4T_TypeDef *timx, uint32_t InputPrescale) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_I3PRES_MSK, (InputPrescale << AD16C4T_CHMR2_INPUT_I3PRES_POSS)); +} + +/** + * @brief Get timer input capture 3 prescaler. + * @param timx AD16C4T instance + * @retval Timer input capture 3 prescaler. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_i3pres(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_I3PRES_MSK) >> AD16C4T_CHMR2_INPUT_I3PRES_POSS); +} + +/** + * @brief Timer cpture/compare 3 selection setup. + * @param timx AD16C4T instance + * @param ChannelMode Channel mode selection + @arg @ref MD_AD16C4T_CHMODE_OUTPUT + @arg @ref MD_AD16C4T_CHMODE_INPUT_DIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_INDIRECT + @arg @ref MD_AD16C4T_CHMODE_INPUT_TRC + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_chmr2_input_cc3ssel(AD16C4T_TypeDef *timx, uint32_t ChannelMode) +{ + MODIFY_REG(timx->CHMR2, AD16C4T_CHMR2_INPUT_CC3SSEL_MSK, (ChannelMode << AD16C4T_CHMR2_INPUT_CC3SSEL_POSS)); +} + +/** + * @brief Get timer cpture/compare 3 selection. + * @param timx AD16C4T instance + * @retval Timer cpture/compare 3 selection. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_chmr2_input_cc3ssel(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CHMR2, AD16C4T_CHMR2_INPUT_CC3SSEL_MSK) >> AD16C4T_CHMR2_INPUT_CC3SSEL_POSS); +} + +/** + * @brief Timer CCEP setup. + * @param timx AD16C4T instance + * @param value (CC4NPOL | CC4POL | CC4EN | CC3NPOL | CC3NEN | CC3POL | CC3EN | CC2NPOL | + * CC2NEN | CC2POL | CC2EN | CC1NPOL | CC1NEN | CC1POL | CC1EN ) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CCEP, value); +} + +/** + * @brief GET Timer CCEP register value. + * @param timx AD16C4T instance + * @retval Timer CCEP register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CCEP)); +} + +/** + * @brief Timer capture/compare 4 complementary output polarity setup. + * @param timx AD16C4T instance + * @param OutputPolarity Output polarity + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep_cc4npol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC4NPOL_MSK, (OutputPolarity << AD16C4T_CCEP_CC4NPOL_POS)); +} + +/** + * @brief Get timer capture/compare 4 complementary output polarity. + * @param timx AD16C4T instance + * @retval Timer capture/compare 4 complementary output polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc4npol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC4NPOL_MSK) >> AD16C4T_CCEP_CC4NPOL_POS); +} + +/** + * @brief Timer capture/compare 4 output polarity setup. + * @param timx AD16C4T instance + * @param OutputPolarity Output polarity + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep_cc4pol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC4POL_MSK, (OutputPolarity << AD16C4T_CCEP_CC4POL_POS)); +} + +/** + * @brief Get timer capture/compare 4 output polarity. + * @param timx AD16C4T instance + * @retval Timer capture/compare 4 output polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc4pol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC4POL_MSK) >> AD16C4T_CCEP_CC4POL_POS); +} + +/** + * @brief Timer Capture/Compare 4 output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ccep_cc4en(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CCEP, AD16C4T_CCEP_CC4EN_MSK); +} + +/** + * @brief Timer Capture/Compare 4 output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_ccep_cc4en(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC4EN_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 4 output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc4en(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC4EN_MSK) == (AD16C4T_CCEP_CC4EN_MSK)); +} + +/** + * @brief Timer capture/compare 3 complementary output polarity setup. + * @param timx AD16C4T instance + * @param OutputPolarity Output polarity + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep_cc3npol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC3NPOL_MSK, (OutputPolarity << AD16C4T_CCEP_CC3NPOL_POS)); +} + +/** + * @brief Get timer capture/compare 3 complementary output polarity. + * @param timx AD16C4T instance + * @retval Timer capture/compare 3 complementary output polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc3npol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC3NPOL_MSK) >> AD16C4T_CCEP_CC3NPOL_POS); +} + +/** + * @brief Timer Capture/Compare 3 complementary output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ccep_cc3nen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CCEP, AD16C4T_CCEP_CC3NEN_MSK); +} + +/** + * @brief Timer Capture/Compare 3 complementary output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_ccep_cc3nen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC3NEN_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 3 complementary output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc3nen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC3NEN_MSK) == (AD16C4T_CCEP_CC3NEN_MSK)); +} + +/** + * @brief Timer capture/compare 3 output polarity setup. + * @param timx AD16C4T instance + * @param OutputPolarity Output polarity + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep_cc3pol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC3POL_MSK, (OutputPolarity << AD16C4T_CCEP_CC3POL_POS)); +} + +/** + * @brief Get timer capture/compare 3 output polarity. + * @param timx AD16C4T instance + * @retval Timer capture/compare 3 output polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc3pol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC3POL_MSK) >> AD16C4T_CCEP_CC3POL_POS); +} + +/** + * @brief Timer Capture/Compare 3 output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ccep_cc3en(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CCEP, AD16C4T_CCEP_CC3EN_MSK); +} + +/** + * @brief Timer Capture/Compare 3 output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_ccep_cc3en(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC3EN_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 3 output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc3en(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC3EN_MSK) == (AD16C4T_CCEP_CC3EN_MSK)); +} + +/** + * @brief Timer capture/compare 2 complementary output polarity setup. + * @param timx AD16C4T instance + * @param OutputPolarity Output polarity + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep_cc2npol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC2NPOL_MSK, (OutputPolarity << AD16C4T_CCEP_CC2NPOL_POS)); +} + +/** + * @brief Get timer capture/compare 2 complementary output polarity. + * @param timx AD16C4T instance + * @retval Timer capture/compare 2 complementary output polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc2npol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC2NPOL_MSK) >> AD16C4T_CCEP_CC2NPOL_POS); +} + +/** + * @brief Timer Capture/Compare 2 complementary output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ccep_cc2nen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CCEP, AD16C4T_CCEP_CC2NEN_MSK); +} + +/** + * @brief Timer Capture/Compare 2 complementary output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_ccep_cc2nen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC2NEN_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 2 complementary output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc2nen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC2NEN_MSK) == (AD16C4T_CCEP_CC2NEN_MSK)); +} + +/** + * @brief Timer capture/compare 2 output polarity setup. + * @param timx AD16C4T instance + * @param OutputPolarity Output polarity + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep_cc2pol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC2POL_MSK, (OutputPolarity << AD16C4T_CCEP_CC2POL_POS)); +} + +/** + * @brief Get timer capture/compare 2 output polarity. + * @param timx AD16C4T instance + * @retval Timer capture/compare 2 output polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc2pol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC2POL_MSK) >> AD16C4T_CCEP_CC2POL_POS); +} + +/** + * @brief Timer Capture/Compare 2 output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ccep_cc2en(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CCEP, AD16C4T_CCEP_CC2EN_MSK); +} + +/** + * @brief Timer Capture/Compare 2 output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_ccep_cc2en(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC2EN_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 2 output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc2en(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC2EN_MSK) == (AD16C4T_CCEP_CC2EN_MSK)); +} + +/** + * @brief Timer capture/compare 1 complementary output polarity setup. + * @param timx AD16C4T instance + * @param OutputPolarity Output polarity + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep_cc1npol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC1NPOL_MSK, (OutputPolarity << AD16C4T_CCEP_CC1NPOL_POS)); +} + +/** + * @brief Get timer capture/compare 1 complementary output polarity. + * @param timx AD16C4T instance + * @retval Timer capture/compare 1 complementary output polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc1npol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC1NPOL_MSK) >> AD16C4T_CCEP_CC1NPOL_POS); +} + +/** + * @brief Timer Capture/Compare 1 complementary output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ccep_cc1nen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CCEP, AD16C4T_CCEP_CC1NEN_MSK); +} + +/** + * @brief Timer Capture/Compare 1 complementary output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_ccep_cc1nen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC1NEN_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 1 complementary output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc1nen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC1NEN_MSK) == (AD16C4T_CCEP_CC1NEN_MSK)); +} + +/** + * @brief Timer capture/compare 1 output polarity setup. + * @param timx AD16C4T instance + * @param OutputPolarity Output polarity + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_HIGH + @arg @ref MD_AD16C4T_OUTPUTPOLARITY_LOW + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccep_cc1pol(AD16C4T_TypeDef *timx, uint32_t OutputPolarity) +{ + MODIFY_REG(timx->CCEP, AD16C4T_CCEP_CC1POL_MSK, (OutputPolarity << AD16C4T_CCEP_CC1POL_POS)); +} + +/** + * @brief Get timer capture/compare 1 output polarity. + * @param timx AD16C4T instance + * @retval Timer capture/compare 1 output polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccep_cc1pol(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC1POL_MSK) >> AD16C4T_CCEP_CC1POL_POS); +} + +/** + * @brief Timer Capture/Compare 1 output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_ccep_cc1en(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->CCEP, AD16C4T_CCEP_CC1EN_MSK); +} + +/** + * @brief Timer Capture/Compare 1 output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_ccep_cc1en(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->CCEP, AD16C4T_CCEP_CC1EN_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 1 output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_ccep_cc1en(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCEP, AD16C4T_CCEP_CC1EN_MSK) == (AD16C4T_CCEP_CC1EN_MSK)); +} + +/** + * @brief Timer COUNT setup. + * @param timx AD16C4T instance + * @param value COUNT + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_count(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->COUNT, value); +} + +/** + * @brief GET Timer COUNT register value. + * @param timx AD16C4T instance + * @retval Timer COUNT register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_count(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->COUNT)); +} + +/** + * @brief Timer counter value setup. + * @param timx AD16C4T instance + * @param counter Counter value (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_count_cntv(AD16C4T_TypeDef *timx, uint32_t counter) +{ + MODIFY_REG(timx->COUNT, AD16C4T_COUNT_CNTV_MSK, counter); +} + +/** + * @brief Get timer counter value. + * @param timx AD16C4T instance + * @retval Timer counter value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_cnt_cntv(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->COUNT, AD16C4T_COUNT_CNTV_MSK) >> AD16C4T_COUNT_CNTV_POSS); +} + +/** + * @brief Timer PRES setup. + * @param timx AD16C4T instance + * @param value PRES + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_pres(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->PRES, value); +} + +/** + * @brief GET Timer PRES register value. + * @param timx AD16C4T instance + * @retval Timer PRES register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_pres(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->PRES)); +} + +/** + * @brief Timer prescaler value setup. + * @param timx AD16C4T instance + * @param prescaler Prescaler value (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_pres_pscv(AD16C4T_TypeDef *timx, uint32_t prescaler) +{ + MODIFY_REG(timx->PRES, AD16C4T_PRES_PSCV_MSK, prescaler); +} + +/** + * @brief Get timer prescaler value. + * @param timx AD16C4T instance + * @retval Timer prescaler value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_pres_pscv(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->PRES, AD16C4T_PRES_PSCV_MSK) >> AD16C4T_PRES_PSCV_POSS); +} + +/** + * @brief Timer AR setup. + * @param timx AD16C4T instance + * @param value AR + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ar(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->AR, value); +} + +/** + * @brief GET Timer AR register value. + * @param timx AD16C4T instance + * @retval Timer AR register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ar(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->AR)); +} + +/** + * @brief Timer auto-reload value setup. + * @param timx AD16C4T instance + * @param reload Auto-reload value (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ar_arv(AD16C4T_TypeDef *timx, uint32_t reload) +{ + MODIFY_REG(timx->AR, AD16C4T_AR_ARV_MSK, reload); +} + +/** + * @brief Get timer auto-reload value. + * @param timx AD16C4T instance + * @retval Timer auto-reload value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ar_arv(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->AR, AD16C4T_AR_ARV_MSK) >> AD16C4T_AR_ARV_POSS); +} + +/** + * @brief Timer REPAR setup. + * @param timx AD16C4T instance + * @param value REPAR + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_rcr(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->REPAR, value); +} + +/** + * @brief GET Timer REPAR register value. + * @param timx AD16C4T instance + * @retval Timer REPAR register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_repar(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->REPAR)); +} + +/** + * @brief Timer repetition counter value setup. + * @param timx AD16C4T instance + * @param repetition Repetition counter value (between Min_Data=0 and Max_Data=0xFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_repar_repv(AD16C4T_TypeDef *timx, uint32_t repetition) +{ + MODIFY_REG(timx->REPAR, AD16C4T_REPAR_REPV_MSK, repetition); +} + +/** + * @brief Get timer repetition counter value. + * @param timx AD16C4T instance + * @retval Timer repetition counter value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_repar_repv(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->REPAR, AD16C4T_REPAR_REPV_MSK) >> AD16C4T_REPAR_REPV_POSS); +} + +/** + * @brief Timer CCVAL1 setup. + * @param timx AD16C4T instance + * @param value CCVAL1 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccval1(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CCVAL1, value); +} + +/** + * @brief GET Timer CCVAL1 register value. + * @param timx AD16C4T instance + * @retval Timer CCVAL1 register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccval1(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CCVAL1)); +} + +/** + * @brief Timer capture/compare value 1 setup. + * @param timx AD16C4T instance + * @param CapCompValue Capture/Compare value 1 (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccval1_ccrv1(AD16C4T_TypeDef *timx, uint32_t CapCompValue) +{ + MODIFY_REG(timx->CCVAL1, AD16C4T_CCVAL1_CCRV1_MSK, CapCompValue); +} + +/** + * @brief Get timer capture/compare value 1. + * @param timx AD16C4T instance + * @retval Timer capture/compare value 1. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccval1_ccrv1(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCVAL1, AD16C4T_CCVAL1_CCRV1_MSK) >> AD16C4T_CCVAL1_CCRV1_POSS); +} + +/** + * @brief Timer CCVAL2 setup. + * @param timx AD16C4T instance + * @param value CCVAL2 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccval2(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CCVAL2, value); +} + +/** + * @brief GET Timer CCVAL2 register value. + * @param timx AD16C4T instance + * @retval Timer CCVAL2 register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccval2(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CCVAL2)); +} + +/** + * @brief Timer capture/compare value 2 setup. + * @param timx AD16C4T instance + * @param CapCompValue Capture/Compare value 2 (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccval2_ccrv2(AD16C4T_TypeDef *timx, uint32_t CapCompValue) +{ + MODIFY_REG(timx->CCVAL2, AD16C4T_CCVAL2_CCRV2_MSK, CapCompValue); +} + +/** + * @brief Get timer capture/compare value 2. + * @param timx AD16C4T instance + * @retval Timer capture/compare value 2. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccval2_ccrv2(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCVAL2, AD16C4T_CCVAL2_CCRV2_MSK) >> AD16C4T_CCVAL2_CCRV2_POSS); +} + +/** + * @brief Timer CCVAL3 setup. + * @param timx AD16C4T instance + * @param value CCVAL3 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccval3(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CCVAL3, value); +} + +/** + * @brief GET Timer CCVAL3 register value. + * @param timx AD16C4T instance + * @retval Timer CCVAL3 register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccval3(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CCVAL3)); +} + +/** + * @brief Timer capture/compare value 3 setup. + * @param timx AD16C4T instance + * @param CapCompValue Capture/Compare value 3 (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccval3_ccrv3(AD16C4T_TypeDef *timx, uint32_t CapCompValue) +{ + MODIFY_REG(timx->CCVAL3, AD16C4T_CCVAL3_CCRV3_MSK, CapCompValue); +} + +/** + * @brief Get timer capture/compare value 3. + * @param timx AD16C4T instance + * @retval Timer capture/compare value 3. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccval3_ccrv3(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCVAL3, AD16C4T_CCVAL3_CCRV3_MSK) >> AD16C4T_CCVAL3_CCRV3_POSS); +} + +/** + * @brief Timer CCVAL4 setup. + * @param timx AD16C4T instance + * @param value CCVAL4 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccval4(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->CCVAL4, value); +} + +/** + * @brief GET Timer CCVAL4 register value. + * @param timx AD16C4T instance + * @retval Timer CCVAL4 register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccval4(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->CCVAL4)); +} + +/** + * @brief Timer capture/compare value 4 setup. + * @param timx AD16C4T instance + * @param CapCompValue Capture/Compare value 4 (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_ccval4_ccrv4(AD16C4T_TypeDef *timx, uint32_t CapCompValue) +{ + MODIFY_REG(timx->CCVAL4, AD16C4T_CCVAL4_CCRV4_MSK, CapCompValue); +} + +/** + * @brief Get timer capture/compare value 4. + * @param timx AD16C4T instance + * @retval Timer capture/compare value 4. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_ccval4_ccrv4(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->CCVAL4, AD16C4T_CCVAL4_CCRV4_MSK) >> AD16C4T_CCVAL4_CCRV4_POSS); +} + +/** + * @brief Timer BDCFG setup. + * @param timx AD16C4T instance + * @param value (GOEN | AOEN | BRKP | BRKEN | OFFSSR | OFFSSI | LOCKLVL | DT) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_bdcfg(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->BDCFG, value); +} + +/** + * @brief GET Timer BDCFG register value. + * @param timx AD16C4T instance + * @retval Timer BDCFG register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->BDCFG)); +} + +/** + * @brief Timer main output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_bdcfg_goen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->BDCFG, AD16C4T_BDCFG_GOEN_MSK); +} + +/** + * @brief Timer main output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_bdcfg_goen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->BDCFG, AD16C4T_BDCFG_GOEN_MSK); +} + +/** + * @brief Indicates whether the timer main output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_bdcfg_goen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_GOEN_MSK) == (AD16C4T_BDCFG_GOEN_MSK)); +} + +/** + * @brief Timer automatic output enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_bdcfg_aoen(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->BDCFG, AD16C4T_BDCFG_AOEN_MSK); +} + +/** + * @brief Timer automatic output disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_bdcfg_aoen(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->BDCFG, AD16C4T_BDCFG_AOEN_MSK); +} + +/** + * @brief Indicates whether the timer automatic output is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_bdcfg_aoen(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_AOEN_MSK) == (AD16C4T_BDCFG_AOEN_MSK)); +} + +/** + * @brief Timer break polarity setup. + * @param timx AD16C4T instance + * @param BreakPolarity Break polarity + * @arg @ref MD_AD16C4T_BREAKPOLARITY_LOW + * @arg @ref MD_AD16C4T_BREAKPOLARITY_HIGH + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_bdcfg_brkp(AD16C4T_TypeDef *timx, uint32_t BreakPolarity) +{ + MODIFY_REG(timx->BDCFG, AD16C4T_BDCFG_BRKP_MSK, BreakPolarity); +} + +/** + * @brief Get timer break polarity. + * @param timx AD16C4T instance + * @retval Timer break polarity. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg_brkp(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_BRKP_MSK) >> AD16C4T_BDCFG_BRKP_POS); +} + +/** + * @brief Timer break enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_bdcfg_brken(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->BDCFG, AD16C4T_BDCFG_BRKEN_MSK); +} + +/** + * @brief Timer break disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_bdcfg_brken(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->BDCFG, AD16C4T_BDCFG_BRKEN_MSK); +} + +/** + * @brief Indicates whether the timer break is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_bdcfg_brken(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_BRKEN_MSK) == (AD16C4T_BDCFG_BRKEN_MSK)); +} + +/** + * @brief Timer off-state selection for run mode setup. + * @param timx AD16C4T instance + * @param OffStateRun Off-state selection for run mode + * @arg @ref MD_AD16C4T_OFFSTATERUN_DISABLE + * @arg @ref MD_AD16C4T_OFFSTATERUN_ENABLE + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_bdcfg_offssr(AD16C4T_TypeDef *timx, uint32_t OffStateRun) +{ + MODIFY_REG(timx->BDCFG, AD16C4T_BDCFG_OFFSSR_MSK, OffStateRun); +} + +/** + * @brief Get timer off-state selection for run mode. + * @param timx AD16C4T instance + * @retval Timer off-state selection for run mode. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg_offssr(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_OFFSSR_MSK) >> AD16C4T_BDCFG_OFFSSR_POS); +} + +/** + * @brief Timer off-state selection for idle mode setup. + * @param timx AD16C4T instance + * @param OffStateIdle Off-state selection for idle mode + * @arg @ref MD_AD16C4T_OFFSTATEIDLE_DISABLE + * @arg @ref MD_AD16C4T_OFFSTATEIDLE_ENABLE + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_bdcfg_offssi(AD16C4T_TypeDef *timx, uint32_t OffStateIdle) +{ + MODIFY_REG(timx->BDCFG, AD16C4T_BDCFG_OFFSSI_MSK, OffStateIdle); +} + +/** + * @brief Get timer off-state selection for idle mode. + * @param timx AD16C4T instance + * @retval Timer off-state selection for idle mode. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg_offssi(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_OFFSSI_MSK) >> AD16C4T_BDCFG_OFFSSI_POS); +} + +/** + * @brief Timer lock configuration setup. + * @param timx AD16C4T instance + * @param LockLevel Lock configuration + * @arg @ref MD_AD16C4T_LOCKLEVEL_0 + * @arg @ref MD_AD16C4T_LOCKLEVEL_1 + * @arg @ref MD_AD16C4T_LOCKLEVEL_2 + * @arg @ref MD_AD16C4T_LOCKLEVEL_3 + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_bdcfg_locklvl(AD16C4T_TypeDef *timx, uint32_t LockLevel) +{ + MODIFY_REG(timx->BDCFG, AD16C4T_BDCFG_LOCKLVL_MSK, LockLevel); +} + +/** + * @brief Get timer lock configuration. + * @param timx AD16C4T instance + * @retval Timer lock configuration. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg_locklvl(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_LOCKLVL_MSK) >> AD16C4T_BDCFG_LOCKLVL_POSS); +} + +/** + * @brief Timer dead-time generator setup. + * @param timx AD16C4T instance + * @param DeadTime Dead-time generator (between Min_Data=0 and Max_Data=0xFF) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_bdcfg_dt(AD16C4T_TypeDef *timx, uint32_t DeadTime) +{ + MODIFY_REG(timx->BDCFG, AD16C4T_BDCFG_DT_MSK, DeadTime); +} + +/** + * @brief Get timer dead-time generator. + * @param timx AD16C4T instance + * @retval Timer dead-time generator. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_bdcfg_dt(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->BDCFG, AD16C4T_BDCFG_DT_MSK) >> AD16C4T_BDCFG_DT_POSS); +} + +/** + * @brief Timer DMAEN setup. + * @param timx AD16C4T instance + * @param value (TRGIDE | COMDE | CH4DE | CH3DE | CH2DE | CH1DE | UDE) + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_set_dmaen(AD16C4T_TypeDef *timx, uint32_t value) +{ + WRITE_REG(timx->DMAEN, value); +} + +/** + * @brief GET Timer DMAEN register value. + * @param timx AD16C4T instance + * @retval Timer DMAEN register value. + */ + +__STATIC_INLINE uint32_t md_ad16c4t_get_dmaen(AD16C4T_TypeDef *timx) +{ + return (READ_REG(timx->DMAEN)); +} + +/** + * @brief Timer trigger DMA request enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_dmaen_trgide(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, AD16C4T_DMAEN_TRGIDE_MSK); +} + +/** + * @brief Timer trigger DMA request disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_dmaen_trgide(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_TRGIDE_MSK); +} + +/** + * @brief Indicates whether the timer trigger DMA request is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_trgide(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_TRGIDE_MSK) == (AD16C4T_DMAEN_TRGIDE_MSK)); +} + +/** + * @brief Timer COM DMA request enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_dmaen_comde(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, AD16C4T_DMAEN_COMDE_MSK); +} + +/** + * @brief Timer COM DMA request disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_dmaen_comde(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_COMDE_MSK); +} + +/** + * @brief Indicates whether the timer trigger COM request is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_comde(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_COMDE_MSK) == (AD16C4T_DMAEN_COMDE_MSK)); +} + +/** + * @brief Timer Capture/Compare 4 DMA request enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_dmaen_ch4de(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, AD16C4T_DMAEN_CH4DE_MSK); +} + +/** + * @brief Timer Capture/Compare 4 DMA request disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_dmaen_ch4de(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_CH4DE_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 4 DMA request is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_ch4de(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_CH4DE_MSK) == (AD16C4T_DMAEN_CH4DE_MSK)); +} + +/** + * @brief Timer Capture/Compare 3 DMA request enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_dmaen_ch3de(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, AD16C4T_DMAEN_CH3DE_MSK); +} + +/** + * @brief Timer Capture/Compare 3 DMA request disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_dmaen_ch3de(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_CH3DE_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 3 DMA request is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_ch3de(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_CH3DE_MSK) == (AD16C4T_DMAEN_CH3DE_MSK)); +} + +/** + * @brief Timer Capture/Compare 2 DMA request enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_dmaen_ch2de(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, AD16C4T_DMAEN_CH2DE_MSK); +} + +/** + * @brief Timer Capture/Compare 2 DMA request disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_dmaen_ch2de(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_CH2DE_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 2 DMA request is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_ch2de(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_CH2DE_MSK) == (AD16C4T_DMAEN_CH2DE_MSK)); +} + +/** + * @brief Timer Capture/Compare 1 DMA request enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_dmaen_ch1de(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, AD16C4T_DMAEN_CH1DE_MSK); +} + +/** + * @brief Timer Capture/Compare 1 DMA request disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_dmaen_ch1de(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_CH1DE_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare 1 DMA request is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_ch1de(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_CH1DE_MSK) == (AD16C4T_DMAEN_CH1DE_MSK)); +} + +/** + * @brief Timer update DMA request enable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_enable_dmaen_ude(AD16C4T_TypeDef *timx) +{ + SET_BIT(timx->DMAEN, AD16C4T_DMAEN_UDE_MSK); +} + +/** + * @brief Timer update DMA request disable. + * @param timx AD16C4T instance + * @retval None + */ + +__STATIC_INLINE void md_ad16c4t_disable_dmaen_ude(AD16C4T_TypeDef *timx) +{ + CLEAR_BIT(timx->DMAEN, AD16C4T_DMAEN_UDE_MSK); +} + +/** + * @brief Indicates whether the timer Capture/Compare update DMA request is enabled. + * @param timx AD16C4T instance + * @retval State of bit (1 or 0). + */ + +__STATIC_INLINE uint32_t md_ad16c4t_is_enabled_dmaen_ude(AD16C4T_TypeDef *timx) +{ + return (READ_BIT(timx->DMAEN, AD16C4T_DMAEN_UDE_MSK) == (AD16C4T_DMAEN_UDE_MSK)); +} +/** + * @} MD_AD16C4T_Public_Macro + */ + +/* Public functions -----------------------------------------------------------*/ + + + +/** + * @} AD16C4T + */ + + +#endif + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_adc.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..3c3bdbc5f85bd817163d23908de1b3a97c8abc1a --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_adc.h @@ -0,0 +1,6109 @@ +/** + ****************************************************************************** + * @file md_ADC.h + * @brief ES32F0271 ADC Header File. + * + * @version V1.00.01 + * @date 04/12/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_ADC_H__ +#define __MD_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_adc.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined ADC + +/** @defgroup ADC ADC + * @brief ADC micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Public types ---------------------------------------------------------------*/ +/* Public constants -----------------------------------------------------------*/ +/* Public functions -----------------------------------------------------------*/ + +/** @defgroup MD_ADC_Public_Constants ADC Public Constants + * @{ + */ + +/** + * @brief ADC Init structure. + */ +typedef struct +{ + uint8_t VRLS; + uint8_t SSx; + uint32_t Sel; + uint32_t Type; + uint32_t Cntini; + uint32_t Cnt; + uint8_t End; + uint8_t Ckdiv; +} md_adc_inittypedef; +/** @defgroup MD_ADC_CFG ADC_CFG Register + * @{ + */ +#define MD_ADC_CFG_TESTEN (0xEDU) /** @brief data ADC Test Enable */ + +#define MD_ADC_CFG_MODE_NORMAL (0x00000000U<CFG, ADC_CFG_TESTEN_MSK, MD_ADC_CFG_TESTEN<CFG, ADC_CFG_MODE_MSK, Mode<CFG, ADC_CFG_MODE_MSK))>>ADC_CFG_MODE_POS); +} + +/** + * @brief Set ADC Wait Counter Value. + * @note Set the wait cycle between each ADC sample. + * @param ADCx ADC Instance + * @param CNT Value between Min_Value=0x00 and Max_Value=0xFF + * @retval None + */ +__STATIC_INLINE void md_adc_set_srate_cnt(ADC_TypeDef *ADCx, uint32_t cnt) +{ + MODIFY_REG(ADCx->SRATE, ADC_SRATE_CNT_MSK, cnt<SRATE, ADC_SRATE_CNT_MSK))>>ADC_SRATE_CNT_POSS); +} + +/** + * @brief Set ADC Wait Counter Initial Value. + * @note Set the Initial Value of ADC wait counter. + * @param ADCx ADC Instance + * @param CNTINI + * @arg @ref CNTINI Value between Min_Value=0x00 and Max_Value=0xFF + * @retval None + */ +__STATIC_INLINE void md_adc_set_srate_cntini(ADC_TypeDef *adcx, uint32_t cntini) +{ + MODIFY_REG(adcx->SRATE, ADC_SRATE_CNTINI_MSK, cntini<SRATE, ADC_SRATE_CNTINI_MSK))>>ADC_SRATE_CNTINI_POSS); +} + +/** + * @brief Set ADC Converter Clock Division. + * @note Get the division ratio of ADC converter clock. 0 to 15 division ratio + * where 0 indicates no division is implemented. To modify CLKDIV, user + * should first set CLKEN to 0 and re-enable this bit after modification + * on CLKDIV. + * @param ADCx ADC Instance + * @param ADC Converter Clock Division + * @arg @ref MD_ADC_SRATE_CKDIV1 + * @arg @ref MD_ADC_SRATE_CKDIV2 + * @arg @ref MD_ADC_SRATE_CKDIV4 + * @arg @ref MD_ADC_SRATE_CKDIV6 + * @arg @ref MD_ADC_SRATE_CKDIV8 + * @arg @ref MD_ADC_SRATE_CKDIV10 + * @arg @ref MD_ADC_SRATE_CKDIV12 + * @arg @ref MD_ADC_SRATE_CKDIV14 + * @arg @ref MD_ADC_SRATE_CKDIV16 + * @arg @ref MD_ADC_SRATE_CKDIV18 + * @arg @ref MD_ADC_SRATE_CKDIV20 + * @arg @ref MD_ADC_SRATE_CKDIV22 + * @arg @ref MD_ADC_SRATE_CKDIV24 + * @arg @ref MD_ADC_SRATE_CKDIV26 + * @arg @ref MD_ADC_SRATE_CKDIV28 + * @arg @ref MD_ADC_SRATE_CKDIV30 + * @retval None + */ +__STATIC_INLINE void md_adc_set_srate_clkdiv(ADC_TypeDef *ADCx, uint32_t clkdiv) +{ + MODIFY_REG(ADCx->SRATE, ADC_SRATE_CKDIV_MSK, clkdiv<SRATE, ADC_SRATE_CKDIV_MSK))>>ADC_SRATE_CKDIV_POSS); +} + +/** + * @brief ADC clock enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_clken(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_SRATE_CKEN_MSK); +} + +/** + * @brief ADC clock sisable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_clken(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_SRATE_CKEN_MSK); +} + +/** + * @brief Check if ADC clock is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_clken(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_SRATE_CKEN_MSK) == (ADC_SRATE_CKEN_MSK)); +} + +/** + * @brief Channel 15 Invert Control enable. + * @note This is used to invert the data of channel 15. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch15inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH15INV_MSK); +} + +/** + * @brief Channel 15 Invert Control disable. + * @note This is used to invert the data of channel 15. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch15inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH15INV_MSK); +} + +/** + * @brief Check if Channel 15 Invert Control is enabled. + * @note This is used to invert the data of channel 15. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch15inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH15INV_MSK) == (ADC_CHINV_CH15INV_MSK)); +} + +/** + * @brief Channel 14 Invert Control enable. + * @note This is used to invert the data of channel 14. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch14inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH14INV_MSK); +} + +/** + * @brief Channel 14 Invert Control disable. + * @note This is used to invert the data of channel 14. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch14inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH14INV_MSK); +} + +/** + * @brief Check if Channel 14 Invert Control is enabled. + * @note This is used to invert the data of channel 14. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch14inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH14INV_MSK) == (ADC_CHINV_CH14INV_MSK)); +} + +/** + * @brief Channel 13 Invert Control enable. + * @note This is used to invert the data of channel 13. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch13inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH13INV_MSK); +} + +/** + * @brief Channel 13 Invert Control disable. + * @note This is used to invert the data of channel 13. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch13inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH13INV_MSK); +} + +/** + * @brief Check if Channel 13 Invert Control is enabled. + * @note This is used to invert the data of channel 13. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch13inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH13INV_MSK) == (ADC_CHINV_CH13INV_MSK)); +} + +/** + * @brief Channel 12 Invert Control enable. + * @note This is used to invert the data of channel 12. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch12inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH12INV_MSK); +} + +/** + * @brief Channel 12 Invert Control disable. + * @note This is used to invert the data of channel 12. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch12inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH12INV_MSK); +} + +/** + * @brief Check if Channel 12 Invert Control is enabled. + * @note This is used to invert the data of channel 12. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch12inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH12INV_MSK) == (ADC_CHINV_CH12INV_MSK)); +} + +/** + * @brief Channel 11 Invert Control enable. + * @note This is used to invert the data of channel 11. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch11inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH15INV_MSK); +} + +/** + * @brief Channel 11 Invert Control disable. + * @note This is used to invert the data of channel 11. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch11inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH11INV_MSK); +} + +/** + * @brief Check if Channel 11 Invert Control is enabled. + * @note This is used to invert the data of channel 11. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch11inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH11INV_MSK) == (ADC_CHINV_CH11INV_MSK)); +} + +/** + * @brief Channel 10 Invert Control enable. + * @note This is used to invert the data of channel 10. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch10inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH10INV_MSK); +} + +/** + * @brief Channel 10 Invert Control disable. + * @note This is used to invert the data of channel 10. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch10inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH10INV_MSK); +} + +/** + * @brief Check if Channel 10 Invert Control is enabled. + * @note This is used to invert the data of channel 10. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch10inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH10INV_MSK) == (ADC_CHINV_CH10INV_MSK)); +} + +/** + * @brief Channel 9 Invert Control enable. + * @note This is used to invert the data of channel 9. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch9inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH9INV_MSK); +} + +/** + * @brief Channel 9 Invert Control disable. + * @note This is used to invert the data of channel 9. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch9inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH9INV_MSK); +} + +/** + * @brief Check if Channel 9 Invert Control is enabled. + * @note This is used to invert the data of channel 9. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch9inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH9INV_MSK) == (ADC_CHINV_CH9INV_MSK)); +} + +/** + * @brief Channel 8 Invert Control enable. + * @note This is used to invert the data of channel 8. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch8inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH8INV_MSK); +} + +/** + * @brief Channel 8 Invert Control disable. + * @note This is used to invert the data of channel 8. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch8inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH8INV_MSK); +} + +/** + * @brief Check if Channel 8 Invert Control is enabled. + * @note This is used to invert the data of channel 8. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch8inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH8INV_MSK) == (ADC_CHINV_CH8INV_MSK)); +} + +/** + * @brief Channel 7 Invert Control enable. + * @note This is used to invert the data of channel 7. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch7inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH7INV_MSK); +} + +/** + * @brief Channel 7 Invert Control disable. + * @note Disable invert data channel 7. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch7inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH7INV_MSK); +} + +/** + * @brief Check if Channel 7 Invert Control is enabled. + * @note Check invert state of data channel 7. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch7inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH7INV_MSK) == (ADC_CHINV_CH7INV_MSK)); +} + +/** + * @brief Channel 6 Invert Control enable. + * @note This is used to invert the data of channel 6. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch6inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH6INV_MSK); +} + +/** + * @brief Channel 6 Invert Control disable. + * @note Disable invert data channel 6. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch6inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH6INV_MSK); +} + +/** + * @brief Check if Channel 6 Invert Control is enabled. + * @note Check invert state of data channel 6. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch6inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH6INV_MSK) == (ADC_CHINV_CH6INV_MSK)); +} + +/** + * @brief Channel 5 Invert Control enable. + * @note This is used to invert the data of channel 5. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch5inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH5INV_MSK); +} + +/** + * @brief Channel 5 Invert Control disable. + * @note Disable invert data channel 5. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch5inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH5INV_MSK); +} + +/** + * @brief Check if Channel 5 Invert Control is enabled. + * @note Check invert state of data channel 5. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch5inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH5INV_MSK) == (ADC_CHINV_CH5INV_MSK)); +} + +/** + * @brief Channel 4 Invert Control enable. + * @note This is used to invert the data of channel 4. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch4inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH4INV_MSK); +} + +/** + * @brief Channel 4 Invert Control disable. + * @note Disable invert data channel 4. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch4inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH4INV_MSK); +} + +/** + * @brief Check if Channel 4 Invert Control is enabled. + * @note Check invert state of data channel 4. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch4inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH4INV_MSK) == (ADC_CHINV_CH4INV_MSK)); +} + +/** + * @brief Channel 3 Invert Control enable. + * @note This is used to invert the data of channel 3. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch3inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH3INV_MSK); +} + +/** + * @brief Channel 3 Invert Control disable. + * @note Disable invert data channel 3. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch3inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH3INV_MSK); +} + +/** + * @brief Check if Channel 3 Invert Control is enabled. + * @note Check invert state of data of channel 3. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch3inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH3INV_MSK) == (ADC_CHINV_CH3INV_MSK)); +} + +/** + * @brief Channel 2 Invert Control enable. + * @note This is used to invert the data of channel 2. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch2inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH2INV_MSK); +} + +/** + * @brief Channel 2 Invert Control disable. + * @note Disable invert data channel 2. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch2inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH2INV_MSK); +} + +/** + * @brief Check if Channel 2 Invert Control is enabled. + * @note Check invert state of data of channel 2. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch2inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH2INV_MSK) == (ADC_CHINV_CH2INV_MSK)); +} + +/** + * @brief Channel 1 Invert Control enable. + * @note This is used to invert the data of channel 1. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch1inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH1INV_MSK); +} + +/** + * @brief Channel 1 Invert Control disable. + * @note Disable invert data channel 1. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch1inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH1INV_MSK); +} + +/** + * @brief Check if Channel 1 Invert Control is enabled. + * @note Check invert of data of channel 1. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch1inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH1INV_MSK) == (ADC_CHINV_CH1INV_MSK)); +} + +/** + * @brief Channel 0 Invert Control enable. + * @note This is used to invert the data of channel 0. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_srate_ch0inv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SRATE, ADC_CHINV_CH0INV_MSK); +} + +/** + * @brief Channel 0 Invert Control disable. + * @note Disable invert data channel 0. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_srate_ch0inv(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SRATE, ADC_CHINV_CH0INV_MSK); +} + +/** + * @brief Check if Channel 0 Invert Control is enabled. + * @note Check invert state of data of channel 0. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_srate_ch0inv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SRATE, ADC_CHINV_CH0INV_MSK) == (ADC_CHINV_CH0INV_MSK)); +} + +/** + * @brief Set ADC SRATE register. + * @note This is used to set SRATE register. + * @param ADCx ADC Instance + * @param SRATE + * @retval NONE. + */ +__STATIC_INLINE void md_adc_set_srate(ADC_TypeDef *adcx, uint32_t srate) +{ + WRITE_REG(adcx->SRATE, srate); +} + +/** + * @brief Get ADC SRATE register. + * @note This is used to read SRATE register. + * @param ADCx ADC Instance + * @param SRATE + * @retval SRATE Register Value. + */ +__STATIC_INLINE uint32_t md_adc_get_srate(ADC_TypeDef *adcx) +{ + return READ_REG(adcx->SRATE); +} + +/** + * @brief Set ADC Channel 7 PGA Gain. + * @note This is used to select channel 7 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl_ch7pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH7PGA_MSK, Gain<GAINL, ADC_GAINL_CH7PGA_MSK)>>ADC_GAINL_CH7PGA_POSS); +} + +/** + * @brief Set ADC Channel 6 PGA Gain. + * @note This is used to select channel 6 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl_ch6pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH6PGA_MSK, Gain<GAINL, ADC_GAINL_CH6PGA_MSK)>>ADC_GAINL_CH6PGA_POSS); +} + +/** + * @brief Set ADC Channel 5 PGA Gain. + * @note This is used to select channel 5 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl_ch5pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH5PGA_MSK, Gain<GAINL, ADC_GAINL_CH5PGA_MSK)>>ADC_GAINL_CH5PGA_POSS); +} + +/** + * @brief Set ADC Channel 4 PGA Gain. + * @note This is used to select channel 4 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl_ch4pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH4PGA_MSK, Gain<GAINL, ADC_GAINL_CH4PGA_MSK)>>ADC_GAINL_CH4PGA_POSS); +} + +/** + * @brief Set ADC Channel 3 PGA Gain. + * @note This is used to select channel 3 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl_ch3pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH3PGA_MSK, Gain<GAINL, ADC_GAINL_CH3PGA_MSK)>>ADC_GAINL_CH3PGA_POSS); +} + +/** + * @brief Set ADC Channel 2 PGA Gain. + * @note This is used to select channel 2 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl_ch2pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH2PGA_MSK, Gain<GAINL, ADC_GAINL_CH2PGA_MSK)>>ADC_GAINL_CH2PGA_POSS); +} + +/** + * @brief Set ADC Channel 1 PGA Gain. + * @note This is used to select channel 1 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl_ch1pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH1PGA_MSK, Gain<GAINL, ADC_GAINL_CH1PGA_MSK)>>ADC_GAINL_CH1PGA_POSS); +} + +/** + * @brief Set ADC Channel 0 PGA Gain. + * @note This is used to select channel 0 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl_ch0pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINL, ADC_GAINL_CH0PGA_MSK, Gain<GAINL, ADC_GAINL_CH0PGA_MSK)>>ADC_GAINL_CH0PGA_POSS); +} + +/** + * @brief Set ADC Channels 0~7 PGA Gain. + * @note This is used to select channels 0-7 PGA gain. + * @param ADCx ADC Instance + * @param GainL Register Values for CH0~CH7. + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainl(ADC_TypeDef *ADCx, uint32_t GainL) +{ + WRITE_REG(ADCx->GAINL, GainL); +} + +/** + * @brief Get ADC Channels 0~7 PGA Gain. + * @note This is used to read channels 0-7 PGA gain. + * @param ADCx ADC Instance + * @retval GainL Register Values for CH0~CH7. + */ +__STATIC_INLINE uint32_t md_adc_get_gainl(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->GAINL); +} + +/** + * @brief Set ADC Channel 15 PGA Gain. + * @note This is used to select channel 15 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh_ch15pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH15PGA_MSK, Gain<GAINH, ADC_GAINH_CH15PGA_MSK)>>ADC_GAINH_CH15PGA_POSS); +} + +/** + * @brief Set ADC Channel 14 PGA Gain. + * @note This is used to select channel 14 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh_ch14pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH14PGA_MSK, Gain<GAINH, ADC_GAINH_CH14PGA_MSK)>>ADC_GAINH_CH14PGA_POSS); +} + +/** + * @brief Set ADC Channel 13 PGA Gain. + * @note This is used to select channel 13 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh_ch13pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH13PGA_MSK, Gain<GAINH, ADC_GAINH_CH13PGA_MSK)>>ADC_GAINH_CH13PGA_POSS); +} + +/** + * @brief Set ADC Channel 12 PGA Gain. + * @note This is used to select channel 12 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh_ch12pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH12PGA_MSK, Gain<GAINH, ADC_GAINH_CH12PGA_MSK)>>ADC_GAINH_CH12PGA_POSS); +} + +/** + * @brief Set ADC Channel 11 PGA Gain. + * @note This is used to select channel 11 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh_ch11pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH11PGA_MSK, Gain<GAINH, ADC_GAINH_CH11PGA_MSK)>>ADC_GAINH_CH11PGA_POSS); +} + +/** + * @brief Set ADC Channel 10 PGA Gain. + * @note This is used to select channel 10 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh_ch10pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH10PGA_MSK, Gain<GAINH, ADC_GAINH_CH10PGA_MSK)>>ADC_GAINH_CH10PGA_POSS); +} + +/** + * @brief Set ADC Channel 9 PGA Gain. + * @note This is used to select channel 9 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh_ch9pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH9PGA_MSK, Gain<GAINH, ADC_GAINH_CH9PGA_MSK)>>ADC_GAINH_CH9PGA_POSS); +} + +/** + * @brief Set ADC Channel 8 PGA Gain. + * @note This is used to select channel 8 PGA gain. + * @param ADCx ADC Instance + * @param ADC PGA Gain + * @param Gain parameter can be one of the following values: + * @arg @ref MD_ADC_PGA_GAIN_X1 + * @arg @ref MD_ADC_PGA_GAIN_X2 + * @arg @ref MD_ADC_PGA_GAIN_X3 + * @arg @ref MD_ADC_PGA_GAIN_X4 + * @arg @ref MD_ADC_PGA_GAIN_X5 + * @arg @ref MD_ADC_PGA_GAIN_X6 + * @arg @ref MD_ADC_PGA_GAIN_X7 + * @arg @ref MD_ADC_PGA_GAIN_X8 + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh_ch8pga(ADC_TypeDef *ADCx, uint32_t Gain) +{ + MODIFY_REG(ADCx->GAINH, ADC_GAINH_CH8PGA_MSK, Gain<GAINH, ADC_GAINH_CH8PGA_MSK)>>ADC_GAINH_CH8PGA_POSS); +} + +/** + * @brief Set ADC Channels 8~15 PGA Gain. + * @note This register is used to select channels 8-15 PGA gain. + * @param GainH Register Values for CH8~CH15. + * @retval None + */ +__STATIC_INLINE void md_adc_set_gainh(ADC_TypeDef *ADCx, uint32_t GainH) +{ + WRITE_REG(ADCx->GAINH, GainH); +} + +/** + * @brief Get ADC Channels 8~15 PGA Gain. + * @note This register is used to read channels 8-15 PGA gain. + * @param ADCx ADC Instance + * @retval GainH Register Values for CH8~CH15. + */ +__STATIC_INLINE uint32_t md_adc_get_gainh(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->GAINH); +} + +/** + * @brief Refresh ADC FIFOs SS0~SS3. + * @note This register allowed users to reset ADC FIFO when starting a + * new Sample Sequencer. + * @param ADCx ADC Instance + * @param Value if bit (1 or 0) + * @retval None + */ +__STATIC_INLINE void md_adc_set_frf_ffrst(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->FRF, ADC_FRF_FFRST_MSK); +} + +/** + * @brief Get ADC FIFO Refresh Status. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_frf_ffrst(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->FRF, ADC_FRF_FFRST_MSK)>>ADC_FRF_FFRST_POS); +} + +/** + * @brief Refresh ADC SS3 FIFO. + * @note This register is used to refresh the FIFO of sequencer 3 at any + * time. This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_frf_ss3rf(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->FRF, ADC_FRF_SS3RF_MSK); +} + +/** + * @brief Refresh ADC SS32 FIFO. + * @note This register is used to refresh the FIFO of sequencer 2 at any + * time. This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_frf_ss2rf(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->FRF, ADC_FRF_SS2RF_MSK); +} + +/** + * @brief Refresh ADC SS1 FIFO. + * @note This register is used to refresh the FIFO of sequencer 1 at any + * time. This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_frf_ss1rf(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->FRF, ADC_FRF_SS1RF_MSK); +} + +/** + * @brief Refresh ADC SS0 FIFO. + * @note This register is used to refresh the FIFO of sequencer 0 at any + * time. This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_frf_ss0rf(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->FRF, ADC_FRF_SS0RF_MSK); +} + +/** + * @brief Refresh ADC FIFO Register. + * @note This is used to set RFR register. + * @param ADCx ADC Instance + * @param Register Value + * @retval None + */ +__STATIC_INLINE void md_adc_set_frf(ADC_TypeDef *ADCx, uint32_t Value) +{ + WRITE_REG(ADCx->FRF, Value); +} + +/** + * @brief Get ADC FIFO Refresh Register. + * @note This is used to get RFR register. + * @param ADCx ADC Instance + * @retval Register Value + */ +__STATIC_INLINE uint32_t md_adc_get_frf(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->FRF); +} + +/** + * @brief Check if all ADC Sequencer is idle. + * @note Check if SS0~SS3 is idle. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_idle(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SSEN, ADC_SSEN_IDLE_MSK) == (ADC_SSEN_IDLE_MSK)); +} + +/** + * @brief ADC Sample Sequencer 3 (SS3) Enable. + * @note User can set this bit to enable sample sequencer 3 (SS3). + * This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ssen_ss3en(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SSEN, ADC_SSEN_SS3EN_MSK); +} + +/** + * @brief ADC Sample Sequencer 3 (SS3) Disable. + * @note Disable sample sequencer 3 (SS3). + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ssen_ss3en(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SSEN, ADC_SSEN_SS3EN_MSK); +} + +/** + * @brief Check if ADC Sample Sequencer 3 (SS3) is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ssen_ss3en(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SSEN, ADC_SSEN_SS3EN_MSK) == (ADC_SSEN_SS3EN_MSK)); +} + +/** + * @brief ADC Sample Sequencer 2 (SS2) Enable. + * @note User can set this bit to enable sample sequencer 2 (SS2). + * This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ssen_ss2en(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SSEN, ADC_SSEN_SS2EN_MSK); +} + +/** + * @brief ADC Sample Sequencer 2 (SS2) Disable. + * @note Disable sample sequencer 2 (SS2). + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ssen_ss2en(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SSEN, ADC_SSEN_SS2EN_MSK); +} + +/** + * @brief Check if ADC Sample Sequencer 2 (SS2) is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ssen_ss2en(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SSEN, ADC_SSEN_SS2EN_MSK) == (ADC_SSEN_SS2EN_MSK)); +} + +/** + * @brief ADC Sample Sequencer 1 (SS1) Enable. + * @note User can set this bit to enable sample sequencer 1 (SS1). + * This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ssen_ss1en(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SSEN, ADC_SSEN_SS1EN_MSK); +} + +/** + * @brief ADC Sample Sequencer 1 (SS1) Disable. + * @note Disable sample sequencer 1 (SS1). + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ssen_ss1en(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SSEN, ADC_SSEN_SS1EN_MSK); +} + +/** + * @brief Check if ADC Sample Sequencer 1 (SS1) is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ssen_ss1en(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SSEN, ADC_SSEN_SS1EN_MSK) == (ADC_SSEN_SS1EN_MSK)); +} + +/** + * @brief ADC Sample Sequencer 0 (SS0) Enable. + * @note User can set this bit to enable sequencer 0 (SS0). + * This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ssen_ss0en(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SSEN, ADC_SSEN_SS0EN_MSK); +} + +/** + * @brief AADC Sample Sequencer 0 (SS0) Disable. + * @note Disable sample sequencer 0 (SS0). + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ssen_ss0en(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SSEN, ADC_SSEN_SS0EN_MSK); +} + +/** + * @brief Check if ADC Sample Sequencer 0 (SS0) is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ssen_ss0en(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SSEN, ADC_SSEN_SS0EN_MSK) == (ADC_SSEN_SS0EN_MSK)); +} + +/** + * @brief ADC Sample Sequencer 3 (SS3) Initiate. + * @note Triggers smapling on SS3 if the sequencer is enabled in the ADC_SSEN_SS3EN. + * This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_set_swtri_ss3(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SWTRI, ADC_SWTRI_SS3_MSK); +} + +/** + * @brief ADC Sample Sequencer 2 (SS2) Initiate. + * @note Triggers smapling on SS2 if the sequencer is enabled in the ADC_SSEN_SS2EN. + * This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_set_swtri_ss2(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SWTRI, ADC_SWTRI_SS2_MSK); +} + +/** + * @brief ADC Sample Sequencer 1 (SS1) Initiate. + * @note Triggers smapling on SS1 if the sequencer is enabled in the ADC_SSEN_SS1EN. + * This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_set_swtri_ss1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SWTRI, ADC_SWTRI_SS1_MSK); +} + +/** + * @brief ADC Sample Sequencer 0 (SS0) Initiate. + * @note Triggers smapling on SS0 if the sequencer is enabled in the ADC_SSEN_SS0EN. + * This bit will cleared by itself. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_set_swtri_ss0(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SWTRI, ADC_SWTRI_SS0_MSK); +} + +/** + * @brief ADC Timeout Interrupt Enable. + * @note User can set this bit to enable timeout Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ier_toie(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_TOIE_MSK); +} + +/** + * @brief ADC Sample Sequencer 3 (SS3) Interrupt Enable. + * @note User can set this bit to enable sequencer 3 Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ier_ss3ie(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_SS3IE_MSK); +} + +/** + * @brief ADC Sample Sequencer 2 (SS2) Interrupt Enable. + * @note User can set this bit to enable sequencer 2 Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ier_ss2ie(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_SS2IE_MSK); +} + +/** + * @brief ADC Sample Sequencer 1 (SS1) Interrupt Enable. + * @note User can set this bit to enable sequencer 1 Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ier_ss1ie(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_SS1IE_MSK); +} + +/** + * @brief ADC Sample Sequencer 0 (SS0) Interrupt Enable. + * @note User can set this bit to enable sequencer 0 Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ier_ss0ie(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, ADC_IER_SS0IE_MSK); +} + +/** + * @brief ADC Timeout Interrupt Disable. + * @note User can set this bit to disable timeout Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_idr_toid(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_TOID_MSK); +} + +/** + * @brief ADC Sample Sequencer 3 (SS3) Interrupt Disable. + * @note User can set this bit to disable sequencer 3 Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_idr_ss3id(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_SS3ID_MSK); +} + +/** + * @brief ADC Sample Sequencer 2 (SS2) Interrupt Disable. + * @note User can set this bit to disable sequencer 2 Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_idr_ss2id(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_SS2ID_MSK); +} + +/** + * @brief ADC Sample Sequencer 1 (SS1) Interrupt Disable. + * @note User can set this bit to disable sequencer 1 Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_idr_ss1id(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_SS1ID_MSK); +} + +/** + * @brief ADC Sample Sequencer 0 (SS0) Interrupt Disable. + * @note User can set this bit to disable sequencer 0 Interrupt function. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_idr_ss0id(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IDR, ADC_IDR_SS0ID_MSK); +} + +/** + * @brief Check if ADC Timeout Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ivs_toivs(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_TOIVS_MSK) == (ADC_IVS_TOIVS_MSK)); +} + +/** + * @brief Check if ADC Sample Sequencer 3 (SS3) Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ivs_ss3ivs(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_SS3IVS_MSK) == (ADC_IVS_SS3IVS_MSK)); +} + +/** + * @brief Check if ADC Sample Sequencer 2 (SS2) Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ivs_ss2ivs(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_SS2IVS_MSK) == (ADC_IVS_SS2IVS_MSK)); +} + +/** + * @brief Check if ADC Sample Sequencer 1 (SS1) Interrupt is Enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ivs_ss1ivs(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_SS1IVS_MSK) == (ADC_IVS_SS1IVS_MSK)); +} + +/** + * @brief Check if ADC Sample Sequencer 0 (SS0) Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ivs_ss0ivs(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IVS, ADC_IVS_SS0IVS_MSK) == (ADC_IVS_SS0IVS_MSK)); +} + +/** + * @brief Check Timeout Raw Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_rif_torif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_TORIF_MSK) == (ADC_RIF_TORIF_MSK)); +} + +/** + * @brief Check ADC Sample Sequencer 3 (SS3) Raw Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_rif_ss3rif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_SS3RIF_MSK) == (ADC_RIF_SS3RIF_MSK)); +} + +/** + * @brief Check ADC Sample Sequencer 2 (SS2) Raw Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_rif_ss2rif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_SS2RIF_MSK) == (ADC_RIF_SS2RIF_MSK)); +} + +/** + * @brief Check ADC Sample Sequencer 1 (SS1) Raw Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_rif_ss1rif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_SS1RIF_MSK) == (ADC_RIF_SS1RIF_MSK)); +} + +/** + * @brief Check ADC Sample Sequencer 0 (SS0) Raw Interrupt Flag Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_rif_ss0rif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->RIF, ADC_RIF_SS0RIF_MSK) == (ADC_RIF_SS0RIF_MSK)); +} + +/** + * @brief Check Timeout Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ifm_torif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_TOIFM_MSK) == (ADC_IFM_TOIFM_MSK)); +} + +/** + * @brief Check ADC Sample Sequencer 3 (SS3) Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ifm_ss3rif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_SS3IFM_MSK) == (ADC_IFM_SS3IFM_MSK)); +} + +/** + * @brief Check ADC Sample Sequencer 2 (SS2) Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ifm_ss2rif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_SS2IFM_MSK) == (ADC_IFM_SS2IFM_MSK)); +} + +/** + * @brief Check ADC Sample Sequencer 1 (SS1) Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ifm_ss1rif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_SS1IFM_MSK) == (ADC_IFM_SS1IFM_MSK)); +} + +/** + * @brief Check ADC Sample Sequencer 0 (SS0) Interrupt Flag Masked Status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ifm_ss0rif(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IFM, ADC_IFM_SS0IFM_MSK) == (ADC_IFM_SS0IFM_MSK)); +} + +/** + * @brief ADC Timeout Interrupt Clear. + * @note User can set this bit to clear timeout interrupt status. + * @param ADCx ADC Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_icr_toicr(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_TOICR_MSK); +} + +/** + * @brief ADC Sample Sequencer 3 (SS3) Interrupt Clear. + * @note User can set this bit to clear SS3 interrupt status. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_icr_ss3icr(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_SS3ICR_MSK); +} + +/** + * @brief ADC Sample Sequencer 2 (SS2) Interrupt Clear. + * @note User can set this bit to clear SS2 interrupt status. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_icr_ss2icr(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_SS2ICR_MSK); +} + +/** + * @brief ADC Sample Sequencer 1 (SS1) Interrupt Clear. + * @note User can set this bit to clear SS1 interrupt status. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_icr_ss1icr(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_SS1ICR_MSK); +} + +/** + * @brief ADC Sample Sequencer 0 (SS0) Interrupt Clear. + * @note User can set this bit to clear SS0 interrupt status. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_clear_flag_icr_ss0icr(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->ICR, ADC_ICR_SS0ICR_MSK); +} + +/** + * @brief ADC SS3 DMA Function Enable. + * @note User can set this register to enable DMA function. + * For S3, if set when FIFO is not empty, DMA Single REQ will rise. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_dma_ss3dmaen(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->DMA, ADC_DMA_SS3_DMAEN_MSK); +} + +/** + * @brief ADC SS3 DMA Function Disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_dma_ss3dmaen(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->DMA, ADC_DMA_SS3_DMAEN_MSK); +} + +/** + * @brief Check if ADC SS3 DMA is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_dma_ss3dmaen(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->DMA, ADC_DMA_SS3_DMAEN_MSK) == (ADC_DMA_SS3_DMAEN_MSK)); +} + +/** + * @brief ADC SS2 DMA Function Enable. + * @note User can set this register to enable DMA function. + * For S2, if set when FIFO is not empty, DMA Single REQ will rise. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_dma_ss2dmaen(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->DMA, ADC_DMA_SS2_DMAEN_MSK); +} + +/** + * @brief ADC SS2 DMA Function Disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_dma_ss2dmaen(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->DMA, ADC_DMA_SS2_DMAEN_MSK); +} + +/** + * @brief Check if ADC SS2 DMA is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_dma_ss2dmaen(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->DMA, ADC_DMA_SS2_DMAEN_MSK) == (ADC_DMA_SS2_DMAEN_MSK)); +} + +/** + * @brief ADC SS1 DMA Function Enable. + * @note User can set this register to enable DMA function. + * For S1, if set when FIFO is not empty, DMA Single REQ will rise. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_dma_ss1dmaen(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->DMA, ADC_DMA_SS1_DMAEN_MSK); +} + +/** + * @brief ADC SS1 DMA Function Disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_dma_ss1dmaen(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->DMA, ADC_DMA_SS1_DMAEN_MSK); +} + +/** + * @brief Check if ADC SS1 DMA is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_dma_ss1dmaen(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->DMA, ADC_DMA_SS1_DMAEN_MSK) == (ADC_DMA_SS1_DMAEN_MSK)); +} + +/** + * @brief ADC SS0 DMA Function Enable. + * @note User can set this register to enable DMA function. + * For S0, if set when FIFO is not empty, DMA Single REQ will rise. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_dma_ss0dmaen(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->DMA, ADC_DMA_SS0_DMAEN_MSK); +} + +/** + * @brief ADC SS0 DMA Function Disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_dma_ss0dmaen(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->DMA, ADC_DMA_SS0_DMAEN_MSK); +} + +/** + * @brief Check if ADC SS3 DMA is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_dma_ss0dmaen(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->DMA, ADC_DMA_SS0_DMAEN_MSK) == (ADC_DMA_SS0_DMAEN_MSK)); +} + +/** + * @brief Set SS0 Trigger Select. + * @note This field selects the trigger source for Sample Sequencer 0. + * @param ADCx ADC Instance. + * @param Sample sequencer trigger sources. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_SEL_SW + * @arg @ref MD_ADC_SS_CON_SEL_BS16T1 + * @arg @ref MD_ADC_SS_CON_SEL_ALWAYS + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T2 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T3 + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T2 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T3 + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T4 + * @arg @ref MD_ADC_SS_CON_SEL_AD16C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GPIO + * @arg @ref MD_ADC_SS_CON_SEL_CMP0 + * @arg @ref MD_ADC_SS_CON_SEL_CMP1 + * @arg @ref MD_ADC_SS_CON_SEL_CMP2 + * @arg @ref MD_ADC_SS_CON_SEL_CMP3 + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss0_con_sel(ADC_TypeDef *ADCx, uint32_t TrigSource) +{ + MODIFY_REG(ADCx->SS0_CON, ADC_SS0_CON_SEL_MSK, TrigSource<SS0_CON, ADC_SS0_CON_SEL_MSK)>>ADC_SS0_CON_SEL_POSS); +} + +/** + * @brief Set ADC Sample Sequencer 0 (SS0) Trigger Type select. + * @note User can set this bit to select the type of trigger. + * @param Sample sequencer trigger types. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_TYP_EDGE + * @arg @ref MD_ADC_SS_COM_TYP_LEVEL + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss0_con_type(ADC_TypeDef *ADCx, uint32_t TrigType) +{ + MODIFY_REG(ADCx->SS0_CON, ADC_SS0_CON_TYP_MSK, TrigType<SS0_CON, ADC_SS0_CON_TYP_MSK)>>ADC_SS0_CON_TYP_POS); +} + +/** + * @brief Set ADC Sample Sequencer 0 (SS0) Priority. + * @note This field contains a binary-encoded value specifying the + * priority encoding of SS0. The prioriteies assigned to the + * sequencers must be uniquely mapped. + * @param ADCx ADC Instance. + * @param Sample sequencer trigger priorities. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS0_CON_PRI_HIGHEST + * @arg @ref MD_ADC_SS0_CON_PRI_SECOND + * @arg @ref MD_ADC_SS0_CON_PRI_THIRD + * @arg @ref MD_ADC_SS0_CON_PRI_LOWEST + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss0_con_pri(ADC_TypeDef *ADCx, uint32_t priority) +{ + MODIFY_REG(ADCx->SS0_CON, ADC_SS0_CON_PRI_MSK, priority<SS0_CON, ADC_SS0_CON_PRI_MSK)>>ADC_SS0_CON_PRI_POSS); +} + +/** + * @brief Enable One Shot Trigger Mode. + * @note When set HIGH, each trigger will only sample once and use one slot in FIFO. + * @param ADCx ADC Instance. + * @retval None + */ +__STATIC_INLINE void md_adc_enable_ss0_con_one(ADC_TypeDef *adcx) +{ + SET_BIT(adcx->SS0_CON, ADC_SS0_CON_ONE_MSK); +} + +/** + * @brief Disable One Shot Trigger Mode. + * @param ADCx ADC Instance. + * @retval None + */ +__STATIC_INLINE void md_adc_disable_ss0_con_one(ADC_TypeDef *adcx) +{ + CLEAR_BIT(adcx->SS0_CON, ADC_SS0_CON_ONE_MSK); +} + +/** + * @brief Set 8th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux0_mux7(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX7_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX7_MSK)>>ADC_SS0_MUX0_MUX7_POSS); +} + +/** + * @brief Set 7th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux0_mux6(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX6_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX6_MSK)>>ADC_SS0_MUX0_MUX6_POSS); +} + +/** + * @brief Set 6th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux0_mux5(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX5_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX5_MSK)>>ADC_SS0_MUX0_MUX5_POSS); +} + +/** + * @brief Set 5th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux0_mux4(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX4_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX4_MSK)>>ADC_SS0_MUX0_MUX4_POSS); +} + +/** + * @brief Set 4th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux0_mux3(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX3_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX3_MSK)>>ADC_SS0_MUX0_MUX3_POSS); +} + +/** + * @brief Set 3rd Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux0_mux2(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX2_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX2_MSK)>>ADC_SS0_MUX0_MUX2_POSS); +} + +/** + * @brief Set 2nd Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux0_mux1(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX1_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX1_MSK)>>ADC_SS0_MUX0_MUX1_POSS); +} + +/** + * @brief Set 1st Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux0_mux0(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX0, ADC_SS0_MUX0_MUX0_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX0_MUX0_MSK)>>ADC_SS0_MUX0_MUX0_POSS); +} + +/** + * @brief Set ADC channels MUX 0~7. + * @note Set ADC SS0_MUX0 register. + * @note Mapping ADINx to ADC channels 0~7. + + * @param ADC Channel + * @param MUX Register + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss0_mux0(ADC_TypeDef *ADCx, uint32_t RegValue) +{ + WRITE_REG(ADCx->SS0_MUX0, RegValue); +} + +/** + * @brief Get ADC channels MUX 0~7. + * @note Get ADC SS0_MUX0 register. + * @param ADCx ADC Instance + * @retval SS0_MUX0 Register Value + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_mux0(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->SS0_MUX0); +} + +/** + * @brief Set 16th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux1_mux15(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX15_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX15_MSK)>>ADC_SS0_MUX1_MUX15_POSS); +} + +/** + * @brief Set 15th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux1_mux14(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX14_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX14_MSK)>>ADC_SS0_MUX1_MUX14_POSS); +} + +/** + * @brief Set 14th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux1_mux13(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX13_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX13_MSK)>>ADC_SS0_MUX1_MUX13_POSS); +} + +/** + * @brief Set 13th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux1_mux12(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX12_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX12_MSK)>>ADC_SS0_MUX1_MUX12_POSS); +} + +/** + * @brief Set 12th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux1_mux11(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX11_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX11_MSK)>>ADC_SS0_MUX1_MUX11_POSS); +} + +/** + * @brief Set 11th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux1_mux10(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX10_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX10_MSK)>>ADC_SS0_MUX1_MUX10_POSS); +} + +/** + * @brief Set 10th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux1_mux9(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX9_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX9_MSK)>>ADC_SS0_MUX1_MUX9_POSS); +} + +/** + * @brief Set 9th Sample Input Select. + * @note User can set this register to select which channel will be + * sampled. For example, a value of n indicates the input is + * channel n. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss0_mux1_mux8(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS0_MUX1, ADC_SS0_MUX1_MUX8_MSK, AdinPin<SS0_MUX0, ADC_SS0_MUX1_MUX8_MSK)>>ADC_SS0_MUX1_MUX8_POSS); +} + +/** + * @brief Set ADC channels MUX 8~15. + * @note Set SS0_MUX1 register for channels 8~15. + * @param ADCx ADC Instance. + * @param SS0 MUX1 Register. + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss0_mux1(ADC_TypeDef *ADCx, uint32_t RegValue) +{ + WRITE_REG(ADCx->SS0_MUX1, RegValue); +} + +/** + * @brief Get ADC channels MUX 8~15. + * @note Get SS0_MUX1 register for channels 8~15. + * @param ADCx ADC Instance. + * @retval SS0 MUX1 Register. + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_mux1(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->SS0_MUX1); +} + +/** + * @brief 16th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie15(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE15_MSK); +} + +/** + * @brief 16th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie15(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE15_MSK); +} + +/** + * @brief Check if 16th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie15(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE15_MSK) == (ADC_SS0_END_IE15_MSK)); +} + +/** + * @brief 15th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie14(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE14_MSK); +} + +/** + * @brief 15th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie14(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE14_MSK); +} + +/** + * @brief Check if 15th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie14(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE14_MSK) == (ADC_SS0_END_IE14_MSK)); +} + +/** + * @brief 14th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie13(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE13_MSK); +} + +/** + * @brief 14th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie13(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE13_MSK); +} + +/** + * @brief Check if 14th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie13(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE13_MSK) == (ADC_SS0_END_IE13_MSK)); +} + +/** + * @brief 13th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie12(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE12_MSK); +} + +/** + * @brief 13th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie12(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE12_MSK); +} + +/** + * @brief Check if 13th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie12(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE12_MSK) == (ADC_SS0_END_IE12_MSK)); +} + +/** + * @brief 12th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie11(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE11_MSK); +} + +/** + * @brief 12th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie11(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE11_MSK); +} + +/** + * @brief Check 12th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie11(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE11_MSK) == (ADC_SS0_END_IE11_MSK)); +} + +/** + * @brief 11th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie10(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE10_MSK); +} + +/** + * @brief 11th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie10(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE10_MSK); +} + +/** + * @brief Check if 11th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie10(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE10_MSK) == (ADC_SS0_END_IE10_MSK)); +} + +/** + * @brief 10th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie9(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE9_MSK); +} + +/** + * @brief 10th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie9(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE9_MSK); +} + +/** + * @brief Check if 10th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie9(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE9_MSK) == (ADC_SS0_END_IE9_MSK)); +} + +/** + * @brief 9th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie8(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE8_MSK); +} + +/** + * @brief 9th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie8(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE8_MSK); +} + +/** + * @brief Check if 9th Sample Interrupt is Enable. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie8(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE8_MSK) == (ADC_SS0_END_IE8_MSK)); +} + +/** + * @brief 8th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie7(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE7_MSK); +} + +/** + * @brief 8th Sample Interrupt Disable + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie7(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE7_MSK); +} + +/** + * @brief Check if 8th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie7(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE7_MSK) == (ADC_SS0_END_IE7_MSK)); +} + +/** + * @brief 7th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie6(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE6_MSK); +} + +/** + * @brief 7th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie6(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE6_MSK); +} + +/** + * @brief Check if 7th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie6(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE6_MSK) == (ADC_SS0_END_IE6_MSK)); +} + + +/** + * @brief 6th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie5(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE5_MSK); +} + +/** + * @brief 6th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie5(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE5_MSK); +} + +/** + * @brief Check if 6th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie5(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE5_MSK) == (ADC_SS0_END_IE5_MSK)); +} + +/** + * @brief 5th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie4(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE4_MSK); +} + +/** + * @brief 5th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie4(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE4_MSK); +} + +/** + * @brief Check if 5th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie4(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE4_MSK) == (ADC_SS0_END_IE4_MSK)); +} + +/** + * @brief 4th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie3(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE3_MSK); +} + +/** + * @brief 4th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie3(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE3_MSK); +} + +/** + * @brief Check if 4th Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie3(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE3_MSK) == (ADC_SS0_END_IE3_MSK)); +} + +/** + * @brief 3rd Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie2(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE2_MSK); +} + +/** + * @brief 3rd Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie2(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE2_MSK); +} + +/** + * @brief Check if 3rd Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie2(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE2_MSK) == (ADC_SS0_END_IE2_MSK)); +} + +/** + * @brief 2nd Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE1_MSK); +} + +/** + * @brief 2nd Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE1_MSK); +} + +/** + * @brief Check if 2nd Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE1_MSK) == (ADC_SS0_END_IE1_MSK)); +} + +/** + * @brief 1st Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss0_end_ie0(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_END_IE0_MSK); +} + +/** + * @brief 1st Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss0_end_ie0(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS0_END, ADC_SS0_END_IE0_MSK); +} + +/** + * @brief Check if 1st Sample Interrupt is Enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss0_end_ie0(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_END, ADC_SS0_END_IE0_MSK) == (ADC_SS0_END_IE0_MSK)); +} + +/** + * @brief Set ADC SS0 sample counts. + * @note User can set this register to select how many times will ADC samples data. + * @param ADCx ADC Instance. + * @param End Value Min_Value=0x00 Max_Value=0x0F. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss0_end_end(ADC_TypeDef *ADCx, uint32_t EndValue) +{ + MODIFY_REG(ADCx->SS0_END, ADC_SS0_END_END_MSK, EndValue<SS0_END, ADC_SS0_END_END_MSK)>>ADC_SS0_END_END_POSS); +} + +/** + * @brief Set ADC Sample Sequence 0 End Control Register. + * @note Set ADC_SS0_END register + * @param ADCx ADC Instance + * @param ADC_SS0_END Register Value + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss0_end(ADC_TypeDef *ADCx, uint32_t RegValue) +{ + MODIFY_REG(ADCx->SS0_END, ADC_SS0_END_END_MSK, RegValue); +} + +/** + * @brief Get ADC Sample Sequence 0 End Control Register. + * @param ADCx ADC Instance + * @retval ADC_SS0_END Register Value + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_end(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->SS0_END); +} + +/** + * @brief Set ADC Sample Sequencer 0 (SS0) FIFO Overflow status + * @note When the FIFO is full and a write was requested. + * When an overflow is detected, the most recent write is dropped. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss0_fstat_ov(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_FSTAT_OV_MSK); +} + +/** + * @brief Get ADC Sample Sequencer 0 (SS0) FIFO Overflow status + * @param ADCx ADC Instance + * @retval 1 or 0 + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_ov(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_OV_MSK)>>ADC_SS0_FSTAT_OV_POS); +} + +/** + * @brief Check if ADC SS0 FSTAT OV is actived. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss0_fstat_ov(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_OV_MSK) == (ADC_SS0_FSTAT_OV_MSK)); +} + +/** + * @brief Get ADC SS0 FSTAT FULL + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_full(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_FULL_MSK)>>ADC_SS0_FSTAT_FULL_POS); +} + +/** + * @brief Check if ADC SS0 FSTAT FULL is actived. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss0_fstat_full(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_FULL_MSK) == (ADC_SS0_FSTAT_FULL_MSK)); +} + +/** + * @brief Set ADC SS0 FSTAT UV. + * @note When the FIFO is empty and a read was requested. + * The problematic read does not move the FIFO pointers, and 0s are returned. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss0_fstat_uv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS0_END, ADC_SS0_FSTAT_UV_MSK); +} + +/** + * @brief Get ADC SS0 FSTAT UV + * @param ADCx ADC Instance + * @retval 1 or 0 + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_uv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_UV_MSK)>>ADC_SS0_FSTAT_UV_POS); +} + +/** + * @brief Check if ADC SS0 FSTAT UV is actived. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss0_fstat_uv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_UV_MSK) == (ADC_SS0_FSTAT_UV_MSK)); +} + +/** + * @brief Get ADC SS0 FSTAT EMPTY + * @param ADCx ADC Instance + * @retval 1 or 0 + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_empty(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_EMPTY_MSK)>>ADC_SS0_FSTAT_EMPTY_POS); +} + +/** + * @brief Check if ADC SS0 FSTAT EMPTY is actived. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss0_fstat_empty(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_EMPTY_MSK) == (ADC_SS0_FSTAT_EMPTY_MSK)); +} + +/** + * @brief Get ADC SS0 FSTAT HPTR + * @note The field contains the current head pointer index, which is the + * next entry to be written to FIFO. + * @param ADCx ADC Instance + * @retval 1 or 0 + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_hptr(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_HPTR_MSK)>>ADC_SS0_FSTAT_HPTR_POSS); +} + +/** + * @brief Get ADC SS0 FSTAT TPTR + * @note The field contains the current tail pointer index, which is the + * next entry to be read from FIFO. + * @param ADCx ADC Instance + * @retval 1 or 0 + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_fstat_tptr(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS0_FSTAT, ADC_SS0_FSTAT_TPTR_MSK)>>ADC_SS0_FSTAT_TPTR_POSS); +} + +/** + * @brief Get ADC sample sequencer 0(SS0) result FIFO data. + * @note User can read conversion result data by reading this register. + * @param ADCx ADC Instance + * @retval ADC Sampled Data + */ +__STATIC_INLINE uint32_t md_adc_get_ss0_data(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADC->SS0_DATA)); +} + +/** + * @brief Set SS1 Trigger Select. + * @note This field selects the trigger source for Sample Sequencer 1. + * @param ADCx ADC Instance + * @param Sample sequencer trigger sources. + * This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_SEL_SW + * @arg @ref MD_ADC_SS_CON_SEL_BS16T1 + * @arg @ref MD_ADC_SS_CON_SEL_ALWAYS + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T2 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T3 + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T2 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T3 + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T4 + * @arg @ref MD_ADC_SS_CON_SEL_AD16C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GPIO + * @arg @ref MD_ADC_SS_CON_SEL_CMP0 + * @arg @ref MD_ADC_SS_CON_SEL_CMP1 + * @arg @ref MD_ADC_SS_CON_SEL_CMP2 + * @arg @ref MD_ADC_SS_CON_SEL_CMP3 + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss1_con_sel(ADC_TypeDef *ADCx, uint32_t TrigSource) +{ + MODIFY_REG(ADCx->SS1_CON, ADC_SS1_CON_SEL_MSK, TrigSource<SS1_CON, ADC_SS1_CON_SEL_MSK)>>ADC_SS1_CON_SEL_POSS); +} + +/** + * @brief ADC Sample Sequencer 1 (SS1) Trigger Type select. + * @note User can set this bit to select the type of trigger. + * @param ADCx ADC Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_TYP_EDGE + * @arg @ref MD_ADC_SS_COM_TYP_LEVEL + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss1_con_type(ADC_TypeDef *ADCx, uint32_t TrigType) +{ + MODIFY_REG(ADCx->SS1_CON, ADC_SS1_CON_TYP_MSK, TrigType<SS1_CON, ADC_SS1_CON_TYP_MSK)>>ADC_SS1_CON_TYP_POS); +} + +/** + * @brief Set ADC Sample Sequencer 1 (SS1) Priority. + * @note This field contains a binary-encoded value specifying the + * priority encoding of SS1. The prioriteies assigned to the + * sequencers must be uniquely mapped. + * @param ADCx ADC Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS0_CON_PRI_HIGHEST + * @arg @ref MD_ADC_SS0_CON_PRI_SECOND + * @arg @ref MD_ADC_SS0_CON_PRI_THIRD + * @arg @ref MD_ADC_SS0_CON_PRI_LOWEST + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss1_con_pri(ADC_TypeDef *adcx, uint32_t priority) +{ + MODIFY_REG(adcx->SS1_CON, ADC_SS1_CON_PRI_MSK, priority<SS1_CON, ADC_SS1_CON_PRI_MSK)>>ADC_SS1_CON_PRI_POSS); +} + +/** + * @brief One Shot Trigger Mode enable. + * @note When set HIGH, each trigger will only sample once and use one + * slot in FIFO. + * @param ADCx ADC Instance. + * @retval None + */ +__STATIC_INLINE void md_adc_enable_ss1_con_one(ADC_TypeDef *adcx) +{ + SET_BIT(adcx->SS1_CON, ADC_SS1_CON_ONE_MSK); +} + +/** + * @brief One Shot Trigger Mode disable. + * @param ADCx ADC Instance. + * @retval None + */ +__STATIC_INLINE void md_adc_disable_ss1_con_one(ADC_TypeDef *adcx) +{ + CLEAR_BIT(adcx->SS1_CON, ADC_SS1_CON_ONE_MSK); +} + +/** + * @brief Set ADC SS1 MUX7 ADINx Input Pin. + * @note 8th Sample Input Select. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss1_mux0_mux7(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX7_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX7_MSK)>>ADC_SS1_MUX0_MUX7_POSS); +} + +/** + * @brief Set ADC SS1 MUX6 Input ADIN Pin. + * @note 7th Sample Input Select. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss1_mux0_mux6(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX6_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX6_MSK)>>ADC_SS1_MUX0_MUX6_POSS); +} + +/** + * @brief Set ADC SS1 MUX0 MUX5 Input ADIN Pin. + * @note 6th Sample Input Select. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss1_mux0_mux5(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX5_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX5_MSK)>>ADC_SS1_MUX0_MUX5_POSS); +} + +/** + * @brief Set ADC SS1 MUX0 MUX4 Input ADIN Pin. + * @note 5th Sample Input Select. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss1_mux0_mux4(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX4_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX4_MSK)>>ADC_SS1_MUX0_MUX4_POSS); +} + +/** + * @brief Set ADC SS1 MUX0 MUX3 Input ADIN Pin. + * @note 4th Sample Input Select. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss1_mux0_mux3(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX3_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX3_MSK)>>ADC_SS1_MUX0_MUX3_POSS); +} + +/** + * @brief Set ADC SS1 MUX0 MUX2 Input ADIN Pin. + * @note 3rd Sample Input Select. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss1_mux0_mux2(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX2_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX2_MSK)>>ADC_SS1_MUX0_MUX2_POSS); +} + +/** + * @brief Set ADC SS1 MUX0 MUX1 Input ADIN Pin. + * @note 2nd Sample Input Select. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss1_mux0_mux1(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX1_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX1_MSK)>>ADC_SS1_MUX0_MUX1_POSS); +} + +/** + * @brief Set ADC SS1 MUX0 MUX0 Input ADIN Pin. + * @note 1st Sample Input Select. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss1_mux0_mux0(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS1_MUX0, ADC_SS1_MUX0_MUX0_MSK, AdinPin<SS1_MUX0, ADC_SS1_MUX0_MUX0_MSK)>>ADC_SS1_MUX0_MUX0_POSS); +} + +/** + * @brief Set ADC_SS1_MUX0 register. + * @note Set ADC_SS1_MUX0 channels 0~7. + * @param ADCx ADC Instance. + * @param ADC_SS1_MUX0 register value. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss1_mux0(ADC_TypeDef *ADCx, uint32_t RegValue) +{ + WRITE_REG(ADCx->SS1_MUX0, RegValue); +} + +/** + * @brief Get ADC_SS1_MUX0 register. + * @param ADCx ADC Instance. + * @retval ADC_SS1_MUX0 register value. + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_mux0(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->SS1_MUX0); +} + +/** + * @brief 8th Sample Interrupt Enable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_enable_ss1_end_ie7(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE7_MSK); +} + +/** + * @brief 8th Sample Interrupt Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_ss1_end_ie7(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE7_MSK); +} + +/** + * @brief Check if 8th Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie7(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE7_MSK) == (ADC_SS1_END_IE7_MSK)); +} + +/** + * @brief 7th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss1_end_ie6(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE6_MSK); +} + +/** + * @brief 7th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss1_end_ie6(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE6_MSK); +} + +/** + * @brief Check if 7th Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie6(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE6_MSK) == (ADC_SS1_END_IE6_MSK)); +} + + +/** + * @brief 6th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss10_end_ie5(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE5_MSK); +} + +/** + * @brief 8th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss1_end_ie5(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE5_MSK); +} + +/** + * @brief Check if 6th Sample Interrupt is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie5(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE5_MSK) == (ADC_SS1_END_IE5_MSK)); +} + +/** + * @brief 5th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss1_end_ie4(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE4_MSK); +} + +/** + * @brief 5th Sample Interrupt Disable. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_disable_ss1_end_ie4(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE4_MSK); +} + +/** + * @brief Check if 5th Sample Interrupt is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie4(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE4_MSK) == (ADC_SS1_END_IE4_MSK)); +} + +/** + * @brief 4th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss1_end_ie3(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE3_MSK); +} + +/** + * @brief 8th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss1_end_ie3(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE3_MSK); +} + +/** + * @brief Check if 4th Sample Interrupt is enabled. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie3(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE3_MSK) == (ADC_SS1_END_IE3_MSK)); +} + +/** + * @brief 3rd Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss1_end_ie2(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE2_MSK); +} + +/** + * @brief 3rd Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss1_end_ie2(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE2_MSK); +} + +/** + * @brief Check if 3rd Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie2(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE2_MSK) == (ADC_SS1_END_IE2_MSK)); +} + +/** + * @brief 2nd Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss1_end_ie1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE1_MSK); +} + +/** + * @brief 2nd Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss1_end_ie1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE1_MSK); +} + +/** + * @brief Check if 2nd Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE1_MSK) == (ADC_SS1_END_IE1_MSK)); +} + +/** + * @brief 1st Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss1_end_ie0(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_END_IE0_MSK); +} + +/** + * @brief 1st Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss1_end_ie0(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS1_END, ADC_SS1_END_IE0_MSK); +} + +/** + * @brief Check if 1st Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss1_end_ie0(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS1_END_IE0_MSK) == (ADC_SS1_END_IE0_MSK)); +} + +/** + * @brief Set end sample counts. + * @note User can set this register to select how many times will ADC + * samples data. + * @param ADCx ADC Instance. + * @param End Value Min_Value=0x00 Max_Value=0x07. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss1_end_end(ADC_TypeDef *ADCx, uint32_t EndValue) +{ + MODIFY_REG(ADCx->SS1_END, ADC_SS1_END_END_MSK, EndValue<SS1_END, ADC_SS1_END_END_MSK)>>ADC_SS1_END_END_POSS); +} + +/** + * @brief Set ADC_SS1_END Control Register + * @param ADCx ADC Instance. + * @param ADC_SS1_END register value. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss1_end(ADC_TypeDef *ADCx, uint32_t RegValue) +{ + MODIFY_REG(ADCx->SS1_END, ADC_SS1_END_END_MSK, RegValue); +} + +/** + * @brief Get ADC_SS1_End Control Register + * @param ADCx ADC Instance. + * @retval ADC_SS1_END register value. + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_end(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->SS1_END); +} + +/** + * @brief Set ADC Sample Sequencer 1 (SS1) FIFO Overflow status. + * @note When the FIFO is full and a write was requested, the + * most recent write is dropped. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss1_fstat_ov(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_FSTAT_OV_MSK); +} + +/** + * @brief Get ADC Sample Sequencer 1 (SS1) FIFO Overflow status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_ov(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_OV_MSK)>>ADC_SS1_FSTAT_OV_POS); +} + +/** + * @brief Check if ADC Sample Sequencer 1 (SS1) FIFO Overflow is actived. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss1_fstat_ov(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_OV_MSK) == (ADC_SS1_FSTAT_OV_MSK)); +} + +/** + * @brief Get ADC SS1 FIFO Full status + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_full(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_FULL_MSK)>>ADC_SS1_FSTAT_FULL_POS); +} + +/** + * @brief Check if ADC SS1 FIFO Full is actived. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss1_fstat_full(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_FULL_MSK) == (ADC_SS1_FSTAT_FULL_MSK)); +} + +/** + * @brief Set ADC Sample Sequencer 1 (SS1) FIFO Underflow status. + * @note When the FIFO is empty and a read was requested. + * The problematic read does not move the FIFO pointers, and 0s are returned. + * @param ADCx ADC Instance + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss1_fstat_uv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS1_FSTAT_UV_MSK); +} + +/** + * @brief Get ADC Sample Sequencer 1 (SS1) FIFO Underflow status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_uv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_UV_MSK)>>ADC_SS1_FSTAT_UV_POS); +} + +/** + * @brief Check if ADC Sample Sequencer 1 (SS1) FIFO Underflow status is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss1_fstat_uv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_UV_MSK) == (ADC_SS1_FSTAT_UV_MSK)); +} + +/** + * @brief Get ADC SS1 FIFO Empty status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_empty(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_EMPTY_MSK)>>ADC_SS1_FSTAT_EMPTY_POS); +} + +/** + * @brief Check if ADC SS1 FIFO Empty is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss1_fstat_empty(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_EMPTY_MSK) == (ADC_SS1_FSTAT_EMPTY_MSK)); +} + +/** + * @brief Get ADC SS1 FIFO Head Pointer. + * @note The field contains the current head pointer index, which is the + * next entry to be written to FIFO. + * @param ADCx ADC Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x0F + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_hptr(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_HPTR_MSK)>>ADC_SS1_FSTAT_HPTR_POSS); +} + +/** + * @brief Get ADC SS1 FIFO Tail Pointer. + * @note The field contains the current tail pointer index, which is the + * next entry to be read from FIFO. + * @param ADCx ADC Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x0F + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_fstat_tptr(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_FSTAT, ADC_SS1_FSTAT_TPTR_MSK)>>ADC_SS1_FSTAT_TPTR_POSS); +} + +/** + * @brief Get ADC sample sequencer 1(SS1) Conversion Result Data. + * @note User can read conversion result data by reading this register. + * @param ADCx ADC Instance. + * @retval ADC Sampled Data. + */ +__STATIC_INLINE uint32_t md_adc_get_ss1_data(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADC->SS1_DATA)); +} + +/** + * @brief Set ADC SS2 Trigger Select. + * @note This field selects the trigger source for Sample Sequencer 1. + * @param ADCx ADC Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_SEL_SW + * @arg @ref MD_ADC_SS_CON_SEL_BS16T1 + * @arg @ref MD_ADC_SS_CON_SEL_ALWAYS + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T2 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T3 + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T2 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T3 + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T4 + * @arg @ref MD_ADC_SS_CON_SEL_AD16C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GPIO + * @arg @ref MD_ADC_SS_CON_SEL_CMP0 + * @arg @ref MD_ADC_SS_CON_SEL_CMP1 + * @arg @ref MD_ADC_SS_CON_SEL_CMP2 + * @arg @ref MD_ADC_SS_CON_SEL_CMP3 + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss2_con_sel(ADC_TypeDef *ADCx, uint32_t TrigSource) +{ + MODIFY_REG(ADCx->SS2_CON, ADC_SS2_CON_SEL_MSK, TrigSource<SS2_CON, ADC_SS2_CON_SEL_MSK)>>ADC_SS2_CON_SEL_POSS); +} + +/** + * @brief ADC Sample Sequencer 2 (SS2) Trigger Type select. + * @param ADCx ADC Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_TYP_EDGE + * @arg @ref MD_ADC_SS_COM_TYP_LEVEL + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss2_con_type(ADC_TypeDef *ADCx, uint32_t TrigType) +{ + MODIFY_REG(ADCx->SS2_CON, ADC_SS2_CON_TYP_MSK, TrigType<SS2_CON, ADC_SS2_CON_TYP_MSK)>>ADC_SS2_CON_TYP_POS); +} + +/** + * @brief Set ADC Sample Sequencer 2(SS2) Priority. + * @note This field contains a binary-encoded value specifying the + * priority encoding of SS2. The prioriteies assigned to the + * sequencers must be uniquely mapped. + * @param ADCx ADC Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_PRI_HIGHEST + * @arg @ref MD_ADC_SS_CON_PRI_SECOND + * @arg @ref MD_ADC_SS_CON_PRI_THIRD + * @arg @ref MD_ADC_SS_CON_PRI_LOWEST + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss2_con_pri(ADC_TypeDef *adcx, uint32_t priority) +{ + MODIFY_REG(adcx->SS2_CON, ADC_SS2_CON_PRI_MSK, priority<SS2_CON, ADC_SS2_CON_PRI_MSK)>>ADC_SS2_CON_PRI_POSS); +} + +/** + * @brief Enable One Shot Trigger Mode. + * @note When set HIGH, each trigger will only sample once and use one + * slot in FIFO. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss2_con_one(ADC_TypeDef *adcx) +{ + SET_BIT(adcx->SS2_CON, ADC_SS2_CON_ONE_MSK); +} + +/** + * @brief Disable One Shot Trigger Mode. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss2_con_one(ADC_TypeDef *adcx) +{ + CLEAR_BIT(adcx->SS2_CON, ADC_SS2_CON_ONE_MSK); +} + +/** + * @brief 4th Sample Input Select.. + * @param ADCx ADC Instance + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss2_mux0_mux3(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS2_MUX0, ADC_SS2_MUX0_MUX3_MSK, AdinPin<SS2_MUX0, ADC_SS2_MUX0_MUX3_MSK)>>ADC_SS2_MUX0_MUX3_POSS); +} + +/** + * @brief 3rd Sample Input Select. + * @param ADCx ADC Instance. + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss2_mux0_mux2(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS2_MUX0, ADC_SS2_MUX0_MUX2_MSK, AdinPin<SS2_MUX0, ADC_SS2_MUX0_MUX2_MSK)>>ADC_SS2_MUX0_MUX2_POSS); +} + +/** + * @brief 2nd Sample Input Select. + * @param ADCx ADC Instance. + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss2_mux0_mux1(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS2_MUX0, ADC_SS2_MUX0_MUX1_MSK, AdinPin<SS2_MUX0, ADC_SS2_MUX0_MUX1_MSK)>>ADC_SS2_MUX0_MUX1_POSS); +} + +/** + * @brief 1st Sample Input Select. + * @param ADCx ADC Instance. + * @param ADIN Pin: + * @arg @ref MD_ADC_SS_MUX_ADIN15 + * @arg @ref MD_ADC_SS_MUX_ADIN14 + * @arg @ref MD_ADC_SS_MUX_ADIN13 + * @arg @ref MD_ADC_SS_MUX_ADIN12 + * @arg @ref MD_ADC_SS_MUX_ADIN11 + * @arg @ref MD_ADC_SS_MUX_ADIN10 + * @arg @ref MD_ADC_SS_MUX_ADIN9 + * @arg @ref MD_ADC_SS_MUX_ADIN8 + * @arg @ref MD_ADC_SS_MUX_ADIN7 + * @arg @ref MD_ADC_SS_MUX_ADIN6 + * @arg @ref MD_ADC_SS_MUX_ADIN5 + * @arg @ref MD_ADC_SS_MUX_ADIN4 + * @arg @ref MD_ADC_SS_MUX_ADIN3 + * @arg @ref MD_ADC_SS_MUX_ADIN2 + * @arg @ref MD_ADC_SS_MUX_ADIN1 + * @arg @ref MD_ADC_SS_MUX_ADIN0 + */ +__STATIC_INLINE void md_adc_set_ss2_mux0_mux0(ADC_TypeDef *ADCx, uint32_t AdinPin) +{ + MODIFY_REG(ADCx->SS2_MUX0, ADC_SS2_MUX0_MUX0_MSK, AdinPin<SS2_MUX0, ADC_SS2_MUX0_MUX0_MSK)>>ADC_SS2_MUX0_MUX0_POSS); +} + +/** + * @brief Set ADC_SS2_MUX0 register value. + * @param ADCx ADC Instance. + * @param ADC_SS2_MUX0 Register + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss2_mux0(ADC_TypeDef *ADCx, uint32_t RegValue) +{ + WRITE_REG(ADCx->SS2_MUX0, RegValue); +} + +/** + * @brief Get ADC_SS2_MUX0 register value. + * @param ADCx ADC Instance. + * @retval ADC_SS2_MUX0 Register + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_mux0(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->SS2_MUX0); +} + +/** + * @brief 4th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss2_end_ie3(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS2_END, ADC_SS2_END_IE3_MSK); +} + +/** + * @brief 4th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss2_end_ie3(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS2_END, ADC_SS2_END_IE3_MSK); +} + +/** + * @brief Check if 4th Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss2_end_ie3(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_END, ADC_SS2_END_IE3_MSK) == (ADC_SS2_END_IE3_MSK)); +} + +/** + * @brief 3rd Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss2_end_ie2(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS2_END, ADC_SS2_END_IE2_MSK); +} + +/** + * @brief 3rd Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss2_end_ie2(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS2_END, ADC_SS2_END_IE2_MSK); +} + +/** + * @brief Check if 3rd Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss2_end_ie2(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_END, ADC_SS2_END_IE2_MSK) == (ADC_SS2_END_IE2_MSK)); +} + +/** + * @brief 2nd Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss2_end_ie1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS1_END, ADC_SS2_END_IE1_MSK); +} + +/** + * @brief 2nd Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss2_end_ie1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS2_END, ADC_SS2_END_IE1_MSK); +} + +/** + * @brief Check if 2nd Sample Interrupt Enable is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss2_end_ie1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS1_END, ADC_SS2_END_IE1_MSK) == (ADC_SS2_END_IE1_MSK)); +} + +/** + * @brief 1st Sample Interrupt Enable + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss2_end_ie0(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS2_END, ADC_SS2_END_IE0_MSK); +} + +/** + * @brief 4th Sample Interrupt Disable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss2_end_ie0(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS2_END, ADC_SS2_END_IE0_MSK); +} + +/** + * @brief Check if 1st Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss2_end_ie0(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_END, ADC_SS2_END_IE0_MSK) == (ADC_SS2_END_IE0_MSK)); +} + +/** + * @brief Set ADC SS2 END sample. + * @param ADCx ADC Instance. + * @param End Value Min_Value=0x00 Max_Value=0x03 + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss2_end_end(ADC_TypeDef *ADCx, uint32_t EndValue) +{ + MODIFY_REG(ADCx->SS2_END, ADC_SS2_END_END_MSK, EndValue<SS2_END, ADC_SS2_END_END_MSK)>>ADC_SS2_END_END_POSS); +} + +/** + * @brief Set ADC_SS2_End Control Register. + * @param ADCx ADC Instance. + * @param ADC_SS2_End Register Value. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss2_end(ADC_TypeDef *ADCx, uint32_t RegValue) +{ + MODIFY_REG(ADCx->SS2_END, ADC_SS2_END_END_MSK, RegValue); +} + +/** + * @brief Get ADC_SS2_End Control Register. + * @param ADCx ADC Instance. + * @retval ADC_SS2_End Register Value. + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_end(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->SS2_END); +} + +/** + * @brief Set ADC Sample Sequencer 2(SS2) FIFO Overflow status. + * @note When the FIFO is full and a write was requested, the + * most recent write is dropped. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss2_fstat_ov(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS2_END, ADC_SS2_FSTAT_OV_MSK); +} + +/** + * @brief Get ADC Sample Sequencer 2(SS2) FIFO Overflow status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_ov(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_OV_MSK)>>ADC_SS2_FSTAT_OV_POS); +} + +/** + * @brief Check if ADC Sample Sequencer 2(SS2) FIFO Overflow status is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss2_fstat_ov(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_OV_MSK) == (ADC_SS2_FSTAT_OV_MSK)); +} + +/** + * @brief Get ADC SS2 FIFO Full status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_full(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_FULL_MSK)>>ADC_SS2_FSTAT_FULL_POS); +} + +/** + * @brief Check if ADC SS2 FIFO Full is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss2_fstat_full(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_FULL_MSK) == (ADC_SS2_FSTAT_FULL_MSK)); +} + +/** + * @brief Set ADC Sample Sequencer 2(SS2) FIFO Underflow status. + * @note When the FIFO is empty and a read was requested. + * The problematic read does not move the FIFO pointers, and 0s are returned. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss2_fstat_uv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS2_END, ADC_SS2_FSTAT_UV_MSK); +} + +/** + * @brief Get ADC Sample Sequencer 2(SS2) FIFO Underflow status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_uv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_UV_MSK)>>ADC_SS2_FSTAT_UV_POS); +} + +/** + * @brief Check if ADC Sample Sequencer 2(SS2) FIFO Underflow status is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss2_fstat_uv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_UV_MSK) == (ADC_SS2_FSTAT_UV_MSK)); +} + +/** + * @brief Get ADC SS2 FIFO Empty status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_empty(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_EMPTY_MSK)>>ADC_SS2_FSTAT_EMPTY_POS); +} + +/** + * @brief Check if ADC SS2 FIFO Empty is actived. + * @param ADCx ADC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss2_fstat_empty(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_EMPTY_MSK) == (ADC_SS2_FSTAT_EMPTY_MSK)); +} + +/** + * @brief Get ADC SS2 FIFO Head Pointer. + * @param ADCx ADC Instance. + * @retval Return value between Min_Data=0x00 and Max_Data=0x0F. + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_hptr(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_HPTR_MSK)>>ADC_SS2_FSTAT_HPTR_POSS); +} + +/** + * @brief Get ADC SS2 FSTAT TPTR + * @param ADCx ADC Instance + * @retval Return value between Min_Data=0x00 and Max_Data=0x0F. + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_fstat_tptr(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS2_FSTAT, ADC_SS2_FSTAT_TPTR_MSK)>>ADC_SS2_FSTAT_TPTR_POSS); +} + +/** + * @brief Get ADC sample sequencer 2(SS2) Conversion Result Data. + * @note User can read conversion result data by reading this register. + * @param ADCx ADC Instance. + * @retval ADC Sampled Data. + */ +__STATIC_INLINE uint32_t md_adc_get_ss2_data(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADC->SS2_DATA)); +} + +/** + * @brief Set SS3 Trigger Select. + * @note This field selects the trigger source for Sample Sequencer 3. + * @param ADCx ADC Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_SEL_SW + * @arg @ref MD_ADC_SS_CON_SEL_BS16T1 + * @arg @ref MD_ADC_SS_CON_SEL_ALWAYS + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T2 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C4T3 + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T2 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T3 + * @arg @ref MD_ADC_SS_CON_SEL_GP32C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GP16C2T4 + * @arg @ref MD_ADC_SS_CON_SEL_AD16C4T1 + * @arg @ref MD_ADC_SS_CON_SEL_GPIO + * @arg @ref MD_ADC_SS_CON_SEL_CMP0 + * @arg @ref MD_ADC_SS_CON_SEL_CMP1 + * @arg @ref MD_ADC_SS_CON_SEL_CMP2 + * @arg @ref MD_ADC_SS_CON_SEL_CMP3 + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss3_con_sel(ADC_TypeDef *ADCx, uint32_t TrigSource) +{ + MODIFY_REG(ADCx->SS3_CON, ADC_SS3_CON_SEL_MSK, TrigSource<SS3_CON, ADC_SS3_CON_SEL_MSK)>>ADC_SS3_CON_SEL_POSS); +} + +/** + * @brief ADC Sample Sequencer 2 (SS2) Trigger Type select. + * @param ADCx ADC Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_TYP_EDGE + * @arg @ref MD_ADC_SS_COM_TYP_LEVEL + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss3_con_type(ADC_TypeDef *ADCx, uint32_t TrigType) +{ + MODIFY_REG(ADCx->SS3_CON, ADC_SS3_CON_TYP_MSK, TrigType<SS3_CON, ADC_SS3_CON_TYP_MSK)>>ADC_SS3_CON_TYP_POS); +} + +/** + * @brief Set ADC Sample Sequencer 3(SS3) Priority. + * @note This field contains a binary-encoded value specifying the + * priority encoding of SS2. The prioriteies assigned to the + * sequencers must be uniquely mapped. + * @param ADCx ADC Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_ADC_SS_CON_PRI_HIGHEST + * @arg @ref MD_ADC_SS_CON_PRI_SECOND + * @arg @ref MD_ADC_SS_CON_PRI_THIRD + * @arg @ref MD_ADC_SS_CON_PRI_LOWEST + * @retval None + */ +__STATIC_INLINE void md_adc_set_ss3_con_pri(ADC_TypeDef *adcx, uint32_t priority) +{ + MODIFY_REG(adcx->SS3_CON, ADC_SS3_CON_PRI_MSK, priority<SS3_CON, ADC_SS3_CON_PRI_MSK)>>ADC_SS3_CON_PRI_POSS); +} + +/** + * @brief Enable ADC sample sequencer 3(SS3) one shot mode. + * @note When set HIGH, each trigger will only sample once and use one + * slot in FIFO. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss3_con_one(ADC_TypeDef *adcx) +{ + SET_BIT(adcx->SS3_CON, ADC_SS3_CON_ONE_MSK); +} + +/** + * @brief Disable ADC sample sequencer 3(SS3) one shot mode. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss3_con_one(ADC_TypeDef *adcx) +{ + CLEAR_BIT(adcx->SS3_CON, ADC_SS3_CON_ONE_MSK); +} + +/** + * @brief Enable ADC SS3 1th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_enable_ss3_end_ie0(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS3_END, ADC_SS3_END_IE0_MSK); +} + +/** + * @brief Disable ADC SS3 1th Sample Interrupt Enable. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_disable_ss3_end_ie0(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->SS3_END, ADC_SS3_END_IE0_MSK); +} + +/** + * @brief Check if ADC SS3 1th Sample Interrupt is enabled. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_enabled_ss3_end_ie0(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_END, ADC_SS3_END_IE0_MSK) == (ADC_SS3_END_IE0_MSK)); +} + +/** + * @brief Set ADC SS3 END sample. + * @param ADCx ADC Instance. + * @param End Value Min_Value=0x00 Max_Value=0x01. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss3_end_end(ADC_TypeDef *ADCx, uint32_t EndValue) +{ + MODIFY_REG(ADCx->SS3_END, ADC_SS3_END_END_MSK, EndValue<SS3_END, ADC_SS3_END_END_MSK)>>ADC_SS3_END_END_POS); +} + +/** + * @brief Set ADC_SS3_End Control Register. + * @param ADCx ADC Instance. + * @param ADC_SS3_END Register Value. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss3_end(ADC_TypeDef *ADCx, uint32_t RegValue) +{ + MODIFY_REG(ADCx->SS2_END, ADC_SS3_END_END_MSK, RegValue); +} + +/** + * @brief Get ADC_SS3_End Control Register + * @param ADCx ADC Instance. + * @retval ADC_SS3_End Register Value. + */ +__STATIC_INLINE uint32_t md_adc_get_ss3_end(ADC_TypeDef *ADCx) +{ + return READ_REG(ADCx->SS3_END); +} + +/** + * @brief Set ADC Sample Sequencer 3 (SS3) FIFO Overflow status. + * @note When the FIFO is full and a write was requested, the + * most recent write is dropped. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss3_fstat_ov(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS3_END, ADC_SS3_FSTAT_OV_MSK); +} + +/** + * @brief Get ADC Sample Sequencer 3 (SS3) FIFO Overflow status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss3_fstat_ov(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_OV_MSK)>>ADC_SS3_FSTAT_OV_POS); +} + +/** + * @brief Check if ADC Sample Sequencer 3 (SS3) FIFO Overflow status is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss3_fstat_ov(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_OV_MSK) == (ADC_SS3_FSTAT_OV_MSK)); +} + +/** + * @brief Get ADC SS3 FIFO Full status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss3_fstat_full(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_FULL_MSK)>>ADC_SS3_FSTAT_FULL_POS); +} + +/** + * @brief Check if ADC SS3 FIFO Full status is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss3_fstat_full(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_FULL_MSK) == (ADC_SS3_FSTAT_FULL_MSK)); +} + +/** + * @brief Set ADC Sample Sequencer 3 (SS3) FIFO Underflow status. + * @note When the FIFO is empty and a read was requested. + * The problematic read does not move the FIFO pointers, and 0s are returned. + * @param ADCx ADC Instance. + * @retval None. + */ +__STATIC_INLINE void md_adc_set_ss3_fstat_uv(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->SS3_END, ADC_SS3_FSTAT_UV_MSK); +} + +/** + * @brief Get ADC Sample Sequencer 3 (SS3) FIFO Underflow status. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss3_fstat_uv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_UV_MSK)>>ADC_SS3_FSTAT_UV_POS); +} + +/** + * @brief Check if ADC Sample Sequencer 3 (SS3) FIFO Underflow status is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss3_fstat_uv(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_UV_MSK) == (ADC_SS3_FSTAT_UV_MSK)); +} + +/** + * @brief Get ADC SS3 FIFO Empty. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_get_ss3_fstat_empty(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_EMPTY_MSK)>>ADC_SS3_FSTAT_EMPTY_POS); +} + +/** + * @brief Check if ADC SS3 FIFO Empty is actived. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_adc_is_active_flag_ss3_fstat_empty(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_EMPTY_MSK) == (ADC_SS3_FSTAT_EMPTY_MSK)); +} + +/** + * @brief Get ADC SS3 FIFO Head Pointer. + * @param ADCx ADC Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x01. + */ +__STATIC_INLINE uint32_t md_adc_get_ss23_fstat_hptr(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_HPTR_MSK)>>ADC_SS3_FSTAT_HPTR_POSS); +} + +/** + * @brief Get ADC SS3 FIFO Tail Pointer. + * @param ADCx ADC Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x01. + */ +__STATIC_INLINE uint32_t md_adc_get_ss3_fstat_tptr(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SS3_FSTAT, ADC_SS3_FSTAT_TPTR_MSK)>>ADC_SS3_FSTAT_TPTR_POSS); +} + +/** + * @brief Get ADC sample sequencer 3(SS3) Conversion Result Data. + * @note User can read conversion result data by reading this register. + * @param ADCx ADC Instance. + * @retval ADC Sampled Data. + */ +__STATIC_INLINE uint32_t md_adc_get_ss3_data(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_REG(ADC->SS3_DATA)); +} + +/** @defgroup MD_ADC_PM_WRITE_READ Common Write and read registers Macros + * @} + */ +#endif + +void md_adc_init(ADC_TypeDef *ADCx, md_adc_inittypedef *ADC_InitStruct,uint8_t *); +void md_adc_calibration_data(double, double ,double * ,double *); +void md_adc_get_data(uint8_t, double, double, uint16_t *); +/** + * @} MD_ADC_Public_Macros + */ + +/** @} ADC + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_aes.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_aes.h new file mode 100644 index 0000000000000000000000000000000000000000..e4e16693d54de70434bfb43f83a617e45e2195b6 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_aes.h @@ -0,0 +1,941 @@ +/** + ****************************************************************************** + * @file md_aes.h + * @brief M601 AES Head File. + * + * @version V0.01 + * @date 28/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_AES_H__ +#define __MD_AES_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (AES) + +/** @defgroup AES AES + * @brief AES micro driver + * @{ + */ + +/* Private Types --------------------------------------------------------------*/ +/* Private Variables ----------------------------------------------------------*/ +/* Private Macros -------------------------------------------------------------*/ +/* Public Types ---------------------------------------------------------------*/ +/** @defgroup MD_AES_INIT AES public init structure + * @brief + * @{ + */ +typedef struct +{ + volatile uint8_t aes_con_bl; + volatile uint8_t aes_con_mode; + volatile uint32_t aes_key[4]; + volatile uint32_t aes_iv[4]; + volatile uint32_t aes_din[4]; + volatile uint32_t aes_dout[4]; +} md_aes_init_typedef; +/** + * @} MD_AES_INIT + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_AES_Public_Constants AES Public Constants + * @brief + * @{ + */ + +/** @defgroup MD_AES_CON_registers AES Control Registers + * @brief + * @{ + */ +#define MD_AES_CON_READY_BUSY 0 /*!< This allow user to read AES Encryption/Decryption Ready Status. */ +#define MD_AES_CON_READY_READY 1 /*!< This allow user to read AES Encryption/Decryption Ready Status. */ +#define MD_AES_CON_OT_DMA_ST_PASS 1 /*!< This allow user to read AES DMA Output Status. */ +#define MD_AES_CON_OT_DMA_ST_FAIL 0 /*!< This allow user to read AES DMA Output Status. */ +#define MD_AES_CON_IT_DMA_ST_PASS 1 /*!< This allow user to read AES DMA Input Status. */ +#define MD_AES_CON_IT_DMA_ST_FAIL 0 /*!< This allow user to read AES DMA Input Status. */ +#define MD_AES_CON_OT_DEPTH_0 0 /*!< This allow user to read AES DIO data depth status (X=0). */ +#define MD_AES_CON_OT_DEPTH_1 1 /*!< This allow user to read AES DIO data depth status (X=1). */ +#define MD_AES_CON_OT_DEPTH_2 2 /*!< This allow user to read AES DIO data depth status (X=2). */ +#define MD_AES_CON_OT_DEPTH_3 3 /*!< This allow user to read AES DIO data depth status (X=3). */ +#define MD_AES_CON_IT_DEPTH_0 0 /*!< This allow user to read AES DIO data depth status (X=0). */ +#define MD_AES_CON_IT_DEPTH_1 1 /*!< This allow user to read AES DIO data depth status (X=1). */ +#define MD_AES_CON_IT_DEPTH_2 2 /*!< This allow user to read AES DIO data depth status (X=2). */ +#define MD_AES_CON_IT_DEPTH_3 3 /*!< This allow user to read AES DIO data depth status (X=3). */ +#define MD_AES_CON_RE_INIT_SET 1 /*!< This allow user to set AES Re-initial. */ +#define MD_AES_CON_RE_INIT_UNSET 0 /*!< This allow user to set AES Re-initial. */ +#define MD_AES_CON_DMA_EN_INPUT_ENABLE (1 << 0) /*!< This allow user to set AES DMA Function Enable. 0:AES input DMA disable */ +#define MD_AES_CON_DMA_EN_INPUT_DISABLE (0 << 0) /*!< This allow user to set AES DMA Function Enable. 1:AES input DMA enable */ +#define MD_AES_CON_DMA_EN_OUTPUT_ENABLE (1 << 1 /*!< This allow user to set AES DMA Function Enable. 0:AES output DMA disable */ +#define MD_AES_CON_DMA_EN_OUTPUT_DISABLE (0 << 1) /*!< This allow user to set AES DMA Function Enable. 1:AES outut DMA enable */ +#define MD_AES_CON_BL_CBC 0 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 000:CBC */ +#define MD_AES_CON_BL_CFB 1 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 001:CFB */ +#define MD_AES_CON_BL_OFB 2 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 010:OFB */ +#define MD_AES_CON_BL_CTR 3 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 011:CTR */ +#define MD_AES_CON_BL_ECB 4 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 100:ECB */ +#define MD_AES_CON_BL_GCM 5 /*!< This allow user to set Block Cipher Encryption / Decryption Mode. 101:GCM */ +#define MD_AES_CON_REV_NORMAL 0 /*!< This allow user to set AES Input Reverse. 0:Normal Mode */ +#define MD_AES_CON_REV_REVERSE 1 /*!< This allow user to set AES Input Reverse. 1:KEY, IV, DI, DO Byte Reverse Mode */ +#define MD_AES_CON_MODE_ENCRYPT 0 /*!< This allow user to set AES Mode Control. 0:Encryption Mode */ +#define MD_AES_CON_MODE_DECRYPT 1 /*!< This allow user to set AES Mode Control. 1:Decryption Mode */ +#define MD_AES_CON_START 1 /*!< This allow user to set AES Start. AES function will start after this bit is set to 1. */ +/** + * @} MD_AES_CON_registers + */ + +/** @defgroup MD_AES_IER_registers AES Interrupt Enable Registers + * @brief + * @{ + */ +#define MD_AES_IER_DECIE 1 /*!< This allow user to set AES Decryption Interrupt Enable. */ +#define MD_AES_IER_ENCIE 1 /*!< This allow user to set AES Encryption Interrupt Enable. */ +/** + * @} MD_AES_IER_registers + */ + +/** @defgroup MD_AES_IDR_registers AES Interrupt Disable Registers + * @brief + * @{ + */ +#define MD_AES_IDR_DECID 1 /*!< This allow user to set AES Decryption Interrupt Disable. */ +#define MD_AES_IDR_ENCID 1 /*!< This allow user to set AES Encryption Interrupt Disable. */ +/** + * @} MD_AES_IDR_registers + */ + +/** @defgroup MD_AES_IVS_registers AES Interrupt Valid Status Registers + * @brief + * @{ + */ +#define MD_AES_IVS_DECIVS_DISABLE 0 /*!< This allow user to set AES Decryption Interrupt Valid Status. 0:AES Decryption interrupt is disabled. */ +#define MD_AES_IVS_DECIVS_ENABLE 1 /*!< This allow user to set AES Decryption Interrupt Valid Status. 1:AES Decryption interrupt is enabled. */ +#define MD_AES_IVS_ENCIVS_DISABLE 0 /*!< This allow user to set AES Encryption Interrupt Valid Status. 0:AES Encryption interrupt is disabled. */ +#define MD_AES_IVS_ENCIVS_ENABLE 1 /*!< This allow user to set AES Encryption Interrupt Valid Status. 1:AES Encryption interrupt is enabled. */ +/** + * @} MD_AES_IVS_registers + */ + +/** @defgroup MD_AES_RIF_registers AES Raw Interrupt Flag Registers + * @brief + * @{ + */ +#define MD_AES_RIF_DECRIF_NO_INTERRUPT 0 /*!< This allow user to set AES Decryption Raw Interrupt Flag Status. 0: No interrupt. */ +#define MD_AES_RIF_DECRIF_INTERRUPT 1 /*!< This allow user to set AES Decryption Raw Interrupt Flag Status. 1: AES Decryption interrupt is asserting. */ +#define MD_AES_RIF_ENCRIF_NO_INTERRUPT 0 /*!< This allow user to set AES Encryption Raw Interrupt Flag Status. 0: No interrupt. */ +#define MD_AES_RIF_ENCRIF_INTERRUPT 1 /*!< This allow user to set AES Encryption Raw Interrupt Flag Status. 1: AES Encryption interrupt is asserting. */ +/** + * @} MD_AES_RIF_registers + */ + +/** @defgroup MD_AES_IFM_registers AES Interrupt Flag Mask Registers + * @brief + * @{ + */ +#define MD_AES_IFM_DECRIF_MASK 0 /*!< This allow user to set AES Decryption Interrupt Flag Masked Status. 0: No interrupt or the interrupt has been masked. */ +#define MD_AES_IFM_DECRIF_SIGNAL 1 /*!< This allow user to set AES Decryption Interrupt Flag Masked Status. 1: AES Decryption interrupt has been signalled. */ +#define MD_AES_IFM_ENCRIF_MASK 0 /*!< This allow user to set AES Encryption Interrupt Flag Masked Status. 0: No interrupt or the interrupt has been masked. */ +#define MD_AES_IFM_ENCRIF_SIGNAL 1 /*!< This allow user to set AES Encryption Interrupt Flag Masked Status. 1: AES Encryption interrupt has been signalled. */ +/** + * @} MD_AES_IFM_registers + */ + +/** @defgroup MD_AES_ICR_registers AES Interrupt Clear Registers + * @brief + * @{ + */ +#define MD_AES_ICR_DECICR 1 /*!< This allow user to set AES Decryption Interrupt Clear. User can set this bit to clear AES Decryption interrupt status. */ +#define MD_AES_ICR_ENCICR 1 /*!< This allow user to set AES Decryption Interrupt Clear. User can set this bit to clear AES Encryption interrupt status. */ +/** + * @} MD_AES_ICR_registers + */ + +/** + * @} MD_AES_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_AES_Public_Macros AES Public Macros + * @brief + * @{ + */ + +/** + * @brief AES Control Register + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_READY_BUSY 0 + * @arg @ref MD_AES_CON_READY_READY 1 + * @arg @ref MD_AES_CON_OT_DMA_ST_PASS 1 + * @arg @ref MD_AES_CON_OT_DMA_ST_FAIL 0 + * @arg @ref MD_AES_CON_IT_DMA_ST_PASS 1 + * @arg @ref MD_AES_CON_IT_DMA_ST_FAIL 0 + * @arg @ref MD_AES_CON_OT_DEPTH_0 0 + * @arg @ref MD_AES_CON_OT_DEPTH_1 1 + * @arg @ref MD_AES_CON_OT_DEPTH_2 2 + * @arg @ref MD_AES_CON_OT_DEPTH_3 3 + * @arg @ref MD_AES_CON_IT_DEPTH_0 0 + * @arg @ref MD_AES_CON_IT_DEPTH_1 1 + * @arg @ref MD_AES_CON_IT_DEPTH_2 2 + * @arg @ref MD_AES_CON_IT_DEPTH_3 3 + * @arg @ref MD_AES_CON_RE_INIT_SET 1 + * @arg @ref MD_AES_CON_RE_INIT_UNSET 0 + * @arg @ref MD_AES_CON_DMA_EN_INPUT_ENABLE (1 << 0) + * @arg @ref MD_AES_CON_DMA_EN_INPUT_DISABLE (0 << 0) + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_ENABLE (1 << 1) + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_DISABLE (0 << 1) + * @arg @ref MD_AES_CON_BL_CBC 0 + * @arg @ref MD_AES_CON_BL_CFB 1 + * @arg @ref MD_AES_CON_BL_OFB 2 + * @arg @ref MD_AES_CON_BL_CTR 3 + * @arg @ref MD_AES_CON_BL_ECB 4 + * @arg @ref MD_AES_CON_BL_GCM 5 + * @arg @ref MD_AES_CON_REV_NORMAL 0 + * @arg @ref MD_AES_CON_REV_REVERSE 1 + * @arg @ref MD_AES_CON_MODE_ENCRYPT 0 + * @arg @ref MD_AES_CON_MODE_DECRYPT 1 + * @arg @ref MD_AES_CON_START 1 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_con(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->CON, value); +} + +/** + * @brief AES Control Register + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_READY_BUSY 0 + * @arg @ref MD_AES_CON_READY_READY 1 + * @arg @ref MD_AES_CON_OT_DMA_ST_PASS 1 + * @arg @ref MD_AES_CON_OT_DMA_ST_FAIL 0 + * @arg @ref MD_AES_CON_IT_DMA_ST_PASS 1 + * @arg @ref MD_AES_CON_IT_DMA_ST_FAIL 0 + * @arg @ref MD_AES_CON_OT_DEPTH_0 0 + * @arg @ref MD_AES_CON_OT_DEPTH_1 1 + * @arg @ref MD_AES_CON_OT_DEPTH_2 2 + * @arg @ref MD_AES_CON_OT_DEPTH_3 3 + * @arg @ref MD_AES_CON_IT_DEPTH_0 0 + * @arg @ref MD_AES_CON_IT_DEPTH_1 1 + * @arg @ref MD_AES_CON_IT_DEPTH_2 2 + * @arg @ref MD_AES_CON_IT_DEPTH_3 3 + * @arg @ref MD_AES_CON_RE_INIT_SET 1 + * @arg @ref MD_AES_CON_RE_INIT_UNSET 0 + * @arg @ref MD_AES_CON_DMA_EN_INPUT_ENABLE (1 << 0) + * @arg @ref MD_AES_CON_DMA_EN_INPUT_DISABLE (0 << 0) + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_ENABLE (1 << 1) + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_DISABLE (0 << 1) + * @arg @ref MD_AES_CON_BL_CBC 0 + * @arg @ref MD_AES_CON_BL_CFB 1 + * @arg @ref MD_AES_CON_BL_OFB 2 + * @arg @ref MD_AES_CON_BL_CTR 3 + * @arg @ref MD_AES_CON_BL_ECB 4 + * @arg @ref MD_AES_CON_BL_GCM 5 + * @arg @ref MD_AES_CON_REV_NORMAL 0 + * @arg @ref MD_AES_CON_REV_REVERSE 1 + * @arg @ref MD_AES_CON_MODE_ENCRYPT 0 + * @arg @ref MD_AES_CON_MODE_DECRYPT 1 + * @arg @ref MD_AES_CON_START 1 + */ +__STATIC_INLINE uint32_t md_aes_get_con(AES_TypeDef *aes) +{ + return (READ_REG(aes->CON)); +} + +/** + * @brief AES Encryption / Decryption Ready Status + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_READY_BUSY 0 + * @arg @ref MD_AES_CON_READY_READY 1 + */ +__STATIC_INLINE uint32_t md_aes_get_con_ready(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_READY_MSK) >> AES_CON_READY_POS) & 0x1); +} + +/** + * @brief AES DMA Output Status + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_OT_DMA_ST_PASS 0 + * @arg @ref MD_AES_CON_OT_DMA_ST_FAIL 1 + */ +__STATIC_INLINE uint32_t md_aes_get_con_ot_dma_st(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_OT_DMA_ST_MSK) >> AES_CON_OT_DMA_ST_POS) & 0x1); +} + +/** + * @brief AES DMA Intput Status + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_IT_DMA_ST_PASS 0 + * @arg @ref MD_AES_CON_IT_DMA_ST_FAIL 1 + */ +__STATIC_INLINE uint32_t md_aes_get_con_it_dma_st(AES_TypeDef *aes, uint32_t value) +{ + return ((READ_BIT(aes->CON, AES_CON_IT_DMA_ST_MSK) >> AES_CON_IT_DMA_ST_POS) & 0x1); +} + +/** + * @brief AES DIO data depth status (X=0,1,2,3) + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_OT_DEPTH_0 0 + * @arg @ref MD_AES_CON_OT_DEPTH_1 1 + * @arg @ref MD_AES_CON_OT_DEPTH_2 2 + * @arg @ref MD_AES_CON_OT_DEPTH_3 3 + */ +__STATIC_INLINE uint32_t md_aes_get_con_ot_depth(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_OT_DEPTH_MSK) >> AES_CON_OT_DEPTH_POSS) & 0x3); +} + +/** + * @brief AES DIO data depth status (X=0,1,2,3) + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_IT_DEPTH_0 0 + * @arg @ref MD_AES_CON_IT_DEPTH_1 1 + * @arg @ref MD_AES_CON_IT_DEPTH_2 2 + * @arg @ref MD_AES_CON_IT_DEPTH_3 3 + */ +__STATIC_INLINE uint32_t md_aes_get_con_it_depth(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_IT_DEPTH_MSK) >> AES_CON_IT_DEPTH_POSS) & 0x3); +} + +/** + * @brief AES Re-initial + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_RE_INIT_SET 1 + * @arg @ref MD_AES_CON_RE_INIT_UNSET 0 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_con_re_init(AES_TypeDef *aes, uint32_t value) +{ + MODIFY_REG(aes->CON, AES_CON_RE_INIT_MSK, (value << AES_CON_RE_INIT_POS)); +} + +/** + * @brief AES Re-initial + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_RE_INIT_SET 1 + * @arg @ref MD_AES_CON_RE_INIT_UNSET 0 + */ +__STATIC_INLINE uint32_t md_aes_get_con_re_init(AES_TypeDef *aes) +{ + + return ((READ_BIT(aes->CON, AES_CON_RE_INIT_MSK) >> AES_CON_RE_INIT_POS) & 0x1); +} + +/** + * @brief AES DMA Function Enable + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_DMA_EN_INPUT_ENABLE (1 << 0) + * @arg @ref MD_AES_CON_DMA_EN_INPUT_DISABLE (0 << 0) + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_ENABLE (1 << 1) + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_DISABLE (0 << 1) + * @retval None. + */ +__STATIC_INLINE void md_aes_set_con_dma_en(AES_TypeDef *aes, uint32_t value) +{ + MODIFY_REG(aes->CON, AES_CON_DMA_EN_MSK, (value << AES_CON_DMA_EN_POSS)); +} + +/** + * @brief AES DMA Function Enable + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_DMA_EN_INPUT_ENABLE (1 << 0) + * @arg @ref MD_AES_CON_DMA_EN_INPUT_DISABLE (0 << 0) + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_ENABLE (1 << 1) + * @arg @ref MD_AES_CON_DMA_EN_OUTPUT_DISABLE (0 << 1) + */ +__STATIC_INLINE uint32_t md_aes_get_con_dma_en(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_DMA_EN_MSK) >> AES_CON_DMA_EN_POSS) & 0x3); +} + +/** + * @brief Block Cipher Encryption / Decryption Mode + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_BL_CBC 0 + * @arg @ref MD_AES_CON_BL_CFB 1 + * @arg @ref MD_AES_CON_BL_OFB 2 + * @arg @ref MD_AES_CON_BL_CTR 3 + * @arg @ref MD_AES_CON_BL_ECB 4 + * @arg @ref MD_AES_CON_BL_GCM 5 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_con_bl(AES_TypeDef *aes, uint32_t value) +{ + MODIFY_REG(aes->CON, AES_CON_BL_MSK, (value << AES_CON_BL_POSS)); +} + +/** + * @brief Block Cipher Encryption / Decryption Mode + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_BL_CBC 0 + * @arg @ref MD_AES_CON_BL_CFB 1 + * @arg @ref MD_AES_CON_BL_OFB 2 + * @arg @ref MD_AES_CON_BL_CTR 3 + * @arg @ref MD_AES_CON_BL_ECB 4 + * @arg @ref MD_AES_CON_BL_GCM 5 + */ +__STATIC_INLINE uint32_t md_aes_get_con_bl(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_BL_MSK) >> AES_CON_BL_POSS) & 0x7); +} + +/** + * @brief AES Input Reverse + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_REV_NORMAL 0 + * @arg @ref MD_AES_CON_REV_REVERSE 1 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_con_rev(AES_TypeDef *aes, uint32_t value) +{ + MODIFY_REG(aes->CON, AES_CON_REV_MSK, (value << AES_CON_REV_POS)); +} + +/** + * @brief AES Input Reverse + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_REV_NORMAL 0 + * @arg @ref MD_AES_CON_REV_REVERSE 1 + */ +__STATIC_INLINE uint32_t md_aes_get_con_rev(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_REV_MSK) >> AES_CON_REV_POS) & 0x1); +} + +/** + * @brief AES Mode Control + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_MODE_ENCRYPT 0 + * @arg @ref MD_AES_CON_MODE_DECRYPT 1 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_con_mode(AES_TypeDef *aes, uint32_t value) +{ + MODIFY_REG(aes->CON, AES_CON_MODE_MSK, (value << AES_CON_MODE_POS)); +} + +/** + * @brief AES Mode Control + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_MODE_ENCRYPT 0 + * @arg @ref MD_AES_CON_MODE_DECRYPT 1 + */ +__STATIC_INLINE uint32_t md_aes_get_con_mode(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_MODE_MSK) >> AES_CON_MODE_POS) & 0x1); +} + +/** + * @brief AES Start + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_START 1 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_con_start(AES_TypeDef *aes, uint32_t value) +{ + MODIFY_REG(aes->CON, AES_CON_START_MSK, (value << AES_CON_START_POS)); +} + +/** + * @brief AES Start + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_CON_START 1 + */ +__STATIC_INLINE uint32_t md_aes_get_con_start(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->CON, AES_CON_START_MSK) >> AES_CON_START_POS) & 0x1); +} + +/** + * @brief AES Interrupt Enable Register + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_IER_DECIE 1 + * @arg @ref MD_AES_IER_ENCIE 1 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_ier(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IER, value); +} + +/** + * @brief AES Decryption Interrupt Enable + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_enable_ier_decie(AES_TypeDef *aes) +{ + MODIFY_REG(aes->IER, AES_IER_DECIE_MSK, (1 << AES_IER_DECIE_POS)); +} + +/** + * @brief AES Encryption Interrupt Enable + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_enable_ier_encie(AES_TypeDef *aes) +{ + MODIFY_REG(aes->IER, AES_IER_ENCIE_MSK, (1 << AES_IER_ENCIE_POS)); +} + +/** + * @brief AES Interrupt Disable Register + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_AES_IDR_DECID 1 + * @arg @ref MD_AES_IDR_ENCID 1 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_idr(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IDR, value); +} + +/** + * @brief AES Decryption Interrupt Disable + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_disable_idr_decid(AES_TypeDef *aes) +{ + MODIFY_REG(aes->IDR, AES_IDR_DECID_MSK, (1 << AES_IDR_DECID_POS)); +} + +/** + * @brief AES Encryption Interrupt Disable + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_disable_idr_encid(AES_TypeDef *aes) +{ + MODIFY_REG(aes->IDR, AES_IDR_DECID_MSK, (1 << AES_IDR_DECID_POS)); +} + +/** + * @brief AES Interrupt Valid Status Register + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @ref MD_AES_IVS_DECIVS_DISABLE 0 + * @arg @ref MD_AES_IVS_DECIVS_ENABLE 1 + * @arg @ref MD_AES_IVS_ENCIVS_DISABLE 0 + * @arg @ref MD_AES_IVS_ENCIVS_ENABLE 1 + */ +__STATIC_INLINE uint32_t md_aes_get_ivs(AES_TypeDef *aes) +{ + return (READ_REG(aes->IVS)); +} + +/** + * @brief AES Decryption Interrupt Valid Status + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg value true, false + */ +__STATIC_INLINE bool md_aes_is_enabled_ivs_decivs(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->IVS, AES_IVS_DECIVS_MSK) >> AES_IVS_DECIVS_POS) & 0x1) ? true : false; +} + +/** + * @brief AES Encryption Interrupt Valid Status + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg value true, false + */ +__STATIC_INLINE bool md_aes_is_enabled_ivs_encivs(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->IVS, AES_IVS_ENCIVS_MSK) >> AES_IVS_ENCIVS_POS) & 0x1) ? true : false; +} + +/** + * @brief AES Raw Interrupt Flag Status + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @reg MD_AES_RIF_DECRIF_NO_INTERRUPT 0 + * @arg @reg MD_AES_RIF_DECRIF_INTERRUPT 1 + */ +__STATIC_INLINE uint32_t md_aes_get_rif(AES_TypeDef *aes) +{ + return (READ_REG(aes->RIF)); +} + +/** + * @brief AES Encryption Raw Interrupt Flag Status + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg value true, false + */ +__STATIC_INLINE bool md_aes_is_active_rif_decrif(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->RIF, AES_RIF_DECRIF_MSK) >> AES_RIF_DECRIF_POS) & 0x1) ? true : false; +} + +/** + * @brief AES Encryption Raw Interrupt Flag Status + * @param Mode This parameter can be one of the following values: + * @arg value true, false + * @retval None. + */ +__STATIC_INLINE bool md_aes_is_active_rif_encrif(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->RIF, AES_RIF_ENCRIF_MSK) >> AES_RIF_ENCRIF_POS) & 0x1) ? true : false; +} + +/** + * @brief AES Interrupt Flag Mask Status Register + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg @reg MD_AES_IFM_DECRIF_MASK 0 + * @arg @reg MD_AES_IFM_DECRIF_SIGNAL 1 + * @arg @reg MD_AES_IFM_ENCRIF_MASK 0 + * @arg @reg MD_AES_IFM_ENCRIF_SIGNAL 1 + */ +__STATIC_INLINE uint32_t md_aes_get_ifm(AES_TypeDef *aes) +{ + return (READ_REG(aes->IFM)); +} + +/** + * @brief AES Interrupt Flag Mask Status Register + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg value true, false + */ +__STATIC_INLINE bool md_aes_is_active_ifm_decifm(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->IFM, AES_IFM_DECIFM_MSK) >> AES_IFM_DECIFM_POS) & 0x1) ? true : false; +} + +/** + * @brief AES Interrupt Flag Mask Status Register + * @param AES Instance + * @retval value This parameter can be one of the following values: + * @arg value true, false + */ +__STATIC_INLINE bool md_aes_is_active_ifm_encifm(AES_TypeDef *aes) +{ + return ((READ_BIT(aes->IFM, AES_IFM_ENCIFM_MSK) >> AES_IFM_ENCIFM_POS) & 0x1) ? true : false; +} + +/** + * @brief AES Interrupt Clear Register + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg @reg MD_AES_ICR_DECICR 1 + * @arg @reg MD_AES_ICR_ENCICR 1 + * @retval None. + */ +__STATIC_INLINE void md_aes_set_icr(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->ICR, value); +} + +/** + * @brief AES Decryption Interrupt Clear + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_clear_icr_decicr(AES_TypeDef *aes) +{ + MODIFY_REG(aes->ICR, AES_ICR_DECICR_MSK, (1 << AES_ICR_DECICR_POS)); +} + +/** + * @brief AES Encryption Interrupt Clear + * @param AES Instance + * @retval None. + */ +__STATIC_INLINE void md_aes_clear_icr_encicr(AES_TypeDef *aes) +{ + MODIFY_REG(aes->ICR, AES_ICR_ENCICR_MSK, (1 << AES_ICR_ENCICR_POS)); +} + +/** + * @brief AES 128-bit Input / Ouput Data Register + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_dio(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->DIO, value); +} + +/** + * @brief AES 128-bit Input / Ouput Data Register + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +//#pragma push +//#pragma O0 +__STATIC_INLINE uint32_t md_aes_get_dio(AES_TypeDef *aes) +{ + return (READ_REG(aes->DIO)); +} +//#pragma pop + +/** + * @brief AES 128-bit Keyword Register 0 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_key0(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->KEY0, value); +} + +/** + * @brief AES 128-bit Keyword Register 0 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_key0(AES_TypeDef *aes) +{ + return (READ_REG(aes->KEY0)); +} + +/** + * @brief AES 128-bit Keyword Register 1 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_key1(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->KEY1, value); +} + +/** + * @brief AES 128-bit Keyword Register 1 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_key1(AES_TypeDef *aes) +{ + return (READ_REG(aes->KEY1)); +} + +/** + * @brief AES 128-bit Keyword Register 2 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_key2(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->KEY2, value); +} + +/** + * @brief AES 128-bit Keyword Register 2 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_key2(AES_TypeDef *aes) +{ + return (READ_REG(aes->KEY2)); +} + +/** + * @brief AES 128-bit Keyword Register 3 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_key3(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->KEY3, value); +} + +/** + * @brief AES 128-bit Keyword Register 3 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_key3(AES_TypeDef *aes) +{ + return (READ_REG(aes->KEY3)); +} + +/** + * @brief AES 128-bit Initial Vector Register 0 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_iv0(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IV0, value); +} + +/** + * @brief AES 128-bit Initial Vector Register 0 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_iv0(AES_TypeDef *aes) +{ + return (READ_REG(aes->IV0)); +} + +/** + * @brief AES 128-bit Initial Vector Register 1 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_iv1(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IV1, value); +} + +/** + * @brief AES 128-bit Initial Vector Register 1 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_iv1(AES_TypeDef *aes) +{ + return (READ_REG(aes->IV1)); +} + +/** + * @brief AES 128-bit Initial Vector Register 2 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_iv2(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IV2, value); +} + +/** + * @brief AES 128-bit Initial Vector Register 2 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_iv2(AES_TypeDef *aes) +{ + return (READ_REG(aes->IV2)); +} + +/** + * @brief AES 128-bit Initial Vector Register 3 + * @param AES Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_aes_set_iv3(AES_TypeDef *aes, uint32_t value) +{ + WRITE_REG(aes->IV3, value); +} + +/** + * @brief AES 128-bit Initial Vector Register 3 + * @param AES Instance + * @retval value + * @arg Minimum 0x0000000 + * @arg Maximum 0xFFFFFFF + */ +__STATIC_INLINE uint32_t md_aes_get_iv3(AES_TypeDef *aes) +{ + return (READ_REG(aes->IV3)); +} + +/** + * @} MD_AES_Public_Macros + */ + +/** + * @} AES + */ + +#endif + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_cmp.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_cmp.h new file mode 100644 index 0000000000000000000000000000000000000000..b2b6d2b2e0fbf3d7c1237319d12982d1d74be13c --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_cmp.h @@ -0,0 +1,573 @@ +/** + ****************************************************************************** + * @file md_CMP.h + * @brief ES32F0271 CMP Head File. + * + * @version V1.00.01 + * @date 11/23/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + + /* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_CMP_H__ +#define __MD_CMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_cmp.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (CMP) +/** @defgroup CMP CMP + * @brief CMP micro driver + * @{ + */ + + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Public types ---------------------------------------------------------------*/ +/* Public constants -----------------------------------------------------------*/ + +/** @defgroup MD_CMP_Public_Constants CMP Public Constants + * @{ + */ + +/** @defgroup MD_CMP_PC_CARS CMP Reference voltage + * @{ + */ +#define MD_CMP_CARS_1_25V (0x00000000UL) /*!< @brief Select CARS for 0.25*5V */ +#define MD_CMP_CARS_2_50V (0x00000001UL) /*!< @brief Select CARS for 0.5*5V */ +#define MD_CMP_CARS_3_75V (0x00000002UL) /*!< @brief Select CARS for 0.75*5V */ +#define MD_CMP_CARS_5_00V (0x00000003UL) /*!< @brief Select CARS for 5V */ + +/** + * @} MD_CMP_PC_CARS + */ + + +/** + * @} MD_CMP_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_CMP_Public_Macros CMP Public Macros + * @{ + */ + +/** @defgroup MD_CMP_PF_CON CMP Control Register + * @{ + */ +/** + * @brief Set CMP control register (CMP_CON) + * @param cmp CMP Instance + * @param value The value write in CMP_CON + * @retval None + */ +__STATIC_INLINE void md_cmp_set_con(CMP_TypeDef *cmp, uint32_t value) +{ + WRITE_REG(cmp->CON, value); +} + +/** + * @brief Get CMP control register (CMP_CON) + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_get_con(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_REG(cmp->CON)); +} + +/** + * @brief Enable Comparator 1 enable set + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_con_cmpon1(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CON, CMP_CON_CMPON1_MSK); +} +/** + * @brief Disable Comparator 1 enable set + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_con_cmpon1(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CON, CMP_CON_CMPON1_MSK); +} + +/** + * @brief Check if Comparator 1 enable set is enable + * @param cmp CMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_con_cmpon1(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CON, CMP_CON_CMPON1_MSK)); +} + +/** + * @brief Enable Comparator 2 enable set + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_con_cmpon2(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CON, CMP_CON_CMPON2_MSK); +} +/** + * @brief Disable Comparator 2 enable set + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_con_cmpon2(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CON, CMP_CON_CMPON2_MSK); +} + +/** + * @brief Check if Comparator 2 enable set is enable + * @param cmp CMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_con_caon2(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CON, CMP_CON_CMPON2_MSK)); +} + +/** + * @} MD_CMP_PF_CON + */ + + +/** @defgroup MD_CMP_PF_Configuration CMP Configuration Manangement + * @{ + */ + + +/** + * @brief Set CMP control register 1(CMP_CFG1) + * @param cmp CMP Instance + * @param value The value write in CMP_CFG1 + * @retval None + */ +__STATIC_INLINE void md_cmp_set_cfg1(CMP_TypeDef *cmp, uint32_t value) +{ + WRITE_REG(cmp->CFG1, value); +} +/** + * @brief Get CMP control register 1(CMP_CFG1) + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_get_cfg1(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_REG(cmp->CFG1)); +} + + +/** + * @brief Set Comparator 1 reference voltage selection. + * @param cmp CMP Instance + * @param RefVol This parameter can be one of the following values: + * @arg MD_CMP_CARS_1_25V + * @arg MD_CMP_CARS_2_50V + * @arg MD_CMP_CARS_3_75V + * @arg MD_CMP_CARS_5_00V + * @retval None + */ +__STATIC_INLINE void md_cmp_set_cfg1_rs(CMP_TypeDef *cmp, uint32_t RefVol) +{ + MODIFY_REG(cmp->CFG1, CMP_CFG1_RS_MSK, RefVol<CFG1, CMP_CFG1_RS_MSK) >> CMP_CFG1_RS_POSS); +} + + +/** + * @brief Enable Comparator 1 Filter circuit + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_cfg1_fen(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG1, CMP_CFG1_FEN_MSK); +} +/** + * @brief Disable Comparator 1 Filter circuit + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_cfg1_fen(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG1, CMP_CFG1_FEN_MSK); +} + +/** + * @brief Check if Comparator 1 Filter circuit is enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_cfg1_fen(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG1, CMP_CFG1_FEN_MSK) == (CMP_CFG1_FEN_MSK)); +} + + +/** + * @brief Enable comparator 1 reverse circuit enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_cfg1_psen(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG1, CMP_CFG1_PSEN_MSK); +} +/** + * @brief Disable comparator 1 reverse circuit enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_cfg1_psen(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG1, CMP_CFG1_PSEN_MSK); +} + +/** + * @brief Check if comparator 1 reverse circuit enable is enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_cfg1_capsen(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG1, CMP_CFG1_PSEN_MSK) == (CMP_CFG1_PSEN_MSK) ); +} + + +/** + * @brief Enable Comparator 1 Negative input select + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_cfg1_insel(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG1, CMP_CFG1_INSEL_MSK); +} +/** + * @brief Disable Comparator 1 Negative input select + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_cfg1_insel(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG1, CMP_CFG1_INSEL_MSK); +} + +/** + * @brief Check if comparator 1 Negative input select is enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_cfg1_insel(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG1, CMP_CFG1_INSEL_MSK) == (CMP_CFG1_INSEL_MSK)); +} + + +/** + * @brief Enable comparator 1 Positive input select + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_cfg1_ipsel(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG1, CMP_CFG1_IPSEL_MSK); +} +/** + * @brief Disable comparator 1 Positive input select + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_cfg1_ipsel(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG1, CMP_CFG1_IPSEL_MSK); +} + +/** + * @brief Check if comparator 1 Positive input select is enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_cfg1_ipsel(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG1, CMP_CFG1_IPSEL_MSK) == (CMP_CFG1_IPSEL_MSK)); +} + + +/** + * @brief Set CMP control register 2(CMP_CFG2) + * @param cmp CMP Instance + * @param value The value write in CMP_CFG2 + * @retval None + */ +__STATIC_INLINE void md_cmp_set_cfg2(CMP_TypeDef *cmp, uint32_t value) +{ + WRITE_REG(cmp->CFG2, value); +} +/** + * @brief Get CMP control register 2(CMP_CFG2) + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_get_cfg2(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_REG(cmp->CFG2)); +} + + +/** + * @brief Set Comparator 2 reference voltage selection. + * @param cmp CMP Instance + * @param RefVol This parameter can be one of the following values: + * @arg MD_CMP_CARS_1_25V + * @arg MD_CMP_CARS_2_50V + * @arg MD_CMP_CARS_3_75V + * @arg MD_CMP_CARS_5_00V + * @retval None + */ +__STATIC_INLINE void md_cmp_set_cfg2_rs(CMP_TypeDef *cmp, uint32_t RefVol) +{ + MODIFY_REG(cmp->CFG2, CMP_CFG2_RS_MSK, RefVol << CMP_CFG2_RS_POSS); +} + +/** + * @brief Return Comparator 2 reference voltage + * @param cmp CMP Instance + * @retval None + * @arg MD_CMP_CARS_1_25V + * @arg MD_CMP_CARS_2_50V + * @arg MD_CMP_CARS_3_75V + * @arg MD_CMP_CARS_5_00V + */ +__STATIC_INLINE uint32_t md_cmp_get_cfg2_rs(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_BIT(cmp->CFG2, CMP_CFG2_RS_MSK) >> CMP_CFG2_RS_POSS); +} + + +/** + * @brief Enable Comparator 2 Filter circuit + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_cfg2_fen(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG2, CMP_CFG2_FEN_MSK); +} +/** + * @brief Disable Comparator 2 Filter circuit + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_cfg2_fen(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG2, CMP_CFG2_FEN_MSK); +} + +/** + * @brief Check if Comparator 2 Filter circuit is enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_cfg2_fen(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG2, CMP_CFG2_FEN_MSK) == (CMP_CFG2_FEN_MSK)) ; +} + + +/** + * @brief Enable comparator 2 reverse circuit enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_cfg2_psen(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG2, CMP_CFG2_PSEN_MSK); +} +/** + * @brief Disable comparator 2 reverse circuit enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_cfg2_psen(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG2, CMP_CFG2_PSEN_MSK); +} + +/** + * @brief Check if comparator 2 reverse circuit enable is enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_cfg2_psen(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG2, CMP_CFG2_PSEN_MSK) == (CMP_CFG2_PSEN_MSK)); +} + + +/** + * @brief Enable Comparator 2 Negative input select + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_cfg2_insel(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG2, CMP_CFG2_INSEL_MSK); +} +/** + * @brief Disable Comparator 2 Negative input select + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_cfg2_insel(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG2, CMP_CFG2_INSEL_MSK); +} + +/** + * @brief Check if comparator 2 Negative input select is enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_cfg2_insel(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG2, CMP_CFG2_INSEL_MSK) == (CMP_CFG2_INSEL_MSK)); +} + + +/** + * @brief Enable comparator 2 Positive input select + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_enable_cfg2_ipsel(CMP_TypeDef *cmp) +{ + SET_BIT(cmp->CFG2, CMP_CFG2_IPSEL_MSK); +} +/** + * @brief Disable comparator 2 Positive input select + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE void md_cmp_disable_cfg2_ipsel(CMP_TypeDef *cmp) +{ + CLEAR_BIT(cmp->CFG2, CMP_CFG2_IPSEL_MSK); +} + +/** + * @brief Check if comparator 2 Positive input select is enable + * @param cmp CMP Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_cmp_is_enable_cfg2_ipsel(CMP_TypeDef *cmp) +{ + return (READ_BIT(cmp->CFG2, CMP_CFG2_IPSEL_MSK) == (CMP_CFG2_IPSEL_MSK)); +} + + +/** + * @} MD_CMP_PF_Configuration + */ + +/** @defgroup MD_CMP_PC_RULT CMP Comparator Output Register. + * @{ + */ + +/** + * @brief Return Comparator output result(CMP_RULT) + * @param cmp CMP Instance + * @retval The state of 1 or 0 + */ +__STATIC_INLINE uint32_t md_cmp_get_rult(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_REG(cmp->RULT)); +} + +/** + * @brief Return Comparator 1 output result + * @param cmp CMP Instance + * @retval The state of 1 or 0 + */ +__STATIC_INLINE uint32_t md_cmp_get_rult_cmpo1(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_BIT(cmp->RULT, CMP_RULT_CMPO1_MSK)); +} +/** + * @brief Return Comparator 2 output result + * @param cmp CMP Instance + * @retval The state of 1 or 0 + */ +__STATIC_INLINE uint32_t md_cmp_get_rult_cmpo2(CMP_TypeDef *cmp) +{ + return (uint32_t)(READ_BIT(cmp->RULT, CMP_RULT_CMPO2_MSK)); +} + + +/** + * @} MD_CMP_PC_RULT + */ + + +/** + * @} MD_CMP_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ + +/** + * @} CMP + */ + +#endif + + +/** + * @} Micro_Driver + */ + +#endif + +#ifdef __cplusplus +} +#endif + + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_crc.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..f1b65692e7711aa5bd86017a53d8256606b0398e --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_crc.h @@ -0,0 +1,519 @@ +/** + ****************************************************************************** + * @file md_crc.h + * @brief M601 CRC Head File. + * + * @version V0.01 + * @date 28/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_CRC_H__ +#define __MD_CRC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (CRC) + +/** @defgroup CRC CRC + * @brief CRC module driver + * @{ + */ + +/* Private Types --------------------------------------------------------------*/ +/* Private Variables ----------------------------------------------------------*/ +/* Private Macros -------------------------------------------------------------*/ +/* Public Types ---------------------------------------------------------------*/ +/** @defgroup MD_CRC_INIT CRC public init structure + * @brief + * @{ + */ +typedef struct +{ + uint32_t xorout; + uint32_t refout; + uint32_t refin; + uint32_t byte; + uint32_t mode; + uint32_t req; + uint32_t ds; + uint32_t rst; +} md_crc_init_typedef; +/** + * @} MD_CRC_INIT + */ + +/* Public Constants -----------------------------------------------------------*/ +/** @defgroup MD_CRC_Public_Constants CRC Public Constants + * @brief + * @{ + */ + +/** @defgroup MD_CRC_CON_registers CRC Control Registers + * @brief + * @{ + */ +#define MD_CRC_CON_DMA_ON 1 /*!< This allow user to enable DMA function. */ +#define MD_CRC_CON_DMA_OFF 0 /*!< This allow user to disable DMA function. */ +#define MD_CRC_CON_MSB_ON 1 /*!< User can set this bit to change the 'byte' order of input data. */ +#define MD_CRC_CON_MSB_OFF 1 /*!< User can set this bit to change the 'byte' order of input data. */ +#define MD_CRC_CON_REOUT 0 /*!< This allow user to reverse the order of CRC output data. */ +#define MD_CRC_CON_REOUT_REV 1 /*!< This allow user to reverse the order of CRC output data. */ +#define MD_CRC_CON_REIN 0 /*!< This allow user to reverse the order of CRC input data. */ +#define MD_CRC_CON_REIN_REV 1 /*!< This allow user to reverse the order of CRC input data. */ +#define MD_CRC_CON_SIZE_POLY32 0 /*!< This allow user to select polynomial size. */ +#define MD_CRC_CON_SIZE_POLY16 1 /*!< This allow user to select polynomial size. */ +#define MD_CRC_CON_SIZE_POLY8 2 /*!< This allow user to select polynomial size. */ +#define MD_CRC_CON_MODE_COMP_DISABLE 0 /*!< This allow user to check CRC result. */ +#define MD_CRC_CON_MODE_COMP_ZERO 1 /*!< This allow user to check CRC result. */ +#define MD_CRC_CON_MODE_COMP_ENABLE 2 /*!< This allow user to check CRC result. */ +#define MD_CRC_CON_RESET 1 /*!< User can set this bit to reset CRC function. */ +/** + * @} MD_CRC_CON_registers + */ + +/** @defgroup MD_CRC_STAT_registers CRC Status Registers + * @brief + * @{ + */ +#define MD_CRC_STAT_FAIL 1 /*!< This bit is set when CRC result is not correct. */ +#define MD_CRC_STAT_EMPTY 1 /*!< This bit is cleaned after an CRC calculation. */ +#define MD_CRC_STAT_BUSY 1 /*!< This bit is set when CRC module is calculating result. */ +#define MD_CRC_STAT_DONE 1 /*!< This bit is set when CRC calculation is finish. */ +/** + * @} MD_CRC_STAT_registers + */ + +/** + * @} MD_CRC_Public_Constants + */ + +/* Public Macros --------------------------------------------------------------*/ +/** @defgroup MD_CRC_Public_Macros CRC Public Macros + * @brief + * @{ + */ + +/** + * @brief This register is used to write the CRC initial data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x00000000 + * @arg Maximum 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_init(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->INIT, value); +} + +/** + * @brief This register is used to read the CRC initial data. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_init(CRC_TypeDef *crc) +{ + return (READ_REG(crc->INIT)); +} + +/** + * @brief This register is used to write the coefficient of the CRC polynomial. Default coefficient is for CRC32. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x00000000 + * @arg Maximum 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_poly(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->POLY, value); +} + +/** + * @brief This register is used to read the coefficient of the CRC polynomial. Default coefficient is for CRC32. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_poly(CRC_TypeDef *crc) +{ + return (READ_REG(crc->POLY)); +} + +/** + * @brief This register is used to write the CRC input data. CRC will start to calculate result after this register is written. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x00000000 + * @arg Maximum 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_data(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->DATA, value); +} + +/** + * @brief This register is used to read the CRC input data. CRC will start to calculate result after this register is written. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_data(CRC_TypeDef *crc) +{ + return (READ_REG(crc->DATA)); +} + +/** + * @brief This register is used to compare with the CRC output data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x00000000 + * @arg Maximum 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_comp(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->COMP, value); +} + +/** + * @brief This register is used to compare with the CRC output data. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_comp(CRC_TypeDef *crc) +{ + return (READ_REG(crc->COMP)); +} + +/** + * @brief This register is used to set a parameter to do exclusive OR with CRC output data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg Minimum 0x00000000 + * @arg Maximum 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void md_crc_set_rema(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->REMA, value); +} + +/** + * @brief This register is used to set a parameter to do exclusive OR with CRC output data. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_rema(CRC_TypeDef *crc) +{ + return (READ_REG(crc->REMA)); +} + +/** + * @brief This register is used to set a parameter. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_CRC_CON_DMA_ON 1 + * @arg @ref MD_CRC_CON_DMA_OFF 0 + * @arg @ref MD_CRC_CON_MSB_ON 1 + * @arg @ref MD_CRC_CON_MSB_OFF 0 + * @arg @ref MD_CRC_CON_REOUT 0 + * @arg @ref MD_CRC_CON_REOUT_REV 1 + * @arg @ref MD_CRC_CON_REIN 0 + * @arg @ref MD_CRC_CON_REIN_REV 1 + * @arg @ref MD_CRC_CON_SIZE_POLY32 0 + * @arg @ref MD_CRC_CON_SIZE_POLY16 1 + * @arg @ref MD_CRC_CON_SIZE_POLY8 2 + * @arg @ref MD_CRC_CON_MODE_COMP_DISABLE 0 + * @arg @ref MD_CRC_CON_MODE_COMP_ZERO 1 + * @arg @ref MD_CRC_CON_MODE_COMP_ENABLE 2 + * @arg @ref MD_CRC_CON_RESET 1 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_con(CRC_TypeDef *crc, uint32_t value) +{ + WRITE_REG(crc->CON, value); +} + +/** + * @brief This register is used to get a parameter. + * @param CRC Instance + * @retval value 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_con(CRC_TypeDef *crc) +{ + return (READ_REG(crc->CON)); +} + +/** + * @brief This function allow user to enable DMA function. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_CRC_CON_DMA_ON 1 + * @arg @ref MD_CRC_CON_DMA_OFF 0 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_con_dma(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_DMA_MSK, value << CRC_CON_DMA_POS); +} + +/** + * @brief This function allow user to enable DMA function. + * @param CRC Instance + * @retval value 0: disable, 1: enable. + */ +__STATIC_INLINE uint32_t md_crc_get_con_dma(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->CON, CRC_CON_DMA_MSK) >> CRC_CON_DMA_POS) & 0x1); +} + +/** + * @brief User can set this bit to change the 'byte' order of input data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_CRC_CON_MSB_ON 1 + * @arg @ref MD_CRC_CON_MSB_OFF 0 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_con_msb(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_MSB_MSK, value << CRC_CON_MSB_POS); +} + +/** + * @brief User can set this bit to change the 'byte' order of input data. + * @param CRC Instance + * @retval value 0: disable, 1: enable. + */ +__STATIC_INLINE uint32_t md_crc_get_con_msb(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->CON, CRC_CON_MSB_MSK) >> CRC_CON_MSB_POS) & 0x1); +} + +/** + * @brief This function allow user to reverse the order of CRC output data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @reg MD_CRC_CON_REOUT 0 + * @arg @reg MD_CRC_CON_REOUT_REV 1 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_con_reout(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_REOUT_MSK, value << CRC_CON_REOUT_POS); +} + +/** + * @brief This function allow user to reverse the order of CRC output data. + * @param CRC Instance + * @retval value 0: Disable reverse operation, 1: Reverse output data. + */ +__STATIC_INLINE uint32_t md_crc_get_con_reout(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->CON, CRC_CON_REOUT_MSK) >> CRC_CON_REOUT_POS) & 0x1); +} + +/** + * @brief This function allow user to reverse the order of CRC input data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @reg MD_CRC_CON_REIN 0 + * @arg @reg MD_CRC_CON_REIN_REV 1 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_con_rein(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_REIN_MSK, value << CRC_CON_REIN_POS); +} + +/** + * @brief User can set this bit to change the 'byte' order of input data. + * @param CRC Instance + * @retval value 0: Disable reverse operation, 1: Bit reversal done by byte. + */ +__STATIC_INLINE uint32_t md_crc_get_con_rein(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->CON, CRC_CON_REIN_MSK) >> CRC_CON_REIN_POS) & 0x1); +} + +/** + * @brief User can set this bit to change the 'byte' order of input data. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_CRC_CON_SIZE_POLY32 0 + * @arg @ref MD_CRC_CON_SIZE_POLY16 1 + * @arg @ref MD_CRC_CON_SIZE_POLY8 2 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_con_size(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_SIZE_MSK, value << CRC_CON_SIZE_POSS); +} + +/** + * @brief User can set this bit to change the 'byte' order of input data. + * @param CRC Instance + * @retval value 00: 32 bit polynomial, 01: 16 bit polynomial, 10: 8 bit polynomial. + */ +__STATIC_INLINE uint32_t md_crc_get_con_size(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->CON, CRC_CON_SIZE_MSK) >> CRC_CON_SIZE_POSS) & 0x3); +} + +/** + * @brief This function allow user to check CRC result. If CRC result is not correct, the status “FAIL” in CRC_STA will be set to 1. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_CRC_CON_MODE_COMP_DISABLE 0 + * @arg @ref MD_CRC_CON_MODE_COMP_ZERO 1 + * @arg @ref MD_CRC_CON_MODE_COMP_ENABLE 2 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_con_mode(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_MODE_MSK, value << CRC_CON_MODE_POSS); +} + +/** + * @brief This function allow user to check CRC result. If CRC result is not correct, the status “FAIL” in CRC_STA will be set to 1. + * @param CRC Instance + * @retval value 00: Disable compare function, 01: Compare CRC result with 32’h0000_0000, 10: Compare CRC result with CRC_COMP. + */ +__STATIC_INLINE uint32_t md_crc_get_con_mode(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->CON, CRC_CON_MODE_MSK) >> CRC_CON_MODE_POSS) & 0x3); +} + +/** + * @brief User can set this bit to reset CRC function. This bit will be cleared by itself. + * @param CRC Instance + * @param value This parameter can be one of the following values: + * @arg @ref MD_CRC_CON_RESET 1 + * @retval None. + */ +__STATIC_INLINE void md_crc_set_con_reset(CRC_TypeDef *crc, uint32_t value) +{ + MODIFY_REG(crc->CON, CRC_CON_RESET_MSK, value << CRC_CON_RESET_POS); +} + +/** + * @brief User can set this bit to reset CRC function. This bit will be cleared by itself. + * @param CRC Instance + * @retval value 0. + */ +__STATIC_INLINE uint32_t md_crc_get_con_reset(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->CON, CRC_CON_RESET_MSK) >> CRC_CON_RESET_POS) & 0x1); +} + +/** + * @brief This register is used to show the CRC calculation result. + * @param CRC Instance + * @retval value: 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_dout(CRC_TypeDef *crc) +{ + return (READ_REG(crc->DOUT)); +} + +/** + * @brief This register is used to show the CRC calculation exculsive OR result. + * @param CRC Instance + * @retval value: 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_dout_xor(CRC_TypeDef *crc) +{ + return (READ_REG(crc->DOUT_XOR)); +} + +/** + * @brief This register is used to show the CRC calculation exculsive OR result. + * @param CRC Instance + * @retval value: 0x00000000 ~ 0xffffffff. + */ +__STATIC_INLINE uint32_t md_crc_get_stat(CRC_TypeDef *crc) +{ + return (READ_REG(crc->STAT)); +} + +/** + * @brief This bit is set when CRC result is not correct. + * @param CRC Instance + * @retval value: 1 = FAIL, 0 = PASS. + @arg @ref MD_CRC_STAT_FAIL 1 + */ +__STATIC_INLINE uint32_t md_crc_get_stat_fail(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->STAT, CRC_STAT_FAIL_MSK) >> CRC_STAT_FAIL_POS) & 0x1); +} + +/** + * @brief This bit is cleaned after an CRC calculation. + * @param CRC Instance + * @retval value: 1 = FAIL, 0 = PASS. + @arg @ref MD_CRC_STAT_EMPTY 1 + */ +__STATIC_INLINE uint32_t md_crc_get_stat_empty(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->STAT, CRC_STAT_EMPTY_MSK) >> CRC_STAT_EMPTY_POS) & 0x1); +} + +/** + * @brief This bit is set when CRC module is calculating result. + * @param CRC Instance + * @retval value: 1 = FAIL, 0 = PASS. + @arg @ref MD_CRC_STAT_BUSY 1 + */ +__STATIC_INLINE uint32_t md_crc_get_stat_busy(CRC_TypeDef *crc) +{ + return ((READ_BIT(crc->STAT, CRC_STAT_BUSY_MSK) >> CRC_STAT_BUSY_POS) & 0x1); +} + +/** + * @brief This bit is set when CRC module is calculating result. + * @param CRC Instance + * @retval value: 1 = FAIL, 0 = PASS. + @arg @ref MD_CRC_STAT_DONE 1 + */ +__STATIC_INLINE uint32_t md_crc_get_stat_done(CRC_TypeDef *crc) +{ + return (READ_BIT(crc->STAT, CRC_STAT_DONE_MSK) >> CRC_STAT_DONE_POS); +} + +/** + * @} MD_CRC_Public_Macros + */ + +/** + * @} CRC + */ + +#endif + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dac.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dac.h new file mode 100644 index 0000000000000000000000000000000000000000..199fc195b1345342f0b73e8a88f25edbebe9d8fa --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dac.h @@ -0,0 +1,290 @@ +/** + ****************************************************************************** + * @file md_ADC.h + * @brief ES32F0271 DAC Header File. + * + * @version V1.00.01 + * @date 01/14/2019 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_DAC_H__ +#define __MD_DAC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_dac.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined DAC + +/** @defgroup DAC DAC + * @brief DAC micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Public types ---------------------------------------------------------------*/ +/* Public constants -----------------------------------------------------------*/ +/* Public functions -----------------------------------------------------------*/ + +/** @defgroup MD_DAC_Public_Constants DAC Public Constants + * @{ + */ + +/** @defgroup MD_DAC_CON DAC_CON Register + * @{ + */ + +#define MD_ADC_CON_TSEL_SW (0x00000000U<CON, DAC_CON_INVREN_MSK); +} + +/** + * @brief DAC INVREN Disable. + * @param None + * @retval None + */ +__STATIC_INLINE void md_dac_disable_con_invren(DAC_TypeDef *DACx) +{ + CLEAR_BIT(DACx->CON, DAC_CON_INVREN_MSK); +} + +/** + * @brief Check if DAC INVREN is enabled. + * @param None + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dac_is_enabled_con_invren(DAC_TypeDef *DACx) +{ + return (READ_BIT(DACx->CON, DAC_CON_INVREN_MSK) == (DAC_CON_INVREN_MSK)); +} + +/** + * @brief TRIGGER enable. + * @param DACx DAC Instance + * @retval None + */ +__STATIC_INLINE void md_dac_enable_con_trien(DAC_TypeDef *DACx) +{ + SET_BIT(DACx->CON, DAC_CON_TRIEN_MSK); +} + +/** + * @brief TRIGGER Disable. + * @param DACx DAC Instance + * @retval None + */ +__STATIC_INLINE void md_dac_disable_en_trien(DAC_TypeDef *DACx) +{ + CLEAR_BIT(DACx->CON, DAC_CON_TRIEN_MSK); +} + +/** + * @brief Check if DAC TRIGGER is enabled. + * @param DACx DAC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dac_is_enabled_con_trien(DAC_TypeDef *DACx) +{ + return (READ_BIT(DACx->EN, DAC_CON_TRIEN_MSK) == (DAC_CON_TRIEN_MSK)); +} + +/** + * @brief Set DACx DIV register. + * @note This bits can only be written none zero value. + * @param DACx DAC Instance. + * @param DIV value. + * @retval None + */ +__STATIC_INLINE void md_dac_set_div(DAC_TypeDef *DACx, uint32_t div) +{ + WRITE_REG(DACx->DIV, div); +} + +/** + * @brief Set DACx DAC_CON WAVE value. + * @param DACx DAC Instance. + * @param WAVE value. + * @retval None + */ +__STATIC_INLINE void md_dac_set_con_wave(DAC_TypeDef *DACx, uint32_t wave) +{ + MODIFY_REG(DACx->CON, DAC_CON_MAMP_MSK, wave<CON, DAC_CON_MAMP_MSK, mamp<CON, DAC_CON_T_SEL_MSK, tsel<TRIG, DAC_TRIG_S_TRIG_MSK); +} + +/** + * @brief Check if Transmit FIFO full. + * @note This bit is set and cleared by hardware when the TX FIFO is no + * longer full. + * @param DACx DAC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dac_is_active_flag_stat_txfull(DAC_TypeDef *DACx) +{ + return (READ_BIT(DACx->STAT, DAC_STAT_TX_FULL_MSK) == (DAC_STAT_TX_FULL_MSK)); +} + +/** + * @brief Check if Transmit DAC is busy. + * @param DACx DAC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dac_is_active_flag_stat_busy(DAC_TypeDef *DACx) +{ + return (READ_BIT(DACx->STAT, DAC_STAT_BUSY_MSK) == (DAC_STAT_BUSY_MSK)); +} + +/** + * @brief DAC enable. + * @param DACx DAC Instance + * @retval None + */ +__STATIC_INLINE void md_dac_enable_en_dacen(DAC_TypeDef *DACx) +{ + SET_BIT(DACx->EN, DAC_EN_DAC_EN_MSK); +} + +/** + * @brief DAC Disable. + * @param DACx DAC Instance + * @retval None + */ +__STATIC_INLINE void md_dac_disable_en_dacen(DAC_TypeDef *DACx) +{ + CLEAR_BIT(DACx->EN, DAC_EN_DAC_EN_MSK); +} + +/** + * @brief Set DACx data register. + * @param DACx DAC Instance. + * @param Tx data value. + * @retval None + */ +__STATIC_INLINE void md_dac_set_txdata(DAC_TypeDef *DACx, uint32_t data) +{ + WRITE_REG(DACx->DATA, data); +} + +#endif + +/** + * @} MD_GPIO_Public_Macros + */ + +/** @} ADC + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dma.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..521ce1e61ecce88de6f5ee4de05ab0c9585d2427 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_dma.h @@ -0,0 +1,5561 @@ +/** + ****************************************************************************** + * @file md_DMA.h + * @brief ES32F0271 DMA HEAD File. + * + * @version V1.00.02 + * @date 30/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_DMA_H__ +#define __MD_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_dma.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (DMA1) + +/** @defgroup DMA DMA + * @brief DMA micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_DMA_PT_INIT DMA Public Init structures + * @{ + */ + +/** + * @brief MD DMA Init Structure definition + */ + + +/** + * @} MD_DMA_PT_INIT + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_DMA_Public_Constants DMA Public Constants + * @{ + */ + +/** @defgroup MD_DMA_DINCOS Destination Increment Offset Size + * @{ + */ +#define MD_DMA_DINCOS_LINKED_DWSEL (0x00000000UL) /** @brief The offset size for the peripheral address calculation is + linked to the DWSEL */ +#define MD_DMA_DINCOS_FIXED_TO_4 (0X00000001UL) /** @brief The offset size for the peripheral address calculation is + fixed to 4 (32-bit alignment). */ +/** + * @} MD_DMA_DINCOS + */ + +/** @defgroup MD_DMA_DBUSEL Destination Transfer Burst Selection + * @{ + */ +#define MD_DMA_DBUSEL_SINGLE (0x00000000U) +#define MD_DMA_DBUSEL_WRAP4 (0x00000002U) +#define MD_DMA_DBUSEL_INCR4 (0x00000003U) +#define MD_DMA_DBUSEL_WRAP8 (0x00000004U) +#define MD_DMA_DBUSEL_INCR8 (0x00000005U) +#define MD_DMA_DBUSEL_WRAP16 (0x00000006U) +#define MD_DMA_DBUSEL_INCR16 (0x00000007U) +/** + * @} MD_DMA_DBUSEL + */ + +/** @defgroup MD_DMA_DDWSEL Destination Transfer Data Width Selection. + * @{ + */ +#define MD_DMA_DDWSEL_ONE_BYTE (0x00000000UL) /** @brief One byte (8-bit) is transferred for every DMA operation. */ +#define MD_DMA_DDWSEL_ONE_HALF_WORD (0x00000001UL) /** @brief One half-word (16-bit) is transferred for every DMA operation. */ +#define MD_DMA_DDWSEL_ONE_WORD (0x00000002UL) /** @brief One word (32-bit) is transferred for every DMA operation. */ +/** + * @} MD_DMA_DDWSEL + */ + +/** @defgroup MD_DMA_SINCOS Source Increment Offset Size + * @{ + */ +#define MD_DMA_SINCOS_LINKED_SWSEL (0x00000000UL) /** @brief The offset size for the peripheral address calculation is + linked to the SWSEL */ +#define MD_DMA_SINCOS_FIXED_TO_4 (0X00000001UL) /** @brief The offset size for the peripheral address calculation is + fixed to 4 (32-bit alignment). */ +/** + * @} MD_DMA_SINCOS + */ + +/** @defgroup MD_DMA_SBUSEL Source Transfer Burst Selection. + * @{ + */ +#define MD_DMA_SBUSEL_SINGLE (0x00000000U) +#define MD_DMA_SBUSEL_WRAP4 (0x00000002U) +#define MD_DMA_SBUSEL_INCR4 (0x00000003U) +#define MD_DMA_SBUSEL_WRAP8 (0x00000004U) +#define MD_DMA_SBUSEL_INCR8 (0x00000005U) +#define MD_DMA_SBUSEL_WRAP16 (0x00000006U) +#define MD_DMA_SBUSEL_INCR16 (0x00000007U) +/** + * @} MD_DMA_SBUSEL + */ + +/** @defgroup MD_DMA_SDWSEL Source Transfer Data Width Selection. + * @{ + */ +#define MD_DMA_SDWSEL_ONE_BYTE (0x00000000UL) /** @brief One byte (8-bit) is transferred for every DMA operation. */ +#define MD_DMA_SDWSEL_ONE_HALF_WORD (0x00000001UL) /** @brief One half-word (16-bit) is transferred for every DMA operation. */ +#define MD_DMA_SDWSEL_ONE_WORD (0x00000002UL) /** @brief One word (32-bit) is transferred for every DMA operation. */ +/** + * @} MD_DMA_SDWSEL + */ + +/** @defgroup MD_DMA_CHPRI DMA Channel Priority. + * @{ + */ +#define MD_DMA_CHPRI_LV0 (0x00000000U) +#define MD_DMA_CHPRI_LV1 (0x00000001U) +#define MD_DMA_CHPRI_LV2 (0x00000002U) +#define MD_DMA_CHPRI_LV3 (0x00000003U) +#define MD_DMA_CHPRI_LV4 (0x00000004U) +#define MD_DMA_CHPRI_LV5 (0x00000005U) +/** + * @} MD_DMA_CHPRI + */ + +/** @defgroup MD_DMA_MODESEL DMA Mode Select. + * @{ + */ +#define MD_DMA_MODESEL_MEM_TO_MEM (0x0000000UL) /** @brief Memory to Memory mode (Memory-to-Memory). */ +#define MD_DMA_MODESEL_PER_TO_MEM (0x0000001UL) /** @brief Peripheral to Memory mode (Peripheral-to-Memory). */ +#define MD_DMA_MODESEL_MEM_TO_PER (0x0000002UL) /** @brief Memory to Peripheral mode (Memory-to-Peripheral). */ +/** + * @} MD_DMA_MODESEL + */ + +/** @defgroup MD_DMA_PFCTRL Peripheral flow controller + * @{ + */ +#define MD_DMA_PFCTRL_DMA_CTRL (0x0000000UL) /** @brief The DMA is the flow controller */ +#define MD_DMA_PFCTRL_PER_CTRL (0x0000001UL) /** @brief The peripheral is the flow controller */ +/** + * @} MD_DMA_PFCTRL + */ + +/** @defgroup MD_DMA_PHSS Peripheral Handshake Software Select + * @{ + */ +#define MD_DMA_PHSS_UART1_TX (0x0000000UL) +#define MD_DMA_PHSS_UART2_TX (0x0000001UL) +#define MD_DMA_PHSS_UART3_TX (0x0000002UL) +#define MD_DMA_PHSS_SUART1_TX (0x0000003UL) +#define MD_DMA_PHSS_SUART2_TX (0x0000004UL) +#define MD_DMA_PHSS_SPI1_TX (0x0000005UL) +#define MD_DMA_PHSS_SPI2_TX (0x0000006UL) +#define MD_DMA_PHSS_I2C1_TX (0x0000007UL) +#define MD_DMA_PHSS_I2C2_TX (0x0000008UL) +#define MD_DMA_PHSS_AES_IN (0x0000009UL) +#define MD_DMA_PHSS_DAC (0x000000AUL) +#define MD_DMA_PHSS_CRC (0x000000BUL) +#define MD_DMA_PHSS_UART1_RX (0x000000FUL) +#define MD_DMA_PHSS_UART2_RX (0x0000010UL) +#define MD_DMA_PHSS_UART3_RX (0x0000011UL) +#define MD_DMA_PHSS_SUART1_RX (0x0000012UL) +#define MD_DMA_PHSS_SUART2_RX (0x0000013UL) +#define MD_DMA_PHSS_SPI1_RTX (0x0000014UL) +#define MD_DMA_PHSS_SPI2_RX (0x0000015UL) +#define MD_DMA_PHSS_I2C1_RX (0x0000016UL) +#define MD_DMA_PHSS_I2C2_RX (0x0000017UL) +#define MD_DMA_PHSS_AES_OUT (0x0000018UL) +#define MD_DMA_PHSS_ADCSS0 (0x0000019UL) +#define MD_DMA_PHSS_ADCSS1 (0x000001AUL) +#define MD_DMA_PHSS_ADCSS2 (0x000001BUL) +#define MD_DMA_PHSS_ADCSS3 (0x000001CUL) +#define MD_DMA_PHSS_BS16T1_UP (0x0000020UL) +#define MD_DMA_PHSS_AD16C4T1_CH1 (0x0000021UL) +#define MD_DMA_PHSS_AD16C4T1_CH2 (0x0000022UL) +#define MD_DMA_PHSS_AD16C4T1_CH3 (0x0000023UL) +#define MD_DMA_PHSS_AD16C4T1_CH4 (0x0000024UL) +#define MD_DMA_PHSS_AD16C4T1_UP (0x0000025UL) +#define MD_DMA_PHSS_AD16C4T1_TRIG (0x0000026UL) +#define MD_DMA_PHSS_AD16C4T1_COM (0x0000027UL) +#define MD_DMA_PHSS_GP32C4T1_CH1 (0x0000028UL) +#define MD_DMA_PHSS_GP32C4T1_CH2 (0x0000029UL) +#define MD_DMA_PHSS_GP32C4T1_CH3 (0x000002AUL) +#define MD_DMA_PHSS_GP32C4T1_CH4 (0x000002BUL) +#define MD_DMA_PHSS_GP32C4T1_UP (0x000002CUL) +#define MD_DMA_PHSS_GP32C4T1_TRIG (0x000002DUL) +#define MD_DMA_PHSS_GP16C4T1_CH1 (0x000002EUL) +#define MD_DMA_PHSS_GP16C4T1_CH2 (0x000002FUL) +#define MD_DMA_PHSS_GP16C4T1_CH3 (0x0000030UL) +#define MD_DMA_PHSS_GP16C4T1_CH4 (0x0000031UL) +#define MD_DMA_PHSS_GP16C4T1_UP (0x0000032UL) +#define MD_DMA_PHSS_GP16C4T1_TRIG (0x0000033UL) +#define MD_DMA_PHSS_GP16C4T2_CH1 (0x0000034UL) +#define MD_DMA_PHSS_GP16C4T2_CH2 (0x0000035UL) +#define MD_DMA_PHSS_GP16C4T2_CH3 (0x0000036UL) +#define MD_DMA_PHSS_GP16C4T2_CH4 (0x0000037UL) +#define MD_DMA_PHSS_GP16C4T2_UP (0x0000038UL) +#define MD_DMA_PHSS_GP16C4T2_TRIG (0x0000039UL) +#define MD_DMA_PHSS_GP16C4T3_CH1 (0x000003AUL) +#define MD_DMA_PHSS_GP16C4T3_CH2 (0x000003BUL) +#define MD_DMA_PHSS_GP16C4T3_CH3 (0x000003CUL) +#define MD_DMA_PHSS_GP16C4T3_CH4 (0x000003DUL) +#define MD_DMA_PHSS_GP16C4T3_UP (0x000003EUL) +#define MD_DMA_PHSS_GP16C4T3_TRIG (0x000003FUL) +#define MD_DMA_PHSS_GP16C2T1_CH1 (0x0000040UL) +#define MD_DMA_PHSS_GP16C2T1_CH2 (0x0000041UL) +#define MD_DMA_PHSS_GP16C2T1_UP (0x0000042UL) +#define MD_DMA_PHSS_GP16C2T1_TRIG (0x0000043UL) +#define MD_DMA_PHSS_GP16C2T1_COM (0x0000044UL) +#define MD_DMA_PHSS_GP16C2T2_CH1 (0x0000046UL) +#define MD_DMA_PHSS_GP16C2T2_CH2 (0x0000047UL) +#define MD_DMA_PHSS_GP16C2T2_UP (0x0000048UL) +#define MD_DMA_PHSS_GP16C2T2_TRIG (0x0000049UL) +#define MD_DMA_PHSS_GP16C2T2_COM (0x000004AUL) +#define MD_DMA_PHSS_GP16C2T3_CH1 (0x000004CUL) +#define MD_DMA_PHSS_GP16C2T3_CH2 (0x000004DUL) +#define MD_DMA_PHSS_GP16C2T3_UP (0x000004EUL) +#define MD_DMA_PHSS_GP16C2T3_TRIG (0x000004FUL) +#define MD_DMA_PHSS_GP16C2T3_COM (0x0000050UL) +#define MD_DMA_PHSS_GP16C2T4_CH1 (0x0000052UL) +#define MD_DMA_PHSS_GP16C2T4_CH2 (0x0000053UL) +#define MD_DMA_PHSS_GP16C2T4_UP (0x0000054UL) +#define MD_DMA_PHSS_GP16C2T4_TRIG (0x0000055UL) +#define MD_DMA_PHSS_GP16C2T4_COM (0x0000056UL) +/** + * @} MD_DMA_PHSS + */ + +/** + * @} MD_DMA_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_DMA_Public_Macros DMA Public Macros + * @{ + */ + +/** + * @brief DMA Channel 5 TABORT Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch5tabie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH5TABIE_MSK); +} +/** + * @brief DMA Channel 5 Block Transmit Done Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch5btdie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH5BTDIE_MSK); +} +/** + * @brief DMA Channel 4 TABORT Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch4tabie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH4TABIE_MSK); +} +/** + * @brief DMA Channel 4 Block Transmit Done Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch4btdie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH4BTDIE_MSK); +} +/** + * @brief DMA Channel 3 TABORT Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch3tabie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH3TABIE_MSK); +} +/** + * @brief DMA Channel 3 Block Transmit Done Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch3btdie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH3BTDIE_MSK); +} +/** + * @brief DMA Channel 2 TABORT Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch2tabie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH2TABIE_MSK); +} +/** + * @brief DMA Channel 2 Block Transmit Done Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch2btdie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH2BTDIE_MSK); +} +/** + * @brief DMA Channel 1 TABORT Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch1tabie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH1TABIE_MSK); +} +/** + * @brief DMA Channel 1 Block Transmit Done Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch1btdie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH1BTDIE_MSK); +} +/** + * @brief DMA Channel 0 TABORT Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch0tabie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH0TABIE_MSK); +} +/** + * @brief DMA Channel 0 Block Transmit Done Interrupt Enable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_ier_ch0btdie(DMA_TypeDef *dma) +{ + SET_BIT(dma->IER, DMA_IER_CH0BTDIE_MSK); +} + +/** @defgroup MD_DMA_IER_CH5TABIE CH5TABIE + * @brief Set DMA Channel 5 TABORT Interrupt Enable bit for md_dma_set_ier() function used + * @param ch5tabie This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_dma_set_ier_ch5tabie_fun(ch5tabie) (ch5tabie<IER, (ch5tabie|ch5btdie|ch4tabie|ch4btdie|ch3tabie|ch3btdie|ch2tabie|ch2btdie|ch1tabie|ch1btdie|ch0tabie|ch0btdie)); +} + +/** + * @brief DMA Channel 5 TABORT Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch5tabid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH5TABID_MSK); +} +/** + * @brief DMA Channel 5 Block Transmit Done Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch5btdid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH5BTDID_MSK); +} +/** + * @brief DMA Channel 4 TABORT Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch4tabid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH4TABID_MSK); +} +/** + * @brief DMA Channel 4 Block Transmit Done Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch4btdid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH4BTDID_MSK); +} +/** + * @brief DMA Channel 3 TABORT Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch3tabid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH3TABID_MSK); +} +/** + * @brief DMA Channel 3 Block Transmit Done Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch3btdid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH3BTDID_MSK); +} +/** + * @brief DMA Channel 2 TABORT Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch2tabid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH2TABID_MSK); +} +/** + * @brief DMA Channel 2 Block Transmit Done Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch2btdid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH2BTDID_MSK); +} +/** + * @brief DMA Channel 1 TABORT Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch1tabid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH1TABID_MSK); +} +/** + * @brief DMA Channel 1 Block Transmit Done Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch1btdid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH1BTDID_MSK); +} +/** + * @brief DMA Channel 0 TABORT Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch0tabid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH0TABID_MSK); +} +/** + * @brief DMA Channel 0 Block Transmit Done Interrupt Disable bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_enable_idr_ch0btdid(DMA_TypeDef *dma) +{ + SET_BIT(dma->IDR, DMA_IDR_CH0BTDID_MSK); +} + + +/** + * @brief DMA Channel 5 TABORT Interrupt Valid Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch5tabivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH5TABIVS_MSK)>>DMA_IVS_CH5TABIVS_POS); +} +/** + * @brief DMA Channel 5 Block Transmit Done Interrupt Valid Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch5btdivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH5BTDIVS_MSK)>>DMA_IVS_CH5BTDIVS_POS); +} +/** + * @brief DMA Channel 4 TABORT Interrupt Valid Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch4tabivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH4TABIVS_MSK)>>DMA_IVS_CH4TABIVS_POS); +} +/** + * @brief DMA Channel 4 Block Transmit Done Interrupt Valid Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch4btdivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH4BTDIVS_MSK)>>DMA_IVS_CH4BTDIVS_POS); +} +/** + * @brief DMA Channel 3 TABORT Interrupt Valid Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch3tabivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH3TABIVS_MSK)>>DMA_IVS_CH3TABIVS_POS); +} +/** + * @brief DMA Channel 3 Block Transmit Done Interrupt Valid Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch3btdivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH3BTDIVS_MSK)>>DMA_IVS_CH3BTDIVS_POS); +} +/** + * @brief DMA Channel 2 TABORT Interrupt Valid Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch2tabivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH2TABIVS_MSK)>>DMA_IVS_CH2TABIVS_POS); +} +/** + * @brief DMA Channel 2 Block Transmit Done Interrupt Valid Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch2btdivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH2BTDIVS_MSK)>>DMA_IVS_CH2BTDIVS_POS); +} +/** + * @brief DMA Channel 1 TABORT Interrupt Valid Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch1tabivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH1TABIVS_MSK)>>DMA_IVS_CH1TABIVS_POS); +} +/** + * @brief DMA Channel 1 Block Transmit Done Interrupt Valid Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch1btdivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH1BTDIVS_MSK)>>DMA_IVS_CH1BTDIVS_POS); +} +/** + * @brief DMA Channel 0 TABORT Interrupt Valid Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch0tabivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH0TABIVS_MSK)>>DMA_IVS_CH0TABIVS_POS); +} +/** + * @brief DMA Channel 0 Block Transmit Done Interrupt Valid Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch0btdivs(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IVS, DMA_IVS_CH0BTDIVS_MSK)>>DMA_IVS_CH0BTDIVS_POS); +} +/** + * @brief Get DMA interrupt valid status register + * @param dma DMA Instance + * @retval DMA channel interrupt valid status + */ +__STATIC_INLINE uint32_t md_dma_get_ivs(DMA_TypeDef *dma) +{ + return (READ_REG(dma->IVS)); +} + +/** + * @brief DMA Channel 5 TABORT Raw Interrupt Flag Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch5tabrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH5TABRIF_MSK)>>DMA_RIF_CH5TABRIF_POS); +} +/** + * @brief DMA Channel 5 Block Transmit Done Raw Interrupt Flag Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch5btdrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH5BTDRIF_MSK)>>DMA_RIF_CH5BTDRIF_POS); +} +/** + * @brief DMA Channel 4 TABORT Raw Interrupt Flag Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch4tabrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH4TABRIF_MSK)>>DMA_RIF_CH4TABRIF_POS); +} +/** + * @brief DMA Channel 4 Block Transmit Done Raw Interrupt Flag Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch4btdrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH4BTDRIF_MSK)>>DMA_RIF_CH4BTDRIF_POS); +} +/** + * @brief DMA Channel 3 TABORT Raw Interrupt Flag Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch3tabrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH3TABRIF_MSK)>>DMA_RIF_CH3TABRIF_POS); +} +/** + * @brief DMA Channel 3 Block Transmit Done Raw Interrupt Flag Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch3btdrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH3BTDRIF_MSK)>>DMA_RIF_CH3BTDRIF_POS); +} +/** + * @brief DMA Channel 2 TABORT Raw Interrupt Flag Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch2tabrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH2TABRIF_MSK)>>DMA_RIF_CH2TABRIF_POS); +} +/** + * @brief DMA Channel 2 Block Transmit Done Raw Interrupt Flag Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch2btdrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH2BTDRIF_MSK)>>DMA_RIF_CH2BTDRIF_POS); +} +/** + * @brief DMA Channel 1 TABORT Raw Interrupt Flag Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch1tabrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH1TABRIF_MSK)>>DMA_RIF_CH1TABRIF_POS); +} +/** + * @brief DMA Channel 1 Block Transmit Done Raw Interrupt Flag Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch1btdrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH1BTDRIF_MSK)>>DMA_RIF_CH1BTDRIF_POS); +} +/** + * @brief DMA Channel 0 TABORT Raw Interrupt Flag Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch0tabrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH0TABRIF_MSK)>>DMA_RIF_CH0TABRIF_POS); +} +/** + * @brief DMA Channel 0 Block Transmit Done Raw Interrupt Flag Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ivs_ch0btdrif(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->RIF, DMA_RIF_CH0BTDRIF_MSK)>>DMA_RIF_CH0BTDRIF_POS); +} +/** + * @brief Get DMA raw interrupt flag status register + * @param dma DMA Instance + * @retval DMA channel raw interrupt flag status + */ +__STATIC_INLINE uint32_t md_dma_get_rif(DMA_TypeDef *dma) +{ + return (READ_REG(dma->RIF)); +} + +/** + * @brief DMA Channel 5 TABORT Interrupt Flag Masked Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch5tabifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH5TABIFM_MSK)>>DMA_IFM_CH5TABIFM_POS); +} +/** + * @brief DMA Channel 5 Block Transmit Done Interrupt Flag Masked Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch5btdifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH5BTDIFM_MSK)>>DMA_IFM_CH5BTDIFM_POS); +} +/** + * @brief DMA Channel 4 TABORT Interrupt Flag Masked Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch4tabifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH4TABIFM_MSK)>>DMA_IFM_CH4TABIFM_POS); +} +/** + * @brief DMA Channel 4 Block Transmit Done Interrupt Flag Masked Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch4btdifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH4BTDIFM_MSK)>>DMA_IFM_CH4BTDIFM_POS); +} +/** + * @brief DMA Channel 3 TABORT Interrupt Flag Masked Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch3tabifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH3TABIFM_MSK)>>DMA_IFM_CH3TABIFM_POS); +} +/** + * @brief DMA Channel 3 Block Transmit Done Interrupt Flag Masked Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch3btdifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH3BTDIFM_MSK)>>DMA_IFM_CH3BTDIFM_POS); +} +/** + * @brief DMA Channel 2 TABORT Interrupt Flag Masked Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch2tabifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH2TABIFM_MSK)>>DMA_IFM_CH2TABIFM_POS); +} +/** + * @brief DMA Channel 2 Block Transmit Done Interrupt Flag Masked Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch2btdifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH2BTDIFM_MSK)>>DMA_IFM_CH2BTDIFM_POS); +} +/** + * @brief DMA Channel 1 TABORT Interrupt Flag Masked Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch1tabifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH1TABIFM_MSK)>>DMA_IFM_CH1TABIFM_POS); +} +/** + * @brief DMA Channel 1 Block Transmit Done Interrupt Flag Masked Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch1btdifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH1BTDIFM_MSK)>>DMA_IFM_CH1BTDIFM_POS); +} +/** + * @brief DMA Channel 0 TABORT Interrupt Flag Masked Status bit + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch0tabifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH0TABIFM_MSK)>>DMA_IFM_CH0TABIFM_POS); +} +/** + * @brief DMA Channel 0 Block Transmit Done Interrupt Flag Masked Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_ifm_ch0btdifm(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->IFM, DMA_IFM_CH0BTDIFM_MSK)>>DMA_IFM_CH0BTDIFM_POS); +} +/** + * @brief Get DMA interrupt flag masked status register + * @param dma DMA Instance + * @retval DMA channel interrupt flag masked status + */ +__STATIC_INLINE uint32_t md_dma_get_ifm(DMA_TypeDef *dma) +{ + return (READ_REG(dma->IFM)); +} + + +/** + * @brief DMA Channel 5 TABORT Interrupt Clear bit + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch5tabicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH5TABICR_MSK); +} +/** + * @brief DMA Channel 5 Block Transmit Done Interrupt Clear bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch5btdicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH5BTDICR_MSK); +} +/** + * @brief DMA Channel 4 TABORT Interrupt Clear bit + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch4tabicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH4TABICR_MSK); +} +/** + * @brief DMA Channel 4 Block Transmit Done Interrupt Clear bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch4btdicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH4BTDICR_MSK); +} +/** + * @brief DMA Channel 3 TABORT Interrupt Clear bit + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch3tabicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH3TABICR_MSK); +} +/** + * @brief DMA Channel 3 Block Transmit Done Interrupt Clear bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch3btdicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH3BTDICR_MSK); +} +/** + * @brief DMA Channel 2 TABORT Interrupt Clear bit + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch2tabicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH2TABICR_MSK); +} +/** + * @brief DMA Channel 2 Block Transmit Done Interrupt Clear bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch2btdicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH2BTDICR_MSK); +} +/** + * @brief DMA Channel 1 TABORT Interrupt Clear bit + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch1tabicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH1TABICR_MSK); +} +/** + * @brief DMA Channel 1 Block Transmit Done Interrupt Clear bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch1btdicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH1BTDICR_MSK); +} +/** + * @brief DMA Channel 0 TABORT Interrupt Clear bit + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch0tabicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH0TABICR_MSK); +} +/** + * @brief DMA Channel 0 Block Transmit Done Interrupt Clear bit. + * @param dma DMA Instance + * @retval None + */ +__STATIC_INLINE void md_dma_clear_icr_ch0btdicr(DMA_TypeDef *dma) +{ + SET_BIT(dma->ICR, DMA_ICR_CH0BTDICR_MSK); +} + +/** @defgroup MD_DMA_ICR_CH5TABICR CH5TABICR + * @brief Set DMA Channel 5 TABORT Interrupt Clear bit for md_dma_set_icr() function used + * @param ch5tabicr This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_dma_set_icr_ch5tabicr_fun(ch5tabicr) (ch5tabicr<ICR, ( ch5tabicr|ch5btdicr|ch4tabicr|ch4btdicr|ch3tabicr|ch3btdicr|ch2tabicr|ch2btdicr| + ch1tabicr|ch1btdicr|ch0tabicr|ch0btdicr)); +} +/** + * @brief Set DMA interrupt clear register(2) + * @param dma DMA Instance + * @param icr is interrupt clear register + * @retval None + */ +__STATIC_INLINE void md_dma_set_icr_icr(DMA_TypeDef *dma, uint32_t icr) +{ + WRITE_REG(dma->ICR, icr); +} + + +/** + * @brief DMA Channel 5 PFCTRL Size not match,last data have error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch5pfser(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH5PFSER_MSK)>>DMA_EMSG_CH5PFSER_POS); +} +/** + * @brief DMA Channel 5 PFCTRL Over run Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch5pfov(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH5PFOV_MSK)>>DMA_EMSG_CH5PFOV_POS); +} +/** + * @brief DMA Channel 5 Setting Burst Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch5setbuer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH5SETBUER_MSK)>>DMA_EMSG_CH5SETBUER_POS); +} +/** + * @brief DMA Channel 5 Setting BCR Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch5setbcer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH5SETBCER_MSK)>>DMA_EMSG_CH5SETBCER_POS); +} +/** + * @brief DMA Channel 4 PFCTRL Size not match,last data have error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch4pfser(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH4PFSER_MSK)>>DMA_EMSG_CH4PFSER_POS); +} +/** + * @brief DMA Channel 4 PFCTRL Over run Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch4pfov(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH4PFOV_MSK)>>DMA_EMSG_CH4PFOV_POS); +} +/** + * @brief DMA Channel 4 Setting Burst Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch4setbuer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH4SETBUER_MSK)>>DMA_EMSG_CH4SETBUER_POS); +} +/** + * @brief DMA Channel 4 Setting BCR Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch4setbcer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH4SETBCER_MSK)>>DMA_EMSG_CH4SETBCER_POS); +} +/** + * @brief DMA Channel 3 PFCTRL Size not match,last data have error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch3pfser(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH3PFSER_MSK)>>DMA_EMSG_CH3PFSER_POS); +} +/** + * @brief DMA Channel 3 PFCTRL Over run Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch3pfov(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH3PFOV_MSK)>>DMA_EMSG_CH3PFOV_POS); +} +/** + * @brief DMA Channel 3 Setting Burst Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch3setbuer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH3SETBUER_MSK)>>DMA_EMSG_CH3SETBUER_POS); +} +/** + * @brief DMA Channel 3 Setting BCR Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch3setbcer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH3SETBCER_MSK)>>DMA_EMSG_CH3SETBCER_POS); +} +/** + * @brief DMA Channel 2 PFCTRL Size not match,last data have error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch2pfser(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH2PFSER_MSK)>>DMA_EMSG_CH2PFSER_POS); +} +/** + * @brief DMA Channel 2 PFCTRL Over run Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch2pfov(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH2PFOV_MSK)>>DMA_EMSG_CH2PFOV_POS); +} +/** + * @brief DMA Channel 2 Setting Burst Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch2setbuer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH2SETBUER_MSK)>>DMA_EMSG_CH2SETBUER_POS); +} +/** + * @brief DMA Channel 2 Setting BCR Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch2setbcer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH2SETBCER_MSK)>>DMA_EMSG_CH2SETBCER_POS); +} +/** + * @brief DMA Channel 1 PFCTRL Size not match,last data have error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch1pfser(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH1PFSER_MSK)>>DMA_EMSG_CH1PFSER_POS); +} +/** + * @brief DMA Channel 1 PFCTRL Over run Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch1pfov(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH1PFOV_MSK)>>DMA_EMSG_CH1PFOV_POS); +} +/** + * @brief DMA Channel 1 Setting Burst Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch1setbuer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH1SETBUER_MSK)>>DMA_EMSG_CH1SETBUER_POS); +} +/** + * @brief DMA Channel 1 Setting BCR Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch1setbcer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH1SETBCER_MSK)>>DMA_EMSG_CH1SETBCER_POS); +} +/** + * @brief DMA Channel 0 PFCTRL Size not match,last data have error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch0pfser(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH0PFSER_MSK)>>DMA_EMSG_CH0PFSER_POS); +} +/** + * @brief DMA Channel 0 PFCTRL Over run Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch0pfov(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH0PFOV_MSK)>>DMA_EMSG_CH0PFOV_POS); +} +/** + * @brief DMA Channel 0 Setting Burst Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch0setbuer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH0SETBUER_MSK)>>DMA_EMSG_CH0SETBUER_POS); +} +/** + * @brief DMA Channel 0 Setting BCR Error Status bit. + * @param dma DMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_dma_get_emsg_ch0setbcer(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->EMSG, DMA_EMSG_CH0SETBCER_MSK)>>DMA_EMSG_CH0SETBCER_POS); +} +/** + * @brief Get DMA error message register + * @param dma DMA Instance + * @retval DMA channel error message status + */ +__STATIC_INLINE uint32_t md_dma_get_emsg(DMA_TypeDef *dma) +{ + return (READ_REG(dma->EMSG)); +} + +/** + * @brief Set Destination Increment Offset Size bit. + * @note This bit has no meaning if bit DINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if DBUSEL are different from 00. + * @param dma DMA Instance + * @param dincos can be one of the following values: + * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL + * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_dincos(DMA_TypeDef *dma, uint32_t dincos) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_DINCOS_MSK, (dincos<CSR0, DMA_CSR0_DINCOS_MSK)>>DMA_CSR0_DINCOS_POS); +} +/** + * @brief Set Destination Transfer Burst Selection. + * @param dma DMA Instance + * @param dbusel can be one of the following values: + * @arg @ref MD_DMA_DBUSEL_SINGLE + * @arg @ref MD_DMA_DBUSEL_WRAP4 + * @arg @ref MD_DMA_DBUSEL_INCR4 + * @arg @ref MD_DMA_DBUSEL_WRAP8 + * @arg @ref MD_DMA_DBUSEL_INCR8 + * @arg @ref MD_DMA_DBUSEL_WRAP16 + * @arg @ref MD_DMA_DBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_dbusel(DMA_TypeDef *dma, uint32_t dbusel) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_DBUSEL_MSK, (dbusel<CSR0, DMA_CSR0_DBUSEL_MSK)>>DMA_CSR0_DBUSEL_POSS); +} +/** + * @brief Set Destination Transfer Data Width Selection. + * @param dma DMA Instance + * @param ddwsel can be one of the following values: + * @arg @ref MD_DMA_DDWSEL_ONE_BYTE + * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_DDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_DDWSEL_MSK, (ddwsel<CSR0, DMA_CSR0_DDWSEL_MSK)>>DMA_CSR0_DDWSEL_POSS); +} +/** + * @brief Set Destination Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_dinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_DINC_MSK, (dinc<CSR0, DMA_CSR0_DINC_MSK)>>DMA_CSR0_DINC_POS); +} +/** + * @brief Set Source Increment Offset Size bit. + * @note This bit has no meaning if bit SINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if SBUSEL are different from 00. + * @param dma DMA Instance + * @param sincos can be one of the following values: + * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL + * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_sincos(DMA_TypeDef *dma, uint32_t sincos) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_SINCOS_MSK, (sincos<CSR0, DMA_CSR0_SINCOS_MSK)>>DMA_CSR0_SINCOS_POS); +} +/** + * @brief Set Source Transfer Burst Selection. + * @param dma DMA Instance + * @param sbusel can be one of the following values: + * @arg @ref MD_DMA_SBUSEL_SINGLE + * @arg @ref MD_DMA_SBUSEL_WRAP4 + * @arg @ref MD_DMA_SBUSEL_INCR4 + * @arg @ref MD_DMA_SBUSEL_WRAP8 + * @arg @ref MD_DMA_SBUSEL_INCR8 + * @arg @ref MD_DMA_SBUSEL_WRAP16 + * @arg @ref MD_DMA_SBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_sbusel(DMA_TypeDef *dma, uint32_t sbusel) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_SBUSEL_MSK, (sbusel<CSR0, DMA_CSR0_SBUSEL_MSK)>>DMA_CSR0_SBUSEL_POSS); +} +/** + * @brief Set Source Transfer Data Width Selection. + * @param dma DMA Instance + * @param sdwsel can be one of the following values: + * @arg @ref MD_DMA_SDWSEL_ONE_BYTE + * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_SDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_SDWSEL_MSK, (sdwsel<CSR0, DMA_CSR0_SDWSEL_MSK)>>DMA_CSR0_SDWSEL_POSS); +} +/** + * @brief Set Source Transfer Increment Mode + * @param dma DMA Instance + * @param sinc can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_sinc(DMA_TypeDef *dma, uint32_t sinc) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_SINC_MSK, (sinc<CSR0, DMA_CSR0_SINC_MSK)>>DMA_CSR0_SINC_POS); +} +/** + * @brief Set Peripheral Handshake Software Select + * @param dma DMA Instance + * @param phss can be one of the following values: + * @arg @ref MD_DMA_PHSS_UART1_TX + * @arg @ref MD_DMA_PHSS_UART2_TX + * @arg @ref MD_DMA_PHSS_UART3_TX + * @arg @ref MD_DMA_PHSS_SUART1_TX + * @arg @ref MD_DMA_PHSS_SUART2_TX + * @arg @ref MD_DMA_PHSS_SPI1_TX + * @arg @ref MD_DMA_PHSS_SPI2_TX + * @arg @ref MD_DMA_PHSS_I2C1_TX + * @arg @ref MD_DMA_PHSS_I2C2_TX + * @arg @ref MD_DMA_PHSS_AES_IN + * @arg @ref MD_DMA_PHSS_DAC + * @arg @ref MD_DMA_PHSS_CRC + * @arg @ref MD_DMA_PHSS_UART1_RX + * @arg @ref MD_DMA_PHSS_UART2_RX + * @arg @ref MD_DMA_PHSS_UART3_RX + * @arg @ref MD_DMA_PHSS_SUART1_RX + * @arg @ref MD_DMA_PHSS_SUART2_RX + * @arg @ref MD_DMA_PHSS_SPI1_RTX + * @arg @ref MD_DMA_PHSS_SPI2_RX + * @arg @ref MD_DMA_PHSS_I2C1_RX + * @arg @ref MD_DMA_PHSS_I2C2_RX + * @arg @ref MD_DMA_PHSS_AES_OUT + * @arg @ref MD_DMA_PHSS_ADCSS0 + * @arg @ref MD_DMA_PHSS_ADCSS1 + * @arg @ref MD_DMA_PHSS_ADCSS2 + * @arg @ref MD_DMA_PHSS_ADCSS3 + * @arg @ref MD_DMA_PHSS_BS16T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_AD16C4T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_AD16C4T1_COM + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP32C4T1_UP + * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T1_UP + * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T2_UP + * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T3_UP + * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T1_UP + * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_COM + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T2_UP + * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T2_COM + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T3_UP + * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T3_COM + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T4_UP + * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T4_COM + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_phss(DMA_TypeDef *dma, uint32_t phss) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_PHSS_MSK, (phss<CSR0, DMA_CSR0_PHSS_MSK)>>DMA_CSR0_PHSS_POSS); +} +/** + * @brief Set DMA Channel Priority. + * @param dma DMA Instance + * @param chpri can be one of the following values: + * @arg @ref MD_DMA_CHPRI_LV0 + * @arg @ref MD_DMA_CHPRI_LV1 + * @arg @ref MD_DMA_CHPRI_LV2 + * @arg @ref MD_DMA_CHPRI_LV3 + * @arg @ref MD_DMA_CHPRI_LV4 + * @arg @ref MD_DMA_CHPRI_LV5 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_chpri(DMA_TypeDef *dma, uint32_t chpri) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_CHPRI_MSK, (chpri<CSR0, DMA_CSR0_CHPRI_MSK)>>DMA_CSR0_CHPRI_POSS); +} +/** + * @brief Set DMA Mode Select. + * @param dma DMA Instance + * @param modesel can be one of the following values: + * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM + * @arg @ref MD_DMA_MODESEL_PER_TO_MEM + * @arg @ref MD_DMA_MODESEL_MEM_TO_PER + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_modesel(DMA_TypeDef *dma, uint32_t modesel) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_MODESEL_MSK, (modesel<CSR0, DMA_CSR0_MODESEL_MSK)>>DMA_CSR0_MODESEL_POSS); +} +/** + * @brief Set Direct Mode Enable. + * @param dma DMA Instance + * @param dirmden can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_dirmden(DMA_TypeDef *dma, uint32_t dirmden) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_DIRMDEN_MSK, (dirmden<CSR0, DMA_CSR0_DIRMDEN_MSK)>>DMA_CSR0_DIRMDEN_POS); +} +/** + * @brief Set Peripheral flow controller + * @param dma DMA Instance + * @param pfctrl can be one of the following values: + * @arg @ref MD_DMA_PFCTRL_DMA_CTRL + * @arg @ref MD_DMA_PFCTRL_PER_CTRL + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_PFCTRL_MSK, (pfctrl<CSR0, DMA_CSR0_PFCTRL_MSK)>>DMA_CSR0_PFCTRL_POS); +} +/** + * @brief Set Circular mode + * @param dma DMA Instance + * @param circ can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_circ(DMA_TypeDef *dma, uint32_t circ) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_CIRC_MSK, (circ<CSR0, DMA_CSR0_CIRC_MSK)>>DMA_CSR0_CIRC_POS); +} +/** + * @brief Set DMA Channel Enable. + * @param dma DMA Instance + * @param chen can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr0_chen(DMA_TypeDef *dma, uint32_t chen) +{ + MODIFY_REG(dma->CSR0, DMA_CSR0_CHEN_MSK, (chen<CSR0, DMA_CSR0_CHEN_MSK)>>DMA_CSR0_CHEN_POS); +} + +/** @defgroup MD_DMA_CSR0_DINCOS DINCOS + * @brief Set Destination Increment Offset Size bit for md_dma_set_cs0() function used + * @param dincos This parameter can be one of the following values: + * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL + * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 + * @{ + */ +#define md_dma_set_csr0_dincos_fun(dincos) (dincos<CSR0, (dincos|dbusel|ddwsel|dinc|sincos|sbusel|sdwsel|sinc| + phss|chpri|modesel|dirmden|pfctrl|circ|chen)); +} + + +/** + * @brief Set DMA Transfer Source Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param sar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_sar0_sar(DMA_TypeDef *dma, uint32_t sar) +{ + MODIFY_REG(dma->SAR0, DMA_SAR0_SAR_MSK, (sar<SAR0, DMA_SAR0_SAR_MSK)>>DMA_SAR0_SAR_POSS); +} + +/** + * @brief Set DMA Transfer Destination Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param dar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_dar0_dar(DMA_TypeDef *dma, uint32_t dar) +{ + MODIFY_REG(dma->DAR0, DMA_DAR0_DAR_MSK, (dar<DAR0, DMA_DAR0_DAR_MSK)>>DMA_DAR0_DAR_POSS); +} + +/** + * @brief Get DMA Current Transfer Byte Count + * @param dma DMA Instance + * @retval The retval can be one of the following values: + * @arg Max Value 65535 + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_dma_get_bcr0_cbcr(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->BCR0, DMA_BCR0_CBCR_MSK)>>DMA_BCR0_CBCR_POSS); +} +/** + * @brief Set DMA Transfer Byte Count Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param bcr This field indicates a 16-bit transfer byte count of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_bcr0_bcr(DMA_TypeDef *dma, uint32_t bcr) +{ + MODIFY_REG(dma->BCR0, DMA_BCR0_BCR_MSK, (bcr<BCR0, DMA_BCR0_BCR_MSK)>>DMA_BCR0_BCR_POSS); +} + +/** + * @brief Set Destination Increment Offset Size bit. + * @note This bit has no meaning if bit DINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if DBUSEL are different from 00. + * @param dma DMA Instance + * @param dincos can be one of the following values: + * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL + * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_dincos(DMA_TypeDef *dma, uint32_t dincos) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_DINCOS_MSK, (dincos<CSR1, DMA_CSR1_DINCOS_MSK)>>DMA_CSR1_DINCOS_POS); +} +/** + * @brief Set Destination Transfer Burst Selection. + * @param dma DMA Instance + * @param dbusel can be one of the following values: + * @arg @ref MD_DMA_DBUSEL_SINGLE + * @arg @ref MD_DMA_DBUSEL_WRAP4 + * @arg @ref MD_DMA_DBUSEL_INCR4 + * @arg @ref MD_DMA_DBUSEL_WRAP8 + * @arg @ref MD_DMA_DBUSEL_INCR8 + * @arg @ref MD_DMA_DBUSEL_WRAP16 + * @arg @ref MD_DMA_DBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_dbusel(DMA_TypeDef *dma, uint32_t dbusel) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_DBUSEL_MSK, (dbusel<CSR1, DMA_CSR1_DBUSEL_MSK)>>DMA_CSR1_DBUSEL_POSS); +} +/** + * @brief Set Destination Transfer Data Width Selection. + * @param dma DMA Instance + * @param ddwsel can be one of the following values: + * @arg @ref MD_DMA_DDWSEL_ONE_BYTE + * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_DDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_DDWSEL_MSK, (ddwsel<CSR1, DMA_CSR1_DDWSEL_MSK)>>DMA_CSR1_DDWSEL_POSS); +} +/** + * @brief Set Destination Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_dinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_DINC_MSK, (dinc<CSR1, DMA_CSR1_DINC_MSK)>>DMA_CSR1_DINC_POS); +} +/** + * @brief Set Source Increment Offset Size bit. + * @note This bit has no meaning if bit SINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if SBUSEL are different from 00. + * @param dma DMA Instance + * @param sincos can be one of the following values: + * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL + * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_sincos(DMA_TypeDef *dma, uint32_t sincos) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_SINCOS_MSK, (sincos<CSR1, DMA_CSR1_SINCOS_MSK)>>DMA_CSR1_SINCOS_POS); +} +/** + * @brief Set Source Transfer Burst Selection. + * @param dma DMA Instance + * @param sbusel can be one of the following values: + * @arg @ref MD_DMA_SBUSEL_SINGLE + * @arg @ref MD_DMA_SBUSEL_WRAP4 + * @arg @ref MD_DMA_SBUSEL_INCR4 + * @arg @ref MD_DMA_SBUSEL_WRAP8 + * @arg @ref MD_DMA_SBUSEL_INCR8 + * @arg @ref MD_DMA_SBUSEL_WRAP16 + * @arg @ref MD_DMA_SBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_sbusel(DMA_TypeDef *dma, uint32_t sbusel) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_SBUSEL_MSK, (sbusel<CSR1, DMA_CSR1_SBUSEL_MSK)>>DMA_CSR1_SBUSEL_POSS); +} +/** + * @brief Set Source Transfer Data Width Selection. + * @param dma DMA Instance + * @param sdwsel can be one of the following values: + * @arg @ref MD_DMA_SDWSEL_ONE_BYTE + * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_SDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_SDWSEL_MSK, (sdwsel<CSR1, DMA_CSR1_SDWSEL_MSK)>>DMA_CSR1_SDWSEL_POSS); +} +/** + * @brief Set Source Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_sinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_SINC_MSK, (dinc<CSR1, DMA_CSR1_SINC_MSK)>>DMA_CSR1_SINC_POS); +} +/** + * @brief Set Peripheral Handshake Software Select + * @param dma DMA Instance + * @param phss can be one of the following values: + * @arg @ref MD_DMA_PHSS_UART1_TX + * @arg @ref MD_DMA_PHSS_UART2_TX + * @arg @ref MD_DMA_PHSS_UART3_TX + * @arg @ref MD_DMA_PHSS_SUART1_TX + * @arg @ref MD_DMA_PHSS_SUART2_TX + * @arg @ref MD_DMA_PHSS_SPI1_TX + * @arg @ref MD_DMA_PHSS_SPI2_TX + * @arg @ref MD_DMA_PHSS_I2C1_TX + * @arg @ref MD_DMA_PHSS_I2C2_TX + * @arg @ref MD_DMA_PHSS_AES_IN + * @arg @ref MD_DMA_PHSS_DAC + * @arg @ref MD_DMA_PHSS_CRC + * @arg @ref MD_DMA_PHSS_UART1_RX + * @arg @ref MD_DMA_PHSS_UART2_RX + * @arg @ref MD_DMA_PHSS_UART3_RX + * @arg @ref MD_DMA_PHSS_SUART1_RX + * @arg @ref MD_DMA_PHSS_SUART2_RX + * @arg @ref MD_DMA_PHSS_SPI1_RTX + * @arg @ref MD_DMA_PHSS_SPI2_RX + * @arg @ref MD_DMA_PHSS_I2C1_RX + * @arg @ref MD_DMA_PHSS_I2C2_RX + * @arg @ref MD_DMA_PHSS_AES_OUT + * @arg @ref MD_DMA_PHSS_ADCSS0 + * @arg @ref MD_DMA_PHSS_ADCSS1 + * @arg @ref MD_DMA_PHSS_ADCSS2 + * @arg @ref MD_DMA_PHSS_ADCSS3 + * @arg @ref MD_DMA_PHSS_BS16T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_AD16C4T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_AD16C4T1_COM + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP32C4T1_UP + * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T1_UP + * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T2_UP + * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T3_UP + * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T1_UP + * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_COM + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T2_UP + * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T2_COM + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T3_UP + * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T3_COM + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T4_UP + * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T4_COM + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_phss(DMA_TypeDef *dma, uint32_t phss) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_PHSS_MSK, (phss<CSR1, DMA_CSR1_PHSS_MSK)>>DMA_CSR1_PHSS_POSS); +} +/** + * @brief Set DMA Channel Priority. + * @param dma DMA Instance + * @param chpri can be one of the following values: + * @arg @ref MD_DMA_CHPRI_LV0 + * @arg @ref MD_DMA_CHPRI_LV1 + * @arg @ref MD_DMA_CHPRI_LV2 + * @arg @ref MD_DMA_CHPRI_LV3 + * @arg @ref MD_DMA_CHPRI_LV4 + * @arg @ref MD_DMA_CHPRI_LV5 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_chpri(DMA_TypeDef *dma, uint32_t chpri) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_CHPRI_MSK, (chpri<CSR1, DMA_CSR1_CHPRI_MSK)>>DMA_CSR1_CHPRI_POSS); +} +/** + * @brief Set DMA Mode Select. + * @param dma DMA Instance + * @param modesel can be one of the following values: + * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM + * @arg @ref MD_DMA_MODESEL_PER_TO_MEM + * @arg @ref MD_DMA_MODESEL_MEM_TO_PER + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_modesel(DMA_TypeDef *dma, uint32_t modesel) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_MODESEL_MSK, (modesel<CSR1, DMA_CSR1_MODESEL_MSK)>>DMA_CSR1_MODESEL_POSS); +} +/** + * @brief Set Direct Mode Enable. + * @param dma DMA Instance + * @param dirmden can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_dirmden(DMA_TypeDef *dma, uint32_t dirmden) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_DIRMDEN_MSK, (dirmden<CSR1, DMA_CSR1_DIRMDEN_MSK)>>DMA_CSR1_DIRMDEN_POS); +} +/** + * @brief Set Peripheral flow controller + * @param dma DMA Instance + * @param pfctrl can be one of the following values: + * @arg @ref MD_DMA_PFCTRL_DMA_CTRL + * @arg @ref MD_DMA_PFCTRL_PER_CTRL + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_PFCTRL_MSK, (pfctrl<CSR1, DMA_CSR1_PFCTRL_MSK)>>DMA_CSR1_PFCTRL_POS); +} +/** + * @brief Set Circular mode + * @param dma DMA Instance + * @param circ can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_circ(DMA_TypeDef *dma, uint32_t circ) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_CIRC_MSK, (circ<CSR1, DMA_CSR1_CIRC_MSK)>>DMA_CSR1_CIRC_POS); +} +/** + * @brief Set DMA Channel Enable. + * @param dma DMA Instance + * @param chen can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr1_chen(DMA_TypeDef *dma, uint32_t chen) +{ + MODIFY_REG(dma->CSR1, DMA_CSR1_CHEN_MSK, (chen<CSR1, DMA_CSR1_CHEN_MSK)>>DMA_CSR1_CHEN_POS); +} + +/** + * @brief Set DMA Transfer Source Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param sar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_sar1_sar(DMA_TypeDef *dma, uint32_t sar) +{ + MODIFY_REG(dma->SAR1, DMA_SAR1_SAR_MSK, (sar<SAR1, DMA_SAR1_SAR_MSK)>>DMA_SAR1_SAR_POSS); +} + +/** + * @brief Set DMA Transfer Destination Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param dar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_dar1_dar(DMA_TypeDef *dma, uint32_t dar) +{ + MODIFY_REG(dma->DAR1, DMA_DAR1_DAR_MSK, (dar<DAR1, DMA_DAR1_DAR_MSK)>>DMA_DAR1_DAR_POSS); +} + +/** + * @brief Get DMA Current Transfer Byte Count + * @param dma DMA Instance + * @retval The retval can be one of the following values: + * @arg Max Value 65535 + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_dma_get_bcr1_cbcr(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->BCR1, DMA_BCR1_CBCR_MSK)>>DMA_BCR1_CBCR_POSS); +} +/** + * @brief Set DMA Transfer Byte Count Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param bcr This field indicates a 16-bit transfer byte count of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_bcr1_bcr(DMA_TypeDef *dma, uint32_t bcr) +{ + MODIFY_REG(dma->BCR1, DMA_BCR1_BCR_MSK, (bcr<BCR1, DMA_BCR1_BCR_MSK)>>DMA_BCR1_BCR_POSS); +} + +/** + * @brief Set Destination Increment Offset Size bit. + * @note This bit has no meaning if bit DINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if DBUSEL are different from 00. + * @param dma DMA Instance + * @param dincos can be one of the following values: + * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL + * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_dincos(DMA_TypeDef *dma, uint32_t dincos) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_DINCOS_MSK, (dincos<CSR2, DMA_CSR2_DINCOS_MSK)>>DMA_CSR2_DINCOS_POS); +} +/** + * @brief Set Destination Transfer Burst Selection. + * @param dma DMA Instance + * @param dbusel can be one of the following values: + * @arg @ref MD_DMA_DBUSEL_SINGLE + * @arg @ref MD_DMA_DBUSEL_WRAP4 + * @arg @ref MD_DMA_DBUSEL_INCR4 + * @arg @ref MD_DMA_DBUSEL_WRAP8 + * @arg @ref MD_DMA_DBUSEL_INCR8 + * @arg @ref MD_DMA_DBUSEL_WRAP16 + * @arg @ref MD_DMA_DBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_dbusel(DMA_TypeDef *dma, uint32_t dbusel) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_DBUSEL_MSK, (dbusel<CSR2, DMA_CSR2_DBUSEL_MSK)>>DMA_CSR2_DBUSEL_POSS); +} +/** + * @brief Set Destination Transfer Data Width Selection. + * @param dma DMA Instance + * @param ddwsel can be one of the following values: + * @arg @ref MD_DMA_DDWSEL_ONE_BYTE + * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_DDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_DDWSEL_MSK, (ddwsel<CSR2, DMA_CSR2_DDWSEL_MSK)>>DMA_CSR2_DDWSEL_POSS); +} +/** + * @brief Set Destination Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_dinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_DINC_MSK, (dinc<CSR2, DMA_CSR2_DINC_MSK)>>DMA_CSR2_DINC_POS); +} +/** + * @brief Set Source Increment Offset Size bit. + * @note This bit has no meaning if bit SINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if SBUSEL are different from 00. + * @param dma DMA Instance + * @param sincos can be one of the following values: + * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL + * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_sincos(DMA_TypeDef *dma, uint32_t sincos) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_SINCOS_MSK, (sincos<CSR2, DMA_CSR2_SINCOS_MSK)>>DMA_CSR2_SINCOS_POS); +} +/** + * @brief Set Source Transfer Burst Selection. + * @param dma DMA Instance + * @param sbusel can be one of the following values: + * @arg @ref MD_DMA_SBUSEL_SINGLE + * @arg @ref MD_DMA_SBUSEL_WRAP4 + * @arg @ref MD_DMA_SBUSEL_INCR4 + * @arg @ref MD_DMA_SBUSEL_WRAP8 + * @arg @ref MD_DMA_SBUSEL_INCR8 + * @arg @ref MD_DMA_SBUSEL_WRAP16 + * @arg @ref MD_DMA_SBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_sbusel(DMA_TypeDef *dma, uint32_t sbusel) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_SBUSEL_MSK, (sbusel<CSR2, DMA_CSR2_SBUSEL_MSK)>>DMA_CSR2_SBUSEL_POSS); +} +/** + * @brief Set Source Transfer Data Width Selection. + * @param dma DMA Instance + * @param sdwsel can be one of the following values: + * @arg @ref MD_DMA_SDWSEL_ONE_BYTE + * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_SDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_SDWSEL_MSK, (sdwsel<CSR2, DMA_CSR2_SDWSEL_MSK)>>DMA_CSR2_SDWSEL_POSS); +} +/** + * @brief Set Source Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_sinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_SINC_MSK, (dinc<CSR2, DMA_CSR2_SINC_MSK)>>DMA_CSR2_SINC_POS); +} +/** + * @brief Set Peripheral Handshake Software Select + * @param dma DMA Instance + * @param phss can be one of the following values: + * @arg @ref MD_DMA_PHSS_UART1_TX + * @arg @ref MD_DMA_PHSS_UART2_TX + * @arg @ref MD_DMA_PHSS_UART3_TX + * @arg @ref MD_DMA_PHSS_SUART1_TX + * @arg @ref MD_DMA_PHSS_SUART2_TX + * @arg @ref MD_DMA_PHSS_SPI1_TX + * @arg @ref MD_DMA_PHSS_SPI2_TX + * @arg @ref MD_DMA_PHSS_I2C1_TX + * @arg @ref MD_DMA_PHSS_I2C2_TX + * @arg @ref MD_DMA_PHSS_AES_IN + * @arg @ref MD_DMA_PHSS_DAC + * @arg @ref MD_DMA_PHSS_CRC + * @arg @ref MD_DMA_PHSS_UART1_RX + * @arg @ref MD_DMA_PHSS_UART2_RX + * @arg @ref MD_DMA_PHSS_UART3_RX + * @arg @ref MD_DMA_PHSS_SUART1_RX + * @arg @ref MD_DMA_PHSS_SUART2_RX + * @arg @ref MD_DMA_PHSS_SPI1_RTX + * @arg @ref MD_DMA_PHSS_SPI2_RX + * @arg @ref MD_DMA_PHSS_I2C1_RX + * @arg @ref MD_DMA_PHSS_I2C2_RX + * @arg @ref MD_DMA_PHSS_AES_OUT + * @arg @ref MD_DMA_PHSS_ADCSS0 + * @arg @ref MD_DMA_PHSS_ADCSS1 + * @arg @ref MD_DMA_PHSS_ADCSS2 + * @arg @ref MD_DMA_PHSS_ADCSS3 + * @arg @ref MD_DMA_PHSS_BS16T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_AD16C4T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_AD16C4T1_COM + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP32C4T1_UP + * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T1_UP + * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T2_UP + * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T3_UP + * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T1_UP + * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_COM + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T2_UP + * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T2_COM + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T3_UP + * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T3_COM + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T4_UP + * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T4_COM + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_phss(DMA_TypeDef *dma, uint32_t phss) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_PHSS_MSK, (phss<CSR2, DMA_CSR2_PHSS_MSK)>>DMA_CSR2_PHSS_POSS); +} +/** + * @brief Set DMA Channel Priority. + * @param dma DMA Instance + * @param chpri can be one of the following values: + * @arg @ref MD_DMA_CHPRI_LV0 + * @arg @ref MD_DMA_CHPRI_LV1 + * @arg @ref MD_DMA_CHPRI_LV2 + * @arg @ref MD_DMA_CHPRI_LV3 + * @arg @ref MD_DMA_CHPRI_LV4 + * @arg @ref MD_DMA_CHPRI_LV5 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_chpri(DMA_TypeDef *dma, uint32_t chpri) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_CHPRI_MSK, (chpri<CSR2, DMA_CSR2_CHPRI_MSK)>>DMA_CSR2_CHPRI_POSS); +} +/** + * @brief Set DMA Mode Select. + * @param dma DMA Instance + * @param modesel can be one of the following values: + * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM + * @arg @ref MD_DMA_MODESEL_PER_TO_MEM + * @arg @ref MD_DMA_MODESEL_MEM_TO_PER + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_modesel(DMA_TypeDef *dma, uint32_t modesel) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_MODESEL_MSK, (modesel<CSR2, DMA_CSR2_MODESEL_MSK)>>DMA_CSR2_MODESEL_POSS); +} +/** + * @brief Set Direct Mode Enable. + * @param dma DMA Instance + * @param dirmden can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_dirmden(DMA_TypeDef *dma, uint32_t dirmden) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_DIRMDEN_MSK, (dirmden<CSR2, DMA_CSR2_DIRMDEN_MSK)>>DMA_CSR2_DIRMDEN_POS); +} +/** + * @brief Set Peripheral flow controller + * @param dma DMA Instance + * @param pfctrl can be one of the following values: + * @arg @ref MD_DMA_PFCTRL_DMA_CTRL + * @arg @ref MD_DMA_PFCTRL_PER_CTRL + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_PFCTRL_MSK, (pfctrl<CSR2, DMA_CSR2_PFCTRL_MSK)>>DMA_CSR2_PFCTRL_POS); +} +/** + * @brief Set Circular mode + * @param dma DMA Instance + * @param circ can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_circ(DMA_TypeDef *dma, uint32_t circ) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_CIRC_MSK, (circ<CSR2, DMA_CSR2_CIRC_MSK)>>DMA_CSR2_CIRC_POS); +} +/** + * @brief Set DMA Channel Enable. + * @param dma DMA Instance + * @param chen can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr2_chen(DMA_TypeDef *dma, uint32_t chen) +{ + MODIFY_REG(dma->CSR2, DMA_CSR2_CHEN_MSK, (chen<CSR2, DMA_CSR2_CHEN_MSK)>>DMA_CSR2_CHEN_POS); +} + +/** + * @brief Set DMA Transfer Source Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param sar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_sar2_sar(DMA_TypeDef *dma, uint32_t sar) +{ + MODIFY_REG(dma->SAR2, DMA_SAR2_SAR_MSK, (sar<SAR2, DMA_SAR2_SAR_MSK)>>DMA_SAR2_SAR_POSS); +} + +/** + * @brief Set DMA Transfer Destination Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param dar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_dar2_dar(DMA_TypeDef *dma, uint32_t dar) +{ + MODIFY_REG(dma->DAR2, DMA_DAR2_DAR_MSK, (dar<DAR2, DMA_DAR2_DAR_MSK)>>DMA_DAR2_DAR_POSS); +} + +/** + * @brief Get DMA Current Transfer Byte Count + * @param dma DMA Instance + * @retval The retval can be one of the following values: + * @arg Max Value 65535 + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_dma_get_bcr2_cbcr(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->BCR2, DMA_BCR2_CBCR_MSK)>>DMA_BCR2_CBCR_POSS); +} +/** + * @brief Set DMA Transfer Byte Count Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param bcr This field indicates a 16-bit transfer byte count of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_bcr2_bcr(DMA_TypeDef *dma, uint32_t bcr) +{ + MODIFY_REG(dma->BCR2, DMA_BCR2_BCR_MSK, (bcr<BCR2, DMA_BCR2_BCR_MSK)>>DMA_BCR2_BCR_POSS); +} + +/** + * @brief Set Destination Increment Offset Size bit. + * @note This bit has no meaning if bit DINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if DBUSEL are different from 00. + * @param dma DMA Instance + * @param dincos can be one of the following values: + * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL + * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_dincos(DMA_TypeDef *dma, uint32_t dincos) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_DINCOS_MSK, (dincos<CSR3, DMA_CSR3_DINCOS_MSK)>>DMA_CSR3_DINCOS_POS); +} +/** + * @brief Set Destination Transfer Burst Selection. + * @param dma DMA Instance + * @param dbusel can be one of the following values: + * @arg @ref MD_DMA_DBUSEL_SINGLE + * @arg @ref MD_DMA_DBUSEL_WRAP4 + * @arg @ref MD_DMA_DBUSEL_INCR4 + * @arg @ref MD_DMA_DBUSEL_WRAP8 + * @arg @ref MD_DMA_DBUSEL_INCR8 + * @arg @ref MD_DMA_DBUSEL_WRAP16 + * @arg @ref MD_DMA_DBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_dbusel(DMA_TypeDef *dma, uint32_t dbusel) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_DBUSEL_MSK, (dbusel<CSR3, DMA_CSR3_DBUSEL_MSK)>>DMA_CSR3_DBUSEL_POSS); +} +/** + * @brief Set Destination Transfer Data Width Selection. + * @param dma DMA Instance + * @param ddwsel can be one of the following values: + * @arg @ref MD_DMA_DDWSEL_ONE_BYTE + * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_DDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_DDWSEL_MSK, (ddwsel<CSR3, DMA_CSR3_DDWSEL_MSK)>>DMA_CSR3_DDWSEL_POSS); +} +/** + * @brief Set Destination Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_dinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_DINC_MSK, (dinc<CSR3, DMA_CSR3_DINC_MSK)>>DMA_CSR3_DINC_POS); +} +/** + * @brief Set Source Increment Offset Size bit. + * @note This bit has no meaning if bit SINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if SBUSEL are different from 00. + * @param dma DMA Instance + * @param sincos can be one of the following values: + * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL + * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_sincos(DMA_TypeDef *dma, uint32_t sincos) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_SINCOS_MSK, (sincos<CSR3, DMA_CSR3_SINCOS_MSK)>>DMA_CSR3_SINCOS_POS); +} +/** + * @brief Set Source Transfer Burst Selection. + * @param dma DMA Instance + * @param sbusel can be one of the following values: + * @arg @ref MD_DMA_SBUSEL_SINGLE + * @arg @ref MD_DMA_SBUSEL_WRAP4 + * @arg @ref MD_DMA_SBUSEL_INCR4 + * @arg @ref MD_DMA_SBUSEL_WRAP8 + * @arg @ref MD_DMA_SBUSEL_INCR8 + * @arg @ref MD_DMA_SBUSEL_WRAP16 + * @arg @ref MD_DMA_SBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_sbusel(DMA_TypeDef *dma, uint32_t sbusel) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_SBUSEL_MSK, (sbusel<CSR3, DMA_CSR3_SBUSEL_MSK)>>DMA_CSR3_SBUSEL_POSS); +} +/** + * @brief Set Source Transfer Data Width Selection. + * @param dma DMA Instance + * @param sdwsel can be one of the following values: + * @arg @ref MD_DMA_SDWSEL_ONE_BYTE + * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_SDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_SDWSEL_MSK, (sdwsel<CSR3, DMA_CSR3_SDWSEL_MSK)>>DMA_CSR3_SDWSEL_POSS); +} +/** + * @brief Set Source Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_sinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_SINC_MSK, (dinc<CSR3, DMA_CSR3_SINC_MSK)>>DMA_CSR3_SINC_POS); +} +/** + * @brief Set Peripheral Handshake Software Select + * @param dma DMA Instance + * @param phss can be one of the following values: + * @arg @ref MD_DMA_PHSS_UART1_TX + * @arg @ref MD_DMA_PHSS_UART2_TX + * @arg @ref MD_DMA_PHSS_UART3_TX + * @arg @ref MD_DMA_PHSS_SUART1_TX + * @arg @ref MD_DMA_PHSS_SUART2_TX + * @arg @ref MD_DMA_PHSS_SPI1_TX + * @arg @ref MD_DMA_PHSS_SPI2_TX + * @arg @ref MD_DMA_PHSS_I2C1_TX + * @arg @ref MD_DMA_PHSS_I2C2_TX + * @arg @ref MD_DMA_PHSS_AES_IN + * @arg @ref MD_DMA_PHSS_DAC + * @arg @ref MD_DMA_PHSS_CRC + * @arg @ref MD_DMA_PHSS_UART1_RX + * @arg @ref MD_DMA_PHSS_UART2_RX + * @arg @ref MD_DMA_PHSS_UART3_RX + * @arg @ref MD_DMA_PHSS_SUART1_RX + * @arg @ref MD_DMA_PHSS_SUART2_RX + * @arg @ref MD_DMA_PHSS_SPI1_RTX + * @arg @ref MD_DMA_PHSS_SPI2_RX + * @arg @ref MD_DMA_PHSS_I2C1_RX + * @arg @ref MD_DMA_PHSS_I2C2_RX + * @arg @ref MD_DMA_PHSS_AES_OUT + * @arg @ref MD_DMA_PHSS_ADCSS0 + * @arg @ref MD_DMA_PHSS_ADCSS1 + * @arg @ref MD_DMA_PHSS_ADCSS2 + * @arg @ref MD_DMA_PHSS_ADCSS3 + * @arg @ref MD_DMA_PHSS_BS16T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_AD16C4T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_AD16C4T1_COM + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP32C4T1_UP + * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T1_UP + * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T2_UP + * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T3_UP + * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T1_UP + * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_COM + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T2_UP + * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T2_COM + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T3_UP + * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T3_COM + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T4_UP + * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T4_COM + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_phss(DMA_TypeDef *dma, uint32_t phss) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_PHSS_MSK, (phss<CSR3, DMA_CSR3_PHSS_MSK)>>DMA_CSR3_PHSS_POSS); +} +/** + * @brief Set DMA Channel Priority. + * @param dma DMA Instance + * @param chpri can be one of the following values: + * @arg @ref MD_DMA_CHPRI_LV0 + * @arg @ref MD_DMA_CHPRI_LV1 + * @arg @ref MD_DMA_CHPRI_LV2 + * @arg @ref MD_DMA_CHPRI_LV3 + * @arg @ref MD_DMA_CHPRI_LV4 + * @arg @ref MD_DMA_CHPRI_LV5 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_chpri(DMA_TypeDef *dma, uint32_t chpri) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_CHPRI_MSK, (chpri<CSR3, DMA_CSR3_CHPRI_MSK)>>DMA_CSR3_CHPRI_POSS); +} +/** + * @brief Set DMA Mode Select. + * @param dma DMA Instance + * @param modesel can be one of the following values: + * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM + * @arg @ref MD_DMA_MODESEL_PER_TO_MEM + * @arg @ref MD_DMA_MODESEL_MEM_TO_PER + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_modesel(DMA_TypeDef *dma, uint32_t modesel) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_MODESEL_MSK, (modesel<CSR3, DMA_CSR3_MODESEL_MSK)>>DMA_CSR3_MODESEL_POSS); +} +/** + * @brief Set Direct Mode Enable. + * @param dma DMA Instance + * @param dirmden can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_dirmden(DMA_TypeDef *dma, uint32_t dirmden) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_DIRMDEN_MSK, (dirmden<CSR3, DMA_CSR3_DIRMDEN_MSK)>>DMA_CSR3_DIRMDEN_POS); +} +/** + * @brief Set Peripheral flow controller + * @param dma DMA Instance + * @param pfctrl can be one of the following values: + * @arg @ref MD_DMA_PFCTRL_DMA_CTRL + * @arg @ref MD_DMA_PFCTRL_PER_CTRL + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_PFCTRL_MSK, (pfctrl<CSR3, DMA_CSR3_PFCTRL_MSK)>>DMA_CSR3_PFCTRL_POS); +} +/** + * @brief Set Circular mode + * @param dma DMA Instance + * @param circ can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_circ(DMA_TypeDef *dma, uint32_t circ) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_CIRC_MSK, (circ<CSR3, DMA_CSR3_CIRC_MSK)>>DMA_CSR3_CIRC_POS); +} +/** + * @brief Set DMA Channel Enable. + * @param dma DMA Instance + * @param chen can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr3_chen(DMA_TypeDef *dma, uint32_t chen) +{ + MODIFY_REG(dma->CSR3, DMA_CSR3_CHEN_MSK, (chen<CSR3, DMA_CSR3_CHEN_MSK)>>DMA_CSR3_CHEN_POS); +} + +/** + * @brief Set DMA Transfer Source Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param sar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_sar3_sar(DMA_TypeDef *dma, uint32_t sar) +{ + MODIFY_REG(dma->SAR3, DMA_SAR3_SAR_MSK, (sar<SAR3, DMA_SAR3_SAR_MSK)>>DMA_SAR3_SAR_POSS); +} + +/** + * @brief Set DMA Transfer Destination Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param dar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_dar3_dar(DMA_TypeDef *dma, uint32_t dar) +{ + MODIFY_REG(dma->DAR3, DMA_DAR3_DAR_MSK, (dar<DAR3, DMA_DAR3_DAR_MSK)>>DMA_DAR3_DAR_POSS); +} + +/** + * @brief Get DMA Current Transfer Byte Count + * @param dma DMA Instance + * @retval The retval can be one of the following values: + * @arg Max Value 65535 + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_dma_get_bcr3_cbcr(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->BCR3, DMA_BCR3_CBCR_MSK)>>DMA_BCR3_CBCR_POSS); +} +/** + * @brief Set DMA Transfer Byte Count Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param bcr This field indicates a 16-bit transfer byte count of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_bcr3_bcr(DMA_TypeDef *dma, uint32_t bcr) +{ + MODIFY_REG(dma->BCR3, DMA_BCR3_BCR_MSK, (bcr<BCR3, DMA_BCR3_BCR_MSK)>>DMA_BCR3_BCR_POSS); +} + +/** + * @brief Set Destination Increment Offset Size bit. + * @note This bit has no meaning if bit DINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if DBUSEL are different from 00. + * @param dma DMA Instance + * @param dincos can be one of the following values: + * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL + * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_dincos(DMA_TypeDef *dma, uint32_t dincos) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_DINCOS_MSK, (dincos<CSR4, DMA_CSR4_DINCOS_MSK)>>DMA_CSR4_DINCOS_POS); +} +/** + * @brief Set Destination Transfer Burst Selection. + * @param dma DMA Instance + * @param dbusel can be one of the following values: + * @arg @ref MD_DMA_DBUSEL_SINGLE + * @arg @ref MD_DMA_DBUSEL_WRAP4 + * @arg @ref MD_DMA_DBUSEL_INCR4 + * @arg @ref MD_DMA_DBUSEL_WRAP8 + * @arg @ref MD_DMA_DBUSEL_INCR8 + * @arg @ref MD_DMA_DBUSEL_WRAP16 + * @arg @ref MD_DMA_DBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_dbusel(DMA_TypeDef *dma, uint32_t dbusel) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_DBUSEL_MSK, (dbusel<CSR4, DMA_CSR4_DBUSEL_MSK)>>DMA_CSR4_DBUSEL_POSS); +} +/** + * @brief Set Destination Transfer Data Width Selection. + * @param dma DMA Instance + * @param ddwsel can be one of the following values: + * @arg @ref MD_DMA_DDWSEL_ONE_BYTE + * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_DDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_DDWSEL_MSK, (ddwsel<CSR4, DMA_CSR4_DDWSEL_MSK)>>DMA_CSR4_DDWSEL_POSS); +} +/** + * @brief Set Destination Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_dinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_DINC_MSK, (dinc<CSR4, DMA_CSR4_DINC_MSK)>>DMA_CSR4_DINC_POS); +} +/** + * @brief Set Source Increment Offset Size bit. + * @note This bit has no meaning if bit SINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if SBUSEL are different from 00. + * @param dma DMA Instance + * @param sincos can be one of the following values: + * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL + * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_sincos(DMA_TypeDef *dma, uint32_t sincos) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_SINCOS_MSK, (sincos<CSR4, DMA_CSR4_SINCOS_MSK)>>DMA_CSR4_SINCOS_POS); +} +/** + * @brief Set Source Transfer Burst Selection. + * @param dma DMA Instance + * @param sbusel can be one of the following values: + * @arg @ref MD_DMA_SBUSEL_SINGLE + * @arg @ref MD_DMA_SBUSEL_WRAP4 + * @arg @ref MD_DMA_SBUSEL_INCR4 + * @arg @ref MD_DMA_SBUSEL_WRAP8 + * @arg @ref MD_DMA_SBUSEL_INCR8 + * @arg @ref MD_DMA_SBUSEL_WRAP16 + * @arg @ref MD_DMA_SBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_sbusel(DMA_TypeDef *dma, uint32_t sbusel) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_SBUSEL_MSK, (sbusel<CSR4, DMA_CSR4_SBUSEL_MSK)>>DMA_CSR4_SBUSEL_POSS); +} +/** + * @brief Set Source Transfer Data Width Selection. + * @param dma DMA Instance + * @param sdwsel can be one of the following values: + * @arg @ref MD_DMA_SDWSEL_ONE_BYTE + * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_SDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_SDWSEL_MSK, (sdwsel<CSR4, DMA_CSR4_SDWSEL_MSK)>>DMA_CSR4_SDWSEL_POSS); +} +/** + * @brief Set Source Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_sinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_SINC_MSK, (dinc<CSR4, DMA_CSR4_SINC_MSK)>>DMA_CSR4_SINC_POS); +} +/** + * @brief Set Peripheral Handshake Software Select + * @param dma DMA Instance + * @param phss can be one of the following values: + * @arg @ref MD_DMA_PHSS_UART1_TX + * @arg @ref MD_DMA_PHSS_UART2_TX + * @arg @ref MD_DMA_PHSS_UART3_TX + * @arg @ref MD_DMA_PHSS_SUART1_TX + * @arg @ref MD_DMA_PHSS_SUART2_TX + * @arg @ref MD_DMA_PHSS_SPI1_TX + * @arg @ref MD_DMA_PHSS_SPI2_TX + * @arg @ref MD_DMA_PHSS_I2C1_TX + * @arg @ref MD_DMA_PHSS_I2C2_TX + * @arg @ref MD_DMA_PHSS_AES_IN + * @arg @ref MD_DMA_PHSS_DAC + * @arg @ref MD_DMA_PHSS_CRC + * @arg @ref MD_DMA_PHSS_UART1_RX + * @arg @ref MD_DMA_PHSS_UART2_RX + * @arg @ref MD_DMA_PHSS_UART3_RX + * @arg @ref MD_DMA_PHSS_SUART1_RX + * @arg @ref MD_DMA_PHSS_SUART2_RX + * @arg @ref MD_DMA_PHSS_SPI1_RTX + * @arg @ref MD_DMA_PHSS_SPI2_RX + * @arg @ref MD_DMA_PHSS_I2C1_RX + * @arg @ref MD_DMA_PHSS_I2C2_RX + * @arg @ref MD_DMA_PHSS_AES_OUT + * @arg @ref MD_DMA_PHSS_ADCSS0 + * @arg @ref MD_DMA_PHSS_ADCSS1 + * @arg @ref MD_DMA_PHSS_ADCSS2 + * @arg @ref MD_DMA_PHSS_ADCSS3 + * @arg @ref MD_DMA_PHSS_BS16T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_AD16C4T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_AD16C4T1_COM + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP32C4T1_UP + * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T1_UP + * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T2_UP + * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T3_UP + * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T1_UP + * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_COM + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T2_UP + * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T2_COM + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T3_UP + * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T3_COM + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T4_UP + * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T4_COM + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_phss(DMA_TypeDef *dma, uint32_t phss) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_PHSS_MSK, (phss<CSR4, DMA_CSR4_PHSS_MSK)>>DMA_CSR4_PHSS_POSS); +} +/** + * @brief Set DMA Channel Priority. + * @param dma DMA Instance + * @param chpri can be one of the following values: + * @arg @ref MD_DMA_CHPRI_LV0 + * @arg @ref MD_DMA_CHPRI_LV1 + * @arg @ref MD_DMA_CHPRI_LV2 + * @arg @ref MD_DMA_CHPRI_LV3 + * @arg @ref MD_DMA_CHPRI_LV4 + * @arg @ref MD_DMA_CHPRI_LV5 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_chpri(DMA_TypeDef *dma, uint32_t chpri) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_CHPRI_MSK, (chpri<CSR4, DMA_CSR4_CHPRI_MSK)>>DMA_CSR4_CHPRI_POSS); +} +/** + * @brief Set DMA Mode Select. + * @param dma DMA Instance + * @param modesel can be one of the following values: + * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM + * @arg @ref MD_DMA_MODESEL_PER_TO_MEM + * @arg @ref MD_DMA_MODESEL_MEM_TO_PER + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_modesel(DMA_TypeDef *dma, uint32_t modesel) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_MODESEL_MSK, (modesel<CSR4, DMA_CSR4_MODESEL_MSK)>>DMA_CSR4_MODESEL_POSS); +} +/** + * @brief Set Direct Mode Enable. + * @param dma DMA Instance + * @param dirmden can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_dirmden(DMA_TypeDef *dma, uint32_t dirmden) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_DIRMDEN_MSK, (dirmden<CSR4, DMA_CSR4_DIRMDEN_MSK)>>DMA_CSR4_DIRMDEN_POS); +} +/** + * @brief Set Peripheral flow controller + * @param dma DMA Instance + * @param pfctrl can be one of the following values: + * @arg @ref MD_DMA_PFCTRL_DMA_CTRL + * @arg @ref MD_DMA_PFCTRL_PER_CTRL + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_PFCTRL_MSK, (pfctrl<CSR4, DMA_CSR4_PFCTRL_MSK)>>DMA_CSR4_PFCTRL_POS); +} +/** + * @brief Set Circular mode + * @param dma DMA Instance + * @param circ can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_circ(DMA_TypeDef *dma, uint32_t circ) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_CIRC_MSK, (circ<CSR4, DMA_CSR4_CIRC_MSK)>>DMA_CSR4_CIRC_POS); +} +/** + * @brief Set DMA Channel Enable. + * @param dma DMA Instance + * @param chen can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr4_chen(DMA_TypeDef *dma, uint32_t chen) +{ + MODIFY_REG(dma->CSR4, DMA_CSR4_CHEN_MSK, (chen<CSR4, DMA_CSR4_CHEN_MSK)>>DMA_CSR4_CHEN_POS); +} + +/** + * @brief Set DMA Transfer Source Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param sar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_sar4_sar(DMA_TypeDef *dma, uint32_t sar) +{ + MODIFY_REG(dma->SAR4, DMA_SAR4_SAR_MSK, (sar<SAR4, DMA_SAR4_SAR_MSK)>>DMA_SAR4_SAR_POSS); +} + +/** + * @brief Set DMA Transfer Destination Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param dar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_dar4_dar(DMA_TypeDef *dma, uint32_t dar) +{ + MODIFY_REG(dma->DAR4, DMA_DAR4_DAR_MSK, (dar<DAR4, DMA_DAR4_DAR_MSK)>>DMA_DAR4_DAR_POSS); +} + +/** + * @brief Get DMA Current Transfer Byte Count + * @param dma DMA Instance + * @retval The retval can be one of the following values: + * @arg Max Value 65535 + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_dma_get_bcr4_cbcr(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->BCR4, DMA_BCR4_CBCR_MSK)>>DMA_BCR4_CBCR_POSS); +} +/** + * @brief Set DMA Transfer Byte Count Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param bcr This field indicates a 16-bit transfer byte count of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_bcr4_bcr(DMA_TypeDef *dma, uint32_t bcr) +{ + MODIFY_REG(dma->BCR4, DMA_BCR4_BCR_MSK, (bcr<BCR4, DMA_BCR4_BCR_MSK)>>DMA_BCR4_BCR_POSS); +} + +/** + * @brief Set Destination Increment Offset Size bit. + * @note This bit has no meaning if bit DINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if DBUSEL are different from 00. + * @param dma DMA Instance + * @param dincos can be one of the following values: + * @arg @ref MD_DMA_DINCOS_LINKED_DWSEL + * @arg @ref MD_DMA_DINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_dincos(DMA_TypeDef *dma, uint32_t dincos) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_DINCOS_MSK, (dincos<CSR5, DMA_CSR5_DINCOS_MSK)>>DMA_CSR5_DINCOS_POS); +} +/** + * @brief Set Destination Transfer Burst Selection. + * @param dma DMA Instance + * @param dbusel can be one of the following values: + * @arg @ref MD_DMA_DBUSEL_SINGLE + * @arg @ref MD_DMA_DBUSEL_WRAP4 + * @arg @ref MD_DMA_DBUSEL_INCR4 + * @arg @ref MD_DMA_DBUSEL_WRAP8 + * @arg @ref MD_DMA_DBUSEL_INCR8 + * @arg @ref MD_DMA_DBUSEL_WRAP16 + * @arg @ref MD_DMA_DBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_dbusel(DMA_TypeDef *dma, uint32_t dbusel) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_DBUSEL_MSK, (dbusel<CSR5, DMA_CSR5_DBUSEL_MSK)>>DMA_CSR5_DBUSEL_POSS); +} +/** + * @brief Set Destination Transfer Data Width Selection. + * @param dma DMA Instance + * @param ddwsel can be one of the following values: + * @arg @ref MD_DMA_DDWSEL_ONE_BYTE + * @arg @ref MD_DMA_DDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_DDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_ddwsel(DMA_TypeDef *dma, uint32_t ddwsel) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_DDWSEL_MSK, (ddwsel<CSR5, DMA_CSR5_DDWSEL_MSK)>>DMA_CSR5_DDWSEL_POSS); +} +/** + * @brief Set Destination Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_dinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_DINC_MSK, (dinc<CSR5, DMA_CSR5_DINC_MSK)>>DMA_CSR5_DINC_POS); +} +/** + * @brief Set Source Increment Offset Size bit. + * @note This bit has no meaning if bit SINC = '0'. + * This bit is protected and can be written only if EN = '0'. + * This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct mode is selected or + * if SBUSEL are different from 00. + * @param dma DMA Instance + * @param sincos can be one of the following values: + * @arg @ref MD_DMA_SINCOS_LINKED_SWSEL + * @arg @ref MD_DMA_SINCOS_FIXED_TO_4 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_sincos(DMA_TypeDef *dma, uint32_t sincos) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_SINCOS_MSK, (sincos<CSR5, DMA_CSR5_SINCOS_MSK)>>DMA_CSR5_SINCOS_POS); +} +/** + * @brief Set Source Transfer Burst Selection. + * @param dma DMA Instance + * @param sbusel can be one of the following values: + * @arg @ref MD_DMA_SBUSEL_SINGLE + * @arg @ref MD_DMA_SBUSEL_WRAP4 + * @arg @ref MD_DMA_SBUSEL_INCR4 + * @arg @ref MD_DMA_SBUSEL_WRAP8 + * @arg @ref MD_DMA_SBUSEL_INCR8 + * @arg @ref MD_DMA_SBUSEL_WRAP16 + * @arg @ref MD_DMA_SBUSEL_INCR16 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_sbusel(DMA_TypeDef *dma, uint32_t sbusel) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_SBUSEL_MSK, (sbusel<CSR5, DMA_CSR5_SBUSEL_MSK)>>DMA_CSR5_SBUSEL_POSS); +} +/** + * @brief Set Source Transfer Data Width Selection. + * @param dma DMA Instance + * @param sdwsel can be one of the following values: + * @arg @ref MD_DMA_SDWSEL_ONE_BYTE + * @arg @ref MD_DMA_SDWSEL_ONE_HALF_WORD + * @arg @ref MD_DMA_SDWSEL_ONE_WORD + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_sdwsel(DMA_TypeDef *dma, uint32_t sdwsel) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_SDWSEL_MSK, (sdwsel<CSR5, DMA_CSR5_SDWSEL_MSK)>>DMA_CSR5_SDWSEL_POSS); +} +/** + * @brief Set Source Transfer Increment Mode + * @param dma DMA Instance + * @param dinc can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_sinc(DMA_TypeDef *dma, uint32_t dinc) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_SINC_MSK, (dinc<CSR5, DMA_CSR5_SINC_MSK)>>DMA_CSR5_SINC_POS); +} +/** + * @brief Set Peripheral Handshake Software Select + * @param dma DMA Instance + * @param phss can be one of the following values: + * @arg @ref MD_DMA_PHSS_UART1_TX + * @arg @ref MD_DMA_PHSS_UART2_TX + * @arg @ref MD_DMA_PHSS_UART3_TX + * @arg @ref MD_DMA_PHSS_SUART1_TX + * @arg @ref MD_DMA_PHSS_SUART2_TX + * @arg @ref MD_DMA_PHSS_SPI1_TX + * @arg @ref MD_DMA_PHSS_SPI2_TX + * @arg @ref MD_DMA_PHSS_I2C1_TX + * @arg @ref MD_DMA_PHSS_I2C2_TX + * @arg @ref MD_DMA_PHSS_AES_IN + * @arg @ref MD_DMA_PHSS_DAC + * @arg @ref MD_DMA_PHSS_CRC + * @arg @ref MD_DMA_PHSS_UART1_RX + * @arg @ref MD_DMA_PHSS_UART2_RX + * @arg @ref MD_DMA_PHSS_UART3_RX + * @arg @ref MD_DMA_PHSS_SUART1_RX + * @arg @ref MD_DMA_PHSS_SUART2_RX + * @arg @ref MD_DMA_PHSS_SPI1_RTX + * @arg @ref MD_DMA_PHSS_SPI2_RX + * @arg @ref MD_DMA_PHSS_I2C1_RX + * @arg @ref MD_DMA_PHSS_I2C2_RX + * @arg @ref MD_DMA_PHSS_AES_OUT + * @arg @ref MD_DMA_PHSS_ADCSS0 + * @arg @ref MD_DMA_PHSS_ADCSS1 + * @arg @ref MD_DMA_PHSS_ADCSS2 + * @arg @ref MD_DMA_PHSS_ADCSS3 + * @arg @ref MD_DMA_PHSS_BS16T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_AD16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_AD16C4T1_UP + * @arg @ref MD_DMA_PHSS_AD16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_AD16C4T1_COM + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP32C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP32C4T1_UP + * @arg @ref MD_DMA_PHSS_GP32C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T1_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T1_UP + * @arg @ref MD_DMA_PHSS_GP16C4T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T2_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T2_UP + * @arg @ref MD_DMA_PHSS_GP16C4T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH3 + * @arg @ref MD_DMA_PHSS_GP16C4T3_CH4 + * @arg @ref MD_DMA_PHSS_GP16C4T3_UP + * @arg @ref MD_DMA_PHSS_GP16C4T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T1_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T1_UP + * @arg @ref MD_DMA_PHSS_GP16C2T1_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T1_COM + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T2_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T2_UP + * @arg @ref MD_DMA_PHSS_GP16C2T2_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T2_COM + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T3_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T3_UP + * @arg @ref MD_DMA_PHSS_GP16C2T3_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T3_COM + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH1 + * @arg @ref MD_DMA_PHSS_GP16C2T4_CH2 + * @arg @ref MD_DMA_PHSS_GP16C2T4_UP + * @arg @ref MD_DMA_PHSS_GP16C2T4_TRIG + * @arg @ref MD_DMA_PHSS_GP16C2T4_COM + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_phss(DMA_TypeDef *dma, uint32_t phss) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_PHSS_MSK, (phss<CSR5, DMA_CSR5_PHSS_MSK)>>DMA_CSR5_PHSS_POSS); +} +/** + * @brief Set DMA Channel Priority. + * @param dma DMA Instance + * @param chpri can be one of the following values: + * @arg @ref MD_DMA_CHPRI_LV0 + * @arg @ref MD_DMA_CHPRI_LV1 + * @arg @ref MD_DMA_CHPRI_LV2 + * @arg @ref MD_DMA_CHPRI_LV3 + * @arg @ref MD_DMA_CHPRI_LV4 + * @arg @ref MD_DMA_CHPRI_LV5 + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_chpri(DMA_TypeDef *dma, uint32_t chpri) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_CHPRI_MSK, (chpri<CSR5, DMA_CSR5_CHPRI_MSK)>>DMA_CSR5_CHPRI_POSS); +} +/** + * @brief Set DMA Mode Select. + * @param dma DMA Instance + * @param modesel can be one of the following values: + * @arg @ref MD_DMA_MODESEL_MEM_TO_MEM + * @arg @ref MD_DMA_MODESEL_PER_TO_MEM + * @arg @ref MD_DMA_MODESEL_MEM_TO_PER + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_modesel(DMA_TypeDef *dma, uint32_t modesel) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_MODESEL_MSK, (modesel<CSR5, DMA_CSR5_MODESEL_MSK)>>DMA_CSR5_MODESEL_POSS); +} +/** + * @brief Set Direct Mode Enable. + * @param dma DMA Instance + * @param dirmden can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_dirmden(DMA_TypeDef *dma, uint32_t dirmden) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_DIRMDEN_MSK, (dirmden<CSR5, DMA_CSR5_DIRMDEN_MSK)>>DMA_CSR5_DIRMDEN_POS); +} +/** + * @brief Set Peripheral flow controller + * @param dma DMA Instance + * @param pfctrl can be one of the following values: + * @arg @ref MD_DMA_PFCTRL_DMA_CTRL + * @arg @ref MD_DMA_PFCTRL_PER_CTRL + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_pfctrl(DMA_TypeDef *dma, uint32_t pfctrl) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_PFCTRL_MSK, (pfctrl<CSR5, DMA_CSR5_PFCTRL_MSK)>>DMA_CSR5_PFCTRL_POS); +} +/** + * @brief Set Circular mode + * @param dma DMA Instance + * @param circ can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_circ(DMA_TypeDef *dma, uint32_t circ) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_CIRC_MSK, (circ<CSR5, DMA_CSR5_CIRC_MSK)>>DMA_CSR5_CIRC_POS); +} +/** + * @brief Set DMA Channel Enable. + * @param dma DMA Instance + * @param chen can be one of the following values: + * @arg Disable + * @arg Enable + * @retval None + */ +__STATIC_INLINE void md_dma_set_csr5_chen(DMA_TypeDef *dma, uint32_t chen) +{ + MODIFY_REG(dma->CSR5, DMA_CSR5_CHEN_MSK, (chen<CSR5, DMA_CSR5_CHEN_MSK)>>DMA_CSR5_CHEN_POS); +} + +/** + * @brief Set DMA Transfer Source Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param sar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_sar5_sar(DMA_TypeDef *dma, uint32_t sar) +{ + MODIFY_REG(dma->SAR5, DMA_SAR5_SAR_MSK, (sar<SAR5, DMA_SAR5_SAR_MSK)>>DMA_SAR5_SAR_POSS); +} + +/** + * @brief Set DMA Transfer Destination Address Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param dar This field indicates a 32-bit source address of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_dar5_dar(DMA_TypeDef *dma, uint32_t dar) +{ + MODIFY_REG(dma->DAR5, DMA_DAR5_DAR_MSK, (dar<DAR5, DMA_DAR5_DAR_MSK)>>DMA_DAR5_DAR_POSS); +} + +/** + * @brief Get DMA Current Transfer Byte Count + * @param dma DMA Instance + * @retval The retval can be one of the following values: + * @arg Max Value 65535 + * @arg Min Value 0 + */ +__STATIC_INLINE uint32_t md_dma_get_bcr5_cbcr(DMA_TypeDef *dma) +{ + return (READ_BIT(dma->BCR5, DMA_BCR5_CBCR_MSK)>>DMA_BCR5_CBCR_POSS); +} +/** + * @brief Set DMA Transfer Byte Count Register + * @note These bits are write-protected and can be written only when bit EN = '0' + * @param dma DMA Instance + * @param bcr This field indicates a 16-bit transfer byte count of DMA. + * @retval None + */ +__STATIC_INLINE void md_dma_set_bcr5_bcr(DMA_TypeDef *dma, uint32_t bcr) +{ + MODIFY_REG(dma->BCR5, DMA_BCR5_BCR_MSK, (bcr<BCR5, DMA_BCR5_BCR_MSK)>>DMA_BCR5_BCR_POSS); +} + +/** + * @} MD_DMA_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_DMA_Public_Functions DMA Public Functions + * @{ + */ + +/** @defgroup MD_DMA_Basic_Configuration Basic Configuration + * @{ + */ + +/** + * @} MD_DMA_Basic_Configuration + */ + + +/** + * @} MD_DMA_Public_Functions + */ + +#endif + +/** + * @} DMA + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_exti.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_exti.h new file mode 100644 index 0000000000000000000000000000000000000000..7f00f8320e03f0d68bb9cf6fa15fc064abdd593e --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_exti.h @@ -0,0 +1,5167 @@ +/** + ****************************************************************************** + * @file md_EXTI.h + * @brief ES32F0271 EXTI HEAD File. + * + * @version V1.00.01 + * @date 22/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_EXTI_H__ +#define __MD_EXTI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_exti.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (EXTI) +/** @defgroup EXTI EXTI + * @brief EXTI micro driver + * @{ + */ + + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Public types ---------------------------------------------------------------*/ +/* Public constants -----------------------------------------------------------*/ + +/** @defgroup MD_EXTI_Public_Constants EXTI Public Constants + * @{ + */ + +/** @defgroup MD_EXTI_PC_Source EXTI Line Source + * @{ + */ +#define MD_EXTI_Pin_GPIOA (0x00000000UL) /*!< @brief Select GPIOA for EXTIx */ +#define MD_EXTI_Pin_GPIOB (0x00000001UL) /*!< @brief Select GPIOB for EXTIx */ +#define MD_EXTI_Pin_GPIOC (0x00000002UL) /*!< @brief Select GPIOC for EXTIx */ +#define MD_EXTI_Pin_GPIOD (0x00000003UL) /*!< @brief Select GPIOD for EXTIx */ + + /** + * @} MD_EXTI_PC_Source + */ + +/** +* @} MD_EXTI_Public_Constants +*/ + + + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_EXTI_Public_Macros EXTI Public Macros + * @{ + */ + + + +/** @defgroup MD_EXTI_PF_Basic_Configuration EXTI Configuration Management + * @{ + */ +/** + * @brief Set EXTI interrupt configuration register 1 + * @param exti EXTI Instance + * @param value The value write in EXTI->ICFG1 + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->ICFG1, value); +} + +/** + * @brief Get EXTI interrupt configuration register 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->ICFG1)); +} + +/** + * @brief Set EXTI interrupt configuration register 2 + * @param exti EXTI Instance + * @param value The value write in EXTI->ICFG2 + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->ICFG2, value); +} + +/** + * @brief Get EXTI interrupt configuration register 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->ICFG2)); +} + +/** + * @brief Set EXTI0 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1_gpio0(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO0_MSK, Source); +} + +/** + * @brief Get EXTI0 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio0(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO0_MSK)>>EXTI_ICFG1_GPIO0_POSS); +} + +/** + * @brief Set EXTI1 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1_gpio1(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO1_MSK, Source << EXTI_ICFG1_GPIO1_POSS); +} + +/** + * @brief Get EXTI1 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio1(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO1_MSK)>>EXTI_ICFG1_GPIO1_POSS); +} + +/** + * @brief Set EXTI2 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1_gpio2(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO2_MSK, Source << EXTI_ICFG1_GPIO2_POSS); +} + +/** + * @brief Get EXTI2 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio2(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO2_MSK)>>EXTI_ICFG1_GPIO2_POSS); +} + +/** + * @brief Set EXTI3 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1_gpio3(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO3_MSK, Source << EXTI_ICFG1_GPIO3_POSS); +} + +/** + * @brief Get EXTI3 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio3(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO3_MSK)>>EXTI_ICFG1_GPIO0_POSS); +} + +/** + * @brief Set EXTI4 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1_gpio4(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO4_MSK, Source << EXTI_ICFG1_GPIO4_POSS); +} + +/** + * @brief Get EXTI4 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio4(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO4_MSK)>>EXTI_ICFG1_GPIO4_POSS); +} + +/** + * @brief Set EXTI5 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1_gpio5(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO5_MSK, Source << EXTI_ICFG1_GPIO5_POSS); +} + +/** + * @brief Get EXTI5 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio5(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO5_MSK)>>EXTI_ICFG1_GPIO5_POSS); +} + +/** + * @brief Set EXTI6 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1_gpio6(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO6_MSK, Source << EXTI_ICFG1_GPIO6_POSS); +} + +/** + * @brief Get EXTI6 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio6(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO6_MSK)>>EXTI_ICFG1_GPIO6_POSS); +} + +/** + * @brief Set EXTI7 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg1_gpio7(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG1, EXTI_ICFG1_GPIO7_MSK, Source << EXTI_ICFG1_GPIO7_POSS); +} + +/** + * @brief Get EXTI7 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg1_gpio7(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG1, EXTI_ICFG1_GPIO7_MSK)>>EXTI_ICFG1_GPIO7_POSS); +} + + +/** + * @brief Set EXTI8 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2_gpio8(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO8_MSK, Source << EXTI_ICFG2_GPIO8_POSS); +} + +/** + * @brief Get EXTI8 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio8(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO8_MSK)>>EXTI_ICFG2_GPIO8_POSS); +} + +/** + * @brief Set EXTI9 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2_gpio9(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO9_MSK, Source << EXTI_ICFG2_GPIO9_POSS); +} + +/** + * @brief Get EXTI9 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio9(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO9_MSK)>>EXTI_ICFG2_GPIO9_POSS); +} + +/** + * @brief Set EXTI10 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2_gpio10(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO10_MSK, Source << EXTI_ICFG2_GPIO10_POSS); +} + +/** + * @brief Get EXTI10 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio10(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO10_MSK)>>EXTI_ICFG2_GPIO10_POSS); +} + +/** + * @brief Set EXTI11 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2_gpio11(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO11_MSK, Source << EXTI_ICFG2_GPIO11_POSS); +} + +/** + * @brief Get EXTI11 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio11(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO11_MSK)>>EXTI_ICFG2_GPIO11_POSS); +} + +/** + * @brief Set EXTI12 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2_gpio12(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO12_MSK, Source << EXTI_ICFG2_GPIO12_POSS); +} + +/** + * @brief Get EXTI12 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio12(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO12_MSK)>>EXTI_ICFG2_GPIO12_POSS); +} + +/** + * @brief Set EXTI13 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2_gpio13(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO13_MSK, Source << EXTI_ICFG2_GPIO13_POSS); +} + +/** + * @brief Get EXTI13 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio13(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO13_MSK)>>EXTI_ICFG2_GPIO13_POSS); +} + +/** + * @brief Set EXTI14 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2_gpio14(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO14_MSK, Source << EXTI_ICFG2_GPIO14_POSS); +} + +/** + * @brief Get EXTI14 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio14(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO14_MSK)>>EXTI_ICFG2_GPIO14_POSS); +} + +/** + * @brief Set EXTI15 configuration + * @param exti EXTI Instance + * @param Source This parameter can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + * @retval None + */ +__STATIC_INLINE void md_exti_set_icfg2_gpio15(EXTI_TypeDef *exti, uint32_t Source) +{ + MODIFY_REG(exti->ICFG2, EXTI_ICFG2_GPIO15_MSK, Source << EXTI_ICFG2_GPIO15_POSS); +} + +/** + * @brief Get EXTI15 configuration + * @param exti EXTI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_EXTI_Pin_GPIOA + * @arg @ref MD_EXTI_Pin_GPIOB + * @arg @ref MD_EXTI_Pin_GPIOC + * @arg @ref MD_EXTI_Pin_GPIOD + */ +__STATIC_INLINE uint32_t md_exti_get_icfg2_gpio15(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->ICFG2, EXTI_ICFG2_GPIO15_MSK)>>EXTI_ICFG2_GPIO15_POSS); +} + +/** + * @} MD_EXTI_PF_Basic_Configuration + */ + +/** @defgroup MD_EXTI_PF_RTS EXTI Rising Edge Trigger Selection Register + * @{ + */ + +/** + * @brief Set rising trigger event configuration bit of line + * @param exti EXTI Instance + * @param value The value write in EXTI->RTS + * @retval None + */ +__STATIC_INLINE void md_exti_set_rts(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->RTS, value); +} + +/** + * @brief Get rising trigger event configuration bit of line + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_get_rts(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->RTS)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO0_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO0_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 0 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO0_MSK) == (EXTI_RTS_GPIO0_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO1_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO1_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 1 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO1_MSK) == (EXTI_RTS_GPIO1_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO2_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO2_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 2 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO2_MSK) == (EXTI_RTS_GPIO2_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio3(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO3_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio3(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO3_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 3 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio3(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO3_MSK) == (EXTI_RTS_GPIO3_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio4(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO4_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio4(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO4_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 4 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio4(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO4_MSK) == (EXTI_RTS_GPIO4_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio5(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO5_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio5(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO5_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 5 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio5(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO5_MSK) == (EXTI_RTS_GPIO5_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio6(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO6_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio6(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO6_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 1 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio6(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO6_MSK) == (EXTI_RTS_GPIO6_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio7(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO7_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio7(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO7_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 7 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio7(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO7_MSK) == (EXTI_RTS_GPIO7_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio8(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO8_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio8(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO8_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 8 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio8(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO8_MSK) == (EXTI_RTS_GPIO8_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio9(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO9_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio9(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO9_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 9 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio9(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO9_MSK) == (EXTI_RTS_GPIO9_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio10(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO10_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio10(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO10_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 10 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio10(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO10_MSK) == (EXTI_RTS_GPIO10_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio11(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO11_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio11(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO11_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 11 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio11(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO11_MSK) == (EXTI_RTS_GPIO11_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio12(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO12_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio12(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO12_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 12 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio12(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO12_MSK) == (EXTI_RTS_GPIO12_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio13(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO13_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio13(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO13_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 13 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio13(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO13_MSK) == (EXTI_RTS_GPIO13_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio14(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO14_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio14(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO14_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 14 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio14(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO14_MSK) == (EXTI_RTS_GPIO14_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_gpio15(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_GPIO15_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_gpio15(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_GPIO15_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 15 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_gpio15(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_GPIO15_MSK) == (EXTI_RTS_GPIO15_MSK)); +} + + +/** + * @brief Enable rising trigger event configuration bit of line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_cmp1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_CMP1_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_cmp1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_CMP1_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 16 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_cmp1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_CMP1_MSK) == (EXTI_RTS_CMP1_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_cmp2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_CMP2_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_cmp2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_CMP2_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 17 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_cmp2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_CMP2_MSK) == (EXTI_RTS_CMP2_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_pvd0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_PVD0_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_pvd0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_PVD0_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 20 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_pvd0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_PVD0_MSK) == (EXTI_RTS_PVD0_MSK)); +} + +/** + * @brief Enable rising trigger event configuration bit of line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_rts_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->RTS, EXTI_RTS_WAKEUP_MSK); +} + +/** + * @brief Disable rising trigger event configuration bit of line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_rts_wakeup(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->RTS, EXTI_RTS_WAKEUP_MSK); +} + +/** + * @brief Check if rising trigger event configuration bit of line 21 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_rts_wakeup(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->RTS, EXTI_RTS_WAKEUP_MSK) == (EXTI_RTS_WAKEUP_MSK)); +} + +/** + * @} MD_EXTI_PF_RTS + */ + +/** @defgroup MD_EXTI_PF_FTS EXTI Falling Edge Trigger Selection Register + * @{ + */ + +/** + * @brief Set falling trigger event configuration bit of line + * @param exti EXTI Instance + * @param value The value write in EXTI->FTS + * @retval None + */ +__STATIC_INLINE void md_exti_set_fts(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->FTS, value); +} + +/** + * @brief Get falling trigger event configuration bit of line + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_get_fts(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->FTS)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO0_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO0_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 0 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO0_MSK) == (EXTI_FTS_GPIO0_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO1_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO1_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 1 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO1_MSK) == (EXTI_FTS_GPIO1_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO2_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO2_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 2 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO2_MSK) == (EXTI_FTS_GPIO2_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio3(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO3_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio3(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO3_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 3 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio3(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO3_MSK) == (EXTI_FTS_GPIO3_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio4(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO4_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio4(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO4_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 4 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio4(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO4_MSK) == (EXTI_FTS_GPIO4_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio5(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO5_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio5(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO5_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 5 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio5(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO5_MSK) == (EXTI_FTS_GPIO5_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio6(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO6_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio6(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO6_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 6 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio6(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO6_MSK) == (EXTI_FTS_GPIO6_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio7(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO7_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio7(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO7_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 7 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio7(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO7_MSK) == (EXTI_FTS_GPIO7_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio8(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO8_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio8(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO8_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 8 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio8(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO8_MSK) == (EXTI_FTS_GPIO8_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio9(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO9_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio9(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO9_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 9 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio9(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO9_MSK) == (EXTI_FTS_GPIO9_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio10(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO10_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio10(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO10_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 10 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio10(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO10_MSK) == (EXTI_FTS_GPIO10_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio11(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO11_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio11(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO11_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 11 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio11(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO11_MSK) == (EXTI_FTS_GPIO11_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio12(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO12_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio12(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO12_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 12 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio12(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO12_MSK) == (EXTI_FTS_GPIO12_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio13(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO13_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio13(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO13_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 13 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio13(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO13_MSK) == (EXTI_FTS_GPIO13_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio14(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO14_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio14(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO14_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 14 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio14(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO14_MSK) == (EXTI_FTS_GPIO14_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_gpio15(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_GPIO15_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_gpio15(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO15_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 15 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_gpio15(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_GPIO15_MSK) == (EXTI_FTS_GPIO15_MSK)); +} + + + +/** + * @brief Enable falling trigger event configuration bit of line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_cmp1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_CMP1_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_cmp1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_CMP1_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 16 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_cmp1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_CMP1_MSK) == (EXTI_FTS_CMP1_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_cmp2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_CMP2_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 18 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_cmp2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_CMP2_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 18 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_cmp2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_CMP2_MSK) == (EXTI_RTS_CMP2_MSK)); +} + + +/** + * @brief Enable falling trigger event configuration bit of line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_pvd0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_PVD0_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_pvd0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_PVD0_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 17 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_pvd0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_PVD0_MSK) == (EXTI_FTS_PVD0_MSK)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_fts_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->FTS, EXTI_FTS_WAKEUP_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_fts_wakeup(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_WAKEUP_MSK); +} + +/** + * @brief Check if falling trigger event configuration bit of line 21 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_fts_wakeup(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->FTS, EXTI_FTS_WAKEUP_MSK) == (EXTI_FTS_WAKEUP_MSK)); +} + + + +/** + * @} MD_EXTI_PF_FTS + */ + +/** @defgroup MD_EXTI_PF_SWI EXTI Software Interrupt Event register + * @{ + */ + +/** + * @brief Set software interrupt on line + * @param exti EXTI Instance + * @param value The value write in EXTI->SWI + * @retval None + */ +__STATIC_INLINE void md_exti_set_swi(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->SWI, value); +} + +/** + * @brief Get software interrupt on line + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_get_swi(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->SWI)); +} + +/** + * @brief Enable falling trigger event configuration bit of line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO0_MSK); +} + +/** + * @brief Disable software interrupt on line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO0_MSK); +} + +/** + * @brief Check if software interrupt on line 0 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO0_MSK) == (EXTI_SWI_GPIO0_MSK)); +} + +/** + * @brief Enable software interrupt on line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO1_MSK); +} + +/** + * @brief Disable software interrupt on line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO1_MSK); +} + +/** + * @brief Check if software interrupt on line 1 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO1_MSK) == (EXTI_SWI_GPIO1_MSK)); +} + +/** + * @brief Enable software interrupt on line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO2_MSK); +} + +/** + * @brief Disable software interrupt on line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO2_MSK); +} + +/** + * @brief Check if software interrupt on line 2 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO2_MSK) == (EXTI_SWI_GPIO2_MSK)); +} + +/** + * @brief Enable software interrupt on line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio3(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO3_MSK); +} + +/** + * @brief Disable software interrupt on line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio3(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO3_MSK); +} + +/** + * @brief Check if software interrupt on line 3 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio3(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO3_MSK) == (EXTI_SWI_GPIO3_MSK)); +} + +/** + * @brief Enable software interrupt on line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio4(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO4_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio4(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO4_MSK); +} + +/** + * @brief Check if software interrupt on line 4 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio4(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO4_MSK) == (EXTI_SWI_GPIO4_MSK)); +} + +/** + * @brief Enable software interrupt on line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio5(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO5_MSK); +} + +/** + * @brief Disable software interrupt on line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio5(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO5_MSK); +} + +/** + * @brief Check if software interrupt on line 5 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio5(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO5_MSK) == (EXTI_SWI_GPIO5_MSK)); +} + +/** + * @brief Enable software interrupt on line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio6(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO6_MSK); +} + +/** + * @brief Disable software interrupt on line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio6(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO6_MSK); +} + +/** + * @brief Check if software interrupt on line 6 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio6(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO6_MSK) == (EXTI_SWI_GPIO6_MSK)); +} + +/** + * @brief Enable software interrupt on line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio7(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO7_MSK); +} + +/** + * @brief Disable software interrupt on line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio7(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO7_MSK); +} + +/** + * @brief Check if software interrupt on line 7 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio7(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO7_MSK) == (EXTI_SWI_GPIO7_MSK)); +} + +/** + * @brief Enable software interrupt on line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio8(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO8_MSK); +} + +/** + * @brief Disable software interrupt on line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio8(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO8_MSK); +} + +/** + * @brief Check if software interrupt on line 8 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio8(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO8_MSK) == (EXTI_SWI_GPIO8_MSK)); +} + +/** + * @brief Enable software interrupt on line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio9(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO9_MSK); +} + +/** + * @brief Disable software interrupt on line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio9(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO9_MSK); +} + +/** + * @brief Check if software interrupt on line 9 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio9(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO9_MSK) == (EXTI_SWI_GPIO9_MSK)); +} + +/** + * @brief Enable software interrupt on line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio10(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO10_MSK); +} + +/** + * @brief Disable software interrupt on line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio10(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO10_MSK); +} + +/** + * @brief Check if software interrupt on line 10 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio10(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO10_MSK) == (EXTI_SWI_GPIO10_MSK)); +} + +/** + * @brief Enable software interrupt on line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio11(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO11_MSK); +} + +/** + * @brief Disable falling trigger event configuration bit of line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio11(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->FTS, EXTI_FTS_GPIO11_MSK); +} + +/** + * @brief Check if software interrupt on line 11 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio11(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO11_MSK) == (EXTI_SWI_GPIO11_MSK)); +} + +/** + * @brief Enable software interrupt on line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio12(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO12_MSK); +} + +/** + * @brief Disable software interrupt on line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio12(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO12_MSK); +} + +/** + * @brief Check if software interrupt on line 12 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio12(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO12_MSK) == (EXTI_SWI_GPIO12_MSK)); +} + +/** + * @brief Enable software interrupt on line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio13(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO13_MSK); +} + +/** + * @brief Disable software interrupt on line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio13(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO13_MSK); +} + +/** + * @brief Check if software interrupt on line 13 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio13(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO13_MSK) == (EXTI_SWI_GPIO13_MSK)); +} + +/** + * @brief Enable software interrupt on line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio14(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO14_MSK); +} + +/** + * @brief Disable software interrupt on line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio14(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO14_MSK); +} + +/** + * @brief Check if software interrupt on line 14 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio14(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO14_MSK) == (EXTI_SWI_GPIO14_MSK)); +} + +/** + * @brief Enable software interrupt on line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_gpio15(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_GPIO15_MSK); +} + +/** + * @brief Disable software interrupt on line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_gpio15(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_GPIO15_MSK); +} + +/** + * @brief Check if software interrupt on line is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_gpio15(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_GPIO15_MSK) == (EXTI_SWI_GPIO15_MSK)); +} + +/** + * @brief Enable software interrupt on line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_cmp1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_CMP1_MSK); +} + +/** + * @brief Disable software interrupt on line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_cmp1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_CMP1_MSK); +} + +/** + * @brief Check if software interrupt on line 16 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_cmp1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_CMP1_MSK) == (EXTI_SWI_CMP1_MSK)); +} + +/** + * @brief Enable software interrupt on line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_cmp2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_CMP2_MSK); +} + +/** + * @brief Disable software interrupt on line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_cmp2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_CMP2_MSK); +} + +/** + * @brief Check if software interrupt on line 17 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_cmp2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_CMP2_MSK) == (EXTI_SWI_CMP2_MSK)); +} + + +/** + * @brief Enable software interrupt on line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_pvd0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_PVD0_MSK); +} + +/** + * @brief Disable software interrupt on line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_pvd0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_PVD0_MSK); +} + +/** + * @brief Check if software interrupt on line 20 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_pvd0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_PVD0_MSK) == (EXTI_SWI_PVD0_MSK)); +} + +/** + * @brief Enable software interrupt on line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_swi_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->SWI, EXTI_SWI_WAKEUP_MSK); +} + +/** + * @brief Disable software interrupt on line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_swi_wakeup(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->SWI, EXTI_SWI_WAKEUP_MSK); +} + +/** + * @brief Check if software interrupt on line 21 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_swi_wakeup(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->SWI, EXTI_SWI_WAKEUP_MSK) == (EXTI_SWI_WAKEUP_MSK)); +} + +/** + * @} MD_EXTI_PF_SWI + */ + + +/** @defgroup MD_EXTI_PF_ADTE EXTI ADC Trigger Enable Register + * @{ + */ +/** + * @brief Set ADC trigger enable on line + * @param exti EXTI Instance + * @param value The value write in EXTI->ADTE + * @retval None + */ +__STATIC_INLINE void md_exti_set_adte(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->ADTE, value); +} + +/** + * @brief Get ADC trigger enable on line + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_get_adte(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->ADTE)); +} + +/** + * @brief Enable ADC trigger on line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO0_MSK); +} + +/** + * @brief Disable ADC trigger on line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO0_MSK); +} + +/** + * @brief Check if ADC trigger on line 0 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO0_MSK) == (EXTI_ADTE_GPIO0_MSK)); +} + +/** + * @brief Enable ADC trigger on line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO1_MSK); +} + +/** + * @brief Disable ADC trigger on line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO1_MSK); +} + +/** + * @brief Check if ADC trigger on line 1 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO1_MSK) == (EXTI_ADTE_GPIO1_MSK)); +} + +/** + * @brief Enable ADC trigger on line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO2_MSK); +} + +/** + * @brief Disable ADC trigger on line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO2_MSK); +} + +/** + * @brief Check if ADC trigger on line 2 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO2_MSK) == (EXTI_ADTE_GPIO2_MSK)); +} + +/** + * @brief Enable ADC trigger on line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio3(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO3_MSK); +} + +/** + * @brief Disable ADC trigger on line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio3(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO3_MSK); +} + +/** + * @brief Check if ADC trigger on line 3 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio3(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO3_MSK) == (EXTI_ADTE_GPIO3_MSK)); +} + +/** + * @brief Enable ADC trigger on line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio4(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO4_MSK); +} + +/** + * @brief Disable ADC trigger on line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio4(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO4_MSK); +} + +/** + * @brief Check if ADC trigger on line 4 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio4(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO4_MSK) == (EXTI_ADTE_GPIO4_MSK)); +} + +/** + * @brief Enable ADC trigger on line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio5(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO5_MSK); +} + +/** + * @brief Disable ADC trigger on line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio5(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO5_MSK); +} + +/** + * @brief Check if ADC trigger on line 5 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio5(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO5_MSK) == (EXTI_ADTE_GPIO5_MSK)); +} + +/** + * @brief Enable ADC trigger on line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio6(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO6_MSK); +} + +/** + * @brief Disable ADC trigger on line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio6(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO6_MSK); +} + +/** + * @brief Check if ADC trigger on line 6 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio6(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO6_MSK) == (EXTI_ADTE_GPIO6_MSK)); +} + +/** + * @brief Enable ADC trigger on line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio7(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO7_MSK); +} + +/** + * @brief Disable ADC trigger on line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio7(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO7_MSK); +} + +/** + * @brief Check if ADC trigger on line 7 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio7(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO7_MSK) == (EXTI_ADTE_GPIO7_MSK)); +} + +/** + * @brief Enable ADC trigger on line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio8(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO8_MSK); +} + +/** + * @brief Disable ADC trigger on line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio8(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO8_MSK); +} + +/** + * @brief Check if ADC trigger on line 8 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio8(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO8_MSK) == (EXTI_ADTE_GPIO8_MSK)); +} + +/** + * @brief Enable ADC trigger on line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio9(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO9_MSK); +} + +/** + * @brief Disable ADC trigger on line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio9(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO9_MSK); +} + +/** + * @brief Check if ADC trigger on line 9 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio9(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO9_MSK) == (EXTI_ADTE_GPIO9_MSK)); +} + +/** + * @brief Enable ADC trigger on line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio10(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO10_MSK); +} + +/** + * @brief Disable ADC trigger on line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio10(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO10_MSK); +} + +/** + * @brief Check if ADC trigger on line 10 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio10(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO10_MSK) == (EXTI_ADTE_GPIO10_MSK)); +} + +/** + * @brief Enable ADC trigger on line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio11(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO11_MSK); +} + +/** + * @brief Disable ADC trigger on line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio11(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO11_MSK); +} + +/** + * @brief Check if ADC trigger on line 11 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio11(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO11_MSK) == (EXTI_ADTE_GPIO11_MSK)); +} + +/** + * @brief Enable ADC trigger on line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio12(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO12_MSK); +} + +/** + * @brief Disable ADC trigger on line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio12(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO12_MSK); +} + +/** + * @brief Check if ADC trigger on line 12 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio12(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO12_MSK) == (EXTI_ADTE_GPIO12_MSK)); +} + +/** + * @brief Enable ADC trigger on line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio13(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO13_MSK); +} + +/** + * @brief Disable ADC trigger on line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio13(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO13_MSK); +} + +/** + * @brief Check if ADC trigger on line 13 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio13(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO13_MSK) == (EXTI_ADTE_GPIO13_MSK)); +} + +/** + * @brief Enable ADC trigger on line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio14(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO14_MSK); +} + +/** + * @brief Disable ADC trigger on line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio14(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO14_MSK); +} + +/** + * @brief Check if ADC trigger on line 14 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio14(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO14_MSK) == (EXTI_ADTE_GPIO14_MSK)); +} + +/** + * @brief Enable ADC trigger on line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_gpio15(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_GPIO15_MSK); +} + +/** + * @brief Disable ADC trigger on line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_gpio15(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_GPIO15_MSK); +} + +/** + * @brief Check if ADC trigger on line is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_gpio15(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_GPIO15_MSK) == (EXTI_ADTE_GPIO15_MSK)); +} + +/** + * @brief Enable ADC trigger on line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_cmp1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_CMP1_MSK); +} + +/** + * @brief Disable ADC trigger on line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_cmp1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_CMP1_MSK); +} + +/** + * @brief Check if ADC trigger on line 16 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_cmp1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_CMP1_MSK) == (EXTI_ADTE_CMP1_MSK)); +} + +/** + * @brief Enable ADC trigger on line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_cmp2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_CMP2_MSK); +} + +/** + * @brief Disable ADC trigger on line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_cmp2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_CMP2_MSK); +} + +/** + * @brief Check if ADC trigger on line 17 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_cmp2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_CMP2_MSK) == (EXTI_ADTE_CMP2_MSK)); +} + +/** + * @brief Enable ADC trigger on line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_pvd0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_PVD0_MSK); +} + +/** + * @brief Disable ADC trigger on line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_pvd0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_PVD0_MSK); +} + +/** + * @brief Check if ADC trigger on line 20 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_pvd0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_PVD0_MSK) == (EXTI_ADTE_PVD0_MSK)); +} + +/** + * @brief Enable ADC trigger on line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_adte_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ADTE, EXTI_ADTE_WAKEUP_MSK); +} + +/** + * @brief Disable ADC trigger on line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_adte_wakeup(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->ADTE, EXTI_ADTE_WAKEUP_MSK); +} + +/** + * @brief Check if ADC trigger on line 21 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_adte_wakeup(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->ADTE, EXTI_ADTE_WAKEUP_MSK) == (EXTI_ADTE_WAKEUP_MSK)); +} + + +/** + * @} MD_EXTI_PF_ADTE + */ + +/** @defgroup MD_EXTI_PF_INTERRUNPT_MANAGEMENT EXTI Interrupt Management + * @{ + */ + +/** @defgroup MD_EXTI_PF_IER EXTI Interrupt Enable Register + * @{ + */ + + +/** + * @brief Set interrupt enable on line + * @param exti EXTI Instance + * @param value The value write in EXTI->IER + * @retval None + */ +__STATIC_INLINE void md_spi_set_exti_ier(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->IER, value); +} + +/** + * @brief Enable interrupt on line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO0_MSK); +} + +/** + * @brief Enable interrupt on line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO1_MSK); +} + +/** + * @brief Enable interrupt on line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO2_MSK); +} + +/** + * @brief Enable interrupt on line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio3(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO3_MSK); +} + +/** + * @brief Enable interrupt on line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio4(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO4_MSK); +} + +/** + * @brief Enable interrupt on line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio5(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO5_MSK); +} + +/** + * @brief Enable interrupt on line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio6(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO6_MSK); +} + +/** + * @brief Enable interrupt on line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio7(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO7_MSK); +} + +/** + * @brief Enable interrupt on line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio8(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO8_MSK); +} + +/** + * @brief Enable interrupt on line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio9(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO9_MSK); +} + +/** + * @brief Enable interrupt on line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio10(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO10_MSK); +} + +/** + * @brief Enable interrupt on line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio11(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO11_MSK); +} + +/** + * @brief Enable interrupt on line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio12(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO12_MSK); +} + +/** + * @brief Enable interrupt on line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio13(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO13_MSK); +} + +/** + * @brief Enable interrupt on line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio14(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO14_MSK); +} + +/** + * @brief Enable interrupt on line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_gpio15(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_GPIO15_MSK); +} + + +/** + * @brief Enable interrupt on line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_cmp1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_CMP1_MSK); +} + +/** + * @brief Enable interrupt on line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_cmp2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_CMP2_MSK); +} + +/** + * @brief Enable interrupt on line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_pvd0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_PVD0_MSK); +} + +/** + * @brief Enable interrupt on line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_ier_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IER, EXTI_IER_WAKEUP_MSK); +} + +/** + * @} MD_EXTI_PF_IER + */ + +/** @defgroup MD_EXTI_PF_IDR EXTI Interrupt Disable Register + * @{ + */ + +/** + * @brief Disable interrupt on line + * @param exti EXTI Instance + * @param value The value write in EXTI->IDR + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->IDR, value); +} + + +/** + * @brief Disable interrupt on line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO0_MSK); +} + +/** + * @brief Disable interrupt on line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO1_MSK); +} + +/** + * @brief Disable interrupt on line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO2_MSK); +} + +/** + * @brief Disable interrupt on line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio3(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO3_MSK); +} + +/** + * @brief Disable interrupt on line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio4(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO4_MSK); +} + +/** + * @brief Disable interrupt on line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio5(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO5_MSK); +} + +/** + * @brief Disable interrupt on line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio6(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO6_MSK); +} + +/** + * @brief Disable interrupt on line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio7(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO7_MSK); +} + +/** + * @brief Disable interrupt on line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio8(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO8_MSK); +} + +/** + * @brief Disable interrupt on line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio9(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO9_MSK); +} + +/** + * @brief Disable interrupt on line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio10(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO10_MSK); +} + +/** + * @brief Disable interrupt on line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio11(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO11_MSK); +} + +/** + * @brief Disable interrupt on line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio12(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO12_MSK); +} + +/** + * @brief Disable interrupt on line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio13(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO13_MSK); +} + +/** + * @brief Disable interrupt on line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio14(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->IDR, EXTI_IDR_GPIO14_MSK); +} + +/** + * @brief Disable interrupt on line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_gpio15(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_GPIO15_MSK); +} + +/** + * @brief Disable interrupt on line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_cmp1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->IDR, EXTI_IDR_CMP1_MSK); +} + +/** + * @brief Disable interrupt on line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_cmp2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_CMP2_MSK); +} + +/** + * @brief Disable interrupt on line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_pvd0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_PVD0_MSK); +} + +/** + * @brief Disable interrupt on line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_idr_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->IDR, EXTI_IDR_WAKEUP_MSK); +} + + +/** + * @} MD_EXTI_PF_IDR + */ + +/** @defgroup MD_EXTI_PF_ICR EXTI Interrupt Clear Register + * @{ + */ + +/** + * @brief Interrupt Clear on line + * @param exti EXTI Instance + * @param value The value write in EXTI->ICR + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->ICR, value); +} + +/** + * @brief Interrupt Clear on line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO0_MSK); +} + +/** + * @brief Interrupt Clear on line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO1_MSK); +} + +/** + * @brief Interrupt Clear on line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO2_MSK); +} + +/** + * @brief Interrupt Clear on line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio3(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO3_MSK); +} + +/** + * @brief Interrupt Clear on line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio4(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO4_MSK); +} + +/** + * @brief Interrupt Clear on line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio5(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO5_MSK); +} + +/** + * @brief Interrupt Clear on line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio6(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO6_MSK); +} + +/** + * @brief Interrupt Clear on line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio7(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO7_MSK); +} + +/** + * @brief Interrupt Clear on line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio8(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO8_MSK); +} + +/** + * @brief Interrupt Clear on line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio9(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO9_MSK); +} + +/** + * @brief Interrupt Clear on line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio10(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO10_MSK); +} + +/** + * @brief Interrupt Clear on line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio11(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO11_MSK); +} + +/** + * @brief Interrupt Clear on line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio12(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO12_MSK); +} + +/** + * @brief Interrupt Clear on line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio13(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO13_MSK); +} + +/** + * @brief Interrupt Clear on line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio14(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO14_MSK); +} + +/** + * @brief Interrupt Clear on line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_gpio15(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_GPIO15_MSK); +} + + +/** + * @brief Interrupt Clear on line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_cmp1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_CMP1_MSK); +} + +/** + * @brief Interrupt Clear on line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_cmp2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_CMP2_MSK); +} + + +/** + * @brief Interrupt Clear on line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_pvd0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_PVD0_MSK); +} + +/** + * @brief Interrupt Clear on line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_clear_icr_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->ICR, EXTI_ICR_WAKEUP_MSK); +} + +/** + * @} MD_EXTI_PF_ICR + */ + +/** @defgroup MD_EXTI_PF_IVS EXTI Interrupt Valid Status Register + * @{ + */ + +/** + * @brief Interrupt Valid Status on line + * @param exti EXTI Instance + * @param value The value write in EXTI->IVS + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs(EXTI_TypeDef *exti, uint32_t value) +{ + return (READ_REG(exti->IVS)); +} + +/** + * @brief Interrupt Valid Status on line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO0_MSK) == EXTI_IVS_GPIO0_POS); +} + +/** + * @brief Interrupt Valid Status on line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO1_MSK) == EXTI_IVS_GPIO1_POS); +} + +/** + * @brief Interrupt Valid Status on line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO2_MSK) == EXTI_IVS_GPIO2_POS); +} + +/** + * @brief Interrupt Valid Status on line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio3(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO3_MSK) == EXTI_IVS_GPIO3_POS); +} + +/** + * @brief Interrupt Valid Status on line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio4(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO4_MSK) == EXTI_IVS_GPIO4_POS); +} + +/** + * @brief Interrupt Valid Status on line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio5(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO5_MSK)>>EXTI_IVS_GPIO5_POS); +} + +/** + * @brief Interrupt Valid Status on line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio6(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO6_MSK) == EXTI_IVS_GPIO6_POS); +} + +/** + * @brief Interrupt Valid Status on line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio7(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO7_MSK) == EXTI_IVS_GPIO7_POS); +} + +/** + * @brief Interrupt Valid Status on line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio8(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO8_MSK) == EXTI_IVS_GPIO8_POS); +} + +/** + * @brief Interrupt Valid Status on line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio9(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO9_MSK) == EXTI_IVS_GPIO9_POS); +} + +/** + * @brief Interrupt Valid Status on line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio10(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO10_MSK) == EXTI_IVS_GPIO10_POS); +} + +/** + * @brief Interrupt Valid Status on line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio11(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO11_MSK) == EXTI_IVS_GPIO11_POS); +} + +/** + * @brief Interrupt Valid Status on line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio12(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO12_MSK) == EXTI_IVS_GPIO12_POS); +} + +/** + * @brief Interrupt Valid Status on line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio13(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO13_MSK) == EXTI_IVS_GPIO13_POS); +} + +/** + * @brief Interrupt Valid Status on line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio14(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO14_MSK) == EXTI_IVS_GPIO14_POS); +} + +/** + * @brief Interrupt Valid Status on line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_gpio15(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_GPIO15_MSK) == EXTI_IVS_GPIO15_POS); +} + +/** + * @brief Interrupt Valid Status on line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_cmp1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_CMP1_MSK) == EXTI_IVS_CMP1_POS); +} + +/** + * @brief Interrupt Valid Status on line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_cmp2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_CMP2_MSK) == EXTI_IVS_CMP2_POS); +} + + +/** + * @brief Interrupt Valid Status on line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_pvd0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_PVD0_MSK) == EXTI_IVS_PVD0_POS); +} + +/** + * @brief Interrupt Valid Status on line 21 + * @param exti EXTI Instance + * @retval None + */ + +__STATIC_INLINE uint32_t md_exti_is_enable_ivs_wakeup(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->IVS, EXTI_IVS_WAKEUP_MSK) == EXTI_IVS_WAKEUP_POS); +} + + +/** + * @} MD_EXTI_PF_IVS + */ + +/** @defgroup MD_EXTI_PF_IFM EXTI Interrupt Flag Masked Status Register + * @{ + */ + +/** + * @brief Check if Interrupt Flag Masked Status on line is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->IFM)); +} + + +/** + * @brief Check if Interrupt Flag Masked Status on line 0 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio0(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO0_MSK) == EXTI_IFM_GPIO0_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 1 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio1(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO1_MSK) == EXTI_IFM_GPIO1_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 2 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio2(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO2_MSK) == EXTI_IFM_GPIO2_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 3 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio3(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO3_MSK) == EXTI_IFM_GPIO3_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 4 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio4(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO4_MSK) == EXTI_IFM_GPIO4_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 5 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio5(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO5_MSK) == EXTI_IFM_GPIO5_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 6 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio6(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO6_MSK) == EXTI_IFM_GPIO6_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 7 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio7(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO7_MSK) == EXTI_IFM_GPIO7_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 8 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio8(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO8_MSK) == EXTI_IFM_GPIO8_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 9 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio9(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO9_MSK) == EXTI_IFM_GPIO9_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 10 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio10(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO10_MSK) == EXTI_IFM_GPIO10_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 11 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio11(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO11_MSK) == EXTI_IFM_GPIO11_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 12 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio12(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO12_MSK) == EXTI_IFM_GPIO12_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 13 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio13(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO13_MSK) == EXTI_IFM_GPIO13_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 14 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio14(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO14_MSK) == EXTI_IFM_GPIO14_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 15 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_gpio15(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_GPIO15_MSK) == EXTI_IFM_GPIO15_POS); +} + + +/** + * @brief Check if Interrupt Flag Masked Status on line 16 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_cmp1(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_CMP1_MSK) == EXTI_IFM_CMP1_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 17 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_cmp2(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_CMP2_MSK) == EXTI_IFM_CMP2_POS); +} + + +/** + * @brief Check if Interrupt Flag Masked Status on line 20 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_pvd0(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_PVD0_MSK) == EXTI_IFM_PVD0_POS); +} + +/** + * @brief Check if Interrupt Flag Masked Status on line 21 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_ifm_WAKEUP(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->IFM, EXTI_IFM_WAKEUP_MSK) == EXTI_IFM_WAKEUP_POS); +} + +/** + * @} MD_EXTI_PF_IFM + */ + +/** @defgroup MD_EXTI_PF_RIF EXTI Raw Interrupt Flag Status Register + * @{ + */ + + +/** + * @brief Check if Raw interrupt flag Status on line is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->RIF)); +} + + +/** + * @brief Check if Raw interrupt flag Status on line 0 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio0(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO0_MSK) == EXTI_RIF_GPIO0_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 1 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio1(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO1_MSK) == EXTI_RIF_GPIO1_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 2 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio2(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO2_MSK) == EXTI_RIF_GPIO2_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 3 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio3(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO3_MSK) == EXTI_RIF_GPIO3_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 4 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio4(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO4_MSK) == EXTI_RIF_GPIO4_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 5 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio5(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO5_MSK) == EXTI_RIF_GPIO5_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 6 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio6(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO6_MSK) == EXTI_RIF_GPIO6_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 7 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio7(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO7_MSK) == EXTI_RIF_GPIO7_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 8 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio8(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO8_MSK) == EXTI_RIF_GPIO8_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 9 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio9(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO9_MSK) == EXTI_RIF_GPIO9_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 10 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio10(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO10_MSK) == EXTI_RIF_GPIO10_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 11 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio11(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO11_MSK) == EXTI_RIF_GPIO11_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 12 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio12(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO12_MSK) == EXTI_RIF_GPIO12_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 13 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio13(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO13_MSK) == EXTI_RIF_GPIO13_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 14 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio14(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO14_MSK) == EXTI_RIF_GPIO14_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 15 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_gpio15(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_GPIO15_MSK) == EXTI_RIF_GPIO15_POS); +} + + +/** + * @brief Check if Raw interrupt flag Status on line 16 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_cmp1(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_CMP1_MSK) == EXTI_RIF_CMP1_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 17 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_cmp2(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_CMP2_MSK) == EXTI_RIF_CMP2_POS); +} + + +/** + * @brief Check if Raw interrupt flag Status on line 20 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_pvd0(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_PVD0_MSK) == EXTI_RIF_PVD0_POS); +} + +/** + * @brief Check if Raw interrupt flag Status on line 21 is actived + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_exti_is_active_flag_rif_WAKEUP(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_BIT(exti->RIF, EXTI_RIF_WAKEUP_MSK) == EXTI_RIF_WAKEUP_POS); +} + + +/** + * @} MD_EXTI_PF_RIF + */ + + + + +/** + * @} MD_EXTI_PF_INTERRUNPT_MANAGEMENT + */ + + + + + + +/** @defgroup MD_EXTI_PF_DEBOUNCE_SETTING EXTI Debounce Management + * @{ + */ +/** + * @brief Set debounce enable bit of line + * @param exti EXTI Instance + * @param value The value write in EXTI->DB + * @retval None + */ +__STATIC_INLINE void md_spi_set_exti_db(EXTI_TypeDef *exti, uint32_t value) +{ + WRITE_REG(exti->DB, value); +} + +/** + * @brief Get debounce enable bit of line + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_exti_db(EXTI_TypeDef *exti) +{ + return (uint32_t)(READ_REG(exti->DB)); +} + +/** + * @brief Enable debounce enable bit of line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO0_MSK); +} + +/** + * @brief Disable debounce enable bit of line 0 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO0_MSK); +} + +/** + * @brief Check if debounce enable bit of line 0 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO0_MSK) == (EXTI_DB_GPIO0_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO1_MSK); +} + +/** + * @brief Disable debounce enable bit of line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO1_MSK); +} + +/** + * @brief Check if debounce enable bit of line 1 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO1_MSK) == (EXTI_DB_GPIO1_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO2_MSK); +} + +/** + * @brief Disable debounce enable bit of line 2 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO2_MSK); +} + +/** + * @brief Check if debounce enable bit of line 2 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO2_MSK) == (EXTI_DB_GPIO2_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio3(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO3_MSK); +} + +/** + * @brief Disable debounce enable bit of line 3 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio3(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO3_MSK); +} + +/** + * @brief Check if debounce enable bit of line 3 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio3(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO3_MSK) == (EXTI_DB_GPIO3_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio4(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO4_MSK); +} + +/** + * @brief Disable debounce enable bit of line 4 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio4(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO4_MSK); +} + +/** + * @brief Check if debounce enable bit of line 4 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio4(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO4_MSK) == (EXTI_DB_GPIO4_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio5(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO5_MSK); +} + +/** + * @brief Disable debounce enable bit of line 5 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio5(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO5_MSK); +} + +/** + * @brief Check if debounce enable bit of line 5 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio5(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO5_MSK) == (EXTI_DB_GPIO5_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio6(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO6_MSK); +} + +/** + * @brief Disable debounce enable bit of line 6 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio6(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO6_MSK); +} + +/** + * @brief Check if debounce enable bit of line 6 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio6(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO6_MSK) == (EXTI_DB_GPIO6_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio7(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO7_MSK); +} + +/** + * @brief Disable debounce enable bit of line 7 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio7(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO7_MSK); +} + +/** + * @brief Check if debounce enable bit of line 7 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio7(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO7_MSK) == (EXTI_DB_GPIO7_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio8(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO8_MSK); +} + +/** + * @brief Disable debounce enable bit of line 8 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio8(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO1_MSK); +} + +/** + * @brief Check if debounce enable bit of line 8 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio8(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO8_MSK) == (EXTI_DB_GPIO8_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio9(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO9_MSK); +} + +/** + * @brief Disable debounce enable bit of line 9 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio9(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO9_MSK); +} + +/** + * @brief Check if debounce enable bit of line 9 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio9(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO9_MSK) == (EXTI_DB_GPIO9_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio10(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO10_MSK); +} + +/** + * @brief Disable debounce enable bit of line 10 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio10(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO10_MSK); +} + +/** + * @brief Check if debounce enable bit of line 10 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio10(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO10_MSK) == (EXTI_DB_GPIO10_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio11(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO11_MSK); +} + +/** + * @brief Disable debounce enable bit of line 11 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio11(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO11_MSK); +} + +/** + * @brief Check if debounce enable bit of line 11 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio11(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO11_MSK) == (EXTI_DB_GPIO11_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio12(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO12_MSK); +} + +/** + * @brief Disable debounce enable bit of line 12 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio12(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO12_MSK); +} + +/** + * @brief Check if debounce enable bit of line 12 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio12(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO12_MSK) == (EXTI_DB_GPIO12_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio13(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO13_MSK); +} + +/** + * @brief Disable debounce enable bit of line 13 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio13(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO13_MSK); +} + +/** + * @brief Check if debounce enable bit of line 13 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio13(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO13_MSK) == (EXTI_DB_GPIO13_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio14(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO14_MSK); +} + +/** + * @brief Disable debounce enable bit of line 14 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio14(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO14_MSK); +} + +/** + * @brief Check if debounce enable bit of line 14 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio14(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO14_MSK) == (EXTI_DB_GPIO14_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 1 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_gpio15(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_GPIO15_MSK); +} + +/** + * @brief Disable debounce enable bit of line 15 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_gpio15(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_GPIO15_MSK); +} + +/** + * @brief Check if debounce enable bit of line 15 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_gpio15(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_GPIO15_MSK) == (EXTI_DB_GPIO15_MSK)); +} + + +/** + * @brief Enable debounce enable bit of line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_cmp1(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_CMP1_MSK); +} + +/** + * @brief Disable debounce enable bit of line 16 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_cmp1(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_CMP1_MSK); +} + +/** + * @brief Check if debounce enable bit of line 16 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_cmp1(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_CMP1_MSK) == (EXTI_DB_CMP1_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_cmp2(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_CMP2_MSK); +} + +/** + * @brief Disable debounce enable bit of line 17 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_cmp2(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_CMP2_MSK); +} + +/** + * @brief Check if debounce enable bit of line 17 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_cmp2(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_CMP2_MSK) == (EXTI_DB_CMP2_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_pvd0(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_PVD0_MSK); +} + +/** + * @brief Disable debounce enable bit of line 20 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_pvd0(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_PVD0_MSK); +} + +/** + * @brief Check if debounce enable bit of line 20 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_pvd0(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_PVD0_MSK) == (EXTI_DB_PVD0_MSK)); +} + +/** + * @brief Enable debounce enable bit of line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_enable_db_wakeup(EXTI_TypeDef *exti) +{ + SET_BIT(exti->DB, EXTI_DB_WAKEUP_MSK); +} + +/** + * @brief Disable debounce enable bit of line 21 + * @param exti EXTI Instance + * @retval None + */ +__STATIC_INLINE void md_exti_disable_db_wakeup(EXTI_TypeDef *exti) +{ + CLEAR_BIT(exti->DB, EXTI_DB_WAKEUP_MSK); +} + +/** + * @brief Check if debounce enable bit of line 21 is enabled + * @param exti EXTI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_exti_is_enable_db_wakeup(EXTI_TypeDef *exti) +{ + return (READ_BIT(exti->DB, EXTI_DB_WAKEUP_MSK) == (EXTI_DB_WAKEUP_MSK)); +} + +/** + * @brief Set Debounce counter + * @param exti EXTI Port + * @param dbcnt This bit can be one of following valus: + * @arg Max Value 7 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_exti_set_dbcon_dbcnt(EXTI_TypeDef *exti, uint32_t dbcnt) +{ + MODIFY_REG(exti->DBCON, EXTI_DBCON_DBCNT_MSK, (dbcnt<DBCON, EXTI_DBCON_DBCNT_MSK)>>EXTI_DBCON_DBCNT_POSS); +} + +/** + * @brief Set Debounce prescale + * @param exti EXTI Port + * @param prescale This bit can be one of following valus: + * @arg Max Value 255 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_exti_set_dbcon_dbpre(EXTI_TypeDef *exti, uint32_t prescale) +{ + MODIFY_REG(exti->DBCON, EXTI_DBCON_DBPRE_MSK, (prescale<DBCON, EXTI_DBCON_DBPRE_MSK)>>EXTI_DBCON_DBPRE_POSS); +} + + +/** + * @} MD_EXTI_PF_DEBOUNCE_SETTING + */ + + + + + + +/** + * @} MD_EXTI_Public_Macros + */ + + + + +/* Public functions -----------------------------------------------------------*/ + + + +/** + * @} EXTI + */ + +#endif + + + +/** + * @} Micro_Driver + */ + +#endif + +#ifdef __cplusplus +} +#endif + + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_fc.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_fc.h new file mode 100644 index 0000000000000000000000000000000000000000..a7d85653bd8bc9dfdb0e60da6820ec53b67d19ce --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_fc.h @@ -0,0 +1,832 @@ +/** + ****************************************************************************** + * @file md_FC.h + * @brief ES32F0271 FC HEAD File. + * + * @version V1.00.01 + * @date 11/20/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_FC_H__ +#define __MD_FC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_fc.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (FC) + +/** @defgroup FC FC + * @brief FC micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_FC_Public_Types FC Public Types + * @{ + */ + +/** + * @brief MD FC Parameter Structure definition + */ +typedef struct +{ + uint32_t SAddr; /*!< Specifies the FC sector address to be erased. + This parameter should be aligned with 0x400*/ + + uint32_t SAddrC; /*!< Specifies the complement of FC sector address to be erased. + This parameter should be the complement of FC page address*/ + + uint16_t BCnt; /*!< Specifies the control byte count. + For program, this parameter should be aligned with 8 and smaller than 0x400 + For read, this parameter should be aligned with 4*/ + + uint32_t *pU32Buf; /*!< Specifies the uint32_t data buffer to program. + This parameter should be the pointer to uint32_t*/ + +} md_fc_ControlTypeDef; + +/** + * @brief MD FC Update Protect Level Structure definition + */ +typedef struct +{ + uint32_t UpdateL; /*!< Specifies the protect page bit mapping low byte (page 31~0) (0=protect, 1=unprotect). + This parameter can be any value between 0~65535*/ + + uint32_t UpdateH; /*!< Specifies the protect page bit mapping high byte (page 63~32) (0=protect, 1=unprotect). + This parameter can be any value between 0~65535*/ + + uint32_t ClearL; /*!< Specifies the reserve page bit mapping low byte (page 31~0) (0=reserve, 1=erase). + This parameter can be any value between 0~65535*/ + + uint32_t ClearH; /*!< Specifies the reserve page bit mapping high byte (page 63~32) (0=reserve, 1=erase). + This parameter can be any value between 0~65535*/ + +} md_fc_UpdProtTypeDef; + +/** + * @} MD_FC_Public_Types + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_FC_Public_Constants FC Public Constants + * @{ + */ + +#define MD_FC_PC_EF_MPAGESZ (0x00000400UL) /** @brief Select main page size */ +#define MD_FC_PC_EF_IPAGESZ (0x00000400UL) /** @brief Select information page size */ +#define MD_FC_PC_EF_MERASEID (0xA5A5AA55UL) /** @brief Select main erase ID */ + +#define MD_FC_PC_CMD_PROG_EFLASH (0xF0) /** @brief Program EFlash */ +#define MD_FC_PC_CMD_SECTOR_ERASE (0xF1) /** @brief Sector Erase */ +#define MD_FC_PC_CMD_MACRO_ERASE (0xF2) /** @brief Macro Erase */ +#define MD_FC_PC_CMD_UPDATE_LV1_PROTECT (0xF3) /** @brief Update Lv1 Protect */ +#define MD_FC_PC_CMD_UPDATE_LV2_PROTECT (0xF4) /** @brief Update Lv2 Protect */ +#define MD_FC_PC_CMD_OPTION_BYTE_ERASE (0xF5) /** @brief Option Byte Erase(Only for ISP) */ + +#define MD_FC_PC_SREMAP_MAIN (0x00) /** @brief Main Flash memory mapped at 0x0000 0000 */ +#define MD_FC_PC_SREMAP_SYSTEM (0x01) /** @brief System Flash memory mapped at 0x0000 0000 */ +#define MD_FC_PC_SREMAP_SRAM (0x02) /** @brief SRAM mapped at 0x0000 0000 */ + +/** + * @} MD_FC_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_FC_Public_Macros FC Public Macros + * @{ + */ + +/** @defgroup MD_FC_PM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in FC register + * @param __INSTANCE__ FC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define MD_FC_WRITEREG(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in FC register + * @param __INSTANCE__ FC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define MD_FC_READREG(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + +/** + * @brief Modify value in FC register + * @param __INSTANCE__ FC Instance + * @param __REG__ Register to be written + * @param __MASK__ Mask value to be written in the register + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define MD_FC_MODIFYREG(__INSTANCE__, __REG__, __MASK__, __VALUE__) MODIFY_REG(__INSTANCE__->__REG__, __MASK__, (__VALUE__)) + +/** + * @brief Set bit value in FC register + * @param __INSTANCE__ FC Instance + * @param __REG__ Register to be written + * @param __MASK__ Mask value to be set in the register + * @retval None + */ +#define MD_FC_SET_BIT(__INSTANCE__, __REG__, __MASK__) SET_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @brief Clear bit value in FC register + * @param __INSTANCE__ FC Instance + * @param __REG__ Register to be written + * @param __MASK__ Mask value to be cleared in the register + * @retval None + */ +#define MD_FC_CLEAR_BIT(__INSTANCE__, __REG__, __MASK__) CLEAR_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @brief Read bit value in FC register + * @param __INSTANCE__ FC Instance + * @param __REG__ Register to be read + * @param __MASK__ Mask value to be read in the register + * @retval Register bit value + */ +#define MD_FC_READBIT(__INSTANCE__, __REG__, __MASK__) READ_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @} MD_FC_PM_WRITE_READ + */ + +/** @defgroup MD_FC_Macro_Drivers FC Public Macro Drivers + * @{ + */ + +/** + * @brief Set FC CMD + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_cmd(uint32_t U32) +{ + MD_FC_WRITEREG(FC, CMD, U32); +} + +/** + * @brief Get FC CMD + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_cmd(void) +{ + return (MD_FC_READREG(FC, CMD)); +} + +/** + * @brief Set FC CMD Flash Command + * @note After procedure is finished, Flash command will be cleaned by itself + * @param @arg @ref MD_FC_PC_CMD_PROG_EFLASH(0xF0) : Program EFlash + * @arg @ref MD_FC_PC_CMD_SECTOR_ERASE(0xF1) : Sector Erase + * @arg @ref MD_FC_PC_CMD_MACRO_ERASE(0xF2) : Macro Erase + * @arg @ref MD_FC_PC_CMD_UPDATE_LV1_PROTECT(0xF3) : Update Lv1 Protect + * @arg @ref MD_FC_PC_CMD_UPDATE_LV2_PROTECT(0xF4) : Update Lv2 Protect + * @arg @ref MD_FC_PC_CMD_OPTION_BYTE_ERASE(0xF5) : Option Byte Erase(Only for ISP) + * @arg Else : Reserved + * @retval None + */ +__STATIC_INLINE void md_fc_set_fc_cmd(uint32_t Cmd) +{ + MD_FC_MODIFYREG(FC, CMD, FC_CMD_FC_CMD_MSK, (Cmd<>FC_CMD_FC_CMD_POSS); +} + +/** + * @brief Set FC PA + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_pa(uint32_t U32) +{ + MD_FC_WRITEREG(FC, PA, U32); +} + +/** + * @brief Get FC PA + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_pa(void) +{ + return (MD_FC_READREG(FC, PA)); +} + +/** + * @brief Set FC Program Counter + * @note Provide maximum 128 times continuous program + * @note Meanwhile user needs to fill out FC_PLD, FC_PHD and FC_CMD only + * @param @arg Max Value 0x7f + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_pa_pcnt(uint32_t PCnt) +{ + MD_FC_MODIFYREG(FC, PA, FC_PA_PCNT_MSK, (((PCnt>>3)-1)<>FC_PA_PCNT_POSS); +} + +/** + * @brief Enable FC Information Block + * @note User can program/erase Info. Block page 7 when Flash protect is disable + * @param None + * @retval None + */ +__STATIC_INLINE void md_fc_enable_pa_ifren(void) +{ + MD_FC_SET_BIT(FC, PA, FC_PA_IFREN_MSK); +} + +/** + * @brief Disable FC Information Block + * @param None + * @retval None + */ +__STATIC_INLINE void md_fc_disble_pa_ifren(void) +{ + MD_FC_CLEAR_BIT(FC, PA, FC_PA_IFREN_MSK); +} + +/** + * @brief Is FC Information Block Enabled + * @param None + * @retval The retval can be one of the following values: + * @arg 0x1 : Enable + * @arg 0x0 : Disable + */ +__STATIC_INLINE uint8_t md_fc_is_enabled_pa_ifren(void) +{ + return (MD_FC_READBIT(FC, PA, FC_PA_IFREN_MSK)>>FC_PA_IFREN_POS); +} + +/** + * @brief Set FC Program/Erase Address + * @note Program : PROG_ADDR[15:3] is double word address + * @note Sector Erase : PROG_ADDR[15:10] is page address, and PROG_ADDR[9:0] dont care + * @note Macro Erase : PROG_ADDR[15:0] dont care + * @param @arg Max Value 0xffc0 + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_pa_prog_addr(uint32_t PAddr) +{ + MD_FC_MODIFYREG(FC, PA, FC_PA_PROG_ADDR_MSK, (PAddr<>FC_PA_PROG_ADDR_POSS); +} + +/** + * @brief Set FC Program Low Data + * @note Eflash supports 64 bits data program, this register provides Low 32 bits data + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_pld(uint32_t U32) +{ + MD_FC_WRITEREG(FC, PLD, U32); +} + +/** + * @brief Get FC Program Low Data + * @note Eflash supports 64 bits data program, this register provides Low 32 bits data + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_pld(void) +{ + return (MD_FC_READREG(FC, PLD)); +} + +/** + * @brief Set FC Program High Data + * @note Eflash supports 64 bits data program, this register provides high 32 bits data + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_phd(uint32_t U32) +{ + MD_FC_WRITEREG(FC, PHD, U32); +} + +/** + * @brief Get FC Program High Data + * @note Eflash supports 64 bits data program, this register provides high 32 bits data + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_phd(void) +{ + return (MD_FC_READREG(FC, PHD)); +} + +/** + * @brief Set FC CON + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_con(uint32_t U32) +{ + MD_FC_WRITEREG(FC, CON, U32); +} + +/** + * @brief Get FC CON + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_con(void) +{ + return (MD_FC_READREG(FC, CON)); +} + +/** + * @brief Enable FC Control Sleep + * @note When receive sleep or deep sleep from CPU, controller will mask Eflash control signal when this option is selected. + * @param None + * @retval None + */ +__STATIC_INLINE void md_fc_enable_con_sleep(void) +{ + MD_FC_SET_BIT(FC, CON, FC_CON_SLEEP_MSK); +} + +/** + * @brief Disable FC Control Sleep + * @note When receive sleep or deep sleep from CPU, controller will mask Eflash control signal when this option is selected. + * @param None + * @retval None + */ +__STATIC_INLINE void md_fc_disable_con_sleep(void) +{ + MD_FC_CLEAR_BIT(FC, CON, FC_CON_SLEEP_MSK); +} + +/** + * @brief Is FC Control Sleep Enabled + * @note When receive sleep or deep sleep from CPU, controller will mask Eflash control signal when this option is selected. + * @param None + * @retval The retval can be one of the following values: + * 0x0:Disable Flash sleep mask function + * 0x1:Enable Flash sleep mask function + */ +__STATIC_INLINE uint8_t md_fc_is_enabled_con_sleep(void) +{ + return (MD_FC_READBIT(FC, CON, FC_CON_SLEEP_MSK)>>FC_CON_SLEEP_POS); +} + +/** + * @brief Enable FC Control PreFetch + * @note This function allow user to pre-fetch 64 bits data from Eflash when the last 32bits data in data buffer has been read + * @param None + * @retval None + */ +__STATIC_INLINE void md_fc_enable_con_pfen(void) +{ + MD_FC_SET_BIT(FC, CON, FC_CON_PFEN_MSK); +} + +/** + * @brief Disable FC Control PreFetch + * @note This function allow user to pre-fetch 64 bits data from Eflash when the last 32bits data in data buffer has been read + * @param None + * @retval None + */ +__STATIC_INLINE void md_fc_disable_con_pfen(void) +{ + MD_FC_CLEAR_BIT(FC, CON, FC_CON_PFEN_MSK); +} + +/** + * @brief Is FC Control PreFetch Enabled + * @note This function allow user to pre-fetch 64 bits data from Eflash when the last 32bits data in data buffer has been read + * @param None + * @retval The retval can be one of the following values: + * 0x0:Disable pre-fetch function + * 0x1:Enable pre-fetch function + */ +__STATIC_INLINE uint8_t md_fc_is_enabled_con_pfen(void) +{ + return (MD_FC_READBIT(FC, CON, FC_CON_PFEN_MSK)>>FC_CON_PFEN_POS); +} + +/** + * @brief Set FC Control Wait Cycle + * @note Eflash supports 64 bits data program, this register provides high 32 bits data + * @param @arg Max Value 0x3 + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_con_wait(uint32_t Wait) +{ + MD_FC_MODIFYREG(FC, CON, FC_CON_WAIT_MSK, (Wait<>FC_CON_WAIT_POSS); +} + +/** + * @brief Get FC STAT + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_sta(void) +{ + return (MD_FC_READREG(FC, STAT)); +} + +/** + * @brief Get FC Status Option Valid + * @note This bit is set when Option Byte Data is valid + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 : Option Byte Data is valid + * @arg Min Value 0x0 : Option Byte Data is invalid + */ +__STATIC_INLINE uint8_t md_fc_get_stat_opvd(void) +{ + return (MD_FC_READBIT(FC, STAT, FC_STAT_OPVD_MSK)>>FC_STAT_OPVD_POS); +} + +/** + * @brief Get FC Status Main Unprotect Level2 Status + * @note This bit is set when Flash main block is unprotect + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 : Lv2 Protect Function is disabled + * @arg Min Value 0x0 : Lv2 Protect Function is enabled + */ +__STATIC_INLINE uint8_t md_fc_get_stat_munp2(void) +{ + return (MD_FC_READBIT(FC, STAT, FC_STAT_MUNP2_MSK)>>FC_STAT_MUNP2_POS); +} + +/** + * @brief Get FC Status Main Unprotect Level1 Status + * @note This bit is set when Flash main block is unprotect + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 : Lv1 Protect Function is disabled + * @arg Min Value 0x0 : Lv1 Protect Function is enabled + */ +__STATIC_INLINE uint8_t md_fc_get_stat_munp1(void) +{ + return (MD_FC_READBIT(FC, STAT, FC_STAT_MUNP1_MSK)>>FC_STAT_MUNP1_POS); +} + +/** + * @brief Set FC Protect Update Low Data + * @note Update main block Lv2 Protect Page 0 ~ Page 31 + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_upl(uint32_t U32) +{ + MD_FC_WRITEREG(FC, UPL, U32); +} + +/** + * @brief Get FC Protect Update Low Data + * @note Update main block Lv2 Protect Page 0 ~ Page 31 + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_upl(void) +{ + return (MD_FC_READREG(FC, UPL)); +} + +/** + * @brief Set FC Protect Update High Data + * @note Update main block Lv2 Protect Page 63 ~ Page 32 + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_fc_set_uph(uint32_t U32) +{ + MD_FC_WRITEREG(FC, UPH, U32); +} + +/** + * @brief Get FC Protect Update High Data + * @note Update main block Lv2 Protect Page 63 ~ Page 32 + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_uph(void) +{ + return (MD_FC_READREG(FC, UPH)); +} + +/** + * @brief Get FC OP_TRIM + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_op_trim(void) +{ + return (MD_FC_READREG(FC, OP_TRIM)); +} + +/** + * @brief Get FC OP_TRIM BangGap trim valid + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @arg Value 0xa5 BG Trim is Valid + */ +__STATIC_INLINE uint32_t md_fc_get_op_trim_bgtrimvd(void) +{ + return (MD_FC_READBIT(FC, OP_TRIM, FC_OP_TRIM_BGTRIMVD_MSK)>>FC_OP_TRIM_BGTRIMVD_POSS); +} + +/** + * @brief Get FC Trim BangGap trim value + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_op_trim_bgtrim(void) +{ + return (MD_FC_READBIT(FC, OP_TRIM, FC_OP_TRIM_BGTRIM_MSK)>>FC_OP_TRIM_BGTRIM_POSS); +} + +/** + * @brief Get FC Trim HRC calibration value valid + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @arg Value 0xa5 BG Trim is Valid + */ +__STATIC_INLINE uint32_t md_fc_get_op_trim_hrctrimvd(void) +{ + return (MD_FC_READBIT(FC, OP_TRIM, FC_OP_TRIM_HRCTRIMVD_MSK)>>FC_OP_TRIM_HRCTRIMVD_POSS); +} + +/** + * @brief Get FC Trim HRC calibration value + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_op_trim_hrctrim(void) +{ + return (MD_FC_READBIT(FC, OP_TRIM, FC_OP_TRIM_HRCTRIM_MSK)>>FC_OP_TRIM_HRCTRIM_POSS); +} + +/** + * @brief Get FC Lv2 Protect Low 32 bits + * @note Lv2 Protect Page 0 ~ Page 31.The Bit is set to 0 when the page is protected + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_op_prt2l(void) +{ + return (MD_FC_READREG(FC, OP_PRT2L)); +} + +/** + * @brief Get FC Lv2 Protect High 32 bits + * @note Lv2 Protect Page 63 ~ Page 32.The Bit is set to 0 when the page is protected + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_op_prt2h(void) +{ + return (MD_FC_READREG(FC, OP_PRT2H)); +} + +/** + * @brief Get FC Lv1 Protect Low 32 bits + * @note Lv1 Protect Page 0 ~ Page 31.The Bit is set to 0 when the page is protected + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_op_prt1l(void) +{ + return (MD_FC_READREG(FC, OP_PRT1L)); +} + +/** + * @brief Get FC Lv1 Protect High 32 bits + * @note Lv1 Protect Page 63 ~ Page 32.The Bit is set to 0 when the page is protected + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_op_prt1h(void) +{ + return (MD_FC_READREG(FC, OP_PRT1H)); +} + +/** + * @brief Get FC OP_REMAP + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_fc_get_op_remap(void) +{ + return (MD_FC_READREG(FC, OP_REMAP)); +} + +/** + * @brief Get FC Hardware Remap Option + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xff + * @arg Min Value 0x0 + * @arg Value 0xa5 skip boot loader + */ +__STATIC_INLINE uint8_t md_fc_get_op_remap_hremap(void) +{ + return (MD_FC_READBIT(FC, OP_REMAP, FC_OP_REMAP_HREMAP_MSK)>>FC_OP_REMAP_HREMAP_POSS); +} + +/** + * @brief Get FC Software Remap Option + * @param None + * @retval The retval can be one of the following values: + * @arg @ref MD_FC_PC_SREMAP_MAIN(0x0) : Main Flash memory mapped at 0x0000 0000 + * @arg @ref MD_FC_PC_SREMAP_SYSTEM(0x1) : System Flash memory mapped at 0x0000 0000 + * @arg @ref MD_FC_PC_SREMAP_SRAM(0x2) : SRAM mapped at 0x0000 0000 + * @arg Else : Reserved + */ +__STATIC_INLINE uint8_t md_fc_get_op_remap_sremap(void) +{ + return (MD_FC_READBIT(FC, OP_REMAP, FC_OP_REMAP_SREMAP_MSK)>>FC_OP_REMAP_SREMAP_POSS); +} + +/** + * @brief Get FC Software Remap Base Address Settng Data + * @note If set 0x1, it means second 4k Byte, If set 0x2, it means third 4k Byte, and so on + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xf + * @arg Min Value 0x0 + * @note This value is invalid if the value in SREMAP field is 0x3 + */ +__STATIC_INLINE uint8_t md_fc_get_op_remap_sefbase(void) +{ + return (MD_FC_READBIT(FC, OP_REMAP, FC_OP_REMAP_SEFBASE_MSK)>>FC_OP_REMAP_SEFBASE_POSS); +} + +/** + * @} MD_FC_Macro_Drivers + */ + +/** + * @} MD_FC_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_FC_Public_Functions FC Public Functions + * @{ + */ +ErrorStatus md_fc_merase(uint32_t MEraseID); +ErrorStatus md_fc_serase(md_fc_ControlTypeDef *pSErasePara); +ErrorStatus md_fc_program(md_fc_ControlTypeDef *pProgramPara); +ErrorStatus md_fc_read(md_fc_ControlTypeDef *pReadPara); +ErrorStatus md_fc_updprotl1(md_fc_UpdProtTypeDef *pUpdPL1Para); +ErrorStatus md_fc_updprotl2(md_fc_UpdProtTypeDef *pUpdPL2Para); +ErrorStatus md_fc_updremap(uint8_t UpdRemap); +/** + * @} MD_FC_Public_Functions + */ + +#endif + +/** + * @} FC + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ + diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_gpio.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..a096fa7a01a57bd0e1d249d4feb6a43fd9dc5a08 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_gpio.h @@ -0,0 +1,2873 @@ +/** + ****************************************************************************** + * @file md_GPIO.h + * @brief ES32F0271 GPIO HEAD File. + * + * @version V1.00.02 + * @date 30/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_GPIO_H__ +#define __MD_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_gpio.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) + +/** @defgroup GPIO GPIO + * @brief GPIO micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_GPIO_PT_INIT GPIO Public Init structures + * @{ + */ + +/** + * @brief MD GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref MD_GPIO_PC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref MD_GPIO_PC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_set_mode().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref MD_GPIO_PC_OT. + + GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_set_output_type().*/ + + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref MD_GPIO_PC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_set_pull().*/ + + uint32_t OutDrive; /*!< Specifies the output driving current for the selected pins. + This parameter can be a value of @ref MD_GPIO_PC_DS. + + GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_get_ds().*/ + + uint32_t Function; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref MD_GPIO_PC_FUNCTION. + + GPIO HW configuration can be modified afterwards using unitary function @ref md_gpio_set_function0_7() and md_gpio_set_function8_15().*/ +} md_gpio_inittypedef; + +/** + * @} MD_GPIO_PT_INIT + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_GPIO_Public_Constants GPIO Public Constants + * @{ + */ + +/** @defgroup MD_GPIO_PC_PIN PIN + * @{ + */ +#define MD_GPIO_PIN_0 (0X1<<0) /*!< Select pin 0 */ +#define MD_GPIO_PIN_1 (0X1<<1) /*!< Select pin 1 */ +#define MD_GPIO_PIN_2 (0X1<<2) /*!< Select pin 2 */ +#define MD_GPIO_PIN_3 (0X1<<3) /*!< Select pin 3 */ +#define MD_GPIO_PIN_4 (0X1<<4) /*!< Select pin 4 */ +#define MD_GPIO_PIN_5 (0X1<<5) /*!< Select pin 5 */ +#define MD_GPIO_PIN_6 (0X1<<6) /*!< Select pin 6 */ +#define MD_GPIO_PIN_7 (0X1<<7) /*!< Select pin 7 */ +#define MD_GPIO_PIN_8 (0X1<<8) /*!< Select pin 8 */ +#define MD_GPIO_PIN_9 (0X1<<9) /*!< Select pin 9 */ +#define MD_GPIO_PIN_10 (0X1<<10) /*!< Select pin 10 */ +#define MD_GPIO_PIN_11 (0X1<<11) /*!< Select pin 11 */ +#define MD_GPIO_PIN_12 (0X1<<12) /*!< Select pin 12 */ +#define MD_GPIO_PIN_13 (0X1<<13) /*!< Select pin 13 */ +#define MD_GPIO_PIN_14 (0X1<<14) /*!< Select pin 14 */ +#define MD_GPIO_PIN_15 (0X1<<15) /*!< Select pin 15 */ +#define MD_GPIO_PIN_ALL (MD_GPIO_PIN_0 | MD_GPIO_PIN_1 | MD_GPIO_PIN_2 | \ + MD_GPIO_PIN_3 | MD_GPIO_PIN_4 | MD_GPIO_PIN_5 | \ + MD_GPIO_PIN_6 | MD_GPIO_PIN_7 | MD_GPIO_PIN_8 | \ + MD_GPIO_PIN_9 | MD_GPIO_PIN_10 | MD_GPIO_PIN_11 | \ + MD_GPIO_PIN_12 | MD_GPIO_PIN_13 | MD_GPIO_PIN_14 | \ + MD_GPIO_PIN_15) /*!< Select all pins */ +/** + * @} MD_GPIO_PC_PIN + */ + +/** @defgroup MD_GPIO_PC_MODE Mode + * @{ + */ +#define MD_GPIO_MODE_INPUT (0x00000000UL) /** @brief Select input mode */ +#define MD_GPIO_MODE_OUTPUT (0X00000001UL) /** @brief Select output mode */ +#define MD_GPIO_MODE_FUNCTION (0X00000002UL) /** @brief Select function mode */ +#define MD_GPIO_MODE_ANALOG (0x00000003UL) /** @brief Select analog mode */ +/** + * @} MD_GPIO_PC_MODE + */ + +/** @defgroup MD_GPIO_PC_OT Output Type + * @{ + */ +#define MD_GPIO_OUTPUT_PUSHPULL (0x00000000U) /** @brief Select push-pull as output type */ +#define MD_GPIO_OUTPUT_OPENDRAIN (0x00000001U) /** @brief Select open-drain as output type */ +/** + * @} MD_GPIO_PC_OT + */ + +/** @defgroup MD_GPIO_PC_PULL Pull Up Pull Down + * @{ + */ +#define MD_GPIO_PULL_FLOATING (0x00000000UL) /** @brief Select I/O no pull */ +#define MD_GPIO_PULL_UP (0x00000001UL) /** @brief Select I/O pull up */ +#define MD_GPIO_PULL_DOWN (0x00000002UL) /** @brief Select I/O pull down */ +/** + * @} MD_GPIO_PC_PULL + */ + +/** @defgroup MD_GPIO_PC_DS Output driving/sinking current + * @{ + */ +#define MD_GPIO_DS_16mA (0x00000001U) /** @brief Select I/O 16mA driving/sinking current */ +#define MD_GPIO_DS_8mA (0x00000000U) /** @brief Select I/O 8mA driving/sinking current */ +/** + * @} MD_GPIO_PC_DS + */ + +/** @defgroup MD_GPIO_PC_FUNCTION Alternate Function + * @{ + */ +#define MD_GPIO_AF0 (0x00000000UL) /** @brief Select alternate function 0 */ +#define MD_GPIO_AF1 (0x00000001UL) /** @brief Select alternate function 1 */ +#define MD_GPIO_AF2 (0x00000002UL) /** @brief Select alternate function 2 */ +#define MD_GPIO_AF3 (0x00000003UL) /** @brief Select alternate function 3 */ +#define MD_GPIO_AF4 (0x00000004UL) /** @brief Select alternate function 4 */ +#define MD_GPIO_AF5 (0x00000005UL) /** @brief Select alternate function 5 */ +#define MD_GPIO_AF6 (0x00000006UL) /** @brief Select alternate function 6 */ +#define MD_GPIO_AF7 (0x00000007UL) /** @brief Select alternate function 7 */ +#define MD_GPIO_AF8 (0x00000008UL) /** @brief Select alternate function 8 */ +/** + * @} MD_GPIO_PC_FUNCTION + */ + +/** @defgroup MD_GPIO_PC_FILTER Input Filter + * @{ + */ +#define MD_GPIO_FILTER_BYPASS (0x00000000UL) /** @brief Select bypass */ +#define MD_GPIO_FILTER_GLITCH (0x00000001UL) /** @brief Select glitch free for 20ns plus */ +/** + * @} MD_GPIO_PC_FILTER + */ + +/** @defgroup MD_GPIO_PC_IST Input Schmitt Trigger + * @{ + */ +#define MD_GPIO_IST_TTL (0x00000000UL) /** @brief Select TTL IO Level */ +#define MD_GPIO_IST_CMOS (0x00000001UL) /** @brief Select CMOS IO Level */ +/** + * @} MD_GPIO_PC_IST + */ + +/** @defgroup MD_GPIO_ODATA_SEL GPIO Output Select + * @{ + */ +#define MD_GPIO_OUTPUT_LOW (0x00000000UL) /** @brief Select GPIO Output Low*/ +#define MD_GPIO_OUTPUT_HIGH (0x00000001UL) /** @brief Select GPIO Output High*/ +/** + * @} MD_GPIO_ODATA_SEL + */ + +/** + * @} MD_GPIO_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_GPIO_Public_Macros GPIO Public Macros + * @{ + */ + +/** @defgroup MD_GPIO_MOD_MOD15 MOD15 + * @brief Set MOD15 configure I/O mode bit for md_gpio_set_mod() function used + * @param mod15 This parameter can be one of the following values: + * @arg @ref MD_GPIO_MODE_INPUT + * @arg @ref MD_GPIO_MODE_OUTPUT + * @arg @ref MD_GPIO_MODE_FUNCTION + * @arg @ref MD_GPIO_MODE_ANALOG + * @{ + */ +#define md_gpio_set_mod_mod15_fun(mod15) (mod15<MOD, (mod15|mod14|mod13|mod12|mod11|mod10|mod9|mod8|mod7|mod6|mod5|mod4|mod3|mod2|mod1|mod0)); +} + + + + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, output mode, Alternate function mode, or Analog mode. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref MD_GPIO_MODE_INPUT + * @arg @ref MD_GPIO_MODE_OUTPUT + * @arg @ref MD_GPIO_MODE_FUNCTION + * @arg @ref MD_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void md_gpio_set_mode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MOD, (GPIO_MOD_MOD0_MSK << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, output mode, Alternate function mode, or Analog mode. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_MODE_INPUT + * @arg @ref MD_GPIO_MODE_OUTPUT + * @arg @ref MD_GPIO_MODE_FUNCTION + * @arg @ref MD_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t md_gpio_get_mode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MOD, + (GPIO_MOD_MOD0_MSK << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** @defgroup MD_GPIO_OT_OT15 OT15 + * @brief Set OT15 output data bit for md_gpio_set_ot() function used + * @param ot15 This parameter can be one of the following values: + * @arg @ref MD_GPIO_OUTPUT_PUSHPULL + * @arg @ref MD_GPIO_OUTPUT_OPENDRAIN + * @{ + */ +#define md_gpio_set_ot_ot15_fun(ot15) (ot15<OT, (ot15|ot14|ot13|ot12|ot11|ot10|ot9|ot8|ot7|ot6|ot5|ot4|ot3|ot2|ot1|ot0)); +} + + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @param GPIOx GPIO Port + * @param Pin This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param OutputType This parameter can be one of the following values: + * @arg @ref MD_GPIO_OUTPUT_PUSHPULL + * @arg @ref MD_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void md_gpio_set_output_type(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OT, (GPIO_OT_OT0_MSK << (POSITION_VAL(Pin))), (OutputType << (POSITION_VAL(Pin)))); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_OUTPUT_PUSHPULL + * @arg @ref MD_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t md_gpio_get_output_type(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)((READ_BIT(GPIOx->OT, + (GPIO_OT_OT_MSK << (POSITION_VAL(Pin)))) >> (POSITION_VAL(Pin))) & (0x1U)); +} + + +/** @defgroup MD_GPIO_PUD_PUD15 PUD15 + * @brief Set PUD15 I/O pull-up or pull-down bit for md_gpio_set_pud() function used + * @param pud15 This parameter can be one of the following values: + * @arg @ref MD_GPIO_PULL_FLOATING + * @arg @ref MD_GPIO_PULL_UP + * @arg @ref MD_GPIO_PULL_DOWN + * @{ + */ +#define md_gpio_set_pud_pud15_fun(pud15) (pud15<PUD, (pud15|pud14|pud13|pud12|pud11|pud10|pud9|pud8|pud7|pud6|pud5|pud4|pud3|pud2|pud1|pud0)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref MD_GPIO_PULL_FLOATING + * @arg @ref MD_GPIO_PULL_UP + * @arg @ref MD_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUD, (GPIO_PUD_PUD0_MSK << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_PULL_FLOATING + * @arg @ref MD_GPIO_PULL_UP + * @arg @ref MD_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t md_gpio_get_pull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUD, + (GPIO_PUD_PUD0_MSK << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + + +/** @defgroup MD_GPIO_DS_DS15 DS15 + * @brief Set DS15 I/O Driving/Sinking current bit for md_gpio_set_ds() function used + * @param ds15 This parameter can be one of the following values: + * @arg @ref MD_GPIO_DS_8mA + * @arg @ref MD_GPIO_DS_16mA + * @{ + */ +#define md_gpio_set_ds_ds15_fun(ds15) (ds15<DS, (ds15|ds14|ds13|ds12|ds11|ds10|ds9|ds8|ds7|ds6|ds5|ds4|ds3|ds2|ds1|ds0)); +} + + +/** + * @brief Configure gpio output driving/sinking current a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param Odrv This parameter can be one of the following values: + * @arg @ref MD_GPIO_DS_8mA + * @arg @ref MD_GPIO_DS_16mA + * @retval None + */ +__STATIC_INLINE void md_gpio_set_ds(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Odrv) +{ + MODIFY_REG(GPIOx->DS, (GPIO_DS_DS_MSK << (POSITION_VAL(Pin))), (Odrv << (POSITION_VAL(Pin)))); +} + +/** + * @brief Return gpio output driving/sinking current a dedicated pin on a dedicated port. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_DS_8mA + * @arg @ref MD_GPIO_DS_16mA + */ +__STATIC_INLINE uint32_t md_gpio_get_ds(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->DS, + (GPIO_DS_DS_MSK << (POSITION_VAL(Pin)))) >> (POSITION_VAL(Pin))); +} + +/** @defgroup MD_GPIO_AFL_AF0 AF0 + * @brief Set AF0 Alternate function selection bit for md_gpio_set_afl() function used + * @param af0 This parameter can be one of the following values: + * @arg @ref MD_GPIO_AF0 + * @arg @ref MD_GPIO_AF1 + * @arg @ref MD_GPIO_AF2 + * @arg @ref MD_GPIO_AF3 + * @arg @ref MD_GPIO_AF4 + * @arg @ref MD_GPIO_AF5 + * @arg @ref MD_GPIO_AF6 + * @arg @ref MD_GPIO_AF7 + * @{ + */ +#define md_gpio_set_afl_af0_fun(af0) (af0<AFL, (af7|af6|af5|af4|af3|af2|af1|af0)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from FUNCTION0 to FUNCTION7 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @param Function This parameter can be one of the following values: + * @arg @ref MD_GPIO_AF0 + * @arg @ref MD_GPIO_AF1 + * @arg @ref MD_GPIO_AF2 + * @arg @ref MD_GPIO_AF3 + * @arg @ref MD_GPIO_AF4 + * @arg @ref MD_GPIO_AF5 + * @arg @ref MD_GPIO_AF6 + * @arg @ref MD_GPIO_AF7 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_function0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Function) +{ + MODIFY_REG(GPIOx->AFL, (GPIO_AFL_AF0_MSK << (POSITION_VAL(Pin) * 4U)), + (Function << (POSITION_VAL(Pin) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_AF0 + * @arg @ref MD_GPIO_AF1 + * @arg @ref MD_GPIO_AF2 + * @arg @ref MD_GPIO_AF3 + * @arg @ref MD_GPIO_AF4 + * @arg @ref MD_GPIO_AF5 + * @arg @ref MD_GPIO_AF6 + * @arg @ref MD_GPIO_AF7 + */ +__STATIC_INLINE uint32_t md_gpio_get_function0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFL, + (GPIO_AFL_AF0_MSK << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); +} + + +/** @defgroup MD_GPIO_AFH_AF8 AF8 + * @brief Set AF8 Alternate function selection bit for md_gpio_set_afh() function used + * @param af8 This parameter can be one of the following values: + * @arg @ref MD_GPIO_AF0 + * @arg @ref MD_GPIO_AF1 + * @arg @ref MD_GPIO_AF2 + * @arg @ref MD_GPIO_AF3 + * @arg @ref MD_GPIO_AF4 + * @arg @ref MD_GPIO_AF5 + * @arg @ref MD_GPIO_AF6 + * @arg @ref MD_GPIO_AF7 + * @{ + */ +#define md_gpio_set_afh_af8_fun(af8) (af8<AFH, (af15|af14|af13|af12|af11|af10|af9|af8)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from FUNCTION0 to FUNCTION7 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param Function This parameter can be one of the following values: + * @arg @ref MD_GPIO_AF0 + * @arg @ref MD_GPIO_AF1 + * @arg @ref MD_GPIO_AF2 + * @arg @ref MD_GPIO_AF3 + * @arg @ref MD_GPIO_AF4 + * @arg @ref MD_GPIO_AF5 + * @arg @ref MD_GPIO_AF6 + * @arg @ref MD_GPIO_AF7 + * @retval None + */ +__STATIC_INLINE void md_gpio_set_function8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Function) +{ + MODIFY_REG(GPIOx->AFH, (GPIO_AFH_AF8_MSK << (POSITION_VAL(Pin >> 8U) * 4U)), + (Function << (POSITION_VAL(Pin >> 8U) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref MD_GPIO_AF0 + * @arg @ref MD_GPIO_AF1 + * @arg @ref MD_GPIO_AF2 + * @arg @ref MD_GPIO_AF3 + * @arg @ref MD_GPIO_AF4 + * @arg @ref MD_GPIO_AF5 + * @arg @ref MD_GPIO_AF6 + * @arg @ref MD_GPIO_AF7 + */ +__STATIC_INLINE uint32_t md_gpio_get_function8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFH, + (GPIO_AFH_AF8_MSK << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); +} + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note LOCK key write sequence: + * WR GPIOx_LCK = (~LCK[15:0]<<16) + LCK[15:0] + * WR GPIOx_LCK = (~LCK[15:0]<<16) + LCK[15:0] + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void md_gpio_set_lock(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + SET_BIT(GPIOx->LCK, PinMask); +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_gpio_get_lock(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->LCK, PinMask) == (PinMask)); +} + + + +/** @defgroup MD_GPIO_IST_IST15 IST15 + * @brief Set IST15 configure the input schmitt trigger level bit for md_gpio_set_ist_fun() function used + * @param ist15 This parameter can be one of the following values: + * @arg @ref MD_GPIO_IST_TTL + * @arg @ref MD_GPIO_IST_CMOS + * @{ + */ +#define md_gpio_set_ist_ist15_fun(ist15) (ist15<IST, (ist15|ist14|ist13|ist12|ist11|ist10|ist9|ist8|ist7|ist6|ist5|ist4|ist3|ist2|ist1|ist0)); +} + +/** + * @brief Configure GPIOx port Input Schmitt Trigger Register. + * @note Warning: only one pin can be passed as parameter. + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @param Iolev This parameter can be one of the following values: + * @arg @ref MD_GPIO_IST_TTL + * @arg @ref MD_GPIO_IST_CMOS + * @retval None + */ +__STATIC_INLINE void md_gpio_set_ist(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Iolev) +{ + MODIFY_REG(GPIOx->IST, (GPIO_IST_IST_MSK << (POSITION_VAL(Pin))), (Iolev << (POSITION_VAL(Pin)))); +} + +/** + * @brief Return GPIOx port Input Schmitt Trigger Register + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @retval The retval can be one of the following values: + * @arg @ref MD_GPIO_IST_TTL + * @arg @ref MD_GPIO_IST_CMOS + */ +__STATIC_INLINE uint32_t md_gpio_get_ist(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->IST, (GPIO_IST_IST_MSK << (POSITION_VAL(Pin)))) >> (POSITION_VAL(Pin))); +} + +/** + * @brief Return full input data register value for a dedicated port. + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t md_gpio_get_input_port(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDATA)); +} + + + + +/** @defgroup MD_GPIO_ODATA_OD15 OD15 + * @brief Set OD15 set/reset bit for md_gpio_set_bsbr() function used + * @param od15 This parameter can be one of the following values: + * @arg @ref MD_GPIO_OUTPUT_LOW + * @arg @ref MD_GPIO_OUTPUT_HIGH + * @{ + */ +#define md_gpio_set_odata_od15_fun(od15) (od15<ODATA, (od15|od14|od13|od12|od11|od10|od9|od8|od7|od6|od5|od4|od3|od2|od1|od0)); +} + + + + + +/** + * @brief Write output data register for the port. + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void md_gpio_set_output_port(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODATA, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t md_gpio_get_output_port(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODATA)); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_high(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSBR, PinMask); +} + +/** + * @brief Reset several pins to low level on dedicated gpio port. + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void md_gpio_set_pin_low(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSBR, (PinMask << 16)); +} + + +/** @defgroup MD_GPIO_FIR_FIR15 FIR15 + * @brief Set FIR15 configure the input signal over thought a glitch filter bit for md_gpio_set_fir() function used + * @param fir15 This parameter can be one of the following values: + * @arg @ref MD_GPIO_FILTER_BYPASS + * @arg @ref MD_GPIO_FILTER_GLITCH + * @{ + */ +#define md_gpio_set_fir_fir15_fun(fir15) (fir15<FIR, (fir15|fir14|fir13|fir12|fir11|fir10|fir9|fir8|fir7|fir6|fir5|fir4|fir3|fir2|fir1|fir0)); +} + + +/** + * @brief Write input filter register for the port. + * @note These bits are written by software to configure + * the input signal over thought a glitch filter. + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void md_gpio_set_filter(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->FIR, PinMask); +} + +/** + * @brief Return full input filter data register value for a dedicated port. + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref MD_GPIO_PIN_0 + * @arg @ref MD_GPIO_PIN_1 + * @arg @ref MD_GPIO_PIN_2 + * @arg @ref MD_GPIO_PIN_3 + * @arg @ref MD_GPIO_PIN_4 + * @arg @ref MD_GPIO_PIN_5 + * @arg @ref MD_GPIO_PIN_6 + * @arg @ref MD_GPIO_PIN_7 + * @arg @ref MD_GPIO_PIN_8 + * @arg @ref MD_GPIO_PIN_9 + * @arg @ref MD_GPIO_PIN_10 + * @arg @ref MD_GPIO_PIN_11 + * @arg @ref MD_GPIO_PIN_12 + * @arg @ref MD_GPIO_PIN_13 + * @arg @ref MD_GPIO_PIN_14 + * @arg @ref MD_GPIO_PIN_15 + * @arg @ref MD_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_gpio_get_filter(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->FIR, PinMask) == (PinMask)); +} + +/** + * @} MD_GPIO_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_GPIO_Public_Functions GPIO Public Functions + * @{ + */ + +/** @defgroup MD_GPIO_PF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @} MD_GPIO_PF_Port_Configuration + */ + +/** @defgroup MD_GPIO_PF_Data_Access Data Access + * @{ + */ + +/** + * @} MD_GPIO_PF_Data_Access + */ + + +/** @defgroup MD_GPIO_PF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus md_gpio_deinit(GPIO_TypeDef *GPIOx); +ErrorStatus md_gpio_init(GPIO_TypeDef *GPIOx, md_gpio_inittypedef *GPIO_InitStruct); +void md_gpio_struct_init(md_gpio_inittypedef *GPIO_InitStruct); + +/** + * @} MD_GPIO_PF_Init + */ + +/** + * @} MD_GPIO_Public_Functions + */ + +#endif + +/** + * @} GPIO + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_hdiv.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_hdiv.h new file mode 100644 index 0000000000000000000000000000000000000000..5baf2d5d2364f984ca854923a1d81e364b4f7dd5 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_hdiv.h @@ -0,0 +1,292 @@ +/** + ****************************************************************************** + * @file md_HDIV.h + * @brief ES32F0271 HDIV HEAD File. + * + * @version V1.00.01 + * @date 11/20/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_HDIV_H__ +#define __MD_HDIV_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_hdiv.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (HDIV) + +/** @defgroup HDIV HDIV + * @brief HDIV micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ + +/** + * @brief MD HDIV Parameter Structure definition + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_HDIV_Public_Constants HDIV Public Constants + * @{ + */ + +/** + * @} MD_HDIV_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_HDIV_Public_Macros HDIV Public Macros + * @{ + */ + +/** @defgroup MD_HDIV_PM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in HDIV register + * @param __INSTANCE__ HDIV Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define MD_HDIV_WRITEREG(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in HDIV register + * @param __INSTANCE__ HDIV Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define MD_HDIV_READREG(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + +/** + * @brief Modify value in HDIV register + * @param __INSTANCE__ HDIV Instance + * @param __REG__ Register to be written + * @param __MASK__ Mask value to be written in the register + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define MD_HDIV_MODIFYREG(__INSTANCE__, __REG__, __MASK__, __VALUE__) MODIFY_REG(__INSTANCE__->__REG__, __MASK__, (__VALUE__)) + +/** + * @brief Set bit value in HDIV register + * @param __INSTANCE__ HDIV Instance + * @param __REG__ Register to be read + * @param __MASK__ Mask value to be set in the register + * @retval None + */ +#define MD_HDIV_SET_BIT(__INSTANCE__, __REG__, __MASK__) SET_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @brief Clear bit value in HDIV register + * @param __INSTANCE__ HDIV Instance + * @param __REG__ Register to be read + * @param __MASK__ Mask value to be cleased in the register + * @retval None + */ +#define MD_HDIV_CLEAR_BIT(__INSTANCE__, __REG__, __MASK__) CLEAR_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @brief Read bit value in HDIV register + * @param __INSTANCE__ HDIV Instance + * @param __REG__ Register to be read + * @param __MASK__ Mask value to be read in the register + * @retval Register bit value + */ +#define MD_HDIV_READBIT(__INSTANCE__, __REG__, __MASK__) READ_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @} MD_HDIV_PM_WRITE_READ + */ + +/** @defgroup MD_HDIV_Macro_Drivers HDIV Public Macro Drivers + * @{ + */ + +/** + * @brief Set HDIV DIVDR + * @note This register is given the dividend of divider before calculation starting + * @note When this register is written, hardware divider will start calculate + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_hdiv_set_divdr(uint32_t U32) +{ + MD_HDIV_WRITEREG(HDIV, DIVDR, U32); +} + +/** + * @brief Get HDIV DIVIDEND + * @note This register is given the dividend of divider before calculation starting + * @note When this register is written, hardware divider will start calculate + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_hdiv_get_divdr(void) +{ + return (MD_HDIV_READREG(HDIV, DIVDR)); +} + +/** + * @brief Set HDIV DIVSR + * @note This register is given the divisor of divider before calculation starts + * @note When this register is written, hardware divider will start calculate + * @param @arg Max Value 0xffffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_hdiv_set_divsr(uint32_t U32) +{ + MD_HDIV_WRITEREG(HDIV, DIVSR, U32); +} + +/** + * @brief Get HDIV DIVSR + * @note This register is given the divisor of divider before calculation starts. + * @note When this register is written, hardware divider will start calculate + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_hdiv_get_divsr(void) +{ + return (MD_HDIV_READREG(HDIV, DIVSR)); +} + +/** + * @brief Get HDIV DIVQR + * @note This register holds the quotient result of divider after calculation complete + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_hdiv_get_divqr(void) +{ + return (MD_HDIV_READREG(HDIV, DIVQR)); +} + +/** + * @brief Get HDIV DIVRR + * @note This register holds the remainder result of divider after calculation complete + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_hdiv_get_divrr(void) +{ + return (MD_HDIV_READREG(HDIV, DIVRR)); +} + +/** + * @brief Get HDIV DIVSTAT + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x7 + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_hdiv_get_divstat(void) +{ + return (MD_HDIV_READREG(HDIV, DIVSTAT)); +} + +/** + * @brief Is HDIV DIVSTAT SIGN Active + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 : Signed + * @arg Min Value 0x0 : Unsigned + */ +__STATIC_INLINE uint8_t md_hdiv_get_divsts_sign(void) +{ + return (MD_HDIV_READBIT(HDIV, DIVSTAT, HDIV_DIVSTAT_SIGN_MSK)>>HDIV_DIVSTAT_SIGN_POS); +} + +/** + * @brief Is HDIV DIVSTAT DIV0 Active + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 : The divisor is 0 + * @arg Min Value 0x0 : The divisor is not 0 + */ +__STATIC_INLINE uint8_t md_hdiv_get_divsts_div0(void) +{ + return (MD_HDIV_READBIT(HDIV, DIVSTAT, HDIV_DIVSTAT_DIV0_MSK)>>HDIV_DIVSTAT_DIV0_POS); +} + +/** + * @brief Is HDIV DIVSTAT BUSY Active + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 : The divider is busy + * @arg Min Value 0x0 : The divider is not busy + */ +__STATIC_INLINE uint8_t md_hdiv_get_divsts_busy(void) +{ + return (MD_HDIV_READBIT(HDIV, DIVSTAT, HDIV_DIVSTAT_BUSY_MSK)>>HDIV_DIVSTAT_BUSY_POS); +} + +/** + * @} MD_HDIV_Macro_Drivers + */ + +/** + * @} MD_HDIV_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_HDIV_Public_Functions HDIV Public Functions + * @{ + */ + +/** + * @} MD_HDIV_Public_Functions + */ + +#endif + +/** + * @} HDIV + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_i2c.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..9f2e2ff964225944ae73df335e3e3691d58885c4 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_i2c.h @@ -0,0 +1,3273 @@ +/** + ****************************************************************************** + * @file md_i2c.h + * @brief ES32F0271 I2C HEAD File. + * + * @version V0.01 + * @date 4/12/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_I2C_H__ +#define __MD_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_i2c.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (I2C1) | defined (I2C2) + +/** @defgroup I2C I2C + * @brief I2C micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + + +/* Public Init Structure ------------------------------------------------------*/ +/** @defgroup MD_I2C_PT_INIT I2C Public Init structure + * @brief I2C Init structure. + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization section in Reference manual */ + + uint32_t Address1; /*!< Specifies the first device address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddrSize; /*!< Specifies the device address 1 size (7-bit or 10-bit). + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1 + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t Address2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t Address2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ +} md_i2c_inittypedef; +/** + * @} MD_I2C_PT_INIT + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_I2C_Public_Constants I2C Public Constants + * @{ + */ + +/** @defgroup MD_I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define MD_I2C_ADDRESSINGMODE_7BIT (0x00000000U) /*!< DISABLE */ +#define MD_I2C_ADDRESSINGMODE_10BIT (I2C_CON2_ADD10_MSK) /*!< I2C_CON2_ADD10_MSK = 1<<11 */ +/** + * @} MD_I2C_ADDRESSING_MODE + */ + +/** @defgroup MD_I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define MD_I2C_DUALADDRESS_DISABLE (0x00000000U) /*!< DISABLE */ +#define MD_I2C_DUALADDRESS_ENABLE (I2C_ADDR2_OA2EN_MSK) /*!< I2C_ADDR2_OA2EN_MSK = 1<<15 */ +/** + * @} MD_I2C_DUAL_ADDRESSING_MODE + */ + +/** @defgroup MD_I2C_TIMING_CONFIG I2C Timing Config + * @note pllmul<<28|presc<<24|scll<<16|sclh<<8|sdadel<<4|scldel + * @{ + */ +/* pllmul presc scll sclh sdadel scldel */ +#define CLK10kHz8M (1<<28) |(1<<24) |(0xC7<<16)|(0xC3<<8)|(2<<4)|(4) /*!< APB = 8MHz; CLK = 10kHz */ +#define CLK100kHz8M (1<<28) |(1<<24) |(0x13<<16)|(0xF<<8) |(2<<4)|(4) /*!< APB = 8MHz; CLK = 100kHz */ +#define CLK400kHz8M (1<<28) |(0<<24) |(9<<16) |(3<<8) |(1<<4)|(3) /*!< APB = 8MHz; CLK = 400kHz */ +#define CLK500kHz8M (1<<28) |(0<<24) |(6<<16) |(3<<8) |(0<<4)|(1) /*!< APB = 8MHz; CLK = 500kHz */ +#define CLK10kHz16M (3<<28) |(3<<24) |(0xC7<<16)|(0xC3<<8)|(2<<4)|(4) /*!< APB = 16MHz; CLK = 10kHz */ +#define CLK100kHz16M (3<<28) |(3<<24) |(0x13<<16)|(0xF<<8) |(2<<4)|(4) /*!< APB = 16MHz; CLK = 100kHz */ +#define CLK400kHz16M (3<<28) |(1<<24) |(9<<16) |(3<<8) |(2<<4)|(3) /*!< APB = 16MHz; CLK = 400kHz */ +#define CLK1000kHz16M (3<<28) |(0<<24) |(4<<16) |(2<<8) |(0<<4)|(2) /*!< APB = 16MHz; CLK = 1000kHz */ +#define CLK10kHz48M (11U<<28)|(0xB<<24)|(0xC7<<16)|(0xC3<<8)|(2<<4)|(4) /*!< APB = 48MHz; CLK = 10kHz */ +#define CLK100kHz48M (11U<<28)|(0xB<<24)|(0x13<<16)|(0xF<<8) |(2<<4)|(4) /*!< APB = 48MHz; CLK = 100kHz */ +#define CLK400kHz48M (11U<<28)|(5<<24) |(9<<16) |(3<<8) |(3<<4)|(3) /*!< APB = 48MHz; CLK = 400kHz */ +#define CLK1000kHz48M (11U<<28)|(5<<24) |(3<<16) |(1<<8) |(0<<4)|(1) /*!< APB = 48MHz; CLK = 1000kHz */ +/** + * @} MD_I2C_TIMING_CONFIG + */ + +/** @defgroup MD_I2C_ADDRESS2_MASKS I2C Address2 Masks + * @{ + */ +#define MD_I2C_ADDR2_NOMASK (0x0000U) /*!< NOMASK */ +#define MD_I2C_ADDR2_MASK01 (0x0100U) /*!< MASK01 */ +#define MD_I2C_ADDR2_MASK02 (0x0200U) /*!< MASK02 */ +#define MD_I2C_ADDR2_MASK03 (0x0300U) /*!< MASK03 */ +#define MD_I2C_ADDR2_MASK04 (0x0400U) /*!< MASK04 */ +#define MD_I2C_ADDR2_MASK05 (0x0500U) /*!< MASK05 */ +#define MD_I2C_ADDR2_MASK06 (0x0600U) /*!< MASK06 */ +#define MD_I2C_ADDR2_MASK07 (0x0700U) /*!< MASK07 */ +/** + * @} MD_I2C_ADDRESS2_MASKS + */ + +/** @defgroup MD_I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define MD_I2C_GENERALCALL_DISABLE (0x00000000U) /*!< DISABLE */ +#define MD_I2C_GENERALCALL_ENABLE (I2C_CON1_GCEN_MSK) /*!< I2C_CON1_GCEN_MSK = 1<<19 */ +/** + * @} MD_I2C_GENERAL_CALL_ADDRESSING_MODE + */ + +/** @defgroup MD_I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define MD_I2C_NOSTRETCH_DISABLE (0x00000000U) /*!< DISABLE */ +#define MD_I2C_NOSTRETCH_ENABLE (I2C_CON1_NOSTRETCH_MSK) /*!< I2C_CON1_NOSTRETCH_MSK = 1<<17 */ +/** + * @} MD_I2C_NOSTRETCH_MODE + */ + +/** @defgroup MD_I2C_MODE I2C Mode + * @{ + */ +#define MD_I2C_MODE_NONE ((uint8_t)0x00U /*!< None */ +#define MD_I2C_MODE_MASTER ((uint8_t)0x10U) /*!< Master */ +#define MD_I2C_MODE_SLAVE ((uint8_t)0x20U) /*!< Slave */ +#define MD_I2C_MODE_MEM ((uint8_t)0x40U) /*!< Mem */ +/** + * @} MD_I2C_MODE + */ + +/** @defgroup MD_I2C_PECBYTE_ENABLE Pecbyte Enable + * @{ + */ +#define MD_I2C_PECBYTE_ENABLE I2C_CON2_PECBYTE_MSK /*!< I2C_CON2_PECBYTE_MSK = 1<<26 */ +/** + * @} MD_I2C_PECBYTE_ENABLE + */ + +/** @defgroup MD_I2C_AUTOEND_ENABLE I2C Autoend Enable + * @{ + */ +#define MD_I2C_SOFTEND_MODE (0x00000000U) /*!< DISABLE */ +#define MD_I2C_AUTOEND_MODE (I2C_CON2_AUTOEND_MSK) /*!< I2C_CON2_AUTOEND_MSK = 1<<25 */ +/** + * @} MD_I2C_AUTOEND_ENABLE + */ + +/** @defgroup MD_I2C_RELOAD_MODE I2C Reload Mode + * @{ + */ +#define MD_I2C_NORELOAD_MODE (0x00000000U) /*!< DISABLE */ +#define MD_I2C_RELOAD_MODE (I2C_CON2_RELOAD_MSK) /*!< I2C_CON2_RELOAD_MSK = 1<<24 */ +/** + * @} MD_I2C_RELOAD_MODE + */ + +/** @defgroup MD_I2C_NACKNOWLEDGE Acknowledge Generation + * @{ + */ +#define MD_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ +#define MD_I2C_NACK I2C_CON2_NACK_MSK /*!< NACK is sent after current received byte, I2C_CON2_NACK_MSK = 1<<15 */ +/** + * @} MD_I2C_NACKNOWLEDGE + */ + +/** @defgroup MD_I2C_STOP_GENERATION Stop Generation + * @{ + */ +#define MD_I2C_STOP_GENERATION I2C_CON2_STOP_MSK /*!< I2C_CON2_STOP_MSK = 1<<14 */ +/** + * @} MD_I2C_STOP_GENERATION + */ + +/** @defgroup MD_I2C_START_GENERATION Start Generation + * @{ + */ +#define MD_I2C_START_GENERATION I2C_CON2_START_MSK /*!< I2C_CON2_PECBYTE_MSK = 1<<13 */ +/** + * @} MD_I2C_START_GENERATION + */ + +/** @defgroup MD_I2C_HEAD10R Acknowledge Generation + * @{ + */ +#define MD_I2C_GENERAL_10BIT_READ 0x00000000U /*!< DISABLE */ +#define MD_I2C_SIMPLIFIED_10BIT_READ I2C_CON2_HEAD10R_MSK /*!< I2C_CON2_HEAD10R_MSK = 1<<12 */ +/** + * @} MD_I2C_HEAD10R + */ + +/** @defgroup MD_I2C_TRANSFER_DIRECTION Transfer direction (master mode) + * @{ + */ +#define MD_I2C_MASTER_WRITE 0x00000000U /*!< Master Write */ +#define MD_I2C_MASTER_READ I2C_CON2_RD_WRN_MSK /*!< I2C_CON2_RD_WRN_MSK = 1<<10 */ +/** + * @} MD_I2C_TRANSFER_DIRECTION + */ + +/** @defgroup MD_I2C_OA1_MODE Own Address 1 mode + * @{ + */ +#define MD_I2C_OA1_7BIT 0x00000000U /*!< OA1 7-bit mode */ +#define MD_I2C_OA1_10BIT I2C_ADDR1_OA1MODE_MSK /*!< I2C_ADDR1_OA1MODE_MSK = 1<<10 */ +/** + * @} MD_I2C_OA1_MODE + */ + +/** @defgroup MD_I2C_TIDLE_MODE Tidle mode + * @{ + */ +#define MD_I2C_LOW_TIMEOUTA 0x00000000U /*!< TIMEOUTA is used to detect SCL low timeout */ +#define MD_I2C_IDLE_TIMEOUTA I2C_TIMEOUTR_TIDLE_MSK /*!< TIMEOUTA is used to detectbus idle condition, I2C_TIMEOUTR_TIDLE_MSK = 1<<12 */ +/** + * @} MD_I2C_TIDLE_MODE + */ + +/** @defgroup MD_I2C_RXFIFO_THRESHOLD FIFO Threshold + * @{ + */ +#define MD_I2C_RXFIFO_THRESHOLD_RX1 0U<CON1, Reg_Value); +} + +/** + * @brief I2C Get CON1 + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_con1(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->CON1)); +} + +/** + * @brief I2C PEC Enable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_pecen(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_PECEN_MSK); +} + +/** + * @brief I2C PEC Disable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_pecen(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_PECEN_MSK); +} + +/** + * @brief Indicate if I2C PEC is enabled + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to '0' + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_pecen(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_PECEN_MSK) == (I2C_CON1_PECEN_MSK)); +} + +/** + * @brief I2C Alert Enable + * @note When ALERTEN = 0, the SMBA pin can be used as a standard GPIO.If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_alerten(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_ALERTEN_MSK); +} + +/** + * @brief I2C Alert Disable + * @note When ALERTEN = 0, the SMBA pin can be used as a standard GPIO.If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_alerten(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_ALERTEN_MSK); +} + +/** + * @brief Indicate if I2C PEC is enabled + * @note When ALERTEN = 0, the SMBA pin can be used as a standard GPIO.If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_alerten(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_ALERTEN_MSK) == (I2C_CON1_ALERTEN_MSK)); +} + +/** + * @brief I2C SMBus Device Default address Enable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Device default address 0b1100 001. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_smbden(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_SMBDEN_MSK); +} + +/** + * @brief I2C SMBus Device Default address Disable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Device default address 0b1100 001. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_smbden(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_SMBDEN_MSK); +} + +/** + * @brief Indicate if I2C SMBus Device Default address is enabled + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Device default address 0b1100 001. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_smbden(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_SMBDEN_MSK) == (I2C_CON1_SMBDEN_MSK)); +} + +/** + * @brief I2C SMBus Host address Enable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Host default address 0b0001 000. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_smbhen(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_SMBHEN_MSK); +} + +/** + * @brief I2C SMBus Host address Disable + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Host default address 0b0001 000. + * This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_smbhen(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_SMBHEN_MSK); +} + +/** + * @brief Indicate if I2C SMBus Host address is enabled + * @note If the SMBus feature is not supported,this bit is reserved and forced by hardware to 0. Host default address 0b0001 000. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_smbhen(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_SMBHEN_MSK) == (I2C_CON1_SMBHEN_MSK)); +} + +/** + * @brief I2C general call Enable + * @note This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_gcen(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_GCEN_MSK); +} + +/** + * @brief I2C general call Disable + * @note This register must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_gcen(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_GCEN_MSK); +} + +/** + * @brief Indicate if I2C general call is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_gcen(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_GCEN_MSK) == (I2C_CON1_GCEN_MSK)); +} + +/** + * @brief I2C clock stretching Disable + * @note Clock stretching disables. This bit can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_nostretch(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_NOSTRETCH_MSK); +} + +/** + * @brief I2C clock stretching Enable + * @note Clock stretching enables.This bit can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_nostretch(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_NOSTRETCH_MSK); +} + +/** + * @brief Indicate if I2C clock nostretching is enabled + * @note This bit can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_nostretch(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_NOSTRETCH_MSK) == (I2C_CON1_NOSTRETCH_MSK)); +} + +/** + * @brief I2C slave byte control Enable + * @note This bit can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_sbc(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_SBC_MSK); +} + +/** + * @brief I2C slave byte control Disable + * @note This bit can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_sbc(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_SBC_MSK); +} + +/** + * @brief Indicate if I2C slave byte control is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_sbc(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_SBC_MSK) == (I2C_CON1_SBC_MSK)); +} + +/** + * @brief I2C DMA reception requests Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_rxdmaen(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_RXDMAEN_MSK); +} + +/** + * @brief I2C DMA reception requests Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_rxdmaen(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_RXDMAEN_MSK); +} + +/** + * @brief Indicate if I2C DMA reception requests is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_rxdmaen(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_RXDMAEN_MSK) == (I2C_CON1_RXDMAEN_MSK)); +} + +/** + * @brief I2C DMA transmission requests Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_txdmaen(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_TXDMAEN_MSK); +} + +/** + * @brief I2C DMA transmission requests Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_txdmaen(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_TXDMAEN_MSK); +} + +/** + * @brief Indicate if I2C DMA transmission requests is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_txdmaen(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_TXDMAEN_MSK) == (I2C_CON1_TXDMAEN_MSK)); +} + +/** + * @brief Set I2C digital noise filter + * @note If the analog filter is also enabled,the digital filter is added to the analog filter. + * This filter can only be programmed when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param filter_capability digital noise filter capability + * @arg Max Value 0xFF + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con1_dnf(I2C_TypeDef *I2Cx, uint32_t filter_capability) +{ + MODIFY_REG(I2Cx->CON1, I2C_CON1_DNF_MSK, filter_capability<CON1, I2C_CON1_DNF_MSK)>>I2C_CON1_DNF_POSS); +} + +/** + * @brief I2C Peripheral Enable + * @note When PE = 0, the I2C SCL and SDA lines are released. + * Internal state machines and status bits are put back to their reset value. + * When cleared, PE must be kept low for at least 3 APB clock cycles. + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con1_pe(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON1, I2C_CON1_PE_MSK); +} + +/** + * @brief I2C Peripheral Disable + * @note When PE = 0, the I2C SCL and SDA lines are released.Internal state machines and status bits are put back to their reset value.When cleared,PE must be kept low for at least 3 APB clock cycles + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con1_pe(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON1, I2C_CON1_PE_MSK); +} + +/** + * @brief Indicate if Peripheral is enabled + * @note When PE = 0, the I2C SCL and SDA lines are released.Internal state machines and status bits are put back to their reset value.When cleared,PE must be kept low for at least 3 APB clock cycles + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con1_pe(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON1, I2C_CON1_PE_MSK) == (I2C_CON1_PE_MSK)); +} + +/** + * @brief I2C Set CON2 + * @note None + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->CON2, Reg_Value); +} + +/** + * @brief I2C Get CON2 + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_con2(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->CON2)); +} + +/** + * @brief I2C Set ACK Update + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_ack_upd(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_ACK_UPD_MSK); +} + +/** + * @brief I2C Hold Ack Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_con2_holdack(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CON2, I2C_CON2_HOLDACK_MSK); +} + +/** + * @brief I2C Hold Ack Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_con2_holdack(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CON2, I2C_CON2_HOLDACK_MSK); +} + +/** + * @brief Indicate if I2C Hold Ack is enabled + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_con2_holdack(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CON2, I2C_CON2_HOLDACK_MSK) == (I2C_CON2_HOLDACK_MSK)); +} + +/** + * @brief Set I2C Packet error checking byte + * @note This bit is set by software, and cleared by hardware when the PEC is transferred, + * or when a STOP condition or an Address matched is received, also when PE=0. + * Writing 0 to this bit has no effet. This bit has no effect when RELOAD is set, + * and when SBC is 0 in the slave mode. + * If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. + * @param I2Cx I2C Instance + * @param setbit + * @arg @ref MD_I2C_PECBYTE_ENABLE + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_pecbyte(I2C_TypeDef *I2Cx, uint32_t setbit) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_PECBYTE_MSK, setbit); +} + +/** + * @brief Get I2C Packet error checking byte + * @note This bit is set by software, and cleared by hardware when the PEC is transferred, + * or when a STOP condition or an Address matched is received, also when PE=0. + * Writing 0 to this bit has no effet. This bit has no effect when RELOAD is set, + * and when SBC is 0 in the slave mode. + * If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_pecbyte(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_PECBYTE_MSK)>>I2C_CON2_PECBYTE_POS); +} + +/** + * @brief Set I2C automatic end mode or software end mode(master mode) + * @note This bit has no effect in slave mode or when the RELOAD bit is set. + * Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. + * Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. + * @param I2Cx I2C Instance + * @param setbit + * @arg @ref MD_I2C_SOFTEND_MODE + * @arg @ref MD_I2C_AUTOEND_MODE + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_autoend(I2C_TypeDef *I2Cx, uint32_t setbit) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_AUTOEND_MSK, setbit); +} + +/** + * @brief Get I2C automatic or software end mode(master mode) + * @note This bit has no effect in slave mode or when the RELOAD bit is set. + * Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. + * Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_autoend(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_AUTOEND_MSK)>>I2C_CON2_AUTOEND_POS); +} + +/** + * @brief Set I2C NBYTES reload mode or not + * @note RELOAD = 0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow). + * RELOAD = 1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded). + * TCR flag is set when NBYTES data are transferred, stretching SCL low. + * @param I2Cx I2C Instance + * @param setbit + * @arg @ref MD_I2C_NORELOAD_MODE + * @arg @ref MD_I2C_RELOAD_MODE + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_reload(I2C_TypeDef *I2Cx, uint32_t setbit) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_RELOAD_MSK, setbit); +} + +/** + * @brief Get I2C RELOAD value + * @note RELOAD = 0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow). + * RELOAD = 1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded). + * TCR flag is set when NBYTES data are transferred, stretching SCL low. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_reload(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_RELOAD_MSK)>>I2C_CON2_RELOAD_POS); +} + +/** + * @brief Set I2C number of bytes + * @note The number of bytes to be transmitted/received is programmed there. + * This field is dont care in slave mode with SBC=0. + * Changing these bits when the START bit is set is not allowed. + * @param I2Cx I2C Instance + * @param nbytes number of bytes + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_nbytes(I2C_TypeDef *I2Cx, uint32_t nbytes) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_NBYTES_MSK, nbytes<CON2, I2C_CON2_NBYTES_MSK)>>I2C_CON2_NBYTES_POSS); +} + +/** + * @brief Set I2C NACK generation(slave mode) + * @note Writing 0 to this bit has no effect. This bit is used in slave mode only. + * When an overrun occurs in slave receiver NOSTRETCH mode,a NACK is automatically generated whatever the NACK bit value. + * When hardware PEC checking is enabled(PECBYTE = 1),the PEC acknowledge value does not depend on the NACK value. + * @param I2Cx I2C Instance + * @param nack nack generation + * @arg @ref MD_I2C_NACK + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_nack(I2C_TypeDef *I2Cx, uint32_t nack) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_NACK_MSK, nack); +} + +/** + * @brief Get I2C NACK bit state(slave mode) + * @note NACK=1: will generate NACK + * NACK=0: will generate ACK + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_nack(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_NACK_MSK)>>I2C_CON2_NACK_POS); +} + +/** + * @brief Set I2C Stop generation(master mode) + * @note Writing 0 to this bit has no effect. + * @param I2Cx I2C Instance + * @param stop_generate stop generate + * @arg MD_I2C_STOP_GENERATION + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_stop(I2C_TypeDef *I2Cx, uint32_t stop_generate) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_STOP_MSK, stop_generate); +} + +/** + * @brief Get I2C state of STOP bit(master mode) + * @note Writing 0 to this bit has no effect. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_stop(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_STOP_MSK)>>I2C_CON2_STOP_POS); +} + +/** + * @brief Set I2C Start generation + * @note Writing 0 to this bit has no effect.The START bit can be set even if the bus is BUSY or I2C is in slave mode. + * In 10-bit addressing mode, if a NACK is received on the first part of the address, + * the START bit is not cleared by hardware and the master will resend the address sequence. + * @param I2Cx I2C Instance + * @param start_generate stop generate + * @arg MD_I2C_START_GENERATION + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_start(I2C_TypeDef *I2Cx, uint32_t start_generate) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_START_MSK, start_generate); +} + +/** + * @brief Get I2C state of START bit + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_start(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_START_MSK)>>I2C_CON2_START_POS); +} + +/** + * @brief Set the master operates in 10-bit addressing mode(master receiver mode) + * @note Changing this bit when the START bit is set is not allowed. + * It can be used when the 10-bit transmission was done before. + * @param I2Cx I2C Instance + * @param read_header format of read header + * @arg @ref MD_I2C_GENERAL_10BIT_READ + * @arg @ref MD_I2C_SIMPLIFIED_10BIT_READ + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_head10r(I2C_TypeDef *I2Cx, uint32_t read_header) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_HEAD10R_MSK, read_header); +} + +/** + * @brief Indicate if I2C 10-bit address header only read direction is enabled(master receiver mode) + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_head10r(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_HEAD10R_MSK)>>I2C_CON2_HEAD10R_POS); +} + +/** + * @brief I2C 10-bit addressing mode Enable(master mode) + * @note Changing this bit when the START bit is set is not allowed. + * @param I2Cx I2C Instance + * @param addrmode + @arg @ref MD_I2C_ADDRESSINGMODE_7BIT + @arg @ref MD_I2C_ADDRESSINGMODE_10BIT + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_add10(I2C_TypeDef *I2Cx, uint32_t addrmode) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_ADD10_MSK, addrmode); +} + +/** + * @brief Get I2C addressing mode is 10-bit or 7-bit mode(master mode) + * @note ADD10=1: 10-bit mode + * ADD10=0: 7-bit mode + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_add10(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_ADD10_MSK)>>I2C_CON2_ADD10_POS); +} + +/** + * @brief Set Master transfer direction(master mode) + * @note Changing this bit when the START bit is set is not allowed. + * @param I2Cx I2C Instance + * @param direction + * @arg @ref MD_I2C_MASTER_WRITE + * @arg @ref MD_I2C_MASTER_READ + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_rd_wrn(I2C_TypeDef *I2Cx, uint32_t direction) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_RD_WRN_MSK, direction); +} + +/** + * @brief Get Master transfer direction(master mode) + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_con2_rd_wrn(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_RD_WRN_MSK)>>I2C_CON2_RD_WRN_POS); +} + +/** + * @brief Set I2C slave address(master mode) + * @note Changing these bits when the START bit is set is not allowed + * For 7-bit mode, bit 7 to 1 are valid; for 10-bit mode, all 10 bits are valid. + * @param I2Cx I2C Instance + * @param slave_addr I2C slave address + * @arg Max Value 7-bit: 0xFF / 10-bit: 0x3FF + * @arg Min Value 7-bit: 0x2 / 10-bit: 0x1 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_con2_sadd(I2C_TypeDef *I2Cx, uint32_t slave_addr) +{ + MODIFY_REG(I2Cx->CON2, I2C_CON2_SADD_MSK, slave_addr); +} + +/** + * @brief Get I2C slave address(master mode) + * @note Changing these bits when the START bit is set is not allowed + * For 7-bit mode, bit 7 to 1 are valid; for 10-bit mode, all 10 bits are valid. + * @param I2Cx I2C Instance + * @retval I2C slave address + * @arg Max Value 7-bit: 0xFF / 10-bit: 0x3FF + * @arg Min Value 7-bit: 0x2 / 10-bit: 0x1 + */ +__STATIC_INLINE uint32_t md_i2c_get_sadd_7bit(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CON2, I2C_CON2_SADD_MSK)); +} + +/** + * @brief Set I2C ADDR1 + * @note These bits can be written only when OA1EN=0 except OA1EN. + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_addr1(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->ADDR1, Reg_Value); +} + +/** + * @brief Get I2C ADDR1 + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_addr1(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->ADDR1)); +} + +/** + * @brief I2C address register 1 Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_addr1_oa1en(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN_MSK); +} + +/** + * @brief I2C address register 1 Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_addr1_oa1en(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN_MSK); +} + +/** + * @brief Indicate if address register 1 is enabled + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_addr1_oa1en(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1EN_MSK) == (I2C_ADDR1_OA1EN_MSK)); +} + +/** + * @brief Set I2C OA1 bit mode + * @param I2Cx I2C Instance + * @param oa1mode + * @arg @ref MD_I2C_OA1_7BIT + * @arg @ref MD_I2C_OA1_10BIT + * @retval None + */ +__STATIC_INLINE void md_i2c_set_addr1_oa1mode(I2C_TypeDef *I2Cx, uint32_t oa1mode) +{ + MODIFY_REG(I2Cx->ADDR1, I2C_ADDR1_OA1MODE_MSK, oa1mode); +} + +/** + * @brief Get I2C own address 1 mode + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_addr1_oa1mode(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1MODE_MSK)>>I2C_ADDR1_OA1MODE_POS); +} + +/** + * @brief Set I2C address1 + * @note For 7-bit mode, bit 7 to 1 are valid; for 10-bit mode, all 10 bits are valid. + * @param I2Cx I2C Instance + * @param own_addr I2C own address1 + * @arg Max Value 7-bit: 0xFF / 10-bit: 0x3FF + * @arg Min Value 7-bit: 0x2 / 10-bit: 0x1 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_addr1_oa1(I2C_TypeDef *I2Cx, uint32_t own_addr) +{ + MODIFY_REG(I2Cx->ADDR1, I2C_ADDR1_OA1_MSK, own_addr); +} + +/** + * @brief Get I2C address1 + * @note For 7-bit mode, bit 7 to 1 are valid; for 10-bit mode, all 10 bits are valid. + * @param I2Cx I2C Instance + * @retval I2C own address1 + * @arg Max Value 7-bit: 0xFF / 10-bit: 0x3FF + * @arg Min Value 7-bit: 0x2 / 10-bit: 0x1 + */ +__STATIC_INLINE uint32_t md_i2c_get_addr1_oa1(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ADDR1, I2C_ADDR1_OA1_MSK)); +} + +/** + * @brief Set I2C ADDR2 + * @note These bits can be written only when OA2EN=0 except OA2EN. + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_addr2(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->ADDR2, Reg_Value); +} + +/** + * @brief Get I2C ADDR2 + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_addr2(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->ADDR2)); +} + +/** + * @brief I2C own address register 2 Enable + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_addr2_oa2en(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN_MSK); +} + +/** + * @brief I2C own address register 2 Disable + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_addr2_oa2en(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN_MSK); +} + +/** + * @brief Indicate if address register 2 is enabled + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_addr2_oa2en(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2EN_MSK) == (I2C_ADDR2_OA2EN_MSK)); +} + +/** + * @brief Set I2C own address2 mask + * @note These bits can be written only when OA2EN=0. + * As soon as OA2MSK is not equal to 0,the reserved I2C addresses(0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. + * @param I2Cx I2C Instance + * @param oa2_mask I2C own address2 mask + * @arg @ref MD_I2C_ADDR2_NOMASK + * @arg @ref MD_I2C_ADDR2_MASK01 + * @arg @ref MD_I2C_ADDR2_MASK02 + * @arg @ref MD_I2C_ADDR2_MASK03 + * @arg @ref MD_I2C_ADDR2_MASK04 + * @arg @ref MD_I2C_ADDR2_MASK05 + * @arg @ref MD_I2C_ADDR2_MASK06 + * @arg @ref MD_I2C_ADDR2_MASK07 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_addr2_oa2mask(I2C_TypeDef *I2Cx, uint32_t oa2_mask) +{ + MODIFY_REG(I2Cx->ADDR2, I2C_ADDR2_OA2MSK_MSK, oa2_mask); +} + +/** + * @brief Get I2C address2 mask + * @note None + * As soon as OA2MSK is not equal to 0,the reserved I2C addresses(0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches. + * @param I2Cx I2C Instance + * @retval I2C own address2 mask(value 0 to 7) + */ +__STATIC_INLINE uint32_t md_i2c_get_addr2_oa2mask(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->ADDR2, I2C_ADDR2_OA2MSK_MSK)>>I2C_ADDR2_OA2MSK_POSS); +} + +/** + * @brief Set I2C own address2 + * @note These bits can be written only when OA2EN=0. + * @param I2Cx I2C Instance + * @param own_addr I2C own address2 + * @arg Max Value 0x7F + * @arg Min Value 0x1 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_addr2_oa2(I2C_TypeDef *I2Cx, uint32_t own_addr) +{ + MODIFY_REG(I2Cx->ADDR2, I2C_ADDR2_OA2_MSK, own_addr <ADDR2, I2C_ADDR2_OA2_MSK)>>I2C_ADDR2_OA2_POSS); +} + +/** + * @brief Set I2C TIMINGR + * @note These bits must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timingr(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->TIMINGR, Reg_Value); +} + +/** + * @brief Get I2C TIMINGR + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_timingr(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->TIMINGR)); +} + +/** + * @brief Set I2C Timing prescaler + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param timing_prescaler + * @arg Max Value 0xF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timingr_presc(I2C_TypeDef *I2Cx, uint32_t timing_prescaler) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_PRESC_MSK, timing_prescaler << I2C_TIMINGR_PRESC_POSS); +} + +/** + * @brief Get I2C Timing prescaler + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval timing_prescaler + * @arg Max Value 0xF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_timingr_presc(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC_MSK)>>I2C_TIMINGR_PRESC_POSS); +} + +/** + * @brief Set I2C date setup time + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param data_setup_time + * @arg Max Value 0xF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timingr_scldel(I2C_TypeDef *I2Cx, uint32_t data_setup_time) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, data_setup_time <TIMINGR, I2C_TIMINGR_SCLDEL_MSK)>>I2C_TIMINGR_SCLDEL_POSS); +} + +/** + * @brief Set I2C date hold time + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param data_hold_time + * @arg Max Value 0xF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timingr_sdadel(I2C_TypeDef *I2Cx, uint32_t data_hold_time) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL_MSK, data_hold_time << I2C_TIMINGR_SDADEL_POSS); +} + +/** + * @brief Get I2C date hold time + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval data_hold_time + * @arg Max Value 0xF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_timingr_sdadel(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL_MSK)>>I2C_TIMINGR_SDADEL_POSS); +} + +/** + * @brief Set I2C SCL high period(master mode) + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param SCL_hperiod + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timingr_sclh(I2C_TypeDef *I2Cx, uint32_t SCL_hperiod) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLH_MSK, SCL_hperiod << I2C_TIMINGR_SCLH_POSS); +} + +/** + * @brief Get I2C SCL high period(master mode) + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval SCL_hperiod + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_timingr_sclh(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH_MSK)>>I2C_TIMINGR_SCLH_POSS); +} + +/** + * @brief Set I2C SCL low period(master mode) + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @param SCL_lperiod + * @arg Max Value 0xFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timingr_scll(I2C_TypeDef *I2Cx, uint32_t SCL_lperiod) +{ + MODIFY_REG(I2Cx->TIMINGR, I2C_TIMINGR_SCLL_MSK, SCL_lperiod << I2C_TIMINGR_SCLL_POSS); +} + +/** + * @brief Get I2C SCL low period(master mode) + * @note This register must be configured when the I2C is disabled(PE = 0) + * @param I2Cx I2C Instance + * @retval SCL_lperiod + * @arg Max Value 0xFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_timingr_scll(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL_MSK)); +} + +/** + * @brief Set I2C TIMEOUTR + * @note These bits can be written only when TEXTEN=0 and TIMEOUTEN=0 except TEXTEN and TIMEOUTEN. + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timeoutr(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->TIMEOUTR, Reg_Value); +} + +/** + * @brief Get I2C TIMEOUTR + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_timeoutr(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->TIMEOUTR)); +} + +/** + * @brief I2C Extended clock timeout Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_timeoutr_texten(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TEXTEN_MSK); +} + +/** + * @brief I2C Extended clock timeout Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_timeoutr_texten(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TEXTEN_MSK); +} + +/** + * @brief Indicate if I2C Extended clock timeout is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_timeoutr_texten(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TEXTEN_MSK) == (I2C_TIMEOUTR_TEXTEN_MSK)); +} + +/** + * @brief Set I2C Bus timeout B + * @note These bits can be written only when TEXTEN = 0 + * @param I2Cx I2C Instance + * @param timeoutb Bus timeout B + * @arg Max Value 0xFFFFFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timeoutr_timeoutb(I2C_TypeDef *I2Cx, uint32_t timeoutb) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB_MSK, timeoutb << I2C_TIMEOUTR_TIMEOUTB_POSS); +} + +/** + * @brief Get I2C Bus timeout B + * @note These bits can be written only when TEXTEN = 0 + * @param I2Cx I2C Instance + * @retval Bus timeout B + * @arg Max Value 0xFFFFFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_timeoutr_timeoutb(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB_MSK)>>I2C_TIMEOUTR_TIMEOUTB_POSS); +} + +/** + * @brief I2C clock timeout Enable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_timeoutr_timeouten(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTEN_MSK); +} + +/** + * @brief I2C clock timeout Disable + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_timeoutr_timeouten(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTEN_MSK); +} + +/** + * @brief Indicate if I2C clock timeout is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_timeoutr_timeouten(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTEN_MSK) == (I2C_TIMEOUTR_TIMEOUTEN_MSK)); +} + +/** + * @brief Set I2C Tidle to decide a timeouta mode + * @note This bit can be written only when TIMOUTEN = 0 + * @param I2Cx I2C Instance + * @param tidle_mode + * @arg @ref MD_I2C_LOW_TIMEOUTA + * @arg @ref MD_I2C_IDLE_TIMEOUTA + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timeoutr_tidle(I2C_TypeDef *I2Cx, uint32_t tidle_mode) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE_MSK, tidle_mode); +} + +/** + * @brief Get I2C Tidle to know a timeouta mode + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_timeoutr_tidle(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE_MSK)>>I2C_TIMEOUTR_TIDLE_POS); +} + +/** + * @brief Set I2C Bus timeout A + * @note These bits can be written only when TIMOUTEN = 0 + * @param I2Cx I2C Instance + * @param timeouta Bus timeout A + * @arg Max Value 0xFFFFFF + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_timeoutr_timeouta(I2C_TypeDef *I2Cx, uint32_t timeouta) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA_MSK, timeouta << I2C_TIMEOUTR_TIMEOUTA_POSS); +} + +/** + * @brief Get I2C Bus timeout A + * @note These bits can be written only when TIMOUTEN = 0 + * @param I2Cx I2C Instance + * @retval Bus timeout A + * @arg Max Value 0xFFFFFF + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_i2c_get_timeoutr_timeouta(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA_MSK)); +} + +/** + * @brief Get I2C STAT + * @note All bits are read-only + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_stat(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->STAT)); +} + +/** + * @brief Get address match code(slave mode) + * @note These bits are updated with the received address when an address match event occurs(ADDR=1). + * @param I2Cx I2C Instance + * @retval 7-bit received address value + */ +__STATIC_INLINE uint32_t md_i2c_get_stat_addcode(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_ADDCODE_MSK)>>I2C_STAT_ADDCODE_POSS); +} + +/** + * @brief Get transfer direction(slave mode) + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_get_stat_dir(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->STAT, I2C_STAT_DIR_MSK)>>I2C_STAT_DIR_POS); +} + +/** + * @brief Indicate if I2C busy flag is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_busy(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_BUSY_MSK) == (I2C_STAT_BUSY_MSK)); +} + +/** + * @brief Indicate if I2C transfer complete reload flag (TCR) is active + * @note This bit is cleared by hardware when PE = 0. + * This flag is only for master mode,or for slave mode when the SBC bit is set + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_tcr(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TCR_MSK) == (I2C_STAT_TCR_MSK)); +} + +/** + * @brief Indicate if I2C transfer complete flag (TC) is active + * @note This bit is cleared by hardware when PE = 0. + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_tc(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TC_MSK) == (I2C_STAT_TC_MSK)); +} + +/** + * @brief Indicate if I2C Rx FIFO level over threshold flag (RXTH) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_rxth(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_RXTH_MSK) == (I2C_STAT_RXTH_MSK)); +} + +/** + * @brief Indicate if I2C Rx buffer underflow flag (RXUD) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_rxud(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_RXUD_MSK) == (I2C_STAT_RXUD_MSK)); +} + +/** + * @brief Indicate if I2C Rx buffer overflow flag (RXOV) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_rxov(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_RXOV_MSK) == (I2C_STAT_RXOV_MSK)); +} + +/** + * @brief Indicate if I2C Rx buffer full flag (RXF) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_rxf(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_RXF_MSK) == (I2C_STAT_RXF_MSK)); +} + +/** + * @brief Indicate if I2C Rx buffer empty flag (RXE) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_rxe(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_RXE_MSK) == (I2C_STAT_RXE_MSK)); +} + +/** + * @brief Indicate if I2C Tx FIFO level over threshold flag (TXTH) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_txth(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TXTH_MSK) == (I2C_STAT_TXTH_MSK)); +} + +/** + * @brief Indicate if I2C Tx buffer underflow flag (TXUD) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_is_active_stat_txud(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TXUD_MSK) == (I2C_STAT_TXUD_MSK)); +} + +/** + * @brief Indicate if I2C Tx buffer overflow flag (TXOV) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_txov(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TXOV_MSK) == (I2C_STAT_TXOV_MSK)); +} + +/** + * @brief Indicate if I2C Tx buffer full flag (TXF) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_txf(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TXF_MSK) == (I2C_STAT_TXF_MSK)); +} + +/** + * @brief Indicate if I2C Tx buffer empty flag (TXE) is active + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_stat_txe(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->STAT, I2C_STAT_TXE_MSK) == (I2C_STAT_TXE_MSK)); +} + +/** + * @brief Set I2C FCON + * @note FIFO trigger threshold must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_i2c_set_fcon(I2C_TypeDef *I2Cx, uint32_t Reg_Value) +{ + WRITE_REG(I2Cx->FCON, Reg_Value); +} + +/** + * @brief Get I2C FCON + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_fcon(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->FCON)); +} + +/** + * @brief Set RXFIFO trigger threshold + * @note Receive FIFO trigger threshold must be configured when the I2C is disabled (PE = 0). + * @param I2Cx I2C Instance + * @param rxfifo_trigger_threshold This parameter can be one of the following values: + * @arg @ref MD_I2C_RXFIFO_THRESHOLD_RX1 + * @arg @ref MD_I2C_RXFIFO_THRESHOLD_RX4 + * @arg @ref MD_I2C_RXFIFO_THRESHOLD_RX8 + * @arg @ref MD_I2C_RXFIFO_THRESHOLD_RX14 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_fcon_rxfth(I2C_TypeDef *I2Cx, uint32_t rxfifo_trigger_threshold) +{ + MODIFY_REG(I2Cx->FCON, I2C_FCON_RXFTH_MSK, rxfifo_trigger_threshold); +} + +/** + * @brief Get RXFIFO trigger threshold + * @note None + * @param I2Cx I2C Instance + * @retval The retval can be 0 to 3 + */ +__STATIC_INLINE uint32_t md_i2c_get_fcon_rxfth(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->FCON, I2C_FCON_RXFTH_MSK)>>I2C_FCON_RXFTH_POSS); +} + +/** + * @brief Set I2C RXFIFO reset + * @note None + * @param I2Cx I2C Instance + * @arg @ref MD_I2C_RXFIFO_RESET + * @retval None + */ +__STATIC_INLINE void md_i2c_set_fcon_rxfrst(I2C_TypeDef *I2Cx, uint32_t reset) +{ + MODIFY_REG(I2Cx->FCON, I2C_FCON_RXFRST_MSK, reset); +} + +/** + * @brief Get I2C RXFIFO level + * @note None + * @param I2Cx I2C Instance + * @retval It's from 0 to 16 + */ +__STATIC_INLINE uint32_t md_i2c_get_rxfifo_level(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->FCON, I2C_FCON_RXFLV_MSK)>>I2C_FCON_RXFLV_POSS); +} + +/** + * @brief Set TXFIFO trigger threshold + * @param I2Cx I2C Instance + * @param txfifo_trigger_threshold This parameter can be one of the following values: + * @arg @ref MD_I2C_TXFIFO_THRESHOLD_TX0 + * @arg @ref MD_I2C_TXFIFO_THRESHOLD_TX2 + * @arg @ref MD_I2C_TXFIFO_THRESHOLD_TX4 + * @arg @ref MD_I2C_TXFIFO_THRESHOLD_TX8 + * @retval None + */ +__STATIC_INLINE void md_i2c_set_fcon_txfth(I2C_TypeDef *I2Cx, uint32_t txfifo_trigger_threshold) +{ + MODIFY_REG(I2Cx->FCON, I2C_FCON_TXFTH_MSK, txfifo_trigger_threshold); +} + +/** + * @brief Get TXFIFO trigger threshold + * @param I2Cx I2C Instance + * @retval It's from 0 to 3 + */ +__STATIC_INLINE uint32_t md_i2c_get_txfifo_trigger_threshold(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->FCON, I2C_FCON_TXFTH_MSK)>>I2C_FCON_TXFTH_POSS); +} + +/** + * @brief I2C TXFIFO reset + * @note None + * @param I2Cx I2C Instance + * @arg @ref MD_I2C_TXFIFO_RESET + * @retval None + */ +__STATIC_INLINE void md_i2c_set_fcon_txfrst(I2C_TypeDef *I2Cx, uint32_t reset) +{ + MODIFY_REG(I2Cx->FCON, I2C_FCON_TXFRST_MSK, reset); +} + +/** + * @brief Get TXFIFO level + * @note None + * @param I2Cx I2C Instance + * @retval It's from 0 to 16 + */ +__STATIC_INLINE uint32_t md_i2c_get_txfifo_level(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->FCON, I2C_FCON_TXFLV_MSK)); +} + +/** + * @brief Get packet error checking register + * @note None + * @param I2Cx I2C Instance + * @retval 8-bit pec value + */ +__STATIC_INLINE uint32_t md_i2c_get_pecr_pec(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->PECR, I2C_PECR_PEC_MSK)); +} + +/** + * @brief 8-bit receive data + * @note None + * @param I2Cx I2C Instance + * @retval 8-bit receive data + */ +__STATIC_INLINE uint32_t md_i2c_recv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RXDATA, I2C_RXDATA_RXDATA_MSK)); +} + +/** + * @brief 8-bit transmit data + * @note These bits can be written only when TXE = 1. + * @param I2Cx I2C Instance + * @param txdata Transmit Data + * @arg Max value 0xFF + * @arg Min value 0 + * @retval None + */ +__STATIC_INLINE void md_i2c_send(I2C_TypeDef *I2Cx, uint32_t txdata) +{ + MODIFY_REG(I2Cx->TXDATA, I2C_TXDATA_TXDATA_MSK, txdata); +} + +/** + * @brief Set I2C IER + * @note None + * @param I2Cx I2C Instance + * @param ier + * @retval None + */ +__STATIC_INLINE void md_i2c_set_ier(I2C_TypeDef *I2Cx, uint32_t ier) +{ + WRITE_REG(I2Cx->IER, ier); +} + +/** + * @brief Enable SMBus alert interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_alertie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_ALERTIE_MSK); +} + +/** + * @brief Enable timeout interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_toutie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TOUTIE_MSK); +} + +/** + * @brief Enable PEC error interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_peceie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_PECEIE_MSK); +} + +/** + * @brief Enable arbitration loss interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_arloie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_ARLOIE_MSK); +} + +/** + * @brief Enable bus error interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_berrie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_BERRIE_MSK); +} + +/** + * @brief Enable stop detection interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_stopie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_STOPIE_MSK); +} + +/** + * @brief Enable NACK reception interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_nackie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_NACKIE_MSK); +} + +/** + * @brief Enable address matched interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_addrie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_ADDRIE_MSK); +} + +/** + * @brief Enable transfer complete and reload interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_tcrie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TCRIE_MSK); +} + +/** + * @brief Enable transfer complete interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_tcie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TCIE_MSK); +} + +/** + * @brief Enable receive buffer over threshold interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_rxthie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_RXTHIE_MSK); +} + +/** + * @brief Enable receive buffer underrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_rxudie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_RXUDIE_MSK); +} + +/** + * @brief Enable receive buffer ovrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_rxovie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_RXOVIE_MSK); +} + +/** + * @brief Enable receive buffer full interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_rxfie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_RXFIE_MSK); +} + +/** + * @brief Enable transmit buffer under threshold interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_txthie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TXTHIE_MSK); +} + +/** + * @brief Enable transmit buffer underrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_txudie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TXUDIE_MSK); +} + +/** + * @brief Enable transmit buffer ovrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_txovie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TXOVIE_MSK); +} + +/** + * @brief Enable transmit buffer empty interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_enable_ier_txeie(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->IER, I2C_IER_TXEIE_MSK); +} + +/** + * @brief Set I2C IDR + * @note None + * @param I2Cx I2C Instance + * @param ier + * @retval None + */ +__STATIC_INLINE void md_i2c_set_idr(I2C_TypeDef *I2Cx, uint32_t idr) +{ + WRITE_REG(I2Cx->IDR, idr); +} + +/** + * @brief Disable SMBus alert interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_alertid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_ALERTID_MSK); +} + +/** + * @brief Disable timeout interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_toutid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_TOUTID_MSK); +} + +/** + * @brief Disable PEC error interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_peceid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_PECEID_MSK); +} + +/** + * @brief Disable arbitration loss interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_arloid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_ARLOID_MSK); +} + +/** + * @brief Disable bus error interrupt. + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_berrid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_BERRID_MSK); +} + +/** + * @brief Disable stop detection interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_stopid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_STOPID_MSK); +} + +/** + * @brief Disable NACK reception interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_nackid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_NACKID_MSK); +} + +/** + * @brief Disable address matched interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_addrid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_ADDRID_MSK); +} + +/** + * @brief Disable transfer complete and reload interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_tcrid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_TCRID_MSK); +} + +/** + * @brief Disable transfer complete interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_tcid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_TCID_MSK); +} + +/** + * @brief Disable receive buffer over threshold interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_rxthid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_RXTHID_MSK); +} + +/** + * @brief Disable receive buffer underrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_rxudid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_RXUDID_MSK); +} + +/** + * @brief Disable receive buffer ovrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_rxovid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_RXOVID_MSK); +} + +/** + * @brief Disable receive buffer full interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_rxfid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_RXFID_MSK); +} + +/** + * @brief Disable transmit buffer under threshold interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_txthid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_TXTHID_MSK); +} + +/** + * @brief Disable transmit buffer underrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_txudid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_TXUDID_MSK); +} + +/** + * @brief Disable transmit buffer ovrun interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_txovid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_TXOVID_MSK); +} + +/** + * @brief Disable transmit buffer empty interrupt + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_disable_idr_txeid(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->IDR, I2C_IDR_TXEID_MSK); +} + +/** + * @brief Get I2C IVS + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_ivs(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->IVS)); +} + +/** + * @brief Check if SMBus alert interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_alertiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_ALERTIV_MSK) == (I2C_IVS_ALERTIV_MSK)); +} + +/** + * @brief Check if timeout interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_toutiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TOUTIV_MSK) == (I2C_IVS_TOUTIV_MSK)); +} + +/** + * @brief Check if PEC error interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_peceiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_PECEIV_MSK) == (I2C_IVS_PECEIV_MSK)); +} + +/** + * @brief Check if arbitration loss interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_arloiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_ARLOIV_MSK) == (I2C_IVS_ARLOIV_MSK)); +} + +/** + * @brief Check if bus error interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_berriv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_BERRIV_MSK) == (I2C_IVS_BERRIV_MSK)); +} + +/** + * @brief Check if stop detection interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_stopiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_STOPIV_MSK) == (I2C_IVS_STOPIV_MSK)); +} + +/** + * @brief Check if NACK reception interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_nackiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_NACKIV_MSK) == (I2C_IVS_NACKIV_MSK)); +} + +/** + * @brief Check if address matched interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_addriv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_ADDRIV_MSK) == (I2C_IVS_ADDRIV_MSK)); +} + +/** + * @brief Check if transfer complete and reload interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_tcriv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TCRIV_MSK) == (I2C_IVS_TCRIV_MSK)); +} + +/** + * @brief Check if transfer complete interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_tciv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TCIV_MSK) == (I2C_IVS_TCIV_MSK)); +} + +/** + * @brief Check if receive buffer over threshold interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_rxthiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_RXTHIV_MSK) == (I2C_IVS_RXTHIV_MSK)); +} + +/** + * @brief Check if receive buffer underrun interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_rxudiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_RXUDIV_MSK) == (I2C_IVS_RXUDIV_MSK)); +} + +/** + * @brief Check if receive buffer ovrun interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_rxoviv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_RXOVIV_MSK) == (I2C_IVS_RXOVIV_MSK)); +} + +/** + * @brief Check if receive buffer full interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_rxfiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_RXFIV_MSK) == (I2C_IVS_RXFIV_MSK)); +} + +/** + * @brief Check if transmit buffer under threshold interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_txthiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TXTHIV_MSK) == (I2C_IVS_TXTHIV_MSK)); +} + +/** + * @brief Check if transmit buffer underrun interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_txudiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TXUDIV_MSK) == (I2C_IVS_TXUDIV_MSK)); +} + +/** + * @brief Check if transmit buffer ovrun interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_txoviv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TXOVIV_MSK) == (I2C_IVS_TXOVIV_MSK)); +} + +/** + * @brief Check if transmit buffer empty interrupt is enabled + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_enabled_ivs_txeiv(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IVS, I2C_IVS_TXEIV_MSK) == (I2C_IVS_TXEIV_MSK)); +} + +/** + * @brief Get I2C RIF + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_rif(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->RIF)); +} + +/** + * @brief Get SMBus alert raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_alertri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_ALERTRI_MSK) == (I2C_RIF_ALERTRI_MSK)); +} + +/** + * @brief Get timeout raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_toutri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TOUTRI_MSK) == (I2C_RIF_TOUTRI_MSK)); +} + +/** + * @brief Get PEC error raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_peceri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_PECERI_MSK) == (I2C_RIF_PECERI_MSK)); +} + +/** + * @brief Get arbitration loss raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_arlori(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_ARLORI_MSK) == (I2C_RIF_ARLORI_MSK)); +} + +/** + * @brief Get bus error raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_berrri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_BERRRI_MSK) == (I2C_RIF_BERRRI_MSK)); +} + +/** + * @brief Get stop detection raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_stopri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_STOPRI_MSK) == (I2C_RIF_STOPRI_MSK)); +} + +/** + * @brief Get NACK reception raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_nackri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_NACKRI_MSK) == (I2C_RIF_NACKRI_MSK)); +} + +/** + * @brief Get address matched raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_addrri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_ADDRRI_MSK) == (I2C_RIF_ADDRRI_MSK)); +} + +/** + * @brief Get transfer complete and reload raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_tcrri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TCRRI_MSK) == (I2C_RIF_TCRRI_MSK)); +} + +/** + * @brief Get transfer complete raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_tcri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TCRI_MSK) == (I2C_RIF_TCRI_MSK)); +} + +/** + * @brief Get receive buffer over threshold raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_rxthri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_RXTHRI_MSK) == (I2C_RIF_RXTHRI_MSK)); +} + +/** + * @brief Get receive buffer underrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_rxudri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_RXUDRI_MSK) == (I2C_RIF_RXUDRI_MSK)); +} + +/** + * @brief Get receive buffer ovrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_rxovri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_RXOVRI_MSK) == (I2C_RIF_RXOVRI_MSK)); +} + +/** + * @brief Get receive buffer full raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_rxfri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_RXFRI_MSK) == (I2C_RIF_RXFRI_MSK)); +} + +/** + * @brief Get transmit buffer under threshold raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_txthri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TXTHRI_MSK) == (I2C_RIF_TXTHRI_MSK)); +} + +/** + * @brief Get transmit buffer underrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_txudri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TXUDRI_MSK) == (I2C_RIF_TXUDRI_MSK)); +} + +/** + * @brief Get transmit buffer ovrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_txovri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TXOVRI_MSK) == (I2C_RIF_TXOVRI_MSK)); +} + +/** + * @brief Get transmit buffer empty raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_rif_txeri(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->RIF, I2C_RIF_TXERI_MSK) == (I2C_RIF_TXERI_MSK)); +} + +/** + * @brief Set I2C ICR + * @note None + * @param I2Cx I2C Instance + * @param icr + * @retval None + */ +__STATIC_INLINE void md_i2c_set_icr(I2C_TypeDef *I2Cx, uint32_t icr) +{ + WRITE_REG(I2Cx->ICR, icr); +} + +/** + * @brief Clear SMBus alert raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_alertic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ALERTIC_MSK); +} + +/** + * @brief Clear timeout raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_toutic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TOUTIC_MSK); +} + +/** + * @brief Clear PEC error raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_peceic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_PECEIC_MSK); +} + +/** + * @brief Clear arbitration loss raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_arloic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ARLOIC_MSK); +} + +/** + * @brief Clear bus error raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_berric(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_BERRIC_MSK); +} + +/** + * @brief Clear stop detection raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_stopic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_STOPIC_MSK); +} + +/** + * @brief Clear NACK reception raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_nackic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_NACKIC_MSK); +} + +/** + * @brief Clear address matched raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_addric(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ADDRIC_MSK); +} + +/** + * @brief Clear transfer complete and reload raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_tcric(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TCRIC_MSK); +} + +/** + * @brief Clear transfer complete raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_tcic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TCIC_MSK); +} + +/** + * @brief Clear receive buffer over threshold raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_rxthic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_RXTHIC_MSK); +} + +/** + * @brief Clear receive buffer underrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_rxudic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_RXUDIC_MSK); +} + +/** + * @brief Clear receive buffer ovrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_rxovic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_RXOVIC_MSK); +} + +/** + * @brief Clear receive buffer full raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_rxfic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_RXFIC_MSK); +} + +/** + * @brief Clear transmit buffer under threshold raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_txthic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TXTHIC_MSK); +} + +/** + * @brief Clear transmit buffer underrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_txudic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TXUDIC_MSK); +} + +/** + * @brief Clear transmit buffer ovrun raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_txovic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TXOVIC_MSK); +} + +/** + * @brief Clear transmit buffer empty raw interrupt flag + * @note None + * @param I2Cx I2C Instance + * @retval None + */ +__STATIC_INLINE void md_i2c_clear_icr_txeic(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TXEIC_MSK); +} + +/** + * @brief Get I2C IFM + * @note None + * @param I2Cx I2C Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_i2c_get_ifm(I2C_TypeDef *I2Cx) +{ + return (uint32_t) (READ_REG(I2Cx->IFM)); +} + +/** + * @brief Get SMBus alert interrupt flag massked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_alertfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_ALERTFM_MSK) == (I2C_IFM_ALERTFM_MSK)); +} + +/** + * @brief Get timeout interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_toutfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TOUTFM_MSK) == (I2C_IFM_TOUTFM_MSK)); +} + +/** + * @brief Get PEC error interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_pecefm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_PECEFM_MSK) == (I2C_IFM_PECEFM_MSK)); +} + +/** + * @brief Get arbitration loss interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_arlofm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_ARLOFM_MSK) == (I2C_IFM_ARLOFM_MSK)); +} + +/** + * @brief Get bus error interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_berrfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_BERRFM_MSK) == (I2C_IFM_BERRFM_MSK)); +} + +/** + * @brief Get stop detection interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_stopfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_STOPFM_MSK) == (I2C_IFM_STOPFM_MSK)); +} + +/** + * @brief Get NACK reception interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_nackfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_NACKFM_MSK) == (I2C_IFM_NACKFM_MSK)); +} + +/** + * @brief Get address matched interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_addrfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_ADDRFM_MSK) == (I2C_IFM_ADDRFM_MSK)); +} + +/** + * @brief Get transfer complete and reload interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_tcrfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TCRFM_MSK) == (I2C_IFM_TCRFM_MSK)); +} + +/** + * @brief Get transfer complete interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_tcfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TCFM_MSK) == (I2C_IFM_TCFM_MSK)); +} + +/** + * @brief Get receive buffer over threshold interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_rxthfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_RXTHFM_MSK) == (I2C_IFM_RXTHFM_MSK)); +} + +/** + * @brief Get receive buffer underrun interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_rxudfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_RXUDFM_MSK) == (I2C_IFM_RXUDFM_MSK)); +} + +/** + * @brief Get receive buffer ovrun interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_rxovfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_RXOVFM_MSK) == (I2C_IFM_RXOVFM_MSK)); +} + +/** + * @brief Get receive buffer full interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_rxffm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_RXFFM_MSK) == (I2C_IFM_RXFFM_MSK)); +} + +/** + * @brief Get transmit buffer under threshold interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_txthfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TXTHFM_MSK) == (I2C_IFM_TXTHFM_MSK)); +} + +/** + * @brief Get transmit buffer underrun interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_txudfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TXUDFM_MSK) == (I2C_IFM_TXUDFM_MSK)); +} + +/** + * @brief Get transmit buffer ovrun interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_txovfm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TXOVFM_MSK) == (I2C_IFM_TXOVFM_MSK)); +} + +/** + * @brief Get transmit buffer empty interrupt flag masked status + * @note None + * @param I2Cx I2C Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_i2c_is_active_ifm_txefm(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->IFM, I2C_IFM_TXEFM_MSK) == (I2C_IFM_TXEFM_MSK)); +} + +/** + * @} MD_I2C_Public_Macros + */ + + + + + + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_I2C_Public_Functions I2C Public Functions + * @{ + */ + +/** @defgroup MD_I2C_PF_Basic_Configuration I2C Configuration + * @{ + */ + +//ErrorStatus md_i2c_deinit(I2C_TypeDef *I2Cx); +ErrorStatus md_i2c_init(I2C_TypeDef *I2Cx, md_i2c_inittypedef *I2C_InitStruct); +void md_i2c_struct_init(md_i2c_inittypedef *I2C_InitStruct); +void md_i2c_master_send(I2C_TypeDef *I2Cx, uint8_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t *txbuf); +void md_i2c_master_rece(I2C_TypeDef *I2Cx, uint8_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t *rxbuf); +void md_i2c_slave_send(I2C_TypeDef *I2Cx, uint8_t Num, uint8_t *txbuf); +void md_i2c_slave_rece(I2C_TypeDef *I2Cx, uint8_t Num, uint8_t *rxbuf); + +/** + * @} MD_I2C_PF_Init + */ + +/** + * @} MD_I2C_Public_Functions + */ + +#endif + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup MD_I2C_Private_Macro I2C Private Macros + * @{ + */ +#define IS_MD_I2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__ == I2C1) \ + || (__INSTANCE__ == I2C2) \ + || (__INSTANCE__ == I2C3)) + +#define IS_MD_I2C_TIMING(__VALUE__) ((__VALUE__ == CLK10kHz8M) \ + || (__VALUE__ == CLK100kHz8M)) \ + || (__VALUE__ == CLK400kHz8M)) \ + || (__VALUE__ == CLK500kHz8M)) \ + || (__VALUE__ == CLK10kHz16M)) \ + || (__VALUE__ == CLK100kHz16M)) \ + || (__VALUE__ == CLK400kHz16M)) \ + || (__VALUE__ == CLK1000kHz16M)) \ + || (__VALUE__ == CLK10kHz48M)) \ + || (__VALUE__ == CLK100kHz48M)) \ + || (__VALUE__ == CLK400kHz48M)) \ + || (__VALUE__ == CLK1000kHz48M)) + +#define IS_MD_I2C_ADDRSIZE(__VALUE__) ((__VALUE__ == MD_I2C_ADDRESSINGMODE_7BIT) \ + || (__VALUE__ == MD_I2C_ADDRESSINGMODE_10BIT)) + +#define IS_MD_I2C_ADDRESS1(__VALUE__) (__VALUE__ <= 0x000003FFU) +#define IS_MD_I2C_ADDRESS2(__VALUE__) (__VALUE__ <= (uint16_t)0x00FFU) + +#define IS_MD_I2C_DUALADDRESSMODE(__VALUE__) ((__VALUE__ == MD_I2C_DUALADDRESS_DISABLE) \ + || (__VALUE__ == MD_I2C_DUALADDRESS_ENABLE)) +#define IS_MD_I2C_ADDRESS2MASKS(__VALUE__) ((__VALUE__ == MD_I2C_ADDR2_NOMASK) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK01) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK02) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK03) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK04) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK05) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK06) \ + || (__VALUE__ == MD_I2C_ADDR2_MASK07)) + +/** + * @} MD_I2C_Private_Macro + */ + +/** + * @} I2C + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rcu.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rcu.h new file mode 100644 index 0000000000000000000000000000000000000000..1b9b6ff09b6907433f5be84ee04700f7acf1310e --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rcu.h @@ -0,0 +1,5804 @@ +/** + ****************************************************************************** + * @file md_RCU.h + * @brief ES32F0271 RCU HEAD File. + * + * @version V1.00.02 + * @date 30/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_RCU_H__ +#define __MD_RCU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include +#include "es32f0271.h" +#include "reg_rcu.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (RCU) + +/** @defgroup RCU RCU + * @brief RCU micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/** @defgroup MD_RCU_Private_Constants RCU Private Constants + * @{ + */ + +#define __HOSC (8000000UL) +#define __HRC (4000000UL) +#define __LOSC ( 32768UL) +#define __LRC ( 32000UL) +#define __PLL1 (48000000UL) + +/** + * @} MD_RCU_Private_Constants + */ +/* Private macros -------------------------------------------------------------*/ +/* Public types ---------------------------------------------------------------*/ +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_RCU_Public_Types RCU Public Init Type + * @{ + */ + +typedef struct +{ + uint32_t Mpre; /*! MCO clock prescaler */ + uint32_t Msw; /*! MCO clock output */ + uint32_t PllMul; /*! PLL multiplication factor */ + uint32_t PllSrc; /*! PLL clock source */ + uint32_t HoscDiv; /*! PLL base clock 4MHz HOSC clock prescale */ + uint32_t Ppre; /*! APB clock prescaler */ + uint32_t Hpre; /*! AHB clock prescaler */ + uint32_t Sw; /*! system clock */ + uint8_t SysClock;/*! system clock enable */ +} md_rcu_init_typedef; + +/** + * @} MD_RCU_Public_Types + */ +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_RCU_Public_Constants RCU Public Constants + * @{ + */ + +/** @defgroup MD_RCU_SWRDY_FLAG System clock switch ready flag + * @{ + */ +#define MD_RCU_SWRDY_NOT_READY (0x00000000UL) /** @brief System clock not ready */ +#define MD_RCU_SWRDY_READY (0x00000001UL) /** @brief System clock ready */ +/** + * @} MD_RCU_SWRDY_FLAG + */ + +/** @defgroup MD_RCU_CSSFLG_FLAG Clock Security System flag + * @{ + */ +#define MD_RCU_CSSFLG_NO_FAIL (0x00000000UL) /** @brief No clock security event caused by HOSC clock failure */ +#define MD_RCU_CSSFLG_FAIL (0x00000001UL) /** @brief Clock security event caused by HOSC clock failure */ +/** + * @} MD_RCU_CSSFLG_FLAG + */ + +/** @defgroup MD_RCU_PLL1_FLAG PLL1 clock ready flag + * @{ + */ +#define MD_RCU_PLL1_NOT_READY (0x00000000UL) /** @brief PLL1 not ready */ +#define MD_RCU_PLL1_READY (0x00000001UL) /** @brief PLL1 ready */ +/** + * @} MD_RCU_PLL1_FLAG + */ + +/** @defgroup MD_RCU_PLL0_FLAG PLL0 clock ready flag + * @{ + */ +#define MD_RCU_PLL0_NOT_READY (0x00000000UL) /** @brief PLL0 not ready */ +#define MD_RCU_PLL0_READY (0x00000001UL) /** @brief PLL0 ready */ +/** + * @} MD_RCU_PLL0_FLAG + */ + +/** @defgroup MD_RCU_LOSCRDY_FLAG LOSC clock ready flag + * @{ + */ +#define MD_RCU_LOSCRDY_NOT_READY (0x00000000UL) /** @brief LOSC oscillator not ready */ +#define MD_RCU_LOSCRDY_READY (0x00000001UL) /** @brief LOSC oscillator ready */ +/** + * @} MD_RCU_LOSCRDY_FLAG + */ + +/** @defgroup MD_RCU_LRCRDY_FLAG LRC clock ready flag + * @{ + */ +#define MD_RCU_LRCRDY_NOT_READY (0x00000000UL) /** @brief LRC oscillator not ready */ +#define MD_RCU_LRCRDY_READY (0x00000001UL) /** @brief LRC oscillator ready */ +/** + * @} MD_RCU_LRCRDY_FLAG + */ + +/** @defgroup MD_RCU_HOSCRDY_FLAG HOSC clock ready flag + * @{ + */ +#define MD_RCU_HOSCRDY_NOT_READY (0x00000000UL) /** @brief HOSC oscillator not ready */ +#define MD_RCU_HOSCRDY_READY (0x00000001UL) /** @brief HOSC oscillator ready */ +/** + * @} MD_RCU_HOSCRDY_FLAG + */ + +/** @defgroup MD_RCU_HRCRDY_FLAG HRC clock ready flag + * @{ + */ +#define MD_RCU_HRCRDY_NOT_READY (0x00000000UL) /** @brief HRC oscillator not ready */ +#define MD_RCU_HRCRDY_READY (0x00000001UL) /** @brief HRC oscillator ready */ +/** + * @} MD_RCU_HRCRDY_FLAG + */ + +/** @defgroup MD_RCU_MCO_OUTPUT Microcontroller clock output select + * @{ + */ +#define MD_RCU_MCO_DISABLE (0x00000000UL) /** @brief MCO output disabled, no clock on MCO */ +#define MD_RCU_MCO_LRC (0x00000001UL) /** @brief Internal low speed (LRC) oscillator clock selected */ +#define MD_RCU_MCO_LOSC (0x00000002UL) /** @brief External low speed (LOSC) oscillator clock selected */ +#define MD_RCU_MCO_HRC (0x00000003UL) /** @brief Internal high speed (HRC) oscillator clock selected */ +#define MD_RCU_MCO_HOSC (0x00000004UL) /** @brief External high speed (HOSC) oscillator clock selected */ +#define MD_RCU_MCO_PLL0 (0x00000005UL) /** @brief PLL0 clock selected */ +#define MD_RCU_MCO_PLL1 (0x00000006UL) /** @brief PLL1 clock selected */ +#define MD_RCU_MCO_SYSCLK (0x00000007UL) /** @brief System clock selected(SYSCLK) */ +#define MD_RCU_MCO_HCLK (0x00000008UL) /** @brief AHB clock selected(HCLK) */ +#define MD_RCU_MCO_PCLK (0x00000009UL) /** @brief APB clock selected(PCLK) */ +/** + * @} MD_RCU_MCO_OUTPUT + */ + +/** @defgroup MD_RCU_PLL_SRC PLL0/1 reference clock source + * @{ + */ +#define MD_RCU_PLL_SRC_HRC (0x00000000UL) /** @brief HRC selected as PLL0/1 reference clock */ +#define MD_RCU_PLL_SRC_HOSCDIV (0x00000001UL) /** @brief HOSC/HOSCDIV selected as PLL reference clock */ +/** + * @} MD_RCU_PLL_SRC + */ + +/** @defgroup MD_RCU_APB_CLK_DIV APB clock prescaler(PCLK) + * @{ + */ +#define MD_RCU_PPRE_HCLK_DIV_1 (0x00000000UL) /** @brief HCLK not divided */ +#define MD_RCU_PPRE_HCLK_DIV_2 (0x00000004UL) /** @brief HCLK divided by 2 */ +#define MD_RCU_PPRE_HCLK_DIV_4 (0x00000005UL) /** @brief HCLK divided by 4 */ +#define MD_RCU_PPRE_HCLK_DIV_8 (0x00000006UL) /** @brief HCLK divided by 8 */ +#define MD_RCU_PPRE_HCLK_DIV_16 (0x00000007UL) /** @brief HCLK divided by 16 */ +/** + * @} MD_RCU_APB_CLK_DIV + */ + +/** @defgroup MD_RCU_AHB_CLK_DIV AHB clock prescaler(HCLK) + * @{ + */ +#define MD_RCU_HPRE_SYSCLK_DIV_1 (0x00000000UL) /** @brief SYSCLK not divided */ +#define MD_RCU_HPRE_SYSCLK_DIV_2 (0x00000008UL) /** @brief SYSCLK divided by 2 */ +#define MD_RCU_HPRE_SYSCLK_DIV_4 (0x00000009UL) /** @brief SYSCLK divided by 4 */ +#define MD_RCU_HPRE_SYSCLK_DIV_8 (0x0000000AUL) /** @brief SYSCLK divided by 8 */ +#define MD_RCU_HPRE_SYSCLK_DIV_16 (0x0000000BUL) /** @brief SYSCLK divided by 16 */ +/** + * @} MD_RCU_AHB_CLK_DIV + */ + +/** @defgroup MD_RCU_SYS_CLK_SW System clock switch(SYSCLK) + * @{ + */ +#define MD_RCU_SYSCLK_HRC (0x00000000UL) /** @brief HRC selected as system clock */ +#define MD_RCU_SYSCLK_HOSC (0x00000001UL) /** @brief HOSC selected as system clock */ +#define MD_RCU_SYSCLK_LRC (0x00000002UL) /** @brief LRC selected as system clock */ +#define MD_RCU_SYSCLK_LOSC (0x00000003UL) /** @brief LOSC selected as system clock */ +#define MD_RCU_SYSCLK_PLL0 (0x00000004UL) /** @brief PLL0 selected as system clock */ +/** + * @} MD_RCU_SYS_CLK_SW + */ + +/** @defgroup MD_RCU_PSCK_I2S2CKSL SPI2/I2S2 External Clock Source Select + * @{ + */ +#define MD_RCU_PSCK_I2S2CKSL_DISABLE (0x00000000UL) /** @brief Disable External Clock (default value) */ +#define MD_RCU_PSCK_I2S2CKSL_I2SCLK1 (0x00000001UL) +#define MD_RCU_PSCK_I2S2CKSL_I2SCLK2 (0x00000002UL) +/** + * @} MD_RCU_PSCK_I2S2CKSL + */ + +/** @defgroup MD_RCU_PSCK_I2S1CKSL SPI1/I2S1 External Clock Source Select + * @{ + */ +#define MD_RCU_PSCK_I2S1CKSL_DISABLE (0x00000000UL) /** @brief Disable External Clock (default value) */ +#define MD_RCU_PSCK_I2S1CKSL_I2SCLK1 (0x00000001UL) +#define MD_RCU_PSCK_I2S1CKSL_I2SCLK2 (0x00000002UL) +/** + * @} MD_RCU_PSCK_I2S1CKSL + */ + + +/** + * @} MD_RCU_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_RCU_Public_Macros RCU Public Macros + * @{ + */ + +/** + * @brief Get System clock switch ready flag + * @note This bit is set by hardware to indicate that the system clock change is stable. + * When the CKCFG bit was set and finish configuartion process. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_SWRDY_NOT_READY + * @arg @ref MD_RCU_SWRDY_READY + */ +__STATIC_INLINE uint32_t md_rcu_get_con_swrdy(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_SWRDY_MSK)>>RCU_CON_SWRDY_POS); +} +/** + * @brief Get Clock Security System flag + * @note This bit is reset by software by writing the CSSON bit. + * It is set by hardware in case of HOSC clock failure. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_CSSFLG_NO_FAIL + * @arg @ref MD_RCU_CSSFLG_FAIL + */ +__STATIC_INLINE uint32_t md_rcu_get_con_cssflg(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_CSSFLG_MSK)>>RCU_CON_CSSFLG_POS); +} +/** + * @brief Get PLL1 clock ready flag + * @note This bit is set by hardware to indicate that the PLL1 oscillator is stable. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_PLL1_NOT_READY + * @arg @ref MD_RCU_PLL1_READY + */ +__STATIC_INLINE uint32_t md_rcu_get_con_pll1rdy(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_PLL1RDY_MSK)>>RCU_CON_PLL1RDY_POS); +} +/** + * @brief Get PLL0 clock ready flag + * @note This bit is set by hardware to indicate that the PLL0 oscillator is stable. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_PLL0_NOT_READY + * @arg @ref MD_RCU_PLL0_READY + */ +__STATIC_INLINE uint32_t md_rcu_get_con_pll0rdy(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_PLL0RDY_MSK)>>RCU_CON_PLL0RDY_POS); +} +/** + * @brief Get LOSCRDY clock ready flag + * @note This bit is set by hardware to indicate that the LOSC oscillator is stable. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_LOSCRDY_NOT_READY + * @arg @ref MD_RCU_LOSCRDY_READY + */ +__STATIC_INLINE uint32_t md_rcu_get_con_loscrdy(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_LOSCRDY_MSK)>>RCU_CON_LOSCRDY_POS); +} +/** + * @brief Get LRCRDY clock ready flag + * @note This bit is set by hardware to indicate that the LRC oscillator is stable. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_LRCRDY_NOT_READY + * @arg @ref MD_RCU_LRCRDY_READY + */ +__STATIC_INLINE uint32_t md_rcu_get_con_lrcrdy(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_LRCRDY_MSK)>>RCU_CON_LRCRDY_POS); +} +/** + * @brief Get HOSCRDY clock ready flag + * @note This bit is set by hardware to indicate that the HOSC oscillator is stable. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_HOSCRDY_NOT_READY + * @arg @ref MD_RCU_HOSCRDY_READY + */ +__STATIC_INLINE uint32_t md_rcu_get_con_hoscrdy(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_HOSCRDY_MSK)>>RCU_CON_HOSCRDY_POS); +} +/** + * @brief Get HRCRDY clock ready flag + * @note This bit is set by hardware to indicate that the HRC oscillator is stable. + * @param rcu RCU Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RCU_HRCRDY_NOT_READY + * @arg @ref MD_RCU_HRCRDY_READY + */ +__STATIC_INLINE uint32_t md_rcu_get_con_hrcrdy(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_HRCRDY_MSK)>>RCU_CON_HRCRDY_POS); +} +/** + * @brief Clock security system enable(CSS) + * @note Set and cleared by software to enable the clock security system. + * When CSSON is set, the clock detector is enabled by hardware when the HOSC oscillator is ready, + * and disabled by hardware if a HOSC clock failure is detected. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_con_csson(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_CSSON_MSK); +} +/** + * @brief Clock security system disable(CSS) + * @note Set and cleared by software to enable the clock security system. + * When CSSON is set, the clock detector is enabled by hardware when the HOSC oscillator is ready, + * and disabled by hardware if a HOSC clock failure is detected. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_con_csson(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_CSSON_MSK); +} +/** + * @brief Get Clock security system (CSS) + * @note Set and cleared by software to enable the clock security system. + * When CSSON is set, the clock detector is enabled by hardware when the HOSC oscillator is ready, + * and disabled by hardware if a HOSC clock failure is detected. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_con_csson(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_CSSON_MSK)>>RCU_CON_CSSON_POS); +} +/** + * @brief PLL1 enable bit(for USB PHY) + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_con_pll1on(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_PLL1ON_MSK); +} +/** + * @brief PLL1 disable bit(for USB PHY) + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_con_pll1on(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_PLL1ON_MSK); +} +/** + * @brief Get PLL1 bit(for USB PHY) + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_con_pll1on(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_PLL1ON_MSK)>>RCU_CON_PLL1ON_POS); +} +/** + * @brief PLL0 enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_con_pll0on(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_PLL0ON_MSK); +} +/** + * @brief PLL0 disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_con_pll0on(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_PLL0ON_MSK); +} +/** + * @brief Get PLL0 bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_con_pll0on(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_PLL0ON_MSK)>>RCU_CON_PLL0ON_POS); +} +/** + * @brief External low speed oscillator clock enbale bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_con_loscon(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_LOSCON_MSK); +} +/** + * @brief External low speed oscillator clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_con_loscon(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_LOSCON_MSK); +} +/** + * @brief Get External low speed oscillator clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_con_loscon(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_LOSCON_MSK)>>RCU_CON_LOSCON_POS); +} +/** + * @brief Internal low speed oscillator clock enbale bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_con_lrcon(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_LRCON_MSK); +} +/** + * @brief Internal low speed oscillator clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_con_lrcon(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_LRCON_MSK); +} +/** + * @brief Get Internal low speed oscillator clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_con_lrcon(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_LRCON_MSK)>>RCU_CON_LRCON_POS); +} +/** + * @brief External high speed oscillator clock enbale bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_con_hoscon(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_HOSCON_MSK); +} +/** + * @brief External high speed oscillator clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_con_hoscon(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_HOSCON_MSK); +} +/** + * @brief Get External high speed oscillator clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_con_hoscon(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_HOSCON_MSK)>>RCU_CON_HOSCON_POS); +} +/** + * @brief Internal high speed oscillator clock enbale bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_con_hrcon(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CON, RCU_CON_HRCON_MSK); +} +/** + * @brief Internal high speed oscillator clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_con_hrcon(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->CON, RCU_CON_HRCON_MSK); +} +/** + * @brief Get Internal high speed oscillator clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_con_hrcon(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->CON, RCU_CON_HRCON_MSK)>>RCU_CON_HRCON_POS); +} + +/** @defgroup MD_RCU_CON_CSSON CSSON + * @brief Set Clock security system bit for md_rcu_set_con() function used + * @param csson This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_rcu_set_con_csson_fun(csson) (csson<CON, (csson|pll1on|pll0on|loscon|lrcon|hoscon|hrcon)); +} + +/** + * @brief Clock configuration set bit + * @note This bit is write-only. A read to this bit returns the value 0. + * If set is bit to high, start to configurate clock setting. + * When the clock configuration process was finished, this bit was clear to zero by self. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_ckcfg(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->CFG, RCU_CFG_CKCFG_MSK); +} +/** + * @brief Set Microcontroller clock output prescaler + * @note Output Frequency = MCO/(MPRE+1) + * @param rcu RCU Instance + * @param mpre This parameter can be one of the following values: + * @arg Max Value 7 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_mpre(RCU_TypeDef *rcu, uint32_t mpre) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_MPRE_MSK, (mpre<CFG, RCU_CFG_MPRE_MSK)>>RCU_CFG_MPRE_POSS); +} +/** + * @brief Set Microcontroller clock output (MCO) + * @param rcu RCU Instance + * @param msw This parameter can be one of the following values: + * @arg @ref MD_RCU_MCO_DISABLE + * @arg @ref MD_RCU_MCO_LRC + * @arg @ref MD_RCU_MCO_LOSC + * @arg @ref MD_RCU_MCO_HRC + * @arg @ref MD_RCU_MCO_HOSC + * @arg @ref MD_RCU_MCO_PLL0 + * @arg @ref MD_RCU_MCO_PLL1 + * @arg @ref MD_RCU_MCO_SYSCLK + * @arg @ref MD_RCU_MCO_HCLK + * @arg @ref MD_RCU_MCO_PCLK + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_msw(RCU_TypeDef *rcu, uint32_t msw) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_MSW_MSK, (msw<CFG, RCU_CFG_MSW_MSK)>>RCU_CFG_MSW_POSS); +} +/** + * @brief Set PLL0 multiplication factor + * @note PLL0 output clock frequency is 4*(PLL0MUL+1)MHz + * @param rcu RCU Instance + * @param pllmul can be one of the following values: + * @arg Max Value 31 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_pllmul(RCU_TypeDef *rcu, uint32_t pllmul) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_PLLMUL_MSK, (pllmul<CFG, RCU_CFG_PLLMUL_MSK)>>RCU_CFG_PLLMUL_POSS); +} +/** + * @brief Set PLL0/1 reference clock source + * @param rcu RCU Instance + * @param pllsrc This parameter can be one of the following values: + * @arg @ref MD_RCU_PLL_SRC_HRC + * @arg @ref MD_RCU_PLL_SRC_HOSCDIV + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_pllsrc(RCU_TypeDef *rcu, uint32_t pllsrc) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_PLLSRC_MSK, (pllsrc<CFG, RCU_CFG_PLLSRC_MSK)>>RCU_CFG_PLLSRC_POS); +} +/** + * @brief Set HOSC clock division factor for PLL0/1 reference clock 4 MHz + * @note These bits are set and cleared by software to select HOSCDIV division factor. + * @note PLL_reference_clock (4 MHz) = HOSC / (HOSCDIV+1) + * @param rcu RCU Instance + * @param hoscdiv can be one of the following values: + * @arg Max Value 7 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_hoscdiv(RCU_TypeDef *rcu, uint32_t hoscdiv) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_HOSCDIV_MSK, (hoscdiv<CFG, RCU_CFG_HOSCDIV_MSK)>>RCU_CFG_HOSCDIV_POSS); +} +/** + * @brief Set APB clock prescaler(PCLK) + * @param rcu RCU Instance + * @param ppre The retval can be one of the following values: + * @arg @ref MD_RCU_PPRE_HCLK_DIV_1 + * @arg @ref MD_RCU_PPRE_HCLK_DIV_2 + * @arg @ref MD_RCU_PPRE_HCLK_DIV_4 + * @arg @ref MD_RCU_PPRE_HCLK_DIV_8 + * @arg @ref MD_RCU_PPRE_HCLK_DIV_16 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_ppre(RCU_TypeDef *rcu, uint32_t ppre) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_PPRE_MSK, (ppre<CFG, RCU_CFG_PPRE_MSK)>>RCU_CFG_PPRE_POSS); +} +/** + * @brief Set AHB clock prescaler(HCLK) + * @param rcu RCU Instance + * @param hpre can be one of the following values: + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_1 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_2 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_4 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_8 + * @arg @ref MD_RCU_HPRE_SYSCLK_DIV_16 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_hpre(RCU_TypeDef *rcu, uint32_t hpre) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_HPRE_MSK, (hpre<CFG, RCU_CFG_HPRE_MSK)>>RCU_CFG_HPRE_POSS); +} +/** + * @brief Set System clock switch(SYSCLK) + * @param rcu RCU Instance + * @param sw can be one of the following values: + * @arg @ref MD_RCU_SYSCLK_HRC + * @arg @ref MD_RCU_SYSCLK_HOSC + * @arg @ref MD_RCU_SYSCLK_LRC + * @arg @ref MD_RCU_SYSCLK_LOSC + * @arg @ref MD_RCU_SYSCLK_PLL0 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_cfg_sw(RCU_TypeDef *rcu, uint32_t sw) +{ + MODIFY_REG(rcu->CFG, RCU_CFG_SW_MSK, (sw<CFG, RCU_CFG_SW_MSK)>>RCU_CFG_SW_POSS); +} +/** @defgroup MD_RCU_CFG_MPRE MPRE + * @brief Set Microcontroller clock output prescaler bit for md_rcu_set_cfg() function used + * @param mpre This parameter can be one of the following values: + * @arg Max Value 7 + * @arg Min Value 0 + * @{ + */ +#define md_rcu_set_cfg_mpre_fun(mpre) (mpre<CFG, (mpre|msw|pllmul|pllsrc|hoscdiv|ppre|hpre|sw)); +} + +/** + * @brief Set SPI2/I2S2 External Clock Source Select + * @param rcu RCU Instance + * @param i2s2ckdl This parameter can be one of the following values: + * @arg @ref MD_RCU_PSCK_I2S2CKSL_DISABLE + * @arg @ref MD_RCU_PSCK_I2S2CKSL_I2SCLK1 + * @arg @ref MD_RCU_PSCK_I2S2CKSL_I2SCLK2 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_psck_i2s2ckdl(RCU_TypeDef *rcu, uint32_t i2s2ckdl) +{ + MODIFY_REG(rcu->PSCK, RCU_PSCK_I2S2CKSL_MSK, (i2s2ckdl<PSCK, RCU_PSCK_I2S2CKSL_MSK)>>RCU_PSCK_I2S2CKSL_POSS); +} +/** + * @brief Set SPI1/I2S1 External Clock Source Select + * @param rcu RCU Instance + * @param i2s1ckdl This parameter can be one of the following values: + * @arg @ref MD_RCU_PSCK_I2S1CKSL_DISABLE + * @arg @ref MD_RCU_PSCK_I2S1CKSL_I2SCLK1 + * @arg @ref MD_RCU_PSCK_I2S1CKSL_I2SCLK2 + * @retval None + */ +__STATIC_INLINE void md_rcu_set_psck_i2s1ckdl(RCU_TypeDef *rcu, uint32_t i2s1ckdl) +{ + MODIFY_REG(rcu->PSCK, RCU_PSCK_I2S1CKSL_MSK, (i2s1ckdl<PSCK, RCU_PSCK_I2S1CKSL_MSK)>>RCU_PSCK_I2S1CKSL_POSS); +} + +/** @defgroup MD_RCU_PSCK_I2S2CKSL_ I2S2CKSL + * @brief Set SPI2/I2S2 External Clock Source Select bit for md_rcu_set_psck() function used + * @param i2s2ckdl This parameter can be one of the following values: + * @arg @ref MD_RCU_PSCK_I2S2CKSL_DISABLE + * @arg @ref MD_RCU_PSCK_I2S2CKSL_I2SCLK1 + * @arg @ref MD_RCU_PSCK_I2S2CKSL_I2SCLK2 + * @{ + */ +#define md_rcu_set_psck_i2s2ckdl_fun(i2s2ckdl) (i2s2ckdl<PSCK, (i2s2ckdl|i2s1ckdl)); +} + +/** + * @brief GPIOD reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_gpden(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_GPDEN_MSK); +} +/** + * @brief GPIOD reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_gpden(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_GPDEN_MSK); +} +/** + * @brief Get GPIOD reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_gpden(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_GPDEN_MSK)>>RCU_AHBRST_GPDEN_POS); +} +/** + * @brief GPIOC reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_gpcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_GPCEN_MSK); +} +/** + * @brief GPIOC reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_gpcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_GPCEN_MSK); +} +/** + * @brief Get GPIOC reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_gpcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_GPCEN_MSK)>>RCU_AHBRST_GPCEN_POS); +} +/** + * @brief GPIOB reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_gpben(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_GPBEN_MSK); +} +/** + * @brief GPIOB reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_gpben(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_GPBEN_MSK); +} +/** + * @brief Get GPIOB reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_gpben(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_GPBEN_MSK)>>RCU_AHBRST_GPBEN_POS); +} +/** + * @brief GPIOA reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_gpaen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_GPAEN_MSK); +} +/** + * @brief GPIOA reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_gpaen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_GPAEN_MSK); +} +/** + * @brief Get GPIOA reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_gpaen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_GPAEN_MSK)>>RCU_AHBRST_GPAEN_POS); +} +/** + * @brief HDIV reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_hdiven(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_HDIVEN_MSK); +} +/** + * @brief HDIV reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_hdiven(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_HDIVEN_MSK); +} +/** + * @brief Get HDIV reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_hdiven(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_HDIVEN_MSK)>>RCU_AHBRST_HDIVEN_POS); +} +/** + * @brief USB reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_usben(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_USBEN_MSK); +} +/** + * @brief USB reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_usben(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_USBEN_MSK); +} +/** + * @brief Get USB reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_usben(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_USBEN_MSK)>>RCU_AHBRST_USBEN_POS); +} +/** + * @brief AES reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_aesen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_AESEN_MSK); +} +/** + * @brief AES reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_aesen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_AESEN_MSK); +} +/** + * @brief Get AES reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_aesen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_AESEN_MSK)>>RCU_AHBRST_AESEN_POS); +} +/** + * @brief CRC reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_crcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_CRCEN_MSK); +} +/** + * @brief CRC reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_crcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_CRCEN_MSK); +} +/** + * @brief Get CRC reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_crcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_CRCEN_MSK)>>RCU_AHBRST_CRCEN_POS); +} +/** + * @brief RTC reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_rtcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_RTCEN_MSK); +} +/** + * @brief RTC reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_rtcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_RTCEN_MSK); +} +/** + * @brief Get RTC reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_rtcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_RTCEN_MSK)>>RCU_AHBRST_RTCEN_POS); +} +/** + * @brief DMA1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbrst_dma1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBRST, RCU_AHBRST_DMA1EN_MSK); +} +/** + * @brief DMA1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbrst_dma1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBRST, RCU_AHBRST_DMA1EN_MSK); +} +/** + * @brief Get DMA1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbrst_dma1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBRST, RCU_AHBRST_DMA1EN_MSK)>>RCU_AHBRST_DMA1EN_POS); +} + +/** @defgroup MD_RCU_AHBRST_GPDEN GPDEN + * @brief Set GPIOD reset request bit for md_rcu_set_ahbrst() function used + * @param gpden This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_rcu_set_ahbrst_gpden_fun(gpden) (gpden<AHBRST, (gpden|gpcen|gpben|gpaen|hdiven|usben|aesen|crcen|rtcen|dma1en)); +} + +/** + * @brief DAC reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_dacen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_DACEN_MSK); +} +/** + * @brief DAC reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_dacen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_DACEN_MSK); +} +/** + * @brief Get DAC reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_dacen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_DACEN_MSK)>>RCU_APB1RST_DACEN_POS); +} +/** + * @brief I2C2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_i2c2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_I2C2EN_MSK); +} +/** + * @brief I2C2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_i2c2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_I2C2EN_MSK); +} +/** + * @brief Get I2C2 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_i2c2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_I2C2EN_MSK)>>RCU_APB1RST_I2C2EN_POS); +} +/** + * @brief I2C1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_i2c1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_I2C1EN_MSK); +} +/** + * @brief I2C1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_i2c1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_I2C1EN_MSK); +} +/** + * @brief Get I2C1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_i2c1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_I2C1EN_MSK)>>RCU_APB1RST_I2C1EN_POS); +} +/** + * @brief SUART2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_suart2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_SUART2EN_MSK); +} +/** + * @brief SUART2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_suart2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_SUART2EN_MSK); +} +/** + * @brief Get SUART2 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_suart2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_SUART2EN_MSK)>>RCU_APB1RST_SUART2EN_POS); +} +/** + * @brief SUART1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_suart1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_SUART1EN_MSK); +} +/** + * @brief SUART1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_suart1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_SUART1EN_MSK); +} +/** + * @brief Get SUART1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_suart1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_SUART1EN_MSK)>>RCU_APB1RST_SUART1EN_POS); +} +/** + * @brief UART3 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_uart3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_UART3EN_MSK); +} +/** + * @brief UART3 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_uart3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_UART3EN_MSK); +} +/** + * @brief Get UART3 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_uart3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_UART3EN_MSK)>>RCU_APB1RST_UART3EN_POS); +} +/** + * @brief UART2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_uart2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_UART2EN_MSK); +} +/** + * @brief UART2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_uart2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_UART2EN_MSK); +} +/** + * @brief Get UART2 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_uart2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_UART2EN_MSK)>>RCU_APB1RST_UART2EN_POS); +} +/** + * @brief SPI2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_spi2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_SPI2EN_MSK); +} +/** + * @brief SPI2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_spi2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_SPI2EN_MSK); +} +/** + * @brief Get SPI2 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_spi2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_SPI2EN_MSK)>>RCU_APB1RST_SPI2EN_POS); +} +/** + * @brief IWDT reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_iwdten(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_IWDTEN_MSK); +} +/** + * @brief IWDT reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_iwdten(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_IWDTEN_MSK); +} +/** + * @brief Get IWDT reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_iwdten(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_IWDTEN_MSK)>>RCU_APB1RST_IWDTEN_POS); +} +/** + * @brief WWDT reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_wwdten(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_WWDTEN_MSK); +} +/** + * @brief WWDT reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_wwdten(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_WWDTEN_MSK); +} +/** + * @brief Get WWDT reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_wwdten(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_WWDTEN_MSK)>>RCU_APB1RST_WWDTEN_POS); +} +/** + * @brief BS16T1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_bs16t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_BS16T1EN_MSK); +} +/** + * @brief BS16T1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_bs16t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_BS16T1EN_MSK); +} +/** + * @brief Get BS16T1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_bs16t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_BS16T1EN_MSK)>>RCU_APB1RST_BS16T1EN_POS); +} +/** + * @brief GP16C4T3 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_gp16c4t3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T3EN_MSK); +} +/** + * @brief GP16C4T3 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_gp16c4t3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T3EN_MSK); +} +/** + * @brief Get GP16C4T3 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_gp16c4t3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T3EN_MSK)>>RCU_APB1RST_GP16C4T3EN_POS); +} +/** + * @brief GP16C4T2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_gp16c4t2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T2EN_MSK); +} +/** + * @brief GP16C4T2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_gp16c4t2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T2EN_MSK); +} +/** + * @brief Get GP16C4T2 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_gp16c4t2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T2EN_MSK)>>RCU_APB1RST_GP16C4T2EN_POS); +} +/** + * @brief GP16C4T1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_gp16c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T1EN_MSK); +} +/** + * @brief GP16C4T1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_gp16c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T1EN_MSK); +} +/** + * @brief Get GP16C4T1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_gp16c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_GP16C4T1EN_MSK)>>RCU_APB1RST_GP16C4T1EN_POS); +} +/** + * @brief GP32C4T1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1rst_gp32c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1RST, RCU_APB1RST_GP32C4T1EN_MSK); +} +/** + * @brief GP32C4T1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1rst_gp32c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1RST, RCU_APB1RST_GP32C4T1EN_MSK); +} +/** + * @brief Get GP32C4T1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1rst_gp32c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1RST, RCU_APB1RST_GP32C4T1EN_MSK)>>RCU_APB1RST_GP32C4T1EN_POS); +} + +/** @defgroup MD_RCU_APB1RST_DACEN DACEN + * @brief Set DAC reset request bit for md_rcu_set_apb1rst() function used + * @param dacen This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_rcu_set_apb1rst_dacen_fun(dacen) (dacen<APB1RST, (dacen|i2c2en|i2c1en|suart2en|suart1en|uart3en|uart2en|spi2en|iwdten|wwdten| + bs16t1en|gp16c4t3en|gp16c4t2en|gp16c4t1en|gp32c4t1en)); +} + +/** + * @brief CMP reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_cmpen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_CMPEN_MSK); +} +/** + * @brief CMP reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_cmpen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_CMPEN_MSK); +} +/** + * @brief Get CMP reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_cmpen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_CMPEN_MSK)>>RCU_APB2RST_CMPEN_POS); +} +/** + * @brief GP16C2T4 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_gp16c2t4en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T4EN_MSK); +} +/** + * @brief GP16C2T4 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_gp16c2t4en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T4EN_MSK); +} +/** + * @brief Get GP16C2T4 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_gp16c2t4en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T4EN_MSK)>>RCU_APB2RST_GP16C2T4EN_POS); +} +/** + * @brief GP16C2T3 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_gp16c2t3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T3EN_MSK); +} +/** + * @brief GP16C2T3 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_gp16c2t3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T3EN_MSK); +} +/** + * @brief Get GP16C2T3 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_gp16c2t3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T3EN_MSK)>>RCU_APB2RST_GP16C2T3EN_POS); +} +/** + * @brief GP16C2T2 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_gp16c2t2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T2EN_MSK); +} +/** + * @brief GP16C2T2 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_gp16c2t2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T2EN_MSK); +} +/** + * @brief Get GP16C2T2 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_gp16c2t2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T2EN_MSK)>>RCU_APB2RST_GP16C2T2EN_POS); +} +/** + * @brief GP16C2T1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_gp16c2t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T1EN_MSK); +} +/** + * @brief GP16C2T1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_gp16c2t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T1EN_MSK); +} +/** + * @brief Get GP16C2T1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_gp16c2t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_GP16C2T1EN_MSK)>>RCU_APB2RST_GP16C2T1EN_POS); +} +/** + * @brief UART1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_uart1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_UART1EN_MSK); +} +/** + * @brief UART1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_uart1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_UART1EN_MSK); +} +/** + * @brief Get UART1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_uart1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_UART1EN_MSK)>>RCU_APB2RST_UART1EN_POS); +} +/** + * @brief SPI1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_spi1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_SPI1EN_MSK); +} +/** + * @brief SPI1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_spi1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_SPI1EN_MSK); +} +/** + * @brief Get SPI1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_spi1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_SPI1EN_MSK)>>RCU_APB2RST_SPI1EN_POS); +} +/** + * @brief AD16C4T1 reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_ad16c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_AD16C4T1EN_MSK); +} +/** + * @brief AD16C4T1 reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_ad16c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_AD16C4T1EN_MSK); +} +/** + * @brief Get AD16C4T1 reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_ad16c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_AD16C4T1EN_MSK)>>RCU_APB2RST_AD16C4T1EN_POS); +} +/** + * @brief ADC reset request enable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2rst_adcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2RST, RCU_APB2RST_ADCEN_MSK); +} +/** + * @brief ADC reset request disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2rst_adcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2RST, RCU_APB2RST_ADCEN_MSK); +} +/** + * @brief Get ADC reset request bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2rst_adcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2RST, RCU_APB2RST_ADCEN_MSK)>>RCU_APB2RST_ADCEN_POS); +} + +/** @defgroup MD_RCU_APB2RST_CMPEN CMPEN + * @brief Set CMP reset request bit for md_rcu_set_apb2rst() function used + * @param cmpen This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_rcu_set_apb2rst_cmpen_fun(cmpen) (cmpen<APB2RST, (cmpen|gp16c2t4en|gp16c2t3en|gp16c2t2en|gp16c2t1en|uart1en|spi1en|ad16c4t1en|adcen)); +} + +/** + * @brief GPIOD clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_gpden(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_GPDEN_MSK); +} +/** + * @brief GPIOD Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_gpden(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_GPDEN_MSK); +} +/** + * @brief Get GPIOD Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_gpden(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_GPDEN_MSK)>>RCU_AHBEN_GPDEN_POS); +} +/** + * @brief GPIOC clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_gpcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_GPCEN_MSK); +} +/** + * @brief GPIOC Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_gpcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_GPCEN_MSK); +} +/** + * @brief Get GPIOC Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_gpcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_GPCEN_MSK)>>RCU_AHBEN_GPCEN_POS); +} +/** + * @brief GPIOB clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_gpben(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_GPBEN_MSK); +} +/** + * @brief GPIOB Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_gpben(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_GPBEN_MSK); +} +/** + * @brief Get GPIOB Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_gpben(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_GPBEN_MSK)>>RCU_AHBEN_GPBEN_POS); +} +/** + * @brief GPIOA clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_gpaen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_GPAEN_MSK); +} +/** + * @brief GPIOA Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_gpaen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_GPAEN_MSK); +} +/** + * @brief Get GPIOA Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_gpaen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_GPAEN_MSK)>>RCU_AHBEN_GPAEN_POS); +} +/** + * @brief HDIV clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_hdiven(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_HDIVEN_MSK); +} +/** + * @brief HDIV Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_hdiven(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_HDIVEN_MSK); +} +/** + * @brief Get HDIV Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_hdiven(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_HDIVEN_MSK)>>RCU_AHBEN_HDIVEN_POS); +} +/** + * @brief USB clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_usben(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_USBEN_MSK); +} +/** + * @brief USB Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_usben(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_USBEN_MSK); +} +/** + * @brief Get USB Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_usben(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_USBEN_MSK)>>RCU_AHBEN_USBEN_POS); +} +/** + * @brief AES clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_aesen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_AESEN_MSK); +} +/** + * @brief AES Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_aesen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_AESEN_MSK); +} +/** + * @brief Get AES Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_aesen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_AESEN_MSK)>>RCU_AHBEN_AESEN_POS); +} +/** + * @brief CRC clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_crcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_CRCEN_MSK); +} +/** + * @brief CRC Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_crcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_CRCEN_MSK); +} +/** + * @brief Get CRC Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_crcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_CRCEN_MSK)>>RCU_AHBEN_CRCEN_POS); +} +/** + * @brief RTC clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_rtcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_RTCEN_MSK); +} +/** + * @brief RTC Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_rtcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_RTCEN_MSK); +} +/** + * @brief Get RTC Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_rtcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_RTCEN_MSK)>>RCU_AHBEN_RTCEN_POS); +} +/** + * @brief DMA1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahben_dma1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBEN, RCU_AHBEN_DMA1EN_MSK); +} +/** + * @brief DMA1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahben_dma1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBEN, RCU_AHBEN_DMA1EN_MSK); +} +/** + * @brief Get DMA1 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahben_dma1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBEN, RCU_AHBEN_DMA1EN_MSK)>>RCU_AHBEN_DMA1EN_POS); +} + +/** @defgroup MD_RCU_AHBEN_GPDEN GPDEN + * @brief Set GPIOD clock bit for md_rcu_set_ahben() function used + * @param gpden This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_rcu_set_ahben_gpden_fun(gpden) (gpden<AHBEN, (gpden|gpcen|gpben|gpaen|hdiven|usben|aesen|crcen|rtcen|dma1en)); +} + +/** + * @brief DAC clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_dacen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_DACEN_MSK); +} +/** + * @brief DAC Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_dacen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_DACEN_MSK); +} +/** + * @brief Get DAC Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_dacen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_DACEN_MSK)>>RCU_APB1EN_DACEN_POS); +} +/** + * @brief I2C2 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_i2c2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_I2C2EN_MSK); +} +/** + * @brief I2C2 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_i2c2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_I2C2EN_MSK); +} +/** + * @brief Get I2C2 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_i2c2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_I2C2EN_MSK)>>RCU_APB1EN_I2C2EN_POS); +} +/** + * @brief I2C1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_i2c1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_I2C1EN_MSK); +} +/** + * @brief I2C1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_i2c1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_I2C1EN_MSK); +} +/** + * @brief Get I2C1 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_i2c1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_I2C1EN_MSK)>>RCU_APB1EN_I2C1EN_POS); +} +/** + * @brief SUART2 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_suart2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_SUART2EN_MSK); +} +/** + * @brief SUART2 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_suart2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_SUART2EN_MSK); +} +/** + * @brief Get SUART2 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_suart2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_SUART2EN_MSK)>>RCU_APB1EN_SUART2EN_POS); +} +/** + * @brief SUART1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_suart1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_SUART1EN_MSK); +} +/** + * @brief SUART1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_suart1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_SUART1EN_MSK); +} +/** + * @brief Get SUART1 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_suart1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_SUART1EN_MSK)>>RCU_APB1EN_SUART1EN_POS); +} +/** + * @brief UART3 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_uart3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_UART3EN_MSK); +} +/** + * @brief UART3 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_uart3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_UART3EN_MSK); +} +/** + * @brief Get UART3 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_uart3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_UART3EN_MSK)>>RCU_APB1EN_UART3EN_POS); +} +/** + * @brief UART2 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_uart2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_UART2EN_MSK); +} +/** + * @brief UART2 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_uart2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_UART2EN_MSK); +} +/** + * @brief Get UART2 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_uart2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_UART2EN_MSK)>>RCU_APB1EN_UART2EN_POS); +} +/** + * @brief SPI2 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_spi2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_SPI2EN_MSK); +} +/** + * @brief SPI2 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_spi2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_SPI2EN_MSK); +} +/** + * @brief Get SPI2 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_spi2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_SPI2EN_MSK)>>RCU_APB1EN_SPI2EN_POS); +} +/** + * @brief IWDT clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_iwdten(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_IWDTEN_MSK); +} +/** + * @brief IWDT Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_iwdten(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_IWDTEN_MSK); +} +/** + * @brief Get IWDT Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_iwdten(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_IWDTEN_MSK)>>RCU_APB1EN_IWDTEN_POS); +} +/** + * @brief WWDT clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_wwdten(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_WWDTEN_MSK); +} +/** + * @brief WWDT Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_wwdten(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_WWDTEN_MSK); +} +/** + * @brief Get WWDT Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_wwdten(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_WWDTEN_MSK)>>RCU_APB1EN_WWDTEN_POS); +} +/** + * @brief BS16T1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_bs16t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_BS16T1EN_MSK); +} +/** + * @brief BS16T1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_bs16t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_BS16T1EN_MSK); +} +/** + * @brief Get BS16T1 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_bs16t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_BS16T1EN_MSK)>>RCU_APB1EN_BS16T1EN_POS); +} +/** + * @brief GP16C4T3 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_gp16c4t3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T3EN_MSK); +} +/** + * @brief GP16C4T3 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_gp16c4t3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T3EN_MSK); +} +/** + * @brief Get GP16C4T3 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_gp16c4t3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T3EN_MSK)>>RCU_APB1EN_GP16C4T3EN_POS); +} +/** + * @brief GP16C4T2 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_gp16c4t2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T2EN_MSK); +} +/** + * @brief GP16C4T2 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_gp16c4t2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T2EN_MSK); +} +/** + * @brief Get GP16C4T2 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_gp16c4t2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T2EN_MSK)>>RCU_APB1EN_GP16C4T2EN_POS); +} +/** + * @brief GP16C4T1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_gp16c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T1EN_MSK); +} +/** + * @brief GP16C4T1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_gp16c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T1EN_MSK); +} +/** + * @brief Get GP16C4T1 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_gp16c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_GP16C4T1EN_MSK)>>RCU_APB1EN_GP16C4T1EN_POS); +} +/** + * @brief GP32C4T1 clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1en_gp32c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1EN, RCU_APB1EN_GP32C4T1EN_MSK); +} +/** + * @brief GP32C4T1 Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1en_gp32c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1EN, RCU_APB1EN_GP32C4T1EN_MSK); +} +/** + * @brief Get GP32C4T1 Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1en_gp32c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1EN, RCU_APB1EN_GP32C4T1EN_MSK)>>RCU_APB1EN_GP32C4T1EN_POS); +} + +/** @defgroup MD_RCU_APB1EN_DACEN DACEN + * @brief Set DAC clock bit for md_rcu_set_apb1en() function used + * @param dacen This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_rcu_set_apb1en_dacen_fun(dacen) (dacen<APB1EN, (dacen|i2c2en|i2c1en|suart2en|suart1en|uart3en|uart2en|spi2en|iwdten|wwdten| + bs16t1en|gp16c4t3en|gp16c4t2en|gp16c4t1en|gp32c4t1en)); +} + +/** + * @brief CMP clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_cmpen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_CMPEN_MSK); +} +/** + * @brief CMP Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_cmpen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_CMPEN_MSK); +} +/** + * @brief Get CMP Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_cmpen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_CMPEN_MSK)>>RCU_APB2EN_CMPEN_POS); +} +/** + * @brief GP16C2T4EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_gp16c2t4en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T4EN_MSK); +} +/** + * @brief GP16C2T4EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_gp16c2t4en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T4EN_MSK); +} +/** + * @brief Get GP16C2T4EN Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_gp16c2t4en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T4EN_MSK)>>RCU_APB2EN_GP16C2T4EN_POS); +} +/** + * @brief GP16C2T3EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_gp16c2t3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T3EN_MSK); +} +/** + * @brief GP16C2T3EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_gp16c2t3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T3EN_MSK); +} +/** + * @brief Get GP16C2T3EN Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_gp16c2t3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T3EN_MSK)>>RCU_APB2EN_GP16C2T3EN_POS); +} +/** + * @brief GP16C2T2EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_gp16c2t2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T2EN_MSK); +} +/** + * @brief GP16C2T2EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_gp16c2t2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T2EN_MSK); +} +/** + * @brief Get GP16C2T2EN Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_gp16c2t2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T2EN_MSK)>>RCU_APB2EN_GP16C2T2EN_POS); +} +/** + * @brief GP16C2T1EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_gp16c2t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T1EN_MSK); +} +/** + * @brief GP16C2T1EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_gp16c2t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T1EN_MSK); +} +/** + * @brief Get GP16C2T1EN Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_gp16c2t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_GP16C2T1EN_MSK)>>RCU_APB2EN_GP16C2T1EN_POS); +} +/** + * @brief UART1EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_uart1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_UART1EN_MSK); +} +/** + * @brief UART1EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_uart1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_UART1EN_MSK); +} +/** + * @brief Get UART1EN Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_uart1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_UART1EN_MSK)>>RCU_APB2EN_UART1EN_POS); +} +/** + * @brief SPI1EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_spi1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_SPI1EN_MSK); +} +/** + * @brief SPI1EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_spi1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_SPI1EN_MSK); +} +/** + * @brief Get SPI1EN Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_spi1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_SPI1EN_MSK)>>RCU_APB2EN_SPI1EN_POS); +} +/** + * @brief AD16C4T1EN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_ad16c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_AD16C4T1EN_MSK); +} +/** + * @brief AD16C4T1EN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_ad16c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_AD16C4T1EN_MSK); +} +/** + * @brief Get AD16C4T1EN Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_ad16c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_AD16C4T1EN_MSK)>>RCU_APB2EN_AD16C4T1EN_POS); +} +/** + * @brief ADCEN clock enable bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2en_adcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2EN, RCU_APB2EN_ADCEN_MSK); +} +/** + * @brief ADCEN Clock disable bit + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2en_adcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2EN, RCU_APB2EN_ADCEN_MSK); +} +/** + * @brief Get ADCEN Clock bit + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2en_adcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2EN, RCU_APB2EN_ADCEN_MSK)>>RCU_APB2EN_ADCEN_POS); +} + +/** @defgroup MD_RCU_APB2EN_CMPEN CMPEN + * @brief Set CMP clock bit for md_rcu_set_apb2en() function used + * @param cmpen This parameter can be one of the following values: + * @arg @ref DISABLE + * @arg @ref ENABLE + * @{ + */ +#define md_rcu_set_apb2en_cmpen_fun(cmpen) (cmpen<APB2EN, (cmpen|gp16c2t4en|gp16c2t3en|gp16c2t2en|gp16c2t1en|uart1en|spi1en|ad16c4t1en|adcen)); +} + + + + + + + + + + +/** + * @brief GPDEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_gpden(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_GPDEN_MSK); +} +/** + * @brief GPDEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_gpden(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_GPDEN_MSK); +} +/** + * @brief Get GPDEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_gpden(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_GPDEN_MSK)>>RCU_AHBSL_GPDEN_POS); +} +/** + * @brief GPCEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_gpcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_GPCEN_MSK); +} +/** + * @brief GPCEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_gpcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_GPCEN_MSK); +} +/** + * @brief Get GPCEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_gpcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_GPCEN_MSK)>>RCU_AHBSL_GPCEN_POS); +} +/** + * @brief GPBEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_gpben(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_GPBEN_MSK); +} +/** + * @brief GPBEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_gpben(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_GPBEN_MSK); +} +/** + * @brief Get GPBEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_gpben(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_GPBEN_MSK)>>RCU_AHBSL_GPBEN_POS); +} +/** + * @brief GPAEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_gpaen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_GPAEN_MSK); +} +/** + * @brief GPAEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_gpaen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_GPAEN_MSK); +} +/** + * @brief Get GPAEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_gpaen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_GPAEN_MSK)>>RCU_AHBSL_GPAEN_POS); +} +/** + * @brief HDIVEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_hdiven(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_HDIVEN_MSK); +} +/** + * @brief HDIVEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_hdiven(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_HDIVEN_MSK); +} +/** + * @brief Get HDIVEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_hdiven(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_HDIVEN_MSK)>>RCU_AHBSL_HDIVEN_POS); +} +/** + * @brief USBEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_usben(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_USBEN_MSK); +} +/** + * @brief USBEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_usben(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_USBEN_MSK); +} +/** + * @brief Get USBEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_usben(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_USBEN_MSK)>>RCU_AHBSL_USBEN_POS); +} +/** + * @brief AESEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_aesen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_AESEN_MSK); +} +/** + * @brief AESEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_aesen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_AESEN_MSK); +} +/** + * @brief Get AESEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_aesen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_AESEN_MSK)>>RCU_AHBSL_AESEN_POS); +} +/** + * @brief CRCEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_crcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_CRCEN_MSK); +} +/** + * @brief CRCEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_crcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_CRCEN_MSK); +} +/** + * @brief Get CRCEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_crcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_CRCEN_MSK)>>RCU_AHBSL_CRCEN_POS); +} +/** + * @brief RTCEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_rtcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_RTCEN_MSK); +} +/** + * @brief RTCEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_rtcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_RTCEN_MSK); +} +/** + * @brief Get RTCEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_rtcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_RTCEN_MSK)>>RCU_AHBSL_RTCEN_POS); +} +/** + * @brief DMA1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbsl_dma1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBSL, RCU_AHBSL_DMA1EN_MSK); +} +/** + * @brief DMA1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbsl_dma1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBSL, RCU_AHBSL_DMA1EN_MSK); +} +/** + * @brief Get DMA1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbsl_dma1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBSL, RCU_AHBSL_DMA1EN_MSK)>>RCU_AHBSL_DMA1EN_POS); +} + +/** + * @brief DAC clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_dacen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_DACEN_MSK); +} +/** + * @brief DAC clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_dacen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_DACEN_MSK); +} +/** + * @brief Get DAC clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_dacen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_DACEN_MSK)>>RCU_APB1SL_DACEN_POS); +} +/** + * @brief I2C2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_i2c2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_I2C2EN_MSK); +} +/** + * @brief I2C2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_i2c2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_I2C2EN_MSK); +} +/** + * @brief Get I2C2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_i2c2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_I2C2EN_MSK)>>RCU_APB1SL_I2C2EN_POS); +} +/** + * @brief I2C1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_i2c1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_I2C1EN_MSK); +} +/** + * @brief I2C1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_i2c1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_I2C1EN_MSK); +} +/** + * @brief Get I2C1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_i2c1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_I2C1EN_MSK)>>RCU_APB1SL_I2C1EN_POS); +} +/** + * @brief SUART2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_suart2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_SUART2EN_MSK); +} +/** + * @brief SUART2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_suart2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_SUART2EN_MSK); +} +/** + * @brief Get SUART2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_suart2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_SUART2EN_MSK)>>RCU_APB1SL_SUART2EN_POS); +} +/** + * @brief SUART1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_suart1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_SUART1EN_MSK); +} +/** + * @brief SUART1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_suart1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_SUART1EN_MSK); +} +/** + * @brief Get SUART1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_suart1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_SUART1EN_MSK)>>RCU_APB1SL_SUART1EN_POS); +} +/** + * @brief UART3EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_uart3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_UART3EN_MSK); +} +/** + * @brief UART3EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_uart3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_UART3EN_MSK); +} +/** + * @brief Get UART3EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_uart3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_UART3EN_MSK)>>RCU_APB1SL_UART3EN_POS); +} +/** + * @brief UART2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_uart2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_UART2EN_MSK); +} +/** + * @brief UART2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_uart2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_UART2EN_MSK); +} +/** + * @brief Get UART2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_uart2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_UART2EN_MSK)>>RCU_APB1SL_UART2EN_POS); +} +/** + * @brief SPI2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_spi2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_SPI2EN_MSK); +} +/** + * @brief SPI2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_spi2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_SPI2EN_MSK); +} +/** + * @brief Get SPI2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_spi2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_SPI2EN_MSK)>>RCU_APB1SL_SPI2EN_POS); +} +/** + * @brief IWDTEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_iwdten(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_IWDTEN_MSK); +} +/** + * @brief IWDTEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_iwdgen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_IWDTEN_MSK); +} +/** + * @brief Get IWDTEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_iwdten(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_IWDTEN_MSK)>>RCU_APB1SL_IWDTEN_POS); +} +/** + * @brief WWDTEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_wwdten(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_WWDTEN_MSK); +} +/** + * @brief WWDTEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_wwdten(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_WWDTEN_MSK); +} +/** + * @brief Get WWDTEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_wwdten(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_WWDTEN_MSK)>>RCU_APB1SL_WWDTEN_POS); +} +/** + * @brief BS16T1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_bs16t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_BS16T1EN_MSK); +} +/** + * @brief BS16T1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_bs16t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_BS16T1EN_MSK); +} +/** + * @brief Get BS16T1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_bs16t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_BS16T1EN_MSK)>>RCU_APB1SL_BS16T1EN_POS); +} +/** + * @brief GP16C4T3EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_gp16c4t3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T3EN_MSK); +} +/** + * @brief GP16C4T3EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_gp16c4t3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T3EN_MSK); +} +/** + * @brief Get GP16C4T3EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_gp16c4t3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T3EN_MSK)>>RCU_APB1SL_GP16C4T3EN_POS); +} +/** + * @brief GP16C4T2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_gp16c4t2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T2EN_MSK); +} +/** + * @brief GP16C4T2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_gp16c4t2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T2EN_MSK); +} +/** + * @brief Get GP16C4T2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). +y*/ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_gp16c4t2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T2EN_MSK)>>RCU_APB1SL_GP16C4T2EN_POS); +} +/** + * @brief GP16C4T1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_gp16c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T1EN_MSK); +} +/** + * @brief GP16C4T1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_gp16c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T1EN_MSK); +} +/** + * @brief Get GP16C4T1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_gp16c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_GP16C4T1EN_MSK)>>RCU_APB1SL_GP16C4T1EN_POS); +} +/** + * @brief GP32C4T1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1sl_gp32c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1SL, RCU_APB1SL_GP32C4T1EN_MSK); +} +/** + * @brief GP32C4T1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1sl_gp32c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1SL, RCU_APB1SL_GP32C4T1EN_MSK); +} +/** + * @brief Get GP32C4T1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1sl_gp32c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1SL, RCU_APB1SL_GP32C4T1EN_MSK)>>RCU_APB1SL_GP32C4T1EN_POS); +} + +/** + * @brief CMP clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_cmpen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_CMPEN_MSK); +} +/** + * @brief CMP clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_cmpen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_CMPEN_MSK); +} +/** + * @brief Get CMP clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_cmpen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_CMPEN_MSK)>>RCU_APB2SL_CMPEN_POS); +} +/** + * @brief GP16C2T4EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_gp16c2t4en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T4EN_MSK); +} +/** + * @brief GP16C2T4EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_gp16c2t4en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T4EN_MSK); +} +/** + * @brief Get GP16C2T4EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_gp16c2t4en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T4EN_MSK)>>RCU_APB2SL_GP16C2T4EN_POS); +} +/** + * @brief GP16C2T3EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_gp16c2t3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T3EN_MSK); +} +/** + * @brief GP16C2T3EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_gp16c2t3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T3EN_MSK); +} +/** + * @brief Get GP16C2T3EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_gp16c2t3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T3EN_MSK)>>RCU_APB2SL_GP16C2T3EN_POS); +} +/** + * @brief GP16C2T2EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_gp16c2t2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T2EN_MSK); +} +/** + * @brief GP16C2T2EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_gp16c2t2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T2EN_MSK); +} +/** + * @brief Get GP16C2T2EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_gp16c2t2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T2EN_MSK)>>RCU_APB2SL_GP16C2T2EN_POS); +} +/** + * @brief GP16C2T1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_gp16c2t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T1EN_MSK); +} +/** + * @brief GP16C2T1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_gp16c2t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T1EN_MSK); +} +/** + * @brief Get GP16C2T1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_gp16c2t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_GP16C2T1EN_MSK)>>RCU_APB2SL_GP16C2T1EN_POS); +} +/** + * @brief UART1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_uart1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_UART1EN_MSK); +} +/** + * @brief UART1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_uart1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_UART1EN_MSK); +} +/** + * @brief Get UART1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_uart1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_UART1EN_MSK)>>RCU_APB2SL_UART1EN_POS); +} +/** + * @brief SPI1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_spi1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_SPI1EN_MSK); +} +/** + * @brief SPI1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_spi1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_SPI1EN_MSK); +} +/** + * @brief Get SPI1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_spi1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_SPI1EN_MSK)>>RCU_APB2SL_SPI1EN_POS); +} +/** + * @brief AD16C4T1EN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_ad16c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_AD16C4T1EN_MSK); +} +/** + * @brief AD16C4T1EN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_ad16c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_AD16C4T1EN_MSK); +} +/** + * @brief Get AD16C4T1EN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_ad16c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_AD16C4T1EN_MSK)>>RCU_APB2SL_AD16C4T1EN_POS); +} +/** + * @brief ADCEN clock enable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2sl_adcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2SL, RCU_APB2SL_ADCEN_MSK); +} +/** + * @brief ADCEN clock disable during Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2sl_adcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2SL, RCU_APB2SL_ADCEN_MSK); +} +/** + * @brief Get ADCEN clock during Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2sl_adcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2SL, RCU_APB2SL_ADCEN_MSK)>>RCU_APB2SL_ADCEN_POS); +} + +/** + * @brief GPIOD clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_gpden(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_GPDEN_MSK); +} +/** + * @brief GPIOD clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_gpden(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_GPDEN_MSK); +} +/** + * @brief Get GPIOD clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_gpden(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_GPDEN_MSK)>>RCU_AHBDSL_GPDEN_POS); +} +/** + * @brief GPIOC clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_gpcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_GPCEN_MSK); +} +/** + * @brief GPIOC clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_gpcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_GPCEN_MSK); +} +/** + * @brief Get GPIOC clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_gpcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_GPCEN_MSK)>>RCU_AHBDSL_GPCEN_POS); +} +/** + * @brief GPIOB clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_gpben(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_GPBEN_MSK); +} +/** + * @brief GPIOB clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_gpben(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_GPBEN_MSK); +} +/** + * @brief Get GPIOB clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_gpben(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_GPBEN_MSK)>>RCU_AHBDSL_GPBEN_POS); +} +/** + * @brief GPIOA clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_gpaen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_GPAEN_MSK); +} +/** + * @brief GPIOA clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_gpaen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_GPAEN_MSK); +} +/** + * @brief Get GPIOA clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_gpaen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_GPAEN_MSK)>>RCU_AHBDSL_GPAEN_POS); +} +/** + * @brief HDIV clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_hdiven(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_HDIVEN_MSK); +} +/** + * @brief HDIV clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_hdiven(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_HDIVEN_MSK); +} +/** + * @brief Get HDIV clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_hdiven(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_HDIVEN_MSK)>>RCU_AHBDSL_HDIVEN_POS); +} +/** + * @brief USB clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_usben(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_USBEN_MSK); +} +/** + * @brief USB clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_usben(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_USBEN_MSK); +} +/** + * @brief Get USB clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_usben(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_USBEN_MSK)>>RCU_AHBDSL_USBEN_POS); +} +/** + * @brief AES clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_aesen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_AESEN_MSK); +} +/** + * @brief AES clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_aesen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_AESEN_MSK); +} +/** + * @brief Get AES clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_aesen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_AESEN_MSK)>>RCU_AHBDSL_AESEN_POS); +} +/** + * @brief CRC clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_crcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_CRCEN_MSK); +} +/** + * @brief CRC clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_crcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_CRCEN_MSK); +} +/** + * @brief Get CRC clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_crcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_CRCEN_MSK)>>RCU_AHBDSL_CRCEN_POS); +} +/** + * @brief RTC clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_rtcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_RTCEN_MSK); +} +/** + * @brief RTC clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_rtcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_RTCEN_MSK); +} +/** + * @brief Get RTC clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_rtcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_RTCEN_MSK)>>RCU_AHBDSL_RTCEN_POS); +} +/** + * @brief DMA1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_ahbdsl_dma1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->AHBDSL, RCU_AHBDSL_DMA1EN_MSK); +} +/** + * @brief DMA1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_ahbdsl_dma1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->AHBDSL, RCU_AHBDSL_DMA1EN_MSK); +} +/** + * @brief Get DMA1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_ahbdsl_dma1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->AHBDSL, RCU_AHBDSL_DMA1EN_MSK)>>RCU_AHBDSL_DMA1EN_POS); +} + +/** + * @brief DAC clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_dacen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_DACEN_MSK); +} +/** + * @brief DAC clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_dacen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_DACEN_MSK); +} +/** + * @brief Get DAC clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_dacen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_DACEN_MSK)>>RCU_APB1DSL_DACEN_POS); +} +/** + * @brief I2C2 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_apb1dslen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C2EN_MSK); +} +/** + * @brief I2C2 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_apb1dslen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C2EN_MSK); +} +/** + * @brief Get I2C2 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_apb1dslen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C2EN_MSK)>>RCU_APB1DSL_I2C2EN_POS); +} +/** + * @brief I2C1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_i2c1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C1EN_MSK); +} +/** + * @brief I2C1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_i2c1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C1EN_MSK); +} +/** + * @brief Get I2C1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_i2c1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_I2C1EN_MSK)>>RCU_APB1DSL_I2C1EN_POS); +} +/** + * @brief SUART2 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_suart2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART2EN_MSK); +} +/** + * @brief SUART2 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_suart2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART2EN_MSK); +} +/** + * @brief Get SUART2 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_suart2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART2EN_MSK)>>RCU_APB1DSL_SUART2EN_POS); +} +/** + * @brief SUART1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_suart1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART1EN_MSK); +} +/** + * @brief SUART1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_suart1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART1EN_MSK); +} +/** + * @brief Get SUART1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_suart1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_SUART1EN_MSK)>>RCU_APB1DSL_SUART1EN_POS); +} +/** + * @brief UART3 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_uart3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_UART3EN_MSK); +} +/** + * @brief UART3 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_uart3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_UART3EN_MSK); +} +/** + * @brief Get UART3 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_uart3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_UART3EN_MSK)>>RCU_APB1DSL_UART3EN_POS); +} +/** + * @brief UART2 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_uart2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_UART2EN_MSK); +} +/** + * @brief UART2 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_uart2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_UART2EN_MSK); +} +/** + * @brief Get UART2 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_uart2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_UART2EN_MSK)>>RCU_APB1DSL_UART2EN_POS); +} +/** + * @brief SPI2 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_spi2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_SPI2EN_MSK); +} +/** + * @brief SPI2 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_spi2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_SPI2EN_MSK); +} +/** + * @brief Get SPI2 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_spi2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_SPI2EN_MSK)>>RCU_APB1DSL_SPI2EN_POS); +} +/** + * @brief IWDT clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_iwdten(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_IWDTEN_MSK); +} +/** + * @brief IWDT clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_iwdten(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_IWDTEN_MSK); +} +/** + * @brief Get IWDT clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_iwdten(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_IWDTEN_MSK)>>RCU_APB1DSL_IWDTEN_POS); +} +/** + * @brief WWDT clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_wwdten(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_WWDTEN_MSK); +} +/** + * @brief WWDT clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_wwdten(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_WWDTEN_MSK); +} +/** + * @brief Get WWDT clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_wwdten(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_WWDTEN_MSK)>>RCU_APB1DSL_WWDTEN_POS); +} +/** + * @brief BS16T1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_bs16t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_BS16T1EN_MSK); +} +/** + * @brief BS16T1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_bs16t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_BS16T1EN_MSK); +} +/** + * @brief Get BS16T1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_bs16t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_BS16T1EN_MSK)>>RCU_APB1DSL_BS16T1EN_POS); +} +/** + * @brief GP16C4T3 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_gp16c4t3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T3EN_MSK); +} +/** + * @brief GP16C4T3 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_gp16c4t3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T3EN_MSK); +} +/** + * @brief Get GP16C4T3 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_gp16c4t3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T3EN_MSK)>>RCU_APB1DSL_GP16C4T3EN_POS); +} +/** + * @brief GP16C4T2 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_gp16c4t2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T2EN_MSK); +} +/** + * @brief GP16C4T2 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_gp16c4t2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T2EN_MSK); +} +/** + * @brief Get GP16C4T2 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_gp16c4t2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T2EN_MSK)>>RCU_APB1DSL_GP16C4T2EN_POS); +} +/** + * @brief GP16C4T1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_gp16c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T1EN_MSK); +} +/** + * @brief GP16C4T1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_gp16c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T1EN_MSK); +} +/** + * @brief Get GP16C4T1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_gp16c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_GP16C4T1EN_MSK)>>RCU_APB1DSL_GP16C4T1EN_POS); +} +/** + * @brief GP32C4T1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb1dsl_gp32c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB1DSL, RCU_APB1DSL_GP32C4T1EN_MSK); +} +/** + * @brief GP32C4T1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb1dsl_gp32c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB1DSL, RCU_APB1DSL_GP32C4T1EN_MSK); +} +/** + * @brief Get GP32C4T1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb1dsl_gp32c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB1DSL, RCU_APB1DSL_GP32C4T1EN_MSK)>>RCU_APB1DSL_GP32C4T1EN_POS); +} + +/** + * @brief CMP clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_cmpen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_CMPEN_MSK); +} +/** + * @brief CMP clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_cmpen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_CMPEN_MSK); +} +/** + * @brief Get CMP clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_cmpen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_CMPEN_MSK)>>RCU_APB2DSL_CMPEN_POS); +} +/** + * @brief GP16C2T4 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_gp16c2t4en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T4EN_MSK); +} +/** + * @brief GP16C2T4 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_gp16c2t4en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T4EN_MSK); +} +/** + * @brief Get GP16C2T4 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_gp16c2t4en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T4EN_MSK)>>RCU_APB2DSL_GP16C2T4EN_POS); +} +/** + * @brief GP16C2T3 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_gp16c2t3en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T3EN_MSK); +} +/** + * @brief GP16C2T3 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_gp16c2t3en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T3EN_MSK); +} +/** + * @brief Get GP16C2T3 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_gp16c2t3en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T3EN_MSK)>>RCU_APB2DSL_GP16C2T3EN_POS); +} +/** + * @brief GP16C2T2 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_gp16c2t2en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T2EN_MSK); +} +/** + * @brief GP16C2T2 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_gp16c2t2en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T2EN_MSK); +} +/** + * @brief Get GP16C2T2 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_gp16c2t2en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T2EN_MSK)>>RCU_APB2DSL_GP16C2T2EN_POS); +} +/** + * @brief GP16C2T1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_gp16c2t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T1EN_MSK); +} +/** + * @brief GP16C2T1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_gp16c2t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T1EN_MSK); +} +/** + * @brief Get GP16C2T1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_gp16c2t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_GP16C2T1EN_MSK)>>RCU_APB2DSL_GP16C2T1EN_POS); +} +/** + * @brief UART1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_uart1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_UART1EN_MSK); +} +/** + * @brief UART1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_uart1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_UART1EN_MSK); +} +/** + * @brief Get UART1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_uart1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_UART1EN_MSK)>>RCU_APB2DSL_UART1EN_POS); +} +/** + * @brief SPI1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_spi1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_SPI1EN_MSK); +} +/** + * @brief SPI1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_spi1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_SPI1EN_MSK); +} +/** + * @brief Get SPI1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_spi1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_SPI1EN_MSK)>>RCU_APB2DSL_SPI1EN_POS); +} +/** + * @brief AD16C4T1 clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_ad16c4t1en(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_AD16C4T1EN_MSK); +} +/** + * @brief AD16C4T1 clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_ad16c4t1en(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_AD16C4T1EN_MSK); +} +/** + * @brief Get AD16C4T1 clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_ad16c4t1en(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_AD16C4T1EN_MSK)>>RCU_APB2DSL_AD16C4T1EN_POS); +} +/** + * @brief ADC clock enable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_enable_apb2dsl_adcen(RCU_TypeDef *rcu) +{ + SET_BIT(rcu->APB2DSL, RCU_APB2DSL_ADCEN_MSK); +} +/** + * @brief ADC clock disable during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval None + */ +__STATIC_INLINE void md_rcu_disable_apb2dsl_adcen(RCU_TypeDef *rcu) +{ + CLEAR_BIT(rcu->APB2DSL, RCU_APB2DSL_ADCEN_MSK); +} +/** + * @brief Get ADC clock during Deep Sleep mode bit. + * @param rcu RCU Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_rcu_get_apb2dsl_adcen(RCU_TypeDef *rcu) +{ + return (READ_BIT(rcu->APB2DSL, RCU_APB2DSL_ADCEN_MSK)>>RCU_APB2DSL_ADCEN_POS); +} + +/** + * @} MD_RCU_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_RCU_Public_Functions RCU Public Functions + * @{ + */ + +/** @defgroup MD_RCU_PF_Basic_Configuration Basic Configuration + * @{ + */ +void md_rcu_init(void); +void md_rcu_init_set(RCU_TypeDef *, md_rcu_init_typedef *); +void md_rcu_pllreinit(uint8_t); +/** + * @} MD_RCU_PF_Basic_Configuration + */ + +/** + * @} MD_RCU_Public_Functions + */ + +#endif + +/** + * @} RCU + */ + +/** + * @} Micro_Driver + */ +#ifdef __cplusplus +} + +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rtc.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..4de23ae6289047d60cd0bbb71b4993641a5eaf74 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_rtc.h @@ -0,0 +1,2785 @@ +/** + ****************************************************************************** + * @file md_RTC.h + * @brief ES32F0271 RTC HEAD File. + * + * @version V1.00.02 + * @date 30/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_RTC_H__ +#define __MD_RTC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include +#include "es32f0271.h" +#include "reg_rtc.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (RTC) + +/** @defgroup RTC RTC + * @brief RTC micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_RTC_PT_INIT RTC Public Init structures + * @{ + */ + +/** + * @brief MD RTC Init Structure definition + */ + + +/** + * @} MD_RTC_PT_INIT + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_RTC_Public_Constants RTC Public Constants + * @{ + */ + +/** @defgroup MD_RTC_CON_MODE_ RTC Clock Calibration Mode + * @{ + */ +#define MD_RTC_CON_MODE_INCR (0x00000000UL) /** @brief Increase calibration value when match calibration cycle. */ +#define MD_RTC_CON_MODE_DECR (0X00000001UL) /** @brief DMA Decrease calibration value when match calibration cycle. */ +/** + * @} MD_RTC_CON_MODE_ + */ + +/** @defgroup MD_RTC_CON_CYCLE_ RTC Calibration Cycle Select + * @{ + */ +#define MD_RTC_CON_CYCLE_60S (0x00000000UL) /** @brief When enable Calibration Function, the calibrate cycle is 60s. */ +#define MD_RTC_CON_CYCLE_1S (0X00000001UL) /** @brief When enable Calibration Function, the calibrate cycle is 1s. */ +/** + * @} MD_RTC_CON_CYCLE_ + */ + +/** @defgroup MD_RTC_CON_CKSEL_ RTC Clock Source Selection + * @{ + */ +#define MD_RTC_CON_CKSEL_NO (0x00000000UL) /** @brief No clock */ +#define MD_RTC_CON_CKSEL_LOSC (0X00000001UL) /** @brief LOSC oscillator clock used as RTC clock */ +#define MD_RTC_CON_CKSEL_LRC (0x00000002UL) /** @brief LRC oscillator clock used as RTC clock */ +#define MD_RTC_CON_CKSEL_PLL (0X00000003UL) /** @brief PLL Reference clock source divided by 128 used as RTC clock */ +/** + * @} MD_RTC_CON_CKSEL_ + */ + +/** @defgroup MD_RTC_WKUP_WKSCAL RTC Wakeup Counter Scale Value + * @{ + */ +#define MD_RTC_WKUP_WKSCAL_DIV1 (0x00000000UL) /** @brief Divide 1, wakeup counter will count each second. */ +#define MD_RTC_WKUP_WKSCAL_DIV2 (0X00000001UL) /** @brief Divide 2, wakeup counter will count each 1/2 second. */ +#define MD_RTC_WKUP_WKSCAL_DIV4 (0x00000002UL) /** @brief Divide 4, wakeup counter will count each 1/4 second. */ +#define MD_RTC_WKUP_WKSCAL_DIV8 (0X00000003UL) /** @brief Divide 8, wakeup counter will count each 1/8 second. */ +#define MD_RTC_WKUP_WKSCAL_DIV16 (0X00000004UL) /** @brief Divide 16, wakeup counter will count each 1/16 second. */ +/** + * @} MD_RTC_WKUP_WKSCAL + */ + +/** @defgroup MD_RTC_WKUP_WKSEL RTC Wakeup Counter Events Select + * @{ + */ +#define MD_RTC_WKUP_WKSEL_OFF (0x00000000UL) /** @brief OFF */ +#define MD_RTC_WKUP_WKSEL_RTC (0X00000001UL) /** @brief Start counter when RTC start. */ +#define MD_RTC_WKUP_WKSEL_SLEEP (0x00000002UL) /** @brief Start counter when receive sleep flag. */ +/** + * @} MD_RTC_WKUP_WKSEL + */ + +/** @defgroup MD_RTC_STAT_SYNDONE RTC Calendar Synchronization status + * @{ + */ +#define MD_RTC_STAT_SYNDONE_UNDER (0x00000000UL) /** @brief RTC is under Synchronization procedure */ +#define MD_RTC_STAT_SYNDONE_CMP (0X00000001UL) /** @brief RTC Synchronization procedure is Completed */ +/** + * @} MD_RTC_STAT_SYNDONE + */ + +/** @defgroup MD_RTC_BKEN_BKEN Read RTC Backup Register Enable + * @{ + */ +#define MD_RTC_BKEN_BKEN_CONTROL (0x00000000UL) /** @brief Read RTCTIME & RTCCAL From control register. */ +#define MD_RTC_BKEN_BKEN_BACKUP (0X00000001UL) /** @brief Read RTCTIME & RTCCAL From backup register. */ +/** + * @} MD_RTC_BKEN_BKEN + */ + +/** + * @} MD_RTC_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_RTC_Public_Macros RTC Public Macros + * @{ + */ + +/** + * @brief Set RTC Clock Calibration Mode + * @param rtc RTC Instance + * @param mode can be one of the following values: + * @arg @ref MD_RTC_CON_MODE_INCR + * @arg @ref MD_RTC_CON_MODE_DECR + * @retval None + */ +__STATIC_INLINE void md_rtc_set_con_mode(RTC_TypeDef *rtc, uint32_t mode) +{ + MODIFY_REG(rtc->CON, RTC_CON_MODE_MSK, (mode<CON, RTC_CON_MODE_MSK)>>RTC_CON_MODE_POS); +} +/** + * @brief Set RTC Clock Calibration Value + * @param rtc RTC Instance + * @param calval Max calibration value is CALV. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_con_calval(RTC_TypeDef *rtc, uint32_t calval) +{ + MODIFY_REG(rtc->CON, RTC_CON_CALVAL_MSK, (calval<CON, RTC_CON_CALVAL_MSK)>>RTC_CON_CALVAL_POSS); +} +/** + * @brief Set RTC Clock Counter Scale + * @param rtc RTC Instance + * @param scale Max divider of This counter is (SCALE+1). + * @retval None + */ +__STATIC_INLINE void md_rtc_set_con_scale(RTC_TypeDef *rtc, uint32_t scale) +{ + MODIFY_REG(rtc->CON, RTC_CON_SCALE_MSK, (scale<CON, RTC_CON_SCALE_MSK)>>RTC_CON_SCALE_POSS); +} +/** + * @brief Set RTC Clock Counter Prescale + * @param rtc RTC Instance + * @param pscale Max divider of This counter is (PSCALE+1). + * @retval None + */ +__STATIC_INLINE void md_rtc_set_con_pscale(RTC_TypeDef *rtc, uint32_t pscale) +{ + MODIFY_REG(rtc->CON, RTC_CON_PSCALE_MSK, (pscale<CON, RTC_CON_PSCALE_MSK)>>RTC_CON_PSCALE_POSS); +} +/** + * @brief Set RTC Calibration Cycle Select + * @param rtc RTC Instance + * @param cycle This parameter can be one of the following values: + * @arg @ref MD_RTC_CON_CYCLE_60S + * @arg @ref MD_RTC_CON_CYCLE_1S + * @retval None + */ +__STATIC_INLINE void md_rtc_set_con_cycle(RTC_TypeDef *rtc, uint32_t cycle) +{ + MODIFY_REG(rtc->CON, RTC_CON_CYCLE_MSK, (cycle<CON, RTC_CON_CYCLE_MSK)>>RTC_CON_CYCLE_POS); +} +/** + * @brief Set RTC Calibration Function Enable + * @param rtc RTC Instance + * @param calib This parameter can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_con_calib(RTC_TypeDef *rtc, uint32_t calib) +{ + MODIFY_REG(rtc->CON, RTC_CON_CALIB_MSK, (calib<CON, RTC_CON_CALIB_MSK)>>RTC_CON_CALIB_POS); +} +/** + * @brief Set RTC Clock Source Selection + * @param rtc RTC Instance + * @param cksel This parameter can be one of the following values: + * @arg @ref MD_RTC_CON_CKSEL_NO + * @arg @ref MD_RTC_CON_CKSEL_LOSC + * @arg @ref MD_RTC_CON_CKSEL_LRC + * @arg @ref MD_RTC_CON_CKSEL_PLL + * @retval None + */ +__STATIC_INLINE void md_rtc_set_con_cksel(RTC_TypeDef *rtc, uint32_t cksel) +{ + MODIFY_REG(rtc->CON, RTC_CON_CKSEL_MSK, (cksel<CON, RTC_CON_CKSEL_MSK)>>RTC_CON_CKSEL_POSS); +} +/** + * @brief Set RTC Counter Enable bit + * @param rtc RTC Instance + * @param rtcen This parameter can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_con_rtcen(RTC_TypeDef *rtc, uint32_t rtcen) +{ + MODIFY_REG(rtc->CON, RTC_CON_RTCEN_MSK, (rtcen<CON, RTC_CON_RTCEN_MSK)>>RTC_CON_RTCEN_POS); +} + +/** @defgroup MD_RTC_CON_MODE MODE + * @brief Set RTC Clock Calibration Mode bit for md_rtc_set_con() function used + * @param mode This parameter can be one of the following values: + * @arg @ref MD_RTC_CON_MODE_INCR + * @arg @ref MD_RTC_CON_MODE_DECR + * @{ + */ +#define md_rtc_set_con_mode_fun(mode) (mode<CON, (mode|calval|scale|pscale|cycle|calib|cksel|rtcen)); +} + + +/** + * @brief Set RTC Wakeup Counter Scale Value + * @param rtc RTC Instance + * @param wkscal This parameter can be one of the following values: + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV1 + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV2 + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV4 + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV8 + * @arg @ref MD_RTC_WKUP_WKSCAL_DIV16 + * @retval None + */ +__STATIC_INLINE void md_rtc_set_wkup_wkscal(RTC_TypeDef *rtc, uint32_t wkscal) +{ + MODIFY_REG(rtc->WKUP, RTC_WKUP_WKSCAL_MSK, (wkscal<WKUP, RTC_WKUP_WKSCAL_MSK)>>RTC_WKUP_WKSCAL_POSS); +} +/** + * @brief Set RTC Wakeup Counter Events Select + * @param rtc RTC Instance + * @param wksel This parameter can be one of the following values: + * @arg @ref MD_RTC_WKUP_WKSEL_OFF + * @arg @ref MD_RTC_WKUP_WKSEL_RTC + * @arg @ref MD_RTC_WKUP_WKSEL_SLEEP + * @retval None + */ +__STATIC_INLINE void md_rtc_set_wkup_wksel(RTC_TypeDef *rtc, uint32_t wksel) +{ + MODIFY_REG(rtc->WKUP, RTC_WKUP_WKSEL_MSK, (wksel<WKUP, RTC_WKUP_WKSEL_MSK)>>RTC_WKUP_WKSEL_POSS); +} +/** + * @brief Set RTC Wakeup Counter setting value + * @param rtc RTC Instance + * @param wkcal Max value is WKCAL seconds + * @retval None + */ +__STATIC_INLINE void md_rtc_set_wkup_wkcal(RTC_TypeDef *rtc, uint32_t wkcal) +{ + MODIFY_REG(rtc->WKUP, RTC_WKUP_WKCAL_MSK, (wkcal<WKUP, RTC_WKUP_WKCAL_MSK)>>RTC_WKUP_WKCAL_POSS); +} + + +/** + * @brief Set Week Value + * @param rtc RTC Instance + * @param week value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_week(RTC_TypeDef *rtc, uint32_t week) +{ + MODIFY_REG(rtc->TIME, RTC_TIME_WEEK_MSK, (week<TIME, RTC_TIME_WEEK_MSK)>>RTC_TIME_WEEK_POSS); +} +/** + * @brief Set Hour Tens Value + * @param rtc RTC Instance + * @param hour_t Hour tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_hour_t(RTC_TypeDef *rtc, uint32_t hour_t) +{ + MODIFY_REG(rtc->TIME, RTC_TIME_HOUR_T_MSK, (hour_t<TIME, RTC_TIME_HOUR_T_MSK)>>RTC_TIME_HOUR_T_POSS); +} +/** + * @brief Set Hour Units Value + * @param rtc RTC Instance + * @param hour_u Hour units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_hour_u(RTC_TypeDef *rtc, uint32_t hour_u) +{ + MODIFY_REG(rtc->TIME, RTC_TIME_HOUR_U_MSK, (hour_u<TIME, RTC_TIME_HOUR_U_MSK)>>RTC_TIME_HOUR_U_POSS); +} +/** + * @brief Set Minute Tens Value + * @param rtc RTC Instance + * @param min_t Minute tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_min_t(RTC_TypeDef *rtc, uint32_t min_t) +{ + MODIFY_REG(rtc->TIME, RTC_TIME_MIN_T_MSK, (min_t<TIME, RTC_TIME_MIN_T_MSK)>>RTC_TIME_MIN_T_POSS); +} +/** + * @brief Set Minute Units Value + * @param rtc RTC Instance + * @param min_u Minute units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_min_u(RTC_TypeDef *rtc, uint32_t min_u) +{ + MODIFY_REG(rtc->TIME, RTC_TIME_MIN_U_MSK, (min_u<TIME, RTC_TIME_MIN_U_MSK)>>RTC_TIME_MIN_U_POSS); +} +/** + * @brief Set Second Tens Value + * @param rtc RTC Instance + * @param sec_t Second tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_sec_t(RTC_TypeDef *rtc, uint32_t sec_t) +{ + MODIFY_REG(rtc->TIME, RTC_TIME_SEC_T_MSK, (sec_t<TIME, RTC_TIME_SEC_T_MSK)>>RTC_TIME_SEC_T_POSS); +} +/** + * @brief Set Second Units Value + * @param rtc RTC Instance + * @param sec_u Second units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_time_sec_u(RTC_TypeDef *rtc, uint32_t sec_u) +{ + MODIFY_REG(rtc->TIME, RTC_TIME_SEC_U_MSK, (sec_u<TIME, RTC_TIME_SEC_U_MSK)>>RTC_TIME_SEC_U_POSS); +} + +/** @defgroup MD_RTC_TIME_WEEK WEEK + * @brief Set Week Value bit bit for md_rtc_set_time() function used + * @param week value in RTC timer, in BCD format. + * @{ + */ +#define md_rtc_set_time_week_fun(week) (week<TIME, (week|hour_t|hour_u|min_t|min_u|sec_t|sec_u)); +} + + + + + + + + + + +/** + * @brief Set Year Tens Value + * @param rtc RTC Instance + * @param year_t Year tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_cal_year_t(RTC_TypeDef *rtc, uint32_t year_t) +{ + MODIFY_REG(rtc->CAL, RTC_CAL_YEAR_T_MSK, (year_t<CAL, RTC_CAL_YEAR_T_MSK)>>RTC_CAL_YEAR_T_POSS); +} +/** + * @brief Set Year Units Value + * @param rtc RTC Instance + * @param year_u Year units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_cal_year_u(RTC_TypeDef *rtc, uint32_t year_u) +{ + MODIFY_REG(rtc->CAL, RTC_CAL_YEAR_U_MSK, (year_u<CAL, RTC_CAL_YEAR_U_MSK)>>RTC_CAL_YEAR_U_POSS); +} +/** + * @brief Set Month Tens Value + * @param rtc RTC Instance + * @param mon_t Month tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_cal_mon_t(RTC_TypeDef *rtc, uint32_t mon_t) +{ + MODIFY_REG(rtc->CAL, RTC_CAL_MON_T_MSK, (mon_t<CAL, RTC_CAL_MON_T_MSK)>>RTC_CAL_MON_T_POS); +} +/** + * @brief Set Month Units Value + * @param rtc RTC Instance + * @param mon_u Month units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_cal_mon_u(RTC_TypeDef *rtc, uint32_t mon_u) +{ + MODIFY_REG(rtc->CAL, RTC_CAL_MON_U_MSK, (mon_u<CAL, RTC_CAL_MON_U_MSK)>>RTC_CAL_MON_U_POSS); +} +/** + * @brief Set Date Tens Value + * @param rtc RTC Instance + * @param date_t Date tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_cal_date_t(RTC_TypeDef *rtc, uint32_t date_t) +{ + MODIFY_REG(rtc->CAL, RTC_CAL_DATE_T_MSK, (date_t<CAL, RTC_CAL_DATE_T_MSK)>>RTC_CAL_DATE_T_POSS); +} +/** + * @brief Set Date Units Value + * @param rtc RTC Instance + * @param date_u Date units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_cal_date_u(RTC_TypeDef *rtc, uint32_t date_u) +{ + MODIFY_REG(rtc->CAL, RTC_CAL_DATE_U_MSK, (date_u<CAL, RTC_CAL_DATE_U_MSK)>>RTC_CAL_DATE_U_POSS); +} + +/** + * @brief Set Alarm Week Value + * @param rtc RTC Instance + * @param week Alarm Week value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_altime_week(RTC_TypeDef *rtc, uint32_t week) +{ + MODIFY_REG(rtc->ALTIME, RTC_ALTIME_WEEK_MSK, (week<ALTIME, RTC_ALTIME_WEEK_MSK)>>RTC_ALTIME_WEEK_POSS); +} +/** + * @brief Set Alarm Hour Tens Value + * @param rtc RTC Instance + * @param hour_t Alarm Hour tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_altime_hour_t(RTC_TypeDef *rtc, uint32_t hour_t) +{ + MODIFY_REG(rtc->ALTIME, RTC_ALTIME_HOUR_T_MSK, (hour_t<ALTIME, RTC_ALTIME_HOUR_T_MSK)>>RTC_ALTIME_HOUR_T_POSS); +} +/** + * @brief Set Alarm Hour Units Value + * @param rtc RTC Instance + * @param hour_u Alarm Hour units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_altime_hour_u(RTC_TypeDef *rtc, uint32_t hour_u) +{ + MODIFY_REG(rtc->ALTIME, RTC_ALTIME_HOUR_U_MSK, (hour_u<ALTIME, RTC_ALTIME_HOUR_U_MSK)>>RTC_ALTIME_HOUR_U_POSS); +} +/** + * @brief Set Alarm Minute Tens Value + * @param rtc RTC Instance + * @param min_t Alarm Minute tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_altime_min_t(RTC_TypeDef *rtc, uint32_t min_t) +{ + MODIFY_REG(rtc->ALTIME, RTC_ALTIME_MIN_T_MSK, (min_t<ALTIME, RTC_ALTIME_MIN_T_MSK)>>RTC_ALTIME_MIN_T_POSS); +} +/** + * @brief Set Alarm Minute Units Value + * @param rtc RTC Instance + * @param min_u Alarm Minute units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_altime_min_u(RTC_TypeDef *rtc, uint32_t min_u) +{ + MODIFY_REG(rtc->ALTIME, RTC_ALTIME_MIN_U_MSK, (min_u<ALTIME, RTC_ALTIME_MIN_U_MSK)>>RTC_ALTIME_MIN_U_POSS); +} +/** + * @brief Set Alarm Second Tens Value + * @param rtc RTC Instance + * @param sec_t Alarm Second tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_altime_sec_t(RTC_TypeDef *rtc, uint32_t sec_t) +{ + MODIFY_REG(rtc->ALTIME, RTC_ALTIME_SEC_T_MSK, (sec_t<ALTIME, RTC_ALTIME_SEC_T_MSK)>>RTC_ALTIME_SEC_T_POSS); +} +/** + * @brief Set Alarm Second Units Value + * @param rtc RTC Instance + * @param sec_u Alarm Second units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_altime_sec_u(RTC_TypeDef *rtc, uint32_t sec_u) +{ + MODIFY_REG(rtc->ALTIME, RTC_ALTIME_SEC_U_MSK, (sec_u<ALTIME, RTC_ALTIME_SEC_U_MSK)>>RTC_ALTIME_SEC_U_POSS); +} + +/** + * @brief Set Alarm Year Tens Value + * @param rtc RTC Instance + * @param year_t Alarm Year tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alcal_year_t(RTC_TypeDef *rtc, uint32_t year_t) +{ + MODIFY_REG(rtc->ALCAL, RTC_ALCAL_YEAR_T_MSK, (year_t<ALCAL, RTC_ALCAL_YEAR_T_MSK)>>RTC_ALCAL_YEAR_T_POSS); +} +/** + * @brief Set Alarm Year Units Value + * @param rtc RTC Instance + * @param year_u Alarm Year units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alcal_year_u(RTC_TypeDef *rtc, uint32_t year_u) +{ + MODIFY_REG(rtc->ALCAL, RTC_ALCAL_YEAR_U_MSK, (year_u<ALCAL, RTC_ALCAL_YEAR_U_MSK)>>RTC_ALCAL_YEAR_U_POSS); +} +/** + * @brief Set Alarm Month Tens Value + * @param rtc RTC Instance + * @param mon_t Alarm Month tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alcal_mon_t(RTC_TypeDef *rtc, uint32_t mon_t) +{ + MODIFY_REG(rtc->ALCAL, RTC_ALCAL_MON_T_MSK, (mon_t<ALCAL, RTC_ALCAL_MON_T_MSK)>>RTC_ALCAL_MON_T_POS); +} +/** + * @brief Set Alarm Month Units Value + * @param rtc RTC Instance + * @param mon_u Alarm Month units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alcal_mon_u(RTC_TypeDef *rtc, uint32_t mon_u) +{ + MODIFY_REG(rtc->ALCAL, RTC_ALCAL_MON_U_MSK, (mon_u<ALCAL, RTC_ALCAL_MON_U_MSK)>>RTC_ALCAL_MON_U_POSS); +} +/** + * @brief Set Alarm Date Tens Value + * @param rtc RTC Instance + * @param date_t Alarm Date tens value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alcal_date_t(RTC_TypeDef *rtc, uint32_t date_t) +{ + MODIFY_REG(rtc->ALCAL, RTC_ALCAL_DATE_T_MSK, (date_t<ALCAL, RTC_ALCAL_DATE_T_MSK)>>RTC_ALCAL_DATE_T_POSS); +} +/** + * @brief Set Alarm Date Units Value + * @param rtc RTC Instance + * @param date_u Alarm Date units value in RTC timer, in BCD format. + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alcal_date_u(RTC_TypeDef *rtc, uint32_t date_u) +{ + MODIFY_REG(rtc->ALCAL, RTC_ALCAL_DATE_U_MSK, (date_u<ALCAL, RTC_ALCAL_DATE_U_MSK)>>RTC_ALCAL_DATE_U_POSS); +} + +/** + * @brief Set Year Alarm Function Enable + * @param rtc RTC Instance + * @param year can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alen_year(RTC_TypeDef *rtc, uint32_t year) +{ + MODIFY_REG(rtc->ALEN, RTC_ALEN_YEAR_MSK, (year<ALEN, RTC_ALEN_YEAR_MSK)>>RTC_ALEN_YEAR_POS); +} +/** + * @brief Set Month Alarm Function Enable + * @param rtc RTC Instance + * @param month can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alen_month(RTC_TypeDef *rtc, uint32_t month) +{ + MODIFY_REG(rtc->ALEN, RTC_ALEN_MONTH_MSK, (month<ALEN, RTC_ALEN_MONTH_MSK)>>RTC_ALEN_MONTH_POS); +} +/** + * @brief Set Date Alarm Function Enable + * @param rtc RTC Instance + * @param date can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alen_date(RTC_TypeDef *rtc, uint32_t date) +{ + MODIFY_REG(rtc->ALEN, RTC_ALEN_DATE_MSK, (date<ALEN, RTC_ALEN_DATE_MSK)>>RTC_ALEN_DATE_POS); +} +/** + * @brief Set Week Alarm Function Enable + * @param rtc RTC Instance + * @param week can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alen_week(RTC_TypeDef *rtc, uint32_t week) +{ + MODIFY_REG(rtc->ALEN, RTC_ALEN_WEEK_MSK, (week<ALEN, RTC_ALEN_WEEK_MSK)>>RTC_ALEN_WEEK_POS); +} +/** + * @brief Set Hour Alarm Function Enable + * @param rtc RTC Instance + * @param hour can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alen_hour(RTC_TypeDef *rtc, uint32_t hour) +{ + MODIFY_REG(rtc->ALEN, RTC_ALEN_HOUR_MSK, (hour<ALEN, RTC_ALEN_HOUR_MSK)>>RTC_ALEN_HOUR_POS); +} +/** + * @brief Set Minute Alarm Function Enable + * @param rtc RTC Instance + * @param min can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alen_min(RTC_TypeDef *rtc, uint32_t min) +{ + MODIFY_REG(rtc->ALEN, RTC_ALEN_MIN_MSK, (min<ALEN, RTC_ALEN_MIN_MSK)>>RTC_ALEN_MIN_POS); +} +/** + * @brief Set Second Alarm Function Enable + * @param rtc RTC Instance + * @param sec can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_alen_sec(RTC_TypeDef *rtc, uint32_t sec) +{ + MODIFY_REG(rtc->ALEN, RTC_ALEN_SEC_MSK, (sec<ALEN, RTC_ALEN_SEC_MSK)>>RTC_ALEN_SEC_POS); +} + +/** + * @brief Set RTC Wakeup Counter Match Trigger Enable + * @param rtc RTC Instance + * @param wktm can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_wktm(RTC_TypeDef *rtc, uint32_t wktm) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_WKTM_MSK, (wktm<TRIG, RTC_TRIG_WKTM_MSK)>>RTC_TRIG_WKTM_POS); +} +/** + * @brief Set RTC 1 Hz Trigger Enable + * @param rtc RTC Instance + * @param f1hz can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_f1hz(RTC_TypeDef *rtc, uint32_t f1hz) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_F1HZ_MSK, (f1hz<TRIG, RTC_TRIG_F1HZ_MSK)>>RTC_TRIG_F1HZ_POS); +} +/** + * @brief Set RTC Year Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @param ryear can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_ryear(RTC_TypeDef *rtc, uint32_t ryear) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_RYEAR_MSK, (ryear<TRIG, RTC_TRIG_RYEAR_MSK)>>RTC_TRIG_RYEAR_POS); +} +/** + * @brief Set RTC Month Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @param rmon can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_rmon(RTC_TypeDef *rtc, uint32_t rmon) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_RMON_MSK, (rmon<TRIG, RTC_TRIG_RMON_MSK)>>RTC_TRIG_RMON_POS); +} +/** + * @brief Set RTC Date Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @param rdate can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_rdate(RTC_TypeDef *rtc, uint32_t rdate) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_RDATE_MSK, (rdate<TRIG, RTC_TRIG_RDATE_MSK)>>RTC_TRIG_RDATE_POS); +} +/** + * @brief Set RTC Week Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @param rweek can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_rweek(RTC_TypeDef *rtc, uint32_t rweek) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_RWEEK_MSK, (rweek<TRIG, RTC_TRIG_RWEEK_MSK)>>RTC_TRIG_RWEEK_POS); +} +/** + * @brief Set RTC Hour Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @param rhour can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_rhour(RTC_TypeDef *rtc, uint32_t rhour) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_RHOUR_MSK, (rhour<TRIG, RTC_TRIG_RHOUR_MSK)>>RTC_TRIG_RHOUR_POS); +} +/** + * @brief Set RTC Minute Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @param rmin can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_rmin(RTC_TypeDef *rtc, uint32_t rmin) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_RMIN_MSK, (rmin<TRIG, RTC_TRIG_RMIN_MSK)>>RTC_TRIG_RMIN_POS); +} +/** + * @brief Set RTC Second Roll Alarm Trigger Enable + * @param rtc RTC Instance + * @param rsec can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_rsec(RTC_TypeDef *rtc, uint32_t rsec) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_RSEC_MSK, (rsec<TRIG, RTC_TRIG_RSEC_MSK)>>RTC_TRIG_RSEC_POS); +} +/** + * @brief Set RTC Match All Alarm Trigger Enable + * @param rtc RTC Instance + * @param amall can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_amall(RTC_TypeDef *rtc, uint32_t amall) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_AMALL_MSK, (amall<TRIG, RTC_TRIG_AMALL_MSK)>>RTC_TRIG_AMALL_POS); +} +/** + * @brief Set RTC Match Year Alarm Trigger Enable + * @param rtc RTC Instance + * @param ayear can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_ayear(RTC_TypeDef *rtc, uint32_t ayear) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_AYEAR_MSK, (ayear<TRIG, RTC_TRIG_AYEAR_MSK)>>RTC_TRIG_AYEAR_POS); +} +/** + * @brief Set RTC Match Month Alarm Trigger Enable + * @param rtc RTC Instance + * @param amon can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_amon(RTC_TypeDef *rtc, uint32_t amon) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_AMON_MSK, (amon<TRIG, RTC_TRIG_AMON_MSK)>>RTC_TRIG_AMON_POS); +} +/** + * @brief Set RTC Match Date Alarm Trigger Enable + * @param rtc RTC Instance + * @param adate can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_adate(RTC_TypeDef *rtc, uint32_t adate) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_ADTAE_MSK, (adate<TRIG, RTC_TRIG_ADTAE_MSK)>>RTC_TRIG_ADTAE_POS); +} +/** + * @brief Set RTC Match Week Alarm Trigger Enable + * @param rtc RTC Instance + * @param aweek can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_aweek(RTC_TypeDef *rtc, uint32_t aweek) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_AWEEK_MSK, (aweek<TRIG, RTC_TRIG_AWEEK_MSK)>>RTC_TRIG_AWEEK_POS); +} +/** + * @brief Set RTC Match Hour Alarm Trigger Enable + * @param rtc RTC Instance + * @param ahour can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_ahour(RTC_TypeDef *rtc, uint32_t ahour) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_AHOUR_MSK, (ahour<TRIG, RTC_TRIG_AHOUR_MSK)>>RTC_TRIG_AHOUR_POS); +} +/** + * @brief Set RTC Match Minute Alarm Trigger Enable + * @param rtc RTC Instance + * @param amin can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_amin(RTC_TypeDef *rtc, uint32_t amin) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_AMIN_MSK, (amin<TRIG, RTC_TRIG_AMIN_MSK)>>RTC_TRIG_AMIN_POS); +} +/** + * @brief Set RTC Match Second Alarm Trigger Enable + * @param rtc RTC Instance + * @param asec can be one of the following values: + * @arg DISABLE + * @arg ENABLE + * @retval None + */ +__STATIC_INLINE void md_rtc_set_trig_asec(RTC_TypeDef *rtc, uint32_t asec) +{ + MODIFY_REG(rtc->TRIG, RTC_TRIG_ASEC_MSK, (asec<TRIG, RTC_TRIG_ASEC_MSK)>>RTC_TRIG_ASEC_POS); +} + +/** + * @brief Set RTC Wakeup Counter Match Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_wktm(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_WKTM_MSK); +} +/** + * @brief Set RTC 1 Hz Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_f1hz(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_F1HZ_MSK); +} +/** + * @brief Set RTC Year Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_ryear(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RYEAR_MSK); +} +/** + * @brief Set RTC Month Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_rmon(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RMON_MSK); +} +/** + * @brief Set RTC Date Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_rdate(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RDATE_MSK); +} +/** + * @brief Set RTC Week Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_rweek(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RWEEK_MSK); +} +/** + * @brief Set RTC Hour Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_rhour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RHOUR_MSK); +} +/** + * @brief Set RTC Minute Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_rmin(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RMIN_MSK); +} +/** + * @brief Set RTC Second Roll Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_rsec(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_RSEC_MSK); +} +/** + * @brief Set RTC Match All Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_amall(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AMALL_MSK); +} +/** + * @brief Set RTC Match Year Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_ayear(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AYEAR_MSK); +} +/** + * @brief Set RTC Match Month Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_amon(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AMON_MSK); +} +/** + * @brief Set RTC Match Date Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_adate(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_ADTAE_MSK); +} +/** + * @brief Set RTC Match Week Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_aweek(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AWEEK_MSK); +} +/** + * @brief Set RTC Match Hour Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_ahour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AHOUR_MSK); +} +/** + * @brief Set RTC Match Minute Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_amin(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_AMIN_MSK); +} +/** + * @brief Set RTC Match Second Alarm Interrupt Enable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_ier_asec(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IER, RTC_IER_ASEC_MSK); +} + +/** + * @brief Set RTC Wakeup Counter Match Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_wktm(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_WKTM_MSK); +} +/** + * @brief Set RTC 1 Hz Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_f1hz(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_F1HZ_MSK); +} +/** + * @brief Set RTC Year Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_ryear(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RYEAR_MSK); +} +/** + * @brief Set RTC Month Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_rmon(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RMON_MSK); +} +/** + * @brief Set RTC Date Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_rdate(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RDATE_MSK); +} +/** + * @brief Set RTC Week Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_rweek(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RWEEK_MSK); +} +/** + * @brief Set RTC Hour Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_rhour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RHOUR_MSK); +} +/** + * @brief Set RTC Minute Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_rmin(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RMIN_MSK); +} +/** + * @brief Set RTC Second Roll Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_rsec(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_RSEC_MSK); +} +/** + * @brief Set RTC Match All Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_amall(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AMALL_MSK); +} +/** + * @brief Set RTC Match Year Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_ayear(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AYEAR_MSK); +} +/** + * @brief Set RTC Match Month Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_amon(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AMON_MSK); +} +/** + * @brief Set RTC Match Date Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_adate(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_ADTAE_MSK); +} +/** + * @brief Set RTC Match Week Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_aweek(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AWEEK_MSK); +} +/** + * @brief Set RTC Match Hour Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_ahour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AHOUR_MSK); +} +/** + * @brief Set RTC Match Minute Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_amin(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_AMIN_MSK); +} +/** + * @brief Set RTC Match Second Alarm Interrupt Disable bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_enable_idr_asec(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->IDR, RTC_IDR_ASEC_MSK); +} + +/** + * @brief Get RTC Wakeup Counter Match Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_wktm(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_WKTM_MSK)>>RTC_IVS_WKTM_POS); +} +/** + * @brief Get RTC 1 Hz Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_f1hz(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_F1HZ_MSK)>>RTC_IVS_F1HZ_POS); +} +/** + * @brief Get RTC Year Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_ryear(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RYEAR_MSK)>>RTC_IVS_RYEAR_POS); +} +/** + * @brief Get RTC Month Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_rmon(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RMON_MSK)>>RTC_IVS_RMON_POS); +} +/** + * @brief Get RTC Date Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_rdate(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RDATE_MSK)>>RTC_IVS_RDATE_POS); +} +/** + * @brief Get RTC Week Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_rweek(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RWEEK_MSK)>>RTC_IVS_RWEEK_POS); +} +/** + * @brief Get RTC Hour Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_rhour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RHOUR_MSK)>>RTC_IVS_RHOUR_POS); +} +/** + * @brief Get RTC Minute Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_rmin(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RMIN_MSK)>>RTC_IVS_RMIN_POS); +} +/** + * @brief Get RTC Second Roll Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_rsec(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_RSEC_MSK)>>RTC_IVS_RSEC_POS); +} +/** + * @brief Get RTC Match All Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_amall(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AMALL_MSK)>>RTC_IVS_AMALL_POS); +} +/** + * @brief Get RTC Match Year Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_ayear(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AYEAR_MSK)>>RTC_IVS_AYEAR_POS); +} +/** + * @brief Get RTC Match Month Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_amon(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AMON_MSK)>>RTC_IVS_AMON_POS); +} +/** + * @brief Get RTC Match Date Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_adate(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_ADTAE_MSK)>>RTC_IVS_ADTAE_POS); +} +/** + * @brief Get RTC Match Week Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_aweek(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AWEEK_MSK)>>RTC_IVS_AWEEK_POS); +} +/** + * @brief Get RTC Match Hour Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_ahour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AHOUR_MSK)>>RTC_IVS_AHOUR_POS); +} +/** + * @brief Get RTC Match Minute Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_amin(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_AMIN_MSK)>>RTC_IVS_AMIN_POS); +} +/** + * @brief Get RTC Match Second Alarm Interrupt Valid Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ivs_asec(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IVS, RTC_IVS_ASEC_MSK)>>RTC_IVS_ASEC_POS); +} + +/** + * @brief Get RTC Wakeup Counter Match Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_wktm(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_WKTM_MSK)>>RTC_RIF_WKTM_POS); +} +/** + * @brief Get RTC 1 Hz Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_f1hz(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_F1HZ_MSK)>>RTC_RIF_F1HZ_POS); +} +/** + * @brief Get RTC Year Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_ryear(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RYEAR_MSK)>>RTC_RIF_RYEAR_POS); +} +/** + * @brief Get RTC Month Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_rmon(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RMON_MSK)>>RTC_RIF_RMON_POS); +} +/** + * @brief Get RTC Date Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_rdate(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RDATE_MSK)>>RTC_RIF_RDATE_POS); +} +/** + * @brief Get RTC Week Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_rweek(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RWEEK_MSK)>>RTC_RIF_RWEEK_POS); +} +/** + * @brief Get RTC Hour Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_rhour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RHOUR_MSK)>>RTC_RIF_RHOUR_POS); +} +/** + * @brief Get RTC Minute Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_rmin(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RMIN_MSK)>>RTC_RIF_RMIN_POS); +} +/** + * @brief Get RTC Second Roll Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_rsec(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_RSEC_MSK)>>RTC_RIF_RSEC_POS); +} +/** + * @brief Get RTC Match All Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_amall(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AMALL_MSK)>>RTC_RIF_AMALL_POS); +} +/** + * @brief Get RTC Match Year Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_ayear(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AYEAR_MSK)>>RTC_RIF_AYEAR_POS); +} +/** + * @brief Get RTC Match Month Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_amon(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AMON_MSK)>>RTC_RIF_AMON_POS); +} +/** + * @brief Get RTC Match Date Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_adate(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_ADTAE_MSK)>>RTC_RIF_ADTAE_POS); +} +/** + * @brief Get RTC Match Week Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_aweek(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AWEEK_MSK)>>RTC_RIF_AWEEK_POS); +} +/** + * @brief Get RTC Match Hour Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_ahour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AHOUR_MSK)>>RTC_RIF_AHOUR_POS); +} +/** + * @brief Get RTC Match Minute Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_amin(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_AMIN_MSK)>>RTC_RIF_AMIN_POS); +} +/** + * @brief Get RTC Match Second Alarm Raw Interrupt Flag Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_rif_asec(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->RIF, RTC_RIF_ASEC_MSK)>>RTC_RIF_ASEC_POS); +} + +/** + * @brief Get RTC Wakeup Counter Match Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_wktm(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_WKTM_MSK)>>RTC_IFM_WKTM_POS); +} +/** + * @brief Get RTC 1 Hz Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_f1hz(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_F1HZ_MSK)>>RTC_IFM_F1HZ_POS); +} +/** + * @brief Get RTC Year Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_ryear(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RYEAR_MSK)>>RTC_IFM_RYEAR_POS); +} +/** + * @brief Get RTC Month Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_rmon(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RMON_MSK)>>RTC_IFM_RMON_POS); +} +/** + * @brief Get RTC Date Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_rdate(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RDATE_MSK)>>RTC_IFM_RDATE_POS); +} +/** + * @brief Get RTC Week Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_rweek(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RWEEK_MSK)>>RTC_IFM_RWEEK_POS); +} +/** + * @brief Get RTC Hour Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_rhour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RHOUR_MSK)>>RTC_IFM_RHOUR_POS); +} +/** + * @brief Get RTC Minute Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_rmin(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RMIN_MSK)>>RTC_IFM_RMIN_POS); +} +/** + * @brief Get RTC Second Roll Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_rsec(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_RSEC_MSK)>>RTC_IFM_RSEC_POS); +} +/** + * @brief Get RTC Match All Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_amall(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AMALL_MSK)>>RTC_IFM_AMALL_POS); +} +/** + * @brief Get RTC Match Year Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_ayear(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AYEAR_MSK)>>RTC_IFM_AYEAR_POS); +} +/** + * @brief Get RTC Match Month Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_amon(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AMON_MSK)>>RTC_IFM_AMON_POS); +} +/** + * @brief Get RTC Match Date Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_adate(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_ADTAE_MSK)>>RTC_IFM_ADTAE_POS); +} +/** + * @brief Get RTC Match Week Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_aweek(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AWEEK_MSK)>>RTC_IFM_AWEEK_POS); +} +/** + * @brief Get RTC Match Hour Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_ahour(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AHOUR_MSK)>>RTC_IFM_AHOUR_POS); +} +/** + * @brief Get RTC Match Minute Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_amin(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_AMIN_MSK)>>RTC_IFM_AMIN_POS); +} +/** + * @brief Get RTC Match Second Alarm Interrupt Flag Masked Status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg DISABLE + * @arg ENABLE + */ +__STATIC_INLINE uint32_t md_rtc_get_ifm_asec(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->IFM, RTC_IFM_ASEC_MSK)>>RTC_IFM_ASEC_POS); +} + +/** + * @brief Set RTC Wakeup Counter Match Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_wktm(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_WKTM_MSK); +} +/** + * @brief Set RTC 1 Hz Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_f1hz(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_F1HZ_MSK); +} +/** + * @brief Set RTC Year Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_ryear(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RYEAR_MSK); +} +/** + * @brief Set RTC Month Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_rmon(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RMON_MSK); +} +/** + * @brief Set RTC Date Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_rdate(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RDATE_MSK); +} +/** + * @brief Set RTC Week Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_rweek(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RWEEK_MSK); +} +/** + * @brief Set RTC Hour Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_rhour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RHOUR_MSK); +} +/** + * @brief Set RTC Minute Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_rmin(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RMIN_MSK); +} +/** + * @brief Set RTC Second Roll Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_rsec(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_RSEC_MSK); +} +/** + * @brief Set RTC Match All Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_amall(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AMALL_MSK); +} +/** + * @brief Set RTC Match Year Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_ayear(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AYEAR_MSK); +} +/** + * @brief Set RTC Match Month Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_amon(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AMON_MSK); +} +/** + * @brief Set RTC Match Date Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_adate(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_ADTAE_MSK); +} +/** + * @brief Set RTC Match Week Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_aweek(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AWEEK_MSK); +} +/** + * @brief Set RTC Match Hour Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_ahour(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AHOUR_MSK); +} +/** + * @brief Set RTC Match Minute Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_amin(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_AMIN_MSK); +} +/** + * @brief Set RTC Match Second Alarm Interrupt Clear bit + * @param rtc RTC Instance + * @retval None + */ +__STATIC_INLINE void md_rtc_clear_icr_asec(RTC_TypeDef *rtc) +{ + SET_BIT(rtc->ICR, RTC_ICR_ASEC_MSK); +} + +/** + * @brief Get RTC Calendar Synchronization status bit + * @param rtc RTC Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_RTC_STAT_SYNDONE_UNDER + * @arg @ref MD_RTC_STAT_SYNDONE_CMP + */ +__STATIC_INLINE uint32_t md_rtc_get_stat_syndone(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->STAT, RTC_STAT_SYNDONE_MSK)>>RTC_STAT_SYNDONE_POS); +} +/** + * @brief Get RTC Calendar Status bit + * @param rtc RTC Instance + * @retval State of bit (1 or 0). + * @note 0 = RTC calendar is not empty + * 1 = RTC calendar is empty + */ +__STATIC_INLINE uint32_t md_rtc_get_stat_empty(RTC_TypeDef *rtc) +{ + return (READ_BIT(rtc->STAT, RTC_STAT_EMPTY_MSK)>>RTC_STAT_EMPTY_POS); +} + +/** + * @brief Set Read RTC Backup Register Enable bit + * @param rtc RTC Instance + * @param bken can be one of the following values: + * @arg @ref MD_RTC_BKEN_BKEN_CONTROL + * @arg @ref MD_RTC_BKEN_BKEN_BACKUP + * @retval None + */ +__STATIC_INLINE void md_rtc_set_bken_bken(RTC_TypeDef *rtc, uint32_t bken) +{ + MODIFY_REG(rtc->BKEN, RTC_BKEN_BKEN_MSK, (bken<BKEN, RTC_BKEN_BKEN_MSK)>>RTC_BKEN_BKEN_POS); +} + +/** + * @} MD_RTC_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_RTC_Public_Functions RTC Public Functions + * @{ + */ + +/** @defgroup MD_RTC_PF_Basic_Configuration Basic Configuration + * @{ + */ + +/** + * @} MD_RTC_PF_Basic_Configuration + */ + +/** @defgroup MD_RTC_PF_Data_Access Data Access + * @{ + */ + +/** + * @} MD_RTC_PF_Data_Access + */ + +/** @defgroup MD_RTC_PF_Init Initialization and de-initialization functions + * @{ + */ + +/** + * @} MD_RTC_PF_Init + */ + +/** + * @} MD_RTC_Public_Functions + */ + +#endif + +/** + * @} RTC + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} + +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_spi.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..74f01e6312de04f956ed7b4292496531c3c21183 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_spi.h @@ -0,0 +1,2523 @@ +/** + ****************************************************************************** + * @file md_spi.h + * @brief ES32F0271 SPI Head File. + * + * @version V1.00.01 + * @date 06/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_SPI_H__ +#define __MD_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_spi.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (SPI1) || defined (SPI2) + +/** @defgroup SPI SPI + * @brief SPI micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_SPI_Public_Types SPI Public Types + * @{ + */ + +/** @defgroup MD_SPI_PT_INIT SPI Public Init structure + * @{ + */ + +/** + * @brief SPI Init structure. + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref MD_SPI_PC_MODE. + + This feature can be modified afterwards using unitary function @ref md_spi_set_con1_mstren().*/ + + uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref MD_SPI_PC_PHASE. + + This feature can be modified afterwards using unitary function @ref md_spi_set_con1_cpha().*/ + + uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref MD_SPI_PC_POLARITY. + + This feature can be modified afterwards using unitary function @ref md_spi_get_con1_cpol().*/ + + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref MD_SPI_PC_BAUDRATEPRESCALER. + @note The communication clock is derived from the master clock. The slave clock does not need to be set. + + This feature can be modified afterwards using unitary function @ref md_spi_set_con1_baud().*/ + + uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref MD_SPI_PC_BIT_ORDER. + + This feature can be modified afterwards using unitary function @ref md_spi_set_con1_lsbfirst().*/ + + uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref MD_SPI_PC_TRANSFER_DIRECTION. + + This feature can be modified afterwards using unitary function @ref md_spi_set_con1_bidimode().*/ + + uint32_t DataWidth; /*!< Specifies the SPI data width. + This parameter can be a value of @ref MD_SPI_PC_FRAME_FORMAT. + + This feature can be modified afterwards using unitary function @ref md_spi_set_con1_dlen().*/ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref MD_SPI_PC_NSS_MODE. + + This feature can be modified afterwards using unitary function @ref md_spi_set_con1_ssout().*/ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref MD_SPI_EC_CRC_CALCULATION. + + This feature can be modified afterwards using unitary functions @ref md_spi_enable_con1_crcen() and @ref md_spi_disable_con1_crcen().*/ + + uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function.*/ + +} md_spi_inittypedef; + + + + +/** + * @} MD_SPI_PT_INIT + */ + +/** + * @} MD_SPI_Public_Types + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_SPI_Public_Constants SPI Public Constants + * @{ + */ + +/** @defgroup MD_SPI_PC_MODE SPI Operation Mode + * @{ + */ +#define MD_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ +#define MD_SPI_MODE_MASTER (SPI_CON1_MSTREN_MSK) /*!< Master configuration */ +/** + * @} MD_SPI_PC_MODE + */ + +/** @defgroup MD_SPI_PC_PROTOCOL SPI Serial Protocol + * @{ + */ +#define MD_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */ +#define MD_SPI_PROTOCOL_TI (SPI_CON2_FRF_MSK) /*!< TI mode */ +/** + * @} MD_SPI_PC_PROTOCOL + */ + +/** @defgroup MD_SPI_PC_PHASE SPI Clock Phase + * @{ + */ +#define MD_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ +#define MD_SPI_PHASE_2EDGE (SPI_CON1_CPHA_MSK) /*!< Second clock transition is the first data capture edge */ +/** + * @} MD_SPI_PC_PHASE + */ + +/** @defgroup MD_SPI_PC_POLARITY SPI Clock Polarity + * @{ + */ +#define MD_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ +#define MD_SPI_POLARITY_HIGH (SPI_CON1_CPOL_MSK) /*!< Clock to 1 when idle */ +/** + * @} MD_SPI_PC_POLARITY + */ + +/** @defgroup MD_SPI_PC_BAUDRATEPRESCALER SPI Baud Rate Prescaler + * @{ + */ +#define MD_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ +#define MD_SPI_BAUDRATEPRESCALER_DIV4 (0x1U<CON1, value); +} + +/** + * @brief Get SPI control register (SPIx_CON1) + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_con1(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CON1)); +} + +/** + + * @brief Set SPI clock phase + * @note This bit should not be changed when communication is ongoing. \n + This bit is not used in SPI TI mode. + * @param SPIx SPI Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref MD_SPI_PHASE_1EDGE + * @arg @ref MD_SPI_PHASE_2EDGE + * @retval None + + */ +__STATIC_INLINE void md_spi_set_con1_cpha(SPI_TypeDef *SPIx, uint32_t ClockPhase) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_CPHA_MSK, ClockPhase); +} + +/** + * @brief Get SPI clock phase + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_PHASE_1EDGE + * @arg @ref MD_SPI_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t md_spi_get_con1_cpha(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_CPHA_MSK)>>SPI_CON1_CPHA_POS); +} + +/** + * @brief Set SPI clock polarity + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref MD_SPI_POLARITY_LOW + * @arg @ref MD_SPI_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_cpol(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_CPOL_MSK, ClockPolarity); +} + +/** + * @brief Get SPI clock polarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_POLARITY_LOW + * @arg @ref MD_SPI_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t md_spi_get_con1_cpol(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_CPOL_MSK)>>SPI_CON1_CPOL_POS); +} + +/** + * @brief Set SPI master selection + * @note This bit should not be changed when communication is ongoing. + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref MD_SPI_MODE_MASTER + * @arg @ref MD_SPI_MODE_SLAVE + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_mstren(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_MSTREN_MSK, Mode); +} + +/** + * @brief Get SPI SPI operation mode (Master or Slave) + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_MODE_MASTER + * @arg @ref MD_SPI_MODE_SLAVE + */ +__STATIC_INLINE uint32_t md_spi_get_con1_mstren(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_MSTREN_MSK )>>SPI_CON1_MSTREN_POS); +} + +/** + * @brief Set SPI baud rate control + * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. + * @param SPIx SPI Instance + * @param BaudRate This parameter can be one of the following values: + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_baud(SPI_TypeDef *SPIx, uint32_t BaudRate) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_BAUD_MSK, BaudRate); +} + +/** + * @brief Get SPI baud rate prescaler + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref MD_SPI_BAUDRATEPRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t md_spi_get_con1_baud(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_BAUD_MSK)>>SPI_CON1_BAUD_POSS); +} + +/** + * @brief Enable SPI peripheral + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_con1_spien(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_SPIEN_MSK); +} + +/** + * @brief Disable SPI peripheral + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_con1_spien(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_SPIEN_MSK); +} + +/** + * @brief Check if SPI peripheral is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_con1_spien(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_SPIEN_MSK) == (SPI_CON1_SPIEN_MSK)); +} + +/** + * @brief Set SPI frame format + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @param SPIx SPI Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref MD_SPI_LSB_FIRST + * @arg @ref MD_SPI_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_lsbfirst(SPI_TypeDef *SPIx, uint32_t BitOrder) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_LSBFST_MSK, BitOrder); +} + +/** + * @brief Get SPI transfer bit order + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_LSB_FIRST + * @arg @ref MD_SPI_MSB_FIRST + */ +__STATIC_INLINE uint32_t md_spi_get_con1_lsbfirst(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_LSBFST_MSK)>>SPI_CON1_LSBFST_POS); +} + +/** + * @brief Set SPI Internal slave select + * @note This bit has an effect only when the SSEN bit is set. The value of this bit is forced onto the NSS pin. + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg BIT_SET + * @arg BIT_RESET + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_ssout(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_SSOUT_MSK , value); +} + +/** + * @brief Get SPI Internal slave select + * @param SPIx SPI Instance + * @retval State of 1 or 0 + */ +__STATIC_INLINE uint32_t md_spi_get_con1_ssout(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_SSOUT_MSK)>>SPI_CON1_SSOUT_POS); +} + +/** + * @brief Enable SPI software slave management + * @note When the SSEN bit is set, the NSS pin input is replaced with the value from the SSOUT bit. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_con1_ssen(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_SSEN_MSK); +} + +/** + * @brief Disable SPI software slave management + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_con1_ssen(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_SSEN_MSK); +} + +/** + * @brief Check if SPI peripheral is software slave management + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_con1_ssen(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_SSEN_MSK) == (SPI_CON1_SSEN_MSK)); +} + +/** + * @brief Set SPI receive only mode enable + * @note This bit enables simplex communication using a single unidirectional line to receive data exclusively. \n + Keep BIDEN bit clear when receive only mode is active.This bit is also useful in a multislave system \n + in which this particular slave is not accessed, the output from the accessed slave is not corrupted. + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg BIT_SET + * @arg BIT_RESET + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_rxo(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_RXO_MSK , value); +} + +/** + * @brief Set SPI receive only mode enable + * @param SPIx SPI Instance + * @retval State of 1 or 0 + */ +__STATIC_INLINE uint32_t md_spi_get_con1_rxo(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_RXO_MSK)>>SPI_CON1_RXO_POS); +} + +/** + * @brief Set data frame format + * @param SPIx SPI Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref MD_SPI_FRAME_FORMAT_8BIT + * @arg @ref MD_SPI_FRAME_FORMAT_16BIT + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_flen(SPI_TypeDef *SPIx, uint32_t DataWidth) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_FLEN_MSK, DataWidth); +} + +/** + * @brief Get data frame format + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_FRAME_FORMAT_8BIT + * @arg @ref MD_SPI_FRAME_FORMAT_16BIT + */ +__STATIC_INLINE uint32_t md_spi_get_con1_flen(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_FLEN_MSK)>>SPI_CON1_FLEN_POS); +} + +/** + * @brief Set CRCNext to transfer CRC on the line + * @note This bit has to be written as soon as the last data is written in the SPIx_DATA register. + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg BIT_SET + * @arg BIT_RESET + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_crcnext(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_NXTCRC_MSK, value); +} + +/** + * @brief Get CRCNext to transfer CRC on the line + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval State of 1 or 0 + */ +__STATIC_INLINE uint32_t md_spi_get_con1_crcnext(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_NXTCRC_MSK)>>SPI_CON1_NXTCRC_POS); +} + +/** + * @brief Enable SPI hardware CRC calculation + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_con1_crcen(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_CRCEN_MSK); +} + +/** + * @brief Disable SPI hardware CRC calculation + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_con1_crcen(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_CRCEN_MSK); +} + +/** + * @brief Check if hardware CRC calculation is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_con1_crcen(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_CRCEN_MSK) == (SPI_CON1_CRCEN_MSK)); +} + +/** + * @brief Enable SPI Output enable in bidirectional mode + * @note Output enable in bidirectional mode. This bit combined with the BIDEN bit selects the direction of \n + transfer in bidirectional mode + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_con1_bidoen(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON1, SPI_CON1_BIDOEN_MSK); +} + +/** + * @brief Disable Output enable in bidirectional mode + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_con1_bidoen(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON1, SPI_CON1_BIDOEN_MSK); +} + +/** + * @brief Check if Output enable in bidirectional mode is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_con1_bidoen(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON1, SPI_CON1_BIDOEN_MSK) == (SPI_CON1_BIDOEN_MSK)); +} + +/** + * @brief Set Bidirectional data mode enable + * @note Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional \n + data line. Keep RXO bit clear when bidirectional mode is active. + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg @ref MD_SPI_FULL_DUPLEX + * @arg @ref MD_SPI_HALF_DUPLEX + * @retval None + */ +__STATIC_INLINE void md_spi_set_con1_bidimode(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->CON1, SPI_CON1_BIDEN_MSK, value); +} + +/** + * @brief Get Bidirectional data mode enable + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow: + * @arg @ref MD_SPI_FULL_DUPLEX + * @arg @ref MD_SPI_HALF_DUPLEX + */ +__STATIC_INLINE uint32_t md_spi_get_con1_bidimode(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON1, SPI_CON1_BIDEN_MSK)>>SPI_CON1_BIDEN_POS); +} + + +/** + * @} MD_SPI_CON1 + */ + + + +/** @defgroup MD_SPI_CON2 SPI Control Register 2 + * @{ + */ + +/** + * @brief Set SPI control register 2 (SPIx_CON2) + * @param SPIx SPI Instance + * @param value The value write in SPIx_CON2 + * @retval None + */ +__STATIC_INLINE void md_spi_set_con2(SPI_TypeDef *SPIx, uint32_t value) +{ + WRITE_REG(SPIx->CON2, value); +} + +/** + * @brief Get SPI control register 2(SPIx_CON2) + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_con2(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CON2)); +} + + +/** + * @brief Enable Rx buffer DMA + * @note When this bit is set, a DMA request is generated whenever the RXTH flag is set. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_con2_rxdmaen(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_RXDMA_MSK); +} + +/** + * @brief Disable Rx buffer DMA + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_con2_rxdmaen(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_RXDMA_MSK); +} + +/** + * @brief Check if Rx buffer DMA is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_con2_rxdmaen(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_RXDMA_MSK) == (SPI_CON2_RXDMA_MSK)); +} + +/** + * @brief Enable Tx buffer DMA enable + * @note When this bit is set, a DMA request is generated whenever the TXTH flag is set. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_con2_txdmaen(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_TXDMA_MSK); +} + +/** + * @brief Disable Tx buffer DMA enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_con2_txdmaen(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_TXDMA_MSK); +} + +/** + * @brief Check if Tx buffer DMA enable is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_con2_txdmaen(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_TXDMA_MSK) == (SPI_CON2_TXDMA_MSK)); +} + +/** + * @brief Enable SS output enable + * @note SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot \n + work in a multimaster environment. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_con2_ssoe(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_NSSOE_MSK); +} + +/** + * @brief Disable SS output enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_con2_ssoe(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_NSSOE_MSK); +} + +/** + * @brief Check if SS output enable is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_con2_ssoe(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_NSSOE_MSK) == (SPI_CON2_NSSOE_MSK)); +} + +/** + * @brief Enable NSS pulse management + * @note This bit is used in master mode only. It allow the SPI to generate an NSS pulse between two consecutive \n + data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high \n + level after the transfer. It has no meaning if CPHA = ’1’, or FRF = ’1’.This bit should not be changed \n + when communication is ongoing. This bit is not used in SPI TI mode. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_con2_nssp(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CON2, SPI_CON2_NSSP_MSK); +} + +/** + * @brief Disable NSS pulse management + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_con2_nssp(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CON2, SPI_CON2_NSSP_MSK); +} + +/** + * @brief Check if NSS pulse is enabled + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_con2_nssp(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CON2, SPI_CON2_NSSP_MSK) == (SPI_CON2_NSSP_MSK)); +} + +/** + * @brief Set frame format + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref MD_SPI_PROTOCOL_MOTOROLA + * @arg @ref MD_SPI_PROTOCOL_TI + * @retval None + */ +__STATIC_INLINE void md_spi_set_con2_frf(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->CON2, SPI_CON2_FRF_MSK, Standard); +} + +/** + * @brief Get frame format + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_SPI_PROTOCOL_MOTOROLA + * @arg @ref MD_SPI_PROTOCOL_TI + */ +__STATIC_INLINE uint32_t md_spi_get_con2_frf(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON2, SPI_CON2_FRF_MSK)>>SPI_CON2_FRF_POS); +} + + +/** + * @brief Set transmit FIFO trigger threshold + * @note This is used to select the threshold level in the transmit FIFO at which the Transmit FIFO \n + trigger threshold flag is generated. + * @param SPIx SPI Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref MD_SPI_TX_FIFO_TH_0BIT + * @arg @ref MD_SPI_TX_FIFO_TH_2BIT + * @arg @ref MD_SPI_TX_FIFO_TH_4BIT + * @arg @ref MD_SPI_TX_FIFO_TH_8BIT + * @retval None + */ +__STATIC_INLINE void md_spi_set_con2_txfth(SPI_TypeDef *SPIx, uint32_t Threshold) +{ + MODIFY_REG(SPIx->CON2, SPI_CON2_TXFTH_MSK, Threshold<CON2, SPI_CON2_TXFTH_MSK)>>SPI_CON2_TXFTH_POSS); +} + +/** + * @brief Set receive FIFO trigger threshold + * @note This is used to select the threshold level in the receiver FIFO at which the Receive FIFO \n + trigger threshold flag is generated. + * @param SPIx SPI Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref MD_SPI_RX_FIFO_TH_1BIT + * @arg @ref MD_SPI_RX_FIFO_TH_4BIT + * @arg @ref MD_SPI_RX_FIFO_TH_8BIT + * @arg @ref MD_SPI_RX_FIFO_TH_14BIT + * @retval None + */ +__STATIC_INLINE void md_spi_set_con2_rxfth(SPI_TypeDef *SPIx, uint32_t Threshold) +{ + MODIFY_REG(SPIx->CON2, SPI_CON2_RXFTH_MSK, Threshold<CON2, SPI_CON2_RXFTH_MSK)>>SPI_CON2_RXFTH_POSS); +} + + +/** + * @} MD_SPI_CON2 + */ + +/** + * @defgroup MD_SPI_STAT SPI Status Register + * @{ + */ + + +/** + * @brief Get SPI status register(SPIx_STAT) + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_stat(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->STAT)); +} + +/** + * @brief Check if SPI transmit buffer empty is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_txe(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXE_MSK)== (SPI_STAT_TXE_MSK)); +} + +/** + * @brief Check if SPI transmit buffer full is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_txf(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXF_MSK)== (SPI_STAT_TXF_MSK)); +} + +/** + * @brief Check if SPI transmit buffer overflow is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_txov(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXOV_MSK)== (SPI_STAT_TXOV_MSK)); +} + +/** + * @brief Check if SPI transmit buffer underflow is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_txud(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXUD_MSK) == (SPI_STAT_TXUD_MSK)); +} + +/** + * @brief Check if SPI Tx FIFO level under threshold is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_txth(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXTH_MSK) == (SPI_STAT_TXTH_MSK)); +} + +/** + * @brief Check if SPI receive buffer empty is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_rxe(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_RXE_MSK) == (SPI_STAT_RXE_MSK)); +} + +/** + * @brief Check if SPI receive buffer full is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_rxf(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_RXF_MSK)== (SPI_STAT_RXF_MSK)); +} + +/** + * @brief Get SPI receive buffer overflow + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_rxov(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CON2, SPI_STAT_RXOV_MSK)== (SPI_STAT_RXOV_MSK)); +} + +/** + * @brief Check if SPI receive buffer underflow is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_rxud(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_RXUD_MSK)== (SPI_STAT_RXUD_MSK)); +} + +/** + * @brief Check if SPI Rx FIFO level over threshold is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_rxth(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_RXTH_MSK)== (SPI_STAT_RXTH_MSK)); +} + +/** + * @brief Check if SPI channel side is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_chside(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_CHSIDE_MSK)== (SPI_STAT_CHSIDE_MSK)); +} + +/** + * @brief Check if SPI busy flag is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_stat_busy(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_BUSY_MSK)== (SPI_STAT_BUSY_MSK)); +} + +/** + * @brief Get SPI Tx FIFO level + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_stat_txflv(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_TXFLV_MSK) >> SPI_STAT_TXFLV_POSS); +} + +/** + * @brief Get SPI Rx FIFO level + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_stat_rxflv(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->STAT, SPI_STAT_RXFLV_MSK) >> SPI_STAT_RXFLV_POSS); +} + +/** + * @} MD_SPI_STAT + */ + + +/** @defgroup MD_SPI_DATA SPI Data Register + * @{ + */ + +/** + * @brief Read 8-Bits in the data register + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t md_spi_recv_data8(SPI_TypeDef *SPIx) +{ + return (uint8_t)(READ_REG(SPIx->DATA)); +} + +/** + * @brief Read 16-Bits in the data register + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t md_spi_recv_data16(SPI_TypeDef *SPIx) +{ + return (uint16_t)(READ_REG(SPIx->DATA)); +} + +/** + * @brief Write 8-Bits in the data register + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void md_spi_send_data8(SPI_TypeDef *SPIx, uint8_t TxData) +{ + SPIx->DATA = (uint8_t)TxData; +} + +/** + * @brief Write 16-Bits in the data register + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void md_spi_send_data16(SPI_TypeDef *SPIx, uint16_t TxData) +{ + SPIx->DATA = (uint16_t)TxData; +} + +/** + * @} MD_SPI_DATA + */ + +/** @defgroup MD_SPI_CRC SPI CRC Manangement + * @{ MD_SPI_CRC + */ + +/** + * @brief Set CRC polynmomial register (SPIx_CRCPLOY) + * @note When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently \n + received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is \n + calculated serially using the polynomial programmed in the SPIx_CRCPLOY register. Only the 8 LSB bits are \n + considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPIx_CON1 is cleared). CRC \n + calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a \n + 16-bit CRC frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based \n + on any CRC16 standard. + Note: A read to this register when the BSY Flag is set could return an incorrect value. These bits are not \n + used in I2S mode. + * @param SPIx SPI Instance + * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF + * @retval None + */ +__STATIC_INLINE void md_spi_set_crcploy(SPI_TypeDef *SPIx, uint32_t CRCPoly) +{ + WRITE_REG(SPIx->CRCPOLY, (uint16_t)CRCPoly); +} + +/** + * @brief Get CRC polynmomial register (SPIx_CRCPLOY) + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t md_spi_get_crcploy(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CRCPOLY)); +} + +/** + * @brief Get Rx CRC register + * @note When CRC calculation is enabled, the RxCRC[7:0] bits contain the computed CRC value of the subsequently \n + transmitted bytes. This register is reset when the CRCEN bit of SPIx_CON1 is written to 1. The CRC is calculated \n + serially using the polynomial programmed in the SPIx_CRCPLOY register. Only the 8 LSB bits are considered \n + when the CRC frame format is set to be 8-bit length (FLEN bit in the SPIx_CON1 is cleared). CRC calculation is \n + done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame \n + format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. \n + Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used \n + in I2S mode. + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t md_spi_get_rxcrc(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->RXCRC)); +} + +/** + * @brief Get Tx CRC register + * @note When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently \n + transmitted bytes. This register is reset when the CRCEN bit of SPIx_CON1 is written to 1. The CRC is calculated \n + serially using the polynomial programmed in the SPIx_CRCPLOY register. Only the 8 LSB bits are considered \n + when the CRC frame format is set to be 8-bit length (FLEN bit in the SPIx_CR1 is cleared). CRC calculation is \n + done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame \n + format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. \n + Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used \n + in I2S mode. + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t md_spi_get_txcrc(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->TXCRC)); +} + +/** + * @} MD_SPI_CRC + */ + + + +/** @defgroup MD_SPI_I2S I2S Configuration Management + * @{ + */ + + +/** @defgroup MD_SPI_I2SCFG I2S Configuration register + * @{ + */ + +/** + * @brief Set SPI I2S configuration register(SPIx_I2SCFG) + * @param SPIx SPI Instance + * @param value The value write in SPIx_I2SCFG + * @retval None + */ +__STATIC_INLINE void md_spi_set_I2SCFG(SPI_TypeDef *SPIx, uint32_t value) +{ + WRITE_REG(SPIx->I2SCFG, value); +} + +/** + * @brief Get SPI I2S configuration register (SPIx_I2SCFG) + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_I2SCFG(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->I2SCFG)); +} + +/** + * @brief Set channel legth(number of bits per audio channel) + * @note The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by \n + hardware whatever the value filled in. + Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg @ref MD_I2S_CHANNEL_LENGTH_16BIT + * @arg @ref MD_I2S_CHANNEL_LENGTH_32BIT + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2scfg_chlen(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_CHLEN_MSK, value); +} + +/** + * @brief Get channel legth(number of bits per audio channel) + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return: + * @arg @ref MD_I2S_CHANNEL_LENGTH_16BIT + * @arg @ref MD_I2S_CHANNEL_LENGTH_32BIT + */ +__STATIC_INLINE uint32_t md_spi_get_i2scfg_chlen(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_CHLEN_MSK)); +} + +/** + * @brief Set Data length to be transferred + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg @ref MD_I2S_DATA_LENGTH_16BIT + * @arg @ref MD_I2S_DATA_LENGTH_24BIT + * @arg @ref MD_I2S_DATA_LENGTH_32BIT + * @arg @ref MD_I2S_DATA_LENGTH_NOT_ALLOWED + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2scfg_datlen(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_DATLEN_MSK, value); +} + +/** + * @brief Get Data length to be transferred + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref MD_I2S_DATA_LENGTH_16BIT + * @arg @ref MD_I2S_DATA_LENGTH_24BIT + * @arg @ref MD_I2S_DATA_LENGTH_32BIT + * @arg @ref MD_I2S_DATA_LENGTH_NOT_ALLOWED + */ +__STATIC_INLINE uint32_t md_spi_get_i2scfg_datlen(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_DATLEN_MSK)>>SPI_I2SCFG_DATLEN_POSS); +} + +/** + * @brief Set Inactive state clock polarity + * @note Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used \n + in SPI mode. The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD \n + and WS signals. + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg @ref MD_I2S_POLARITY_LOW + * @arg @ref MD_I2S_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2scfg_ckpol(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_CKPOL_MSK, value); +} + +/** + * @brief Get Inactive state clock polarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow : + * @arg @ref MD_I2S_POLARITY_LOW + * @arg @ref MD_I2S_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t md_spi_get_i2scfg_ckpol(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_CKPOL_MSK)>>SPI_I2SCFG_CKPOL_POS); +} + +/** + * @brief Set I2S standard selection + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg @ref MD_I2S_PHILIPS_STANDARD + * @arg @ref MD_I2S_MSB_STANDARD + * @arg @ref MD_I2S_LSB_STANDARD + * @arg @ref MD_I2S_PCM_STANDARD + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2scfg_i2sstd(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_I2SSTD_MSK, value); +} + +/** + * @brief Get I2S standard selection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow : + * @arg @ref MD_I2S_PHILIPS_STANDARD + * @arg @ref MD_I2S_MSB_STANDARD + * @arg @ref MD_I2S_LSB_STANDARD + * @arg @ref MD_I2S_PCM_STANDARD + */ +__STATIC_INLINE uint32_t md_spi_get_i2scfg_i2sstd(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SSTD_MSK)>>SPI_I2SCFG_I2SSTD_POSS); +} + +/** + * @brief Set PCM frame synchronization + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg @ref MD_I2S_FRAME_SYN_SHORT + * @arg @ref MD_I2S_FRAME_SYN_LONG + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2scfg_pcmsync(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_PCMSYNC_MSK, value); +} + +/** + * @brief Get PCM frame synchronization + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow : + * @arg @ref MD_I2S_FRAME_SYN_SHORT + * @arg @ref MD_I2S_FRAME_SYN_LONG + */ +__STATIC_INLINE uint32_t md_spi_get_i2scfg_pcmsync(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_PCMSYNC_MSK)>>SPI_I2SCFG_PCMSYNC_POS); +} + +/** + * @brief Set I2S configuration mode + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg @ref MD_I2S_SLAVE_TX + * @arg @ref MD_I2S_SLAVE_RX + * @arg @ref MD_I2S_MASTER_TX + * @arg @ref MD_I2S_MASTER_RX + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2scfg_i2scfg(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, value); +} + +/** + * @brief Get I2S configuration mode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow : + * @arg @ref MD_I2S_SLAVE_TX + * @arg @ref MD_I2S_SLAVE_RX + * @arg @ref MD_I2S_MASTER_TX + * @arg @ref MD_I2S_MASTER_RX + */ +__STATIC_INLINE uint32_t md_spi_get_i2scfg_i2scfg(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SCFG_MSK)>>SPI_I2SCFG_I2SCFG_POSS); +} + +/** + * @brief Enable I2S enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_i2scfg_i2se(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SE_MSK); +} + +/** + * @brief Disable I2S enable + * @note When disabling the I2S, follow the procedure described in the Reference Manual. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_i2scfg_i2se(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SE_MSK); +} + +/** + * @brief Check if I2S enable is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_i2scfg_i2se(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SE_MSK) == (SPI_I2SCFG_I2SE_MSK)); +} + +/** + * @brief Set I2S mode selection + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg @ref MD_I2S_MODE_SPI + * @arg @ref MD_I2S_MODE_I2S + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2scfg_i2smod(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SCFG, SPI_I2SCFG_I2SMOD_MSK, value); +} + +/** + * @brief Get I2S mode selection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow : + * @arg @ref MD_I2S_MODE_SPI + * @arg @ref MD_I2S_MODE_I2S + */ +__STATIC_INLINE uint32_t md_spi_get_i2scfg_i2smod(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFG, SPI_I2SCFG_I2SMOD_MSK)>>SPI_I2SCFG_I2SMOD_POS); +} + + +/** + * @} MD_SPI_I2SCFG + */ + +/**@defgroup MD_SPI_I2SPR I2S Prescaler register + * @{ + */ + + + +/** + * @brief Set SPI I2S configuration register(SPIx_I2SPR) + * @param SPIx SPI Instance + * @param value The value write in SPIx_I2SPR + * @retval None + */ +__STATIC_INLINE void md_spi_set_I2SPR(SPI_TypeDef *SPIx, uint32_t value) +{ + WRITE_REG(SPIx->I2SPR, value); +} + +/** + * @brief Get SPI I2S configuration register (SPIx_I2SPR) + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_get_I2SPR(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->I2SPR)); +} + +/** + * @brief Set I2S linear prescaler + * @note I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. \n + Note: These bits should be configured when the I2S is disabled. \n + They are used only when the I2S is in master mode. They are not used in SPI mode. + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg Max:255 + * @arg Min:2 + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2spr_i2sdiv(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV_MSK, value); +} + +/** + * @brief Get I2S linear prescaler + * @note 0 or 1 are forbidden values + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow : + * @arg Max:255 + * @arg Min:2 + */ +__STATIC_INLINE uint32_t md_spi_get_i2spr_i2sdiv(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV_MSK)>>SPI_I2SPR_I2SDIV_POSS); +} + +/** + * @brief Set Odd factor for the prescaler + * @note 0 or 1 are forbidden values + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg MD_I2S_EVEN + * @arg MD_I2S_ODD + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2spr_odd(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD_MSK, value); +} + +/** + * @brief Get Odd factor for the prescaler + * @note 0 or 1 are forbidden values + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow : + * @arg MD_I2S_EVEN + * @arg MD_I2S_ODD + */ +__STATIC_INLINE uint32_t md_spi_get_i2spr_odd(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD_MSK)>>SPI_I2SPR_ODD_POS); +} + +/** + * @brief Master clock output enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_i2spr_mckoe(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE_MSK); +} + +/** + * @brief Master clock output disable + * @note When disabling the I2S, follow the procedure described in the Reference Manual. + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_i2spr_mckoe(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFG, SPI_I2SPR_MCKOE_MSK); +} + +/** + * @brief Check if Master clock output enable is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enable_i2spr_mckoe(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE_MSK) == (SPI_I2SPR_MCKOE_MSK)); +} + +/** + * @brief Set External I2S Clock Enable + * @note 0 or 1 are forbidden values + * @param SPIx SPI Instance + * @param value This bit can be set to: + * @arg MD_I2S_APB_CLOCK + * @arg MD_I2S_EXTERNAL_CLOCK + * @retval None + */ +__STATIC_INLINE void md_spi_set_i2spr_extcken(SPI_TypeDef *SPIx, uint32_t value) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_EXTCKEN_MSK, value); +} + +/** + * @brief Get External I2S Clock Enable + * @note 0 or 1 are forbidden values + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @retval Return follow : + * @arg MD_I2S_APB_CLOCK + * @arg MD_I2S_EXTERNAL_CLOCK + */ +__STATIC_INLINE uint32_t md_spi_get_i2spr_extcken(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_EXTCKEN_MSK)>>SPI_I2SPR_EXTCKEN_POS); +} + + + + + + +/** + * @} MD_SPI_I2SPR + */ + + + +/** + * @} MD_SPI_I2S + */ + + +/** @defgroup MD_SPI_PF_Interrupt_Management SPI Interrupt Management + * @{ + */ + +/** @defgroup MD_SPI_IER SPI Interrupt Enable Register + * @{ + */ + + +/** + * @brief Frame format error interrupt enable + * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_freie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_FREIE_MSK); +} + +/** + * @brief Mode fault interrupt enable + * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_modfie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_MODFIE_MSK); +} + +/** + * @brief CRC error interrupt enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_crcerrie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_CRCERRIE_MSK); +} + +/** + * @brief Receive buffer over threshold interrupt enable + * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_rxthie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXTHIE_MSK); +} + +/** + * @brief Transmit buffer over threshold interrupt enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_txthie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXTHIE_MSK); +} + +/** + * @brief Receive buffer underrun interrupt enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_rxudie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXUDIE_MSK); +} + +/** + * @brief Transmit buffer underrun interrupt enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_txudie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXUDIE_MSK); +} + +/** + * @brief Receive buffer overrun interrupt enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_rxovie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXOVIE_MSK); +} + +/** + * @brief Transmit buffer overrun interrupt enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_txovie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXOVIE_MSK); +} + +/** + * @brief Receive buffer full interrupt enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_rxfie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXFIE_MSK); +} + +/** + * @brief Transmit buffer empty interrupt enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_enable_ier_txeie(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXEIE_MSK); +} + +/** + * @} MD_SPI_IER + */ + + +/** @defgroup MD_SPI_IDR SPI Interrupt Disable Register + * @{ + */ + +/** + * @brief Frame format error interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_freid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_FREID_MSK); +} + +/** + * @brief Mode fault interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_modfid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_MODFID_MSK); +} + +/** + * @brief CRC error interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_crcerrid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_CRCERRID_MSK); +} + +/** + * @brief Receive buffer under threshold interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_rxthid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXTHID_MSK); +} + +/** + * @brief Transmit buffer under threshold interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_txthid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_TXTHID_MSK); +} + +/** + * @brief Receive buffer underrun interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_rxudid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXUDID_MSK); +} + +/** + * @brief Transmit buffer underrun interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_txudid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_TXUDID_MSK); +} + +/** + * @brief Receive buffer overrun interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_rxovid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXOVID_MSK); +} + +/** + * @brief Transmit buffer overrun interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_txovid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_TXOVID_MSK); +} + +/** + * @brief Receive buffer full interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_rxfid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_RXFID_MSK); +} + +/** + * @brief Transmit buffer empty interrupt disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void md_spi_disable_idr_txeid(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IDR, SPI_IDR_TXEID_MSK); +} + +/** + * @} MD_SPI_IDR + */ + +/** @defgroup MD_SPI_ICR SPI Interrupt Clear Status Register + * @{ + */ + +/** + * @brief Frame format error interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_freic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_FREIC_MSK); +} + +/** + * @brief Mode fault interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_modfic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_MODFIC_MSK); +} + +/** + * @brief CRC error interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_crcerric(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_CRCERRIC_MSK); +} + +/** + * @brief Receive buffer over threshold interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_rxthic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXTHIC_MSK); +} + +/** + * @brief Transmit buffer over threshold interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_txthic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_TXTHIC_MSK); +} + +/** + * @brief Receive buffer underrun interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_rxudic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXUDIC_MSK); +} + +/** + * @brief Transmit buffer underrun interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_txudic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_TXUDIC_MSK); +} + +/** + * @brief Receive buffer overrun interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_rxovic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXOVIC_MSK); +} + +/** + * @brief Transmit buffer overrun interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_txovic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_TXOVIC_MSK); +} + +/** + * @brief Receive buffer full interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_rxfic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_RXFIC_MSK); +} + +/** + * @brief Transmit buffer empty interrupt clear + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_spi_clear_icr_txeic(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->ICR, SPI_ICR_TXEIC_MSK); +} + +/** + * @} MD_SPI_ICR + */ + +/** @defgroup MD_SPI_IVS SPI Interrupt Valid Status Register + * @{ + */ + + +/** + * @brief Check if Frame format error interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_freiv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_FREIV_MSK) == (SPI_IVS_FREIV_MSK)); +} + +/** + * @brief Check if Mode fault interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_modfiv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_MODFIV_MSK) == (SPI_IVS_MODFIV_MSK)); +} + +/** + * @brief Check if CRC error interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_crcerriv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_CRCERRIV_MSK) == (SPI_IVS_CRCERRIV_MSK)); +} + +/** + * @brief Check if Receive buffer under threshold interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_rxthiv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXTHIV_MSK) == (SPI_IVS_RXTHIV_MSK)); +} + +/** + * @brief Check if Transmit buffer under threshold interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_it_txthiv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_TXTHIV_MSK) == (SPI_IVS_TXTHIV_MSK)); +} + +/** + * @brief Check if Receive buffer under underrun interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_rxudiv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXUDIV_MSK) == (SPI_IVS_RXUDIV_MSK)); +} + +/** + * @brief Check if Transmit buffer underrun interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_it_txudiv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_TXUDIV_MSK) == (SPI_IVS_TXUDIV_MSK)); +} + +/** + * @brief Check if Receive buffer overrun interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_rxoviv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXOVIV_MSK) == (SPI_IVS_RXOVIV_MSK)); +} + +/** + * @brief Check if Transmit buffer overrun interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_txoviv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_TXOVIV_MSK) == (SPI_IVS_TXOVIV_MSK)); +} + +/** + * @brief Check if Receive buffer full interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_rxfiv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_RXFIV_MSK) == (SPI_IVS_RXFIV_MSK)); +} + +/** + * @brief Check if Transmit buffer empty interrupt valid is enabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_spi_is_enabled_ivs_txeiv(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->IVS, SPI_IVS_TXEIV_MSK) == (SPI_IVS_TXEIV_MSK)); +} + + +/** + * @} MD_SPI_IVS + */ + + +/** @defgroup MD_SPI_RIF SPI Raw Interrupt Flag Status Register + * @{ + */ + +/** + * @brief Check if Transmit buffer empty interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_txeri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_TXERI_MSK)==(SPI_RIF_TXERI_MSK)); +} + +/** + * @brief Check if Transmit buffer overrun interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_txovri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_TXOVRI_MSK)==(SPI_RIF_TXOVRI_MSK)); +} + +/** + * @brief Check if Transmit buffer underrun interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_txudri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_TXUDRI_MSK)==(SPI_RIF_TXUDRI_MSK)); +} + +/** + * @brief Check if Transmit buffer under threshold interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_txthri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_TXTHRI_MSK)==(SPI_RIF_TXTHRI_MSK)); +} + +/** + * @brief Check if Receive buffer full interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_rxfri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_RXFRI_MSK)==(SPI_RIF_RXFRI_MSK)); +} + +/** + * @brief Check if Receive buffer overrun interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_rxovri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_RXOVRI_MSK)==(SPI_RIF_RXOVRI_MSK)); +} + +/** + * @brief Check if Receive buffer underrun interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_rxudri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_RXUDRI_MSK)==(SPI_RIF_RXUDRI_MSK)); +} + +/** + * @brief Check if Receive buffer over threshold interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_rxthri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_RXTHRI_MSK)==(SPI_RIF_RXTHRI_MSK)); +} + +/** + * @brief Check if CRC error interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_crcerrri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_CRCERRRI_MSK)==(SPI_RIF_CRCERRRI_MSK)); +} + +/** + * @brief Check if Mode fault interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_modfri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_MODFRI_MSK)==(SPI_RIF_MODFRI_MSK)); +} + +/** + * @brief Check if Frame format error interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_rif_freri(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->RIF, SPI_RIF_FRERI_MSK)==(SPI_RIF_FRERI_MSK)); +} + +/** + * @} MD_SPI_RIF + */ + +/** @defgroup MD_SPI_IFM SPI Interrupt Masked Flag Status Register + * @{ + */ + +/** + * @brief Check if Transmit buffer empty interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_txefm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_TXEFM_MSK)==(SPI_IFM_TXEFM_MSK)); +} + +/** + * @brief Check if Transmit buffer overrun interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_txovfm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_TXOVFM_MSK)==(SPI_IFM_TXOVFM_MSK)); +} + +/** + * @brief Check if Transmit buffer underrun interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_txudfm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_TXUDFM_MSK)==(SPI_IFM_TXUDFM_MSK)); +} + +/** + * @brief Check if Transmit buffer under threshold interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_txthfm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_TXTHFM_MSK)==(SPI_IFM_TXTHFM_MSK)); +} + +/** + * @brief Check if Receive buffer full interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_rxffm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_RXFFM_MSK)==(SPI_IFM_RXFFM_MSK)); +} + +/** + * @brief Check if Receive buffer overrun interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_rxovfm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_RXOVFM_MSK)==(SPI_IFM_RXOVFM_MSK)); +} + +/** + * @brief Check if Receive buffer underrun interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_rxudfm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_RXUDFM_MSK)==(SPI_IFM_RXUDFM_MSK)); +} + +/** + * @brief Check if Receive buffer over threshold interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_rxthfm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_RXTHFM_MSK)==(SPI_IFM_RXTHFM_MSK)); +} + +/** + * @brief Check if CRC error interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_crcerrfm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_CRCERRFM_MSK)==(SPI_IFM_CRCERRFM_MSK)); +} + +/** + * @brief Check if Mode fault interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_modffm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_MODFFM_MSK)==(SPI_IFM_MODFFM_MSK)); +} + +/** + * @brief Check if Frame format error interrupt flag status is actived + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE uint32_t md_spi_is_active_flag_ifm_frefm(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->IFM, SPI_IFM_FREFM_MSK)==(SPI_IFM_FREFM_MSK)); +} + +/** + * @} MD_SPI_IFM + */ + + + +/** + * @} MD_SPI_PF_Interrupt_Management + */ + + + +/** + * @} MD_SPI_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_SPI_Public_Functions SPI Public Functions + * @{ + */ + + + + +/** @defgroup MD_SPI_PF_Init SPI Initialization and De-Initialization functions + * @{ + */ + +ErrorStatus md_spi_init(SPI_TypeDef *SPIx, md_spi_inittypedef *SPI_InitStruct); +void md_spi_struct_init(md_spi_inittypedef *SPI_InitStruct); +void SPISingleWr(SPI_TypeDef *SPIx, uint8_t data); +uint8_t SPISSingleRd(SPI_TypeDef *SPIx); +/** + * @} MD_SPI_PF_Init + */ + +/** + * @} MD_SPI_Public_Functions + */ + +/** + * @} SPI + */ + +#endif + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_syscfg.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_syscfg.h new file mode 100644 index 0000000000000000000000000000000000000000..0da1bfc14d8d2055f2aefc37f63d8c70825a5693 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_syscfg.h @@ -0,0 +1,1249 @@ +/** + ****************************************************************************** + * @file md_SYSCFG.h + * @brief ES32F0271 SYSCFG HEAD File. + * + * @version V1.00.02 + * @date 30/11/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_SYSCFG_H__ +#define __MD_SYSCFG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include +#include "es32f0271.h" +#include "reg_syscfg.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (SYSCFG) + +/** @defgroup SYSCFG SYSCFG + * @brief SYSCFG micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_SYSCFG_PT_INIT RCC Public Init structures + * @{ + */ + +/** + * @brief MD SYSCFG Init Structure definition + */ + + +/** + * @} MD_SYSCFG_PT_INIT + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_SYSCFG_Public_Constants SYSCFG Public Constants + * @{ + */ + +/** @defgroup MD_SYSCFG_REMAP_REALMOD_FLAG Current Memory mapping Status + * @{ + */ +#define MD_SYSCFG_REALMOD_MAIN (0x00000000UL) /** @brief Main Flash memory mapped at 0x00000000 */ +#define MD_SYSCFG_REALMOD_SYSTEM (0x00000001UL) /** @brief System Flash memory mapped at 0x00000000 */ +#define MD_SYSCFG_REALMOD_SRAM (0x00000002UL) /** @brief SRAM mapped at 0x00000000 */ +/** + * @} MD_SYSCFG_REMAP_REALMOD_FLAG + */ + +/** @defgroup MD_SYSCFG_REMAP_MEMMOD_FLAG Memory mapping selection bits + * @{ + */ +#define MD_SYSCFG_MEMMOD_MAIN (0x00000000UL) /** @brief Main Flash memory mapped at 0x00000000 */ +#define MD_SYSCFG_MEMMOD_SYSTEM (0x00000001UL) /** @brief System Flash memory mapped at 0x00000000 */ +#define MD_SYSCFG_MEMMOD_SRAM (0x00000002UL) /** @brief SRAM mapped at 0x00000000 */ +/** + * @} MD_SYSCFG_REMAP_MEMMOD_FLAG + */ + +/** @defgroup MD_SYSCFG_IRSEL_PLR_FLAG IR Polarity + * @{ + */ +#define MD_SYSCFG_PLR_INV_SEL1_AND_SEL2 (0x00000000UL) /** @brief IR out = ~(SEL1 & SEL2) */ +#define MD_SYSCFG_PLR_SEL1_AND_SEL2 (0x00000001UL) /** @brief IR out = SEL1 & SEL2 */ +/** + * @} MD_SYSCFG_IRSEL_PLR_FLAG + */ + +/** @defgroup MD_SYSCFG_IRSEL_SEL2 IR Select 2 + * @{ + */ +#define MD_SYSCFG_SEL2_OFF (0x00000000UL) /** @brief 0000: OFF */ +#define MD_SYSCFG_SEL2_GP16C2T4_CH1 (0x00000001UL) /** @brief 0001: GP16C2T4_CH1 */ +#define MD_SYSCFG_SEL2_GP16C2T4_CH2 (0x00000002UL) /** @brief 0010: GP16C2T4_CH2 */ +#define MD_SYSCFG_SEL2_UART3_TX (0x00000003UL) /** @brief 0100: UART3_TX */ +#define MD_SYSCFG_SEL2_SUART2_TX (0x00000004UL) /** @brief 1000: SUART2_TX */ +/** + * @} MD_SYSCFG_IRSEL_SEL2 + */ + +/** @defgroup MD_SYSCFG_IRSEL_SEL1 IR Select 1 + * @{ + */ +#define MD_SYSCFG_SEL1_OFF (0x00000000UL) /** @brief 0000: OFF */ +#define MD_SYSCFG_SEL1_GP16C2T2_CH1 (0x00000001UL) /** @brief 0001: GP16C2T2_CH1 */ +#define MD_SYSCFG_SEL1_GP16C2T2_CH2 (0x00000002UL) /** @brief 0010: GP16C2T2_CH2 */ +#define MD_SYSCFG_SEL1_GP16C2T3_CH1 (0x00000003UL) /** @brief 0100: GP16C2T3_CH1 */ +#define MD_SYSCFG_SEL1_GP16C2T3_CH2 (0x00000004UL) /** @brief 1000: GP16C2T3_CH2 */ +/** + * @} MD_SYSCFG_IRSEL_SEL1 + */ + +/** @defgroup MD_SYSCFG_CFG_DBGH_EN DBG Halt enable bit + * @{ + */ +#define MD_SYSCFG_DBGH_EN_IWDT (0x00002000UL) +#define MD_SYSCFG_DBGH_EN_WWDT (0x00001000UL) +#define MD_SYSCFG_DBGH_EN_BS16T1 (0x00000200UL) +#define MD_SYSCFG_DBGH_EN_GP16C4T3 (0x00000100UL) +#define MD_SYSCFG_DBGH_EN_GP16C4T2 (0x00000080UL) +#define MD_SYSCFG_DBGH_EN_GP16C4T1 (0x00000040UL) +#define MD_SYSCFG_DBGH_EN_GP32C4T1 (0x00000020UL) +#define MD_SYSCFG_DBGH_EN_GP16C2T4 (0x00000010UL) +#define MD_SYSCFG_DBGH_EN_GP16C2T3 (0x00000008UL) +#define MD_SYSCFG_DBGH_EN_GP16C2T2 (0x00000004UL) +#define MD_SYSCFG_DBGH_EN_GP16C2T1 (0x00000002UL) +#define MD_SYSCFG_DBGH_EN_AD16C4T1 (0x00000001UL) +/** + * @} MD_SYSCFG_CFG_DBGH_EN + */ + +/** @defgroup MD_SYSCFG_CFG_VTST Voltage testing + * @{ + */ +#define MD_SYSCFG_VTST_LDO (0x00000000UL) /** @brief 00: LDO Buffer Voltage */ +#define MD_SYSCFG_VTST_BANDGAP_REF (0x00000001UL) /** @brief 01: BandGap Reference Voltage */ +#define MD_SYSCFG_VTST_LDO1V2 (0x00000002UL) /** @brief 10: LDO1V2 Voltage */ +#define MD_SYSCFG_VTST_LDO1V5 (0x00000003UL) /** @brief 11: LDO1V5 Voltage */ +/** + * @} MD_SYSCFG_CFG_VTST + */ + +/** @defgroup MD_SYSCFG_CFG_VRLS These bits are written by software to select the voltage reference level by the ADC/DAC + * @{ + */ +#define MD_SYSCFG_VRLS_1V5 (0x00000000UL) /** @brief 000: 1.5V */ +#define MD_SYSCFG_VRLS_2V (0x00000001UL) /** @brief 001: 2.0V */ +#define MD_SYSCFG_VRLS_2V5 (0x00000002UL) /** @brief 010: 2.5V */ +#define MD_SYSCFG_VRLS_3V (0x00000003UL) /** @brief 011: 3.0V */ +#define MD_SYSCFG_VRLS_3V5 (0x00000004UL) /** @brief 100: 3.5V */ +#define MD_SYSCFG_VRLS_4V (0x00000005UL) /** @brief 101: 4.0V */ +#define MD_SYSCFG_VRLS_4V5 (0x00000006UL) /** @brief 110: 4.5V */ +#define MD_SYSCFG_VRLS_5V (0x00000007UL) /** @brief 111: 5.0V(VDD5) */ +/** + * @} MD_SYSCFG_CFG_VRLS + */ + +/** @defgroup MD_SYSCFG_PWCON_PVLS These bits are written by software to select the voltage reference level by the ADC/DAC + * @{ + */ +#define MD_SYSCFG_PVLS_R1V9_F2V (0x00000000UL) /** @brief 0000: R-1.9V, F-2.0V */ +#define MD_SYSCFG_PVLS_R2V1_F2V2 (0x00000001UL) /** @brief 0001: R-2.1V, F-2.2V */ +#define MD_SYSCFG_PVLS_R2V3_F2V4 (0x00000002UL) /** @brief 0010: R-2.3V, F-2.4V */ +#define MD_SYSCFG_PVLS_R2V5_F2V6 (0x00000003UL) /** @brief 0011: R-2.5V, F-2.6V */ +#define MD_SYSCFG_PVLS_R2V7_F2V8 (0x00000004UL) /** @brief 0100: R-2.7V, F-2.8V */ +#define MD_SYSCFG_PVLS_R2V9_F3V (0x00000005UL) /** @brief 0101: R-2.9V, F-3.0V */ +#define MD_SYSCFG_PVLS_R3V1_F3V2 (0x00000006UL) /** @brief 0110: R-3.1V, F-3.2V */ +#define MD_SYSCFG_PVLS_R3V3_F3V4 (0x00000007UL) /** @brief 0111: R-3.3V, F-3.4V */ +#define MD_SYSCFG_PVLS_R3V5_F3V6 (0x00000008UL) /** @brief 1000: R-3.5V, F-3.6V */ +#define MD_SYSCFG_PVLS_R3V7_F3V8 (0x00000009UL) /** @brief 1001: R-3.7V, F-3.8V */ +#define MD_SYSCFG_PVLS_R3V9_F4V (0x0000000AUL) /** @brief 1010: R-3.9V, F-4.0V */ +#define MD_SYSCFG_PVLS_R4V1_F4V2 (0x0000000BUL) /** @brief 1011: R-4.1V, F-4.2V */ +#define MD_SYSCFG_PVLS_R4V3_F4V4 (0x0000000CUL) /** @brief 1100: R-4.3V, F-4.4V */ +#define MD_SYSCFG_PVLS_R4V5_F4V6 (0x0000000DUL) /** @brief 1101: R-4.5V, F-4.6V */ +#define MD_SYSCFG_PVLS_R4V7_F4V8 (0x0000000EUL) /** @brief 1110: R-4.7V, F-4.8V */ +#define MD_SYSCFG_PVLS_R4V9_F5V (0x0000000FUL) /** @brief 1111: R-4.9V, F-5.0V */ +/** + * @} MD_SYSCFG_PWCON_PVLS + */ + +/** @defgroup MD_SYSCFG_WKCON_LPLS Low Power Level Select + * @{ + */ +#define MD_SYSCFG_LPLS_LV0 (0x00000000UL) /** @brief 0 : Level 0, Sleep Mode (Normal) */ +#define MD_SYSCFG_LPLS_LV1 (0x00000001UL) /** @brief 1 : Level 1, Stop Mode (All Clock OFF) */ +#define MD_SYSCFG_LPLS_LV2 (0x00000002UL) /** @brief 2 : Level 2, Standby Mode (SRAM retention) */ +#define MD_SYSCFG_LPLS_LV3 (0x00000003UL) /** @brief 3 : Level 3, Low Power Mode (LDO off) */ +#define MD_SYSCFG_LPLS_LV4 (0x00000004UL) /** @brief 4 : Level 3, Ultra Low Power Mode(LDO off/BandGap off) */ +/** + * @} MD_SYSCFG_WKCON_LPLS + */ + +/** @defgroup MD_SYSCFG_WKCON_WKEG WKEGx:WKUPx pin edge sensitive type select + * @{ + */ +#define MD_SYSCFG_WKCON_WKEG_NRST (0x00000800UL) +#define MD_SYSCFG_WKCON_WKEG_PVD (0x00000400UL) +#define MD_SYSCFG_WKCON_WKEG_CMP0 (0x00000200UL) +#define MD_SYSCFG_WKCON_WKEG_RTC (0x00000100UL) +#define MD_SYSCFG_WKCON_WKEG_PIN7 (0x00000080UL) +#define MD_SYSCFG_WKCON_WKEG_PIN6 (0x00000040UL) +#define MD_SYSCFG_WKCON_WKEG_PIN5 (0x00000020UL) +#define MD_SYSCFG_WKCON_WKEG_PIN4 (0x00000010UL) +#define MD_SYSCFG_WKCON_WKEG_PIN3 (0x00000008UL) +#define MD_SYSCFG_WKCON_WKEG_PIN2 (0x00000004UL) +#define MD_SYSCFG_WKCON_WKEG_PIN1 (0x00000002UL) +#define MD_SYSCFG_WKCON_WKEG_PIN0 (0x00000001UL) +/** + * @} MD_SYSCFG_WKCON_WKEG + */ + +/** @defgroup MD_SYSCFG_WKCON_WKEN WKENx: Enable WKUPx pin or wakeup event + * @{ + */ +#define MD_SYSCFG_WKCON_WKEN_NRST (0x00000800UL) +#define MD_SYSCFG_WKCON_WKEN_PVD (0x00000400UL) +#define MD_SYSCFG_WKCON_WKEN_CMP0 (0x00000200UL) +#define MD_SYSCFG_WKCON_WKEN_RTC (0x00000100UL) +#define MD_SYSCFG_WKCON_WKEN_PIN7 (0x00000080UL) +#define MD_SYSCFG_WKCON_WKEN_PIN6 (0x00000040UL) +#define MD_SYSCFG_WKCON_WKEN_PIN5 (0x00000020UL) +#define MD_SYSCFG_WKCON_WKEN_PIN4 (0x00000010UL) +#define MD_SYSCFG_WKCON_WKEN_PIN3 (0x00000008UL) +#define MD_SYSCFG_WKCON_WKEN_PIN2 (0x00000004UL) +#define MD_SYSCFG_WKCON_WKEN_PIN1 (0x00000002UL) +#define MD_SYSCFG_WKCON_WKEN_PIN0 (0x00000001UL) +/** + * @} MD_SYSCFG_WKCON_WKEN + */ + +/** @defgroup MD_SYSCFG_WKSTAT_FG FGx: WKUPx pin or wakeup event flag + * @{ + */ +#define MD_SYSCFG_WKSTAT_FG_NRST (0x00000800UL) +#define MD_SYSCFG_WKSTAT_FG_PVD (0x00000400UL) +#define MD_SYSCFG_WKSTAT_FG_CMP0 (0x00000200UL) +#define MD_SYSCFG_WKSTAT_FG_RTC (0x00000100UL) +#define MD_SYSCFG_WKSTAT_FG_PIN7 (0x00000080UL) +#define MD_SYSCFG_WKSTAT_FG_PIN6 (0x00000040UL) +#define MD_SYSCFG_WKSTAT_FG_PIN5 (0x00000020UL) +#define MD_SYSCFG_WKSTAT_FG_PIN4 (0x00000010UL) +#define MD_SYSCFG_WKSTAT_FG_PIN3 (0x00000008UL) +#define MD_SYSCFG_WKSTAT_FG_PIN2 (0x00000004UL) +#define MD_SYSCFG_WKSTAT_FG_PIN1 (0x00000002UL) +#define MD_SYSCFG_WKSTAT_FG_PIN0 (0x00000001UL) +/** + * @} MD_SYSCFG_WKSTAT_FG + */ + +/** + * @} MD_SYSCFG_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_SYSCFG_Public_Macros SYSCFG Public Macros + * @{ + */ + +/** + * @brief Get Current Memory mapping Status + * @param syscfg SYSCFG Instance + * @retval The retval can be one of the following values: + * @arg @ref MD_SYSCFG_REALMOD_MAIN + * @arg @ref MD_SYSCFG_REALMOD_SYSTEM + * @arg @ref MD_SYSCFG_REALMOD_SRAM + */ +__STATIC_INLINE uint32_t md_syscfg_get_remap_REALMOD(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->REMAP, SYSCFG_REMAP_REALMOD_MSK)>>SYSCFG_REMAP_REALMOD_POSS); +} +/** + * @brief Set Remap Main Flash Base Address Selection + * @note If set 0x1, it means second 4k Byte, If set 0x2, it means third 4k Byte, and so on. + * @param syscfg SYSCFG Instance + * @param efbase This parameter can be one of the following values: + * @arg Max Value 15 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_remap_efbase(SYSCFG_TypeDef *syscfg, uint32_t efbase) +{ + MODIFY_REG(syscfg->REMAP, SYSCFG_REMAP_EFBASE_MSK, (efbase<REMAP, SYSCFG_REMAP_EFBASE_MSK)>>SYSCFG_REMAP_EFBASE_POSS); +} +/** + * @brief Set Memory mapping selection bits + * @param syscfg SYSCFG Instance + * @param memmod This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_MEMMOD_MAIN + * @arg @ref MD_SYSCFG_MEMMOD_SYSTEM + * @arg @ref MD_SYSCFG_MEMMOD_SRAM + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_remap_memmod(SYSCFG_TypeDef *syscfg, uint32_t memmod) +{ + MODIFY_REG(syscfg->REMAP, SYSCFG_REMAP_MEMMOD_MSK, (memmod<REMAP, SYSCFG_REMAP_MEMMOD_MSK)>>SYSCFG_REMAP_MEMMOD_POSS); +} +/** + * @brief Set Start Remap bit + * @note This bit set High to start remapping process, that will be auto clear when process was finish. + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_remap_remap(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->REMAP, SYSCFG_REMAP_REMAP_MSK); +} +/** + * @brief Get Start Remap bit + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_remap_remap(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->REMAP, SYSCFG_REMAP_REMAP_MSK)>>SYSCFG_REMAP_REMAP_POS); +} + +/** + * @brief Set IR Polarity + * @param syscfg SYSCFG Instance + * @param plr This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_PLR_INV_SEL1_AND_SEL2 + * @arg @ref MD_SYSCFG_PLR_SEL1_AND_SEL2 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_irsel_plr(SYSCFG_TypeDef *syscfg, uint32_t plr) +{ + MODIFY_REG(syscfg->IRSEL, SYSCFG_IRSEL_PLR_MSK, (plr<IRSEL, SYSCFG_IRSEL_PLR_MSK)>>SYSCFG_IRSEL_PLR_POS); +} +/** + * @brief Set IR Select 2 + * @param syscfg SYSCFG Instance + * @param sel2 This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_SEL2_OFF + * @arg @ref MD_SYSCFG_SEL2_GP16C2T4_CH1 + * @arg @ref MD_SYSCFG_SEL2_GP16C2T4_CH2 + * @arg @ref MD_SYSCFG_SEL2_UART3_TX + * @arg @ref MD_SYSCFG_SEL2_SUART2_TX + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_irsel_sel2(SYSCFG_TypeDef *syscfg, uint32_t sel2) +{ + MODIFY_REG(syscfg->IRSEL, SYSCFG_IRSEL_SEL2_MSK, (sel2<IRSEL, SYSCFG_IRSEL_SEL2_MSK)>>SYSCFG_IRSEL_SEL2_POSS); +} +/** + * @brief Set IR Select 1 + * @param syscfg SYSCFG Instance + * @param sel1 This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_SEL1_OFF + * @arg @ref MD_SYSCFG_SEL1_GP16C2T2_CH1 + * @arg @ref MD_SYSCFG_SEL1_GP16C2T2_CH2 + * @arg @ref MD_SYSCFG_SEL1_GP16C2T3_CH1 + * @arg @ref MD_SYSCFG_SEL1_GP16C2T3_CH2 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_irsel_sel1(SYSCFG_TypeDef *syscfg, uint32_t sel1) +{ + MODIFY_REG(syscfg->IRSEL, SYSCFG_IRSEL_SEL1_MSK, (sel1<IRSEL, SYSCFG_IRSEL_SEL1_MSK)>>SYSCFG_IRSEL_SEL1_POSS); +} + +/** + * @brief Set DBG Halt enable bit + * @note 0: The counter clock is fed even if the core is halted + * 1: The counter clock is stopped when the core is halted + * @param syscfg SYSCFG Instance + * @param sel1 This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_DBGH_EN_IWDT + * @arg @ref MD_SYSCFG_DBGH_EN_WWDT + * @arg @ref MD_SYSCFG_DBGH_EN_BS16T1 + * @arg @ref MD_SYSCFG_DBGH_EN_GP16C4T3 + * @arg @ref MD_SYSCFG_DBGH_EN_GP16C4T2 + * @arg @ref MD_SYSCFG_DBGH_EN_GP16C4T1 + * @arg @ref MD_SYSCFG_DBGH_EN_GP32C4T1 + * @arg @ref MD_SYSCFG_DBGH_EN_GP16C2T4 + * @arg @ref MD_SYSCFG_DBGH_EN_GP16C2T3 + * @arg @ref MD_SYSCFG_DBGH_EN_GP16C2T2 + * @arg @ref MD_SYSCFG_DBGH_EN_GP16C2T1 + * @arg @ref MD_SYSCFG_DBGH_EN_AD16C4T1 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_cfg_dbgh_en(SYSCFG_TypeDef *syscfg, uint32_t sel1) +{ + MODIFY_REG(syscfg->CFG, SYSCFG_CFG_DBGH_EN_MSK, (sel1<CFG, SYSCFG_CFG_DBGH_EN_MSK)>>SYSCFG_CFG_DBGH_EN_POSS); +} +/** + * @brief PVD lock enable bit + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_cfg_pvdlck(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_PVD_LCK_MSK); +} +/** + * @brief PVD lock disable bit + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_cfg_pvdlck(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_PVD_LCK_MSK); +} +/** + * @brief Get PVD lock bit + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_cfg_pvdlck(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_PVD_LCK_MSK)>>SYSCFG_CFG_PVD_LCK_POS); +} +/** + * @brief Clock security system lock enable bit + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_cfg_csslck(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_CSS_LCK_MSK); +} +/** + * @brief Clock security system lock enable bit + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_cfg_csslck(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_CSS_LCK_MSK); +} +/** + * @brief Clock security system lock enable bit + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_cfg_csslck(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_CSS_LCK_MSK)>>SYSCFG_CFG_CSS_LCK_POS); +} +/** + * @brief Cortex-M0 LOCKUP bit enable bit + * @note This bit is set by software and cleared by a system reset. + * It can be use to enable and lock the connection of Cortex-M0 LOCKUP (Hardfault) output to AD16C4T/GP16C2T1-4 Break input. + * @note 1: Cortex-M0 LOCKUP output connected to AD16C4T/GP16C2T1/GP16C2T2/GP16C2T3/GP16C2T4 Break input + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_cfg_cpulck(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_CPU_LCK_MSK); +} +/** + * @brief Cortex-M0 LOCKUP bit disable bit + * @note 0: Cortex-M0 LOCKUP output disconnected from AD16C4T / GP16C2T1-4 Break input + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_cfg_cpulck(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_CPU_LCK_MSK); +} +/** + * @brief Get Cortex-M0 LOCKUP bit + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_cfg_cpulck(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_CPU_LCK_MSK)>>SYSCFG_CFG_CPU_LCK_POS); +} +/** + * @brief Set Voltage testing, This bit is set and cleared by software. + * @param syscfg SYSCFG Instance + * @param vtst This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_VTST_LDO + * @arg @ref MD_SYSCFG_VTST_BANDGAP_REF + * @arg @ref MD_SYSCFG_VTST_LDO1V2 + * @arg @ref MD_SYSCFG_VTST_LDO1V5 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_cfg_vtst(SYSCFG_TypeDef *syscfg, uint32_t vtst) +{ + MODIFY_REG(syscfg->CFG, SYSCFG_CFG_VTST_MSK, (vtst<CFG, SYSCFG_CFG_VTST_MSK)>>SYSCFG_CFG_VTST_POSS); +} +/** + * @brief Enable External NRST Pin reset request + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_cfg_nrstreq(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_NRSTREQ_MSK); +} +/** + * @brief Disable External NRST Pin reset request + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_cfg_nrstreq(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_NRSTREQ_MSK); +} +/** + * @brief External NRST Pin reset request + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_cfg_nrstreq(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_NRSTREQ_MSK)>>SYSCFG_CFG_NRSTREQ_POS); +} +/** + * @brief ADC/DAC current generator enabled + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_cfg_currgen(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_CURRGEN_MSK); +} +/** + * @brief ADC/DAC current generator disabled + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_cfg_currgen(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_CURRGEN_MSK); +} +/** + * @brief ADC/DAC current generator status + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_cfg_currgen(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_CURRGEN_MSK)>>SYSCFG_CFG_CURRGEN_POS); +} +/** + * @brief Temperature sensor enabled + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_cfg_tempen(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_TEMPEN_MSK); +} +/** + * @brief Temperature sensor disabled + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_cfg_tempen(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_TEMPEN_MSK); +} +/** + * @brief Get Temperature sensor status + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_cfg_tempen(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_TEMPEN_MSK)>>SYSCFG_CFG_TEMPEN_POS); +} +/** + * @brief Voltage reference enabled + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_cfg_vrefen(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->CFG, SYSCFG_CFG_VREFEN_MSK); +} +/** + * @brief Voltage reference disabled + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_cfg_vrefen(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->CFG, SYSCFG_CFG_VREFEN_MSK); +} +/** + * @brief Get Voltage reference status + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_cfg_vrefen(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->CFG, SYSCFG_CFG_VREFEN_MSK)>>SYSCFG_CFG_VREFEN_POS); +} +/** + * @brief Set These bits are written by software to select the voltage reference level by the ADC/DAC: + * @param syscfg SYSCFG Instance + * @param vlrs This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_VRLS_1V5 + * @arg @ref MD_SYSCFG_VRLS_2V + * @arg @ref MD_SYSCFG_VRLS_2V5 + * @arg @ref MD_SYSCFG_VRLS_3V + * @arg @ref MD_SYSCFG_VRLS_3V5 + * @arg @ref MD_SYSCFG_VRLS_4V + * @arg @ref MD_SYSCFG_VRLS_4V5 + * @arg @ref MD_SYSCFG_VRLS_5V + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_cfg_vlrs(SYSCFG_TypeDef *syscfg, uint32_t vlrs) +{ + MODIFY_REG(syscfg->CFG, SYSCFG_CFG_VRLS_MSK, (vlrs<CFG, SYSCFG_CFG_VRLS_MSK)>>SYSCFG_CFG_VRLS_POSS); +} + +/** + * @brief WKCON0-7 IO Setting Value LOCKED enabled + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_pwcon_iolock(SYSCFG_TypeDef *syscfg) +{ + MODIFY_REG(syscfg->PWCON, SYSCFG_PWCON_IOLOCK_MSK, (ENABLE<PWCON, SYSCFG_PWCON_IOLOCK_MSK, (DISABLE<PWCON, SYSCFG_PWCON_IOLOCK_MSK)>>SYSCFG_PWCON_IOLOCK_POS); +} +/** + * @brief Set BandGap Trimming Value + * @param syscfg SYSCFG Instance + * @param bgtrim This parameter can be one of the following values: + * @arg Max Value 15 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_pwcon_bgtrim(SYSCFG_TypeDef *syscfg, uint32_t bgtrim) +{ + MODIFY_REG(syscfg->PWCON, SYSCFG_PWCON_BGTRIM_MSK, (bgtrim<PWCON, SYSCFG_PWCON_BGTRIM_MSK)>>SYSCFG_PWCON_BGTRIM_POSS); +} +/** + * @brief HSI auto calibration result value LOCK + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_pwcon_hrclock(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->PWCON, SYSCFG_PWCON_HRCLOCK_MSK); +} +/** + * @brief HSI auto calibration result value unLOCK + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_pwcon_hrclock(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->PWCON, SYSCFG_PWCON_HRCLOCK_MSK); +} +/** + * @brief Get HSI auto calibration result value + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_pwcon_hrclock(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->PWCON, SYSCFG_PWCON_HRCLOCK_MSK)>>SYSCFG_PWCON_HRCLOCK_POS); +} +/** + * @brief Set HSI auto calibration result value + * @param syscfg SYSCFG Instance + * @param hsitrim This parameter can be one of the following values: + * @arg Max Value 255 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_pwcon_hrctrim(SYSCFG_TypeDef *syscfg, uint32_t hsitrim) +{ + MODIFY_REG(syscfg->PWCON, SYSCFG_PWCON_HRCTRIM_MSK, (hsitrim<PWCON, SYSCFG_PWCON_HRCTRIM_MSK)>>SYSCFG_PWCON_HRCTRIM_POSS); +} +/** + * @brief Set LSI Driver Select + * @param syscfg SYSCFG Instance + * @param loscdrv This parameter can be one of the following values: + * @arg Max Value 7 + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_pwcon_loscdrv(SYSCFG_TypeDef *syscfg, uint32_t loscdrv) +{ + MODIFY_REG(syscfg->PWCON, SYSCFG_PWCON_LOSCDRV_MSK, (loscdrv<PWCON, SYSCFG_PWCON_LOSCDRV_MSK)>>SYSCFG_PWCON_LOSCDRV_POSS); +} +/** + * @brief Power voltage detector(PVD) enable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_pwcon_pvden(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->PWCON, SYSCFG_PWCON_PVDEN_MSK); +} +/** + * @brief Power voltage detector(PVD) disable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_disable_pwcon_pvden(SYSCFG_TypeDef *syscfg) +{ + CLEAR_BIT(syscfg->PWCON, SYSCFG_PWCON_PVDEN_MSK); +} +/** + * @brief Get Power voltage detector(PVD) status + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_pwcon_pvden(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->PWCON, SYSCFG_PWCON_PVDEN_MSK)>>SYSCFG_PWCON_PVDEN_POS); +} +/** + * @brief Set power voltage detector + * @note These bits are written by software to select the voltage threshold detected by the power voltage detector + * @param syscfg SYSCFG Instance + * @param pvls This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_PVLS_R1V9_F2V + * @arg @ref MD_SYSCFG_PVLS_R2V1_F2V2 + * @arg @ref MD_SYSCFG_PVLS_R2V3_F2V4 + * @arg @ref MD_SYSCFG_PVLS_R2V5_F2V6 + * @arg @ref MD_SYSCFG_PVLS_R2V7_F2V8 + * @arg @ref MD_SYSCFG_PVLS_R2V9_F3V + * @arg @ref MD_SYSCFG_PVLS_R3V1_F3V2 + * @arg @ref MD_SYSCFG_PVLS_R3V3_F3V4 + * @arg @ref MD_SYSCFG_PVLS_R3V5_F3V6 + * @arg @ref MD_SYSCFG_PVLS_R3V7_F3V8 + * @arg @ref MD_SYSCFG_PVLS_R3V9_F4V + * @arg @ref MD_SYSCFG_PVLS_R4V1_F4V2 + * @arg @ref MD_SYSCFG_PVLS_R4V3_F4V4 + * @arg @ref MD_SYSCFG_PVLS_R4V5_F4V6 + * @arg @ref MD_SYSCFG_PVLS_R4V7_F4V8 + * @arg @ref MD_SYSCFG_PVLS_R4V9_F5V + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_pwcon_pvls(SYSCFG_TypeDef *syscfg, uint32_t pvls) +{ + MODIFY_REG(syscfg->PWCON, SYSCFG_PWCON_PVLS_MSK, (pvls<PWCON, SYSCFG_PWCON_PVLS_MSK)>>SYSCFG_PWCON_PVLS_POSS); +} + +/** + * @brief Clear Wake Flag enable + * @param syscfg SYSCFG Instance + * @retval None + */ +__STATIC_INLINE void md_syscfg_enable_wkcon_wkclr(SYSCFG_TypeDef *syscfg) +{ + SET_BIT(syscfg->WKCON, SYSCFG_WKCON_WKCLR_MSK); +} +/** + * @brief Set Low Power Level Select + * @param syscfg SYSCFG Instance + * @param lpls The parameter can be one of the following values: + * @arg @ref MD_SYSCFG_LPLS_LV0 + * @arg @ref MD_SYSCFG_LPLS_LV1 + * @arg @ref MD_SYSCFG_LPLS_LV2 + * @arg @ref MD_SYSCFG_LPLS_LV3 + * @arg @ref MD_SYSCFG_LPLS_LV4 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_wkcon_lpls(SYSCFG_TypeDef *syscfg, uint32_t lpls) +{ + MODIFY_REG(syscfg->WKCON, SYSCFG_WKCON_LPLS_MSK, (lpls<WKCON, SYSCFG_WKCON_LPLS_MSK)>>SYSCFG_WKCON_LPLS_POSS); +} +/** + * @brief Set WKUPx pin edge sensitive type select + * @note 0 : Falling Edge-sensitive (default) + * 1 : Rising Edge-sensitive + * @param syscfg SYSCFG Instance + * @param wkeg This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_WKCON_WKEG_NRST + * @arg @ref MD_SYSCFG_WKCON_WKEG_PVD + * @arg @ref MD_SYSCFG_WKCON_WKEG_CMP0 + * @arg @ref MD_SYSCFG_WKCON_WKEG_RTC + * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN7 + * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN6 + * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN5 + * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN4 + * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN3 + * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN2 + * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN1 + * @arg @ref MD_SYSCFG_WKCON_WKEG_PIN0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_wkcon_wkeg(SYSCFG_TypeDef *syscfg, uint32_t wkeg) +{ + MODIFY_REG(syscfg->WKCON, SYSCFG_WKCON_WKEG_MSK, (wkeg<WKCON, SYSCFG_WKCON_WKEG_MSK)>>SYSCFG_WKCON_WKEG_POSS); +} + +/** + * @brief Set Enable WKUPx pin or wakeup event + * @note 0: WKUPx pin is used for general purpose I/Os. An event on the WKUPx pin does not wakeup the device from Standby mode. + * 1: WKUPx pin is used for wakeup from Standby mode. + * @param syscfg SYSCFG Instance + * @param wken This parameter can be one of the following values: + * @arg @ref MD_SYSCFG_WKCON_WKEN_NRST + * @arg @ref MD_SYSCFG_WKCON_WKEN_PVD + * @arg @ref MD_SYSCFG_WKCON_WKEN_CMP0 + * @arg @ref MD_SYSCFG_WKCON_WKEN_RTC + * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN7 + * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN6 + * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN5 + * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN4 + * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN3 + * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN2 + * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN1 + * @arg @ref MD_SYSCFG_WKCON_WKEN_PIN0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_wkcon_wken(SYSCFG_TypeDef *syscfg, uint32_t wken) +{ + MODIFY_REG(syscfg->WKCON, SYSCFG_WKCON_WKEN_MSK, (wken<WKCON, SYSCFG_WKCON_WKEN_MSK)>>SYSCFG_WKCON_WKEN_POSS); +} +/** + * @brief Set SYSCFG WCON register + * @param syscfg SYSCFG Instance + * @param uint32_t wcon + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_wkcon(SYSCFG_TypeDef *syscfg, uint32_t wcon) +{ + WRITE_REG(syscfg->WKCON, wcon); +} + +/** + * @brief Get Wakeup Flag + * @param syscfg SYSCFG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_syscfg_get_wkstat_flag(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->WKSTAT, SYSCFG_WKSTAT_FLAG_MSK)>>SYSCFG_WKSTAT_FLAG_POS); +} +/** + * @brief Get WKCON pin0 or wakeup event flag. + * @note When this bit was set to 1, a wakeup event occurs. + * @param syscfg SYSCFG Instance + * @retval State of bit. + * @arg @ref MD_SYSCFG_WKSTAT_FG_NRST + * @arg @ref MD_SYSCFG_WKSTAT_FG_PVD + * @arg @ref MD_SYSCFG_WKSTAT_FG_CMP0 + * @arg @ref MD_SYSCFG_WKSTAT_FG_RTC + * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN7 + * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN6 + * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN5 + * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN4 + * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN3 + * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN2 + * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN1 + * @arg @ref MD_SYSCFG_WKSTAT_FG_PIN0 + */ +__STATIC_INLINE uint32_t md_syscfg_get_wkstat_fg(SYSCFG_TypeDef *syscfg) +{ + return (READ_BIT(syscfg->WKSTAT, SYSCFG_WKSTAT_FG_MSK)>>SYSCFG_WKSTAT_FG_POSS); +} + + +/** + * @brief Set Backup Register 0. + * @note This field was saved in the always on block, reset by power reset. + * @param syscfg SYSCFG Instance + * @param bkreg0 This parameter can be one of the following values: + * @arg Max Value 0xFFFFFFFF + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_bkreg0(SYSCFG_TypeDef *syscfg, uint32_t bkreg0) +{ + MODIFY_REG(syscfg->BKREG0, SYSCFG_BKREG0_BKREG0_MSK, (bkreg0<BKREG0, SYSCFG_BKREG0_BKREG0_MSK)>>SYSCFG_BKREG0_BKREG0_POSS); +} + +/** + * @brief Set Backup Register 1. + * @note This field was saved in the always on block, reset by power reset. + * @param syscfg SYSCFG Instance + * @param bkreg1 This parameter can be one of the following values: + * @arg Max Value 0xFFFFFFFF + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_bkreg1(SYSCFG_TypeDef *syscfg, uint32_t bkreg1) +{ + MODIFY_REG(syscfg->BKREG1, SYSCFG_BKREG1_BKREG1_MSK, (bkreg1<BKREG1, SYSCFG_BKREG1_BKREG1_MSK)>>SYSCFG_BKREG1_BKREG1_POSS); +} + +/** + * @brief Set Backup Register 2. + * @note This field was saved in the always on block, reset by power reset. + * @param syscfg SYSCFG Instance + * @param bkreg2 This parameter can be one of the following values: + * @arg Max Value 0xFFFFFFFF + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_bkreg2(SYSCFG_TypeDef *syscfg, uint32_t bkreg2) +{ + MODIFY_REG(syscfg->BKREG2, SYSCFG_BKREG2_BKREG2_MSK, (bkreg2<BKREG2, SYSCFG_BKREG2_BKREG2_MSK)>>SYSCFG_BKREG2_BKREG2_POSS); +} + +/** + * @brief Set Backup Register 3. + * @note This field was saved in the always on block, reset by power reset. + * @param syscfg SYSCFG Instance + * @param bkreg3 This parameter can be one of the following values: + * @arg Max Value 0xFFFFFFFF + * @arg Min Value 0 + * @retval None + */ +__STATIC_INLINE void md_syscfg_set_bkreg3(SYSCFG_TypeDef *syscfg, uint32_t bkreg3) +{ + MODIFY_REG(syscfg->BKREG3, SYSCFG_BKREG3_BKREG3_MSK, (bkreg3<BKREG3, SYSCFG_BKREG3_BKREG3_MSK)>>SYSCFG_BKREG3_BKREG3_POSS); +} + +/** + * @} MD_SYSCFG_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_SYSCFG_Public_Functions SYSCFG Public Functions + * @{ + */ + +/** @defgroup MD_SYSCFG_PF_Basic_Configuration Basic Configuration + * @{ + */ + +/** + * @} MD_SYSCFG_PF_Basic_Configuration + */ + +/** @defgroup MD_SYSCFG_PF_Data_Access Data Access + * @{ + */ + +/** + * @} MD_SYSCFG_PF_Data_Access + */ + +/** @defgroup MD_SYSCFG_PF_Init Initialization and de-initialization functions + * @{ + */ + +/** + * @} MD_SYSCFG_PF_Init + */ + +/** + * @} MD_SYSCFG_Public_Functions + */ + +#endif + +/** + * @} SYSCFG + */ + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} + +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_tick.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_tick.h new file mode 100644 index 0000000000000000000000000000000000000000..f8570471e94ffc7d585f1de3e7d8293cbce7c2fb --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_tick.h @@ -0,0 +1,433 @@ +/** + ****************************************************************************** + * @file md_TICK.h + * @brief ES32F0271 TICK HEAD File. + * + * @version V1.00.01 + * @date 11/20/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_TICK_H__ +#define __MD_TICK_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_tick.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (TICK) + +/** @defgroup TICK TICK + * @brief TICK micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ + +/** + * @brief MD TICK Parameter Structure definition + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_TICK_Public_Constants TICK Public Constants + * @{ + */ + +/** + * @} MD_TICK_Public_Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_TICK_Public_Macros TICK Public Macros + * @{ + */ + +/** @defgroup MD_TICK_PM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in TICK register + * @param __INSTANCE__ TICK Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define MD_TICK_WRITEREG(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in TICK register + * @param __INSTANCE__ TICK Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define MD_TICK_READREG(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + +/** + * @brief Modify value in TICK register + * @param __INSTANCE__ TICK Instance + * @param __REG__ Register to be written + * @param __MASK__ Mask value to be written in the register + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define MD_TICK_MODIFYREG(__INSTANCE__, __REG__, __MASK__, __VALUE__) MODIFY_REG(__INSTANCE__->__REG__, __MASK__, (__VALUE__)) + +/** + * @brief Set bit value in TICK register + * @param __INSTANCE__ TICK Instance + * @param __REG__ Register to be read + * @param __MASK__ Mask value to be set in the register + * @retval None + */ +#define MD_TICK_SET_BIT(__INSTANCE__, __REG__, __MASK__) SET_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @brief Clear bit value in TICK register + * @param __INSTANCE__ TICK Instance + * @param __REG__ Register to be read + * @param __MASK__ Mask value to be cleased in the register + * @retval None + */ +#define MD_TICK_CLEAR_BIT(__INSTANCE__, __REG__, __MASK__) CLEAR_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @brief Read bit value in TICK register + * @param __INSTANCE__ TICK Instance + * @param __REG__ Register to be read + * @param __MASK__ Mask value to be read in the register + * @retval Register bit value + */ +#define MD_TICK_READBIT(__INSTANCE__, __REG__, __MASK__) READ_BIT(__INSTANCE__->__REG__, __MASK__) + +/** + * @} MD_TICK_PM_WRITE_READ + */ + +/** @defgroup MD_TICK_Macro_Drivers TICK Public Macro Drivers + * @{ + */ + +/** + * @brief Set TICK CSR + * @param @arg Max Value 0x7 + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_csr(uint32_t U32) +{ + MD_TICK_WRITEREG(TICK, CSR, U32); +} + +/** + * @brief Get TICK CSR + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x10007 + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_tick_get_csr(void) +{ + return (MD_TICK_READREG(TICK, CSR)); +} + +/** + * @brief Get TICK CSR Count Flag + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_tick_is_active_csr_countflag(void) +{ + return (MD_TICK_READBIT(TICK, CSR, TICK_CSR_COUNTFLAG_MSK)>>TICK_CSR_COUNTFLAG_POS); +} + +/** + * @brief Set TICK CSR Clock Source + * @param @arg Max Value 0x1 + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_csr_clksource(uint32_t ClkSource) +{ + MD_TICK_MODIFYREG(TICK, CSR, TICK_CSR_CLKSOURCE_MSK, (ClkSource<>TICK_CSR_CLKSOURCE_POS); +} + +/** + * @brief Enable TICK CSR Tick Interrupt + * @param None + * @retval None + */ +__STATIC_INLINE void md_tick_enable_csr_tickint(void) +{ + MD_TICK_SET_BIT(TICK, CSR, TICK_CSR_TICKINT_MSK); +} + +/** + * @brief Disable TICK CSR Tick Interrupt + * @param None + * @retval None + */ +__STATIC_INLINE void md_tick_disable_csr_tickint(void) +{ + MD_TICK_CLEAR_BIT(TICK, CSR, TICK_CSR_TICKINT_MSK); +} + +/** + * @brief is TICK CSR Tick Interrupt Enabled + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_tick_is_enabled_csr_tickint(void) +{ + return (MD_TICK_READBIT(TICK, CSR, TICK_CSR_TICKINT_MSK)>>TICK_CSR_TICKINT_POS); +} + +/** + * @brief Enable TICK CSR Enable + * @param None + * @retval None + */ +__STATIC_INLINE void md_tick_enable_csr_enable(void) +{ + MD_TICK_SET_BIT(TICK, CSR, TICK_CSR_ENABLE_MSK); +} + +/** + * @brief Disable TICK CSR Enable + * @param None + * @retval None + */ +__STATIC_INLINE void md_tick_disable_csr_enable(void) +{ + MD_TICK_CLEAR_BIT(TICK, CSR, TICK_CSR_ENABLE_MSK); +} + +/** + * @brief is TICK CSR Enable Enabled + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_tick_is_enabled_csr_enable(void) +{ + return (MD_TICK_READBIT(TICK, CSR, TICK_CSR_ENABLE_MSK)>>TICK_CSR_ENABLE_POS); +} + +/** + * @brief Set TICK RVR + * @param @arg Max Value 0xffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_rvr(uint32_t U32) +{ + MD_TICK_WRITEREG(TICK, RVR, U32); +} + +/** + * @brief Get TICK RVR + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_tick_get_rvr(void) +{ + return (MD_TICK_READREG(TICK, RVR)); +} + +/** + * @brief Set TICK RVR Reload + * @param @arg Max Value 0xfffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_rvr_reload(uint32_t Reload) +{ + MD_TICK_MODIFYREG(TICK, RVR, TICK_RVR_RELOAD_MSK, (Reload<>TICK_RVR_RELOAD_POSS); +} + +/** + * @brief Set TICK CVR + * @param @arg Max Value 0xffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_cvr(uint32_t U32) +{ + MD_TICK_WRITEREG(TICK, CVR, U32); +} + +/** + * @brief Get TICK CVR + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_tick_get_cvr(void) +{ + return (MD_TICK_READREG(TICK, CVR)); +} + +/** + * @brief Set TICK CVR Current + * @param @arg Max Value 0xfffffff + * @arg Min Value 0x0 + * @retval None + */ +__STATIC_INLINE void md_tick_set_cvr_current(uint32_t Current) +{ + MD_TICK_MODIFYREG(TICK, CVR, TICK_CVR_CURRENT_MSK, (Current<>TICK_CVR_CURRENT_POSS); +} + +/** + * @brief Get TICK CALIB + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xffffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_tick_get_calib(void) +{ + return (MD_TICK_READREG(TICK, CALIB)); +} + +/** + * @brief Get TICK CALIB NOREF + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_tick_get_calib_noref(void) +{ + return (MD_TICK_READBIT(TICK, CALIB, TICK_CALIB_NOREF_MSK)>>TICK_CALIB_NOREF_POS); +} + +/** + * @brief Get TICK CALIB SKEW + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0x1 + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint8_t md_tick_get_calib_skew(void) +{ + return (MD_TICK_READBIT(TICK, CALIB, TICK_CALIB_SKEW_MSK)>>TICK_CALIB_SKEW_POS); +} + +/** + * @brief Get TICK CALIB 10ms Value + * @param None + * @retval The retval can be one of the following values: + * @arg Max Value 0xfffffff + * @arg Min Value 0x0 + */ +__STATIC_INLINE uint32_t md_tick_get_calib_tenms(void) +{ + return (MD_TICK_READBIT(TICK, CALIB, TICK_CALIB_TENMS_MSK)>>TICK_CALIB_TENMS_POSS); +} + + +/** + * @} MD_TICK_Macro_Drivers + */ + +/** + * @} MD_TICK_Public_Macros + */ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_TICK_Public_Functions TICK Public Functions + * @{ + */ +void md_tick_init(void); +uint32_t md_tick_get_mscnt(void); +uint32_t md_tick_get_100uscnt(void); +uint32_t md_tick_get_10uscnt(void); +void md_tick_waitms(uint8_t Unit, uint16_t msCnt); +void md_tick_wait100us(uint16_t Unit, uint16_t usCnt); +void md_tick_wait10us(uint16_t Unit, uint16_t usCnt); +/** + * @} MD_TICK_Public_Functions + */ + +#endif + +/** + * @} TICK + */ + +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_uart.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..e638ab0a7a42502f0c50784d5bd83e04f7fd2ab4 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_uart.h @@ -0,0 +1,2874 @@ +/** + ****************************************************************************** + * @file md_UART.h + * @brief ES32F0271 UART Header File. + * + * @version V1.00.01 + * @date 04/12/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_UART_H__ +#define __MD_UART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include +#include "es32f0271.h" +#include "reg_uart.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (UART1) | defined (UART2) | defined (UART3) | defined (SUART1) | defined (SUART2) + +/** @defgroup UART UART + * @brief UART micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public types ---------------------------------------------------------------*/ +/** @defgroup MD_UART_Public_Types UART Public Init Type + * @{ + */ + +typedef struct +{ + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.*/ + + uint32_t BitOrder; /*!< Specifies the MSB of data bits will be transmitted or received first. + This parameter can be a value of @ref MD_UART_LCON_MSB_FIRST.*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref MD_UART_LCON_PS_EVEN.*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref MD_UART_LCON_STOP_1.*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref MD_UART_LCON_DLS_8.*/ + +} md_uart_init_typedef; + +/** + * @} MD_UART_Public_Types + */ + +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Public functions -----------------------------------------------------------*/ +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_UART_Public_Constants UART Public Constants + * @{ + */ + +/** @defgroup UART_BAUDRATE UART Baudrate Definitation + * @{ + */ +#define MD_UART_BAUDRATE_1200 (1200U) /* baud rate=1200 bps */ +#define MD_UART_BAUDRATE_2400 (2400U) /* baud rate=2400 bps */ +#define MD_UART_BAUDRATE_4800 (4800U) /* baud rate=4800 bps */ +#define MD_UART_BAUDRATE_9600 (9600U) /* baud rate=9600 bps */ +#define MD_UART_BAUDRATE_19200 (19200U) /* baud rate=19200 bps */ +#define MD_UART_BAUDRATE_38400 (38400U) /* baud rate=38400 bps */ +#define MD_UART_BAUDRATE_57600 (57600U) /* baud rate=57600 bps */ +#define MD_UART_BAUDRATE_115200 (115200U) /* baud rate=115200 bps */ +#define MD_UART_BAUDRATE_230400 (230400U) /* baud rate=230400 bps */ +#define MD_UART_BAUDRATE_460800 (460800U) /* baud rate=460800 bps */ +#define MD_UART_BAUDRATE_512000 (512000U) /* baud rate=512000 bps */ +#define MD_UART_BAUDRATE_921600 (921600U) /* baud rate=921600 bps */ +/** + * @} UART_BAUDRATE UART Baudrate Definitation + */ + +/** @defgroup UART_LCON UART_LCON Register + * @{ + */ +#define MD_UART_LCON_MSB_FIRST (1U) /** @brief data Most significant bit first */ +#define MD_UART_LCON_LSB_FIRST (0U) /** @brief data Least significant bit first */ +#define MD_UART_LCON_PS_EVEN (1U) /** @brief data Even parity bit selection */ +#define MD_UART_LCON_PS_ODD (0U) /** @brief data Odd parity bit selection */ +#define MD_UART_LCON_STOP_2 (1U) /** @brief data 2(1.5) Stop bit */ +#define MD_UART_LCON_STOP_1 (0U) /** @brief data 2(1.5) Stop bit */ +#define MD_UART_LCON_DLS_8 (0U) /** @brief data Date length 8 */ +#define MD_UART_LCON_DLS_7 (1U) /** @brief data Date length 7 */ +#define MD_UART_LCON_DLS_6 (2U) /** @brief data Date length 6 */ +#define MD_UART_LCON_DLS_5 (3U) /** @brief data Date length 5 */ +/** + * @} UART_LCON UART_LCON Register + */ + +/** @defgroup UART_MCON UART_MCON Register + * @{ + */ +#define MD_UART_MCON_ABRMOD_0 (0U) /** @brief data Receiver DMA disable */ +#define MD_UART_MCON_ABRMOD_1 (1U) /** @brief data Repeat auto-baud rate detection after timeout enable */ +#define MD_UART_MCON_ABRMOD_2 (2U) /** @brief data Repeat auto-baud rate detection after timeout disable */ +#define MD_UART_MCON_RTSSET_LOW (1U) /** @brief data RTSn set control bit RTSn level is 0 */ +#define MD_UART_MCON_RTSSET_HIGH (0U) /** @brief data RTSn set control bit RTSn level is 1 */ +/** + * @} UART_MCON UART_MCON Register + */ + +/** @defgroup UART_MCON UART_MCON Register + * @{ + */ +#define MD_UART_RS485_AADINV_LOW (0U) /** @brief data Low : Transfering data, High: Idle */ +#define MD_UART_RS485_AADINV_HIGH (1U) /** @brief data High: Transfering data, Low : Idle */ +/** + * @} UART_MCON UART_MCON Register + */ + +/** @defgroup UART_FCON UART_FCON Register + * @{ + */ +#define MD_UART_FCON_TXTH_0 (0U) /** @brief data Transmit FIFO trigger threshold: FIFO empty */ +#define MD_UART_FCON_TXTH_2 (1U) /** @brief data Transmit FIFO trigger threshold: 2 characters in the FIFO */ +#define MD_UART_FCON_TXTH_4 (2U) /** @brief data Transmit FIFO trigger threshold: 4 characters in the FIFO */ +#define MD_UART_FCON_TXTH_8 (3U) /** @brief data Transmit FIFO trigger threshold: 8 characters in the FIFO */ +#define MD_UART_FCON_TFRST (1U) /** @brief data Transmitter FIFO reset */ +#define MD_UART_FCON_RXTH_1 (0U) /** @brief data Receive FIFO trigger threshold: 1 character in the FIFO */ +#define MD_UART_FCON_RXTH_4 (1U) /** @brief data Receive FIFO trigger threshold: 4 characters in the FIFO */ +#define MD_UART_FCON_RXTH_8 (2U) /** @brief data Receive FIFO trigger threshold: 8 characters in the FIFO */ +#define MD_UART_FCON_RXTH_14 (3U) /** @brief data Receive FIFO trigger threshold: 14 characters in the FIFO */ +#define MD_UART_FCON_RFRST (1U) /** @brief data Receive FIFO reset */ +/** + * @} UART_FCON UART_FCON Register + */ + +/** + * @} MD_UART_Public_Constants UART Public Constants + */ + +/* Public macro ---------------------------------------------------------------*/ +/** @defgroup MD_UART_Public_Macros UART Public Macros + * @{ + */ + +/** + * @brief Read Receiver Buffer Register + * @note Contains the received data character. + * The RXBR register provides the parallel interface between the + * input shift register and the internal bus. + * When receiving with the parity enabled, the value read in the + * MSB bit is the received parity bit. + * @param UARTx UART Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t md_uart_get_rxbuf(UART_TypeDef *UARTx) +{ + return (uint16_t) ((READ_REG(UARTx->RXBUF))>>UART_RXBUF_RXBUF_POSS); +} + +/** + * @brief Write Transmit buffer register + * @note Contains the data character to be transmitted. + * The TXBR register provides the parallel interface between the + * internal bus and the output shift register. + * When transmitting with the parity enabled the value written in + * the MSB (bit 7 or bit 8 depending on the data length) has no + * effect because it is replaced by the parity. + * @param UARTx UART Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void md_uart_send_txbuf(UART_TypeDef *UARTx, uint8_t TxData) +{ + WRITE_REG (UARTx->TXBUF, (uint8_t)TxData); +} + +/** + * @brief Set UARTx Baud rate register. + * @note This bits can only be written when the UART is disabled. + * (RXEN and TXEN=0 in the LCR register). + * @param UARTx UART Instance. + * @param UART buad rate value. + * @retval None + */ +__STATIC_INLINE void md_uart_set_brr(UART_TypeDef *UARTx, uint32_t baudrate) +{ + WRITE_REG(UARTx->BRR, baudrate); +} + +/** + * @brief Get UARTx baud rate. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @retval UARTx Baudrate. + */ +__STATIC_INLINE uint32_t md_uart_get_brr(UART_TypeDef *UARTx) +{ + return (uint32_t) (READ_REG(UARTx->BRR)>>UART_BRR_BRR_POSS); +} + +/** + * @brief UARTx Transmitter enable. + * @note This bit enables the transmitter. It is set and cleared by + * software. + * @param UARTx UART Instance + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lcon_txen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_TXEN_MSK); +} + +/** + * @brief UARTx Transmitter disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lcon_txen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_TXEN_MSK); +} + +/** + * @brief Check if UART Transmitter is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_tx(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_TXEN_MSK) == (UART_LCON_TXEN_MSK)); +} + +/** + * @brief UARTx Receiver enable + * @note This bit enables the receiver. It is set and cleared by software. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_lcon_rxen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_RXEN_MSK); +} + +/** + * @brief UARTx Receiver Disable + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_lcon_rxen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_RXEN_MSK); +} + +/** + * @brief Check if UARTx Receiver is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_rxen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_RXEN_MSK) == (UART_LCON_RXEN_MSK)); +} + +/** + * @brief UARTx Debounce Enable. + * @note This bit enables the debounce. It is set and cleared by software. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lcon_decen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_DBCEN_MSK); +} + +/** + * @brief UART Debounce Disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lcon_dbcen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_DBCEN_MSK); +} + +/** + * @brief Check if UART Debounce is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_dbcen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_DBCEN_MSK) == (UART_LCON_DBCEN_MSK)); +} + +/** + * @brief Enable UARTx Break control bit. + * @note This is used to cause a break condition to be transmitted to the + * receiving device. The serial data output (Tx) is forced to the + * Spacing State (logic 0). + * This bit can only be written when the UART is disabled. + * (RXENand TXEN=0). + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_lcon_break(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_BREAK_MSK); +} + +/** + * @brief Disable UARTx Break control bit. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lcon_break(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_BREAK_MSK); +} + +/** + * @brief Check if UARTx Break control bit is enabled. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_break(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_BREAK_MSK) == (UART_LCON_BREAK_MSK)); +} + +/** + * @brief UARTx Swap TX/RX pins. + * @note This allows to work in the case of a cross-wired connection to another UART. + * This bit can only be written when the UART is disabled (RXEN and TXEN=0). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lcon_swap(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_SWAP_MSK); +} + +/** + * @brief UARTx Swap TX/RX pins disabl. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_disable_lcon_swap(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_SWAP_MSK); +} + +/** + * @brief Check if UART Swap TX/RX pins is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_swap(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_SWAP_MSK) == (UART_LCON_SWAP_MSK)); +} + +/** + * @brief UARTx TX pin active level inversion. + * @note This allows the use of an external inverter on the TX line. + * This bit can only be written when the UART is disabled (RXEN and TXEN=0). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lcon_txinv(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_TXINV_MSK); +} + +/** + * @brief UARTx TX pin active level inversion disable. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lcon_txinv(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_TXINV_MSK); +} + +/** + * @brief Check if UARTx TX pin active level is inverted. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_txinv(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_TXINV_MSK) == (UART_LCON_TXINV_MSK)); +} + +/** + * @brief UARTx RX pin active level inversion. + * @note This allows the use of an external inverter on the RX line. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lcon_rxinv(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_RXINV_MSK); +} + +/** + * @brief UARTx RX pin active level inversion disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lcon_rxinv(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_RXINV_MSK); +} + +/** + * @brief Check if UART RX pin active level is inverted. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_rxinv(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_RXINV_MSK) == (UART_LCON_RXINV_MSK)); +} + +/** + * @brief UARTx Binary data inversion. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * The parity bit is also inverted. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lcon_datainv(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_RXINV_MSK); +} + +/** + * @brief UARTx Binary data inverted disable. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lcon_datainv(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_RXINV_MSK); +} + +/** + * @brief Check if UARTx Binary data is inverted. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_datainv(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_DATAINV_MSK) == (UART_LCON_DATAINV_MSK)); +} + +/** + * @brief Set UARTx Most significant bit first. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @param msb This parameter can be one of the following values: + * @arg @ref MD_UART_LCON_LSB_FIRST + * @arg @ref MD_UART_LCON_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void md_uart_set_lcon_msb(UART_TypeDef *UARTx, uint32_t msb) +{ + MODIFY_REG(UARTx->LCON, UART_LCON_MSB_MSK, msb<LCON, UART_LCON_MSB_MSK))>>UART_LCON_MSB_POS); +} + +/** + * @brief UARTx Parity bit selection. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @param parity This parameter can be one of the following values: + * @arg @ref MD_UART_LCON_PS_ODD + * @arg @ref MD_UART_LCON_PS_EVEN + * @retval None + */ +__STATIC_INLINE void md_uart_set_lcon_ps(UART_TypeDef *UARTx, uint32_t parity) +{ + MODIFY_REG(UARTx->LCON, UART_LCON_PS_MSK, parity<LCON, UART_LCON_PS_MSK))>>UART_LCON_PS_POS); +} + +/** + * @brief UARTx Parity enable. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lcon_pe(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_LCON_PE_MSK); +} + +/** + * @brief UARTx Parity disable. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lcon_pe(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_LCON_PE_MSK); +} + +/** + * @brief Check if UARTx Parity is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lcon_pe(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LCON, UART_LCON_PE_MSK) == (UART_LCON_PE_MSK)); +} + +/** + * @brief Set UARTx Stop bit. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0) + * @param UARTx UART Instance. + * @param stop This parameter can be one of the following values: + * @arg @ref MD_UART_LCON_STOP_1 + * @arg @ref MD_UART_LCON_STOP_2 + * @retval None + */ +__STATIC_INLINE void md_uart_set_lcon_stop(UART_TypeDef *UARTx, uint32_t stop) +{ + MODIFY_REG(UARTx->LCON, UART_LCON_STOP_MSK, stop<LCON, UART_LCON_STOP_MSK))>>UART_LCON_STOP_POS); +} + +/** + * @brief UARTx Date length selection. + * @note This bit can only be written when UART is disabled(TXEN and RXEN=0). + * @param UARTx UART Instance. + * @param width This parameter can be one of the following values: + * @arg @ref MD_UART_LCON_DLS_8 + * @arg @ref MD_UART_LCON_DLS_7 + * @arg @ref MD_UART_LCON_DLS_6 + * @arg @ref MD_UART_LCON_DLS_5 + * @retval None + */ +__STATIC_INLINE void md_uart_set_lcon_dls(UART_TypeDef *UARTx, uint32_t width) +{ + MODIFY_REG(UARTx->LCON, UART_LCON_DLS_MSK, width<LCON, UART_LCON_DLS_MSK))>>UART_LCON_DLS_POSS); +} + +/** + * @brief UARTx Transmitter DMA enable. + * @note This bit is set and cleared by software. This bit enables the DMA transmitter. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_mcon_txdmaen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_TXDMAEN_MSK); +} + +/** + * @brief UARTx Transmitter DMA enable disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_mcon_txdmaen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_TXDMAEN_MSK); +} + +/** + * @brief Check if UARTx Transmitter DMA is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_txdmaen(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->MCON, UART_MCON_TXDMAEN_MSK) == (UART_MCON_TXDMAEN_MSK)); +} + +/** + * @brief UARTx Receiver DMA enable. + * @note This bit is set and cleared by software. This bit enables the DMA Receiver. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_mcon_rxdmaen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_RXDMAEN_MSK); +} + +/** + * @brief UARTx Receiver DMA disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_mcon_rxdmaen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_RXDMAEN_MSK); +} + +/** + * @brief Check if UARTx UARTx Receiver DMA is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_rxdmaen(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->MCON, UART_MCON_RXDMAEN_MSK) == (UART_MCON_RXDMAEN_MSK)); +} + +/** + * @brief UARTx Auto baud rate detection repeat enable. + * @note This bit is set to enable baud rate detection repeat one more time + * after the first failure of auto-baud rate detection. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_mcon_abrrept(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_MCON_ABRREPT_MSK); +} + +/** + * @brief UARTx Auto baud rate detection repeat disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_mcon_abrrept(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_MCON_ABRREPT_MSK); +} + +/** + * @brief Check if UARTx Auto baud rate detection repeat is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_abrrept(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_ABRREPT_MSK) == (UART_MCON_ABRREPT_MSK)); +} + +/** + * @brief Set UARTx Auto baud rate mode. + * @note MD_UART_MCON_ABRMOD_0: Mode 0 detect falling edge to second falling edge (detect 2 Bps). + * MD_UART_MCON_ABRMOD_1: Mode 1 detect falling edge to first rising edge (detect 1 Bps). + * MD_UART_MCON_ABRMOD_2: Mode 2 detect falling edge to first rising edge (detect 2 Bps). + * @param UARTx UART Instance. + * @param mode This parameter can be one of the following values: + * @arg @ref MD_UART_MCON_ABRMOD_0 + * @arg @ref MD_UART_MCON_ABRMOD_1 + * @arg @ref MD_UART_MCON_ABRMOD_2 + * @retval None + */ +__STATIC_INLINE void md_uart_set_mcon_abrmod(UART_TypeDef *UARTx, uint32_t mode) +{ + MODIFY_REG(UARTx->MCON, UART_MCON_ABRMOD_MSK, mode<MCON, UART_MCON_ABRMOD_MSK))>>UART_MCON_ABRMOD_POSS); +} + +/** + * @brief UARTx Auto baud rate enable. + * @note This bit is set by software and cleared by hardware after the + * auto-baud rate finish. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_mcon_abren(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LCON, UART_MCON_ABREN_MSK); +} + +/** + * @brief UARTx Auto baud rate disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_mcon_abren(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LCON, UART_MCON_ABREN_MSK); +} + +/** + * @brief Check if UARTx Auto baud rate is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_abren(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_ABREN_MSK) == (UART_MCON_ABREN_MSK)); +} + +/** + * @brief UARTx break request enable. + * @note This bit is set by software and automatically cleared by + * hardware in the next clock cycle. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_mcon_bkreq(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_BKREQ_MSK); +} + +/** + * @brief UARTx break request disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_mcon_bkreq(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_BKREQ_MSK); +} + +/** + * @brief Check if UARTx break request is enabled + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_bkreq(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_BKREQ_MSK) == (UART_MCON_BKREQ_MSK)); +} + +/** + * @brief UARTx Half-duplex enable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_mcon_hden(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_HDEN_MSK); +} + +/** + * @brief UARTx Half-duplex disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_mcon_hden(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_HDEN_MSK); +} + +/** + * @brief Check if UARTx Half-duplex is enabled. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_hden(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_HDEN_MSK) == (UART_MCON_HDEN_MSK)); +} + +/** + * @brief UARTx IrDA mode enable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_mcon_iren(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_IREN_MSK); +} + +/** + * @brief UARTx IrDA mode disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_mcon_iren(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_IREN_MSK); +} + +/** + * @brief Check if UARTx IrDA mode is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_iren(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_IREN_MSK) == (UART_MCON_IREN_MSK)); +} + +/** + * @brief UARTx Auto flow control enable. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_mcon_afcen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_AFCEN_MSK); +} + +/** + * @brief UARTx Auto flow control disable. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_disable_mcon_afcen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_AFCEN_MSK); +} + +/** + * @brief Check if Auto flow control is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_mcon_afcen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_AFCEN_MSK) == (UART_MCON_AFCEN_MSK)); +} + +/** + * @brief Set UARTx RTSn set control bit. + * @note If Auto flow control disable, user can control RTSn output level by this bit. + * MD_UART_MCON_RTSSET_LOW : RTSn level is 0 + * MD_UART_MCON_RTSSET_HIGH: RTSn level is 1 + * @param UARTx UART Instance. + * @param This parameter can be one of the following values: + * @arg @ref MD_UART_MCON_RTSSET_LOW + * @arg @ref MD_UART_MCON_RTSSET_HIGH + * @retval None + */ +__STATIC_INLINE void md_uart_set_mcon_rtsset(UART_TypeDef *UARTx, uint32_t level) +{ + MODIFY_REG(UARTx->MCON, UART_MCON_RTSSET_MSK, level<MCON, UART_MCON_RTSSET_MSK))>>UART_MCON_RTSSET_POS); +} + +/** + * @brief UARTx LoopBack enable. + * @note This is used to put the UART into a diagnostic mode for test purpose. + * If operating in UART mode, data on the TXD line is held high, + * while serial data output is looped back to the RXD line, internally. + * In this mode, all the interrupts are fully functional. + * If operating in infrared mode, data on the TXD with IrDA line is held low, + * while serial data output is inverted and looped back to the RXD line. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_mcon_lpbken(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->MCON, UART_MCON_LPBKEN_MSK); +} + +/** + * @brief UARTx LoopBack disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_mcon_lpbken(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->MCON, UART_MCON_LPBKEN_MSK); +} + +/** + * @brief Check if UARTx LoopBack is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lpbken(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->MCON, UART_MCON_LPBKEN_MSK) == (UART_MCON_LPBKEN_MSK)); +} + +/** + * @brief Set UARTx Delay value. + * @note Contains a direction control RTSn Delay value. This register + * works in conjunction with an 8-bit counter in terms of number of + * DIVISOR bit duration. + * @param UARTx UART Instance. + * @param UARTx Delay value. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_rs485_dly(UART_TypeDef *UARTx, uint32_t delay) +{ + MODIFY_REG(UARTx->RS485, UART_RS485_DLY_MSK, delay<RS485, UART_RS485_DLY_MSK))>>UART_RS485_DLY_POSS); +} + +/** + * @brief Set UARTx Address match value. + * @param UARTx UART Instance. + * @param UARTx Address match value. + * @retval None + */ +__STATIC_INLINE void md_uart_set_rs485_addr(UART_TypeDef *UARTx, uint32_t address) +{ + MODIFY_REG(UARTx->RS485, UART_RS485_ADDR_MSK, address<RS485, UART_RS485_ADDR_MSK))>>UART_RS485_ADDR_POSS); +} + +/** + * @brief Set UARTx Automatic address detection invert. + * @note This bit retains the DE(RTSn) polarity direction control signal on pin. + * @param UARTx UART Instance. + * @param aadinv can be one of the following value: + * @arg @ref MD_UART_RS485_AADINV_LOW (Low : Transfering data, High: Idle) + * @arg @ref MD_UART_RS485_AADINV_HIGH (High: Transfering data, Low : Idle) + * @retval None + */ +__STATIC_INLINE void md_uart_set_rs485_aadinv(UART_TypeDef *UARTx, uint32_t aadinv) +{ + MODIFY_REG(UARTx->RS485, UART_RS485_AADINV_MSK, aadinv<RS485, UART_RS485_AADINV_MSK))>>UART_RS485_AADINV_POS); +} + +/** + * @brief UARTx Automatic address detection auto-control enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_rs485_aadacen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->RS485, UART_RS485_AADACEN_MSK); +} + +/** + * @brief UARTx Automatic address detection auto-control disable + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_rs485_aadacen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->RS485, UART_RS485_AADACEN_MSK); +} + +/** + * @brief Check if UARTx Automatic address detection auto-control is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_rs485_aadacen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RS485, UART_RS485_AADACEN_MSK) == (UART_RS485_AADACEN_MSK)); +} + +/** + * @brief UARTx Automatic address detection normal mode enable. + * @note Note that it can be active with RS-485 AAD operation mode. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_rs485_aadnen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->RS485, UART_RS485_AADNEN_MSK); +} + +/** + * @brief UARTx Automatic address detection normal mode disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_rs485_aadnen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->RS485, UART_RS485_AADNEN_MSK); +} + +/** + * @brief Check if Automatic address detection normal mode is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_rs485_aadnen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RS485, UART_RS485_AADNEN_MSK) == (UART_RS485_AADNEN_MSK)); +} + +/** + * @brief UARTx Automatic address detection operation mode enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_rs485_aaden(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->RS485, UART_RS485_AADEN_MSK); +} + +/** + * @brief UARTx Automatic address detection operation mode disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_rs485_aaden(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->RS485, UART_RS485_AADEN_MSK); +} + +/** + * @brief Check if UARTx Automatic address detection operation mode is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_rs485_aaden(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RS485, UART_RS485_AADEN_MSK) == (UART_RS485_AADEN_MSK)); +} + +/** + * @brief Set UARTx Block Length (Only UART). + * @note This bit-field gives the Block length in Smartcard T=1 + * Reception. Its value equals the number of information + * characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. + * This bit-field can be used also in other modes. In this case, the + * Block length counter is reset when RXEN=0 (receiver disabled). + * @param UARTx UART Instance. + * @param Block Length. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_scard_blen(UART_TypeDef *UARTx, uint32_t blocklength) +{ + MODIFY_REG(UARTx->SCARD, UART_SCARD_BLEN_MSK, blocklength<SCARD, UART_SCARD_BLEN_MSK))>>UART_SCARD_BLEN_POSS); +} + +/** + * @brief Set UARTx Guard time value(Only UART). + * @param UARTx UART Instance. + * @param Guard time value. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_scard_gt(UART_TypeDef *UARTx, uint32_t guardtime) +{ + MODIFY_REG(UARTx->SCARD, UART_SCARD_GT_MSK, guardtime<SCARD, UART_SCARD_GT_MSK))>>UART_SCARD_GT_POSS); +} + +/** + * @brief Set UARTx Prescaler value (Only UART). + * @note In IrDA Low-power and normal IrDA mode: + * Used for programming the prescaler for dividing the UART + * source clock to achieve the low-power frequency. + * The source clock is divided by the value given in the register (8 + * significant bits) + * In Smartcard mode: + * Used for programming the prescaler for dividing the UART + * source clock to provide the Smartcard clock. + * The value given in the register (5 significant bits) is multiplied by + * 2 to give the division factor of the source clock frequency. + * @param UARTx UART Instance. + * @param Prescaler value. + * @retval None + */ +__STATIC_INLINE void md_uart_set_scard_psc(UART_TypeDef *UARTx, uint32_t prescaler) +{ + MODIFY_REG(UARTx->SCARD, UART_SCARD_PSC_MSK, prescaler<SCARD, UART_SCARD_PSC_MSK))>>UART_SCARD_PSC_POSS); +} + +/** + * @brief Set UARTx Smartcard auto-retry count (Only UART). + * @note This bit-field specifies the number of retries in transmit and + * receive, in Smartcard mode. + * In transmission mode, it specifies the number of automatic + * retransmission retries, before generating a transmission error + * (FE bit set). + * In reception mode, it specifies the number or erroneous + * reception trials, before generating a reception error (RXNE and + * PE bits set). + * @param UARTx UART Instance. + * @param smartcard auto-retry count Min_Value=0x00 Max_Value=0x07. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_scard_sccnt(UART_TypeDef *UARTx, uint32_t count) +{ + MODIFY_REG(UARTx->SCARD, UART_SCARD_SCCNT_MSK, count<SCARD, UART_SCARD_SCCNT_MSK))>>UART_SCARD_SCCNT_POSS); +} + +/** + * @brief Smartcard clock enable(Only UART). + * @note This bit allows the user to enable the SCK pin. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_scard_sclken(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->SCARD, UART_SCARD_SCLKEN_MSK); +} + +/** + * @brief Smartcard clock disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_scard_sclken(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->SCARD, UART_SCARD_SCLKEN_MSK); +} + +/** + * @brief Check if Smartcard clock is enable. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_scard_sclken(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->SCARD, UART_SCARD_SCLKEN_MSK) == (UART_SCARD_SCLKEN_MSK)); +} + +/** + * @brief Smartcard NACK enable(Only UART). + * @note This bit allows the user to enable nack detection. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_scard_scnack(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->SCARD, UART_SCARD_SCNACK_MSK); +} + +/** + * @brief Smartcard NACK disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_scard_scnack(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->SCARD, UART_SCARD_SCNACK_MSK); +} + +/** + * @brief Check if Smartcard NACK is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_scard_scnack(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->SCARD, UART_SCARD_SCNACK_MSK) == (UART_SCARD_SCNACK_MSK)); +} + +/** + * @brief Smartcard mode enable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_scard_scen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->SCARD, UART_SCARD_SCEN_MSK); +} + +/** + * @brief Smartcard mode disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_scard_scen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->SCARD, UART_SCARD_SCEN_MSK); +} + +/** + * @brief Check if Smartcard mode is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_scard_scen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->SCARD, UART_SCARD_SCEN_MSK) == (UART_SCARD_SCEN_MSK)); +} + +/** + * @brief Enable LIN mode break request. + * @note This bit is set by software and automatically cleared by + * hardware in the next clock cycle. + * Writing 1 to this bit sets request to send a BREAK on the line, as + * soon as the transmit machine is available. + * It generates 13 bits rate low pulse in Lin mode. + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_lin_linbkreq(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LIN, UART_LIN_LINBKREQ_MSK); +} + +/** + * @brief Disable LIN mode break request. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_linbkreq(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LIN, UART_LIN_LINBKREQ_MSK); +} + +/** + * @brief Check if LIN break is enabled + * @param None + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enable_linbkreq(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->LIN, UART_LIN_LINBKREQ_MSK) == (UART_LIN_LINBKREQ_MSK)); +} + +/** + * @brief UARTx LIN mode enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_lin_linen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->LIN, UART_LIN_LINEN_MSK); +} + +/** + * @brief UART LIN mode disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_lin_linen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->LIN, UART_LIN_LINEN_MSK); +} + +/** + * @brief Check if UARTx LIN mode is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_lin_linen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->LIN, UART_LIN_LINEN_MSK) == (UART_LIN_LINEN_MSK)); +} + +/** + * @brief UARTx receive timeout enable. + * @note When this feature is enabled, the RTOIF flag in the UART_RIF + * register is set if the RX line is idle (no reception) for the duration + * programmed in the RTOR (receiver timeout register). + * @param UARTx UART Instance + * @retval None + */ +__STATIC_INLINE void md_uart_enable_rtor_rtoen(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->RTOR, UART_RTOR_RTOEN_MSK); +} + +/** + * @brief UARTx receive timeout disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_rtor_rtoen(UART_TypeDef *UARTx) +{ + CLEAR_BIT(UARTx->RTOR, UART_RTOR_RTOEN_MSK); +} + +/** + * @brief Check if UARTx receive timeout is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_rtor_rtoen(UART_TypeDef *UARTx) +{ + return (uint32_t)(READ_BIT(UARTx->RTOR, UART_RTOR_RTOEN_MSK) == (UART_RTOR_RTOEN_MSK)); +} + +/** + * @brief Set UARTx receiver timeout value. + * @note This bit-field gives the Receiver timeout value in terms of number of bit duration. + * In standard mode: + * the RTOF flag is set if, after the last received character, + * no new start bit is detected for more than the RTO value. + * In Smartcard mode: + * this value is used to implement the CWT and BWT. See Smartcard section for more details. + * In this case, the timeout measurement is done starting from the Stop Bit of the last + * received character. + * @param UARTx UART Instance. + * @param timeout UART timeout value. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_rtor_rto(UART_TypeDef *UARTx, uint32_t timeout) +{ + MODIFY_REG(UARTx->RTOR, UART_RTOR_RTO_MSK, timeout<RTOR, UART_RTOR_RTO_MSK))>>UART_RTOR_RTO_POSS); +} + +/** + * @brief Set UARTx Transmit FIFO level. + * @note This is used to indicate the number of data entries in the Transmit FIFO. + * It's value from 0 to 16. + * @param UARTx UART Instance. + * @param Value between Min_Data=0x00 and Max_Data=0x010. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_fcon_txfl(UART_TypeDef *UARTx, uint32_t level) +{ + MODIFY_REG(UARTx->FCON, UART_FCON_TXFL_MSK, level<FCON, UART_FCON_TXFL_MSK))>>UART_FCON_TXFL_POSS); +} + +/** + * @brief Set UARTx Transmit FIFO trigger threshold. + * @note This is used to select the threshold level in the transmit FIFO at + * which the Transmit FIFO trigger threshold flag is generated. + * @param UARTx UART Instance + * @param level This parameter can be one of the following values: + * @arg @ref MD_UART_FCON_TXTH_0 + * @arg @ref MD_UART_FCON_TXTH_2 + * @arg @ref MD_UART_FCON_TXTH_4 + * @arg @ref MD_UART_FCON_TXTH_8 + * @retval None + */ +__STATIC_INLINE void md_uart_set_fcon_txth(UART_TypeDef *UARTx, uint32_t level) +{ + MODIFY_REG(UARTx->FCON, UART_FCON_TXTH_MSK, level<FCON, UART_FCON_TXTH_MSK))>>UART_FCON_TXTH_POSS); +} + +/** + * @brief Transmit FIFO reset. + * @note When FIFO is set, all the byte in the transmit FIFO are cleared + * and treats the FIFO as empty. Note that this bit will return to 0 in + * the next clock cycle. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_fcon_tfrst(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->FCON, UART_FCON_TFRST_MSK); +} + +/** + * @brief Set UARTx Receive FIFO level. + * @note This bit is set by hardware. This is used to indicate the number + * of data entries in the Receive FIFO. It's value from 0 to 16. + * @param UARTx UART Instance. + * @param Value between Min_Data=0x00 and Max_Data=0x010. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_fcon_rxfl(UART_TypeDef *UARTx, uint32_t level) +{ + MODIFY_REG(UARTx->FCON, UART_FCON_RXFL_MSK, level<FCON, UART_FCON_RXFL_MSK))>>UART_FCON_TXFL_POSS); +} + +/** + * @brief Set UARTx Receive FIFO trigger threshold. + * @note This is used to select the threshold level in the receiver FIFO at + * which the Receive FIFO trigger threshold flag is generated. + * @param UARTx UART Instance. + * @param level This parameter can be one of the following values: + * @arg @ref MD_UART_FCON_RXTH_1 + * @arg @ref MD_UART_FCON_RXTH_4 + * @arg @ref MD_UART_FCON_RXTH_8 + * @arg @ref MD_UART_FCON_RXTH_14 + * @retval None + */ +__STATIC_INLINE void md_uart_set_fcon_rxth(UART_TypeDef *UARTx, uint32_t level) +{ + MODIFY_REG(UARTx->FCON, UART_FCON_RXTH_MSK, level<FCON, UART_FCON_RXTH_MSK))>>UART_FCON_RXTH_POSS); +} + +/** + * @brief Receive FIFO reset + * @note When FIFO is set, all the byte in the receiver FIFO are cleared + * and treats the FIFO as empty. Note that this bit will return to 0 in + * the next clock cycle. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_set_fcon_rfrst(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->FCON, UART_FCON_RFRST_MSK); +} + +/** + * @brief Check if Transmit FIFO overrun error. + * @note This bit is set and cleared by hardware Tx line start transmit + * data. An overrun error occurs when the FIFO is full and a new + * character write at the Transmit. The data in the FIFO is retained + * and the data in the TXBR register is lost. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_tfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_TFOERR_MSK) == (UART_STAT_TFOERR_MSK)); +} + +/** + * @brief Check if Transmit FIFO full. + * @note This bit is set and cleared by hardware when the TX FIFO is no + * longer full. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_tffull(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_TFFULL_MSK) == (UART_STAT_TFFULL_MSK)); +} + +/** + * @brief Check if Transmit FIFO empty. + * @note This bit is set and cleared by hardware when the TX FIFO is no + * longer empty. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_tfempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_TFEMPTY_MSK) == (UART_STAT_TFEMPTY_MSK)); +} + +/** + * @brief Check if Transmit FIFO trigger threshold flag. + * @note This bit is set and cleared by hardware when transmit FIFO + * arrived threshold level in the FCR register. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_tfth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_TFTH_MSK) == (UART_STAT_TFTH_MSK)); +} + +/** + * @brief Check if Transmit shift register busy. + * @note This bit is cleared by hardware. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_tsbsy(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_TSBUSY_MSK) == (UART_STAT_TSBUSY_MSK)); +} + +/** + * @brief Check if Receive FIFO underrun error. + * @note This bit is set and cleared by hardware when receive a new + * data. An underrun error occurs when the FIFO is empty at the + * receive. The data in the FIFO is read 0 in the RXBR register. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rfuerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RFUERR_MSK) == (UART_STAT_RFUERR_MSK)); +} + +/** + * @brief Check if Receive FIFO overrun error. + * @note This bit is set and cleared by hardware when read data in the + * RXBR register. An overrun error occurs when the FIFO is full + * and a new character arrives at the receiver. The data in the + * FIFO is retained and the data in the RXBR register is lost. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RFOERR_MSK) == (UART_STAT_RFOERR_MSK)); +} + +/** + * @brief Check if Receive FIFO full. + * @note This bit is set and cleared by hardware when the RX FIFO is no + * longer full. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rffull(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RFFULL_MSK) == (UART_STAT_RFFULL_MSK)); +} + +/** + * @brief Check if Receive FIFO empty. + * @note This bit is cleared when the RX FIFO is no longer empty. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rfempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RFEMPTY_MSK) == (UART_STAT_RFEMPTY_MSK)); +} + +/** + * @brief Check if Receive FIFO trigger threshold flag. + * @note This bit is set and cleared by hardware when receive FIFO + * arrived threshold level in the FCR register. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rfth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RFTH_MSK) == (UART_STAT_RFTH_MSK)); +} + +/** + * @brief Check if Receive shiftregister busy. + * @note This bit is set and cleared by hardware. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_rsbsy(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_RSBUSY_MSK) == (UART_STAT_RSBUSY_MSK)); +} + +/** + * @brief Get UARTx Clear to send status. + * @note This bit is the complement of CTSn. When CTSn is asserted, it + * is an indication that the modem or data set is ready to exchange + * data with UART. + * @param ADCx ADC Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_get_stat_ctssta(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_CTSSTA_MSK)>>UART_STAT_CTSSTA_POS); +} + +/** + * @brief Check if Break error. + * @note This bit is used to indicate the detection of a break sequence on + * the serial input data. + * This error is associated with the character at the top of the FIFO. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_bkerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_BKERR_MSK) == (UART_STAT_BKERR_MSK)); +} + +/** + * @brief Check if Framing Error. + * @note When the received characters stop bit is a logic 0(i.e. the + * receiver did not have a valid stop bit), a framing error occurs. + * This error is associated with the character at the top of the FIFO. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_ferr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_FERR_MSK) == (UART_STAT_FERR_MSK)); +} + +/** + * @brief Check if Parity Error. + * @note When the receive character does not have correct parity + * information and is suspect, a parity error occurs. + * This error is associated with the character at the top of the FIFO. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_stat_perr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->STAT, UART_STAT_PERR_MSK) == (UART_STAT_PERR_MSK)); +} + +/** + * @brief Transmit FIFO overrun interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_tfover(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_TFOVER_MSK); +} + +/** + * @brief Transmit FIFO empty interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_tfempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_TFEMPTY_MSK); +} + +/** + * @brief Transmit FIFO trigger threshold interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_tfth(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_TFTH_MSK); +} + +/** + * @brief Transmission byte complete enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_tbc(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_TBC_MSK); +} + +/** + * @brief Receive FIFO underrun interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_rfuerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RFUERR_MSK); +} + +/** + * @brief Receive FIFO overrun interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_rfoerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RFOERR_MSK); +} + +/** + * @brief Receive FIFO full interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_rffull(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RFFULL_MSK); +} + +/** + * @brief Receive FIFO trigger threshold interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_rfth(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RFTH_MSK); +} + +/** + * @brief Bit Noise detection enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_noise(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_NOISE_MSK); +} + +/** + * @brief End of block interrupt enable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_eob(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_EOB_MSK); +} + +/** + * @brief LINBK: LIN break detection interrupt enable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_linbk(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_LINBK_MSK); +} + +/** + * @brief Address match interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_addrm(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_ADDRM_MSK); +} + +/** + * @brief Receiver Timeout interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_rxto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RXTO_MSK); +} + +/** + * @brief Delta CTS status interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_dcts(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_DCTS_MSK); +} + +/** + * @brief Auto-Baud rate detection Timeout interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_abto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_ABTO_MSK); +} + +/** + * @brief Auto-Baud rate detection End interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_abend(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_ABEND_MSK); +} + +/** + * @brief Receiver byte error interrupt enable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_enable_ier_rxberr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IER, UART_IER_RXBERR_MSK); +} + +/** + * @brief Transmit FIFO overrun interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_tfover(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_TFOVER_MSK); +} + +/** + * @brief Transmit FIFO empty interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_tfempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_TFEMPTY_MSK); +} + +/** + * @brief Transmit FIFO trigger threshold interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_tfth(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_TFTH_MSK); +} + +/** + * @brief Transmission byte complete interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_tbc(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_TBC_MSK); +} + +/** + * @brief Receive FIFO underrun interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_rfuerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RFUERR_MSK); +} + +/** + * @brief Receive FIFO overrun interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_rfoerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RFOERR_MSK); +} + +/** + * @brief Receive FIFO full interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_rffull(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RFFULL_MSK); +} + +/** + * @brief Receive FIFO trigger threshold interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_rfth(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RFTH_MSK); +} + +/** + * @brief Bit Noise detection disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_noise(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_NOISE_MSK); +} + +/** + * @brief End of block interrupt disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_eob(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_EOB_MSK); +} + +/** + * @brief LIN break detection interrupt disable(Only UART). + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_linbk(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_LINBK_MSK); +} + +/** + * @brief Address match interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_addrm(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_ADDRM_MSK); +} + +/** + * @brief Receiver Timeout interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_rxto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RXTO_MSK); +} + +/** + * @brief Delta CTS status interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_dcts(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_DCTS_MSK); +} + +/** + * @brief Auto-Baud rate detection Timeout interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_abto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_ABTO_MSK); +} + +/** + * @brief Auto-Baud rate detection End interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_abend(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_ABEND_MSK); +} + +/** + * @brief Receiver byte error interrupt disable. + * @param UARTx UART Instance. + * @retval None. + */ +__STATIC_INLINE void md_uart_disable_idr_rxberr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->IDR, UART_IDR_RXBERR_MSK); +} + +/** + * @brief Check if Tx FIFO overrun interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_tfover(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_TFOVER_MSK) == (UART_IVS_TFOVER_MSK)); +} + +/** + * @brief Check if Tx FIFO empty interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_tfempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_TFEMPTY_MSK) == (UART_IVS_TFEMPTY_MSK)); +} + +/** + * @brief Check if Tx FIFO trigger threshold interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_tfth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_TFTH_MSK) == (UART_IVS_TFTH_MSK)); +} + +/** + * @brief Check if Tx complete interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_tbc(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_TBC_MSK) == (UART_IVS_TBC_MSK)); +} + +/** + * @brief Check if Rx FIFO underrun interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rfuerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RFUERR_MSK) == (UART_IVS_RFUERR_MSK)); +} + +/** + * @brief Check if Rx FIFO overrun interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RFOERR_MSK) == (UART_IVS_RFOERR_MSK)); +} + +/** + * @brief Check if Rx FIFO full interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rffull(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RFFULL_MSK) == (UART_IVS_RFFULL_MSK)); +} + +/** + * @brief Check if Rx FIFO trigger threshold interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rfth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RFTH_MSK) == (UART_IVS_RFTH_MSK)); +} + +/** + * @brief Check if noise detection interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_noise(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_NOISE_MSK) == (UART_IVS_NOISE_MSK)); +} + +/** + * @brief Check if end of block detection interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_eob(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_EOB_MSK) == (UART_IVS_EOB_MSK)); +} + +/** + * @brief Check if LIN break detection interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_linbk(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_LINBK_MSK) == (UART_IVS_LINBK_MSK)); +} + +/** + * @brief Check if address match interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_addrm(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_ADDRM_MSK) == (UART_IVS_ADDRM_MSK)); +} + +/** + * @brief Check if RX timeout interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rxto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RXTO_MSK) == (UART_IVS_RXTO_MSK)); +} + +/** + * @brief Check if delta CTS status interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_dcts(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_DCTS_MSK) == (UART_IVS_DCTS_MSK)); +} + +/** + * @brief Check if auto-baud rate detection interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_abto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_ABTO_MSK) == (UART_IVS_ABTO_MSK)); +} + +/** + * @brief Check if auto-baud rate detection end interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_abend(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_ABEND_MSK) == (UART_IVS_ABEND_MSK)); +} + +/** + * @brief Check if RX byte error interrupt is enabled. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_enabled_ivs_rxberr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IVS, UART_IVS_RXBERR_MSK) == (UART_IVS_RXBERR_MSK)); +} + +/** + * @brief Get Transmit FIFO overrun interrupt flag. + * @note This bit is set by hardware when an overrun error occurs that + * the FIFO is full and a new character write at the Transmit. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_tfover(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_TFOVER_MSK) == (UART_RIF_TFOVER_MSK)); +} + +/** + * @brief Get Transmit FIFO empty interrupt flag. + * @note This bit is set by hardware when transmit FIFO is empty from + * have data to empty. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_txempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_TFEMPTY_MSK) == (UART_RIF_TFEMPTY_MSK)); +} + +/** + * @brief Get Transmit FIFO trigger threshold interrupt flag + * @note This bit is set by hardware when transmit FIFO arrived + * threshold level in the FCR register. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_tfth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_TFTH_MSK) == (UART_RIF_TFTH_MSK)); +} + +/** + * @brief Get Transmission byte complete interrupt flag. + * @note This bit is set by hardware when transmission byte complete. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_tbc(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_TBC_MSK) == (UART_RIF_TBC_MSK)); +} + +/** + * @brief Get Receive FIFO underrun interrupt flag + * @note This bit is set by hardware when an underrun error occurs that + * the FIFO is empty and a new character read at the Receive. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rfuerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RFUERR_MSK) == (UART_RIF_RFUERR_MSK)); +} + +/** + * @brief Get Receive FIFO overrun interrupt flag. + * @note This bit is set by hardware when an overrun error occurs that + * the FIFO is full and a new character arrive at the Receive. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RFOERR_MSK) == (UART_RIF_RFOERR_MSK)); +} + +/** + * @brief Get Receive FIFO full interrupt flag. + * @note This bit is set by hardware when receive FIFO is full. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rffull(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RFFULL_MSK) == (UART_RIF_RFFULL_MSK)); +} + +/** + * @brief Get Receive FIFO trigger threshold interrupt flag. + * @note This bit is set by hardware when receive FIFO arrived threshold + * level in the FCR register. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rfth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RFTH_MSK) == (UART_RIF_RFTH_MSK)); +} + +/** + * @brief Get Bit Noise detection interrupt flag. + * @note This bit is set by hardware when START bit Noise is detected. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_noise(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_NOISE_MSK) == (UART_RIF_NOISE_MSK)); +} + +/** + * @brief Get End of block interrupt flag(Only UART). + * @note This bit is set by hardware when blcok length value equals the + * number of data byte. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_eob(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_EOB_MSK) == (UART_RIF_EOB_MSK)); +} + +/** + * @brief Get LIN break detection interrupt flag(Only UART). + * @note This bit is set by hardware when lin break is detected. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_linbk(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_LINBK_MSK) == (UART_RIF_LINBK_MSK)); +} + +/** + * @brief Get Address match interrupt flag. + * @note This bit is set by hardware when the data in the RXBR register + * defined by ADD[7:0] in the RS485 register is received. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_addrm(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_ADDRM_MSK) == (UART_RIF_ADDRM_MSK)); +} + +/** + * @brief Get Receiver Timeout interrupt flag. + * @note This bit is set by hardware when the timeout value, + * programmed in the RTOR register has lapsed, without any + * communication. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rxto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RXTO_MSK) == (UART_RIF_RXTO_MSK)); +} + +/** + * @brief Get Delta CTS status interrupt flag. + * @note This bit is set by hardware when the CTS input toggles. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_dcts(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_DCTS_MSK) == (UART_RIF_DCTS_MSK)); +} + +/** + * @brief Get Auto-Baud rate detection timeout interrupt flag. + * @note This bit is set by hardware when the baud rate detection timeout. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_abto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_ABTO_MSK) == (UART_RIF_ABTO_MSK)); +} + +/** + * @brief Get Auto-Baud rate detection end interrupt flag. + * @note This bit is set by hardware when the baud rate detection end. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_abend(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_ABEND_MSK) == (UART_RIF_ABEND_MSK)); +} + +/** + * @brief Get Receiver byte error flag. + * @note This bit is set by hardware when a parity error or frame error + * occurs in receiver. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_rif_rxberr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_RIF_RXBERR_MSK) == (UART_RIF_RXBERR_MSK)); +} + +/** + * @brief Get Transmit FIFO overrun interrupt flag masked. + * @note This bit is set by hardware when an overrun error occurs that + * the FIFO is full and a new character write at the Transmit. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_tfover(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_TFOVER_MSK) == (UART_IFM_TFOVER_MSK)); +} + +/** + * @brief Get Transmit FIFO empty interrupt flag masked. + * @note This bit is set by hardware when transmit FIFO is empty from + * have data to empty. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_txempty(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_TFEMPTY_MSK) == (UART_IFM_TFEMPTY_MSK)); +} + +/** + * @brief Get Transmit FIFO trigger threshold interrupt flag masked. + * @note This bit is set by hardware when transmit FIFO arrived + * threshold level in the FCR register. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_tfth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_TFTH_MSK) == (UART_IFM_TFTH_MSK)); +} + +/** + * @brief Get Transmission byte complete interrupt flag masked. + * @note This bit is set by hardware when transmission byte complete. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_tbc(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_TBC_MSK) == (UART_IFM_TBC_MSK)); +} + +/** + * @brief Get Receive FIFO underrun interrupt flag masked. + * @note This bit is set by hardware when an underrun error occurs that + * the FIFO is empty and a new character read at the Receive. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rfuerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_RFUERR_MSK) == (UART_IFM_RFUERR_MSK)); +} + +/** + * @brief Get Receive FIFO overrun interrupt flag masked. + * @note This bit is set by hardware when an overrun error occurs that + * the FIFO is full and a new character arrive at the Receive. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rfoerr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_RFOERR_MSK) == (UART_IFM_RFOERR_MSK)); +} + +/** + * @brief Get Receive FIFO full interrupt flag masked. + * @note This bit is set by hardware when receive FIFO is full. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rffull(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_RFFULL_MSK) == (UART_IFM_RFFULL_MSK)); +} + +/** + * @brief Get Receive FIFO trigger threshold interrupt flag masked. + * @note This bit is set by hardware when receive FIFO arrived threshold + * level in the FCR register. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rfth(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_RFTH_MSK) == (UART_IFM_RFTH_MSK)); +} + +/** + * @brief Get Bit Noise detection interrupt flag masked. + * @note This bit is set by hardware when START bit Noise is detected. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_noise(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_NOISE_MSK) == (UART_IFM_NOISE_MSK)); +} + +/** + * @brief Get End of block interrupt flag masked(Only UART). + * @note This bit is set by hardware when block length value equals the + * number of data byte. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_eob(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_EOB_MSK) == (UART_IFM_EOB_MSK)); +} + +/** + * @brief Get LIN break detection interrupt flag masked(Only UART). + * @note This bit is set by hardware when lin break is detected. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_linbk(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_LINBK_MSK) == (UART_IFM_LINBK_MSK)); +} + +/** + * @brief Get Address match interrupt flag masked. + * @note This bit is set by hardware when the data in the RXBR register + * defined by ADD[7:0] in the RS485 register is received. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_addrm(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_ADDRM_MSK) == (UART_IFM_ADDRM_MSK)); +} + +/** + * @brief Get Receiver Timeout interrupt flag masked. + * @note This bit is set by hardware when the timeout value, + * programmed in the RTOR register has lapsed, without any + * communication. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rxto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_RXTO_MSK) == (UART_IFM_RXTO_MSK)); +} + +/** + * @brief Get Delta CTS status interrupt flag masked. + * @note This bit is set by hardware when the CTS input toggles. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_dcts(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->IFM, UART_RIF_DCTS_MSK) == (UART_IFM_DCTS_MSK)); +} + +/** + * @brief Get Auto-Baud rate detection timeout interrupt flag masked. + * @note This bit is set by hardware when the baud rate detection timeout. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_abto(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_ABTO_MSK) == (UART_IFM_ABTO_MSK)); +} + +/** + * @brief Get Auto-Baud rate detection end interrupt flag masked. + * @note This bit is set by hardware when the baud rate detection end. + * @param UARTx UART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_abend(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_ABEND_MSK) == (UART_IFM_ABEND_MSK)); +} + +/** + * @brief Get Receiver byte error interrupt flag masked. + * @note This bit is set by hardware when a parity error, frame error or + * break error occurs in receiver. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_uart_is_active_flag_ifm_rxberr(UART_TypeDef *UARTx) +{ + return (READ_BIT(UARTx->RIF, UART_IFM_RXBERR_MSK) == (UART_IFM_RXBERR_MSK)); +} + +/** + * @brief Transmit FIFO overrun interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_txover(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_TFOVER_MSK); +} + +/** + * @brief Transmit FIFO empty interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_txempty(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_TFEMPTY_MSK); +} + +/** + * @brief Transmit FIFO trigger threshold interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_tfth(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_TFTH_MSK); +} + +/** + * @brief Transmission byte complete interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_tbc(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_TBC_MSK); +} + +/** + * @brief Receive FIFO underrun interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_rfuerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RFUERR_MSK); +} + +/** + * @brief Receive FIFO overrun interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_rfoerr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RFOERR_MSK); +} + +/** + * @brief Receive FIFO full interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_rffull(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RFFULL_MSK); +} + +/** + * @brief Receive FIFO trigger threshold interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_rfth(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RFTH_MSK); +} + +/** + * @brief Bit Noise detection interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_noise(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_NOISE_MSK); +} + +/** + * @brief End of block interrupt flag clear(Only UART). + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_eob(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_EOB_MSK); +} + +/** + * @brief LIN break detection interrupt flag clear(Only UART). + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_linbk(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_LINBK_MSK); +} + +/** + * @brief Address match interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_addrm(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_ADDRM_MSK); +} + +/** + * @brief Receiver Timeout interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_rxto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RXTO_MSK); +} + +/** + * @brief Delta CTS status interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_dcts(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_DCTS_MSK); +} + +/** + * @brief Auto-Baud rate detection timeout interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_abto(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_ABTO_MSK); +} + +/** + * @brief Auto-Baud rate detection end interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_abend(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_ABEND_MSK); +} + +/** + * @brief Receiver byte error interrupt flag clear. + * @param UARTx UART Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void md_uart_clear_flag_rxberr(UART_TypeDef *UARTx) +{ + SET_BIT(UARTx->ICR, UART_ICR_RXBERR_MSK); +} + +/** + * @} MD_UART_Public_Macros UART Public Macros + */ + +/* Public functions -----------------------------------------------------------*/ +void md_uart_set_baudrate (UART_TypeDef *UARTx, uint32_t baudrate); +void md_uart_init(UART_TypeDef *UARTx, md_uart_init_typedef *UART_InitStruct); +void md_uart_send (UART_TypeDef *UARTx, uint8_t ch); +uint8_t md_uart_recv (UART_TypeDef *UARTx); +uint32_t md_uart_get_baudrate (UART_TypeDef *UARTx); + +/** + * @} UART + */ + +#endif + +/** + * @} Micro_Driver + */ + + +#ifdef __cplusplus +} + +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_wwdt.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_wwdt.h new file mode 100644 index 0000000000000000000000000000000000000000..f2f1a86a2980284e9bd70cea93ee5e0dccbd6965 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/md_wwdt.h @@ -0,0 +1,382 @@ +/** + ****************************************************************************** + * @file md_wwdt.h + * @brief ES32F0271 WWDT HEAD File. + * + * @version V0.01 + * @date 4/12/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MD_WWDT_H__ +#define __MD_WWDT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "reg_wwdt.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (WWDT) +/** @defgroup WWDT WWDT + * @brief WWDT micro driver + * @{ + */ + +/* Public Init Structure ------------------------------------------------------*/ +/** @defgroup MD_WWDT_PT_INIT WWDT Public Init Structure + * @brief WWDT Init Structure. + * @{ + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDT. + This parameter can be a value of @ref WWDT_Prescaler */ + + uint32_t Window; /*!< Specifies the WWDT window value to be compared to the downcounter. + This parameter must be a number a minimum, 0x40 and a maximum, 0x7F */ + + uint32_t Counter; /*!< Specifies the WWDT free-running downcounter value. + This parameter must be a number between a minimum, 0x40 and a maximum, 0x7F */ + + uint32_t EWIMode ; /*!< Specifies if WWDT Early Wakeup Interupt is enable or not. + This parameter can be a value of @ref WWDT_EWI_Mode */ + +} md_wwdt_inittypedef; +/** + * @} MD_WWDT_PT_INIT + */ + +/* Public constants -----------------------------------------------------------*/ +/** @defgroup MD_WWDT_PUBLIC_CONSTANTS WWDT Public Constants + * @{ + */ + +/** @defgroup MD_WWDT_Prescaler WWDT Prescaler + * @{ + */ +#define WWDT_PRESCALER_1 0x00000000U /*!< WWDT counter clock = (PCLK1/4096)/1 */ +#define WWDT_PRESCALER_2 1U<CON, Reg_Value); +} + +/** + * @brief Get the WWDT_CON value + * @note None. + * @param WWD WWDT Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_wwdt_get_con(WWDT_TypeDef *WWD) +{ + return (uint32_t) (READ_REG(WWD->CON)); +} + +/** + * @brief WWDT WDG Enable + * @note This bit is set by software and only cleared by hardware after a reset. + * A write of 0 has no effect. When WDGA=1, the watchdog can generate a reset. + * @param WWD WWDT Instance + * @retval None + */ +__STATIC_INLINE void md_wwdt_enable_con_wdga(WWDT_TypeDef *WWD) +{ + SET_BIT(WWD->CON, WWDT_CON_WDGA_MSK); +} + +/** + * @brief Indicate if WWDT WDG is enabled + * @note This bit is set by software and only cleared by hardware after a reset. + * A write of 0 has no effect. When WDGA=1, the watchdog can generate a reset. + * @param WWD WWDT Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_wwdt_is_enabled_wdga(WWDT_TypeDef *WWD) +{ + return (uint32_t)(READ_BIT(WWD->CON, WWDT_CON_WDGA_MSK) == (WWDT_CON_WDGA_MSK)); +} + +/** + * @brief Set WWDT T 7-bit counter + * @note These bits contain the value of the watchdog counter. + * It is decremented every (4096 x 2^WDGTB[1:0]) PCLK cycles. + * A reset is produced when it is decremented from 0x40 to 0x3F(T6 becomes cleared), + * and when it is renewed on the condition the value is more than the window value and the WDGA bit is enabled. + * @param WWD WWDT Instance + * @param counter is a 7-bit number + * @arg Max Value 0x7F + * @arg Min Value 0x40 + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_con_t(WWDT_TypeDef *WWD, uint32_t counter) +{ + MODIFY_REG(WWD->CON, WWDT_CON_T_MSK, counter); +} + +/** + * @brief Get WWDT T 7-bit counter + * @note These bits contain the value of the watchdog counter. + * It is decremented every (4096 x 2^WDGTB[1:0]) PCLK cycles. + * A reset is produced when it is decremented from 0x40 to 0x3F(T6 becomes cleared), + * and when it is renewed on the condition the value is more than the window value and the WDGA bit is enabled. + * @param WWD WWDT Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0x7F + * @arg Min Value 0x40 + */ +__STATIC_INLINE uint32_t md_wwdt_get_con_t(WWDT_TypeDef *WWD) +{ + return (READ_BIT(WWD->CON, WWDT_CON_T_MSK)>>WWDT_CON_T_POSS); +} + +/** + * @brief Set the WWDT_CFG value + * @note None. + * @param WWD WWDT Instance + * @param Reg_Value is a 32-bit value + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_cfg(WWDT_TypeDef *WWD, uint32_t Reg_Value) +{ + WRITE_REG(WWD->CFG, Reg_Value); +} + +/** + * @brief Get the WWDT_CFG value + * @note None. + * @param WWD WWDT Instance + * @retval a 32-bit value + */ +__STATIC_INLINE uint32_t md_wwdt_get_cfg(WWDT_TypeDef *WWD) +{ + return (uint32_t) (READ_REG(WWD->CFG)); +} + +/** + * @brief Set WWDT WDGTB 2-bit prescaler value + * @note The time base of the prescaler can be modified as follows: + * 00: CK Counter Clock (PCLK div 4096) div 1 + * 01: CK Counter Clock (PCLK div 4096) div 2 + * 10: CK Counter Clock (PCLK div 4096) div 4 + * 11: CK Counter Clock (PCLK div 4096) div 8 + * @param WWD WWDT Instance + * @param prescaler is a 2-bit number + * @arg @ref WWDT_PRESCALER_1 + * @arg @ref WWDT_PRESCALER_2 + * @arg @ref WWDT_PRESCALER_4 + * @arg @ref WWDT_PRESCALER_8 + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_cfg_wdgtb(WWDT_TypeDef *WWD, uint32_t prescaler) +{ + MODIFY_REG(WWD->CFG, WWDT_CFG_WDGTB_MSK, prescaler); +} + +/** + * @brief Get WWDT WDGTB 2-bit prescaler value + * @note The time base of the prescaler can be modified as follows: + 00: CK Counter Clock (PCLK div 4096) div 1 + 01: CK Counter Clock (PCLK div 4096) div 2 + 10: CK Counter Clock (PCLK div 4096) div 4 + 11: CK Counter Clock (PCLK div 4096) div 8 + * @param WWD WWDT Instance + * @retval The retval can be one of the following values: + * @arg @ref WWDT_PRESCALER_1 + * @arg @ref WWDT_PRESCALER_2 + * @arg @ref WWDT_PRESCALER_4 + * @arg @ref WWDT_PRESCALER_8 + */ +__STATIC_INLINE uint32_t md_wwdt_get_cfg_wdgtb(WWDT_TypeDef *WWD) +{ + return (READ_BIT(WWD->CFG, WWDT_CFG_WDGTB_MSK)>>WWDT_CFG_WDGTB_POSS); +} + +/** + * @brief Set WWDT W 7-bit window + * @note These bits contain the window value to be compared to the downcounter. + * @param WWD WWDT Instance + * @param window is a 7-bit number + * @arg Max Value 0x7F + * @arg Min Value 0x40 + * @retval None + */ +__STATIC_INLINE void md_wwdt_set_cfg_w(WWDT_TypeDef *WWD, uint32_t window) +{ + MODIFY_REG(WWD->CFG, WWDT_CFG_W_MSK, window); +} + +/** + * @brief Get WWDT W 7-bit window + * @note These bits contain the window value to be compared to the downcounter. + * @param WWD WWDT Instance + * @retval The retval can be a value of the area: + * @arg Max Value 0x7F + * @arg Min Value 0x40 + */ +__STATIC_INLINE uint32_t md_wwdt_get_cfg_w(WWDT_TypeDef *WWD) +{ + return (READ_BIT(WWD->CFG, WWDT_CFG_W_MSK)>>WWDT_CFG_W_POSS); +} + +/** + * @brief WWDT Early wakeup interrupt Enable + * @note A write of 1 in IER to enable this interrupt. + * @param WWD WWDT Instance + * @retval None + */ +__STATIC_INLINE void md_wwdt_enable_ier_ewis(WWDT_TypeDef *WWD) +{ + SET_BIT(WWD->IER, WWDT_IER_EWIS_MSK); +} + +/** + * @brief WWDT Early wakeup interrupt Disable + * @note A write of 1 in IDR to disable this interrupt. + * @param WWD WWDT Instance + * @retval None + */ +__STATIC_INLINE void md_wwdt_disable_idr_ewis(WWDT_TypeDef *WWD) +{ + SET_BIT(WWD->IDR, WWDT_IDR_EWIS_MSK); +} + +/** + * @brief Indicate if WWDT EWI is enabled + * @note To check EWI enable or not. + * @param WWD WWDT Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_wwdt_is_enabled_ivs_ewis(WWDT_TypeDef *WWD) +{ + return (uint32_t) (READ_BIT(WWD->IVS, WWDT_IVS_EWIS_MSK) == (WWDT_IVS_EWIS_MSK)); +} + +/** + * @brief Get the early wakeup interrupt flag status + * @note This bit is set by hardware when the counter has reached the value 0x40. + It can be cleared by software by writing 1 in WWDT_ICR. This bit is + also set if the interrupt is not enabled. + * @param WWD WWDT Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_wwdt_is_active_rif_ewif(WWDT_TypeDef *WWD) +{ + return (uint32_t) (READ_BIT(WWD->RIF, WWDT_RIF_EWIF_MSK) == (WWDT_RIF_EWIF_MSK)); +} + +/** + * @brief Get the early wakeup interrupt flag masked status + * @note This bit is set by hardware when the counter has reached the value 0x40 + and the interrupt is enabled. + * @param WWD WWDT Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t md_wwdt_is_active_ifm_ewim(WWDT_TypeDef *WWD) +{ + return (uint32_t) (READ_BIT(WWD->IFM, WWDT_IFM_EWIM_MSK) == (WWDT_IFM_EWIM_MSK)); +} + +/** + * @brief Clear the early wakeup interrupt flag + * @param WWD WWDT Instance + * @retval None + */ +__STATIC_INLINE void md_wwdt_clear_icr_ewic(WWDT_TypeDef *WWD) +{ + SET_BIT(WWD->ICR, WWDT_ICR_EWIC_MSK); +} + +/** + * @} MD_WWDT_Public_Macros + */ + +/** @defgroup MD_WWDT_PF_Init WWDT Init Function + * @{ + */ +void md_wwdt_init(WWDT_TypeDef *WWD, md_wwdt_inittypedef *WWDT_InitStruct); +/** + * @} MD_WWDT_PF_Init + */ + +#endif + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup MD_WWDT_Private_Macros WWDG Private Macros + * @{ + */ +#define IS_MD_WWDT_ALL_INSTANCE(__INSTANCE__) (__INSTANCE__ == WWDT) + +#define IS_MD_WWDT_PRESCALER(__VALUE__) (((__VALUE__) == WWDT_PRESCALER_1) \ + || ((__VALUE__) == WWDT_PRESCALER_2) \ + || ((__VALUE__) == WWDT_PRESCALER_4) \ + || ((__VALUE__) == WWDT_PRESCALER_8)) + +#define IS_MD_WWDT_WINDOW(__VALUE__) (((__VALUE__) >= 0x40) && ((__VALUE__) <= 0x7F)) + +#define IS_MD_WWDT_COUNTER(__VALUE__) (((__VALUE__) >= 0x40) && ((__VALUE__) <= 0x7F)) + +#define IS_MD_WWDT_EWI_MODE(__VALUE__) (((__VALUE__) == WWDT_EWI_ENABLE) \ + || ((__VALUE__) == WWDT_EWI_DISABLE)) +/** + * @} MD_WWDT_Private_Macros + */ + +/** + * @} WWDT + */ +/** + * @} Micro_Driver + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/usb_lowlayer_api.h b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/usb_lowlayer_api.h new file mode 100644 index 0000000000000000000000000000000000000000..5fee2e973e81058f50820544c7793ccc47fa15e8 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Include/usb_lowlayer_api.h @@ -0,0 +1,728 @@ +/** + ************************************************************************************** + * @file usb_lowlayer_api.h + * @brief USB library lower layer api + * @data 11/9/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +/* Includes-------------------------------------------------------------------*/ +#include "stdint.h" +#include + +#ifndef __USB_LOWLAYER_API_H__ +#define __USB_LOWLAYER_API_H__ + + +/** + * If building with a C++ compiler, make all of the definitions in this header + * have a C binding. + */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Public constants -----------------------------------------------------------*/ + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hosdev_int_enable() and +// md_usb_hosdev_int_disable() as the ui32Flags parameter, and are returned from +// md_usb_hosdev_int_status(). +// +//***************************************************************************** +#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources +#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts +#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error +#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected +#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected +#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected +#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected +#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected +#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled +#define USB_INTCTRL_RESET 0x00000004 // Reset signaled +#define USB_INTCTRL_RESUME 0x00000002 // Resume detected +#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected +#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid +#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hosdev_endpoint_int_enable() +// and md_usb_hosdev_endpoint_int_disable() as the ui32Flags parameter, and +// are returned from md_usb_hosdev_endpoint_int_status(). +// +//***************************************************************************** +#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts +#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts +#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt +#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt +#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt +#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt +#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt +#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt +#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt +#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt +#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt +#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt +#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt +#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt +#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt +#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt +#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt + +#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts +#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt + +#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts +#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt + +#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts +#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt +#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt +#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt +#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt +#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt +#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt +#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt +#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt +#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt +#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt +#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt +#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt +#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt +#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt +#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt + +#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are values that are returned from md_usb_hos_speed_get() 0r +// md_usb_dev_speed_get(). +// +//***************************************************************************** +#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined +#define USB_HIGH_SPEED 0x00000002 // Current speed is High Speed +#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed +#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed + +//***************************************************************************** +// +// The following are values that are returned from md_usb_hosdev_endpoint_status(). The +// USB_HOST_* values are used when the USB controller is in host mode and the +// USB_DEV_* values are used when the USB controller is in device mode. +// +//***************************************************************************** +#define USB_HOST_IN_STATUS 0x114F0000 // Mask of all host IN interrupts +#define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received +#define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond +#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received +#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error +// (ISOC Mode) +#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the +// specified timeout period +#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a +// device +#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready +#define USB_HOST_OUT_STATUS 0x000000A7 // Mask of all host OUT interrupts +#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the +// specified timeout period +#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device +// (ISOC mode) +#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received +#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a +// device +#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty +#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted +#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the +// specified timeout period +#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet +#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a +// device +#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received +#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready +#define USB_DEV_RX_PID_ERROR 0x01000000 // PID error in isochronous +// transfer +#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint +#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data +#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to +// a full FIFO +#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready +#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data +// to come +#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint +#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready +#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty +#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted +#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before +// Data End seen +#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint +#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hos_endpoint_config_set() and +// md_usb_dev_endpoint_config_set() as the ui32Flags parameter. +// +//***************************************************************************** +#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled +#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled +#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled +#define USB_EP_DUAL_BUFFERING 0x00000008 // Dual buffering enabled +#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0 +#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1 +#define USB_EP_DIS_NYET 0x00000020 // Disable NYET response for +// high-speed Bulk and Interrupt +// endpoints in device mode. +#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint +#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint +#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint +#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint +#define USB_EP_MODE_MASK 0x00000300 // Mode Mask +#define USB_EP_SPEED_LOW 0x00000000 // Low Speed +#define USB_EP_SPEED_FULL 0x00001000 // Full Speed +#define USB_EP_SPEED_HIGH 0x00004000 // High Speed +#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint +#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint +#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint +#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hos_pwr_config() as the +// ui32Flags parameter. +// +//***************************************************************************** +#define USB_HOST_PWRFLT_LOW 0x00000010 +#define USB_HOST_PWRFLT_HIGH 0x00000030 +#define USB_HOST_PWRFLT_EP_NONE 0x00000000 +#define USB_HOST_PWRFLT_EP_TRI 0x00000140 +#define USB_HOST_PWRFLT_EP_LOW 0x00000240 +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 +#define USB_HOST_PWREN_MAN_LOW 0x00000000 +#define USB_HOST_PWREN_MAN_HIGH 0x00000001 +#define USB_HOST_PWREN_AUTOLOW 0x00000002 +#define USB_HOST_PWREN_AUTOHIGH 0x00000003 +#define USB_HOST_PWREN_FILTER 0x00010000 + +//***************************************************************************** +// +// The following are the valid values that can be passed to the +// md_usb_hos_lpm_config() function in the ui32Config parameter. +// +//***************************************************************************** +#define USB_HOST_LPM_RMTWAKE 0x00000100 +#define USB_HOST_LPM_L1 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that can be passed to the +// md_usb_dev_lpm_config() function in the ui32Config parameter. +// +//***************************************************************************** +#define USB_DEV_LPM_NAK 0x00000010 +#define USB_DEV_LPM_NONE 0x00000000 +#define USB_DEV_LPM_EN 0x0000000c +#define USB_DEV_LPM_EXTONLY 0x00000004 + +//***************************************************************************** +// +// The following are the valid values that are returned from the +// md_usb_lpm_link_state_get() function. +// +//***************************************************************************** +#define USB_DEV_LPM_LS_RMTWAKE 0x00000100 +#define USB_DEV_LPM_LS_L1 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that are passed to the md_usb_lpm_int_enable() +// or md_usb_lpm_int_disable() functions or are returned from the md_usb_lpm_status() +// function. +// +//***************************************************************************** +#define USB_INTLPM_ERROR 0x00000020 +#define USB_INTLPM_RESUME 0x00000010 +#define USB_INTLPM_INCOMPLETE 0x00000008 +#define USB_INTLPM_ACK 0x00000004 +#define USB_INTLPM_NYET 0x00000002 +#define USB_INTLPM_STALL 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that are passed to the md_usb_clock_enable() +// functions. +// +//***************************************************************************** +#define USB_CLOCK_INTERNAL 0x00000200 +#define USB_CLOCK_EXTERNAL 0x00000300 + +//***************************************************************************** +// +// The configuration options used with the md_usb_ulpi_config() API. +// +//***************************************************************************** +#define USB_ULPI_EXTVBUS 0x00000001 +#define USB_ULPI_EXTVBUS_IND 0x00000002 + +//***************************************************************************** +// +// The following are special values that can be passed to +// md_usb_hos_endpoint_config_set() as the ui32NAKPollInterval parameter. +// +//***************************************************************************** +#define MAX_NAK_LIMIT 31 // Maximum NAK interval +#define DISABLE_NAK_LIMIT 0 // No NAK timeouts + +//***************************************************************************** +// +// This value specifies the maximum size of transfers on endpoint 0 as 64 +// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. +// +//***************************************************************************** +#define MAX_PACKET_SIZE_EP0 64 + +//***************************************************************************** +// +// These values are used to indicate which endpoint to access. +// +//***************************************************************************** +#define USB_EP_0 0x00000000 // Endpoint 0 +#define USB_EP_1 0x00000010 // Endpoint 1 +#define USB_EP_2 0x00000020 // Endpoint 2 +#define USB_EP_3 0x00000030 // Endpoint 3 +#define USB_EP_4 0x00000040 // Endpoint 4 +#define USB_EP_5 0x00000050 // Endpoint 5 +#define USB_EP_6 0x00000060 // Endpoint 6 +#define USB_EP_7 0x00000070 // Endpoint 7 +#define NUM_USB_EP 8 // Number of supported endpoints + +//***************************************************************************** +// +// These macros allow conversion between 0-based endpoint indices and the +// USB_EP_x values required when calling various USB APIs. +// +//***************************************************************************** +#define IndexToUSBEP(x) ((x) << 4) +#define USBEPToIndex(x) ((x) >> 4) + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hosdev_fifo_config_set() as the +// ui32FIFOSize parameter. +// +//***************************************************************************** +#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO +#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO +#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO +#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO +#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO +#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO +#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO +#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO +#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO + +//***************************************************************************** +// +// This macro allow conversion from a FIFO size label as defined above to +// a number of bytes +// +//***************************************************************************** +#define USBFIFOSizeToBytes(x) (8 << (x)) + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hosdev_endpoint_data_send() +// as the ui32TransType parameter. +// +//***************************************************************************** +#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction +#define USB_TRANS_IN 0x00000102 // Normal IN transaction +#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for +// endpoint 0 in device mode) +#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint +// 0) +#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint +// 0) + +//***************************************************************************** +// +// The following are values are returned by the md_usb_hosdev_mode_get() function. +// +//***************************************************************************** +#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host +// mode. +#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in +// Device mode. +#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not +// set. +#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of +// the cable. +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of +// the cable. +#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of +// the cable Session Valid. +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of +// the cable A valid. +#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of +// the cable. +#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of +// the cable. +#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of +// the cable. +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of +// the cable. +#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set. + +//***************************************************************************** +// +// Channel configuration values. +// +//***************************************************************************** +#define DMA_DST_INC_8 0x00000000 +#define DMA_DST_INC_16 0x40000000 +#define DMA_DST_INC_32 0x80000000 +#define DMA_DST_INC_NONE 0xc0000000 +#define DMA_SRC_INC_8 0x00000000 +#define DMA_SRC_INC_16 0x04000000 +#define DMA_SRC_INC_32 0x08000000 +#define DMA_SRC_INC_NONE 0x0c000000 +#define DMA_SIZE_8 0x00000000 +#define DMA_SIZE_16 0x11000000 +#define DMA_SIZE_32 0x22000000 +#define DMA_DST_PROT_PRIV 0x00200000 +#define DMA_SRC_PROT_PRIV 0x00040000 +#define DMA_ARB_1 0x00000000 +#define DMA_ARB_2 0x00004000 +#define DMA_ARB_4 0x00008000 +#define DMA_ARB_8 0x0000c000 +#define DMA_ARB_16 0x00010000 +#define DMA_ARB_32 0x00014000 +#define DMA_ARB_64 0x00018000 +#define DMA_ARB_128 0x0001c000 +#define DMA_ARB_256 0x00020000 +#define DMA_ARB_512 0x00024000 +#define DMA_ARB_1024 0x00028000 +#define DMA_NEXT_USEBURST 0x00000008 + +//***************************************************************************** +// +// The values for the md_usb_dma_channel_int_enable() and md_usb_dma_channel_int_status() +// APIs. +// +//***************************************************************************** +#define USB_DMA_INT_CH8 0x00000080 +#define USB_DMA_INT_CH7 0x00000040 +#define USB_DMA_INT_CH6 0x00000020 +#define USB_DMA_INT_CH5 0x00000010 +#define USB_DMA_INT_CH4 0x00000008 +#define USB_DMA_INT_CH3 0x00000004 +#define USB_DMA_INT_CH2 0x00000002 +#define USB_DMA_INT_CH1 0x00000001 + +//***************************************************************************** +// +// The values for the md_usb_dma_channel_status() API. +// +//***************************************************************************** +#define USB_DMA_STATUS_ERROR 0x00000100 + +//***************************************************************************** +// +// The valid return values for the USBDMAModeSet() and USBDMAModeGet() APIs or +// USBDMAChannelConfig(). +// +//***************************************************************************** +#define USB_DMA_CFG_BURST_NONE 0x00000000 +#define USB_DMA_CFG_BURST_4 0x00000200 +#define USB_DMA_CFG_BURST_8 0x00000400 +#define USB_DMA_CFG_BURST_16 0x00000600 +#define USB_DMA_CFG_INT_EN 0x00000008 +#define USB_DMA_CFG_MODE_0 0x00000000 +#define USB_DMA_CFG_MODE_1 0x00000004 +#define USB_DMA_CFG_DIR_RX 0x00000000 +#define USB_DMA_CFG_DIR_TX 0x00000002 +#define USB_DMA_CFG_EN 0x00000001 + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_mode_config() as the +// ui3Mode parameter. +// +//***************************************************************************** +#define USB_MODE_HOST_VBUS 0x00000004 +#define USB_MODE_HOST 0x00000002 +#define USB_MODE_DEV_VBUS 0x00000005 +#define USB_MODE_DEV 0x00000003 +#define USB_MODE_OTG 0x00000000 + +//***************************************************************************** +// +// Flags that can be passed to DMAChannelAttributeEnable(), +// DMAChannelAttributeDisable(), and returned from DMAChannelAttributeGet(). +// +//***************************************************************************** +#define DMA_ATTR_USEBURST 0x00000001 +#define DMA_ATTR_ALTSELECT 0x00000002 +#define DMA_ATTR_HIGH_PRIORITY 0x00000004 +#define DMA_ATTR_REQMASK 0x00000008 +#define DMA_ATTR_ALL 0x0000000F + +/* Public functions -----------------------------------------------------------*/ +/** + * @{ SYSTEM API. + */ +extern void md_usb_system_int_disable(void); +extern void md_usb_system_int_enable(void); +extern void md_usb_re_config(bool Device); /* Weak defination */ +extern void md_usb_system_delayms(uint32_t delayms); /* Weak defination */ +extern void md_usb_systic_disable(void); +extern void md_usb_controller_reset(void); +extern void md_usb_controller_enable(void); +extern void md_usb_controller_disable(void); +extern void md_usb_clk_phy_enable(void); +extern void md_usb_clk_phy_disable(void); +extern uint32_t md_usb_nvic_number_get(void); +extern void md_usb_nvic_config(uint32_t NvicNum); /* Weak defination */ +extern void md_usb_nvic_enable(void); +extern void md_usb_nvic_disable(void); +/** + * @} SYSTEM API. + */ + +/** + * @{ USB basic API. + */ +/* Host Mode */ +extern void md_usb_hos_reset(bool bStart); +extern void md_usb_hos_resume(bool bStart); +extern void md_usb_hos_suspend(void); +extern void md_usb_hos_request_status(void); +extern void md_usb_hos_request_in(uint32_t ui32Endpoint); +extern void md_usb_hos_request_in_clear(uint32_t ui32Endpoint); +extern uint32_t md_usb_hos_speed_get(void); +extern uint32_t md_usb_hos_addr_get(uint32_t ui32Endpoint, uint32_t ui32Flags); +extern void md_usb_hos_addr_set(uint32_t ui32Endpoint, + uint32_t ui32Addr, + uint32_t ui32Flags); +extern uint32_t md_usb_hos_hub_addr_get(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hos_hub_addr_set(uint32_t ui32Endpoint, + uint32_t ui32Addr, + uint32_t ui32Flags); +/* Device Mode */ +extern void md_usb_dev_addr_set(uint8_t ui32Address); +extern uint8_t md_usb_dev_addr_get(void); +extern void md_usb_dev_connect(void); +extern void md_usb_dev_disconnect(void); +extern uint32_t md_usb_dev_speed_get(void); +/* Host/Device Mode */ +extern uint32_t md_usb_hosdev_frame_get(void); +extern void md_usb_hosdev_int_disable(uint32_t ui32IntFlags); +extern void md_usb_hosdev_int_enable(uint32_t ui32IntFlags); +extern uint32_t md_usb_hosdev_int_status(void); +extern uint32_t md_usb_hosdev_mode_get(void); +/* otg Mode */ +extern void md_usb_otg_session_request(bool bStart); +extern void md_usb_force_host_mode(void); +extern void md_usb_force_device_mode(void); +extern void md_usb_force_otg_mode(void); +extern void md_usb_mode_config(uint32_t ui32Mode); +/** + * @} USB basic API. + */ + +/** + * @{ USB endpoint API. + */ +/* Host Mode */ +extern void md_usb_hos_endpoint_config_set(uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_data_ack(uint32_t ui32Endpoint); +extern void md_usb_hos_endpoint_data_toggle(uint32_t ui32Endpoint, + bool bDataToggle, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_status_clear(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_speed(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_ping(uint32_t ui32Endpoint, + bool bEnable); +/* Device Mode */ +extern void md_usb_dev_endpoint_config_set(uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32Flags); +extern void md_usb_dev_endpoint_config_get(uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, + uint32_t *pui32Flags); +extern void md_usb_dev_endpoint_ack(uint32_t ui32Endpoint, + bool bIsLastPacket); +extern void md_usb_dev_endpoint_stall(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_dev_endpoint_stall_clear(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_dev_endpoint_status_clear(uint32_t ui32Endpoint, + uint32_t ui32Flags); +/* Host/Device Mode */ +extern uint32_t md_usb_hosdev_endpoint_datavai(uint32_t ui32Endpoint); +extern int32_t md_usb_hosdev_endpoint_data_get(uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size); +extern int32_t md_usb_hosdev_endpoint_data_put(uint32_t ui32Endpoint, + uint8_t *pui8Data, + uint32_t ui32Size); +extern int32_t md_usb_hosdev_endpoint_data_send(uint32_t ui32Endpoint, + uint32_t ui32TransType); +extern void md_usb_hosdev_endpoint_data_togglec(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hosdev_endpoint_pkcount_set(uint32_t ui32Endpoint, + uint32_t ui32Count); +extern uint32_t md_usb_hosdev_endpoint_status(uint32_t ui32Endpoint); +extern void md_usb_hosdev_endpoint_int_disable(uint32_t ui32IntFlags); +extern void md_usb_hosdev_endpoint_int_enable(uint32_t ui32IntFlags); +extern uint32_t md_usb_hosdev_endpoint_int_status(void); +extern uint32_t md_usb_endpoint_number_get(void); +/** + * @} USB endpoint API. + */ + +/** + * @{ USB FIFO API. + */ +extern uint32_t md_usb_hosdev_fifo_addr_get(uint32_t ui32Endpoint); +extern void md_usb_hosdev_fifo_config_get(uint32_t ui32Endpoint, uint32_t *pui32FIFOAddress, + uint32_t *pui32FIFOSize, uint32_t ui32Flags); +extern void md_usb_hosdev_fifo_config_set(uint32_t ui32Endpoint, uint32_t ui32FIFOAddress, + uint32_t ui32FIFOSize, uint32_t ui32Flags); +extern void md_usb_hosdev_fifo_flush(uint32_t ui32Endpoint, uint32_t ui32Flags); +/** + * @} USB FIFO API. + */ + +/** + * @{ USB PWR API.it is not supported by es32f0271. + */ +extern void md_usb_hos_pwr_disable(void); +extern void md_usb_hos_pwr_enable(void); +extern void md_usb_hos_pwr_config(uint32_t ui32Flags); +extern void md_usb_hos_pwrfault_disable(void); +extern void md_usb_hos_pwrfault_enable(void); +/** + * @} USB PWR API. + */ + +/** + * @{ USB LPM API.it is not supported by es32f0271. + */ +extern void md_usb_hos_lpm_send(uint32_t ui32Address, + uint32_t uiEndpoint); +extern void md_usb_hos_lpm_config(uint32_t ui32ResumeTime, + uint32_t ui32Config); +extern bool md_usb_lpm_remotewake_is_enabled(void); +extern void md_usb_hos_lpm_resume(void); +extern void md_usb_dev_lpm_remotewake(void); +extern void md_usb_dev_lpm_config(uint32_t ui32Config); +extern void md_usb_dev_lpm_enable(void); +extern void md_usb_dev_lpm_disable(void); +extern uint32_t md_usb_lpm_link_state_get(void); +extern uint32_t md_usb_lpm_endpoint_get(void); +extern uint32_t md_usb_lpm_status(void); +extern void md_usb_lpm_int_disable(uint32_t ui32Ints); +extern void md_usb_lpm_int_enable(uint32_t ui32Ints); +/** + * @} USB LPM API. + */ + +/** + * @{ USB ULPI API.it is not supported by es32f0271. + */ +extern void md_usb_ulpi_config(uint32_t ui32Config); +extern void md_usb_ulpi_enable(void); +extern void md_usb_ulpi_disable(void); +extern uint8_t md_usb_ulpi_reg_read(uint8_t ui8Reg); +extern void md_usb_ulpi_reg_write(uint8_t ui8Reg, + uint8_t ui8Data); +/** + * @} USB ULPI API. + */ + +/** + * @{ USB DMA API.it is not supported by es32f0271. + */ +extern void md_usb_dma_endpoint_channel_set(uint32_t ui32Endpoint, + uint32_t ui32Channel); +extern void md_usb_dma_endpoint_enable(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_dma_endpoint_disable(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_dma_endpoint_config(uint32_t ui32Endpoint, + uint32_t ui32Config); +extern void md_usb_dma_channel_config(uint32_t ui32Channel, + uint32_t ui32Endpoint, + uint32_t ui32Config); +extern void md_usb_dma_channel_address_set(uint32_t ui32Channel, + void *pvAddress); +extern void *md_usb_dma_channel_address_get(uint32_t ui32Channel); +extern void md_usb_dma_channel_count_set(uint32_t ui32Count, + uint32_t ui32Channel); +extern uint32_t md_usb_dma_channel_count_get(uint32_t ui32Channel); +extern void md_usb_dma_channel_int_enable(uint32_t ui32Channel); +extern void md_usb_dma_channel_int_disable(uint32_t ui32Channel); +extern uint32_t md_usb_dma_channel_int_status(void); +extern void md_usb_dma_channel_enable(uint32_t ui32Channel); +extern void md_usb_dma_channel_disable(uint32_t ui32Channel); +extern uint32_t md_usb_dma_channel_isenabled(uint32_t ui32Channel); +extern uint32_t md_usb_dma_channel_status(uint32_t ui32Channel); +extern void md_usb_dma_channel_status_clear(uint32_t ui32Channel, + uint32_t ui32Status); +/** + * @} USB DMA API. + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics Co., Ltd. *** END OF FILE ****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/ReleaseNote.html b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/ReleaseNote.html new file mode 100644 index 0000000000000000000000000000000000000000..de5a1aada3ce5ba777e37769174f013d1ba49a80 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/ReleaseNote.html @@ -0,0 +1,17 @@ + + + + +ReleaseNote +

    ES32F0271 MD Release Note

    +

    V1.00 2019-1-4

    +

    初版发布

    +

    V1.01 2019-5-7

    +

    1.修改USB MD库相关接口

    +

    V1.03 2019-09-23

    +
      +
    1. 增加ADC校準函數
      2. + +
    + + \ No newline at end of file diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_adc.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..d8571b0912eec9f0450b874fa185d5d04f46cf13 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_adc.c @@ -0,0 +1,298 @@ +/** + ****************************************************************************** + * @file md_adc.c + * @brief ES32F0271 ADC Source File. + * + * @version V1.00.01 + * @data 7/01/2019 + * @author Taipei AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + + +/* Includes -------------------------------------------------------------------*/ +#include "md_adc.h" +#include "md_syscfg.h" +#include + + +/** @addtogroup Micro_Driver + * @{ + */ + + +/** @defgroup ADC ADC + * @brief ADC micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +#define Reference_V1 1 //First reference point +#define Reference_V2 2 //Second reference point + +double Ideal_V1; +double Ideal_V2; +double Reference_V1_ADCValue ; +double Reference_V2_ADCValue ; + +/* Private function prototypes ------------------------------------------------*/ +void (*md_adc_SS0_sample[])(ADC_TypeDef *, uint32_t) = +{ + md_adc_set_ss0_mux0_mux0, + md_adc_set_ss0_mux0_mux1, + md_adc_set_ss0_mux0_mux2, + md_adc_set_ss0_mux0_mux3, + md_adc_set_ss0_mux0_mux4, + md_adc_set_ss0_mux0_mux5, + md_adc_set_ss0_mux0_mux6, + md_adc_set_ss0_mux0_mux7, + md_adc_set_ss0_mux1_mux8, + md_adc_set_ss0_mux1_mux9, + md_adc_set_ss0_mux1_mux10, + md_adc_set_ss0_mux1_mux11, + md_adc_set_ss0_mux1_mux12, + md_adc_set_ss0_mux1_mux13, + md_adc_set_ss0_mux1_mux14, + md_adc_set_ss0_mux1_mux15 +}; + +void (*md_adc_SS1_sample[])(ADC_TypeDef *, uint32_t) = +{ + md_adc_set_ss0_mux0_mux0, + md_adc_set_ss0_mux0_mux1, + md_adc_set_ss0_mux0_mux2, + md_adc_set_ss0_mux0_mux3, + md_adc_set_ss0_mux0_mux4, + md_adc_set_ss0_mux0_mux5, + md_adc_set_ss0_mux0_mux6, + md_adc_set_ss0_mux0_mux7, +}; + +void (*md_adc_SS2_sample[])(ADC_TypeDef *, uint32_t) = +{ + md_adc_set_ss0_mux0_mux0, + md_adc_set_ss0_mux0_mux1, + md_adc_set_ss0_mux0_mux2, + md_adc_set_ss0_mux0_mux3, +}; + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup ADC_PUB_FUNC ADC Public Functions + * @brief ADC Public Functions + * @{ + */ +/** + * @brief ADC Initialization Function. + * @param ADC Instance. + * @param channel + * @retval None + */ +void md_adc_init(ADC_TypeDef *ADCx, md_adc_inittypedef *ADC_InitStruct, uint8_t *channel) +{ + uint8_t i = 0; + + md_syscfg_enable_cfg_currgen(SYSCFG); + md_syscfg_set_cfg_vlrs(SYSCFG, ADC_InitStruct->VRLS); + md_syscfg_enable_cfg_vrefen(SYSCFG); + + if (ADC_InitStruct->SSx == 0) + { + md_adc_set_ss0_con_sel(ADC, ADC_InitStruct->Sel); + md_adc_set_ss0_con_type(ADC, ADC_InitStruct->Type); + + md_adc_set_srate_cntini(ADC, ADC_InitStruct->Cntini); + md_adc_set_srate_cnt(ADC, ADC_InitStruct->Cnt); + md_adc_set_frf_ffrst(ADC); + + + for (i = 0; i < 16; i++) + md_adc_SS0_sample[i](ADC, channel[i]); + + md_adc_enable_ier_ss0ie(ADC); + md_adc_set_ss0_end_end(ADC, ADC_InitStruct->End); + md_adc_enable_ss0_end_ie15(ADC); + md_adc_set_gainh_ch8pga(ADC, MD_ADC_GAIN_CHPGA_X1); + + + md_adc_set_srate(ADC, (ADC_InitStruct->Ckdiv) | ADC_SRATE_CKEN_MSK); + md_adc_enable_ssen_ss0en(ADC); + } + else if (ADC_InitStruct->SSx == 1) + { + md_adc_set_ss1_con_sel(ADC, ADC_InitStruct->Sel); + md_adc_set_ss1_con_type(ADC, ADC_InitStruct->Type); + + md_adc_set_srate_cntini(ADC, ADC_InitStruct->Cntini); + md_adc_set_srate_cnt(ADC, ADC_InitStruct->Cnt); + md_adc_set_frf_ffrst(ADC); + + for (i = 0; i < 8; i++) + md_adc_SS1_sample[i](ADC, channel[i]); + + md_adc_enable_ier_ss1ie(ADC); + md_adc_set_ss1_end_end(ADC, ADC_InitStruct->End); + md_adc_enable_ss1_end_ie7(ADC); + md_adc_set_gainh_ch8pga(ADC, MD_ADC_GAIN_CHPGA_X1); + + md_adc_set_srate(ADC, (ADC_InitStruct->Ckdiv) | ADC_SRATE_CKEN_MSK); + md_adc_enable_ssen_ss1en(ADC); + } + else if (ADC_InitStruct->SSx == 2) + { + md_adc_set_ss2_con_sel(ADC, ADC_InitStruct->Sel); + md_adc_set_ss2_con_type(ADC, ADC_InitStruct->Type); + + md_adc_set_srate_cntini(ADC, ADC_InitStruct->Cntini); + md_adc_set_srate_cnt(ADC, ADC_InitStruct->Cnt); + md_adc_set_frf_ffrst(ADC); + + for (i = 0; i < 4; i++) + md_adc_SS2_sample[i](ADC, channel[i]); + + md_adc_enable_ier_ss2ie(ADC); + md_adc_set_ss2_end_end(ADC, ADC_InitStruct->End); + md_adc_enable_ss2_end_ie3(ADC); + md_adc_set_gainh_ch8pga(ADC, MD_ADC_GAIN_CHPGA_X1); + + md_adc_set_srate(ADC, (ADC_InitStruct->Ckdiv) | ADC_SRATE_CKEN_MSK); + md_adc_enable_ssen_ss2en(ADC); + } + else + { + md_adc_set_ss3_con_sel(ADC, ADC_InitStruct->Sel); + md_adc_set_ss3_con_type(ADC, ADC_InitStruct->Type); + + md_adc_set_srate_cntini(ADC, ADC_InitStruct->Cntini); + md_adc_set_srate_cnt(ADC, ADC_InitStruct->Cnt); + md_adc_set_frf_ffrst(ADC); + + MODIFY_REG(ADC->SS3_MUX0, ADC_SS3_MUX0_MUX0_MSK, MD_ADC_SS_MUX_ADIN8 << ADC_SS3_MUX0_MUX0_POSS); + + md_adc_enable_ier_ss3ie(ADC); + md_adc_set_ss3_end_end(ADC, ADC_InitStruct->End); + md_adc_enable_ss3_end_ie0(ADC); + md_adc_set_gainh_ch8pga(ADC, MD_ADC_GAIN_CHPGA_X1); + + md_adc_set_srate(ADC, (ADC_InitStruct->Ckdiv) | ADC_SRATE_CKEN_MSK); + md_adc_enable_ssen_ss3en(ADC); + } +} + + +/** + * @brief Get the ADC calibration offset data + * @param vref: reference v + * @param vdd: external v + * @param offset: Get Offset + * @param coefficient: Get Coefficient + * @retval None + */ +void md_adc_calibration_data(double vdd, double vref,double *offset,double *coefficient) +{ + Ideal_V1 = Reference_V1 / vref * 4096; + Ideal_V2 = Reference_V2 / vref * 4096; + if (vdd == 5 && vref == 5) + { + if ((FC->ADCTRIM_VDD5V_VREF5V >> 24) == 0xA5) + { + Reference_V1_ADCValue = FC->ADCTRIM_VDD5V_VREF5V & 0xFFF; + Reference_V2_ADCValue = (FC->ADCTRIM_VDD5V_VREF5V >> 12) & 0xFFF; + } + } + else if (vdd == 3.3 && vref == 3.3) + { + if ((FC->ADCTRIM_VDD3V3_VREF3V3 >> 24) == 0xA5) + { + Reference_V1_ADCValue = FC->ADCTRIM_VDD3V3_VREF3V3 & 0xFFF; + Reference_V2_ADCValue = (FC->ADCTRIM_VDD3V3_VREF3V3 >> 12) & 0xFFF; + } + } + else if ((vdd == 5 && vref == 2.5) || (vdd == 3.3 && vref == 2.5)) + { + if ((FC->ADCTRIM_VDD5V_VREF2V5 >> 24) == 0xA5) + { + Reference_V1_ADCValue = FC->ADCTRIM_VDD5V_VREF2V5 & 0xFFF; + Reference_V2_ADCValue = (FC->ADCTRIM_VDD5V_VREF2V5 >> 12) & 0xFFF; + } + } + else + { + + } + +// Reference_V1_ADCValue = 115 ; +// Reference_V2_ADCValue = 365 ; + + printf("Ideal_V1:%.2f\r\n", Ideal_V1); + printf("Ideal_V2:%.2f\r\n", Ideal_V2); + printf("Reference_V1_ADCValue:%.2f\r\n", Reference_V1_ADCValue); + printf("Reference_V2_ADCValue:%.2f\r\n", Reference_V2_ADCValue); + + *offset = (Reference_V2 * Reference_V1_ADCValue - Reference_V1 * Reference_V2_ADCValue) / (Reference_V2 - Reference_V1); + printf("Offset=%.2f\r\n", *offset); + *coefficient = Ideal_V1 / (Reference_V1_ADCValue - *offset); + printf("Coefficient=%.2f\r\n", *coefficient); +} + +/** + * @brief Get the ADC fixed data + * @param SSx: Sequence SSx + * @param offset:input offset + * @param coefficient: input coefficient + * @param calibration :get calibration result + * @retval None + */ + +void md_adc_get_data(uint8_t SSx,double offset,double coefficient, uint16_t *calibration) +{ + uint16_t i, data, s_times; + double calibration_value = 0; + + if (SSx == 0) + s_times = 16; + else if (SSx == 1) + s_times = 8; + else if (SSx == 2) + s_times = 4; + else + s_times = 1; + + for (i = 0; i < s_times; i++) + { + if(SSx == 0) + data = md_adc_get_ss0_data(ADC); + else if(SSx == 1) + data = md_adc_get_ss1_data(ADC); + else if(SSx == 2) + data = md_adc_get_ss2_data(ADC); + else + data = md_adc_get_ss3_data(ADC); + if(data >= 4095) + data = 4095; + printf("data = %4d\r\n",data); + calibration_value = (data - offset) * coefficient; + if (calibration_value >= 4095) + calibration_value = 4095; + *calibration++=(uint16_t)calibration_value; + } +} +/** + * @} ADC_PUB_FUNC ADC Public Functions + */ + +/** + * @} ADC + */ + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_fc.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_fc.c new file mode 100644 index 0000000000000000000000000000000000000000..ce5d644209d90e0dceec35a37771905c72a81eb8 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_fc.c @@ -0,0 +1,300 @@ +/** + ****************************************************************************** + * @file md_fc.c + * @brief ES32F0271 FC Source File. + * + * @version V1.00.01 + * @date day/mon/year + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_syscfg.h" +#include "md_fc.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (FC) + +/** @defgroup FC FC + * @brief FC micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Private constants ----------------------------------------------------------*/ +/** @defgroup MD_FC_Private_Constants FC Private Constants + * @{ + */ + +#define REMAPDATA_BASE (( uint32_t)0x00000000) /* FLASH Main (64K Bytes) */ +#define REMAPINFO_BASE (( uint32_t)0x00000000) /* FLASH Info ( 6K Bytes) - Boot Loader Memory */ + +#define EFOPT_PAGE6_OFFSET (MD_FC_PC_EF_IPAGESZ*6) +#define EFOPT_PAGE7_OFFSET (MD_FC_PC_EF_IPAGESZ*7) +#define EFOPT_PL1_OFFSET (MD_FC_PC_EF_IPAGESZ*7+0x0) +#define EFOPT_PL2_OFFSET (MD_FC_PC_EF_IPAGESZ*6+0x28) +#define EFOPT_REMAP_OFFSET (MD_FC_PC_EF_IPAGESZ*7+0x8) + +/** + * @} MD_FC_Private_Constants + */ + +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_FC_Public_Functions FC Public Functions + * @{ + */ + +/** + * @brief FC main erase. + * @note To prevent unexpected code branch, the main erase function must specify a dedicated main erase ID + * @param MEraseID Key for main erase, must be 0xA5A5AA55 + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Main flash erased + * - ERROR: Main erase ID mismatch + */ +ErrorStatus md_fc_merase(uint32_t MEraseID) +{ + ErrorStatus status = ERROR; + + /* Check the ID */ + if (MEraseID != MD_FC_PC_EF_MERASEID) + return status; + + /* Write MERASE to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_MACRO_ERASE); + + status = SUCCESS; + return status; +} + +/** + * @brief FC Sector Erase + * @note To prevent unexpected code branch, the page erase function must specify the complement start address + * @param pSErasePara Pointer to structure md_fc_ControlTypeDef + * @retval An ErrorStatus enumeration value. + * - SUCCESS: Specified page address erased + * - ERROR: Complement of start address mismatch + */ +ErrorStatus md_fc_serase(md_fc_ControlTypeDef *pSErasePara) +{ + ErrorStatus status = ERROR; + + /* Check the start address and complement of start address*/ + if (pSErasePara->SAddr & pSErasePara->SAddrC) + return status; + + /* Write sector address to PA*/ + md_fc_set_pa_prog_addr(pSErasePara->SAddr); + /* Write SERASE to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_SECTOR_ERASE); + + status = SUCCESS; + return status; +} + +/** + * @brief FC Page Program + * @note To prevent unexpected code branch, the page program function must specify the complement start address + * @param pProgramPara Pointer to structure md_fc_ControlTypeDef + * @retval An ErrorStatus enumeration value. + * - SUCCESS: Data in data buffer programed to specified page address + * - ERROR: Complement of start address mismatch + */ +ErrorStatus md_fc_program(md_fc_ControlTypeDef *pProgramPara) +{ + ErrorStatus status = ERROR; + uint16_t BCnt; + + md_fc_set_pa_pcnt(pProgramPara->BCnt); + md_fc_set_pa_prog_addr(pProgramPara->SAddr); + BCnt = pProgramPara->BCnt; + BCnt >>= 3; + + while (BCnt--) + { + /* Check the start address and complement of start address*/ + if (pProgramPara->SAddr & pProgramPara->SAddrC) + return status; + + /* Write lower 32bit program data to PLD*/ + md_fc_set_pld(*pProgramPara->pU32Buf++); + /* Write higher 32bit program data to PHD*/ + md_fc_set_phd(*pProgramPara->pU32Buf++); + /* Write PROGRAM to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_PROG_EFLASH); + } + + status = SUCCESS; + return status; +} + +/** + * @brief FC Page Read + * @param pReadPara Pointer to structure md_fc_ControlTypeDef + * @retval Always return SUCCESS + * - Data in specified page address read to data buffer + */ +ErrorStatus md_fc_read(md_fc_ControlTypeDef *pReadPara) +{ + ErrorStatus status = SUCCESS; + uint32_t *EFAddr; + uint16_t BCnt; + + if (md_syscfg_get_remap_memmod(SYSCFG) == MD_SYSCFG_MEMMOD_MAIN) /* Reamp from Main */ + EFAddr = (uint32_t *)(REMAPDATA_BASE + pReadPara->SAddr); + else + EFAddr = (uint32_t *)(FLASH_BASE + pReadPara->SAddr); + + BCnt = pReadPara->BCnt; + BCnt >>= 2; + + while (BCnt--) + *pReadPara->pU32Buf++ = *EFAddr++; + + return status; +} + +/** + * @brief FC Update Protect Level 1 Setting + * @param pUpdPL1Para Pointer to structure md_fc_UpdProtTypeDdef + * @retval Always return SUCCESS + */ +ErrorStatus md_fc_updprotl1(md_fc_UpdProtTypeDef *pUpdPL1Para) +{ + ErrorStatus status = SUCCESS; + uint32_t EFProtL1L, EFProtL1H; + + EFProtL1L = FC->OP_PRT1L; + EFProtL1H = FC->OP_PRT1H; + + if ((EFProtL1L == 0xffffffffUL) && (EFProtL1H == 0xffffffffUL)) /* First Time to Set Level1 */ + { + /* Write offset address to PA*/ + md_fc_set_pa_prog_addr(EFOPT_PL1_OFFSET); + md_fc_enable_pa_ifren(); + /* Write lower 32bit update data to PLD*/ + md_fc_set_pld(pUpdPL1Para->UpdateL); + /* Write higher 32bit update data to PHD*/ + md_fc_set_phd(pUpdPL1Para->UpdateH); + + /* Write PROGRAM to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_PROG_EFLASH); + } + else + { + /* Write lower 32bit clear data to PLD*/ + md_fc_set_pld(pUpdPL1Para->ClearL); + /* Write higher 32bit clear data to PHD*/ + md_fc_set_phd(pUpdPL1Para->ClearH); + + /* Write lower 32bit data to UPL*/ + md_fc_set_upl(pUpdPL1Para->UpdateL); + /* Write higher 32bit data to UPH*/ + md_fc_set_uph(pUpdPL1Para->UpdateH); + + /* Write UPDPL1 to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_UPDATE_LV1_PROTECT); + } + + return status; +} + +/** + * @brief FC Update Protect Level 2 Setting + * @param pUpdPL2Para Pointer to structure md_fc_UpdProtTypeDdef + * @retval Always return SUCCESS + */ +ErrorStatus md_fc_updprotl2(md_fc_UpdProtTypeDef *pUpdPL2Para) +{ + ErrorStatus status = SUCCESS; + uint32_t EFProtL2L, EFProtL2H; + + EFProtL2L = FC->OP_PRT2L; + EFProtL2H = FC->OP_PRT2H; + + if ((EFProtL2L == 0xffffffffUL) && (EFProtL2H == 0xffffffffUL)) /* First Time to Set Level2 */ + { + /* Write offset address to PA*/ + md_fc_set_pa_prog_addr(EFOPT_PL2_OFFSET); + md_fc_enable_pa_ifren(); + /* Write lower 32bit update data to PLD*/ + md_fc_set_pld(pUpdPL2Para->UpdateL); + /* Write higher 32bit update data to PHD*/ + md_fc_set_phd(pUpdPL2Para->UpdateH); + + /* Write PROGRAM to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_PROG_EFLASH); + } + else + { + /* Write lower 32bit clear data to PLD*/ + md_fc_set_pld(pUpdPL2Para->ClearL); + /* Write higher 32bit clear data to PHD*/ + md_fc_set_phd(pUpdPL2Para->ClearH); + + /* Write lower 32bit data to UPL*/ + md_fc_set_upl(pUpdPL2Para->UpdateL); + /* Write higher 32bit data to UPH*/ + md_fc_set_uph(pUpdPL2Para->UpdateH); + + /* Write UPDPL2 to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_UPDATE_LV2_PROTECT); + } + + return status; +} + +/** + * @brief FC Update Remap Option + * @param UpdRemap New remap setting value (remap address=valus(0x0~0xf)*0x1000, 0x10=BootLoader) + * @retval Always return SUCCESS + */ +ErrorStatus md_fc_updremap(uint8_t UpdRemap) +{ + ErrorStatus status = SUCCESS; + + /* Write sector address to PA*/ + md_fc_enable_pa_ifren(); + md_fc_set_pa_prog_addr(EFOPT_PAGE7_OFFSET); + /* Write SERASE to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_SECTOR_ERASE); + /* Write remap offset address to PA*/ + md_fc_set_pa_prog_addr(EFOPT_REMAP_OFFSET); + md_fc_enable_pa_ifren(); + /* Write lower 32bit remap data to PLD*/ + md_fc_set_pld(0xffffff00UL | UpdRemap); + /* Write higher 32bit remap data to PHD*/ + md_fc_set_phd(0xffffffffUL); + /* Write PROGRAM to CMD*/ + md_fc_set_fc_cmd(MD_FC_PC_CMD_PROG_EFLASH); + + return status; +} + +/** + * @} MD_FC_Public_Functions + */ + +/** + * @} FC + */ +#endif + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_gpio.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..0fa1126bab3d2b47582e0fe5d13eb2398213c9cb --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_gpio.c @@ -0,0 +1,215 @@ +/** + ****************************************************************************** + * @file md_gpio.c + * @brief ES32F0271 GPIO Source File. + * + * @version V1.00.01 + * @data day/mon/year + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_rcu.h" +#include "md_gpio.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) + +/** @defgroup GPIO GPIO + * @brief GPIO micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/** @defgroup MD_GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_MD_GPIO_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__ == GPIOA) \ + || (__INSTANCE__ == GPIOB)) \ +|| (__INSTANCE__ == GPIOC)) \ +|| (__INSTANCE__ == GPIOD)) + +#define IS_MD_GPIO_PIN(__VALUE__) (((__VALUE__) == MD_GPIO_PIN_0) \ + || ((__VALUE__) == MD_GPIO_PIN_1) \ + || ((__VALUE__) == MD_GPIO_PIN_2) \ + || ((__VALUE__) == MD_GPIO_PIN_3) \ + || ((__VALUE__) == MD_GPIO_PIN_4) \ + || ((__VALUE__) == MD_GPIO_PIN_5) \ + || ((__VALUE__) == MD_GPIO_PIN_6) \ + || ((__VALUE__) == MD_GPIO_PIN_7) \ + || ((__VALUE__) == MD_GPIO_PIN_8) \ + || ((__VALUE__) == MD_GPIO_PIN_9) \ + || ((__VALUE__) == MD_GPIO_PIN_10) \ + || ((__VALUE__) == MD_GPIO_PIN_11) \ + || ((__VALUE__) == MD_GPIO_PIN_12) \ + || ((__VALUE__) == MD_GPIO_PIN_13) \ + || ((__VALUE__) == MD_GPIO_PIN_14) \ + || ((__VALUE__) == MD_GPIO_PIN_15)) \ + +#define IS_MD_GPIO_MODE(__VALUE__) (((__VALUE__) == MD_GPIO_MODE_INPUT) \ + || ((__VALUE__) == MD_GPIO_MODE_OUTPUT) \ + || ((__VALUE__) == MD_GPIO_MODE_FUNCTION) \ + || ((__VALUE__) == MD_GPIO_MODE_ANALOG)) + +#define IS_MD_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == MD_GPIO_OUTPUT_PUSHPULL) \ + || ((__VALUE__) == MD_GPIO_OUTPUT_OPENDRAIN)) + +#define IS_MD_GPIO_PULL(__VALUE__) (((__VALUE__) == MD_GPIO_PULL_FLOATING) \ + || ((__VALUE__) == MD_GPIO_PULL_UP) \ + || ((__VALUE__) == MD_GPIO_PULL_DOWN) + +#define IS_MD_GPIO_DS(__VALUE__) (((__VALUE__) == MD_GPIO_DS_8mA) \ + || ((__VALUE__) == MD_GPIO_DS_16mA)) + +#define IS_MD_GPIO_FUNCTION(__VALUE__) (((__VALUE__) == MD_GPIO_AF0) \ + || ((__VALUE__) == MD_GPIO_AF1) \ + || ((__VALUE__) == MD_GPIO_AF2) \ + || ((__VALUE__) == MD_GPIO_AF3) \ + || ((__VALUE__) == MD_GPIO_AF4) \ + || ((__VALUE__) == MD_GPIO_AF5) \ + || ((__VALUE__) == MD_GPIO_AF6) \ + || ((__VALUE__) == MD_GPIO_AF7)) + +#define IS_MD_GPIO_IST(__VALUE__) (((__VALUE__) == MD_GPIO_IST_TTL) \ + || ((__VALUE__) == MD_GPIO_IST_CMOS)) + +/** + * @} MD_GPIO_Private_Macros + */ + +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ +/** @addtogroup MD_GPIO_Public_Functions GPIO Public Functions + * @{ + */ + +/** @addtogroup MD_GPIO_PF_Init GPIO Public Init Functions + * @{ + */ + +/** + * @brief De-initialize the GPIO registers to their default reset values. + * @param GPIOx GPIO Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are de-initialized + * - ERROR: GPIO registers are not de-initialized + */ +ErrorStatus md_gpio_deinit(GPIO_TypeDef *GPIOx) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_MD_GPIO_ALL_INSTANCE(GPIOx)); + + /* Force reset of GPIO clock */ + if (GPIOx == GPIOA) + { + md_rcu_enable_ahbrst_gpaen(RCU); + } + else if (GPIOx == GPIOB) + { + md_rcu_enable_ahbrst_gpben(RCU); + } + else if (GPIOx == GPIOC) + { + md_rcu_enable_ahbrst_gpcen(RCU); + } + else /* if(GPIOx==GPIOD) */ + { + md_rcu_enable_ahbrst_gpden(RCU); + } + + status = SUCCESS; + + return status; +} + +/** + * @brief Initialize the GPIO registers according to the specified parameters in GPIO_InitStruct. + * @note As some bits in GPIO configuration registers can only be written when the GPIO is disabled (GPIO_CR1_SPE bit =0), + * GPIO IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @param GPIOx GPIO Instance + * @param GPIO_InitStruct pointer to a @ref md_gpio_inittypedef structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus md_gpio_init(GPIO_TypeDef *GPIOx, md_gpio_inittypedef *GPIO_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the GPIO Instance GPIOx*/ + assert_param(IS_MD_GPIO_ALL_INSTANCE(GPIOx)); + + /* Check the GPIO parameters from GPIO_InitStruct*/ + assert_param(IS_MD_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_MD_GPIO_MODE(GPIO_InitStruct->Mode)); + assert_param(IS_MD_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + assert_param(IS_MD_GPIO_PULL(GPIO_InitStruct->Pull)); + assert_param(IS_MD_GPIO_DS(GPIO_InitStruct->OutDrive)); + assert_param(IS_MD_GPIO_FUNCTION(GPIO_InitStruct->Function)); + + if (POSITION_VAL(GPIO_InitStruct->Pin) <= 7) + { + md_gpio_set_function0_7(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->Function); + } + else + { + md_gpio_set_function8_15(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->Function); + } + + md_gpio_set_mode(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->Mode); + md_gpio_set_output_type(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); + md_gpio_set_pull(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->Pull); + md_gpio_set_ds(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutDrive); + + status = SUCCESS; + + return status; +} + +/** + * @brief Set each @ref md_gpio_inittypedef field to default value. + * @param GPIO_InitStruct pointer to a @ref md_gpio_inittypedef structure + * whose fields will be set to default values. + * @retval None + */ +void md_gpio_struct_init(md_gpio_inittypedef *GPIO_InitStruct) +{ + /* Set GPIO_InitStruct fields to default values */ + GPIO_InitStruct->Function = MD_GPIO_AF0; + GPIO_InitStruct->Mode = MD_GPIO_MODE_ANALOG; + GPIO_InitStruct->OutDrive = MD_GPIO_DS_8mA; + GPIO_InitStruct->OutputType = MD_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct->Pull = MD_GPIO_PULL_FLOATING; + GPIO_InitStruct->Pin = MD_GPIO_PIN_ALL; +} + +/** + * @} MD_GPIO_PF_Init + */ + +/** + * @} MD_GPIO_Public_Functions + */ + +/** + * @} GPIO + */ +#endif + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_i2c.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..e2dab7dc57ad99e2b39faf375025aab336c1aa8c --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_i2c.c @@ -0,0 +1,245 @@ +/** + ****************************************************************************** + * @file md_i2c.c + * @brief ES32F0271 I2C Source File. + * + * @version V1.00.01 + * @date 4/12/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_i2c.h" +#include "md_rcu.h" +#include +#include "stdint.h" +/** @addtogroup Micro_Driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/** + * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct. + * @note The parameters in md_i2c_init should be expected values. Otherwise, ERROR result will be returned. + * @param I2Cx I2C Instance + * @param I2C_InitStruct pointer to a @ref md_i2c_inittypedef structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus md_i2c_init(I2C_TypeDef *I2Cx, md_i2c_inittypedef *I2C_InitStruct) +{ + ErrorStatus status = ERROR; + uint8_t pllmulnow; + + /* Check the I2C Instance I2Cx */ + assert_param(IS_MD_I2C_ALL_INSTANCE(I2Cx)); + + /* Check the I2C parameters from I2C_InitStruct */ + assert_param(IS_MD_I2C_TIMING(I2C_InitStruct->Timing)); + assert_param(IS_MD_I2C_ADDRSIZE(I2C_InitStruct->AddrSize)); + assert_param(IS_MD_I2C_ADDRESS1(I2C_InitStruct->Address1)); + assert_param(IS_MD_I2C_DUALADDRESSMODE(I2C_InitStruct->DualAddressMode)); + assert_param(IS_MD_I2C_ADDRESS2(I2C_InitStruct->Address2)); + assert_param(IS_MD_I2C_ADDRESS2MASKS(I2C_InitStruct->Address2Masks)); + /* Check the PLL clock, if not corrt, modify it */ + pllmulnow = md_rcu_get_cfg_pllmul(RCU); + + if (pllmulnow != (uint8_t)((I2C_InitStruct->Timing) >> 28)) + { + md_rcu_pllreinit((uint8_t)((I2C_InitStruct->Timing) >> 28)); + } + + md_i2c_disable_con1_pe(I2Cx); + md_i2c_set_timingr_presc(I2Cx, ((I2C_InitStruct->Timing) >> 24) & 0xF); + md_i2c_set_timingr_scll(I2Cx, ((I2C_InitStruct->Timing) >> 16) & 0xFF); + md_i2c_set_timingr_sclh(I2Cx, ((I2C_InitStruct->Timing) >> 8) & 0xFF); + md_i2c_set_timingr_sdadel(I2Cx, ((I2C_InitStruct->Timing) >> 4) & 0xF); + md_i2c_set_timingr_scldel(I2Cx, (I2C_InitStruct->Timing) & 0xF); + md_i2c_enable_con1_pe(I2Cx); + + md_i2c_disable_addr1_oa1en(I2Cx); + md_i2c_set_addr1_oa1(I2Cx, I2C_InitStruct->Address1); + + if (I2C_InitStruct->AddrSize == MD_I2C_OA1_10BIT) + md_i2c_set_addr1_oa1mode(I2Cx, MD_I2C_OA1_10BIT); + else + md_i2c_set_addr1_oa1mode(I2Cx, MD_I2C_OA1_7BIT); + + md_i2c_enable_addr1_oa1en(I2Cx); + + if (I2C_InitStruct->DualAddressMode == MD_I2C_DUALADDRESS_ENABLE) + { + md_i2c_disable_addr2_oa2en(I2Cx); + md_i2c_set_addr2_oa2mask(I2Cx, I2C_InitStruct->Address2Masks); + md_i2c_set_addr2_oa2(I2Cx, I2C_InitStruct->Address2); + md_i2c_enable_addr2_oa2en(I2Cx); + } + + status = SUCCESS; + + return status; +} + +/** + * @brief Set each @ref md_i2c_inittypedef field to default value. + * @param UART_InitStruct pointer to a @ref md_i2c_inittypedef structure + * whose fields will be set to default values. + * @retval None + */ +void md_i2c_struct_init(md_i2c_inittypedef *I2C_InitStruct) +{ + /* Set UART_InitStruct fields to default values */ + I2C_InitStruct->Timing = CLK100kHz48M; + I2C_InitStruct->AddrSize = MD_I2C_ADDRESSINGMODE_7BIT; + I2C_InitStruct->Address1 = 0x50 << 1; + I2C_InitStruct->DualAddressMode = MD_I2C_DUALADDRESS_DISABLE; + I2C_InitStruct->Address2 = 0x70 << 1; + I2C_InitStruct->Address2Masks = MD_I2C_ADDR2_NOMASK; +} + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param I2Cx I2C Instance + * @param The number of bytes to be transmitted + * @param Enable/Disable 10-bit addressing mode + * @param Device(slave) address + * @param The pointer to a data buffer + * @retval None + */ +void md_i2c_master_send(I2C_TypeDef *I2Cx, uint8_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t *txbuf) +{ + uint8_t index; + + /* Config Device(slave) address */ + if (addr10 == MD_I2C_ADDRESSINGMODE_10BIT) + md_i2c_set_con2_add10(I2Cx, MD_I2C_ADDRESSINGMODE_10BIT); + else + md_i2c_set_con2_add10(I2Cx, MD_I2C_ADDRESSINGMODE_7BIT); + + md_i2c_set_con2_sadd(I2Cx, DevAddr); + md_i2c_set_con2_nbytes(I2Cx, Nbyte); + md_i2c_set_fcon_txfrst(I2Cx, MD_I2C_TXFIFO_RESET); + md_i2c_set_con2_rd_wrn(I2Cx, MD_I2C_MASTER_WRITE); + md_i2c_set_con2_reload(I2Cx, MD_I2C_NORELOAD_MODE); + /* When NBYTES is matched, the communication will be automatically stop */ + md_i2c_set_con2_autoend(I2Cx, MD_I2C_AUTOEND_MODE); + + if (Nbyte <= 8) + { + for (index = 0; index < Nbyte; index++) + md_i2c_send(I2Cx, *txbuf++); + + Nbyte = 0; + } + else + { + for (index = 0; index < 8; index++) + md_i2c_send(I2Cx, *txbuf++); + + Nbyte -= 8; + } + + /* Start the I2C communication */ + md_i2c_set_con2_start(I2Cx, MD_I2C_START_GENERATION); + + while (Nbyte > 0) + { + while (md_i2c_is_active_stat_txf(I2Cx)); + + md_i2c_send(I2Cx, *txbuf++); + Nbyte--; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param I2Cx I2C Instance + * @param The number of bytes to be received + * @param Enable/Disable 10-bit addressing mode + * @param Device(slave) address + * @param The pointer to a data buffer + * @retval None + */ +void md_i2c_master_rece(I2C_TypeDef *I2Cx, uint8_t Nbyte, uint32_t addr10, uint16_t DevAddr, uint8_t *rxbuf) +{ + /* Config Device(slave) address */ + if (addr10 == MD_I2C_ADDRESSINGMODE_10BIT) + md_i2c_set_con2_add10(I2Cx, MD_I2C_ADDRESSINGMODE_10BIT); + else + md_i2c_set_con2_add10(I2Cx, MD_I2C_ADDRESSINGMODE_7BIT); + + md_i2c_set_con2_sadd(I2Cx, DevAddr); + md_i2c_set_con2_nbytes(I2Cx, Nbyte); + md_i2c_set_fcon_rxfrst(I2Cx, MD_I2C_RXFIFO_RESET); + md_i2c_set_con2_rd_wrn(I2Cx, MD_I2C_MASTER_READ); + md_i2c_set_con2_reload(I2Cx, MD_I2C_NORELOAD_MODE); + /* When NBYTES is matched, the communication will be automatically stop */ + md_i2c_set_con2_autoend(I2Cx, MD_I2C_AUTOEND_MODE); + /* Start the I2C communication */ + md_i2c_set_con2_start(I2Cx, MD_I2C_START_GENERATION); + + while (Nbyte > 0) + { + /* Wait Rx FIFO non-empty */ + while (md_i2c_is_active_stat_rxe(I2Cx)); + + *rxbuf++ = md_i2c_recv(I2Cx); + Nbyte--; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param I2Cx I2C Instance + * @param The number of bytes to be transmitted, not for NBYTES + * @param The pointer to a data buffer + * @retval None + */ +void md_i2c_slave_send(I2C_TypeDef *I2Cx, uint8_t Num, uint8_t *txbuf) +{ + md_i2c_set_fcon_txfrst(I2Cx, MD_I2C_TXFIFO_RESET); + + while (!(md_i2c_is_active_stat_busy(I2Cx))); + + while (Num > 0) + { + while (md_i2c_is_active_stat_txf(I2Cx)); + + md_i2c_send(I2Cx, *txbuf++); + Num--; + } +} + +/** + * @brief Receives in slave mode an amount of data in blocking mode. + * @param I2Cx I2C Instance + * @param The number of bytes to be transmitted, not for NBYTES + * @param The pointer to a data buffer + * @retval None + */ +void md_i2c_slave_rece(I2C_TypeDef *I2Cx, uint8_t Num, uint8_t *rxbuf) +{ + md_i2c_set_fcon_rxfrst(I2Cx, MD_I2C_RXFIFO_RESET); + + while (!(md_i2c_is_active_stat_busy(I2Cx))); + + while (Num > 0) + { + while (md_i2c_is_active_stat_rxe(I2Cx)); + + *rxbuf++ = md_i2c_recv(I2Cx); + Num--; + } +} + +/** + * @} Micro_Driver + */ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_rcu.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_rcu.c new file mode 100644 index 0000000000000000000000000000000000000000..99ac22cf91bb4fc692980a72cff3bd70378bcea5 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_rcu.c @@ -0,0 +1,378 @@ +/** + ****************************************************************************** + * @file md_rcu.c + * @brief ES32F0271 RCU Source File. + * + * @version V1.00.01 + * @data 6/12/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_rcu.h" +#include "md_fc.h" +#include "system_es32f027x.h" + +/** @addtogroup Micro_Driver + * @{ + */ + + +/** @defgroup RCU RCU + * @brief RCU micro driver + * @{ + */ + + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/** @defgroup MD_RCU_Private_Macros RCU Private Macros + * @{ + */ + + +/** + * @} MD_RCU_Private_Macros + */ + +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ +/** @addtogroup MD_RCU_Public_Functions RCU Public Functions + * @{ + */ + +/** @addtogroup MD_RCU_PF_Init RCU Public Init Functions + * @{ + */ + +/** + * @brief + * @param + * @retval None + */ +void md_rcu_init(void) +{ + uint8_t pllmux; + + md_fc_set_con_wait(3); + + md_rcu_set_cfg_mpre(RCU, 0UL); + md_rcu_set_cfg_msw(RCU, MD_RCU_MCO_DISABLE); + md_rcu_set_cfg_pllmul(RCU, 12 - 1); + md_rcu_set_cfg_pllsrc(RCU, MD_RCU_PLL_SRC_HRC); + md_rcu_set_cfg_hoscdiv(RCU, 2 - 1); + md_rcu_set_cfg_ppre(RCU, MD_RCU_PPRE_HCLK_DIV_1); + md_rcu_set_cfg_hpre(RCU, MD_RCU_HPRE_SYSCLK_DIV_1); + md_rcu_set_cfg_sw(RCU, MD_RCU_SYSCLK_PLL0); + + md_rcu_disable_con_csson(RCU); + md_rcu_disable_con_pll1on(RCU); + md_rcu_enable_con_pll0on(RCU); + md_rcu_disable_con_loscon(RCU); + md_rcu_disable_con_lrcon(RCU); + md_rcu_disable_con_hoscon(RCU); + md_rcu_enable_con_hrcon(RCU); + + md_rcu_set_cfg_ckcfg(RCU); + + /* while(md_rcu_get_con_hoscrdy(RCU)==0) {} */ + + /* while(md_rcu_get_con_pll0rdy(RCU)==0) {} */ + + + if (RCU->CON & RCU_CON_HRCON_MSK) /* if HRC enbale */ + while (md_rcu_get_con_hrcrdy(RCU) == 0); /* Wait for HRCRDY = 1 (HRC is ready)*/ + + + if (RCU->CON & RCU_CON_HOSCON_MSK) /* if HOSC enbale */ + while (md_rcu_get_con_hoscrdy(RCU) == 0); /* Wait for HOSCRDY = 1 (HOSC is ready)*/ + + + if (RCU->CON & RCU_CON_LRCON_MSK) /* if LRC enbale */ + while (md_rcu_get_con_lrcrdy(RCU) == 0); /* Wait for LRCRDY = 1 (LRC is ready)*/ + + + if (RCU->CON & RCU_CON_LOSCON_MSK) /* if LOSC enbale */ + while (md_rcu_get_con_loscrdy(RCU) == 0); /* Wait for LOSCRDY = 1 (LOSC is ready)*/ + + if (RCU->CON & RCU_CON_PLL0ON_MSK) /* if PLL enbale */ + while (md_rcu_get_con_pll0rdy(RCU) == 0); /* Wait for PLLRDY = 1 (PLL is ready)*/ + + + + /* PLL Reference Clock Source*/ + if (md_rcu_get_cfg_pllsrc(RCU)) + PLL0Frequency = (uint32_t)(__HOSC / (md_rcu_get_cfg_pllsrc(RCU) + 1)); + else + PLL0Frequency = (uint32_t)(__HRC); + + /* System Frequency */ + switch (md_rcu_get_cfg_sw(RCU)) /* System clock switch(SYSCLK) */ + { + case 0: /*================= HRC selected as system clock*/ + SystemCoreClock = (uint32_t)(__HRC); + break; + + case 1: /*================= HOSC selected as system clock*/ + SystemCoreClock = (uint32_t)(__HOSC); + break; + + case 2: /*================= LRC selected as system clock*/ + SystemCoreClock = (uint32_t)(__LRC); + break; + + case 3: /*================= LOSC selected as system clock*/ + SystemCoreClock = (uint32_t)(__LOSC); + break; + + case 4: /*================= PLL selected as system clock*/ + pllmux = md_rcu_get_cfg_pllmul(RCU) + 1; + + if (pllmux >= 18) pllmux = 18; + + SystemCoreClock = (uint32_t)(PLL0Frequency * pllmux); + break; + + default: + SystemCoreClock = (uint32_t)(__HRC); + break; + } + + /* Core Frequency */ + if (md_rcu_get_cfg_hpre(RCU)) + SystemFrequency_SysClk = SystemCoreClock >> ((md_rcu_get_cfg_hpre(RCU) & 0x07) + 1); + else + SystemFrequency_SysClk = SystemCoreClock; + + /* AHB Frequency */ + SystemFrequency_AHBClk = SystemFrequency_SysClk; + + /* APB Frequency */ + if (md_rcu_get_cfg_ppre(RCU)) + SystemFrequency_APBClk = SystemFrequency_SysClk >> ((md_rcu_get_cfg_ppre(RCU) & 0x03) + 1); + else + SystemFrequency_APBClk = SystemFrequency_SysClk; + + + if (SystemFrequency_AHBClk / 1000000 > 72) + md_fc_set_con_wait(3); + else if (SystemFrequency_AHBClk / 1000000 > 48) + md_fc_set_con_wait(2); + else if (SystemFrequency_AHBClk / 1000000 > 24) + md_fc_set_con_wait(1); + else + md_fc_set_con_wait(0); +} + +void md_rcu_init_set(RCU_TypeDef *rcu, md_rcu_init_typedef *RCU_InitStruct) +{ + uint8_t pllmux; + + md_fc_set_con_wait(3); + + md_rcu_set_cfg_mpre(rcu, RCU_InitStruct->Mpre); + md_rcu_set_cfg_msw(rcu, RCU_InitStruct->Msw); + md_rcu_set_cfg_pllmul(rcu, (RCU_InitStruct->PllMul) - 1); + md_rcu_set_cfg_pllsrc(rcu, RCU_InitStruct->PllSrc); + md_rcu_set_cfg_hoscdiv(rcu, (RCU_InitStruct->HoscDiv) - 1); + md_rcu_set_cfg_ppre(rcu, RCU_InitStruct->Ppre); + md_rcu_set_cfg_hpre(rcu, RCU_InitStruct->Hpre); + md_rcu_set_cfg_sw(rcu, RCU_InitStruct->Sw); + + if(RCU_InitStruct->SysClock & RCU_CON_CSSON_MSK) + md_rcu_enable_con_csson(rcu); + else + md_rcu_disable_con_csson(rcu); + + if(RCU_InitStruct->SysClock & RCU_CON_PLL1ON_MSK) + md_rcu_enable_con_pll1on(rcu); + else + md_rcu_disable_con_pll1on(rcu); + + if(RCU_InitStruct->SysClock & RCU_CON_PLL0ON_MSK) + md_rcu_enable_con_pll0on(rcu); + else + md_rcu_disable_con_pll0on(rcu); + + if(RCU_InitStruct->SysClock & RCU_CON_LOSCON_MSK) + md_rcu_enable_con_loscon(rcu); + else + md_rcu_disable_con_loscon(rcu); + + if(RCU_InitStruct->SysClock & RCU_CON_LRCON_MSK) + md_rcu_enable_con_lrcon(rcu); + else + md_rcu_disable_con_lrcon(rcu); + + if(RCU_InitStruct->SysClock & RCU_CON_HOSCON_MSK) + md_rcu_enable_con_hoscon(rcu); + else + md_rcu_disable_con_hoscon(rcu); + + if(RCU_InitStruct->SysClock & RCU_CON_HRCON_MSK) + md_rcu_enable_con_hrcon(rcu); + else + md_rcu_disable_con_hrcon(rcu); + + md_rcu_set_cfg_ckcfg(rcu); + + /* while(md_rcu_get_con_hoscrdy(RCU)==0) {} */ + + /* while(md_rcu_get_con_pll0rdy(RCU)==0) {} */ + + + if (RCU->CON & RCU_CON_HRCON_MSK) /* if HRC enbale */ + while (md_rcu_get_con_hrcrdy(rcu) == 0); /* Wait for HRCRDY = 1 (HRC is ready)*/ + + + if (RCU->CON & RCU_CON_HOSCON_MSK) /* if HOSC enbale */ + while (md_rcu_get_con_hoscrdy(rcu) == 0); /* Wait for HOSCRDY = 1 (HOSC is ready)*/ + + + if (RCU->CON & RCU_CON_LRCON_MSK) /* if LRC enbale */ + while (md_rcu_get_con_lrcrdy(rcu) == 0); /* Wait for LRCRDY = 1 (LRC is ready)*/ + + + if (RCU->CON & RCU_CON_LOSCON_MSK) /* if LOSC enbale */ + while (md_rcu_get_con_loscrdy(rcu) == 0); /* Wait for LOSCRDY = 1 (LOSC is ready)*/ + + if (RCU->CON & RCU_CON_PLL0ON_MSK) /* if PLL enbale */ + while (md_rcu_get_con_pll0rdy(rcu) == 0); /* Wait for PLLRDY = 1 (PLL is ready)*/ + + + + /* PLL Reference Clock Source*/ + if (md_rcu_get_cfg_pllsrc(rcu)) + PLL0Frequency = (uint32_t)(__HOSC / (md_rcu_get_cfg_pllsrc(rcu) + 1)); + else + PLL0Frequency = (uint32_t)(__HRC); + + /* System Frequency */ + switch (md_rcu_get_cfg_sw(rcu)) /* System clock switch(SYSCLK) */ + { + case 0: /*================= HRC selected as system clock*/ + SystemCoreClock = (uint32_t)(__HRC); + break; + + case 1: /*================= HOSC selected as system clock*/ + SystemCoreClock = (uint32_t)(__HOSC); + break; + + case 2: /*================= LRC selected as system clock*/ + SystemCoreClock = (uint32_t)(__LRC); + break; + + case 3: /*================= LOSC selected as system clock*/ + SystemCoreClock = (uint32_t)(__LOSC); + break; + + case 4: /*================= PLL selected as system clock*/ + pllmux = md_rcu_get_cfg_pllmul(rcu) + 1; + + if (pllmux >= 18) pllmux = 18; + + SystemCoreClock = (uint32_t)(PLL0Frequency * pllmux); + break; + + default: + SystemCoreClock = (uint32_t)(__HRC); + break; + } + + /* Core Frequency */ + if (md_rcu_get_cfg_hpre(rcu)) + SystemFrequency_SysClk = SystemCoreClock >> ((md_rcu_get_cfg_hpre(rcu) & 0x07) + 1); + else + SystemFrequency_SysClk = SystemCoreClock; + + /* AHB Frequency */ + SystemFrequency_AHBClk = SystemFrequency_SysClk; + + /* APB Frequency */ + if (md_rcu_get_cfg_ppre(rcu)) + SystemFrequency_APBClk = SystemFrequency_SysClk >> ((md_rcu_get_cfg_ppre(rcu) & 0x03) + 1); + else + SystemFrequency_APBClk = SystemFrequency_SysClk; + + + if (SystemFrequency_AHBClk / 1000000 > 72) + md_fc_set_con_wait(3); + else if (SystemFrequency_AHBClk / 1000000 > 48) + md_fc_set_con_wait(2); + else if (SystemFrequency_AHBClk / 1000000 > 24) + md_fc_set_con_wait(1); + else + md_fc_set_con_wait(0); +} + + +/** + * @brief + * @param + * @retval None + */ +void md_rcu_pllreinit(uint8_t pllmul) +{ + md_rcu_set_cfg_pllmul(RCU, pllmul); + md_rcu_set_cfg_ckcfg(RCU); + + /* PLL Reference Clock Source */ + if (md_rcu_get_cfg_pllsrc(RCU)) + PLL0Frequency = (uint32_t)(__HOSC / (md_rcu_get_cfg_pllsrc(RCU) + 1)); + else + PLL0Frequency = (uint32_t)(__HRC); + + SystemCoreClock = (uint32_t)(PLL0Frequency * (pllmul + 1)); + + /* Core Frequency */ + if (md_rcu_get_cfg_hpre(RCU)) + SystemFrequency_SysClk = SystemCoreClock >> ((md_rcu_get_cfg_hpre(RCU) & 0x07) + 1); + else + SystemFrequency_SysClk = SystemCoreClock; + + /* AHB Frequency */ + SystemFrequency_AHBClk = SystemFrequency_SysClk; + + /* APB Frequency */ + if (md_rcu_get_cfg_ppre(RCU)) + SystemFrequency_APBClk = SystemFrequency_SysClk >> ((md_rcu_get_cfg_ppre(RCU) & 0x03) + 1); + else + SystemFrequency_APBClk = SystemFrequency_SysClk; + + md_fc_set_con_wait(3); + + if (SystemFrequency_AHBClk / 1000000 > 72) + md_fc_set_con_wait(3); + else if (SystemFrequency_AHBClk / 1000000 > 48) + md_fc_set_con_wait(2); + else if (SystemFrequency_AHBClk / 1000000 > 24) + md_fc_set_con_wait(1); + else + md_fc_set_con_wait(0); +} + +/** + * @} MD_RCU_PF_Init + */ + +/** + * @} MD_RCU_Public_Functions + */ + +/** + * @} RCU + */ + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_spi.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..c29bb54be6bb7d3f5b2a3fe7f903ef647b04f2f2 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_spi.c @@ -0,0 +1,108 @@ +/** + ****************************************************************************** + * @file md_spi.c + * @brief ES32F0271 I2C Source File. + * + * @version V1.00.01 + * @date 4/12/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_spi.h" +#include "md_rcu.h" +#include +#include "stdint.h" +/** @addtogroup Micro_Driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/** + * @brief Initialize the SPI registers according to the specified parameters in SPI_initStruct. + * @note The parameters in md_spi_init should be expected values. Otherwise, ERROR result will be returned. + * @param SPIx SPI Instance + * @param SPI_initStruct pointer to a @ref SPI_initStruct structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +void md_spi_struct_init(md_spi_inittypedef *SPI_initStruct) +{ + SPI_initStruct->Mode = MD_SPI_MODE_MASTER; + SPI_initStruct->ClockPhase = MD_SPI_PHASE_1EDGE; + SPI_initStruct->ClockPolarity = MD_SPI_POLARITY_LOW; + SPI_initStruct->BaudRate = MD_SPI_BAUDRATEPRESCALER_DIV256; + SPI_initStruct->BitOrder = MD_SPI_MSB_FIRST; + SPI_initStruct->TransferDirection = MD_SPI_FULL_DUPLEX; + SPI_initStruct->DataWidth = MD_SPI_FRAME_FORMAT_8BIT; + SPI_initStruct->CRCCalculation = MD_SPI_CRCCALCULATION_DISABLE; + SPI_initStruct->CRCPoly = 0x7; + SPI_initStruct->NSS = MD_SPI_NSS_HARD; +} + +/** + * @brief Initialize the SPI registers according to the specified parameters in SPI_initStruct. + * @note The parameters in md_i2c_init should be expected values. Otherwise, ERROR result will be returned. + * @param SPIx SPI Instance + * @param SPI_initStruct pointer to a @ref SPI_initStruct structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus md_spi_init(SPI_TypeDef *SPIx, md_spi_inittypedef *SPI_InitStruct) +{ + ErrorStatus status = ERROR; + + md_spi_disable_con1_spien(SPIx); + + md_spi_set_con1_mstren(SPIx, SPI_InitStruct->Mode); + md_spi_set_con1_cpha(SPIx, SPI_InitStruct->ClockPhase); + md_spi_set_con1_cpol(SPIx, SPI_InitStruct->ClockPolarity); + md_spi_set_con1_baud(SPIx, SPI_InitStruct->BaudRate); + md_spi_set_con1_lsbfirst(SPIx, SPI_InitStruct->BitOrder); + md_spi_set_con1_bidimode(SPIx, SPI_InitStruct->TransferDirection); + md_spi_set_con1_ssout(SPIx, SPI_InitStruct->NSS); + md_spi_enable_con2_ssoe(SPIx); + + md_spi_enable_con1_spien(SPIx); + + status = SUCCESS; + + return status; +} + +/** + * @brief use to receive single one byte data. + * @note SPI Slave receive data + * @param SPIx SPI Instance + */ +uint8_t SPISSingleRd(SPI_TypeDef *SPIx) +{ + while (md_spi_is_active_flag_stat_rxe(SPIx)); + + return (md_spi_recv_data8(SPIx)); +} + + +/** + * @brief use to send single one byte data. + * @note SPI receive data + * @param SPIx SPI Instance + * @param data SPI send one byte data. + */ +void SPISingleWr(SPI_TypeDef *SPIx, uint8_t data) +{ + while (md_spi_is_active_flag_stat_txf(SPIx)); + + md_spi_send_data8(SPIx, data); +} + +/** + * @} Micro_Driver + */ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_tick.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_tick.c new file mode 100644 index 0000000000000000000000000000000000000000..f1420c6eb3c39a20fb22fcf415eb9346c752b1a1 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_tick.c @@ -0,0 +1,207 @@ +/** + ****************************************************************************** + * @file md_tick.c + * @brief ES32F0271 TICK Source File. + * + * @version V1.00.01 + * @date day/mon/year + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ******************************************************************************* + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_rcu.h" +#include "md_tick.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (TICK) + +/** @addtogroup TICK TICK + * @brief TICK micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Private function prototypes ------------------------------------------------*/ + +#define HDIVON 0 + +/* Private variables ----------------------------------------------------------*/ +/** @defgroup MD_TICK_Private_Variables TICK Private Variables + * @{ + */ +static uint32_t TICKms; +static uint32_t TICK100us; +static uint32_t TICK10us; + +/** + * @} MD_TICK_Private_Variables + */ +/* Public functions -----------------------------------------------------------*/ +/** @defgroup MD_TICK_Public_Functions TICK Public Functions + * @{ + */ + +/** + * @brief Tick Initialization + * @note This function set the maximun load and enable TICK counter + * @note This function also calculate ms, 100us ans 10us counter + * @param None + * @retval None + */ +void md_tick_init(void) +{ +#if HDIVON + HDIV->DIVIDEND = SystemFrequency_SysClk; + HDIV->DIVISOR = 1000; + TICKms = HDIV->QUOTIENT; + HDIV->DIVISOR = 10000; + TICK100us = HDIV->QUOTIENT; + HDIV->DIVISOR = 100000; + TICK10us = HDIV->QUOTIENT; +#else + TICKms = SystemFrequency_SysClk / 1000; + TICK100us = SystemFrequency_SysClk / 10000; + TICK10us = SystemFrequency_SysClk / 100000; +#endif + + md_tick_set_rvr_reload((1 << 24) - 1); /* Maximun ReLoad */ + md_tick_set_cvr_current(0); /* Reset CVR */ + md_tick_set_csr_clksource(1); /* MCU Clock */ + md_tick_enable_csr_enable(); /* Counter Enable */ +} + +/** + * @brief Retrive the TICK counter and converted to millisecond + * @param None + * @retval The ms value converted by TICK counter + */ +uint32_t md_tick_get_mscnt(void) +{ +#if HDIVON + HDIV->DIVIDEND = md_tick_get_cvr_current(); + HDIV->DIVISOR = TICKms; + return (HDIV->QUOTIENT); +#else + return (md_tick_get_cvr_current() / TICKms); +#endif +} + +/** + * @brief Retrive the TICK counter and converted to 100 microseconds + * @param None + * @retval The 100 microseconds value converted by TICK counter + */ +uint32_t md_tick_get_100uscnt(void) +{ +#if HDIVON + HDIV->DIVIDEND = md_tick_get_cvr_current(); + HDIV->DIVISOR = TICK100us; + return (HDIV->QUOTIENT); +#else + return (md_tick_get_cvr_current() / TICK100us); +#endif +} + +/** + * @brief Retrive the TICK counter and converted to 10 microseconds + * @param None + * @retval The 10 microseconds value converted by TICK counter + */ +uint32_t md_tick_get_10uscnt(void) +{ +#if HDIVON + HDIV->DIVIDEND = md_tick_get_cvr_current(); + HDIV->DIVISOR = TICK10us; + return (HDIV->QUOTIENT); +#else + return (md_tick_get_cvr_current() / TICK10us); +#endif +} + +/** + * @brief Delay based on milliseconds + * @param Unit The number of ms in one delay period + * @param msCnt The counter of delay period + * @etVal None + */ +void md_tick_waitms(uint8_t Unit, uint16_t msCnt) +{ + uint32_t mstime; + + mstime = (1 << 24) - (Unit * TICKms); + + while (msCnt--) + { + md_tick_set_cvr_current((1 << 24) - 1); /* Reset CVR */ + + while (md_tick_get_cvr_current() > mstime); + } +} + +/** + * @brief Delay based on 100 microseconds + * @param Unit The number of 100 microseconds in one delay period + * @param msCnt The counter of delay period + * @etVal None + */ +void md_tick_wait100us(uint16_t Unit, uint16_t usCnt) +{ + uint32_t ustime; + + ustime = (1 << 24) - (Unit * TICK100us); + + while (usCnt--) + { + md_tick_set_cvr_current((1 << 24) - 1); /* Reset CVR */ + + while (md_tick_get_cvr_current() > ustime); + } +} + +/** + * @brief Delay based on 10 microseconds + * @param Unit The number of 10 microseconds in one delay period + * @param msCnt The counter of delay period + * @etVal None + */ +void md_tick_wait10us(uint16_t Unit, uint16_t usCnt) +{ + uint32_t ustime; + + ustime = (1 << 24) - (Unit * TICK10us); + + while (usCnt--) + { + md_tick_set_cvr_current((1 << 24) - 1); /* Reset CVR */ + + while (md_tick_get_cvr_current() > ustime); + } +} + + +/** + * @} MD_TICK_Public_Functions + */ + +/** + * @} TICK + */ +#endif + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_uart.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..5ec9ccf3af433c3a431c17d2b853d7ba9186c821 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_uart.c @@ -0,0 +1,127 @@ +/** + ****************************************************************************** + * @file md_uart.c + * @brief ES32F0271 UART Source File. + * + * @version V1.00.01 + * @date 04/12/2018 + * @author Eastsoft AE Team + * @note UART Public Functions + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Includes -------------------------------------------------------------------*/ +#include "system_es32f027x.h" +#include "md_uart.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief UART micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ + +/** @defgroup UART_PUB_FUNC UART Public Functions + * @brief UART Public Functions + * @{ + */ +/** + * @brief Set UART1 baudrate. + * @param UARTx UART Instance. + * @param Baudrate + * @retval None. + */ +void md_uart_set_baudrate(UART_TypeDef *UARTx, uint32_t baudrate) +{ + uint32_t brr; + brr = ((SystemFrequency_APBClk + (baudrate >> 1)) / baudrate); + md_uart_set_brr(UARTx, brr); +} + +/** + * @brief UART Initialization + * @param UART Init Structure + * @retval None + */ +void md_uart_init(UART_TypeDef *UARTx, md_uart_init_typedef *UART_InitStruct) +{ + /* Check the UART_InitStruct */ + assert_param((UART_InitStruct != NULL)); + + md_uart_set_baudrate(UARTx, MD_UART_BAUDRATE_115200); + md_uart_disable_lcon_txen(UARTx); + md_uart_disable_lcon_rxen(UARTx); + md_uart_set_lcon_dls(UARTx, UART_InitStruct->DataWidth); + md_uart_set_lcon_stop(UARTx, UART_InitStruct->StopBits); + md_uart_set_lcon_ps(UARTx, UART_InitStruct->Parity); + md_uart_enable_lcon_pe(UARTx); + md_uart_set_fcon_tfrst(UARTx); + md_uart_set_fcon_rfrst(UARTx); + md_uart_enable_lcon_txen(UARTx); + md_uart_enable_lcon_rxen(UARTx); +} + +/** + * @brief UART1 send character + * @param Character + * @retval None + */ +void md_uart_send(UART_TypeDef *UARTx, uint8_t ch) +{ + while (md_uart_is_active_flag_stat_tffull(UARTx)); // Tx FIFO full + + md_uart_send_txbuf(UART1, ch); // Sent byte +} + +/** + * @brief UART1 receive character. + * @param UART_TypeDef *UARTx. + * @retval unsigned char. + */ +uint8_t md_uart_recv(UART_TypeDef *UARTx) +{ + while (md_uart_is_active_flag_stat_rfempty(UART1)); // Rx FIFO empty + + return (md_uart_get_rxbuf(UART1)); +} + +/** + * @brief Get UARTx baudrate. + * @param UART_TypeDef *UARTx. + * @retval Baudrate. + */ +uint32_t md_uart_get_baudrate(UART_TypeDef *UARTx) +{ + uint32_t brr, baudrate; + + brr = md_uart_get_brr(UARTx); + baudrate = SystemFrequency_APBClk / brr; + return baudrate; +} + + +/** + * @} UART_PUB_FUNC UART Public Functions + */ + +/** + * @} UART + */ + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_usb.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_usb.c new file mode 100644 index 0000000000000000000000000000000000000000..b3ae9ce6d590ebdbb55254e57fcf4aa60fc623b5 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_usb.c @@ -0,0 +1,3804 @@ +/** + ************************************************************************************** + * @file md_usb.c + * @brief USB Source File of MD Library. + * @data 03/12/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +/* Incudes -------------------------------------------------------------------*/ +#include "es32f0271.h" +#include "stdint.h" +#include +#include "usblib\drivers\usb_lowlayer_api.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (USB) + +/** @defgroup USB USB + * @brief USB micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +#define INTERRUPT_MASK_HOST 0x7e +#define INTERRUPT_MASK_DEV 0x6f + +/* Private macros -------------------------------------------------------------*/ +/* Private function prototypes ------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ +/** @addtogroup USB_MD_Public_Functions USB Public Functions + * @{ + */ + +/** @addtogroup USB_MD_PF_SYS USB Public System Functions + * @{ + */ + +/** + * @brief Mask all interrupts except NMI and Hardfault. + * @param None. + * @retval None. + */ +void md_usb_system_int_disable(void) +{ + __set_PRIMASK(1); +} + +/** + * @brief Enable all interrupts. + * @param None. + * @retval None. + */ +void md_usb_system_int_enable(void) +{ + __set_PRIMASK(0); +} + +/** + * @brief Reconfig USB. + * + * This config USB clock to xx MHz as the default configuration. + * If user want to change the clock,just redefine the + * md_usb_re_config() function. + * @param Device Chose device is in device mode or host mode. + * @retval None. + */ +__weak void md_usb_re_config(bool Device) +{ + // + // Config FIFO size of endpoint 0. + // No configuration required for ES32F0271. + // + + // + // For ES32F0271,full-speed is supported in device mode, + // Both full-speeed and low-speed is supported in host mode. + // + if (Device == true) + { + // + // DP pin pull up, in full-speed mode. + // + USB->DPDMCTRL |= (0X01 << USB_DPDMCTL_DPPUD_POSS); + + // + // Enable CID hardware control. + // + USB->SWCID &= ~USB_SWCID_CIDCTRL_MSK; + } + else + { + // + // DM\DP pin pull down, in host mode. + // Connect USN PHY power. + // + USB->DPDMCTRL = (0X02 << USB_DPDMCTL_DPPUD_POSS) | + (0X02 << USB_DPDMCTL_DMPUD_POSS) | + (USB_DPDMCTL_PHYPWREN_MSK); + // + // Enable CID hardware control. + // + USB->SWCID &= ~USB_SWCID_HOST_MSK; + + // + // Enable CID hardware control. + // + USB->SWCID &= ~USB_SWCID_CIDCTRL_MSK; + } +} + +/** + * @brief Delay ticks ms. + * @param ticks The delay ticks. + * @retval None. + */ +__weak void md_usb_system_delayms(uint32_t ticks) +{ + +} + +/** + * @brief Disable systic. + * @param None. + * @retval None. + */ +void md_usb_systic_disable(void) +{ + SysTick->CTRL &= (~SysTick_CTRL_ENABLE_Msk); +} + +/** + * @brief Reset colck of USB controller. + * @param None. + * @retval None. + */ +void md_usb_controller_reset(void) +{ + RCU->AHBRST |= RCU_AHBRST_USBEN_MSK; + RCU->AHBRST &= ~RCU_AHBRST_USBEN_MSK; +} + +/** + * @brief Enable colck of USB controller. + * @param None. + * @retval None. + */ +void md_usb_controller_enable(void) +{ + RCU->AHBEN |= RCU_AHBEN_USBEN_MSK; +} + +/** + * @brief Disable colck of USB controller. + * @param None. + * @retval None. + */ +void md_usb_controller_disable(void) +{ + RCU->AHBEN &= ~RCU_AHBEN_USBEN_MSK; +} + +/** + * @brief Enable phy colck of USB controller. + * + * This function enables clock of USB.To use USB,first, + * open its clock,then enable USB peripheral by clock + * clock manage peripheral. + * + * @param None. + * @retval None. + */ +void md_usb_clk_phy_enable(void) +{ + // + // Make sure the PLL1 has not been enabled. + // + if ((RCU->CON & RCU_CON_PLL1RDY_MSK) + && (RCU->CON & RCU_CON_PLL1ON_MSK)) + { + return; + } + + // + //Open PLL1 and wait it is ready. + // + RCU->CON |= RCU_CON_PLL1ON_MSK; + + while ((RCU->CON & RCU_CON_PLL1RDY_MSK) == 0); +} + +/** + * @brief Disable phy colck of USB controller. + * @param None. + * @retval None. + */ +void md_usb_clk_phy_disable(void) +{ + // + // Close PLL1. + // + RCU->CON &= ~RCU_CON_PLL1ON_MSK; +} + +/** + * @brief Get the USB interrupt number of NVIC. + * @param None. + * @retval None. + */ +uint32_t md_usb_nvic_number_get(void) +{ + return (uint32_t)USB_IRQn; +} + +/** + * @brief Config the USB interrupt of NVIC. + * @note The default priority is 1. + * @param None. + * @retval None. + */ +__weak void md_usb_nvic_config(uint32_t NvicNum) +{ + NVIC_SetPriority((IRQn_Type)NvicNum, 1); +} + +/** + * @brief Enable the USB interrupt of NVIC. + * @param None. + * @retval None. + */ +void md_usb_nvic_enable(void) +{ + NVIC_EnableIRQ((IRQn_Type)USB_IRQn); +} + +/** + * @brief Disable the USB interrupt of NVIC. + * @param None. + * @retval None. + */ +void md_usb_nvic_disable(void) +{ + NVIC_DisableIRQ((IRQn_Type)USB_IRQn); +} + +/** + * @} USB_MD_PF_SYS + */ + +/** @addtogroup USB_MD_PF_BASIC USB Public Basic Functions + * @{ + */ + +/** + * @brief Handles the USB bus reset condition. + * + * When this function is called with the \e bStart parameter set to \b true, + * this function causes the start of a reset condition on the USB bus. + * The caller must then delay at least 20ms before calling this function + * again with the \e bStart parameter set to \b false. + * + * @param bStart specifies whether to start or stop signaling reset on the USB + * bus. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_reset(bool bStart) +{ + // + // Send a reset signal to the bus. + // + if (bStart) + { + USB->POWER |= USB_POWER_RESET_MSK; + } + else + { + USB->POWER &= ~USB_POWER_RESET_MSK; + } +} + +/** + * @brief Handles the USB bus resume condition. + * + * When in device mode, this function brings the USB controller out of the + * suspend state. This call must first be made with the \e bStart parameter + * set to \b true to start resume signaling. The device application must + * then delay at least 10ms but not more than 15ms before calling this + * function with the \e bStart parameter set to \b false. + * + * When in host mode, this function signals devices to leave the suspend + * state. This call must first be made with the \e bStart parameter set to + * \b true to start resume signaling. The host application must then delay + * at least 20ms before calling this function with the \e bStart parameter set + * to \b false. This action causes the controller to complete the resume + * signaling on the USB bus. + * + * @param bStart specifies if the USB controller is entering or leaving the + * resume signaling state. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_resume(bool bStart) +{ + // + // Send a resume signal to the bus. + // + if (bStart) + { + USB->POWER |= USB_POWER_RESUME_MSK; + } + else + { + USB->POWER &= ~USB_POWER_RESUME_MSK; + } +} + +/** + * @brief Puts the USB bus in a suspended state. + * + * When used in host mode, this function puts the USB bus in the suspended + * state. + * + * @note This function must only be called in host mode. + * @retval Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, + * \b USB_HIGH_SPEED, or \b USB_UNDEF_SPEED. + */ +void md_usb_hos_suspend(void) +{ + // + // Send the suspend signaling to the USB bus. + // + USB->POWER |= USB_POWER_SUSPEND_MSK; +} + +/** + * @brief Issues a request for a status IN transaction on endpoint zero. + * + * This function is used to cause a request for a status IN transaction from + * a device on endpoint zero. This function can only be used with endpoint + * zero as that is the only control endpoint that supports this ability. This + * function is used to complete the last phase of a control transaction to a + * device and an interrupt is signaled when the status packet has been + * received. + * + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_request_status(void) +{ + // + // Set the request for a status IN transaction. + // + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_REQPKT_MSK | USB_CSR0L_TXCSRL_STATUSPKT_MSK; +} + +/** + * @brief Schedules a request for an IN transaction on an endpoint in host mode. + * + * This function schedules a request for an IN transaction. When the USB + * device being communicated with responds with the data, the data can be + * retrieved by calling md_usb_hosdev_endpoint_data_get() or via a DMA + * transfer. + * + * @note This function must only be called in host mode and only for IN + * endpoints. + * @param ui32Endpoint is the endpoint to access. + * @retval None. + */ +void md_usb_hos_request_in(uint32_t ui32Endpoint) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + if (ui32Endpoint == USB_EP_0) + { + // + // Set the request for an IN transaction. + // + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_REQPKT_MSK; + } + else + { + // + // Set the request for an IN transaction. + // + USB->RXCSR1 |= USB_RXCSRL_REQPKT_MSK; + } +} + +/** + * @brief Clears a scheduled IN transaction for an endpoint in host mode. + * + * This function clears a previously scheduled IN transaction if it is still + * pending. This function is used to safely disable any scheduled IN + * transactions if the endpoint specified by \e ui32Endpoint is reconfigured + * for communications with other devices. + * + * @note This function must only be called in host mode and only for IN + * endpoints. + * @param ui32Endpoint is the endpoint to access. + * @retval None. + */ +void md_usb_hos_request_in_clear(uint32_t ui32Endpoint) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Set the request for an IN transaction. + // For es32f0271,setup packet is only supported by endpoint0. + // + USB->CSR0L_TXCSRL &= ~USB_CSR0L_TXCSRL_REQPKT_MSK; +} + +/** + * @brief Returns the current speed of the USB device connected. + * + * This function returns the current speed of the USB bus in host mode. + * + * @note This function must only be called in host mode. + * @retval Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, + * \b USB_HIGH_SPEED, or \b USB_UNDEF_SPEED. + */ +uint32_t md_usb_hos_speed_get(void) +{ + // + // If the Full Speed device bit is set, then this is a full speed device. + // + if (USB->DEVCTRL & USB_DEVCTRL_FSDEV_MSK) + { + return (USB_FULL_SPEED); + } + + // + // If the Low Speed device bit is set, then this is a low speed device. + // + if (USB->DEVCTRL & USB_DEVCTRL_LSDEV_MSK) + { + return (USB_LOW_SPEED); + } + + // + // The device speed is not known. + // + return (USB_UNDEF_SPEED); +} + +/** + * @brief Gets the current functional device address for an endpoint. + * + * This function returns the current functional address that an endpoint is + * using to communicate with a device. The \e ui32Flags parameter determines + * if the IN or OUT endpoint's device address is returned. + * + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags determines if this is an IN or an OUT endpoint. + * @note This function must only be called in host mode. + * @retval Returns the current function address being used by an endpoint. + */ +uint32_t md_usb_hos_addr_get(uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Because es32f0271 can not read device function address, + // the return value can always be 0. + // + + // + // See if the transmit or receive address is returned. + // + if (ui32Flags & USB_EP_HOST_OUT) + { + // + // Return this endpoint's transmit address. + // + return (USB->FADDR); + } + else + { + // + // Return this endpoint's receive address. + // + return (USB->FADDR); + } +} + +/** + * @brief Sets the functional address for the device that is connected to an + * endpoint in host mode. + * + * This function configures the functional address for a device that is using + * this endpoint for communication. This \e ui32Addr parameter is the address + * of the target device that this endpoint is communicating with. The + * \e ui32Flags parameter indicates if the IN or OUT endpoint is set. + * + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags determines if this is an IN or an OUT endpoint. + * @param ui32Addr is the functional address for the controller to use for + * this endpoint. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_addr_set(uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + +// USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // See if the transmit or receive address is set. + // + if (ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transmit address. + // + USB->FADDR = ui32Addr; + } + else + { + // + // Set the receive address. + // + USB->FADDR = ui32Addr; + } +} + +/** + * @brief Gets the current device hub address for this endpoint. + * + * This function returns the current hub address that an endpoint is using + * to communicate with a device. The \e ui32Flags parameter determines if the + * device address for the IN or OUT endpoint is returned. + * + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags determines if this is an IN or an OUT endpoint. + * @note This function must only be called in host mode. + * @retval None. + */ +uint32_t md_usb_hos_hub_addr_get(uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // es32f0271 does not support + // + return 0; +} + +/** + * @brief Sets the hub address for the device that is connected to an endpoint. + * + * This function configures the hub address for a device that is using this + * endpoint for communication. The \e ui32Flags parameter determines if the + * device address for the IN or the OUT endpoint is configured by this call + * and sets the speed of the downstream device. Valid values are one of + * \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with + * \b USB_EP_SPEED_LOW. + * + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags determines if this is an IN or an OUT endpoint. + * @param ui32Addr is the hub address and port for the device using this + * endpoint. The hub address must be defined in bits 0 through 6 with the + * port number in bits 8 through 14. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_hub_addr_set(uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags) +{ + // + // es32f0271 does not support + // +} + +/** + * @brief Get USB address. + * @param None. + * @retval USB address. + */ +uint8_t md_usb_dev_addr_get(void) +{ + return (USB->FADDR); +} + +/** + * @brief Set USB address. + * @param ui8Address USB address. + * @retval None. + */ +void md_usb_dev_addr_set(uint8_t ui8Address) +{ + USB->FADDR = ui8Address; +} + +/** + * @brief USB soft connect. + * @param None. + * @retval None. + */ +void md_usb_dev_connect(void) +{ + // + // Enable connection to the USB bus. + // + USB->DPDMCTRL |= USB_DPDMCTL_PHYPWREN_MSK; +} + +/** + * @brief USB soft disconnect. + * @param None. + * @retval None. + */ +void md_usb_dev_disconnect(void) +{ + // + // Disable connection to the USB bus. + // + USB->DPDMCTRL &= ~USB_DPDMCTL_PHYPWREN_MSK; +} + +/** + * @brief Returns the current speed of the USB device connected. + * + * This function returns the current speed of the USB bus in device mode. + * + * @note This function must only be called in device mode. + * @retval Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, + * \b USB_HIGH_SPEED, or \b USB_UNDEF_SPEED. + */ +uint32_t md_usb_dev_speed_get(void) +{ + if (USB->DPDMCTRL & USB_DPDMCTL_DPPUD_MSK) + return USB_FULL_SPEED; + else if (USB->DPDMCTRL & USB_DPDMCTL_DMPUD_MSK) + return USB_LOW_SPEED; + + return USB_UNDEF_SPEED; +} + +/** + * @brief Gets the current frame number. + * + * This function returns the last frame number received. + * + * @param None. + * @retval The last frame number received. + */ +uint32_t md_usb_hosdev_frame_get(void) +{ + uint8_t temp = USB->FRAME1 & 0xff; + return (temp | (uint32_t)((USB->FRAME2 & 0x07) << 8)); +} + +/** + * @brief Disables control interrupts on a specified USB controller. + * + * This function disables the control interrupts for the USB controller + * specified by the \e ui32Base parameter. The \e ui32Flags parameter + * specifies which control interrupts to disable. The flags passed in the + * \e ui32Flags parameters must be the definitions that start with + * \b USB_INTCTRL_* and not any other \b USB_INT flags. + * + * @param ui32IntFlags specifies which control interrupts to disable. + * @retval None. + */ +void md_usb_hosdev_int_disable(uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + assert_param((ui32IntFlags & ~(USB_INTCTRL_ALL)) == 0); + + // + // If any general interrupts were disabled then write the general interrupt + // settings out to the hardware. + // + if (ui32IntFlags & USB_INTCTRL_STATUS) + { + USB->IDR &= ~(ui32IntFlags & USB_INTCTRL_STATUS); + } +} + +/** + * @brief Enables control interrupts on a specified USB controller. + * + * This function Enables the control interrupts for the USB controller + * specified by the \e ui32Base parameter. The \e ui32Flags parameter + * specifies which control interrupts to disable. The flags passed in the + * \e ui32Flags parameters must be the definitions that start with + * \b USB_INTCTRL_* and not any other \b USB_INT flags. + * + * @param ui32IntFlags specifies which control interrupts to Enable. + * @retval None. + */ +void md_usb_hosdev_int_enable(uint32_t ui32IntFlags) +{ + // + // Check the arguments. + // + assert_param((ui32IntFlags & ~(USB_INTCTRL_ALL)) == 0); + + // + // If any general interrupts were disabled then write the general interrupt + // settings out to the hardware. + // + if (ui32IntFlags & USB_INTCTRL_STATUS) + { + USB->IER |= ui32IntFlags & USB_INTCTRL_STATUS; + } +} + +/** + * @brief Returns the control interrupt status on a specified USB controller. + * + * This function reads control interrupt status for a USB controller. This + * call returns the current status for control interrupts only, the endpoint + * interrupt status is retrieved by calling md_usb_hosdev_endpoint_int_status(). + * The bit values returned are compared against the \b USB_INTCTRL_* values. + * + * The following are the meanings of all \b USB_INCTRL_ flags and the modes + * for which they are valid. These values apply to any calls to + * md_usb_hosdev_int_status(), md_usb_hosdev_int_enable(), + * and md_usb_hosdev_int_disable(). + * Some of these flags are only valid in the following modes as indicated in + * the parentheses: Host, Device, and OTG. + * + * - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. + * - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). + * - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable + * (OTG Only). + * - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) + * - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) + * - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) + * - \b USB_INTCTRL_SOF - Start of Frame Detected. + * - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past + * the end of a frame (Host Only) + * - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) + * - \b USB_INTCTRL_RESUME - Resume signaling detected. + * - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device + * Only) + * - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed + * (OTG Only) + * - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) + * + * @param ui32IntFlags specifies which control interrupts to Enable. + * @note This call clears the source of all of the control status interrupts. + * @retval Returns the status of the control interrupts for a USB controller. + */ +uint32_t md_usb_hosdev_int_status(void) +{ + uint32_t ui32Status; + + // + // Get the general interrupt status, these bits go into the upper 8 bits + // of the returned value. + // + ui32Status = USB->RIF & 0x7F; + + // + // Clear all the general interrupt status. + // + USB->ICR = 0xff; + + // + // Return the combined interrupt status. + // + return (ui32Status); +} + +/** + * @brief Returns the current operating mode of the controller. + * + * This function returns the current operating mode on USB controllers with + * OTG or Dual mode functionality. + * + * For OTG controllers: + * + * The function returns one of the following values on OTG controllers: + * + * \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode + * on the A-side of the cable. + * + * \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode + * on the A-side of the cable. + * + * \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode + * on the B-side of the cable. + * + * \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode + * on the B-side of the cable. If an OTG session request is started with no + * cable in place, this mode is the default. + * + * \b USB_OTG_MODE_NONE indicates that the controller is not attempting to + * determine its role in the system. + * + * For Dual Mode controllers: + * + * The function returns one of the following values: + * + * \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host. + * + * \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device. + * + * \b USB_DUAL_MODE_NONE indicates that the controller is not active as + * either a host or device. + * + * @param None. + * @retval Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, + * \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, + * \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or + * \b USB_DUAL_MODE_NONE. + */ +uint32_t md_usb_hosdev_mode_get(void) +{ + // + // It will not be called for es32f0271,because OTG is not supported. + // + // Checks the current mode in the USB_O_DEVCTL and returns the current + // mode. + // + // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION + // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION + // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION | + // USB_DEVCTL_HOST + // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION + // USB_OTG_MODE_NONE: USB_DEVCTL_DEV + // + return (USB->DEVCTRL & (USB_DEVCTRL_HOST_MSK | USB_DEVCTRL_SESSION_MSK)); +} + +/** + * @brief Starts or ends a session. + * + * This function is used in OTG mode to start a session request or end a + * session. If the \e bStart parameter is set to \b true, then this function + * starts a session and if it is \b false it ends a session. + * + * @param bStart specifies if this call starts or ends a session. + * @retval None. + */ +void md_usb_otg_session_request(bool bStart) +{ + // + // Start or end the session as directed. + // + if (bStart) + { + USB->DEVCTRL |= USB_DEVCTRL_SESSION_MSK; + } + else + { + USB->DEVCTRL &= ~USB_DEVCTRL_SESSION_MSK; + } +} + +/** + * @brief Change the mode of the USB controller to host. + * + * This function changes the mode of the USB controller to host mode. + * + * @note This function must only be called on microcontrollers that support + * OTG operation. + * @param None. + * @retval None. + */ +void md_usb_force_host_mode(void) +{ + unsigned int i; + // + // Force host mode. + // + USB->SWCID &= ~USB_SWCID_HOST_MSK; + USB->SWCID |= USB_SWCID_CIDCTRL_MSK; + USB->DEVCTRL = USB_DEVCTRL_HOSTREQ_MSK; + + i = 20; + + while ((!(USB->DEVCTRL & USB_DEVCTRL_HOST_MSK)) && (i != 0)) + { + i--; + } +} + +/** + * @brief Change the mode of the USB controller to device. + * + * This function changes the mode of the USB controller to device mode. + * + * @note This function must only be called on microcontrollers that support + * OTG operation. + * @param None. + * @retval None. + */ +void md_usb_force_device_mode(void) +{ + // + // Force mode in OTG parts that support forcing USB controller mode. + // This bit is not writable in USB controllers that do not support + // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a + // force of device mode. + // + USB->SWCID |= USB_SWCID_HOST_MSK; + USB->SWCID |= USB_SWCID_CIDCTRL_MSK; +} + +/** + * @brief Change the mode of the USB controller to OTG. + * + * This function changes the mode of the USB controller to OTG mode. + * + * @note This function must only be called on microcontrollers that support + * OTG operation. + * @param None. + * @retval None. + */ +void md_usb_force_otg_mode(void) +{ + // + // Force mode in OTG parts that support forcing USB controller mode. + // This bit is not writable in USB controllers that do not support + // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a + // force of OTG mode. + // + USB->SWCID |= USB_SWCID_HOST_MSK; + USB->SWCID &= ~USB_SWCID_CIDCTRL_MSK; +} + +/** + * @brief Change the operating mode of the USB controller. + * + * This function changes the operating modes of the USB controller. When + * operating in full OTG mode, the USB controller uses the VBUS and ID pins to + * detect mode and voltage changes. While these pins are primarily used in + * OTG mode, they can also affect the operation of host and device modes. In + * device mode, the USB controller can be configured to monitor or ignore + * VBUS. Monitoring VBUS allows the controller to determine if it has been + * disconnected from the host. In host mode, the USB controller uses the + * VBUS pin to detect loss of VBUS caused by excessive power draw due to a + * drop in the VBUS voltage. This call takes the place of + * md_usb_force_host_mode(),md_usb_force_device_mode(), + * and md_usb_force_otg_mode(). + * The \e ui32Mode value should be one of the following values: + * + * - \b USB_MODE_OTG enables operating in full OTG mode, VBUS and ID are + * used by the controller. + * - \b USB_MODE_HOST enables operating only as a host with no monitoring of + * VBUS or ID pins. + * - \b USB_MODE_HOST_VBUS enables operating only as a host with monitoring of + * VBUS pin. This configuration enables detection of VBUS droop while still + * forcing host mode. + * - \b USB_MODE_DEVICE enables operating only as a device with no monitoring + * of VBUS or ID pins. + * - \b USB_MODE_DEVICE_VBUS enables operating only as a device with + * monitoring of VBUS pin. This configuration enables disconnect detection + * while still forcing device mode. + * + * @note Some of the options above are not available on some ES32 devices. + * Please check the data sheet to determine if the USB controller supports a + * particular mode. + * @param ui32Mode specifies the operating mode of the USB OTG pins. + * @retval None. + */ +void md_usb_mode_config(uint32_t ui32Mode) +{ + // + // It is not supported by es32f0271. + // +} + +/** + * @} USB_MD_PF_BASIC + */ + +/** @addtogroup USB_MD_PF_ENDPOINT USB Public Endpoint Functions + * @{ + */ + +/** + * @brief Sets the base configuration for a host endpoint. + * + * This function sets the basic configuration for the transmit or receive + * portion of an endpoint in host mode. The \e ui32Flags parameter determines + * some of the configuration while the other parameters provide the rest. The + * \e ui32Flags parameter determines whether this is an IN endpoint + * (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint + * (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed + * endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint + * (\b USB_EP_SPEED_LOW). + * + * The \b USB_EP_MODE_ flags control the type of the endpoint. + * - \b USB_EP_MODE_CTRL is a control endpoint. + * - \b USB_EP_MODE_ISOC is an isochronous endpoint. + * - \b USB_EP_MODE_BULK is a bulk endpoint. + * - \b USB_EP_MODE_INT is an interrupt endpoint. + * + * The \e ui32NAKPollInterval parameter has different meanings based on the + * \b USB_EP_MODE value and whether or not this call is being made for + * endpoint zero or another endpoint. For endpoint zero or any Bulk + * endpoints, this value always indicates the number of frames to allow a + * device to NAK before considering it a timeout. If this endpoint is an + * isochronous or interrupt endpoint, this value is the polling interval for + * this endpoint. + * + * For interrupt endpoints, the polling interval is the number of frames + * between interrupt IN requests to an endpoint and has a range of 1 to 255. + * For isochronous endpoints this value represents a polling interval of + * 2 ^ (\e ui32NAKPollInterval - 1) frames. When used as a NAK timeout, the + * \e ui32NAKPollInterval value specifies 2 ^ (\e ui32NAKPollInterval - 1) + * frames before issuing a time out. + * + * There are two special time out values that can be specified when setting + * the \e ui32NAKPollInterval value. The first is \b MAX_NAK_LIMIT, which is + * the maximum value that can be passed in this variable. The other is + * \b DISABLE_NAK_LIMIT, which indicates that there is no limit on the + * number of NAKs. + * + * The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the + * endpoint data FIFOs. The choice of the DMA mode depends on how the DMA + * controller is configured and how it is being used. See the ``Using USB + * with the DMA Controller'' or the ''Using the integrated USB DMA + * Controller'' section for more information on DMA configuration depending + * on the type of DMA that is supported by the USB controller. + * + * When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit + * is specified to cause the transmission of data on the USB bus to start + * as soon as the number of bytes specified by \e ui32MaxPayload has been + * written into the OUT FIFO for this endpoint. + * + * When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST + * bit can be specified to trigger the request for more data once the FIFO has + * been drained enough to fit \e ui32MaxPayload bytes. The + * \b USB_EP_AUTO_CLEAR bit can be used to clear the data packet ready flag + * automatically once the data has been read from the FIFO. If this option is + * not used, this flag must be manually cleared via a call to + * md_usb_dev_endpoint_status_clear() or md_usb_hos_endpoint_status_clear(). + * + * For interrupt endpoints in low or full speed mode, the polling interval + * (\e ui32NAKPollInterval) is the number of frames between interrupt IN + * requests to an endpoint and has a range of 1 to 255. For interrupt + * endpoints in high speed mode the polling interval is + * 2 ^ (\e ui32NAKPollInterval - 1) microframes between interrupt IN requests + * to an endpoint and has a range of 1 to 16. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags are the status bits that are cleared. + * @param ui32MaxPacketSize is the maximum payload for this endpoint. + * @param ui32NAKPollInterval is the either the NAK timeout limit or the + * polling interval, depending on the type of endpoint. + * @param ui32TargetEndpoint is the endpoint that the host endpoint is + * targeting. + * @param ui32Flags are used to configure other endpoint settings. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_endpoint_config_set(uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, + uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Endpoint zero is configured differently than the other endpoints, so see + // if this is endpoint zero. + // + if (ui32Endpoint == USB_EP_0) + { + // + // Set the NAK timeout. + // + USB->NAKLIMIT0_TXINTERVAL = (uint8_t)ui32NAKPollInterval; + + // + // Set the transfer type information. + // + + // + // Set the speed of this endpoint. + // + if (ui32Flags & USB_EP_SPEED_HIGH) + { + // + // es32f0271 does not support high sepeed + // + } + else if (ui32Flags & USB_EP_SPEED_FULL) + { + } + else + { + } + } + else + { + // + // Start with the target endpoint. + // + ui32Register = ui32TargetEndpoint; + + // + // Set the speed for the device using this endpoint. + // + if (ui32Flags & USB_EP_SPEED_HIGH) + { + // + // es32f0271 does not support high sepeed + // + } + else if (ui32Flags & USB_EP_SPEED_FULL) + { + + } + else + { + + } + + // + // Set the protocol for the device using this endpoint. + // + switch (ui32Flags & USB_EP_MODE_MASK) + { + // + // The bulk protocol is being used. + // + case USB_EP_MODE_BULK: + { + ui32Register |= 0x20; + break; + } + + // + // The isochronous protocol is being used. + // + case USB_EP_MODE_ISOC: + { + ui32Register |= 0x10; + break; + } + + // + // The interrupt protocol is being used. + // + case USB_EP_MODE_INT: + { + ui32Register |= 0x30; + break; + } + + // + // The control protocol is being used. + // + case USB_EP_MODE_CTRL: + { + ui32Register |= 0x00; + break; + } + } + + // + // See if the transmit or receive endpoint is being configured. + // + if (ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transfer type information. + // + USB->TXTYPE = ui32Register; + + // + // Set the NAK timeout or polling interval. + // + USB->NAKLIMIT0_TXINTERVAL = ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + USB->TXMAXP = ui32MaxPacketSize; + + // + // Set the transmit control value to zero. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been + // loaded into the FIFO. + // + if (ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_CSR0H_TXCSRH_AUTOSET_MSK; + } + +// // +// // Configure the DMA Mode. +// // +// if(ui32Flags & USB_EP_DMA_MODE_1) +// { +// ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; +// } +// else if(ui32Flags & USB_EP_DMA_MODE_0) +// { +// ui32Register |= USB_TXCSRH1_DMAEN; +// } + + // + // Write out the transmit control value. + // + USB->CSR0H_TXCSRH = (uint8_t)ui32Register; + } + else + { + // + // Set the transfer type information. + // + USB->RXTYPE = ui32Register; + + // + // Set the NAK timeout or polling interval. + // + USB->RXINTERVAL = ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + USB->RXMAXP = ui32MaxPacketSize; + + // + // Set the receive control value to zero. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if (ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register |= USB_RXCSRH_AUTOCLR_MSK; + } + + // + // Allow auto generation of DMA requests. + // + if (ui32Flags & USB_EP_AUTO_REQUEST) + { + ui32Register |= USB_RXCSRH_AUTOREQ_MSK; + } + +// // +// // Configure the DMA Mode. +// // +// if(ui32Flags & USB_EP_DMA_MODE_1) +// { +// ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; +// } +// else if(ui32Flags & USB_EP_DMA_MODE_0) +// { +// ui32Register |= USB_RXCSRH1_DMAEN; +// } + + // + // Write out the receive control value. + // + USB->RXCSR2 = (uint8_t)ui32Register; + + +// USB->RXFIFO1=0x18; //Start Address=0x18 +// USB->RXFIFO2=(3<<5); //Size=64, No Double-Packet Buffering +// USB->RXCSR1|=USB_RXCSRL_FLUSH_MSK; //Flush FIFO + } + } +} + +/** + * @brief Acknowledge that data was read from the specified endpoint's FIFO in host mode. + * + * This function acknowledges that the data was read from the endpoint's FIFO. + * This call is used if processing is required between reading the data and + * acknowledging that the data has been read. + * @param ui32Endpoint is the endpoint to access. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_endpoint_data_ack(uint32_t ui32Endpoint) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Clear RxPktRdy. + // + if (ui32Endpoint == USB_EP_0) + { + USB->CSR0L_TXCSRL &= ~USB_CSR0L_TXCSRL_RXRDY_MSK; + } + else + { + USB->RXCSR1 &= ~(USB_RXCSRL_RXRDY_MSK); + } +} + +/** + * @brief Sets the value data toggle on an endpoint in host mode. + * + * This function is used to force the state of the data toggle in host mode. + * If the value passed in the \e bDataToggle parameter is \b false, then the + * data toggle is set to the DATA0 state, and if it is \b true it is set to + * the DATA1 state. The \e ui32Flags parameter can be \b USB_EP_HOST_IN or + * \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The + * \e ui32Flags parameter is ignored for endpoint zero. + * @param ui32Endpoint is the endpoint to access. + * @param bDataToggle specifies whether to set the state to DATA0 or DATA1. + * @param ui32Flags specifies whether to set the IN or OUT endpoint. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_endpoint_data_toggle(uint32_t ui32Endpoint, + bool bDataToggle, uint32_t ui32Flags) +{ + // + // It is not supported by es32f0271. + // + UNUSED(ui32Endpoint); + UNUSED(bDataToggle); + UNUSED(ui32Flags); +} + +/** + * @brief Clears the status bits in this endpoint in host mode. + * + * This function clears the status of any bits that are passed in the + * \e ui32Flags parameter. The \e ui32Flags parameter can take the value + * returned from the md_usb_hosdev_endpoint_status() call. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags are the status bits that are cleared. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_endpoint_status_clear(uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Clear the specified flags for the endpoint. + // + if (ui32Endpoint == USB_EP_0) + { + USB->CSR0L_TXCSRL &= ~(ui32Flags & 0xff); + } + else + { + USB->CSR0L_TXCSRL &= ~(ui32Flags & 0xff); + USB->RXCSR1 &= ~((ui32Flags >> 16) & 0xff); + } +} + +/** + * @brief Changes the speed of the connection for a host endpoint. + * + * This function sets the USB speed for an IN or OUT endpoint in host mode. + * The \e ui32Flags parameter specifies the speed using one of the following + * values: \b USB_EP_SPEED_LOW, \b USB_EP_SPEED_FULL, or \b USB_EP_SPEED_HIGH. + * The \e ui32Flags parameter also specifies which direction is set by + * adding the logical OR in either \b USB_EP_HOST_IN or \b USB_EP_HOST_OUT. + * All other flags are ignored. This function is typically only used for + * endpoint 0, but could be used with other endpoints as well. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags are used to configure other endpoint settings. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_endpoint_speed(uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // For es32f0271,we can not config endpoint speed. + // + UNUSED(ui32Endpoint); + UNUSED(ui32Flags); +} + +/** + * @brief Enables or disables ping tokens for an endpoint using high-speed control + * transfers in host mode. + * + * This function configures the USB controller to either send or not send ping + * tokens during the data and status phase of high speed control transfers. + * The only supported value for \e ui32Endpoint is \b USB_EP_0 because all + * control transfers are handled using this endpoint. If the \e bEnable is + * \b true then ping tokens are enabled, if \b false then ping tokens are + * disabled. This must be used if the controller must support + * communications with devices that do not support ping tokens in high speed + * mode. + * @param ui32Endpoint specifies the endpoint to enable/disable ping tokens. + * @param bEnable specifies whether enable or disable ping tokens. + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_endpoint_ping(uint32_t ui32Endpoint, + bool bEnable) +{ + // + // It is not supported by es32f0271. + // + UNUSED(ui32Endpoint); + UNUSED(bEnable); +} + +/** + * @brief USB endpoint configuration. + * + * This function sets the basic configuration for an endpoint in device mode. + * Endpoint zero does not have a dynamic configuration, so this function + * must not be called for endpoint zero. The \e ui32Flags parameter + * determines some of the configuration while the other parameters provide the + * rest. + * + * When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be + * specified to cause the automatic transmission of data on the USB bus as + * soon as \e ui32MaxPacketSize bytes of data are written into the FIFO for + * this endpoint. This option is commonly used with DMA as no interaction + * is required to start the transmission of data. + * + * The \b USB_EP_MODE_ flags define what the type is for the specified endpoint. + * USB_EP_MODE_CTRL is a control endpoint. + * USB_EP_MODE_ISOC is an isochronous endpoint. + * USB_EP_MODE_BULK is a bulk endpoint. + * USB_EP_MODE_INT is an interrupt endpoint. + * + * When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is + * specified to trigger the request for more data once the FIFO has been + * drained enough to receive \e ui32MaxPacketSize more bytes of data. Also + * for OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the + * data packet ready flag automatically once the data has been read from the + * FIFO. If this option is not used, this flag must be manually cleared via a + * call to md_usb_dev_endpoint_status_clear(). Both of these settings can be + * used to remove the need for extra calls when using the controller with DMA. + * + * @param ui32Endpoint The USB endpoint. + * @param ui32MaxPacketSize is the maximum packet size for this endpoint. + * @param ui32Flags are used to configure other endpoint settings. + * @retval None. + */ +void md_usb_dev_endpoint_config_set(uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Determine if a transmit or receive endpoint is being configured. + // + if (ui32Flags & USB_EP_DEV_IN) /*IN*/ + { + // + // Set the max packet size. + // + USB->TXMAXP = ui32MaxPacketSize; + + // + // The transmit control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been loaded + // into the FIFO. + // + if (ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_CSR0H_TXCSRH_AUTOSET_MSK; + } + + // + // Configure the DMA mode. + // + /* es32f0271 does not support DMA */ + + // + // Enable isochronous mode if requested. + // + if ((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_CSR0H_TXCSRH_ISO_MSK; + } + + // + // Write the transmit control value. + // + USB->CSR0H_TXCSRH = (uint8_t)ui32Register; + + // + // Reset the Data toggle to zero. + // + USB->CSR0L_TXCSRL = USB_CSR0L_TXCSRL_CLRDATAT_MSK; + } + else /*OUT*/ + { + // + // Set the MaxPacketSize. + // + USB->RXMAXP = ui32MaxPacketSize; + + // + // The receive control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if (ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register = USB_RXCSRH_AUTOCLR_MSK; + } + +// // +// // Configure the DMA mode. +// // + +// // +// // If requested, disable NYET responses for high-speed bulk and +// // interrupt endpoints. +// // + /*es32f0271 does not support*/ + + // + // Enable isochronous mode if requested. + // + if ((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_RXCSRH_ISO_MSK; + } + + // + // Write the receive control value. + // + USB->RXCSR2 = ui32Register; + + // + // Reset the Data toggle to zero. + // + USB->RXCSR1 = USB_RXCSRL_CLRDT_MSK; + } +} + +/** + * @brief Gets the current configuration for an endpoint. + * + * This function returns the basic configuration for an endpoint in device + * mode. The values returned in \e *pui32MaxPacketSize and \e *pui32Flags are + * equivalent to the \e ui32MaxPacketSize and \e ui32Flags previously passed + * to md_usb_dev_endpoint_config_get() for this endpoint. + * + * @note This function must only be called in device mode. + * @param ui32Endpoint is the endpoint to access. + * @param pui32MaxPacketSize is a pointer which is written with the maximum + * packet size for this endpoint. + * @param pui32Flags is a pointer which is written with the current endpoint + * settings. On entry to the function, this pointer must contain either + * \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT + * endpoint is to be queried. + * @retval None. + */ +void md_usb_dev_endpoint_config_get(uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, + uint32_t *pui32Flags) +{ + uint32_t ui32Register; + + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Determine if a transmit or receive endpoint is being queried. + // + if (*pui32Flags & USB_EP_DEV_IN) + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_IN; + + // + // Get the maximum packet size. + // + *pui32MaxPacketSize = (uint32_t)USB->TXMAXP; + + // + // Get the current transmit control register value.` + // + ui32Register = (uint32_t)(USB->CSR0H_TXCSRH); + + // + // Are we allowing auto setting of TxPktRdy when max packet size has + // been loaded into the FIFO? + // + if (ui32Register & USB_CSR0H_TXCSRH_AUTOSET_MSK) + { + *pui32Flags |= USB_EP_AUTO_SET; + } + + // + // Get the DMA mode. + // + + // + // Are we in isochronous mode? + // + if (ui32Register & USB_CSR0H_TXCSRH_ISO_MSK) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode change. + // If they decode the returned mode, however, they may be in for + // a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } + else + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_OUT; + + // + // Get the MaxPacketSize. + // + *pui32MaxPacketSize = (uint32_t)USB->RXMAXP; + + // + // Get the current receive control register value. + // + ui32Register = (uint32_t)(USB->RXCSR2); + + // + // Are we allowing auto clearing of RxPktRdy when packet of size max + // packet has been unloaded from the FIFO? + // + if (ui32Register & USB_RXCSRH_AUTOCLR_MSK) + { + *pui32Flags |= USB_EP_AUTO_CLEAR; + } + + // + // Get the DMA mode. + // + + // + // Are we in isochronous mode? + // + if (ui32Register & USB_RXCSRH_ISO_MSK) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode change. + // If they decode the returned mode, however, they may be in for + // a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } +} + +/** + * @brief Acknowledge that data was read from the specified endpoint's FIFO in device + * mode. + * + * This function acknowledges that the data was read from the endpoint's FIFO. + * The \e bIsLastPacket parameter is set to a \b true value if this is the + * last in a series of data packets on endpoint zero. The \e bIsLastPacket + * parameter is not used for endpoints other than endpoint zero. This call + * can be used if processing is required between reading the data and + * acknowledging that the data has been read. + * @param ui32Endpoint is the endpoint to access. + * @param bIsLastPacket indicates if this packet is the last one. + * @note This function must only be called in device mode. + * @retval None. + */ +void md_usb_dev_endpoint_ack(uint32_t ui32Endpoint, + bool bIsLastPacket) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Determine which endpoint is being acked. + // + if (ui32Endpoint == USB_EP_0) + { + // + // Clear RxPktRdy, and optionally DataEnd, on endpoint zero. + // + USB->CSR0L_TXCSRL = USB_CSR0L_TXCSRL_RXRDYC_MSK | (bIsLastPacket ? USB_CSR0L_TXCSRL_DATAEND_MSK : 0); + } + else + { + // + // Clear RxPktRdy on all other endpoints. + // + USB->RXCSR1 &= ~USB_RXCSRL_RXRDY_MSK; + } +} + +/** + * @brief Stalls the specified endpoint in device mode. + * + * This function causes the endpoint number passed in to go into a stall + * condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the + * stall is issued on the IN portion of this endpoint. If the \e ui32Flags + * parameter is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion + * of this endpoint. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags specifies whether to stall the IN or OUT endpoint. + * @note This function must only be called in device mode. + * @retval None. + */ +void md_usb_dev_endpoint_stall(uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Determine how to stall this endpoint. + // + if (ui32Endpoint == USB_EP_0) + { + // + // Perform a stall on endpoint zero. + // + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_RXRDYC_MSK | USB_CSR0L_TXCSRL_STALL_MSK; + } + else if (ui32Flags == USB_EP_DEV_IN) + { + // + // Perform a stall on an IN endpoint. + // + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_STALL_MSK; + } + else + { + // + // Perform a stall on an OUT endpoint. + // + USB->RXCSR1 |= USB_RXCSRL_STALL_MSK; + } +} + +/** + * @brief Clears the stall condition on the specified endpoint in device mode. + * + * This function causes the endpoint number passed in to exit the stall + * condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the + * stall is cleared on the IN portion of this endpoint. If the \e ui32Flags + * parameter is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT + * portion of this endpoint. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags specifies whether to stall the IN or OUT endpoint. + * @note This function must only be called in device mode. + * @retval None. + */ +void md_usb_dev_endpoint_stall_clear(uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Determine how to clear the stall on this endpoint. + // + if (ui32Endpoint == USB_EP_0) + { + // + // Clear the stall on endpoint zero. + // + USB->CSR0L_TXCSRL &= ~USB_CSR0L_TXCSRL_STALLED_MSK; + } + else if (ui32Flags == USB_EP_DEV_IN) + { + // + // Clear the stall on an IN endpoint. + // + USB->CSR0L_TXCSRL &= ~(USB_CSR0L_TXCSRL_SENTSTALL_MSK | USB_CSR0L_TXCSRL_SENDSTALL_MSK); + + // + // Reset the data toggle. + // + /* @yuzr es32f0271 can not realize */ + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_CLRDATAT_MSK; + } + else + { + // + // Clear the stall on an OUT endpoint. + // +// HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= +// ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + USB->RXCSR1 &= ~(USB_RXCSRL_STALL_MSK | USB_RXCSRL_STALLED_MSK); + + // + // Reset the data toggle. + // + USB->RXCSR1 |= USB_RXCSRL_CLRDT_MSK; + } +} + +/** + * @brief Clears the status bits in this endpoint in device mode. + * + * This function clears the status of any bits that are passed in the + * \e ui32Flags parameter. The \e ui32Flags parameter can take the value + * returned from the USBEndpointStatus() call. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags are the status bits that are cleared. + * @note This function must only be called in device mode. + * @retval None. + */ +void md_usb_dev_endpoint_status_clear(uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // If this is endpoint 0, then the bits have different meaning and map + // into the TX memory location. + // + if (ui32Endpoint == USB_EP_0) + { + // + // Set the Serviced RxPktRdy bit to clear the RxPktRdy. + // + if (ui32Flags & USB_DEV_EP0_OUT_PKTRDY) + { + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_RXRDYC_MSK; + } + + // + // Set the serviced Setup End bit to clear the SetupEnd status. + // + if (ui32Flags & USB_DEV_EP0_SETUP_END) + { + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_SETENDC_MSK; + } + + // + // Clear the Sent Stall status flag. + // + if (ui32Flags & USB_DEV_EP0_SENT_STALL) + { + USB->CSR0L_TXCSRL &= ~(USB_CSR0L_TXCSRL_STALLED_MSK); + } + } + else + { + // + // Clear out any TX flags that were passed in. Only + // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN must be cleared. + // + USB->CSR0L_TXCSRL &= ~(ui32Flags & (USB_CSR0L_TXCSRL_STALL_MSK | USB_DEV_TX_UNDERRUN)); + + // + // Clear out valid RX flags that were passed in. Only + // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN + // must be cleared. + // + USB->RXCSR1 &= ~((ui32Flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR | + USB_DEV_RX_OVERRUN)) >> 16); + } +} + +/** + * @brief Determines the number of bytes of data available in a specified endpoint's + * FIFO. + * + * This function returns the number of bytes of data currently available in the + * FIFO for the specified receive (OUT) endpoint. It may be used prior to calling + * md_usb_hosdev_endpoint_data_get() to determine the size of buffer required to + * hold the newly-received packet. + * @param ui32Endpoint is the endpoint to access. + * @retval This call returns the number of bytes available in a specified endpoint + * FIFO. + */ +uint32_t md_usb_hosdev_endpoint_datavai(uint32_t ui32Endpoint) +{ + uint8_t temp; //use to clear warning in IAR system + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if (ui32Endpoint == USB_EP_0) + { + // + // Is there a packet ready in the FIFO? + // + if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_RXRDY_MSK) + { + // + // Return the byte count in the FIFO. + // + return (uint32_t)(USB->RXCOUNT1); + } + + return (0); + } + else + { + // + // Is there a packet ready in the FIFO? + // + if (USB->RXCSR1 & USB_RXCSRL_RXRDY_MSK) + { + // + // Return the byte count in the FIFO. + // + temp = USB->RXCOUNT1; + return (uint32_t)(temp | USB->RXCOUNT2 << 8); + } + + return (0); + } +} + +/** + * @brief Retrieves data from the specified endpoint's FIFO. + * + * This function returns the data from the FIFO for the specified endpoint. + * The \e pui32Size parameter indicates the size of the buffer passed in + * the \e pui32Data parameter. The data in the \e pui32Size parameter is + * changed to match the amount of data returned in the \e pui8Data parameter. + * If a zero-byte packet is received, this call does not return an error but + * instead just returns a zero in the \e pui32Size parameter. The only error + * case occurs when there is no data packet available. + * @param ui32Endpoint is the endpoint to access. + * @param pui8Data is a pointer to the data area used to return the data from + * the FIFO. + * @param pui32Size is initially the size of the buffer passed into this call + * via the \e pui8Data parameter. It is set to the amount of data returned in + * the buffer. + * @retval This call returns 0, or -1 if no packet was received. + */ +int32_t md_usb_hosdev_endpoint_data_get(uint32_t ui32Endpoint, + uint8_t *pui8Data, + uint32_t *pui32Size) +{ + uint32_t ui32ByteCount, ui32FIFO; + uint8_t temp; //use to clear warning in IAR system + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Don't allow reading of data if the RxPktRdy bit is not set. + // + if (ui32Endpoint == USB_EP_0) + { + if ((USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_RXRDY_MSK) == 0) + { + // + // Can't read the data because none is available. + // + *pui32Size = 0; + + // + // Return a failure since there is no data to read. + // + return (-1); + } + } + else + { + if ((USB->RXCSR1 & USB_RXCSRL_RXRDY_MSK) == 0) + { + // + // Can't read the data because none is available. + // + *pui32Size = 0; + + // + // Return a failure since there is no data to read. + // + return (-1); + } + } + + // + // Get the byte count in the FIFO. + // + if (ui32Endpoint == USB_EP_0) + { + ui32ByteCount = (uint32_t)(USB->RXCOUNT1); + } + else + { + temp = USB->RXCOUNT1; + ui32ByteCount = (uint32_t)(temp | (USB->RXCOUNT2 << 8)); + } + + // + // Determine how many bytes are copied. + // + ui32ByteCount = (ui32ByteCount < *pui32Size) ? ui32ByteCount : *pui32Size; + + // + // Return the number of bytes we are going to read. + // + *pui32Size = ui32ByteCount; + + // + // Calculate the FIFO address. + // + ui32FIFO = (uint32_t)(&USB->EP0FIFO) + 4 * (uint32_t)USBEPToIndex(ui32Endpoint); + + // + // Read the data out of the FIFO. + // + for (; ui32ByteCount > 0; ui32ByteCount--) + { + // + // Read a byte at a time from the FIFO. + // + *pui8Data++ = *((volatile uint8_t *)(ui32FIFO)); + } + + // + // Success. + // + return (0); +} + +/** + * @brief Puts data into the specified endpoint's FIFO. + * + * This function puts the data from the \e pui8Data parameter into the FIFO + * for this endpoint. If a packet is already pending for transmission, then + * this call does not put any of the data into the FIFO and returns -1. Care + * must be taken to not write more data than can fit into the FIFO + * allocated by the call to md_usb_dev_endpoint_config_set(). + * @param ui32Endpoint is the endpoint to access. + * @param pui8Data is a pointer to the data area used as the source for the + * data to put into the FIFO. + * @param ui32Size is the amount of data to put into the FIFO. + * @retval This call returns 0 on success, or -1 to indicate that the FIFO + * is in use and cannot be written. + */ +int32_t md_usb_hosdev_endpoint_data_put(uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t ui32Size) +{ + uint32_t ui32FIFO; + + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if (ui32Endpoint == USB_EP_0) + { + if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_TXRDY_MSK) + return (-1); + } + else + { + if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_TXPKTRDY_MSK) + return (-1); + } + + // + // Calculate the FIFO address. + // + ui32FIFO = (uint32_t)(&USB->EP0FIFO) + 4 * (uint32_t)USBEPToIndex(ui32Endpoint); + + // + // Write the data to the FIFO. + // + for (; ui32Size > 0; ui32Size--) + { + *((volatile uint8_t *)(ui32FIFO)) = *pui8Data++; + } + + // + // Success. + // + return (0); +} + +/** + * @brief Starts the transfer of data from an endpoint's FIFO. + * + * This function starts the transfer of data from the FIFO for a specified + * endpoint. This function is called if the \b USB_EP_AUTO_SET bit was + * not enabled for the endpoint. Setting the \e ui32TransType parameter + * allows the appropriate signaling on the USB bus for the type of transaction + * being requested. The \e ui32TransType parameter must be one of the + * following: + * + * - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode. + * - \b USB_TRANS_IN for IN transaction on any endpoint in device mode. + * - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a + * sequence of IN transactions. + * \b USB_TRANS_SETUP for setup transactions on endpoint zero. + * \b USB_TRANS_STATUS for status results on endpoint zero. + * @param ui32Endpoint is the endpoint to access. + * @param ui32TransType is set to indicate what type of data is being sent. + * @retval This call returns 0 on success, or -1 if a transmission is already + * in progress. + */ +int32_t md_usb_hosdev_endpoint_data_send(uint32_t ui32Endpoint, + uint32_t ui32TransType) +{ + uint32_t ui32TxPktRdy; + + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if (ui32Endpoint == USB_EP_0) + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_TXRDY_MSK) + { + return (-1); + } + + ui32TxPktRdy = ui32TransType & 0xff; + } + else + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_TXPKTRDY_MSK) + { + return (-1); + } + + ui32TxPktRdy = (ui32TransType >> 8) & 0xff; + } + + // + // Set TxPktRdy in order to send the data. + // + USB->CSR0L_TXCSRL = ui32TxPktRdy; + + // + // Success. + // + return (0); +} + +/** + * @brief Forces a flush of an endpoint's FIFO. + * + * This function forces the USB controller to flush out the data in the FIFO. + * The function can be called with either host or device controllers and + * requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT, + * \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags specifies if the IN or OUT endpoint is accessed. + * @retval None. + */ +void md_usb_hosdev_endpoint_data_togglec(uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + if (ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_CLRDATAT_MSK; + } + else + { + USB->RXCSR1 |= USB_RXCSRL_CLRDT_MSK; + } +} + +/** + * @brief Sets the number of packets to request when transferring multiple bulk + * packets. + * + * This function sets the number of consecutive bulk packets to request + * when transferring multiple bulk packets with DMA. + * + * @param ui32Endpoint is the endpoint to access. + * @param ui32Count is the number of packets to request. + * @retval None. + */ +void md_usb_hosdev_endpoint_pkcount_set(uint32_t ui32Endpoint, + uint32_t ui32Count) +{ + /* It's not supported by es32f0271 */ +} + +/** + * @brief Returns the current status of an endpoint. + * + * This function returns the status of a specified endpoint. If any of these + * status bits must be cleared, then the md_usb_dev_endpoint_status_clear() or the + * md_usb_hos_endpoint_status_clear() functions must be called. + * + * The following are the status flags for host mode: + * + * - \b USB_HOST_IN_PID_ERROR - PID error on the specified endpoint. + * - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request. + * - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint. + * - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN + * endpoint in Isochronous mode. + * - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than + * the specified timeout period. + * - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN + * endpoint. + * - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full. + * - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint. + * - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than + * the specified timeout period. + * - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT + * request. + * - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint. + * - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this + * OUT endpoint. + * - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty. + * - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not + * completed. + * - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the + * specified timeout period. + * - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on + * endpoint zero. + * - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an + * IN transaction. + * - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN + * transaction. + * + * The following are the status flags for device mode: + * + * - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint. + * - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT + * endpoint. + * - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO. + * - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full. + * - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT + * endpoint's FIFO. + * - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come. + * - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint. + * - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no + * data was ready. + * - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty. + * - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not + * completed. + * - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End + * condition was sent. + * - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero. + * - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not + * completed. + * - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint + * zero's OUT FIFO. + * + * @param The current status flags for the endpoint depending on mode. + * @retval None. + */ +uint32_t md_usb_hosdev_endpoint_status(uint32_t ui32Endpoint) +{ + uint32_t ui32Status; + + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Get the TX portion of the endpoint status. + // + ui32Status = USB->CSR0L_TXCSRL; + + // + // Get the RX portion of the endpoint status. + // Return zero if ui32Endpoint is equal to USB_EP_0. + // + ui32Status |= (((ui32Endpoint == USB_EP_0) ? 0x00 : USB->RXCSR1) << 16); + + // + // Return the endpoint status. + // + return (ui32Status); +} + +/** + * @brief Disables endpoint interrupts on a specified USB controller. + * + * This function disables endpoint interrupts for the USB controller specified + * by the \e ui32Base parameter. The \e ui32Flags parameter specifies which + * endpoint interrupts to disable. The flags passed in the \e ui32Flags + * parameters must be the definitions that start with \b USB_INTEP_* and not + * any other \b USB_INT flags. + * @param ui32IntFlags specifies which endpoint interrupts to disable. + * @retval None. + */ +void md_usb_hosdev_endpoint_int_disable(uint32_t ui32IntFlags) +{ + // + // If any transmit interrupts were disabled, then write the transmit + // interrupt settings out to the hardware. + // + USB->TXIER &= + ~(ui32IntFlags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); + + // + // If any receive interrupts were disabled, then write the receive + // interrupt settings out to the hardware. + // + USB->RXIER &= + ~((ui32IntFlags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> 16); +} + +/** + * @brief Enable endpoint interrupts on a specified USB controller. + * + * This function Enable endpoint interrupts for the USB controller specified + * by the \e ui32Base parameter. The \e ui32Flags parameter specifies which + * endpoint interrupts to disable. The flags passed in the \e ui32Flags + * parameters must be the definitions that start with \b USB_INTEP_* and not + * any other \b USB_INT flags. + * @param ui32IntFlags specifies which endpoint interrupts to Enable. + * @retval None. + */ +void md_usb_hosdev_endpoint_int_enable(uint32_t ui32IntFlags) +{ + // + // If any transmit interrupts were disabled, then write the transmit + // interrupt settings out to the hardware. + // + USB->TXIER |= + ui32IntFlags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0); + + // + // If any receive interrupts were disabled, then write the receive + // interrupt settings out to the hardware. + // + USB->RXIER |= + ((ui32IntFlags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> 16); +} + +/** + * @brief Returns the endpoint interrupt status on a specified USB controller. + * + * This function reads endpoint interrupt status for a USB controller. This + * call returns the current status for endpoint interrupts only, the control + * interrupt status is retrieved by calling md_usb_hosdev_int_status(). The bit + * values returned are compared against the \b USB_INTEP_* values. + * These values are grouped into classes for \b USB_INTEP_HOST_* and + * \b USB_INTEP_DEV_* values to handle both host and device modes with all + * endpoints. + * @param None. + * @note This call clears the source of all of the endpoint interrupts. + * @retval Returns the status of the endpoint interrupts for a USB controller. + */ +uint32_t md_usb_hosdev_endpoint_int_status(void) +{ + uint32_t ui32Status; + + // + // Get the transmit interrupt status. + // + ui32Status = USB->TXRIF; + ui32Status |= (USB->RXRIF << 16); + + // + // Clear the transmit interrupt status. + // + USB->TXICR = 0xff; + USB->RXICR = 0xff; + + // + // Return the combined interrupt status. + // + return (ui32Status); +} + +/** + * @brief Change the mode of the USB controller to OTG. + * + * This function changes the mode of the USB controller to OTG mode. + * + * @note This function must only be called on microcontrollers that support + * OTG operation. + * @param None. + * @retval None. + */ +uint32_t md_usb_endpoint_number_get(void) +{ + return 13; +} + +/** + * @} USB_MD_PF_ENDPOINT + */ + +/** @addtogroup USB_MD_PF_FIFO USB Public FIFO Functions + * @{ + */ + +/** + * @brief Returns the absolute FIFO address for a specified endpoint. + * + * This function returns the actual physical address of the FIFO. This + * address is needed when the USB is going to be used with the DMA + * controller and the source or destination address must be set to the + * physical FIFO address for a specified endpoint. This function can also be + * used to provide the physical address to manually read data from an + * endpoints FIFO. + * + * @param ui32Endpoint specifies which endpoint's FIFO address to return. + * @retval None. + */ +uint32_t md_usb_hosdev_fifo_addr_get(uint32_t ui32Endpoint) +{ + return (uint32_t)((uint32_t)(&USB->EP0FIFO) + ((uint32_t)USBEPToIndex(ui32Endpoint) << 2)); +} + +/** + * @brief Returns the FIFO configuration for an endpoint. + * + * This function returns the starting address and size of the FIFO for a + * specified endpoint. Endpoint zero does not have a dynamically configurable + * FIFO, so this function must not be called for endpoint zero. The + * \e ui32Flags parameter specifies whether the endpoint's OUT or IN FIFO must + * be read. If in host mode, the \e ui32Flags parameter must be + * \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the + * \e ui32Flags parameter must be either \b USB_EP_DEV_OUT or + * \b USB_EP_DEV_IN. + * + * @param ui32Endpoint is the endpoint to access. + * @param ui32FIFOAddress is the starting address for the FIFO. + * @param ui32FIFOSize is the size of the FIFO specified by one of the + * USB_FIFO_SZ_ values. + * @param ui32Flags specifies what information to set in the FIFO + * configuration. + * @retval None. + */ +void md_usb_hosdev_fifo_config_get(uint32_t ui32Endpoint, uint32_t *pui32FIFOAddress, + uint32_t *pui32FIFOSize, uint32_t ui32Flags) +{ + uint8_t temp; //use to clear warning in IAR system + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // See if the transmit or receive FIFO is being configured. + // + if (ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + temp = USB->TXFIFO1 & 0xff; + // + // Get the transmit FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (temp | ((USB->TXFIFO2 & 0x0f) << 8)) << 3; + *pui32FIFOSize = (USB->TXFIFO2 & 0xe0) >> USB_TXFIFO2_MAXPKTSIZE_POSS; + } + else + { + temp = USB->RXFIFO1 & 0xff; + // + // Get the receive FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (temp | ((USB->TXFIFO2 & 0x0f) << 8)) << 3; + + *pui32FIFOSize = (USB->RXFIFO2 & 0xe0) >> USB_RXFIFO2_MAXPKTSIZE_POSS; + } +} + +/** + * @brief Sets the FIFO configuration for an endpoint. + * + * This function configures the starting FIFO RAM address and size of the FIFO + * for a specified endpoint. Endpoint zero does not have a dynamically + * configurable FIFO, so this function must not be called for endpoint zero. + * The \e ui32FIFOSize parameter must be one of the values in the + * \b USB_FIFO_SZ_ values. + * + * The \e ui32FIFOAddress value must be a multiple of 8 bytes and directly + * indicates the starting address in the USB controller's FIFO RAM. For + * example, a value of 64 indicates that the FIFO starts 64 bytes into + * the USB controller's FIFO memory. The \e ui32Flags value specifies whether + * the endpoint's OUT or IN FIFO must be configured. If in host mode, use + * \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use + * \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. + * + * @param ui32Endpoint is the endpoint to access. + * @param ui32FIFOAddress is the starting address for the FIFO. + * @param ui32FIFOSize is the size of the FIFO specified by one of the + * USB_FIFO_SZ_ values. + * @param ui32Flags specifies what information to set in the FIFO + * configuration. + * @retval None. + */ +void md_usb_hosdev_fifo_config_set(uint32_t ui32Endpoint, uint32_t ui32FIFOAddress, + uint32_t ui32FIFOSize, uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // See if the transmit or receive FIFO is being configured. + // + if (ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Set the transmit FIFO location and size for this endpoint. + // + USB->TXFIFO1 = (uint8_t)((ui32FIFOAddress & 0xffff) >> 3); + + USB->TXFIFO2 = (uint8_t)((((ui32FIFOAddress & 0xffff) >> 3 >> 8) & 0x0f) + | (ui32FIFOSize) << USB_TXFIFO2_MAXPKTSIZE_POSS); + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_FLUSHFIFO_MSK; + } + else + { + // + // Set the receive FIFO location and size for this endpoint. + // + USB->RXFIFO1 = (uint8_t)((ui32FIFOAddress & 0xffff) >> 3); + + USB->RXFIFO2 = (uint8_t)((((ui32FIFOAddress & 0xffff) >> 3 >> 8) & 0x0f) + | (ui32FIFOSize) << USB_RXFIFO2_MAXPKTSIZE_POSS); + USB->RXCSR1 |= USB_RXCSRL_FLUSH_MSK; + } +} + +/** + * @brief Forces a flush of an endpoint's FIFO. + * + * This function forces the USB controller to flush out the data in the FIFO. + * The function can be called with either host or device controllers and + * requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT, + * \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. + * + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags specifies if the IN or OUT endpoint is accessed. + * @retval None. + */ +void md_usb_hosdev_fifo_flush(uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Endpoint zero has a different register set for FIFO flushing. + // + if (ui32Endpoint == USB_EP_0) + { + // + // Nothing in the FIFO if neither of these bits are set. + // + if ((USB->CSR0L_TXCSRL + & (USB_CSR0L_TXCSRL_TXRDY_MSK | USB_CSR0L_TXCSRL_RXRDY_MSK)) != 0) + { + // + // Hit the Flush FIFO bit. + // + USB->CSR0H_TXCSRH |= USB_CSR0H_TXCSRH_FLUSH_MSK; + } + } + else + { + // + // Only reset the IN or OUT FIFO. + // + if (ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Make sure the FIFO is not empty. + // + if (USB->CSR0L_TXCSRL & USB_CSR0L_TXCSRL_TXPKTRDY_MSK) + { + // + // Hit the Flush FIFO bit. + // + USB->CSR0L_TXCSRL |= USB_CSR0L_TXCSRL_FLUSHFIFO_MSK; + } + } + else + { + // + // Make sure that the FIFO is not empty. + // + if (USB->RXCSR1 & USB_RXCSRL_RXRDY_MSK) + { + // + // Hit the Flush FIFO bit. + // + USB->RXCSR1 |= USB_RXCSRL_FLUSH_MSK; + } + } + } +} + +/** + * @} USB_MD_PF_FIFO + */ + + +/** @addtogroup USB_MD_PF_EXPWR USB Public External Power Functions + * @{ + */ + +// +// The following pwr function is not supported by es32f0271 +// +/** + * @brief Disables the external power pin. + * + * This function disables the USBnEPEN signal, which disables an external + * power supply in host mode operation. + * + * @note This function must only be called in host mode. + * @retval None. + */ +__weak void md_usb_hos_pwr_disable(void) +{ +} + +/** + * @brief Enable the external power pin. + * + * This function disables the USBnEPEN signal, which disables an external + * power supply in host mode operation. + * + * @note This function must only be called in host mode. + * @retval None. + */ +__weak void md_usb_hos_pwr_enable(void) +{ + // + // Although Vbus is not supported by es32f0271,we provide Vbus + // from outside. + // + +} + +/** + * @brief Sets the configuration for USB power fault. + * + * This function controls how the USB controller uses its external power + * control pins (USBnPFLT and USBnEPEN). The flags specify the power + * fault level sensitivity, the power fault action, and the power enable level + * and source. + * + * One of the following can be selected as the power fault level sensitivity: + * + * - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin + * being driven low. + * - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin + * being driven high. + * + * One of the following can be selected as the power fault action: + * + * - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault + * detected. + * - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a + * power fault. + * - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a + * power fault. + * - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a + * power fault. + * + * One of the following can be selected as the power enable level and source: + * + * - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller + * when USBHostPwrEnable() is called. + * - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB + * controller when USBHostPwrEnable() is + * called. + * - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller + * automatically if USBOTGSessionRequest() has + * enabled a session. + * - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB + * controller automatically if + * USBOTGSessionRequest() has enabled a + * session. + * + * When using the VBUS glitch filter, the \b USB_HOST_PWREN_FILTER can be + * addded to ignore small, short drops in VBUS level caused by high power + * consumption. This feature is mainly used to avoid causing VBUS errors + * caused by devices with high in-rush current. + * + * @note This function must only be called on microcontrollers that support + * host mode or OTG operation. The \b USB_HOST_PWREN_AUTOLOW and + * \b USB_HOST_PWREN_AUTOHIGH parameters can only be specified on devices that + * support OTG operation. + * @retval None. + */ +void md_usb_hos_pwr_config(uint32_t ui32Flags) +{ +} + +/** + * @brief Disable power fault detection. + * + * This function enables power fault detection in the USB controller. If the + * USBnPFLT pin is not in use, this function must not be used. + * + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_pwrfault_disable(void) +{ +} + +/** + * @brief Enable power fault detection. + * + * This function enables power fault detection in the USB controller. If the + * USBnPFLT pin is not in use, this function must not be used. + * + * @note This function must only be called in host mode. + * @retval None. + */ +void md_usb_hos_pwrfault_enable(void) +{ +} + +/** + * @} USB_MD_PF_EXPWR + */ + +/** @addtogroup USB_MD_PF_LPM USB Public LPM Functions + * @{ + */ + +// +// LPM is not supported by es32f0271 +// + +/** + * @brief Sends an LPM request to a device at a specified address and endpoint number. + * + * This function sends an LPM request to a connected device in host mode. + * The \e ui32Address parameter specifies the device address and has a range + * of values from 1 to 127. The \e ui32Endpoint parameter specifies the + * endpoint on the device to which to send the LPM request and must be one of + * the \b USB_EP_* values. The function returns before the LPM request is + * sent, requiring the caller to poll the md_usb_lpm_status() function or wait + * for an interrupt to signal completion of the LPM transaction. This + * function must only be called after the md_usb_hos_lpm_config() has configured + * the LPM transaction settings. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param ui32Address is the target device address for the LPM request. + * @param ui32Endpoint is the target endpoint for the LPM request. + * @retval None. + */ +void md_usb_hos_lpm_send(uint32_t ui32Address, + uint32_t uiEndpoint) +{ +} + +/** + * @brief Sets the global configuration for all LPM requests. + * + * This function sets the global configuration options for LPM transactions + * and must be called at least once before ever calling md_usb_hos_lpm_send(). The + * \e ui32ResumeTime specifies the length of time that the host drives resume + * signaling on the bus in microseconds. The valid values + * for \e ui32ResumeTime are from 50us to 1175us in 75us increments. The + * remaining configuration is specified by the \e ui32Config parameter and + * includes the following options: + * + * - \b USB_HOST_LPM_RMTWAKE allows the device to signal a remote wake from + * the LPM state. + * - \b USB_HOST_LPM_L1 is the LPM mode to enter and must always be included + * in the configuration. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param ui32Address is the target device address for the LPM request. + * @param ui32Endpoint is the target endpoint for the LPM request. + * @retval None. + */ +void md_usb_hos_lpm_config(uint32_t ui32ResumeTime, + uint32_t ui32Config) +{ +} + +/** + * @brief Returns if remote wake is currently enabled. + * + * This function returns the current state of the remote wake setting for host + * or device mode operation. If the controller is acting as a host this + * returns the current setting that is sent to devices when LPM requests are + * sent to a device. If the controller is in device mode, this function + * returns the state of the last LPM request sent from the host and indicates + * if the host enabled remote wakeup. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param None. + * @retval The \b true if remote wake is enabled or \b false if it is not. + */ +bool md_usb_lpm_remotewake_is_enabled(void) +{ + return 0; +} + +/** + * @brief Initiates resume signaling to wake a device from LPM suspend mode. + * + * In host mode, this function initiates resume signaling to wake a device + * that has entered an LPM-triggered low power mode. This LPM-triggered low + * power mode is entered when the md_usb_hos_lpm_send() is called to put a specific + * device into a low power state. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param None. + * @retval None. + */ +void md_usb_hos_lpm_resume(void) +{ +} + +/** + * @brief Initiates remote wake signaling to request the device to leave LPM + * suspend mode. + * + * This function initiates remote wake signaling to request that the host + * wake a device that has entered an LPM-triggered low power mode. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param None. + * @retval None. + */ +void md_usb_dev_lpm_remotewake(void) +{ +} + +/** + * @brief Configures the USB device mode response to LPM requests. + * + * This function sets the global configuration options for LPM + * transactions in device mode and must be called before ever calling + * md_usb_dev_lpm_enable() to set the configuration for LPM transactions. The + * configuration options in device mode are specified in the \e ui32Config + * parameter and include one of the following: + * + * - \b USB_DEV_LPM_NONE disables the USB controller from responding to LPM + * transactions. + * - \b USB_DEV_LPM_EN enables the USB controller to respond to LPM + * and extended transactions. + * - \b USB_DEV_LPM_EXTONLY enables the USB controller to respond to + * extended transactions, but not LPM transactions. + * + * The \e ui32Config option can also optionally include the + * \b USB_DEV_LPM_NAK value to cause the USB controller to NAK all + * transactions other than an LPM transaction once the USB controller is in + * LPM suspend mode. If this value is not included in the \e ui32Config + * parameter, the USB controller does not respond in suspend mode. + * + * The USB controller does not enter LPM suspend mode until the application + * calls the md_usb_dev_lpm_enable() function. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param ui32Config is the combination of configuration options for LPM + * transactions in device mode. + * @retval None. + */ +void md_usb_dev_lpm_config(uint32_t ui32Config) +{ +} + +/** + * @brief Enables the USB controller to respond to LPM suspend requests. + * + * This function is used to automatically respond to an LPM sleep request from + * the USB host controller. If there is no data pending in any transmit + * FIFOs, then the USB controller acknowledges the packet and enters the + * LPM L1 state and generates the \b USB_INTLPM_ACK interrupt. If the USB + * controller has pending transmit data in at least one FIFO, then the USB + * controller responds with NYET and signals the \b USB_INTLPM_INCOMPLETE or + * \b USB_INTLPM_NYET depending on if data is pending in receive or transmit + * FIFOs. A call to md_usb_dev_lpm_enable() is required after every + * LPM resume event to re-enable LPM mode. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param None. + * @retval None. + */ +void md_usb_dev_lpm_enable(void) +{ +} + +/** + * @brief Disables the USB controller to respond to LPM suspend requests. + * + * This function disables the USB controller from responding to LPM + * transactions. When the device enters LPM L1 mode, the USB controller + * automatically disables responding to further LPM transactions. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param None. + * @retval None. + */ +void md_usb_dev_lpm_disable(void) +{ +} + +/** + * @brief Returns the current link state setting. + * + * This function returns the current link state setting for the USB + * controller. When the controller is operating as a host, this link + * state is sent with an LPM request. When the controller is acting + * as a device, this link state was received by the last LPM transaction + * whether it was acknowledged or stalled because the requested + * LPM mode is not supported. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param None. + * @retval The current LPM link state. + */ +uint32_t md_usb_lpm_link_state_get(void) +{ + return 0; +} + +/** + * @brief Returns the current LPM endpoint value. + * + * This function returns the current LPM endpoint value. The meaning of the + * value depends on the mode of operation of the USB controller. When in + * device mode, the value returned is the endpoint that received the last + * LPM transaction. When in host mode this is the endpoint that was last + * sent an LPM transaction, or the endpoint that is configured to be sent when + * the LPM transaction is triggered. The value returned is in the + * \b USB_EP_[0-7] value and a direct endpoint index. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param None. + * @retval The last endpoint to receive an LPM request in device mode or the + * endpoint that the host sends an LPM request as one of the \b USB_EP_[0-7] + * values. + */ +uint32_t md_usb_lpm_endpoint_get(void) +{ + return 0; +} + +/** + * @brief Returns the current LPM interrupt status. + * + * This function returns the current LPM interrupt status for the USB + * controller. + * + * The valid interrupt status bits when the USB controller is acting as a host + * are the following: + * + * - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM + * transaction. + * - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low + * power state. + * - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout + * occurred or there were bit errors in the response for three attempts. + * - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. + * - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM + * transaction. + * - \b USB_INTLPM_STALL the device has stalled an LPM transaction. + * + * The valid interrupt status bits when the USB controller is acting as a + * device are the following: + * + * - \b USB_INTLPM_ERROR an LPM transaction was received that has an + * unsupported link state field. The transaction was stalled, but the + * requested link state can still be read using the md_usb_lpm_link_state_get() + * function. + * - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low + * power state. + * - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM + * transaction with a NYET because data was still in the transmit FIFOs. + * - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and + * is now in the LPM suspend mode. + * - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction + * with a NYET because LPM transactions are not yet enabled by a call to + * md_usb_dev_lpm_enable(). + * - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM + * transaction. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param None. + * @retval The \b true if remote wake is enabled or \b false if it is not. + */ +uint32_t md_usb_lpm_status(void) +{ + return 0; +} + +/** + * @brief Enables LPM interrupts. + * + * This function enables a set of LPM interrupts so that they can trigger a + * USB interrupt. The \e ui32Ints parameter specifies which of the + * \b USB_INTLPM_* to enable. + * + * The valid interrupt status bits when the USB controller is acting as a host + * are the following: + * + * - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM + * transaction. + * - \b USB_INTLPM_RESUME the USB controller has resumed from LPM low power + * state. + * - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout + * occurred or there were bit errors in the response for three attempts. + * - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. + * - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM + * transaction. + * - \b USB_INTLPM_STALL the device has stalled an LPM transaction. + * + * The valid interrupt status bits when the USB controller is acting as a + * device are the following: + * + * - \b USB_INTLPM_ERROR an LPM transaction was received that has an + * unsupported link state field. The transaction was stalled, but the + * requested link state can still be read using the md_usb_lpm_link_state_get() + * function. + * - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low + * power state. + * - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM + * transaction with a NYET because data was still in the transmit FIFOs. + * - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and + * is now in the LPM suspend mode. + * - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction + * with a NYET because LPM transactions are not yet enabled by a call to + * md_usb_dev_lpm_enable(). + * - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM + * transaction. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param ui32Ints specifies which LPM interrupts to enable. + * @retval None. + */ +void md_usb_lpm_int_enable(uint32_t ui32Ints) +{ +} + +/** + * @brief Disables LPM interrupts. + * + * This function disables the LPM interrupts specified in the \e ui32Ints + * parameter, preventing them from triggering a USB interrupt. + * + * The valid interrupt status bits when the USB controller is acting as a host + * are the following: + * + * - \b USB_INTLPM_ERROR a bus error occurred in the transmission of an LPM + * transaction. + * - \b USB_INTLPM_RESUME the USB controller has resumed from LPM low power + * state. + * - \b USB_INTLPM_INCOMPLETE the LPM transaction failed because a timeout + * occurred or there were bit errors in the response for three attempts. + * - \b USB_INTLPM_ACK the device has acknowledged an LPM transaction. + * - \b USB_INTLPM_NYET the device has responded with a NYET to an LPM + * transaction. + * - \b USB_INTLPM_STALL the device has stalled an LPM transaction. + * + * The valid interrupt status bits when the USB controller is acting as a + * device are the following: + * + * - \b USB_INTLPM_ERROR an LPM transaction was received that has an + * unsupported link state field. The transaction was stalled, but the + * requested link state can still be read using the md_usb_lpm_link_state_get() + * function. + * - \b USB_INTLPM_RESUME the USB controller has resumed from the LPM low + * power state. + * - \b USB_INTLPM_INCOMPLETE the USB controller responded to an LPM + * transaction with a NYET because data was still in the transmit FIFOs. + * - \b USB_INTLPM_ACK the USB controller acknowledged an LPM transaction and + * is now in the LPM suspend mode. + * - \b USB_INTLPM_NYET the USB controller responded to an LPM transaction + * with a NYET because LPM transactions are not yet enabled by a call to + * md_usb_dev_lpm_enable(). + * - \b USB_INTLPM_STALL the USB controller has stalled an incoming LPM + * transaction. + * + * @note This function must only be called in host mode. The USB LPM feature + * is not available on all ES32 devices. Please consult the data sheet for + * the ES32 device that you are using to determine if this feature is + * available. + * @param ui32Ints specifies which LPM interrupts to disable. + * @retval None. + */ +void md_usb_lpm_int_disable(uint32_t ui32Ints) +{ +} + +/** + * @} USB_MD_PF_LPM + */ + +/** @addtogroup USB_MD_PF_ULPI USB Public ULPI Functions + * @{ + */ + +// +// ULPI is not supported by es32f0271 +// + +/** + * @brief Configures the USB controller's ULPI function. + * + * This function is used to configure the USB controller's ULPI function. + * The configuration options are set in the \e ui32Config parameter and are a + * logical OR of the following values: + * + * - \b USB_ULPI_EXTVBUS enables the external ULPI PHY as the source for VBUS + * signaling. + * - \b USB_ULPI_EXTVBUS_IND enables the external ULPI PHY to detect external + * VBUS over-current condition. + * + * @note The USB ULPI feature is not available on all Tiva devices. + * Please consult the data sheet for the Tiva device that you + * are using to determine if this feature is available. + * @param ui32Config contains the configuration options. + * @retval None. + */ +void md_usb_ulpi_config(uint32_t ui32Config) +{ +} + +/** + * @brief Enables the USB controller's ULPI function. + * + * This function enables the USB controller's ULPI function and must be + * called before attempting to access an external ULPI-connected USB PHY. + * + * @note The USB ULPI feature is not available on all Tiva devices. + * Please consult the data sheet for the Tiva device that you + * are using to determine if this feature is available. + * @param None. + * @retval None. + */ +void md_usb_ulpi_enable(void) +{ +} + +/** + * @brief Disables the USB controller's ULPI function. + * + * This function Disables the USB controller's ULPI function and must be + * called before attempting to access an external ULPI-connected USB PHY. + * + * @note The USB ULPI feature is not available on all Tiva devices. + * Please consult the data sheet for the Tiva device that you + * are using to determine if this feature is available. + * @param None. + * @retval None. + */ +void md_usb_ulpi_disable(void) +{ +} + +/** + * @brief Disables the USB controller's ULPI function. + * + * This function Disables the USB controller's ULPI function and must be + * called before attempting to access an external ULPI-connected USB PHY. + * + * @note The USB ULPI feature is not available on all Tiva devices. + * Please consult the data sheet for the Tiva device that you + * are using to determine if this feature is available. + * @param None. + * @retval None. + */ +uint8_t md_usb_ulpi_reg_read(uint8_t ui8Reg) +{ + return 0; +} + +/** + * @brief Writes a value to a register on an external ULPI-connected USB PHY. + * + * This function writes the register address specified in the \e ui8Reg + * parameter with the value specified in the \e ui8Data parameter using the + * ULPI function. This function is blocking and only returns when the + * write access completes. The function does not return if there is not a + * ULPI-connected USB PHY present. + * + * @note The USB ULPI feature is not available on all Tiva devices. + * Please consult the data sheet for the Tiva device that you + * are using to determine if this feature is available. + * @param ui8Reg specifies the register address to write. + * @param ui8Data specifies the data to write. + * @retval None. + */ +void md_usb_ulpi_reg_write(uint8_t ui8Reg, + uint8_t ui8Data) +{ +} + +/** + * @} USB_MD_PF_ULPI + */ + +/** @addtogroup USB_MD_PF_DMA USB Public DMA Functions + * @{ + */ + +// +// USB DMA is not supported by es32f0271 +// + +/** + * @brief Sets the DMA channel to use for a specified endpoint. + * + * This function is used to configure which DMA channel to use with a specified + * endpoint. Receive DMA channels can only be used with receive endpoints + * and transmit DMA channels can only be used with transmit endpoints. + * + * @note This function only has an effect on microcontrollers that have the + * ability to change the DMA channel for an endpoint. Calling this function + * on other devices has no effect. + * @param ui32Endpoint specifies which endpoint's FIFO address to return. + * @param ui32Channel specifies which DMA channel to use for which endpoint. + * @retval None. + */ +void md_usb_dma_endpoint_channel_set(uint32_t ui32Endpoint, + uint32_t ui32Channel) +{ + // + // It is not supported by es32f0271 + // + return; +} + +/** + * @brief Enable DMA on a specified endpoint. + * + * This function enables DMA on a specified endpoint and configures the mode + * according to the values in the \e ui32Flags parameter. The \e ui32Flags + * parameter must have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. Once this + * function is called the only DMA or error interrupts are generated by the + * USB controller. + * + * @note This function only has an effect on microcontrollers that have the + * ability to change the DMA channel for an endpoint. Calling this function + * on other devices has no effect. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags specifies which direction and what mode to use when + * enabling DMA. + * @retval None. + */ +void md_usb_dma_endpoint_enable(uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // It is not supported by es32f0271 + // + return; +} + +/** + * @brief Disable DMA on a specified endpoint. + * + * This function disables DMA on a specified endpoint to allow non-DMA USB + * transactions to generate interrupts normally. The \e ui32Flags parameter + * must be \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored. + * + * @note This function only has an effect on microcontrollers that have the + * ability to change the DMA channel for an endpoint. Calling this function + * on other devices has no effect. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Flags specifies which direction to disable. + * @retval None. + */ +void md_usb_dma_endpoint_disable(uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // It is not supported by es32f0271 + // + return; +} + +/** + * @brief Configure the DMA settings for an endpoint. + * + * This function configures the DMA settings for a specified endpoint without + * changing other options that may already be configured. In order for the + * DMA transfer to be enabled, the md_usb_dma_endpoint_enable() function must be + * called before starting the DMA transfer. The configuration + * options are passed in the \e ui32Config parameter and can have the values + * described below. + * + * One of the following values to specify direction: + * - \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN - This setting is used with + * DMA transfers from memory to the USB controller. + * - \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT - This setting is used with + * DMA transfers from the USB controller to memory. + * + * One of the following values: + * - \b USB_EP_DMA_MODE_0(default) - This setting is typically used for + * transfers that do not span multiple packets or when interrupts are + * required for each packet. + * - \b USB_EP_DMA_MODE_1 - This setting is typically used for + * transfers that span multiple packets and do not require interrupts + * between packets. + * + * Values only used with \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN: + * - \b USB_EP_AUTO_SET - This setting is used to allow transmit DMA transfers + * to automatically be sent when a full packet is loaded into a FIFO. + * This is needed with \b USB_EP_DMA_MODE_1 to ensure that packets go + * out when the FIFO becomes full and the DMA has more data to send. + * + * Values only used with \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT: + * - \b USB_EP_AUTO_CLEAR - This setting is used to allow receive DMA + * transfers to automatically be acknowledged as they are received. This is + * needed with \b USB_EP_DMA_MODE_1 to ensure that packets continue to + * be received and acknowledged when the FIFO is emptied by the DMA + * transfer. + * + * Values only used with \b USB_EP_HOST_IN: + * - \b USB_EP_AUTO_REQUEST - This setting is used to allow receive DMA + * transfers to automatically request a new IN transaction when the + * previous transfer has emptied the FIFO. This is typically used in + * conjunction with \b USB_EP_AUTO_CLEAR so that receive DMA transfers + * can continue without interrupting the main processor. + * + * @note This function only has an effect on microcontrollers that have the + * ability to change the DMA channel for an endpoint. Calling this function + * on other devices has no effect. + * @param ui32Endpoint is the endpoint to access. + * @param ui32Config specifies the configuration options for an endpoint. + * @retval None. + */ +void md_usb_dma_endpoint_config(uint32_t ui32Endpoint, uint32_t ui32Config) +{ + // + //Chose endpoint. + // + USB->INDEX = (uint8_t)USBEPToIndex(ui32Endpoint); + + // + // Host out or device in. + // + if ((ui32Config & USB_EP_HOST_OUT) && (ui32Config & USB_EP_AUTO_SET)) + { + USB->CSR0H_TXCSRH |= USB_CSR0H_TXCSRH_AUTOSET_MSK; + } + else + { + if (ui32Config & USB_EP_AUTO_REQUEST) + { + USB->RXCSR2 |= USB_RXCSRH_AUTOREQ_MSK; + } + + if (ui32Config & USB_EP_AUTO_CLEAR) + { + USB->RXCSR2 |= USB_RXCSRH_AUTOCLR_MSK; + } + } +} + +/** + * @brief Assigns and configures an endpoint to a specified integrated USB DMA + * channel. + * + * This function assigns an endpoint and configures the settings for a + * USB DMA channel. The \e ui32Endpoint parameter is one of the + * \b USB_EP_* values and the \e ui32Channel value is a zero-based index of + * the DMA channel to configure. The \e ui32Config parameter is a combination + * of the \b USB_DMA_CFG_* values using the following guidelines. + * + * Use one of the following to set the DMA burst mode: + * - \b USB_DMA_CFG_BURST_NONE disables bursting. + * - \b USB_DMA_CFG_BURST_4 sets the DMA burst size to 4 words. + * - \b USB_DMA_CFG_BURST_8 sets the DMA burst size to 8 words. + * - \b USB_DMA_CFG_BURST_16 sets the DMA burst size to 16 words. + * + * Use one of the following to set the DMA mode: + * - \b USB_DMA_CFG_MODE_0 is typically used when only a single packet is + * being sent via DMA and triggers one completion interrupt per packet. + * - \b USB_DMA_CFG_MODE_1 is typically used when multiple packets are being + * sent via DMA and triggers one completion interrupt per transfer. + * + * Use one of the following to set the direction of the transfer: + * - \b USB_DMA_CFG_DIR_RX selects a DMA transfer from the endpoint to a + * memory location. + * - \b USB_DMA_CFG_DIR_TX selects a DMA transfer to the endpoint from a + * memory location. + * + * The following two optional settings allow an application to immediately + * enable the DMA transfer and/or DMA interrupts when configuring the DMA + * channel: + * - \b USB_DMA_CFG_INT_EN enables interrupts for this channel immediately so + * that an added call to md_usb_dma_channel_int_enable() is not necessary. + * - \b USB_DMA_CFG_EN enables the DMA channel immediately so that an added + * call to md_usb_dma_channel_enable() is not necessary. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller or if it must use the DMA controller for DMA transfers. + * @param ui32Channel specifies which DMA channel to access. + * @param ui32Endpoint is the endpoint to assign to the USB DMA channel. + * @param ui32Config is used to specify the configuration of the USB DMA channel. + * @retval None. + */ +void md_usb_dma_channel_config(uint32_t ui32Channel, + uint32_t ui32Endpoint, uint32_t ui32Config) +{ + // + // It is not supported by es32f0271 + // +} + +/** + * @brief Sets the source or destination address for an integrated USB DMA transfer + * on a specified channel. + * + * This function sets the source or destination address for the USB DMA + * channel number specified in the \e ui32Channel parameter. The + * \e ui32Channel value is a zero-based index of the USB DMA channel. The + * \e pvAddress parameter is a source address if the transfer type for the DMA + * channel is transmit and a destination address if the transfer type is + * receive. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller or if it must use the DMA controller for DMA transfers. + * @param ui32Channel specifies which DMA channel to access. + * @param pvAddress specifies the source or destination address for the USB + * DMA transfer. + * @retval None. + */ +void md_usb_dma_channel_address_set(uint32_t ui32Channel, + void *pvAddress) +{ + // + // It is not supported by es32f0271 + // + return; +} + +/** + * @brief Returns the source or destination address for the specified integrated USB + * DMA channel. + * + * This function returns the DMA address for the channel number specified + * in the \e ui32Channel parameter. The \e ui32Channel value is a zero-based + * index of the DMA channel to query. This function must not be used on + * devices that return \b USB_CONTROLLER_VER_0 from the USBControllerVersion() + * function. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller or if it must use the DMA controller for DMA transfers. + * @param ui32Channel specifies which DMA channel to access. + * @retval The current DMA address for a USB DMA channel. + */ +void *md_usb_dma_channel_address_get(uint32_t ui32Channel) +{ + // + // It is not supported by es32f0271 + // + return 0; +} + +/** + * @brief Sets the transfer count for an integrated USB DMA channel. + * + * This function sets the USB DMA transfer count in bytes for the channel + * number specified in the \e ui32Channel parameter. The \e ui32Channel + * value is a zero-based index of the DMA channel. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller or if it must use the DMA controller for DMA transfers. + * @param ui32Count specifies the number of bytes to transfer. + * @param ui32Channel specifies which DMA channel to access. + * @retval None. + */ +void md_usb_dma_channel_count_set(uint32_t ui32Count, + uint32_t ui32Channel) +{ + // + // It is not supported by es32f0271 + // + return; +} + +/** + * @brief Returns the transfer count for an integrated USB DMA channel. + * + * This function returns the USB DMA transfer count in bytes for the channel + * number specified in the \e ui32Channel parameter. The \e ui32Channel value + * is a zero-based index of the DMA channel to query. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller or if it must use the DMA controller for DMA transfers. + * @param ui32Channel specifies which DMA channel to access. + * @retval The current count for a USB DMA channel. + */ +uint32_t md_usb_dma_channel_count_get(uint32_t ui32Channel) +{ + // + // It is not supported by es32f0271 + // + return 0; +} + +/** + * @brief Returns the available number of integrated USB DMA channels. + * + * This function returns the total number of DMA channels available when using + * the integrated USB DMA controller. This function returns 0 if the + * integrated controller is not present. + * + * @note The number of integrated USB DMA channels or zero if the + * integrated USB DMA controller is not present. + * @param None. + * @retval The number of integrated USB DMA channels or zero if the + * integrated USB DMA controller is not present. + */ +uint32_t md_usb_dma_channel_number(void) +{ + // + // It is not supported by es32f0271 + // + return 0; +} + +/** + * @brief Enable interrupts for a specified integrated USB DMA channel. + * + * This function enables the USB DMA channel interrupt based on the + * \e ui32Channel parameter. The \e ui32Channel value is a zero-based + * index of the USB DMA channel. Once enabled, the md_usb_dma_channel_int_status() + * function returns if a DMA channel has generated an interrupt. + * + * @note The number of integrated USB DMA channels or zero if the + * integrated USB DMA controller is not present. + * @param ui32Channel specifies which DMA channel interrupt to enable. + * @retval None. + */ +void md_usb_dma_channel_int_enable(uint32_t ui32Channel) +{ + // + // It is not supported by es32f0271 + // +} + +/** + * @brief Return the current status of the integrated USB DMA interrupts. + * + * This function returns the current bit-mapped interrupt status for all USB + * DMA channel interrupt sources. Calling this function automatically clears + * all currently pending USB DMA interrupts. + * + * @param None. + * @retval None. + */ +uint32_t md_usb_dma_channel_int_status(void) +{ + return 0; +} + +/** + * @brief Enables USB DMA for a specified channel. + * + * This function enables the USB DMA channel passed in the \e ui32Channel + * parameter. The \e ui32Channel value is a zero-based index of the USB DMA + * channel. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller. + * @param ui32Channel specifies the USB DMA channel to enable. + * @retval None. + */ +void md_usb_dma_channel_enable(uint32_t ui32Channel) +{ + // + // DMA1 will be used by es32f0271 + // + SET_BIT(*(&DMA1->CSR0 + 4 * ui32Channel), DMA_CSR0_CHEN_MSK); +} + +/** + * @brief Disables USB DMA for a specified channel. + * + * This function Disables the USB DMA channel passed in the \e ui32Channel + * parameter. The \e ui32Channel value is a zero-based index of the USB DMA + * channel. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller. + * @param ui32Channel specifies the USB DMA channel to Disable. + * @retval None. + */ +void md_usb_dma_channel_disable(uint32_t ui32Channel) +{ + // + // DMA1 will be used by es32f0271 + // + CLEAR_BIT(*(&DMA1->CSR0 + 4 * ui32Channel), DMA_CSR0_CHEN_MSK); +} + +/** + * @brief Check if the USB channel is enabled. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller. + * @param ui32Channel specifies the USB DMA channel. + * @retval Return 1 if the channel is enabled. + */ +uint32_t md_usb_dma_channel_isenabled(uint32_t ui32Channel) +{ + if (*((uint32_t *)(&DMA1->CSR0 + ui32Channel * 4)) & DMA_CSR0_CHEN_MSK) + return 1; + + return 0; +} + +/** + * @brief Returns the current status for an integrated USB DMA channel. + * + * This function returns the current status for the USB DMA channel specified + * by the \e ui32Channel parameter. The \e ui32Channel value is a zero-based + * index of the USB DMA channel to query. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller or if it must use the DMA controller for DMA transfers. + * @param ui32Channel specifies the USB DMA channel to Disable. + * @retval Returns zero or \b USB_DMACTL0_ERR if there is a pending error + * condition on a DMA channel. + */ +uint32_t md_usb_dma_channel_status(uint32_t ui32Channel) +{ + // + // It is not supported by es32f0271 + // + return 0; +} + +/** + * @brief Clears the integrated USB DMA status for a specified channel. + * + * This function clears the USB DMA channel status for the channel specified + * by the \e ui32Channel parameter. The \e ui32Channel value is a zero-based + * index of the USB DMA channel to query. The \e ui32Status parameter + * specifies the status bits to clear and must be the valid values that are + * returned from a call to the md_usb_dma_channel_status() function. + * + * @note This feature is not available on all ES32 devices. Please + * check the data sheet to determine if the USB controller has a DMA + * controller or if it must use the DMA controller for DMA transfers. + * @param ui32Channel specifies the USB DMA channel to Disable. + * @retval None. + */ +void md_usb_dma_channel_status_clear(uint32_t ui32Channel, + uint32_t ui32Status) +{ + // + // It is not supported by es32f0271 + // +} + +/** + * @} USB_MD_PF_DMA + */ + +/** + * @} USB_MD_Public_Functions + */ + +/** + * @} USB + */ + +#endif + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics END OF MAIN.C****/ diff --git a/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_wwdt.c b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_wwdt.c new file mode 100644 index 0000000000000000000000000000000000000000..fdba390e172e688d9ddb0cb4acb7c82d3a5b8a9b --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/ES32F027x_MD_StdPeriph_Driver/Source/md_wwdt.c @@ -0,0 +1,86 @@ +/** + ****************************************************************************** + * @file md_wwdt.c + * @brief ES32F0271 WWDT Source File. + * + * @version V1.00.01 + * @date 4/12/2018 + * @author Eastsoft AE Team + * @note + * detailed description + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + ******************************************************************************* + */ + +/* Includes -------------------------------------------------------------------*/ +#include "md_rcu.h" +#include "md_wwdt.h" + +/** @addtogroup Micro_Driver + * @{ + */ + +#if defined (WWDT) + +/** @defgroup WWDT WWDT + * @brief WWDT micro driver + * @{ + */ + +/* Private types --------------------------------------------------------------*/ +/* Private variables ----------------------------------------------------------*/ +/* Private constants ----------------------------------------------------------*/ +/* Private macros -------------------------------------------------------------*/ + +/* Public functions -----------------------------------------------------------*/ +/** @addtogroup MD_RCU_Public_Functions RCU Public Functions + * @{ + */ +/** + * @brief De-initialize the GPIO registers to their default reset values. + * @param GPIOx GPIO Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are de-initialized + * - ERROR: GPIO registers are not de-initialized + */ +void md_wwdt_init(WWDT_TypeDef *WWD, md_wwdt_inittypedef *WWDT_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_MD_WWDT_ALL_INSTANCE(WWD)); + assert_param(IS_MD_WWDT_PRESCALER(WWDT_InitStruct->Prescaler)); + assert_param(IS_MD_WWDT_WINDOW(WWDT_InitStruct->Window)); + assert_param(IS_MD_WWDT_COUNTER(WWDT_InitStruct->Counter)); + assert_param(IS_MD_WWDT_EWI_MODE(WWDT_InitStruct->EWIMode)); + + if (WWDT_InitStruct->EWIMode == WWDT_EWI_ENABLE) + md_wwdt_enable_ier_ewis(WWD); + else + md_wwdt_disable_idr_ewis(WWD); + + md_wwdt_set_con_t(WWD, WWDT_InitStruct->Counter); + md_wwdt_set_cfg_wdgtb(WWD, WWDT_InitStruct->Prescaler); + md_wwdt_set_cfg_w(WWD, WWDT_InitStruct->Window); + md_wwdt_enable_con_wdga(WWD); +} + + + + + + + + + + + +/** + * @} GPIO + */ +#endif + +/** + * @} Micro_Driver + */ + +/******************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ diff --git a/bsp/essemi/es32f0271/libraries/SConscript b/bsp/essemi/es32f0271/libraries/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..00008f5fca116c0de9fb7f71ecf1407921c6a66a --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/SConscript @@ -0,0 +1,32 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = [] + +src += Glob('ES32F027x_MD_StdPeriph_Driver/Source/*.c') + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['CMSIS/Device/EastSoft/ES32F0271/Startup/gcc/startup_es32f027x.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['CMSIS/Device/EastSoft/ES32F0271/Startup/keil/startup_es32f027x.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['CMSIS/Device/EastSoft/ES32F0271/Startup/iar/startup_es32f027x.s'] + +src = src + ['CMSIS/Device/EastSoft/ES32F0271/System/system_es32f027x.c'] + +path = [cwd + '/CMSIS/Device/EastSoft/ES32F0271/Include', + cwd + '/CMSIS/Device/EastSoft/ES32F0271/Include/ES32F0271', + cwd + '/CMSIS/Device/EastSoft/ES32F0271/System', + cwd + '/CMSIS/Include', + cwd + '/', + cwd + '/ES32F027x_MD_StdPeriph_Driver/Include'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/essemi/es32f0271/libraries/usblib/drivers/type.h b/bsp/essemi/es32f0271/libraries/usblib/drivers/type.h new file mode 100644 index 0000000000000000000000000000000000000000..3d6a812bf64fa1302f7119e4e4a4cac5ccc397c2 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/usblib/drivers/type.h @@ -0,0 +1,41 @@ +/** + ************************************************************************************** + * @file type.h + * @brief Common types and macros. + * @data 12/21/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +#ifndef __TYPES_H__ +#define __TYPES_H__ + +//***************************************************************************** +// +// Macros for hardware access. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile uint32_t *)(x))) +#define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +#define HWREGB(x) \ + (*((volatile uint8_t *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ + (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ + (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \ + (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics Co., Ltd. *** END OF FILE ****/ diff --git a/bsp/essemi/es32f0271/libraries/usblib/drivers/usb_lowlayer_api.h b/bsp/essemi/es32f0271/libraries/usblib/drivers/usb_lowlayer_api.h new file mode 100644 index 0000000000000000000000000000000000000000..5fee2e973e81058f50820544c7793ccc47fa15e8 --- /dev/null +++ b/bsp/essemi/es32f0271/libraries/usblib/drivers/usb_lowlayer_api.h @@ -0,0 +1,728 @@ +/** + ************************************************************************************** + * @file usb_lowlayer_api.h + * @brief USB library lower layer api + * @data 11/9/2018 + * @author Eastsoft AE Team + * @note + * + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved. + * + ************************************************************************************** + */ + +/* Includes-------------------------------------------------------------------*/ +#include "stdint.h" +#include + +#ifndef __USB_LOWLAYER_API_H__ +#define __USB_LOWLAYER_API_H__ + + +/** + * If building with a C++ compiler, make all of the definitions in this header + * have a C binding. + */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Public constants -----------------------------------------------------------*/ + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hosdev_int_enable() and +// md_usb_hosdev_int_disable() as the ui32Flags parameter, and are returned from +// md_usb_hosdev_int_status(). +// +//***************************************************************************** +#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources +#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts +#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error +#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected +#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected +#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected +#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected +#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected +#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled +#define USB_INTCTRL_RESET 0x00000004 // Reset signaled +#define USB_INTCTRL_RESUME 0x00000002 // Resume detected +#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected +#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid +#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hosdev_endpoint_int_enable() +// and md_usb_hosdev_endpoint_int_disable() as the ui32Flags parameter, and +// are returned from md_usb_hosdev_endpoint_int_status(). +// +//***************************************************************************** +#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts +#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts +#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt +#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt +#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt +#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt +#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt +#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt +#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt +#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt +#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt +#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt +#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt +#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt +#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt +#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt +#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt + +#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts +#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt + +#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts +#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt + +#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts +#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt +#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt +#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt +#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt +#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt +#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt +#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt +#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt +#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt +#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt +#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt +#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt +#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt +#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt +#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt + +#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are values that are returned from md_usb_hos_speed_get() 0r +// md_usb_dev_speed_get(). +// +//***************************************************************************** +#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined +#define USB_HIGH_SPEED 0x00000002 // Current speed is High Speed +#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed +#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed + +//***************************************************************************** +// +// The following are values that are returned from md_usb_hosdev_endpoint_status(). The +// USB_HOST_* values are used when the USB controller is in host mode and the +// USB_DEV_* values are used when the USB controller is in device mode. +// +//***************************************************************************** +#define USB_HOST_IN_STATUS 0x114F0000 // Mask of all host IN interrupts +#define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received +#define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond +#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received +#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error +// (ISOC Mode) +#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the +// specified timeout period +#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a +// device +#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready +#define USB_HOST_OUT_STATUS 0x000000A7 // Mask of all host OUT interrupts +#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the +// specified timeout period +#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device +// (ISOC mode) +#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received +#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a +// device +#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty +#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted +#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the +// specified timeout period +#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet +#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a +// device +#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received +#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready +#define USB_DEV_RX_PID_ERROR 0x01000000 // PID error in isochronous +// transfer +#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint +#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data +#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to +// a full FIFO +#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready +#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data +// to come +#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint +#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready +#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty +#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted +#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before +// Data End seen +#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint +#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hos_endpoint_config_set() and +// md_usb_dev_endpoint_config_set() as the ui32Flags parameter. +// +//***************************************************************************** +#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled +#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled +#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled +#define USB_EP_DUAL_BUFFERING 0x00000008 // Dual buffering enabled +#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0 +#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1 +#define USB_EP_DIS_NYET 0x00000020 // Disable NYET response for +// high-speed Bulk and Interrupt +// endpoints in device mode. +#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint +#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint +#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint +#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint +#define USB_EP_MODE_MASK 0x00000300 // Mode Mask +#define USB_EP_SPEED_LOW 0x00000000 // Low Speed +#define USB_EP_SPEED_FULL 0x00001000 // Full Speed +#define USB_EP_SPEED_HIGH 0x00004000 // High Speed +#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint +#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint +#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint +#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hos_pwr_config() as the +// ui32Flags parameter. +// +//***************************************************************************** +#define USB_HOST_PWRFLT_LOW 0x00000010 +#define USB_HOST_PWRFLT_HIGH 0x00000030 +#define USB_HOST_PWRFLT_EP_NONE 0x00000000 +#define USB_HOST_PWRFLT_EP_TRI 0x00000140 +#define USB_HOST_PWRFLT_EP_LOW 0x00000240 +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 +#define USB_HOST_PWREN_MAN_LOW 0x00000000 +#define USB_HOST_PWREN_MAN_HIGH 0x00000001 +#define USB_HOST_PWREN_AUTOLOW 0x00000002 +#define USB_HOST_PWREN_AUTOHIGH 0x00000003 +#define USB_HOST_PWREN_FILTER 0x00010000 + +//***************************************************************************** +// +// The following are the valid values that can be passed to the +// md_usb_hos_lpm_config() function in the ui32Config parameter. +// +//***************************************************************************** +#define USB_HOST_LPM_RMTWAKE 0x00000100 +#define USB_HOST_LPM_L1 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that can be passed to the +// md_usb_dev_lpm_config() function in the ui32Config parameter. +// +//***************************************************************************** +#define USB_DEV_LPM_NAK 0x00000010 +#define USB_DEV_LPM_NONE 0x00000000 +#define USB_DEV_LPM_EN 0x0000000c +#define USB_DEV_LPM_EXTONLY 0x00000004 + +//***************************************************************************** +// +// The following are the valid values that are returned from the +// md_usb_lpm_link_state_get() function. +// +//***************************************************************************** +#define USB_DEV_LPM_LS_RMTWAKE 0x00000100 +#define USB_DEV_LPM_LS_L1 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that are passed to the md_usb_lpm_int_enable() +// or md_usb_lpm_int_disable() functions or are returned from the md_usb_lpm_status() +// function. +// +//***************************************************************************** +#define USB_INTLPM_ERROR 0x00000020 +#define USB_INTLPM_RESUME 0x00000010 +#define USB_INTLPM_INCOMPLETE 0x00000008 +#define USB_INTLPM_ACK 0x00000004 +#define USB_INTLPM_NYET 0x00000002 +#define USB_INTLPM_STALL 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that are passed to the md_usb_clock_enable() +// functions. +// +//***************************************************************************** +#define USB_CLOCK_INTERNAL 0x00000200 +#define USB_CLOCK_EXTERNAL 0x00000300 + +//***************************************************************************** +// +// The configuration options used with the md_usb_ulpi_config() API. +// +//***************************************************************************** +#define USB_ULPI_EXTVBUS 0x00000001 +#define USB_ULPI_EXTVBUS_IND 0x00000002 + +//***************************************************************************** +// +// The following are special values that can be passed to +// md_usb_hos_endpoint_config_set() as the ui32NAKPollInterval parameter. +// +//***************************************************************************** +#define MAX_NAK_LIMIT 31 // Maximum NAK interval +#define DISABLE_NAK_LIMIT 0 // No NAK timeouts + +//***************************************************************************** +// +// This value specifies the maximum size of transfers on endpoint 0 as 64 +// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. +// +//***************************************************************************** +#define MAX_PACKET_SIZE_EP0 64 + +//***************************************************************************** +// +// These values are used to indicate which endpoint to access. +// +//***************************************************************************** +#define USB_EP_0 0x00000000 // Endpoint 0 +#define USB_EP_1 0x00000010 // Endpoint 1 +#define USB_EP_2 0x00000020 // Endpoint 2 +#define USB_EP_3 0x00000030 // Endpoint 3 +#define USB_EP_4 0x00000040 // Endpoint 4 +#define USB_EP_5 0x00000050 // Endpoint 5 +#define USB_EP_6 0x00000060 // Endpoint 6 +#define USB_EP_7 0x00000070 // Endpoint 7 +#define NUM_USB_EP 8 // Number of supported endpoints + +//***************************************************************************** +// +// These macros allow conversion between 0-based endpoint indices and the +// USB_EP_x values required when calling various USB APIs. +// +//***************************************************************************** +#define IndexToUSBEP(x) ((x) << 4) +#define USBEPToIndex(x) ((x) >> 4) + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hosdev_fifo_config_set() as the +// ui32FIFOSize parameter. +// +//***************************************************************************** +#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO +#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO +#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO +#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO +#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO +#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO +#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO +#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO +#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO + +//***************************************************************************** +// +// This macro allow conversion from a FIFO size label as defined above to +// a number of bytes +// +//***************************************************************************** +#define USBFIFOSizeToBytes(x) (8 << (x)) + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_hosdev_endpoint_data_send() +// as the ui32TransType parameter. +// +//***************************************************************************** +#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction +#define USB_TRANS_IN 0x00000102 // Normal IN transaction +#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for +// endpoint 0 in device mode) +#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint +// 0) +#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint +// 0) + +//***************************************************************************** +// +// The following are values are returned by the md_usb_hosdev_mode_get() function. +// +//***************************************************************************** +#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host +// mode. +#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in +// Device mode. +#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not +// set. +#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of +// the cable. +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of +// the cable. +#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of +// the cable Session Valid. +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of +// the cable A valid. +#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of +// the cable. +#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of +// the cable. +#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of +// the cable. +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of +// the cable. +#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set. + +//***************************************************************************** +// +// Channel configuration values. +// +//***************************************************************************** +#define DMA_DST_INC_8 0x00000000 +#define DMA_DST_INC_16 0x40000000 +#define DMA_DST_INC_32 0x80000000 +#define DMA_DST_INC_NONE 0xc0000000 +#define DMA_SRC_INC_8 0x00000000 +#define DMA_SRC_INC_16 0x04000000 +#define DMA_SRC_INC_32 0x08000000 +#define DMA_SRC_INC_NONE 0x0c000000 +#define DMA_SIZE_8 0x00000000 +#define DMA_SIZE_16 0x11000000 +#define DMA_SIZE_32 0x22000000 +#define DMA_DST_PROT_PRIV 0x00200000 +#define DMA_SRC_PROT_PRIV 0x00040000 +#define DMA_ARB_1 0x00000000 +#define DMA_ARB_2 0x00004000 +#define DMA_ARB_4 0x00008000 +#define DMA_ARB_8 0x0000c000 +#define DMA_ARB_16 0x00010000 +#define DMA_ARB_32 0x00014000 +#define DMA_ARB_64 0x00018000 +#define DMA_ARB_128 0x0001c000 +#define DMA_ARB_256 0x00020000 +#define DMA_ARB_512 0x00024000 +#define DMA_ARB_1024 0x00028000 +#define DMA_NEXT_USEBURST 0x00000008 + +//***************************************************************************** +// +// The values for the md_usb_dma_channel_int_enable() and md_usb_dma_channel_int_status() +// APIs. +// +//***************************************************************************** +#define USB_DMA_INT_CH8 0x00000080 +#define USB_DMA_INT_CH7 0x00000040 +#define USB_DMA_INT_CH6 0x00000020 +#define USB_DMA_INT_CH5 0x00000010 +#define USB_DMA_INT_CH4 0x00000008 +#define USB_DMA_INT_CH3 0x00000004 +#define USB_DMA_INT_CH2 0x00000002 +#define USB_DMA_INT_CH1 0x00000001 + +//***************************************************************************** +// +// The values for the md_usb_dma_channel_status() API. +// +//***************************************************************************** +#define USB_DMA_STATUS_ERROR 0x00000100 + +//***************************************************************************** +// +// The valid return values for the USBDMAModeSet() and USBDMAModeGet() APIs or +// USBDMAChannelConfig(). +// +//***************************************************************************** +#define USB_DMA_CFG_BURST_NONE 0x00000000 +#define USB_DMA_CFG_BURST_4 0x00000200 +#define USB_DMA_CFG_BURST_8 0x00000400 +#define USB_DMA_CFG_BURST_16 0x00000600 +#define USB_DMA_CFG_INT_EN 0x00000008 +#define USB_DMA_CFG_MODE_0 0x00000000 +#define USB_DMA_CFG_MODE_1 0x00000004 +#define USB_DMA_CFG_DIR_RX 0x00000000 +#define USB_DMA_CFG_DIR_TX 0x00000002 +#define USB_DMA_CFG_EN 0x00000001 + +//***************************************************************************** +// +// The following are values that can be passed to md_usb_mode_config() as the +// ui3Mode parameter. +// +//***************************************************************************** +#define USB_MODE_HOST_VBUS 0x00000004 +#define USB_MODE_HOST 0x00000002 +#define USB_MODE_DEV_VBUS 0x00000005 +#define USB_MODE_DEV 0x00000003 +#define USB_MODE_OTG 0x00000000 + +//***************************************************************************** +// +// Flags that can be passed to DMAChannelAttributeEnable(), +// DMAChannelAttributeDisable(), and returned from DMAChannelAttributeGet(). +// +//***************************************************************************** +#define DMA_ATTR_USEBURST 0x00000001 +#define DMA_ATTR_ALTSELECT 0x00000002 +#define DMA_ATTR_HIGH_PRIORITY 0x00000004 +#define DMA_ATTR_REQMASK 0x00000008 +#define DMA_ATTR_ALL 0x0000000F + +/* Public functions -----------------------------------------------------------*/ +/** + * @{ SYSTEM API. + */ +extern void md_usb_system_int_disable(void); +extern void md_usb_system_int_enable(void); +extern void md_usb_re_config(bool Device); /* Weak defination */ +extern void md_usb_system_delayms(uint32_t delayms); /* Weak defination */ +extern void md_usb_systic_disable(void); +extern void md_usb_controller_reset(void); +extern void md_usb_controller_enable(void); +extern void md_usb_controller_disable(void); +extern void md_usb_clk_phy_enable(void); +extern void md_usb_clk_phy_disable(void); +extern uint32_t md_usb_nvic_number_get(void); +extern void md_usb_nvic_config(uint32_t NvicNum); /* Weak defination */ +extern void md_usb_nvic_enable(void); +extern void md_usb_nvic_disable(void); +/** + * @} SYSTEM API. + */ + +/** + * @{ USB basic API. + */ +/* Host Mode */ +extern void md_usb_hos_reset(bool bStart); +extern void md_usb_hos_resume(bool bStart); +extern void md_usb_hos_suspend(void); +extern void md_usb_hos_request_status(void); +extern void md_usb_hos_request_in(uint32_t ui32Endpoint); +extern void md_usb_hos_request_in_clear(uint32_t ui32Endpoint); +extern uint32_t md_usb_hos_speed_get(void); +extern uint32_t md_usb_hos_addr_get(uint32_t ui32Endpoint, uint32_t ui32Flags); +extern void md_usb_hos_addr_set(uint32_t ui32Endpoint, + uint32_t ui32Addr, + uint32_t ui32Flags); +extern uint32_t md_usb_hos_hub_addr_get(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hos_hub_addr_set(uint32_t ui32Endpoint, + uint32_t ui32Addr, + uint32_t ui32Flags); +/* Device Mode */ +extern void md_usb_dev_addr_set(uint8_t ui32Address); +extern uint8_t md_usb_dev_addr_get(void); +extern void md_usb_dev_connect(void); +extern void md_usb_dev_disconnect(void); +extern uint32_t md_usb_dev_speed_get(void); +/* Host/Device Mode */ +extern uint32_t md_usb_hosdev_frame_get(void); +extern void md_usb_hosdev_int_disable(uint32_t ui32IntFlags); +extern void md_usb_hosdev_int_enable(uint32_t ui32IntFlags); +extern uint32_t md_usb_hosdev_int_status(void); +extern uint32_t md_usb_hosdev_mode_get(void); +/* otg Mode */ +extern void md_usb_otg_session_request(bool bStart); +extern void md_usb_force_host_mode(void); +extern void md_usb_force_device_mode(void); +extern void md_usb_force_otg_mode(void); +extern void md_usb_mode_config(uint32_t ui32Mode); +/** + * @} USB basic API. + */ + +/** + * @{ USB endpoint API. + */ +/* Host Mode */ +extern void md_usb_hos_endpoint_config_set(uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_data_ack(uint32_t ui32Endpoint); +extern void md_usb_hos_endpoint_data_toggle(uint32_t ui32Endpoint, + bool bDataToggle, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_status_clear(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_speed(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hos_endpoint_ping(uint32_t ui32Endpoint, + bool bEnable); +/* Device Mode */ +extern void md_usb_dev_endpoint_config_set(uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32Flags); +extern void md_usb_dev_endpoint_config_get(uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, + uint32_t *pui32Flags); +extern void md_usb_dev_endpoint_ack(uint32_t ui32Endpoint, + bool bIsLastPacket); +extern void md_usb_dev_endpoint_stall(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_dev_endpoint_stall_clear(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_dev_endpoint_status_clear(uint32_t ui32Endpoint, + uint32_t ui32Flags); +/* Host/Device Mode */ +extern uint32_t md_usb_hosdev_endpoint_datavai(uint32_t ui32Endpoint); +extern int32_t md_usb_hosdev_endpoint_data_get(uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size); +extern int32_t md_usb_hosdev_endpoint_data_put(uint32_t ui32Endpoint, + uint8_t *pui8Data, + uint32_t ui32Size); +extern int32_t md_usb_hosdev_endpoint_data_send(uint32_t ui32Endpoint, + uint32_t ui32TransType); +extern void md_usb_hosdev_endpoint_data_togglec(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_hosdev_endpoint_pkcount_set(uint32_t ui32Endpoint, + uint32_t ui32Count); +extern uint32_t md_usb_hosdev_endpoint_status(uint32_t ui32Endpoint); +extern void md_usb_hosdev_endpoint_int_disable(uint32_t ui32IntFlags); +extern void md_usb_hosdev_endpoint_int_enable(uint32_t ui32IntFlags); +extern uint32_t md_usb_hosdev_endpoint_int_status(void); +extern uint32_t md_usb_endpoint_number_get(void); +/** + * @} USB endpoint API. + */ + +/** + * @{ USB FIFO API. + */ +extern uint32_t md_usb_hosdev_fifo_addr_get(uint32_t ui32Endpoint); +extern void md_usb_hosdev_fifo_config_get(uint32_t ui32Endpoint, uint32_t *pui32FIFOAddress, + uint32_t *pui32FIFOSize, uint32_t ui32Flags); +extern void md_usb_hosdev_fifo_config_set(uint32_t ui32Endpoint, uint32_t ui32FIFOAddress, + uint32_t ui32FIFOSize, uint32_t ui32Flags); +extern void md_usb_hosdev_fifo_flush(uint32_t ui32Endpoint, uint32_t ui32Flags); +/** + * @} USB FIFO API. + */ + +/** + * @{ USB PWR API.it is not supported by es32f0271. + */ +extern void md_usb_hos_pwr_disable(void); +extern void md_usb_hos_pwr_enable(void); +extern void md_usb_hos_pwr_config(uint32_t ui32Flags); +extern void md_usb_hos_pwrfault_disable(void); +extern void md_usb_hos_pwrfault_enable(void); +/** + * @} USB PWR API. + */ + +/** + * @{ USB LPM API.it is not supported by es32f0271. + */ +extern void md_usb_hos_lpm_send(uint32_t ui32Address, + uint32_t uiEndpoint); +extern void md_usb_hos_lpm_config(uint32_t ui32ResumeTime, + uint32_t ui32Config); +extern bool md_usb_lpm_remotewake_is_enabled(void); +extern void md_usb_hos_lpm_resume(void); +extern void md_usb_dev_lpm_remotewake(void); +extern void md_usb_dev_lpm_config(uint32_t ui32Config); +extern void md_usb_dev_lpm_enable(void); +extern void md_usb_dev_lpm_disable(void); +extern uint32_t md_usb_lpm_link_state_get(void); +extern uint32_t md_usb_lpm_endpoint_get(void); +extern uint32_t md_usb_lpm_status(void); +extern void md_usb_lpm_int_disable(uint32_t ui32Ints); +extern void md_usb_lpm_int_enable(uint32_t ui32Ints); +/** + * @} USB LPM API. + */ + +/** + * @{ USB ULPI API.it is not supported by es32f0271. + */ +extern void md_usb_ulpi_config(uint32_t ui32Config); +extern void md_usb_ulpi_enable(void); +extern void md_usb_ulpi_disable(void); +extern uint8_t md_usb_ulpi_reg_read(uint8_t ui8Reg); +extern void md_usb_ulpi_reg_write(uint8_t ui8Reg, + uint8_t ui8Data); +/** + * @} USB ULPI API. + */ + +/** + * @{ USB DMA API.it is not supported by es32f0271. + */ +extern void md_usb_dma_endpoint_channel_set(uint32_t ui32Endpoint, + uint32_t ui32Channel); +extern void md_usb_dma_endpoint_enable(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_dma_endpoint_disable(uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void md_usb_dma_endpoint_config(uint32_t ui32Endpoint, + uint32_t ui32Config); +extern void md_usb_dma_channel_config(uint32_t ui32Channel, + uint32_t ui32Endpoint, + uint32_t ui32Config); +extern void md_usb_dma_channel_address_set(uint32_t ui32Channel, + void *pvAddress); +extern void *md_usb_dma_channel_address_get(uint32_t ui32Channel); +extern void md_usb_dma_channel_count_set(uint32_t ui32Count, + uint32_t ui32Channel); +extern uint32_t md_usb_dma_channel_count_get(uint32_t ui32Channel); +extern void md_usb_dma_channel_int_enable(uint32_t ui32Channel); +extern void md_usb_dma_channel_int_disable(uint32_t ui32Channel); +extern uint32_t md_usb_dma_channel_int_status(void); +extern void md_usb_dma_channel_enable(uint32_t ui32Channel); +extern void md_usb_dma_channel_disable(uint32_t ui32Channel); +extern uint32_t md_usb_dma_channel_isenabled(uint32_t ui32Channel); +extern uint32_t md_usb_dma_channel_status(uint32_t ui32Channel); +extern void md_usb_dma_channel_status_clear(uint32_t ui32Channel, + uint32_t ui32Status); +/** + * @} USB DMA API. + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/******************* (C) COPYRIGHT Eastsoft Microelectronics Co., Ltd. *** END OF FILE ****/ diff --git a/bsp/essemi/es32f0271/project.uvoptx b/bsp/essemi/es32f0271/project.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..bd379df962cc044c682312fc6471414d42319ba1 --- /dev/null +++ b/bsp/essemi/es32f0271/project.uvoptx @@ -0,0 +1,797 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
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libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_spi.c + md_spi.c + 0 + 0 + + + 4 + 25 + 1 + 0 + 0 + 0 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_tick.c + md_tick.c + 0 + 0 + + + 4 + 26 + 1 + 0 + 0 + 0 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_uart.c + md_uart.c + 0 + 0 + + + 4 + 27 + 1 + 0 + 0 + 0 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_usb.c + md_usb.c + 0 + 0 + + + 4 + 28 + 1 + 0 + 0 + 0 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_wwdt.c + md_wwdt.c + 0 + 0 + + + 4 + 29 + 2 + 0 + 0 + 0 + libraries\CMSIS\Device\EastSoft\ES32F0271\Startup\keil\startup_es32f027x.s + startup_es32f027x.s + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + libraries\CMSIS\Device\EastSoft\ES32F0271\System\system_es32f027x.c + system_es32f027x.c + 0 + 0 + + + + + cpu + 0 + 0 + 0 + 0 + + 5 + 31 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 5 + 32 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 5 + 33 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 5 + 34 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m0\cpuport.c + cpuport.c + 0 + 0 + + + 5 + 35 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S + context_rvds.S + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 6 + 42 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 6 + 43 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 6 + 44 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + + + finsh + 0 + 0 + 0 + 0 + + 7 + 45 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 7 + 46 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 7 + 47 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + +     diff --git a/bsp/essemi/es32f0271/project.uvprojx b/bsp/essemi/es32f0271/project.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..664a6e8f023a63bbed15617419d66874992fe7f8 --- /dev/null +++ b/bsp/essemi/es32f0271/project.uvprojx @@ -0,0 +1,662 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ES32F0271LT + Eastsoft + Eastsoft.ES32_DFP.1.0.4 + http://www.essemi.com + IRAM(0x20000000,0x00002000) IROM(0x00000000,0x00010000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0ES32F0271 -FS00 -FL010000 -FP0($$Device:ES32F0271LT$Flash\ES32F0271.FLM)) + 0 + $$Device:ES32F0271LT$Device\Include\es32f027x.h + + + + + + + + + + $$Device:ES32F0271LT$SVD\es32f027x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\keil\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + -MPU + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + .;..\..\..\include;applications;.;drivers;libraries\CMSIS\Device\EastSoft\ES32F0271\Include;libraries\CMSIS\Device\EastSoft\ES32F0271\Include\ES32F0271;libraries\CMSIS\Device\EastSoft\ES32F0271\System;libraries\CMSIS\Include;libraries;libraries\ES32F027x_MD_StdPeriph_Driver\Include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + signal.c + 1 + ..\..\..\src\signal.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_uart.c + 1 + drivers\drv_uart.c + + + + + Libraries + + + md_adc.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_adc.c + + + md_fc.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_fc.c + + + md_gpio.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_gpio.c + + + md_i2c.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_i2c.c + + + md_rcu.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_rcu.c + + + md_spi.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_spi.c + + + md_tick.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_tick.c + + + md_uart.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_uart.c + + + md_usb.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_usb.c + + + md_wwdt.c + 1 + libraries\ES32F027x_MD_StdPeriph_Driver\Source\md_wwdt.c + + + startup_es32f027x.s + 2 + libraries\CMSIS\Device\EastSoft\ES32F0271\Startup\keil\startup_es32f027x.s + + + system_es32f027x.c + 1 + libraries\CMSIS\Device\EastSoft\ES32F0271\System\system_es32f027x.c + + + + + cpu + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m0\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + + + + + + + + + +     diff --git a/bsp/essemi/es32f0271/rtconfig.h b/bsp/essemi/es32f0271/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..4a0cf3306a074e2f9f2ccc1c0a89debfbf6fc3ca --- /dev/null +++ b/bsp/essemi/es32f0271/rtconfig.h @@ -0,0 +1,183 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40002 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 256 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 2048 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_ES32F0271LT + +/* Hardware Drivers Config */ + +/* On-chip Peripheral Drivers */ + +/* PIN Drivers */ + +#define BSP_USING_GPIO + +/* UART Drivers */ + +#define BSP_USING_UART1 + +/* SPI Drivers */ + + +/* I2C Drivers */ + + +/* HWtimer Drivers */ + + +/* PWM Drivers */ + + +/* RTC Drivers */ + + +/* ADC Drivers */ + + +/* Onboard Peripheral Drivers */ + +/* Offboard Peripheral Drivers */ + + +#endif diff --git a/bsp/es32f0654/rtconfig.py b/bsp/essemi/es32f0271/rtconfig.py similarity index 100% rename from bsp/es32f0654/rtconfig.py rename to bsp/essemi/es32f0271/rtconfig.py diff --git a/bsp/essemi/es32f0271/template.uvoptx b/bsp/essemi/es32f0271/template.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..bb8cce6ff239433f865a076c0a65468edf11b7e5 --- /dev/null +++ b/bsp/essemi/es32f0271/template.uvoptx @@ -0,0 +1,177 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0ES32F0271 -FL010000 -FS00 -FP0($$Device:ES32F0271LT$Flash\ES32F0271.FLM) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0ES32F0271.FLM -FS00 -FL010000 -FP0($$Device:ES32F0271LT$Flash\ES32F0271.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + +     diff --git a/bsp/essemi/es32f0271/template.uvprojx b/bsp/essemi/es32f0271/template.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..ce19e112f525126e07269fab57b4f661434b4b02 --- /dev/null +++ b/bsp/essemi/es32f0271/template.uvprojx @@ -0,0 +1,389 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + rt-thread + 0x4 + ARM-ADS + 0 + + + ES32F0271LT + Eastsoft + Eastsoft.ES32_DFP.1.0.4 + http://www.essemi.com + IRAM(0x20000000,0x00002000) IROM(0x00000000,0x00010000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0ES32F0271 -FS00 -FL010000 -FP0($$Device:ES32F0271LT$Flash\ES32F0271.FLM)) + 0 + $$Device:ES32F0271LT$Device\Include\es32f027x.h + + + + + + + + + + $$Device:ES32F0271LT$SVD\es32f027x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\keil\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + -MPU + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + + + + + + + +     diff --git a/bsp/es32f0654/.config b/bsp/essemi/es32f0654/.config similarity index 69% rename from bsp/es32f0654/.config rename to bsp/essemi/es32f0654/.config index 9853f9b6d0bff953a2dd6fb01c753cd28b09642e..56a52e8087befe972a89219b5be2a16eb17e682b 100644 --- a/bsp/es32f0654/.config +++ b/bsp/essemi/es32f0654/.config @@ -7,6 +7,7 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -63,7 +64,8 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" -CONFIG_RT_VER_NUM=0x40001 +CONFIG_RT_VER_NUM=0x40002 +# CONFIG_RT_USING_CPU_FFS is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # @@ -108,6 +110,7 @@ CONFIG_FINSH_ARG_MAX=10 # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y # CONFIG_RT_SERIAL_USING_DMA is not set CONFIG_RT_SERIAL_RB_BUFSZ=64 @@ -120,7 +123,6 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set @@ -128,10 +130,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_WIFI is not set # @@ -145,6 +147,7 @@ CONFIG_RT_USING_PIN=y # # CONFIG_RT_USING_LIBC is not set # CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_LIBC_USING_TIME is not set # # Network @@ -156,14 +159,14 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_SAL is not set # -# light weight TCP/IP stack +# Network interface device # -# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_NETDEV is not set # -# Modbus master and slave stack +# light weight TCP/IP stack # -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_LWIP is not set # # AT commands @@ -178,7 +181,6 @@ CONFIG_RT_USING_PIN=y # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set @@ -192,10 +194,13 @@ CONFIG_RT_USING_PIN=y # # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -213,10 +218,14 @@ CONFIG_RT_USING_PIN=y # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set # # IoT Cloud @@ -225,6 +234,21 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set # # security packages @@ -245,6 +269,9 @@ CONFIG_RT_USING_PIN=y # # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set # # tools packages @@ -253,6 +280,12 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set # # system packages @@ -266,17 +299,42 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set # # peripheral libraries and drivers # -# CONFIG_PKG_USING_STM32F4_HAL is not set -# CONFIG_PKG_USING_STM32F4_DRIVERS is not set +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set # CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_LCD_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set # # miscellaneous packages @@ -287,13 +345,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set - -# -# sample package -# +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -302,11 +362,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# # CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set CONFIG_SOC_ES32F0654LT=y # @@ -350,7 +414,6 @@ CONFIG_BSP_USING_UART2=y # HWtimer Drivers # # CONFIG_BSP_USING_HWTIMER0 is not set -# CONFIG_BSP_USING_HWTIMER1 is not set # CONFIG_BSP_USING_HWTIMER2 is not set # CONFIG_BSP_USING_HWTIMER3 is not set diff --git a/bsp/es32f0654/Kconfig b/bsp/essemi/es32f0654/Kconfig similarity index 94% rename from bsp/es32f0654/Kconfig rename to bsp/essemi/es32f0654/Kconfig index 188eb5bfc04c1de7403688f56f5ee0a36b5445de..2d3814dfe94d8504578e98a619ca6e5f48f425e1 100644 --- a/bsp/es32f0654/Kconfig +++ b/bsp/essemi/es32f0654/Kconfig @@ -8,7 +8,7 @@ config BSP_DIR config RTT_DIR string option env="RTT_ROOT" - default "../.." + default "../../.." config PKGS_DIR string diff --git a/bsp/es32f0654/README.md b/bsp/essemi/es32f0654/README.md similarity index 98% rename from bsp/es32f0654/README.md rename to bsp/essemi/es32f0654/README.md index 8111adeda57a5ff9d6cbf520a81ec2bd1b35d2c0..120cf0f4798abcf7a494d5deab8d37490e80f83c 100644 --- a/bsp/es32f0654/README.md +++ b/bsp/essemi/es32f0654/README.md @@ -40,6 +40,7 @@ ES-PDS-ES32F0654-V1.1 | UART | 支持 | UART0/1/2/3 | | SPI | 支持 | SPI0/1 | | I2C | 支持 | I2C0/1 | +| CAN | 支持 | CAN0 | | PWM | 支持 | PWM0/1/2/3 | | TIMER | 支持 | TIMER0/1/2/3 | | RTC | 支持 | RTC | diff --git a/bsp/essemi/es32f0654/SConscript b/bsp/essemi/es32f0654/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..468297b6a99ab9c400a87ed01dcdedc3d60da45d --- /dev/null +++ b/bsp/essemi/es32f0654/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +objs = [] +cwd = str(Dir('#')) +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/es32f0654/SConstruct b/bsp/essemi/es32f0654/SConstruct similarity index 94% rename from bsp/es32f0654/SConstruct rename to bsp/essemi/es32f0654/SConstruct index ac791958337caba15ec8cd8f32fe5f13b21c13d7..e75d75371b9d36fe3c5bd73b14db2d5f0fa5a95b 100644 --- a/bsp/es32f0654/SConstruct +++ b/bsp/essemi/es32f0654/SConstruct @@ -5,7 +5,7 @@ import rtconfig if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] try: diff --git a/bsp/essemi/es32f0654/applications/SConscript b/bsp/essemi/es32f0654/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..e0c84e8f1426ab2abb2c870cea377371a7c752f3 --- /dev/null +++ b/bsp/essemi/es32f0654/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') + +CPPPATH = [cwd, str(Dir('#'))] +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/es32f0654/applications/main.c b/bsp/essemi/es32f0654/applications/main.c similarity index 100% rename from bsp/es32f0654/applications/main.c rename to bsp/essemi/es32f0654/applications/main.c diff --git a/bsp/es32f0654/drivers/Kconfig b/bsp/essemi/es32f0654/drivers/Kconfig similarity index 95% rename from bsp/es32f0654/drivers/Kconfig rename to bsp/essemi/es32f0654/drivers/Kconfig index f7a64ea678b920dc8f238bc5d1774b302bc3fdf6..888308497ae24c4c7a45bad8e58e01f353ba27de 100644 --- a/bsp/es32f0654/drivers/Kconfig +++ b/bsp/essemi/es32f0654/drivers/Kconfig @@ -56,6 +56,13 @@ menu "Hardware Drivers Config" default n endmenu + menu "CAN Drivers" + config BSP_USING_CAN + bool "Enable CAN BUS PA11/PA12(RX/TX)" + select RT_USING_CAN + default n + endmenu + menu "PWM Drivers" config BSP_USING_PWM0 bool "Using PWM0 PA08/PA09/PA10/PA11" diff --git a/bsp/es32f0654/drivers/SConscript b/bsp/essemi/es32f0654/drivers/SConscript similarity index 94% rename from bsp/es32f0654/drivers/SConscript rename to bsp/essemi/es32f0654/drivers/SConscript index a5ecf863ab5a3631ddbce451d1e52ca832d33429..ad5cf3c7836b27f4741ae3c66f922ad2be01f446 100644 --- a/bsp/es32f0654/drivers/SConscript +++ b/bsp/essemi/es32f0654/drivers/SConscript @@ -23,6 +23,10 @@ if GetDepend('BSP_USING_SPI0') or GetDepend('BSP_USING_SPI1'): if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'): src += ['drv_i2c.c'] +# add can driver code +if GetDepend('BSP_USING_CAN'): + src += ['drv_can.c'] + # add spi flash driver code if GetDepend('BSP_USING_SPI_FLASH'): src += ['drv_spiflash.c'] diff --git a/bsp/es32f0654/drivers/board.c b/bsp/essemi/es32f0654/drivers/board.c similarity index 89% rename from bsp/es32f0654/drivers/board.c rename to bsp/essemi/es32f0654/drivers/board.c index 46b3d472a03b1431856e02094d70e7fecd9d1cbb..94b259e48524b9cc3c1cb899711e92ed4ed64380 100644 --- a/bsp/es32f0654/drivers/board.c +++ b/bsp/essemi/es32f0654/drivers/board.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-01-23 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -43,10 +44,10 @@ void NVIC_Configuration(void) void SystemClock_Config(void) { /* hosc 12MHz, from hosc/3 pll to 48MHz */ - cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_48M); + ald_cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_48M); /* MCLK 48MHz*/ - cmu_clock_config(CMU_CLOCK_PLL1, 48000000); + ald_cmu_clock_config(CMU_CLOCK_PLL1, 48000000); } /******************************************************************************* @@ -59,14 +60,14 @@ void SystemClock_Config(void) void SysTick_Configuration(void) { /* ticks = sysclk / RT_TICK_PER_SECOND */ - SysTick_Config(cmu_get_sys_clock() / RT_TICK_PER_SECOND); + SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND); } /** * This is the timer interrupt service routine. * */ -void systick_irq_cbk(void) +void SysTick_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); @@ -113,7 +114,7 @@ void rt_hw_us_delay(rt_uint32_t us) unsigned int start, now, delta, reload, us_tick; start = SysTick->VAL; reload = SysTick->LOAD; - us_tick = cmu_get_sys_clock() / 1000000UL; + us_tick = ald_cmu_get_sys_clock() / 1000000UL; do { now = SysTick->VAL; diff --git a/bsp/es32f0654/drivers/board.h b/bsp/essemi/es32f0654/drivers/board.h similarity index 100% rename from bsp/es32f0654/drivers/board.h rename to bsp/essemi/es32f0654/drivers/board.h diff --git a/bsp/es32f0654/drivers/drv_adc.c b/bsp/essemi/es32f0654/drivers/drv_adc.c similarity index 71% rename from bsp/es32f0654/drivers/drv_adc.c rename to bsp/essemi/es32f0654/drivers/drv_adc.c index 9a90e4d3944e48eb7d3737407848fab555709931..81a269d5c3eb5a9e9a874120bc395d10855cdce6 100644 --- a/bsp/es32f0654/drivers/drv_adc.c +++ b/bsp/essemi/es32f0654/drivers/drv_adc.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-04-03 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -58,67 +59,67 @@ static adc_channel_t es32f0_adc_get_channel(rt_uint32_t channel) { case 0: es32f0_channel = ADC_CHANNEL_0; - gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct); break; case 1: es32f0_channel = ADC_CHANNEL_1; - gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct); + ald_gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct); break; case 2: es32f0_channel = ADC_CHANNEL_2; - gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct); + ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct); break; case 3: es32f0_channel = ADC_CHANNEL_3; - gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct); + ald_gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct); break; case 4: es32f0_channel = ADC_CHANNEL_4; - gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct); break; case 5: es32f0_channel = ADC_CHANNEL_5; - gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct); + ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct); break; case 6: es32f0_channel = ADC_CHANNEL_6; - gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct); + ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct); break; case 7: es32f0_channel = ADC_CHANNEL_7; - gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct); + ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct); break; case 8: es32f0_channel = ADC_CHANNEL_8; - gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct); + ald_gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct); break; case 9: es32f0_channel = ADC_CHANNEL_9; - gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct); + ald_gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct); break; case 10: es32f0_channel = ADC_CHANNEL_10; - gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct); + ald_gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct); break; case 11: es32f0_channel = ADC_CHANNEL_11; - gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct); + ald_gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct); break; case 12: es32f0_channel = ADC_CHANNEL_12; - gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct); + ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct); break; case 13: es32f0_channel = ADC_CHANNEL_13; - gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct); + ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct); break; case 14: es32f0_channel = ADC_CHANNEL_14; - gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct); + ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct); break; case 15: es32f0_channel = ADC_CHANNEL_15; - gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct); + ald_gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct); break; case 16: es32f0_channel = ADC_CHANNEL_16; @@ -139,21 +140,21 @@ static adc_channel_t es32f0_adc_get_channel(rt_uint32_t channel) static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) { adc_handle_t *_hadc = (adc_handle_t *)device->parent.user_data; - adc_channel_conf_t nm_config; + adc_nch_conf_t nm_config; RT_ASSERT(device != RT_NULL); RT_ASSERT(value != RT_NULL); /* config adc channel */ nm_config.channel = es32f0_adc_get_channel(channel); - nm_config.rank = ADC_NC_RANK_1; - nm_config.sampling_time = ADC_SAMPLETIME_4; - adc_normal_channel_config(_hadc, &nm_config); + nm_config.rank = ADC_NCH_RANK_1; + nm_config.samp_time = ADC_SAMPLETIME_4; + ald_adc_normal_channel_config(_hadc, &nm_config); - adc_normal_start(_hadc); + ald_adc_normal_start(_hadc); - if (adc_normal_poll_for_conversion(_hadc, 5000) == OK) - *value = adc_normal_get_value(_hadc); + if (ald_adc_normal_poll_for_conversion(_hadc, 5000) == OK) + *value = ald_adc_normal_get_value(_hadc); return RT_EOK; } @@ -172,17 +173,16 @@ int rt_hw_adc_init(void) /* adc function initialization */ _h_adc0.perh = ADC0; _h_adc0.init.data_align = ADC_DATAALIGN_RIGHT; - _h_adc0.init.scan_mode = ADC_SCAN_DISABLE; + _h_adc0.init.scan_mode = DISABLE; _h_adc0.init.cont_mode = DISABLE; - _h_adc0.init.conv_nbr = ADC_NM_NBR_1; - _h_adc0.init.disc_mode = DISABLE; + _h_adc0.init.disc_mode = ADC_ALL_DISABLE; _h_adc0.init.disc_nbr = ADC_DISC_NBR_1; _h_adc0.init.conv_res = ADC_CONV_RES_10; _h_adc0.init.clk_div = ADC_CKDIV_128; - _h_adc0.init.nche_mode = ADC_NCHESEL_MODE_ALL; + _h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL; _h_adc0.init.neg_ref = ADC_NEG_REF_VSS; _h_adc0.init.pos_ref = ADC_POS_REF_VDD; - adc_init(&_h_adc0); + ald_adc_init(&_h_adc0); rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, &_h_adc0); diff --git a/bsp/es32f0654/drivers/drv_adc.h b/bsp/essemi/es32f0654/drivers/drv_adc.h similarity index 100% rename from bsp/es32f0654/drivers/drv_adc.h rename to bsp/essemi/es32f0654/drivers/drv_adc.h diff --git a/bsp/essemi/es32f0654/drivers/drv_can.c b/bsp/essemi/es32f0654/drivers/drv_can.c new file mode 100644 index 0000000000000000000000000000000000000000..0524fdaf07aa909a1d7c9b9e5f2d5ee6f4168cdd --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/drv_can.c @@ -0,0 +1,605 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-11-09 wangyq the first version + */ + +#include "drv_can.h" + +#ifdef BSP_USING_CAN + +static struct es32f0_can can; + +/* attention !!! baud calculation example: Pclk / ((sjw + seg1 + seg2) * psc) 48 / ((1 + 3 + 2) * 8) = 1MHz */ +static const struct es32f0_baud_rate_tab can_baud_rate_tab[] = +{ + {CAN1MBaud, 8}, + {CAN800kBaud, 10}, + {CAN500kBaud, 16}, + {CAN250kBaud, 32}, + {CAN125kBaud, 64}, + {CAN100kBaud, 80}, + {CAN50kBaud, 160}, + {CAN20kBaud, 400}, + {CAN10kBaud, 800} +}; + +static rt_uint32_t get_can_baud_index(rt_uint32_t baud) +{ + rt_uint32_t len, index; + + len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]); + for (index = 0; index < len; index++) + { + if (can_baud_rate_tab[index].baud_rate == baud) + return index; + } + + return 0; /* default baud is CAN1MBaud */ +} + +static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configure *cfg) +{ + struct es32f0_can *drv_can; + rt_uint32_t baud_index; + + RT_ASSERT(can_device); + RT_ASSERT(cfg); + drv_can = (struct es32f0_can *)can_device->parent.user_data; + RT_ASSERT(drv_can); + + drv_can->CanHandle.perh = CAN0; + drv_can->CanHandle.init.ttcm = DISABLE; + drv_can->CanHandle.init.abom = ENABLE; + drv_can->CanHandle.init.awk = DISABLE; + drv_can->CanHandle.init.artx = DISABLE; + drv_can->CanHandle.init.rfom = DISABLE; + drv_can->CanHandle.init.txmp = ENABLE; + + switch (cfg->mode) + { + case RT_CAN_MODE_NORMAL: + drv_can->CanHandle.init.mode = CAN_MODE_NORMAL; + break; + case RT_CAN_MODE_LISEN: + drv_can->CanHandle.init.mode = CAN_MODE_SILENT; + break; + case RT_CAN_MODE_LOOPBACK: + drv_can->CanHandle.init.mode = CAN_MODE_LOOPBACK; + break; + case RT_CAN_MODE_LOOPBACKANLISEN: + drv_can->CanHandle.init.mode = CAN_MODE_SILENT_LOOPBACK; + break; + } + + baud_index = get_can_baud_index(cfg->baud_rate); + drv_can->CanHandle.init.sjw = CAN_SJW_1; + drv_can->CanHandle.init.seg1 = CAN_SEG1_3; + drv_can->CanHandle.init.seg2 = CAN_SEG2_2; + drv_can->CanHandle.init.psc = can_baud_rate_tab[baud_index].config_data; + /* init can */ + if (ald_can_init(&drv_can->CanHandle) != OK) + { + return -RT_ERROR; + } + /* default filter config */ + ald_can_filter_config(&drv_can->CanHandle, &drv_can->FilterConfig); + + return RT_EOK; +} + +static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *arg) +{ + rt_uint32_t argval; + struct es32f0_can *drv_can; + struct rt_can_filter_config *filter_cfg; + + RT_ASSERT(can_device != RT_NULL); + drv_can = (struct es32f0_can *)can_device->parent.user_data; + RT_ASSERT(drv_can != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + argval = (rt_uint32_t) arg; + if (argval == RT_DEVICE_FLAG_INT_RX) + { + ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FF0 | CAN_IT_FOV0 | + CAN_IT_FP1 | CAN_IT_FF1 | CAN_IT_FOV1), DISABLE); + } + else if (argval == RT_DEVICE_FLAG_INT_TX) + { + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_TXM, DISABLE); + } + else if (argval == RT_DEVICE_CAN_INT_ERR) + { + ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF | + CAN_IT_PRERR | CAN_IT_ERR), DISABLE); + } + break; + case RT_DEVICE_CTRL_SET_INT: + argval = (rt_uint32_t) arg; + if (argval == RT_DEVICE_FLAG_INT_RX) + { + NVIC_SetPriority(CAN0_IRQn, 1); + NVIC_EnableIRQ(CAN0_IRQn); + + ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FP1), ENABLE); + } + else if (argval == RT_DEVICE_FLAG_INT_TX) + { + NVIC_SetPriority(CAN0_IRQn, 1); + NVIC_EnableIRQ(CAN0_IRQn); + + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_TXM, ENABLE); + } + else if (argval == RT_DEVICE_CAN_INT_ERR) + { + NVIC_SetPriority(CAN0_IRQn, 1); + NVIC_EnableIRQ(CAN0_IRQn); + + ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF | + CAN_IT_PRERR | CAN_IT_ERR), ENABLE); + } + break; + case RT_CAN_CMD_SET_FILTER: + if (RT_NULL == arg) + { + /* default filter config */ + ald_can_filter_config(&drv_can->CanHandle, &drv_can->FilterConfig); + } + else + { + filter_cfg = (struct rt_can_filter_config *)arg; + /* get default filter */ + for (int i = 0; i < filter_cfg->count; i++) + { + drv_can->FilterConfig.number = filter_cfg->items[i].hdr; + drv_can->FilterConfig.id_high = (filter_cfg->items[i].id >> 13) & 0xFFFF; + drv_can->FilterConfig.id_low = ((filter_cfg->items[i].id << 3) | + (filter_cfg->items[i].ide << 2) | + (filter_cfg->items[i].rtr << 1)) & 0xFFFF; + drv_can->FilterConfig.mask_id_high = (filter_cfg->items[i].mask >> 16) & 0xFFFF; + drv_can->FilterConfig.mask_id_low = filter_cfg->items[i].mask & 0xFFFF; + drv_can->FilterConfig.mode = (can_filter_mode_t)filter_cfg->items[i].mode; + /* Filter conf */ + ald_can_filter_config(&drv_can->CanHandle, &drv_can->FilterConfig); + } + } + break; + case RT_CAN_CMD_SET_MODE: + argval = (rt_uint32_t) arg; + if (argval != RT_CAN_MODE_NORMAL && + argval != RT_CAN_MODE_LISEN && + argval != RT_CAN_MODE_LOOPBACK && + argval != RT_CAN_MODE_LOOPBACKANLISEN) + { + return -RT_ERROR; + } + if (argval != drv_can->device.config.mode) + { + drv_can->device.config.mode = argval; + return _can_config(&drv_can->device, &drv_can->device.config); + } + break; + case RT_CAN_CMD_SET_BAUD: + argval = (rt_uint32_t) arg; + if (argval != CAN1MBaud && + argval != CAN800kBaud && + argval != CAN500kBaud && + argval != CAN250kBaud && + argval != CAN125kBaud && + argval != CAN100kBaud && + argval != CAN50kBaud && + argval != CAN20kBaud && + argval != CAN10kBaud) + { + return -RT_ERROR; + } + if (argval != drv_can->device.config.baud_rate) + { + drv_can->device.config.baud_rate = argval; + return _can_config(&drv_can->device, &drv_can->device.config); + } + break; + case RT_CAN_CMD_SET_PRIV: + argval = (rt_uint32_t) arg; + if (argval != RT_CAN_MODE_PRIV && + argval != RT_CAN_MODE_NOPRIV) + { + return -RT_ERROR; + } + if (argval != drv_can->device.config.privmode) + { + drv_can->device.config.privmode = argval; + return _can_config(&drv_can->device, &drv_can->device.config); + } + break; + case RT_CAN_CMD_GET_STATUS: + { + rt_uint32_t errtype; + errtype = drv_can->CanHandle.perh->ERRSTAT; + drv_can->device.status.rcverrcnt = errtype >> 24; + drv_can->device.status.snderrcnt = (errtype >> 16 & 0xFF); + drv_can->device.status.lasterrtype = errtype & 0x70; + drv_can->device.status.errcode = errtype & 0x07; + + rt_memcpy(arg, &drv_can->device.status, sizeof(drv_can->device.status)); + } + break; + } + + return RT_EOK; +} + +static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num) +{ + can_handle_t *h_can; + h_can = &((struct es32f0_can *) can->parent.user_data)->CanHandle; + struct rt_can_msg *pmsg = (struct rt_can_msg *) buf; + can_tx_msg_t txheader = {0}; + can_state_t state = h_can->state; + + /* Check the parameters */ + RT_ASSERT(IS_CAN_DATA_LEN(pmsg->len)); + + if ((state == CAN_STATE_READY) || + (state == CAN_STATE_BUSY_RX)) + { + /*check select mailbox is empty */ + switch (1 << box_num) + { + case CAN_TX_MAILBOX_0: + if (ald_can_get_flag_status(h_can, CAN_FLAG_TXM0) != SET) + { + /* Change CAN state */ + h_can->state = CAN_STATE_ERROR; + /* Return function status */ + return -RT_ERROR; + } + break; + case CAN_TX_MAILBOX_1: + if (ald_can_get_flag_status(h_can, CAN_FLAG_TXM1) != SET) + { + /* Change CAN state */ + h_can->state = CAN_STATE_ERROR; + /* Return function status */ + return -RT_ERROR; + } + break; + case CAN_TX_MAILBOX_2: + if (ald_can_get_flag_status(h_can, CAN_FLAG_TXM2) != SET) + { + /* Change CAN state */ + h_can->state = CAN_STATE_ERROR; + /* Return function status */ + return -RT_ERROR; + } + break; + default: + RT_ASSERT(0); + break; + } + + if (RT_CAN_STDID == pmsg->ide) + { + txheader.type = CAN_ID_STD; + RT_ASSERT(IS_CAN_STDID(pmsg->id)); + txheader.std = pmsg->id; + } + else + { + txheader.type = CAN_ID_EXT; + RT_ASSERT(IS_CAN_EXTID(pmsg->id)); + txheader.ext = pmsg->id; + } + + if (RT_CAN_DTR == pmsg->rtr) + { + txheader.rtr = CAN_RTR_DATA; + } + else + { + txheader.rtr = CAN_RTR_REMOTE; + } + /* clear TIR */ + h_can->perh->TxMailBox[box_num].TXID &= CAN_TXID0_TXMREQ_MSK; + /* Set up the Id */ + if (RT_CAN_STDID == pmsg->ide) + { + h_can->perh->TxMailBox[box_num].TXID |= (txheader.std << CAN_TXID0_STDID_POSS) | txheader.rtr; + } + else + { + h_can->perh->TxMailBox[box_num].TXID |= (txheader.ext << CAN_TXID0_EXID_POSS) | txheader.type | txheader.rtr; + } + /* Set up the DLC */ + h_can->perh->TxMailBox[box_num].TXFCON = pmsg->len & 0x0FU; + /* Set up the data field */ + WRITE_REG(h_can->perh->TxMailBox[box_num].TXDH, + ((uint32_t)pmsg->data[7] << CAN_TXDH0_BYTE7_POSS) | + ((uint32_t)pmsg->data[6] << CAN_TXDH0_BYTE6_POSS) | + ((uint32_t)pmsg->data[5] << CAN_TXDH0_BYTE5_POSS) | + ((uint32_t)pmsg->data[4] << CAN_TXDH0_BYTE4_POSS)); + WRITE_REG(h_can->perh->TxMailBox[box_num].TXDL, + ((uint32_t)pmsg->data[3] << CAN_TXDL0_BYTE3_POSS) | + ((uint32_t)pmsg->data[2] << CAN_TXDL0_BYTE2_POSS) | + ((uint32_t)pmsg->data[1] << CAN_TXDL0_BYTE1_POSS) | + ((uint32_t)pmsg->data[0] << CAN_TXDL0_BYTE0_POSS)); + /* Request transmission */ + SET_BIT(h_can->perh->TxMailBox[box_num].TXID, CAN_TXID0_TXMREQ_MSK); + + return RT_EOK; + } + else + { + /* Update error code */ + h_can->err |= 0x00040000U; + + return -RT_ERROR; + } +} + +static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) +{ + can_handle_t *h_can; + struct rt_can_msg *pmsg; + can_rx_msg_t rxheader = {0}; + + RT_ASSERT(can); + + h_can = &((struct es32f0_can *)can->parent.user_data)->CanHandle; + pmsg = (struct rt_can_msg *) buf; + + /* get data */ + if (ald_can_recv(h_can, (can_rx_fifo_t)fifo, &rxheader, 0xFFFF) != OK) + return -RT_ERROR; + pmsg->data[0] = rxheader.data[0]; + pmsg->data[1] = rxheader.data[1]; + pmsg->data[2] = rxheader.data[2]; + pmsg->data[3] = rxheader.data[3]; + pmsg->data[4] = rxheader.data[4]; + pmsg->data[5] = rxheader.data[5]; + pmsg->data[6] = rxheader.data[6]; + pmsg->data[7] = rxheader.data[7]; + + /* get id */ + if (CAN_ID_STD == rxheader.type) + { + pmsg->ide = RT_CAN_STDID; + pmsg->id = rxheader.std; + } + else + { + pmsg->ide = RT_CAN_EXTID; + pmsg->id = rxheader.ext; + } + /* get type */ + if (CAN_RTR_DATA == rxheader.rtr) + { + pmsg->rtr = RT_CAN_DTR; + } + else + { + pmsg->rtr = RT_CAN_RTR; + } + /* get len */ + pmsg->len = rxheader.len; + /* get hdr */ + pmsg->hdr = (rxheader.fmi + 1) >> 1; + + return RT_EOK; +} + + +static const struct rt_can_ops _can_ops = +{ + _can_config, + _can_control, + _can_sendmsg, + _can_recvmsg, +}; + +static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) +{ + can_handle_t *h_can; + RT_ASSERT(can); + h_can = &((struct es32f0_can *) can->parent.user_data)->CanHandle; + + switch (fifo) + { + case CAN_RX_FIFO0: + /* Check Overrun flag for FIFO0 */ + if (ald_can_get_flag_status(h_can, CAN_FLAG_FOV0) && ald_can_get_it_status(h_can, CAN_IT_FOV0)) + { + /* Clear FIFO0 Overrun Flag */ + ald_can_clear_flag_status(h_can, CAN_FLAG_FOV0); + rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8); + } + /* RX interrupt */ + else + { + /* save to user list */ + rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + + /* Clear FIFO0 rx Flag */ + SET_BIT(h_can->perh->RXF0, CAN_RXF0_FREE_MSK); + } + break; + case CAN_RX_FIFO1: + /* Check Overrun flag for FIFO1 */ + if (ald_can_get_flag_status(h_can, CAN_FLAG_FOV1) && ald_can_get_it_status(h_can, CAN_IT_FOV1)) + { + /* Clear FIFO1 Overrun Flag */ + ald_can_clear_flag_status(h_can, CAN_FLAG_FOV1); + rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8); + } + /* RX interrupt */ + else + { + /* save to user list */ + rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + + /* Clear FIFO0 rx Flag */ + SET_BIT(h_can->perh->RXF1, CAN_RXF1_FREE_MSK); + } + break; + } +} + +/** + * @brief This function handles CAN interrupts. + */ +void CAN0_Handler(void) +{ + rt_interrupt_enter(); + + rt_uint32_t errtype; + can_handle_t *h_can; + h_can = &can.CanHandle; + + /* RX FIFO0 interrupt */ + if ((ald_can_get_it_status(h_can, CAN_IT_FP0)) && (CAN_RX_MSG_PENDING(h_can, CAN_RX_FIFO0) != 0)) + { + _can_rx_isr(&can.device, CAN_RX_FIFO0); + } + + /* RX FIFO1 interrupt */ + if ((ald_can_get_it_status(h_can, CAN_IT_FP1)) && (CAN_RX_MSG_PENDING(h_can, CAN_RX_FIFO1) != 0)) + { + _can_rx_isr(&can.device, CAN_RX_FIFO1); + } + + /* TX interrupt. transmit fifo0/1/2 is empty can trigger this interrupt */ + if (ald_can_get_flag_status(h_can, CAN_FLAG_M0REQC) && ald_can_get_it_status(h_can, CAN_IT_TXM)) + { + if (ald_can_get_flag_status(h_can, CAN_FLAG_M0TXC)) + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_DONE | 0 << 8); + } + else + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 0 << 8); + } + /* Clear transmission status flag M0REQC */ + ald_can_clear_flag_status(h_can, CAN_FLAG_M0REQC); + } + else if (ald_can_get_flag_status(h_can, CAN_FLAG_M1REQC) && ald_can_get_it_status(h_can, CAN_IT_TXM)) + { + if (ald_can_get_flag_status(h_can, CAN_FLAG_M1TXC)) + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_DONE | 1 << 8); + } + else + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 1 << 8); + } + ald_can_clear_flag_status(h_can, CAN_FLAG_M1REQC); + } + else if (ald_can_get_flag_status(h_can, CAN_FLAG_M2REQC) && ald_can_get_it_status(h_can, CAN_IT_TXM)) + { + if (ald_can_get_flag_status(h_can, CAN_FLAG_M2REQC)) + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_DONE | 2 << 8); + } + else + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 2 << 8); + } + ald_can_clear_flag_status(h_can, CAN_FLAG_M2REQC); + } + + /* CAN error interrupt */ + if (ald_can_get_flag_status(h_can, CAN_FLAG_ERR) && ald_can_get_it_status(h_can, CAN_IT_ERR)) + { + errtype = h_can->perh->ERRSTAT; + switch ((errtype & 0x70) >> 4) + { + case RT_CAN_BUS_BIT_PAD_ERR: + can.device.status.bitpaderrcnt++; + break; + case RT_CAN_BUS_FORMAT_ERR: + can.device.status.formaterrcnt++; + break; + case RT_CAN_BUS_ACK_ERR:/* attention !!! test ack err's unit is transmit unit */ + can.device.status.ackerrcnt++; + if (!READ_BIT(can.CanHandle.perh->TXSTAT, CAN_FLAG_M0TXC)) + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 0 << 8); + else if (!READ_BIT(can.CanHandle.perh->TXSTAT, CAN_FLAG_M0TXC)) + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 1 << 8); + else if (!READ_BIT(can.CanHandle.perh->TXSTAT, CAN_FLAG_M0TXC)) + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 2 << 8); + break; + case RT_CAN_BUS_IMPLICIT_BIT_ERR: + case RT_CAN_BUS_EXPLICIT_BIT_ERR: + can.device.status.biterrcnt++; + break; + case RT_CAN_BUS_CRC_ERR: + can.device.status.crcerrcnt++; + break; + } + + can.device.status.lasterrtype = errtype & 0x70; + can.device.status.rcverrcnt = errtype >> 24; + can.device.status.snderrcnt = (errtype >> 16 & 0xFF); + can.device.status.errcode = errtype & 0x07; + h_can->perh->IFC |= CAN_IFC_ERRIFC_MSK; + } + + rt_interrupt_leave(); +} + +int rt_hw_can_init(void) +{ + gpio_init_t h_gpio; + struct can_configure config = CANDEFAULTCONFIG; + + config.privmode = RT_CAN_MODE_NOPRIV; + config.ticks = 50; +#ifdef RT_CAN_USING_HDR + config.maxhdr = 14; +#endif + + /* Initialize can common pin */ + h_gpio.odos = GPIO_PUSH_PULL; + h_gpio.pupd = GPIO_PUSH_UP; + h_gpio.odrv = GPIO_OUT_DRIVE_NORMAL; + h_gpio.flt = GPIO_FILTER_DISABLE; + h_gpio.type = GPIO_TYPE_TTL; + h_gpio.func = GPIO_FUNC_4; + + /* Initialize can rx pin */ + h_gpio.mode = GPIO_MODE_INPUT; + ald_gpio_init(GPIOA, GPIO_PIN_11, &h_gpio); + + /* Initialize can tx pin */ + h_gpio.mode = GPIO_MODE_OUTPUT; + ald_gpio_init(GPIOA, GPIO_PIN_12, &h_gpio); + + /* config default filter */ + can_filter_t filter = {0}; + filter.id_high = 0x0000; + filter.id_low = 0x0000; + filter.mask_id_high = 0x0000; + filter.mask_id_low = 0x0000; + filter.fifo = CAN_FILTER_FIFO0; + filter.number = 0; + filter.mode = CAN_FILTER_MODE_MASK; + filter.scale = CAN_FILTER_SCALE_32; + filter.active = ENABLE; + filter.bank_number = 14; + + can.FilterConfig = filter; + can.device.config = config; + /* register CAN1 device */ + rt_hw_can_register(&can.device, "can", &_can_ops, &can); + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_can_init); + +#endif /* BSP_USING_CAN */ diff --git a/bsp/essemi/es32f0654/drivers/drv_can.h b/bsp/essemi/es32f0654/drivers/drv_can.h new file mode 100644 index 0000000000000000000000000000000000000000..798a3a8653bced33147f4c71b14d3575d9cacffe --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/drv_can.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-11-09 wangyq the first version + */ + +#ifndef DRV_CAN_H__ +#define DRV_CAN_H__ + +#include +#include +#include + +#include +#include + +struct es32f0_baud_rate_tab +{ + rt_uint32_t baud_rate; + rt_uint32_t config_data; +}; + +/* es32f0 can device */ +struct es32f0_can +{ + can_handle_t CanHandle; + can_filter_t FilterConfig; + struct rt_can_device device; /* inherit from can device */ +}; + +int rt_hw_can_init(void); + +#endif /*DRV_CAN_H__ */ diff --git a/bsp/es32f0654/drivers/drv_gpio.c b/bsp/essemi/es32f0654/drivers/drv_gpio.c similarity index 93% rename from bsp/es32f0654/drivers/drv_gpio.c rename to bsp/essemi/es32f0654/drivers/drv_gpio.c index 4374772ede4538c6468d4bb87ba55601b53e520e..680860757f750ece7fd56ea74fe6f32b5d6580ea 100644 --- a/bsp/es32f0654/drivers/drv_gpio.c +++ b/bsp/essemi/es32f0654/drivers/drv_gpio.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-01-23 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -167,7 +168,7 @@ void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) { return; } - gpio_write_pin(index->gpio, index->pin, value); + ald_gpio_write_pin(index->gpio, index->pin, value); } int es32f0_pin_read(rt_device_t dev, rt_base_t pin) @@ -180,7 +181,7 @@ int es32f0_pin_read(rt_device_t dev, rt_base_t pin) { return value; } - value = gpio_read_pin(index->gpio, index->pin); + value = ald_gpio_read_pin(index->gpio, index->pin); return value; } @@ -233,7 +234,7 @@ void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) gpio_initstruct.pupd = GPIO_FLOATING; gpio_initstruct.odos = GPIO_OPEN_DRAIN; } - gpio_init(index->gpio, index->pin, &gpio_initstruct); + ald_gpio_init(index->gpio, index->pin, &gpio_initstruct); } rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin) @@ -360,7 +361,7 @@ rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin, return RT_ENOSYS; } irqmap = &pin_irq_map[irqindex]; - gpio_exti_init(index->gpio, index->pin, &exti_initstruct); + ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct); /* Configure GPIO_InitStructure */ gpio_initstruct.mode = GPIO_MODE_INPUT; gpio_initstruct.func = GPIO_FUNC_1; @@ -368,18 +369,18 @@ rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin, { case PIN_IRQ_MODE_RISING: gpio_initstruct.pupd = GPIO_PUSH_DOWN; - gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE); + ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE); break; case PIN_IRQ_MODE_FALLING: gpio_initstruct.pupd = GPIO_PUSH_UP; - gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE); + ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE); break; case PIN_IRQ_MODE_RISING_FALLING: gpio_initstruct.pupd = GPIO_FLOATING; - gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE); + ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE); break; } - gpio_init(index->gpio, index->pin, &gpio_initstruct); + ald_gpio_init(index->gpio, index->pin, &gpio_initstruct); NVIC_EnableIRQ(irqmap->irqno); rt_hw_interrupt_enable(level); } @@ -412,7 +413,7 @@ const static struct rt_pin_ops _es32f0_pin_ops = int rt_hw_pin_init(void) { int result; - cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); + ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); result = rt_device_pin_register("pin", &_es32f0_pin_ops, RT_NULL); return result; } @@ -439,9 +440,9 @@ rt_inline void pin_irq_hdr(uint16_t GPIO_Pin) void GPIO_EXTI_Callback(uint16_t GPIO_Pin) { - if (gpio_exti_get_flag_status(GPIO_Pin) != RESET) + if (ald_gpio_exti_get_flag_status(GPIO_Pin) != RESET) { - gpio_exti_clear_flag_status(GPIO_Pin); + ald_gpio_exti_clear_flag_status(GPIO_Pin); pin_irq_hdr(GPIO_Pin); } } diff --git a/bsp/es32f0654/drivers/drv_gpio.h b/bsp/essemi/es32f0654/drivers/drv_gpio.h similarity index 100% rename from bsp/es32f0654/drivers/drv_gpio.h rename to bsp/essemi/es32f0654/drivers/drv_gpio.h diff --git a/bsp/es32f0654/drivers/drv_hwtimer.c b/bsp/essemi/es32f0654/drivers/drv_hwtimer.c similarity index 77% rename from bsp/es32f0654/drivers/drv_hwtimer.c rename to bsp/essemi/es32f0654/drivers/drv_hwtimer.c index 6eceab627be96ae7e9b5f2d67c9473f8c2965768..4d7614a3234b91746e66d907dedeee0e3e390ff4 100644 --- a/bsp/es32f0654/drivers/drv_hwtimer.c +++ b/bsp/essemi/es32f0654/drivers/drv_hwtimer.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-3-19 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -30,12 +31,12 @@ static struct es32f0_hwtimer_dev hwtimer0; void BS16T0_Handler(void) { - timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE); + ald_timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE); rt_device_hwtimer_isr(&hwtimer0.parent); if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode) { - timer_base_stop(hwtimer0.hwtimer_periph); + ald_timer_base_stop(hwtimer0.hwtimer_periph); } } #endif @@ -46,15 +47,15 @@ static struct es32f0_hwtimer_dev hwtimer1; void BS16T1_UART2_Handler(void) { /* if BS16T1 it */ - if (timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) && - timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE)) + if (ald_timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) && + ald_timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE)) { - timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE); + ald_timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE); rt_device_hwtimer_isr(&hwtimer1.parent); if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode) { - timer_base_stop(hwtimer1.hwtimer_periph); + ald_timer_base_stop(hwtimer1.hwtimer_periph); } } } @@ -66,15 +67,15 @@ static struct es32f0_hwtimer_dev hwtimer2; void BS16T2_UART3_Handler(void) { /* if BS16T2 it */ - if (timer_get_it_status(hwtimer2.hwtimer_periph, TIMER_IT_UPDATE) && - timer_get_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE)) + if (ald_timer_get_it_status(hwtimer2.hwtimer_periph, TIMER_IT_UPDATE) && + ald_timer_get_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE)) { - timer_clear_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE); + ald_timer_clear_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE); rt_device_hwtimer_isr(&hwtimer2.parent); if (HWTIMER_MODE_ONESHOT == hwtimer2.parent.mode) { - timer_base_stop(hwtimer2.hwtimer_periph); + ald_timer_base_stop(hwtimer2.hwtimer_periph); } } } @@ -86,15 +87,15 @@ static struct es32f0_hwtimer_dev hwtimer3; void BS16T3_DAC0_Handler(void) { /* if BS16T3 it */ - if (timer_get_it_status(hwtimer3.hwtimer_periph, TIMER_IT_UPDATE) && - timer_get_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE)) + if (ald_timer_get_it_status(hwtimer3.hwtimer_periph, TIMER_IT_UPDATE) && + ald_timer_get_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE)) { - timer_clear_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE); + ald_timer_clear_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE); rt_device_hwtimer_isr(&hwtimer3.parent); if (HWTIMER_MODE_ONESHOT == hwtimer3.parent.mode) { - timer_base_stop(hwtimer3.hwtimer_periph); + ald_timer_base_stop(hwtimer3.hwtimer_periph); } } } @@ -116,13 +117,13 @@ static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) if (1 == state) { - timer_base_init(hwtimer->hwtimer_periph); - timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE); + ald_timer_base_init(hwtimer->hwtimer_periph); + ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE); NVIC_EnableIRQ(hwtimer->IRQn); } - hwtimer->parent.freq = cmu_get_pclk1_clock(); - es32f0_hwtimer_info.maxfreq = cmu_get_pclk1_clock(); - es32f0_hwtimer_info.minfreq = cmu_get_pclk1_clock(); + hwtimer->parent.freq = ald_cmu_get_pclk1_clock(); + es32f0_hwtimer_info.maxfreq = ald_cmu_get_pclk1_clock(); + es32f0_hwtimer_info.minfreq = ald_cmu_get_pclk1_clock(); } static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer, @@ -134,7 +135,7 @@ static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer, RT_ASSERT(hwtimer != RT_NULL); WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt); - timer_base_start(hwtimer->hwtimer_periph); + ald_timer_base_start(hwtimer->hwtimer_periph); return RT_EOK; } @@ -145,7 +146,7 @@ static void es32f0_hwtimer_stop(rt_hwtimer_t *timer) RT_ASSERT(hwtimer != RT_NULL); - timer_base_stop(hwtimer->hwtimer_periph); + ald_timer_base_stop(hwtimer->hwtimer_periph); } static rt_uint32_t es32f0_hwtimer_count_get(rt_hwtimer_t *timer) @@ -174,14 +175,14 @@ static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer, { case HWTIMER_CTRL_FREQ_SET: freq = *(rt_uint32_t *)args; - if (freq != cmu_get_pclk1_clock()) + if (freq != ald_cmu_get_pclk1_clock()) { ret = -RT_ERROR; } break; case HWTIMER_CTRL_STOP: - timer_base_stop(hwtimer->hwtimer_periph); + ald_timer_base_stop(hwtimer->hwtimer_periph); break; default: diff --git a/bsp/es32f0654/drivers/drv_hwtimer.h b/bsp/essemi/es32f0654/drivers/drv_hwtimer.h similarity index 100% rename from bsp/es32f0654/drivers/drv_hwtimer.h rename to bsp/essemi/es32f0654/drivers/drv_hwtimer.h diff --git a/bsp/es32f0654/drivers/drv_i2c.c b/bsp/essemi/es32f0654/drivers/drv_i2c.c similarity index 86% rename from bsp/es32f0654/drivers/drv_i2c.c rename to bsp/essemi/es32f0654/drivers/drv_i2c.c index ce726ae7ad43c6642f84b6471f7e3ccd28045f3e..c40902047f6a0c2afa81c8b50f2702c96209b9fb 100644 --- a/bsp/es32f0654/drivers/drv_i2c.c +++ b/bsp/essemi/es32f0654/drivers/drv_i2c.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-01-24 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -45,10 +46,10 @@ static void _i2c_init(void) _h_i2c0.init.general_call = I2C_GENERALCALL_DISABLE; _h_i2c0.init.no_stretch = I2C_NOSTRETCH_ENABLE; - i2c_reset(&_h_i2c0); - i2c_init(&_h_i2c0); + ald_i2c_reset(&_h_i2c0); + ald_i2c_init(&_h_i2c0); /* I2C0_SCL->PB8, I2C0_SDA->PB9 */ - gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct); + ald_gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct); #endif #ifdef BSP_USING_I2C1 @@ -61,10 +62,10 @@ static void _i2c_init(void) _h_i2c1.init.general_call = I2C_GENERALCALL_DISABLE; _h_i2c1.init.no_stretch = I2C_NOSTRETCH_ENABLE; - i2c_reset(&_h_i2c1); - i2c_init(&_h_i2c1); + ald_i2c_reset(&_h_i2c1); + ald_i2c_init(&_h_i2c1); /* I2C1_SCL->PB10, I2C1_SDA->PB11 */ - gpio_init(GPIOB, GPIO_PIN_10 | GPIO_PIN_11, &gpio_instruct); + ald_gpio_init(GPIOB, GPIO_PIN_10 | GPIO_PIN_11, &gpio_instruct); #endif } @@ -81,7 +82,7 @@ static rt_size_t es32f0_master_xfer(struct rt_i2c_bus_device *bus, msg = &msgs[i]; if (msg->flags & RT_I2C_RD) { - if (i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) + if (ald_i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) { i2c_dbg("i2c bus write failed,i2c bus stop!\n"); goto out; @@ -89,7 +90,7 @@ static rt_size_t es32f0_master_xfer(struct rt_i2c_bus_device *bus, } else { - if (i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) + if (ald_i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) { i2c_dbg("i2c bus write failed,i2c bus stop!\n"); goto out; diff --git a/bsp/es32f0654/drivers/drv_i2c.h b/bsp/essemi/es32f0654/drivers/drv_i2c.h similarity index 100% rename from bsp/es32f0654/drivers/drv_i2c.h rename to bsp/essemi/es32f0654/drivers/drv_i2c.h diff --git a/bsp/essemi/es32f0654/drivers/drv_pm.c b/bsp/essemi/es32f0654/drivers/drv_pm.c new file mode 100644 index 0000000000000000000000000000000000000000..821d3bc843f138cbbeb73715912e17d5972e6de0 --- /dev/null +++ b/bsp/essemi/es32f0654/drivers/drv_pm.c @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-04-08 wangyq the first version + * 2019-11-01 wangyq adapt to the new power management interface + */ + +#include +#include +#include +#include + +#ifdef RT_USING_PM + +static void uart_console_reconfig(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config); +} + +/** + * This function will put ES32F033x into sleep mode. + * + * @param pm pointer to power manage structure + */ +static void sleep(struct rt_pm *pm, uint8_t mode) +{ + switch (mode) + { + case PM_SLEEP_MODE_NONE: + break; + + case PM_SLEEP_MODE_IDLE: + //__WFI(); + break; + + case PM_SLEEP_MODE_LIGHT: + /* Enter SLEEP Mode, Main regulator is ON */ + ald_pmu_stop1_enter(); + break; + + case PM_SLEEP_MODE_DEEP: + /* Enter STOP 2 mode */ + ald_pmu_stop2_enter(); + break; + + case PM_SLEEP_MODE_STANDBY: + /* Enter STANDBY mode */ + ald_pmu_stop2_enter(); + break; + + case PM_SLEEP_MODE_SHUTDOWN: + /* Enter SHUTDOWNN mode */ + ald_pmu_stop2_enter(); + break; + + default: + RT_ASSERT(0); + break; + } +} + +static uint8_t run_speed[PM_RUN_MODE_MAX][2] = +{ + {48, 0}, + {48, 1}, + {24, 2}, + {2, 3}, +}; + +static void run(struct rt_pm *pm, uint8_t mode) +{ + static uint8_t last_mode; + static char *run_str[] = PM_RUN_MODE_NAMES; + extern uint32_t __system_clock; + + if (mode == last_mode) + return; + last_mode = mode; + + ald_cmu_clock_config_default(); + __system_clock = 24000000; + switch (mode) + { + case PM_RUN_MODE_HIGH_SPEED: + case PM_RUN_MODE_NORMAL_SPEED: + /* hosc 12MHz, from hosc/3 pll to 48MHz */ + ald_cmu_pll1_config(CMU_PLL1_INPUT_HRC_6, CMU_PLL1_OUTPUT_48M); + /* MCLK 48MHz */ + ald_cmu_clock_config(CMU_CLOCK_PLL1, 48000000); + break; + case PM_RUN_MODE_MEDIUM_SPEED: + break; + case PM_RUN_MODE_LOW_SPEED: + ald_cmu_clock_config(CMU_CLOCK_HRC, 2000000); + break; + default: + break; + } + + /* 4. 更新外设时钟 */ + uart_console_reconfig(); + /* Re-Configure the Systick time */ + SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND); + + rt_kprintf("switch to %s mode, frequency = %d MHz\n", run_str[mode], run_speed[mode][0]); +} + +/** + * This function caculate the PM tick from OS tick + * + * @param tick OS tick + * + * @return the PM tick + */ +static rt_tick_t es32f0_pm_tick_from_os_tick(rt_tick_t tick) +{ + rt_uint32_t freq = 1; + + return (freq * tick / RT_TICK_PER_SECOND); +} + +/** + * This function caculate the OS tick from PM tick + * + * @param tick PM tick + * + * @return the OS tick + */ +static rt_tick_t es32f0_os_tick_from_pm_tick(rt_uint32_t tick) +{ + static rt_uint32_t os_tick_remain = 0; + rt_uint32_t ret, freq; + + freq = 1; + ret = (tick * RT_TICK_PER_SECOND + os_tick_remain) / freq; + + os_tick_remain += (tick * RT_TICK_PER_SECOND); + os_tick_remain %= freq; + + return ret; +} + +/** + * This function start the timer of pm + * + * @param pm Pointer to power manage structure + * @param timeout How many OS Ticks that MCU can sleep + */ +static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout) +{ + RT_ASSERT(pm != RT_NULL); + RT_ASSERT(timeout > 0); + + if (timeout != RT_TICK_MAX) + { + /* Convert OS Tick to pmtimer timeout value */ + timeout = es32f0_pm_tick_from_os_tick(timeout); + /* MAX 0xFFFF */ + if (timeout > 0xFFFF) + { + timeout = 0xFFFF; + } + } +} + +/** + * This function stop the timer of pm + * + * @param pm Pointer to power manage structure + */ +static void pm_timer_stop(struct rt_pm *pm) +{ + RT_ASSERT(pm != RT_NULL); +} + +/** + * This function calculate how many OS Ticks that MCU have suspended + * + * @param pm Pointer to power manage structure + * + * @return OS Ticks + */ +static rt_tick_t pm_timer_get_tick(struct rt_pm *pm) +{ + rt_uint32_t timer_tick; + + RT_ASSERT(pm != RT_NULL); + + timer_tick = 1; + + return es32f0_os_tick_from_pm_tick(timer_tick); +} + +/** + * This function initialize the power manager + */ +int drv_pm_hw_init(void) +{ + static const struct rt_pm_ops _ops = + { + sleep, + run, + pm_timer_start, + pm_timer_stop, + pm_timer_get_tick + }; + + rt_uint8_t timer_mask = 0; + + /* initialize timer mask */ + timer_mask = 1UL << PM_SLEEP_MODE_DEEP; + + /* initialize system pm module */ + rt_system_pm_init(&_ops, timer_mask, RT_NULL); + + return 0; +} +INIT_BOARD_EXPORT(drv_pm_hw_init); + +#endif diff --git a/bsp/es32f0654/drivers/drv_pm.h b/bsp/essemi/es32f0654/drivers/drv_pm.h similarity index 100% rename from bsp/es32f0654/drivers/drv_pm.h rename to bsp/essemi/es32f0654/drivers/drv_pm.h diff --git a/bsp/es32f0654/drivers/drv_pwm.c b/bsp/essemi/es32f0654/drivers/drv_pwm.c similarity index 79% rename from bsp/es32f0654/drivers/drv_pwm.c rename to bsp/essemi/es32f0654/drivers/drv_pwm.c index 4bb747654d2d814520d676417f96d31448931431..d324e2bbbb12c6d38a0b33e7d1b5c683c709c4a7 100644 --- a/bsp/es32f0654/drivers/drv_pwm.c +++ b/bsp/essemi/es32f0654/drivers/drv_pwm.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-03-11 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -18,7 +19,7 @@ static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns) { - uint64_t _arr = (uint64_t)cmu_get_pclk1_clock() * ns / 1000000000 / + uint64_t _arr = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 / (timer_initstruct->init.prescaler + 1); WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr); @@ -27,7 +28,7 @@ static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns) static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, uint32_t ns) { - uint64_t tmp = (uint64_t)cmu_get_pclk1_clock() * ns / 1000000000 / + uint64_t tmp = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 / (timer_initstruct->init.prescaler + 1); if (ch == TIMER_CHANNEL_1) @@ -87,11 +88,11 @@ static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void * switch (cmd) { case PWM_CMD_ENABLE: - timer_pwm_start(timer_initstruct, pwm_channel); + ald_timer_pwm_start(timer_initstruct, pwm_channel); break; case PWM_CMD_DISABLE: - timer_pwm_stop(timer_initstruct, pwm_channel); + ald_timer_pwm_stop(timer_initstruct, pwm_channel); break; case PWM_CMD_SET: @@ -105,13 +106,13 @@ static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void * while (timer_initstruct->init.period > 0xFFFF); /* update prescaler */ WRITE_REG(timer_initstruct->perh->PRES, --timer_initstruct->init.prescaler); - timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel); + ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel); pwm_set_duty(timer_initstruct, pwm_channel, cfg->pulse); timer_initstruct->perh->CCEP = _ccep; break; case PWM_CMD_GET: - cfg->pulse = timer_read_capture_value(timer_initstruct, pwm_channel) * 100 / + cfg->pulse = ald_timer_read_capture_value(timer_initstruct, pwm_channel) * 100 / READ_REG(timer_initstruct->perh->AR); break; @@ -143,14 +144,14 @@ int rt_hw_pwm_init(void) static timer_handle_t timer_initstruct0; timer_initstruct0.perh = AD16C4T0; - timer_pwm_init(&timer_initstruct0); + ald_timer_pwm_init(&timer_initstruct0); /* gpio initialization */ gpio_initstructure.func = GPIO_FUNC_2; - gpio_init(GPIOA, GPIO_PIN_8, &gpio_initstructure); - gpio_init(GPIOA, GPIO_PIN_9, &gpio_initstructure); - gpio_init(GPIOA, GPIO_PIN_10, &gpio_initstructure); - gpio_init(GPIOA, GPIO_PIN_11, &gpio_initstructure); + ald_gpio_init(GPIOA, GPIO_PIN_8, &gpio_initstructure); + ald_gpio_init(GPIOA, GPIO_PIN_9, &gpio_initstructure); + ald_gpio_init(GPIOA, GPIO_PIN_10, &gpio_initstructure); + ald_gpio_init(GPIOA, GPIO_PIN_11, &gpio_initstructure); ret = rt_device_pwm_register(&pwm_dev0, "pwm0", &es32f0_pwm_ops, &timer_initstruct0); @@ -161,14 +162,14 @@ int rt_hw_pwm_init(void) static timer_handle_t timer_initstruct1; timer_initstruct1.perh = GP16C4T0; - timer_pwm_init(&timer_initstruct1); + ald_timer_pwm_init(&timer_initstruct1); /* gpio initialization */ gpio_initstructure.func = GPIO_FUNC_2; - gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure); - gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure); - gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure); - gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure); + ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure); + ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure); + ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure); + ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure); ret = rt_device_pwm_register(&pwm_dev1, "pwm1", &es32f0_pwm_ops, &timer_initstruct1); @@ -179,12 +180,12 @@ int rt_hw_pwm_init(void) static timer_handle_t timer_initstruct2; timer_initstruct2.perh = GP16C2T0; - timer_pwm_init(&timer_initstruct2); + ald_timer_pwm_init(&timer_initstruct2); /* gpio initialization */ gpio_initstructure.func = GPIO_FUNC_2; - gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure); - gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure); + ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure); + ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure); ret = rt_device_pwm_register(&pwm_dev2, "pwm2", &es32f0_pwm_ops, &timer_initstruct2); @@ -195,12 +196,12 @@ int rt_hw_pwm_init(void) static timer_handle_t timer_initstruct3; timer_initstruct3.perh = GP16C2T1; - timer_pwm_init(&timer_initstruct3); + ald_timer_pwm_init(&timer_initstruct3); /* gpio initialization */ gpio_initstructure.func = GPIO_FUNC_3; - gpio_init(GPIOC, GPIO_PIN_6, &gpio_initstructure); - gpio_init(GPIOC, GPIO_PIN_7, &gpio_initstructure); + ald_gpio_init(GPIOC, GPIO_PIN_6, &gpio_initstructure); + ald_gpio_init(GPIOC, GPIO_PIN_7, &gpio_initstructure); ret = rt_device_pwm_register(&pwm_dev3, "pwm3", &es32f0_pwm_ops, &timer_initstruct3); diff --git a/bsp/es32f0654/drivers/drv_pwm.h b/bsp/essemi/es32f0654/drivers/drv_pwm.h similarity index 100% rename from bsp/es32f0654/drivers/drv_pwm.h rename to bsp/essemi/es32f0654/drivers/drv_pwm.h diff --git a/bsp/es32f0654/drivers/drv_rtc.c b/bsp/essemi/es32f0654/drivers/drv_rtc.c similarity index 93% rename from bsp/es32f0654/drivers/drv_rtc.c rename to bsp/essemi/es32f0654/drivers/drv_rtc.c index a16d4f179cb32d73582dc0af57ec5e1052fb4d15..32a68c3011016fd20ef6c42e446abf926dcc95fc 100644 --- a/bsp/es32f0654/drivers/drv_rtc.c +++ b/bsp/essemi/es32f0654/drivers/drv_rtc.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-03-22 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -25,7 +26,7 @@ static void __rtc_init(rtc_init_t *init) assert_param(IS_RTC_OUTPUT_SEL(init->output)); assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity)); - rtc_reset(); + ald_rtc_reset(); RTC_UNLOCK(); MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS); @@ -51,7 +52,7 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args) { case RT_DEVICE_CTRL_RTC_GET_TIME: - rtc_get_date_time(&date, &time, RTC_FORMAT_DEC); + ald_rtc_get_date_time(&date, &time, RTC_FORMAT_DEC); time_temp.tm_sec = time.second; time_temp.tm_min = time.minute; time_temp.tm_hour = time.hour; @@ -77,8 +78,8 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args) date.year = time_temp.tm_year + 1900 - 2000; date.month = time_temp.tm_mon + 1; date.day = time_temp.tm_mday; - rtc_set_time(&time, RTC_FORMAT_DEC); - rtc_set_date(&date, RTC_FORMAT_DEC); + ald_rtc_set_time(&time, RTC_FORMAT_DEC); + ald_rtc_set_date(&date, RTC_FORMAT_DEC); /* start RTC */ RTC_UNLOCK(); SET_BIT(RTC->CON, RTC_CON_GO_MSK); @@ -118,7 +119,7 @@ int rt_hw_rtc_init(void) /* enable external 32.768kHz */ CMU_LOSC_ENABLE(); - cmu_losc_safe_config(ENABLE); + ald_cmu_losc_safe_config(ENABLE); /* set default time */ RTC_UNLOCK(); WRITE_REG(RTC->TIME, 0x134251); diff --git a/bsp/es32f0654/drivers/drv_rtc.h b/bsp/essemi/es32f0654/drivers/drv_rtc.h similarity index 100% rename from bsp/es32f0654/drivers/drv_rtc.h rename to bsp/essemi/es32f0654/drivers/drv_rtc.h diff --git a/bsp/es32f0654/drivers/drv_spi.c b/bsp/essemi/es32f0654/drivers/drv_spi.c similarity index 82% rename from bsp/es32f0654/drivers/drv_spi.c rename to bsp/essemi/es32f0654/drivers/drv_spi.c index f79258df3ac95db68008f9266192e639a1683a14..a029c6c772849e6809371425574ecaf7dd86a7e8 100644 --- a/bsp/es32f0654/drivers/drv_spi.c +++ b/bsp/essemi/es32f0654/drivers/drv_spi.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-01-24 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -80,14 +81,14 @@ rt_err_t spi_configure(struct rt_spi_device *device, } /* config spi clock */ - if (cfg->max_hz >= cmu_get_pclk1_clock() / 2) + if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 2) { /* pclk1 max speed 48MHz, spi master max speed 10MHz */ - if (cmu_get_pclk1_clock() / 2 <= 10000000) + if (ald_cmu_get_pclk1_clock() / 2 <= 10000000) { hspi->init.baud = SPI_BAUD_2; } - else if (cmu_get_pclk1_clock() / 4 <= 10000000) + else if (ald_cmu_get_pclk1_clock() / 4 <= 10000000) { hspi->init.baud = SPI_BAUD_4; } @@ -96,10 +97,10 @@ rt_err_t spi_configure(struct rt_spi_device *device, hspi->init.baud = SPI_BAUD_8; } } - else if (cfg->max_hz >= cmu_get_pclk1_clock() / 4) + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 4) { /* pclk1 max speed 48MHz, spi master max speed 10MHz */ - if (cmu_get_pclk1_clock() / 4 <= 10000000) + if (ald_cmu_get_pclk1_clock() / 4 <= 10000000) { hspi->init.baud = SPI_BAUD_4; } @@ -108,23 +109,23 @@ rt_err_t spi_configure(struct rt_spi_device *device, hspi->init.baud = SPI_BAUD_8; } } - else if (cfg->max_hz >= cmu_get_pclk1_clock() / 8) + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 8) { hspi->init.baud = SPI_BAUD_8; } - else if (cfg->max_hz >= cmu_get_pclk1_clock() / 16) + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 16) { hspi->init.baud = SPI_BAUD_16; } - else if (cfg->max_hz >= cmu_get_pclk1_clock() / 32) + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 32) { hspi->init.baud = SPI_BAUD_32; } - else if (cfg->max_hz >= cmu_get_pclk1_clock() / 64) + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 64) { hspi->init.baud = SPI_BAUD_64; } - else if (cfg->max_hz >= cmu_get_pclk1_clock() / 128) + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 128) { hspi->init.baud = SPI_BAUD_128; } @@ -132,7 +133,7 @@ rt_err_t spi_configure(struct rt_spi_device *device, { hspi->init.baud = SPI_BAUD_256; } - spi_init(hspi); + ald_spi_init(hspi); return RT_EOK; } @@ -157,7 +158,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * { rt_pin_write(cs->pin, 0); } - res = spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); + res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); if (message->cs_release) { rt_pin_write(cs->pin, 1); @@ -173,7 +174,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * { rt_pin_write(cs->pin, 0); } - res = spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); + res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); if (message->cs_release) { rt_pin_write(cs->pin, 1); @@ -189,8 +190,8 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message * { rt_pin_write(cs->pin, 0); } - res = spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, - (rt_int32_t)message->length, SPITIMEOUT); + res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, + (rt_int32_t)message->length, SPITIMEOUT); if (message->cs_release) { rt_pin_write(cs->pin, 1); @@ -230,11 +231,11 @@ int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name) gpio_instruct.flt = GPIO_FILTER_DISABLE; /* PB3->SPI0_SCK, PB5->SPI0_MOSI */ - gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct); + ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct); /* PB4->SPI0_MISO */ gpio_instruct.mode = GPIO_MODE_INPUT; - gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct); + ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct); } else if (SPIx == SPI1) { @@ -250,11 +251,11 @@ int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name) gpio_instruct.flt = GPIO_FILTER_DISABLE; /* PB13->SPI1_SCK, PB15->SPI1_MOSI */ - gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct); + ald_gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct); /* PB14->SPI1_MISO */ gpio_instruct.mode = GPIO_MODE_INPUT; - gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct); + ald_gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct); } else { diff --git a/bsp/es32f0654/drivers/drv_spi.h b/bsp/essemi/es32f0654/drivers/drv_spi.h similarity index 100% rename from bsp/es32f0654/drivers/drv_spi.h rename to bsp/essemi/es32f0654/drivers/drv_spi.h diff --git a/bsp/es32f0654/drivers/drv_spiflash.c b/bsp/essemi/es32f0654/drivers/drv_spiflash.c similarity index 92% rename from bsp/es32f0654/drivers/drv_spiflash.c rename to bsp/essemi/es32f0654/drivers/drv_spiflash.c index 0ed0dcc4458a63bc230b265b655f0290dc87a162..c84fe1be78c063358e9b93e48bc8ee3314c033c5 100644 --- a/bsp/es32f0654/drivers/drv_spiflash.c +++ b/bsp/essemi/es32f0654/drivers/drv_spiflash.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-02-15 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include diff --git a/bsp/es32f0654/drivers/drv_spiflash.h b/bsp/essemi/es32f0654/drivers/drv_spiflash.h similarity index 100% rename from bsp/es32f0654/drivers/drv_spiflash.h rename to bsp/essemi/es32f0654/drivers/drv_spiflash.h diff --git a/bsp/es32f0654/drivers/drv_uart.c b/bsp/essemi/es32f0654/drivers/drv_uart.c similarity index 90% rename from bsp/es32f0654/drivers/drv_uart.c rename to bsp/essemi/es32f0654/drivers/drv_uart.c index 776f1de9ad3c695b9bb426bd7a8ecc5c9b3a555b..4ebd18f826389393e36d87ded7418803db58ac5d 100644 --- a/bsp/es32f0654/drivers/drv_uart.c +++ b/bsp/essemi/es32f0654/drivers/drv_uart.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2019-01-23 wangyq the first version + * 2019-11-01 wangyq update libraries */ #include @@ -43,38 +44,38 @@ static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial #ifdef BSP_USING_UART0 gpio_initstructure.func = GPIO_FUNC_3; - gpio_init(GPIOB, GPIO_PIN_10, &gpio_initstructure); + ald_gpio_init(GPIOB, GPIO_PIN_10, &gpio_initstructure); /* Initialize rx pin ,the same as txpin except mode */ gpio_initstructure.mode = GPIO_MODE_INPUT; - gpio_init(GPIOB, GPIO_PIN_11, &gpio_initstructure); + ald_gpio_init(GPIOB, GPIO_PIN_11, &gpio_initstructure); #endif /* uart0 gpio init */ #ifdef BSP_USING_UART1 gpio_initstructure.func = GPIO_FUNC_3; - gpio_init(GPIOC, GPIO_PIN_10, &gpio_initstructure); + ald_gpio_init(GPIOC, GPIO_PIN_10, &gpio_initstructure); /* Initialize rx pin ,the same as txpin except mode */ gpio_initstructure.mode = GPIO_MODE_INPUT; - gpio_init(GPIOC, GPIO_PIN_11, &gpio_initstructure); + ald_gpio_init(GPIOC, GPIO_PIN_11, &gpio_initstructure); #endif /* uart1 gpio init */ #ifdef BSP_USING_UART2 gpio_initstructure.func = GPIO_FUNC_5; - gpio_init(GPIOC, GPIO_PIN_12, &gpio_initstructure); + ald_gpio_init(GPIOC, GPIO_PIN_12, &gpio_initstructure); /* Initialize rx pin ,the same as txpin except mode */ gpio_initstructure.mode = GPIO_MODE_INPUT; - gpio_init(GPIOD, GPIO_PIN_2, &gpio_initstructure); + ald_gpio_init(GPIOD, GPIO_PIN_2, &gpio_initstructure); #endif /* uart2 gpio init */ #ifdef BSP_USING_UART3 gpio_initstructure.func = GPIO_FUNC_4; - gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstructure); + ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstructure); /* Initialize rx pin ,the same as txpin except mode */ gpio_initstructure.mode = GPIO_MODE_INPUT; - gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstructure); + ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstructure); #endif /* uart3 gpio init */ uart->huart.init.mode = UART_MODE_UART; @@ -82,7 +83,7 @@ static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial uart->huart.init.word_length = (uart_word_length_t)(cfg->data_bits - 5); uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity); uart->huart.init.fctl = UART_HW_FLOW_CTL_DISABLE; - uart_init(&uart->huart); + ald_uart_init(&uart->huart); if (cfg->bit_order == BIT_ORDER_MSB) { @@ -103,7 +104,7 @@ static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial } /* enable rx int */ - uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); + ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); return RT_EOK; } @@ -120,14 +121,14 @@ static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void * /* disable rx irq */ NVIC_DisableIRQ(uart->irq); /* disable interrupt */ - uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE); + ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ NVIC_EnableIRQ(uart->irq); /* enable interrupt */ - uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); + ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE); break; } diff --git a/bsp/es32f0654/drivers/drv_uart.h b/bsp/essemi/es32f0654/drivers/drv_uart.h similarity index 100% rename from bsp/es32f0654/drivers/drv_uart.h rename to bsp/essemi/es32f0654/drivers/drv_uart.h diff --git a/bsp/es32f0654/drivers/linker_scripts/link.sct b/bsp/essemi/es32f0654/drivers/linker_scripts/link.sct similarity index 100% rename from bsp/es32f0654/drivers/linker_scripts/link.sct rename to bsp/essemi/es32f0654/drivers/linker_scripts/link.sct diff --git a/bsp/es32f0654/figures/ES-PDS-ES32F0654-V1.1.jpg b/bsp/essemi/es32f0654/figures/ES-PDS-ES32F0654-V1.1.jpg similarity index 100% rename from bsp/es32f0654/figures/ES-PDS-ES32F0654-V1.1.jpg rename to bsp/essemi/es32f0654/figures/ES-PDS-ES32F0654-V1.1.jpg diff --git a/bsp/es32f0654/figures/ESLinkII-mini.jpg b/bsp/essemi/es32f0654/figures/ESLinkII-mini.jpg similarity index 100% rename from bsp/es32f0654/figures/ESLinkII-mini.jpg rename to bsp/essemi/es32f0654/figures/ESLinkII-mini.jpg diff --git a/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h new file mode 100644 index 0000000000000000000000000000000000000000..645d1ff801340d0295408f37f927435cc5648918 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Include/es32f065x.h @@ -0,0 +1,6631 @@ +/** + ********************************************************************************* + * + * @file es32f065x.h + * @brief ES32F065x Device Head File + * + * @version V1.0 + * @date 07 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ES32F0XX_H__ +#define __ES32F0XX_H__ + + +#define __I volatile const /* defines 'read only' permissions */ +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +#define __CHECK_DEVICE_DEFINES +#define __NVIC_PRIO_BITS 2U +#define __CM0_REV 0x0000U +#define __Vendor_SysTickConfig 0U + +typedef enum IRQn { + /* Cortex-M0 processor cxceptions index */ + Reset_IRQn = -15, + NMI_IRQn = -14, + HardFault_IRQn = -13, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + /* es32f0xx specific interrupt index */ + WWDG_IWDG_IRQn = 0, + LVD_IRQn = 1, + RTC_TSENSE_IRQn = 2, + CRYPT_TRNG_IRQn = 3, + CMU_IRQn = 4, + EXTI0_3_IRQn = 5, + EXTI4_7_IRQn = 6, + EXTI8_11_IRQn = 7, + EXTI12_15_IRQn = 8, + DMA_IRQn = 9, + CAN0_IRQn = 10, + LPTIM0_SPI2_IRQn = 11, + ADC_ACMP_IRQn = 12, + AD16C4T0_BRK_UP_TRIG_COM_IRQn = 13, + AD16C4T0_CC_IRQn = 14, + BS16T0_IRQn = 15, + GP16C2T0_IRQn = 17, + GP16C2T1_IRQn = 18, + BS16T1_UART2_IRQn = 19, + BS16T2_UART3_IRQn = 20, + GP16C4T0_LCD_IRQn = 21, + BS16T3_DAC0_IRQn = 22, + I2C0_IRQn = 23, + I2C1_IRQn = 24, + SPI0_IRQn = 25, + SPI1_IRQn = 26, + UART0_IRQn = 27, + UART1_IRQn = 28, + USART0_IRQn = 29, + USART1_IRQn = 30, + LPUART0_IRQn = 31, +} IRQn_Type; + + +#include +#include "core_cm0.h" + +#if defined (__CC_ARM) +#pragma anon_unions +#endif + +/* Peripheral register define */ + +/****************** Bit definition for SYSCFG_PROT register ************************/ + +#define SYSCFG_PROT_KEY_POSS 1U +#define SYSCFG_PROT_KEY_POSE 31U +#define SYSCFG_PROT_KEY_MSK BITS(SYSCFG_PROT_KEY_POSS,SYSCFG_PROT_KEY_POSE) + +#define SYSCFG_PROT_PROT_POS 0U +#define SYSCFG_PROT_PROT_MSK BIT(SYSCFG_PROT_PROT_POS) + +/****************** Bit definition for SYSCFG_MEMRMP register ************************/ + +#define SYSCFG_MEMRMP_VTOEN_POS 16U +#define SYSCFG_MEMRMP_VTOEN_MSK BIT(SYSCFG_MEMRMP_VTOEN_POS) + +#define SYSCFG_MEMRMP_BFRMPEN_POS 8U +#define SYSCFG_MEMRMP_BFRMPEN_MSK BIT(SYSCFG_MEMRMP_BFRMPEN_POS) + +#define SYSCFG_MEMRMP_BRRMPEN_POS 0U +#define SYSCFG_MEMRMP_BRRMPEN_MSK BIT(SYSCFG_MEMRMP_BRRMPEN_POS) + +/****************** Bit definition for SYSCFG_VTOR register ************************/ + +#define SYSCFG_VTOR_VTO_POSS 0U +#define SYSCFG_VTOR_VTO_POSE 29U +#define SYSCFG_VTOR_VTO_MSK BITS(SYSCFG_VTOR_VTO_POSS,SYSCFG_VTOR_VTO_POSE) + +typedef struct +{ + __IO uint32_t PROT; + __IO uint32_t MEMRMP; + __IO uint32_t VTOR; +} SYSCFG_TypeDef; + +/****************** Bit definition for MSC_FLASHKEY register ************************/ + +#define MSC_FLASHKEY_STATUS_POSS 0U +#define MSC_FLASHKEY_STATUS_POSE 1U +#define MSC_FLASHKEY_STATUS_MSK BITS(MSC_FLASHKEY_STATUS_POSS,MSC_FLASHKEY_STATUS_POSE) + +/****************** Bit definition for MSC_INFOKEY register ************************/ + +#define MSC_INFOKEY_STATUS_POSS 0U +#define MSC_INFOKEY_STATUS_POSE 1U +#define MSC_INFOKEY_STATUS_MSK BITS(MSC_INFOKEY_STATUS_POSS,MSC_INFOKEY_STATUS_POSE) + +/****************** Bit definition for MSC_FLASHADDR register ************************/ + +#define MSC_FLASHADDR_IFREN_POS 18U +#define MSC_FLASHADDR_IFREN_MSK BIT(MSC_FLASHADDR_IFREN_POS) + +#define MSC_FLASHADDR_ADDR_POSS 0U +#define MSC_FLASHADDR_ADDR_POSE 17U +#define MSC_FLASHADDR_ADDR_MSK BITS(MSC_FLASHADDR_ADDR_POSS,MSC_FLASHADDR_ADDR_POSE) + +/****************** Bit definition for MSC_FLASHFIFO register ************************/ + +#define MSC_FLASHFIFO_FIFO_POSS 0U +#define MSC_FLASHFIFO_FIFO_POSE 31U +#define MSC_FLASHFIFO_FIFO_MSK BITS(MSC_FLASHFIFO_FIFO_POSS,MSC_FLASHFIFO_FIFO_POSE) + +/****************** Bit definition for MSC_FLASHDL register ************************/ + +#define MSC_FLASHDL_DATAL_POSS 0U +#define MSC_FLASHDL_DATAL_POSE 31U +#define MSC_FLASHDL_DATAL_MSK BITS(MSC_FLASHDL_DATAL_POSS,MSC_FLASHDL_DATAL_POSE) + +/****************** Bit definition for MSC_FLASHDH register ************************/ + +#define MSC_FLASHDH_DATAH_POSS 0U +#define MSC_FLASHDH_DATAH_POSE 31U +#define MSC_FLASHDH_DATAH_MSK BITS(MSC_FLASHDH_DATAH_POSS,MSC_FLASHDH_DATAH_POSE) + +/****************** Bit definition for MSC_FLASHCMD register ************************/ + +#define MSC_FLASHCMD_CMD_POSS 0U +#define MSC_FLASHCMD_CMD_POSE 31U +#define MSC_FLASHCMD_CMD_MSK BITS(MSC_FLASHCMD_CMD_POSS,MSC_FLASHCMD_CMD_POSE) + +/****************** Bit definition for MSC_FLASHCR register ************************/ + +#define MSC_FLASHCR_FIFOEN_POS 5U +#define MSC_FLASHCR_FIFOEN_MSK BIT(MSC_FLASHCR_FIFOEN_POS) + +#define MSC_FLASHCR_FLASHREQ_POS 4U +#define MSC_FLASHCR_FLASHREQ_MSK BIT(MSC_FLASHCR_FLASHREQ_POS) + +#define MSC_FLASHCR_IAPRST_POS 1U +#define MSC_FLASHCR_IAPRST_MSK BIT(MSC_FLASHCR_IAPRST_POS) + +#define MSC_FLASHCR_IAPEN_POS 0U +#define MSC_FLASHCR_IAPEN_MSK BIT(MSC_FLASHCR_IAPEN_POS) + +/****************** Bit definition for MSC_FLASHSR register ************************/ + +#define MSC_FLASHSR_TIMEOUT_POS 7U +#define MSC_FLASHSR_TIMEOUT_MSK BIT(MSC_FLASHSR_TIMEOUT_POS) + +#define MSC_FLASHSR_PROG_POS 6U +#define MSC_FLASHSR_PROG_MSK BIT(MSC_FLASHSR_PROG_POS) + +#define MSC_FLASHSR_SERA_POS 5U +#define MSC_FLASHSR_SERA_MSK BIT(MSC_FLASHSR_SERA_POS) + +#define MSC_FLASHSR_MASE_POS 4U +#define MSC_FLASHSR_MASE_MSK BIT(MSC_FLASHSR_MASE_POS) + +#define MSC_FLASHSR_ADDR_OV_POS 3U +#define MSC_FLASHSR_ADDR_OV_MSK BIT(MSC_FLASHSR_ADDR_OV_POS) + +#define MSC_FLASHSR_WRP_FLAG_POS 2U +#define MSC_FLASHSR_WRP_FLAG_MSK BIT(MSC_FLASHSR_WRP_FLAG_POS) + +#define MSC_FLASHSR_BUSY_POS 1U +#define MSC_FLASHSR_BUSY_MSK BIT(MSC_FLASHSR_BUSY_POS) + +#define MSC_FLASHSR_FLASHACK_POS 0U +#define MSC_FLASHSR_FLASHACK_MSK BIT(MSC_FLASHSR_FLASHACK_POS) + +/****************** Bit definition for MSC_FLASHPL register ************************/ + +#define MSC_FLASHPL_PROG_LEN_POSS 0U +#define MSC_FLASHPL_PROG_LEN_POSE 15U +#define MSC_FLASHPL_PROG_LEN_MSK BITS(MSC_FLASHPL_PROG_LEN_POSS,MSC_FLASHPL_PROG_LEN_POSE) + +/****************** Bit definition for MSC_MEMWAIT register ************************/ + +#define MSC_MEMWAIT_SRAM_W_POSS 8U +#define MSC_MEMWAIT_SRAM_W_POSE 9U +#define MSC_MEMWAIT_SRAM_W_MSK BITS(MSC_MEMWAIT_SRAM_W_POSS,MSC_MEMWAIT_SRAM_W_POSE) + +#define MSC_MEMWAIT_FLASH_W_POSS 0U +#define MSC_MEMWAIT_FLASH_W_POSE 3U +#define MSC_MEMWAIT_FLASH_W_MSK BITS(MSC_MEMWAIT_FLASH_W_POSS,MSC_MEMWAIT_FLASH_W_POSE) + +typedef struct +{ + __IO uint32_t FLASHKEY; + __IO uint32_t INFOKEY; + __IO uint32_t FLASHADDR; + __O uint32_t FLASHFIFO; + __IO uint32_t FLASHDL; + __IO uint32_t FLASHDH; + __O uint32_t FLASHCMD; + __IO uint32_t FLASHCR; + __I uint32_t FLASHSR; + __IO uint32_t FLASHPL; + __IO uint32_t MEMWAIT; +} MSC_TypeDef; + +/****************** Bit definition for BKPC_PROT register ************************/ + +#define BKPC_PROT_KEY_POSS 1U +#define BKPC_PROT_KEY_POSE 31U +#define BKPC_PROT_KEY_MSK BITS(BKPC_PROT_KEY_POSS,BKPC_PROT_KEY_POSE) + +#define BKPC_PROT_PROT_POS 0U +#define BKPC_PROT_PROT_MSK BIT(BKPC_PROT_PROT_POS) + +/****************** Bit definition for BKPC_CR register ************************/ + +#define BKPC_CR_LDO_VSEL_POSS 24U +#define BKPC_CR_LDO_VSEL_POSE 26U +#define BKPC_CR_LDO_VSEL_MSK BITS(BKPC_CR_LDO_VSEL_POSS,BKPC_CR_LDO_VSEL_POSE) + +#define BKPC_CR_MT_STDB_POS 19U +#define BKPC_CR_MT_STDB_MSK BIT(BKPC_CR_MT_STDB_POS) + +#define BKPC_CR_VR1P5_VSEL_POSS 16U +#define BKPC_CR_VR1P5_VSEL_POSE 18U +#define BKPC_CR_VR1P5_VSEL_MSK BITS(BKPC_CR_VR1P5_VSEL_POSS,BKPC_CR_VR1P5_VSEL_POSE) + +#define BKPC_CR_TC_PWRDWN_POS 13U +#define BKPC_CR_TC_PWRDWN_MSK BIT(BKPC_CR_TC_PWRDWN_POS) + +#define BKPC_CR_WKPOL_POS 12U +#define BKPC_CR_WKPOL_MSK BIT(BKPC_CR_WKPOL_POS) + +#define BKPC_CR_WKPS_POSS 9U +#define BKPC_CR_WKPS_POSE 11U +#define BKPC_CR_WKPS_MSK BITS(BKPC_CR_WKPS_POSS,BKPC_CR_WKPS_POSE) + +#define BKPC_CR_WKPEN_POS 8U +#define BKPC_CR_WKPEN_MSK BIT(BKPC_CR_WKPEN_POS) + +#define BKPC_CR_LRCEN_POS 2U +#define BKPC_CR_LRCEN_MSK BIT(BKPC_CR_LRCEN_POS) + +#define BKPC_CR_LOSMEN_POS 1U +#define BKPC_CR_LOSMEN_MSK BIT(BKPC_CR_LOSMEN_POS) + +#define BKPC_CR_LOSCEN_POS 0U +#define BKPC_CR_LOSCEN_MSK BIT(BKPC_CR_LOSCEN_POS) + +/****************** Bit definition for BKPC_PCCR register ************************/ + +#define BKPC_PCCR_TSENSECS_POSS 4U +#define BKPC_PCCR_TSENSECS_POSE 5U +#define BKPC_PCCR_TSENSECS_MSK BITS(BKPC_PCCR_TSENSECS_POSS,BKPC_PCCR_TSENSECS_POSE) + +#define BKPC_PCCR_RTCCS_POSS 0U +#define BKPC_PCCR_RTCCS_POSE 1U +#define BKPC_PCCR_RTCCS_MSK BITS(BKPC_PCCR_RTCCS_POSS,BKPC_PCCR_RTCCS_POSE) + +/****************** Bit definition for BKPC_PCR register ************************/ + +#define BKPC_PCR_BORS_POSS 1U +#define BKPC_PCR_BORS_POSE 4U +#define BKPC_PCR_BORS_MSK BITS(BKPC_PCR_BORS_POSS,BKPC_PCR_BORS_POSE) + +#define BKPC_PCR_BOREN_POS 0U +#define BKPC_PCR_BOREN_MSK BIT(BKPC_PCR_BOREN_POS) + +typedef struct +{ + __IO uint32_t PROT; + __IO uint32_t CR; + __IO uint32_t PCCR; + __IO uint32_t PCR; +} BKPC_TypeDef; + +/****************** Bit definition for PMU_CR register ************************/ + +#define PMU_CR_MTSTOP_POS 21U +#define PMU_CR_MTSTOP_MSK BIT(PMU_CR_MTSTOP_POS) + +#define PMU_CR_LPSTOP_POS 20U +#define PMU_CR_LPSTOP_MSK BIT(PMU_CR_LPSTOP_POS) + +#define PMU_CR_LPRUN_POS 19U +#define PMU_CR_LPRUN_MSK BIT(PMU_CR_LPRUN_POS) + +#define PMU_CR_LPVS_POSS 16U +#define PMU_CR_LPVS_POSE 18U +#define PMU_CR_LPVS_MSK BITS(PMU_CR_LPVS_POSS,PMU_CR_LPVS_POSE) + +#define PMU_CR_WKPS_POSS 9U +#define PMU_CR_WKPS_POSE 11U +#define PMU_CR_WKPS_MSK BITS(PMU_CR_WKPS_POSS,PMU_CR_WKPS_POSE) + +#define PMU_CR_WKPEN_POS 8U +#define PMU_CR_WKPEN_MSK BIT(PMU_CR_WKPEN_POS) + +#define PMU_CR_CSTANDBYF_POS 3U +#define PMU_CR_CSTANDBYF_MSK BIT(PMU_CR_CSTANDBYF_POS) + +#define PMU_CR_CWUF_POS 2U +#define PMU_CR_CWUF_MSK BIT(PMU_CR_CWUF_POS) + +#define PMU_CR_LPM_POSS 0U +#define PMU_CR_LPM_POSE 1U +#define PMU_CR_LPM_MSK BITS(PMU_CR_LPM_POSS,PMU_CR_LPM_POSE) + +/****************** Bit definition for PMU_SR register ************************/ + +#define PMU_SR_STANDBYF_POS 1U +#define PMU_SR_STANDBYF_MSK BIT(PMU_SR_STANDBYF_POS) + +#define PMU_SR_WUF_POS 0U +#define PMU_SR_WUF_MSK BIT(PMU_SR_WUF_POS) + +/****************** Bit definition for PMU_LVDCR register ************************/ + +#define PMU_LVDCR_LVDO_POS 15U +#define PMU_LVDCR_LVDO_MSK BIT(PMU_LVDCR_LVDO_POS) + +#define PMU_LVDCR_LVDFLT_POS 11U +#define PMU_LVDCR_LVDFLT_MSK BIT(PMU_LVDCR_LVDFLT_POS) + +#define PMU_LVDCR_LVIFS_POSS 8U +#define PMU_LVDCR_LVIFS_POSE 10U +#define PMU_LVDCR_LVIFS_MSK BITS(PMU_LVDCR_LVIFS_POSS,PMU_LVDCR_LVIFS_POSE) + +#define PMU_LVDCR_LVDS_POSS 4U +#define PMU_LVDCR_LVDS_POSE 7U +#define PMU_LVDCR_LVDS_MSK BITS(PMU_LVDCR_LVDS_POSS,PMU_LVDCR_LVDS_POSE) + +#define PMU_LVDCR_LVDCIF_POS 3U +#define PMU_LVDCR_LVDCIF_MSK BIT(PMU_LVDCR_LVDCIF_POS) + +#define PMU_LVDCR_LVDIF_POS 2U +#define PMU_LVDCR_LVDIF_MSK BIT(PMU_LVDCR_LVDIF_POS) + +#define PMU_LVDCR_LVDIE_POS 1U +#define PMU_LVDCR_LVDIE_MSK BIT(PMU_LVDCR_LVDIE_POS) + +#define PMU_LVDCR_LVDEN_POS 0U +#define PMU_LVDCR_LVDEN_MSK BIT(PMU_LVDCR_LVDEN_POS) + +/****************** Bit definition for PMU_PWRCR register ************************/ + +#define PMU_PWRCR_BXCAN_POS 4U +#define PMU_PWRCR_BXCAN_MSK BIT(PMU_PWRCR_BXCAN_POS) + +#define PMU_PWRCR_SRAM_POSS 0U +#define PMU_PWRCR_SRAM_POSE 1U +#define PMU_PWRCR_SRAM_MSK BITS(PMU_PWRCR_SRAM_POSS,PMU_PWRCR_SRAM_POSE) + +/****************** Bit definition for PMU_TWUR register ************************/ + +#define PMU_TWUR_TWU_POSS 0U +#define PMU_TWUR_TWU_POSE 11U +#define PMU_TWUR_TWU_MSK BITS(PMU_TWUR_TWU_POSS,PMU_TWUR_TWU_POSE) + +/****************** Bit definition for PMU_VREFCR register ************************/ + +#define PMU_VREFCR_FLTS_POSS 13U +#define PMU_VREFCR_FLTS_POSE 14U +#define PMU_VREFCR_FLTS_MSK BITS(PMU_VREFCR_FLTS_POSS,PMU_VREFCR_FLTS_POSE) + +#define PMU_VREFCR_CHOPCS_POSS 10U +#define PMU_VREFCR_CHOPCS_POSE 12U +#define PMU_VREFCR_CHOPCS_MSK BITS(PMU_VREFCR_CHOPCS_POSS,PMU_VREFCR_CHOPCS_POSE) + +#define PMU_VREFCR_CHOP1EN_POS 9U +#define PMU_VREFCR_CHOP1EN_MSK BIT(PMU_VREFCR_CHOP1EN_POS) + +#define PMU_VREFCR_CHOPEN_POS 8U +#define PMU_VREFCR_CHOPEN_MSK BIT(PMU_VREFCR_CHOPEN_POS) + +#define PMU_VREFCR_VREFEN_POS 0U +#define PMU_VREFCR_VREFEN_MSK BIT(PMU_VREFCR_VREFEN_POS) + +typedef struct +{ + __IO uint32_t CR; + __I uint32_t SR; + __IO uint32_t LVDCR; + __IO uint32_t PWRCR; + __IO uint32_t TWUR; + __IO uint32_t VREFCR; +} PMU_TypeDef; + +/****************** Bit definition for RMU_CR register ************************/ + +#define RMU_CR_BORVS_POSS 4U +#define RMU_CR_BORVS_POSE 7U +#define RMU_CR_BORVS_MSK BITS(RMU_CR_BORVS_POSS,RMU_CR_BORVS_POSE) + +#define RMU_CR_BORFLT_POSS 1U +#define RMU_CR_BORFLT_POSE 3U +#define RMU_CR_BORFLT_MSK BITS(RMU_CR_BORFLT_POSS,RMU_CR_BORFLT_POSE) + +#define RMU_CR_BOREN_POS 0U +#define RMU_CR_BOREN_MSK BIT(RMU_CR_BOREN_POS) + +/****************** Bit definition for RMU_RSTSR register ************************/ + +#define RMU_RSTSR_CFGERR_POS 16U +#define RMU_RSTSR_CFGERR_MSK BIT(RMU_RSTSR_CFGERR_POS) + +#define RMU_RSTSR_CFG_POS 10U +#define RMU_RSTSR_CFG_MSK BIT(RMU_RSTSR_CFG_POS) + +#define RMU_RSTSR_CPU_POS 9U +#define RMU_RSTSR_CPU_MSK BIT(RMU_RSTSR_CPU_POS) + +#define RMU_RSTSR_MCU_POS 8U +#define RMU_RSTSR_MCU_MSK BIT(RMU_RSTSR_MCU_POS) + +#define RMU_RSTSR_CHIP_POS 7U +#define RMU_RSTSR_CHIP_MSK BIT(RMU_RSTSR_CHIP_POS) + +#define RMU_RSTSR_LOCKUP_POS 6U +#define RMU_RSTSR_LOCKUP_MSK BIT(RMU_RSTSR_LOCKUP_POS) + +#define RMU_RSTSR_WWDT_POS 5U +#define RMU_RSTSR_WWDT_MSK BIT(RMU_RSTSR_WWDT_POS) + +#define RMU_RSTSR_IWDT_POS 4U +#define RMU_RSTSR_IWDT_MSK BIT(RMU_RSTSR_IWDT_POS) + +#define RMU_RSTSR_NMRST_POS 3U +#define RMU_RSTSR_NMRST_MSK BIT(RMU_RSTSR_NMRST_POS) + +#define RMU_RSTSR_BOR_POS 2U +#define RMU_RSTSR_BOR_MSK BIT(RMU_RSTSR_BOR_POS) + +#define RMU_RSTSR_WAKEUP_POS 1U +#define RMU_RSTSR_WAKEUP_MSK BIT(RMU_RSTSR_WAKEUP_POS) + +#define RMU_RSTSR_POR_POS 0U +#define RMU_RSTSR_POR_MSK BIT(RMU_RSTSR_POR_POS) + +/****************** Bit definition for RMU_CRSTSR register ************************/ + +#define RMU_CRSTSR_CFG_POS 10U +#define RMU_CRSTSR_CFG_MSK BIT(RMU_CRSTSR_CFG_POS) + +#define RMU_CRSTSR_CPU_POS 9U +#define RMU_CRSTSR_CPU_MSK BIT(RMU_CRSTSR_CPU_POS) + +#define RMU_CRSTSR_MCU_POS 8U +#define RMU_CRSTSR_MCU_MSK BIT(RMU_CRSTSR_MCU_POS) + +#define RMU_CRSTSR_CHIP_POS 7U +#define RMU_CRSTSR_CHIP_MSK BIT(RMU_CRSTSR_CHIP_POS) + +#define RMU_CRSTSR_LOCKUP_POS 6U +#define RMU_CRSTSR_LOCKUP_MSK BIT(RMU_CRSTSR_LOCKUP_POS) + +#define RMU_CRSTSR_WWDT_POS 5U +#define RMU_CRSTSR_WWDT_MSK BIT(RMU_CRSTSR_WWDT_POS) + +#define RMU_CRSTSR_IWDT_POS 4U +#define RMU_CRSTSR_IWDT_MSK BIT(RMU_CRSTSR_IWDT_POS) + +#define RMU_CRSTSR_NMRST_POS 3U +#define RMU_CRSTSR_NMRST_MSK BIT(RMU_CRSTSR_NMRST_POS) + +#define RMU_CRSTSR_BOR_POS 2U +#define RMU_CRSTSR_BOR_MSK BIT(RMU_CRSTSR_BOR_POS) + +#define RMU_CRSTSR_WAKEUP_POS 1U +#define RMU_CRSTSR_WAKEUP_MSK BIT(RMU_CRSTSR_WAKEUP_POS) + +#define RMU_CRSTSR_POR_POS 0U +#define RMU_CRSTSR_POR_MSK BIT(RMU_CRSTSR_POR_POS) + +/****************** Bit definition for RMU_AHB1RSTR register ************************/ + +#define RMU_AHB1RSTR_PISRST_POS 5U +#define RMU_AHB1RSTR_PISRST_MSK BIT(RMU_AHB1RSTR_PISRST_POS) + +#define RMU_AHB1RSTR_TRNGRST_POS 4U +#define RMU_AHB1RSTR_TRNGRST_MSK BIT(RMU_AHB1RSTR_TRNGRST_POS) + +#define RMU_AHB1RSTR_CRYPTRST_POS 3U +#define RMU_AHB1RSTR_CRYPTRST_MSK BIT(RMU_AHB1RSTR_CRYPTRST_POS) + +#define RMU_AHB1RSTR_CALCRST_POS 2U +#define RMU_AHB1RSTR_CALCRST_MSK BIT(RMU_AHB1RSTR_CALCRST_POS) + +#define RMU_AHB1RSTR_CRCRST_POS 1U +#define RMU_AHB1RSTR_CRCRST_MSK BIT(RMU_AHB1RSTR_CRCRST_POS) + +#define RMU_AHB1RSTR_GPIORST_POS 0U +#define RMU_AHB1RSTR_GPIORST_MSK BIT(RMU_AHB1RSTR_GPIORST_POS) + +/****************** Bit definition for RMU_AHB2RSTR register ************************/ + +#define RMU_AHB2RSTR_CPURST_POS 1U +#define RMU_AHB2RSTR_CPURST_MSK BIT(RMU_AHB2RSTR_CPURST_POS) + +#define RMU_AHB2RSTR_CHIPRST_POS 0U +#define RMU_AHB2RSTR_CHIPRST_MSK BIT(RMU_AHB2RSTR_CHIPRST_POS) + +/****************** Bit definition for RMU_APB1RSTR register ************************/ + +#define RMU_APB1RSTR_CAN0RST_POS 24U +#define RMU_APB1RSTR_CAN0RST_MSK BIT(RMU_APB1RSTR_CAN0RST_POS) + +#define RMU_APB1RSTR_I2C1RST_POS 21U +#define RMU_APB1RSTR_I2C1RST_MSK BIT(RMU_APB1RSTR_I2C1RST_POS) + +#define RMU_APB1RSTR_I2C0RST_POS 20U +#define RMU_APB1RSTR_I2C0RST_MSK BIT(RMU_APB1RSTR_I2C0RST_POS) + +#define RMU_APB1RSTR_SPI2RST_POS 18U +#define RMU_APB1RSTR_SPI2RST_MSK BIT(RMU_APB1RSTR_SPI2RST_POS) + +#define RMU_APB1RSTR_SPI1RST_POS 17U +#define RMU_APB1RSTR_SPI1RST_MSK BIT(RMU_APB1RSTR_SPI1RST_POS) + +#define RMU_APB1RSTR_SPI0RST_POS 16U +#define RMU_APB1RSTR_SPI0RST_MSK BIT(RMU_APB1RSTR_SPI0RST_POS) + +#define RMU_APB1RSTR_USART1RST_POS 13U +#define RMU_APB1RSTR_USART1RST_MSK BIT(RMU_APB1RSTR_USART1RST_POS) + +#define RMU_APB1RSTR_USART0RST_POS 12U +#define RMU_APB1RSTR_USART0RST_MSK BIT(RMU_APB1RSTR_USART0RST_POS) + +#define RMU_APB1RSTR_UART3RST_POS 11U +#define RMU_APB1RSTR_UART3RST_MSK BIT(RMU_APB1RSTR_UART3RST_POS) + +#define RMU_APB1RSTR_UART2RST_POS 10U +#define RMU_APB1RSTR_UART2RST_MSK BIT(RMU_APB1RSTR_UART2RST_POS) + +#define RMU_APB1RSTR_UART1RST_POS 9U +#define RMU_APB1RSTR_UART1RST_MSK BIT(RMU_APB1RSTR_UART1RST_POS) + +#define RMU_APB1RSTR_UART0RST_POS 8U +#define RMU_APB1RSTR_UART0RST_MSK BIT(RMU_APB1RSTR_UART0RST_POS) + +#define RMU_APB1RSTR_TIM7RST_POS 7U +#define RMU_APB1RSTR_TIM7RST_MSK BIT(RMU_APB1RSTR_TIM7RST_POS) + +#define RMU_APB1RSTR_TIM6RST_POS 6U +#define RMU_APB1RSTR_TIM6RST_MSK BIT(RMU_APB1RSTR_TIM6RST_POS) + +#define RMU_APB1RSTR_TIM5RST_POS 5U +#define RMU_APB1RSTR_TIM5RST_MSK BIT(RMU_APB1RSTR_TIM5RST_POS) + +#define RMU_APB1RSTR_TIM4RST_POS 4U +#define RMU_APB1RSTR_TIM4RST_MSK BIT(RMU_APB1RSTR_TIM4RST_POS) + +#define RMU_APB1RSTR_TIM3RST_POS 3U +#define RMU_APB1RSTR_TIM3RST_MSK BIT(RMU_APB1RSTR_TIM3RST_POS) + +#define RMU_APB1RSTR_TIM2RST_POS 2U +#define RMU_APB1RSTR_TIM2RST_MSK BIT(RMU_APB1RSTR_TIM2RST_POS) + +#define RMU_APB1RSTR_TIM1RST_POS 1U +#define RMU_APB1RSTR_TIM1RST_MSK BIT(RMU_APB1RSTR_TIM1RST_POS) + +#define RMU_APB1RSTR_TIM0RST_POS 0U +#define RMU_APB1RSTR_TIM0RST_MSK BIT(RMU_APB1RSTR_TIM0RST_POS) + +/****************** Bit definition for RMU_APB2RSTR register ************************/ + +#define RMU_APB2RSTR_BKPRAMRST_POS 18U +#define RMU_APB2RSTR_BKPRAMRST_MSK BIT(RMU_APB2RSTR_BKPRAMRST_POS) + +#define RMU_APB2RSTR_BKPCRST_POS 17U +#define RMU_APB2RSTR_BKPCRST_MSK BIT(RMU_APB2RSTR_BKPCRST_POS) + +#define RMU_APB2RSTR_TSENSERST_POS 16U +#define RMU_APB2RSTR_TSENSERST_MSK BIT(RMU_APB2RSTR_TSENSERST_POS) + +#define RMU_APB2RSTR_RTCRST_POS 15U +#define RMU_APB2RSTR_RTCRST_MSK BIT(RMU_APB2RSTR_RTCRST_POS) + +#define RMU_APB2RSTR_IWDTRST_POS 14U +#define RMU_APB2RSTR_IWDTRST_MSK BIT(RMU_APB2RSTR_IWDTRST_POS) + +#define RMU_APB2RSTR_LCDRST_POS 13U +#define RMU_APB2RSTR_LCDRST_MSK BIT(RMU_APB2RSTR_LCDRST_POS) + +#define RMU_APB2RSTR_WWDTRST_POS 12U +#define RMU_APB2RSTR_WWDTRST_MSK BIT(RMU_APB2RSTR_WWDTRST_POS) + +#define RMU_APB2RSTR_OPAMPRST_POS 8U +#define RMU_APB2RSTR_OPAMPRST_MSK BIT(RMU_APB2RSTR_OPAMPRST_POS) + +#define RMU_APB2RSTR_ACMP1RST_POS 7U +#define RMU_APB2RSTR_ACMP1RST_MSK BIT(RMU_APB2RSTR_ACMP1RST_POS) + +#define RMU_APB2RSTR_ACMP0RST_POS 6U +#define RMU_APB2RSTR_ACMP0RST_MSK BIT(RMU_APB2RSTR_ACMP0RST_POS) + +#define RMU_APB2RSTR_ADC0RST_POS 4U +#define RMU_APB2RSTR_ADC0RST_MSK BIT(RMU_APB2RSTR_ADC0RST_POS) + +#define RMU_APB2RSTR_LPUART0RST_POS 2U +#define RMU_APB2RSTR_LPUART0RST_MSK BIT(RMU_APB2RSTR_LPUART0RST_POS) + +#define RMU_APB2RSTR_LPTIM0RST_POS 0U +#define RMU_APB2RSTR_LPTIM0RST_MSK BIT(RMU_APB2RSTR_LPTIM0RST_POS) + +typedef struct +{ + __IO uint32_t CR; + uint32_t RESERVED0[3] ; + __I uint32_t RSTSR; + __O uint32_t CRSTSR; + uint32_t RESERVED1[2] ; + __O uint32_t AHB1RSTR; + __O uint32_t AHB2RSTR; + uint32_t RESERVED2[2] ; + __O uint32_t APB1RSTR; + __O uint32_t APB2RSTR; +} RMU_TypeDef; + +/****************** Bit definition for CMU_CSR register ************************/ + +#define CMU_CSR_CFT_RDYN_POS 25U +#define CMU_CSR_CFT_RDYN_MSK BIT(CMU_CSR_CFT_RDYN_POS) + +#define CMU_CSR_CFT_STU_POS 24U +#define CMU_CSR_CFT_STU_MSK BIT(CMU_CSR_CFT_STU_POS) + +#define CMU_CSR_CFT_CMD_POSS 16U +#define CMU_CSR_CFT_CMD_POSE 23U +#define CMU_CSR_CFT_CMD_MSK BITS(CMU_CSR_CFT_CMD_POSS,CMU_CSR_CFT_CMD_POSE) + +#define CMU_CSR_SYS_RDYN_POS 12U +#define CMU_CSR_SYS_RDYN_MSK BIT(CMU_CSR_SYS_RDYN_POS) + +#define CMU_CSR_SYS_STU_POSS 8U +#define CMU_CSR_SYS_STU_POSE 10U +#define CMU_CSR_SYS_STU_MSK BITS(CMU_CSR_SYS_STU_POSS,CMU_CSR_SYS_STU_POSE) + +#define CMU_CSR_SYS_CMD_POSS 0U +#define CMU_CSR_SYS_CMD_POSE 2U +#define CMU_CSR_SYS_CMD_MSK BITS(CMU_CSR_SYS_CMD_POSS,CMU_CSR_SYS_CMD_POSE) + +/****************** Bit definition for CMU_CFGR register ************************/ + +#define CMU_CFGR_HRCFST_POS 25U +#define CMU_CFGR_HRCFST_MSK BIT(CMU_CFGR_HRCFST_POS) + +#define CMU_CFGR_HRCFSW_POS 24U +#define CMU_CFGR_HRCFSW_MSK BIT(CMU_CFGR_HRCFSW_POS) + +#define CMU_CFGR_PCLK2DIV_POSS 20U +#define CMU_CFGR_PCLK2DIV_POSE 23U +#define CMU_CFGR_PCLK2DIV_MSK BITS(CMU_CFGR_PCLK2DIV_POSS,CMU_CFGR_PCLK2DIV_POSE) + +#define CMU_CFGR_PCLK1DIV_POSS 16U +#define CMU_CFGR_PCLK1DIV_POSE 19U +#define CMU_CFGR_PCLK1DIV_MSK BITS(CMU_CFGR_PCLK1DIV_POSS,CMU_CFGR_PCLK1DIV_POSE) + +#define CMU_CFGR_SYSDIV_POSS 12U +#define CMU_CFGR_SYSDIV_POSE 15U +#define CMU_CFGR_SYSDIV_MSK BITS(CMU_CFGR_SYSDIV_POSS,CMU_CFGR_SYSDIV_POSE) + +#define CMU_CFGR_HCLK1DIV_POSS 0U +#define CMU_CFGR_HCLK1DIV_POSE 3U +#define CMU_CFGR_HCLK1DIV_MSK BITS(CMU_CFGR_HCLK1DIV_POSS,CMU_CFGR_HCLK1DIV_POSE) + +/****************** Bit definition for CMU_CLKENR register ************************/ + +#define CMU_CLKENR_PLL2EN_POS 9U +#define CMU_CLKENR_PLL2EN_MSK BIT(CMU_CLKENR_PLL2EN_POS) + +#define CMU_CLKENR_PLL1EN_POS 8U +#define CMU_CLKENR_PLL1EN_MSK BIT(CMU_CLKENR_PLL1EN_POS) + +#define CMU_CLKENR_ULRCEN_POS 4U +#define CMU_CLKENR_ULRCEN_MSK BIT(CMU_CLKENR_ULRCEN_POS) + +#define CMU_CLKENR_LRCEN_POS 3U +#define CMU_CLKENR_LRCEN_MSK BIT(CMU_CLKENR_LRCEN_POS) + +#define CMU_CLKENR_HRCEN_POS 2U +#define CMU_CLKENR_HRCEN_MSK BIT(CMU_CLKENR_HRCEN_POS) + +#define CMU_CLKENR_LOSCEN_POS 1U +#define CMU_CLKENR_LOSCEN_MSK BIT(CMU_CLKENR_LOSCEN_POS) + +#define CMU_CLKENR_HOSCEN_POS 0U +#define CMU_CLKENR_HOSCEN_MSK BIT(CMU_CLKENR_HOSCEN_POS) + +/****************** Bit definition for CMU_CLKSR register ************************/ + +#define CMU_CLKSR_PLL2RDY_POS 25U +#define CMU_CLKSR_PLL2RDY_MSK BIT(CMU_CLKSR_PLL2RDY_POS) + +#define CMU_CLKSR_PLL1RDY_POS 24U +#define CMU_CLKSR_PLL1RDY_MSK BIT(CMU_CLKSR_PLL1RDY_POS) + +#define CMU_CLKSR_LRCRDY_POS 19U +#define CMU_CLKSR_LRCRDY_MSK BIT(CMU_CLKSR_LRCRDY_POS) + +#define CMU_CLKSR_HRCRDY_POS 18U +#define CMU_CLKSR_HRCRDY_MSK BIT(CMU_CLKSR_HRCRDY_POS) + +#define CMU_CLKSR_LOSCRDY_POS 17U +#define CMU_CLKSR_LOSCRDY_MSK BIT(CMU_CLKSR_LOSCRDY_POS) + +#define CMU_CLKSR_HOSCRDY_POS 16U +#define CMU_CLKSR_HOSCRDY_MSK BIT(CMU_CLKSR_HOSCRDY_POS) + +#define CMU_CLKSR_PLL2ACT_POS 9U +#define CMU_CLKSR_PLL2ACT_MSK BIT(CMU_CLKSR_PLL2ACT_POS) + +#define CMU_CLKSR_PLL1ACT_POS 8U +#define CMU_CLKSR_PLL1ACT_MSK BIT(CMU_CLKSR_PLL1ACT_POS) + +#define CMU_CLKSR_ULRCACT_POS 4U +#define CMU_CLKSR_ULRCACT_MSK BIT(CMU_CLKSR_ULRCACT_POS) + +#define CMU_CLKSR_LRCACT_POS 3U +#define CMU_CLKSR_LRCACT_MSK BIT(CMU_CLKSR_LRCACT_POS) + +#define CMU_CLKSR_HRCACT_POS 2U +#define CMU_CLKSR_HRCACT_MSK BIT(CMU_CLKSR_HRCACT_POS) + +#define CMU_CLKSR_LOSCACT_POS 1U +#define CMU_CLKSR_LOSCACT_MSK BIT(CMU_CLKSR_LOSCACT_POS) + +#define CMU_CLKSR_HOSCACT_POS 0U +#define CMU_CLKSR_HOSCACT_MSK BIT(CMU_CLKSR_HOSCACT_POS) + +/****************** Bit definition for CMU_PLLCFG register ************************/ + +#define CMU_PLLCFG_PLL2LCKN_POS 17U +#define CMU_PLLCFG_PLL2LCKN_MSK BIT(CMU_PLLCFG_PLL2LCKN_POS) + +#define CMU_PLLCFG_PLL1LCKN_POS 16U +#define CMU_PLLCFG_PLL1LCKN_MSK BIT(CMU_PLLCFG_PLL1LCKN_POS) + +#define CMU_PLLCFG_PLL2RFS_POSS 8U +#define CMU_PLLCFG_PLL2RFS_POSE 9U +#define CMU_PLLCFG_PLL2RFS_MSK BITS(CMU_PLLCFG_PLL2RFS_POSS,CMU_PLLCFG_PLL2RFS_POSE) + +#define CMU_PLLCFG_PLL1OS_POS 4U +#define CMU_PLLCFG_PLL1OS_MSK BIT(CMU_PLLCFG_PLL1OS_POS) + +#define CMU_PLLCFG_PLL1RFS_POSS 0U +#define CMU_PLLCFG_PLL1RFS_POSE 2U +#define CMU_PLLCFG_PLL1RFS_MSK BITS(CMU_PLLCFG_PLL1RFS_POSS,CMU_PLLCFG_PLL1RFS_POSE) + +/****************** Bit definition for CMU_HOSCCFG register ************************/ + +#define CMU_HOSCCFG_FREQ_POSS 0U +#define CMU_HOSCCFG_FREQ_POSE 4U +#define CMU_HOSCCFG_FREQ_MSK BITS(CMU_HOSCCFG_FREQ_POSS,CMU_HOSCCFG_FREQ_POSE) + +/****************** Bit definition for CMU_HOSMCR register ************************/ + +#define CMU_HOSMCR_NMIE_POS 20U +#define CMU_HOSMCR_NMIE_MSK BIT(CMU_HOSMCR_NMIE_POS) + +#define CMU_HOSMCR_STPIF_POS 19U +#define CMU_HOSMCR_STPIF_MSK BIT(CMU_HOSMCR_STPIF_POS) + +#define CMU_HOSMCR_STRIF_POS 18U +#define CMU_HOSMCR_STRIF_MSK BIT(CMU_HOSMCR_STRIF_POS) + +#define CMU_HOSMCR_STPIE_POS 17U +#define CMU_HOSMCR_STPIE_MSK BIT(CMU_HOSMCR_STPIE_POS) + +#define CMU_HOSMCR_STRIE_POS 16U +#define CMU_HOSMCR_STRIE_MSK BIT(CMU_HOSMCR_STRIE_POS) + +#define CMU_HOSMCR_FRQS_POSS 8U +#define CMU_HOSMCR_FRQS_POSE 10U +#define CMU_HOSMCR_FRQS_MSK BITS(CMU_HOSMCR_FRQS_POSS,CMU_HOSMCR_FRQS_POSE) + +#define CMU_HOSMCR_CLKS_POS 1U +#define CMU_HOSMCR_CLKS_MSK BIT(CMU_HOSMCR_CLKS_POS) + +#define CMU_HOSMCR_EN_POS 0U +#define CMU_HOSMCR_EN_MSK BIT(CMU_HOSMCR_EN_POS) + +/****************** Bit definition for CMU_LOSMCR register ************************/ + +#define CMU_LOSMCR_NMIE_POS 20U +#define CMU_LOSMCR_NMIE_MSK BIT(CMU_LOSMCR_NMIE_POS) + +#define CMU_LOSMCR_STPIF_POS 19U +#define CMU_LOSMCR_STPIF_MSK BIT(CMU_LOSMCR_STPIF_POS) + +#define CMU_LOSMCR_STRIF_POS 18U +#define CMU_LOSMCR_STRIF_MSK BIT(CMU_LOSMCR_STRIF_POS) + +#define CMU_LOSMCR_STPIE_POS 17U +#define CMU_LOSMCR_STPIE_MSK BIT(CMU_LOSMCR_STPIE_POS) + +#define CMU_LOSMCR_STRIE_POS 16U +#define CMU_LOSMCR_STRIE_MSK BIT(CMU_LOSMCR_STRIE_POS) + +#define CMU_LOSMCR_CLKS_POS 1U +#define CMU_LOSMCR_CLKS_MSK BIT(CMU_LOSMCR_CLKS_POS) + +#define CMU_LOSMCR_EN_POS 0U +#define CMU_LOSMCR_EN_MSK BIT(CMU_LOSMCR_EN_POS) + +/****************** Bit definition for CMU_PULMCR register ************************/ + +#define CMU_PULMCR_NMIE_POS 20U +#define CMU_PULMCR_NMIE_MSK BIT(CMU_PULMCR_NMIE_POS) + +#define CMU_PULMCR_ULKIF_POS 19U +#define CMU_PULMCR_ULKIF_MSK BIT(CMU_PULMCR_ULKIF_POS) + +#define CMU_PULMCR_LCKIF_POS 18U +#define CMU_PULMCR_LCKIF_MSK BIT(CMU_PULMCR_LCKIF_POS) + +#define CMU_PULMCR_ULKIE_POS 17U +#define CMU_PULMCR_ULKIE_MSK BIT(CMU_PULMCR_ULKIE_POS) + +#define CMU_PULMCR_LCKIE_POS 16U +#define CMU_PULMCR_LCKIE_MSK BIT(CMU_PULMCR_LCKIE_POS) + +#define CMU_PULMCR_MODE_POSS 8U +#define CMU_PULMCR_MODE_POSE 9U +#define CMU_PULMCR_MODE_MSK BITS(CMU_PULMCR_MODE_POSS,CMU_PULMCR_MODE_POSE) + +#define CMU_PULMCR_CLKS_POS 1U +#define CMU_PULMCR_CLKS_MSK BIT(CMU_PULMCR_CLKS_POS) + +#define CMU_PULMCR_EN_POS 0U +#define CMU_PULMCR_EN_MSK BIT(CMU_PULMCR_EN_POS) + +/****************** Bit definition for CMU_CLKOCR register ************************/ + +#define CMU_CLKOCR_LSCOS_POSS 24U +#define CMU_CLKOCR_LSCOS_POSE 26U +#define CMU_CLKOCR_LSCOS_MSK BITS(CMU_CLKOCR_LSCOS_POSS,CMU_CLKOCR_LSCOS_POSE) + +#define CMU_CLKOCR_LSCOEN_POS 16U +#define CMU_CLKOCR_LSCOEN_MSK BIT(CMU_CLKOCR_LSCOEN_POS) + +#define CMU_CLKOCR_HSCODIV_POSS 12U +#define CMU_CLKOCR_HSCODIV_POSE 14U +#define CMU_CLKOCR_HSCODIV_MSK BITS(CMU_CLKOCR_HSCODIV_POSS,CMU_CLKOCR_HSCODIV_POSE) + +#define CMU_CLKOCR_HSCOS_POSS 8U +#define CMU_CLKOCR_HSCOS_POSE 10U +#define CMU_CLKOCR_HSCOS_MSK BITS(CMU_CLKOCR_HSCOS_POSS,CMU_CLKOCR_HSCOS_POSE) + +#define CMU_CLKOCR_HSCOEN_POS 0U +#define CMU_CLKOCR_HSCOEN_MSK BIT(CMU_CLKOCR_HSCOEN_POS) + +/****************** Bit definition for CMU_BUZZCR register ************************/ + +#define CMU_BUZZCR_DAT_POSS 16U +#define CMU_BUZZCR_DAT_POSE 31U +#define CMU_BUZZCR_DAT_MSK BITS(CMU_BUZZCR_DAT_POSS,CMU_BUZZCR_DAT_POSE) + +#define CMU_BUZZCR_DIV_POSS 8U +#define CMU_BUZZCR_DIV_POSE 10U +#define CMU_BUZZCR_DIV_MSK BITS(CMU_BUZZCR_DIV_POSS,CMU_BUZZCR_DIV_POSE) + +#define CMU_BUZZCR_EN_POS 0U +#define CMU_BUZZCR_EN_MSK BIT(CMU_BUZZCR_EN_POS) + +/****************** Bit definition for CMU_AHB1ENR register ************************/ + +#define CMU_AHB1ENR_PISEN_POS 5U +#define CMU_AHB1ENR_PISEN_MSK BIT(CMU_AHB1ENR_PISEN_POS) + +#define CMU_AHB1ENR_TRNGEN_POS 4U +#define CMU_AHB1ENR_TRNGEN_MSK BIT(CMU_AHB1ENR_TRNGEN_POS) + +#define CMU_AHB1ENR_CRYPTEN_POS 3U +#define CMU_AHB1ENR_CRYPTEN_MSK BIT(CMU_AHB1ENR_CRYPTEN_POS) + +#define CMU_AHB1ENR_CALCEN_POS 2U +#define CMU_AHB1ENR_CALCEN_MSK BIT(CMU_AHB1ENR_CALCEN_POS) + +#define CMU_AHB1ENR_CRCEN_POS 1U +#define CMU_AHB1ENR_CRCEN_MSK BIT(CMU_AHB1ENR_CRCEN_POS) + +#define CMU_AHB1ENR_GPIOEN_POS 0U +#define CMU_AHB1ENR_GPIOEN_MSK BIT(CMU_AHB1ENR_GPIOEN_POS) + +/****************** Bit definition for CMU_APB1ENR register ************************/ + +#define CMU_APB1ENR_CAN0EN_POS 24U +#define CMU_APB1ENR_CAN0EN_MSK BIT(CMU_APB1ENR_CAN0EN_POS) + +#define CMU_APB1ENR_I2C1EN_POS 21U +#define CMU_APB1ENR_I2C1EN_MSK BIT(CMU_APB1ENR_I2C1EN_POS) + +#define CMU_APB1ENR_I2C0EN_POS 20U +#define CMU_APB1ENR_I2C0EN_MSK BIT(CMU_APB1ENR_I2C0EN_POS) + +#define CMU_APB1ENR_SPI2EN_POS 18U +#define CMU_APB1ENR_SPI2EN_MSK BIT(CMU_APB1ENR_SPI2EN_POS) + +#define CMU_APB1ENR_SPI1EN_POS 17U +#define CMU_APB1ENR_SPI1EN_MSK BIT(CMU_APB1ENR_SPI1EN_POS) + +#define CMU_APB1ENR_SPI0EN_POS 16U +#define CMU_APB1ENR_SPI0EN_MSK BIT(CMU_APB1ENR_SPI0EN_POS) + +#define CMU_APB1ENR_USART1EN_POS 13U +#define CMU_APB1ENR_USART1EN_MSK BIT(CMU_APB1ENR_USART1EN_POS) + +#define CMU_APB1ENR_USART0EN_POS 12U +#define CMU_APB1ENR_USART0EN_MSK BIT(CMU_APB1ENR_USART0EN_POS) + +#define CMU_APB1ENR_UART3EN_POS 11U +#define CMU_APB1ENR_UART3EN_MSK BIT(CMU_APB1ENR_UART3EN_POS) + +#define CMU_APB1ENR_UART2EN_POS 10U +#define CMU_APB1ENR_UART2EN_MSK BIT(CMU_APB1ENR_UART2EN_POS) + +#define CMU_APB1ENR_UART1EN_POS 9U +#define CMU_APB1ENR_UART1EN_MSK BIT(CMU_APB1ENR_UART1EN_POS) + +#define CMU_APB1ENR_UART0EN_POS 8U +#define CMU_APB1ENR_UART0EN_MSK BIT(CMU_APB1ENR_UART0EN_POS) + +#define CMU_APB1ENR_TIM7EN_POS 7U +#define CMU_APB1ENR_TIM7EN_MSK BIT(CMU_APB1ENR_TIM7EN_POS) + +#define CMU_APB1ENR_TIM6EN_POS 6U +#define CMU_APB1ENR_TIM6EN_MSK BIT(CMU_APB1ENR_TIM6EN_POS) + +#define CMU_APB1ENR_TIM5EN_POS 5U +#define CMU_APB1ENR_TIM5EN_MSK BIT(CMU_APB1ENR_TIM5EN_POS) + +#define CMU_APB1ENR_TIM4EN_POS 4U +#define CMU_APB1ENR_TIM4EN_MSK BIT(CMU_APB1ENR_TIM4EN_POS) + +#define CMU_APB1ENR_TIM3EN_POS 3U +#define CMU_APB1ENR_TIM3EN_MSK BIT(CMU_APB1ENR_TIM3EN_POS) + +#define CMU_APB1ENR_TIM2EN_POS 2U +#define CMU_APB1ENR_TIM2EN_MSK BIT(CMU_APB1ENR_TIM2EN_POS) + +#define CMU_APB1ENR_TIM1EN_POS 1U +#define CMU_APB1ENR_TIM1EN_MSK BIT(CMU_APB1ENR_TIM1EN_POS) + +#define CMU_APB1ENR_TIM0EN_POS 0U +#define CMU_APB1ENR_TIM0EN_MSK BIT(CMU_APB1ENR_TIM0EN_POS) + +/****************** Bit definition for CMU_APB2ENR register ************************/ + +#define CMU_APB2ENR_DBGCEN_POS 19U +#define CMU_APB2ENR_DBGCEN_MSK BIT(CMU_APB2ENR_DBGCEN_POS) + +#define CMU_APB2ENR_BKPCEN_POS 17U +#define CMU_APB2ENR_BKPCEN_MSK BIT(CMU_APB2ENR_BKPCEN_POS) + +#define CMU_APB2ENR_TSENSEEN_POS 16U +#define CMU_APB2ENR_TSENSEEN_MSK BIT(CMU_APB2ENR_TSENSEEN_POS) + +#define CMU_APB2ENR_RTCEN_POS 15U +#define CMU_APB2ENR_RTCEN_MSK BIT(CMU_APB2ENR_RTCEN_POS) + +#define CMU_APB2ENR_IWDTEN_POS 14U +#define CMU_APB2ENR_IWDTEN_MSK BIT(CMU_APB2ENR_IWDTEN_POS) + +#define CMU_APB2ENR_LCDEN_POS 13U +#define CMU_APB2ENR_LCDEN_MSK BIT(CMU_APB2ENR_LCDEN_POS) + +#define CMU_APB2ENR_WWDTEN_POS 12U +#define CMU_APB2ENR_WWDTEN_MSK BIT(CMU_APB2ENR_WWDTEN_POS) + +#define CMU_APB2ENR_OPAMPEN_POS 8U +#define CMU_APB2ENR_OPAMPEN_MSK BIT(CMU_APB2ENR_OPAMPEN_POS) + +#define CMU_APB2ENR_ACMP1EN_POS 7U +#define CMU_APB2ENR_ACMP1EN_MSK BIT(CMU_APB2ENR_ACMP1EN_POS) + +#define CMU_APB2ENR_ACMP0EN_POS 6U +#define CMU_APB2ENR_ACMP0EN_MSK BIT(CMU_APB2ENR_ACMP0EN_POS) + +#define CMU_APB2ENR_ADC0EN_POS 4U +#define CMU_APB2ENR_ADC0EN_MSK BIT(CMU_APB2ENR_ADC0EN_POS) + +#define CMU_APB2ENR_LPUART0EN_POS 2U +#define CMU_APB2ENR_LPUART0EN_MSK BIT(CMU_APB2ENR_LPUART0EN_POS) + +#define CMU_APB2ENR_LPTIM0EN_POS 0U +#define CMU_APB2ENR_LPTIM0EN_MSK BIT(CMU_APB2ENR_LPTIM0EN_POS) + +/****************** Bit definition for CMU_LPENR register ************************/ + +#define CMU_LPENR_HOSCEN_POS 3U +#define CMU_LPENR_HOSCEN_MSK BIT(CMU_LPENR_HOSCEN_POS) + +#define CMU_LPENR_HRCEN_POS 2U +#define CMU_LPENR_HRCEN_MSK BIT(CMU_LPENR_HRCEN_POS) + +#define CMU_LPENR_LOSCEN_POS 1U +#define CMU_LPENR_LOSCEN_MSK BIT(CMU_LPENR_LOSCEN_POS) + +#define CMU_LPENR_LRCEN_POS 0U +#define CMU_LPENR_LRCEN_MSK BIT(CMU_LPENR_LRCEN_POS) + +/****************** Bit definition for CMU_PERICR register ************************/ + +#define CMU_PERICR_LCD_POSS 16U +#define CMU_PERICR_LCD_POSE 18U +#define CMU_PERICR_LCD_MSK BITS(CMU_PERICR_LCD_POSS,CMU_PERICR_LCD_POSE) + +#define CMU_PERICR_LPUART0_POSS 8U +#define CMU_PERICR_LPUART0_POSE 11U +#define CMU_PERICR_LPUART0_MSK BITS(CMU_PERICR_LPUART0_POSS,CMU_PERICR_LPUART0_POSE) + +#define CMU_PERICR_LPTIM0_POSS 0U +#define CMU_PERICR_LPTIM0_POSE 3U +#define CMU_PERICR_LPTIM0_MSK BITS(CMU_PERICR_LPTIM0_POSS,CMU_PERICR_LPTIM0_POSE) + +/****************** Bit definition for CMU_HRCACR register ************************/ + +#define CMU_HRCACR_IB_POSS 28U +#define CMU_HRCACR_IB_POSE 29U +#define CMU_HRCACR_IB_MSK BITS(CMU_HRCACR_IB_POSS,CMU_HRCACR_IB_POSE) + +#define CMU_HRCACR_CAP_POSS 26U +#define CMU_HRCACR_CAP_POSE 27U +#define CMU_HRCACR_CAP_MSK BITS(CMU_HRCACR_CAP_POSS,CMU_HRCACR_CAP_POSE) + +#define CMU_HRCACR_CAL_POSS 16U +#define CMU_HRCACR_CAL_POSE 25U +#define CMU_HRCACR_CAL_MSK BITS(CMU_HRCACR_CAL_POSS,CMU_HRCACR_CAL_POSE) + +#define CMU_HRCACR_IBSET_POSS 14U +#define CMU_HRCACR_IBSET_POSE 15U +#define CMU_HRCACR_IBSET_MSK BITS(CMU_HRCACR_IBSET_POSS,CMU_HRCACR_IBSET_POSE) + +#define CMU_HRCACR_CAPSET_POSS 12U +#define CMU_HRCACR_CAPSET_POSE 13U +#define CMU_HRCACR_CAPSET_MSK BITS(CMU_HRCACR_CAPSET_POSS,CMU_HRCACR_CAPSET_POSE) + +#define CMU_HRCACR_STA_POSS 9U +#define CMU_HRCACR_STA_POSE 10U +#define CMU_HRCACR_STA_MSK BITS(CMU_HRCACR_STA_POSS,CMU_HRCACR_STA_POSE) + +#define CMU_HRCACR_BUSY_POS 8U +#define CMU_HRCACR_BUSY_MSK BIT(CMU_HRCACR_BUSY_POS) + +#define CMU_HRCACR_WRTRG_POS 7U +#define CMU_HRCACR_WRTRG_MSK BIT(CMU_HRCACR_WRTRG_POS) + +#define CMU_HRCACR_AC_POSS 4U +#define CMU_HRCACR_AC_POSE 6U +#define CMU_HRCACR_AC_MSK BITS(CMU_HRCACR_AC_POSS,CMU_HRCACR_AC_POSE) + +#define CMU_HRCACR_IBS_POS 3U +#define CMU_HRCACR_IBS_MSK BIT(CMU_HRCACR_IBS_POS) + +#define CMU_HRCACR_RFSEL_POS 2U +#define CMU_HRCACR_RFSEL_MSK BIT(CMU_HRCACR_RFSEL_POS) + +#define CMU_HRCACR_FREQ_POS 1U +#define CMU_HRCACR_FREQ_MSK BIT(CMU_HRCACR_FREQ_POS) + +#define CMU_HRCACR_EN_POS 0U +#define CMU_HRCACR_EN_MSK BIT(CMU_HRCACR_EN_POS) + +typedef struct +{ + __O uint32_t CSR; + __IO uint32_t CFGR; + uint32_t RESERVED0[2] ; + __IO uint32_t CLKENR; + __I uint32_t CLKSR; + __IO uint32_t PLLCFG; + __IO uint32_t HOSCCFG; + __IO uint32_t HOSMCR; + __IO uint32_t LOSMCR; + __IO uint32_t PULMCR; + uint32_t RESERVED1 ; + __IO uint32_t CLKOCR; + __IO uint32_t BUZZCR; + uint32_t RESERVED2[2] ; + __IO uint32_t AHB1ENR; + uint32_t RESERVED3[3] ; + __IO uint32_t APB1ENR; + __IO uint32_t APB2ENR; + uint32_t RESERVED4[2] ; + __IO uint32_t LPENR; + uint32_t RESERVED5[7] ; + __IO uint32_t PERICR; + uint32_t RESERVED6[3] ; + __IO uint32_t HRCACR; +} CMU_TypeDef; + +/****************** Bit definition for DMA_STATUS register ************************/ + +#define DMA_STATUS_STATUS_POSS 4U +#define DMA_STATUS_STATUS_POSE 7U +#define DMA_STATUS_STATUS_MSK BITS(DMA_STATUS_STATUS_POSS,DMA_STATUS_STATUS_POSE) + +#define DMA_STATUS_MASTER_ENABLE_POS 0U +#define DMA_STATUS_MASTER_ENABLE_MSK BIT(DMA_STATUS_MASTER_ENABLE_POS) + +/****************** Bit definition for DMA_CFG register ************************/ + +#define DMA_CFG_CHNL_PROT_CTRL_POSS 5U +#define DMA_CFG_CHNL_PROT_CTRL_POSE 7U +#define DMA_CFG_CHNL_PROT_CTRL_MSK BITS(DMA_CFG_CHNL_PROT_CTRL_POSS,DMA_CFG_CHNL_PROT_CTRL_POSE) + +#define DMA_CFG_MASTER_ENABLE_POS 0U +#define DMA_CFG_MASTER_ENABLE_MSK BIT(DMA_CFG_MASTER_ENABLE_POS) + +/****************** Bit definition for DMA_CTRLBASE register ************************/ + +#define DMA_CTRLBASE_CTRL_BASE_PTR_POSS 9U +#define DMA_CTRLBASE_CTRL_BASE_PTR_POSE 31U +#define DMA_CTRLBASE_CTRL_BASE_PTR_MSK BITS(DMA_CTRLBASE_CTRL_BASE_PTR_POSS,DMA_CTRLBASE_CTRL_BASE_PTR_POSE) + +/****************** Bit definition for DMA_ALTCTRLBASE register ************************/ + +#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSS 0U +#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSE 31U +#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_MSK BITS(DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSS,DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSE) + +/****************** Bit definition for DMA_CHWAITSTATUS register ************************/ + +#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS 0U +#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE 31U +#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_MSK BITS(DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS,DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE) + +/****************** Bit definition for DMA_CHSWREQ register ************************/ + +#define DMA_CHSWREQ_CHSWREQ_POSS 0U +#define DMA_CHSWREQ_CHSWREQ_POSE 31U +#define DMA_CHSWREQ_CHSWREQ_MSK BITS(DMA_CHSWREQ_CHSWREQ_POSS,DMA_CHSWREQ_CHSWREQ_POSE) + +/****************** Bit definition for DMA_CHUSEBURSTSET register ************************/ + +#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS 0U +#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE 31U +#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_MSK BITS(DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS,DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE) + +/****************** Bit definition for DMA_CHUSEBURSTCLR register ************************/ + +#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS 0U +#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE 31U +#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_MSK BITS(DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS,DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE) + +/****************** Bit definition for DMA_CHREQMASKSET register ************************/ + +#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS 0U +#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE 31U +#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_MSK BITS(DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS,DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE) + +/****************** Bit definition for DMA_CHREQMASKCLR register ************************/ + +#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS 0U +#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE 31U +#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_MSK BITS(DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS,DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE) + +/****************** Bit definition for DMA_CHENSET register ************************/ + +#define DMA_CHENSET_CHNL_ENABLE_SET_POSS 0U +#define DMA_CHENSET_CHNL_ENABLE_SET_POSE 31U +#define DMA_CHENSET_CHNL_ENABLE_SET_MSK BITS(DMA_CHENSET_CHNL_ENABLE_SET_POSS,DMA_CHENSET_CHNL_ENABLE_SET_POSE) + +/****************** Bit definition for DMA_CHENCLR register ************************/ + +#define DMA_CHENCLR_CHNL_ENABLE_CLR_POSS 0U +#define DMA_CHENCLR_CHNL_ENABLE_CLR_POSE 31U +#define DMA_CHENCLR_CHNL_ENABLE_CLR_MSK BITS(DMA_CHENCLR_CHNL_ENABLE_CLR_POSS,DMA_CHENCLR_CHNL_ENABLE_CLR_POSE) + +/****************** Bit definition for DMA_CHPRIALTSET register ************************/ + +#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS 0U +#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE 31U +#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_MSK BITS(DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS,DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE) + +/****************** Bit definition for DMA_CHPRIALTCLR register ************************/ + +#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS 0U +#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE 31U +#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_MSK BITS(DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS,DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE) + +/****************** Bit definition for DMA_CHPRSET register ************************/ + +#define DMA_CHPRSET_CHNL_PRIORITY_SET_POSS 0U +#define DMA_CHPRSET_CHNL_PRIORITY_SET_POSE 31U +#define DMA_CHPRSET_CHNL_PRIORITY_SET_MSK BITS(DMA_CHPRSET_CHNL_PRIORITY_SET_POSS,DMA_CHPRSET_CHNL_PRIORITY_SET_POSE) + +/****************** Bit definition for DMA_CHPRCLR register ************************/ + +#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS 0U +#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE 31U +#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_MSK BITS(DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS,DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE) + +/****************** Bit definition for DMA_ERRCLR register ************************/ + +#define DMA_ERRCLR_ERR_CLR_POS 0U +#define DMA_ERRCLR_ERR_CLR_MSK BIT(DMA_ERRCLR_ERR_CLR_POS) + +/****************** Bit definition for DMA_IFLAG register ************************/ + +#define DMA_IFLAG_DMAERRIF_POS 31U +#define DMA_IFLAG_DMAERRIF_MSK BIT(DMA_IFLAG_DMAERRIF_POS) + +#define DMA_IFLAG_CH5DONEIF_POS 5U +#define DMA_IFLAG_CH5DONEIF_MSK BIT(DMA_IFLAG_CH5DONEIF_POS) + +#define DMA_IFLAG_CH4DONEIF_POS 4U +#define DMA_IFLAG_CH4DONEIF_MSK BIT(DMA_IFLAG_CH4DONEIF_POS) + +#define DMA_IFLAG_CH3DONEIF_POS 3U +#define DMA_IFLAG_CH3DONEIF_MSK BIT(DMA_IFLAG_CH3DONEIF_POS) + +#define DMA_IFLAG_CH2DONEIF_POS 2U +#define DMA_IFLAG_CH2DONEIF_MSK BIT(DMA_IFLAG_CH2DONEIF_POS) + +#define DMA_IFLAG_CH1DONEIF_POS 1U +#define DMA_IFLAG_CH1DONEIF_MSK BIT(DMA_IFLAG_CH1DONEIF_POS) + +#define DMA_IFLAG_CH0DONEIF_POS 0U +#define DMA_IFLAG_CH0DONEIF_MSK BIT(DMA_IFLAG_CH0DONEIF_POS) + +/****************** Bit definition for DMA_ICFR register ************************/ + +#define DMA_ICFR_DMAERRC_POS 31U +#define DMA_ICFR_DMAERRC_MSK BIT(DMA_ICFR_DMAERRC_POS) + +#define DMA_ICFR_CH5DONEC_POS 5U +#define DMA_ICFR_CH5DONEC_MSK BIT(DMA_ICFR_CH5DONEC_POS) + +#define DMA_ICFR_CH4DONEC_POS 4U +#define DMA_ICFR_CH4DONEC_MSK BIT(DMA_ICFR_CH4DONEC_POS) + +#define DMA_ICFR_CH3DONEC_POS 3U +#define DMA_ICFR_CH3DONEC_MSK BIT(DMA_ICFR_CH3DONEC_POS) + +#define DMA_ICFR_CH2DONEC_POS 2U +#define DMA_ICFR_CH2DONEC_MSK BIT(DMA_ICFR_CH2DONEC_POS) + +#define DMA_ICFR_CH1DONEC_POS 1U +#define DMA_ICFR_CH1DONEC_MSK BIT(DMA_ICFR_CH1DONEC_POS) + +#define DMA_ICFR_CH0DONEC_POS 0U +#define DMA_ICFR_CH0DONEC_MSK BIT(DMA_ICFR_CH0DONEC_POS) + +/****************** Bit definition for DMA_IER register ************************/ + +#define DMA_IER_DMAERRIE_POS 31U +#define DMA_IER_DMAERRIE_MSK BIT(DMA_IER_DMAERRIE_POS) + +#define DMA_IER_CH5DONEIE_POS 5U +#define DMA_IER_CH5DONEIE_MSK BIT(DMA_IER_CH5DONEIE_POS) + +#define DMA_IER_CH4DONEIE_POS 4U +#define DMA_IER_CH4DONEIE_MSK BIT(DMA_IER_CH4DONEIE_POS) + +#define DMA_IER_CH3DONEIE_POS 3U +#define DMA_IER_CH3DONEIE_MSK BIT(DMA_IER_CH3DONEIE_POS) + +#define DMA_IER_CH2DONEIE_POS 2U +#define DMA_IER_CH2DONEIE_MSK BIT(DMA_IER_CH2DONEIE_POS) + +#define DMA_IER_CH1DONEIE_POS 1U +#define DMA_IER_CH1DONEIE_MSK BIT(DMA_IER_CH1DONEIE_POS) + +#define DMA_IER_CH0DONEIE_POS 0U +#define DMA_IER_CH0DONEIE_MSK BIT(DMA_IER_CH0DONEIE_POS) + +/****************** Bit definition for DMA_CH0_SELCON register ************************/ + +#define DMA_CH0_SELCON_MSEL_POSS 8U +#define DMA_CH0_SELCON_MSEL_POSE 13U +#define DMA_CH0_SELCON_MSEL_MSK BITS(DMA_CH0_SELCON_MSEL_POSS,DMA_CH0_SELCON_MSEL_POSE) + +#define DMA_CH0_SELCON_MSIGSEL_POSS 0U +#define DMA_CH0_SELCON_MSIGSEL_POSE 3U +#define DMA_CH0_SELCON_MSIGSEL_MSK BITS(DMA_CH0_SELCON_MSIGSEL_POSS,DMA_CH0_SELCON_MSIGSEL_POSE) + +typedef struct +{ + __I uint32_t STATUS; + __IO uint32_t CFG; + __IO uint32_t CTRLBASE; + __I uint32_t ALTCTRLBASE; + __I uint32_t CHWAITSTATUS; + __IO uint32_t CHSWREQ; + __IO uint32_t CHUSEBURSTSET; + __O uint32_t CHUSEBURSTCLR; + __IO uint32_t CHREQMASKSET; + __O uint32_t CHREQMASKCLR; + __IO uint32_t CHENSET; + __O uint32_t CHENCLR; + __IO uint32_t CHPRIALTSET; + __O uint32_t CHPRIALTCLR; + __IO uint32_t CHPRSET; + __O uint32_t CHPRCLR; + uint32_t RESERVED0[3] ; + __IO uint32_t ERRCLR; + uint32_t RESERVED1[1004] ; + __I uint32_t IFLAG; + uint32_t RESERVED2 ; + __O uint32_t ICFR; + __IO uint32_t IER; + uint32_t RESERVED3[60] ; + __IO uint32_t CH_SELCON[6]; +} DMA_TypeDef; + +/****************** Bit definition for PIS_CH0_CON register ************************/ + +#define PIS_CH0_CON_SYNCSEL_POSS 24U +#define PIS_CH0_CON_SYNCSEL_POSE 26U +#define PIS_CH0_CON_SYNCSEL_MSK BITS(PIS_CH0_CON_SYNCSEL_POSS,PIS_CH0_CON_SYNCSEL_POSE) + +#define PIS_CH0_CON_PULCK_POSS 18U +#define PIS_CH0_CON_PULCK_POSE 19U +#define PIS_CH0_CON_PULCK_MSK BITS(PIS_CH0_CON_PULCK_POSS,PIS_CH0_CON_PULCK_POSE) + +#define PIS_CH0_CON_EDGS_POSS 16U +#define PIS_CH0_CON_EDGS_POSE 17U +#define PIS_CH0_CON_EDGS_MSK BITS(PIS_CH0_CON_EDGS_POSS,PIS_CH0_CON_EDGS_POSE) + +#define PIS_CH0_CON_SRCS_POSS 8U +#define PIS_CH0_CON_SRCS_POSE 13U +#define PIS_CH0_CON_SRCS_MSK BITS(PIS_CH0_CON_SRCS_POSS,PIS_CH0_CON_SRCS_POSE) + +#define PIS_CH0_CON_MSIGS_POSS 0U +#define PIS_CH0_CON_MSIGS_POSE 3U +#define PIS_CH0_CON_MSIGS_MSK BITS(PIS_CH0_CON_MSIGS_POSS,PIS_CH0_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH_OER register ************************/ + +#define PIS_CH_OER_CH3OE_POS 3U +#define PIS_CH_OER_CH3OE_MSK BIT(PIS_CH_OER_CH3OE_POS) + +#define PIS_CH_OER_CH2OE_POS 2U +#define PIS_CH_OER_CH2OE_MSK BIT(PIS_CH_OER_CH2OE_POS) + +#define PIS_CH_OER_CH1OE_POS 1U +#define PIS_CH_OER_CH1OE_MSK BIT(PIS_CH_OER_CH1OE_POS) + +#define PIS_CH_OER_CH0OE_POS 0U +#define PIS_CH_OER_CH0OE_MSK BIT(PIS_CH_OER_CH0OE_POS) + +/****************** Bit definition for PIS_TAR_CON0 register ************************/ + +#define PIS_TAR_CON0_TIM3_CH2IN_SEL_POS 25U +#define PIS_TAR_CON0_TIM3_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH1IN_SEL_POS 24U +#define PIS_TAR_CON0_TIM3_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH2IN_SEL_POS 17U +#define PIS_TAR_CON0_TIM2_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH1IN_SEL_POS 16U +#define PIS_TAR_CON0_TIM2_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_BRKIN_SEL_POS 4U +#define PIS_TAR_CON0_TIM0_BRKIN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_BRKIN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH4IN_SEL_POS 3U +#define PIS_TAR_CON0_TIM0_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH3IN_SEL_POS 2U +#define PIS_TAR_CON0_TIM0_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH2IN_SEL_POS 1U +#define PIS_TAR_CON0_TIM0_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH1IN_SEL_POS 0U +#define PIS_TAR_CON0_TIM0_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH1IN_SEL_POS) + +/****************** Bit definition for PIS_TAR_CON1 register ************************/ + +#define PIS_TAR_CON1_SPI1_CLK_SEL_POS 15U +#define PIS_TAR_CON1_SPI1_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI1_CLK_SEL_POS) + +#define PIS_TAR_CON1_SPI1_RX_SEL_POS 14U +#define PIS_TAR_CON1_SPI1_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI1_RX_SEL_POS) + +#define PIS_TAR_CON1_SPI0_CLK_SEL_POS 13U +#define PIS_TAR_CON1_SPI0_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI0_CLK_SEL_POS) + +#define PIS_TAR_CON1_SPI0_RX_SEL_POS 12U +#define PIS_TAR_CON1_SPI0_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI0_RX_SEL_POS) + +#define PIS_TAR_CON1_LPUART0_RXD_SEL_POS 8U +#define PIS_TAR_CON1_LPUART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_LPUART0_RXD_SEL_POS) + +#define PIS_TAR_CON1_USART1_RXD_SEL_POS 7U +#define PIS_TAR_CON1_USART1_RXD_SEL_MSK BIT(PIS_TAR_CON1_USART1_RXD_SEL_POS) + +#define PIS_TAR_CON1_USART0_RXD_SEL_POS 6U +#define PIS_TAR_CON1_USART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_USART0_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART3_RXD_SEL_POS 3U +#define PIS_TAR_CON1_UART3_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART3_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART2_RXD_SEL_POS 2U +#define PIS_TAR_CON1_UART2_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART2_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART1_RXD_SEL_POS 1U +#define PIS_TAR_CON1_UART1_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART1_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART0_RXD_SEL_POS 0U +#define PIS_TAR_CON1_UART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART0_RXD_SEL_POS) + +/****************** Bit definition for PIS_TXMCR register ************************/ + +#define PIS_TXMCR_TXMLVLS_POS 8U +#define PIS_TXMCR_TXMLVLS_MSK BIT(PIS_TXMCR_TXMLVLS_POS) + +#define PIS_TXMCR_TXMSS_POSS 4U +#define PIS_TXMCR_TXMSS_POSE 7U +#define PIS_TXMCR_TXMSS_MSK BITS(PIS_TXMCR_TXMSS_POSS,PIS_TXMCR_TXMSS_POSE) + +#define PIS_TXMCR_TXSIGS_POSS 0U +#define PIS_TXMCR_TXSIGS_POSE 3U +#define PIS_TXMCR_TXSIGS_MSK BITS(PIS_TXMCR_TXSIGS_POSS,PIS_TXMCR_TXSIGS_POSE) + +typedef struct +{ + __IO uint32_t CH_CON[8]; + uint32_t RESERVED0[8] ; + __IO uint32_t CH_OER; + __IO uint32_t TAR_CON0; + __IO uint32_t TAR_CON1; + uint32_t RESERVED1[5] ; + __IO uint32_t UART0_TXMCR; + __IO uint32_t UART1_TXMCR; + __IO uint32_t UART2_TXMCR; + __IO uint32_t UART3_TXMCR; + __IO uint32_t LPUART0_TXMCR; +} PIS_TypeDef; + +/****************** Bit definition for GPIO_DIN register ************************/ + +#define GPIO_DIN_DIN_POSS 0U +#define GPIO_DIN_DIN_POSE 15U +#define GPIO_DIN_DIN_MSK BITS(GPIO_DIN_DIN_POSS,GPIO_DIN_DIN_POSE) + +/****************** Bit definition for GPIO_DOUT register ************************/ + +#define GPIO_DOUT_DOUT_POSS 0U +#define GPIO_DOUT_DOUT_POSE 15U +#define GPIO_DOUT_DOUT_MSK BITS(GPIO_DOUT_DOUT_POSS,GPIO_DOUT_DOUT_POSE) + +/****************** Bit definition for GPIO_BSRR register ************************/ + +#define GPIO_BSRR_BRR_POSS 16U +#define GPIO_BSRR_BRR_POSE 31U +#define GPIO_BSRR_BRR_MSK BITS(GPIO_BSRR_BRR_POSS,GPIO_BSRR_BRR_POSE) + +#define GPIO_BSRR_BSR_POSS 0U +#define GPIO_BSRR_BSR_POSE 15U +#define GPIO_BSRR_BSR_MSK BITS(GPIO_BSRR_BSR_POSS,GPIO_BSRR_BSR_POSE) + +/****************** Bit definition for GPIO_BIR register ************************/ + +#define GPIO_BIR_BIR_POSS 0U +#define GPIO_BIR_BIR_POSE 15U +#define GPIO_BIR_BIR_MSK BITS(GPIO_BIR_BIR_POSS,GPIO_BIR_BIR_POSE) + +/****************** Bit definition for GPIO_MODE register ************************/ + +#define GPIO_MODE_MODE_POSS 0U +#define GPIO_MODE_MODE_POSE 31U +#define GPIO_MODE_MODE_MSK BITS(GPIO_MODE_MODE_POSS,GPIO_MODE_MODE_POSE) + +/****************** Bit definition for GPIO_ODOS register ************************/ + +#define GPIO_ODOS_ODOS_POSS 0U +#define GPIO_ODOS_ODOS_POSE 31U +#define GPIO_ODOS_ODOS_MSK BITS(GPIO_ODOS_ODOS_POSS,GPIO_ODOS_ODOS_POSE) + +/****************** Bit definition for GPIO_PUPD register ************************/ + +#define GPIO_PUPD_PUPD_POSS 0U +#define GPIO_PUPD_PUPD_POSE 31U +#define GPIO_PUPD_PUPD_MSK BITS(GPIO_PUPD_PUPD_POSS,GPIO_PUPD_PUPD_POSE) + +/****************** Bit definition for GPIO_ODRV register ************************/ + +#define GPIO_ODRV_ODRV_POSS 0U +#define GPIO_ODRV_ODRV_POSE 31U +#define GPIO_ODRV_ODRV_MSK BITS(GPIO_ODRV_ODRV_POSS,GPIO_ODRV_ODRV_POSE) + +/****************** Bit definition for GPIO_FLT register ************************/ + +#define GPIO_FLT_FLT_POSS 0U +#define GPIO_FLT_FLT_POSE 15U +#define GPIO_FLT_FLT_MSK BITS(GPIO_FLT_FLT_POSS,GPIO_FLT_FLT_POSE) + +/****************** Bit definition for GPIO_TYPE register ************************/ + +#define GPIO_TYPE_TYPE_POSS 0U +#define GPIO_TYPE_TYPE_POSE 15U +#define GPIO_TYPE_TYPE_MSK BITS(GPIO_TYPE_TYPE_POSS,GPIO_TYPE_TYPE_POSE) + +/****************** Bit definition for GPIO_FUNC0 register ************************/ + +#define GPIO_FUNC0_FSEL_IO7_POSS 28U +#define GPIO_FUNC0_FSEL_IO7_POSE 31U +#define GPIO_FUNC0_FSEL_IO7_MSK BITS(GPIO_FUNC0_FSEL_IO7_POSS,GPIO_FUNC0_FSEL_IO7_POSE) + +#define GPIO_FUNC0_FSEL_IO6_POSS 24U +#define GPIO_FUNC0_FSEL_IO6_POSE 27U +#define GPIO_FUNC0_FSEL_IO6_MSK BITS(GPIO_FUNC0_FSEL_IO6_POSS,GPIO_FUNC0_FSEL_IO6_POSE) + +#define GPIO_FUNC0_FSEL_IO5_POSS 20U +#define GPIO_FUNC0_FSEL_IO5_POSE 23U +#define GPIO_FUNC0_FSEL_IO5_MSK BITS(GPIO_FUNC0_FSEL_IO5_POSS,GPIO_FUNC0_FSEL_IO5_POSE) + +#define GPIO_FUNC0_FSEL_IO4_POSS 16U +#define GPIO_FUNC0_FSEL_IO4_POSE 19U +#define GPIO_FUNC0_FSEL_IO4_MSK BITS(GPIO_FUNC0_FSEL_IO4_POSS,GPIO_FUNC0_FSEL_IO4_POSE) + +#define GPIO_FUNC0_FSEL_IO3_POSS 12U +#define GPIO_FUNC0_FSEL_IO3_POSE 15U +#define GPIO_FUNC0_FSEL_IO3_MSK BITS(GPIO_FUNC0_FSEL_IO3_POSS,GPIO_FUNC0_FSEL_IO3_POSE) + +#define GPIO_FUNC0_FSEL_IO2_POSS 8U +#define GPIO_FUNC0_FSEL_IO2_POSE 11U +#define GPIO_FUNC0_FSEL_IO2_MSK BITS(GPIO_FUNC0_FSEL_IO2_POSS,GPIO_FUNC0_FSEL_IO2_POSE) + +#define GPIO_FUNC0_FSEL_IO1_POSS 4U +#define GPIO_FUNC0_FSEL_IO1_POSE 7U +#define GPIO_FUNC0_FSEL_IO1_MSK BITS(GPIO_FUNC0_FSEL_IO1_POSS,GPIO_FUNC0_FSEL_IO1_POSE) + +#define GPIO_FUNC0_FSEL_IO0_POSS 0U +#define GPIO_FUNC0_FSEL_IO0_POSE 3U +#define GPIO_FUNC0_FSEL_IO0_MSK BITS(GPIO_FUNC0_FSEL_IO0_POSS,GPIO_FUNC0_FSEL_IO0_POSE) + +/****************** Bit definition for GPIO_FUNC1 register ************************/ + +#define GPIO_FUNC1_FSEL_IO15_POSS 28U +#define GPIO_FUNC1_FSEL_IO15_POSE 31U +#define GPIO_FUNC1_FSEL_IO15_MSK BITS(GPIO_FUNC1_FSEL_IO15_POSS,GPIO_FUNC1_FSEL_IO15_POSE) + +#define GPIO_FUNC1_FSEL_IO14_POSS 24U +#define GPIO_FUNC1_FSEL_IO14_POSE 27U +#define GPIO_FUNC1_FSEL_IO14_MSK BITS(GPIO_FUNC1_FSEL_IO14_POSS,GPIO_FUNC1_FSEL_IO14_POSE) + +#define GPIO_FUNC1_FSEL_IO13_POSS 20U +#define GPIO_FUNC1_FSEL_IO13_POSE 23U +#define GPIO_FUNC1_FSEL_IO13_MSK BITS(GPIO_FUNC1_FSEL_IO13_POSS,GPIO_FUNC1_FSEL_IO13_POSE) + +#define GPIO_FUNC1_FSEL_IO12_POSS 16U +#define GPIO_FUNC1_FSEL_IO12_POSE 19U +#define GPIO_FUNC1_FSEL_IO12_MSK BITS(GPIO_FUNC1_FSEL_IO12_POSS,GPIO_FUNC1_FSEL_IO12_POSE) + +#define GPIO_FUNC1_FSEL_IO11_POSS 12U +#define GPIO_FUNC1_FSEL_IO11_POSE 15U +#define GPIO_FUNC1_FSEL_IO11_MSK BITS(GPIO_FUNC1_FSEL_IO11_POSS,GPIO_FUNC1_FSEL_IO11_POSE) + +#define GPIO_FUNC1_FSEL_IO10_POSS 8U +#define GPIO_FUNC1_FSEL_IO10_POSE 11U +#define GPIO_FUNC1_FSEL_IO10_MSK BITS(GPIO_FUNC1_FSEL_IO10_POSS,GPIO_FUNC1_FSEL_IO10_POSE) + +#define GPIO_FUNC1_FSEL_IO9_POSS 4U +#define GPIO_FUNC1_FSEL_IO9_POSE 7U +#define GPIO_FUNC1_FSEL_IO9_MSK BITS(GPIO_FUNC1_FSEL_IO9_POSS,GPIO_FUNC1_FSEL_IO9_POSE) + +#define GPIO_FUNC1_FSEL_IO8_POSS 0U +#define GPIO_FUNC1_FSEL_IO8_POSE 3U +#define GPIO_FUNC1_FSEL_IO8_MSK BITS(GPIO_FUNC1_FSEL_IO8_POSS,GPIO_FUNC1_FSEL_IO8_POSE) + +/****************** Bit definition for GPIO_LOCK register ************************/ + +#define GPIO_LOCK_KEY_POSS 16U +#define GPIO_LOCK_KEY_POSE 31U +#define GPIO_LOCK_KEY_MSK BITS(GPIO_LOCK_KEY_POSS,GPIO_LOCK_KEY_POSE) + +#define GPIO_LOCK_LOCK_POSS 0U +#define GPIO_LOCK_LOCK_POSE 15U +#define GPIO_LOCK_LOCK_MSK BITS(GPIO_LOCK_LOCK_POSS,GPIO_LOCK_LOCK_POSE) + +typedef struct +{ + __I uint32_t DIN; + __IO uint32_t DOUT; + __O uint32_t BSRR; + __O uint32_t BIR; + __IO uint32_t MODE; + __IO uint32_t ODOS; + __IO uint32_t PUPD; + __IO uint32_t ODRV; + __IO uint32_t FLT; + __IO uint32_t TYPE; + __IO uint32_t FUNC0; + __IO uint32_t FUNC1; + __IO uint32_t LOCK; +} GPIO_TypeDef; + +/****************** Bit definition for GPIO_EXTIRER register ************************/ + +#define GPIO_EXTIRER_EXTIRER_POSS 0U +#define GPIO_EXTIRER_EXTIRER_POSE 15U +#define GPIO_EXTIRER_EXTIRER_MSK BITS(GPIO_EXTIRER_EXTIRER_POSS,GPIO_EXTIRER_EXTIRER_POSE) + +/****************** Bit definition for GPIO_EXTIFER register ************************/ + +#define GPIO_EXTIFER_EXTIFER_POSS 0U +#define GPIO_EXTIFER_EXTIFER_POSE 15U +#define GPIO_EXTIFER_EXTIFER_MSK BITS(GPIO_EXTIFER_EXTIFER_POSS,GPIO_EXTIFER_EXTIFER_POSE) + +/****************** Bit definition for GPIO_EXTIEN register ************************/ + +#define GPIO_EXTIEN_EXTIEN_POSS 0U +#define GPIO_EXTIEN_EXTIEN_POSE 15U +#define GPIO_EXTIEN_EXTIEN_MSK BITS(GPIO_EXTIEN_EXTIEN_POSS,GPIO_EXTIEN_EXTIEN_POSE) + +/****************** Bit definition for GPIO_EXTIFLAG register ************************/ + +#define GPIO_EXTIFLAG_EXTIFLAG_POSS 0U +#define GPIO_EXTIFLAG_EXTIFLAG_POSE 15U +#define GPIO_EXTIFLAG_EXTIFLAG_MSK BITS(GPIO_EXTIFLAG_EXTIFLAG_POSS,GPIO_EXTIFLAG_EXTIFLAG_POSE) + +/****************** Bit definition for GPIO_EXTISFR register ************************/ + +#define GPIO_EXTISFR_EXTISFR_POSS 0U +#define GPIO_EXTISFR_EXTISFR_POSE 15U +#define GPIO_EXTISFR_EXTISFR_MSK BITS(GPIO_EXTISFR_EXTISFR_POSS,GPIO_EXTISFR_EXTISFR_POSE) + +/****************** Bit definition for GPIO_EXTICFR register ************************/ + +#define GPIO_EXTICFR_EXTICFR_POSS 0U +#define GPIO_EXTICFR_EXTICFR_POSE 15U +#define GPIO_EXTICFR_EXTICFR_MSK BITS(GPIO_EXTICFR_EXTICFR_POSS,GPIO_EXTICFR_EXTICFR_POSE) + +/****************** Bit definition for GPIO_EXTIPSR0 register ************************/ + +#define GPIO_EXTIPSR0_EXTIS7_POSS 28U +#define GPIO_EXTIPSR0_EXTIS7_POSE 30U +#define GPIO_EXTIPSR0_EXTIS7_MSK BITS(GPIO_EXTIPSR0_EXTIS7_POSS,GPIO_EXTIPSR0_EXTIS7_POSE) + +#define GPIO_EXTIPSR0_EXTIS6_POSS 24U +#define GPIO_EXTIPSR0_EXTIS6_POSE 26U +#define GPIO_EXTIPSR0_EXTIS6_MSK BITS(GPIO_EXTIPSR0_EXTIS6_POSS,GPIO_EXTIPSR0_EXTIS6_POSE) + +#define GPIO_EXTIPSR0_EXTIS5_POSS 20U +#define GPIO_EXTIPSR0_EXTIS5_POSE 22U +#define GPIO_EXTIPSR0_EXTIS5_MSK BITS(GPIO_EXTIPSR0_EXTIS5_POSS,GPIO_EXTIPSR0_EXTIS5_POSE) + +#define GPIO_EXTIPSR0_EXTIS4_POSS 16U +#define GPIO_EXTIPSR0_EXTIS4_POSE 18U +#define GPIO_EXTIPSR0_EXTIS4_MSK BITS(GPIO_EXTIPSR0_EXTIS4_POSS,GPIO_EXTIPSR0_EXTIS4_POSE) + +#define GPIO_EXTIPSR0_EXTIS3_POSS 12U +#define GPIO_EXTIPSR0_EXTIS3_POSE 14U +#define GPIO_EXTIPSR0_EXTIS3_MSK BITS(GPIO_EXTIPSR0_EXTIS3_POSS,GPIO_EXTIPSR0_EXTIS3_POSE) + +#define GPIO_EXTIPSR0_EXTIS2_POSS 8U +#define GPIO_EXTIPSR0_EXTIS2_POSE 10U +#define GPIO_EXTIPSR0_EXTIS2_MSK BITS(GPIO_EXTIPSR0_EXTIS2_POSS,GPIO_EXTIPSR0_EXTIS2_POSE) + +#define GPIO_EXTIPSR0_EXTIS1_POSS 4U +#define GPIO_EXTIPSR0_EXTIS1_POSE 6U +#define GPIO_EXTIPSR0_EXTIS1_MSK BITS(GPIO_EXTIPSR0_EXTIS1_POSS,GPIO_EXTIPSR0_EXTIS1_POSE) + +#define GPIO_EXTIPSR0_EXTIS0_POSS 0U +#define GPIO_EXTIPSR0_EXTIS0_POSE 2U +#define GPIO_EXTIPSR0_EXTIS0_MSK BITS(GPIO_EXTIPSR0_EXTIS0_POSS,GPIO_EXTIPSR0_EXTIS0_POSE) + +/****************** Bit definition for GPIO_EXTIPSR1 register ************************/ + +#define GPIO_EXTIPSR1_EXTIS15_POSS 28U +#define GPIO_EXTIPSR1_EXTIS15_POSE 30U +#define GPIO_EXTIPSR1_EXTIS15_MSK BITS(GPIO_EXTIPSR1_EXTIS15_POSS,GPIO_EXTIPSR1_EXTIS15_POSE) + +#define GPIO_EXTIPSR1_EXTIS14_POSS 24U +#define GPIO_EXTIPSR1_EXTIS14_POSE 26U +#define GPIO_EXTIPSR1_EXTIS14_MSK BITS(GPIO_EXTIPSR1_EXTIS14_POSS,GPIO_EXTIPSR1_EXTIS14_POSE) + +#define GPIO_EXTIPSR1_EXTIS13_POSS 20U +#define GPIO_EXTIPSR1_EXTIS13_POSE 22U +#define GPIO_EXTIPSR1_EXTIS13_MSK BITS(GPIO_EXTIPSR1_EXTIS13_POSS,GPIO_EXTIPSR1_EXTIS13_POSE) + +#define GPIO_EXTIPSR1_EXTIS12_POSS 16U +#define GPIO_EXTIPSR1_EXTIS12_POSE 18U +#define GPIO_EXTIPSR1_EXTIS12_MSK BITS(GPIO_EXTIPSR1_EXTIS12_POSS,GPIO_EXTIPSR1_EXTIS12_POSE) + +#define GPIO_EXTIPSR1_EXTIS11_POSS 12U +#define GPIO_EXTIPSR1_EXTIS11_POSE 14U +#define GPIO_EXTIPSR1_EXTIS11_MSK BITS(GPIO_EXTIPSR1_EXTIS11_POSS,GPIO_EXTIPSR1_EXTIS11_POSE) + +#define GPIO_EXTIPSR1_EXTIS10_POSS 8U +#define GPIO_EXTIPSR1_EXTIS10_POSE 10U +#define GPIO_EXTIPSR1_EXTIS10_MSK BITS(GPIO_EXTIPSR1_EXTIS10_POSS,GPIO_EXTIPSR1_EXTIS10_POSE) + +#define GPIO_EXTIPSR1_EXTIS9_POSS 4U +#define GPIO_EXTIPSR1_EXTIS9_POSE 6U +#define GPIO_EXTIPSR1_EXTIS9_MSK BITS(GPIO_EXTIPSR1_EXTIS9_POSS,GPIO_EXTIPSR1_EXTIS9_POSE) + +#define GPIO_EXTIPSR1_EXTIS8_POSS 0U +#define GPIO_EXTIPSR1_EXTIS8_POSE 2U +#define GPIO_EXTIPSR1_EXTIS8_MSK BITS(GPIO_EXTIPSR1_EXTIS8_POSS,GPIO_EXTIPSR1_EXTIS8_POSE) + +/****************** Bit definition for GPIO_EXTIFLTCR register ************************/ + +#define GPIO_EXTIFLTCR_FLTCKS_POSS 24U +#define GPIO_EXTIFLTCR_FLTCKS_POSE 25U +#define GPIO_EXTIFLTCR_FLTCKS_MSK BITS(GPIO_EXTIFLTCR_FLTCKS_POSS,GPIO_EXTIFLTCR_FLTCKS_POSE) + +#define GPIO_EXTIFLTCR_FLTSEL_POSS 16U +#define GPIO_EXTIFLTCR_FLTSEL_POSE 23U +#define GPIO_EXTIFLTCR_FLTSEL_MSK BITS(GPIO_EXTIFLTCR_FLTSEL_POSS,GPIO_EXTIFLTCR_FLTSEL_POSE) + +#define GPIO_EXTIFLTCR_FLTEN_POSS 0U +#define GPIO_EXTIFLTCR_FLTEN_POSE 15U +#define GPIO_EXTIFLTCR_FLTEN_MSK BITS(GPIO_EXTIFLTCR_FLTEN_POSS,GPIO_EXTIFLTCR_FLTEN_POSE) + +typedef struct +{ + __IO uint32_t EXTIRER; + uint32_t RESERVED0 ; + __IO uint32_t EXTIFER; + uint32_t RESERVED1 ; + __IO uint32_t EXTIEN; + uint32_t RESERVED2 ; + __I uint32_t EXTIFLAG; + uint32_t RESERVED3 ; + __O uint32_t EXTISFR; + uint32_t RESERVED4 ; + __O uint32_t EXTICFR; + uint32_t RESERVED5 ; + __IO uint32_t EXTIPSR0; + __IO uint32_t EXTIPSR1; + uint32_t RESERVED6[2] ; + __IO uint32_t EXTIFLTCR; +} EXTI_TypeDef; + +/****************** Bit definition for RTC_WPR register ************************/ + +#define RTC_WPR_WP_POS 0U +#define RTC_WPR_WP_MSK BIT(RTC_WPR_WP_POS) + +/****************** Bit definition for RTC_CON register ************************/ + +#define RTC_CON_SSEC_POS 25U +#define RTC_CON_SSEC_MSK BIT(RTC_CON_SSEC_POS) + +#define RTC_CON_BUSY_POS 24U +#define RTC_CON_BUSY_MSK BIT(RTC_CON_BUSY_POS) + +#define RTC_CON_POL_POS 22U +#define RTC_CON_POL_MSK BIT(RTC_CON_POL_POS) + +#define RTC_CON_EOS_POSS 20U +#define RTC_CON_EOS_POSE 21U +#define RTC_CON_EOS_MSK BITS(RTC_CON_EOS_POSS,RTC_CON_EOS_POSE) + +#define RTC_CON_CKOS_POSS 17U +#define RTC_CON_CKOS_POSE 19U +#define RTC_CON_CKOS_MSK BITS(RTC_CON_CKOS_POSS,RTC_CON_CKOS_POSE) + +#define RTC_CON_CKOE_POS 16U +#define RTC_CON_CKOE_MSK BIT(RTC_CON_CKOE_POS) + +#define RTC_CON_WUCKS_POSS 13U +#define RTC_CON_WUCKS_POSE 15U +#define RTC_CON_WUCKS_MSK BITS(RTC_CON_WUCKS_POSS,RTC_CON_WUCKS_POSE) + +#define RTC_CON_WUTE_POS 12U +#define RTC_CON_WUTE_MSK BIT(RTC_CON_WUTE_POS) + +#define RTC_CON_DSTS_POS 10U +#define RTC_CON_DSTS_MSK BIT(RTC_CON_DSTS_POS) + +#define RTC_CON_SUB1H_POS 9U +#define RTC_CON_SUB1H_MSK BIT(RTC_CON_SUB1H_POS) + +#define RTC_CON_ADD1H_POS 8U +#define RTC_CON_ADD1H_MSK BIT(RTC_CON_ADD1H_POS) + +#define RTC_CON_TSPIN_POS 7U +#define RTC_CON_TSPIN_MSK BIT(RTC_CON_TSPIN_POS) + +#define RTC_CON_TSSEL_POS 6U +#define RTC_CON_TSSEL_MSK BIT(RTC_CON_TSSEL_POS) + +#define RTC_CON_TSEN_POS 5U +#define RTC_CON_TSEN_MSK BIT(RTC_CON_TSEN_POS) + +#define RTC_CON_SHDBP_POS 4U +#define RTC_CON_SHDBP_MSK BIT(RTC_CON_SHDBP_POS) + +#define RTC_CON_HFM_POS 3U +#define RTC_CON_HFM_MSK BIT(RTC_CON_HFM_POS) + +#define RTC_CON_ALMBEN_POS 2U +#define RTC_CON_ALMBEN_MSK BIT(RTC_CON_ALMBEN_POS) + +#define RTC_CON_ALMAEN_POS 1U +#define RTC_CON_ALMAEN_MSK BIT(RTC_CON_ALMAEN_POS) + +#define RTC_CON_GO_POS 0U +#define RTC_CON_GO_MSK BIT(RTC_CON_GO_POS) + +/****************** Bit definition for RTC_PSR register ************************/ + +#define RTC_PSR_APRS_POSS 16U +#define RTC_PSR_APRS_POSE 22U +#define RTC_PSR_APRS_MSK BITS(RTC_PSR_APRS_POSS,RTC_PSR_APRS_POSE) + +#define RTC_PSR_SPRS_POSS 0U +#define RTC_PSR_SPRS_POSE 14U +#define RTC_PSR_SPRS_MSK BITS(RTC_PSR_SPRS_POSS,RTC_PSR_SPRS_POSE) + +/****************** Bit definition for RTC_TAMPCON register ************************/ + +#define RTC_TAMPCON_TAMPFLT_POSS 20U +#define RTC_TAMPCON_TAMPFLT_POSE 21U +#define RTC_TAMPCON_TAMPFLT_MSK BITS(RTC_TAMPCON_TAMPFLT_POSS,RTC_TAMPCON_TAMPFLT_POSE) + +#define RTC_TAMPCON_TAMPCKS_POSS 17U +#define RTC_TAMPCON_TAMPCKS_POSE 19U +#define RTC_TAMPCON_TAMPCKS_MSK BITS(RTC_TAMPCON_TAMPCKS_POSS,RTC_TAMPCON_TAMPCKS_POSE) + +#define RTC_TAMPCON_TAMPTS_POS 16U +#define RTC_TAMPCON_TAMPTS_MSK BIT(RTC_TAMPCON_TAMPTS_POS) + +#define RTC_TAMPCON_TAMP2LV_POS 9U +#define RTC_TAMPCON_TAMP2LV_MSK BIT(RTC_TAMPCON_TAMP2LV_POS) + +#define RTC_TAMPCON_TAMP2EN_POS 8U +#define RTC_TAMPCON_TAMP2EN_MSK BIT(RTC_TAMPCON_TAMP2EN_POS) + +#define RTC_TAMPCON_TAMP1LV_POS 1U +#define RTC_TAMPCON_TAMP1LV_MSK BIT(RTC_TAMPCON_TAMP1LV_POS) + +#define RTC_TAMPCON_TAMP1EN_POS 0U +#define RTC_TAMPCON_TAMP1EN_MSK BIT(RTC_TAMPCON_TAMP1EN_POS) + +/****************** Bit definition for RTC_TIME register ************************/ + +#define RTC_TIME_PM_POS 22U +#define RTC_TIME_PM_MSK BIT(RTC_TIME_PM_POS) + +#define RTC_TIME_HRT_POSS 20U +#define RTC_TIME_HRT_POSE 21U +#define RTC_TIME_HRT_MSK BITS(RTC_TIME_HRT_POSS,RTC_TIME_HRT_POSE) + +#define RTC_TIME_HRU_POSS 16U +#define RTC_TIME_HRU_POSE 19U +#define RTC_TIME_HRU_MSK BITS(RTC_TIME_HRU_POSS,RTC_TIME_HRU_POSE) + +#define RTC_TIME_MINT_POSS 12U +#define RTC_TIME_MINT_POSE 14U +#define RTC_TIME_MINT_MSK BITS(RTC_TIME_MINT_POSS,RTC_TIME_MINT_POSE) + +#define RTC_TIME_MINU_POSS 8U +#define RTC_TIME_MINU_POSE 11U +#define RTC_TIME_MINU_MSK BITS(RTC_TIME_MINU_POSS,RTC_TIME_MINU_POSE) + +#define RTC_TIME_SECT_POSS 4U +#define RTC_TIME_SECT_POSE 6U +#define RTC_TIME_SECT_MSK BITS(RTC_TIME_SECT_POSS,RTC_TIME_SECT_POSE) + +#define RTC_TIME_SECU_POSS 0U +#define RTC_TIME_SECU_POSE 3U +#define RTC_TIME_SECU_MSK BITS(RTC_TIME_SECU_POSS,RTC_TIME_SECU_POSE) + +/****************** Bit definition for RTC_DATE register ************************/ + +#define RTC_DATE_WD_POSS 24U +#define RTC_DATE_WD_POSE 26U +#define RTC_DATE_WD_MSK BITS(RTC_DATE_WD_POSS,RTC_DATE_WD_POSE) + +#define RTC_DATE_YRT_POSS 20U +#define RTC_DATE_YRT_POSE 23U +#define RTC_DATE_YRT_MSK BITS(RTC_DATE_YRT_POSS,RTC_DATE_YRT_POSE) + +#define RTC_DATE_YRU_POSS 16U +#define RTC_DATE_YRU_POSE 19U +#define RTC_DATE_YRU_MSK BITS(RTC_DATE_YRU_POSS,RTC_DATE_YRU_POSE) + +#define RTC_DATE_MONT_POS 12U +#define RTC_DATE_MONT_MSK BIT(RTC_DATE_MONT_POS) + +#define RTC_DATE_MONU_POSS 8U +#define RTC_DATE_MONU_POSE 11U +#define RTC_DATE_MONU_MSK BITS(RTC_DATE_MONU_POSS,RTC_DATE_MONU_POSE) + +#define RTC_DATE_DAYT_POSS 4U +#define RTC_DATE_DAYT_POSE 5U +#define RTC_DATE_DAYT_MSK BITS(RTC_DATE_DAYT_POSS,RTC_DATE_DAYT_POSE) + +#define RTC_DATE_DAYU_POSS 0U +#define RTC_DATE_DAYU_POSE 3U +#define RTC_DATE_DAYU_MSK BITS(RTC_DATE_DAYU_POSS,RTC_DATE_DAYU_POSE) + +/****************** Bit definition for RTC_SSEC register ************************/ + +#define RTC_SSEC_VAL_POSS 0U +#define RTC_SSEC_VAL_POSE 15U +#define RTC_SSEC_VAL_MSK BITS(RTC_SSEC_VAL_POSS,RTC_SSEC_VAL_POSE) + +/****************** Bit definition for RTC_WUMAT register ************************/ + +#define RTC_WUMAT_VAL_POSS 0U +#define RTC_WUMAT_VAL_POSE 15U +#define RTC_WUMAT_VAL_MSK BITS(RTC_WUMAT_VAL_POSS,RTC_WUMAT_VAL_POSE) + +/****************** Bit definition for RTC_ALMA register ************************/ + +#define RTC_ALMA_WDS_POS 31U +#define RTC_ALMA_WDS_MSK BIT(RTC_ALMA_WDS_POS) + +#define RTC_ALMA_DAWD_POSS 24U +#define RTC_ALMA_DAWD_POSE 30U +#define RTC_ALMA_DAWD_MSK BITS(RTC_ALMA_DAWD_POSS,RTC_ALMA_DAWD_POSE) + +#define RTC_ALMA_DAYMSK_POS 30U +#define RTC_ALMA_DAYMSK_MSK BIT(RTC_ALMA_DAYMSK_POS) + +#define RTC_ALMA_DAWD_DAYT_POSS 28U +#define RTC_ALMA_DAWD_DAYT_POSE 29U +#define RTC_ALMA_DAWD_DAYT_MSK BITS(RTC_ALMA_DAWD_DAYT_POSS, RTC_ALMA_DAWD_DAYT_POSE) + +#define RTC_ALMA_DAWD_DAYU_POSS 24U +#define RTC_ALMA_DAWD_DAYU_POSE 27U +#define RTC_ALMA_DAWD_DAYU_MSK BITS(RTC_ALMA_DAWD_DAYU_POSS, RTC_ALMA_DAWD_DAYU_POSE) + +#define RTC_ALMA_HRMSK_POS 23U +#define RTC_ALMA_HRMSK_MSK BIT(RTC_ALMA_HRMSK_POS) + +#define RTC_ALMA_PM_POS 22U +#define RTC_ALMA_PM_MSK BIT(RTC_ALMA_PM_POS) + +#define RTC_ALMA_HRT_POSS 20U +#define RTC_ALMA_HRT_POSE 21U +#define RTC_ALMA_HRT_MSK BITS(RTC_ALMA_HRT_POSS,RTC_ALMA_HRT_POSE) + +#define RTC_ALMA_HRU_POSS 16U +#define RTC_ALMA_HRU_POSE 19U +#define RTC_ALMA_HRU_MSK BITS(RTC_ALMA_HRU_POSS,RTC_ALMA_HRU_POSE) + +#define RTC_ALMA_MINMSK_POS 15U +#define RTC_ALMA_MINMSK_MSK BIT(RTC_ALMA_MINMSK_POS) + +#define RTC_ALMA_MINT_POSS 12U +#define RTC_ALMA_MINT_POSE 14U +#define RTC_ALMA_MINT_MSK BITS(RTC_ALMA_MINT_POSS,RTC_ALMA_MINT_POSE) + +#define RTC_ALMA_MINU_POSS 8U +#define RTC_ALMA_MINU_POSE 11U +#define RTC_ALMA_MINU_MSK BITS(RTC_ALMA_MINU_POSS,RTC_ALMA_MINU_POSE) + +#define RTC_ALMA_SECMSK_POS 7U +#define RTC_ALMA_SECMSK_MSK BIT(RTC_ALMA_SECMSK_POS) + +#define RTC_ALMA_SECT_POSS 4U +#define RTC_ALMA_SECT_POSE 6U +#define RTC_ALMA_SECT_MSK BITS(RTC_ALMA_SECT_POSS,RTC_ALMA_SECT_POSE) + +#define RTC_ALMA_SECU_POSS 0U +#define RTC_ALMA_SECU_POSE 3U +#define RTC_ALMA_SECU_MSK BITS(RTC_ALMA_SECU_POSS,RTC_ALMA_SECU_POSE) + +/****************** Bit definition for RTC_ALMB register ************************/ + +#define RTC_ALMB_WDS_POS 31U +#define RTC_ALMB_WDS_MSK BIT(RTC_ALMB_WDS_POS) + +#define RTC_ALMB_DAWD_POSS 24U +#define RTC_ALMB_DAWD_POSE 30U +#define RTC_ALMB_DAWD_MSK BITS(RTC_ALMB_DAWD_POSS,RTC_ALMB_DAWD_POSE) + +#define RTC_ALMB_DAYMSK_POS 30U +#define RTC_ALMB_DAYMSK_MSK BIT(RTC_ALMB_DAYMSK_POS) + +#define RTC_ALMB_DAWD_DAYT_POSS 28U +#define RTC_ALMB_DAWD_DAYT_POSE 29U +#define RTC_ALMB_DAWD_DAYT_MSK BITS(RTC_ALMB_DAWD_DAYT_POSS, RTC_ALMB_DAWD_DAYT_POSE) + +#define RTC_ALMB_DAWD_DAYU_POSS 24U +#define RTC_ALMB_DAWD_DAYU_POSE 27U +#define RTC_ALMB_DAWD_DAYU_MSK BITS(RTC_ALMB_DAWD_DAYU_POSS, RTC_ALMB_DAWD_DAYU_POSE) + +#define RTC_ALMB_HRMSK_POS 23U +#define RTC_ALMB_HRMSK_MSK BIT(RTC_ALMB_HRMSK_POS) + +#define RTC_ALMB_PM_POS 22U +#define RTC_ALMB_PM_MSK BIT(RTC_ALMB_PM_POS) + +#define RTC_ALMB_HRT_POSS 20U +#define RTC_ALMB_HRT_POSE 21U +#define RTC_ALMB_HRT_MSK BITS(RTC_ALMB_HRT_POSS,RTC_ALMB_HRT_POSE) + +#define RTC_ALMB_HRU_POSS 16U +#define RTC_ALMB_HRU_POSE 19U +#define RTC_ALMB_HRU_MSK BITS(RTC_ALMB_HRU_POSS,RTC_ALMB_HRU_POSE) + +#define RTC_ALMB_MINMSK_POS 15U +#define RTC_ALMB_MINMSK_MSK BIT(RTC_ALMB_MINMSK_POS) + +#define RTC_ALMB_MINT_POSS 12U +#define RTC_ALMB_MINT_POSE 14U +#define RTC_ALMB_MINT_MSK BITS(RTC_ALMB_MINT_POSS,RTC_ALMB_MINT_POSE) + +#define RTC_ALMB_MINU_POSS 8U +#define RTC_ALMB_MINU_POSE 11U +#define RTC_ALMB_MINU_MSK BITS(RTC_ALMB_MINU_POSS,RTC_ALMB_MINU_POSE) + +#define RTC_ALMB_SECMSK_POS 7U +#define RTC_ALMB_SECMSK_MSK BIT(RTC_ALMB_SECMSK_POS) + +#define RTC_ALMB_SECT_POSS 4U +#define RTC_ALMB_SECT_POSE 6U +#define RTC_ALMB_SECT_MSK BITS(RTC_ALMB_SECT_POSS,RTC_ALMB_SECT_POSE) + +#define RTC_ALMB_SECU_POSS 0U +#define RTC_ALMB_SECU_POSE 3U +#define RTC_ALMB_SECU_MSK BITS(RTC_ALMB_SECU_POSS,RTC_ALMB_SECU_POSE) + +/****************** Bit definition for RTC_ALMASSEC register ************************/ + +#define RTC_ALMASSEC_SSECM_POSS 24U +#define RTC_ALMASSEC_SSECM_POSE 27U +#define RTC_ALMASSEC_SSECM_MSK BITS(RTC_ALMASSEC_SSECM_POSS,RTC_ALMASSEC_SSECM_POSE) + +#define RTC_ALMASSEC_SSEC_POSS 0U +#define RTC_ALMASSEC_SSEC_POSE 14U +#define RTC_ALMASSEC_SSEC_MSK BITS(RTC_ALMASSEC_SSEC_POSS,RTC_ALMASSEC_SSEC_POSE) + +/****************** Bit definition for RTC_ALMBSSEC register ************************/ + +#define RTC_ALMBSSEC_SSECM_POSS 24U +#define RTC_ALMBSSEC_SSECM_POSE 27U +#define RTC_ALMBSSEC_SSECM_MSK BITS(RTC_ALMBSSEC_SSECM_POSS,RTC_ALMBSSEC_SSECM_POSE) + +#define RTC_ALMBSSEC_SSEC_POSS 0U +#define RTC_ALMBSSEC_SSEC_POSE 14U +#define RTC_ALMBSSEC_SSEC_MSK BITS(RTC_ALMBSSEC_SSEC_POSS,RTC_ALMBSSEC_SSEC_POSE) + +/****************** Bit definition for RTC_TSTIME register ************************/ + +#define RTC_TSTIME_PM_POS 22U +#define RTC_TSTIME_PM_MSK BIT(RTC_TSTIME_PM_POS) + +#define RTC_TSTIME_HRT_POSS 20U +#define RTC_TSTIME_HRT_POSE 21U +#define RTC_TSTIME_HRT_MSK BITS(RTC_TSTIME_HRT_POSS,RTC_TSTIME_HRT_POSE) + +#define RTC_TSTIME_HRU_POSS 16U +#define RTC_TSTIME_HRU_POSE 19U +#define RTC_TSTIME_HRU_MSK BITS(RTC_TSTIME_HRU_POSS,RTC_TSTIME_HRU_POSE) + +#define RTC_TSTIME_MINT_POSS 12U +#define RTC_TSTIME_MINT_POSE 14U +#define RTC_TSTIME_MINT_MSK BITS(RTC_TSTIME_MINT_POSS,RTC_TSTIME_MINT_POSE) + +#define RTC_TSTIME_MINU_POSS 8U +#define RTC_TSTIME_MINU_POSE 11U +#define RTC_TSTIME_MINU_MSK BITS(RTC_TSTIME_MINU_POSS,RTC_TSTIME_MINU_POSE) + +#define RTC_TSTIME_SECT_POSS 4U +#define RTC_TSTIME_SECT_POSE 6U +#define RTC_TSTIME_SECT_MSK BITS(RTC_TSTIME_SECT_POSS,RTC_TSTIME_SECT_POSE) + +#define RTC_TSTIME_SECU_POSS 0U +#define RTC_TSTIME_SECU_POSE 3U +#define RTC_TSTIME_SECU_MSK BITS(RTC_TSTIME_SECU_POSS,RTC_TSTIME_SECU_POSE) + +/****************** Bit definition for RTC_TSDATE register ************************/ + +#define RTC_TSDATE_WD_POSS 24U +#define RTC_TSDATE_WD_POSE 26U +#define RTC_TSDATE_WD_MSK BITS(RTC_TSDATE_WD_POSS,RTC_TSDATE_WD_POSE) + +#define RTC_TSDATE_YRT_POSS 20U +#define RTC_TSDATE_YRT_POSE 23U +#define RTC_TSDATE_YRT_MSK BITS(RTC_TSDATE_YRT_POSS,RTC_TSDATE_YRT_POSE) + +#define RTC_TSDATE_YRU_POSS 16U +#define RTC_TSDATE_YRU_POSE 19U +#define RTC_TSDATE_YRU_MSK BITS(RTC_TSDATE_YRU_POSS,RTC_TSDATE_YRU_POSE) + +#define RTC_TSDATE_MONT_POS 12U +#define RTC_TSDATE_MONT_MSK BIT(RTC_TSDATE_MONT_POS) + +#define RTC_TSDATE_MONU_POSS 8U +#define RTC_TSDATE_MONU_POSE 11U +#define RTC_TSDATE_MONU_MSK BITS(RTC_TSDATE_MONU_POSS,RTC_TSDATE_MONU_POSE) + +#define RTC_TSDATE_DAYT_POSS 4U +#define RTC_TSDATE_DAYT_POSE 5U +#define RTC_TSDATE_DAYT_MSK BITS(RTC_TSDATE_DAYT_POSS,RTC_TSDATE_DAYT_POSE) + +#define RTC_TSDATE_DAYU_POSS 0U +#define RTC_TSDATE_DAYU_POSE 3U +#define RTC_TSDATE_DAYU_MSK BITS(RTC_TSDATE_DAYU_POSS,RTC_TSDATE_DAYU_POSE) + +/****************** Bit definition for RTC_TSSSEC register ************************/ + +#define RTC_TSSSEC_SSEC_POSS 0U +#define RTC_TSSSEC_SSEC_POSE 15U +#define RTC_TSSSEC_SSEC_MSK BITS(RTC_TSSSEC_SSEC_POSS,RTC_TSSSEC_SSEC_POSE) + +/****************** Bit definition for RTC_SSECTR register ************************/ + +#define RTC_SSECTR_INC_POS 31U +#define RTC_SSECTR_INC_MSK BIT(RTC_SSECTR_INC_POS) + +#define RTC_SSECTR_TRIM_POSS 0U +#define RTC_SSECTR_TRIM_POSE 14U +#define RTC_SSECTR_TRIM_MSK BITS(RTC_SSECTR_TRIM_POSS,RTC_SSECTR_TRIM_POSE) + +/****************** Bit definition for RTC_IER register ************************/ + +#define RTC_IER_TCE_POS 25U +#define RTC_IER_TCE_MSK BIT(RTC_IER_TCE_POS) + +#define RTC_IER_TCC_POS 24U +#define RTC_IER_TCC_MSK BIT(RTC_IER_TCC_POS) + +#define RTC_IER_WU_POS 18U +#define RTC_IER_WU_MSK BIT(RTC_IER_WU_POS) + +#define RTC_IER_SSTC_POS 17U +#define RTC_IER_SSTC_MSK BIT(RTC_IER_SSTC_POS) + +#define RTC_IER_RSC_POS 16U +#define RTC_IER_RSC_MSK BIT(RTC_IER_RSC_POS) + +#define RTC_IER_TAMP2_POS 13U +#define RTC_IER_TAMP2_MSK BIT(RTC_IER_TAMP2_POS) + +#define RTC_IER_TAMP1_POS 12U +#define RTC_IER_TAMP1_MSK BIT(RTC_IER_TAMP1_POS) + +#define RTC_IER_TSOV_POS 11U +#define RTC_IER_TSOV_MSK BIT(RTC_IER_TSOV_POS) + +#define RTC_IER_TS_POS 10U +#define RTC_IER_TS_MSK BIT(RTC_IER_TS_POS) + +#define RTC_IER_ALMB_POS 9U +#define RTC_IER_ALMB_MSK BIT(RTC_IER_ALMB_POS) + +#define RTC_IER_ALMA_POS 8U +#define RTC_IER_ALMA_MSK BIT(RTC_IER_ALMA_POS) + +#define RTC_IER_YR_POS 5U +#define RTC_IER_YR_MSK BIT(RTC_IER_YR_POS) + +#define RTC_IER_MON_POS 4U +#define RTC_IER_MON_MSK BIT(RTC_IER_MON_POS) + +#define RTC_IER_DAY_POS 3U +#define RTC_IER_DAY_MSK BIT(RTC_IER_DAY_POS) + +#define RTC_IER_HR_POS 2U +#define RTC_IER_HR_MSK BIT(RTC_IER_HR_POS) + +#define RTC_IER_MIN_POS 1U +#define RTC_IER_MIN_MSK BIT(RTC_IER_MIN_POS) + +#define RTC_IER_SEC_POS 0U +#define RTC_IER_SEC_MSK BIT(RTC_IER_SEC_POS) + +/****************** Bit definition for RTC_IFR register ************************/ + +#define RTC_IFR_TCEF_POS 25U +#define RTC_IFR_TCEF_MSK BIT(RTC_IFR_TCEF_POS) + +#define RTC_IFR_TCCF_POS 24U +#define RTC_IFR_TCCF_MSK BIT(RTC_IFR_TCCF_POS) + +#define RTC_IFR_WUF_POS 18U +#define RTC_IFR_WUF_MSK BIT(RTC_IFR_WUF_POS) + +#define RTC_IFR_SSTCF_POS 17U +#define RTC_IFR_SSTCF_MSK BIT(RTC_IFR_SSTCF_POS) + +#define RTC_IFR_RSCF_POS 16U +#define RTC_IFR_RSCF_MSK BIT(RTC_IFR_RSCF_POS) + +#define RTC_IFR_TAMP2F_POS 13U +#define RTC_IFR_TAMP2F_MSK BIT(RTC_IFR_TAMP2F_POS) + +#define RTC_IFR_TAMP1F_POS 12U +#define RTC_IFR_TAMP1F_MSK BIT(RTC_IFR_TAMP1F_POS) + +#define RTC_IFR_TSOVF_POS 11U +#define RTC_IFR_TSOVF_MSK BIT(RTC_IFR_TSOVF_POS) + +#define RTC_IFR_TSF_POS 10U +#define RTC_IFR_TSF_MSK BIT(RTC_IFR_TSF_POS) + +#define RTC_IFR_ALMBF_POS 9U +#define RTC_IFR_ALMBF_MSK BIT(RTC_IFR_ALMBF_POS) + +#define RTC_IFR_ALMAF_POS 8U +#define RTC_IFR_ALMAF_MSK BIT(RTC_IFR_ALMAF_POS) + +#define RTC_IFR_YRF_POS 5U +#define RTC_IFR_YRF_MSK BIT(RTC_IFR_YRF_POS) + +#define RTC_IFR_MONF_POS 4U +#define RTC_IFR_MONF_MSK BIT(RTC_IFR_MONF_POS) + +#define RTC_IFR_DAYF_POS 3U +#define RTC_IFR_DAYF_MSK BIT(RTC_IFR_DAYF_POS) + +#define RTC_IFR_HRF_POS 2U +#define RTC_IFR_HRF_MSK BIT(RTC_IFR_HRF_POS) + +#define RTC_IFR_MINF_POS 1U +#define RTC_IFR_MINF_MSK BIT(RTC_IFR_MINF_POS) + +#define RTC_IFR_SECF_POS 0U +#define RTC_IFR_SECF_MSK BIT(RTC_IFR_SECF_POS) + +/****************** Bit definition for RTC_IFCR register ************************/ + +#define RTC_IFCR_TCEFC_POS 25U +#define RTC_IFCR_TCEFC_MSK BIT(RTC_IFCR_TCEFC_POS) + +#define RTC_IFCR_TCCFC_POS 24U +#define RTC_IFCR_TCCFC_MSK BIT(RTC_IFCR_TCCFC_POS) + +#define RTC_IFCR_WUFC_POS 18U +#define RTC_IFCR_WUFC_MSK BIT(RTC_IFCR_WUFC_POS) + +#define RTC_IFCR_SSTCFC_POS 17U +#define RTC_IFCR_SSTCFC_MSK BIT(RTC_IFCR_SSTCFC_POS) + +#define RTC_IFCR_RSCFC_POS 16U +#define RTC_IFCR_RSCFC_MSK BIT(RTC_IFCR_RSCFC_POS) + +#define RTC_IFCR_TAMP2FC_POS 13U +#define RTC_IFCR_TAMP2FC_MSK BIT(RTC_IFCR_TAMP2FC_POS) + +#define RTC_IFCR_TAMP1FC_POS 12U +#define RTC_IFCR_TAMP1FC_MSK BIT(RTC_IFCR_TAMP1FC_POS) + +#define RTC_IFCR_TSOVFC_POS 11U +#define RTC_IFCR_TSOVFC_MSK BIT(RTC_IFCR_TSOVFC_POS) + +#define RTC_IFCR_TSSTC_POS 10U +#define RTC_IFCR_TSSTC_MSK BIT(RTC_IFCR_TSSTC_POS) + +#define RTC_IFCR_ALMBFC_POS 9U +#define RTC_IFCR_ALMBFC_MSK BIT(RTC_IFCR_ALMBFC_POS) + +#define RTC_IFCR_ALMAFC_POS 8U +#define RTC_IFCR_ALMAFC_MSK BIT(RTC_IFCR_ALMAFC_POS) + +#define RTC_IFCR_YRFC_POS 5U +#define RTC_IFCR_YRFC_MSK BIT(RTC_IFCR_YRFC_POS) + +#define RTC_IFCR_MONFC_POS 4U +#define RTC_IFCR_MONFC_MSK BIT(RTC_IFCR_MONFC_POS) + +#define RTC_IFCR_DAYFC_POS 3U +#define RTC_IFCR_DAYFC_MSK BIT(RTC_IFCR_DAYFC_POS) + +#define RTC_IFCR_HRFC_POS 2U +#define RTC_IFCR_HRFC_MSK BIT(RTC_IFCR_HRFC_POS) + +#define RTC_IFCR_MINFC_POS 1U +#define RTC_IFCR_MINFC_MSK BIT(RTC_IFCR_MINFC_POS) + +#define RTC_IFCR_SECFC_POS 0U +#define RTC_IFCR_SECFC_MSK BIT(RTC_IFCR_SECFC_POS) + +/****************** Bit definition for RTC_ISR register ************************/ + +#define RTC_ISR_TCEF_POS 25U +#define RTC_ISR_TCEF_MSK BIT(RTC_ISR_TCEF_POS) + +#define RTC_ISR_TCCF_POS 24U +#define RTC_ISR_TCCF_MSK BIT(RTC_ISR_TCCF_POS) + +#define RTC_ISR_WUF_POS 18U +#define RTC_ISR_WUF_MSK BIT(RTC_ISR_WUF_POS) + +#define RTC_ISR_SSTCF_POS 17U +#define RTC_ISR_SSTCF_MSK BIT(RTC_ISR_SSTCF_POS) + +#define RTC_ISR_RSCF_POS 16U +#define RTC_ISR_RSCF_MSK BIT(RTC_ISR_RSCF_POS) + +#define RTC_ISR_TAMP2F_POS 13U +#define RTC_ISR_TAMP2F_MSK BIT(RTC_ISR_TAMP2F_POS) + +#define RTC_ISR_TAMP1F_POS 12U +#define RTC_ISR_TAMP1F_MSK BIT(RTC_ISR_TAMP1F_POS) + +#define RTC_ISR_TSOVF_POS 11U +#define RTC_ISR_TSOVF_MSK BIT(RTC_ISR_TSOVF_POS) + +#define RTC_ISR_TSF_POS 10U +#define RTC_ISR_TSF_MSK BIT(RTC_ISR_TSF_POS) + +#define RTC_ISR_ALMBF_POS 9U +#define RTC_ISR_ALMBF_MSK BIT(RTC_ISR_ALMBF_POS) + +#define RTC_ISR_ALMAF_POS 8U +#define RTC_ISR_ALMAF_MSK BIT(RTC_ISR_ALMAF_POS) + +#define RTC_ISR_YRF_POS 5U +#define RTC_ISR_YRF_MSK BIT(RTC_ISR_YRF_POS) + +#define RTC_ISR_MONF_POS 4U +#define RTC_ISR_MONF_MSK BIT(RTC_ISR_MONF_POS) + +#define RTC_ISR_DAYF_POS 3U +#define RTC_ISR_DAYF_MSK BIT(RTC_ISR_DAYF_POS) + +#define RTC_ISR_HRF_POS 2U +#define RTC_ISR_HRF_MSK BIT(RTC_ISR_HRF_POS) + +#define RTC_ISR_MINF_POS 1U +#define RTC_ISR_MINF_MSK BIT(RTC_ISR_MINF_POS) + +#define RTC_ISR_SECF_POS 0U +#define RTC_ISR_SECF_MSK BIT(RTC_ISR_SECF_POS) + +/****************** Bit definition for RTC_CALWPR register ************************/ + +#define RTC_CALWPR_WP_POS 0U +#define RTC_CALWPR_WP_MSK BIT(RTC_CALWPR_WP_POS) + +/****************** Bit definition for RTC_CALCON register ************************/ + +#define RTC_CALCON_DCMACC_POS 24U +#define RTC_CALCON_DCMACC_MSK BIT(RTC_CALCON_DCMACC_POS) + +#define RTC_CALCON_ALG_POS 23U +#define RTC_CALCON_ALG_MSK BIT(RTC_CALCON_ALG_POS) + +#define RTC_CALCON_TCP_POSS 20U +#define RTC_CALCON_TCP_POSE 22U +#define RTC_CALCON_TCP_MSK BITS(RTC_CALCON_TCP_POSS,RTC_CALCON_TCP_POSE) + +#define RTC_CALCON_ERR_POS 19U +#define RTC_CALCON_ERR_MSK BIT(RTC_CALCON_ERR_POS) + +#define RTC_CALCON_BUSY_POS 18U +#define RTC_CALCON_BUSY_MSK BIT(RTC_CALCON_BUSY_POS) + +#define RTC_CALCON_TCM_POSS 16U +#define RTC_CALCON_TCM_POSE 17U +#define RTC_CALCON_TCM_MSK BITS(RTC_CALCON_TCM_POSS,RTC_CALCON_TCM_POSE) + +#define RTC_CALCON_CALP_POSS 1U +#define RTC_CALCON_CALP_POSE 3U +#define RTC_CALCON_CALP_MSK BITS(RTC_CALCON_CALP_POSS,RTC_CALCON_CALP_POSE) + +#define RTC_CALCON_CALEN_POS 0U +#define RTC_CALCON_CALEN_MSK BIT(RTC_CALCON_CALEN_POS) + +/****************** Bit definition for RTC_CALDR register ************************/ + +#define RTC_CALDR_DATA_POSS 16U +#define RTC_CALDR_DATA_POSE 31U +#define RTC_CALDR_DATA_MSK BITS(RTC_CALDR_DATA_POSS,RTC_CALDR_DATA_POSE) + +#define RTC_CALDR_VAL_POSS 0U +#define RTC_CALDR_VAL_POSE 15U +#define RTC_CALDR_VAL_MSK BITS(RTC_CALDR_VAL_POSS,RTC_CALDR_VAL_POSE) + +/****************** Bit definition for RTC_TEMPR register ************************/ + +#define RTC_TEMPR_DATA_POSS 16U +#define RTC_TEMPR_DATA_POSE 31U +#define RTC_TEMPR_DATA_MSK BITS(RTC_TEMPR_DATA_POSS,RTC_TEMPR_DATA_POSE) + +#define RTC_TEMPR_VAL_POSS 0U +#define RTC_TEMPR_VAL_POSE 15U +#define RTC_TEMPR_VAL_MSK BITS(RTC_TEMPR_VAL_POSS,RTC_TEMPR_VAL_POSE) + +/****************** Bit definition for RTC_TEMPBDR register ************************/ + +#define RTC_TEMPBDR_VAL_POSS 0U +#define RTC_TEMPBDR_VAL_POSE 15U +#define RTC_TEMPBDR_VAL_MSK BITS(RTC_TEMPBDR_VAL_POSS,RTC_TEMPBDR_VAL_POSE) + +/****************** Bit definition for RTC_BKP register ************************/ + +#define RTC_BKP_BKP_POSS 0U +#define RTC_BKP_BKP_POSE 31U +#define RTC_BKP_BKP_MSK BITS(RTC_BKP_BKP_POSS,RTC_BKP_BKP_POSE) + +typedef struct +{ + __IO uint32_t WPR; + __IO uint32_t CON; + __IO uint32_t PSR; + __IO uint32_t TAMPCON; + __IO uint32_t TIME; + __IO uint32_t DATE; + __IO uint32_t SSEC; + __IO uint32_t WUMAT; + __IO uint32_t ALMA; + __IO uint32_t ALMB; + __IO uint32_t ALMASSEC; + __IO uint32_t ALMBSSEC; + __I uint32_t TSTIME; + __I uint32_t TSDATE; + __I uint32_t TSSSEC; + __O uint32_t SSECTR; + __IO uint32_t IER; + __I uint32_t IFR; + __O uint32_t IFCR; + __I uint32_t ISR; + __IO uint32_t CALWPR; + __IO uint32_t CALCON; + __IO uint32_t CALDR; + __IO uint32_t TEMPR; + __IO uint32_t LTCAR; + __IO uint32_t LTCBR; + __IO uint32_t LTCCR; + __IO uint32_t LTCDR; + __IO uint32_t LTCER; + __IO uint32_t HTCAR; + __IO uint32_t HTCBR; + __IO uint32_t HTCCR; + __IO uint32_t HTCDR; + __IO uint32_t HTCER; + __IO uint32_t TEMPBDR; + uint32_t RESERVED0[29] ; + __IO uint32_t BKPR[32]; +} RTC_TypeDef; + +/****************** Bit definition for TIMER_CON1 register ************************/ + +#define TIMER_CON1_DFCKSEL_POSS 8U +#define TIMER_CON1_DFCKSEL_POSE 9U +#define TIMER_CON1_DFCKSEL_MSK BITS(TIMER_CON1_DFCKSEL_POSS,TIMER_CON1_DFCKSEL_POSE) + +#define TIMER_CON1_ARPEN_POS 7U +#define TIMER_CON1_ARPEN_MSK BIT(TIMER_CON1_ARPEN_POS) + +#define TIMER_CON1_CMSEL_POSS 5U +#define TIMER_CON1_CMSEL_POSE 6U +#define TIMER_CON1_CMSEL_MSK BITS(TIMER_CON1_CMSEL_POSS,TIMER_CON1_CMSEL_POSE) + +#define TIMER_CON1_DIRSEL_POS 4U +#define TIMER_CON1_DIRSEL_MSK BIT(TIMER_CON1_DIRSEL_POS) + +#define TIMER_CON1_SPMEN_POS 3U +#define TIMER_CON1_SPMEN_MSK BIT(TIMER_CON1_SPMEN_POS) + +#define TIMER_CON1_UERSEL_POS 2U +#define TIMER_CON1_UERSEL_MSK BIT(TIMER_CON1_UERSEL_POS) + +#define TIMER_CON1_DISUE_POS 1U +#define TIMER_CON1_DISUE_MSK BIT(TIMER_CON1_DISUE_POS) + +#define TIMER_CON1_CNTEN_POS 0U +#define TIMER_CON1_CNTEN_MSK BIT(TIMER_CON1_CNTEN_POS) + +/****************** Bit definition for TIMER_CON2 register ************************/ + +#define TIMER_CON2_OISS4_POS 14U +#define TIMER_CON2_OISS4_MSK BIT(TIMER_CON2_OISS4_POS) + +#define TIMER_CON2_OISS3N_POS 13U +#define TIMER_CON2_OISS3N_MSK BIT(TIMER_CON2_OISS3N_POS) + +#define TIMER_CON2_OISS3_POS 12U +#define TIMER_CON2_OISS3_MSK BIT(TIMER_CON2_OISS3_POS) + +#define TIMER_CON2_OISS2N_POS 11U +#define TIMER_CON2_OISS2N_MSK BIT(TIMER_CON2_OISS2N_POS) + +#define TIMER_CON2_OISS2_POS 10U +#define TIMER_CON2_OISS2_MSK BIT(TIMER_CON2_OISS2_POS) + +#define TIMER_CON2_OISS1N_POS 9U +#define TIMER_CON2_OISS1N_MSK BIT(TIMER_CON2_OISS1N_POS) + +#define TIMER_CON2_OISS1_POS 8U +#define TIMER_CON2_OISS1_MSK BIT(TIMER_CON2_OISS1_POS) + +#define TIMER_CON2_I1FSEL_POS 7U +#define TIMER_CON2_I1FSEL_MSK BIT(TIMER_CON2_I1FSEL_POS) + +#define TIMER_CON2_TRGOSEL_POSS 4U +#define TIMER_CON2_TRGOSEL_POSE 6U +#define TIMER_CON2_TRGOSEL_MSK BITS(TIMER_CON2_TRGOSEL_POSS,TIMER_CON2_TRGOSEL_POSE) + +#define TIMER_CON2_CCDMASEL_POS 3U +#define TIMER_CON2_CCDMASEL_MSK BIT(TIMER_CON2_CCDMASEL_POS) + +#define TIMER_CON2_CCUSEL_POS 2U +#define TIMER_CON2_CCUSEL_MSK BIT(TIMER_CON2_CCUSEL_POS) + +#define TIMER_CON2_CCPCEN_POS 0U +#define TIMER_CON2_CCPCEN_MSK BIT(TIMER_CON2_CCPCEN_POS) + +/****************** Bit definition for TIMER_SMCON register ************************/ + +#define TIMER_SMCON_ETPOL_POS 15U +#define TIMER_SMCON_ETPOL_MSK BIT(TIMER_SMCON_ETPOL_POS) + +#define TIMER_SMCON_ECM2EN_POS 14U +#define TIMER_SMCON_ECM2EN_MSK BIT(TIMER_SMCON_ECM2EN_POS) + +#define TIMER_SMCON_ETPSEL_POSS 12U +#define TIMER_SMCON_ETPSEL_POSE 13U +#define TIMER_SMCON_ETPSEL_MSK BITS(TIMER_SMCON_ETPSEL_POSS,TIMER_SMCON_ETPSEL_POSE) + +#define TIMER_SMCON_ETFLT_POSS 8U +#define TIMER_SMCON_ETFLT_POSE 11U +#define TIMER_SMCON_ETFLT_MSK BITS(TIMER_SMCON_ETFLT_POSS,TIMER_SMCON_ETFLT_POSE) + +#define TIMER_SMCON_MSCFG_POS 7U +#define TIMER_SMCON_MSCFG_MSK BIT(TIMER_SMCON_MSCFG_POS) + +#define TIMER_SMCON_TSSEL_POSS 4U +#define TIMER_SMCON_TSSEL_POSE 6U +#define TIMER_SMCON_TSSEL_MSK BITS(TIMER_SMCON_TSSEL_POSS,TIMER_SMCON_TSSEL_POSE) + +#define TIMER_SMCON_SMODS_POSS 0U +#define TIMER_SMCON_SMODS_POSE 2U +#define TIMER_SMCON_SMODS_MSK BITS(TIMER_SMCON_SMODS_POSS,TIMER_SMCON_SMODS_POSE) + +/****************** Bit definition for TIMER_DIER register ************************/ + +#define TIMER_DIER_TRGDMA_POS 14U +#define TIMER_DIER_TRGDMA_MSK BIT(TIMER_DIER_TRGDMA_POS) + +#define TIMER_DIER_COMDMA_POS 13U +#define TIMER_DIER_COMDMA_MSK BIT(TIMER_DIER_COMDMA_POS) + +#define TIMER_DIER_CC4DMA_POS 12U +#define TIMER_DIER_CC4DMA_MSK BIT(TIMER_DIER_CC4DMA_POS) + +#define TIMER_DIER_CC3DMA_POS 11U +#define TIMER_DIER_CC3DMA_MSK BIT(TIMER_DIER_CC3DMA_POS) + +#define TIMER_DIER_CC2DMA_POS 10U +#define TIMER_DIER_CC2DMA_MSK BIT(TIMER_DIER_CC2DMA_POS) + +#define TIMER_DIER_CC1DMA_POS 9U +#define TIMER_DIER_CC1DMA_MSK BIT(TIMER_DIER_CC1DMA_POS) + +#define TIMER_DIER_UDMA_POS 8U +#define TIMER_DIER_UDMA_MSK BIT(TIMER_DIER_UDMA_POS) + +#define TIMER_DIER_BRKIT_POS 7U +#define TIMER_DIER_BRKIT_MSK BIT(TIMER_DIER_BRKIT_POS) + +#define TIMER_DIER_TRGIT_POS 6U +#define TIMER_DIER_TRGIT_MSK BIT(TIMER_DIER_TRGIT_POS) + +#define TIMER_DIER_COMIT_POS 5U +#define TIMER_DIER_COMIT_MSK BIT(TIMER_DIER_COMIT_POS) + +#define TIMER_DIER_CC4IT_POS 4U +#define TIMER_DIER_CC4IT_MSK BIT(TIMER_DIER_CC4IT_POS) + +#define TIMER_DIER_CC3IT_POS 3U +#define TIMER_DIER_CC3IT_MSK BIT(TIMER_DIER_CC3IT_POS) + +#define TIMER_DIER_CC2IT_POS 2U +#define TIMER_DIER_CC2IT_MSK BIT(TIMER_DIER_CC2IT_POS) + +#define TIMER_DIER_CC1IT_POS 1U +#define TIMER_DIER_CC1IT_MSK BIT(TIMER_DIER_CC1IT_POS) + +#define TIMER_DIER_UIT_POS 0U +#define TIMER_DIER_UIT_MSK BIT(TIMER_DIER_UIT_POS) + +/****************** Bit definition for TIMER_DIDR register ************************/ + +#define TIMER_DIDR_TRGDMA_POS 14U +#define TIMER_DIDR_TRGDMA_MSK BIT(TIMER_DIDR_TRGDMA_POS) + +#define TIMER_DIDR_COMD_POS 13U +#define TIMER_DIDR_COMD_MSK BIT(TIMER_DIDR_COMD_POS) + +#define TIMER_DIDR_CC4D_POS 12U +#define TIMER_DIDR_CC4D_MSK BIT(TIMER_DIDR_CC4D_POS) + +#define TIMER_DIDR_CC3D_POS 11U +#define TIMER_DIDR_CC3D_MSK BIT(TIMER_DIDR_CC3D_POS) + +#define TIMER_DIDR_CC2D_POS 10U +#define TIMER_DIDR_CC2D_MSK BIT(TIMER_DIDR_CC2D_POS) + +#define TIMER_DIDR_CC1D_POS 9U +#define TIMER_DIDR_CC1D_MSK BIT(TIMER_DIDR_CC1D_POS) + +#define TIMER_DIDR_UD_POS 8U +#define TIMER_DIDR_UD_MSK BIT(TIMER_DIDR_UD_POS) + +#define TIMER_DIDR_BRKI_POS 7U +#define TIMER_DIDR_BRKI_MSK BIT(TIMER_DIDR_BRKI_POS) + +#define TIMER_DIDR_TRGI_POS 6U +#define TIMER_DIDR_TRGI_MSK BIT(TIMER_DIDR_TRGI_POS) + +#define TIMER_DIDR_COMI_POS 5U +#define TIMER_DIDR_COMI_MSK BIT(TIMER_DIDR_COMI_POS) + +#define TIMER_DIDR_CC4I_POS 4U +#define TIMER_DIDR_CC4I_MSK BIT(TIMER_DIDR_CC4I_POS) + +#define TIMER_DIDR_CC3I_POS 3U +#define TIMER_DIDR_CC3I_MSK BIT(TIMER_DIDR_CC3I_POS) + +#define TIMER_DIDR_CC2I_POS 2U +#define TIMER_DIDR_CC2I_MSK BIT(TIMER_DIDR_CC2I_POS) + +#define TIMER_DIDR_CC1I_POS 1U +#define TIMER_DIDR_CC1I_MSK BIT(TIMER_DIDR_CC1I_POS) + +#define TIMER_DIDR_UI_POS 0U +#define TIMER_DIDR_UI_MSK BIT(TIMER_DIDR_UI_POS) + +/****************** Bit definition for TIMER_DIVS register ************************/ + +#define TIMER_DIVS_TRGDMA_POS 14U +#define TIMER_DIVS_TRGDMA_MSK BIT(TIMER_DIVS_TRGDMA_POS) + +#define TIMER_DIVS_COMDMA_POS 13U +#define TIMER_DIVS_COMDMA_MSK BIT(TIMER_DIVS_COMDMA_POS) + +#define TIMER_DIVS_CC4DMA_POS 12U +#define TIMER_DIVS_CC4DMA_MSK BIT(TIMER_DIVS_CC4DMA_POS) + +#define TIMER_DIVS_CC3DMA_POS 11U +#define TIMER_DIVS_CC3DMA_MSK BIT(TIMER_DIVS_CC3DMA_POS) + +#define TIMER_DIVS_CC2DMA_POS 10U +#define TIMER_DIVS_CC2DMA_MSK BIT(TIMER_DIVS_CC2DMA_POS) + +#define TIMER_DIVS_CC1DMA_POS 9U +#define TIMER_DIVS_CC1DMA_MSK BIT(TIMER_DIVS_CC1DMA_POS) + +#define TIMER_DIVS_UEDTR_POS 8U +#define TIMER_DIVS_UEDTR_MSK BIT(TIMER_DIVS_UEDTR_POS) + +#define TIMER_DIVS_BKI_POS 7U +#define TIMER_DIVS_BKI_MSK BIT(TIMER_DIVS_BKI_POS) + +#define TIMER_DIVS_TRGI_POS 6U +#define TIMER_DIVS_TRGI_MSK BIT(TIMER_DIVS_TRGI_POS) + +#define TIMER_DIVS_COMI_POS 5U +#define TIMER_DIVS_COMI_MSK BIT(TIMER_DIVS_COMI_POS) + +#define TIMER_DIVS_CC4I_POS 4U +#define TIMER_DIVS_CC4I_MSK BIT(TIMER_DIVS_CC4I_POS) + +#define TIMER_DIVS_CC3I_POS 3U +#define TIMER_DIVS_CC3I_MSK BIT(TIMER_DIVS_CC3I_POS) + +#define TIMER_DIVS_CC2I_POS 2U +#define TIMER_DIVS_CC2I_MSK BIT(TIMER_DIVS_CC2I_POS) + +#define TIMER_DIVS_CC1I_POS 1U +#define TIMER_DIVS_CC1I_MSK BIT(TIMER_DIVS_CC1I_POS) + +#define TIMER_DIVS_UEI_POS 0U +#define TIMER_DIVS_UEI_MSK BIT(TIMER_DIVS_UEI_POS) + +/****************** Bit definition for TIMER_RIF register ************************/ + +#define TIMER_RIF_CH4OVIF_POS 12U +#define TIMER_RIF_CH4OVIF_MSK BIT(TIMER_RIF_CH4OVIF_POS) + +#define TIMER_RIF_CH3OVIF_POS 11U +#define TIMER_RIF_CH3OVIF_MSK BIT(TIMER_RIF_CH3OVIF_POS) + +#define TIMER_RIF_CH2OVIF_POS 10U +#define TIMER_RIF_CH2OVIF_MSK BIT(TIMER_RIF_CH2OVIF_POS) + +#define TIMER_RIF_CH1OVIF_POS 9U +#define TIMER_RIF_CH1OVIF_MSK BIT(TIMER_RIF_CH1OVIF_POS) + +#define TIMER_RIF_BRKIF_POS 7U +#define TIMER_RIF_BRKIF_MSK BIT(TIMER_RIF_BRKIF_POS) + +#define TIMER_RIF_TRGIF_POS 6U +#define TIMER_RIF_TRGIF_MSK BIT(TIMER_RIF_TRGIF_POS) + +#define TIMER_RIF_COMIF_POS 5U +#define TIMER_RIF_COMIF_MSK BIT(TIMER_RIF_COMIF_POS) + +#define TIMER_RIF_CH4IF_POS 4U +#define TIMER_RIF_CH4IF_MSK BIT(TIMER_RIF_CH4IF_POS) + +#define TIMER_RIF_CH3IF_POS 3U +#define TIMER_RIF_CH3IF_MSK BIT(TIMER_RIF_CH3IF_POS) + +#define TIMER_RIF_CH2IF_POS 2U +#define TIMER_RIF_CH2IF_MSK BIT(TIMER_RIF_CH2IF_POS) + +#define TIMER_RIF_CH1IF_POS 1U +#define TIMER_RIF_CH1IF_MSK BIT(TIMER_RIF_CH1IF_POS) + +#define TIMER_RIF_UEVTIF_POS 0U +#define TIMER_RIF_UEVTIF_MSK BIT(TIMER_RIF_UEVTIF_POS) + +/****************** Bit definition for TIMER_IFM register ************************/ + +#define TIMER_IFM_BRKIM_POS 7U +#define TIMER_IFM_BRKIM_MSK BIT(TIMER_IFM_BRKIM_POS) + +#define TIMER_IFM_TRGI_POS 6U +#define TIMER_IFM_TRGI_MSK BIT(TIMER_IFM_TRGI_POS) + +#define TIMER_IFM_COMI_POS 5U +#define TIMER_IFM_COMI_MSK BIT(TIMER_IFM_COMI_POS) + +#define TIMER_IFM_CH4CCI_POS 4U +#define TIMER_IFM_CH4CCI_MSK BIT(TIMER_IFM_CH4CCI_POS) + +#define TIMER_IFM_CH3CCI_POS 3U +#define TIMER_IFM_CH3CCI_MSK BIT(TIMER_IFM_CH3CCI_POS) + +#define TIMER_IFM_CH2CCI_POS 2U +#define TIMER_IFM_CH2CCI_MSK BIT(TIMER_IFM_CH2CCI_POS) + +#define TIMER_IFM_CH1CCI_POS 1U +#define TIMER_IFM_CH1CCI_MSK BIT(TIMER_IFM_CH1CCI_POS) + +#define TIMER_IFM_UEI_POS 0U +#define TIMER_IFM_UEI_MSK BIT(TIMER_IFM_UEI_POS) + +/****************** Bit definition for TIMER_ICR register ************************/ + +#define TIMER_ICR_BRKIC_POS 7U +#define TIMER_ICR_BRKIC_MSK BIT(TIMER_ICR_BRKIC_POS) + +#define TIMER_ICR_TRGIC_POS 6U +#define TIMER_ICR_TRGIC_MSK BIT(TIMER_ICR_TRGIC_POS) + +#define TIMER_ICR_COMIC_POS 5U +#define TIMER_ICR_COMIC_MSK BIT(TIMER_ICR_COMIC_POS) + +#define TIMER_ICR_CH4CCIC_POS 4U +#define TIMER_ICR_CH4CCIC_MSK BIT(TIMER_ICR_CH4CCIC_POS) + +#define TIMER_ICR_CH3CCIC_POS 3U +#define TIMER_ICR_CH3CCIC_MSK BIT(TIMER_ICR_CH3CCIC_POS) + +#define TIMER_ICR_CH2CCIC_POS 2U +#define TIMER_ICR_CH2CCIC_MSK BIT(TIMER_ICR_CH2CCIC_POS) + +#define TIMER_ICR_CH1CCIC_POS 1U +#define TIMER_ICR_CH1CCIC_MSK BIT(TIMER_ICR_CH1CCIC_POS) + +#define TIMER_ICR_UEIC_POS 0U +#define TIMER_ICR_UEIC_MSK BIT(TIMER_ICR_UEIC_POS) + +/****************** Bit definition for TIMER_SGE register ************************/ + +#define TIMER_SGE_SGBRK_POS 7U +#define TIMER_SGE_SGBRK_MSK BIT(TIMER_SGE_SGBRK_POS) + +#define TIMER_SGE_SGTRG_POS 6U +#define TIMER_SGE_SGTRG_MSK BIT(TIMER_SGE_SGTRG_POS) + +#define TIMER_SGE_SGCOM_POS 5U +#define TIMER_SGE_SGCOM_MSK BIT(TIMER_SGE_SGCOM_POS) + +#define TIMER_SGE_SGCC4E_POS 4U +#define TIMER_SGE_SGCC4E_MSK BIT(TIMER_SGE_SGCC4E_POS) + +#define TIMER_SGE_SGCC3E_POS 3U +#define TIMER_SGE_SGCC3E_MSK BIT(TIMER_SGE_SGCC3E_POS) + +#define TIMER_SGE_SGCC2E_POS 2U +#define TIMER_SGE_SGCC2E_MSK BIT(TIMER_SGE_SGCC2E_POS) + +#define TIMER_SGE_SGCC1E_POS 1U +#define TIMER_SGE_SGCC1E_MSK BIT(TIMER_SGE_SGCC1E_POS) + +#define TIMER_SGE_SGU_POS 0U +#define TIMER_SGE_SGU_MSK BIT(TIMER_SGE_SGU_POS) + +/****************** Bit definition for TIMER_CHMR1 register ************************/ +/* Output */ +#define TIMER_CHMR1_CH2OCLREN_POS 15U +#define TIMER_CHMR1_CH2OCLREN_MSK BIT(TIMER_CHMR1_CH2OCLREN_POS) + +#define TIMER_CHMR1_CH2OMOD_POSS 12U +#define TIMER_CHMR1_CH2OMOD_POSE 14U +#define TIMER_CHMR1_CH2OMOD_MSK BITS(TIMER_CHMR1_CH2OMOD_POSS,TIMER_CHMR1_CH2OMOD_POSE) + +#define TIMER_CHMR1_CH2OPEN_POS 11U +#define TIMER_CHMR1_CH2OPEN_MSK BIT(TIMER_CHMR1_CH2OPEN_POS) + +#define TIMER_CHMR1_CH2OFEN_POS 10U +#define TIMER_CHMR1_CH2OFEN_MSK BIT(TIMER_CHMR1_CH2OFEN_POS) + +#define TIMER_CHMR1_CC2SSEL_POSS 8U +#define TIMER_CHMR1_CC2SSEL_POSE 9U +#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) + +#define TIMER_CHMR1_CH1OCLREN_POS 7U +#define TIMER_CHMR1_CH1OCLREN_MSK BIT(TIMER_CHMR1_CH1OCLREN_POS) + +#define TIMER_CHMR1_CH1OMOD_POSS 4U +#define TIMER_CHMR1_CH1OMOD_POSE 6U +#define TIMER_CHMR1_CH1OMOD_MSK BITS(TIMER_CHMR1_CH1OMOD_POSS,TIMER_CHMR1_CH1OMOD_POSE) + +#define TIMER_CHMR1_CH1OPREN_POS 3U +#define TIMER_CHMR1_CH1OPREN_MSK BIT(TIMER_CHMR1_CH1OPREN_POS) + +#define TIMER_CHMR1_CH1OHSEN_POS 2U +#define TIMER_CHMR1_CH1OHSEN_MSK BIT(TIMER_CHMR1_CH1OHSEN_POS) + +#define TIMER_CHMR1_CC1SSEL_POSS 0U +#define TIMER_CHMR1_CC1SSEL_POSE 1U +#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) + +/* Input */ +#define TIMER_CHMR1_I2FLT_POSS 12U +#define TIMER_CHMR1_I2FLT_POSE 15U +#define TIMER_CHMR1_I2FLT_MSK BITS(TIMER_CHMR1_I2FLT_POSS,TIMER_CHMR1_I2FLT_POSE) + +#define TIMER_CHMR1_IC2PRES_POSS 10U +#define TIMER_CHMR1_IC2PRES_POSE 11U +#define TIMER_CHMR1_IC2PRES_MSK BITS(TIMER_CHMR1_IC2PRES_POSS,TIMER_CHMR1_IC2PRES_POSE) + +#define TIMER_CHMR1_CC2SSEL_POSS 8U +#define TIMER_CHMR1_CC2SSEL_POSE 9U +#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) + +#define TIMER_CHMR1_I1FLT_POSS 4U +#define TIMER_CHMR1_I1FLT_POSE 7U +#define TIMER_CHMR1_I1FLT_MSK BITS(TIMER_CHMR1_I1FLT_POSS,TIMER_CHMR1_I1FLT_POSE) + +#define TIMER_CHMR1_IC1PRES_POSS 2U +#define TIMER_CHMR1_IC1PRES_POSE 3U +#define TIMER_CHMR1_IC1PRES_MSK BITS(TIMER_CHMR1_IC1PRES_POSS,TIMER_CHMR1_IC1PRES_POSE) + +#define TIMER_CHMR1_CC1SSEL_POSS 0U +#define TIMER_CHMR1_CC1SSEL_POSE 1U +#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) + +/****************** Bit definition for TIMER_CHMR2 register ************************/ +/* Output */ +#define TIMER_CHMR2_CH4OCLREN_POS 15U +#define TIMER_CHMR2_CH4OCLREN_MSK BIT(TIMER_CHMR2_CH4OCLREN_POS) + +#define TIMER_CHMR2_CH4OMOD_POSS 12U +#define TIMER_CHMR2_CH4OMOD_POSE 14U +#define TIMER_CHMR2_CH4OMOD_MSK BITS(TIMER_CHMR2_CH4OMOD_POSS,TIMER_CHMR2_CH4OMOD_POSE) + +#define TIMER_CHMR2_CH4OPEN_POS 11U +#define TIMER_CHMR2_CH4OPEN_MSK BIT(TIMER_CHMR2_CH4OPEN_POS) + +#define TIMER_CHMR2_CH4OHSEN_POS 10U +#define TIMER_CHMR2_CH4OHSEN_MSK BIT(TIMER_CHMR2_CH4OHSEN_POS) + +#define TIMER_CHMR2_CC4SSEL_POSS 8U +#define TIMER_CHMR2_CC4SSEL_POSE 9U +#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) + +#define TIMER_CHMR2_CH3OCLREN_POS 7U +#define TIMER_CHMR2_CH3OCLREN_MSK BIT(TIMER_CHMR2_CH3OCLREN_POS) + +#define TIMER_CHMR2_CH3OMOD_POSS 4U +#define TIMER_CHMR2_CH3OMOD_POSE 6U +#define TIMER_CHMR2_CH3OMOD_MSK BITS(TIMER_CHMR2_CH3OMOD_POSS,TIMER_CHMR2_CH3OMOD_POSE) + +#define TIMER_CHMR2_CH3OPEN_POS 3U +#define TIMER_CHMR2_CH3OPEN_MSK BIT(TIMER_CHMR2_CH3OPEN_POS) + +#define TIMER_CHMR2_CH3OFEN_POS 2U +#define TIMER_CHMR2_CH3OFEN_MSK BIT(TIMER_CHMR2_CH3OFEN_POS) + +#define TIMER_CHMR2_CC3SSEL_POSS 0U +#define TIMER_CHMR2_CC3SSEL_POSE 1U +#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) + +/* Input */ +#define TIMER_CHMR2_I4FLT_POSS 12U +#define TIMER_CHMR2_I4FLT_POSE 15U +#define TIMER_CHMR2_I4FLT_MSK BITS(TIMER_CHMR2_I4FLT_POSS,TIMER_CHMR2_I4FLT_POSE) + +#define TIMER_CHMR2_IC4PRES_POSS 10U +#define TIMER_CHMR2_IC4PRES_POSE 11U +#define TIMER_CHMR2_IC4PRES_MSK BITS(TIMER_CHMR2_IC4PRES_POSS,TIMER_CHMR2_IC4PRES_POSE) + +#define TIMER_CHMR2_CC4SSEL_POSS 8U +#define TIMER_CHMR2_CC4SSEL_POSE 9U +#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) + +#define TIMER_CHMR2_I3FLT_POSS 4U +#define TIMER_CHMR2_I3FLT_POSE 7U +#define TIMER_CHMR2_I3FLT_MSK BITS(TIMER_CHMR2_I3FLT_POSS,TIMER_CHMR2_I3FLT_POSE) + +#define TIMER_CHMR2_IC3PRES_POSS 2U +#define TIMER_CHMR2_IC3PRES_POSE 3U +#define TIMER_CHMR2_IC3PRES_MSK BITS(TIMER_CHMR2_IC3PRES_POSS,TIMER_CHMR2_IC3PRES_POSE) + +#define TIMER_CHMR2_CC3SSEL_POSS 0U +#define TIMER_CHMR2_CC3SSEL_POSE 1U +#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) + +/****************** Bit definition for TIMER_CCEP register ************************/ + +#define TIMER_CCEP_CC4POL_POS 13U +#define TIMER_CCEP_CC4POL_MSK BIT(TIMER_CCEP_CC4POL_POS) + +#define TIMER_CCEP_CC4EN_POS 12U +#define TIMER_CCEP_CC4EN_MSK BIT(TIMER_CCEP_CC4EN_POS) + +#define TIMER_CCEP_CC3NPOL_POS 11U +#define TIMER_CCEP_CC3NPOL_MSK BIT(TIMER_CCEP_CC3NPOL_POS) + +#define TIMER_CCEP_CC3NEN_POS 10U +#define TIMER_CCEP_CC3NEN_MSK BIT(TIMER_CCEP_CC3NEN_POS) + +#define TIMER_CCEP_CC3POL_POS 9U +#define TIMER_CCEP_CC3POL_MSK BIT(TIMER_CCEP_CC3POL_POS) + +#define TIMER_CCEP_CC3EN_POS 8U +#define TIMER_CCEP_CC3EN_MSK BIT(TIMER_CCEP_CC3EN_POS) + +#define TIMER_CCEP_CC2NPOL_POS 7U +#define TIMER_CCEP_CC2NPOL_MSK BIT(TIMER_CCEP_CC2NPOL_POS) + +#define TIMER_CCEP_CC2NEN_POS 6U +#define TIMER_CCEP_CC2NEN_MSK BIT(TIMER_CCEP_CC2NEN_POS) + +#define TIMER_CCEP_CC2POL_POS 5U +#define TIMER_CCEP_CC2POL_MSK BIT(TIMER_CCEP_CC2POL_POS) + +#define TIMER_CCEP_CC2EN_POS 4U +#define TIMER_CCEP_CC2EN_MSK BIT(TIMER_CCEP_CC2EN_POS) + +#define TIMER_CCEP_CC1NPOL_POS 3U +#define TIMER_CCEP_CC1NPOL_MSK BIT(TIMER_CCEP_CC1NPOL_POS) + +#define TIMER_CCEP_CC1NEN_POS 2U +#define TIMER_CCEP_CC1NEN_MSK BIT(TIMER_CCEP_CC1NEN_POS) + +#define TIMER_CCEP_CC1POL_POS 1U +#define TIMER_CCEP_CC1POL_MSK BIT(TIMER_CCEP_CC1POL_POS) + +#define TIMER_CCEP_CC1EN_POS 0U +#define TIMER_CCEP_CC1EN_MSK BIT(TIMER_CCEP_CC1EN_POS) + +/****************** Bit definition for TIMER_COUNT register ************************/ + +#define TIMER_COUNT_CNTV_POSS 0U +#define TIMER_COUNT_CNTV_POSE 15U +#define TIMER_COUNT_CNTV_MSK BITS(TIMER_COUNT_CNTV_POSS,TIMER_COUNT_CNTV_POSE) + +/****************** Bit definition for TIMER_PRES register ************************/ + +#define TIMER_PRES_PSCV_POSS 0U +#define TIMER_PRES_PSCV_POSE 15U +#define TIMER_PRES_PSCV_MSK BITS(TIMER_PRES_PSCV_POSS,TIMER_PRES_PSCV_POSE) + +/****************** Bit definition for TIMER_AR register ************************/ + +#define TIMER_AR_ARRV_POSS 0U +#define TIMER_AR_ARRV_POSE 15U +#define TIMER_AR_ARRV_MSK BITS(TIMER_AR_ARRV_POSS,TIMER_AR_ARRV_POSE) + +/****************** Bit definition for TIMER_REPAR register ************************/ + +#define TIMER_REPAR_REPV_POSS 0U +#define TIMER_REPAR_REPV_POSE 7U +#define TIMER_REPAR_REPV_MSK BITS(TIMER_REPAR_REPV_POSS,TIMER_REPAR_REPV_POSE) + +/****************** Bit definition for TIMER_CCVAL1 register ************************/ + +#define TIMER_CCVAL1_CCRV1_POSS 0U +#define TIMER_CCVAL1_CCRV1_POSE 15U +#define TIMER_CCVAL1_CCRV1_MSK BITS(TIMER_CCVAL1_CCRV1_POSS,TIMER_CCVAL1_CCRV1_POSE) + +/****************** Bit definition for TIMER_CCVAL2 register ************************/ + +#define TIMER_CCVAL2_CCRV2_POSS 0U +#define TIMER_CCVAL2_CCRV2_POSE 15U +#define TIMER_CCVAL2_CCRV2_MSK BITS(TIMER_CCVAL2_CCRV2_POSS,TIMER_CCVAL2_CCRV2_POSE) + +/****************** Bit definition for TIMER_CCVAL3 register ************************/ + +#define TIMER_CCVAL3_CCRV3_POSS 0U +#define TIMER_CCVAL3_CCRV3_POSE 15U +#define TIMER_CCVAL3_CCRV3_MSK BITS(TIMER_CCVAL3_CCRV3_POSS,TIMER_CCVAL3_CCRV3_POSE) + +/****************** Bit definition for TIMER_CCVAL4 register ************************/ + +#define TIMER_CCVAL4_CCRV4_POSS 0U +#define TIMER_CCVAL4_CCRV4_POSE 15U +#define TIMER_CCVAL4_CCRV4_MSK BITS(TIMER_CCVAL4_CCRV4_POSS,TIMER_CCVAL4_CCRV4_POSE) + +/****************** Bit definition for TIMER_BDCFG register ************************/ + +#define TIMER_BDCFG_GOEN_POS 15U +#define TIMER_BDCFG_GOEN_MSK BIT(TIMER_BDCFG_GOEN_POS) + +#define TIMER_BDCFG_AOEN_POS 14U +#define TIMER_BDCFG_AOEN_MSK BIT(TIMER_BDCFG_AOEN_POS) + +#define TIMER_BDCFG_BRKP_POS 13U +#define TIMER_BDCFG_BRKP_MSK BIT(TIMER_BDCFG_BRKP_POS) + +#define TIMER_BDCFG_BRKEN_POS 12U +#define TIMER_BDCFG_BRKEN_MSK BIT(TIMER_BDCFG_BRKEN_POS) + +#define TIMER_BDCFG_OFFSSR_POS 11U +#define TIMER_BDCFG_OFFSSR_MSK BIT(TIMER_BDCFG_OFFSSR_POS) + +#define TIMER_BDCFG_OFFSSI_POS 10U +#define TIMER_BDCFG_OFFSSI_MSK BIT(TIMER_BDCFG_OFFSSI_POS) + +#define TIMER_BDCFG_LOCKLVL_POSS 8U +#define TIMER_BDCFG_LOCKLVL_POSE 9U +#define TIMER_BDCFG_LOCKLVL_MSK BITS(TIMER_BDCFG_LOCKLVL_POSS,TIMER_BDCFG_LOCKLVL_POSE) + +#define TIMER_BDCFG_DT_POSS 0U +#define TIMER_BDCFG_DT_POSE 7U +#define TIMER_BDCFG_DT_MSK BITS(TIMER_BDCFG_DT_POSS,TIMER_BDCFG_DT_POSE) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t SMCON; + __O uint32_t DIER; + __O uint32_t DIDR; + __I uint32_t DIVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + __O uint32_t SGE; + __IO uint32_t CHMR1; + __IO uint32_t CHMR2; + __IO uint32_t CCEP; + __IO uint32_t COUNT; + __IO uint32_t PRES; + __IO uint32_t AR; + __IO uint32_t REPAR; + __IO uint32_t CCVAL1; + __IO uint32_t CCVAL2; + __IO uint32_t CCVAL3; + __IO uint32_t CCVAL4; + __IO uint32_t BDCFG; +} TIMER_TypeDef; + +/****************** Bit definition for USART_STAT register ************************/ + +#define USART_STAT_CTSIF_POS 9U +#define USART_STAT_CTSIF_MSK BIT(USART_STAT_CTSIF_POS) + +#define USART_STAT_TXEMPIF_POS 7U +#define USART_STAT_TXEMPIF_MSK BIT(USART_STAT_TXEMPIF_POS) + +#define USART_STAT_TXCIF_POS 6U +#define USART_STAT_TXCIF_MSK BIT(USART_STAT_TXCIF_POS) + +#define USART_STAT_RXNEIF_POS 5U +#define USART_STAT_RXNEIF_MSK BIT(USART_STAT_RXNEIF_POS) + +#define USART_STAT_IDLEIF_POS 4U +#define USART_STAT_IDLEIF_MSK BIT(USART_STAT_IDLEIF_POS) + +#define USART_STAT_OVRIF_POS 3U +#define USART_STAT_OVRIF_MSK BIT(USART_STAT_OVRIF_POS) + +#define USART_STAT_NDETIF_POS 2U +#define USART_STAT_NDETIF_MSK BIT(USART_STAT_NDETIF_POS) + +#define USART_STAT_FERRIF_POS 1U +#define USART_STAT_FERRIF_MSK BIT(USART_STAT_FERRIF_POS) + +#define USART_STAT_PERRIF_POS 0U +#define USART_STAT_PERRIF_MSK BIT(USART_STAT_PERRIF_POS) + +/****************** Bit definition for USART_DATA register ************************/ + +#define USART_DATA_VAL_POSS 0U +#define USART_DATA_VAL_POSE 8U +#define USART_DATA_VAL_MSK BITS(USART_DATA_VAL_POSS,USART_DATA_VAL_POSE) + +/****************** Bit definition for USART_BAUDCON register ************************/ + +#define USART_BAUDCON_DIV_M_POSS 4U +#define USART_BAUDCON_DIV_M_POSE 15U +#define USART_BAUDCON_DIV_M_MSK BITS(USART_BAUDCON_DIV_M_POSS,USART_BAUDCON_DIV_M_POSE) + +#define USART_BAUDCON_DIV_F_POSS 0U +#define USART_BAUDCON_DIV_F_POSE 3U +#define USART_BAUDCON_DIV_F_MSK BITS(USART_BAUDCON_DIV_F_POSS,USART_BAUDCON_DIV_F_POSE) + +/****************** Bit definition for USART_CON0 register ************************/ + +#define USART_CON0_EN_POS 13U +#define USART_CON0_EN_MSK BIT(USART_CON0_EN_POS) + +#define USART_CON0_DLEN_POS 12U +#define USART_CON0_DLEN_MSK BIT(USART_CON0_DLEN_POS) + +#define USART_CON0_WKMOD_POS 11U +#define USART_CON0_WKMOD_MSK BIT(USART_CON0_WKMOD_POS) + +#define USART_CON0_PEN_POS 10U +#define USART_CON0_PEN_MSK BIT(USART_CON0_PEN_POS) + +#define USART_CON0_PSEL_POS 9U +#define USART_CON0_PSEL_MSK BIT(USART_CON0_PSEL_POS) + +#define USART_CON0_PERRIE_POS 8U +#define USART_CON0_PERRIE_MSK BIT(USART_CON0_PERRIE_POS) + +#define USART_CON0_TXEMPIE_POS 7U +#define USART_CON0_TXEMPIE_MSK BIT(USART_CON0_TXEMPIE_POS) + +#define USART_CON0_TXCIE_POS 6U +#define USART_CON0_TXCIE_MSK BIT(USART_CON0_TXCIE_POS) + +#define USART_CON0_RXNEIE_POS 5U +#define USART_CON0_RXNEIE_MSK BIT(USART_CON0_RXNEIE_POS) + +#define USART_CON0_IDLEIE_POS 4U +#define USART_CON0_IDLEIE_MSK BIT(USART_CON0_IDLEIE_POS) + +#define USART_CON0_TXEN_POS 3U +#define USART_CON0_TXEN_MSK BIT(USART_CON0_TXEN_POS) + +#define USART_CON0_RXEN_POS 2U +#define USART_CON0_RXEN_MSK BIT(USART_CON0_RXEN_POS) + +#define USART_CON0_RXWK_POS 1U +#define USART_CON0_RXWK_MSK BIT(USART_CON0_RXWK_POS) + +/****************** Bit definition for USART_CON1 register ************************/ + +#define USART_CON1_STPLEN_POSS 12U +#define USART_CON1_STPLEN_POSE 13U +#define USART_CON1_STPLEN_MSK BITS(USART_CON1_STPLEN_POSS,USART_CON1_STPLEN_POSE) + +#define USART_CON1_SCKEN_POS 11U +#define USART_CON1_SCKEN_MSK BIT(USART_CON1_SCKEN_POS) + +#define USART_CON1_SCKPOL_POS 10U +#define USART_CON1_SCKPOL_MSK BIT(USART_CON1_SCKPOL_POS) + +#define USART_CON1_SCKPHA_POS 9U +#define USART_CON1_SCKPHA_MSK BIT(USART_CON1_SCKPHA_POS) + +#define USART_CON1_LBCP_POS 8U +#define USART_CON1_LBCP_MSK BIT(USART_CON1_LBCP_POS) + +#define USART_CON1_ADDR_POSS 0U +#define USART_CON1_ADDR_POSE 3U +#define USART_CON1_ADDR_MSK BITS(USART_CON1_ADDR_POSS,USART_CON1_ADDR_POSE) + +/****************** Bit definition for USART_CON2 register ************************/ + +#define USART_CON2_CTSIE_POS 10U +#define USART_CON2_CTSIE_MSK BIT(USART_CON2_CTSIE_POS) + +#define USART_CON2_CTSEN_POS 9U +#define USART_CON2_CTSEN_MSK BIT(USART_CON2_CTSEN_POS) + +#define USART_CON2_RTSEN_POS 8U +#define USART_CON2_RTSEN_MSK BIT(USART_CON2_RTSEN_POS) + +#define USART_CON2_TXDMAEN_POS 7U +#define USART_CON2_TXDMAEN_MSK BIT(USART_CON2_TXDMAEN_POS) + +#define USART_CON2_RXDMAEN_POS 6U +#define USART_CON2_RXDMAEN_MSK BIT(USART_CON2_RXDMAEN_POS) + +#define USART_CON2_SMARTEN_POS 5U +#define USART_CON2_SMARTEN_MSK BIT(USART_CON2_SMARTEN_POS) + +#define USART_CON2_NACK_POS 4U +#define USART_CON2_NACK_MSK BIT(USART_CON2_NACK_POS) + +#define USART_CON2_HDPSEL_POS 3U +#define USART_CON2_HDPSEL_MSK BIT(USART_CON2_HDPSEL_POS) + +#define USART_CON2_IREN_POS 1U +#define USART_CON2_IREN_MSK BIT(USART_CON2_IREN_POS) + +#define USART_CON2_ERRIE_POS 0U +#define USART_CON2_ERRIE_MSK BIT(USART_CON2_ERRIE_POS) + +/****************** Bit definition for USART_GP register ************************/ + +#define USART_GP_GTVAL_POSS 8U +#define USART_GP_GTVAL_POSE 15U +#define USART_GP_GTVAL_MSK BITS(USART_GP_GTVAL_POSS,USART_GP_GTVAL_POSE) + +#define USART_GP_PSC_POSS 0U +#define USART_GP_PSC_POSE 7U +#define USART_GP_PSC_MSK BITS(USART_GP_PSC_POSS,USART_GP_PSC_POSE) + +typedef struct +{ + __IO uint32_t STAT; + __IO uint32_t DATA; + __IO uint32_t BAUDCON; + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t GP; +} USART_TypeDef; + +/****************** Bit definition for UART_RBR register ************************/ + +#define UART_RBR_RBR_POSS 0U +#define UART_RBR_RBR_POSE 8U +#define UART_RBR_RBR_MSK BITS(UART_RBR_RBR_POSS,UART_RBR_RBR_POSE) + +/****************** Bit definition for UART_TBR register ************************/ + +#define UART_TBR_TBR_POSS 0U +#define UART_TBR_TBR_POSE 8U +#define UART_TBR_TBR_MSK BITS(UART_TBR_TBR_POSS,UART_TBR_TBR_POSE) + +/****************** Bit definition for UART_BRR register ************************/ + +#define UART_BRR_BRR_POSS 0U +#define UART_BRR_BRR_POSE 15U +#define UART_BRR_BRR_MSK BITS(UART_BRR_BRR_POSS,UART_BRR_BRR_POSE) + +/****************** Bit definition for UART_LCR register ************************/ + +#define UART_LCR_SWAP_POS 13U +#define UART_LCR_SWAP_MSK BIT(UART_LCR_SWAP_POS) + +#define UART_LCR_TXINV_POS 12U +#define UART_LCR_TXINV_MSK BIT(UART_LCR_TXINV_POS) + +#define UART_LCR_RXINV_POS 11U +#define UART_LCR_RXINV_MSK BIT(UART_LCR_RXINV_POS) + +#define UART_LCR_DATAINV_POS 10U +#define UART_LCR_DATAINV_MSK BIT(UART_LCR_DATAINV_POS) + +#define UART_LCR_MSBFIRST_POS 9U +#define UART_LCR_MSBFIRST_MSK BIT(UART_LCR_MSBFIRST_POS) + +#define UART_LCR_RTOEN_POS 8U +#define UART_LCR_RTOEN_MSK BIT(UART_LCR_RTOEN_POS) + +#define UART_LCR_BRWEN_POS 7U +#define UART_LCR_BRWEN_MSK BIT(UART_LCR_BRWEN_POS) + +#define UART_LCR_BC_POS 6U +#define UART_LCR_BC_MSK BIT(UART_LCR_BC_POS) + +#define UART_LCR_RXEN_POS 5U +#define UART_LCR_RXEN_MSK BIT(UART_LCR_RXEN_POS) + +#define UART_LCR_PS_POS 4U +#define UART_LCR_PS_MSK BIT(UART_LCR_PS_POS) + +#define UART_LCR_PEN_POS 3U +#define UART_LCR_PEN_MSK BIT(UART_LCR_PEN_POS) + +#define UART_LCR_STOP_POS 2U +#define UART_LCR_STOP_MSK BIT(UART_LCR_STOP_POS) + +#define UART_LCR_DLS_POSS 0U +#define UART_LCR_DLS_POSE 1U +#define UART_LCR_DLS_MSK BITS(UART_LCR_DLS_POSS,UART_LCR_DLS_POSE) + +/****************** Bit definition for UART_MCR register ************************/ + +#define UART_MCR_HDSEL_POS 22U +#define UART_MCR_HDSEL_MSK BIT(UART_MCR_HDSEL_POS) + +#define UART_MCR_ABRRS_POS 15U +#define UART_MCR_ABRRS_MSK BIT(UART_MCR_ABRRS_POS) + +#define UART_MCR_ABRMOD_POSS 13U +#define UART_MCR_ABRMOD_POSE 14U +#define UART_MCR_ABRMOD_MSK BITS(UART_MCR_ABRMOD_POSS,UART_MCR_ABRMOD_POSE) + +#define UART_MCR_ABREN_POS 12U +#define UART_MCR_ABREN_MSK BIT(UART_MCR_ABREN_POS) + +#define UART_MCR_DMAEN_POS 11U +#define UART_MCR_DMAEN_MSK BIT(UART_MCR_DMAEN_POS) + +#define UART_MCR_LINBDL_POS 10U +#define UART_MCR_LINBDL_MSK BIT(UART_MCR_LINBDL_POS) + +#define UART_MCR_BKREQ_POS 9U +#define UART_MCR_BKREQ_MSK BIT(UART_MCR_BKREQ_POS) + +#define UART_MCR_LINEN_POS 8U +#define UART_MCR_LINEN_MSK BIT(UART_MCR_LINEN_POS) + +#define UART_MCR_AADINV_POS 7U +#define UART_MCR_AADINV_MSK BIT(UART_MCR_AADINV_POS) + +#define UART_MCR_AADDIR_POS 6U +#define UART_MCR_AADDIR_MSK BIT(UART_MCR_AADDIR_POS) + +#define UART_MCR_AADNOR_POS 5U +#define UART_MCR_AADNOR_MSK BIT(UART_MCR_AADNOR_POS) + +#define UART_MCR_AADEN_POS 4U +#define UART_MCR_AADEN_MSK BIT(UART_MCR_AADEN_POS) + +#define UART_MCR_RTSCTRL_POS 3U +#define UART_MCR_RTSCTRL_MSK BIT(UART_MCR_RTSCTRL_POS) + +#define UART_MCR_AFCEN_POS 2U +#define UART_MCR_AFCEN_MSK BIT(UART_MCR_AFCEN_POS) + +#define UART_MCR_LBEN_POS 1U +#define UART_MCR_LBEN_MSK BIT(UART_MCR_LBEN_POS) + +#define UART_MCR_IREN_POS 0U +#define UART_MCR_IREN_MSK BIT(UART_MCR_IREN_POS) + +/****************** Bit definition for UART_CR register ************************/ + +#define UART_CR_PSC_POSS 16U +#define UART_CR_PSC_POSE 23U +#define UART_CR_PSC_MSK BITS(UART_CR_PSC_POSS,UART_CR_PSC_POSE) + +#define UART_CR_DLY_POSS 8U +#define UART_CR_DLY_POSE 15U +#define UART_CR_DLY_MSK BITS(UART_CR_DLY_POSS,UART_CR_DLY_POSE) + +#define UART_CR_ADDR_POSS 0U +#define UART_CR_ADDR_POSE 7U +#define UART_CR_ADDR_MSK BITS(UART_CR_ADDR_POSS,UART_CR_ADDR_POSE) + +/****************** Bit definition for UART_RTOR register ************************/ + +#define UART_RTOR_BLEN_POSS 24U +#define UART_RTOR_BLEN_POSE 31U +#define UART_RTOR_BLEN_MSK BITS(UART_RTOR_BLEN_POSS,UART_RTOR_BLEN_POSE) + +#define UART_RTOR_RTO_POSS 0U +#define UART_RTOR_RTO_POSE 23U +#define UART_RTOR_RTO_MSK BITS(UART_RTOR_RTO_POSS,UART_RTOR_RTO_POSE) + +/****************** Bit definition for UART_FCR register ************************/ + +#define UART_FCR_TXFL_POSS 12U +#define UART_FCR_TXFL_POSE 15U +#define UART_FCR_TXFL_MSK BITS(UART_FCR_TXFL_POSS,UART_FCR_TXFL_POSE) + +#define UART_FCR_RXFL_POSS 8U +#define UART_FCR_RXFL_POSE 11U +#define UART_FCR_RXFL_MSK BITS(UART_FCR_RXFL_POSS,UART_FCR_RXFL_POSE) + +#define UART_FCR_TXTL_POSS 6U +#define UART_FCR_TXTL_POSE 7U +#define UART_FCR_TXTL_MSK BITS(UART_FCR_TXTL_POSS,UART_FCR_TXTL_POSE) + +#define UART_FCR_RXTL_POSS 4U +#define UART_FCR_RXTL_POSE 5U +#define UART_FCR_RXTL_MSK BITS(UART_FCR_RXTL_POSS,UART_FCR_RXTL_POSE) + +#define UART_FCR_TFRST_POS 2U +#define UART_FCR_TFRST_MSK BIT(UART_FCR_TFRST_POS) + +#define UART_FCR_RFRST_POS 1U +#define UART_FCR_RFRST_MSK BIT(UART_FCR_RFRST_POS) + +#define UART_FCR_FIFOEN_POS 0U +#define UART_FCR_FIFOEN_MSK BIT(UART_FCR_FIFOEN_POS) + +/****************** Bit definition for UART_SR register ************************/ + +#define UART_SR_CTS_POS 14U +#define UART_SR_CTS_MSK BIT(UART_SR_CTS_POS) + +#define UART_SR_DCTS_POS 13U +#define UART_SR_DCTS_MSK BIT(UART_SR_DCTS_POS) + +#define UART_SR_RFF_POS 12U +#define UART_SR_RFF_MSK BIT(UART_SR_RFF_POS) + +#define UART_SR_RFNE_POS 11U +#define UART_SR_RFNE_MSK BIT(UART_SR_RFNE_POS) + +#define UART_SR_TFEM_POS 10U +#define UART_SR_TFEM_MSK BIT(UART_SR_TFEM_POS) + +#define UART_SR_TFNF_POS 9U +#define UART_SR_TFNF_MSK BIT(UART_SR_TFNF_POS) + +#define UART_SR_BUSY_POS 8U +#define UART_SR_BUSY_MSK BIT(UART_SR_BUSY_POS) + +#define UART_SR_RFE_POS 7U +#define UART_SR_RFE_MSK BIT(UART_SR_RFE_POS) + +#define UART_SR_TEM_POS 6U +#define UART_SR_TEM_MSK BIT(UART_SR_TEM_POS) + +#define UART_SR_TBEM_POS 5U +#define UART_SR_TBEM_MSK BIT(UART_SR_TBEM_POS) + +#define UART_SR_BF_POS 4U +#define UART_SR_BF_MSK BIT(UART_SR_BF_POS) + +#define UART_SR_FE_POS 3U +#define UART_SR_FE_MSK BIT(UART_SR_FE_POS) + +#define UART_SR_PE_POS 2U +#define UART_SR_PE_MSK BIT(UART_SR_PE_POS) + +#define UART_SR_OE_POS 1U +#define UART_SR_OE_MSK BIT(UART_SR_OE_POS) + +#define UART_SR_DR_POS 0U +#define UART_SR_DR_MSK BIT(UART_SR_DR_POS) + +/****************** Bit definition for UART_IER register ************************/ + +#define UART_IER_CMIE_POS 11U +#define UART_IER_CMIE_MSK BIT(UART_IER_CMIE_POS) + +#define UART_IER_EOBIE_POS 10U +#define UART_IER_EOBIE_MSK BIT(UART_IER_EOBIE_POS) + +#define UART_IER_TCIE_POS 9U +#define UART_IER_TCIE_MSK BIT(UART_IER_TCIE_POS) + +#define UART_IER_LINBKIE_POS 8U +#define UART_IER_LINBKIE_MSK BIT(UART_IER_LINBKIE_POS) + +#define UART_IER_ABTOIE_POS 7U +#define UART_IER_ABTOIE_MSK BIT(UART_IER_ABTOIE_POS) + +#define UART_IER_ABEIE_POS 6U +#define UART_IER_ABEIE_MSK BIT(UART_IER_ABEIE_POS) + +#define UART_IER_BZIE_POS 5U +#define UART_IER_BZIE_MSK BIT(UART_IER_BZIE_POS) + +#define UART_IER_RTOIE_POS 4U +#define UART_IER_RTOIE_MSK BIT(UART_IER_RTOIE_POS) + +#define UART_IER_MDSIE_POS 3U +#define UART_IER_MDSIE_MSK BIT(UART_IER_MDSIE_POS) + +#define UART_IER_RXSIE_POS 2U +#define UART_IER_RXSIE_MSK BIT(UART_IER_RXSIE_POS) + +#define UART_IER_TXSIE_POS 1U +#define UART_IER_TXSIE_MSK BIT(UART_IER_TXSIE_POS) + +#define UART_IER_RXRDIE_POS 0U +#define UART_IER_RXRDIE_MSK BIT(UART_IER_RXRDIE_POS) + +/****************** Bit definition for UART_IDR register ************************/ + +#define UART_IDR_CMID_POS 11U +#define UART_IDR_CMID_MSK BIT(UART_IDR_CMID_POS) + +#define UART_IDR_EOBID_POS 10U +#define UART_IDR_EOBID_MSK BIT(UART_IDR_EOBID_POS) + +#define UART_IDR_TCID_POS 9U +#define UART_IDR_TCID_MSK BIT(UART_IDR_TCID_POS) + +#define UART_IDR_LINBKID_POS 8U +#define UART_IDR_LINBKID_MSK BIT(UART_IDR_LINBKID_POS) + +#define UART_IDR_ABTOID_POS 7U +#define UART_IDR_ABTOID_MSK BIT(UART_IDR_ABTOID_POS) + +#define UART_IDR_ABEID_POS 6U +#define UART_IDR_ABEID_MSK BIT(UART_IDR_ABEID_POS) + +#define UART_IDR_BZID_POS 5U +#define UART_IDR_BZID_MSK BIT(UART_IDR_BZID_POS) + +#define UART_IDR_RTOID_POS 4U +#define UART_IDR_RTOID_MSK BIT(UART_IDR_RTOID_POS) + +#define UART_IDR_MDSID_POS 3U +#define UART_IDR_MDSID_MSK BIT(UART_IDR_MDSID_POS) + +#define UART_IDR_RXSID_POS 2U +#define UART_IDR_RXSID_MSK BIT(UART_IDR_RXSID_POS) + +#define UART_IDR_TXSID_POS 1U +#define UART_IDR_TXSID_MSK BIT(UART_IDR_TXSID_POS) + +#define UART_IDR_RXRDID_POS 0U +#define UART_IDR_RXRDID_MSK BIT(UART_IDR_RXRDID_POS) + +/****************** Bit definition for UART_IVS register ************************/ + +#define UART_IVS_CMIS_POS 11U +#define UART_IVS_CMIS_MSK BIT(UART_IVS_CMIS_POS) + +#define UART_IVS_EOBIS_POS 10U +#define UART_IVS_EOBIS_MSK BIT(UART_IVS_EOBIS_POS) + +#define UART_IVS_TCIS_POS 9U +#define UART_IVS_TCIS_MSK BIT(UART_IVS_TCIS_POS) + +#define UART_IVS_LINBKIS_POS 8U +#define UART_IVS_LINBKIS_MSK BIT(UART_IVS_LINBKIS_POS) + +#define UART_IVS_ABTOIS_POS 7U +#define UART_IVS_ABTOIS_MSK BIT(UART_IVS_ABTOIS_POS) + +#define UART_IVS_ABEIS_POS 6U +#define UART_IVS_ABEIS_MSK BIT(UART_IVS_ABEIS_POS) + +#define UART_IVS_BZIS_POS 5U +#define UART_IVS_BZIS_MSK BIT(UART_IVS_BZIS_POS) + +#define UART_IVS_RTOIS_POS 4U +#define UART_IVS_RTOIS_MSK BIT(UART_IVS_RTOIS_POS) + +#define UART_IVS_MDSIS_POS 3U +#define UART_IVS_MDSIS_MSK BIT(UART_IVS_MDSIS_POS) + +#define UART_IVS_RXSIS_POS 2U +#define UART_IVS_RXSIS_MSK BIT(UART_IVS_RXSIS_POS) + +#define UART_IVS_TXSIS_POS 1U +#define UART_IVS_TXSIS_MSK BIT(UART_IVS_TXSIS_POS) + +#define UART_IVS_RXRDIS_POS 0U +#define UART_IVS_RXRDIS_MSK BIT(UART_IVS_RXRDIS_POS) + +/****************** Bit definition for UART_RIF register ************************/ + +#define UART_RIF_CMIF_POS 11U +#define UART_RIF_CMIF_MSK BIT(UART_RIF_CMIF_POS) + +#define UART_RIF_EOBIF_POS 10U +#define UART_RIF_EOBIF_MSK BIT(UART_RIF_EOBIF_POS) + +#define UART_RIF_TCIF_POS 9U +#define UART_RIF_TCIF_MSK BIT(UART_RIF_TCIF_POS) + +#define UART_RIF_LINBKIF_POS 8U +#define UART_RIF_LINBKIF_MSK BIT(UART_RIF_LINBKIF_POS) + +#define UART_RIF_ABTOIF_POS 7U +#define UART_RIF_ABTOIF_MSK BIT(UART_RIF_ABTOIF_POS) + +#define UART_RIF_ABEIF_POS 6U +#define UART_RIF_ABEIF_MSK BIT(UART_RIF_ABEIF_POS) + +#define UART_RIF_BZIF_POS 5U +#define UART_RIF_BZIF_MSK BIT(UART_RIF_BZIF_POS) + +#define UART_RIF_RTOIF_POS 4U +#define UART_RIF_RTOIF_MSK BIT(UART_RIF_RTOIF_POS) + +#define UART_RIF_MDSIF_POS 3U +#define UART_RIF_MDSIF_MSK BIT(UART_RIF_MDSIF_POS) + +#define UART_RIF_RXSIF_POS 2U +#define UART_RIF_RXSIF_MSK BIT(UART_RIF_RXSIF_POS) + +#define UART_RIF_TXSIF_POS 1U +#define UART_RIF_TXSIF_MSK BIT(UART_RIF_TXSIF_POS) + +#define UART_RIF_RXRDIF_POS 0U +#define UART_RIF_RXRDIF_MSK BIT(UART_RIF_RXRDIF_POS) + +/****************** Bit definition for UART_IFM register ************************/ + +#define UART_IFM_CMIM_POS 11U +#define UART_IFM_CMIM_MSK BIT(UART_IFM_CMIM_POS) + +#define UART_IFM_EOBIM_POS 10U +#define UART_IFM_EOBIM_MSK BIT(UART_IFM_EOBIM_POS) + +#define UART_IFM_TCIM_POS 9U +#define UART_IFM_TCIM_MSK BIT(UART_IFM_TCIM_POS) + +#define UART_IFM_LINBKIM_POS 8U +#define UART_IFM_LINBKIM_MSK BIT(UART_IFM_LINBKIM_POS) + +#define UART_IFM_ABTOIM_POS 7U +#define UART_IFM_ABTOIM_MSK BIT(UART_IFM_ABTOIM_POS) + +#define UART_IFM_ABEIM_POS 6U +#define UART_IFM_ABEIM_MSK BIT(UART_IFM_ABEIM_POS) + +#define UART_IFM_BZIM_POS 5U +#define UART_IFM_BZIM_MSK BIT(UART_IFM_BZIM_POS) + +#define UART_IFM_RTOIM_POS 4U +#define UART_IFM_RTOIM_MSK BIT(UART_IFM_RTOIM_POS) + +#define UART_IFM_MDSIM_POS 3U +#define UART_IFM_MDSIM_MSK BIT(UART_IFM_MDSIM_POS) + +#define UART_IFM_RXSIM_POS 2U +#define UART_IFM_RXSIM_MSK BIT(UART_IFM_RXSIM_POS) + +#define UART_IFM_TXSIM_POS 1U +#define UART_IFM_TXSIM_MSK BIT(UART_IFM_TXSIM_POS) + +#define UART_IFM_RXRDIM_POS 0U +#define UART_IFM_RXRDIM_MSK BIT(UART_IFM_RXRDIM_POS) + +/****************** Bit definition for UART_ICR register ************************/ + +#define UART_ICR_CMIC_POS 11U +#define UART_ICR_CMIC_MSK BIT(UART_ICR_CMIC_POS) + +#define UART_ICR_EOBIC_POS 10U +#define UART_ICR_EOBIC_MSK BIT(UART_ICR_EOBIC_POS) + +#define UART_ICR_TCIC_POS 9U +#define UART_ICR_TCIC_MSK BIT(UART_ICR_TCIC_POS) + +#define UART_ICR_LINBKIC_POS 8U +#define UART_ICR_LINBKIC_MSK BIT(UART_ICR_LINBKIC_POS) + +#define UART_ICR_ABTOIC_POS 7U +#define UART_ICR_ABTOIC_MSK BIT(UART_ICR_ABTOIC_POS) + +#define UART_ICR_ABEIC_POS 6U +#define UART_ICR_ABEIC_MSK BIT(UART_ICR_ABEIC_POS) + +#define UART_ICR_BZIC_POS 5U +#define UART_ICR_BZIC_MSK BIT(UART_ICR_BZIC_POS) + +#define UART_ICR_CHTOIC_POS 4U +#define UART_ICR_CHTOIC_MSK BIT(UART_ICR_CHTOIC_POS) + +#define UART_ICR_MDSIC_POS 3U +#define UART_ICR_MDSIC_MSK BIT(UART_ICR_MDSIC_POS) + +#define UART_ICR_RXSIC_POS 2U +#define UART_ICR_RXSIC_MSK BIT(UART_ICR_RXSIC_POS) + +#define UART_ICR_TXSIC_POS 1U +#define UART_ICR_TXSIC_MSK BIT(UART_ICR_TXSIC_POS) + +#define UART_ICR_RXRDIC_POS 0U +#define UART_ICR_RXRDIC_MSK BIT(UART_ICR_RXRDIC_POS) + +typedef struct +{ + __I uint32_t RBR; + __IO uint32_t TBR; + __IO uint32_t BRR; + __IO uint32_t LCR; + __IO uint32_t MCR; + __IO uint32_t CR; + __IO uint32_t RTOR; + __IO uint32_t FCR; + __I uint32_t SR; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} UART_TypeDef; + +/****************** Bit definition for LPUART_CON0 register ************************/ + +#define LPUART_CON0_MODESEL_POSS 30U +#define LPUART_CON0_MODESEL_POSE 31U +#define LPUART_CON0_MODESEL_MSK BITS(LPUART_CON0_MODESEL_POSS,LPUART_CON0_MODESEL_POSE) + +#define LPUART_CON0_TXDMAE_POS 29U +#define LPUART_CON0_TXDMAE_MSK BIT(LPUART_CON0_TXDMAE_POS) + +#define LPUART_CON0_RXDMAE_POS 28U +#define LPUART_CON0_RXDMAE_MSK BIT(LPUART_CON0_RXDMAE_POS) + +#define LPUART_CON0_INTERVAL_POSS 16U +#define LPUART_CON0_INTERVAL_POSE 23U +#define LPUART_CON0_INTERVAL_MSK BITS(LPUART_CON0_INTERVAL_POSS,LPUART_CON0_INTERVAL_POSE) + +#define LPUART_CON0_SYNCBP_POS 15U +#define LPUART_CON0_SYNCBP_MSK BIT(LPUART_CON0_SYNCBP_POS) + +#define LPUART_CON0_CTSPOL_POS 13U +#define LPUART_CON0_CTSPOL_MSK BIT(LPUART_CON0_CTSPOL_POS) + +#define LPUART_CON0_RTSPOL_POS 12U +#define LPUART_CON0_RTSPOL_MSK BIT(LPUART_CON0_RTSPOL_POS) + +#define LPUART_CON0_ATCTSE_POS 11U +#define LPUART_CON0_ATCTSE_MSK BIT(LPUART_CON0_ATCTSE_POS) + +#define LPUART_CON0_ATRTSE_POS 10U +#define LPUART_CON0_ATRTSE_MSK BIT(LPUART_CON0_ATRTSE_POS) + +#define LPUART_CON0_BRKCE_POS 8U +#define LPUART_CON0_BRKCE_MSK BIT(LPUART_CON0_BRKCE_POS) + +#define LPUART_CON0_LPBMOD_POS 7U +#define LPUART_CON0_LPBMOD_MSK BIT(LPUART_CON0_LPBMOD_POS) + +#define LPUART_CON0_STICKPARSEL_POS 6U +#define LPUART_CON0_STICKPARSEL_MSK BIT(LPUART_CON0_STICKPARSEL_POS) + +#define LPUART_CON0_EVENPARSEL_POS 5U +#define LPUART_CON0_EVENPARSEL_MSK BIT(LPUART_CON0_EVENPARSEL_POS) + +#define LPUART_CON0_PARCHKE_POS 4U +#define LPUART_CON0_PARCHKE_MSK BIT(LPUART_CON0_PARCHKE_POS) + +#define LPUART_CON0_STPLENTH_POS 3U +#define LPUART_CON0_STPLENTH_MSK BIT(LPUART_CON0_STPLENTH_POS) + +#define LPUART_CON0_DATLENTH_POSS 0U +#define LPUART_CON0_DATLENTH_POSE 2U +#define LPUART_CON0_DATLENTH_MSK BITS(LPUART_CON0_DATLENTH_POSS,LPUART_CON0_DATLENTH_POSE) + +/****************** Bit definition for LPUART_CON1 register ************************/ + +#define LPUART_CON1_ADDCMP_POSS 24U +#define LPUART_CON1_ADDCMP_POSE 31U +#define LPUART_CON1_ADDCMP_MSK BITS(LPUART_CON1_ADDCMP_POSS,LPUART_CON1_ADDCMP_POSE) + +#define LPUART_CON1_ADETE_POS 23U +#define LPUART_CON1_ADETE_MSK BIT(LPUART_CON1_ADETE_POS) + +#define LPUART_CON1_ATDIRM_POS 22U +#define LPUART_CON1_ATDIRM_MSK BIT(LPUART_CON1_ATDIRM_POS) + +#define LPUART_CON1_ATADETE_POS 21U +#define LPUART_CON1_ATADETE_MSK BIT(LPUART_CON1_ATADETE_POS) + +#define LPUART_CON1_NMPMOD_POS 20U +#define LPUART_CON1_NMPMOD_MSK BIT(LPUART_CON1_NMPMOD_POS) + +#define LPUART_CON1_IRWIDTH_POS 16U +#define LPUART_CON1_IRWIDTH_MSK BIT(LPUART_CON1_IRWIDTH_POS) + +#define LPUART_CON1_TOICMP_POSS 8U +#define LPUART_CON1_TOICMP_POSE 15U +#define LPUART_CON1_TOICMP_MSK BITS(LPUART_CON1_TOICMP_POSS,LPUART_CON1_TOICMP_POSE) + +#define LPUART_CON1_TOCNTE_POS 7U +#define LPUART_CON1_TOCNTE_MSK BIT(LPUART_CON1_TOCNTE_POS) + +#define LPUART_CON1_IRTXINV_POS 3U +#define LPUART_CON1_IRTXINV_MSK BIT(LPUART_CON1_IRTXINV_POS) + +#define LPUART_CON1_IRRXINV_POS 2U +#define LPUART_CON1_IRRXINV_MSK BIT(LPUART_CON1_IRRXINV_POS) + +#define LPUART_CON1_IRTXE_POS 1U +#define LPUART_CON1_IRTXE_MSK BIT(LPUART_CON1_IRTXE_POS) + +#define LPUART_CON1_RTS_POS 0U +#define LPUART_CON1_RTS_MSK BIT(LPUART_CON1_RTS_POS) + +/****************** Bit definition for LPUART_CLKDIV register ************************/ + +#define LPUART_CLKDIV_CLKDIV_POSS 0U +#define LPUART_CLKDIV_CLKDIV_POSE 19U +#define LPUART_CLKDIV_CLKDIV_MSK BITS(LPUART_CLKDIV_CLKDIV_POSS,LPUART_CLKDIV_CLKDIV_POSE) + +/****************** Bit definition for LPUART_FIFOCON register ************************/ + +#define LPUART_FIFOCON_RTSTRGLVL_POSS 12U +#define LPUART_FIFOCON_RTSTRGLVL_POSE 15U +#define LPUART_FIFOCON_RTSTRGLVL_MSK BITS(LPUART_FIFOCON_RTSTRGLVL_POSS,LPUART_FIFOCON_RTSTRGLVL_POSE) + +#define LPUART_FIFOCON_RXTRGLVL_POSS 8U +#define LPUART_FIFOCON_RXTRGLVL_POSE 11U +#define LPUART_FIFOCON_RXTRGLVL_MSK BITS(LPUART_FIFOCON_RXTRGLVL_POSS,LPUART_FIFOCON_RXTRGLVL_POSE) + +#define LPUART_FIFOCON_NMPMRXDIS_POS 2U +#define LPUART_FIFOCON_NMPMRXDIS_MSK BIT(LPUART_FIFOCON_NMPMRXDIS_POS) + +#define LPUART_FIFOCON_TXRESET_POS 1U +#define LPUART_FIFOCON_TXRESET_MSK BIT(LPUART_FIFOCON_TXRESET_POS) + +#define LPUART_FIFOCON_RXRESET_POS 0U +#define LPUART_FIFOCON_RXRESET_MSK BIT(LPUART_FIFOCON_RXRESET_POS) + +/****************** Bit definition for LPUART_RXDR register ************************/ + +#define LPUART_RXDR_FERR_POS 15U +#define LPUART_RXDR_FERR_MSK BIT(LPUART_RXDR_FERR_POS) + +#define LPUART_RXDR_PERR_POS 14U +#define LPUART_RXDR_PERR_MSK BIT(LPUART_RXDR_PERR_POS) + +#define LPUART_RXDR_RXDR_POSS 0U +#define LPUART_RXDR_RXDR_POSE 8U +#define LPUART_RXDR_RXDR_MSK BITS(LPUART_RXDR_RXDR_POSS,LPUART_RXDR_RXDR_POSE) + +/****************** Bit definition for LPUART_TXDR register ************************/ + +#define LPUART_TXDR_TXDR_POSS 0U +#define LPUART_TXDR_TXDR_POSE 8U +#define LPUART_TXDR_TXDR_MSK BITS(LPUART_TXDR_TXDR_POSS,LPUART_TXDR_TXDR_POSE) + +/****************** Bit definition for LPUART_STAT register ************************/ + +#define LPUART_STAT_RTSSTAT_POS 18U +#define LPUART_STAT_RTSSTAT_MSK BIT(LPUART_STAT_RTSSTAT_POS) + +#define LPUART_STAT_CTSSTAT_POS 17U +#define LPUART_STAT_CTSSTAT_MSK BIT(LPUART_STAT_CTSSTAT_POS) + +#define LPUART_STAT_TXIDLE_POS 16U +#define LPUART_STAT_TXIDLE_MSK BIT(LPUART_STAT_TXIDLE_POS) + +#define LPUART_STAT_TXFULL_POS 15U +#define LPUART_STAT_TXFULL_MSK BIT(LPUART_STAT_TXFULL_POS) + +#define LPUART_STAT_TXEMP_POS 14U +#define LPUART_STAT_TXEMP_MSK BIT(LPUART_STAT_TXEMP_POS) + +#define LPUART_STAT_TXPTR_POSS 8U +#define LPUART_STAT_TXPTR_POSE 13U +#define LPUART_STAT_TXPTR_MSK BITS(LPUART_STAT_TXPTR_POSS,LPUART_STAT_TXPTR_POSE) + +#define LPUART_STAT_RXFULL_POS 7U +#define LPUART_STAT_RXFULL_MSK BIT(LPUART_STAT_RXFULL_POS) + +#define LPUART_STAT_RXEMP_POS 6U +#define LPUART_STAT_RXEMP_MSK BIT(LPUART_STAT_RXEMP_POS) + +#define LPUART_STAT_RXPTR_POSS 0U +#define LPUART_STAT_RXPTR_POSE 5U +#define LPUART_STAT_RXPTR_MSK BITS(LPUART_STAT_RXPTR_POSS,LPUART_STAT_RXPTR_POSE) + +/****************** Bit definition for LPUART_IER register ************************/ + +#define LPUART_IER_TCIE_POS 15U +#define LPUART_IER_TCIE_MSK BIT(LPUART_IER_TCIE_POS) + +#define LPUART_IER_ADETIE_POS 12U +#define LPUART_IER_ADETIE_MSK BIT(LPUART_IER_ADETIE_POS) + +#define LPUART_IER_BRKERRIE_POS 11U +#define LPUART_IER_BRKERRIE_MSK BIT(LPUART_IER_BRKERRIE_POS) + +#define LPUART_IER_FERRIE_POS 10U +#define LPUART_IER_FERRIE_MSK BIT(LPUART_IER_FERRIE_POS) + +#define LPUART_IER_PERRIE_POS 9U +#define LPUART_IER_PERRIE_MSK BIT(LPUART_IER_PERRIE_POS) + +#define LPUART_IER_DATWKIE_POS 8U +#define LPUART_IER_DATWKIE_MSK BIT(LPUART_IER_DATWKIE_POS) + +#define LPUART_IER_CTSWKIE_POS 7U +#define LPUART_IER_CTSWKIE_MSK BIT(LPUART_IER_CTSWKIE_POS) + +#define LPUART_IER_TXOVIE_POS 5U +#define LPUART_IER_TXOVIE_MSK BIT(LPUART_IER_TXOVIE_POS) + +#define LPUART_IER_RXOVIE_POS 4U +#define LPUART_IER_RXOVIE_MSK BIT(LPUART_IER_RXOVIE_POS) + +#define LPUART_IER_RXTOIE_POS 3U +#define LPUART_IER_RXTOIE_MSK BIT(LPUART_IER_RXTOIE_POS) + +#define LPUART_IER_CTSDETIE_POS 2U +#define LPUART_IER_CTSDETIE_MSK BIT(LPUART_IER_CTSDETIE_POS) + +#define LPUART_IER_TBEMPIE_POS 1U +#define LPUART_IER_TBEMPIE_MSK BIT(LPUART_IER_TBEMPIE_POS) + +#define LPUART_IER_RBRIE_POS 0U +#define LPUART_IER_RBRIE_MSK BIT(LPUART_IER_RBRIE_POS) + +/****************** Bit definition for LPUART_IFLAG register ************************/ + +#define LPUART_IFLAG_TCIF_POS 15U +#define LPUART_IFLAG_TCIF_MSK BIT(LPUART_IFLAG_TCIF_POS) + +#define LPUART_IFLAG_ADETIF_POS 12U +#define LPUART_IFLAG_ADETIF_MSK BIT(LPUART_IFLAG_ADETIF_POS) + +#define LPUART_IFLAG_BRKERRIF_POS 11U +#define LPUART_IFLAG_BRKERRIF_MSK BIT(LPUART_IFLAG_BRKERRIF_POS) + +#define LPUART_IFLAG_FERRIF_POS 10U +#define LPUART_IFLAG_FERRIF_MSK BIT(LPUART_IFLAG_FERRIF_POS) + +#define LPUART_IFLAG_PERRIF_POS 9U +#define LPUART_IFLAG_PERRIF_MSK BIT(LPUART_IFLAG_PERRIF_POS) + +#define LPUART_IFLAG_DATWKIF_POS 8U +#define LPUART_IFLAG_DATWKIF_MSK BIT(LPUART_IFLAG_DATWKIF_POS) + +#define LPUART_IFLAG_CTSWKIF_POS 7U +#define LPUART_IFLAG_CTSWKIF_MSK BIT(LPUART_IFLAG_CTSWKIF_POS) + +#define LPUART_IFLAG_TXOVIF_POS 5U +#define LPUART_IFLAG_TXOVIF_MSK BIT(LPUART_IFLAG_TXOVIF_POS) + +#define LPUART_IFLAG_RXOVIF_POS 4U +#define LPUART_IFLAG_RXOVIF_MSK BIT(LPUART_IFLAG_RXOVIF_POS) + +#define LPUART_IFLAG_RXTOIF_POS 3U +#define LPUART_IFLAG_RXTOIF_MSK BIT(LPUART_IFLAG_RXTOIF_POS) + +#define LPUART_IFLAG_CTSDETIF_POS 2U +#define LPUART_IFLAG_CTSDETIF_MSK BIT(LPUART_IFLAG_CTSDETIF_POS) + +#define LPUART_IFLAG_TBEMPIF_POS 1U +#define LPUART_IFLAG_TBEMPIF_MSK BIT(LPUART_IFLAG_TBEMPIF_POS) + +#define LPUART_IFLAG_RBRIF_POS 0U +#define LPUART_IFLAG_RBRIF_MSK BIT(LPUART_IFLAG_RBRIF_POS) + +/****************** Bit definition for LPUART_IFC register ************************/ + +#define LPUART_IFC_TCIFC_POS 15U +#define LPUART_IFC_TCIFC_MSK BIT(LPUART_IFC_TCIFC_POS) + +#define LPUART_IFC_ADETIFC_POS 12U +#define LPUART_IFC_ADETIFC_MSK BIT(LPUART_IFC_ADETIFC_POS) + +#define LPUART_IFC_BRKERRIFC_POS 11U +#define LPUART_IFC_BRKERRIFC_MSK BIT(LPUART_IFC_BRKERRIFC_POS) + +#define LPUART_IFC_FERRIFC_POS 10U +#define LPUART_IFC_FERRIFC_MSK BIT(LPUART_IFC_FERRIFC_POS) + +#define LPUART_IFC_PERRIFC_POS 9U +#define LPUART_IFC_PERRIFC_MSK BIT(LPUART_IFC_PERRIFC_POS) + +#define LPUART_IFC_DATWKIFC_POS 8U +#define LPUART_IFC_DATWKIFC_MSK BIT(LPUART_IFC_DATWKIFC_POS) + +#define LPUART_IFC_CTSWKIFC_POS 7U +#define LPUART_IFC_CTSWKIFC_MSK BIT(LPUART_IFC_CTSWKIFC_POS) + +#define LPUART_IFC_TXOVIFC_POS 5U +#define LPUART_IFC_TXOVIFC_MSK BIT(LPUART_IFC_TXOVIFC_POS) + +#define LPUART_IFC_RXOVIFC_POS 4U +#define LPUART_IFC_RXOVIFC_MSK BIT(LPUART_IFC_RXOVIFC_POS) + +#define LPUART_IFC_CTSDETIFC_POS 2U +#define LPUART_IFC_CTSDETIFC_MSK BIT(LPUART_IFC_CTSDETIFC_POS) + +#define LPUART_IFC_TBEMPIFC_POS 1U +#define LPUART_IFC_TBEMPIFC_MSK BIT(LPUART_IFC_TBEMPIFC_POS) + +#define LPUART_IFC_RBRIFC_POS 0U +#define LPUART_IFC_RBRIFC_MSK BIT(LPUART_IFC_RBRIFC_POS) + +/****************** Bit definition for LPUART_ISTAT register ************************/ + +#define LPUART_ISTAT_TCINT_POS 15U +#define LPUART_ISTAT_TCINT_MSK BIT(LPUART_ISTAT_TCINT_POS) + +#define LPUART_ISTAT_RXSTATINT_POS 9U +#define LPUART_ISTAT_RXSTATINT_MSK BIT(LPUART_ISTAT_RXSTATINT_POS) + +#define LPUART_ISTAT_DATWKINT_POS 8U +#define LPUART_ISTAT_DATWKINT_MSK BIT(LPUART_ISTAT_DATWKINT_POS) + +#define LPUART_ISTAT_CTSWKINT_POS 7U +#define LPUART_ISTAT_CTSWKINT_MSK BIT(LPUART_ISTAT_CTSWKINT_POS) + +#define LPUART_ISTAT_BUFERRINT_POS 4U +#define LPUART_ISTAT_BUFERRINT_MSK BIT(LPUART_ISTAT_BUFERRINT_POS) + +#define LPUART_ISTAT_RXTOINT_POS 3U +#define LPUART_ISTAT_RXTOINT_MSK BIT(LPUART_ISTAT_RXTOINT_POS) + +#define LPUART_ISTAT_CTSDETINT_POS 2U +#define LPUART_ISTAT_CTSDETINT_MSK BIT(LPUART_ISTAT_CTSDETINT_POS) + +#define LPUART_ISTAT_TBEMPINT_POS 1U +#define LPUART_ISTAT_TBEMPINT_MSK BIT(LPUART_ISTAT_TBEMPINT_POS) + +#define LPUART_ISTAT_RBRINT_POS 0U +#define LPUART_ISTAT_RBRINT_MSK BIT(LPUART_ISTAT_RBRINT_POS) + +/****************** Bit definition for LPUART_UPDATE register ************************/ + +#define LPUART_UPDATE_UDIS_POS 0U +#define LPUART_UPDATE_UDIS_MSK BIT(LPUART_UPDATE_UDIS_POS) + +/****************** Bit definition for LPUART_SYNCSTAT register ************************/ + +#define LPUART_SYNCSTAT_FIFOCONWBSY_POS 3U +#define LPUART_SYNCSTAT_FIFOCONWBSY_MSK BIT(LPUART_SYNCSTAT_FIFOCONWBSY_POS) + +#define LPUART_SYNCSTAT_CLKDIVWBSY_POS 2U +#define LPUART_SYNCSTAT_CLKDIVWBSY_MSK BIT(LPUART_SYNCSTAT_CLKDIVWBSY_POS) + +#define LPUART_SYNCSTAT_CON1WBSY_POS 1U +#define LPUART_SYNCSTAT_CON1WBSY_MSK BIT(LPUART_SYNCSTAT_CON1WBSY_POS) + +#define LPUART_SYNCSTAT_CON0WBSY_POS 0U +#define LPUART_SYNCSTAT_CON0WBSY_MSK BIT(LPUART_SYNCSTAT_CON0WBSY_POS) + +typedef struct +{ + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t CLKDIV; + __IO uint32_t FIFOCON; + uint32_t RESERVED0 ; + __I uint32_t RXDR; + __O uint32_t TXDR; + __I uint32_t STAT; + __IO uint32_t IER; + __I uint32_t IFLAG; + __O uint32_t IFC; + __I uint32_t ISTAT; + uint32_t RESERVED1[2] ; + __IO uint32_t UPDATE; + __I uint32_t SYNCSTAT; +} LPUART_TypeDef; + +/****************** Bit definition for SPI_CON1 register ************************/ + +#define SPI_CON1_BIDEN_POS 15U +#define SPI_CON1_BIDEN_MSK BIT(SPI_CON1_BIDEN_POS) + +#define SPI_CON1_BIDOEN_POS 14U +#define SPI_CON1_BIDOEN_MSK BIT(SPI_CON1_BIDOEN_POS) + +#define SPI_CON1_CRCEN_POS 13U +#define SPI_CON1_CRCEN_MSK BIT(SPI_CON1_CRCEN_POS) + +#define SPI_CON1_NXTCRC_POS 12U +#define SPI_CON1_NXTCRC_MSK BIT(SPI_CON1_NXTCRC_POS) + +#define SPI_CON1_FLEN_POS 11U +#define SPI_CON1_FLEN_MSK BIT(SPI_CON1_FLEN_POS) + +#define SPI_CON1_RXO_POS 10U +#define SPI_CON1_RXO_MSK BIT(SPI_CON1_RXO_POS) + +#define SPI_CON1_SSEN_POS 9U +#define SPI_CON1_SSEN_MSK BIT(SPI_CON1_SSEN_POS) + +#define SPI_CON1_SSOUT_POS 8U +#define SPI_CON1_SSOUT_MSK BIT(SPI_CON1_SSOUT_POS) + +#define SPI_CON1_LSBFST_POS 7U +#define SPI_CON1_LSBFST_MSK BIT(SPI_CON1_LSBFST_POS) + +#define SPI_CON1_SPIEN_POS 6U +#define SPI_CON1_SPIEN_MSK BIT(SPI_CON1_SPIEN_POS) + +#define SPI_CON1_BAUD_POSS 3U +#define SPI_CON1_BAUD_POSE 5U +#define SPI_CON1_BAUD_MSK BITS(SPI_CON1_BAUD_POSS,SPI_CON1_BAUD_POSE) + +#define SPI_CON1_MSTREN_POS 2U +#define SPI_CON1_MSTREN_MSK BIT(SPI_CON1_MSTREN_POS) + +#define SPI_CON1_CPOL_POS 1U +#define SPI_CON1_CPOL_MSK BIT(SPI_CON1_CPOL_POS) + +#define SPI_CON1_CPHA_POS 0U +#define SPI_CON1_CPHA_MSK BIT(SPI_CON1_CPHA_POS) + +/****************** Bit definition for SPI_CON2 register ************************/ + +#define SPI_CON2_TXBEIE_POS 7U +#define SPI_CON2_TXBEIE_MSK BIT(SPI_CON2_TXBEIE_POS) + +#define SPI_CON2_RXBNEIE_POS 6U +#define SPI_CON2_RXBNEIE_MSK BIT(SPI_CON2_RXBNEIE_POS) + +#define SPI_CON2_ERRIE_POS 5U +#define SPI_CON2_ERRIE_MSK BIT(SPI_CON2_ERRIE_POS) + +#define SPI_CON2_NSSOE_POS 2U +#define SPI_CON2_NSSOE_MSK BIT(SPI_CON2_NSSOE_POS) + +#define SPI_CON2_TXDMA_POS 1U +#define SPI_CON2_TXDMA_MSK BIT(SPI_CON2_TXDMA_POS) + +#define SPI_CON2_RXDMA_POS 0U +#define SPI_CON2_RXDMA_MSK BIT(SPI_CON2_RXDMA_POS) + +/****************** Bit definition for SPI_STAT register ************************/ + +#define SPI_STAT_BUSY_POS 7U +#define SPI_STAT_BUSY_MSK BIT(SPI_STAT_BUSY_POS) + +#define SPI_STAT_OVERR_POS 6U +#define SPI_STAT_OVERR_MSK BIT(SPI_STAT_OVERR_POS) + +#define SPI_STAT_MODERR_POS 5U +#define SPI_STAT_MODERR_MSK BIT(SPI_STAT_MODERR_POS) + +#define SPI_STAT_CRCERR_POS 4U +#define SPI_STAT_CRCERR_MSK BIT(SPI_STAT_CRCERR_POS) + +#define SPI_STAT_TXBE_POS 1U +#define SPI_STAT_TXBE_MSK BIT(SPI_STAT_TXBE_POS) + +#define SPI_STAT_RXBNE_POS 0U +#define SPI_STAT_RXBNE_MSK BIT(SPI_STAT_RXBNE_POS) + +/****************** Bit definition for SPI_DATA register ************************/ + +#define SPI_DATA_VALUE_POSS 0U +#define SPI_DATA_VALUE_POSE 15U +#define SPI_DATA_VALUE_MSK BITS(SPI_DATA_VALUE_POSS,SPI_DATA_VALUE_POSE) + +/****************** Bit definition for SPI_CRCPOLY register ************************/ + +#define SPI_CRCPOLY_VALUE_POSS 0U +#define SPI_CRCPOLY_VALUE_POSE 15U +#define SPI_CRCPOLY_VALUE_MSK BITS(SPI_CRCPOLY_VALUE_POSS,SPI_CRCPOLY_VALUE_POSE) + +/****************** Bit definition for SPI_RXCRC register ************************/ + +#define SPI_RXCRC_CRCVAL_POSS 0U +#define SPI_RXCRC_CRCVAL_POSE 15U +#define SPI_RXCRC_CRCVAL_MSK BITS(SPI_RXCRC_CRCVAL_POSS,SPI_RXCRC_CRCVAL_POSE) + +/****************** Bit definition for SPI_TXCRC register ************************/ + +#define SPI_TXCRC_CRCVAL_POSS 0U +#define SPI_TXCRC_CRCVAL_POSE 15U +#define SPI_TXCRC_CRCVAL_MSK BITS(SPI_TXCRC_CRCVAL_POSS,SPI_TXCRC_CRCVAL_POSE) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t STAT; + __IO uint32_t DATA; + __IO uint32_t CRCPOLY; + __I uint32_t RXCRC; + __I uint32_t TXCRC; +} SPI_TypeDef; + +/****************** Bit definition for I2C_CON1 register ************************/ + +#define I2C_CON1_SRST_POS 15U +#define I2C_CON1_SRST_MSK BIT(I2C_CON1_SRST_POS) + +#define I2C_CON1_ALARM_POS 13U +#define I2C_CON1_ALARM_MSK BIT(I2C_CON1_ALARM_POS) + +#define I2C_CON1_TRPEC_POS 12U +#define I2C_CON1_TRPEC_MSK BIT(I2C_CON1_TRPEC_POS) + +#define I2C_CON1_POSAP_POS 11U +#define I2C_CON1_POSAP_MSK BIT(I2C_CON1_POSAP_POS) + +#define I2C_CON1_ACKEN_POS 10U +#define I2C_CON1_ACKEN_MSK BIT(I2C_CON1_ACKEN_POS) + +#define I2C_CON1_STOP_POS 9U +#define I2C_CON1_STOP_MSK BIT(I2C_CON1_STOP_POS) + +#define I2C_CON1_START_POS 8U +#define I2C_CON1_START_MSK BIT(I2C_CON1_START_POS) + +#define I2C_CON1_DISCS_POS 7U +#define I2C_CON1_DISCS_MSK BIT(I2C_CON1_DISCS_POS) + +#define I2C_CON1_GCEN_POS 6U +#define I2C_CON1_GCEN_MSK BIT(I2C_CON1_GCEN_POS) + +#define I2C_CON1_PECEN_POS 5U +#define I2C_CON1_PECEN_MSK BIT(I2C_CON1_PECEN_POS) + +#define I2C_CON1_ARPEN_POS 4U +#define I2C_CON1_ARPEN_MSK BIT(I2C_CON1_ARPEN_POS) + +#define I2C_CON1_SMBMOD_POS 3U +#define I2C_CON1_SMBMOD_MSK BIT(I2C_CON1_SMBMOD_POS) + +#define I2C_CON1_PMOD_POS 1U +#define I2C_CON1_PMOD_MSK BIT(I2C_CON1_PMOD_POS) + +#define I2C_CON1_PEN_POS 0U +#define I2C_CON1_PEN_MSK BIT(I2C_CON1_PEN_POS) + +/****************** Bit definition for I2C_CON2 register ************************/ + +#define I2C_CON2_LDMA_POS 12U +#define I2C_CON2_LDMA_MSK BIT(I2C_CON2_LDMA_POS) + +#define I2C_CON2_DMAEN_POS 11U +#define I2C_CON2_DMAEN_MSK BIT(I2C_CON2_DMAEN_POS) + +#define I2C_CON2_BUFIE_POS 10U +#define I2C_CON2_BUFIE_MSK BIT(I2C_CON2_BUFIE_POS) + +#define I2C_CON2_EVTIE_POS 9U +#define I2C_CON2_EVTIE_MSK BIT(I2C_CON2_EVTIE_POS) + +#define I2C_CON2_ERRIE_POS 8U +#define I2C_CON2_ERRIE_MSK BIT(I2C_CON2_ERRIE_POS) + +#define I2C_CON2_CLKF_POSS 0U +#define I2C_CON2_CLKF_POSE 5U +#define I2C_CON2_CLKF_MSK BITS(I2C_CON2_CLKF_POSS,I2C_CON2_CLKF_POSE) + +/****************** Bit definition for I2C_ADDR1 register ************************/ + +#define I2C_ADDR1_ADDTYPE_POS 15U +#define I2C_ADDR1_ADDTYPE_MSK BIT(I2C_ADDR1_ADDTYPE_POS) + +#define I2C_ADDR1_ADDH_POSS 8U +#define I2C_ADDR1_ADDH_POSE 9U +#define I2C_ADDR1_ADDH_MSK BITS(I2C_ADDR1_ADDH_POSS,I2C_ADDR1_ADDH_POSE) + +#define I2C_ADDR1_ADD_POSS 1U +#define I2C_ADDR1_ADD_POSE 7U +#define I2C_ADDR1_ADD_MSK BITS(I2C_ADDR1_ADD_POSS,I2C_ADDR1_ADD_POSE) + +#define I2C_ADDR1_ADDLSB_POS 0U +#define I2C_ADDR1_ADDLSB_MSK BIT(I2C_ADDR1_ADDLSB_POS) + +/****************** Bit definition for I2C_ADDR2 register ************************/ + +#define I2C_ADDR2_ADD_POSS 1U +#define I2C_ADDR2_ADD_POSE 7U +#define I2C_ADDR2_ADD_MSK BITS(I2C_ADDR2_ADD_POSS,I2C_ADDR2_ADD_POSE) + +#define I2C_ADDR2_DUALEN_POS 0U +#define I2C_ADDR2_DUALEN_MSK BIT(I2C_ADDR2_DUALEN_POS) + +/****************** Bit definition for I2C_DATA register ************************/ + +#define I2C_DATA_TRBUF_POSS 0U +#define I2C_DATA_TRBUF_POSE 7U +#define I2C_DATA_TRBUF_MSK BITS(I2C_DATA_TRBUF_POSS,I2C_DATA_TRBUF_POSE) + +/****************** Bit definition for I2C_STAT1 register ************************/ + +#define I2C_STAT1_SMBALARM_POS 15U +#define I2C_STAT1_SMBALARM_MSK BIT(I2C_STAT1_SMBALARM_POS) + +#define I2C_STAT1_SMBTO_POS 14U +#define I2C_STAT1_SMBTO_MSK BIT(I2C_STAT1_SMBTO_POS) + +#define I2C_STAT1_PECERR_POS 12U +#define I2C_STAT1_PECERR_MSK BIT(I2C_STAT1_PECERR_POS) + +#define I2C_STAT1_ROUERR_POS 11U +#define I2C_STAT1_ROUERR_MSK BIT(I2C_STAT1_ROUERR_POS) + +#define I2C_STAT1_ACKERR_POS 10U +#define I2C_STAT1_ACKERR_MSK BIT(I2C_STAT1_ACKERR_POS) + +#define I2C_STAT1_LARB_POS 9U +#define I2C_STAT1_LARB_MSK BIT(I2C_STAT1_LARB_POS) + +#define I2C_STAT1_BUSERR_POS 8U +#define I2C_STAT1_BUSERR_MSK BIT(I2C_STAT1_BUSERR_POS) + +#define I2C_STAT1_TXBE_POS 7U +#define I2C_STAT1_TXBE_MSK BIT(I2C_STAT1_TXBE_POS) + +#define I2C_STAT1_RXBNE_POS 6U +#define I2C_STAT1_RXBNE_MSK BIT(I2C_STAT1_RXBNE_POS) + +#define I2C_STAT1_DETSTP_POS 4U +#define I2C_STAT1_DETSTP_MSK BIT(I2C_STAT1_DETSTP_POS) + +#define I2C_STAT1_SENDADD10_POS 3U +#define I2C_STAT1_SENDADD10_MSK BIT(I2C_STAT1_SENDADD10_POS) + +#define I2C_STAT1_BTC_POS 2U +#define I2C_STAT1_BTC_MSK BIT(I2C_STAT1_BTC_POS) + +#define I2C_STAT1_ADDR_POS 1U +#define I2C_STAT1_ADDR_MSK BIT(I2C_STAT1_ADDR_POS) + +#define I2C_STAT1_SENDSTR_POS 0U +#define I2C_STAT1_SENDSTR_MSK BIT(I2C_STAT1_SENDSTR_POS) + +/****************** Bit definition for I2C_STAT2 register ************************/ + +#define I2C_STAT2_PECV_POSS 8U +#define I2C_STAT2_PECV_POSE 15U +#define I2C_STAT2_PECV_MSK BITS(I2C_STAT2_PECV_POSS,I2C_STAT2_PECV_POSE) + +#define I2C_STAT2_DMF_POS 7U +#define I2C_STAT2_DMF_MSK BIT(I2C_STAT2_DMF_POS) + +#define I2C_STAT2_SMBHH_POS 6U +#define I2C_STAT2_SMBHH_MSK BIT(I2C_STAT2_SMBHH_POS) + +#define I2C_STAT2_SMBDEF_POS 5U +#define I2C_STAT2_SMBDEF_MSK BIT(I2C_STAT2_SMBDEF_POS) + +#define I2C_STAT2_RXGCF_POS 4U +#define I2C_STAT2_RXGCF_MSK BIT(I2C_STAT2_RXGCF_POS) + +#define I2C_STAT2_TRF_POS 2U +#define I2C_STAT2_TRF_MSK BIT(I2C_STAT2_TRF_POS) + +#define I2C_STAT2_BSYF_POS 1U +#define I2C_STAT2_BSYF_MSK BIT(I2C_STAT2_BSYF_POS) + +#define I2C_STAT2_MASTER_POS 0U +#define I2C_STAT2_MASTER_MSK BIT(I2C_STAT2_MASTER_POS) + +/****************** Bit definition for I2C_CKCFG register ************************/ + +#define I2C_CKCFG_CLKMOD_POS 15U +#define I2C_CKCFG_CLKMOD_MSK BIT(I2C_CKCFG_CLKMOD_POS) + +#define I2C_CKCFG_DUTY_POS 14U +#define I2C_CKCFG_DUTY_MSK BIT(I2C_CKCFG_DUTY_POS) + +#define I2C_CKCFG_CLKSET_POSS 0U +#define I2C_CKCFG_CLKSET_POSE 11U +#define I2C_CKCFG_CLKSET_MSK BITS(I2C_CKCFG_CLKSET_POSS,I2C_CKCFG_CLKSET_POSE) + +/****************** Bit definition for I2C_RT register ************************/ + +#define I2C_RT_RISET_POSS 0U +#define I2C_RT_RISET_POSE 5U +#define I2C_RT_RISET_MSK BITS(I2C_RT_RISET_POSS,I2C_RT_RISET_POSE) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t ADDR1; + __IO uint32_t ADDR2; + __IO uint32_t DATA; + __IO uint32_t STAT1; + __I uint32_t STAT2; + __IO uint32_t CKCFG; + __IO uint32_t RT; +} I2C_TypeDef; + +/****************** Bit definition for CAN_CON register ************************/ + +#define CAN_CON_DBGSTP_POS 16U +#define CAN_CON_DBGSTP_MSK BIT(CAN_CON_DBGSTP_POS) + +#define CAN_CON_RST_POS 15U +#define CAN_CON_RST_MSK BIT(CAN_CON_RST_POS) + +#define CAN_CON_TTCEN_POS 7U +#define CAN_CON_TTCEN_MSK BIT(CAN_CON_TTCEN_POS) + +#define CAN_CON_ABOFFEN_POS 6U +#define CAN_CON_ABOFFEN_MSK BIT(CAN_CON_ABOFFEN_POS) + +#define CAN_CON_AWKEN_POS 5U +#define CAN_CON_AWKEN_MSK BIT(CAN_CON_AWKEN_POS) + +#define CAN_CON_ARTXDIS_POS 4U +#define CAN_CON_ARTXDIS_MSK BIT(CAN_CON_ARTXDIS_POS) + +#define CAN_CON_RXFOPM_POS 3U +#define CAN_CON_RXFOPM_MSK BIT(CAN_CON_RXFOPM_POS) + +#define CAN_CON_TXMP_POS 2U +#define CAN_CON_TXMP_MSK BIT(CAN_CON_TXMP_POS) + +#define CAN_CON_SLPREQ_POS 1U +#define CAN_CON_SLPREQ_MSK BIT(CAN_CON_SLPREQ_POS) + +#define CAN_CON_INIREQ_POS 0U +#define CAN_CON_INIREQ_MSK BIT(CAN_CON_INIREQ_POS) + +/****************** Bit definition for CAN_STAT register ************************/ + +#define CAN_STAT_RX_POS 11U +#define CAN_STAT_RX_MSK BIT(CAN_STAT_RX_POS) + +#define CAN_STAT_PRESMP_POS 10U +#define CAN_STAT_PRESMP_MSK BIT(CAN_STAT_PRESMP_POS) + +#define CAN_STAT_RXSTAT_POS 9U +#define CAN_STAT_RXSTAT_MSK BIT(CAN_STAT_RXSTAT_POS) + +#define CAN_STAT_TXSTAT_POS 8U +#define CAN_STAT_TXSTAT_MSK BIT(CAN_STAT_TXSTAT_POS) + +#define CAN_STAT_SLPIF_POS 4U +#define CAN_STAT_SLPIF_MSK BIT(CAN_STAT_SLPIF_POS) + +#define CAN_STAT_WKIF_POS 3U +#define CAN_STAT_WKIF_MSK BIT(CAN_STAT_WKIF_POS) + +#define CAN_STAT_ERRIF_POS 2U +#define CAN_STAT_ERRIF_MSK BIT(CAN_STAT_ERRIF_POS) + +#define CAN_STAT_SLPSTAT_POS 1U +#define CAN_STAT_SLPSTAT_MSK BIT(CAN_STAT_SLPSTAT_POS) + +#define CAN_STAT_INISTAT_POS 0U +#define CAN_STAT_INISTAT_MSK BIT(CAN_STAT_INISTAT_POS) + +/****************** Bit definition for CAN_IFC register ************************/ + +#define CAN_IFC_SLPIFC_POS 4U +#define CAN_IFC_SLPIFC_MSK BIT(CAN_IFC_SLPIFC_POS) + +#define CAN_IFC_WKIFC_POS 3U +#define CAN_IFC_WKIFC_MSK BIT(CAN_IFC_WKIFC_POS) + +#define CAN_IFC_ERRIFC_POS 2U +#define CAN_IFC_ERRIFC_MSK BIT(CAN_IFC_ERRIFC_POS) + +/****************** Bit definition for CAN_TXSTAT register ************************/ + +#define CAN_TXSTAT_TXM2LPF_POS 31U +#define CAN_TXSTAT_TXM2LPF_MSK BIT(CAN_TXSTAT_TXM2LPF_POS) + +#define CAN_TXSTAT_TXM1LPF_POS 30U +#define CAN_TXSTAT_TXM1LPF_MSK BIT(CAN_TXSTAT_TXM1LPF_POS) + +#define CAN_TXSTAT_TXM0LPF_POS 29U +#define CAN_TXSTAT_TXM0LPF_MSK BIT(CAN_TXSTAT_TXM0LPF_POS) + +#define CAN_TXSTAT_TXM2EF_POS 28U +#define CAN_TXSTAT_TXM2EF_MSK BIT(CAN_TXSTAT_TXM2EF_POS) + +#define CAN_TXSTAT_TXM1EF_POS 27U +#define CAN_TXSTAT_TXM1EF_MSK BIT(CAN_TXSTAT_TXM1EF_POS) + +#define CAN_TXSTAT_TXM0EF_POS 26U +#define CAN_TXSTAT_TXM0EF_MSK BIT(CAN_TXSTAT_TXM0EF_POS) + +#define CAN_TXSTAT_CODE_POSS 24U +#define CAN_TXSTAT_CODE_POSE 25U +#define CAN_TXSTAT_CODE_MSK BITS(CAN_TXSTAT_CODE_POSS,CAN_TXSTAT_CODE_POSE) + +#define CAN_TXSTAT_M2STPREQ_POS 23U +#define CAN_TXSTAT_M2STPREQ_MSK BIT(CAN_TXSTAT_M2STPREQ_POS) + +#define CAN_TXSTAT_M2TXERR_POS 19U +#define CAN_TXSTAT_M2TXERR_MSK BIT(CAN_TXSTAT_M2TXERR_POS) + +#define CAN_TXSTAT_M2ARBLST_POS 18U +#define CAN_TXSTAT_M2ARBLST_MSK BIT(CAN_TXSTAT_M2ARBLST_POS) + +#define CAN_TXSTAT_M2TXC_POS 17U +#define CAN_TXSTAT_M2TXC_MSK BIT(CAN_TXSTAT_M2TXC_POS) + +#define CAN_TXSTAT_M2REQC_POS 16U +#define CAN_TXSTAT_M2REQC_MSK BIT(CAN_TXSTAT_M2REQC_POS) + +#define CAN_TXSTAT_M1STPREQ_POS 15U +#define CAN_TXSTAT_M1STPREQ_MSK BIT(CAN_TXSTAT_M1STPREQ_POS) + +#define CAN_TXSTAT_M1TXERR_POS 11U +#define CAN_TXSTAT_M1TXERR_MSK BIT(CAN_TXSTAT_M1TXERR_POS) + +#define CAN_TXSTAT_M1ARBLST_POS 10U +#define CAN_TXSTAT_M1ARBLST_MSK BIT(CAN_TXSTAT_M1ARBLST_POS) + +#define CAN_TXSTAT_M1TXC_POS 9U +#define CAN_TXSTAT_M1TXC_MSK BIT(CAN_TXSTAT_M1TXC_POS) + +#define CAN_TXSTAT_M1REQC_POS 8U +#define CAN_TXSTAT_M1REQC_MSK BIT(CAN_TXSTAT_M1REQC_POS) + +#define CAN_TXSTAT_M0STPREQ_POS 7U +#define CAN_TXSTAT_M0STPREQ_MSK BIT(CAN_TXSTAT_M0STPREQ_POS) + +#define CAN_TXSTAT_M0TXERR_POS 3U +#define CAN_TXSTAT_M0TXERR_MSK BIT(CAN_TXSTAT_M0TXERR_POS) + +#define CAN_TXSTAT_M0ARBLST_POS 2U +#define CAN_TXSTAT_M0ARBLST_MSK BIT(CAN_TXSTAT_M0ARBLST_POS) + +#define CAN_TXSTAT_M0TXC_POS 1U +#define CAN_TXSTAT_M0TXC_MSK BIT(CAN_TXSTAT_M0TXC_POS) + +#define CAN_TXSTAT_M0REQC_POS 0U +#define CAN_TXSTAT_M0REQC_MSK BIT(CAN_TXSTAT_M0REQC_POS) + +/****************** Bit definition for CAN_TXSTATC register ************************/ + +#define CAN_TXSTATC_M2TXERR_POS 19U +#define CAN_TXSTATC_M2TXERR_MSK BIT(CAN_TXSTATC_M2TXERR_POS) + +#define CAN_TXSTATC_M2ARBLST_POS 18U +#define CAN_TXSTATC_M2ARBLST_MSK BIT(CAN_TXSTATC_M2ARBLST_POS) + +#define CAN_TXSTATC_M2TXC_POS 17U +#define CAN_TXSTATC_M2TXC_MSK BIT(CAN_TXSTATC_M2TXC_POS) + +#define CAN_TXSTATC_M2REQC_POS 16U +#define CAN_TXSTATC_M2REQC_MSK BIT(CAN_TXSTATC_M2REQC_POS) + +#define CAN_TXSTATC_M1TXERR_POS 11U +#define CAN_TXSTATC_M1TXERR_MSK BIT(CAN_TXSTATC_M1TXERR_POS) + +#define CAN_TXSTATC_M1ARBLST_POS 10U +#define CAN_TXSTATC_M1ARBLST_MSK BIT(CAN_TXSTATC_M1ARBLST_POS) + +#define CAN_TXSTATC_M1TXC_POS 9U +#define CAN_TXSTATC_M1TXC_MSK BIT(CAN_TXSTATC_M1TXC_POS) + +#define CAN_TXSTATC_M1REQC_POS 8U +#define CAN_TXSTATC_M1REQC_MSK BIT(CAN_TXSTATC_M1REQC_POS) + +#define CAN_TXSTATC_M0TXERR_POS 3U +#define CAN_TXSTATC_M0TXERR_MSK BIT(CAN_TXSTATC_M0TXERR_POS) + +#define CAN_TXSTATC_M0ARBLST_POS 2U +#define CAN_TXSTATC_M0ARBLST_MSK BIT(CAN_TXSTATC_M0ARBLST_POS) + +#define CAN_TXSTATC_M0TXC_POS 1U +#define CAN_TXSTATC_M0TXC_MSK BIT(CAN_TXSTATC_M0TXC_POS) + +#define CAN_TXSTATC_M0REQC_POS 0U +#define CAN_TXSTATC_M0REQC_MSK BIT(CAN_TXSTATC_M0REQC_POS) + +/****************** Bit definition for CAN_RXF0 register ************************/ + +#define CAN_RXF0_FREE_POS 5U +#define CAN_RXF0_FREE_MSK BIT(CAN_RXF0_FREE_POS) + +#define CAN_RXF0_OVR_POS 4U +#define CAN_RXF0_OVR_MSK BIT(CAN_RXF0_OVR_POS) + +#define CAN_RXF0_FULL_POS 3U +#define CAN_RXF0_FULL_MSK BIT(CAN_RXF0_FULL_POS) + +#define CAN_RXF0_PEND_POSS 0U +#define CAN_RXF0_PEND_POSE 1U +#define CAN_RXF0_PEND_MSK BITS(CAN_RXF0_PEND_POSS,CAN_RXF0_PEND_POSE) + +/****************** Bit definition for CAN_RXF0C register ************************/ + +#define CAN_RXF0C_OVRC_POS 4U +#define CAN_RXF0C_OVRC_MSK BIT(CAN_RXF0C_OVRC_POS) + +#define CAN_RXF0C_FULLC_POS 3U +#define CAN_RXF0C_FULLC_MSK BIT(CAN_RXF0C_FULLC_POS) + +/****************** Bit definition for CAN_RXF1 register ************************/ + +#define CAN_RXF1_FREE_POS 5U +#define CAN_RXF1_FREE_MSK BIT(CAN_RXF1_FREE_POS) + +#define CAN_RXF1_OVR_POS 4U +#define CAN_RXF1_OVR_MSK BIT(CAN_RXF1_OVR_POS) + +#define CAN_RXF1_FULL_POS 3U +#define CAN_RXF1_FULL_MSK BIT(CAN_RXF1_FULL_POS) + +#define CAN_RXF1_PEND_POSS 0U +#define CAN_RXF1_PEND_POSE 1U +#define CAN_RXF1_PEND_MSK BITS(CAN_RXF1_PEND_POSS,CAN_RXF1_PEND_POSE) + +/****************** Bit definition for CAN_RXF1C register ************************/ + +#define CAN_RXF1C_OVRC_POS 4U +#define CAN_RXF1C_OVRC_MSK BIT(CAN_RXF1C_OVRC_POS) + +#define CAN_RXF1C_FULLC_POS 3U +#define CAN_RXF1C_FULLC_MSK BIT(CAN_RXF1C_FULLC_POS) + +/****************** Bit definition for CAN_IE register ************************/ + +#define CAN_IE_SLPIE_POS 17U +#define CAN_IE_SLPIE_MSK BIT(CAN_IE_SLPIE_POS) + +#define CAN_IE_WKIE_POS 16U +#define CAN_IE_WKIE_MSK BIT(CAN_IE_WKIE_POS) + +#define CAN_IE_ERRIE_POS 15U +#define CAN_IE_ERRIE_MSK BIT(CAN_IE_ERRIE_POS) + +#define CAN_IE_PRERRIE_POS 11U +#define CAN_IE_PRERRIE_MSK BIT(CAN_IE_PRERRIE_POS) + +#define CAN_IE_BOFFIE_POS 10U +#define CAN_IE_BOFFIE_MSK BIT(CAN_IE_BOFFIE_POS) + +#define CAN_IE_PERRIE_POS 9U +#define CAN_IE_PERRIE_MSK BIT(CAN_IE_PERRIE_POS) + +#define CAN_IE_WARNIE_POS 8U +#define CAN_IE_WARNIE_MSK BIT(CAN_IE_WARNIE_POS) + +#define CAN_IE_F1OVRIE_POS 6U +#define CAN_IE_F1OVRIE_MSK BIT(CAN_IE_F1OVRIE_POS) + +#define CAN_IE_F1FULIE_POS 5U +#define CAN_IE_F1FULIE_MSK BIT(CAN_IE_F1FULIE_POS) + +#define CAN_IE_F1PIE_POS 4U +#define CAN_IE_F1PIE_MSK BIT(CAN_IE_F1PIE_POS) + +#define CAN_IE_F0OVRIE_POS 3U +#define CAN_IE_F0OVRIE_MSK BIT(CAN_IE_F0OVRIE_POS) + +#define CAN_IE_F0FULIE_POS 2U +#define CAN_IE_F0FULIE_MSK BIT(CAN_IE_F0FULIE_POS) + +#define CAN_IE_F0PIE_POS 1U +#define CAN_IE_F0PIE_MSK BIT(CAN_IE_F0PIE_POS) + +#define CAN_IE_TXMEIE_POS 0U +#define CAN_IE_TXMEIE_MSK BIT(CAN_IE_TXMEIE_POS) + +/****************** Bit definition for CAN_ERRSTAT register ************************/ + +#define CAN_ERRSTAT_RXERRC_POSS 24U +#define CAN_ERRSTAT_RXERRC_POSE 31U +#define CAN_ERRSTAT_RXERRC_MSK BITS(CAN_ERRSTAT_RXERRC_POSS,CAN_ERRSTAT_RXERRC_POSE) + +#define CAN_ERRSTAT_TXERRC_POSS 16U +#define CAN_ERRSTAT_TXERRC_POSE 23U +#define CAN_ERRSTAT_TXERRC_MSK BITS(CAN_ERRSTAT_TXERRC_POSS,CAN_ERRSTAT_TXERRC_POSE) + +#define CAN_ERRSTAT_PRERRF_POSS 4U +#define CAN_ERRSTAT_PRERRF_POSE 6U +#define CAN_ERRSTAT_PRERRF_MSK BITS(CAN_ERRSTAT_PRERRF_POSS,CAN_ERRSTAT_PRERRF_POSE) + +#define CAN_ERRSTAT_BOFF_POS 2U +#define CAN_ERRSTAT_BOFF_MSK BIT(CAN_ERRSTAT_BOFF_POS) + +#define CAN_ERRSTAT_PERRF_POS 1U +#define CAN_ERRSTAT_PERRF_MSK BIT(CAN_ERRSTAT_PERRF_POS) + +#define CAN_ERRSTAT_WARNF_POS 0U +#define CAN_ERRSTAT_WARNF_MSK BIT(CAN_ERRSTAT_WARNF_POS) + +/****************** Bit definition for CAN_BTIME register ************************/ + +#define CAN_BTIME_SILENT_POS 31U +#define CAN_BTIME_SILENT_MSK BIT(CAN_BTIME_SILENT_POS) + +#define CAN_BTIME_LOOP_POS 30U +#define CAN_BTIME_LOOP_MSK BIT(CAN_BTIME_LOOP_POS) + +#define CAN_BTIME_RESJW_POSS 24U +#define CAN_BTIME_RESJW_POSE 25U +#define CAN_BTIME_RESJW_MSK BITS(CAN_BTIME_RESJW_POSS,CAN_BTIME_RESJW_POSE) + +#define CAN_BTIME_SEG2_POSS 20U +#define CAN_BTIME_SEG2_POSE 22U +#define CAN_BTIME_SEG2_MSK BITS(CAN_BTIME_SEG2_POSS,CAN_BTIME_SEG2_POSE) + +#define CAN_BTIME_SEG1_POSS 16U +#define CAN_BTIME_SEG1_POSE 19U +#define CAN_BTIME_SEG1_MSK BITS(CAN_BTIME_SEG1_POSS,CAN_BTIME_SEG1_POSE) + +#define CAN_BTIME_BPSC_POSS 0U +#define CAN_BTIME_BPSC_POSE 9U +#define CAN_BTIME_BPSC_MSK BITS(CAN_BTIME_BPSC_POSS,CAN_BTIME_BPSC_POSE) + +/****************** Bit definition for CAN_TXID0 register ************************/ + +#define CAN_TXID0_STDID_POSS 21U +#define CAN_TXID0_STDID_POSE 31U +#define CAN_TXID0_STDID_MSK BITS(CAN_TXID0_STDID_POSS,CAN_TXID0_STDID_POSE) + +#define CAN_TXID0_EXID_POSS 3U +#define CAN_TXID0_EXID_POSE 20U +#define CAN_TXID0_EXID_MSK BITS(CAN_TXID0_EXID_POSS,CAN_TXID0_EXID_POSE) + +#define CAN_TXID0_IDE_POS 2U +#define CAN_TXID0_IDE_MSK BIT(CAN_TXID0_IDE_POS) + +#define CAN_TXID0_RTR_POS 1U +#define CAN_TXID0_RTR_MSK BIT(CAN_TXID0_RTR_POS) + +#define CAN_TXID0_TXMREQ_POS 0U +#define CAN_TXID0_TXMREQ_MSK BIT(CAN_TXID0_TXMREQ_POS) + +/****************** Bit definition for CAN_TXFCON0 register ************************/ + +#define CAN_TXFCON0_STAMP_POSS 16U +#define CAN_TXFCON0_STAMP_POSE 31U +#define CAN_TXFCON0_STAMP_MSK BITS(CAN_TXFCON0_STAMP_POSS,CAN_TXFCON0_STAMP_POSE) + +#define CAN_TXFCON0_TXGT_POS 8U +#define CAN_TXFCON0_TXGT_MSK BIT(CAN_TXFCON0_TXGT_POS) + +#define CAN_TXFCON0_DLEN_POSS 0U +#define CAN_TXFCON0_DLEN_POSE 3U +#define CAN_TXFCON0_DLEN_MSK BITS(CAN_TXFCON0_DLEN_POSS,CAN_TXFCON0_DLEN_POSE) + +/****************** Bit definition for CAN_TXDL0 register ************************/ + +#define CAN_TXDL0_BYTE3_POSS 24U +#define CAN_TXDL0_BYTE3_POSE 31U +#define CAN_TXDL0_BYTE3_MSK BITS(CAN_TXDL0_BYTE3_POSS,CAN_TXDL0_BYTE3_POSE) + +#define CAN_TXDL0_BYTE2_POSS 16U +#define CAN_TXDL0_BYTE2_POSE 23U +#define CAN_TXDL0_BYTE2_MSK BITS(CAN_TXDL0_BYTE2_POSS,CAN_TXDL0_BYTE2_POSE) + +#define CAN_TXDL0_BYTE1_POSS 8U +#define CAN_TXDL0_BYTE1_POSE 15U +#define CAN_TXDL0_BYTE1_MSK BITS(CAN_TXDL0_BYTE1_POSS,CAN_TXDL0_BYTE1_POSE) + +#define CAN_TXDL0_BYTE0_POSS 0U +#define CAN_TXDL0_BYTE0_POSE 7U +#define CAN_TXDL0_BYTE0_MSK BITS(CAN_TXDL0_BYTE0_POSS,CAN_TXDL0_BYTE0_POSE) + +/****************** Bit definition for CAN_TXDH0 register ************************/ + +#define CAN_TXDH0_BYTE7_POSS 24U +#define CAN_TXDH0_BYTE7_POSE 31U +#define CAN_TXDH0_BYTE7_MSK BITS(CAN_TXDH0_BYTE7_POSS,CAN_TXDH0_BYTE7_POSE) + +#define CAN_TXDH0_BYTE6_POSS 16U +#define CAN_TXDH0_BYTE6_POSE 23U +#define CAN_TXDH0_BYTE6_MSK BITS(CAN_TXDH0_BYTE6_POSS,CAN_TXDH0_BYTE6_POSE) + +#define CAN_TXDH0_BYTE5_POSS 8U +#define CAN_TXDH0_BYTE5_POSE 15U +#define CAN_TXDH0_BYTE5_MSK BITS(CAN_TXDH0_BYTE5_POSS,CAN_TXDH0_BYTE5_POSE) + +#define CAN_TXDH0_BYTE4_POSS 0U +#define CAN_TXDH0_BYTE4_POSE 7U +#define CAN_TXDH0_BYTE4_MSK BITS(CAN_TXDH0_BYTE4_POSS,CAN_TXDH0_BYTE4_POSE) + +/****************** Bit definition for CAN_TXID1 register ************************/ + +#define CAN_TXID1_STDID_POSS 21U +#define CAN_TXID1_STDID_POSE 31U +#define CAN_TXID1_STDID_MSK BITS(CAN_TXID1_STDID_POSS,CAN_TXID1_STDID_POSE) + +#define CAN_TXID1_EXID_POSS 3U +#define CAN_TXID1_EXID_POSE 20U +#define CAN_TXID1_EXID_MSK BITS(CAN_TXID1_EXID_POSS,CAN_TXID1_EXID_POSE) + +#define CAN_TXID1_IDE_POS 2U +#define CAN_TXID1_IDE_MSK BIT(CAN_TXID1_IDE_POS) + +#define CAN_TXID1_RTR_POS 1U +#define CAN_TXID1_RTR_MSK BIT(CAN_TXID1_RTR_POS) + +#define CAN_TXID1_TXMREQ_POS 0U +#define CAN_TXID1_TXMREQ_MSK BIT(CAN_TXID1_TXMREQ_POS) + +/****************** Bit definition for CAN_TXFCON1 register ************************/ + +#define CAN_TXFCON1_STAMP_POSS 16U +#define CAN_TXFCON1_STAMP_POSE 31U +#define CAN_TXFCON1_STAMP_MSK BITS(CAN_TXFCON1_STAMP_POSS,CAN_TXFCON1_STAMP_POSE) + +#define CAN_TXFCON1_TXGT_POS 8U +#define CAN_TXFCON1_TXGT_MSK BIT(CAN_TXFCON1_TXGT_POS) + +#define CAN_TXFCON1_DLEN_POSS 0U +#define CAN_TXFCON1_DLEN_POSE 3U +#define CAN_TXFCON1_DLEN_MSK BITS(CAN_TXFCON1_DLEN_POSS,CAN_TXFCON1_DLEN_POSE) + +/****************** Bit definition for CAN_TXDL1 register ************************/ + +#define CAN_TXDL1_BYTE3_POSS 24U +#define CAN_TXDL1_BYTE3_POSE 31U +#define CAN_TXDL1_BYTE3_MSK BITS(CAN_TXDL1_BYTE3_POSS,CAN_TXDL1_BYTE3_POSE) + +#define CAN_TXDL1_BYTE2_POSS 16U +#define CAN_TXDL1_BYTE2_POSE 23U +#define CAN_TXDL1_BYTE2_MSK BITS(CAN_TXDL1_BYTE2_POSS,CAN_TXDL1_BYTE2_POSE) + +#define CAN_TXDL1_BYTE1_POSS 8U +#define CAN_TXDL1_BYTE1_POSE 15U +#define CAN_TXDL1_BYTE1_MSK BITS(CAN_TXDL1_BYTE1_POSS,CAN_TXDL1_BYTE1_POSE) + +#define CAN_TXDL1_BYTE0_POSS 0U +#define CAN_TXDL1_BYTE0_POSE 7U +#define CAN_TXDL1_BYTE0_MSK BITS(CAN_TXDL1_BYTE0_POSS,CAN_TXDL1_BYTE0_POSE) + +/****************** Bit definition for CAN_TXDH1 register ************************/ + +#define CAN_TXDH1_BYTE7_POSS 24U +#define CAN_TXDH1_BYTE7_POSE 31U +#define CAN_TXDH1_BYTE7_MSK BITS(CAN_TXDH1_BYTE7_POSS,CAN_TXDH1_BYTE7_POSE) + +#define CAN_TXDH1_BYTE6_POSS 16U +#define CAN_TXDH1_BYTE6_POSE 23U +#define CAN_TXDH1_BYTE6_MSK BITS(CAN_TXDH1_BYTE6_POSS,CAN_TXDH1_BYTE6_POSE) + +#define CAN_TXDH1_BYTE5_POSS 8U +#define CAN_TXDH1_BYTE5_POSE 15U +#define CAN_TXDH1_BYTE5_MSK BITS(CAN_TXDH1_BYTE5_POSS,CAN_TXDH1_BYTE5_POSE) + +#define CAN_TXDH1_BYTE4_POSS 0U +#define CAN_TXDH1_BYTE4_POSE 7U +#define CAN_TXDH1_BYTE4_MSK BITS(CAN_TXDH1_BYTE4_POSS,CAN_TXDH1_BYTE4_POSE) + +/****************** Bit definition for CAN_TXID2 register ************************/ + +#define CAN_TXID2_STDID_POSS 21U +#define CAN_TXID2_STDID_POSE 31U +#define CAN_TXID2_STDID_MSK BITS(CAN_TXID2_STDID_POSS,CAN_TXID2_STDID_POSE) + +#define CAN_TXID2_EXID_POSS 3U +#define CAN_TXID2_EXID_POSE 20U +#define CAN_TXID2_EXID_MSK BITS(CAN_TXID2_EXID_POSS,CAN_TXID2_EXID_POSE) + +#define CAN_TXID2_IDE_POS 2U +#define CAN_TXID2_IDE_MSK BIT(CAN_TXID2_IDE_POS) + +#define CAN_TXID2_RTR_POS 1U +#define CAN_TXID2_RTR_MSK BIT(CAN_TXID2_RTR_POS) + +#define CAN_TXID2_TXMREQ_POS 0U +#define CAN_TXID2_TXMREQ_MSK BIT(CAN_TXID2_TXMREQ_POS) + +/****************** Bit definition for CAN_TXFCON2 register ************************/ + +#define CAN_TXFCON2_STAMP_POSS 16U +#define CAN_TXFCON2_STAMP_POSE 31U +#define CAN_TXFCON2_STAMP_MSK BITS(CAN_TXFCON2_STAMP_POSS,CAN_TXFCON2_STAMP_POSE) + +#define CAN_TXFCON2_TXGT_POS 8U +#define CAN_TXFCON2_TXGT_MSK BIT(CAN_TXFCON2_TXGT_POS) + +#define CAN_TXFCON2_DLEN_POSS 0U +#define CAN_TXFCON2_DLEN_POSE 3U +#define CAN_TXFCON2_DLEN_MSK BITS(CAN_TXFCON2_DLEN_POSS,CAN_TXFCON2_DLEN_POSE) + +/****************** Bit definition for CAN_TXDL2 register ************************/ + +#define CAN_TXDL2_BYTE3_POSS 24U +#define CAN_TXDL2_BYTE3_POSE 31U +#define CAN_TXDL2_BYTE3_MSK BITS(CAN_TXDL2_BYTE3_POSS,CAN_TXDL2_BYTE3_POSE) + +#define CAN_TXDL2_BYTE2_POSS 16U +#define CAN_TXDL2_BYTE2_POSE 23U +#define CAN_TXDL2_BYTE2_MSK BITS(CAN_TXDL2_BYTE2_POSS,CAN_TXDL2_BYTE2_POSE) + +#define CAN_TXDL2_BYTE1_POSS 8U +#define CAN_TXDL2_BYTE1_POSE 15U +#define CAN_TXDL2_BYTE1_MSK BITS(CAN_TXDL2_BYTE1_POSS,CAN_TXDL2_BYTE1_POSE) + +#define CAN_TXDL2_BYTE0_POSS 0U +#define CAN_TXDL2_BYTE0_POSE 7U +#define CAN_TXDL2_BYTE0_MSK BITS(CAN_TXDL2_BYTE0_POSS,CAN_TXDL2_BYTE0_POSE) + +/****************** Bit definition for CAN_TXDH2 register ************************/ + +#define CAN_TXDH2_BYTE7_POSS 24U +#define CAN_TXDH2_BYTE7_POSE 31U +#define CAN_TXDH2_BYTE7_MSK BITS(CAN_TXDH2_BYTE7_POSS,CAN_TXDH2_BYTE7_POSE) + +#define CAN_TXDH2_BYTE6_POSS 16U +#define CAN_TXDH2_BYTE6_POSE 23U +#define CAN_TXDH2_BYTE6_MSK BITS(CAN_TXDH2_BYTE6_POSS,CAN_TXDH2_BYTE6_POSE) + +#define CAN_TXDH2_BYTE5_POSS 8U +#define CAN_TXDH2_BYTE5_POSE 15U +#define CAN_TXDH2_BYTE5_MSK BITS(CAN_TXDH2_BYTE5_POSS,CAN_TXDH2_BYTE5_POSE) + +#define CAN_TXDH2_BYTE4_POSS 0U +#define CAN_TXDH2_BYTE4_POSE 7U +#define CAN_TXDH2_BYTE4_MSK BITS(CAN_TXDH2_BYTE4_POSS,CAN_TXDH2_BYTE4_POSE) + +/****************** Bit definition for CAN_RXF0ID register ************************/ + +#define CAN_RXF0ID_STDID_POSS 21U +#define CAN_RXF0ID_STDID_POSE 31U +#define CAN_RXF0ID_STDID_MSK BITS(CAN_RXF0ID_STDID_POSS,CAN_RXF0ID_STDID_POSE) + +#define CAN_RXF0ID_EXID_POSS 3U +#define CAN_RXF0ID_EXID_POSE 20U +#define CAN_RXF0ID_EXID_MSK BITS(CAN_RXF0ID_EXID_POSS,CAN_RXF0ID_EXID_POSE) + +#define CAN_RXF0ID_IDE_POS 2U +#define CAN_RXF0ID_IDE_MSK BIT(CAN_RXF0ID_IDE_POS) + +#define CAN_RXF0ID_RTR_POS 1U +#define CAN_RXF0ID_RTR_MSK BIT(CAN_RXF0ID_RTR_POS) + +/****************** Bit definition for CAN_RXF0INF register ************************/ + +#define CAN_RXF0INF_STAMP_POSS 16U +#define CAN_RXF0INF_STAMP_POSE 31U +#define CAN_RXF0INF_STAMP_MSK BITS(CAN_RXF0INF_STAMP_POSS,CAN_RXF0INF_STAMP_POSE) + +#define CAN_RXF0INF_FLTIDX_POSS 8U +#define CAN_RXF0INF_FLTIDX_POSE 15U +#define CAN_RXF0INF_FLTIDX_MSK BITS(CAN_RXF0INF_FLTIDX_POSS,CAN_RXF0INF_FLTIDX_POSE) + +#define CAN_RXF0INF_DLEN_POSS 0U +#define CAN_RXF0INF_DLEN_POSE 3U +#define CAN_RXF0INF_DLEN_MSK BITS(CAN_RXF0INF_DLEN_POSS,CAN_RXF0INF_DLEN_POSE) + +/****************** Bit definition for CAN_RXF0DL register ************************/ + +#define CAN_RXF0DL_BYTE3_POSS 24U +#define CAN_RXF0DL_BYTE3_POSE 31U +#define CAN_RXF0DL_BYTE3_MSK BITS(CAN_RXF0DL_BYTE3_POSS,CAN_RXF0DL_BYTE3_POSE) + +#define CAN_RXF0DL_BYTE2_POSS 16U +#define CAN_RXF0DL_BYTE2_POSE 23U +#define CAN_RXF0DL_BYTE2_MSK BITS(CAN_RXF0DL_BYTE2_POSS,CAN_RXF0DL_BYTE2_POSE) + +#define CAN_RXF0DL_BYTE1_POSS 8U +#define CAN_RXF0DL_BYTE1_POSE 15U +#define CAN_RXF0DL_BYTE1_MSK BITS(CAN_RXF0DL_BYTE1_POSS,CAN_RXF0DL_BYTE1_POSE) + +#define CAN_RXF0DL_BYTE0_POSS 0U +#define CAN_RXF0DL_BYTE0_POSE 7U +#define CAN_RXF0DL_BYTE0_MSK BITS(CAN_RXF0DL_BYTE0_POSS,CAN_RXF0DL_BYTE0_POSE) + +/****************** Bit definition for CAN_RXF0DH register ************************/ + +#define CAN_RXF0DH_BYTE7_POSS 24U +#define CAN_RXF0DH_BYTE7_POSE 31U +#define CAN_RXF0DH_BYTE7_MSK BITS(CAN_RXF0DH_BYTE7_POSS,CAN_RXF0DH_BYTE7_POSE) + +#define CAN_RXF0DH_BYTE6_POSS 16U +#define CAN_RXF0DH_BYTE6_POSE 23U +#define CAN_RXF0DH_BYTE6_MSK BITS(CAN_RXF0DH_BYTE6_POSS,CAN_RXF0DH_BYTE6_POSE) + +#define CAN_RXF0DH_BYTE5_POSS 8U +#define CAN_RXF0DH_BYTE5_POSE 15U +#define CAN_RXF0DH_BYTE5_MSK BITS(CAN_RXF0DH_BYTE5_POSS,CAN_RXF0DH_BYTE5_POSE) + +#define CAN_RXF0DH_BYTE4_POSS 0U +#define CAN_RXF0DH_BYTE4_POSE 7U +#define CAN_RXF0DH_BYTE4_MSK BITS(CAN_RXF0DH_BYTE4_POSS,CAN_RXF0DH_BYTE4_POSE) + +/****************** Bit definition for CAN_RXF1ID register ************************/ + +#define CAN_RXF1ID_STDID_POSS 21U +#define CAN_RXF1ID_STDID_POSE 31U +#define CAN_RXF1ID_STDID_MSK BITS(CAN_RXF1ID_STDID_POSS,CAN_RXF1ID_STDID_POSE) + +#define CAN_RXF1ID_EXID_POSS 3U +#define CAN_RXF1ID_EXID_POSE 20U +#define CAN_RXF1ID_EXID_MSK BITS(CAN_RXF1ID_EXID_POSS,CAN_RXF1ID_EXID_POSE) + +#define CAN_RXF1ID_IDE_POS 2U +#define CAN_RXF1ID_IDE_MSK BIT(CAN_RXF1ID_IDE_POS) + +#define CAN_RXF1ID_RTR_POS 1U +#define CAN_RXF1ID_RTR_MSK BIT(CAN_RXF1ID_RTR_POS) + +/****************** Bit definition for CAN_RXF1INF register ************************/ + +#define CAN_RXF1INF_STAMP_POSS 16U +#define CAN_RXF1INF_STAMP_POSE 31U +#define CAN_RXF1INF_STAMP_MSK BITS(CAN_RXF1INF_STAMP_POSS,CAN_RXF1INF_STAMP_POSE) + +#define CAN_RXF1INF_FLTIDX_POSS 8U +#define CAN_RXF1INF_FLTIDX_POSE 15U +#define CAN_RXF1INF_FLTIDX_MSK BITS(CAN_RXF1INF_FLTIDX_POSS,CAN_RXF1INF_FLTIDX_POSE) + +#define CAN_RXF1INF_DLEN_POSS 0U +#define CAN_RXF1INF_DLEN_POSE 3U +#define CAN_RXF1INF_DLEN_MSK BITS(CAN_RXF1INF_DLEN_POSS,CAN_RXF1INF_DLEN_POSE) + +/****************** Bit definition for CAN_RXF1DL register ************************/ + +#define CAN_RXF1DL_BYTE3_POSS 24U +#define CAN_RXF1DL_BYTE3_POSE 31U +#define CAN_RXF1DL_BYTE3_MSK BITS(CAN_RXF1DL_BYTE3_POSS,CAN_RXF1DL_BYTE3_POSE) + +#define CAN_RXF1DL_BYTE2_POSS 16U +#define CAN_RXF1DL_BYTE2_POSE 23U +#define CAN_RXF1DL_BYTE2_MSK BITS(CAN_RXF1DL_BYTE2_POSS,CAN_RXF1DL_BYTE2_POSE) + +#define CAN_RXF1DL_BYTE1_POSS 8U +#define CAN_RXF1DL_BYTE1_POSE 15U +#define CAN_RXF1DL_BYTE1_MSK BITS(CAN_RXF1DL_BYTE1_POSS,CAN_RXF1DL_BYTE1_POSE) + +#define CAN_RXF1DL_BYTE0_POSS 0U +#define CAN_RXF1DL_BYTE0_POSE 7U +#define CAN_RXF1DL_BYTE0_MSK BITS(CAN_RXF1DL_BYTE0_POSS,CAN_RXF1DL_BYTE0_POSE) + +/****************** Bit definition for CAN_RXF1DH register ************************/ + +#define CAN_RXF1DH_BYTE7_POSS 24U +#define CAN_RXF1DH_BYTE7_POSE 31U +#define CAN_RXF1DH_BYTE7_MSK BITS(CAN_RXF1DH_BYTE7_POSS,CAN_RXF1DH_BYTE7_POSE) + +#define CAN_RXF1DH_BYTE6_POSS 16U +#define CAN_RXF1DH_BYTE6_POSE 23U +#define CAN_RXF1DH_BYTE6_MSK BITS(CAN_RXF1DH_BYTE6_POSS,CAN_RXF1DH_BYTE6_POSE) + +#define CAN_RXF1DH_BYTE5_POSS 8U +#define CAN_RXF1DH_BYTE5_POSE 15U +#define CAN_RXF1DH_BYTE5_MSK BITS(CAN_RXF1DH_BYTE5_POSS,CAN_RXF1DH_BYTE5_POSE) + +#define CAN_RXF1DH_BYTE4_POSS 0U +#define CAN_RXF1DH_BYTE4_POSE 7U +#define CAN_RXF1DH_BYTE4_MSK BITS(CAN_RXF1DH_BYTE4_POSS,CAN_RXF1DH_BYTE4_POSE) + +/****************** Bit definition for CAN_FLTCON register ************************/ + +#define CAN_FLTCON_FLTINI_POS 0U +#define CAN_FLTCON_FLTINI_MSK BIT(CAN_FLTCON_FLTINI_POS) + +/****************** Bit definition for CAN_FLTM register ************************/ + +#define CAN_FLTM_MOD_POSS 0U +#define CAN_FLTM_MOD_POSE 13U +#define CAN_FLTM_MOD_MSK BITS(CAN_FLTM_MOD_POSS,CAN_FLTM_MOD_POSE) + +/****************** Bit definition for CAN_FLTWS register ************************/ + +#define CAN_FLTWS_SEL_POSS 0U +#define CAN_FLTWS_SEL_POSE 13U +#define CAN_FLTWS_SEL_MSK BITS(CAN_FLTWS_SEL_POSS,CAN_FLTWS_SEL_POSE) + +/****************** Bit definition for CAN_FLTAS register ************************/ + +#define CAN_FLTAS_ASSIGN_POSS 0U +#define CAN_FLTAS_ASSIGN_POSE 13U +#define CAN_FLTAS_ASSIGN_MSK BITS(CAN_FLTAS_ASSIGN_POSS,CAN_FLTAS_ASSIGN_POSE) + +/****************** Bit definition for CAN_FLTGO register ************************/ + +#define CAN_FLTGO_GO_POSS 0U +#define CAN_FLTGO_GO_POSE 13U +#define CAN_FLTGO_GO_MSK BITS(CAN_FLTGO_GO_POSS,CAN_FLTGO_GO_POSE) + +typedef struct { + __IO uint32_t TXID; + __IO uint32_t TXFCON; + __IO uint32_t TXDL; + __IO uint32_t TXDH; +} CAN_TxMailBox_Typedef; + +typedef struct { + __IO uint32_t RXFID; + __IO uint32_t RXFINF; + __IO uint32_t RXFDL; + __IO uint32_t RXFDH; +} CAN_RxFIFO_Typedef; + +typedef struct { + __IO uint32_t FLT1; + __IO uint32_t FLT2; +} CAN_Filter_Typedef; + +typedef struct +{ + __IO uint32_t CON; + __I uint32_t STAT; + __O uint32_t IFC; + __IO uint32_t TXSTAT; + __O uint32_t TXSTATC; + __IO uint32_t RXF0; + __O uint32_t RXF0C; + __IO uint32_t RXF1; + __O uint32_t RXF1C; + __IO uint32_t IE; + __IO uint32_t ERRSTAT; + __IO uint32_t BTIME; + uint32_t RESERVED0[84] ; + CAN_TxMailBox_Typedef TxMailBox[3]; + CAN_RxFIFO_Typedef RxFIFO[2]; + uint32_t RESERVED1[12] ; + __IO uint32_t FLTCON; + __IO uint32_t FLTM; + uint32_t RESERVED2 ; + __IO uint32_t FLTWS; + uint32_t RESERVED3 ; + __IO uint32_t FLTAS; + uint32_t RESERVED4 ; + __IO uint32_t FLTGO; + uint32_t RESERVED5[8] ; + CAN_Filter_Typedef Filter[14]; +} CAN_TypeDef; + +/****************** Bit definition for CRC_CR register ************************/ +#define CRC_CR_BYTORD_POS 24U +#define CRC_CR_BYTORD_MSK BIT(CRC_CR_BYTORD_POS) + +#define CRC_CR_DATLEN_POSS 22U +#define CRC_CR_DATLEN_POSE 23U +#define CRC_CR_DATLEN_MSK BITS(CRC_CR_DATLEN_POSS,CRC_CR_DATLEN_POSE) + +#define CRC_CR_MODE_POSS 20U +#define CRC_CR_MODE_POSE 21U +#define CRC_CR_MODE_MSK BITS(CRC_CR_MODE_POSS,CRC_CR_MODE_POSE) + +#define CRC_CR_CHSINV_POS 19U +#define CRC_CR_CHSINV_MSK BIT(CRC_CR_CHSINV_POS) + +#define CRC_CR_DATINV_POS 18U +#define CRC_CR_DATINV_MSK BIT(CRC_CR_DATINV_POS) + +#define CRC_CR_CHSREV_POS 17U +#define CRC_CR_CHSREV_MSK BIT(CRC_CR_CHSREV_POS) + +#define CRC_CR_DATREV_POS 16U +#define CRC_CR_DATREV_MSK BIT(CRC_CR_DATREV_POS) + +#define CRC_CR_DMAEN_POS 4U +#define CRC_CR_DMAEN_MSK BIT(CRC_CR_DMAEN_POS) + +#define CRC_CR_CWERR_POS 3U +#define CRC_CR_CWERR_MSK BIT(CRC_CR_CWERR_POS) + +#define CRC_CR_WERR_POS 2U +#define CRC_CR_WERR_MSK BIT(CRC_CR_WERR_POS) + +#define CRC_CR_RST_POS 1U +#define CRC_CR_RST_MSK BIT(CRC_CR_RST_POS) + +#define CRC_CR_EN_POS 0U +#define CRC_CR_EN_MSK BIT(CRC_CR_EN_POS) + +/****************** Bit definition for CRC_DATA register ************************/ + +#define CRC_DATA_DATA_POSS 0U +#define CRC_DATA_DATA_POSE 31U +#define CRC_DATA_DATA_MSK BITS(CRC_DATA_DATA_POSS,CRC_DATA_DATA_POSE) + +/****************** Bit definition for CRC_SEED register ************************/ + +#define CRC_SEED_SEED_POSS 0U +#define CRC_SEED_SEED_POSE 31U +#define CRC_SEED_SEED_MSK BITS(CRC_SEED_SEED_POSS,CRC_SEED_SEED_POSE) + +/****************** Bit definition for CRC_CHECKSUM register ************************/ + +#define CRC_CHECKSUM_CHECKSUM_POSS 0U +#define CRC_CHECKSUM_CHECKSUM_POSE 31U +#define CRC_CHECKSUM_CHECKSUM_MSK BITS(CRC_CHECKSUM_CHECKSUM_POSS,CRC_CHECKSUM_CHECKSUM_POSE) + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t DATA; + __IO uint32_t SEED; + __I uint32_t CHECKSUM; +} CRC_TypeDef; + +/****************** Bit definition for CRYPT_CON register ************************/ + +#define CRYPT_CON_CRYSEL_POS 31U +#define CRYPT_CON_CRYSEL_MSK BIT(CRYPT_CON_CRYSEL_POS) + +#define CRYPT_CON_RESCLR_POS 15U +#define CRYPT_CON_RESCLR_MSK BIT(CRYPT_CON_RESCLR_POS) + +#define CRYPT_CON_DMAEN_POS 14U +#define CRYPT_CON_DMAEN_MSK BIT(CRYPT_CON_DMAEN_POS) + +#define CRYPT_CON_FIFOODR_POS 13U +#define CRYPT_CON_FIFOODR_MSK BIT(CRYPT_CON_FIFOODR_POS) + +#define CRYPT_CON_FIFOEN_POS 12U +#define CRYPT_CON_FIFOEN_MSK BIT(CRYPT_CON_FIFOEN_POS) + +#define CRYPT_CON_DESKS_POS 11U +#define CRYPT_CON_DESKS_MSK BIT(CRYPT_CON_DESKS_POS) + +#define CRYPT_CON_TDES_POS 10U +#define CRYPT_CON_TDES_MSK BIT(CRYPT_CON_TDES_POS) + +#define CRYPT_CON_TYPE_POSS 8U +#define CRYPT_CON_TYPE_POSE 9U +#define CRYPT_CON_TYPE_MSK BITS(CRYPT_CON_TYPE_POSS,CRYPT_CON_TYPE_POSE) + +#define CRYPT_CON_IE_POS 7U +#define CRYPT_CON_IE_MSK BIT(CRYPT_CON_IE_POS) + +#define CRYPT_CON_IVEN_POS 6U +#define CRYPT_CON_IVEN_MSK BIT(CRYPT_CON_IVEN_POS) + +#define CRYPT_CON_MODE_POSS 4U +#define CRYPT_CON_MODE_POSE 5U +#define CRYPT_CON_MODE_MSK BITS(CRYPT_CON_MODE_POSS,CRYPT_CON_MODE_POSE) + +#define CRYPT_CON_AESKS_POSS 2U +#define CRYPT_CON_AESKS_POSE 3U +#define CRYPT_CON_AESKS_MSK BITS(CRYPT_CON_AESKS_POSS,CRYPT_CON_AESKS_POSE) + +#define CRYPT_CON_ENCS_POS 1U +#define CRYPT_CON_ENCS_MSK BIT(CRYPT_CON_ENCS_POS) + +#define CRYPT_CON_GO_POS 0U +#define CRYPT_CON_GO_MSK BIT(CRYPT_CON_GO_POS) + +/****************** Bit definition for CRYPT_IF register ************************/ + +#define CRYPT_IF_DONE_POS 8U +#define CRYPT_IF_DONE_MSK BIT(CRYPT_IF_DONE_POS) + +#define CRYPT_IF_MULTHIF_POS 2U +#define CRYPT_IF_MULTHIF_MSK BIT(CRYPT_IF_MULTHIF_POS) + +#define CRYPT_IF_DESIF_POS 1U +#define CRYPT_IF_DESIF_MSK BIT(CRYPT_IF_DESIF_POS) + +#define CRYPT_IF_AESIF_POS 0U +#define CRYPT_IF_AESIF_MSK BIT(CRYPT_IF_AESIF_POS) + +/****************** Bit definition for CRYPT_IFC register ************************/ + +#define CRYPT_IFC_MULTHIFC_POS 2U +#define CRYPT_IFC_MULTHIFC_MSK BIT(CRYPT_IFC_MULTHIFC_POS) + +#define CRYPT_IFC_DESIFC_POS 1U +#define CRYPT_IFC_DESIFC_MSK BIT(CRYPT_IFC_DESIFC_POS) + +#define CRYPT_IFC_AESIFC_POS 0U +#define CRYPT_IFC_AESIFC_MSK BIT(CRYPT_IFC_AESIFC_POS) + +/****************** Bit definition for CRYPT_FIFO register ************************/ + +#define CRYPT_FIFO_FIFO_POSS 0U +#define CRYPT_FIFO_FIFO_POSE 31U +#define CRYPT_FIFO_FIFO_MSK BITS(CRYPT_FIFO_FIFO_POSS,CRYPT_FIFO_FIFO_POSE) + +typedef struct +{ + __IO uint32_t DATA[4]; + __IO uint32_t KEY[8]; + __IO uint32_t IV[4]; + __I uint32_t RES[4]; + __IO uint32_t CON; + __I uint32_t IF; + __O uint32_t IFC; + __IO uint32_t FIFO; +} CRYPT_TypeDef; + +/****************** Bit definition for LCD_CR register ************************/ + +#define LCD_CR_VCHPS_POSS 24U +#define LCD_CR_VCHPS_POSE 25U +#define LCD_CR_VCHPS_MSK BITS(LCD_CR_VCHPS_POSS,LCD_CR_VCHPS_POSE) + +#define LCD_CR_DSLD_POSS 20U +#define LCD_CR_DSLD_POSE 23U +#define LCD_CR_DSLD_MSK BITS(LCD_CR_DSLD_POSS,LCD_CR_DSLD_POSE) + +#define LCD_CR_DSHD_POSS 16U +#define LCD_CR_DSHD_POSE 19U +#define LCD_CR_DSHD_MSK BITS(LCD_CR_DSHD_POSS,LCD_CR_DSHD_POSE) + +#define LCD_CR_VBUFLD_POS 15U +#define LCD_CR_VBUFLD_MSK BIT(LCD_CR_VBUFLD_POS) + +#define LCD_CR_VBUFHD_POS 14U +#define LCD_CR_VBUFHD_MSK BIT(LCD_CR_VBUFHD_POS) + +#define LCD_CR_RESLD_POSS 12U +#define LCD_CR_RESLD_POSE 13U +#define LCD_CR_RESLD_MSK BITS(LCD_CR_RESLD_POSS,LCD_CR_RESLD_POSE) + +#define LCD_CR_RESHD_POSS 10U +#define LCD_CR_RESHD_POSE 11U +#define LCD_CR_RESHD_MSK BITS(LCD_CR_RESHD_POSS,LCD_CR_RESHD_POSE) + +#define LCD_CR_BIAS_POSS 8U +#define LCD_CR_BIAS_POSE 9U +#define LCD_CR_BIAS_MSK BITS(LCD_CR_BIAS_POSS,LCD_CR_BIAS_POSE) + +#define LCD_CR_DUTY_POSS 4U +#define LCD_CR_DUTY_POSE 6U +#define LCD_CR_DUTY_MSK BITS(LCD_CR_DUTY_POSS,LCD_CR_DUTY_POSE) + +#define LCD_CR_OE_POS 3U +#define LCD_CR_OE_MSK BIT(LCD_CR_OE_POS) + +#define LCD_CR_VSEL_POSS 1U +#define LCD_CR_VSEL_POSE 2U +#define LCD_CR_VSEL_MSK BITS(LCD_CR_VSEL_POSS,LCD_CR_VSEL_POSE) + +#define LCD_CR_EN_POS 0U +#define LCD_CR_EN_MSK BIT(LCD_CR_EN_POS) + +/****************** Bit definition for LCD_FCR register ************************/ + +#define LCD_FCR_WFS_POS 31U +#define LCD_FCR_WFS_MSK BIT(LCD_FCR_WFS_POS) + +#define LCD_FCR_PRS_POSS 24U +#define LCD_FCR_PRS_POSE 27U +#define LCD_FCR_PRS_MSK BITS(LCD_FCR_PRS_POSS,LCD_FCR_PRS_POSE) + +#define LCD_FCR_DIV_POSS 20U +#define LCD_FCR_DIV_POSE 23U +#define LCD_FCR_DIV_MSK BITS(LCD_FCR_DIV_POSS,LCD_FCR_DIV_POSE) + +#define LCD_FCR_BLMOD_POSS 16U +#define LCD_FCR_BLMOD_POSE 17U +#define LCD_FCR_BLMOD_MSK BITS(LCD_FCR_BLMOD_POSS,LCD_FCR_BLMOD_POSE) + +#define LCD_FCR_BLFRQ_POSS 12U +#define LCD_FCR_BLFRQ_POSE 14U +#define LCD_FCR_BLFRQ_MSK BITS(LCD_FCR_BLFRQ_POSS,LCD_FCR_BLFRQ_POSE) + +#define LCD_FCR_DEAD_POSS 8U +#define LCD_FCR_DEAD_POSE 10U +#define LCD_FCR_DEAD_MSK BITS(LCD_FCR_DEAD_POSS,LCD_FCR_DEAD_POSE) + +#define LCD_FCR_HD_POS 7U +#define LCD_FCR_HD_MSK BIT(LCD_FCR_HD_POS) + +#define LCD_FCR_PON_POSS 4U +#define LCD_FCR_PON_POSE 6U +#define LCD_FCR_PON_MSK BITS(LCD_FCR_PON_POSS,LCD_FCR_PON_POSE) + +#define LCD_FCR_VGS_POSS 0U +#define LCD_FCR_VGS_POSE 3U +#define LCD_FCR_VGS_MSK BITS(LCD_FCR_VGS_POSS,LCD_FCR_VGS_POSE) + +/****************** Bit definition for LCD_SEGCR0 register ************************/ + +#define LCD_SEGCR0_SEG_OE_POSS 0U +#define LCD_SEGCR0_SEG_OE_POSE 31U +#define LCD_SEGCR0_SEG_OE_MSK BITS(LCD_SEGCR0_SEG_OE_POSS,LCD_SEGCR0_SEG_OE_POSE) + +/****************** Bit definition for LCD_SEGCR1 register ************************/ + +#define LCD_SEGCR1_SEG_OE_POSS 0U +#define LCD_SEGCR1_SEG_OE_POSE 11U +#define LCD_SEGCR1_SEG_OE_MSK BITS(LCD_SEGCR1_SEG_OE_POSS,LCD_SEGCR1_SEG_OE_POSE) + +/****************** Bit definition for LCD_IE register ************************/ + +#define LCD_IE_UDDIE_POS 1U +#define LCD_IE_UDDIE_MSK BIT(LCD_IE_UDDIE_POS) + +#define LCD_IE_SOFIE_POS 0U +#define LCD_IE_SOFIE_MSK BIT(LCD_IE_SOFIE_POS) + +/****************** Bit definition for LCD_IF register ************************/ + +#define LCD_IF_UDDIF_POS 1U +#define LCD_IF_UDDIF_MSK BIT(LCD_IF_UDDIF_POS) + +#define LCD_IF_SOFIF_POS 0U +#define LCD_IF_SOFIF_MSK BIT(LCD_IF_SOFIF_POS) + +/****************** Bit definition for LCD_IFCR register ************************/ + +#define LCD_IFCR_UDDIFC_POS 1U +#define LCD_IFCR_UDDIFC_MSK BIT(LCD_IFCR_UDDIFC_POS) + +#define LCD_IFCR_SOFIFC_POS 0U +#define LCD_IFCR_SOFIFC_MSK BIT(LCD_IFCR_SOFIFC_POS) + +/****************** Bit definition for LCD_SR register ************************/ + +#define LCD_SR_FCRSF_POS 3U +#define LCD_SR_FCRSF_MSK BIT(LCD_SR_FCRSF_POS) + +#define LCD_SR_UDR_POS 2U +#define LCD_SR_UDR_MSK BIT(LCD_SR_UDR_POS) + +#define LCD_SR_ENS_POS 1U +#define LCD_SR_ENS_MSK BIT(LCD_SR_ENS_POS) + +#define LCD_SR_RDY_POS 0U +#define LCD_SR_RDY_MSK BIT(LCD_SR_RDY_POS) + +/****************** Bit definition for LCD_BUF register ************************/ + +#define LCD_BUF_SEG_DATA_POSS 0U +#define LCD_BUF_SEG_DATA_POSE 31U +#define LCD_BUF_SEG_DATA_MSK BITS(LCD_BUF_SEG_DATA_POSS,LCD_BUF_SEG_DATA_POSE) + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t FCR; + __IO uint32_t SEGCR0; + __IO uint32_t SEGCR1; + __IO uint32_t IE; + __I uint32_t IF; + __O uint32_t IFCR; + __I uint32_t SR; + uint32_t RESERVED0[8] ; + __IO uint32_t BUF[16]; +} LCD_TypeDef; + +/****************** Bit definition for ADC_STAT register ************************/ + +#define ADC_STAT_ICHS_POS 9U +#define ADC_STAT_ICHS_MSK BIT(ADC_STAT_ICHS_POS) + +#define ADC_STAT_NCHS_POS 8U +#define ADC_STAT_NCHS_MSK BIT(ADC_STAT_NCHS_POS) + +#define ADC_STAT_OVR_POS 3U +#define ADC_STAT_OVR_MSK BIT(ADC_STAT_OVR_POS) + +#define ADC_STAT_ICHE_POS 2U +#define ADC_STAT_ICHE_MSK BIT(ADC_STAT_ICHE_POS) + +#define ADC_STAT_NCHE_POS 1U +#define ADC_STAT_NCHE_MSK BIT(ADC_STAT_NCHE_POS) + +#define ADC_STAT_AWDF_POS 0U +#define ADC_STAT_AWDF_MSK BIT(ADC_STAT_AWDF_POS) + +/****************** Bit definition for ADC_CLR register ************************/ + +#define ADC_CLR_ICHS_POS 9U +#define ADC_CLR_ICHS_MSK BIT(ADC_CLR_ICHS_POS) + +#define ADC_CLR_NCHS_POS 8U +#define ADC_CLR_NCHS_MSK BIT(ADC_CLR_NCHS_POS) + +#define ADC_CLR_OVR_POS 3U +#define ADC_CLR_OVR_MSK BIT(ADC_CLR_OVR_POS) + +#define ADC_CLR_ICHE_POS 2U +#define ADC_CLR_ICHE_MSK BIT(ADC_CLR_ICHE_POS) + +#define ADC_CLR_NCHE_POS 1U +#define ADC_CLR_NCHE_MSK BIT(ADC_CLR_NCHE_POS) + +#define ADC_CLR_AWDF_POS 0U +#define ADC_CLR_AWDF_MSK BIT(ADC_CLR_AWDF_POS) + +/****************** Bit definition for ADC_CON0 register ************************/ + +#define ADC_CON0_OVRIE_POS 26U +#define ADC_CON0_OVRIE_MSK BIT(ADC_CON0_OVRIE_POS) + +#define ADC_CON0_RSEL_POSS 24U +#define ADC_CON0_RSEL_POSE 25U +#define ADC_CON0_RSEL_MSK BITS(ADC_CON0_RSEL_POSS,ADC_CON0_RSEL_POSE) + +#define ADC_CON0_NCHWDEN_POS 23U +#define ADC_CON0_NCHWDEN_MSK BIT(ADC_CON0_NCHWDEN_POS) + +#define ADC_CON0_ICHWDTEN_POS 22U +#define ADC_CON0_ICHWDTEN_MSK BIT(ADC_CON0_ICHWDTEN_POS) + +#define ADC_CON0_ETRGN_POSS 13U +#define ADC_CON0_ETRGN_POSE 15U +#define ADC_CON0_ETRGN_MSK BITS(ADC_CON0_ETRGN_POSS,ADC_CON0_ETRGN_POSE) + +#define ADC_CON0_ICHDCEN_POS 12U +#define ADC_CON0_ICHDCEN_MSK BIT(ADC_CON0_ICHDCEN_POS) + +#define ADC_CON0_NCHDCEN_POS 11U +#define ADC_CON0_NCHDCEN_MSK BIT(ADC_CON0_NCHDCEN_POS) + +#define ADC_CON0_IAUTO_POS 10U +#define ADC_CON0_IAUTO_MSK BIT(ADC_CON0_IAUTO_POS) + +#define ADC_CON0_AWDSGL_POS 9U +#define ADC_CON0_AWDSGL_MSK BIT(ADC_CON0_AWDSGL_POS) + +#define ADC_CON0_SCANEN_POS 8U +#define ADC_CON0_SCANEN_MSK BIT(ADC_CON0_SCANEN_POS) + +#define ADC_CON0_ICHEIE_POS 7U +#define ADC_CON0_ICHEIE_MSK BIT(ADC_CON0_ICHEIE_POS) + +#define ADC_CON0_AWDIE_POS 6U +#define ADC_CON0_AWDIE_MSK BIT(ADC_CON0_AWDIE_POS) + +#define ADC_CON0_NCHEIE_POS 5U +#define ADC_CON0_NCHEIE_MSK BIT(ADC_CON0_NCHEIE_POS) + +#define ADC_CON0_AWDCH_POSS 0U +#define ADC_CON0_AWDCH_POSE 4U +#define ADC_CON0_AWDCH_MSK BITS(ADC_CON0_AWDCH_POSS,ADC_CON0_AWDCH_POSE) + +/****************** Bit definition for ADC_CON1 register ************************/ + +#define ADC_CON1_NCHTRG_POS 30U +#define ADC_CON1_NCHTRG_MSK BIT(ADC_CON1_NCHTRG_POS) + +#define ADC_CON1_ICHTRG_POS 22U +#define ADC_CON1_ICHTRG_MSK BIT(ADC_CON1_ICHTRG_POS) + +#define ADC_CON1_ALIGN_POS 11U +#define ADC_CON1_ALIGN_MSK BIT(ADC_CON1_ALIGN_POS) + +#define ADC_CON1_NCHESEL_POS 10U +#define ADC_CON1_NCHESEL_MSK BIT(ADC_CON1_NCHESEL_POS) + +#define ADC_CON1_OVRDIS_POS 8U +#define ADC_CON1_OVRDIS_MSK BIT(ADC_CON1_OVRDIS_POS) + +#define ADC_CON1_CM_POS 1U +#define ADC_CON1_CM_MSK BIT(ADC_CON1_CM_POS) + +#define ADC_CON1_ADCEN_POS 0U +#define ADC_CON1_ADCEN_MSK BIT(ADC_CON1_ADCEN_POS) + +/****************** Bit definition for ADC_SMPT1 register ************************/ + +#define ADC_SMPT1_CHT_POSS 0U +#define ADC_SMPT1_CHT_POSE 31U +#define ADC_SMPT1_CHT_MSK BITS(ADC_SMPT1_CHT_POSS,ADC_SMPT1_CHT_POSE) + +/****************** Bit definition for ADC_SMPT2 register ************************/ + +#define ADC_SMPT2_CHT_POSS 0U +#define ADC_SMPT2_CHT_POSE 7U +#define ADC_SMPT2_CHT_MSK BITS(ADC_SMPT2_CHT_POSS,ADC_SMPT2_CHT_POSE) + +/****************** Bit definition for ADC_ICHOFF1 register ************************/ + +#define ADC_ICHOFF1_IOFF_POSS 0U +#define ADC_ICHOFF1_IOFF_POSE 11U +#define ADC_ICHOFF1_IOFF_MSK BITS(ADC_ICHOFF1_IOFF_POSS,ADC_ICHOFF1_IOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF2 register ************************/ + +#define ADC_ICHOFF2_IOFF_POSS 0U +#define ADC_ICHOFF2_IOFF_POSE 11U +#define ADC_ICHOFF2_IOFF_MSK BITS(ADC_ICHOFF2_IOFF_POSS,ADC_ICHOFF2_IOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF3 register ************************/ + +#define ADC_ICHOFF3_IOFF_POSS 0U +#define ADC_ICHOFF3_IOFF_POSE 11U +#define ADC_ICHOFF3_IOFF_MSK BITS(ADC_ICHOFF3_IOFF_POSS,ADC_ICHOFF3_IOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF4 register ************************/ + +#define ADC_ICHOFF4_IOFF_POSS 0U +#define ADC_ICHOFF4_IOFF_POSE 11U +#define ADC_ICHOFF4_IOFF_MSK BITS(ADC_ICHOFF4_IOFF_POSS,ADC_ICHOFF4_IOFF_POSE) + +/****************** Bit definition for ADC_WDTH register ************************/ + +#define ADC_WDTH_HT_POSS 0U +#define ADC_WDTH_HT_POSE 11U +#define ADC_WDTH_HT_MSK BITS(ADC_WDTH_HT_POSS,ADC_WDTH_HT_POSE) + +/****************** Bit definition for ADC_WDTL register ************************/ + +#define ADC_WDTL_LT_POSS 0U +#define ADC_WDTL_LT_POSE 11U +#define ADC_WDTL_LT_MSK BITS(ADC_WDTL_LT_POSS,ADC_WDTL_LT_POSE) + +/****************** Bit definition for ADC_NCHS1 register ************************/ + +#define ADC_NCHS1_NS4_POSS 24U +#define ADC_NCHS1_NS4_POSE 28U +#define ADC_NCHS1_NS4_MSK BITS(ADC_NCHS1_NS4_POSS,ADC_NCHS1_NS4_POSE) + +#define ADC_NCHS1_NS3_POSS 16U +#define ADC_NCHS1_NS3_POSE 20U +#define ADC_NCHS1_NS3_MSK BITS(ADC_NCHS1_NS3_POSS,ADC_NCHS1_NS3_POSE) + +#define ADC_NCHS1_NS2_POSS 8U +#define ADC_NCHS1_NS2_POSE 12U +#define ADC_NCHS1_NS2_MSK BITS(ADC_NCHS1_NS2_POSS,ADC_NCHS1_NS2_POSE) + +#define ADC_NCHS1_NS1_POSS 0U +#define ADC_NCHS1_NS1_POSE 4U +#define ADC_NCHS1_NS1_MSK BITS(ADC_NCHS1_NS1_POSS,ADC_NCHS1_NS1_POSE) + +/****************** Bit definition for ADC_NCHS2 register ************************/ + +#define ADC_NCHS2_NS8_POSS 24U +#define ADC_NCHS2_NS8_POSE 28U +#define ADC_NCHS2_NS8_MSK BITS(ADC_NCHS2_NS8_POSS,ADC_NCHS2_NS8_POSE) + +#define ADC_NCHS2_NS7_POSS 16U +#define ADC_NCHS2_NS7_POSE 20U +#define ADC_NCHS2_NS7_MSK BITS(ADC_NCHS2_NS7_POSS,ADC_NCHS2_NS7_POSE) + +#define ADC_NCHS2_NS6_POSS 8U +#define ADC_NCHS2_NS6_POSE 12U +#define ADC_NCHS2_NS6_MSK BITS(ADC_NCHS2_NS6_POSS,ADC_NCHS2_NS6_POSE) + +#define ADC_NCHS2_NS5_POSS 0U +#define ADC_NCHS2_NS5_POSE 4U +#define ADC_NCHS2_NS5_MSK BITS(ADC_NCHS2_NS5_POSS,ADC_NCHS2_NS5_POSE) + +/****************** Bit definition for ADC_NCHS3 register ************************/ + +#define ADC_NCHS3_NS12_POSS 24U +#define ADC_NCHS3_NS12_POSE 28U +#define ADC_NCHS3_NS12_MSK BITS(ADC_NCHS3_NS12_POSS,ADC_NCHS3_NS12_POSE) + +#define ADC_NCHS3_NS11_POSS 16U +#define ADC_NCHS3_NS11_POSE 20U +#define ADC_NCHS3_NS11_MSK BITS(ADC_NCHS3_NS11_POSS,ADC_NCHS3_NS11_POSE) + +#define ADC_NCHS3_NS10_POSS 8U +#define ADC_NCHS3_NS10_POSE 12U +#define ADC_NCHS3_NS10_MSK BITS(ADC_NCHS3_NS10_POSS,ADC_NCHS3_NS10_POSE) + +#define ADC_NCHS3_NS9_POSS 0U +#define ADC_NCHS3_NS9_POSE 4U +#define ADC_NCHS3_NS9_MSK BITS(ADC_NCHS3_NS9_POSS,ADC_NCHS3_NS9_POSE) + +/****************** Bit definition for ADC_NCHS4 register ************************/ + +#define ADC_NCHS4_NS16_POSS 24U +#define ADC_NCHS4_NS16_POSE 28U +#define ADC_NCHS4_NS16_MSK BITS(ADC_NCHS4_NS16_POSS,ADC_NCHS4_NS16_POSE) + +#define ADC_NCHS4_NS15_POSS 16U +#define ADC_NCHS4_NS15_POSE 20U +#define ADC_NCHS4_NS15_MSK BITS(ADC_NCHS4_NS15_POSS,ADC_NCHS4_NS15_POSE) + +#define ADC_NCHS4_NS14_POSS 8U +#define ADC_NCHS4_NS14_POSE 12U +#define ADC_NCHS4_NS14_MSK BITS(ADC_NCHS4_NS14_POSS,ADC_NCHS4_NS14_POSE) + +#define ADC_NCHS4_NS13_POSS 0U +#define ADC_NCHS4_NS13_POSE 4U +#define ADC_NCHS4_NS13_MSK BITS(ADC_NCHS4_NS13_POSS,ADC_NCHS4_NS13_POSE) + +/****************** Bit definition for ADC_ICHS register ************************/ + +#define ADC_ICHS_IS4_POSS 24U +#define ADC_ICHS_IS4_POSE 28U +#define ADC_ICHS_IS4_MSK BITS(ADC_ICHS_IS4_POSS,ADC_ICHS_IS4_POSE) + +#define ADC_ICHS_IS3_POSS 16U +#define ADC_ICHS_IS3_POSE 20U +#define ADC_ICHS_IS3_MSK BITS(ADC_ICHS_IS3_POSS,ADC_ICHS_IS3_POSE) + +#define ADC_ICHS_IS2_POSS 8U +#define ADC_ICHS_IS2_POSE 12U +#define ADC_ICHS_IS2_MSK BITS(ADC_ICHS_IS2_POSS,ADC_ICHS_IS2_POSE) + +#define ADC_ICHS_IS1_POSS 0U +#define ADC_ICHS_IS1_POSE 4U +#define ADC_ICHS_IS1_MSK BITS(ADC_ICHS_IS1_POSS,ADC_ICHS_IS1_POSE) + +/****************** Bit definition for ADC_CHSL register ************************/ + +#define ADC_CHSL_ISL_POSS 8U +#define ADC_CHSL_ISL_POSE 9U +#define ADC_CHSL_ISL_MSK BITS(ADC_CHSL_ISL_POSS,ADC_CHSL_ISL_POSE) + +#define ADC_CHSL_NSL_POSS 0U +#define ADC_CHSL_NSL_POSE 3U +#define ADC_CHSL_NSL_MSK BITS(ADC_CHSL_NSL_POSS,ADC_CHSL_NSL_POSE) + +/****************** Bit definition for ADC_ICHDR1 register ************************/ + +#define ADC_ICHDR1_VAL_POSS 0U +#define ADC_ICHDR1_VAL_POSE 15U +#define ADC_ICHDR1_VAL_MSK BITS(ADC_ICHDR1_VAL_POSS,ADC_ICHDR1_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR2 register ************************/ + +#define ADC_ICHDR2_VAL_POSS 0U +#define ADC_ICHDR2_VAL_POSE 15U +#define ADC_ICHDR2_VAL_MSK BITS(ADC_ICHDR2_VAL_POSS,ADC_ICHDR2_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR3 register ************************/ + +#define ADC_ICHDR3_VAL_POSS 0U +#define ADC_ICHDR3_VAL_POSE 15U +#define ADC_ICHDR3_VAL_MSK BITS(ADC_ICHDR3_VAL_POSS,ADC_ICHDR3_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR4 register ************************/ + +#define ADC_ICHDR4_VAL_POSS 0U +#define ADC_ICHDR4_VAL_POSE 15U +#define ADC_ICHDR4_VAL_MSK BITS(ADC_ICHDR4_VAL_POSS,ADC_ICHDR4_VAL_POSE) + +/****************** Bit definition for ADC_NCHDR register ************************/ + +#define ADC_NCHDR_VAL_POSS 0U +#define ADC_NCHDR_VAL_POSE 15U +#define ADC_NCHDR_VAL_MSK BITS(ADC_NCHDR_VAL_POSS,ADC_NCHDR_VAL_POSE) + +/****************** Bit definition for ADC_CCR register ************************/ + +#define ADC_CCR_TRMEN_POS 28U +#define ADC_CCR_TRMEN_MSK BIT(ADC_CCR_TRMEN_POS) + +#define ADC_CCR_GAINCALEN_POS 25U +#define ADC_CCR_GAINCALEN_MSK BIT(ADC_CCR_GAINCALEN_POS) + +#define ADC_CCR_OFFCALEN_POS 24U +#define ADC_CCR_OFFCALEN_MSK BIT(ADC_CCR_OFFCALEN_POS) + +#define ADC_CCR_VREFOEN_POS 19U +#define ADC_CCR_VREFOEN_MSK BIT(ADC_CCR_VREFOEN_POS) + +#define ADC_CCR_VRNSEL_POS 18U +#define ADC_CCR_VRNSEL_MSK BIT(ADC_CCR_VRNSEL_POS) + +#define ADC_CCR_VRPSEL_POSS 16U +#define ADC_CCR_VRPSEL_POSE 17U +#define ADC_CCR_VRPSEL_MSK BITS(ADC_CCR_VRPSEL_POSS,ADC_CCR_VRPSEL_POSE) + +#define ADC_CCR_PWRMODSEL_POS 15U +#define ADC_CCR_PWRMODSEL_MSK BIT(ADC_CCR_PWRMODSEL_POS) + +#define ADC_CCR_DIFFEN_POS 12U +#define ADC_CCR_DIFFEN_MSK BIT(ADC_CCR_DIFFEN_POS) + +#define ADC_CCR_IREFEN_POS 11U +#define ADC_CCR_IREFEN_MSK BIT(ADC_CCR_IREFEN_POS) + +#define ADC_CCR_VRBUFEN_POS 10U +#define ADC_CCR_VRBUFEN_MSK BIT(ADC_CCR_VRBUFEN_POS) + +#define ADC_CCR_VCMBUFEN_POS 9U +#define ADC_CCR_VCMBUFEN_MSK BIT(ADC_CCR_VCMBUFEN_POS) + +#define ADC_CCR_VREFEN_POS 8U +#define ADC_CCR_VREFEN_MSK BIT(ADC_CCR_VREFEN_POS) + +#define ADC_CCR_CKDIV_POSS 0U +#define ADC_CCR_CKDIV_POSE 2U +#define ADC_CCR_CKDIV_MSK BITS(ADC_CCR_CKDIV_POSS,ADC_CCR_CKDIV_POSE) + +typedef struct +{ + __I uint32_t STAT; + __O uint32_t CLR; + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t SMPT1; + __IO uint32_t SMPT2; + __IO uint32_t ICHOFF[4]; + __IO uint32_t WDTH; + __IO uint32_t WDTL; + __IO uint32_t NCHS1; + __IO uint32_t NCHS2; + __IO uint32_t NCHS3; + __IO uint32_t NCHS4; + __IO uint32_t ICHS; + __IO uint32_t CHSL; + __I uint32_t ICHDR[4]; + __I uint32_t NCHDR; + __IO uint32_t CCR; +} ADC_TypeDef; + +/****************** Bit definition for ACMP_CON register ************************/ + +#define ACMP_CON_FALLEN_POS 17U +#define ACMP_CON_FALLEN_MSK BIT(ACMP_CON_FALLEN_POS) + +#define ACMP_CON_RISEEN_POS 16U +#define ACMP_CON_RISEEN_MSK BIT(ACMP_CON_RISEEN_POS) + +#define ACMP_CON_MODSEL_POSS 14U +#define ACMP_CON_MODSEL_POSE 15U +#define ACMP_CON_MODSEL_MSK BITS(ACMP_CON_MODSEL_POSS,ACMP_CON_MODSEL_POSE) + +#define ACMP_CON_WARMUPT_POSS 8U +#define ACMP_CON_WARMUPT_POSE 10U +#define ACMP_CON_WARMUPT_MSK BITS(ACMP_CON_WARMUPT_POSS,ACMP_CON_WARMUPT_POSE) + +#define ACMP_CON_HYSTSEL_POSS 4U +#define ACMP_CON_HYSTSEL_POSE 6U +#define ACMP_CON_HYSTSEL_MSK BITS(ACMP_CON_HYSTSEL_POSS,ACMP_CON_HYSTSEL_POSE) + +#define ACMP_CON_OUTINV_POS 3U +#define ACMP_CON_OUTINV_MSK BIT(ACMP_CON_OUTINV_POS) + +#define ACMP_CON_INACTV_POS 2U +#define ACMP_CON_INACTV_MSK BIT(ACMP_CON_INACTV_POS) + +#define ACMP_CON_EN_POS 0U +#define ACMP_CON_EN_MSK BIT(ACMP_CON_EN_POS) + +/****************** Bit definition for ACMP_INPUTSEL register ************************/ + +#define ACMP_INPUTSEL_VDDLVL_POSS 8U +#define ACMP_INPUTSEL_VDDLVL_POSE 13U +#define ACMP_INPUTSEL_VDDLVL_MSK BITS(ACMP_INPUTSEL_VDDLVL_POSS,ACMP_INPUTSEL_VDDLVL_POSE) + +#define ACMP_INPUTSEL_NSEL_POSS 4U +#define ACMP_INPUTSEL_NSEL_POSE 7U +#define ACMP_INPUTSEL_NSEL_MSK BITS(ACMP_INPUTSEL_NSEL_POSS,ACMP_INPUTSEL_NSEL_POSE) + +#define ACMP_INPUTSEL_PSEL_POSS 0U +#define ACMP_INPUTSEL_PSEL_POSE 2U +#define ACMP_INPUTSEL_PSEL_MSK BITS(ACMP_INPUTSEL_PSEL_POSS,ACMP_INPUTSEL_PSEL_POSE) + +/****************** Bit definition for ACMP_STAT register ************************/ + +#define ACMP_STAT_OUT_POS 1U +#define ACMP_STAT_OUT_MSK BIT(ACMP_STAT_OUT_POS) + +#define ACMP_STAT_ACT_POS 0U +#define ACMP_STAT_ACT_MSK BIT(ACMP_STAT_ACT_POS) + +/****************** Bit definition for ACMP_IES register ************************/ + +#define ACMP_IES_WARMUP_POS 1U +#define ACMP_IES_WARMUP_MSK BIT(ACMP_IES_WARMUP_POS) + +#define ACMP_IES_EDGE_POS 0U +#define ACMP_IES_EDGE_MSK BIT(ACMP_IES_EDGE_POS) + +/****************** Bit definition for ACMP_IEV register ************************/ + +#define ACMP_IEV_WARMUP_POS 1U +#define ACMP_IEV_WARMUP_MSK BIT(ACMP_IEV_WARMUP_POS) + +#define ACMP_IEV_EDGE_POS 0U +#define ACMP_IEV_EDGE_MSK BIT(ACMP_IEV_EDGE_POS) + +/****************** Bit definition for ACMP_IEC register ************************/ + +#define ACMP_IEC_WARMUP_POS 1U +#define ACMP_IEC_WARMUP_MSK BIT(ACMP_IEC_WARMUP_POS) + +#define ACMP_IEC_EDGE_POS 0U +#define ACMP_IEC_EDGE_MSK BIT(ACMP_IEC_EDGE_POS) + +/****************** Bit definition for ACMP_RIF register ************************/ + +#define ACMP_RIF_WARMUP_POS 1U +#define ACMP_RIF_WARMUP_MSK BIT(ACMP_RIF_WARMUP_POS) + +#define ACMP_RIF_EDGE_POS 0U +#define ACMP_RIF_EDGE_MSK BIT(ACMP_RIF_EDGE_POS) + +/****************** Bit definition for ACMP_IFM register ************************/ + +#define ACMP_IFM_WARMUP_POS 1U +#define ACMP_IFM_WARMUP_MSK BIT(ACMP_IFM_WARMUP_POS) + +#define ACMP_IFM_EDGE_POS 0U +#define ACMP_IFM_EDGE_MSK BIT(ACMP_IFM_EDGE_POS) + +/****************** Bit definition for ACMP_IFC register ************************/ + +#define ACMP_IFC_WARMUP_POS 1U +#define ACMP_IFC_WARMUP_MSK BIT(ACMP_IFC_WARMUP_POS) + +#define ACMP_IFC_EDGE_POS 0U +#define ACMP_IFC_EDGE_MSK BIT(ACMP_IFC_EDGE_POS) + +/****************** Bit definition for ACMP_PORT register ************************/ + +#define ACMP_PORT_PEN_POS 0U +#define ACMP_PORT_PEN_MSK BIT(ACMP_PORT_PEN_POS) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t INPUTSEL; + __I uint32_t STAT; + __O uint32_t IES; + __I uint32_t IEV; + __O uint32_t IEC; + __I uint32_t RIF; + __O uint32_t IFM; + __O uint32_t IFC; + __IO uint32_t PORT; +} ACMP_TypeDef; + +/****************** Bit definition for CALC_SQRTSR register ************************/ + +#define CALC_SQRTSR_BUSY_POS 0U +#define CALC_SQRTSR_BUSY_MSK BIT(CALC_SQRTSR_BUSY_POS) + +/****************** Bit definition for CALC_RDCND register ************************/ + +#define CALC_RDCND_RADICAND_POSS 0U +#define CALC_RDCND_RADICAND_POSE 31U +#define CALC_RDCND_RADICAND_MSK BITS(CALC_RDCND_RADICAND_POSS,CALC_RDCND_RADICAND_POSE) + +/****************** Bit definition for CALC_SQRTRES register ************************/ + +#define CALC_SQRTRES_RESULT_POSS 0U +#define CALC_SQRTRES_RESULT_POSE 15U +#define CALC_SQRTRES_RESULT_MSK BITS(CALC_SQRTRES_RESULT_POSS,CALC_SQRTRES_RESULT_POSE) + +/****************** Bit definition for CALC_DIVDR register ************************/ + +#define CALC_DIVDR_DIVD_POSS 0U +#define CALC_DIVDR_DIVD_POSE 31U +#define CALC_DIVDR_DIVD_MSK BITS(CALC_DIVDR_DIVD_POSS,CALC_DIVDR_DIVD_POSE) + +/****************** Bit definition for CALC_DIVSR register ************************/ + +#define CALC_DIVSR_DIVS_POSS 0U +#define CALC_DIVSR_DIVS_POSE 31U +#define CALC_DIVSR_DIVS_MSK BITS(CALC_DIVSR_DIVS_POSS,CALC_DIVSR_DIVS_POSE) + +/****************** Bit definition for CALC_DIVQR register ************************/ + +#define CALC_DIVQR_DIVQ_POSS 0U +#define CALC_DIVQR_DIVQ_POSE 31U +#define CALC_DIVQR_DIVQ_MSK BITS(CALC_DIVQR_DIVQ_POSS,CALC_DIVQR_DIVQ_POSE) + +/****************** Bit definition for CALC_DIVRR register ************************/ + +#define CALC_DIVRR_DIVS_POSS 0U +#define CALC_DIVRR_DIVS_POSE 31U +#define CALC_DIVRR_DIVS_MSK BITS(CALC_DIVRR_DIVS_POSS,CALC_DIVRR_DIVS_POSE) + +/****************** Bit definition for CALC_DIVCSR register ************************/ + +#define CALC_DIVCSR_TRM_POS 9U +#define CALC_DIVCSR_TRM_MSK BIT(CALC_DIVCSR_TRM_POS) + +#define CALC_DIVCSR_SIGN_POS 8U +#define CALC_DIVCSR_SIGN_MSK BIT(CALC_DIVCSR_SIGN_POS) + +#define CALC_DIVCSR_DZ_POS 1U +#define CALC_DIVCSR_DZ_MSK BIT(CALC_DIVCSR_DZ_POS) + +#define CALC_DIVCSR_BUSY_POS 0U +#define CALC_DIVCSR_BUSY_MSK BIT(CALC_DIVCSR_BUSY_POS) + +typedef struct +{ + __I uint32_t SQRTSR; + __IO uint32_t RDCND; + __I uint32_t SQRTRES; + uint32_t RESERVED0[5] ; + __IO uint32_t DIVDR; + __IO uint32_t DIVSR; + __I uint32_t DIVQR; + __I uint32_t DIVRR; + __IO uint32_t DIVCSR; +} CALC_TypeDef; + +/****************** Bit definition for TRNG_CR register ************************/ + +#define TRNG_CR_ADJC_POSS 16U +#define TRNG_CR_ADJC_POSE 17U +#define TRNG_CR_ADJC_MSK BITS(TRNG_CR_ADJC_POSS,TRNG_CR_ADJC_POSE) + +#define TRNG_CR_SDSEL_POSS 10U +#define TRNG_CR_SDSEL_POSE 11U +#define TRNG_CR_SDSEL_MSK BITS(TRNG_CR_SDSEL_POSS,TRNG_CR_SDSEL_POSE) + +#define TRNG_CR_DSEL_POSS 8U +#define TRNG_CR_DSEL_POSE 9U +#define TRNG_CR_DSEL_MSK BITS(TRNG_CR_DSEL_POSS,TRNG_CR_DSEL_POSE) + +#define TRNG_CR_POSTEN_POS 3U +#define TRNG_CR_POSTEN_MSK BIT(TRNG_CR_POSTEN_POS) + +#define TRNG_CR_TRNGSEL_POS 2U +#define TRNG_CR_TRNGSEL_MSK BIT(TRNG_CR_TRNGSEL_POS) + +#define TRNG_CR_ADJM_POS 1U +#define TRNG_CR_ADJM_MSK BIT(TRNG_CR_ADJM_POS) + +#define TRNG_CR_TRNGEN_POS 0U +#define TRNG_CR_TRNGEN_MSK BIT(TRNG_CR_TRNGEN_POS) + +/****************** Bit definition for TRNG_SR register ************************/ + +#define TRNG_SR_OVER_POS 3U +#define TRNG_SR_OVER_MSK BIT(TRNG_SR_OVER_POS) + +#define TRNG_SR_SERR_POS 2U +#define TRNG_SR_SERR_MSK BIT(TRNG_SR_SERR_POS) + +#define TRNG_SR_DAVLD_POS 1U +#define TRNG_SR_DAVLD_MSK BIT(TRNG_SR_DAVLD_POS) + +#define TRNG_SR_START_POS 0U +#define TRNG_SR_START_MSK BIT(TRNG_SR_START_POS) + +/****************** Bit definition for TRNG_DR register ************************/ + +#define TRNG_DR_DATA_POSS 0U +#define TRNG_DR_DATA_POSE 31U +#define TRNG_DR_DATA_MSK BITS(TRNG_DR_DATA_POSS,TRNG_DR_DATA_POSE) + +/****************** Bit definition for TRNG_SEED register ************************/ + +#define TRNG_SEED_SEED_POSS 0U +#define TRNG_SEED_SEED_POSE 31U +#define TRNG_SEED_SEED_MSK BITS(TRNG_SEED_SEED_POSS,TRNG_SEED_SEED_POSE) + +/****************** Bit definition for TRNG_CFGR register ************************/ + +#define TRNG_CFGR_TOPLMT_POSS 16U +#define TRNG_CFGR_TOPLMT_POSE 24U +#define TRNG_CFGR_TOPLMT_MSK BITS(TRNG_CFGR_TOPLMT_POSS,TRNG_CFGR_TOPLMT_POSE) + +#define TRNG_CFGR_CKDIV_POSS 8U +#define TRNG_CFGR_CKDIV_POSE 11U +#define TRNG_CFGR_CKDIV_MSK BITS(TRNG_CFGR_CKDIV_POSS,TRNG_CFGR_CKDIV_POSE) + +#define TRNG_CFGR_TSTART_POSS 0U +#define TRNG_CFGR_TSTART_POSE 2U +#define TRNG_CFGR_TSTART_MSK BITS(TRNG_CFGR_TSTART_POSS,TRNG_CFGR_TSTART_POSE) + +/****************** Bit definition for TRNG_IER register ************************/ + +#define TRNG_IER_SERR_POS 2U +#define TRNG_IER_SERR_MSK BIT(TRNG_IER_SERR_POS) + +#define TRNG_IER_DAVLD_POS 1U +#define TRNG_IER_DAVLD_MSK BIT(TRNG_IER_DAVLD_POS) + +#define TRNG_IER_START_POS 0U +#define TRNG_IER_START_MSK BIT(TRNG_IER_START_POS) + +/****************** Bit definition for TRNG_IFR register ************************/ + +#define TRNG_IFR_SERR_POS 2U +#define TRNG_IFR_SERR_MSK BIT(TRNG_IFR_SERR_POS) + +#define TRNG_IFR_DAVLD_POS 1U +#define TRNG_IFR_DAVLD_MSK BIT(TRNG_IFR_DAVLD_POS) + +#define TRNG_IFR_START_POS 0U +#define TRNG_IFR_START_MSK BIT(TRNG_IFR_START_POS) + +/****************** Bit definition for TRNG_IFCR register ************************/ + +#define TRNG_IFCR_SERRC_POS 2U +#define TRNG_IFCR_SERRC_MSK BIT(TRNG_IFCR_SERRC_POS) + +#define TRNG_IFCR_DAVLDC_POS 1U +#define TRNG_IFCR_DAVLDC_MSK BIT(TRNG_IFCR_DAVLDC_POS) + +#define TRNG_IFCR_STARTC_POS 0U +#define TRNG_IFCR_STARTC_MSK BIT(TRNG_IFCR_STARTC_POS) + +/****************** Bit definition for TRNG_ISR register ************************/ + +#define TRNG_ISR_SERR_POS 2U +#define TRNG_ISR_SERR_MSK BIT(TRNG_ISR_SERR_POS) + +#define TRNG_ISR_DAVLD_POS 1U +#define TRNG_ISR_DAVLD_MSK BIT(TRNG_ISR_DAVLD_POS) + +#define TRNG_ISR_START_POS 0U +#define TRNG_ISR_START_MSK BIT(TRNG_ISR_START_POS) + +typedef struct +{ + __IO uint32_t CR; + __I uint32_t SR; + __I uint32_t DR; + __IO uint32_t SEED; + __IO uint32_t CFGR; + __IO uint32_t IER; + __I uint32_t IFR; + __O uint32_t IFCR; + __I uint32_t ISR; +} TRNG_TypeDef; + +/****************** Bit definition for TSENSE_WPR register ************************/ + +#define TSENSE_WPR_WP_POS 0U +#define TSENSE_WPR_WP_MSK BIT(TSENSE_WPR_WP_POS) + +/****************** Bit definition for TSENSE_CR register ************************/ + +#define TSENSE_CR_TSU_POSS 12U +#define TSENSE_CR_TSU_POSE 14U +#define TSENSE_CR_TSU_MSK BITS(TSENSE_CR_TSU_POSS,TSENSE_CR_TSU_POSE) + +#define TSENSE_CR_TOM_POSS 8U +#define TSENSE_CR_TOM_POSE 10U +#define TSENSE_CR_TOM_MSK BITS(TSENSE_CR_TOM_POSS,TSENSE_CR_TOM_POSE) + +#define TSENSE_CR_CTN_POS 4U +#define TSENSE_CR_CTN_MSK BIT(TSENSE_CR_CTN_POS) + +#define TSENSE_CR_RST_POS 3U +#define TSENSE_CR_RST_MSK BIT(TSENSE_CR_RST_POS) + +#define TSENSE_CR_ENS_POS 2U +#define TSENSE_CR_ENS_MSK BIT(TSENSE_CR_ENS_POS) + +#define TSENSE_CR_REQEN_POS 1U +#define TSENSE_CR_REQEN_MSK BIT(TSENSE_CR_REQEN_POS) + +#define TSENSE_CR_EN_POS 0U +#define TSENSE_CR_EN_MSK BIT(TSENSE_CR_EN_POS) + +/****************** Bit definition for TSENSE_DR register ************************/ + +#define TSENSE_DR_ERR_POS 31U +#define TSENSE_DR_ERR_MSK BIT(TSENSE_DR_ERR_POS) + +#define TSENSE_DR_DATA_POSS 0U +#define TSENSE_DR_DATA_POSE 15U +#define TSENSE_DR_DATA_MSK BITS(TSENSE_DR_DATA_POSS,TSENSE_DR_DATA_POSE) + +/****************** Bit definition for TSENSE_PSR register ************************/ + +#define TSENSE_PSR_PRS_POSS 0U +#define TSENSE_PSR_PRS_POSE 7U +#define TSENSE_PSR_PRS_MSK BITS(TSENSE_PSR_PRS_POSS,TSENSE_PSR_PRS_POSE) + +/****************** Bit definition for TSENSE_IE register ************************/ + +#define TSENSE_IE_TSENSE_POS 0U +#define TSENSE_IE_TSENSE_MSK BIT(TSENSE_IE_TSENSE_POS) + +/****************** Bit definition for TSENSE_IF register ************************/ + +#define TSENSE_IF_TSENSE_POS 0U +#define TSENSE_IF_TSENSE_MSK BIT(TSENSE_IF_TSENSE_POS) + +/****************** Bit definition for TSENSE_IFCR register ************************/ + +#define TSENSE_IFCR_TSENSE_POS 0U +#define TSENSE_IFCR_TSENSE_MSK BIT(TSENSE_IFCR_TSENSE_POS) + +/****************** Bit definition for TSENSE_LTGR register ************************/ + +#define TSENSE_LTGR_LTG_POSS 0U +#define TSENSE_LTGR_LTG_POSE 20U +#define TSENSE_LTGR_LTG_MSK BITS(TSENSE_LTGR_LTG_POSS,TSENSE_LTGR_LTG_POSE) + +/****************** Bit definition for TSENSE_HTGR register ************************/ + +#define TSENSE_HTGR_HTG_POSS 0U +#define TSENSE_HTGR_HTG_POSE 20U +#define TSENSE_HTGR_HTG_MSK BITS(TSENSE_HTGR_HTG_POSS,TSENSE_HTGR_HTG_POSE) + +/****************** Bit definition for TSENSE_TBDR register ************************/ + +#define TSENSE_TBDR_TBD_POSS 0U +#define TSENSE_TBDR_TBD_POSE 15U +#define TSENSE_TBDR_TBD_MSK BITS(TSENSE_TBDR_TBD_POSS,TSENSE_TBDR_TBD_POSE) + +/****************** Bit definition for TSENSE_TCALBDR register ************************/ + +#define TSENSE_TCALBDR_TCAL_POSS 0U +#define TSENSE_TCALBDR_TCAL_POSE 16U +#define TSENSE_TCALBDR_TCAL_MSK BITS(TSENSE_TCALBDR_TCAL_POSS,TSENSE_TCALBDR_TCAL_POSE) + +/****************** Bit definition for TSENSE_SR register ************************/ + +#define TSENSE_SR_TSOUT_POS 31U +#define TSENSE_SR_TSOUT_MSK BIT(TSENSE_SR_TSOUT_POS) + +#define TSENSE_SR_NVLD_POS 25U +#define TSENSE_SR_NVLD_MSK BIT(TSENSE_SR_NVLD_POS) + +#define TSENSE_SR_TCAL_POSS 0U +#define TSENSE_SR_TCAL_POSE 24U +#define TSENSE_SR_TCAL_MSK BITS(TSENSE_SR_TCAL_POSS,TSENSE_SR_TCAL_POSE) + +typedef struct +{ + __IO uint32_t WPR; + __IO uint32_t CR; + __I uint32_t DR; + __IO uint32_t PSR; + __IO uint32_t IE; + __I uint32_t IF; + __IO uint32_t IFCR; + __IO uint32_t LTGR; + __IO uint32_t HTGR; + __IO uint32_t TBDR; + __IO uint32_t TCALBDR; + __I uint32_t SR; +} TSENSE_TypeDef; + +/****************** Bit definition for IWDT_LOAD register ************************/ + +#define IWDT_LOAD_LOAD_POSS 0U +#define IWDT_LOAD_LOAD_POSE 31U +#define IWDT_LOAD_LOAD_MSK BITS(IWDT_LOAD_LOAD_POSS,IWDT_LOAD_LOAD_POSE) + +/****************** Bit definition for IWDT_VALUE register ************************/ + +#define IWDT_VALUE_VALUE_POSS 0U +#define IWDT_VALUE_VALUE_POSE 31U +#define IWDT_VALUE_VALUE_MSK BITS(IWDT_VALUE_VALUE_POSS,IWDT_VALUE_VALUE_POSE) + +/****************** Bit definition for IWDT_CON register ************************/ + +#define IWDT_CON_CLKS_POS 3U +#define IWDT_CON_CLKS_MSK BIT(IWDT_CON_CLKS_POS) + +#define IWDT_CON_RSTEN_POS 2U +#define IWDT_CON_RSTEN_MSK BIT(IWDT_CON_RSTEN_POS) + +#define IWDT_CON_IE_POS 1U +#define IWDT_CON_IE_MSK BIT(IWDT_CON_IE_POS) + +#define IWDT_CON_EN_POS 0U +#define IWDT_CON_EN_MSK BIT(IWDT_CON_EN_POS) + +/****************** Bit definition for IWDT_INTCLR register ************************/ + +#define IWDT_INTCLR_INTCLR_POSS 0U +#define IWDT_INTCLR_INTCLR_POSE 31U +#define IWDT_INTCLR_INTCLR_MSK BITS(IWDT_INTCLR_INTCLR_POSS,IWDT_INTCLR_INTCLR_POSE) + +/****************** Bit definition for IWDT_RIS register ************************/ + +#define IWDT_RIS_WDTIF_POS 0U +#define IWDT_RIS_WDTIF_MSK BIT(IWDT_RIS_WDTIF_POS) + +/****************** Bit definition for IWDT_LOCK register ************************/ + +#define IWDT_LOCK_LOCK_POS 0U +#define IWDT_LOCK_LOCK_MSK BIT(IWDT_LOCK_LOCK_POS) + +typedef struct +{ + __O uint32_t LOAD; + __I uint32_t VALUE; + __IO uint32_t CON; + __O uint32_t INTCLR; + __I uint32_t RIS; + uint32_t RESERVED0[59] ; + __IO uint32_t LOCK; +} IWDT_TypeDef; + +/****************** Bit definition for WWDT_LOAD register ************************/ + +#define WWDT_LOAD_LOAD_POSS 0U +#define WWDT_LOAD_LOAD_POSE 31U +#define WWDT_LOAD_LOAD_MSK BITS(WWDT_LOAD_LOAD_POSS,WWDT_LOAD_LOAD_POSE) + +/****************** Bit definition for WWDT_VALUE register ************************/ + +#define WWDT_VALUE_VALUE_POSS 0U +#define WWDT_VALUE_VALUE_POSE 31U +#define WWDT_VALUE_VALUE_MSK BITS(WWDT_VALUE_VALUE_POSS,WWDT_VALUE_VALUE_POSE) + +/****************** Bit definition for WWDT_CON register ************************/ + +#define WWDT_CON_WWDTWIN_POSS 4U +#define WWDT_CON_WWDTWIN_POSE 5U +#define WWDT_CON_WWDTWIN_MSK BITS(WWDT_CON_WWDTWIN_POSS,WWDT_CON_WWDTWIN_POSE) + +#define WWDT_CON_CLKS_POS 3U +#define WWDT_CON_CLKS_MSK BIT(WWDT_CON_CLKS_POS) + +#define WWDT_CON_RSTEN_POS 2U +#define WWDT_CON_RSTEN_MSK BIT(WWDT_CON_RSTEN_POS) + +#define WWDT_CON_IE_POS 1U +#define WWDT_CON_IE_MSK BIT(WWDT_CON_IE_POS) + +#define WWDT_CON_EN_POS 0U +#define WWDT_CON_EN_MSK BIT(WWDT_CON_EN_POS) + +/****************** Bit definition for WWDT_INTCLR register ************************/ + +#define WWDT_INTCLR_INTCLR_POSS 0U +#define WWDT_INTCLR_INTCLR_POSE 31U +#define WWDT_INTCLR_INTCLR_MSK BITS(WWDT_INTCLR_INTCLR_POSS,WWDT_INTCLR_INTCLR_POSE) + +/****************** Bit definition for WWDT_RIS register ************************/ + +#define WWDT_RIS_WWDTIF_POS 0U +#define WWDT_RIS_WWDTIF_MSK BIT(WWDT_RIS_WWDTIF_POS) + +/****************** Bit definition for WWDT_LOCK register ************************/ + +#define WWDT_LOCK_LOCK_POS 0U +#define WWDT_LOCK_LOCK_MSK BIT(WWDT_LOCK_LOCK_POS) + +typedef struct +{ + __O uint32_t LOAD; + __I uint32_t VALUE; + __IO uint32_t CON; + __O uint32_t INTCLR; + __I uint32_t RIS; + uint32_t RESERVED0[59]; + __IO uint32_t LOCK; +} WWDT_TypeDef; + +/****************** Bit definition for LP16T_CON0 register ************************/ + +#define LP16T_CON0_PRELOAD_POS 22U +#define LP16T_CON0_PRELOAD_MSK BIT(LP16T_CON0_PRELOAD_POS) + +#define LP16T_CON0_WAVEPOL_POS 21U +#define LP16T_CON0_WAVEPOL_MSK BIT(LP16T_CON0_WAVEPOL_POS) + +#define LP16T_CON0_WAVE_POSS 19U +#define LP16T_CON0_WAVE_POSE 20U +#define LP16T_CON0_WAVE_MSK BITS(LP16T_CON0_WAVE_POSS,LP16T_CON0_WAVE_POSE) + +#define LP16T_CON0_TRIGEN_POSS 17U +#define LP16T_CON0_TRIGEN_POSE 18U +#define LP16T_CON0_TRIGEN_MSK BITS(LP16T_CON0_TRIGEN_POSS,LP16T_CON0_TRIGEN_POSE) + +#define LP16T_CON0_TRIGSEL_POSS 13U +#define LP16T_CON0_TRIGSEL_POSE 15U +#define LP16T_CON0_TRIGSEL_MSK BITS(LP16T_CON0_TRIGSEL_POSS,LP16T_CON0_TRIGSEL_POSE) + +#define LP16T_CON0_PRESC_POSS 9U +#define LP16T_CON0_PRESC_POSE 11U +#define LP16T_CON0_PRESC_MSK BITS(LP16T_CON0_PRESC_POSS,LP16T_CON0_PRESC_POSE) + +#define LP16T_CON0_TRGFLT_POSS 6U +#define LP16T_CON0_TRGFLT_POSE 7U +#define LP16T_CON0_TRGFLT_MSK BITS(LP16T_CON0_TRGFLT_POSS,LP16T_CON0_TRGFLT_POSE) + +#define LP16T_CON0_CKFLT_POSS 3U +#define LP16T_CON0_CKFLT_POSE 4U +#define LP16T_CON0_CKFLT_MSK BITS(LP16T_CON0_CKFLT_POSS,LP16T_CON0_CKFLT_POSE) + +#define LP16T_CON0_CKPOL_POS 1U +#define LP16T_CON0_CKPOL_MSK BIT(LP16T_CON0_CKPOL_POS) + +#define LP16T_CON0_CKSEL_POS 0U +#define LP16T_CON0_CKSEL_MSK BIT(LP16T_CON0_CKSEL_POS) + +/****************** Bit definition for LP16T_CON1 register ************************/ + +#define LP16T_CON1_CNTSTRT_POS 2U +#define LP16T_CON1_CNTSTRT_MSK BIT(LP16T_CON1_CNTSTRT_POS) + +#define LP16T_CON1_SNGSTRT_POS 1U +#define LP16T_CON1_SNGSTRT_MSK BIT(LP16T_CON1_SNGSTRT_POS) + +#define LP16T_CON1_ENABLE_POS 0U +#define LP16T_CON1_ENABLE_MSK BIT(LP16T_CON1_ENABLE_POS) + +/****************** Bit definition for LP16T_ARR register ************************/ + +#define LP16T_ARR_ARR_POSS 0U +#define LP16T_ARR_ARR_POSE 15U +#define LP16T_ARR_ARR_MSK BITS(LP16T_ARR_ARR_POSS,LP16T_ARR_ARR_POSE) + +/****************** Bit definition for LP16T_CNT register ************************/ + +#define LP16T_CNT_CNT_POSS 0U +#define LP16T_CNT_CNT_POSE 15U +#define LP16T_CNT_CNT_MSK BITS(LP16T_CNT_CNT_POSS,LP16T_CNT_CNT_POSE) + +/****************** Bit definition for LP16T_CMP register ************************/ + +#define LP16T_CMP_CMP_POSS 0U +#define LP16T_CMP_CMP_POSE 15U +#define LP16T_CMP_CMP_MSK BITS(LP16T_CMP_CMP_POSS,LP16T_CMP_CMP_POSE) + +/****************** Bit definition for LP16T_IER register ************************/ + +#define LP16T_IER_EXTTRIGIE_POS 2U +#define LP16T_IER_EXTTRIGIE_MSK BIT(LP16T_IER_EXTTRIGIE_POS) + +#define LP16T_IER_ARRMIE_POS 1U +#define LP16T_IER_ARRMIE_MSK BIT(LP16T_IER_ARRMIE_POS) + +#define LP16T_IER_CMPMIE_POS 0U +#define LP16T_IER_CMPMIE_MSK BIT(LP16T_IER_CMPMIE_POS) + +/****************** Bit definition for LP16T_ISR register ************************/ + +#define LP16T_ISR_EXTTRIG_POS 2U +#define LP16T_ISR_EXTTRIG_MSK BIT(LP16T_ISR_EXTTRIG_POS) + +#define LP16T_ISR_ARRM_POS 1U +#define LP16T_ISR_ARRM_MSK BIT(LP16T_ISR_ARRM_POS) + +#define LP16T_ISR_CMPM_POS 0U +#define LP16T_ISR_CMPM_MSK BIT(LP16T_ISR_CMPM_POS) + +/****************** Bit definition for LP16T_IFC register ************************/ + +#define LP16T_IFC_EXTTRIG_POS 2U +#define LP16T_IFC_EXTTRIG_MSK BIT(LP16T_IFC_EXTTRIG_POS) + +#define LP16T_IFC_ARRM_POS 1U +#define LP16T_IFC_ARRM_MSK BIT(LP16T_IFC_ARRM_POS) + +#define LP16T_IFC_CMPM_POS 0U +#define LP16T_IFC_CMPM_MSK BIT(LP16T_IFC_CMPM_POS) + +/****************** Bit definition for LP16T_UPDATE register ************************/ + +#define LP16T_UPDATE_UDIS_POS 0U +#define LP16T_UPDATE_UDIS_MSK BIT(LP16T_UPDATE_UDIS_POS) + +/****************** Bit definition for LP16T_SYNCSTAT register ************************/ + +#define LP16T_SYNCSTAT_CMPWBSY_POS 3U +#define LP16T_SYNCSTAT_CMPWBSY_MSK BIT(LP16T_SYNCSTAT_CMPWBSY_POS) + +#define LP16T_SYNCSTAT_ARRWBSY_POS 2U +#define LP16T_SYNCSTAT_ARRWBSY_MSK BIT(LP16T_SYNCSTAT_ARRWBSY_POS) + +#define LP16T_SYNCSTAT_CON1WBSY_POS 1U +#define LP16T_SYNCSTAT_CON1WBSY_MSK BIT(LP16T_SYNCSTAT_CON1WBSY_POS) + +typedef struct +{ + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t ARR; + __I uint32_t CNT; + __IO uint32_t CMP; + uint32_t RESERVED0 ; + __IO uint32_t IER; + __I uint32_t ISR; + __O uint32_t IFC; + uint32_t RESERVED1[3] ; + __IO uint32_t UPDATE; + __I uint32_t SYNCSTAT; +} LPTIM_TypeDef; + +/****************** Bit definition for DBGC_IDCODE register ************************/ + +#define DBGC_IDCODE_REV_ID_POSS 16U +#define DBGC_IDCODE_REV_ID_POSE 31U +#define DBGC_IDCODE_REV_ID_MSK BITS(DBGC_IDCODE_REV_ID_POSS,DBGC_IDCODE_REV_ID_POSE) + +#define DBGC_IDCODE_CORE_ID_POSS 12U +#define DBGC_IDCODE_CORE_ID_POSE 15U +#define DBGC_IDCODE_CORE_ID_MSK BITS(DBGC_IDCODE_CORE_ID_POSS,DBGC_IDCODE_CORE_ID_POSE) + +#define DBGC_IDCODE_DEV_ID_POSS 0U +#define DBGC_IDCODE_DEV_ID_POSE 11U +#define DBGC_IDCODE_DEV_ID_MSK BITS(DBGC_IDCODE_DEV_ID_POSS,DBGC_IDCODE_DEV_ID_POSE) + +/****************** Bit definition for DBGC_CR register ************************/ + +#define DBGC_CR_DBG_STANDBY_POS 3U +#define DBGC_CR_DBG_STANDBY_MSK BIT(DBGC_CR_DBG_STANDBY_POS) + +#define DBGC_CR_DBG_STOP2_POS 2U +#define DBGC_CR_DBG_STOP2_MSK BIT(DBGC_CR_DBG_STOP2_POS) + +#define DBGC_CR_DBG_STOP1_POS 1U +#define DBGC_CR_DBG_STOP1_MSK BIT(DBGC_CR_DBG_STOP1_POS) + +#define DBGC_CR_DBG_SLEEP_POS 0U +#define DBGC_CR_DBG_SLEEP_MSK BIT(DBGC_CR_DBG_SLEEP_POS) + +/****************** Bit definition for DBGC_APB1FZ register ************************/ + +#define DBGC_APB1FZ_CAN_STOP_POS 12U +#define DBGC_APB1FZ_CAN_STOP_MSK BIT(DBGC_APB1FZ_CAN_STOP_POS) + +#define DBGC_APB1FZ_I2C1_SMBUS_TO_POS 9U +#define DBGC_APB1FZ_I2C1_SMBUS_TO_MSK BIT(DBGC_APB1FZ_I2C1_SMBUS_TO_POS) + +#define DBGC_APB1FZ_I2C0_SMBUS_TO_POS 8U +#define DBGC_APB1FZ_I2C0_SMBUS_TO_MSK BIT(DBGC_APB1FZ_I2C0_SMBUS_TO_POS) + +#define DBGC_APB1FZ_TIM7_STOP_POS 7U +#define DBGC_APB1FZ_TIM7_STOP_MSK BIT(DBGC_APB1FZ_TIM7_STOP_POS) + +#define DBGC_APB1FZ_TIM6_STOP_POS 6U +#define DBGC_APB1FZ_TIM6_STOP_MSK BIT(DBGC_APB1FZ_TIM6_STOP_POS) + +#define DBGC_APB1FZ_TIM5_STOP_POS 5U +#define DBGC_APB1FZ_TIM5_STOP_MSK BIT(DBGC_APB1FZ_TIM5_STOP_POS) + +#define DBGC_APB1FZ_TIM4_STOP_POS 4U +#define DBGC_APB1FZ_TIM4_STOP_MSK BIT(DBGC_APB1FZ_TIM4_STOP_POS) + +#define DBGC_APB1FZ_TIM3_STOP_POS 3U +#define DBGC_APB1FZ_TIM3_STOP_MSK BIT(DBGC_APB1FZ_TIM3_STOP_POS) + +#define DBGC_APB1FZ_TIM2_STOP_POS 2U +#define DBGC_APB1FZ_TIM2_STOP_MSK BIT(DBGC_APB1FZ_TIM2_STOP_POS) + +#define DBGC_APB1FZ_TIM1_STOP_POS 1U +#define DBGC_APB1FZ_TIM1_STOP_MSK BIT(DBGC_APB1FZ_TIM1_STOP_POS) + +#define DBGC_APB1FZ_TIM0_STOP_POS 0U +#define DBGC_APB1FZ_TIM0_STOP_MSK BIT(DBGC_APB1FZ_TIM0_STOP_POS) + +/****************** Bit definition for DBGC_APB2FZ register ************************/ + +#define DBGC_APB2FZ_RTC_STOP_POS 10U +#define DBGC_APB2FZ_RTC_STOP_MSK BIT(DBGC_APB2FZ_RTC_STOP_POS) + +#define DBGC_APB2FZ_WWDT_STOP_POS 9U +#define DBGC_APB2FZ_WWDT_STOP_MSK BIT(DBGC_APB2FZ_WWDT_STOP_POS) + +#define DBGC_APB2FZ_IWDT_STOP_POS 8U +#define DBGC_APB2FZ_IWDT_STOP_MSK BIT(DBGC_APB2FZ_IWDT_STOP_POS) + +#define DBGC_APB2FZ_LPTIM0_STOP_POS 0U +#define DBGC_APB2FZ_LPTIM0_STOP_MSK BIT(DBGC_APB2FZ_LPTIM0_STOP_POS) + +typedef struct +{ + __I uint32_t IDCODE; + __IO uint32_t CR; + __IO uint32_t APB1FZ; + __IO uint32_t APB2FZ; +} DBGC_TypeDef; + + +/* Base addresses */ +#define SRAM_BASE (0x20000000UL) +#define APB1_BASE (0x40000000UL) +#define APB2_BASE (0x40040000UL) +#define AHB_BASE (0x40080000UL) + +/* APB1 peripherals Base Address */ +#define AD16C4T0_BASE (APB1_BASE + 0x0000) +#define BS16T0_BASE (APB1_BASE + 0x0400) +#define GP16C2T0_BASE (APB1_BASE + 0x0800) +#define GP16C2T1_BASE (APB1_BASE + 0x0C00) +#define BS16T1_BASE (APB1_BASE + 0x1000) +#define BS16T2_BASE (APB1_BASE + 0x1400) +#define GP16C4T0_BASE (APB1_BASE + 0x1800) +#define BS16T3_BASE (APB1_BASE + 0x1C00) +#define UART0_BASE (APB1_BASE + 0x4000) +#define UART1_BASE (APB1_BASE + 0x4400) +#define UART2_BASE (APB1_BASE + 0x4800) +#define UART3_BASE (APB1_BASE + 0x4C00) +#define USART0_BASE (APB1_BASE + 0x5000) +#define USART1_BASE (APB1_BASE + 0x5400) +#define SPI0_BASE (APB1_BASE + 0x6000) +#define SPI1_BASE (APB1_BASE + 0x6400) +#define SPI2_BASE (APB1_BASE + 0x6800) +#define I2C0_BASE (APB1_BASE + 0x8000) +#define I2C1_BASE (APB1_BASE + 0x8400) +#define CAN0_BASE (APB1_BASE + 0xB000) +#define DMA0_BASE (APB1_BASE + 0xC000) + +/* APB2 peripherals Base Address */ +#define LPTIM0_BASE (APB2_BASE + 0x0000) +#define LPUART0_BASE (APB2_BASE + 0x1000) +#define ADC0_BASE (APB2_BASE + 0x2000) +#define ADC1_BASE (APB2_BASE + 0x2400) +#define ACMP0_BASE (APB2_BASE + 0x3000) +#define ACMP1_BASE (APB2_BASE + 0x3400) +#define OPAMP_BASE (APB2_BASE + 0x4000) +#define DAC0_BASE (APB2_BASE + 0x5000) +#define WWDT_BASE (APB2_BASE + 0x6000) +#define IWDT_BASE (APB2_BASE + 0x6400) +#define LCD_BASE (APB2_BASE + 0x7000) +#define BKPC_BASE (APB2_BASE + 0x8000) +#define RTC_BASE (APB2_BASE + 0x8400) +#define TSENSE_BASE (APB2_BASE + 0x8800) +#define DBGC_BASE (APB2_BASE + 0xA000) + +/* AHB peripherals Base Address */ +#define SYSCFG_BASE (AHB_BASE + 0x0000) +#define CMU_BASE (AHB_BASE + 0x0400) +#define RMU_BASE (AHB_BASE + 0x0800) +#define PMU_BASE (AHB_BASE + 0x0C00) +#define MSC_BASE (AHB_BASE + 0x1000) +#define GPIOA_BASE (AHB_BASE + 0x4000) +#define GPIOB_BASE (AHB_BASE + 0x4040) +#define GPIOC_BASE (AHB_BASE + 0x4080) +#define GPIOD_BASE (AHB_BASE + 0x40C0) +#define GPIOE_BASE (AHB_BASE + 0x4100) +#define GPIOF_BASE (AHB_BASE + 0x4140) +#define GPIOG_BASE (AHB_BASE + 0x4180) +#define GPIOH_BASE (AHB_BASE + 0x41C0) +#define EXTI_BASE (AHB_BASE + 0x4300) +#define CRC_BASE (AHB_BASE + 0x5000) +#define CALC_BASE (AHB_BASE + 0x5400) +#define CRYPT_BASE (AHB_BASE + 0x5800) +#define TRNG_BASE (AHB_BASE + 0x5C00) +#define PIS_BASE (AHB_BASE + 0x6000) + +/* APB1 peripherals */ +#define AD16C4T0 ((TIMER_TypeDef *)AD16C4T0_BASE) +#define BS16T0 ((TIMER_TypeDef *)BS16T0_BASE) +#define GP16C2T0 ((TIMER_TypeDef *)GP16C2T0_BASE) +#define GP16C2T1 ((TIMER_TypeDef *)GP16C2T1_BASE) +#define BS16T1 ((TIMER_TypeDef *)BS16T1_BASE) +#define BS16T2 ((TIMER_TypeDef *)BS16T2_BASE) +#define GP16C4T0 ((TIMER_TypeDef *)GP16C4T0_BASE) +#define BS16T3 ((TIMER_TypeDef *)BS16T3_BASE) +#define UART0 ((UART_TypeDef *)UART0_BASE) +#define UART1 ((UART_TypeDef *)UART1_BASE) +#define UART2 ((UART_TypeDef *)UART2_BASE) +#define UART3 ((UART_TypeDef *)UART3_BASE) +#define USART0 ((USART_TypeDef *)USART0_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define SPI0 ((SPI_TypeDef *)SPI0_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define I2C0 ((I2C_TypeDef *)I2C0_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define CAN0 ((CAN_TypeDef *)CAN0_BASE) +#define DMA0 ((DMA_TypeDef *)DMA0_BASE) + +/* APB2 peripherals */ +#define LPTIM0 ((LPTIM_TypeDef *)LPTIM0_BASE) +#define LPUART0 ((LPUART_TypeDef *)LPUART0_BASE) +#define ADC0 ((ADC_TypeDef *)ADC0_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) +#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) +#define OPAMP ((OPAMP_TypeDef *)OPAMP_BASE) +#define DAC0 ((DAC_TypeDef *)DAC0_BASE) +#define WWDT ((WWDT_TypeDef *)WWDT_BASE) +#define IWDT ((IWDT_TypeDef *)IWDT_BASE) +#define LCD ((LCD_TypeDef *)LCD_BASE) +#define BKPC ((BKPC_TypeDef *)BKPC_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define TSENSE ((TSENSE_TypeDef *)TSENSE_BASE) +#define DBGC ((DBGC_TypeDef *)DBGC_BASE) + +/* AHB peripherals */ +#define SYSCFG ((SYSCFG_TypeDef *)SYSCFG_BASE) +#define CMU ((CMU_TypeDef *)CMU_BASE) +#define RMU ((RMU_TypeDef *)RMU_BASE) +#define PMU ((PMU_TypeDef *)PMU_BASE) +#define MSC ((MSC_TypeDef *)MSC_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *)GPIOH_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define CALC ((CALC_TypeDef *)CALC_BASE) +#define CRYPT ((CRYPT_TypeDef *)CRYPT_BASE) +#define TRNG ((TRNG_TypeDef *)TRNG_BASE) +#define PIS ((PIS_TypeDef *)PIS_BASE) + +#endif diff --git a/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s rename to bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s diff --git a/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s similarity index 56% rename from bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s rename to bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s index 6bf19bc8779764e99877f947c560be2ee61f30a4..dab56328c5b41e64ab73513d230f4e09591e25a5 100644 --- a/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s +++ b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s @@ -45,7 +45,7 @@ __Vectors DCD __initial_sp ;0, load top of stack DCD SysTick_Handler ;15, systick handler DCD WWDG_IWDG_Handler ;16, irq0 WWDG_IWDG handler DCD LVD_Handler ;17, irq1 LVD handler - DCD RTC_TEMP_Handler ;18, irq2 RTC handler + DCD RTC_TSENSE_Handler ;18, irq2 RTC handler DCD CRYPT_TRNG_Handler ;19, irq3 CRYPT handler DCD CMU_Handler ;20, irq4 CMU handler DCD EXTI0_3_Handler ;21, irq5 EXTI0_3 handler @@ -58,8 +58,8 @@ __Vectors DCD __initial_sp ;0, load top of stack DCD ADC_ACMP_Handler ;28, irq12 ADC_ACMP handler DCD AD16C4T0_BRK_UP_TRIG_COM_Handler ;29, irq13 AD16C4T0_BRK_UP_TRIG_COM handler DCD AD16C4T0_CC_Handler ;30, irq14 AD16C4T0_CC handler - DCD BS16T0_Handler ;31, irq15 BS16T0 handler - DCD 0 ;32, irq16 Reserved + DCD BS16T0_Handler ;31, irq15 BS16T0 handler + DCD 0 ;32, irq16 Reserved DCD GP16C2T0_Handler ;33, irq17 GP16C2T0 handler DCD GP16C2T1_Handler ;34, irq18 GP16C2T1 handler DCD BS16T1_UART2_Handler ;35, irq19 BS16T1_UART2 handler @@ -81,255 +81,255 @@ __Vectors DCD __initial_sp ;0, load top of stack ;Reset Handler---------------------------------------------- Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - LDR R0, =__main - BX R0 - NOP - ALIGN - ENDP + EXPORT Reset_Handler [WEAK] + IMPORT __main + LDR R0, =__main + BX R0 + NOP + ALIGN + ENDP ;system int------------------------------------------------- NMI_Handler PROC ;int 2 - EXPORT NMI_Handler [WEAK] - B . - ENDP + EXPORT NMI_Handler [WEAK] + B . + ENDP HardFault_Handler \ - PROC ;int3 - EXPORT HardFault_Handler [WEAK] - B . - ENDP + PROC ;int3 + EXPORT HardFault_Handler [WEAK] + B . + ENDP SVC_Handler \ - PROC ;int11 - EXPORT SVC_Handler [WEAK] - B . - ENDP + PROC ;int11 + EXPORT SVC_Handler [WEAK] + B . + ENDP DebugMon_Handler \ - PROC ;int12 - EXPORT DebugMon_Handler [WEAK] - B . - ENDP + PROC ;int12 + EXPORT DebugMon_Handler [WEAK] + B . + ENDP PendSV_Handler PROC ;int14 - EXPORT PendSV_Handler [WEAK] - B . - ENDP + EXPORT PendSV_Handler [WEAK] + B . + ENDP SysTick_Handler \ - PROC ;int15 - EXPORT SysTick_Handler [WEAK] - B . - ENDP + PROC ;int15 + EXPORT SysTick_Handler [WEAK] + B . + ENDP ;peripheral module int ----------------------------------------------- WWDG_IWDG_Handler \ - PROC ;int16 - EXPORT WWDG_IWDG_Handler [WEAK] - B . - ENDP + PROC ;int16 + EXPORT WWDG_IWDG_Handler [WEAK] + B . + ENDP LVD_Handler \ - PROC ;int17 - EXPORT LVD_Handler [WEAK] - B . - ENDP + PROC ;int17 + EXPORT LVD_Handler [WEAK] + B . + ENDP -RTC_TEMP_Handler \ - PROC ;int18 - EXPORT RTC_TEMP_Handler [WEAK] - B . - ENDP +RTC_TSENSE_Handler \ + PROC ;int18 + EXPORT RTC_TSENSE_Handler [WEAK] + B . + ENDP CRYPT_TRNG_Handler \ - PROC ;int19 - EXPORT CRYPT_TRNG_Handler [WEAK] - B . - ENDP + PROC ;int19 + EXPORT CRYPT_TRNG_Handler [WEAK] + B . + ENDP CMU_Handler \ - PROC ;int20 - EXPORT CMU_Handler [WEAK] - B . - ENDP + PROC ;int20 + EXPORT CMU_Handler [WEAK] + B . + ENDP EXTI0_3_Handler \ - PROC ;int21 - EXPORT EXTI0_3_Handler [WEAK] - B . - ENDP + PROC ;int21 + EXPORT EXTI0_3_Handler [WEAK] + B . + ENDP EXTI4_7_Handler \ - PROC ;int22 - EXPORT EXTI4_7_Handler [WEAK] - B . - ENDP + PROC ;int22 + EXPORT EXTI4_7_Handler [WEAK] + B . + ENDP EXTI8_11_Handler \ - PROC ;int23 - EXPORT EXTI8_11_Handler [WEAK] - B . - ENDP + PROC ;int23 + EXPORT EXTI8_11_Handler [WEAK] + B . + ENDP EXTI12_15_Handler \ - PROC ;int24 - EXPORT EXTI12_15_Handler [WEAK] - B . - ENDP + PROC ;int24 + EXPORT EXTI12_15_Handler [WEAK] + B . + ENDP DMA_Handler \ - PROC ;int25 - EXPORT DMA_Handler [WEAK] - B . - ENDP + PROC ;int25 + EXPORT DMA_Handler [WEAK] + B . + ENDP CAN0_Handler \ - PROC ;int26 - EXPORT CAN0_Handler [WEAK] - B . - ENDP + PROC ;int26 + EXPORT CAN0_Handler [WEAK] + B . + ENDP LPTIM0_SPI2_Handler \ - PROC ;int27 - EXPORT LPTIM0_SPI2_Handler [WEAK] - B . - ENDP + PROC ;int27 + EXPORT LPTIM0_SPI2_Handler [WEAK] + B . + ENDP ADC_ACMP_Handler \ - PROC ;int28 - EXPORT ADC_ACMP_Handler [WEAK] - B . - ENDP + PROC ;int28 + EXPORT ADC_ACMP_Handler [WEAK] + B . + ENDP AD16C4T0_BRK_UP_TRIG_COM_Handler \ - PROC ;int29 - EXPORT AD16C4T0_BRK_UP_TRIG_COM_Handler [WEAK] - B . - ENDP + PROC ;int29 + EXPORT AD16C4T0_BRK_UP_TRIG_COM_Handler [WEAK] + B . + ENDP AD16C4T0_CC_Handler \ - PROC ;int30 - EXPORT AD16C4T0_CC_Handler [WEAK] - B . - ENDP + PROC ;int30 + EXPORT AD16C4T0_CC_Handler [WEAK] + B . + ENDP BS16T0_Handler \ - PROC ;int31 - EXPORT BS16T0_Handler [WEAK] - B . - ENDP + PROC ;int31 + EXPORT BS16T0_Handler [WEAK] + B . + ENDP GP16C2T0_Handler PROC ;int33 - EXPORT GP16C2T0_Handler [WEAK] - B . - ENDP + EXPORT GP16C2T0_Handler [WEAK] + B . + ENDP GP16C2T1_Handler PROC ;int34 - EXPORT GP16C2T1_Handler [WEAK] - B . - ENDP + EXPORT GP16C2T1_Handler [WEAK] + B . + ENDP BS16T1_UART2_Handler \ - PROC ;int35 - EXPORT BS16T1_UART2_Handler [WEAK] - B . - ENDP + PROC ;int35 + EXPORT BS16T1_UART2_Handler [WEAK] + B . + ENDP BS16T2_UART3_Handler \ - PROC ;int36 - EXPORT BS16T2_UART3_Handler [WEAK] - B . - ENDP + PROC ;int36 + EXPORT BS16T2_UART3_Handler [WEAK] + B . + ENDP GP16C4T0_LCD_Handler \ - PROC ;int37 - EXPORT GP16C4T0_LCD_Handler [WEAK] - B . - ENDP + PROC ;int37 + EXPORT GP16C4T0_LCD_Handler [WEAK] + B . + ENDP BS16T3_DAC0_Handler \ - PROC ;int38 - EXPORT BS16T3_DAC0_Handler [WEAK] - B . - ENDP + PROC ;int38 + EXPORT BS16T3_DAC0_Handler [WEAK] + B . + ENDP I2C0_Handler \ - PROC ;int39 - EXPORT I2C0_Handler [WEAK] - B . - ENDP + PROC ;int39 + EXPORT I2C0_Handler [WEAK] + B . + ENDP I2C1_Handler \ - PROC ;int40 - EXPORT I2C1_Handler [WEAK] - B . - ENDP + PROC ;int40 + EXPORT I2C1_Handler [WEAK] + B . + ENDP SPI0_Handler \ - PROC ;int41 - EXPORT SPI0_Handler [WEAK] - B . - ENDP + PROC ;int41 + EXPORT SPI0_Handler [WEAK] + B . + ENDP SPI1_Handler \ - PROC ;int42 - EXPORT SPI1_Handler [WEAK] - B . - ENDP + PROC ;int42 + EXPORT SPI1_Handler [WEAK] + B . + ENDP UART0_Handler \ - PROC ;int43 - EXPORT UART0_Handler [WEAK] - B . - ENDP + PROC ;int43 + EXPORT UART0_Handler [WEAK] + B . + ENDP UART1_Handler \ - PROC ;int44 - EXPORT UART1_Handler [WEAK] - B . - ENDP + PROC ;int44 + EXPORT UART1_Handler [WEAK] + B . + ENDP USART0_Handler \ - PROC ;int45 - EXPORT USART0_Handler [WEAK] - B . - ENDP + PROC ;int45 + EXPORT USART0_Handler [WEAK] + B . + ENDP USART1_Handler \ - PROC ;int46 - EXPORT USART1_Handler [WEAK] - B . - ENDP + PROC ;int46 + EXPORT USART1_Handler [WEAK] + B . + ENDP LPUART0_Handler \ - PROC ;int47 - EXPORT LPUART0_Handler [WEAK] - B . - ENDP + PROC ;int47 + EXPORT LPUART0_Handler [WEAK] + B . + ENDP ; User Initial Stack & Heap----------------------------------------------------- - ALIGN - IF :DEF:__MICROLIB + ALIGN + IF :DEF:__MICROLIB - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit - ELSE + ELSE - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap __user_initial_stackheap - LDR R0, = Heap_Mem - LDR R1, = (Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR - ALIGN + ALIGN - ENDIF + ENDIF - END + END diff --git a/bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/System/system_es32f065x.c b/bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/System/system_es32f065x.c similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/System/system_es32f065x.c rename to bsp/essemi/es32f0654/libraries/CMSIS/Device/EastSoft/ES32F065x/System/system_es32f065x.c diff --git a/bsp/es32f0654/libraries/CMSIS/Include/arm_common_tables.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/arm_common_tables.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/arm_common_tables.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/arm_common_tables.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/arm_const_structs.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/arm_const_structs.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/arm_const_structs.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/arm_const_structs.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/arm_math.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/arm_math.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/arm_math.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/arm_math.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/cmsis_armcc.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/cmsis_armcc.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/cmsis_armcc.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/cmsis_armcc.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/cmsis_armcc_V6.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/cmsis_armcc_V6.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/cmsis_armcc_V6.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/cmsis_armcc_V6.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/cmsis_gcc.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/cmsis_gcc.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/cmsis_gcc.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/cmsis_gcc.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cm0.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cm0.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/core_cm0.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cm0.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cm0plus.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cm0plus.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/core_cm0plus.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cm0plus.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cmFunc.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cmFunc.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/core_cmFunc.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cmFunc.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cmInstr.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cmInstr.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/core_cmInstr.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cmInstr.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_cmSimd.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cmSimd.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/core_cmSimd.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/core_cmSimd.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_sc000.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/core_sc000.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/core_sc000.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/core_sc000.h diff --git a/bsp/es32f0654/libraries/CMSIS/Include/core_sc300.h b/bsp/essemi/es32f0654/libraries/CMSIS/Include/core_sc300.h similarity index 100% rename from bsp/es32f0654/libraries/CMSIS/Include/core_sc300.h rename to bsp/essemi/es32f0654/libraries/CMSIS/Include/core_sc300.h diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h new file mode 100644 index 0000000000000000000000000000000000000000..452deaf516b8b6506cc0d1493de5f50411737b21 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h @@ -0,0 +1,355 @@ +/** + ********************************************************************************* + * + * @file ald_acmp.h + * @brief Header file of ACMP module driver. + * + * @version V1.0 + * @date 13 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_ACMP_H__ +#define __ALD_ACMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup ACMP + * @{ + */ + +/** @defgroup ACMP_Public_Types ACMP Public Types + * @{ + */ + +/** + * @brief Acmp interrupt + */ +typedef enum +{ + ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */ + ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */ +} acmp_it_t; + +/** + * @brief Acmp interrupt + */ +typedef enum +{ + ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */ + ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */ +} acmp_flag_t; + +/** + * @brief Acmp interrupt flag + */ +typedef enum +{ + ACMP_STATUS_EDGE = (1U << 0), /**< Edge interrupt flag */ + ACMP_STATUS_WARMUP = (1U << 1), /**< Warm up interrupt flag */ +} acmp_status_t; + +/** + * @brief Acmp positive input + */ +typedef enum +{ + ACMP_POS_CH0 = 0, /**< Channel 0 as positive input */ + ACMP_POS_CH1 = 1, /**< Channel 1 as positive input */ + ACMP_POS_CH2 = 2, /**< Channel 2 as positive input */ + ACMP_POS_CH3 = 3, /**< Channel 3 as positive input */ + ACMP_POS_CH4 = 4, /**< Channel 4 as positive input */ + ACMP_POS_CH5 = 5, /**< Channel 5 as positive input */ + ACMP_POS_CH6 = 6, /**< Channel 6 as positive input */ + ACMP_POS_CH7 = 7, /**< Channel 7 as positive input */ +} acmp_pos_input_t; + +/** + * @brief Acmp negative input + */ +typedef enum +{ + ACMP_NEG_CH0 = 0, /**< Channel 0 as negative input */ + ACMP_NEG_CH1 = 1, /**< Channel 1 as negative input */ + ACMP_NEG_CH2 = 2, /**< Channel 2 as negative input */ + ACMP_NEG_CH3 = 3, /**< Channel 3 as negative input */ + ACMP_NEG_CH4 = 4, /**< Channel 4 as negative input */ + ACMP_NEG_CH5 = 5, /**< Channel 5 as negative input */ + ACMP_NEG_CH6 = 6, /**< Channel 6 as negative input */ + ACMP_NEG_CH7 = 7, /**< Channel 7 as negative input */ + ACMP_NEG_1V25 = 8, /**< 1.25v as negative input */ + ACMP_NEG_2V5 = 9, /**< 2.5v as negative input */ + ACMP_NEG_VDD = 10, /**< VDD as negative input */ +} acmp_neg_input_t; + +/** + * @brief Acmp mode + */ +typedef enum +{ + ACMP_ULTRA_LOW_POWER = 0, /**< Ultra low power mode */ + ACMP_LOW_POWER = 1, /**< Low power mode */ + ACMP_MIDDLE_POWER = 2, /**< Middle power mode */ + ACMP_HIGH_POWER = 3, /**< High power mode */ +} acmp_mode_t; + +/** + * @brief Acmp warm-up time + */ +typedef enum +{ + ACMP_4_PCLK = 0, /**< 4 hfperclk cycles */ + ACMP_8_PCLK = 1, /**< 4 hfperclk cycles */ + ACMP_16_PCLK = 2, /**< 4 hfperclk cycles */ + ACMP_32_PCLK = 3, /**< 4 hfperclk cycles */ + ACMP_64_PCLK = 4, /**< 4 hfperclk cycles */ + ACMP_128_PCLK = 5, /**< 4 hfperclk cycles */ + ACMP_256_PCLK = 6, /**< 4 hfperclk cycles */ + ACMP_512_PCLK = 7, /**< 4 hfperclk cycles */ +} acmp_warm_time_t; + +/** + * @brief Acmp hysteresis level + */ +typedef enum +{ + ACMP_HYST_0 = 0, /**< No hysteresis */ + ACMP_HYST_15 = 1, /**< 15mV hysteresis */ + ACMP_HYST_22 = 2, /**< 22mV hysteresis */ + ACMP_HYST_29 = 3, /**< 29mV hysteresis */ + ACMP_HYST_36 = 4, /**< 36mV hysteresis */ + ACMP_HYST_43 = 5, /**< 43mV hysteresis */ + ACMP_HYST_50 = 6, /**< 50mV hysteresis */ + ACMP_HYST_57 = 7, /**< 57mV hysteresis */ +} acmp_hystsel_t; + +/** + * @brief Acmp inactive state + */ +typedef enum +{ + ACMP_INACTVAL_LOW = 0, /**< The inactive value is 0 */ + ACMP_INACTVAL_HIGH = 1, /**< The inactive value is 1 */ +} acmp_inactval_t; + +/** + * @brief which edges set up interrupt + */ +typedef enum +{ + ACMP_EDGE_NONE = 0, /**< Disable EDGE interrupt */ + ACMP_EDGE_FALL = 1, /**< Falling edges set EDGE interrupt */ + ACMP_EDGE_RISE = 2, /**< rise edges set EDGE interrupt */ + ACMP_EDGE_ALL = 3, /**< Falling edges and rise edges set EDGE interrupt */ +} acmp_edge_t; + +/** + * @brief Acmp output function + */ +typedef enum +{ + ACMP_OUT_DISABLE = 0, /**< Disable acmp output */ + ACMP_OUT_ENABLE = 1, /**< Enable acmp output */ +} acmp_out_func_t; + +/** + * @brief Acmp warm-up interrupt function + */ +typedef enum +{ + ACMP_WARM_DISABLE = 0, /**< Disable acmp warm-up interrupt */ + ACMP_WARM_ENABLE = 1, /**< Enable acmp warm-up interrupt */ +} acmp_warm_it_func; + +/** + * @brief Acmp gpio output invert + */ +typedef enum +{ + ACMP_GPIO_NO_INV = 0, /**< Acmp output to gpio is not inverted */ + ACMP_GPIO_INV = 1, /**< Acmp output to gpio is inverted */ +} acmp_invert_t; + +/** + * @brief Acmp output config structure definition + */ +typedef struct +{ + acmp_out_func_t out_func; /**< Acmp output function */ + acmp_invert_t gpio_inv; /**< If invert gpio output */ +} acmp_output_config_t; + +/** + * @brief Acmp init structure definition + */ +typedef struct +{ + acmp_mode_t mode; /**< Acmp operation mode */ + acmp_warm_time_t warm_time; /**< Acmp warm up time */ + acmp_hystsel_t hystsel; /**< Acmp hysteresis level */ + acmp_warm_it_func warm_func; /**< Acmp warm-up interrupt enable/disable */ + acmp_pos_input_t pos_port; /**< Acmp positive port select */ + acmp_neg_input_t neg_port; /**< Acmp negative port select */ + acmp_inactval_t inactval; /**< Acmp inavtive output value */ + acmp_edge_t edge; /** Select edges to set interrupt flag */ + uint8_t vdd_level; /** Select scaling factor for CDD reference level, MAX is 63 */ +} acmp_init_t; + +/** + * @brief ACMP Handle Structure definition + */ +typedef struct acmp_handle_s +{ + ACMP_TypeDef *perh; /**< Register base address */ + acmp_init_t init; /**< ACMP required parameters */ + lock_state_t lock; /**< Locking object */ + + void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp warm-up complete callback */ + void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp edge trigger callback */ +} acmp_handle_t; +/** + * @} + */ + +/** @defgroup ACMP_Public_Macros ACMP Public Macros + * @{ + */ +#define ACMP_ENABLE(handle) (SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK)) +#define ACMP_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK)) +/** + * @} + */ + +/** @defgroup ACMP_Private_Macros ACMP Private Macros + * @{ + */ +#define IS_ACMP_TYPE(x) (((x) == ACMP0) || \ + ((x) == ACMP1)) +#define IS_ACMP_MODE_TYPE(x) (((x) == ACMP_ULTRA_LOW_POWER) || \ + ((x) == ACMP_LOW_POWER) || \ + ((x) == ACMP_MIDDLE_POWER) || \ + ((x) == ACMP_HIGH_POWER)) +#define IS_ACMP_IT_TYPE(x) (((x) == ACMP_IT_EDGE) || \ + ((x) == ACMP_IT_WARMUP)) +#define IS_ACMP_FLAG_TYPE(x) (((x) == ACMP_FLAG_EDGE) || \ + ((x) == ACMP_FLAG_WARMUP)) +#define IS_ACMP_STATUS_TYPE(x) (((x) == ACMP_STATUS_EDGE) || \ + ((x) == ACMP_STATUS_WARMUP)) +#define IS_ACMP_POS_INPUT_TYPE(x) (((x) == ACMP_POS_CH0) || \ + ((x) == ACMP_POS_CH1) || \ + ((x) == ACMP_POS_CH2) || \ + ((x) == ACMP_POS_CH3) || \ + ((x) == ACMP_POS_CH4) || \ + ((x) == ACMP_POS_CH5) || \ + ((x) == ACMP_POS_CH6) || \ + ((x) == ACMP_POS_CH7)) +#define IS_ACMP_NEG_INPUT_TYPE(x) (((x) == ACMP_NEG_CH0) || \ + ((x) == ACMP_NEG_CH1) || \ + ((x) == ACMP_NEG_CH2) || \ + ((x) == ACMP_NEG_CH3) || \ + ((x) == ACMP_NEG_CH4) || \ + ((x) == ACMP_NEG_CH5) || \ + ((x) == ACMP_NEG_CH6) || \ + ((x) == ACMP_NEG_CH7) || \ + ((x) == ACMP_NEG_1V25) || \ + ((x) == ACMP_NEG_2V5) || \ + ((x) == ACMP_NEG_VDD)) +#define IS_ACMP_WARM_UP_TIME_TYPE(x) (((x) == ACMP_4_PCLK) || \ + ((x) == ACMP_8_PCLK) || \ + ((x) == ACMP_16_PCLK) || \ + ((x) == ACMP_32_PCLK) || \ + ((x) == ACMP_64_PCLK) || \ + ((x) == ACMP_128_PCLK) || \ + ((x) == ACMP_256_PCLK) || \ + ((x) == ACMP_512_PCLK)) +#define IS_ACMP_HYSTSEL_TYPE(x) (((x) == ACMP_HYST_0) || \ + ((x) == ACMP_HYST_15) || \ + ((x) == ACMP_HYST_22) || \ + ((x) == ACMP_HYST_29) || \ + ((x) == ACMP_HYST_36) || \ + ((x) == ACMP_HYST_43) || \ + ((x) == ACMP_HYST_50) || \ + ((x) == ACMP_HYST_57)) +#define IS_ACMP_INACTVAL_TYPE(x) (((x) == ACMP_INACTVAL_LOW) || \ + ((x) == ACMP_INACTVAL_HIGH)) +#define IS_ACMP_EDGE_TYPE(x) (((x) == ACMP_EDGE_NONE) || \ + ((x) == ACMP_EDGE_FALL) || \ + ((x) == ACMP_EDGE_RISE) || \ + ((x) == ACMP_EDGE_ALL)) +#define IS_ACMP_OUT_FUNC_TYPE(x) (((x) == ACMP_OUT_DISABLE) || \ + ((x) == ACMP_OUT_ENABLE)) +#define IS_ACMP_INVERT_TYPE(x) (((x) == ACMP_GPIO_NO_INV) || \ + ((x) == ACMP_GPIO_INV)) +#define IS_ACMP_WARM_FUNC_TYPE(x) (((x) == ACMP_WARM_DISABLE) || \ + ((x) == ACMP_WARM_ENABLE)) +/** + * @} + */ + +/** @addtogroup ACMP_Public_Functions + * @{ + */ + +/** @addtogroup ACMP_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_acmp_init(acmp_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup ACMP_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state); +ald_status_t ald_acmp_set_interrupt_mask(acmp_handle_t *hperh, acmp_it_t it); +it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it); +it_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t it); +ald_status_t ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t it); +flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t flag); + +/** + * @} + */ + +/** @addtogroup ACMP_Public_Functions_Group3 + * @{ + */ +void ald_acmp_irq_handler(acmp_handle_t *hperh); +ald_status_t ald_acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config); +uint8_t ald_acmp_out_result(acmp_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +extern "C" +} +#endif + +#endif diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..d138f16c88d05e061735d8519e36772fec01a008 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h @@ -0,0 +1,572 @@ +/** + ****************************************************************************** + * @file ald_adc.h + * @brief Header file of ADC Module library. + * + * @version V1.0 + * @date 15 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ****************************************************************************** + */ + +#ifndef __ALD_ADC_H__ +#define __ALD_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" +#include "ald_pis.h" +#include "ald_timer.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Pubulic_Types ADC Pubulic Types + * @{ + */ + +/** + * @brief ADC State structures definition + */ +typedef enum +{ + ADC_STATE_RESET = 0x0, /**< ADC not yet initialized or disabled */ + ADC_STATE_READY = 0x1, /**< ADC peripheral ready for use */ + ADC_STATE_BUSY_INTERNAL = 0x2, /**< ADC is busy to internal process */ + ADC_STATE_TIMEOUT = 0x4, /**< TimeOut occurrence */ + ADC_STATE_ERROR = 0x10, /**< Internal error occurrence */ + ADC_STATE_NM_BUSY = 0x100, /**< Conversion on group normal is ongoing or can occur */ + ADC_STATE_NM_EOC = 0x200, /**< Conversion data available on group normal */ + ADC_STATE_IST_BUSY = 0x1000, /**< Conversion on group insert is ongoing or can occur */ + ADC_STATE_IST_EOC = 0x2000, /**< Conversion data available on group insert */ + ADC_STATE_AWD = 0x10000, /**< Out-of-window occurrence of analog watchdog */ +} adc_state_t; + +/** + *@brief ADC Error Code + */ +typedef enum +{ + ADC_ERROR_NONE = 0x0, /**< No error */ + ADC_ERROR_INTERNAL = 0x1, /**< ADC IP internal error*/ + ADC_ERROR_OVR = 0x2, /**< Overrun error */ + ADC_ERROR_DMA = 0x4, /**< DMA transfer error */ +} adc_error_t; + +/** + *@brief ADC data alignment + */ +typedef enum +{ + ADC_DATAALIGN_RIGHT = 0x0, /**< ADC data alignment right */ + ADC_DATAALIGN_LEFT = 0x1, /**< ADC data alignment left */ +} adc_align_t; + +/** + *@brief ADC config hannal trigger the EOC IT mode + */ +typedef enum +{ + ADC_NCHESEL_MODE_ALL = 0x0, /**< ADC set RCHE after convert sequence finish */ + ADC_NCHESEL_MODE_ONE = 0x1, /**< ADC set RCHE after one convert finish */ +} adc_nchesel_t; + +/** + *@brief ADC channels + */ +typedef enum +{ + ADC_CHANNEL_0 = 0x0, /**< ADC channel 0 */ + ADC_CHANNEL_1 = 0x1, /**< ADC channel 1 */ + ADC_CHANNEL_2 = 0x2, /**< ADC channel 2 */ + ADC_CHANNEL_3 = 0x3, /**< ADC channel 3 */ + ADC_CHANNEL_4 = 0x4, /**< ADC channel 4 */ + ADC_CHANNEL_5 = 0x5, /**< ADC channel 5 */ + ADC_CHANNEL_6 = 0x6, /**< ADC channel 6 */ + ADC_CHANNEL_7 = 0x7, /**< ADC channel 7 */ + ADC_CHANNEL_8 = 0x8, /**< ADC channel 8 */ + ADC_CHANNEL_9 = 0x9, /**< ADC channel 9 */ + ADC_CHANNEL_10 = 0xA, /**< ADC channel 10 */ + ADC_CHANNEL_11 = 0xB, /**< ADC channel 11 */ + ADC_CHANNEL_12 = 0xC, /**< ADC channel 12 */ + ADC_CHANNEL_13 = 0xD, /**< ADC channel 13 */ + ADC_CHANNEL_14 = 0xE, /**< ADC channel 14 */ + ADC_CHANNEL_15 = 0xF, /**< ADC channel 15 */ + ADC_CHANNEL_16 = 0x10, /**< ADC channel 16 */ + ADC_CHANNEL_17 = 0x11, /**< ADC channel 17 */ + ADC_CHANNEL_18 = 0x12, /**< ADC channel 18 */ + ADC_CHANNEL_19 = 0x13, /**< ADC channel 19 */ +} adc_channel_t; + +/** + *@brief ADC sampling times + */ +typedef enum +{ + ADC_SAMPLETIME_1 = 0x0, /**< ADC sampling times 1 clk */ + ADC_SAMPLETIME_2 = 0x1, /**< ADC sampling times 2 clk */ + ADC_SAMPLETIME_4 = 0x2, /**< ADC sampling times 4 clk */ + ADC_SAMPLETIME_15 = 0x3, /**< ADC sampling times 15 clk */ +} adc_samp_t; + +/** + *@brief ADC rank into normal group + */ +typedef enum +{ + ADC_NCH_RANK_1 = 0x1, /**< ADC normal channel rank 1 */ + ADC_NCH_RANK_2 = 0x2, /**< ADC normal channel rank 2 */ + ADC_NCH_RANK_3 = 0x3, /**< ADC normal channel rank 3 */ + ADC_NCH_RANK_4 = 0x4, /**< ADC normal channel rank 4 */ + ADC_NCH_RANK_5 = 0x5, /**< ADC normal channel rank 5 */ + ADC_NCH_RANK_6 = 0x6, /**< ADC normal channel rank 6 */ + ADC_NCH_RANK_7 = 0x7, /**< ADC normal channel rank 7 */ + ADC_NCH_RANK_8 = 0x8, /**< ADC normal channel rank 8 */ + ADC_NCH_RANK_9 = 0x9, /**< ADC normal channel rank 9 */ + ADC_NCH_RANK_10 = 0xA, /**< ADC normal channel rank 10 */ + ADC_NCH_RANK_11 = 0xB, /**< ADC normal channel rank 11 */ + ADC_NCH_RANK_12 = 0xC, /**< ADC normal channel rank 12 */ + ADC_NCH_RANK_13 = 0xD, /**< ADC normal channel rank 13 */ + ADC_NCH_RANK_14 = 0xE, /**< ADC normal channel rank 14 */ + ADC_NCH_RANK_15 = 0xF, /**< ADC normal channel rank 15 */ + ADC_NCH_RANK_16 = 0x10, /**< ADC normal channel rank 16 */ +} adc_nch_rank_t; + +/** + * @brief ADC rank into insert group + */ +typedef enum +{ + ADC_ICH_RANK_1 = 0x1, /**< ADC insert channel rank 1 */ + ADC_ICH_RANK_2 = 0x2, /**< ADC insert channel rank 2 */ + ADC_ICH_RANK_3 = 0x3, /**< ADC insert channel rank 3 */ + ADC_ICH_RANK_4 = 0x4, /**< ADC insert channel rank 4 */ +} adc_ich_rank_t; + +/** + * @brief ADC analog watchdog mode + */ +typedef enum +{ + ADC_ANAWTD_NONE = 0x0, /**< No watch dog */ + ADC_ANAWTD_SING_NM = 0x800200, /**< One normal channel watch dog */ + ADC_ANAWTD_SING_IST = 0x400200, /**< One inset channel Injec watch dog */ + ADC_ANAWTD_SING_NMIST = 0xC00200, /**< One normal and inset channel watch dog */ + ADC_ANAWTD_ALL_NM = 0x800000, /**< All normal channel watch dog */ + ADC_ANAWTD_ALL_IST = 0x400000, /**< All inset channel watch dog */ + ADC_ANAWTD_ALL_NMIST = 0xC00000, /**< All normal and inset channel watch dog */ +} adc_ana_wtd_t; + +/** + * @brief ADC Event type + */ +typedef enum +{ + ADC_AWD_EVENT = (1U << 0), /**< ADC analog watch dog event */ +} adc_event_type_t; + +/** + * @brief ADC interrupts definition + */ +typedef enum +{ + ADC_IT_NCH = (1U << 5), /**< ADC it normal */ + ADC_IT_AWD = (1U << 6), /**< ADC it awd */ + ADC_IT_ICH = (1U << 7), /**< ADC it insert */ + ADC_IT_OVR = (1U << 26), /**< ADC it overring */ +} adc_it_t; + +/** + * @brief ADC flags definition + */ +typedef enum +{ + ADC_FLAG_AWD = (1U << 0), /**perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK)) +#define ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK)) +#define ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET) +#define ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +/** + * @} + */ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +#define IS_ADC_ICH_RANK_TYPE(x) ((x) <= ADC_ICH_RANK_4) +#define IS_ADC_NCH_RANK_TYPE(x) ((x) <= ADC_NCH_RANK_16) +#define IS_ADC_SAMPLING_TIMES_TYPE(x) (((x) == ADC_SAMPLETIME_1) || \ + ((x) == ADC_SAMPLETIME_2) || \ + ((x) == ADC_SAMPLETIME_4) || \ + ((x) == ADC_SAMPLETIME_15)) +#define IS_ADC_CHANNELS_TYPE(x) ((x) <= ADC_CHANNEL_19) +#define IS_ADC_SCAN_MODE_TYPE(x) (((x) == DISABLE) || \ + ((x) == ENABLE)) +#define IS_ADC_DATA_ALIGN_TYPE(x) (((x) == ADC_DATAALIGN_RIGHT) || \ + ((x) == ADC_DATAALIGN_LEFT)) +#define IS_ADC_ANALOG_WTD_MODE_TYPE(x) (((x) == ADC_ANAWTD_NONE) || \ + ((x) == ADC_ANAWTD_SING_NM) || \ + ((x) == ADC_ANAWTD_SING_IST) || \ + ((x) == ADC_ANAWTD_SING_NMIST) || \ + ((x) == ADC_ANAWTD_ALL_NM) || \ + ((x) == ADC_ANAWTD_ALL_IST) || \ + ((x) == ADC_ANAWTD_ALL_NMIST)) +#define IS_ADC_IT_TYPE(x) (((x) == ADC_IT_NCH) || \ + ((x) == ADC_IT_AWD) || \ + ((x) == ADC_IT_ICH) || \ + ((x) == ADC_IT_OVR )) +#define IS_ADC_FLAGS_TYPE(x) (((x) == ADC_FLAG_AWD) || \ + ((x) == ADC_FLAG_NCH) || \ + ((x) == ADC_FLAG_ICH) || \ + ((x) == ADC_FLAG_OVR) || \ + ((x) == ADC_FLAG_NCHS) || \ + ((x) == ADC_FLAG_ICHS)) +#define IS_ADC_CLK_DIV_TYPE(x) (((x) == ADC_CKDIV_1) || \ + ((x) == ADC_CKDIV_2) || \ + ((x) == ADC_CKDIV_4) || \ + ((x) == ADC_CKDIV_8) || \ + ((x) == ADC_CKDIV_16) || \ + ((x) == ADC_CKDIV_32) || \ + ((x) == ADC_CKDIV_64) || \ + ((x) == ADC_CKDIV_128)) +#define IS_ADC_NEG_REF_VOLTAGE_TYPE(x) (((x) == ADC_NEG_REF_VSS ) || \ + ((x) == ADC_NEG_REF_VREFN )) +#define IS_POS_REF_VOLTAGE_TYPE(x) (((x) == ADC_POS_REF_VDD) || \ + ((x) == ADC_POS_REF_VREEFP) || \ + ((x) == ADC_POS_REF_VREEFP_BUF)) +#define IS_ADC_NCH_LEN_TYPE(x) ((x) <= ADC_NCH_LEN_16) +#define IS_ADC_NBR_OF_IST_TYPE(x) ((x) <= ADC_ICH_LEN_4) +#define IS_ADC_DISC_MODE_TYPE(x) (((x) == ADC_ALL_DISABLE) || \ + ((x) == ADC_NCH_DISC_EN) || \ + ((x) == ADC_ICH_DISC_EN)) +#define IS_ADC_DISC_NBR_TYPE(x) ((x) <= ADC_DISC_NBR_8) +#define IS_ADC_CONV_RES_TYPE(x) (((x) == ADC_CONV_RES_12) || \ + ((x) == ADC_CONV_RES_6) || \ + ((x) == ADC_CONV_RES_8) || \ + ((x) == ADC_CONV_RES_10)) +#define IS_ADC_TRIG_MODE_TYPE(x) (((x) == ADC_TRIG_SOFT) || \ + ((x) == ADC_TRIG_PIS) || \ + ((x) == ADC_TRIG_PIS_SOFT)) +#define IS_ADC_TYPE(x) (((x) == ADC0) || \ + ((x) == ADC1)) +#define IS_ADC_NCHESEL_MODE_TYPE(x) (((x) == ADC_NCHESEL_MODE_ALL) || \ + ((x) == ADC_NCHESEL_MODE_ONE)) +#define IS_ADC_EVENT_TYPE(x) ((x) == ADC_AWD_EVENT) +#define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xfff) +#define IS_HTR_TYPE(x) ((x) <= 0xfff) +#define IS_LTR_TYPE(x) ((x) <= 0xfff) +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions + * @{ + */ + +/** @addtogroup ADC_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_adc_init(adc_handle_t *hperh); +ald_status_t ald_adc_reset(adc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_adc_normal_start(adc_handle_t *hperh); +ald_status_t ald_adc_normal_stop(adc_handle_t *hperh); +ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); +ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout); +ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh); +ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh); +#ifdef ALD_DMA +ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh); +ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config); +#endif +uint32_t ald_adc_normal_get_value(adc_handle_t *hperh); +uint32_t ald_adc_get_vdd_value(adc_handle_t *hperh); +ald_status_t ald_adc_insert_start(adc_handle_t *hperh); +ald_status_t ald_adc_insert_stop(adc_handle_t *hperh); +ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); +ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh); +ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh); +uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_rank_t ih_rank); +void ald_adc_irq_handler(adc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group3 + * @{ + */ +ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config); +ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config); +ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config); +void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state); +it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it); +flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag); +void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group4 + * @{ + */ +uint32_t ald_adc_get_state(adc_handle_t *hperh); +uint32_t ald_adc_get_error(adc_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +extern "C" +} +#endif + +#endif /* __ALD_ADC_H */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h similarity index 30% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h index 67923d9a3a2fe9d48cdbf2a77655e1cb57e644f0..7bac14c70ecbba4ed9a32cebfb28916215252f96 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h @@ -35,44 +35,44 @@ extern "C" { /** @defgroup BKPC_Public_Macros BKPC Public Macros * @{ */ -#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0)) -#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55)) -#define BKPC_LRC_ENABLE() \ -do { \ - BKPC_UNLOCK(); \ - SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ - BKPC_LOCK(); \ -} while (0) -#define BKPC_LRC_DISABLE() \ -do { \ - BKPC_UNLOCK(); \ - CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ - BKPC_LOCK(); \ -} while (0) -#define BKPC_LOSM_ENABLE() \ -do { \ - BKPC_UNLOCK(); \ - SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \ - BKPC_LOCK(); \ -} while (0) -#define BKPC_LOSM_DISABLE() \ -do { \ - BKPC_UNLOCK(); \ - CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\ - BKPC_LOCK(); \ -} while (0) -#define BKPC_LOSC_ENABLE() \ -do { \ - BKPC_UNLOCK(); \ - SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \ - BKPC_LOCK(); \ -} while (0) -#define BKPC_LOSC_DISABLE() \ -do { \ - BKPC_UNLOCK(); \ - CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\ - BKPC_LOCK(); \ -} while (0) +#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0)) +#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55)) +#define BKPC_LRC_ENABLE() \ + do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ + BKPC_LOCK(); \ + } while (0) +#define BKPC_LRC_DISABLE() \ + do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ + BKPC_LOCK(); \ + } while (0) +#define BKPC_LOSM_ENABLE() \ + do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \ + BKPC_LOCK(); \ + } while (0) +#define BKPC_LOSM_DISABLE() \ + do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\ + BKPC_LOCK(); \ + } while (0) +#define BKPC_LOSC_ENABLE() \ + do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \ + BKPC_LOCK(); \ + } while (0) +#define BKPC_LOSC_DISABLE() \ + do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\ + BKPC_LOCK(); \ + } while (0) /** * @} */ @@ -85,10 +85,10 @@ do { \ */ typedef enum { - BKPC_LDO_OUTPUT_1_6 = 0x0, /**< 1.6V */ - BKPC_LDO_OUTPUT_1_3 = 0x1, /**< 1.3V */ - BKPC_LDO_OUTPUT_1_4 = 0x2, /**< 1.4V */ - BKPC_LDO_OUTPUT_1_5 = 0x4, /**< 1.5V */ + BKPC_LDO_OUTPUT_1_6 = 0x0, /**< 1.6V */ + BKPC_LDO_OUTPUT_1_3 = 0x1, /**< 1.3V */ + BKPC_LDO_OUTPUT_1_4 = 0x2, /**< 1.4V */ + BKPC_LDO_OUTPUT_1_5 = 0x4, /**< 1.5V */ } bkpc_ldo_output_t; /** @@ -96,22 +96,22 @@ typedef enum */ typedef enum { - BKPC_BOR_VOL_1_7 = 0x0, /**< 1.7V */ - BKPC_BOR_VOL_2_0 = 0x1, /**< 2.0V */ - BKPC_BOR_VOL_2_1 = 0x2, /**< 2.1V */ - BKPC_BOR_VOL_2_2 = 0x3, /**< 2.2V */ - BKPC_BOR_VOL_2_3 = 0x4, /**< 2.3V */ - BKPC_BOR_VOL_2_4 = 0x5, /**< 2.4V */ - BKPC_BOR_VOL_2_5 = 0x6, /**< 2.5V */ - BKPC_BOR_VOL_2_6 = 0x7, /**< 2.6V */ - BKPC_BOR_VOL_2_8 = 0x8, /**< 2.8V */ - BKPC_BOR_VOL_3_0 = 0x9, /**< 3.0V */ - BKPC_BOR_VOL_3_1 = 0xA, /**< 3.1V */ - BKPC_BOR_VOL_3_3 = 0xB, /**< 3.3V */ - BKPC_BOR_VOL_3_6 = 0xC, /**< 3.6V */ - BKPC_BOR_VOL_3_7 = 0xD, /**< 3.7V */ - BKPC_BOR_VOL_4_0 = 0xE, /**< 4.0V */ - BKPC_BOR_VOL_4_3 = 0xF, /**< 4.3V */ + BKPC_BOR_VOL_1_7 = 0x0, /**< 1.7V */ + BKPC_BOR_VOL_2_0 = 0x1, /**< 2.0V */ + BKPC_BOR_VOL_2_1 = 0x2, /**< 2.1V */ + BKPC_BOR_VOL_2_2 = 0x3, /**< 2.2V */ + BKPC_BOR_VOL_2_3 = 0x4, /**< 2.3V */ + BKPC_BOR_VOL_2_4 = 0x5, /**< 2.4V */ + BKPC_BOR_VOL_2_5 = 0x6, /**< 2.5V */ + BKPC_BOR_VOL_2_6 = 0x7, /**< 2.6V */ + BKPC_BOR_VOL_2_8 = 0x8, /**< 2.8V */ + BKPC_BOR_VOL_3_0 = 0x9, /**< 3.0V */ + BKPC_BOR_VOL_3_1 = 0xA, /**< 3.1V */ + BKPC_BOR_VOL_3_3 = 0xB, /**< 3.3V */ + BKPC_BOR_VOL_3_6 = 0xC, /**< 3.6V */ + BKPC_BOR_VOL_3_7 = 0xD, /**< 3.7V */ + BKPC_BOR_VOL_4_0 = 0xE, /**< 4.0V */ + BKPC_BOR_VOL_4_3 = 0xF, /**< 4.3V */ } bkpc_bor_vol_t; /** @@ -122,27 +122,27 @@ typedef enum * @defgroup BKPC_Private_Macros BKPC Private Macros * @{ */ -#define IS_BKPC_LDO_OUTPUT(x) (((x) == BKPC_LDO_OUTPUT_1_6) || \ +#define IS_BKPC_LDO_OUTPUT(x) (((x) == BKPC_LDO_OUTPUT_1_6) || \ ((x) == BKPC_LDO_OUTPUT_1_3) || \ ((x) == BKPC_LDO_OUTPUT_1_4) || \ ((x) == BKPC_LDO_OUTPUT_1_5)) -#define IS_BKPC_BOR_VOL(x) (((x) == BKPC_BOR_VOL_1_7) || \ - ((x) == BKPC_BOR_VOL_2_0) || \ - ((x) == BKPC_BOR_VOL_2_1) || \ - ((x) == BKPC_BOR_VOL_2_2) || \ - ((x) == BKPC_BOR_VOL_2_3) || \ - ((x) == BKPC_BOR_VOL_2_4) || \ - ((x) == BKPC_BOR_VOL_2_5) || \ - ((x) == BKPC_BOR_VOL_2_6) || \ - ((x) == BKPC_BOR_VOL_2_8) || \ - ((x) == BKPC_BOR_VOL_3_0) || \ - ((x) == BKPC_BOR_VOL_3_1) || \ - ((x) == BKPC_BOR_VOL_3_3) || \ - ((x) == BKPC_BOR_VOL_3_6) || \ - ((x) == BKPC_BOR_VOL_3_7) || \ - ((x) == BKPC_BOR_VOL_4_0) || \ - ((x) == BKPC_BOR_VOL_4_3)) -#define IS_BKPC_RAM_IDX(x) ((x) < 32) +#define IS_BKPC_BOR_VOL(x) (((x) == BKPC_BOR_VOL_1_7) || \ + ((x) == BKPC_BOR_VOL_2_0) || \ + ((x) == BKPC_BOR_VOL_2_1) || \ + ((x) == BKPC_BOR_VOL_2_2) || \ + ((x) == BKPC_BOR_VOL_2_3) || \ + ((x) == BKPC_BOR_VOL_2_4) || \ + ((x) == BKPC_BOR_VOL_2_5) || \ + ((x) == BKPC_BOR_VOL_2_6) || \ + ((x) == BKPC_BOR_VOL_2_8) || \ + ((x) == BKPC_BOR_VOL_3_0) || \ + ((x) == BKPC_BOR_VOL_3_1) || \ + ((x) == BKPC_BOR_VOL_3_3) || \ + ((x) == BKPC_BOR_VOL_3_6) || \ + ((x) == BKPC_BOR_VOL_3_7) || \ + ((x) == BKPC_BOR_VOL_4_0) || \ + ((x) == BKPC_BOR_VOL_4_3)) +#define IS_BKPC_RAM_IDX(x) ((x) < 32) /** * @} */ @@ -154,8 +154,8 @@ typedef enum * @{ */ /* control functions */ -extern void bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state); -extern void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state); +extern void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state); +extern void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state); /** * @} */ @@ -163,8 +163,8 @@ extern void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state); * @{ */ /* IO operation functions */ -extern void bkpc_write_ram(uint8_t idx, uint32_t value); -extern uint32_t bkpc_read_ram(uint8_t idx); +extern void ald_bkpc_write_ram(uint8_t idx, uint32_t value); +extern uint32_t ald_bkpc_read_ram(uint8_t idx); /** * @} */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h similarity index 73% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h index 896522b8613f863d8d31f2d169d7f594985c307a..283417d843bc0dcbb880716abf445c20b9b8749e 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h @@ -35,10 +35,10 @@ extern "C" { /** @addtogroup CALC_Public_Functions * @{ */ -extern uint32_t calc_sqrt(uint32_t data); -extern uint32_t calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder); -extern int32_t calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder); -extern flag_status_t calc_get_dz_status(void); +extern uint32_t ald_calc_sqrt(uint32_t data); +extern uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder); +extern int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder); +extern flag_status_t ald_calc_get_dz_status(void); /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h new file mode 100644 index 0000000000000000000000000000000000000000..471c20e6acd2067da9b0fe9159c6fb904a8f6690 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h @@ -0,0 +1,491 @@ +/** + ****************************************************************************** + * @file ald_can.h + * @brief Header file of CAN Module driver. + * + * @version V1.0 + * @date 16 Apr 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ****************************************************************************** + */ + +#ifndef __ALD_CAN_H +#define __ALD_CAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/** @defgroup CAN_Public_Types CAN Public Types + * @{ + */ +/** + * @brief ALD State structures definition + */ +typedef enum +{ + CAN_STATE_RESET = 0x00, /**< CAN not yet initialized or disabled */ + CAN_STATE_READY = 0x01, /**< CAN initialized and ready for use */ + CAN_STATE_BUSY = 0x02, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX = 0x11, /**< CAN process is ongoing */ + CAN_STATE_BUSY_RX = 0x21, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX_RX = 0x31, /**< CAN process is ongoing */ + CAN_STATE_TIMEOUT = 0x03, /**< CAN in Timeout state */ + CAN_STATE_ERROR = 0x04, /**< CAN error state */ +} can_state_t; + +/** + * @brief CAN Error Code + */ +typedef enum +{ + CAN_ERROR_NONE = 0x00, /**< No error */ + CAN_ERROR_EWG = 0x01, /**< EWG error */ + CAN_ERROR_EPV = 0x02, /**< EPV error */ + CAN_ERROR_BOF = 0x04, /**< BOF error */ + CAN_ERROR_STF = 0x08, /**< Stuff error */ + CAN_ERROR_FOR = 0x10, /**< Form error */ + CAN_ERROR_ACK = 0x20, /**< Acknowledgment error */ + CAN_ERROR_BR = 0x40, /**< Bit recessive */ + CAN_ERROR_BD = 0x80, /**< LEC dominant */ + CAN_ERROR_CRC = 0x100, /**< LEC transfer error */ + CAN_ERROR_UNK = 0x200, /**< Unknown error */ +} can_error_t; + +/** + * @brief CAN Operating Mode + */ +typedef enum +{ + CAN_MODE_NORMAL = 0x00, /**< Normal mode */ + CAN_MODE_LOOPBACK = 0x01, /**< Loopback mode */ + CAN_MODE_SILENT = 0x02, /**< Silent mode */ + CAN_MODE_SILENT_LOOPBACK = 0x03, /**< Loopback combined with silent mode */ +} can_operate_mode_t; + +/** + * @brief CAN Synchronization Jump Width + */ +typedef enum +{ + CAN_SJW_1 = 0x0, /**< 1 time quantum */ + CAN_SJW_2 = 0x1, /**< 2 time quantum */ + CAN_SJW_3 = 0x2, /**< 3 time quantum */ + CAN_SJW_4 = 0x3, /**< 4 time quantum */ +} can_sjw_t; + +/** + * @brief CAN Time Quantum in Bit Segment 1 + */ +typedef enum +{ + CAN_SEG1_1 = 0x0, /**< 1 time quantum */ + CAN_SEG1_2 = 0x1, /**< 2 time quantum */ + CAN_SEG1_3 = 0x2, /**< 3 time quantum */ + CAN_SEG1_4 = 0x3, /**< 4 time quantum */ + CAN_SEG1_5 = 0x4, /**< 5 time quantum */ + CAN_SEG1_6 = 0x5, /**< 6 time quantum */ + CAN_SEG1_7 = 0x6, /**< 7 time quantum */ + CAN_SEG1_8 = 0x7, /**< 8 time quantum */ + CAN_SEG1_9 = 0x8, /**< 9 time quantum */ + CAN_SEG1_10 = 0x9, /**< 10 time quantum */ + CAN_SEG1_11 = 0xA, /**< 11 time quantum */ + CAN_SEG1_12 = 0xB, /**< 12 time quantum */ + CAN_SEG1_13 = 0xC, /**< 13 time quantum */ + CAN_SEG1_14 = 0xD, /**< 14 time quantum */ + CAN_SEG1_15 = 0xE, /**< 15 time quantum */ + CAN_SEG1_16 = 0xF, /**< 16 time quantum */ +} can_seg1_t; + +/** + * @brief CAN Time Quantum in Bit Segment 2 + */ +typedef enum +{ + CAN_SEG2_1 = 0x0, /**< 1 time quantum */ + CAN_SEG2_2 = 0x1, /**< 2 time quantum */ + CAN_SEG2_3 = 0x2, /**< 3 time quantum */ + CAN_SEG2_4 = 0x3, /**< 4 time quantum */ + CAN_SEG2_5 = 0x4, /**< 5 time quantum */ + CAN_SEG2_6 = 0x5, /**< 6 time quantum */ + CAN_SEG2_7 = 0x6, /**< 7 time quantum */ + CAN_SEG2_8 = 0x7, /**< 8 time quantum */ +} can_seg2_t; + +/** + * @brief CAN Filter Mode + */ +typedef enum +{ + CAN_FILTER_MODE_MASK = 0x0, /**< Identifier mask mode */ + CAN_FILTER_MODE_LIST = 0x1, /**< Identifier list mode */ +} can_filter_mode_t; + +/** + * @brief CAN Filter Scale + */ +typedef enum +{ + CAN_FILTER_SCALE_16 = 0x0, /**< Two 16-bit filters */ + CAN_FILTER_SCALE_32 = 0x1, /**< One 32-bit filter */ +} can_filter_scale_t; + +/** + * @brief CAN Filter fifo + */ +typedef enum +{ + CAN_FILTER_FIFO0 = 0x0, /**< FIFO 0 assignment for filter */ + CAN_FILTER_FIFO1 = 0x1, /**< FIFO 1 assignment for filter */ +} can_filter_fifo_t; + +/** + * @brief CAN Identifier Type + */ +typedef enum +{ + CAN_ID_STD = 0x0, /**< Standard Id */ + CAN_ID_EXT = 0x1, /**< Extended Id */ +} can_id_type_t; + +/** + * @brief CAN Remote Transmission Request + */ +typedef enum +{ + CAN_RTR_DATA = 0x0, /**< Data frame */ + CAN_RTR_REMOTE = 0x1, /**< Remote frame */ +} can_remote_req_t; + +/** + * @brief CAN Transmit Constants + */ +typedef enum +{ + CAN_TX_MAILBOX_0 = 0x0, /**< TX mailbox index 0 */ + CAN_TX_MAILBOX_1 = 0x1, /**< TX mailbox index 1 */ + CAN_TX_MAILBOX_2 = 0x2, /**< TX mailbox index 2 */ + CAN_TX_MAILBOX_NONE = 0x3, /**< MailBox can't be used */ +} can_tx_mailbox_t; + +/** + * @brief CAN Receive fifo Number + */ +typedef enum +{ + CAN_RX_FIFO0 = 0x0, /**< CAN fifo 0 used to receive */ + CAN_RX_FIFO1 = 0x1, /**< CAN fifo 1 used to receive */ +} can_rx_fifo_t; + +/** + * @brief CAN Flags + */ +typedef enum +{ + CAN_FLAG_SLPS = (1U << 1), /**< Sleep acknowledge flag */ + CAN_FLAG_ERR = (1U << 2), /**< Error flag*/ + CAN_FLAG_WK = (1U << 3), /**< Wake up flag */ + CAN_FLAG_SLP = (1U << 4), /**< Sleep acknowledge flag */ + CAN_FLAG_M0REQC = (1U << 20) | (1U << 0), /**< Request MailBox0 flag */ + CAN_FLAG_M0TXC = (1U << 20) | (1U << 1), /**< Transmission OK MailBox0 flag */ + CAN_FLAG_M1REQC = (1U << 20) | (1U << 8), /**< Request MailBox1 flag */ + CAN_FLAG_M1TXC = (1U << 20) | (1U << 9), /**< Transmission OK MailBox1 flag */ + CAN_FLAG_M2REQC = (1U << 20) | (1U << 16), /**< Request MailBox2 flag */ + CAN_FLAG_M2TXC = (1U << 20) | (1U << 17), /**< Transmission OK MailBox2 flag */ + CAN_FLAG_TXM0 = (1U << 20) | (1U << 26), /**< Transmit mailbox 0 empty flag */ + CAN_FLAG_TXM1 = (1U << 20) | (1U << 27), /**< Transmit mailbox 1 empty flag */ + CAN_FLAG_TXM2 = (1U << 20) | (1U << 28), /**< Transmit mailbox 2 empty flag */ + CAN_FLAG_FF0 = (2U << 20) | (1U << 3), /**< FIFO 0 Full flag */ + CAN_FLAG_FOV0 = (2U << 20) | (1U << 4), /**< FIFO 0 Overrun flag */ + CAN_FLAG_FF1 = (3U << 20) | (1U << 3), /**< FIFO 1 Full flag */ + CAN_FLAG_FOV1 = (3U << 20) | (1U << 4), /**< FIFO 1 Overrun flag */ + CAN_FLAG_WARN = (4U << 20) | (1U << 0), /**< Error warning flag */ + CAN_FLAG_PERR = (4U << 20) | (1U << 1), /**< Error passive flag */ + CAN_FLAG_BOF = (4U << 20) | (1U << 2), /**< Bus-Off flag */ +} can_flag_t; + +/** + * @brief CAN Interrupts + */ +typedef enum +{ + CAN_IT_TXM = (1U << 0), /**< Transmit mailbox empty interrupt bit */ + CAN_IT_FP0 = (1U << 1), /**< FIFO0 message pending interrupt bit */ + CAN_IT_FF0 = (1U << 2), /**< FIFO0 full interrupt bit */ + CAN_IT_FOV0 = (1U << 3), /**< FIFO0 overrun interrupt bit */ + CAN_IT_FP1 = (1U << 4), /**< FIFO1 message pending interrupt bit */ + CAN_IT_FF1 = (1U << 5), /**< FIFO1 full interrupt bit */ + CAN_IT_FOV1 = (1U << 6), /**< FIFO1 overrun interrupt bit */ + CAN_IT_WARN = (1U << 8), /**< Error warning interrupt bit */ + CAN_IT_PERR = (1U << 9), /**< Error passive interrupt bit */ + CAN_IT_BOF = (1U << 10), /**< Bus-off interrupt bit */ + CAN_IT_PRERR = (1U << 11), /**< Last error code interrupt bit */ + CAN_IT_ERR = (1U << 15), /**< Error interrupt bit */ + CAN_IT_WK = (1U << 16), /**< wake-up interrupt bit */ + CAN_IT_SLP = (1U << 17), /**< sleep interrupt bit */ +} can_it_t; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct +{ + uint32_t id_high; /**< Specifies the filter identification number */ + uint32_t id_low; /**< Specifies the filter identification number */ + uint32_t mask_id_high; /**< Specifies the filter mask number or identification number */ + uint32_t mask_id_low; /**< Specifies the filter mask number or identification number */ + can_filter_fifo_t fifo; /**< Specifies the fifo (0 or 1) which will be assigned to the filter. */ + uint32_t number; /**< Specifies the filter which will be initialized. */ + can_filter_mode_t mode; /**< Specifies the filter mode to be initialized. */ + can_filter_scale_t scale; /**< Specifies the filter scale. */ + type_func_t active; /**< Enable or disable the filter. */ + uint32_t bank_number; /**< Select the start slave bank filter. */ +} can_filter_t; + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t psc; /**< Specifies the length of a time quantum. */ + can_operate_mode_t mode; /**< Specifies the CAN operating mode. */ + can_sjw_t sjw; /**< Specifies the maximum number of time quanta the CAN hardware is + allowed to lengthen or shorten a bit to perform resynchronization. */ + can_seg1_t seg1; /**< Specifies the number of time quanta in Bit Segment 1. */ + can_seg2_t seg2; /**< Specifies the number of time quanta in Bit Segment 2. */ + type_func_t ttcm; /**< Enable or disable the time triggered communication mode. */ + type_func_t abom; /**< Enable or disable the automatic bus-off management. */ + type_func_t awk; /**< Enable or disable the automatic wake-up mode. */ + type_func_t artx; /**< Enable or disable the non-automatic retransmission mode. */ + type_func_t rfom; /**< Enable or disable the Receive fifo Locked mode. */ + type_func_t txmp; /**< Enable or disable the transmit fifo priority. */ +} can_init_t; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct +{ + uint32_t std; /**< Specifies the standard identifier. */ + uint32_t ext; /**< Specifies the extended identifier. */ + can_id_type_t type; /**< Specifies the type of identifier for the message that will be transmitted. */ + can_remote_req_t rtr; /**< Specifies the type of frame for the message that will be transmitted. */ + uint32_t len; /**< Specifies the length of the frame that will be transmitted. */ + uint8_t data[8]; /**< Contains the data to be transmitted. */ +} can_tx_msg_t; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct +{ + uint32_t std; /**< Specifies the standard identifier. */ + uint32_t ext; /**< Specifies the extended identifier. */ + can_id_type_t type; /**< Specifies the type of identifier for the message that will be received. */ + can_remote_req_t rtr; /**< Specifies the type of frame for the received message. */ + uint32_t len; /**< Specifies the length of the frame that will be received. */ + uint8_t data[8]; /**< Contains the data to be received. */ + uint32_t fmi; /**< Specifies the index of the filter the message stored in the mailbox passes through. */ + can_rx_fifo_t num; /**< Specifies the receive fifo number. */ +} can_rx_msg_t; + +/** + * @brief CAN handle Structure definition + */ +typedef struct can_handle_s +{ + CAN_TypeDef *perh; /**< Register base address */ + can_init_t init; /**< CAN required parameters */ + can_rx_msg_t *rx_msg; /**< Pointer to receive message */ + lock_state_t lock; /**< CAN locking object */ + can_state_t state; /**< CAN communication state */ + can_error_t err; /**< CAN Error code */ + + void (*tx_cplt_cbk)(struct can_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct can_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct can_handle_s *arg); /**< error callback */ +} can_handle_t; +/** + * @} + */ + +/** @defgroup CAN_Public_Macro CAN Public Macros + * @{ + */ +#define CAN_RESET_HANDLE_STATE(x) ((x)->state = CAN_STATE_RESET) +#define CAN_RX_MSG_PENDING(x, y) (((y) == CAN_RX_FIFO0) ? \ + (READ_BIT((x)->perh->RXF0, CAN_RXF0_PEND_MSK)) : (READ_BIT((x)->perh->RXF1, CAN_RXF1_PEND_MSK))) +#define CAN_DBG_FREEZE(x, y) (MODIFY_REG((x)->perh->CON, CAN_CON_DBGSTP_MSK, (y) << CAN_CON_DBGSTP_POS)) +#define CAN_TX_STAMP_ENABLE(x) (SET_BIT(hperh->perh->TxMailBox[(x)].TXFCON, CAN_TXFCON0_TXGT_MSK)) +#define CAN_TX_STAMP_DISABLE(x) (CLEAR_BIT(hperh->perh->TxMailBox[(x)].TXFCON, CAN_TXFCON0_TXGT_MSK)) +/** + * @} + */ + +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ +#define IS_CAN_ALL(x) ((x) == CAN0) +#define IS_CAN_FILTER_NUMBER(x) ((x) <= 13) +#define IS_CAN_MODE(x) (((x) == CAN_MODE_NORMAL) || \ + ((x) == CAN_MODE_LOOPBACK) || \ + ((x) == CAN_MODE_SILENT) || \ + ((x) == CAN_MODE_SILENT_LOOPBACK)) +#define IS_CAN_SJW(x) (((x) == CAN_SJW_1) || \ + ((x) == CAN_SJW_2) || \ + ((x) == CAN_SJW_3) || \ + ((x) == CAN_SJW_4)) +#define IS_CAN_BS1(x) ((x) <= CAN_SEG1_16) +#define IS_CAN_BS2(x) ((x) <= CAN_SEG2_8) +#define IS_CAN_FILTER_MODE(x) (((x) == CAN_FILTER_MODE_MASK) || \ + ((x) == CAN_FILTER_MODE_LIST)) +#define IS_CAN_FILTER_SCALE(x) (((x) == CAN_FILTER_SCALE_16) || \ + ((x) == CAN_FILTER_SCALE_32)) +#define IS_CAN_FILTER_FIFO(x) (((x) == CAN_FILTER_FIFO0) || \ + ((x) == CAN_FILTER_FIFO1)) +#define IS_CAN_IDTYPE(x) (((x) == CAN_ID_STD) || \ + ((x) == CAN_ID_EXT)) +#define IS_CAN_RTR(x) (((x) == CAN_RTR_DATA) || ((x) == CAN_RTR_REMOTE)) +#define IS_CAN_FIFO(x) (((x) == CAN_RX_FIFO0) || ((x) == CAN_RX_FIFO1)) +#define IS_CAN_BANKNUMBER(x) ((x) <= 28) +#define IS_CAN_TX_MAILBOX(x) ((x) <= CAN_TX_MAILBOX_NONE) +#define IS_CAN_STDID(x) ((x) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(x) ((x) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DATA_LEN(x) ((x) <= ((uint8_t)0x08)) +#define IS_CAN_PRESCALER(x) (((x) >= 1) && ((x) <= 1024)) +#define IS_CAN_GET_FLAG(x) (((x) == CAN_FLAG_SLPS) || \ + ((x) == CAN_FLAG_ERR) || \ + ((x) == CAN_FLAG_WK) || \ + ((x) == CAN_FLAG_SLP) || \ + ((x) == CAN_FLAG_M0REQC) || \ + ((x) == CAN_FLAG_M0TXC) || \ + ((x) == CAN_FLAG_M1REQC) || \ + ((x) == CAN_FLAG_M1TXC) || \ + ((x) == CAN_FLAG_M2REQC) || \ + ((x) == CAN_FLAG_M2TXC) || \ + ((x) == CAN_FLAG_TXM0) || \ + ((x) == CAN_FLAG_TXM1) || \ + ((x) == CAN_FLAG_TXM2) || \ + ((x) == CAN_FLAG_FF0) || \ + ((x) == CAN_FLAG_FOV0) || \ + ((x) == CAN_FLAG_FF1) || \ + ((x) == CAN_FLAG_FOV1) || \ + ((x) == CAN_FLAG_WARN) || \ + ((x) == CAN_FLAG_PERR) || \ + ((x) == CAN_FLAG_BOF)) +#define IS_CAN_CLEAR_FLAG(x) (((x) == CAN_FLAG_ERR) || \ + ((x) == CAN_FLAG_WK) || \ + ((x) == CAN_FLAG_SLP) || \ + ((x) == CAN_FLAG_M0REQC) || \ + ((x) == CAN_FLAG_M1REQC) || \ + ((x) == CAN_FLAG_M2REQC) || \ + ((x) == CAN_FLAG_FF0) || \ + ((x) == CAN_FLAG_FOV0) || \ + ((x) == CAN_FLAG_FF1) || \ + ((x) == CAN_FLAG_FOV1)) +#define IS_CAN_IT(x) (((x) == CAN_IT_TXM) || \ + ((x) == CAN_IT_FP0) || \ + ((x) == CAN_IT_FF0) || \ + ((x) == CAN_IT_FOV0) || \ + ((x) == CAN_IT_FP1) || \ + ((x) == CAN_IT_FF1) || \ + ((x) == CAN_IT_FOV1) || \ + ((x) == CAN_IT_WARN) || \ + ((x) == CAN_IT_PERR) || \ + ((x) == CAN_IT_BOF) || \ + ((x) == CAN_IT_PRERR) || \ + ((x) == CAN_IT_ERR) || \ + ((x) == CAN_IT_WK) || \ + ((x) == CAN_IT_SLP)) +#define CAN_TIMEOUT_VALUE 100 +#define CAN_STATE_TX_MASK (1U << 4) +#define CAN_STATE_RX_MASK (1U << 5) +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions + * @{ + */ + +/** @addtogroup CAN_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void ald_can_reset(can_handle_t *hperh); +ald_status_t ald_can_init(can_handle_t *hperh); +ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config); +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +ald_status_t ald_can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout); +ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg); +ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout); +ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg); +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions_Group3 + * @{ + */ +/* Control function */ +ald_status_t ald_can_sleep(can_handle_t *hperh); +ald_status_t ald_can_wake_up(can_handle_t *hperh); +void ald_can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box); +void ald_can_irq_handler(can_handle_t *hperh); +type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box); +void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state); +it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it); +flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag); +void ald_can_clear_flag_status(can_handle_t *hperh, can_flag_t flag); +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions_Group4 + * @{ + */ +/* State and Error functions */ +can_state_t ald_can_get_state(can_handle_t *hperh); +can_error_t ald_can_get_error(can_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_CAN_H */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h new file mode 100644 index 0000000000000000000000000000000000000000..5bcae0bd075aa20383264f2e98295db69d5770b0 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h @@ -0,0 +1,653 @@ +/** + ********************************************************************************* + * + * @file ald_cmu.h + * @brief Header file of CMU module driver. + * + * @version V1.0 + * @date 22 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_CMU_H__ +#define __ALD_CMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_syscfg.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CMU + * @{ + */ + +/** @defgroup CMU_Public_Macros CMU Public Macros + * @{ + */ +#define CMU_LOSC_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LOSC_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LRC_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LRC_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_ULRC_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_ULRC_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) + +/* Low power mode control */ +#define CMU_LP_LRC_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LP_LRC_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LP_LOSC_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LP_LOSC_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LP_HRC_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LP_HRC_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LP_HOSC_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define CMU_LP_HOSC_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +/** + * @} + */ + + +/** @defgroup CMU_Public_Types CMU Public Types + * @{ + */ +/** + * @brief CMU state structure definition + */ +typedef enum +{ + CMU_CLOCK_HRC = 0x1, /**< HRC */ + CMU_CLOCK_LRC = 0x2, /**< LRC */ + CMU_CLOCK_LOSC = 0x3, /**< LOSC */ + CMU_CLOCK_PLL1 = 0x4, /**< PLL1 */ + CMU_CLOCK_HOSC = 0x5, /**< HOSC */ +} cmu_clock_t; + +/** + * @brief PLL1 output clock + */ +typedef enum +{ + CMU_PLL1_OUTPUT_32M = 0x0, /**< x8 (32MHz) */ + CMU_PLL1_OUTPUT_48M = 0x1, /**< x12 (48MHz) */ +} cmu_pll1_output_t; + +/** + * @brief PLL1 referance clock + */ +typedef enum +{ + CMU_PLL1_INPUT_HRC_6 = 0x0, /**< HRC / 6 */ + CMU_PLL1_INPUT_PLL2 = 0x1, /**< PLL2 */ + CMU_PLL1_INPUT_HOSC = 0x2, /**< HOSC / 1 */ + CMU_PLL1_INPUT_HOSC_2 = 0x3, /**< HOSC / 2 */ + CMU_PLL1_INPUT_HOSC_3 = 0x4, /**< HOSC / 3 */ + CMU_PLL1_INPUT_HOSC_4 = 0x5, /**< HOSC / 4 */ + CMU_PLL1_INPUT_HOSC_5 = 0x6, /**< HOSC / 5 */ + CMU_PLL1_INPUT_HOSC_6 = 0x7, /**< HOSC / 6 */ +} cmu_pll1_input_t; + +/** + * @brief HOSC range + */ +typedef enum +{ + CMU_HOSC_2M = 0x0, + CMU_HOSC_4M = 0x1, + CMU_HOSC_8M = 0x2, + CMU_HOSC_16M = 0x3, + CMU_HOSC_24M = 0x4, +} cmu_hosc_range_t; + +/** + * @brief Auto-calibrate input + */ +typedef enum +{ + CMU_AUTO_CALIB_INPUT_LOSE = 0x0, + CMU_AUTO_CALIB_INPUT_HOSE = 0x1, +} cmu_auto_calib_input_t; + +/** + * @brief Auto-calibrate output + */ +typedef enum +{ + CMU_AUTO_CALIB_OUTPUT_24M = 0x0, + CMU_AUTO_CALIB_OUTPUT_2M = 0x1, +} cmu_auto_calib_output_t; + +/** + * @brief Frequency division select bit + */ +typedef enum +{ + CMU_DIV_1 = 0x0, /**< Division by 1 */ + CMU_DIV_2 = 0x1, /**< Division by 2 */ + CMU_DIV_4 = 0x2, /**< Division by 4 */ + CMU_DIV_8 = 0x3, /**< Division by 8 */ + CMU_DIV_16 = 0x4, /**< Division by 16 */ + CMU_DIV_32 = 0x5, /**< Division by 32 */ + CMU_DIV_64 = 0x6, /**< Division by 64 */ + CMU_DIV_128 = 0x7, /**< Division by 128 */ + CMU_DIV_256 = 0x8, /**< Division by 256 */ + CMU_DIV_512 = 0x9, /**< Division by 512 */ + CMU_DIV_1024 = 0xA, /**< Division by 1024 */ + CMU_DIV_2048 = 0xB, /**< Division by 2048 */ + CMU_DIV_4096 = 0xC, /**< Division by 4096 */ +} cmu_div_t; + +/** + * @brief Bus type + */ +typedef enum +{ + CMU_HCLK_1 = 0x0, /**< AHB1 bus */ + CMU_SYS = 0x1, /**< SYS bus */ + CMU_PCLK_1 = 0x2, /**< APB1 bus */ + CMU_PCLK_2 = 0x3, /**< APB2 bus */ +} cmu_bus_t; + +/** + * @brief Output high clock select + */ +typedef enum +{ + CMU_OUTPUT_HIGH_SEL_HOSC = 0x0, /**< Select HOSC */ + CMU_OUTPUT_HIGH_SEL_LOSC = 0x1, /**< Select LOSC */ + CMU_OUTPUT_HIGH_SEL_HRC = 0x2, /**< Select HRC */ + CMU_OUTPUT_HIGH_SEL_LRC = 0x3, /**< Select LRC */ + CMU_OUTPUT_HIGH_SEL_HOSM = 0x4, /**< Select HOSM */ + CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5, /**< Select PLL1 */ + CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6, /**< Select PLL2 */ + CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7, /**< Select SYSCLK */ +} cmu_output_high_sel_t; + +/** + * @brief Output frequency division + */ +typedef enum +{ + CMU_OUTPUT_DIV_1 = 0x0, /**< Division by 1 */ + CMU_OUTPUT_DIV_2 = 0x1, /**< Division by 2 */ + CMU_OUTPUT_DIV_4 = 0x2, /**< Division by 4 */ + CMU_OUTPUT_DIV_8 = 0x3, /**< Division by 8 */ + CMU_OUTPUT_DIV_16 = 0x4, /**< Division by 16 */ + CMU_OUTPUT_DIV_32 = 0x5, /**< Division by 32 */ + CMU_OUTPUT_DIV_64 = 0x6, /**< Division by 64 */ + CMU_OUTPUT_DIV_128 = 0x7, /**< Division by 128 */ +} cmu_output_high_div_t; + +/** + * @brief Output low clock select + */ +typedef enum +{ + CMU_OUTPUT_LOW_SEL_LOSC = 0x0, /**< Select LOSC */ + CMU_OUTPUT_LOW_SEL_LRC = 0x1, /**< Select LRC */ + CMU_OUTPUT_LOW_SEL_LOSM = 0x2, /**< Select LOSM */ + CMU_OUTPUT_LOW_SEL_BUZZ = 0x3, /**< Select BUZZ */ + CMU_OUTPUT_LOW_SEL_ULRC = 0x4, /**< Select ULRC */ +} cmu_output_low_sel_t; + +/** + * @brief BUZZ frequency division + */ +typedef enum +{ + CMU_BUZZ_DIV_2 = 0x0, /**< Division by 2 */ + CMU_BUZZ_DIV_4 = 0x1, /**< Division by 4 */ + CMU_BUZZ_DIV_8 = 0x2, /**< Division by 8 */ + CMU_BUZZ_DIV_16 = 0x3, /**< Division by 16 */ + CMU_BUZZ_DIV_32 = 0x4, /**< Division by 32 */ + CMU_BUZZ_DIV_64 = 0x5, /**< Division by 64 */ + CMU_BUZZ_DIV_128 = 0x6, /**< Division by 128 */ + CMU_BUZZ_DIV_256 = 0x7, /**< Division by 256 */ +} cmu_buzz_div_t; + +/** + * @brief Low power peripheral clock select + */ +typedef enum +{ + CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0, /**< Select PCLK2 */ + CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1, /**< Select PLL1 */ + CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2, /**< Select PLL2 */ + CMU_LP_PERH_CLOCK_SEL_HRC = 0x3, /**< Select HRC */ + CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4, /**< Select HOSC */ + CMU_LP_PERH_CLOCK_SEL_LRC = 0x5, /**< Select LRC */ + CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6, /**< Select LOSC */ + CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7, /**< Select ULRC */ + CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8, /**< Select HRC down to 1MHz */ + CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9, /**< Select HOSC down to 1MHz */ + CMU_LP_PERH_CLOCK_SEL_LOSM = 0xA, /**< Select LOSM */ + CMU_LP_PERH_CLOCK_SEL_HOSM = 0xB, /**< Select HOSM */ +} cmu_lp_perh_clock_sel_t; + +/** + * @brief LCD clock select + */ +typedef enum +{ + CMU_LCD_SEL_LOSM = 0x0, /**< Select LOSM */ + CMU_LCD_SEL_LOSC = 0x1, /**< Select LOSC */ + CMU_LCD_SEL_LRC = 0x2, /**< Select LRC */ + CMU_LCD_SEL_ULRC = 0x3, /**< Select ULRC */ + CMU_LCD_SEL_HRC_1M = 0x4, /**< Select HRC down to 1MHz */ + CMU_LCD_SEL_HOSC_1M = 0x5, /**< Select HOSC down to 1MHz */ +} cmu_lcd_clock_sel_t; + +/** + * @brief Peripheral clock enable/disable + * @note ES32F065x: + * AD16C4T0--TIMER0 + * GP16C4T0--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + * + * ES32F033x: + * ES32F093x: + * GP16C4T0--TIMER0 + * GP16C4T1--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + */ +typedef enum +{ + CMU_PERH_GPIO = (1U << 0), /**< GPIO */ + CMU_PERH_CRC = (1U << 1), /**< CRC */ + CMU_PERH_CALC = (1U << 2), /**< CALC */ + CMU_PERH_CRYPT = (1U << 3), /**< CRYPT */ + CMU_PERH_TRNG = (1U << 4), /**< TRNG */ + CMU_PERH_PIS = (1U << 5), /**< PIS */ + CMU_PERH_TIMER0 = (1U << 0) | (1U << 27), /**< TIMER0 */ + CMU_PERH_TIMER1 = (1U << 1) | (1U << 27), /**< TIMER1 */ + CMU_PERH_TIMER2 = (1U << 2) | (1U << 27), /**< TIMER2 */ + CMU_PERH_TIMER3 = (1U << 3) | (1U << 27), /**< TIMER3 */ + CMU_PERH_TIMER4 = (1U << 4) | (1U << 27), /**< TIMER4 */ + CMU_PERH_TIMER5 = (1U << 5) | (1U << 27), /**< TIMER5 */ + CMU_PERH_TIMER6 = (1U << 6) | (1U << 27), /**< TIMER6 */ + CMU_PERH_TIMER7 = (1U << 7) | (1U << 27), /**< TIMER7 */ + CMU_PERH_UART0 = (1U << 8) | (1U << 27), /**< UART0 */ + CMU_PERH_UART1 = (1U << 9) | (1U << 27), /**< UART1 */ + CMU_PERH_UART2 = (1U << 10) | (1U << 27), /**< UART2 */ + CMU_PERH_UART3 = (1U << 11) | (1U << 27), /**< UART3 */ + CMU_PERH_USART0 = (1U << 12) | (1U << 27), /**< USART0 */ + CMU_PERH_USART1 = (1U << 13) | (1U << 27), /**< USART1 */ + CMU_PERH_SPI0 = (1U << 16) | (1U << 27), /**< SPI0 */ + CMU_PERH_SPI1 = (1U << 17) | (1U << 27), /**< SPI1 */ + CMU_PERH_SPI2 = (1U << 18) | (1U << 27), /**< SPI2 */ + CMU_PERH_I2C0 = (1U << 20) | (1U << 27), /**< I2C0 */ + CMU_PERH_I2C1 = (1U << 21) | (1U << 27), /**< I2C1 */ + CMU_PERH_CAN = (1U << 24) | (1U << 27), /**< CAN */ + CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28), /**< LPTIM0 */ + CMU_PERH_LPUART0 = (1U << 2) | (1U << 28), /**< LPUART0 */ + CMU_PERH_ADC0 = (1U << 4) | (1U << 28), /**< ADC0 */ + CMU_PERH_ADC1 = (1U << 5) | (1U << 28), /**< ADC1 */ + CMU_PERH_ACMP0 = (1U << 6) | (1U << 28), /**< ACMP0 */ + CMU_PERH_ACMP1 = (1U << 7) | (1U << 28), /**< ACMP1 */ + CMU_PERH_OPAMP = (1U << 8) | (1U << 28), /**< OPAMP */ + CMU_PERH_DAC0 = (1U << 9) | (1U << 28), /**< DAC0 */ + CMU_PERH_WWDT = (1U << 12) | (1U << 28), /**< WWDT */ + CMU_PERH_LCD = (1U << 13) | (1U << 28), /**< LCD */ + CMU_PERH_IWDT = (1U << 14) | (1U << 28), /**< IWDT */ + CMU_PERH_RTC = (1U << 15) | (1U << 28), /**< RTC */ + CMU_PERH_TSENSE = (1U << 16) | (1U << 28), /**< TSENSE */ + CMU_PERH_BKPC = (1U << 17) | (1U << 28), /**< BKPC */ + CMU_PERH_BKRPAM = (1U << 18) | (1U << 28), /**< BKPRAM */ + CMU_PERH_DBGC = (1U << 19) | (1U << 28), /**< DBGC */ + CMU_PERH_ALL = (0x7FFFFFFF), /**< ALL */ +} cmu_perh_t; + +/** + * @brief CMU interrupt type + */ +typedef enum +{ + CMU_LOSC_STOP = 0x0, /**< LOSC STOP INTERRUPT */ + CMU_HOSC_STOP = 0x1, /**< HOSC STOP INTERRUPT */ + CMU_PLL1_UNLOCK = 0x2, /**< PLL1 UNLOCK INTERRUPT */ + CMU_LOSC_START = 0x3, /**< LOSC START INTERRUPT */ + CMU_HOSC_START = 0x4, /**< HOSC START INTERRUPT */ +} cmu_security_t; + +/** + * @brief CMU clock state type + */ +typedef enum +{ + CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */ + CMU_CLOCK_STATE_LOSCACT = (1U << 1), /**< LOSC active */ + CMU_CLOCK_STATE_HRCACT = (1U << 2), /**< HRC active */ + CMU_CLOCK_STATE_LRCACT = (1U << 3), /**< LRC active */ + CMU_CLOCK_STATE_ULRCACT = (1U << 4), /**< ULRC active */ + CMU_CLOCK_STATE_PLLACT = (1U << 8), /**< PLL active */ + CMU_CLOCK_STATE_HOSCRDY = (1U << 16), /**< HOSC ready */ + CMU_CLOCK_STATE_LOSCRDY = (1U << 17), /**< LOSC ready */ + CMU_CLOCK_STATE_HRCRDY = (1U << 18), /**< HRC ready */ + CMU_CLOCK_STATE_LRCRDY = (1U << 19), /**< LRC ready */ + CMU_CLOCK_STATE_PLLRDY = (1U << 24), /**< PLL ready */ +} cmu_clock_state_t; +/** + * @} + */ + +/** + * @defgroup CMU_Private_Macros CMU Private Macros + * @{ + */ +#define IS_CMU_CLOCK(x) (((x) == CMU_CLOCK_HRC) || \ + ((x) == CMU_CLOCK_LRC) || \ + ((x) == CMU_CLOCK_LOSC) || \ + ((x) == CMU_CLOCK_PLL1) || \ + ((x) == CMU_CLOCK_HOSC)) +#define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_32M) || \ + ((x) == CMU_PLL1_OUTPUT_48M)) +#define IS_CMU_PLL1_INPUT(x) (((x) == CMU_PLL1_INPUT_HRC_6) || \ + ((x) == CMU_PLL1_INPUT_PLL2) || \ + ((x) == CMU_PLL1_INPUT_HOSC) || \ + ((x) == CMU_PLL1_INPUT_HOSC_2) || \ + ((x) == CMU_PLL1_INPUT_HOSC_3) || \ + ((x) == CMU_PLL1_INPUT_HOSC_4) || \ + ((x) == CMU_PLL1_INPUT_HOSC_5) || \ + ((x) == CMU_PLL1_INPUT_HOSC_6)) +#define IS_CMU_HOSC_RANGE(x) (((x) == CMU_HOSC_2M) || \ + ((x) == CMU_HOSC_4M) || \ + ((x) == CMU_HOSC_8M) || \ + ((x) == CMU_HOSC_16M) || \ + ((x) == CMU_HOSC_24M)) +#define IS_CMU_DIV(x) (((x) == CMU_DIV_1) || \ + ((x) == CMU_DIV_2) || \ + ((x) == CMU_DIV_4) || \ + ((x) == CMU_DIV_8) || \ + ((x) == CMU_DIV_16) || \ + ((x) == CMU_DIV_32) || \ + ((x) == CMU_DIV_64) || \ + ((x) == CMU_DIV_128) || \ + ((x) == CMU_DIV_256) || \ + ((x) == CMU_DIV_512) || \ + ((x) == CMU_DIV_1024) || \ + ((x) == CMU_DIV_2048) || \ + ((x) == CMU_DIV_4096)) +#define IS_CMU_BUS(x) (((x) == CMU_HCLK_1) || \ + ((x) == CMU_SYS) || \ + ((x) == CMU_PCLK_1) || \ + ((x) == CMU_PCLK_2)) +#define IS_CMU_OUTPUT_HIGH_SEL(x) (((x) == CMU_OUTPUT_HIGH_SEL_HOSC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_HRC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_LRC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK)) +#define IS_CMU_OUTPUT_HIGH_DIV(x) (((x) == CMU_OUTPUT_DIV_1) || \ + ((x) == CMU_OUTPUT_DIV_2) || \ + ((x) == CMU_OUTPUT_DIV_4) || \ + ((x) == CMU_OUTPUT_DIV_8) || \ + ((x) == CMU_OUTPUT_DIV_16) || \ + ((x) == CMU_OUTPUT_DIV_32) || \ + ((x) == CMU_OUTPUT_DIV_64) || \ + ((x) == CMU_OUTPUT_DIV_128)) +#define IS_CMU_OUTPUT_LOW_SEL(x) (((x) == CMU_OUTPUT_LOW_SEL_LOSC) || \ + ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \ + ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \ + ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \ + ((x) == CMU_OUTPUT_LOW_SEL_ULRC)) +#define IS_CMU_AUTO_CALIB_INPUT(x) (((x) == CMU_AUTO_CALIB_INPUT_LOSE) || \ + ((x) == CMU_AUTO_CALIB_INPUT_HOSE)) +#define IS_CMU_AUTO_CALIB_OUTPUT(x) (((x) == CMU_AUTO_CALIB_OUTPUT_24M) || \ + ((x) == CMU_AUTO_CALIB_OUTPUT_2M)) +#define IS_CMU_BUZZ_DIV(x) (((x) == CMU_BUZZ_DIV_2) || \ + ((x) == CMU_BUZZ_DIV_4) || \ + ((x) == CMU_BUZZ_DIV_8) || \ + ((x) == CMU_BUZZ_DIV_16) || \ + ((x) == CMU_BUZZ_DIV_32) || \ + ((x) == CMU_BUZZ_DIV_64) || \ + ((x) == CMU_BUZZ_DIV_128) || \ + ((x) == CMU_BUZZ_DIV_256)) +#define IS_CMU_LP_PERH_CLOCK_SEL(x) (((x) == CMU_LP_PERH_CLOCK_SEL_PCLK2) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LOSC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_ULRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM)) +#define IS_CMU_LCD_CLOCK_SEL(x) (((x) == CMU_LCD_SEL_LOSM) || \ + ((x) == CMU_LCD_SEL_LOSC) || \ + ((x) == CMU_LCD_SEL_LRC) || \ + ((x) == CMU_LCD_SEL_ULRC) || \ + ((x) == CMU_LCD_SEL_HRC_1M) || \ + ((x) == CMU_LCD_SEL_HOSC_1M)) +#define IS_CMU_PERH(x) (((x) == CMU_PERH_GPIO) || \ + ((x) == CMU_PERH_CRC) || \ + ((x) == CMU_PERH_CALC) || \ + ((x) == CMU_PERH_CRYPT) || \ + ((x) == CMU_PERH_TRNG) || \ + ((x) == CMU_PERH_PIS) || \ + ((x) == CMU_PERH_TIMER0) || \ + ((x) == CMU_PERH_TIMER1) || \ + ((x) == CMU_PERH_TIMER2) || \ + ((x) == CMU_PERH_TIMER3) || \ + ((x) == CMU_PERH_TIMER4) || \ + ((x) == CMU_PERH_TIMER5) || \ + ((x) == CMU_PERH_TIMER6) || \ + ((x) == CMU_PERH_TIMER7) || \ + ((x) == CMU_PERH_UART0) || \ + ((x) == CMU_PERH_UART1) || \ + ((x) == CMU_PERH_UART2) || \ + ((x) == CMU_PERH_UART3) || \ + ((x) == CMU_PERH_USART0) || \ + ((x) == CMU_PERH_USART1) || \ + ((x) == CMU_PERH_SPI0) || \ + ((x) == CMU_PERH_SPI1) || \ + ((x) == CMU_PERH_SPI2) || \ + ((x) == CMU_PERH_I2C0) || \ + ((x) == CMU_PERH_I2C1) || \ + ((x) == CMU_PERH_CAN) || \ + ((x) == CMU_PERH_LPTIM0) || \ + ((x) == CMU_PERH_LPUART0) || \ + ((x) == CMU_PERH_ADC0) || \ + ((x) == CMU_PERH_ADC1) || \ + ((x) == CMU_PERH_ACMP0) || \ + ((x) == CMU_PERH_ACMP1) || \ + ((x) == CMU_PERH_OPAMP) || \ + ((x) == CMU_PERH_DAC0) || \ + ((x) == CMU_PERH_WWDT) || \ + ((x) == CMU_PERH_LCD) || \ + ((x) == CMU_PERH_IWDT) || \ + ((x) == CMU_PERH_RTC) || \ + ((x) == CMU_PERH_TSENSE) || \ + ((x) == CMU_PERH_BKPC) || \ + ((x) == CMU_PERH_BKRPAM ) || \ + ((x) == CMU_PERH_DBGC) || \ + ((x) == CMU_PERH_ALL)) +#define IS_CMU_CLOCK_STATE(x) (((x) == CMU_CLOCK_STATE_HOSCACT) || \ + ((x) == CMU_CLOCK_STATE_LOSCACT) || \ + ((x) == CMU_CLOCK_STATE_HRCACT) || \ + ((x) == CMU_CLOCK_STATE_LRCACT) || \ + ((x) == CMU_CLOCK_STATE_ULRCACT) || \ + ((x) == CMU_CLOCK_STATE_PLLACT) || \ + ((x) == CMU_CLOCK_STATE_HOSCRDY) || \ + ((x) == CMU_CLOCK_STATE_LOSCRDY) || \ + ((x) == CMU_CLOCK_STATE_HRCRDY) || \ + ((x) == CMU_CLOCK_STATE_LRCRDY) || \ + ((x) == CMU_CLOCK_STATE_PLLRDY)) +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions + * @{ + */ +/** @addtogroup CMU_Public_Functions_Group1 + * @{ + */ +/* System clock configure */ +ald_status_t ald_cmu_clock_config_default(void); +ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock); +void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output); +uint32_t ald_cmu_get_clock(void); +int32_t ald_cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output_t freq); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group2 + * @{ + */ +/* BUS division control */ +void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div); +uint32_t ald_cmu_get_hclk1_clock(void); +uint32_t ald_cmu_get_sys_clock(void); +uint32_t ald_cmu_get_pclk1_clock(void); +uint32_t ald_cmu_get_pclk2_clock(void); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group3 + * @{ + */ +/* Clock safe configure */ +void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status); +void ald_cmu_losc_safe_config(type_func_t status); +void ald_cmu_pll_safe_config(type_func_t status); +flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr); +void ald_cmu_irq_handler(void); +void ald_cmu_irq_cbk(cmu_security_t se); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group4 + * @{ + */ +/* Clock output configure */ +void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, + cmu_output_high_div_t div, type_func_t status); +void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group5 + * @{ + */ +/* Peripheral Clock configure */ +void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status); +void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock); +void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock); +void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock); +void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_CMU_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h similarity index 100% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h similarity index 37% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h index 5562db71f48cbec008d18f9cf98f22c4261360c9..e3281dc166891a72aae047822aacfed3f1568c26 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h @@ -41,10 +41,10 @@ extern "C" { */ typedef enum { - CRC_MODE_CCITT = 0, /**< Ccitt */ - CRC_MODE_8 = 1, /**< Crc8 */ - CRC_MODE_16 = 2, /**< Crc16 */ - CRC_MODE_32 = 3, /**< Crc32 */ + CRC_MODE_CCITT = 0, /**< Ccitt */ + CRC_MODE_8 = 1, /**< Crc8 */ + CRC_MODE_16 = 2, /**< Crc16 */ + CRC_MODE_32 = 3, /**< Crc32 */ } crc_mode_t; /** @@ -52,10 +52,10 @@ typedef enum */ typedef enum { - CRC_LEN_AUTO = 0, /**< Auto */ - CRC_DATASIZE_8 = 1, /**< Byte */ - CRC_DATASIZE_16 = 2, /**< Half word */ - CRC_DATASIZE_32 = 3, /**< Word */ + CRC_LEN_AUTO = 0, /**< Auto */ + CRC_DATASIZE_8 = 1, /**< Byte */ + CRC_DATASIZE_16 = 2, /**< Half word */ + CRC_DATASIZE_32 = 3, /**< Word */ } crc_datasize_t; /** @@ -63,8 +63,8 @@ typedef enum */ typedef enum { - CRC_WERR_NO = 0, /**< No error */ - CRC_WERR_ERR = 1, /**< Error */ + CRC_WERR_NO = 0, /**< No error */ + CRC_WERR_ERR = 1, /**< Error */ } crc_werr_t; /** @@ -72,10 +72,10 @@ typedef enum */ typedef enum { - CRC_STATE_RESET = 0x0, /**< Peripheral is not initialized */ - CRC_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - CRC_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - CRC_STATE_ERROR = 0x4, /**< Error */ + CRC_STATE_RESET = 0x0, /**< Peripheral is not initialized */ + CRC_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ + CRC_STATE_BUSY = 0x2, /**< An internal process is ongoing */ + CRC_STATE_ERROR = 0x4, /**< Error */ } crc_state_t; /** @@ -83,12 +83,12 @@ typedef enum */ typedef struct { - crc_mode_t mode; /**< CRC mode */ - type_func_t data_rev; /**< CRC data reverse or no */ - type_func_t data_inv; /**< CRC data inverse or no */ - type_func_t chs_rev; /**< CRC check sum reverse or no */ - type_func_t chs_inv; /**< CRC check sum inverse or no */ - uint32_t seed; /**< CRC seed */ + crc_mode_t mode; /**< CRC mode */ + type_func_t data_rev; /**< CRC data reverse or no */ + type_func_t data_inv; /**< CRC data inverse or no */ + type_func_t chs_rev; /**< CRC check sum reverse or no */ + type_func_t chs_inv; /**< CRC check sum inverse or no */ + uint32_t seed; /**< CRC seed */ } crc_init_t; /** @@ -96,18 +96,18 @@ typedef struct */ typedef struct crc_handle_s { - CRC_TypeDef *perh; /**< Register base address */ - crc_init_t init; /**< CRC required parameters */ - uint8_t *cal_buf; /**< The pointer of preparing buffer */ - uint32_t *cal_res; /**< The pointer of result */ + CRC_TypeDef *perh; /**< Register base address */ + crc_init_t init; /**< CRC required parameters */ + uint8_t *cal_buf; /**< The pointer of preparing buffer */ + uint32_t *cal_res; /**< The pointer of result */ #ifdef ALD_DMA - dma_handle_t hdma; /**< CRC DMA handle parameters */ + dma_handle_t hdma; /**< CRC DMA handle parameters */ #endif - lock_state_t lock; /**< Locking object */ - crc_state_t state; /**< CRC operation state */ + lock_state_t lock; /**< Locking object */ + crc_state_t state; /**< CRC operation state */ - void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */ - void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */ + void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */ + void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */ } crc_handle_t; /** * @} @@ -116,12 +116,12 @@ typedef struct crc_handle_s /** @defgroup CRC_Public_Macros CRC Public Macros * @{ */ -#define CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) -#define CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) -#define CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK)) -#define CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) -#define CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) -#define CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK)) +#define CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) +#define CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) +#define CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK)) +#define CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) +#define CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) +#define CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK)) /** * @} */ @@ -129,11 +129,11 @@ typedef struct crc_handle_s /** @defgroup CRC_Private_Macros CRC Private Macros * @{ */ -#define IS_CRC(x) ((x) == CRC) -#define IS_CRC_MODE(x) (((x) == CRC_MODE_CCITT) || \ - ((x) == CRC_MODE_8) || \ - ((x) == CRC_MODE_16) || \ - ((x) == CRC_MODE_32)) +#define IS_CRC(x) ((x) == CRC) +#define IS_CRC_MODE(x) (((x) == CRC_MODE_CCITT) || \ + ((x) == CRC_MODE_8) || \ + ((x) == CRC_MODE_16) || \ + ((x) == CRC_MODE_32)) /** * @} */ @@ -145,7 +145,8 @@ typedef struct crc_handle_s /** @addtogroup CRC_Public_Functions_Group1 * @{ */ -ald_status_t crc_init(crc_handle_t *hperh); +ald_status_t ald_crc_init(crc_handle_t *hperh); +void ald_crc_reset(crc_handle_t *hperh); /** * @} */ @@ -153,7 +154,9 @@ ald_status_t crc_init(crc_handle_t *hperh); /** @addtogroup CRC_Public_Functions_Group2 * @{ */ -uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size); +uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size); +uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size); +uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size); /** * @} */ @@ -162,10 +165,12 @@ uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size); /** @addtogroup CRC_Public_Functions_Group3 * @{ */ -ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel); -ald_status_t crc_dma_pause(crc_handle_t *hperh); -ald_status_t crc_dma_resume(crc_handle_t *hperh); -ald_status_t crc_dma_stop(crc_handle_t *hperh); +ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_dma_pause(crc_handle_t *hperh); +ald_status_t ald_crc_dma_resume(crc_handle_t *hperh); +ald_status_t ald_crc_dma_stop(crc_handle_t *hperh); /** * @} */ @@ -173,7 +178,7 @@ ald_status_t crc_dma_stop(crc_handle_t *hperh); /** @addtogroup CRC_Public_Functions_Group4 * @{ */ -crc_state_t crc_get_state(crc_handle_t *hperh); +crc_state_t ald_crc_get_state(crc_handle_t *hperh); /** * @} */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h similarity index 30% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h index f3a5ebaeb563231a9b2d018e4e941d3a9b0359a2..18340558a2d5e6b2c805d2b2035025bcec1b3e6a 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h @@ -41,8 +41,8 @@ extern "C" { */ typedef enum { - CRYPT_DECRYPT = 0, /**< Decrypt */ - CRYPT_ENCRYPT = 1, /**< Encrypt */ + CRYPT_DECRYPT = 0, /**< Decrypt */ + CRYPT_ENCRYPT = 1, /**< Encrypt */ } crypt_encs_t; /** @@ -50,9 +50,9 @@ typedef enum */ typedef enum { - CRYPT_MODE_ECB = 0, /**< ECB */ - CRYPT_MODE_CBC = 1, /**< CBC */ - CRYPT_MODE_CTR = 2, /**< CTR */ + CRYPT_MODE_ECB = 0, /**< ECB */ + CRYPT_MODE_CBC = 1, /**< CBC */ + CRYPT_MODE_CTR = 2, /**< CTR */ } crypt_mode_t; /** @@ -60,10 +60,10 @@ typedef enum */ typedef enum { - CRYPT_DATA_CHANGE_NO = 0, /**< No exchange */ - CRYPT_DATA_CHANGE_16 = 1, /**< 16bit exchange */ - CRYPT_DATA_CHANGE_8 = 2, /**< 8bit exchange */ - CRYPT_DATA_CHANGE_1 = 3, /**< 1bit exchange */ + CRYPT_DATA_CHANGE_NO = 0, /**< No exchange */ + CRYPT_DATA_CHANGE_16 = 1, /**< 16bit exchange */ + CRYPT_DATA_CHANGE_8 = 2, /**< 8bit exchange */ + CRYPT_DATA_CHANGE_1 = 3, /**< 1bit exchange */ } crypt_datatype_t; /** @@ -71,7 +71,7 @@ typedef enum */ typedef enum { - CRYPT_IT_IT = 0x80, /**< Interrupt */ + CRYPT_IT_IT = 0x80, /**< Interrupt */ } crypt_it_t; /** @@ -79,8 +79,8 @@ typedef enum */ typedef enum { - CRYPT_FLAG_AESIF = 0x1, /**< Aes flag */ - CRYPT_FLAG_DONE = 0x100, /**< Complete flag */ + CRYPT_FLAG_AESIF = 0x1, /**< Aes flag */ + CRYPT_FLAG_DONE = 0x100, /**< Complete flag */ } crypt_flag_t; /** @@ -88,10 +88,10 @@ typedef enum */ typedef enum { - CRYPT_STATE_RESET = 0x0, /**< Peripheral is not initialized */ - CRYPT_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ - CRYPT_STATE_BUSY = 0x2, /**< An internal process is ongoing */ - CRYPT_STATE_ERROR = 0x4, /**< Error */ + CRYPT_STATE_RESET = 0x0, /**< Peripheral is not initialized */ + CRYPT_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ + CRYPT_STATE_BUSY = 0x2, /**< An internal process is ongoing */ + CRYPT_STATE_ERROR = 0x4, /**< Error */ } crypt_state_t; /** @@ -99,10 +99,10 @@ typedef enum */ typedef enum { - DATA_32_BIT = 0, /**< 32 bit data,don't swap */ - DATA_16_BIT = 1, /**< 16 bit data,swap */ - DATA_8_BIT = 2, /**< 8 bit data,swap */ - DATA_1_BIT = 3, /**< 1 bit data, swap */ + DATA_32_BIT = 0, /**< 32 bit data,don't swap */ + DATA_16_BIT = 1, /**< 16 bit data,swap */ + DATA_8_BIT = 2, /**< 8 bit data,swap */ + DATA_1_BIT = 3, /**< 1 bit data, swap */ } crypt_data_t; /** @@ -110,8 +110,8 @@ typedef enum */ typedef struct { - crypt_mode_t mode; /**< Crypt mode */ - crypt_data_t type; /**< Data type select */ + crypt_mode_t mode; /**< Crypt mode */ + crypt_data_t type; /**< Data type select */ } crypt_init_t; /** @@ -119,25 +119,25 @@ typedef struct */ typedef struct crypt_handle_s { - CRYPT_TypeDef *perh; /**< Register base address */ - crypt_init_t init; /**< CRYPT required parameters */ + CRYPT_TypeDef *perh; /**< Register base address */ + crypt_init_t init; /**< CRYPT required parameters */ #ifdef ALD_DMA - dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */ - dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */ + dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */ + dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */ #endif - uint8_t *plain_text; /**< Pointer to plain text */ - uint8_t *cipher_text; /**< Pointer to cipher text */ - uint32_t size; /**< The size of crypt data buf */ - uint32_t count; /**< The count of crypt data buf */ - uint32_t step; /**< The step of once crypt 4(aes) */ - uint32_t dir; /**< ENCRYPT or DECRYPT */ - uint32_t iv[4]; /**< The iv of crypt */ - uint32_t key[4]; /**< The key of crypt */ - lock_state_t lock; /**< Locking object */ - crypt_state_t state; /**< CRYPT operation state */ + uint8_t *plain_text; /**< Pointer to plain text */ + uint8_t *cipher_text; /**< Pointer to cipher text */ + uint32_t size; /**< The size of crypt data buf */ + uint32_t count; /**< The count of crypt data buf */ + uint32_t step; /**< The step of once crypt 4(aes) */ + uint32_t dir; /**< ENCRYPT or DECRYPT */ + uint32_t iv[4]; /**< The iv of crypt */ + uint32_t key[4]; /**< The key of crypt */ + lock_state_t lock; /**< Locking object */ + crypt_state_t state; /**< CRYPT operation state */ - void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */ - void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */ + void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */ + void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */ } crypt_handle_t; /** * @} @@ -146,19 +146,19 @@ typedef struct crypt_handle_s /** @defgroup CRYPT_Public_Macros CRYPT Public Macros * @{ */ -#define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK)) -#define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) -#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT(handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) -#define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) -#define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) -#define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) -#define CRYPT_IE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) -#define CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) -#define CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) -#define CRYPT_SETDIR(handle, dir) do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS); \ - (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0) +#define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK)) +#define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) +#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT(handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) +#define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) +#define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) +#define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) +#define CRYPT_IE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) +#define CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) +#define CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) +#define CRYPT_SETDIR(handle, dir) do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS); \ + (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0) #define CRYPT_WRITE_FIFO(handle, data) ((handle)->perh->FIFO = (data)) -#define CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO) +#define CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO) /** * @} */ @@ -166,15 +166,15 @@ typedef struct crypt_handle_s /** @defgroup CRYPT_Private_Macros CRYPT Private Macros * @{ */ -#define IS_CRYPT(x) ((x) == CRYPT) -#define IS_CRYPT_MODE(x) (((x) == CRYPT_MODE_ECB) || \ - ((x) == CRYPT_MODE_CBC) || \ - ((x) == CRYPT_MODE_CTR)) -#define IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT) -#define IS_CRYPT_FLAG(x) (((x) == CRYPT_FLAG_AESIF) || \ - ((x) == CRYPT_FLAG_DONE)) -#define IS_CRYPT_IV_LEN(x) (((x) == IV_2_LEN) || \ - ((x) == IV_4_LEN)) +#define IS_CRYPT(x) ((x) == CRYPT) +#define IS_CRYPT_MODE(x) (((x) == CRYPT_MODE_ECB) || \ + ((x) == CRYPT_MODE_CBC) || \ + ((x) == CRYPT_MODE_CTR)) +#define IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT) +#define IS_CRYPT_FLAG(x) (((x) == CRYPT_FLAG_AESIF) || \ + ((x) == CRYPT_FLAG_DONE)) +#define IS_CRYPT_IV_LEN(x) (((x) == IV_2_LEN) || \ + ((x) == IV_4_LEN)) /** * @} */ @@ -186,11 +186,11 @@ typedef struct crypt_handle_s /** @addtogroup CRYPT_Public_Functions_Group1 * @{ */ -ald_status_t crypt_init(crypt_handle_t *hperh); -ald_status_t crypt_write_key(crypt_handle_t *hperh, uint32_t *key); -ald_status_t crypt_read_key(crypt_handle_t *hperh, uint32_t *key); -ald_status_t crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv); -ald_status_t crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv); +ald_status_t ald_crypt_init(crypt_handle_t *hperh); +ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t *key); +ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t *key); +ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv); +ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv); /** * @} */ @@ -198,16 +198,16 @@ ald_status_t crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv); /** @addtogroup CRYPT_Public_Functions_Group2 * @{ */ -ald_status_t crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size); -ald_status_t crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size); -ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag); -ald_status_t crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size); -ald_status_t crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size); +ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size); +ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size); +ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag); +ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size); +ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size); #ifdef ALD_DMA -ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, - uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); -ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, - uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); +ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, + uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); +ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, + uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); #endif /** * @} @@ -217,11 +217,11 @@ ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, * @{ */ #ifdef ALD_DMA -ald_status_t crypt_dma_pause(crypt_handle_t *hperh); -ald_status_t crypt_dma_resume(crypt_handle_t *hperh); -ald_status_t crypt_dma_stop(crypt_handle_t *hperh); +ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh); +ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh); +ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh); #endif -void crypt_irq_handle(crypt_handle_t *hperh); +void ald_crypt_irq_handler(crypt_handle_t *hperh); /** * @} */ @@ -229,10 +229,10 @@ void crypt_irq_handle(crypt_handle_t *hperh); /** @addtogroup CRYPT_Public_Functions_Group4 * @{ */ -void crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state); -flag_status_t crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag); -void crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag); -it_status_t crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it); +void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state); +flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag); +void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag); +it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it); /** * @} */ @@ -240,7 +240,7 @@ it_status_t crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it); /** @addtogroup CRYPT_Public_Functions_Group5 * @{ */ -crypt_state_t crypt_get_state(crypt_handle_t *hperh); +crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh); /** * @} */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h similarity index 58% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h index 293997c04e6e72ad50409ff599ee9d6859719394..31b8dc6ca40a811eca70ef4dd86608feec96534b 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h @@ -43,10 +43,10 @@ extern "C" { */ typedef enum { - DEBC_MODE_SLEEP = (1u << 0), /**< Sleep mode */ - DEBC_MODE_STOP1 = (1u << 1), /**< STOP1 mode */ - DEBC_MODE_STOP2 = (1u << 2), /**< STOP2 mode */ - DEBC_MODE_STANDBY = (1u << 3), /**< Standby mode */ + DEBC_MODE_SLEEP = (1u << 0), /**< Sleep mode */ + DEBC_MODE_STOP1 = (1u << 1), /**< STOP1 mode */ + DEBC_MODE_STOP2 = (1u << 2), /**< STOP2 mode */ + DEBC_MODE_STANDBY = (1u << 3), /**< Standby mode */ } dbgc_mode_t; /** @@ -54,21 +54,21 @@ typedef enum */ typedef enum { - DEBC_PERH_TIMER0 = (1u << 0), /**< AD16C4T0 */ - DEBC_PERH_TIMER1 = (1u << 1), /**< BS16T0 */ - DEBC_PERH_TIMER2 = (1u << 2), /**< GP16C2T0 */ - DEBC_PERH_TIMER3 = (1u << 3), /**< GP16C2T1 */ - DEBC_PERH_TIMER4 = (1u << 4), /**< BS16T1 */ - DEBC_PERH_TIMER5 = (1u << 5), /**< BS16T2 */ - DEBC_PERH_TIMER6 = (1u << 6), /**< GP16C4T0 */ - DEBC_PERH_TIMER7 = (1u << 7), /**< BS16T3 */ - DEBC_PERH_I2C0 = (1u << 8), /**< I2C0 SMBUS */ - DEBC_PERH_I2C1 = (1u << 9), /**< I2C1 SMBUS */ - DEBC_PERH_CAN = (1u << 12), /**< CAN */ - DEBC_PERH_LPTIM0 = (1u << 0) | (1u << 16), /**< LPTIM0 */ - DEBC_PERH_IWDT = (1u << 8) | (1u << 16), /**< IWDT */ - DEBC_PERH_WWDT = (1u << 9) | (1u << 16), /**< WWDT */ - DEBC_PERH_RTC = (1u << 10) | (1u << 16), /**< RTC */ + DEBC_PERH_TIMER0 = (1u << 0), /**< AD16C4T0 */ + DEBC_PERH_TIMER1 = (1u << 1), /**< BS16T0 */ + DEBC_PERH_TIMER2 = (1u << 2), /**< GP16C2T0 */ + DEBC_PERH_TIMER3 = (1u << 3), /**< GP16C2T1 */ + DEBC_PERH_TIMER4 = (1u << 4), /**< BS16T1 */ + DEBC_PERH_TIMER5 = (1u << 5), /**< BS16T2 */ + DEBC_PERH_TIMER6 = (1u << 6), /**< GP16C4T0 */ + DEBC_PERH_TIMER7 = (1u << 7), /**< BS16T3 */ + DEBC_PERH_I2C0 = (1u << 8), /**< I2C0 SMBUS */ + DEBC_PERH_I2C1 = (1u << 9), /**< I2C1 SMBUS */ + DEBC_PERH_CAN = (1u << 12), /**< CAN */ + DEBC_PERH_LPTIM0 = (1u << 0) | (1u << 16), /**< LPTIM0 */ + DEBC_PERH_IWDT = (1u << 8) | (1u << 16), /**< IWDT */ + DEBC_PERH_WWDT = (1u << 9) | (1u << 16), /**< WWDT */ + DEBC_PERH_RTC = (1u << 10) | (1u << 16), /**< RTC */ } dbgc_perh_t; /** * @} @@ -81,7 +81,7 @@ typedef enum * @brief Gets version. * @retval Version */ -__INLINE uint32_t dbgc_get_rev_id(void) +__INLINE uint32_t ald_dbgc_get_rev_id(void) { return (DBGC->IDCODE >> 16); } @@ -90,7 +90,7 @@ __INLINE uint32_t dbgc_get_rev_id(void) * @brief Gets core id. * @retval Core id */ -__INLINE uint32_t dbgc_get_core_id(void) +__INLINE uint32_t ald_dbgc_get_core_id(void) { return (DBGC->IDCODE >> 12) & 0xF; } @@ -99,7 +99,7 @@ __INLINE uint32_t dbgc_get_core_id(void) * @brief Gets device id * @retval device id */ -__INLINE uint32_t dbgc_get_device_id(void) +__INLINE uint32_t ald_dbgc_get_device_id(void) { return DBGC->IDCODE & 0xFFF; } @@ -110,7 +110,7 @@ __INLINE uint32_t dbgc_get_device_id(void) * @param state: ENABLE/DISABLE * @retval None */ -__INLINE void dbgc_mode_config(dbgc_mode_t mode, type_func_t state) +__INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state) { if (state) SET_BIT(DBGC->CR, mode); @@ -124,7 +124,7 @@ __INLINE void dbgc_mode_config(dbgc_mode_t mode, type_func_t state) * @param state: ENABLE/DISABLE * @retval None */ -__INLINE void dbgc_perh_config(dbgc_perh_t perh, type_func_t state) +__INLINE void ald_dbgc_perh_config(dbgc_perh_t perh, type_func_t state) { if ((perh >> 16) & 0x1) { diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..364f9e16cb40498c8e85e6deeb80c3b4a1afd769 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h @@ -0,0 +1,409 @@ +/** + ********************************************************************************* + * + * @file ald_dma.h + * @brief DMA module Library. + * + * @version V1.0 + * @date 09 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_DMA_H__ +#define __ALD_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** + * @defgroup DMA_Public_Macros DMA Public Macros + * @{ + */ +#define DMA_CH_COUNT 6 +#define DMA_ERR 31 +/** + * @} + */ + +/** + * @defgroup DMA_Public_Types DMA Public Types + * @{ + */ + +/** + * @brief Input source to DMA channel + * @note ES32F065x: + * AD16C4T0--TIMER0 + * GP16C4T0--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + * + * ES32F033x: + * ES32F093x: + * GP16C4T0--TIMER0 + * GP16C4T1--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + */ +typedef enum +{ + DMA_MSEL_NONE = 0x0, /**< NONE */ + DMA_MSEL_GPIO = 0x1, /**< GPIO */ + DMA_MSEL_CRYPT = 0x2, /**< CRYPT */ + DMA_MSEL_ACMP = 0x3, /**< ACMP */ + DMA_MSEL_DAC0 = 0x4, /**< DAC0 */ + DMA_MSEL_ADC0 = 0x6, /**< ADC0 */ + DMA_MSEL_CRC = 0x7, /**< CRC */ + DMA_MSEL_UART0 = 0x8, /**< UART0 */ + DMA_MSEL_UART1 = 0x9, /**< UART1 */ + DMA_MSEL_UART2 = 0xA, /**< UART2 */ + DMA_MSEL_UART3 = 0xB, /**< UART3 */ + DMA_MSEL_USART0 = 0xC, /**< USART0 */ + DMA_MSEL_USART1 = 0xD, /**< USART1 */ + DMA_MSEL_SPI0 = 0xE, /**< SPI0 */ + DMA_MSEL_SPI1 = 0xF, /**< SPI1 */ + DMA_MSEL_I2C0 = 0x10, /**< I2C0 */ + DMA_MSEL_I2C1 = 0x11, /**< I2C1 */ + DMA_MSEL_TIMER0 = 0x12, /**< TIMER0 */ + DMA_MSEL_TIMER1 = 0x13, /**< TIMER1 */ + DMA_MSEL_TIMER2 = 0x14, /**< TIMER2 */ + DMA_MSEL_TIMER3 = 0x15, /**< TIMER3 */ + DMA_MSEL_RTC = 0x16, /**< RTC */ + DMA_MSEL_LPTIM0 = 0x17, /**< LPTIM0 */ + DMA_MSEL_LPUART0 = 0x18, /**< LPUART0 */ + DMA_MSEL_DMA = 0x19, /**< DMA */ + DMA_MSEL_SPI2 = 0x1A, /**< SPI2 */ + DMA_MSEL_TIMER4 = 0x1B, /**< TIMER4 */ + DMA_MSEL_TIMER5 = 0x1C, /**< TIMER5 */ + DMA_MSEL_TIMER6 = 0x1D, /**< TIMER6 */ + DMA_MSEL_TIMER7 = 0x1E, /**< TIMER7 */ + DMA_MSEL_ADC1 = 0x1F, /**< ADC1 */ + DMA_MSEL_PIS = 0x20, /**< PIS */ + DMA_MSEL_TRNG = 0x21, /**< TRNG */ +} dma_msel_t; + +/** + * @brief Input signal to DMA channel + */ +typedef enum +{ + DMA_MSIGSEL_NONE = 0x0, /**< NONE */ + DMA_MSIGSEL_EXTI_0 = 0x0, /**< External interrupt 0 */ + DMA_MSIGSEL_EXTI_1 = 0x1, /**< External interrupt 1 */ + DMA_MSIGSEL_EXTI_2 = 0x2, /**< External interrupt 2 */ + DMA_MSIGSEL_EXTI_3 = 0x3, /**< External interrupt 3 */ + DMA_MSIGSEL_EXTI_4 = 0x4, /**< External interrupt 4 */ + DMA_MSIGSEL_EXTI_5 = 0x5, /**< External interrupt 5 */ + DMA_MSIGSEL_EXTI_6 = 0x6, /**< External interrupt 6 */ + DMA_MSIGSEL_EXTI_7 = 0x7, /**< External interrupt 7 */ + DMA_MSIGSEL_EXTI_8 = 0x8, /**< External interrupt 8 */ + DMA_MSIGSEL_EXTI_9 = 0x9, /**< External interrupt 9 */ + DMA_MSIGSEL_EXTI_10 = 0xA, /**< External interrupt 10 */ + DMA_MSIGSEL_EXTI_11 = 0xB, /**< External interrupt 11 */ + DMA_MSIGSEL_EXTI_12 = 0xC, /**< External interrupt 12 */ + DMA_MSIGSEL_EXTI_13 = 0xD, /**< External interrupt 13 */ + DMA_MSIGSEL_EXTI_14 = 0xE, /**< External interrupt 14 */ + DMA_MSIGSEL_EXTI_15 = 0xF, /**< External interrupt 15 */ + DMA_MSIGSEL_CRYPT_WRITE = 0x0, /**< CRYPT write mode */ + DMA_MSIGSEL_CRYPT_READ = 0x1, /**< CRYPT read mode */ + DMA_MSIGSEL_CALC_WRITE = 0x0, /**< CALC write mode */ + DMA_MSIGSEL_CALC_READ = 0x1, /**< CALC read mode */ + DMA_MSIGSEL_DAC0_CH0 = 0x0, /**< DAC0 channel 0 complete */ + DMA_MSIGSEL_DAC0_CH1 = 0x1, /**< DAC0 channel 1 complete */ + DMA_MSIGSEL_ADC = 0x0, /**< ADC mode */ + DMA_MSIGSEL_UART_TXEMPTY = 0x0, /**< UART transmit */ + DMA_MSIGSEL_UART_RNR = 0x1, /**< UART receive */ + DMA_MSIGSEL_USART_RNR = 0x0, /**< USART reveive */ + DMA_MSIGSEL_USART_TXEMPTY = 0x1, /**< USART transmit */ + DMA_MSIGSEL_SPI_RNR = 0x0, /**< SPI receive */ + DMA_MSIGSEL_SPI_TXEMPTY = 0x1, /**< SPI transmit */ + DMA_MSIGSEL_I2C_RNR = 0x0, /**< I2C receive */ + DMA_MSIGSEL_I2C_TXEMPTY = 0x1, /**< I2C transmit */ + DMA_MSIGSEL_TIMER_CH1 = 0x0, /**< TIM channal 1 */ + DMA_MSIGSEL_TIMER_CH2 = 0x1, /**< TIM channal 2 */ + DMA_MSIGSEL_TIMER_CH3 = 0x2, /**< TIM channal 3 */ + DMA_MSIGSEL_TIMER_CH4 = 0x3, /**< TIM channal 4 */ + DMA_MSIGSEL_TIMER_TRI = 0x4, /**< TIM trigger */ + DMA_MSIGSEL_TIMER_COMP = 0x5, /**< TIM compare */ + DMA_MSIGSEL_TIMER_UPDATE = 0x6, /**< TIM update */ + DMA_MSIGSEL_LPUART_RNR = 0x0, /**< LPUART receive */ + DMA_MSIGSEL_LPUART_TXEMPTY = 0x1, /**< LPUART transmit */ + DMA_MSIGSEL_PIS_CH0 = 0x0, /**< PIS channal 0 */ + DMA_MSIGSEL_PIS_CH1 = 0x1, /**< PIS channal 1 */ + DMA_MSIGSEL_PIS_CH2 = 0x2, /**< PIS channal 2 */ + DMA_MSIGSEL_PIS_CH3 = 0x3, /**< PIS channal 3 */ + DMA_MSIGSEL_PIS_CH4 = 0x4, /**< PIS channal 4 */ + DMA_MSIGSEL_PIS_CH5 = 0x5, /**< PIS channal 5 */ + DMA_MSIGSEL_PIS_CH6 = 0x6, /**< PIS channal 6 */ + DMA_MSIGSEL_PIS_CH7 = 0x7, /**< PIS channal 7 */ + DMA_MSIGSEL_PIS_CH8 = 0x8, /**< PIS channal 8 */ + DMA_MSIGSEL_PIS_CH9 = 0x9, /**< PIS channal 9 */ + DMA_MSIGSEL_PIS_CH10 = 0xA, /**< PIS channal 10 */ + DMA_MSIGSEL_PIS_CH11 = 0xB, /**< PIS channal 11 */ + DMA_MSIGSEL_PIS_CH12 = 0xC, /**< PIS channal 12 */ + DMA_MSIGSEL_PIS_CH13 = 0xD, /**< PIS channal 13 */ + DMA_MSIGSEL_PIS_CH14 = 0xE, /**< PIS channal 14 */ + DMA_MSIGSEL_PIS_CH15 = 0xF, /**< PIS channal 15 */ +} dma_msigsel_t; + +/** + * @brief DMA Descriptor control type + */ +typedef union +{ + struct + { + uint32_t cycle_ctrl : 3; /**< DMA operating mode @ref dma_cycle_ctrl_t */ + uint32_t next_useburst : 1; /**< Uses the alternate data structure when complete a DMA cycle */ + uint32_t n_minus_1 : 10; /**< Represent the total number of DMA transfers that DMA cycle contains. */ + uint32_t R_power : 4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ + uint32_t src_prot_ctrl : 3; /**< Control the state of HPROT when reads the source data. */ + uint32_t dst_prot_ctrl : 3; /**< Control the state of HPROT when writes the destination data */ + uint32_t src_size : 2; /**< Source data size @ref dma_data_size_t */ + uint32_t src_inc : 2; /**< Control the source address increment. @ref dma_data_inc_t */ + uint32_t dst_size : 2; /**< Destination data size. @ref dma_data_size_t */ + uint32_t dst_inc : 2; /**< Destination address increment. @ref dma_data_inc_t */ + }; + uint32_t word; +} dma_ctrl_t; + +/** + * @brief Channel control data structure + */ +typedef struct +{ + void *src; /**< Source data end pointer */ + void *dst; /**< Destination data end pointer */ + dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */ + uint32_t use; /**< Reserve for user */ +} dma_descriptor_t; + +/** + * @brief data increment + */ +typedef enum +{ + DMA_DATA_INC_BYTE = 0x0, /**< Address increment by byte */ + DMA_DATA_INC_HALFWORD = 0x1, /**< Address increment by halfword */ + DMA_DATA_INC_WORD = 0x2, /**< Address increment by word */ + DMA_DATA_INC_NONE = 0x3, /**< No increment */ +} dma_data_inc_t; + +/** + * @brief Data size + */ +typedef enum +{ + DMA_DATA_SIZE_BYTE = 0x0, /**< Byte */ + DMA_DATA_SIZE_HALFWORD = 0x1, /**< Halfword */ + DMA_DATA_SIZE_WORD = 0x2, /**< Word */ +} dma_data_size_t; + +/** + * @brief The operating mode of the DMA cycle + */ +typedef enum +{ + DMA_CYCLE_CTRL_NONE = 0x0, /**< Stop */ + DMA_CYCLE_CTRL_BASIC = 0x1, /**< Basic */ + DMA_CYCLE_CTRL_AUTO = 0x2, /**< Auto-request */ + DMA_CYCLE_CTRL_PINGPONG = 0x3, /**< Ping-pong */ + DMA_CYCLE_CTRL_MEM_SCATTER_GATHER = 0x4, /**< Memory scatter/gather */ + DMA_CYCLE_CTRL_PER_SCATTER_GATHER = 0x6, /**< Peripheral scatter/gather */ +} dma_cycle_ctrl_t; + +/** + * @brief Control how many DMA transfers can occur + * before the controller re-arbitrates + */ +typedef enum +{ + DMA_R_POWER_1 = 0x0, /**< Arbitrates after each DMA transfer */ + DMA_R_POWER_2 = 0x1, /**< Arbitrates after 2 DMA transfer */ + DMA_R_POWER_4 = 0x2, /**< Arbitrates after 4 DMA transfer */ + DMA_R_POWER_8 = 0x3, /**< Arbitrates after 8 DMA transfer */ + DMA_R_POWER_16 = 0x4, /**< Arbitrates after 16 DMA transfer */ + DMA_R_POWER_32 = 0x5, /**< Arbitrates after 32 DMA transfer */ + DMA_R_POWER_64 = 0x6, /**< Arbitrates after 64 DMA transfer */ + DMA_R_POWER_128 = 0x7, /**< Arbitrates after 128 DMA transfer */ + DMA_R_POWER_256 = 0x8, /**< Arbitrates after 256 DMA transfer */ + DMA_R_POWER_512 = 0x9, /**< Arbitrates after 512 DMA transfer */ + DMA_R_POWER_1024 = 0xA, /**< Arbitrates after 1024 DMA transfer */ +} dma_arbiter_config_t; + +/** + * @brief Callback function pointer and param + */ +typedef struct +{ + void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*err_cbk)(void *arg); /**< DMA occurs error callback */ + void *cplt_arg; /**< The parameter of cplt_cbk() */ + void *err_arg; /**< The parameter of err_cbk() */ +} dma_call_back_t; + +/** + * @brief DMA channal configure structure + */ +typedef struct +{ + void *src; /**< Source data begin pointer */ + void *dst; /**< Destination data begin pointer */ + uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ + dma_data_size_t data_width; /**< Data width, @ref dma_data_size_t */ + dma_data_inc_t src_inc; /**< Source increment type. @ref dma_data_inc_t */ + dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */ + dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ + type_func_t primary; /**< Use primary descriptor or alternate descriptor */ + type_func_t burst; /**< Uses the alternate data structure when complete a DMA cycle */ + type_func_t high_prio; /**< High priority or default priority */ + type_func_t iterrupt; /**< Enable/disable interrupt */ + dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */ + dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */ + uint8_t channel; /**< Channel index */ +} dma_config_t; + +/** + * @brief DMA handle structure definition + */ +typedef struct +{ + DMA_TypeDef *perh; /**< DMA registers base address */ + dma_config_t config; /**< Channel configure structure. @ref dma_config_t */ + void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*err_cbk)(void *arg); /**< DMA bus occurs error callback */ + void *cplt_arg; /**< The parameter of cplt_cbk() */ + void *err_arg; /**< The parameter of err_cbk() */ +} dma_handle_t; +/** + * @} + */ + +/** + * @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ +#define IS_DMA_MSEL_TYPE(x) ((x) <= DMA_MSEL_TRNG) +#define IS_DMA_MSIGSEL_TYPE(x) ((x) <= 0xF) +#define IS_DMA_DATAINC_TYPE(x) (((x) == DMA_DATA_INC_BYTE) || \ + ((x) == DMA_DATA_INC_HALFWORD) || \ + ((x) == DMA_DATA_INC_WORD) || \ + ((x) == DMA_DATA_INC_NONE)) +#define IS_DMA_DATASIZE_TYPE(x) (((x) == DMA_DATA_SIZE_BYTE) || \ + ((x) == DMA_DATA_SIZE_HALFWORD) || \ + ((x) == DMA_DATA_SIZE_WORD)) +#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \ + ((x) == DMA_CYCLE_CTRL_BASIC) || \ + ((x) == DMA_CYCLE_CTRL_AUTO) || \ + ((x) == DMA_CYCLE_CTRL_PINGPONG) || \ + ((x) == DMA_CYCLE_CTRL_MEM_SCATTER_GATHER) || \ + ((x) == DMA_CYCLE_CTRL_PER_SCATTER_GATHER)) +#define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \ + ((x) == DMA_R_POWER_2) || \ + ((x) == DMA_R_POWER_4) || \ + ((x) == DMA_R_POWER_8) || \ + ((x) == DMA_R_POWER_16) || \ + ((x) == DMA_R_POWER_32) || \ + ((x) == DMA_R_POWER_64) || \ + ((x) == DMA_R_POWER_128) || \ + ((x) == DMA_R_POWER_256) || \ + ((x) == DMA_R_POWER_512) || \ + ((x) == DMA_R_POWER_1024)) +#define IS_DMA(x) ((x) == DMA0) +#define IS_DMA_CHANNEL(x) ((x) <= 5) +#define IS_DMA_DATA_SIZE(x) ((x) <= 1024) +#define IS_DMA_IT_TYPE(x) (((x) <= 5) || ((x) == 31)) +/** + * @} + */ + +/** + * @addtogroup DMA_Public_Functions + * @{ + */ + +/** @addtogroup DMA_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +extern void ald_dma_reset(DMA_TypeDef *DMAx); +extern void ald_dma_init(DMA_TypeDef *DMAx); +extern void ald_dma_config_struct(dma_config_t *p); +/** + * @} + */ + + +/** @addtogroup DMA_Public_Functions_Group2 + * @{ + */ +/* Configure DMA channel functions */ +extern void ald_dma_config_auto(dma_handle_t *hperh); +extern void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size); +extern void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, + uint16_t size, uint8_t channel, void (*cbk)(void *arg)); +extern void ald_dma_config_basic(dma_handle_t *hperh); +extern void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size); +extern void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, + dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); +/** + * @} + */ + +/** @addtogroup DMA_Public_Functions_Group3 + * @{ + */ +/* DMA control functions */ +extern void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); +extern void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); +extern it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel); +extern flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel); +extern void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel); +void ald_dma_irq_handler(void); +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__ALD_DMA_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h similarity index 32% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h index 71449f946b42c3799864f70809ddcbdc7f9c0755..9a4a66b0686fcf6dd519a503252441dc25053be6 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h @@ -35,41 +35,41 @@ extern "C" { * @defgroup FLASH_Private_Macros FLASH Private Macros * @{ */ -#define FLASH_REG_UNLOCK() \ -do { \ - if (op_cmd == OP_FLASH) { \ - WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \ - WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \ - } \ - else { \ - WRITE_REG(MSC->INFOKEY, 0x7153BFD9); \ - WRITE_REG(MSC->INFOKEY, 0x0642CEA8); \ - } \ -} while (0) -#define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) -#define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) -#define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) -#define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) -#define FLASH_BASE_ADDR 0x00000000 -#define FLASH_PAGE_SIZE 1024UL -#define FLASH_WORD_SIZE 8UL -#define FLASH_TOTAL_SIZE 256UL -#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) -#define FLASH_WORD_MASK (FLASH_WORD_SIZE - 1) -#define IS_FLASH_ADDRESS(ADDR) ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE)) -#define IS_4BYTES_ALIGN(ADDR) (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0) -#define FLASH_PAGE_ADDR(ADDR) ((ADDR) & (~FLASH_PAGE_MASK)) -#define FLASH_PAGEEND_ADDR(ADDR) ((ADDR) | FLASH_PAGE_MASK) -#define FLASH_WORD_ADDR(ADDR) ((ADDR) & (~FLASH_WORD_MASK)) -#define FLASH_WORDEND_ADDR(ADDR) ((ADDR) | FLASH_WORD_MASK) -#define INFO_PAGE_SIZE 1024UL -#define INFO_PAGE_MASK (INFO_PAGE_SIZE - 1) -#define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK)) +#define FLASH_REG_UNLOCK() \ + do { \ + if (op_cmd == OP_FLASH) { \ + WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \ + WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \ + } \ + else { \ + WRITE_REG(MSC->INFOKEY, 0x7153BFD9); \ + WRITE_REG(MSC->INFOKEY, 0x0642CEA8); \ + } \ + } while (0) +#define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) +#define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) +#define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) +#define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) +#define FLASH_BASE_ADDR 0x00000000 +#define FLASH_PAGE_SIZE 1024UL +#define FLASH_WORD_SIZE 8UL +#define FLASH_TOTAL_SIZE 256UL +#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) +#define FLASH_WORD_MASK (FLASH_WORD_SIZE - 1) +#define IS_FLASH_ADDRESS(ADDR) ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE)) +#define IS_4BYTES_ALIGN(ADDR) (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0) +#define FLASH_PAGE_ADDR(ADDR) ((ADDR) & (~FLASH_PAGE_MASK)) +#define FLASH_PAGEEND_ADDR(ADDR) ((ADDR) | FLASH_PAGE_MASK) +#define FLASH_WORD_ADDR(ADDR) ((ADDR) & (~FLASH_WORD_MASK)) +#define FLASH_WORDEND_ADDR(ADDR) ((ADDR) | FLASH_WORD_MASK) +#define INFO_PAGE_SIZE 1024UL +#define INFO_PAGE_MASK (INFO_PAGE_SIZE - 1) +#define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK)) #ifdef USE_FLASH_FIFO -#define FLASH_FIFO 1 +#define FLASH_FIFO 1 #else -#define FLASH_FIFO 0 +#define FLASH_FIFO 0 #endif /** * @} @@ -80,19 +80,27 @@ do { \ */ typedef enum { - FLASH_CMD_AE = 0x000051AE, /**< Program area erase all */ - FLASH_CMD_PE = 0x00005EA1, /**< Page erase */ - FLASH_CMD_WP = 0x00005DA2, /**< Word program */ - FLASH_CMD_DATAPE = 0x00005BA4, /**< Data flash page page erase */ - FLASH_CMD_DATAWP = 0x00005AA5, /**< Data flash word program */ + FLASH_CMD_AE = 0x000051AE, /**< Program area erase all */ + FLASH_CMD_PE = 0x00005EA1, /**< Page erase */ + FLASH_CMD_WP = 0x00005DA2, /**< Word program */ + FLASH_CMD_DATAPE = 0x00005BA4, /**< Data flash page page erase */ + FLASH_CMD_DATAWP = 0x00005AA5, /**< Data flash word program */ } flash_cmd_type; typedef enum { - OP_FLASH = 0, /**< Operate Pragram area */ - OP_INFO = 1, /**< Operate info area */ + OP_FLASH = 0, /**< Operate Pragram area */ + OP_INFO = 1, /**< Operate info area */ } op_cmd_type; +/** + * @} + */ +/** @addtogroup Flash_Private_Functions + * @{ + */ +ald_status_t flash_page_erase(uint32_t addr); +ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo); /** * @} */ @@ -100,13 +108,12 @@ typedef enum /** @addtogroup Flash_Public_Functions * @{ */ -ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len); -ald_status_t flash_erase(uint32_t addr, uint16_t len); -ald_status_t flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len); +ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len); +ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len); +ald_status_t ald_flash_erase(uint32_t addr, uint16_t len); /** * @} */ - /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..a8a2e9ebe0571b01ebf85abc75c43957e3f85381 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h @@ -0,0 +1,288 @@ +/** + ********************************************************************************* + * + * @file ald_gpio.h + * @brief Header file of GPIO module driver + * + * @version V1.0 + * @date 07 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_GPIO_H__ +#define __ALD_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** + * @defgroup GPIO_Public_Macros GPIO Public Macros + * @{ + */ +#define GPIO_PIN_0 (1U << 0) +#define GPIO_PIN_1 (1U << 1) +#define GPIO_PIN_2 (1U << 2) +#define GPIO_PIN_3 (1U << 3) +#define GPIO_PIN_4 (1U << 4) +#define GPIO_PIN_5 (1U << 5) +#define GPIO_PIN_6 (1U << 6) +#define GPIO_PIN_7 (1U << 7) +#define GPIO_PIN_8 (1U << 8) +#define GPIO_PIN_9 (1U << 9) +#define GPIO_PIN_10 (1U << 10) +#define GPIO_PIN_11 (1U << 11) +#define GPIO_PIN_12 (1U << 12) +#define GPIO_PIN_13 (1U << 13) +#define GPIO_PIN_14 (1U << 14) +#define GPIO_PIN_15 (1U << 15) +#define GPIO_PIN_ALL (0xFFFF) +/** + * @} + */ + +/** + * @defgroup GPIO_Public_Types GPIO Public Types + * @{ + */ + +/** + * @brief GPIO mode + */ +typedef enum +{ + GPIO_MODE_CLOSE = 0x0, /**< Digital close Analog open */ + GPIO_MODE_INPUT = 0x1, /**< Input */ + GPIO_MODE_OUTPUT = 0x2, /**< Output */ +} gpio_mode_t; + +/** + * @brief GPIO open-drain or push-pull + */ +typedef enum +{ + GPIO_PUSH_PULL = 0x0, /**< Push-Pull */ + GPIO_OPEN_DRAIN = 0x2, /**< Open-Drain */ + GPIO_OPEN_SOURCE = 0x3, /**< Open-Source */ +} gpio_odos_t; + +/** + * @brief GPIO push-up or push-down + */ +typedef enum +{ + GPIO_FLOATING = 0x0,/**< Floating */ + GPIO_PUSH_UP = 0x1,/**< Push-Up */ + GPIO_PUSH_DOWN = 0x2,/**< Push-Down */ + GPIO_PUSH_UP_DOWN = 0x3,/**< Push-Up and Push-Down */ +} gpio_push_t; + +/** + * @brief GPIO output drive + */ +typedef enum +{ + GPIO_OUT_DRIVE_NORMAL = 0x0, /**< Normal current flow */ + GPIO_OUT_DRIVE_STRONG = 0x1, /**< Strong current flow */ +} gpio_out_drive_t; + +/** + * @brief GPIO filter + */ +typedef enum +{ + GPIO_FILTER_DISABLE = 0x0, /**< Disable filter */ + GPIO_FILTER_ENABLE = 0x1, /**< Enable filter */ +} gpio_filter_t; + +/** + * @brief GPIO type + */ +typedef enum +{ + GPIO_TYPE_CMOS = 0x0, /**< CMOS Type */ + GPIO_TYPE_TTL = 0x1, /**< TTL Type */ +} gpio_type_t; + +/** + * @brief GPIO functions + */ +typedef enum +{ + GPIO_FUNC_0 = 0, /**< function #0 */ + GPIO_FUNC_1 = 1, /**< function #1 */ + GPIO_FUNC_2 = 2, /**< function #2 */ + GPIO_FUNC_3 = 3, /**< function #3 */ + GPIO_FUNC_4 = 4, /**< function #4 */ + GPIO_FUNC_5 = 5, /**< function #5 */ + GPIO_FUNC_6 = 6, /**< function #6 */ + GPIO_FUNC_7 = 7, /**< function #7 */ +} gpio_func_t; + + +/** + * @brief GPIO Init Structure definition + */ +typedef struct +{ + gpio_mode_t mode; /**< Specifies the operating mode for the selected pins. + This parameter can be any value of @ref gpio_mode_t */ + gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins. + This parameter can be a value of @ref gpio_odos_t */ + gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins. + This parameter can be a value of @ref gpio_push_t */ + gpio_out_drive_t odrv; /**< Specifies the output driver for the selected pins. + This parameter can be a value of @ref gpio_out_drive_t */ + gpio_filter_t flt; /**< Specifies the input filter for the selected pins. + This parameter can be a value of @ref gpio_filter_t */ + gpio_type_t type; /**< Specifies the type for the selected pins. + This parameter can be a value of @ref gpio_type_t */ + gpio_func_t func; /**< Specifies the function for the selected pins. + This parameter can be a value of @ref gpio_func_t */ +} gpio_init_t; + +/** + * @brief EXTI trigger style + */ +typedef enum +{ + EXTI_TRIGGER_RISING_EDGE = 0, /**< Rising edge trigger */ + EXTI_TRIGGER_TRAILING_EDGE = 1, /**< Trailing edge trigger */ + EXTI_TRIGGER_BOTH_EDGE = 2, /**< Rising and trailing edge trigger */ +} exti_trigger_style_t; + +/** + * @brief EXTI filter clock select + */ +typedef enum +{ + EXTI_FILTER_CLOCK_10K = 0, /**< cks = 10KHz */ + EXTI_FILTER_CLOCK_32K = 1, /**< cks = 32KHz */ +} exti_filter_clock_t; + +/** + * @brief EXTI Init Structure definition + */ +typedef struct +{ + type_func_t filter; /**< Enable filter. */ + exti_filter_clock_t cks; /**< Filter clock select. */ + uint8_t filter_time; /**< Filter duration */ +} exti_init_t; +/** + * @} + */ + +/** + * @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define PIN_MASK 0xFFFF +#define UNLOCK_KEY 0x55AA + +#define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0)) +#define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \ + (GPIOx == GPIOB) || \ + (GPIOx == GPIOC) || \ + (GPIOx == GPIOD) || \ + (GPIOx == GPIOE) || \ + (GPIOx == GPIOF) || \ + (GPIOx == GPIOG) || \ + (GPIOx == GPIOH)) +#define IS_GPIO_MODE(x) (((x) == GPIO_MODE_CLOSE) || \ + ((x) == GPIO_MODE_INPUT) || \ + ((x) == GPIO_MODE_OUTPUT)) +#define IS_GPIO_ODOS(x) (((x) == GPIO_PUSH_PULL) || \ + ((x) == GPIO_OPEN_DRAIN) || \ + ((x) == GPIO_OPEN_SOURCE)) +#define IS_GPIO_PUPD(x) (((x) == GPIO_FLOATING) || \ + ((x) == GPIO_PUSH_UP) || \ + ((x) == GPIO_PUSH_DOWN) || \ + ((x) == GPIO_PUSH_UP_DOWN)) +#define IS_GPIO_ODRV(x) (((x) == GPIO_OUT_DRIVE_NORMAL) || \ + ((x) == GPIO_OUT_DRIVE_STRONG)) +#define IS_GPIO_FLT(x) (((x) == GPIO_FILTER_DISABLE) || \ + ((x) == GPIO_FILTER_ENABLE)) +#define IS_GPIO_TYPE(x) (((x) == GPIO_TYPE_TTL) || \ + ((x) == GPIO_TYPE_CMOS)) +#define IS_TRIGGER_STYLE(x) (((x) == EXTI_TRIGGER_RISING_EDGE) || \ + ((x) == EXTI_TRIGGER_TRAILING_EDGE) || \ + ((x) == EXTI_TRIGGER_BOTH_EDGE)) +#define IS_EXTI_FLTCKS_TYPE(x) (((x) == EXTI_FILTER_CLOCK_10K) || \ + ((x) == EXTI_FILTER_CLOCK_32K)) +#define IS_GPIO_FUNC(x) ((x) <= 7) +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions + * @{ + */ + +/** @addtogroup GPIO_Public_Functions_Group1 + * @{ + */ +void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init); +void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_func_default(GPIO_TypeDef *GPIOx); +void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init); +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions_Group2 + * @{ + */ +uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val); +void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx); +void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val); +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions_Group3 + * @{ + */ +void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status); +flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin); +void ald_gpio_exti_clear_flag_status(uint16_t pin); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_GPIO_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..a05aaf0ebb357a68831fa28efc094a41bef9601c --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h @@ -0,0 +1,534 @@ +/** + ********************************************************************************* + * + * @file ald_i2c.h + * @brief Header file of I2C driver + * + * @version V1.0 + * @date 15 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_I2C_H__ +#define __ALD_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" +#include "ald_cmu.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Public_Types I2C Public Types + * @{ + */ +/** + * @brief I2C Error Code + */ +typedef enum +{ + I2C_ERROR_NONE = 0x0, /**< No error */ + I2C_ERROR_BERR = 0x1, /**< Berr error */ + I2C_ERROR_ARLO = 0x2, /**< Arlo error */ + I2C_ERROR_AF = 0x4, /**< Af error */ + I2C_ERROR_OVR = 0x8, /**< Ovr error */ + I2C_ERROR_DMA = 0x10, /**< Dma error */ + I2C_ERROR_TIMEOUT = 0x20, /**< Timeout error */ +} i2c_error_t; + +/** + * @brief I2C state structure definition + */ +typedef enum +{ + I2C_STATE_RESET = 0x0, /**< Peripheral is not yet Initialized */ + I2C_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ + I2C_STATE_BUSY = 0x2, /**< An internal process is ongoing */ + I2C_STATE_BUSY_TX = 0x3, /**< Data Transmission process is ongoing */ + I2C_STATE_BUSY_RX = 0x4, /**< Data Reception process is ongoing */ + I2C_STATE_TIMEOUT = 0x5, /**< timeout state */ + I2C_STATE_ERROR = 0x6, /**< Error */ +} i2c_state_t; + +/** + * @brief I2C Duty Cycle + */ +typedef enum +{ + I2C_DUTYCYCLE_2 = 0x0, /**< duty cycle is 2 */ + I2C_DUTYCYCLE_16_9 = 0x4000, /**< duty cycle is 16/9 */ +} i2c_duty_t; + +/** + * @brief I2C Addressing Mode + */ +typedef enum +{ + I2C_ADDR_7BIT = 0x1, /**< 7 bit address */ + I2C_ADDR_10BIT = 0x2, /**< 10 bit address */ +} i2c_addr_t; + +/** + * @brief I2C Dual Addressing Mode + */ +typedef enum +{ + I2C_DUALADDR_DISABLE = 0x0, /**< dual address is disable */ + I2C_DUALADDR_ENABLE = 0x1, /**< dual address is enable */ +} i2c_dual_addr_t; + +/** + * @brief I2C General Call Addressing mode + */ +typedef enum +{ + I2C_GENERALCALL_DISABLE = 0x0, /**< feneral call address is disable */ + I2C_GENERALCALL_ENABLE = 0x40, /**< feneral call address is enable */ +} i2c_general_addr_t; + +/** + * @brief I2C Nostretch Mode + */ +typedef enum +{ + I2C_NOSTRETCH_DISABLE = 0x0, /**< Nostretch disable */ + I2C_NOSTRETCH_ENABLE = 0x80, /**< Nostretch enable */ +} i2c_nostretch_t; + +/** + * @brief I2C Memory Address Size + */ +typedef enum +{ + I2C_MEMADD_SIZE_8BIT = 0x1, /**< 8 bit memory address size */ + I2C_MEMADD_SIZE_16BIT = 0x10 /**< 10 bit memory address size */ +} i2c_addr_size_t; + +/** + * @brief I2C Flag Definition + */ +typedef enum +{ + I2C_FLAG_SB = (1U << 0), + I2C_FLAG_ADDR = (1U << 1), + I2C_FLAG_BTF = (1U << 2), + I2C_FLAG_ADD10 = (1U << 3), + I2C_FLAG_STOPF = (1U << 4), + I2C_FLAG_RXNE = (1U << 6), + I2C_FLAG_TXE = (1U << 7), + I2C_FLAG_BERR = (1U << 8), + I2C_FLAG_ARLO = (1U << 9), + I2C_FLAG_AF = (1U << 10), + I2C_FLAG_OVR = (1U << 11), + I2C_FLAG_PECERR = (1U << 12), + I2C_FLAG_TIMEOUT = (1U << 14), + I2C_FLAG_SMBALERT = (1U << 15), + I2C_FLAG_MSL = (1U << 16), + I2C_FLAG_BUSY = (1U << 17), + I2C_FLAG_TRA = (1U << 18), + I2C_FLAG_GENCALL = (1U << 20), + I2C_FLAG_SMBDEFAULT = (1U << 21), + I2C_FLAG_SMBHOST = (1U << 22), + I2C_FLAG_DUALF = (1U << 23), +} i2c_flag_t; + +/** + * @brief I2C mode structure definition + */ +typedef enum +{ + I2C_MODE_NONE = 0x0, /**< No I2C communication on going */ + I2C_MODE_MASTER = 0x10, /**< I2C communication is in Master mode */ + I2C_MODE_SLAVE = 0x20, /**< I2C communication is in Slave mode */ + I2C_MODE_MEM = 0x40, /**< I2C communication is in Memory mode */ +} i2c_mode_t; + +/** + * @brief I2C Clock + */ +typedef enum +{ + I2C_STANDARD_MODE_MAX_CLK = 100000, /**< Standard mode clock */ + I2C_FAST_MODE_MAX_CLK = 400000, /**< Fast mode clock */ +} i2c_clock_t; + +/** + * @brief Interrupt Configuration Definition + */ +typedef enum +{ + I2C_IT_BUF = (1U << 10), /**< Buffer interrupt */ + I2C_IT_EVT = (1U << 9), /**< Event interrupt */ + I2C_IT_ERR = (1U << 8), /**< Error interrupt */ +} i2c_interrupt_t; + +/** + * @brief I2C CON1 Register + */ +typedef enum +{ + I2C_CON1_PEN = (1U << 0), /**< PEN BIT */ + I2C_CON1_PMOD = (1U << 1), /**< PMOD BIT */ + I2C_CON1_SMBMOD = (1U << 3), /**< SMBMOD BIT */ + I2C_CON1_ARPEN = (1U << 4), /**< ARPEN BIT */ + I2C_CON1_PECEN = (1U << 5), /**< PECEN BIT */ + I2C_CON1_GCEN = (1U << 6), /**< GCEN BIT */ + I2C_CON1_DISCS = (1U << 7), /**< DISCS BIT */ + I2C_CON1_START = (1U << 8), /**< START BIT */ + I2C_CON1_STOP = (1U << 9), /**< STOP BIT */ + I2C_CON1_ACKEN = (1U << 10), /**< ACKEN BIT */ + I2C_CON1_POSAP = (1U << 11), /**< POSAP BIT */ + I2C_CON1_TRPEC = (1U << 12), /**< TRPEC BIT */ + I2C_CON1_ALARM = (1U << 13), /**< ALARM BIT */ + I2C_CON1_SRST = (1U << 15), /**< SRST BIT */ +} i2c_con1_t; + +/** + * @brief I2C CON2 Register + */ +typedef enum +{ + I2C_CON2_CLKF = 0x3F, /**< CLKF BITS */ + I2C_CON2_CLKF_0 = (1U << 0), /**< CLKF_0 BIT */ + I2C_CON2_CLKF_1 = (1U << 1), /**< CLKF_1 BIT */ + I2C_CON2_CLKF_2 = (1U << 2), /**< CLKF_2 BIT */ + I2C_CON2_CLKF_3 = (1U << 3), /**< CLKF_3 BIT */ + I2C_CON2_CLKF_4 = (1U << 4), /**< CLKF_4 BIT */ + I2C_CON2_CLKF_5 = (1U << 5), /**< CLKF_5 BIT */ + I2C_CON2_ERRIE = (1U << 8), /**< ERRIE BIT */ + I2C_CON2_EVTIE = (1U << 9), /**< EVTIE BIT */ + I2C_CON2_BUFIE = (1U << 10), /**< BUFIE BIT */ + I2C_CON2_DMAEN = (1U << 11), /**< DMAEN BIT */ + I2C_CON2_LDMA = (1U << 12), /**< LDMA BIT */ +} i2c_con2_t; + +/** + * @brief I2C ADDR1 Register + */ +typedef enum +{ + I2C_ADDR1_ADDH0 = (1U << 0), /**< ADDH0 BIT */ + I2C_ADDR1_ADDH1 = (1U << 1), /**< ADDH1 BIT */ + I2C_ADDR1_ADDH2 = (1U << 2), /**< ADDH2 BIT */ + I2C_ADDR1_ADDH3 = (1U << 3), /**< ADDH3 BIT */ + I2C_ADDR1_ADDH4 = (1U << 4), /**< ADDH4 BIT */ + I2C_ADDR1_ADDH5 = (1U << 5), /**< ADDH5 BIT */ + I2C_ADDR1_ADDH6 = (1U << 6), /**< ADDH6 BIT */ + I2C_ADDR1_ADDH7 = (1U << 7), /**< ADDH7 BIT */ + I2C_ADDR1_ADDH8 = (1U << 8), /**< ADDH8 BIT */ + I2C_ADDR1_ADDH9 = (1U << 9), /**< ADDH9 BIT */ + I2C_ADDR1_ADDTYPE = (1U << 15), /**< ADDTYPE BIT */ +} i2c_addr1_t; + +/** + * @brief I2C ADDR2 Register + */ +typedef enum +{ + I2C_ADDR2_DUALEN = (1U << 0), /**< DUALEN BIT */ + I2C_ADDR2_ADD = (1U << 1), /**< ADD BIT */ +} i2c_addr2_t; + +/** + * @brief I2C STAT1 Register + */ +typedef enum +{ + I2C_STAT1_SB = (1U << 0), /**< SB BIT */ + I2C_STAT1_ADDR = (1U << 1), /**< ADDR BIT */ + I2C_STAT1_BTC = (1U << 2), /**< BTC BIT */ + I2C_STAT1_SENDADD10 = (1U << 3), /**< SENDADD10 BIT */ + I2C_STAT1_DETSTP = (1U << 4), /**< DETSTP BIT */ + I2C_STAT1_RXBNE = (1U << 6), /**< RXBNE BIT */ + I2C_STAT1_TXBE = (1U << 7), /**< TXBE BIT */ + I2C_STAT1_BUSERR = (1U << 8), /**< BUSERR BIT */ + I2C_STAT1_LARB = (1U << 9), /**< LARB BIT */ + I2C_STAT1_ACKERR = (1U << 10), /**< ACKERR BIT */ + I2C_STAT1_ROUERR = (1U << 11), /**< ROUERR BIT */ + I2C_STAT1_PECERR = (1U << 12), /**< PECERR BIT */ + I2C_STAT1_SMBTO = (1U << 14), /**< SMBTO BIT */ + I2C_STAT1_SMBALARM = (1U << 15), /**< SMBALARM BIT */ +} i2c_stat1_t; + +/** + * @brief I2C STAT2 Register + */ +typedef enum +{ + I2C_STAT2_MASTER = (1U << 0), /**< MASTER BIT */ + I2C_STAT2_BSYF = (1U << 1), /**< BSYF BIT */ + I2C_STAT2_TRF = (1U << 2), /**< TRF BIT */ + I2C_STAT2_RXGCF = (1U << 4), /**< RXGCF BIT */ + I2C_STAT2_SMBDEF = (1U << 5), /**< SMBDEF BIT */ + I2C_STAT2_SMBHH = (1U << 6), /**< SMBHH BIT */ + I2C_STAT2_DUALF = (1U << 7), /**< DMF BIT */ + I2C_STAT2_PECV = (1U << 8), /**< PECV BIT */ +} i2c_stat2_t; + +/** + * @brief I2C CKCFG Register + */ +typedef enum +{ + I2C_CKCFG_CLKSET = 0xFFF, /**< CLKSET BITS */ + I2C_CKCFG_DUTY = (1U << 14), /**< DUTY BIT */ + I2C_CKCFG_CLKMOD = (1U << 15), /**< CLKMOD BIT */ +} i2c_ckcfg_t; + +/** + * @brief I2C RT Register + */ +typedef enum +{ + I2C_RT_RISET = 0x3F, /**< RISET BITS */ +} i2c_trise_t; + +/** + * @brief I2C Configuration Structure definition + */ +typedef struct +{ + uint32_t clk_speed; /**< Specifies the clock frequency */ + i2c_duty_t duty; /**< Specifies the I2C fast mode duty cycle */ + uint32_t own_addr1; /**< Specifies the first device own address */ + i2c_addr_t addr_mode; /**< Specifies addressing mode */ + i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ + uint32_t own_addr2; /**< Specifies the second device own address */ + i2c_general_addr_t general_call; /**< Specifies if general call mode is selected */ + i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ +} i2c_init_t; + +/** + * @brief I2C handle Structure definition + */ +typedef struct i2c_handle_s +{ + I2C_TypeDef *perh; /**< I2C registers base address */ + i2c_init_t init; /**< I2C communication parameters */ + uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ + uint16_t xfer_size; /**< I2C transfer size */ + __IO uint16_t xfer_count; /**< I2C transfer counter */ +#ifdef ALD_DMA + dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ +#endif + lock_state_t lock; /**< I2C locking object */ + __IO i2c_state_t state; /**< I2C communication state */ + __IO i2c_mode_t mode; /**< I2C communication mode */ + __IO uint32_t error_code; /**< I2C Error code */ + + void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Tx completed callback */ + void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Rx completed callback */ + void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Tx completed callback */ + void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Rx completed callback */ + void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Tx to Memory completed callback */ + void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Rx from Memory completed callback */ + void (*error_callback)(struct i2c_handle_s *arg); /**< Error callback */ +} i2c_handle_t; + +/** + * @} + */ + +/** @defgroup I2C_Public_Macro I2C Public Macros + * @{ + */ +#define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET) +#define I2C_CLEAR_ADDRFLAG(x) \ + do { \ + __IO uint32_t tmpreg; \ + tmpreg = (x)->perh->STAT1; \ + tmpreg = (x)->perh->STAT2; \ + UNUSED(tmpreg); \ + } while (0) +#define __I2C_CLEAR_STOPFLAG(x) \ + do { \ + __IO uint32_t tmpreg; \ + tmpreg = (x)->perh->STAT1; \ + tmpreg = SET_BIT((x)->perh->CON1, I2C_CON1_PEN); \ + UNUSED(tmpreg); \ + } while (0) +#define I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) +#define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK)) +/** + * @} + */ + +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ +#define IS_I2C_TYPE(x) (((x) == I2C0) || \ + ((x) == I2C1)) +#define IS_I2C_ADDRESSING_MODE(x) (((x) == I2C_ADDR_7BIT) || \ + ((x) == I2C_ADDR_10BIT)) +#define IS_I2C_DUAL_ADDRESS(x) (((x) == I2C_DUALADDR_DISABLE) || \ + ((x) == I2C_DUALADDR_ENABLE)) +#define IS_I2C_GENERAL_CALL(x) (((x) == I2C_GENERALCALL_DISABLE) || \ + ((x) == I2C_GENERALCALL_ENABLE)) +#define IS_I2C_MEMADD_size(x) (((x) == I2C_MEMADD_SIZE_8BIT) || \ + ((x) == I2C_MEMADD_SIZE_16BIT)) +#define IS_I2C_NO_STRETCH(x) (((x) == I2C_NOSTRETCH_DISABLE) || \ + ((x) == I2C_NOSTRETCH_ENABLE)) +#define IS_I2C_OWN_ADDRESS1(x) (((x) & (uint32_t)(0xFFFFFC00)) == 0) +#define IS_I2C_OWN_ADDRESS2(x) (((x) & (uint32_t)(0xFFFFFF01)) == 0) +#define IS_I2C_CLOCK_SPEED(x) (((x) > 0) && ((x) <= I2C_FAST_MODE_MAX_CLK)) +#define IS_I2C_DUTY_CYCLE(x) (((x) == I2C_DUTYCYCLE_2) || \ + ((x) == I2C_DUTYCYCLE_16_9)) +#define IS_I2C_IT_TYPE(x) (((x) == I2C_IT_BUF) || \ + ((x) == I2C_IT_EVT) || \ + ((x) == I2C_IT_ERR)) +#define IS_I2C_FLAG(x) (((x) == I2C_FLAG_SB) || \ + ((x) == I2C_FLAG_ADDR) || \ + ((x) == I2C_FLAG_BTF) || \ + ((x) == I2C_FLAG_ADD10) || \ + ((x) == I2C_FLAG_STOPF) || \ + ((x) == I2C_FLAG_RXNE) || \ + ((x) == I2C_FLAG_TXE) || \ + ((x) == I2C_FLAG_BERR) || \ + ((x) == I2C_FLAG_ARLO) || \ + ((x) == I2C_FLAG_AF) || \ + ((x) == I2C_FLAG_OVR) || \ + ((x) == I2C_FLAG_PECERR) || \ + ((x) == I2C_FLAG_TIMEOUT) || \ + ((x) == I2C_FLAG_SMBALERT) || \ + ((x) == I2C_FLAG_MSL) || \ + ((x) == I2C_FLAG_BUSY) || \ + ((x) == I2C_FLAG_TRA) || \ + ((x) == I2C_FLAG_GENCALL) || \ + ((x) == I2C_FLAG_SMBDEFAULT) || \ + ((x) == I2C_FLAG_SMBHOST) || \ + ((x) == I2C_FLAG_DUALF)) + +#define I2C_FREQ_RANGE(x) ((x) / 1000000) +#define I2C_RISE_TIME(x, u) (((u) <= I2C_STANDARD_MODE_MAX_CLK) ? ((x) + 1) :\ + ((((x) * 300) / 1000) + 1)) +#define I2C_SPEED_STANDARD(x, y) (((((x) / ((y) << 1)) & I2C_CKCFG_CLKSET) < 4) ? 4:\ + ((x) / ((y) << 1))) +#define I2C_SPEED_FAST(x, y, z) (((z) == I2C_DUTYCYCLE_2) ? ((x) / ((y) * 3)) :\ + (((x) / ((y) * 25)) | I2C_DUTYCYCLE_16_9)) +#define I2C_SPEED(x, y, z) (((y) <= 100000) ? (I2C_SPEED_STANDARD((x), (y))) :\ + ((I2C_SPEED_FAST((x), (y), (z)) & I2C_CKCFG_CLKSET) == 0) ? 1 : \ + ((I2C_SPEED_FAST((x), (y), (z))) | I2C_CKCFG_CLKMOD)) +#define I2C_MEM_ADD_MSB(x) ((uint8_t)((uint16_t)(((uint16_t)((x) &\ + (uint16_t)(0xFF00))) >> 8))) +#define I2C_MEM_ADD_LSB(x) ((uint8_t)((uint16_t)((x) & (uint16_t)(0x00FF)))) +#define I2C_7BIT_ADD_WRITE(x) ((uint8_t)((x) & (~I2C_ADDR1_ADDH0))) +#define I2C_7BIT_ADD_READ(x) ((uint8_t)((x) | I2C_ADDR1_ADDH0)) +#define I2C_10BIT_ADDRESS(x) ((uint8_t)((uint16_t)((x) & (uint16_t)(0x00FF)))) +#define I2C_10BIT_HEADER_WRITE(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ + (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) +#define I2C_10BIT_HEADER_READ(x) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\ + (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions + * @{ + */ + +/** @addtogroup I2C_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_i2c_init(i2c_handle_t *hperh); +ald_status_t ald_i2c_reset(i2c_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group2 + * @{ + */ +/** Blocking mode: Polling */ +ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout); + +/** Non-Blocking mode: Interrupt */ +ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); +ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size); +ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); +ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size); + +#ifdef ALD_DMA +/** Non-Blocking mode: DMA */ +ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel); +#endif +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group3 + * @{ + */ +i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh); +uint32_t ald_i2c_get_error(i2c_handle_t *hperh); +flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag); +flag_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it); +void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag); +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group4 + * @{ + */ +void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state); +void ald_i2c_ev_irq_handler(i2c_handle_t *hperh); +void ald_i2c_er_irq_handler(i2c_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_I2C_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h similarity index 74% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h index 4109bed4b15b907d536d1d3790995f5927fc6b88..7a841e7c2a32601e2bc3445920576765863ed8dd 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h @@ -36,10 +36,10 @@ extern "C" { * @defgroup IAP_Private_Macros IAP Private Macros * @{ */ -#define IAP_WSP_ADDR 0x10000000 -#define IAP_PE_ADDR 0x10000004 -#define IAP_WP_ADDR 0x10000008 -#define IAP_DWP_ADDR 0x1000000c +#define IAP_WSP_ADDR 0x10000000 +#define IAP_PE_ADDR 0x10000004 +#define IAP_WP_ADDR 0x10000008 +#define IAP_DWP_ADDR 0x1000000c /** * @} */ @@ -58,10 +58,10 @@ typedef uint32_t (*IAP_WSP)(uint32_t addr, uint8_t *data, uint32_t len, uint32_t /** @addtogroup IAP_Public_Functions * @{ */ -uint32_t iap_erase_page(uint32_t addr); -uint32_t iap_program_word(uint32_t addr, uint32_t data); -uint32_t iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h); -uint32_t iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase); +uint32_t ald_iap_erase_page(uint32_t addr); +uint32_t ald_iap_program_word(uint32_t addr, uint32_t data); +uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h); +uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase); /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h new file mode 100644 index 0000000000000000000000000000000000000000..a40bc998d119597634ffde2fca08300e5164b7f6 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h @@ -0,0 +1,692 @@ +/** + ********************************************************************************* + * + * @file ald_pis.h + * @brief Header file of PIS driver. + * + * @version V1.0 + * @date 27 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_PIS_H__ +#define __ALD_PIS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup PIS + * @{ + */ + +/** @defgroup PIS_Public_Types PIS Public Types + * @{ + */ +/** + * @brief Producer entry + * @note ES32F065x: + * AD16C4T0--TIMER0 + * GP16C4T0--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + * + * ES32F033x: + * ES32F093x: + * GP16C4T0--TIMER0 + * GP16C4T1--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + */ +typedef enum +{ + PIS_NON = 0x0, /**< No async */ + PIS_GPIO_PIN0 = 0x10, /**< Pin0, level,support async */ + PIS_GPIO_PIN1 = 0x11, /**< Pin1, level,support async */ + PIS_GPIO_PIN2 = 0x12, /**< Pin2, level,support async */ + PIS_GPIO_PIN3 = 0x13, /**< Pin3, level,support async */ + PIS_GPIO_PIN4 = 0x14, /**< Pin4, level,support async */ + PIS_GPIO_PIN5 = 0x15, /**< Pin5, level,support async */ + PIS_GPIO_PIN6 = 0x16, /**< Pin6, level,support async */ + PIS_GPIO_PIN7 = 0x17, /**< Pin7, level,support async */ + PIS_GPIO_PIN8 = 0x18, /**< Pin8, level,support async */ + PIS_GPIO_PIN9 = 0x19, /**< Pin9, level,support async */ + PIS_GPIO_PIN10 = 0x1a, /**< Pin10, level,support async */ + PIS_GPIO_PIN11 = 0x1b, /**< Pin11, level,support async */ + PIS_GPIO_PIN12 = 0x1c, /**< Pin12, level,support async */ + PIS_GPIO_PIN13 = 0x1d, /**< Pin13, level,support async */ + PIS_GPIO_PIN14 = 0x1e, /**< Pin14, level,support async */ + PIS_GPIO_PIN15 = 0x1f, /**< Pin15, level,support async */ + PIS_ACMP_OUT0 = 0x30, /**< Acmp0 output, level,support async */ + PIS_ACMP_OUT1 = 0x31, /**< Acmp1 output, level,support async */ + PIS_DAC0_CH0 = 0x40, /**< Dac0 channel 0, pclk2 pulse,support async */ + PIS_DAC0_CH1 = 0x41, /**< Dac0 channel 1, pclk2 pulse,support async */ + PIS_ADC0_INJECT = 0x60, /**< Adc0 inject, pclk2 pulse,support async */ + PIS_ADC0_REGULAT = 0x61, /**< Adc0 regulat, pclk2 pulse,support async */ + PIS_ADC0_WINDOW = 0x62, /**< Adc0 window, no have */ + PIS_LVD = 0x70, /**< Lvd, level,support async */ + PIS_UART0_ASY_SEND = 0x80, /**< Uart0 asy send, pulse,support async */ + PIS_UART0_ASY_RECV = 0x81, /**< Uart0 asy recv, pulse,support async */ + PIS_UART0_IRDAOUT = 0x82, /**< Uart0 irdaout, level,support async */ + PIS_UART0_RTSOUT = 0x83, /**< Uart0 rtsout, level,support async */ + PIS_UART0_TXOUT = 0x84, /**< Uart0 txout, level,support async */ + PIS_UART0_SYN_SEND = 0x85, /**< Uart0 syn send, pulse,support async */ + PIS_UART0_SYN_RECV = 0x86, /**< Uart0 syn recv, pulse,support async */ + PIS_UART1_ASY_SEND = 0x90, /**< Uart1 asy send, pulse,support async */ + PIS_UART1_ASY_RECV = 0x91, /**< Uart1 asy recv, pulse,support async */ + PIS_UART1_IRDA = 0x92, /**< Uart1 irdaout, level,support async */ + PIS_UART1_RTS = 0x93, /**< Uart1 rtsout, level,support async */ + PIS_UART1_TXOUT = 0x94, /**< Uart1 txout, level,support async */ + PIS_UART1_SYN_SEND = 0x95, /**< Uart1 syn send, pulse,support async */ + PIS_UART1_SYN_RECV = 0x96, /**< Uart1 syn recv, pulse,support async */ + PIS_UART2_ASY_SEND = 0xa0, /**< Uart2 asy send, pulse,support async */ + PIS_UART2_ASY_RECV = 0xa1, /**< Uart2 asy recv, pulse,support async */ + PIS_UART2_IRDA = 0xa2, /**< Uart2 irdaout, level,support async */ + PIS_UART2_RTS = 0xa3, /**< Uart2 rtsout, level,support async */ + PIS_UART2_TXOUT = 0xa4, /**< Uart2 txout, level,support async */ + PIS_UART2_SYN_SEND = 0xa5, /**< Uart2 syn send, pulse,support async */ + PIS_UART2_SYN_RECV = 0xa6, /**< Uart2 syn recv, pulse,support async */ + PIS_UART3_ASY_SEND = 0xb1, /**< Uart3 asy send, pulse,support async */ + PIS_UART3_ASY_RECV = 0xb2, /**< Uart3 asy recv, pulse,support async */ + PIS_UART3_IRDA = 0xb3, /**< Uart3 irdaout, level,support async */ + PIS_UART3_RTS = 0xb4, /**< Uart3 rtsout, level,support async */ + PIS_UART3_TXOUT = 0xb5, /**< Uart3 txout, level,support async */ + PIS_UART3_SYN_SEND = 0xb6, /**< Uart3 syn send, pulse,support async */ + PIS_UART3_SYN_RECV = 0xb7, /**< Uart3 syn recv, pulse,support async */ + PIS_EUART0_RECV = 0xc0, /**< Euart0 recv, plck1 pulse */ + PIS_EUART0_SEND = 0xc1, /**< Euart0 send, plck1 pulse */ + PIS_EUART0_TXOUT = 0xc2, /**< Euart0 txout, plck1 level */ + PIS_EUART1_RECV = 0xd0, /**< Euart1 recv, plck1 pulse */ + PIS_EUART1_SEND = 0xd1, /**< Euart1 send, plck1 pulse */ + PIS_EUART1_TXOUT = 0xd2, /**< Euart1 txout, plck1 level */ + PIS_SPI0_RECV = 0xe0, /**< Spi0 recv, plck1 pulse */ + PIS_SPI0_SEND = 0xe1, /**< Spi0 send, plck1 pulse */ + PIS_SPI0_NE = 0xe2, /**< Spi0 ne, plck1 level */ + PIS_SPI1_RECV = 0xf0, /**< Spi1 recv, plck1 pulse */ + PIS_SPI1_SEND = 0xf1, /**< Spi1 send, plck1 pulse */ + PIS_SPI1_NE = 0xf2, /**< Spi1 ne, plck1 level */ + PIS_I2C0_RECV = 0x100, /**< I2c0 recv, plck1 level */ + PIS_I2C0_SEND = 0x101, /**< I2c0 send, plck1 level */ + PIS_I2C1_RECV = 0x110, /**< I2c1 recv, plck1 level */ + PIS_I2C1_SEND = 0x111, /**< I2c1 send, plck1 level */ + PIS_TIMER0_UPDATA = 0x120, /**< Timer0 updata, plck1 pulse */ + PIS_TIMER0_TRIG = 0x121, /**< Timer0 trig, plck1 pulse */ + PIS_TIMER0_INPUT = 0x122, /**< Timer0 input, plck1 pulse */ + PIS_TIMER0_OUTPUT = 0x123, /**< Timer0 output, plck1 pulse */ + PIS_TIMER1_UPDATA = 0x130, /**< Timer1 updata, plck1 pulse */ + PIS_TIMER1_TRIG = 0x131, /**< Timer1 trig, plck1 pulse */ + PIS_TIMER1_INPUT = 0x132, /**< Timer1 input, plck1 pulse */ + PIS_TIMER1_OUTPUT = 0x133, /**< Timer1 output, plck1 pulse */ + PIS_TIMER2_UPDATA = 0x140, /**< Timer2 updata, plck1 pulse */ + PIS_TIMER2_TRIG = 0x141, /**< Timer2 trig, plck1 pulse */ + PIS_TIMER2_INPUT = 0x142, /**< Timer2 input, plck1 pulse */ + PIS_TIMER2_OUTPUT = 0x143, /**< Timer2 output, plck1 pulse */ + PIS_TIMER3_UPDATA = 0x150, /**< Timer0 updata, plck1 pulse */ + PIS_TIMER3_TRIG = 0x151, /**< Timer0 trig, plck1 pulse */ + PIS_TIMER3_INPUT = 0x152, /**< Timer0 input, plck1 pulse */ + PIS_TIMER3_OUTPUT = 0x153, /**< Timer0 output, plck1 pulse */ + PIS_RTC_CLOCK = 0x160, /**< Rtc clock, pulse,support async */ + PIS_RTC_ALARM = 0x161, /**< Rtc alarm, pulse,support async */ + PIS_LPTIM0_SYN_UPDATA = 0x170, /**< Lptimer0 syn updata, pulse,support async */ + PIS_LPTIM0_ASY_UPDATA = 0x171, /**< Lptimer0 asy updata, pulse,support async */ + PIS_LPUART0_ASY_RECV = 0x180, /**< Lpuart0 asy recv, pulse,support async */ + PIS_LPUART0_ASY_SEND = 0x181, /**< Lpuart0 asy send, pulse,support async */ + PIS_LPUART0_SYN_RECV = 0x182, /**< Lpuart0 syn recv, pulse,support async */ + PIS_LPUART0_SYN_SEND = 0x183, /**< Lpuart0 syn recv, pulse,support async */ + PIS_DMA = 0x190, /**< Dma, pulse,support async */ + PIS_ADC1_INJECT = 0x1a0, /**< Adc1 inject, pclk2 pulse,support async */ + PIS_ADC1_REGULAT = 0x1a1, /**< Adc1 regulat, pclk2 pulse,support async */ + PIS_ADC1_WINDOW = 0x1a2, /**< Adc1 window, no have */ +} pis_src_t; + +/** + * @brief Consumer entry + * @note ES32F065x: + * AD16C4T0--TIMER0 + * GP16C4T0--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + * + * ES32F033x: + * ES32F093x: + * GP16C4T0--TIMER0 + * GP16C4T1--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + */ +typedef enum +{ + PIS_CH0_TIMER0_BRKIN = 0x0400, /**< Timer0 brkin */ + PIS_CH0_SPI1_CLK = 0x0F10, /**< Spi1 clk */ + PIS_CH0_LPTIM0_EXT0 = 0x0030, /**< Lptimer0 ext0 */ + PIS_CH0_ADC1_NORMAL = 0x0030, /**< Adc1 normal */ + PIS_CH1_TIMER0_CH1IN = 0x0001, /**< Timer0 ch1in */ + PIS_CH1_TIMER2_CH1IN = 0x1001, /**< Timer2 ch1in */ + PIS_CH1_TIMER3_CH1IN = 0x1801, /**< Timer3 ch1in */ + PIS_CH1_LPTIM0_EXT1 = 0x0031, /**< Lptime0 ext1 */ + PIS_CH1_UART0_RX_IRDA = 0x0011, /**< Uart0 rx irda */ + PIS_CH1_ADC1_INSERT = 0x0031, /**< Adc1 insert */ + PIS_CH2_TIMER0_CH2IN = 0x0102, /**< Timer0 ch2in */ + PIS_CH2_TIMER2_CH2IN = 0x1102, /**< Timer2 ch2in */ + PIS_CH2_TIMER3_CH2IN = 0x1902, /**< Timer3 ch2in */ + PIS_CH2_LPTIM0_EXT2 = 0x0032, /**< Lptime0 ext2 */ + PIS_CH2_UART1_RX_IRDA = 0x0112, /**< Uart1 rx irda */ + PIS_CH3_TIMER0_CH3IN = 0x0203, /**< Timer0 ch3in */ + PIS_CH3_LPTIM0_EXT3 = 0x0033, /**< Lptime0 ext3 */ + PIS_CH3_UART2_RX_IRDA = 0x0213, /**< Uart2 rx irda */ + PIS_CH4_TIMER0_CH4IN = 0x0004, /**< Timer0 ch4in */ + PIS_CH4_TIMER0_ITR0 = 0x0034, /**< Timer0 itr0 */ + PIS_CH4_TIMER2_ITR0 = 0x0034, /**< Timer2 itr0 */ + PIS_CH4_TIMER3_ITR0 = 0x0034, /**< Timer3 itr0 */ + PIS_CH4_LPTIM0_EXT4 = 0x0434, /**< Lptime0 ext4 */ + PIS_CH4_UART3_RX_IRDA = 0x0314, /**< Uart3 rx irda */ + PIS_CH5_SPI0_RX = 0x0C15, /**< Spi0 rx */ + PIS_CH5_LPTIM0_EXT5 = 0x0035, /**< Lptime0 ext5 */ + PIS_CH5_EUART0_RX = 0x0615, /**< Euart0 rx */ + PIS_CH5_TIMER0_ITR1 = 0x0035, /**< Timer0 itr1 */ + PIS_CH5_TIMER2_ITR1 = 0x0035, /**< Timer2 itr1 */ + PIS_CH5_TIMER3_ITR1 = 0x0035, /**< Timer3 itr1 */ + PIS_CH6_SPI0_CLK = 0x0D16, /**< Spi0 clk */ + PIS_CH6_ADC0_NORMAL = 0x0036, /**< Adc0 normal */ + PIS_CH6_LPTIM0_EXT6 = 0x0036, /**< Lptime0 ext6 */ + PIS_CH6_EUART1_RX = 0x0716, /**< Euart1 rx */ + PIS_CH6_TIMER0_ITR2 = 0x0036, /**< Timer0 itr2 */ + PIS_CH6_TIMER2_ITR2 = 0x0036, /**< Timer2 itr2 */ + PIS_CH6_TIMER3_ITR2 = 0x0036, /**< Timer3 itr2 */ + PIS_CH6_DAC_CH1 = 0x0036, /**< Dac channel 1 */ + PIS_CH7_SPI1_RX = 0x0E17, /**< Spi1 rx */ + PIS_CH7_ADC0_INSERT = 0x0037, /**< Adc0 insert */ + PIS_CH7_LPTIM0_EXT7 = 0x0037, /**< Lptime0 ext7 */ + PIS_CH7_DMA = 0x0037, /**< Dma */ + PIS_CH7_TIMER0_ITR3 = 0x0037, /**< Timer0 itr3 */ + PIS_CH7_TIMER2_ITR3 = 0x0037, /**< Timer2 itr3 */ + PIS_CH7_TIMER3_ITR3 = 0x0037, /**< Timer3 itr3 */ + PIS_CH7_LPUART_RX = 0x0817, /**< Lpuart rx */ + PIS_CH7_DAC_CH0 = 0x0037, /**< Dac channel 0 */ +} pis_trig_t; + +/** + * @brief Clock select + */ +typedef enum +{ + PIS_CLK_PCLK1 = 0, /**< Pclock1 */ + PIS_CLK_PCLK2 = 1, /**< Pclock2 */ + PIS_CLK_SYS = 2, /**< Sys clock */ + PIS_CLK_LP = 3, /**< Low power clock */ +} pis_clock_t; + +/** + * @brief Level select + */ +typedef enum +{ + PIS_EDGE_NONE = 0, /**< None edge */ + PIS_EDGE_UP = 1, /**< Up edge */ + PIS_EDGE_DOWN = 2, /**< Down edge */ + PIS_EDGE_UP_DOWN = 3, /**< Up and down edge */ +} pis_edge_t; + +/** + * @brief Output style + */ +typedef enum +{ + PIS_OUT_LEVEL = 0, /**< Level */ + PIS_OUT_PULSE = 1, /**< Pulse */ +} pis_output_t; +/** + * @brief Sync select + */ +typedef enum +{ + PIS_SYN_DIRECT = 0, /**< Direct */ + PIS_SYN_ASY_PCLK1 = 1, /**< Asy pclk1 */ + PIS_SYN_ASY_PCLK2 = 2, /**< Asy pclk2 */ + PIS_SYN_ASY_PCLK = 3, /**< Asy pclk */ + PIS_SYN_PCLK2_PCLK1 = 4, /**< Pclk2 to pclk1 */ + PIS_SYN_PCLK1_PCLK2 = 5, /**< Pclk1 to pclk2 */ + PIS_SYN_PCLK12_SYS = 6, /**< Pclk1 or pclk2 to sysclk */ +} pis_syncsel_t; + +/** + * @brief Pis channel + */ +typedef enum +{ + PIS_CH_0 = 0, /**< Channel 0 */ + PIS_CH_1 = 1, /**< Channel 1 */ + PIS_CH_2 = 2, /**< Channel 2 */ + PIS_CH_3 = 3, /**< Channel 3 */ + PIS_CH_4 = 4, /**< Channel 4 */ + PIS_CH_5 = 5, /**< Channel 5 */ + PIS_CH_6 = 6, /**< Channel 6 */ + PIS_CH_7 = 7, /**< Channel 7 */ +} pis_ch_t; + +/** + * @brief Pis output channel + */ +typedef enum +{ + PIS_OUT_CH_0 = 0, /**< Channel 0 */ + PIS_OUT_CH_1 = 1, /**< Channel 1 */ + PIS_OUT_CH_2 = 2, /**< Channel 2 */ + PIS_OUT_CH_3 = 3, /**< Channel 3 */ +} pis_out_ch_t; + +/** + * @brief Indirect value,no care of it. + */ +typedef enum +{ + PIS_CON_0 = 0, /**< Con 0 */ + PIS_CON_1 = 1, /**< Con 1 */ + PIS_CON_NONE = 2, /**< None */ +} pis_con_t; + +/** + * @brief Indirect value,no care of it. + */ +typedef union +{ + struct + { + uint8_t ch : 4; /**< Channel */ + uint8_t con : 4; /**< Contorl */ + uint8_t shift : 8; /**< Shift */ + }; + uint16_t HalfWord; +} pis_divide_t; + +/** + * @brief PIS state structures definition + */ +typedef enum +{ + PIS_STATE_RESET = 0x00, /**< Peripheral is not initialized */ + PIS_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + PIS_STATE_BUSY = 0x02, /**< An internal process is ongoing */ + PIS_STATE_TIMEOUT = 0x03, /**< Timeout state */ + PIS_STATE_ERROR = 0x04, /**< Error */ +} pis_state_t; + +/** + * @brief PIS modulate target + */ +typedef enum +{ + PIS_UART0_TX = 0, /**< Modulate uart0 tx */ + PIS_UART1_TX = 1, /**< Modulate uart1 tx */ + PIS_UART2_TX = 2, /**< Modulate uart2 tx */ + PIS_UART3_TX = 3, /**< Modulate uart3 tx */ + PIS_LPUART0_TX = 4, /**< Modulate lpuart0 tx */ +} pis_modu_targ_t; + +/** + * @brief PIS modulate level + */ +typedef enum +{ + PIS_LOW_LEVEL = 0, /**< Modulate low level */ + PIS_HIGH_LEVEL = 1, /**< Modulate high level */ +} pis_modu_level_t; + +/** + * @brief PIS modulate source + * @note ES32F065x: + * AD16C4T0--TIMER0 + * GP16C4T0--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + * + * ES32F033x: + * ES32F093x: + * GP16C4T0--TIMER0 + * GP16C4T1--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + */ +typedef enum +{ + PIS_SRC_NONE = 0, /**< Stop modulate */ + PIS_SRC_TIMER0 = 1, /**< Modulate source is TIMER0 */ + PIS_SRC_TIMER1 = 2, /**< Modulate source is TIMER1 */ + PIS_SRC_TIMER2 = 3, /**< Modulate source is TIMER2 */ + PIS_SRC_TIMER3 = 4, /**< Modulate source is TIMER3 */ + PIS_SRC_TIMER6 = 5, /**< Modulate source is TIMER6 */ + PIS_SRC_TIMER7 = 6, /**< Modulate source is TIMER7 */ + PIS_SRC_LPTIM0 = 7, /**< Modulate source is LPTIM0 */ + PIS_SRC_BUZ = 8, /**< Modulate source is buz */ +} pis_modu_src_t; + +/** + * @brief PIS modulate channel + */ +typedef enum +{ + PIS_TIMER_CH1 = 0, /**< Src is TIMERx and choose channel 1 */ + PIS_TIMER_CH2 = 1, /**< Src is TIMERx and choose channel 2 */ + PIS_TIMER_CH3 = 2, /**< Src is TIMERx and choose channel 3 */ + PIS_TIMER_CH4 = 3, /**< Src is TIMERx and choose channel 4 */ +} pis_modu_channel_t; + +/** + * @brief PIS init structure definition + */ +typedef struct +{ + pis_src_t producer_src; /**< Producer entry */ + pis_clock_t producer_clk; /**< Producer module clock */ + pis_edge_t producer_edge; /**< Producer module pin output edge */ + pis_trig_t consumer_trig; /**< Consumer entry */ + pis_clock_t consumer_clk; /**< Consumer clock */ +} pis_init_t; + +/** + * @brief PIS modulate config structure definition + */ +typedef struct +{ + pis_modu_targ_t target; /**< Modulate target */ + pis_modu_level_t level; /**< Modulate level */ + pis_modu_src_t src; /**< Modulate src */ + pis_modu_channel_t channel; /**< Modulate channel */ +} pis_modulate_config_t; + +/** + * @brief PIS Handle Structure definition + */ +typedef struct pis_handle_s +{ + PIS_TypeDef *perh; /**< Register base address */ + pis_init_t init; /**< PIS required parameters */ + pis_ch_t consumer_ch; /**< Indirect value, no care of it */ + pis_con_t consumer_con; /**< Indirect value, no care of it */ + uint8_t consumer_pos; /**< Indirect value, no care of it */ + uint32_t check_info; /**< When destroy a handle ,user need check whether is right that ready to destroy */ + lock_state_t lock; /**< Locking object */ + pis_state_t state; /**< PIS operation state */ +} pis_handle_t; +/** + * @} + */ + + +/** @defgroup PIS_Private_Macros PIS Private Macros + * @{ + */ +#define IS_PIS(x) (((x) == PIS)) +#define IS_PIS_SRC(x) (((x) == PIS_NON) || \ + ((x) == PIS_GPIO_PIN0) || \ + ((x) == PIS_GPIO_PIN1) || \ + ((x) == PIS_GPIO_PIN2) || \ + ((x) == PIS_GPIO_PIN3) || \ + ((x) == PIS_GPIO_PIN4) || \ + ((x) == PIS_GPIO_PIN5) || \ + ((x) == PIS_GPIO_PIN6) || \ + ((x) == PIS_GPIO_PIN7) || \ + ((x) == PIS_GPIO_PIN8) || \ + ((x) == PIS_GPIO_PIN9) || \ + ((x) == PIS_GPIO_PIN10) || \ + ((x) == PIS_GPIO_PIN11) || \ + ((x) == PIS_GPIO_PIN12) || \ + ((x) == PIS_GPIO_PIN13) || \ + ((x) == PIS_GPIO_PIN14) || \ + ((x) == PIS_GPIO_PIN15) || \ + ((x) == PIS_ACMP_OUT0) || \ + ((x) == PIS_ACMP_OUT1) || \ + ((x) == PIS_DAC0_CH1) || \ + ((x) == PIS_ACMP_OUT1) || \ + ((x) == PIS_ADC0_INJECT) || \ + ((x) == PIS_ADC0_REGULAT) || \ + ((x) == PIS_ADC0_WINDOW) || \ + ((x) == PIS_LVD) || \ + ((x) == PIS_UART0_ASY_SEND) || \ + ((x) == PIS_UART0_ASY_RECV) || \ + ((x) == PIS_UART0_IRDAOUT) || \ + ((x) == PIS_UART0_RTSOUT) || \ + ((x) == PIS_UART0_TXOUT) || \ + ((x) == PIS_UART0_SYN_SEND) || \ + ((x) == PIS_UART0_SYN_RECV) || \ + ((x) == PIS_UART1_ASY_SEND) || \ + ((x) == PIS_UART1_ASY_RECV) || \ + ((x) == PIS_UART1_IRDA) || \ + ((x) == PIS_UART1_RTS) || \ + ((x) == PIS_UART1_TXOUT) || \ + ((x) == PIS_UART1_SYN_SEND) || \ + ((x) == PIS_UART1_SYN_RECV) || \ + ((x) == PIS_UART2_ASY_SEND) || \ + ((x) == PIS_UART2_ASY_RECV) || \ + ((x) == PIS_UART2_IRDA) || \ + ((x) == PIS_UART2_RTS) || \ + ((x) == PIS_UART2_TXOUT) || \ + ((x) == PIS_UART2_SYN_SEND) || \ + ((x) == PIS_UART2_SYN_RECV) || \ + ((x) == PIS_UART3_ASY_SEND) || \ + ((x) == PIS_UART3_ASY_RECV) || \ + ((x) == PIS_UART3_IRDA) || \ + ((x) == PIS_UART3_RTS) || \ + ((x) == PIS_UART3_TXOUT) || \ + ((x) == PIS_UART3_SYN_SEND) || \ + ((x) == PIS_UART3_SYN_RECV) || \ + ((x) == PIS_EUART0_RECV) || \ + ((x) == PIS_EUART0_SEND) || \ + ((x) == PIS_EUART0_TXOUT) || \ + ((x) == PIS_EUART1_RECV) || \ + ((x) == PIS_EUART1_SEND) || \ + ((x) == PIS_EUART1_TXOUT) || \ + ((x) == PIS_SPI0_RECV) || \ + ((x) == PIS_SPI0_SEND) || \ + ((x) == PIS_SPI0_NE) || \ + ((x) == PIS_SPI1_RECV) || \ + ((x) == PIS_SPI1_SEND) || \ + ((x) == PIS_SPI1_NE) || \ + ((x) == PIS_I2C0_RECV) || \ + ((x) == PIS_I2C0_SEND) || \ + ((x) == PIS_I2C1_RECV) || \ + ((x) == PIS_I2C1_SEND) || \ + ((x) == PIS_TIMER0_UPDATA) || \ + ((x) == PIS_TIMER0_TRIG) || \ + ((x) == PIS_TIMER0_INPUT) || \ + ((x) == PIS_TIMER0_OUTPUT) || \ + ((x) == PIS_TIMER1_UPDATA) || \ + ((x) == PIS_TIMER1_TRIG) || \ + ((x) == PIS_TIMER1_INPUT) || \ + ((x) == PIS_TIMER1_OUTPUT) || \ + ((x) == PIS_TIMER2_UPDATA) || \ + ((x) == PIS_TIMER2_TRIG) || \ + ((x) == PIS_TIMER2_INPUT) || \ + ((x) == PIS_TIMER2_OUTPUT) || \ + ((x) == PIS_TIMER3_UPDATA) || \ + ((x) == PIS_TIMER3_TRIG) || \ + ((x) == PIS_TIMER3_INPUT) || \ + ((x) == PIS_TIMER3_OUTPUT) || \ + ((x) == PIS_RTC_CLOCK) || \ + ((x) == PIS_RTC_ALARM) || \ + ((x) == PIS_LPTIM0_SYN_UPDATA) || \ + ((x) == PIS_LPTIM0_ASY_UPDATA) || \ + ((x) == PIS_LPUART0_ASY_RECV) || \ + ((x) == PIS_LPUART0_ASY_SEND) || \ + ((x) == PIS_LPUART0_SYN_RECV) || \ + ((x) == PIS_LPUART0_SYN_SEND) || \ + ((x) == PIS_DMA) || \ + ((x) == PIS_ADC1_INJECT) || \ + ((x) == PIS_ADC1_REGULAT) || \ + ((x) == PIS_ADC1_WINDOW)) +#define IS_PIS_TRIG(x) (((x) == PIS_CH0_TIMER0_BRKIN) || \ + ((x) == PIS_CH0_SPI1_CLK) || \ + ((x) == PIS_CH0_LPTIM0_EXT0) || \ + ((x) == PIS_CH0_ADC1_NORMAL) || \ + ((x) == PIS_CH1_TIMER0_CH1IN) || \ + ((x) == PIS_CH1_TIMER2_CH1IN) || \ + ((x) == PIS_CH1_TIMER3_CH1IN) || \ + ((x) == PIS_CH1_UART0_RX_IRDA) || \ + ((x) == PIS_CH1_LPTIM0_EXT1) || \ + ((x) == PIS_CH1_ADC1_INSERT) || \ + ((x) == PIS_CH2_TIMER0_CH2IN) || \ + ((x) == PIS_CH2_TIMER2_CH2IN) || \ + ((x) == PIS_CH2_TIMER3_CH2IN) || \ + ((x) == PIS_CH2_LPTIM0_EXT2) || \ + ((x) == PIS_CH2_UART1_RX_IRDA) || \ + ((x) == PIS_CH3_TIMER0_CH3IN) || \ + ((x) == PIS_CH3_LPTIM0_EXT3) || \ + ((x) == PIS_CH3_UART2_RX_IRDA) || \ + ((x) == PIS_CH4_TIMER0_CH4IN) || \ + ((x) == PIS_CH4_TIMER0_ITR0) || \ + ((x) == PIS_CH4_TIMER2_ITR0) || \ + ((x) == PIS_CH4_TIMER3_ITR0) || \ + ((x) == PIS_CH4_LPTIM0_EXT4) || \ + ((x) == PIS_CH4_UART3_RX_IRDA) || \ + ((x) == PIS_CH5_SPI0_RX) || \ + ((x) == PIS_CH5_LPTIM0_EXT5) || \ + ((x) == PIS_CH5_EUART0_RX) || \ + ((x) == PIS_CH5_TIMER0_ITR1) || \ + ((x) == PIS_CH5_TIMER2_ITR1) || \ + ((x) == PIS_CH5_TIMER3_ITR1) || \ + ((x) == PIS_CH6_SPI0_CLK) || \ + ((x) == PIS_CH6_ADC0_NORMAL) || \ + ((x) == PIS_CH6_LPTIM0_EXT6) || \ + ((x) == PIS_CH6_EUART1_RX) || \ + ((x) == PIS_CH6_TIMER0_ITR2) || \ + ((x) == PIS_CH6_TIMER2_ITR2) || \ + ((x) == PIS_CH6_TIMER3_ITR2) || \ + ((x) == PIS_CH6_DAC_CH1) || \ + ((x) == PIS_CH7_SPI1_RX) || \ + ((x) == PIS_CH7_ADC0_INSERT) || \ + ((x) == PIS_CH7_LPTIM0_EXT7) || \ + ((x) == PIS_CH7_DMA) || \ + ((x) == PIS_CH7_TIMER0_ITR3) || \ + ((x) == PIS_CH7_TIMER2_ITR3) || \ + ((x) == PIS_CH7_TIMER3_ITR3) || \ + ((x) == PIS_CH7_DAC_CH0) || \ + ((x) == PIS_CH7_LPUART_RX)) +#define IS_PIS_CLOCK(x) (((x) == PIS_CLK_PCLK1) || \ + ((x) == PIS_CLK_PCLK2) || \ + ((x) == PIS_CLK_SYS) || \ + ((x) == PIS_CLK_LP)) +#define IS_PIS_EDGE(x) (((x) == PIS_EDGE_NONE) || \ + ((x) == PIS_EDGE_UP) || \ + ((x) == PIS_EDGE_DOWN) || \ + ((x) == PIS_EDGE_UP_DOWN)) +#define IS_PIS_OUTPUT(x) (((x) == PIS_OUT_LEVEL) || \ + ((x) == PIS_OUT_PULSE)) +#define IS_PIS_OUPUT_CH(x) (((x) == PIS_OUT_CH_0) || \ + ((x) == PIS_OUT_CH_1) || \ + ((x) == PIS_OUT_CH_2) || \ + ((x) == PIS_OUT_CH_3)) +#define IS_PIS_MODU_TARGET(x) (((x) == PIS_UART0_TX) || \ + ((x) == PIS_UART1_TX) || \ + ((x) == PIS_UART2_TX) || \ + ((x) == PIS_UART3_TX) || \ + ((x) == PIS_LPUART0_TX)) +#define IS_PIS_MODU_LEVEL(x) (((x) == PIS_LOW_LEVEL) || \ + ((x) == PIS_HIGH_LEVEL)) +#define IS_PIS_MODU_SRC(x) (((x) == PIS_SRC_NONE) || \ + ((x) == PIS_SRC_TIMER0) || \ + ((x) == PIS_SRC_TIMER1) || \ + ((x) == PIS_SRC_TIMER2) || \ + ((x) == PIS_SRC_TIMER3) || \ + ((x) == PIS_SRC_TIMER6) || \ + ((x) == PIS_SRC_TIMER7) || \ + ((x) == PIS_SRC_LPTIM0) || \ + ((x) == PIS_SRC_BUZ)) +#define IS_PIS_MODU_CHANNEL(x) (((x) == PIS_TIMER_CH1) || \ + ((x) == PIS_TIMER_CH2) || \ + ((x) == PIS_TIMER_CH3) || \ + ((x) == PIS_TIMER_CH4)) +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions + * @{ + */ + +/** @addtogroup PIS_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_pis_create(pis_handle_t *hperh); +ald_status_t ald_pis_destroy(pis_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch); +ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group3 + * @{ + */ +pis_state_t ald_pis_get_state(pis_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group4 + * @{ + */ +ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_PIS_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h new file mode 100644 index 0000000000000000000000000000000000000000..85c962657879017c50feae5ab7b9380af454b5c7 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h @@ -0,0 +1,211 @@ +/** + ********************************************************************************* + * + * @file ald_pmu.h + * @brief Header file of PMU module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_PMU_H__ +#define __ALD_PMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_syscfg.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup PMU + * @{ + */ + +/** @defgroup PMU_Public_Macros PMU Public Macros + * @{ + */ +#define PMU_SRAM0_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS)); \ + SYSCFG_LOCK(); \ + } while (0) +#define PMU_SRAM0_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\ + SYSCFG_LOCK(); \ + } while (0) +#define PMU_SRAM1_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE)); \ + SYSCFG_LOCK(); \ + } while (0) +#define PMU_SRAM1_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\ + SYSCFG_LOCK(); \ + } while (0) +#define PMU_BXCAN_ENABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) +#define PMU_BXCAN_DISABLE() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) + +#define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS)) +/** + * @} + */ + + +/** @defgroup PMU_Public_Types PMU Public Types + * @{ + */ +/** + * @brief Low power mode + */ +typedef enum +{ + PMU_LP_STOP1 = 0x0, /**< Stop1 */ + PMU_LP_STOP2 = 0x1, /**< Stop2 */ +} pmu_lp_mode_t; + +typedef enum +{ + PMU_SR_WUF = (1U << 0), +} pmu_status_t; + +/** + * @brief LVD voltage select + */ +typedef enum +{ + PMU_LVD_VOL_SEL_2_0 = 0x0, /**< 2.0V ~ 2.05V */ + PMU_LVD_VOL_SEL_2_1 = 0x1, /**< 2.1V ~ 2.15V */ + PMU_LVD_VOL_SEL_2_2 = 0x2, /**< 2.2V ~ 2.25V */ + PMU_LVD_VOL_SEL_2_4 = 0x3, /**< 2.4V ~ 2.45V */ + PMU_LVD_VOL_SEL_2_6 = 0x4, /**< 2.6V ~ 2.65V */ + PMU_LVD_VOL_SEL_2_8 = 0x5, /**< 2.8V ~ 2.85V */ + PMU_LVD_VOL_SEL_3_0 = 0x6, /**< 3.0V ~ 3.05V */ + PMU_LVD_VOL_SEL_3_6 = 0x7, /**< 3.6V ~ 3.65V */ + PMU_LVD_VOL_SEL_4_0 = 0x8, /**< 4.0V ~ 4.05V */ + PMU_LVD_VOL_SEL_4_6 = 0x9, /**< 4.6V ~ 4.65V */ + PMU_LVD_VOL_SEL_2_3 = 0xA, /**< 2.3V ~ 2.35V */ + PMU_LVD_VOL_SEL_EXT = 0xF, /**< Select external input. It must be 1.2V */ +} pmu_lvd_voltage_sel_t; + +/** + * @brief LVD trigger mode + */ +typedef enum +{ + PMU_LVD_TRIGGER_RISING_EDGE = 0x0, /**< Rising edge */ + PMU_LVD_TRIGGER_FALLING_EDGE = 0x1, /**< Falling edge */ + PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2, /**< High level */ + PMU_LVD_TRIGGER_LOW_LEVEL = 0x3, /**< Low level */ + PMU_LVD_TRIGGER_RISING_FALLING = 0x4, /**< Rising and falling edge */ +} pmu_lvd_trigger_mode_t; + +/** + * @} + */ + +/** + * @defgroup PMU_Private_Macros PMU Private Macros + * @{ + */ +#define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \ + ((x) == PMU_LP_STOP2)) +#define IS_PMU_STATUS(x) ((x) == PMU_SR_WUF) +#define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_0) || \ + ((x) == PMU_LVD_VOL_SEL_2_1) || \ + ((x) == PMU_LVD_VOL_SEL_2_2) || \ + ((x) == PMU_LVD_VOL_SEL_2_4) || \ + ((x) == PMU_LVD_VOL_SEL_2_6) || \ + ((x) == PMU_LVD_VOL_SEL_2_8) || \ + ((x) == PMU_LVD_VOL_SEL_3_0) || \ + ((x) == PMU_LVD_VOL_SEL_3_6) || \ + ((x) == PMU_LVD_VOL_SEL_4_0) || \ + ((x) == PMU_LVD_VOL_SEL_4_6) || \ + ((x) == PMU_LVD_VOL_SEL_2_3) || \ + ((x) == PMU_LVD_VOL_SEL_EXT)) +#define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \ + ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \ + ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \ + ((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \ + ((x) == PMU_LVD_TRIGGER_RISING_FALLING)) +/** + * @} + */ + +/** @addtogroup PMU_Public_Functions + * @{ + */ +/** @addtogroup PMU_Public_Functions_Group1 + * @{ + */ +/* Low power mode select */ +__STATIC_INLINE__ void ald_pmu_sleep() +{ + __WFI(); +} + +__STATIC_INLINE__ void ald_pmu_sleep_deep() +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); +} + +void ald_pmu_stop1_enter(void); +void ald_pmu_stop2_enter(void); +flag_status_t ald_pmu_get_status(pmu_status_t sr); +void ald_pmu_clear_status(pmu_status_t sr); +/** + * @} + */ +/** @addtogroup PMU_Public_Functions_Group2 + * @{ + */ +/* LVD configure */ +void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state); +void ald_lvd_irq_handler(void); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_PMU_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h new file mode 100644 index 0000000000000000000000000000000000000000..b6a7060e4e0ee60c584355ce62d266ab40cce573 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h @@ -0,0 +1,285 @@ +/** + ********************************************************************************* + * + * @file ald_rmu.h + * @brief Header file of RMU module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_RMU_H__ +#define __ALD_RMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup RMU + * @{ + */ + +/** @defgroup RMU_Public_Types RMU Public Types + * @{ + */ +/** + * @brief RMU BOR fliter + */ +typedef enum +{ + RMU_BORFLT_1 = 0x1, /**< 1 cycle */ + RMU_BORFLT_2 = 0x2, /**< 2 cycles */ + RMU_BORFLT_3 = 0x3, /**< 3 cycles */ + RMU_BORFLT_4 = 0x4, /**< 4 cycles */ + RMU_BORFLT_5 = 0x5, /**< 5 cycles */ + RMU_BORFLT_6 = 0x6, /**< 6 cycles */ + RMU_BORFLT_7 = 0x7, /**< 7 cycles */ +} rmu_bor_filter_t; + +/** + * @brief RMU BOR voltage + */ +typedef enum +{ + RMU_VOL_1_7 = 0x0, /**< 1.7V */ + RMU_VOL_2_0 = 0x1, /**< 2.0V */ + RMU_VOL_2_1 = 0x2, /**< 2.1V */ + RMU_VOL_2_2 = 0x3, /**< 2.2V */ + RMU_VOL_2_3 = 0x4, /**< 2.3V */ + RMU_VOL_2_4 = 0x5, /**< 2.4V */ + RMU_VOL_2_5 = 0x6, /**< 2.5V */ + RMU_VOL_2_6 = 0x7, /**< 2.6V */ + RMU_VOL_2_8 = 0x8, /**< 2.8V */ + RMU_VOL_3_0 = 0x9, /**< 3.0V */ + RMU_VOL_3_1 = 0xA, /**< 3.1V */ + RMU_VOL_3_3 = 0xB, /**< 3.3V */ + RMU_VOL_3_6 = 0xC, /**< 3.6V */ + RMU_VOL_3_7 = 0xD, /**< 3.7V */ + RMU_VOL_4_0 = 0xE, /**< 4.0V */ + RMU_VOL_4_3 = 0xF, /**< 4.3V */ +} rmu_bor_vol_t; + +/** + * @brief RMU reset status + */ +typedef enum +{ + RMU_RST_POR = (1U << 0), /**< POR */ + RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */ + RMU_RST_BOR = (1U << 2), /**< BOR */ + RMU_RST_NMRST = (1U << 3), /**< NMRST */ + RMU_RST_IWDT = (1U << 4), /**< IWDT */ + RMU_RST_WWDT = (1U << 5), /**< WWDT */ + RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */ + RMU_RST_CHIP = (1U << 7), /**< CHIP */ + RMU_RST_MCU = (1U << 8), /**< MCU */ + RMU_RST_CPU = (1U << 9), /**< CPU */ + RMU_RST_CFG = (1U << 10), /**< CFG */ + RMU_RST_CFGERR = (1U << 16), /**< CFG Error */ +} rmu_state_t; + +/** + * @brief RMU periperal select bit + * @note ES32F065x: + * AD16C4T0--TIMER0 + * GP16C4T0--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + * + * ES32F033x: + * ES32F093x: + * GP16C4T0--TIMER0 + * GP16C4T1--TIMER6 + * GP16C2T0--TIMER2 + * GP16C2T1--TIMER3 + * BS16T0----TIMER1 + * BS16T1----TIMER4 + * BS16T2----TIMER5 + * BS16T3----TIMER7 + */ +typedef enum +{ + RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */ + RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */ + RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */ + RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */ + RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */ + RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */ + RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */ + RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */ + RMU_PERH_TIMER0 = (1U << 0) | (1U << 28), /**< APB1: TIMER0 */ + RMU_PERH_TIMER1 = (1U << 1) | (1U << 28), /**< APB1: TIMER1 */ + RMU_PERH_TIMER2 = (1U << 2) | (1U << 28), /**< APB1: TIMER2 */ + RMU_PERH_TIMER3 = (1U << 3) | (1U << 28), /**< APB1: TIMER3 */ + RMU_PERH_TIMER4 = (1U << 4) | (1U << 28), /**< APB1: TIMER4 */ + RMU_PERH_TIMER5 = (1U << 5) | (1U << 28), /**< APB1: TIMER5 */ + RMU_PERH_TIMER6 = (1U << 6) | (1U << 28), /**< APB1: TIMER6 */ + RMU_PERH_TIMER7 = (1U << 7) | (1U << 28), /**< APB1: TIMER7 */ + RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */ + RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */ + RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */ + RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */ + RMU_PERH_USART0 = (1U << 12) | (1U << 28), /**< APB1: EUART0 */ + RMU_PERH_USART1 = (1U << 13) | (1U << 28), /**< APB1: EUART1 */ + RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */ + RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */ + RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */ + RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */ + RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */ + RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */ + RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */ + RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */ + RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */ + RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */ + RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */ + RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */ + RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */ + RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */ + RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */ + RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */ + RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */ + RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */ + RMU_PERH_TSENSE = (1U << 16) | (1U << 29), /**< APB2: TSENSE */ + RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */ + RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */ +} rmu_peripheral_t; +/** + * @} + */ + +/** + * @defgroup RMU_Private_Macros RMU Private Macros + * @{ + */ +#define IS_RMU_BORFLT(x) (((x) == RMU_BORFLT_1) || \ + ((x) == RMU_BORFLT_2) || \ + ((x) == RMU_BORFLT_3) || \ + ((x) == RMU_BORFLT_4) || \ + ((x) == RMU_BORFLT_5) || \ + ((x) == RMU_BORFLT_6) || \ + ((x) == RMU_BORFLT_7)) +#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_7) || \ + ((x) == RMU_VOL_2_0) || \ + ((x) == RMU_VOL_2_1) || \ + ((x) == RMU_VOL_2_2) || \ + ((x) == RMU_VOL_2_3) || \ + ((x) == RMU_VOL_2_4) || \ + ((x) == RMU_VOL_2_5) || \ + ((x) == RMU_VOL_2_6) || \ + ((x) == RMU_VOL_2_8) || \ + ((x) == RMU_VOL_3_0) || \ + ((x) == RMU_VOL_3_1) || \ + ((x) == RMU_VOL_3_3) || \ + ((x) == RMU_VOL_3_6) || \ + ((x) == RMU_VOL_3_7) || \ + ((x) == RMU_VOL_4_0) || \ + ((x) == RMU_VOL_4_3)) +#define IS_RMU_STATE(x) (((x) == RMU_RST_POR) || \ + ((x) == RMU_RST_WAKEUP) || \ + ((x) == RMU_RST_BOR) || \ + ((x) == RMU_RST_NMRST) || \ + ((x) == RMU_RST_IWDT) || \ + ((x) == RMU_RST_WWDT) || \ + ((x) == RMU_RST_LOCKUP) || \ + ((x) == RMU_RST_CHIP) || \ + ((x) == RMU_RST_MCU) || \ + ((x) == RMU_RST_CPU) || \ + ((x) == RMU_RST_CFG) || \ + ((x) == RMU_RST_CFGERR)) +#define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \ + ((x) == RMU_RST_WAKEUP) || \ + ((x) == RMU_RST_BOR) || \ + ((x) == RMU_RST_NMRST) || \ + ((x) == RMU_RST_IWDT) || \ + ((x) == RMU_RST_WWDT) || \ + ((x) == RMU_RST_LOCKUP) || \ + ((x) == RMU_RST_CHIP) || \ + ((x) == RMU_RST_MCU) || \ + ((x) == RMU_RST_CPU) || \ + ((x) == RMU_RST_CFG)) +#define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \ + ((x) == RMU_PERH_CRC) || \ + ((x) == RMU_PERH_CALC) || \ + ((x) == RMU_PERH_CRYPT) || \ + ((x) == RMU_PERH_TRNG) || \ + ((x) == RMU_PERH_PIS) || \ + ((x) == RMU_PERH_CHIP) || \ + ((x) == RMU_PERH_CPU) || \ + ((x) == RMU_PERH_TIMER0) || \ + ((x) == RMU_PERH_TIMER1) || \ + ((x) == RMU_PERH_TIMER2) || \ + ((x) == RMU_PERH_TIMER3) || \ + ((x) == RMU_PERH_TIMER4) || \ + ((x) == RMU_PERH_TIMER5) || \ + ((x) == RMU_PERH_TIMER6) || \ + ((x) == RMU_PERH_TIMER7) || \ + ((x) == RMU_PERH_UART0) || \ + ((x) == RMU_PERH_UART1) || \ + ((x) == RMU_PERH_UART2) || \ + ((x) == RMU_PERH_UART3) || \ + ((x) == RMU_PERH_USART0) || \ + ((x) == RMU_PERH_USART1) || \ + ((x) == RMU_PERH_SPI0) || \ + ((x) == RMU_PERH_SPI1) || \ + ((x) == RMU_PERH_SPI2) || \ + ((x) == RMU_PERH_I2C0) || \ + ((x) == RMU_PERH_I2C1) || \ + ((x) == RMU_PERH_CAN0) || \ + ((x) == RMU_PERH_LPTIM0) || \ + ((x) == RMU_PERH_LPUART0) || \ + ((x) == RMU_PERH_ADC0) || \ + ((x) == RMU_PERH_ADC1) || \ + ((x) == RMU_PERH_ACMP0) || \ + ((x) == RMU_PERH_ACMP1) || \ + ((x) == RMU_PERH_OPAMP) || \ + ((x) == RMU_PERH_DAC0) || \ + ((x) == RMU_PERH_WWDT) || \ + ((x) == RMU_PERH_LCD) || \ + ((x) == RMU_PERH_IWDT) || \ + ((x) == RMU_PERH_RTC) || \ + ((x) == RMU_PERH_TSENSE) || \ + ((x) == RMU_PERH_BKPC) || \ + ((x) == RMU_PERH_BKPRAM)) +/** + * @} + */ + +/** @addtogroup RMU_Public_Functions + * @{ + */ +void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state); +flag_status_t ald_rmu_get_reset_status(rmu_state_t state); +void ald_rmu_clear_reset_status(rmu_state_t state); +void ald_rmu_reset_periperal(rmu_peripheral_t perh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_RMU_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..e14f542363707152db84d1ace5f3a59c874c31b5 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h @@ -0,0 +1,699 @@ +/** + ****************************************************************************** + * @file ald_rtc.h + * @brief Header file of RTC Module driver. + * + * @version V1.0 + * @date 16 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************* + */ + +#ifndef __ALD_RTC_H__ +#define __ALD_RTC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** @defgroup RTC_Public_Types RTC Public Types + * @{ + */ + +/** + * @brief Hours format + */ +typedef enum +{ + RTC_HOUR_FORMAT_24 = 0x0, /**< 24-hours format */ + RTC_HOUR_FORMAT_12 = 0x1, /**< 12-hours format */ +} rtc_hour_format_t; + +/** + * @brief Output mode + */ +typedef enum +{ + RTC_OUTPUT_DISABLE = 0x0, /**< Disable output */ + RTC_OUTPUT_ALARM_A = 0x1, /**< Output alarm_a signal */ + RTC_OUTPUT_ALARM_B = 0x2, /**< Output alarm_b signal */ + RTC_OUTPUT_WAKEUP = 0x3, /**< Output wakeup signal */ +} rtc_output_select_t; + +/** + * @brief Output polarity + */ +typedef enum +{ + RTC_OUTPUT_POLARITY_HIGH = 0x0, /**< Polarity is high */ + RTC_OUTPUT_POLARITY_LOW = 0x0, /**< Polarity is low */ +} rtc_output_polarity_t; + +/** + * @brief Initialization structure + */ +typedef struct +{ + rtc_hour_format_t hour_format; /**< Hours format */ + uint32_t asynch_pre_div; /**< Asynchronous predivider value */ + uint32_t synch_pre_div; /**< Synchronous predivider value */ + rtc_output_select_t output; /**< Output signal type */ + rtc_output_polarity_t output_polarity; /**< Output polarity */ +} rtc_init_t; + +/** + * @brief Source select + */ +typedef enum +{ + RTC_SOURCE_LOSC = 0x0, /**< LOSC */ + RTC_SOURCE_LRC = 0x1, /**< LRC */ + RTC_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */ + RTC_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */ +} rtc_source_sel_t; + +/** + * @brief Time structure + */ +typedef struct +{ + uint8_t hour; /**< Hours */ + uint8_t minute; /**< Minutes */ + uint8_t second; /**< Seconds */ + uint16_t sub_sec; /**< Sub-seconds */ +} rtc_time_t; + +/** + * @brief Date structure + */ +typedef struct +{ + uint8_t week; /**< Weeks */ + uint8_t day; /**< days */ + uint8_t month; /**< months */ + uint8_t year; /**< years */ +} rtc_date_t; + +/** + * @brief Data format + */ +typedef enum +{ + RTC_FORMAT_DEC = 0, + RTC_FORMAT_BCD = 1, +} rtc_format_t; + +/** + * @brief Index of alarm + */ +typedef enum +{ + RTC_ALARM_A = 0x0, /**< Alarm-A */ + RTC_ALARM_B = 0x1, /**< Alarm-B */ +} rtc_alarm_idx_t; + +/** + * @brief Alarm mask + */ +typedef enum +{ + RTC_ALARM_MASK_NONE = 0x0, /**< Mask is disable */ + RTC_ALARM_MASK_WEEK_DAY = (1U << 30), /**< Mask week or day */ + RTC_ALARM_MASK_HOUR = (1U << 23), /**< Mask hour */ + RTC_ALARM_MASK_MINUTE = (1U << 15), /**< Mask minute */ + RTC_ALARM_MASK_SECOND = (1U << 7), /**< Mask second */ + RTC_ALARM_MASK_ALL = 0x40808080, /**< Mask all */ +} rtc_alarm_mask_t; + +/** + * @brief Alarm sub-second mask + */ +typedef enum +{ + RTC_ALARM_SS_MASK_NONE = 0xF, /**< Mask is disable */ + RTC_ALARM_SS_MASK_14_1 = 0x1, /**< Mask bit(1-14) */ + RTC_ALARM_SS_MASK_14_2 = 0x2, /**< Mask bit(2-14) */ + RTC_ALARM_SS_MASK_14_3 = 0x3, /**< Mask bit(3-14) */ + RTC_ALARM_SS_MASK_14_4 = 0x4, /**< Mask bit(4-14) */ + RTC_ALARM_SS_MASK_14_5 = 0x5, /**< Mask bit(5-14) */ + RTC_ALARM_SS_MASK_14_6 = 0x6, /**< Mask bit(6-14) */ + RTC_ALARM_SS_MASK_14_7 = 0x7, /**< Mask bit(7-14) */ + RTC_ALARM_SS_MASK_14_8 = 0x8, /**< Mask bit(8-14) */ + RTC_ALARM_SS_MASK_14_9 = 0x9, /**< Mask bit(9-14) */ + RTC_ALARM_SS_MASK_14_10 = 0xA, /**< Mask bit(10-14) */ + RTC_ALARM_SS_MASK_14_11 = 0xB, /**< Mask bit(11-14) */ + RTC_ALARM_SS_MASK_14_12 = 0xC, /**< Mask bit(12-14) */ + RTC_ALARM_SS_MASK_14_13 = 0xD, /**< Mask bit(13-14) */ + RTC_ALARM_SS_MASK_14 = 0xE, /**< Mask bit14 */ + RTC_ALARM_SS_MASK_ALL = 0x0, /**< Mask bit(0-14) */ +} rtc_sub_second_mask_t; + +/** + * @brief Alarm select week or day */ +typedef enum +{ + RTC_SELECT_DAY = 0x0, /**< Alarm select day */ + RTC_SELECT_WEEK = 0x1, /**< Alarm select week */ +} rtc_week_day_sel_t; + +/** + * @brief Alarm structure + */ +typedef struct +{ + rtc_alarm_idx_t idx; /**< Index of alarm */ + rtc_time_t time; /**< Time structure */ + uint32_t mask; /**< Alarm mask */ + rtc_sub_second_mask_t ss_mask; /**< Alarm sub-second mask */ + rtc_week_day_sel_t sel; /**< Select week or day */ + + union + { + uint8_t week; /**< Alarm select week */ + uint8_t day; /**< Alarm select day */ + }; +} rtc_alarm_t; + +/** + * @brief Time stamp signel select + */ +typedef enum +{ + RTC_TS_SIGNAL_SEL_TAMPER0 = 0, /**< Select tamper0 */ + RTC_TS_SIGNAL_SEL_TAMPER1 = 1, /**< Select tamper1 */ +} rtc_ts_signal_sel_t; + +/** + * @brief Time stamp trigger style + */ +typedef enum +{ + RTC_TS_RISING_EDGE = 0, /**< Rising edge */ + RTC_TS_FALLING_EDGE = 1, /**< Falling edge */ +} rtc_ts_trigger_style_t; + +/** + * @brief Index of tamper + */ +typedef enum +{ + RTC_TAMPER_0 = 0, /**< Tamper0 */ + RTC_TAMPER_1 = 1, /**< Tamper1 */ +} rtc_tamper_idx_t; + +/** + * @brief Tamper trigger type + */ +typedef enum +{ + RTC_TAMPER_TRIGGER_LOW = 0, /**< High trigger */ + RTC_TAMPER_TRIGGER_HIGH = 1, /**< Low trigger */ +} rtc_tamper_trigger_t; + +/** + * @brief Tamper sampling frequency + */ +typedef enum +{ + RTC_TAMPER_SAMPLING_FREQ_32768 = 0, /**< RTCCLK / 32768 */ + RTC_TAMPER_SAMPLING_FREQ_16384 = 1, /**< RTCCLK / 16384 */ + RTC_TAMPER_SAMPLING_FREQ_8192 = 2, /**< RTCCLK / 8192 */ + RTC_TAMPER_SAMPLING_FREQ_4096 = 3, /**< RTCCLK / 4096 */ + RTC_TAMPER_SAMPLING_FREQ_2048 = 4, /**< RTCCLK / 2048 */ + RTC_TAMPER_SAMPLING_FREQ_1024 = 5, /**< RTCCLK / 1024 */ + RTC_TAMPER_SAMPLING_FREQ_512 = 6, /**< RTCCLK / 512 */ + RTC_TAMPER_SAMPLING_FREQ_256 = 7, /**< RTCCLK / 256 */ +} rtc_tamper_sampling_freq_t; + +/** + * @brief Tamper filter time + */ +typedef enum +{ + RTC_TAMPER_DURATION_1 = 0, /**< Duration 1 sampling */ + RTC_TAMPER_DURATION_2 = 1, /**< Duration 2 sampling */ + RTC_TAMPER_DURATION_4 = 2, /**< Duration 4 sampling */ + RTC_TAMPER_DURATION_8 = 3, /**< Duration 8 sampling */ +} rtc_tamper_duration_t; + +/** + * @brief Tamper structure + */ +typedef struct +{ + rtc_tamper_idx_t idx; /**< Index of tamper */ + rtc_tamper_trigger_t trig; /**< Trigger type */ + rtc_tamper_sampling_freq_t freq; /**< Sampling frequency */ + rtc_tamper_duration_t dur; /**< Filter time */ + type_func_t ts; /**< Enable/Disable trigger time stamp event */ +} rtc_tamper_t; + +/** + * @brief Wake-up clock + */ +typedef enum +{ + RTC_WAKEUP_CLOCK_DIV_16 = 0, /**< RTCCLK / 16 */ + RTC_WAKEUP_CLOCK_DIV_8 = 1, /**< RTCCLK / 8 */ + RTC_WAKEUP_CLOCK_DIV_4 = 2, /**< RTCCLK / 4 */ + RTC_WAKEUP_CLOCK_DIV_2 = 3, /**< RTCCLK / 2 */ + RTC_WAKEUP_CLOCK_1HZ = 4, /**< 1Hz */ + RTC_WAKEUP_CLOCK_1HZ_PULS = 6, /**< 1Hz and WUT + 65536 */ +} rtc_wakeup_clock_t; + +/** + * @brief RTC clock output type + */ +typedef enum +{ + RTC_CLOCK_OUTPUT_32768 = 0, /**< 32768Hz */ + RTC_CLOCK_OUTPUT_1024 = 1, /**< 1024Hz */ + RTC_CLOCK_OUTPUT_32 = 2, /**< 32Hz */ + RTC_CLOCK_OUTPUT_1 = 3, /**< 1Hz */ + RTC_CLOCK_OUTPUT_CAL_1 = 4, /**< 1Hz after calibration */ + RTC_CLOCK_OUTPUT_EXA_1 = 5, /**< Exact 1Hz */ +} rtc_clock_output_t; + +/** + * @ Calibration frequency + */ +typedef enum +{ + RTC_CALI_FREQ_10_SEC = 0, /**< Calibrate every 10 seconds */ + RTC_CALI_FREQ_20_SEC = 1, /**< Calibrate every 20 seconds */ + RTC_CALI_FREQ_1_MIN = 2, /**< Calibrate every 1 minute */ + RTC_CALI_FREQ_2_MIN = 3, /**< Calibrate every 2 minutes */ + RTC_CALI_FREQ_5_MIN = 4, /**< Calibrate every 5 minutes */ + RTC_CALI_FREQ_10_MIN = 5, /**< Calibrate every 10 minutes */ + RTC_CALI_FREQ_20_MIN = 6, /**< Calibrate every 20 minutes */ + RTC_CALI_FREQ_1_SEC = 7, /**< Calibrate every 1 second */ +} rtc_cali_freq_t; + +/** + * @brief Temperature compensate type + */ +typedef enum +{ + RTC_CALI_TC_NONE = 0, /**< Temperature compensate disable */ + RTC_CALI_TC_AUTO_BY_HW = 1, /**< Temperature compensate by hardware */ + RTC_CALI_TC_AUTO_BY_SF = 2, /**< Temperature compensate by software */ + RTC_CALI_TC_AUTO_BY_HW_SF = 3, /**< Temperature compensate by hardware, trigger by software */ +} rtc_cali_tc_t; + +/** + * @ Calculate frequency + */ +typedef enum +{ + RTC_CALI_CALC_FREQ_10_SEC = 0, /**< Calculate every 10 seconds */ + RTC_CALI_CALC_FREQ_20_SEC = 1, /**< Calculate every 20 seconds */ + RTC_CALI_CALC_FREQ_1_MIN = 2, /**< Calculate every 1 minute */ + RTC_CALI_CALC_FREQ_2_MIN = 3, /**< Calculate every 2 minutes */ + RTC_CALI_CALC_FREQ_5_MIN = 4, /**< Calculate every 5 minutes */ + RTC_CALI_CALC_FREQ_10_MIN = 5, /**< Calculate every 10 minutes */ + RTC_CALI_CALC_FREQ_20_MIN = 6, /**< Calculate every 20 minutes */ + RTC_CALI_CALC_FREQ_1_HOUR = 7, /**< Calculate every 1 hour */ +} rtc_cali_calc_freq_t; + +/** + * @brief Calibration algorithm + */ +typedef enum +{ + RTC_CALI_CALC_4 = 0, /**< 4-polynomial */ + RTC_CALI_CALC_2 = 1, /**< 2-parabola */ +} rtc_cali_calc_t; + +/** + * @brief Calibration structure + */ +typedef struct +{ + rtc_cali_freq_t cali_freq; /**< calibrate frequency */ + rtc_cali_tc_t tc; /**< Temperature compensate type */ + rtc_cali_calc_freq_t calc_freq; /**< Calculate frequency */ + rtc_cali_calc_t calc; /**< algorithm */ + type_func_t acc; /**< Enable/Disable decimal accumulate */ +} rtc_cali_t; + +/** + * @brief Interrupt type + */ +typedef enum +{ + RTC_IT_SEC = (1U << 0), /**< Second */ + RTC_IT_MIN = (1U << 1), /**< Minute */ + RTC_IT_HR = (1U << 2), /**< Hour */ + RTC_IT_DAY = (1U << 3), /**< Day */ + RTC_IT_MON = (1U << 4), /**< Month */ + RTC_IT_YR = (1U << 5), /**< Year */ + RTC_IT_ALMA = (1U << 8), /**< Alarm-A */ + RTC_IT_ALMB = (1U << 9), /**< Alarm-B */ + RTC_IT_TS = (1U << 10), /**< Time stamp */ + RTC_IT_TSOV = (1U << 11), /**< Time stamp overflow */ + RTC_IT_TP0 = (1U << 12), /**< Tamper-0 */ + RTC_IT_TP1 = (1U << 13), /**< Tamper-1 */ + RTC_IT_RSC = (1U << 16), /**< Synchronous complete */ + RTC_IT_SFC = (1U << 17), /**< Shift complete */ + RTC_IT_WU = (1U << 18), /**< Wake-up */ + RTC_IT_TCC = (1U << 24), /**< Temperature compensate complete */ + RTC_IT_TCE = (1U << 25), /**< Temperature compensate error */ +} rtc_it_t; + +/** + * @brief Interrupt flag + */ +typedef enum +{ + RTC_IF_SEC = (1U << 0), /**< Second */ + RTC_IF_MIN = (1U << 1), /**< Minute */ + RTC_IF_HR = (1U << 2), /**< Hour */ + RTC_IF_DAY = (1U << 3), /**< Day */ + RTC_IF_MON = (1U << 4), /**< Month */ + RTC_IF_YR = (1U << 5), /**< Year */ + RTC_IF_ALMA = (1U << 8), /**< Alarm-A */ + RTC_IF_ALMB = (1U << 9), /**< Alarm-B */ + RTC_IF_TS = (1U << 10), /**< Time stamp */ + RTC_IF_TSOV = (1U << 11), /**< Time stamp overflow */ + RTC_IF_TP0 = (1U << 12), /**< Tamper-0 */ + RTC_IF_TP1 = (1U << 13), /**< Tamper-1 */ + RTC_IF_RSC = (1U << 16), /**< Synchronous complete */ + RTC_IF_SFC = (1U << 17), /**< Shift complete */ + RTC_IF_WU = (1U << 18), /**< Wake-up */ + RTC_IF_TCC = (1U << 24), /**< Temperature compensate complete */ + RTC_IF_TCE = (1U << 25), /**< Temperature compensate error */ +} rtc_flag_t; +/** + * @} + */ + +/** @defgroup RTC_Public_Macro RTC Public Macros + * @{ + */ +#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55)) +#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0)) +#define RTC_BY_PASS_ENABLE() \ + do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ + RTC_LOCK(); \ + } while (0) +#define RTC_BY_PASS_DISABLE() \ + do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ + RTC_LOCK(); \ + } while (0) +#define RTC_SUMMER_TIME_ENABLE() \ + do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ + RTC_LOCK(); \ + } while (0) +#define RTC_SUMMER_TIME_DISABLE() \ + do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ + RTC_LOCK(); \ + } while (0) +#define RTC_WINTER_TIME_ENABLE() \ + do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ + RTC_LOCK(); \ + } while (0) +#define RTC_WINTER_TIME_DISABLE() \ + do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ + RTC_LOCK(); \ + } while (0) +/** + * @} + */ + +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ +#define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AA)) +#define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0)) +#define ALARM_MASK_ALL 0x40808080 +#define RTC_TIMEOUT_VALUE 100 + +#define IS_SHIFT_SUB_SS(x) ((x) < (1U << 15)) +#define IS_RTC_HOUR_FORMAT(x) (((x) == RTC_HOUR_FORMAT_24) || \ + ((x) == RTC_HOUR_FORMAT_12)) +#define IS_RTC_OUTPUT_SEL(x) (((x) == RTC_OUTPUT_DISABLE) || \ + ((x) == RTC_OUTPUT_ALARM_A) || \ + ((x) == RTC_OUTPUT_ALARM_B) || \ + ((x) == RTC_OUTPUT_WAKEUP)) +#define IS_RTC_OUTPUT_POLARITY(x) (((x) == RTC_OUTPUT_POLARITY_HIGH) || \ + ((x) == RTC_OUTPUT_POLARITY_LOW)) +#define IS_RTC_SOURCE_SEL(x) (((x) == RTC_SOURCE_LOSC) || \ + ((x) == RTC_SOURCE_LRC) || \ + ((x) == RTC_SOURCE_HRC_DIV_1M ) || \ + ((x) == RTC_SOURCE_HOSC_DIV_1M)) +#define IS_RTC_ALARM(x) (((x) == RTC_ALARM_A) || \ + ((x) == RTC_ALARM_B)) +#define IS_RTC_ALARM_SEL(x) (((x) == RTC_SELECT_DAY) || \ + ((x) == RTC_SELECT_WEEK)) +#define IS_RTC_ALARM_MASK(x) (((x) == RTC_ALARM_MASK_NONE) || \ + ((x) == RTC_ALARM_MASK_WEEK_DAY) || \ + ((x) == RTC_ALARM_MASK_HOUR) || \ + ((x) == RTC_ALARM_MASK_MINUTE) || \ + ((x) == RTC_ALARM_MASK_SECOND) || \ + ((x) == RTC_ALARM_MASK_ALL)) +#define IS_RTC_ALARM_SS_MASK(x) (((x) == RTC_ALARM_SS_MASK_NONE) || \ + ((x) == RTC_ALARM_SS_MASK_14_1) || \ + ((x) == RTC_ALARM_SS_MASK_14_2) || \ + ((x) == RTC_ALARM_SS_MASK_14_3) || \ + ((x) == RTC_ALARM_SS_MASK_14_4) || \ + ((x) == RTC_ALARM_SS_MASK_14_5) || \ + ((x) == RTC_ALARM_SS_MASK_14_6) || \ + ((x) == RTC_ALARM_SS_MASK_14_7) || \ + ((x) == RTC_ALARM_SS_MASK_14_8) || \ + ((x) == RTC_ALARM_SS_MASK_14_9) || \ + ((x) == RTC_ALARM_SS_MASK_14_10) || \ + ((x) == RTC_ALARM_SS_MASK_14_11) || \ + ((x) == RTC_ALARM_SS_MASK_14_12) || \ + ((x) == RTC_ALARM_SS_MASK_14_13) || \ + ((x) == RTC_ALARM_SS_MASK_14) || \ + ((x) == RTC_ALARM_SS_MASK_ALL)) +#define IS_RTC_TS_SIGNAL(x) (((x) == RTC_TS_SIGNAL_SEL_TAMPER0) || \ + ((x) == RTC_TS_SIGNAL_SEL_TAMPER1)) +#define IS_RTC_TS_STYLE(x) (((x) == RTC_TS_RISING_EDGE) || \ + ((x) == RTC_TS_FALLING_EDGE)) +#define IS_RTC_FORMAT(x) (((x) == RTC_FORMAT_DEC) || \ + ((x) == RTC_FORMAT_BCD)) +#define IS_RTC_TAMPER(x) (((x) == RTC_TAMPER_0) || \ + ((x) == RTC_TAMPER_1)) +#define IS_RTC_TAMPER_TRIGGER(x) (((x) == RTC_TAMPER_TRIGGER_LOW) || \ + ((x) == RTC_TAMPER_TRIGGER_HIGH)) +#define IS_RTC_TAMPER_SAMPLING_FREQ(x) (((x) == RTC_TAMPER_SAMPLING_FREQ_32768) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_8192) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_4096) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_2048) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_1024) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_512) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_256)) +#define IS_RTC_TAMPER_DURATION(x) (((x) == RTC_TAMPER_DURATION_1) || \ + ((x) == RTC_TAMPER_DURATION_2) || \ + ((x) == RTC_TAMPER_DURATION_4) || \ + ((x) == RTC_TAMPER_DURATION_8)) +#define IS_RTC_WAKEUP_CLOCK(x) (((x) == RTC_WAKEUP_CLOCK_DIV_16) || \ + ((x) == RTC_WAKEUP_CLOCK_DIV_8) || \ + ((x) == RTC_WAKEUP_CLOCK_DIV_4) || \ + ((x) == RTC_WAKEUP_CLOCK_DIV_2) || \ + ((x) == RTC_WAKEUP_CLOCK_1HZ) || \ + ((x) == RTC_WAKEUP_CLOCK_1HZ_PULS)) +#define IS_RTC_CLOCK_OUTPUT(x) (((x) == RTC_CLOCK_OUTPUT_32768) || \ + ((x) == RTC_CLOCK_OUTPUT_1024) || \ + ((x) == RTC_CLOCK_OUTPUT_32) || \ + ((x) == RTC_CLOCK_OUTPUT_1) || \ + ((x) == RTC_CLOCK_OUTPUT_CAL_1) || \ + ((x) == RTC_CLOCK_OUTPUT_EXA_1)) +#define IS_RTC_CALI_FREQ(x) (((x) == RTC_CALI_FREQ_10_SEC) || \ + ((x) == RTC_CALI_FREQ_20_SEC) || \ + ((x) == RTC_CALI_FREQ_1_MIN) || \ + ((x) == RTC_CALI_FREQ_2_MIN) || \ + ((x) == RTC_CALI_FREQ_5_MIN) || \ + ((x) == RTC_CALI_FREQ_10_MIN) || \ + ((x) == RTC_CALI_FREQ_20_MIN) || \ + ((x) == RTC_CALI_FREQ_1_SEC)) +#define IS_RTC_CALI_TC(x) (((x) == RTC_CALI_TC_NONE) || \ + ((x) == RTC_CALI_TC_AUTO_BY_HW) || \ + ((x) == RTC_CALI_TC_AUTO_BY_SF) || \ + ((x) == RTC_CALI_TC_AUTO_BY_HW_SF)) +#define IS_RTC_CALC_FREQ(x) (((x) == RTC_CALI_CALC_FREQ_10_SEC) || \ + ((x) == RTC_CALI_CALC_FREQ_20_SEC) || \ + ((x) == RTC_CALI_CALC_FREQ_1_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_2_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_5_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_10_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_20_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_1_HOUR)) +#define IS_RTC_CALI_CALC(x) (((x) == RTC_CALI_CALC_4) || \ + ((x) == RTC_CALI_CALC_2)) +#define IS_RTC_IT(x) (((x) == RTC_IT_SEC) || \ + ((x) == RTC_IT_MIN) || \ + ((x) == RTC_IT_HR) || \ + ((x) == RTC_IT_DAY) || \ + ((x) == RTC_IT_MON) || \ + ((x) == RTC_IT_YR) || \ + ((x) == RTC_IT_ALMA) || \ + ((x) == RTC_IT_ALMB) || \ + ((x) == RTC_IT_TS) || \ + ((x) == RTC_IT_TSOV) || \ + ((x) == RTC_IT_TP0) || \ + ((x) == RTC_IT_TP1) || \ + ((x) == RTC_IT_RSC) || \ + ((x) == RTC_IT_SFC) || \ + ((x) == RTC_IT_WU) || \ + ((x) == RTC_IT_TCC) || \ + ((x) == RTC_IT_TCE)) +#define IS_RTC_IF(x) (((x) == RTC_IF_SEC) || \ + ((x) == RTC_IF_MIN) || \ + ((x) == RTC_IF_HR) || \ + ((x) == RTC_IF_DAY) || \ + ((x) == RTC_IF_MON) || \ + ((x) == RTC_IF_YR) || \ + ((x) == RTC_IF_ALMA) || \ + ((x) == RTC_IF_ALMB) || \ + ((x) == RTC_IF_TS) || \ + ((x) == RTC_IF_TSOV) || \ + ((x) == RTC_IF_TP0) || \ + ((x) == RTC_IF_TP1) || \ + ((x) == RTC_IF_RSC) || \ + ((x) == RTC_IF_SFC) || \ + ((x) == RTC_IF_WU) || \ + ((x) == RTC_IF_TCC) || \ + ((x) == RTC_IF_TCE)) +#define IS_RTC_SECOND(x) ((x) < 60) +#define IS_RTC_MINUTE(x) ((x) < 60) +#define IS_RTC_HOUR(x) ((x) < 24) +#define IS_RTC_DAY(x) (((x) > 0) && ((x) < 32)) +#define IS_RTC_MONTH(x) (((x) > 0) && ((x) < 13)) +#define IS_RTC_YEAR(x) ((x) < 100) +/** + * @} + */ + +/** @addtogroup RTC_Public_Functions + * @{ + */ + +/** @addtogroup RTC_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void ald_rtc_reset(void); +void ald_rtc_init(rtc_init_t *init); +void ald_rtc_source_select(rtc_source_sel_t sel); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group2 + * @{ + */ +/* Time and date operation functions */ +ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format); +ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format); +void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format); +void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format); +int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group3 + * @{ + */ +/* Alarm functions */ +void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format); +void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group4 + * @{ + */ +/* Time stamp functions */ +void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style); +void ald_rtc_cancel_time_stamp(void); +void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group5 + * @{ + */ +/* Tamper functions */ +void ald_rtc_set_tamper(rtc_tamper_t *tamper); +void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group6 + * @{ + */ +/* Wakeup functions */ +void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value); +void ald_rtc_cancel_wakeup(void); +uint16_t ald_rtc_get_wakeup_timer_value(void); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group7 + * @{ + */ +/* Clock output functions */ +ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock); +void ald_rtc_cancel_clock_output(void); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group8 + * @{ + */ +/* Control functions */ +void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state); +void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state); +ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss); +void ald_rtc_set_cali(rtc_cali_t *config); +void ald_rtc_cancel_cali(void); +ald_status_t ald_rtc_get_cali_status(void); +void ald_rtc_write_temp(uint16_t temp); +it_status_t ald_rtc_get_it_status(rtc_it_t it); +flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag); +void ald_rtc_clear_flag_status(rtc_flag_t flag); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h similarity index 34% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h index 1d5564bd765842869e83e06f420f0da4b38deef1..b04380ee6d0973f1fc31238a247a07616adce0c3 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h @@ -43,12 +43,12 @@ extern "C" { */ typedef enum { - SMARTCARD_ERROR_NONE = ((uint32_t)0x00), /**< No error */ - SMARTCARD_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ - SMARTCARD_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ - SMARTCARD_ERROR_FE = ((uint32_t)0x04), /**< frame error */ - SMARTCARD_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ - SMARTCARD_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ + SMARTCARD_ERROR_NONE = ((uint32_t)0x00), /**< No error */ + SMARTCARD_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ + SMARTCARD_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ + SMARTCARD_ERROR_FE = ((uint32_t)0x04), /**< frame error */ + SMARTCARD_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ + SMARTCARD_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ } smartcard_error_t; /** @@ -56,37 +56,37 @@ typedef enum */ typedef enum { - SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1), /**< SYSCLK divided by 2 */ - SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2), /**< SYSCLK divided by 4 */ - SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3), /**< SYSCLK divided by 6 */ - SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4), /**< SYSCLK divided by 8 */ - SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5), /**< SYSCLK divided by 10 */ - SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6), /**< SYSCLK divided by 12 */ - SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7), /**< SYSCLK divided by 14 */ - SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8), /**< SYSCLK divided by 16 */ - SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9), /**< SYSCLK divided by 18 */ - SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xA), /**< SYSCLK divided by 20 */ - SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xB), /**< SYSCLK divided by 22 */ - SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xC), /**< SYSCLK divided by 24 */ - SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xD), /**< SYSCLK divided by 26 */ - SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xE), /**< SYSCLK divided by 28 */ - SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xF), /**< SYSCLK divided by 30 */ - SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10), /**< SYSCLK divided by 32 */ - SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11), /**< SYSCLK divided by 34 */ - SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12), /**< SYSCLK divided by 36 */ - SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13), /**< SYSCLK divided by 38 */ - SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14), /**< SYSCLK divided by 40 */ - SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15), /**< SYSCLK divided by 42 */ - SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16), /**< SYSCLK divided by 44 */ - SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17), /**< SYSCLK divided by 46 */ - SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18), /**< SYSCLK divided by 48 */ - SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19), /**< SYSCLK divided by 50 */ - SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1A), /**< SYSCLK divided by 52 */ - SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1B), /**< SYSCLK divided by 54 */ - SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1C), /**< SYSCLK divided by 56 */ - SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1D), /**< SYSCLK divided by 58 */ - SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1E), /**< SYSCLK divided by 60 */ - SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1F), /**< SYSCLK divided by 62 */ + SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1), /**< SYSCLK divided by 2 */ + SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2), /**< SYSCLK divided by 4 */ + SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3), /**< SYSCLK divided by 6 */ + SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4), /**< SYSCLK divided by 8 */ + SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5), /**< SYSCLK divided by 10 */ + SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6), /**< SYSCLK divided by 12 */ + SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7), /**< SYSCLK divided by 14 */ + SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8), /**< SYSCLK divided by 16 */ + SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9), /**< SYSCLK divided by 18 */ + SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xA), /**< SYSCLK divided by 20 */ + SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xB), /**< SYSCLK divided by 22 */ + SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xC), /**< SYSCLK divided by 24 */ + SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xD), /**< SYSCLK divided by 26 */ + SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xE), /**< SYSCLK divided by 28 */ + SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xF), /**< SYSCLK divided by 30 */ + SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10), /**< SYSCLK divided by 32 */ + SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11), /**< SYSCLK divided by 34 */ + SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12), /**< SYSCLK divided by 36 */ + SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13), /**< SYSCLK divided by 38 */ + SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14), /**< SYSCLK divided by 40 */ + SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15), /**< SYSCLK divided by 42 */ + SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16), /**< SYSCLK divided by 44 */ + SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17), /**< SYSCLK divided by 46 */ + SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18), /**< SYSCLK divided by 48 */ + SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19), /**< SYSCLK divided by 50 */ + SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1A), /**< SYSCLK divided by 52 */ + SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1B), /**< SYSCLK divided by 54 */ + SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1C), /**< SYSCLK divided by 56 */ + SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1D), /**< SYSCLK divided by 58 */ + SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1E), /**< SYSCLK divided by 60 */ + SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1F), /**< SYSCLK divided by 62 */ } smartcard_prescaler_t; /** @@ -102,25 +102,25 @@ typedef enum */ typedef struct { - uint32_t baud; /**< This member configures the SmartCard communication baud rate. */ + uint32_t baud; /**< This member configures the SmartCard communication baud rate. */ usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ - usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ - usart_parity_t parity; /**< Specifies the parity mode. - @note When parity is enabled, the computed parity is inserted + usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ + usart_parity_t parity; /**< Specifies the parity mode. + @note When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).*/ - usart_mode_t mode; /**< Specifies whether the Receive or Transmit mode is enabled or disabled. */ - usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ - usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made.*/ - usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. + usart_mode_t mode; /**< Specifies whether the Receive or Transmit mode is enabled or disabled. */ + usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ + usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made.*/ + usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref usart_last_bit_t */ smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock - to provide the smartcard clock. The value given in the register (5 significant bits) - is multiplied by 2 to give the division factor of the source clock frequency. */ - uint32_t guard_time; /**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */ - type_func_t nack; /**< Specifies the SmartCard NACK Transmission state. */ + to provide the smartcard clock. The value given in the register (5 significant bits) + is multiplied by 2 to give the division factor of the source clock frequency. */ + uint32_t guard_time; /**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */ + type_func_t nack; /**< Specifies the SmartCard NACK Transmission state. */ } smartcard_init_t; /** @@ -128,14 +128,14 @@ typedef struct */ typedef enum { - SMARTCARD_STATE_RESET = 0x00, /**< Peripheral is not yet Initialized */ - SMARTCARD_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - SMARTCARD_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - SMARTCARD_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ - SMARTCARD_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ - SMARTCARD_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission and Reception process is ongoing */ - SMARTCARD_STATE_TIMEOUT = 0x03, /**< Timeout state */ - SMARTCARD_STATE_ERROR = 0x04 /**< Error */ + SMARTCARD_STATE_RESET = 0x00, /**< Peripheral is not yet Initialized */ + SMARTCARD_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + SMARTCARD_STATE_BUSY = 0x02, /**< an internal process is ongoing */ + SMARTCARD_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ + SMARTCARD_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ + SMARTCARD_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission and Reception process is ongoing */ + SMARTCARD_STATE_TIMEOUT = 0x03, /**< Timeout state */ + SMARTCARD_STATE_ERROR = 0x04 /**< Error */ } smartcard_state_t; @@ -144,25 +144,25 @@ typedef enum */ typedef struct smartcard_handle_s { - USART_TypeDef *perh; /**< USART registers base address */ - smartcard_init_t init; /**< SmartCard communication parameters */ - uint8_t *tx_buf; /**< Pointer to SmartCard Tx transfer Buffer */ - uint16_t tx_size; /**< SmartCard Tx Transfer size */ - uint16_t tx_count; /**< SmartCard Tx Transfer Counter */ - uint8_t *rx_buf; /**< Pointer to SmartCard Rx transfer Buffer */ - uint16_t rx_size; /**< SmartCard Rx Transfer size */ - uint16_t rx_count; /**< SmartCard Rx Transfer Counter */ + USART_TypeDef *perh; /**< USART registers base address */ + smartcard_init_t init; /**< SmartCard communication parameters */ + uint8_t *tx_buf; /**< Pointer to SmartCard Tx transfer Buffer */ + uint16_t tx_size; /**< SmartCard Tx Transfer size */ + uint16_t tx_count; /**< SmartCard Tx Transfer Counter */ + uint8_t *rx_buf; /**< Pointer to SmartCard Rx transfer Buffer */ + uint16_t rx_size; /**< SmartCard Rx Transfer size */ + uint16_t rx_count; /**< SmartCard Rx Transfer Counter */ #ifdef ALD_DMA - dma_handle_t hdmatx; /**< SmartCard Tx DMA Handle parameters */ - dma_handle_t hdmarx; /**< SmartCard Rx DMA Handle parameters */ + dma_handle_t hdmatx; /**< SmartCard Tx DMA Handle parameters */ + dma_handle_t hdmarx; /**< SmartCard Rx DMA Handle parameters */ #endif - lock_state_t lock; /**< Locking object */ - smartcard_state_t state; /**< SmartCard communication state */ - uint32_t err_code; /**< SmartCard Error code */ + lock_state_t lock; /**< Locking object */ + smartcard_state_t state; /**< SmartCard communication state */ + uint32_t err_code; /**< SmartCard Error code */ - void (*tx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Rx completed callback */ - void (*error_cbk)(struct smartcard_handle_s *arg); /**< error callback */ + void (*tx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct smartcard_handle_s *arg); /**< error callback */ } smartcard_handle_t; /** @@ -192,7 +192,7 @@ typedef struct smartcard_handle_s /** @defgroup SMARTCARD_Public_Macros_3 SMARTCARD enable * @{ */ -#define SMARTCARD_ENABLE(handle) (SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) +#define SMARTCARD_ENABLE(handle) (SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) /** * @} */ @@ -200,7 +200,7 @@ typedef struct smartcard_handle_s /** @defgroup SMARTCARD_Public_Macros_4 SMARTCARD disable * @{ */ -#define SMARTCARD_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) +#define SMARTCARD_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) /** * @} */ @@ -214,7 +214,7 @@ typedef struct smartcard_handle_s */ #define IS_SMARTCARD_PRESCALER(x) (((x) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \ - ((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62)) + ((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62)) /** * @} */ @@ -227,8 +227,8 @@ typedef struct smartcard_handle_s * @{ */ /* Initialization functions */ -ald_status_t smartcard_init(smartcard_handle_t *hperh); -ald_status_t smartcard_reset(smartcard_handle_t *hperh); +ald_status_t ald_smartcard_init(smartcard_handle_t *hperh); +ald_status_t ald_smartcard_reset(smartcard_handle_t *hperh); /** * @} */ @@ -237,15 +237,15 @@ ald_status_t smartcard_reset(smartcard_handle_t *hperh); * @{ */ /* IO operation functions */ -ald_status_t smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size); #ifdef ALD_DMA -ald_status_t smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); #endif -void smartcard_irq_handle(smartcard_handle_t *hperh); +void ald_smartcard_irq_handler(smartcard_handle_t *hperh); /** * @} */ @@ -254,8 +254,8 @@ void smartcard_irq_handle(smartcard_handle_t *hperh); * @{ */ /* Peripheral State and Errors functions functions */ -smartcard_state_t smartcard_get_state(smartcard_handle_t *hperh); -uint32_t smartcard_get_error(smartcard_handle_t *hperh); +smartcard_state_t ald_smartcard_get_state(smartcard_handle_t *hperh); +uint32_t ald_smartcard_get_error(smartcard_handle_t *hperh); /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..d92aefb219bd36f88c6b54c2f17eb07cdb7d180a --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h @@ -0,0 +1,398 @@ +/** + ********************************************************************************* + * + * @file ald_spi.c + * @brief Header file of SPI module driver. + * + * @version V1.0 + * @date 13 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_SPI_H__ +#define __ALD_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Public_Types SPI Public Types + * @{ + */ + +/** + * @brief clock phase + */ +typedef enum +{ + SPI_CPHA_FIRST = 0, /**< Transiting data in the first edge */ + SPI_CPHA_SECOND = 1, /**< Transiting data in the seconde edge */ +} spi_cpha_t; + +/** + * @brief clock polarity + */ +typedef enum +{ + SPI_CPOL_LOW = 0, /**< Polarity hold low when spi-bus is idle */ + SPI_CPOL_HIGH = 1, /**< Polarity hold high when spi-bus is idle */ +} spi_cpol_t; + +/** + * @brief master selection + */ +typedef enum +{ + SPI_MODE_SLAVER = 0, /**< Slave mode */ + SPI_MODE_MASTER = 1, /**< Master mode */ +} spi_mode_t; + +/** + * @brief baud rate control + */ +typedef enum +{ + SPI_BAUD_2 = 0, /**< fpclk/2 */ + SPI_BAUD_4 = 1, /**< fpclk/4 */ + SPI_BAUD_8 = 2, /**< fpclk/8 */ + SPI_BAUD_16 = 3, /**< fpclk/16 */ + SPI_BAUD_32 = 4, /**< fpclk/32 */ + SPI_BAUD_64 = 5, /**< fpclk/64 */ + SPI_BAUD_128 = 6, /**< fpclk/128 */ + SPI_BAUD_256 = 7, /**< fpclk/256 */ +} spi_baud_t; + +/** + * @brief frame format + */ +typedef enum +{ + SPI_FIRSTBIT_MSB = 0, /**< MSB transmitted first */ + SPI_FIRSTBIT_LSB = 1, /**< LSB transmitted first */ +} spi_firstbit_t; + +/** + * @brief data frame format + */ +typedef enum +{ + SPI_DATA_SIZE_8 = 0, /**< 8-bit data frame format is selected for transmission/reception */ + SPI_DATA_SIZE_16 = 1, /**< 16-bit data frame format is selected for transmission/reception */ +} spi_datasize_t; + +/** + * @brief interrupt control + */ +typedef enum +{ + SPI_IT_ERR = (1U << 5), /**< error interrupt */ + SPI_IT_RXBNE = (1U << 6), /**< rx buffer not empty interrupt */ + SPI_IT_TXBE = (1U << 7), /**< tx buffer empty interrupt */ +} spi_it_t; + +/** + * @brief interrupt flag + */ +typedef enum +{ + SPI_IF_RXBNE = (1U << 0), /**< receive buffer not empty */ + SPI_IF_TXBE = (1U << 1), /**< transmit buffer empty */ + SPI_IF_CRCERR = (1U << 4), /**< crc error flag */ + SPI_IF_MODF = (1U << 5), /**< mode fault */ + SPI_IF_OVE = (1U << 6), /**< overrun flag */ + SPI_IF_BUSY = (1U << 7), /**< busy flag */ +} spi_flag_t; + +/** + * @brief SPI error status + */ +typedef enum +{ + SPI_ERROR_NONE = 0, /**< none */ + SPI_ERROR_MODF = 1, /**< mode fault */ + SPI_ERROR_CRC = 2, /**< crc error */ + SPI_ERROR_OVE = 4, /**< overrun error */ + SPI_ERROR_DMA = 8, /**< dma error */ + SPI_ERROR_FLAG = 0x10, /**< interrupt flag error */ +} spi_error_t; + + + +/** + * @brief SPI state structures definition + */ +typedef enum +{ + SPI_STATE_RESET = 0x00, /**< Peripheral is not initialized */ + SPI_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + SPI_STATE_BUSY = 0x02, /**< an internal process is ongoing */ + SPI_STATE_BUSY_TX = 0x11, /**< transmit is ongoing */ + SPI_STATE_BUSY_RX = 0x21, /**< receive is ongoing */ + SPI_STATE_BUSY_TX_RX = 0x31, /**< transmit and receive are ongoing */ + SPI_STATE_TIMEOUT = 0x03, /**< Timeout state */ + SPI_STATE_ERROR = 0x04, /**< Error */ +} spi_state_t; + +/** + * @brief SPI status definition + */ +typedef enum +{ + SPI_STATUS_RXBNE = (1U << 0), /**< Receive not empty status */ + SPI_STATUS_TXBE = (1U << 1), /**< Transmit empty status */ + SPI_STATUS_CRCERR = (1U << 4), /**< CRC error status */ + SPI_STATUS_MODEERR = (1U << 5), /**< Mode error status */ + SPI_STATUS_OVERR = (1U << 6), /**< Overflow status */ + SPI_STATUS_BUSY = (1U << 7), /**< Busy status */ + +} spi_status_t; + +/** + * @brief SPI direction definition + */ +typedef enum +{ + SPI_DIRECTION_2LINES = 0, /**< 2 lines */ + SPI_DIRECTION_2LINES_RXONLY = 1, /**< 2 lines only rx */ + SPI_DIRECTION_1LINE = 2, /**< 1 line */ + SPI_DIRECTION_1LINE_RX = 3, /**< 1 line only rx */ +} spi_direction_t; + +/** + * @brief SPI dma request definition + */ +typedef enum +{ + SPI_DMA_REQ_TX = 0, /**< TX dma request */ + SPI_DMA_REQ_RX = 1, /**< RX dma request */ +} spi_dma_req_t; + +/** + * @brief SPI TXE/RXNE status definition + */ +typedef enum +{ + SPI_SR_TXBE = 0, /**< SR.TXE set */ + SPI_SR_RXBNE = 1, /**< SR.RXNE set */ + SPI_SR_TXBE_RXBNE = 2, /**< SR.TXE and SR.RXNE set */ +} spi_sr_status_t; + +/** + * @brief SPI init structure definition + */ +typedef struct +{ + spi_mode_t mode; /**< SPI mode */ + spi_direction_t dir; /**< SPI direction */ + spi_datasize_t data_size; /**< SPI data size */ + spi_baud_t baud; /**< SPI baudrate prescaler */ + spi_cpha_t phase; /**< SPI clock phase */ + spi_cpol_t polarity; /**< SPI clock polarity */ + spi_firstbit_t first_bit; /**< SPI first bit */ + type_func_t ss_en; /**< SPI ssm enable or disable */ + type_func_t crc_calc; /**< SPI crc calculation */ + uint16_t crc_poly; /**< SPI crc polynomial */ +} spi_init_t; + +/** + * @brief SPI handle structure definition + */ +typedef struct spi_handle_s +{ + SPI_TypeDef *perh; /**< SPI registers base address */ + spi_init_t init; /**< SPI communication parameters */ + uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */ + uint16_t tx_size; /**< SPI Tx transfer size */ + uint16_t tx_count; /**< SPI Tx transfer counter */ + uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */ + uint16_t rx_size; /**< SPI Rx Transfer size */ + uint16_t rx_count; /**< SPI Rx Transfer Counter */ +#ifdef ALD_DMA + dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */ +#endif + lock_state_t lock; /**< Locking object */ + spi_state_t state; /**< SPI communication state */ + uint32_t err_code; /**< SPI error code */ + + void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */ + void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */ + void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */ +} spi_handle_t; +/** + * @} + */ + +/** @defgroup SPI_Public_Macros SPI Public Macros + * @{ + */ +#define SPI_RESET_HANDLE_STATE(x) ((x)->state = SPI_STATE_RESET) +#define SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS)) +#define SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS)) +#define SPI_CRC_RESET(x) \ + do { \ + CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ + SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ + } while (0) +#define SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) +#define SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) +#define SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) +#define SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) +#define SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) +#define SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) +#define SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) +#define SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) +#define SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) +#define SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) +/** + * @} + */ + +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ +#define IS_SPI(x) (((x) == SPI0) || \ + ((x) == SPI1) || \ + ((x) == SPI2)) +#define IS_SPI_CPHA(x) (((x) == SPI_CPHA_FIRST) || \ + ((x) == SPI_CPHA_SECOND)) +#define IS_SPI_CPOL(x) (((x) == SPI_CPOL_LOW) || \ + ((x) == SPI_CPOL_HIGH)) +#define IS_SPI_MODE(x) (((x) == SPI_MODE_SLAVER) || \ + ((x) == SPI_MODE_MASTER)) +#define IS_SPI_BAUD(x) (((x) == SPI_BAUD_2) || \ + ((x) == SPI_BAUD_4) || \ + ((x) == SPI_BAUD_8) || \ + ((x) == SPI_BAUD_16) || \ + ((x) == SPI_BAUD_32) || \ + ((x) == SPI_BAUD_64) || \ + ((x) == SPI_BAUD_128) || \ + ((x) == SPI_BAUD_256)) +#define IS_SPI_DATASIZE(x) (((x) == SPI_DATA_SIZE_8) || \ + ((x) == SPI_DATA_SIZE_16)) +#define IS_SPI_BIDOE(x) (((x) == SPI_BID_RX) || \ + ((x) == SPI_BID_TX)) +#define IS_SPI_BIDMODE(x) (((x) == SPI_BIDMODE_DUAL) || \ + ((x) == SPI_BIDMODE_SOLE)) +#define IS_SPI_DIRECTION(x) (((x) == SPI_DIRECTION_2LINES) || \ + ((x) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((x) == SPI_DIRECTION_1LINE) || \ + ((x) == SPI_DIRECTION_1LINE_RX)) +#define IS_SPI_DMA_REQ(x) (((x) == SPI_DMA_REQ_TX) || \ + ((x) == SPI_DMA_REQ_RX)) +#define IS_SPI_SR_STATUS(x) (((x) == SPI_SR_TXBE) || \ + ((x) == SPI_SR_RXBNE) || \ + ((x) == SPI_SR_TXBE_RXBNE)) +#define IS_SPI_IT(x) (((x) == SPI_IT_ERR) || \ + ((x) == SPI_IT_RXBNE) || \ + ((x) == SPI_IT_TXBE)) +#define IS_SPI_IF(x) (((x) == SPI_IF_RXBNE) || \ + ((x) == SPI_IF_TXBE) || \ + ((x) == SPI_IF_CRCERR) || \ + ((x) == SPI_IF_MODF) || \ + ((x) == SPI_IF_OVE) || \ + ((x) == SPI_IF_BUSY)) +#define IS_SPI_STATUS(x) (((x) == SPI_STATUS_RXBNE) || \ + ((x) == SPI_STATUS_TXBE) || \ + ((x) == SPI_STATUS_CRCERR) || \ + ((x) == SPI_STATUS_MODEERR) || \ + ((x) == SPI_STATUS_OVERR) || \ + ((x) == SPI_STATUS_BUSY)) +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions + * @{ + */ + +/** @addtogroup SPI_Public_Functions_Group1 + * @{ + */ + +ald_status_t ald_spi_init(spi_handle_t *hperh); +void ald_spi_reset(spi_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions_Group2 + * @{ + */ +int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data); +int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data); +uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh); +ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size); +#ifdef ALD_DMA +ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); +ald_status_t ald_spi_dma_pause(spi_handle_t *hperh); +ald_status_t ald_spi_dma_resume(spi_handle_t *hperh); +ald_status_t ald_spi_dma_stop(spi_handle_t *hperh); +#endif +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions_Group3 + * @{ + */ +void ald_spi_irq_handler(spi_handle_t *hperh); +void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state); +void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed); +void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state); +it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it); +flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status); +flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag); +void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag); +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions_Group4 + * @{ + */ +spi_state_t ald_spi_get_state(spi_handle_t *hperh); +uint32_t ald_spi_get_error(spi_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h similarity index 50% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h index 22ef750f702191fe78d6be39165fc42d910d0d32..d173be011f324fc1bfbb603fbef600f7f14bdebe 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h @@ -36,33 +36,33 @@ extern "C" { /** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros * @{ */ -#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0) -#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996) -#define GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK) - -#define BOOT_FROM_BOOT_ROM() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) - -#define BOOT_FROM_BOOT_FLASH() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) - -#define BOOT_FROM_FLASH() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ - SYSCFG_LOCK(); \ -} while (0) +#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0) +#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996) +#define GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK) + +#define BOOT_FROM_BOOT_ROM() \ + do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) + +#define BOOT_FROM_BOOT_FLASH() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) + +#define BOOT_FROM_FLASH() \ + do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ + } while (0) /** * @} */ @@ -71,7 +71,7 @@ do { \ /** @defgroup SYSCFG_Public_Functions SYSCFG Public Functions * @{ */ -__STATIC_INLINE__ void vtor_config(uint32_t offset, type_func_t status) +__STATIC_INLINE__ void ald_vtor_config(uint32_t offset, type_func_t status) { SYSCFG_UNLOCK(); diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..9fe5ee6d6445ab35e2f8e49becf616b63f24c3c9 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h @@ -0,0 +1,1193 @@ +/** + ********************************************************************************* + * + * @file ald_timer.h + * @brief TIMER module driver. + * This is the common part of the TIMER initialization + * + * @version V1.0 + * @date 06 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_TIMER_H__ +#define __ALD_TIMER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +/** @defgroup TIMER_Public_Types TIMER Public Types + * @{ + */ + +/** + * @brief TIMER counter mode + */ +typedef enum +{ + TIMER_CNT_MODE_UP = 0, /**< Counter mode up */ + TIMER_CNT_MODE_DOWN = 1, /**< Counter mode down */ + TIMER_CNT_MODE_CENTER1 = 2, /**< Counter mode center1 */ + TIMER_CNT_MODE_CENTER2 = 3, /**< Counter mode center2 */ + TIMER_CNT_MODE_CENTER3 = 4, /**< Counter mode center3 */ +} timer_cnt_mode_t; + +/** + * @brief TIMER clock division + */ +typedef enum +{ + TIMER_CLOCK_DIV1 = 0, /**< No prescaler is used */ + TIMER_CLOCK_DIV2 = 1, /** Clock is divided by 2 */ + TIMER_CLOCK_DIV4 = 2, /** Clock is divided by 4 */ +} timer_clock_division_t; + +/** + * @brief TIMER output compare and PWM modes + */ +typedef enum +{ + TIMER_OC_MODE_TIMERING = 0, /**< Output compare mode is timering */ + TIMER_OC_MODE_ACTIVE = 1, /**< Output compare mode is active */ + TIMER_OC_MODE_INACTIVE = 2, /**< Output compare mode is inactive */ + TIMER_OC_MODE_TOGGLE = 3, /**< Output compare mode is toggle */ + TIMER_OC_MODE_FORCE_INACTIVE = 4, /**< Output compare mode is force inactive */ + TIMER_OC_MODE_FORCE_ACTIVE = 5, /**< Output compare mode is force active */ + TIMER_OC_MODE_PWM1 = 6, /**< Output compare mode is pwm1 */ + TIMER_OC_MODE_PWM2 = 7, /**< Output compare mode is pwm2 */ +} timer_oc_mode_t; + +/** + * @brief TIMER output compare polarity + */ +typedef enum +{ + TIMER_OC_POLARITY_HIGH = 0, /**< Output compare polarity is high */ + TIMER_OC_POLARITY_LOW = 1, /**< Output compare polarity is low */ +} timer_oc_polarity_t; + +/** + * @brief TIMER complementary output compare polarity + */ +typedef enum +{ + TIMER_OCN_POLARITY_HIGH = 0, /**< Complementary output compare polarity is high */ + TIMER_OCN_POLARITY_LOW = 1, /**< Complementary output compare polarity is low */ +} timer_ocn_polarity_t; + +/** + * @brief TIMER output compare idle state + */ +typedef enum +{ + TIMER_OC_IDLE_RESET = 0, /**< Output compare idle state is reset */ + TIMER_OC_IDLE_SET = 1, /**< Output compare idle state is set */ +} timer_oc_idle_t; + +/** + * @brief TIMER complementary output compare idle state + */ +typedef enum +{ + TIMER_OCN_IDLE_RESET = 0, /**< Complementary output compare idle state is reset */ + TIMER_OCN_IDLE_SET = 1, /**< Complementary output compare idle state is set */ +} timer_ocn_idle_t; + +/** + * @brief TIMER channel + */ +typedef enum +{ + TIMER_CHANNEL_1 = 0, /**< Channel 1 */ + TIMER_CHANNEL_2 = 1, /**< Channel 2 */ + TIMER_CHANNEL_3 = 2, /**< Channel 3 */ + TIMER_CHANNEL_4 = 4, /**< Channel 4 */ + TIMER_CHANNEL_ALL = 0xF, /**< All channel */ +} timer_channel_t; + +/** + * @brief TIMER one pulse mode + */ +typedef enum +{ + TIMER_OP_MODE_REPEAT = 0, /**< Repetitive */ + TIMER_OP_MODE_SINGLE = 1, /**< single */ +} timer_op_mode_t; + +/** + * @brief TIMER one pulse output channel + */ +typedef enum +{ + TIMER_OP_OUTPUT_CHANNEL_1 = 0, /**< One pulse output channal 1 */ + TIMER_OP_OUTPUT_CHANNEL_2 = 1, /**< One pulse output channal 2 */ +} timer_op_output_channel_t; + +/** + * @brief TIMER time base configuration structure definition + */ +typedef struct +{ + uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */ + timer_cnt_mode_t mode; /**< Specifies the counter mode. */ + uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */ + timer_clock_division_t clk_div; /**< Specifies the clock division.*/ + uint32_t re_cnt; /**< Specifies the repetition counter value. */ +} timer_base_init_t; + +/** + * @brief TIMER output compare configuration structure definition + */ +typedef struct +{ + timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */ + uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */ + timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */ + timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity. */ + type_func_t oc_fast_en; /**< Specifies the Fast mode state. */ + timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ + timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ +} timer_oc_init_t; + +/** + * @brief State structures definition + */ +typedef enum +{ + TIMER_STATE_RESET = 0x00, /**< Peripheral not yet initialized or disabled */ + TIMER_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + TIMER_STATE_BUSY = 0x02, /**< An internal process is ongoing */ + TIMER_STATE_TIMEREOUT = 0x03, /**< Timeout state */ + TIMER_STATE_ERROR = 0x04, /**< Reception process is ongoing */ +} timer_state_t; + +/** + * @brief Active channel structures definition + */ +typedef enum +{ + TIMER_ACTIVE_CHANNEL_1 = 0x01, /**< The active channel is 1 */ + TIMER_ACTIVE_CHANNEL_2 = 0x02, /**< The active channel is 2 */ + TIMER_ACTIVE_CHANNEL_3 = 0x04, /**< The active channel is 3 */ + TIMER_ACTIVE_CHANNEL_4 = 0x08, /**< The active channel is 4 */ + TIMER_ACTIVE_CHANNEL_CLEARED = 0x00, /**< All active channels cleared */ +} timer_active_channel_t; + +/** + * @brief TIMER time base handle structure definition + */ +typedef struct timer_handle_s +{ + TIMER_TypeDef *perh; /**< Register base address */ + timer_base_init_t init; /**< TIMER Time Base required parameters */ + timer_active_channel_t ch; /**< Active channel */ + lock_state_t lock; /**< Locking object */ + timer_state_t state; /**< TIMER operation state */ + + void (*period_elapse_cbk)(struct timer_handle_s *arg); /**< Period elapse callback */ + void (*delay_elapse_cbk)(struct timer_handle_s *arg); /**< Delay_elapse callback */ + void (*capture_cbk)(struct timer_handle_s *arg); /**< Capture callback */ + void (*pwm_pulse_finish_cbk)(struct timer_handle_s *arg); /**< PWM_pulse_finish callback */ + void (*trigger_cbk)(struct timer_handle_s *arg); /**< Trigger callback */ + void (*break_cbk)(struct timer_handle_s *arg); /**< Break callback */ + void (*com_cbk)(struct timer_handle_s *arg); /**< commutation callback */ + void (*error_cbk)(struct timer_handle_s *arg); /**< Error callback */ +} timer_handle_t; + + +/** + * @brief TIMER encoder mode + */ +typedef enum +{ + TIMER_ENC_MODE_TI1 = 1, /**< encoder mode 1 */ + TIMER_ENC_MODE_TI2 = 2, /**< encoder mode 2 */ + TIMER_ENC_MODE_TI12 = 3, /**< encoder mode 3 */ +} timer_encoder_mode_t; + +/** + * @brief TIMER input capture polarity + */ +typedef enum +{ + TIMER_IC_POLARITY_RISE = 0, /**< Input capture polarity rising */ + TIMER_IC_POLARITY_FALL = 1, /**< Input capture polarity falling */ +} timer_ic_polarity_t; + +/** + *@brief TIMER input capture selection + */ +typedef enum +{ + TIMER_IC_SEL_DIRECT = 1, /**< IC1 -- TI1 */ + TIMER_IC_SEL_INDIRECT = 2, /**< IC1 -- TI2 */ + TIMER_IC_SEL_TRC = 3, /**< IC1 -- TRC */ +} timer_ic_select_t; + +/** + * @brief TIMER input capture prescaler + */ +typedef enum +{ + TIMER_IC_PSC_DIV1 = 0, /**< Capture performed once every 1 events */ + TIMER_IC_PSC_DIV2 = 1, /**< Capture performed once every 2 events */ + TIMER_IC_PSC_DIV4 = 2, /**< Capture performed once every 4 events */ + TIMER_IC_PSC_DIV8 = 3, /**< Capture performed once every 4 events */ +} timer_ic_prescaler_t; + +/** + * @brief TIMER encoder configuration structure definition + */ +typedef struct +{ + timer_encoder_mode_t mode; /**< Specifies the encoder mode */ + timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t ic1_sel; /**< Specifies the input */ + timer_ic_prescaler_t ic1_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic1_filter; /**< Specifies the input capture filter */ + timer_ic_polarity_t ic2_polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t ic2_sel; /**< Specifies the input */ + timer_ic_prescaler_t ic2_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic2_filter; /**< Specifies the input capture filter */ +} timer_encoder_init_t; + +/** + * @brief TIMER input capture configuration structure definition + */ +typedef struct +{ + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t sel; /**< Specifies the input */ + timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ + uint32_t filter; /**< Specifies the input capture filter */ +} timer_ic_init_t; + +/** + * @brief TIMER one pulse mode configuration structure definition + */ +typedef struct +{ + timer_oc_mode_t mode; /**< Specifies the TIMER mode */ + uint16_t pulse; /**< Specifies the pulse value */ + timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity */ + timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity */ + timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t sel; /**< Specifies the input */ + uint32_t filter; /**< Specifies the input capture filter */ +} timer_one_pulse_init_t; + +/** @brief TIMER clear input source + */ +typedef enum +{ + TIMER_INPUT_NONE = 0, /**< Clear input none */ + TIMER_INPUT_ETR = 1, /**< Clear input etr */ +} timer_clear_input_source_t; + +/** @brief TIMER clear input polarity + */ +typedef enum +{ + TIMER_POLARITY_NO_INV = 0, /**< Polarity for ETRx pin */ + TIMER_POLARITY_INV = 1, /**< Polarity for ETRx pin */ +} timer_clear_input_polarity_t; + +/** @brief TIMER clear input polarity + */ +typedef enum +{ + TIMER_ETR_PSC_DIV1 = 0, /**< No prescaler is used */ + TIMER_ETR_PSC_DIV2 = 1, /**< ETR input source is divided by 2 */ + TIMER_ETR_PSC_DIV4 = 2, /**< ETR input source is divided by 4 */ + TIMER_ETR_PSC_DIV8 = 3, /**< ETR input source is divided by 8 */ +} timer_etr_psc_t; + +/** + * @brief TIMER clear input configuration handle structure definition + */ +typedef struct +{ + type_func_t state; /**< TIMER clear Input state */ + timer_clear_input_source_t source; /**< TIMER clear Input sources */ + timer_clear_input_polarity_t polarity; /**< TIMER Clear Input polarity */ + timer_etr_psc_t psc; /**< TIMER Clear Input prescaler */ + uint32_t filter; /**< TIMER Clear Input filter */ +} timer_clear_input_config_t; + +/** @brief TIMER clock source + */ +typedef enum +{ + TIMER_SRC_ETRMODE2 = 0, /**< Clock source is etr mode2 */ + TIMER_SRC_INTER = 1, /**< Clock source is etr internal */ + TIMER_SRC_ITR0 = 2, /**< Clock source is etr itr0 */ + TIMER_SRC_ITR1 = 3, /**< Clock source is etr itr1 */ + TIMER_SRC_ITR2 = 4, /**< Clock source is etr itr2 */ + TIMER_SRC_ITR3 = 5, /**< Clock source is etr itr3 */ + TIMER_SRC_TI1ED = 6, /**< Clock source is etr ti1ed */ + TIMER_SRC_TI1 = 7, /**< Clock source is etr ti1 */ + TIMER_SRC_TI2 = 8, /**< Clock source is etr ti2 */ + TIMER_SRC_ETRMODE1 = 9, /**< Clock source is etr mode1 */ +} timer_clock_source_t; + +/** @brief TIMER clock polarity + */ +typedef enum +{ + TIMER_CLK_POLARITY_INV = 1, /**< Polarity for ETRx clock sources */ + TIMER_CLK_POLARITY_NO_INV = 0, /**< Polarity for ETRx clock sources */ + TIMER_CLK_POLARITY_RISE = 0, /**< Polarity for TIx clock sources */ + TIMER_CLK_POLARITY_FALL = 1, /**< Polarity for TIx clock sources */ + TIMER_CLK_POLARITY_BOTH = 3, /**< Polarity for TIx clock sources */ +} timer_clock_polarity_t; + +/** + * @brief TIMER clock config structure definition + */ +typedef struct +{ + timer_clock_source_t source; /**< TIMER clock sources */ + timer_clock_polarity_t polarity; /**< TIMER clock polarity */ + timer_etr_psc_t psc; /**< TIMER clock prescaler */ + uint32_t filter; /**< TIMER clock filter */ +} timer_clock_config_t; + +/** + * @brief TIMER slave mode + */ +typedef enum +{ + TIMER_MODE_DISABLE = 0, /**< Slave mode is disable */ + TIMER_MODE_ENC1 = 1, /**< Slave mode is encoder1 */ + TIMER_MODE_ENC2 = 2, /**< Slave mode is encoder2 */ + TIMER_MODE_ENC3 = 3, /**< Slave mode is encoder3 */ + TIMER_MODE_RESET = 4, /**< Slave mode is reset */ + TIMER_MODE_GATED = 5, /**< Slave mode is gated */ + TIMER_MODE_TRIG = 6, /**< Slave mode is trigger */ + TIMER_MODE_EXTERNAL1 = 7, /**< Slave mode is external1 */ +} timer_slave_mode_t; + +/** + * @brief TIMER ts definition + */ +typedef enum +{ + TIMER_TS_ITR0 = 0, /**< ITR0 */ + TIMER_TS_ITR1 = 1, /**< ITR1 */ + TIMER_TS_ITR2 = 2, /**< ITR2 */ + TIMER_TS_ITR3 = 3, /**< ITR3 */ + TIMER_TS_TI1F_ED = 4, /**< TI1F_ED */ + TIMER_TS_TI1FP1 = 5, /**< TI1FP1 */ + TIMER_TS_TI2FP2 = 6, /**< TI2FP2 */ + TIMER_TS_ETRF = 7, /**< ETRF */ +} timer_ts_t; + +/** + * @brief TIMER slave configuration structure definition + */ +typedef struct +{ + timer_slave_mode_t mode; /**< Slave mode selection */ + timer_ts_t input; /**< Input Trigger source */ + timer_clock_polarity_t polarity; /**< Input Trigger polarity */ + timer_etr_psc_t psc; /**< Input trigger prescaler */ + uint32_t filter; /**< Input trigger filter */ +} timer_slave_config_t; + +/** + * @brief TIMER hall sensor configuretion structure definition + */ +typedef struct +{ + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ + uint32_t filter; /**< Specifies the input capture filter [0x0, 0xF] */ + uint32_t delay; /**< Specifies the pulse value to be loaded into the register [0x0, 0xFFFF] */ +} timer_hall_sensor_init_t; + +/** + * @brief TIMER lock level + */ +typedef enum +{ + TIMER_LOCK_LEVEL_OFF = 0, /**< Lock off */ + TIMER_LOCK_LEVEL_1 = 1, /**< Lock level 1 */ + TIMER_LOCK_LEVEL_2 = 2, /**< Lock level 2 */ + TIMER_LOCK_LEVEL_3 = 3, /**< Lock level 3 */ +} timer_lock_level_t; + +/** + * @brief TIMER break polarity + */ +typedef enum +{ + TIMER_BREAK_POLARITY_LOW = 0, /**< LOW */ + TIMER_BREAK_POLARITY_HIGH = 1, /**< HIGH */ +} timer_break_polarity_t; + +/** + * @brief TIMER break and dead time configuretion structure definition + */ +typedef struct +{ + type_func_t off_run; /**< Enalbe/Disable off state in run mode */ + type_func_t off_idle; /**< Enalbe/Disable off state in idle mode */ + timer_lock_level_t lock_level; /**< Lock level */ + uint32_t dead_time; /**< Dead time, [0x0, 0xFF] */ + type_func_t break_state; /**< Break state */ + timer_break_polarity_t polarity; /**< Break input polarity */ + type_func_t auto_out; /**< Enalbe/Disable automatic output */ +} timer_break_dead_time_t; + +/** + * @brief TIMER commutation event channel configuretion structure definition + */ +typedef struct +{ + type_func_t en; /**< Enalbe/Disable the channel */ + type_func_t n_en; /**< Enalbe/Disable the complementary channel */ + timer_oc_mode_t mode; /**< Mode of the channel */ +} timer_channel_config_t; + +/** + * @brief TIMER commutation event configuretion structure definition + */ +typedef struct +{ + timer_channel_config_t ch[3]; /**< Configure of channel */ +} timer_com_channel_config_t; + +/** + * @brief TIMER master mode selection + */ +typedef enum +{ + TIMER_TRGO_RESET = 0, /**< RESET */ + TIMER_TRGO_ENABLE = 1, /**< ENABLE */ + TIMER_TRGO_UPDATE = 2, /**< UPDATE */ + TIMER_TRGO_OC1 = 3, /**< OC1 */ + TIMER_TRGO_OC1REF = 4, /**< OC1REF */ + TIMER_TRGO_OC2REF = 5, /**< OC2REF */ + TIMER_TRGO_OC3REF = 6, /**< OC3REF */ + TIMER_TRGO_OC4REF = 7, /**< OC4REF */ +} timer_master_mode_sel_t; + +/** + * @brief TIMER master configuretion structure definition + */ +typedef struct +{ + timer_master_mode_sel_t sel; /**< Specifies the active edge of the input signal */ + type_func_t master_en; /**< Master/Slave mode selection */ +} timer_master_config_t; + +/** + * @brief Specifies the event source + */ +typedef enum +{ + TIMER_SRC_UPDATE = (1U << 0), /**< Event source is update */ + TIMER_SRC_CC1 = (1U << 1), /**< Event source is channel1 */ + TIMER_SRC_CC2 = (1U << 2), /**< Event source is channel2 */ + TIMER_SRC_CC3 = (1U << 3), /**< Event source is channel3 */ + TIMER_SRC_CC4 = (1U << 4), /**< Event source is channel4 */ + TIMER_SRC_COM = (1U << 5), /**< Event source is compare */ + TIMER_SRC_TRIG = (1U << 6), /**< Event source is trigger */ + TIMER_SRC_BREAK = (1U << 7), /**< Event source is break */ +} timer_event_source_t; + +/** + * @brief TIMER interrupt definition + */ +typedef enum +{ + TIMER_IT_UPDATE = (1U << 0), /**< Update interrupt bit */ + TIMER_IT_CC1 = (1U << 1), /**< Channel1 interrupt bit */ + TIMER_IT_CC2 = (1U << 2), /**< Channel2 interrupt bit */ + TIMER_IT_CC3 = (1U << 3), /**< Channel3 interrupt bit */ + TIMER_IT_CC4 = (1U << 4), /**< Channel4 interrupt bit */ + TIMER_IT_COM = (1U << 5), /**< compare interrupt bit */ + TIMER_IT_TRIGGER = (1U << 6), /**< Trigger interrupt bit */ + TIMER_IT_BREAK = (1U << 7), /**< Break interrupt bit */ +} timer_it_t; + +/** + * @brief TIMER DMA request + */ +typedef enum +{ + TIMER_DMA_UPDATE = (1U << 8), /**< DMA request from update */ + TIMER_DMA_CC1 = (1U << 9), /**< DMA request from channel1 */ + TIMER_DMA_CC2 = (1U << 10), /**< DMA request from channel2 */ + TIMER_DMA_CC3 = (1U << 11), /**< DMA request from channel3 */ + TIMER_DMA_CC4 = (1U << 12), /**< DMA request from channel4 */ + TIMER_DMA_COM = (1U << 13), /**< DMA request from compare */ + TIMER_DMA_TRIGGER = (1U << 14), /**< DMA request from trigger */ +} timer_dma_req_t; + +/** + * @brief TIMER flag definition + */ +typedef enum +{ + TIMER_FLAG_UPDATE = (1U << 0), /**< Update interrupt flag */ + TIMER_FLAG_CC1 = (1U << 1), /**< Channel1 interrupt flag */ + TIMER_FLAG_CC2 = (1U << 2), /**< Channel2 interrupt flag */ + TIMER_FLAG_CC3 = (1U << 3), /**< Channel3 interrupt flag */ + TIMER_FLAG_CC4 = (1U << 4), /**< Channel4 interrupt flag */ + TIMER_FLAG_COM = (1U << 5), /**< Compare interrupt flag */ + TIMER_FLAG_TRIGGER = (1U << 6), /**< Trigger interrupt flag */ + TIMER_FLAG_BREAK = (1U << 7), /**< Break interrupt flag */ + TIMER_FLAG_CC1OF = (1U << 9), /**< Channel1 override state flag */ + TIMER_FLAG_CC2OF = (1U << 10), /**< Channel2 override state flag */ + TIMER_FLAG_CC3OF = (1U << 11), /**< Channel3 override state flag */ + TIMER_FLAG_CC4OF = (1U << 12), /**< Channel4 override state flag */ +} timer_flag_t; +/** + * @} + */ + +/** @defgroup TIMER_Public_Macros TIMER Public Macros + * @{ + */ +#define CCER_CCxE_MASK ((1U << 0) | (1U << 4) | (1U << 8) | (1U << 12)) +#define CCER_CCxNE_MASK ((1U << 2) | (1U << 6) | (1U << 10)) + +/** + * @brief Reset TIMER handle state + */ +#define TIMER_RESET_HANDLE_STATE(hperh) ((hperh)->state = TIMER_STATE_RESET) + +/** + * @brief Enable the TIMER peripheral. + */ +#define TIMER_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK)) + +/** + * @brief Enable the TIMER main output. + */ +#define TIMER_MOE_ENABLE(hperh) (SET_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK)) + +/** + * @brief Disable the TIMER peripheral. + */ +#define TIMER_DISABLE(hperh) \ + do { \ + if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \ + } while (0) + +/** + * @brief Disable the TIMER main output. + * @note The Main Output Enable of a timer instance is disabled only if + * all the CCx and CCxN channels have been disabled + */ +#define TIMER_MOE_DISABLE(hperh) \ + do { \ + if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \ + } while (0) + +/** + * @brief Sets the TIMER autoreload register value on runtime without calling + * another time any Init function. + */ +#define TIMER_SET_AUTORELOAD(handle, AUTORELOAD) \ + do { \ + (handle)->perh->AR = (AUTORELOAD); \ + (handle)->init.period = (AUTORELOAD); \ + } while (0) + +/** + * @brief Gets the TIMER autoreload register value on runtime + */ +#define TIMER_GET_AUTORELOAD(handle) ((handle)->perh->AR) + +/** + * @brief Gets the TIMER count register value on runtime + */ +#define TIMER_GET_CNT(handle) ((handle)->perh->COUNT) + +/** + * @brief Gets the TIMER count direction value on runtime + */ +#define TIMER_GET_DIR(handle) (READ_BITS((handle)->perh->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS)) + +/** + * @brief CCx DMA request sent when CCx event occurs + */ +#define TIMER_CCx_DMA_REQ_CCx(handle) (CLEAR_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) + +/** + * @brief CCx DMA request sent when update event occurs + */ +#define TIMER_CCx_DMA_REQ_UPDATE(handle) (SET_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) + +/** + * @brief Enable channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + * TIMER_CHANNEL_4 + */ +#define TIMER_CCx_ENABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ + (SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2)))))) + +/** + * @brief Disable channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + * TIMER_CHANNEL_4 + */ +#define TIMER_CCx_DISABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ + (CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2)))) + +/** + * @brief Enable complementary channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + */ +#define TIMER_CCxN_ENABLE(handle, ch) ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2))) + +/** + * @brief Disable complementary channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + */ +#define TIMER_CCxN_DISABLE(handle, ch) ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2))) +/** + * @} + */ + +/** @defgroup TIMER_Private_Macros TIMER Private Macros + * @{ + */ +#if defined (ES32F065x) +#define IS_TIMER_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1) || \ + ((x) == BS16T0) || \ + ((x) == BS16T1) || \ + ((x) == BS16T2) || \ + ((x) == BS16T3)) +#define IS_ADTIMER_INSTANCE(x) ((x) == AD16C4T0) +#define IS_TIMER_XOR_INSTANCE(x) (((x) == AD16C4T0) || ((x) == GP16C4T0)) +#define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) +#define IS_TIMER_CC2_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) +#define IS_TIMER_CC4_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == GP16C4T0)) +#define IS_TIMER_BREAK_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) +#define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == AD16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == AD16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2)))) +#define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == AD16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP16C2T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4)))) +#define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == AD16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) +#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) +#define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) + +#elif defined (ES32F033x) || defined (ES32F093x) + +#define IS_TIMER_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == BS16T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1) || \ + ((x) == BS16T1) || \ + ((x) == BS16T2) || \ + ((x) == GP16C4T1) || \ + ((x) == BS16T3)) +#define IS_ADTIMER_INSTANCE(x) ((x) == AD16C4T0) +#define IS_TIMER_XOR_INSTANCE(x) (((x) == GP16C4T0) || ((x) == GP16C4T1)) +#define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) +#define IS_TIMER_CC2_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1) || \ + ((x) == GP16C4T1)) +#define IS_TIMER_CC4_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP16C4T1)) +#define IS_TIMER_BREAK_INSTANCE(x) (((x) == GP16C4T0)) +#define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == GP16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2)))) +#define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == GP16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP16C2T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C2T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4)))) +#define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == GP16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) +#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP16C2T0) || \ + ((x) == GP16C2T1)) +#define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) +#endif + +#define IS_TIMER_COUNTER_MODE(x) (((x) == TIMER_CNT_MODE_UP) || \ + ((x) == TIMER_CNT_MODE_DOWN) || \ + ((x) == TIMER_CNT_MODE_CENTER1) || \ + ((x) == TIMER_CNT_MODE_CENTER2) || \ + ((x) == TIMER_CNT_MODE_CENTER3)) +#define IS_TIMER_CLOCK_DIVISION(x) (((x) == TIMER_CLOCK_DIV1) || \ + ((x) == TIMER_CLOCK_DIV2) || \ + ((x) == TIMER_CLOCK_DIV4)) +#define IS_TIMER_PWM_MODE(x) (((x) == TIMER_OC_MODE_PWM1) || \ + ((x) == TIMER_OC_MODE_PWM2)) +#define IS_TIMER_OC_MODE(x) (((x) == TIMER_OC_MODE_TIMERING) || \ + ((x) == TIMER_OC_MODE_ACTIVE) || \ + ((x) == TIMER_OC_MODE_INACTIVE) || \ + ((x) == TIMER_OC_MODE_TOGGLE) || \ + ((x) == TIMER_OC_MODE_FORCE_ACTIVE) || \ + ((x) == TIMER_OC_MODE_FORCE_INACTIVE) || \ + ((x) == TIMER_OC_MODE_PWM1) || \ + ((x) == TIMER_OC_MODE_PWM2)) +#define IS_TIMER_OC_POLARITY(x) (((x) == TIMER_OC_POLARITY_HIGH) || \ + ((x) == TIMER_OC_POLARITY_LOW)) +#define IS_TIMER_OCN_POLARITY(x) (((x) == TIMER_OCN_POLARITY_HIGH) || \ + ((x) == TIMER_OCN_POLARITY_LOW)) +#define IS_TIMER_OCIDLE_STATE(x) (((x) == TIMER_OC_IDLE_RESET) || \ + ((x) == TIMER_OC_IDLE_SET)) +#define IS_TIMER_OCNIDLE_STATE(x) (((x) == TIMER_OCN_IDLE_RESET) || \ + ((x) == TIMER_OCN_IDLE_SET)) +#define IS_TIMER_CHANNELS(x) (((x) == TIMER_CHANNEL_1) || \ + ((x) == TIMER_CHANNEL_2) || \ + ((x) == TIMER_CHANNEL_3) || \ + ((x) == TIMER_CHANNEL_4) || \ + ((x) == TIMER_CHANNEL_ALL)) +#define IS_TIMER_OP_MODE(x) (((x) == TIMER_OP_MODE_REPEAT) || \ + ((x) == TIMER_OP_MODE_SINGLE)) +#define IS_TIMER_OP_OUTPUT_CH(x) (((x) == TIMER_OP_OUTPUT_CHANNEL_1) || \ + ((x) == TIMER_OP_OUTPUT_CHANNEL_2)) +#define IS_TIMER_ENCODER_MODE(x) (((x) == TIMER_ENC_MODE_TI1) || \ + ((x) == TIMER_ENC_MODE_TI2) || \ + ((x) == TIMER_ENC_MODE_TI12)) +#define IS_TIMER_IC_POLARITY(x) (((x) == TIMER_IC_POLARITY_RISE) || \ + ((x) == TIMER_IC_POLARITY_FALL)) +#define IS_TIMER_IC_SELECT(x) (((x) == TIMER_IC_SEL_DIRECT) || \ + ((x) == TIMER_IC_SEL_INDIRECT) || \ + ((x) == TIMER_IC_SEL_TRC)) +#define IS_TIMER_IC_PSC(x) (((x) == TIMER_IC_PSC_DIV1) || \ + ((x) == TIMER_IC_PSC_DIV2) || \ + ((x) == TIMER_IC_PSC_DIV4) || \ + ((x) == TIMER_IC_PSC_DIV8)) +#define IS_TIMER_IC_FILTER(x) ((x) <= 0xF) +#define IS_TIMER_DEAD_TIMERE(x) ((x) <= 0xFF) +#define IS_TIMER_CLEAR_INPUT_SOURCE(x) (((x) == TIMER_INPUT_NONE) || \ + ((x) == TIMER_INPUT_ETR)) +#define IS_TIMER_CLEAR_INPUT_POLARITY(x) (((x) == TIMER_POLARITY_NO_INV) || \ + ((x) == TIMER_POLARITY_INV)) +#define IS_TIMER_ETR_PSC(x) (((x) == TIMER_ETR_PSC_DIV1) || \ + ((x) == TIMER_ETR_PSC_DIV2) || \ + ((x) == TIMER_ETR_PSC_DIV4) || \ + ((x) == TIMER_ETR_PSC_DIV8)) +#define IS_TIMER_CLOCK_SOURCE(x) (((x) == TIMER_SRC_ETRMODE2) || \ + ((x) == TIMER_SRC_INTER) || \ + ((x) == TIMER_SRC_ITR0) || \ + ((x) == TIMER_SRC_ITR1) || \ + ((x) == TIMER_SRC_ITR2) || \ + ((x) == TIMER_SRC_ITR3) || \ + ((x) == TIMER_SRC_TI1ED) || \ + ((x) == TIMER_SRC_TI1) || \ + ((x) == TIMER_SRC_TI2) || \ + ((x) == TIMER_SRC_ETRMODE1)) +#define IS_TIMER_CLOCK_POLARITY(x) (((x) == TIMER_CLK_POLARITY_INV) || \ + ((x) == TIMER_CLK_POLARITY_NO_INV) || \ + ((x) == TIMER_CLK_POLARITY_RISE) || \ + ((x) == TIMER_CLK_POLARITY_FALL) || \ + ((x) == TIMER_CLK_POLARITY_BOTH)) +#define IS_TIMER_SLAVE_MODE(x) (((x) == TIMER_MODE_DISABLE) || \ + ((x) == TIMER_MODE_ENC1) || \ + ((x) == TIMER_MODE_ENC2) || \ + ((x) == TIMER_MODE_ENC3) || \ + ((x) == TIMER_MODE_RESET) || \ + ((x) == TIMER_MODE_GATED) || \ + ((x) == TIMER_MODE_TRIG) || \ + ((x) == TIMER_MODE_EXTERNAL1)) +#define IS_TIMER_EVENT_SOURCE(x) (((x) == TIMER_SRC_UPDATE) || \ + ((x) == TIMER_SRC_CC1) || \ + ((x) == TIMER_SRC_CC2) || \ + ((x) == TIMER_SRC_CC3) || \ + ((x) == TIMER_SRC_CC4) || \ + ((x) == TIMER_SRC_COM) || \ + ((x) == TIMER_SRC_TRIG) || \ + ((x) == TIMER_SRC_BREAK)) +#define IS_TIMER_TS(x) (((x) == TIMER_TS_ITR0) || \ + ((x) == TIMER_TS_ITR1) || \ + ((x) == TIMER_TS_ITR2) || \ + ((x) == TIMER_TS_ITR3) || \ + ((x) == TIMER_TS_TI1F_ED) || \ + ((x) == TIMER_TS_TI1FP1) || \ + ((x) == TIMER_TS_TI2FP2) || \ + ((x) == TIMER_TS_ETRF)) +#define IS_TIMER_CLOCK_LEVEL(x) (((x) == TIMER_LOCK_LEVEL_OFF) || \ + ((x) == TIMER_LOCK_LEVEL_1) || \ + ((x) == TIMER_LOCK_LEVEL_2) || \ + ((x) == TIMER_LOCK_LEVEL_3)) +#define IS_TIMER_BREAK_POLARITY(x) (((x) == TIMER_BREAK_POLARITY_LOW) || \ + ((x) == TIMER_BREAK_POLARITY_HIGH)) +#define IS_TIMER_MASTER_MODE_SEL(x) (((x) == TIMER_TRGO_RESET) || \ + ((x) == TIMER_TRGO_ENABLE) || \ + ((x) == TIMER_TRGO_UPDATE) || \ + ((x) == TIMER_TRGO_OC1) || \ + ((x) == TIMER_TRGO_OC1REF) || \ + ((x) == TIMER_TRGO_OC2REF) || \ + ((x) == TIMER_TRGO_OC3REF) || \ + ((x) == TIMER_TRGO_OC4REF)) +#define IS_TIMER_IT(x) (((x) == TIMER_IT_UPDATE) || \ + ((x) == TIMER_IT_CC1) || \ + ((x) == TIMER_IT_CC2) || \ + ((x) == TIMER_IT_CC3) || \ + ((x) == TIMER_IT_CC4) || \ + ((x) == TIMER_IT_COM) || \ + ((x) == TIMER_IT_TRIGGER) || \ + ((x) == TIMER_IT_BREAK)) +#define IS_TIMER_DMA_REQ(x) (((x) == TIMER_DMA_UPDATE) || \ + ((x) == TIMER_DMA_CC1) || \ + ((x) == TIMER_DMA_CC2) || \ + ((x) == TIMER_DMA_CC3) || \ + ((x) == TIMER_DMA_CC4) || \ + ((x) == TIMER_DMA_COM) || \ + ((x) == TIMER_DMA_TRIGGER)) +#define IS_TIMER_FLAG(x) (((x) == TIMER_FLAG_UPDATE) || \ + ((x) == TIMER_FLAG_CC1) || \ + ((x) == TIMER_FLAG_CC2) || \ + ((x) == TIMER_FLAG_CC3) || \ + ((x) == TIMER_FLAG_CC4) || \ + ((x) == TIMER_FLAG_COM) || \ + ((x) == TIMER_FLAG_TRIGGER) || \ + ((x) == TIMER_FLAG_BREAK) || \ + ((x) == TIMER_FLAG_CC1OF) || \ + ((x) == TIMER_FLAG_CC2OF) || \ + ((x) == TIMER_FLAG_CC3OF) || \ + ((x) == TIMER_FLAG_CC4OF)) +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions + * @{ + */ +/** @addtogroup TIMER_Public_Functions_Group1 + * @{ + */ +/* Time Base functions */ +ald_status_t ald_timer_base_init(timer_handle_t *hperh); +void ald_timer_base_reset(timer_handle_t *hperh); +void ald_timer_base_start(timer_handle_t *hperh); +void ald_timer_base_stop(timer_handle_t *hperh); +void ald_timer_base_start_by_it(timer_handle_t *hperh); +void ald_timer_base_stop_by_it(timer_handle_t *hperh); +#ifdef ALD_DMA +ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_base_stop_by_dma(timer_handle_t *hperh); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group2 + * @{ + */ +/* Timer Output Compare functions */ +ald_status_t ald_timer_oc_init(timer_handle_t *hperh); +void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group3 + * @{ + */ +/* Timer PWM functions */ +ald_status_t ald_timer_pwm_init(timer_handle_t *hperh); +void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq); +void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty); +void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group4 + * @{ + */ +/* Timer Input Capture functions */ +ald_status_t ald_timer_ic_init(timer_handle_t *hperh); +void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group5 + * @{ + */ +/* Timer One Pulse functions */ +ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode); +void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch); +void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch); +void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch); +void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group6 + * @{ + */ +/* Timer encoder functions */ +ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config); +void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, + uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2); +void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group7 + * @{ + */ +/* Timer hall sensor functions */ +ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config); +void ald_timer_hall_sensor_start(timer_handle_t *hperh); +void ald_timer_hall_sensor_stop(timer_handle_t *hperh); +void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh); +void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh); +#ifdef ALD_DMA +ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group8 + * @{ + */ +/* Timer complementary output compare functions */ +void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group9 + * @{ + */ +/* Timer complementary PWM functions */ +void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +#ifdef ALD_DMA +ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +#endif +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group10 + * @{ + */ +/* Timer complementary one pulse functions */ +void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group11 + * @{ + */ +/* Control functions */ +ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch); +ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch); +ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, + timer_channel_t ch_out, timer_channel_t ch_in); +ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch); +ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config); +ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select); +ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config); +ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config); +ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_t event); +uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch); +void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config); +void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi); +void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi); +void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config); +void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config); +void ald_timer_irq_handler(timer_handle_t *hperh); +void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state); +void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state); +it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it); +flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag); +void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group12 + * @{ + */ +/* State functions */ +timer_state_t ald_timer_get_state(timer_handle_t *hperh); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_TIMER_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h new file mode 100644 index 0000000000000000000000000000000000000000..a1142838eb5fe1e247e0e5fea1e0fc93381d77ae --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h @@ -0,0 +1,210 @@ +/** + ********************************************************************************* + * + * @file ald_trng.h + * @brief Header file of TRNG module driver. + * + * @version V1.0 + * @date 04 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_TRNG_H__ +#define __ALD_TRNG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup TRNG + * @{ + */ + +/** @defgroup TRNG_Public_Types TRNG Public Types + * @{ + */ +/** + * @brief Data width + */ +typedef enum +{ + TRNG_DSEL_1B = 0x0, /**< 1-bit */ + TRNG_DSEL_8B = 0x1, /**< 8-bit */ + TRNG_DSEL_16B = 0x2, /**< 16-bit */ + TRNG_DSEL_32B = 0x3, /**< 32-bit */ +} trng_data_width_t; + +/** + * @brief seed type + */ +typedef enum +{ + TRNG_SEED_TYPE_0 = 0x0, /**< Using 0 as seed */ + TRNG_SEED_TYPE_1 = 0x1, /**< Using 1 as seed */ + TRNG_SEED_TYPE_LAST = 0x2, /**< Using last seed */ + TRNG_SEED_TYPE_SEED = 0x3, /**< Using value of register */ +} trng_seed_type_t; + +/** + * @brief TRNG init structure definition + */ +typedef struct +{ + trng_data_width_t data_width; /**< The width of data */ + trng_seed_type_t seed_type; /**< The seed type */ + uint32_t seed; /**< The value of seed */ + uint16_t t_start; /**< T(start) = T(hclk) * (t_start + 1), T(start) > 1ms */ + uint8_t adjc; /**< Adjust parameter */ + type_func_t posten; /**< Data back handle function */ +} trng_init_t; + +/** + * @brief TRNG state structures definition + */ +typedef enum +{ + TRNG_STATE_RESET = 0x0, /**< Peripheral is not initialized */ + TRNG_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ + TRNG_STATE_BUSY = 0x2, /**< An internal process is ongoing */ + TRNG_STATE_ERROR = 0x4, /**< Error */ +} trng_state_t; + +/** + * @brief State type + */ +typedef enum +{ + TRNG_STATUS_START = (1U << 0), /**< Start state */ + TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */ + TRNG_STATUS_SERR = (1U << 2), /**< Error state */ +} trng_status_t; + +/** + * @brief Interrupt type + */ +typedef enum +{ + TRNG_IT_START = (1U << 0), /**< Start */ + TRNG_IT_DAVLD = (1U << 1), /**< Data valid */ + TRNG_IT_SERR = (1U << 2), /**< Error */ +} trng_it_t; + +/** + * @brief Interrupt flag type + */ +typedef enum +{ + TRNG_IF_START = (1U << 0), /**< Start */ + TRNG_IF_DAVLD = (1U << 1), /**< Data valid */ + TRNG_IF_SERR = (1U << 2), /**< Error */ +} trng_flag_t; + +/** + * @brief TRNG Handle Structure definition + */ +typedef struct trng_handle_s +{ + TRNG_TypeDef *perh; /**< Register base address */ + trng_init_t init; /**< TRNG required parameters */ + uint32_t data; /**< result data */ + lock_state_t lock; /**< Locking object */ + trng_state_t state; /**< TRNG operation state */ + + void (*trng_cplt_cbk)(struct trng_handle_s *arg); /**< Trng completed callback */ + void (*err_cplt_cbk)(struct trng_handle_s *arg); /**< Trng error callback */ + void (*init_cplt_cbk)(struct trng_handle_s *arg); /**< Trng init completed callback */ +} trng_handle_t; +/** + * @} + */ + +/** @defgroup TRNG_Public_Macros TRNG Public Macros + * @{ + */ +#define TRNG_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK)) +#define TRNG_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK)) +#define TRNG_ADJM_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK)) +#define TRNG_ADJM_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK)) +/** + * @} + */ + +/** + * @defgroup TRNG_Private_Macros TRNG Private Macros + * @{ + */ +#define IS_TRNG_DATA_WIDTH(x) (((x) == TRNG_DSEL_1B) || \ + ((x) == TRNG_DSEL_8B) || \ + ((x) == TRNG_DSEL_16B) || \ + ((x) == TRNG_DSEL_32B)) +#define IS_TRNG_SEED_TYPE(x) (((x) == TRNG_SEED_TYPE_0) || \ + ((x) == TRNG_SEED_TYPE_1) || \ + ((x) == TRNG_SEED_TYPE_LAST) || \ + ((x) == TRNG_SEED_TYPE_SEED)) +#define IS_TRNG_STATUS(x) (((x) == TRNG_STATUS_START) || \ + ((x) == TRNG_STATUS_DAVLD) || \ + ((x) == TRNG_STATUS_SERR)) +#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \ + ((x) == TRNG_IT_DAVLD) || \ + ((x) == TRNG_IT_SERR)) +#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \ + ((x) == TRNG_IF_DAVLD) || \ + ((x) == TRNG_IF_SERR)) +#define IS_TRNG_ADJC(x) ((x) < 4) +/** + * @} + */ + +/** @addtogroup TRNG_Public_Functions + * @{ + */ +/** @addtogroup TRNG_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +extern ald_status_t ald_trng_init(trng_handle_t *hperh); +/** + * @} + */ +/** @addtogroup TRNG_Public_Functions_Group2 + * @{ + */ +/* Control functions */ +extern uint32_t ald_trng_get_result(trng_handle_t *hperh); +extern void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state); +extern flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status); +extern it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it); +extern flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag); +extern void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag); +extern void ald_trng_irq_handler(trng_handle_t *hperh); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_TRNG_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h new file mode 100644 index 0000000000000000000000000000000000000000..0f55db2a2981f546e323e3ff1d7417558b01ed50 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h @@ -0,0 +1,227 @@ +/** + ********************************************************************************* + * + * @file ald_tsense.h + * @brief Header file of TSENSE module driver. + * + * @version V1.0 + * @date 15 Dec 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_TSENSE_H__ +#define __ALD_TSENSE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup TSENSE + * @{ + */ + +/** @defgroup TSENSE_Public_Macros TSENSE Public Macros + * @{ + */ +#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0)) +#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669)) +#define TSENSE_ENABLE() \ + do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ + TSENSE_LOCK(); \ + } while (0) +#define TSENSE_DISABLE() \ + do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ + TSENSE_LOCK(); \ + } while (0) +#define TSENSE_REQ_ENABLE() \ + do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ + TSENSE_LOCK(); \ + } while (0) +#define TSENSE_REQ_DISABLE() \ + do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ + TSENSE_LOCK(); \ + } while (0) +#define TSENSE_CTN_ENABLE() \ + do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ + TSENSE_LOCK(); \ + } while (0) +#define TSENSE_CTN_DISABLE() \ + do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ + TSENSE_LOCK(); \ + } while (0) +#define TSENSE_RESET() \ + do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_RST_MSK); \ + TSENSE_LOCK(); \ + } while (0) +#define TSENSE_LTGR_WR(data) \ + do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->LTGR, (data)); \ + TSENSE_LOCK(); \ + } while(0) +#define TSENSE_HTGR_WR(data) \ + do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->HTGR, (data)); \ + TSENSE_LOCK(); \ + } while(0) +#define TSENSE_TBDR_WR(data) \ + do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->TBDR, (data)); \ + TSENSE_LOCK(); \ + } while(0) +#define TSENSE_TCALBDR_WR(data) \ + do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->TCALBDR, (data)); \ + TSENSE_LOCK(); \ + } while(0) +/** + * @} + */ + +/** @defgroup TSENSE_Public_Types TSENSE Public Types + * @{ + */ +/** + * @brief Temperature update time + */ +typedef enum +{ + TSENSE_UPDATE_CYCLE_3 = 0x3, /**< 3 Cycles */ + TSENSE_UPDATE_CYCLE_4 = 0x4, /**< 4 Cycles */ + TSENSE_UPDATE_CYCLE_5 = 0x5, /**< 5 Cycles */ + TSENSE_UPDATE_CYCLE_6 = 0x6, /**< 6 Cycles */ + TSENSE_UPDATE_CYCLE_7 = 0x7, /**< 7 Cycles */ +} tsense_update_cycle_t; + +/** + * @brief Temperature output mode + */ +typedef enum +{ + TSENSE_OUTPUT_MODE_200 = 0x0, /**< 200 cycles update one temperature */ + TSENSE_OUTPUT_MODE_400 = 0x1, /**< 400 cycles update one temperature */ + TSENSE_OUTPUT_MODE_800 = 0x2, /**< 800 cycles update one temperature */ + TSENSE_OUTPUT_MODE_1600 = 0x3, /**< 1600 cycles update one temperature */ + TSENSE_OUTPUT_MODE_3200 = 0x4, /**< 3200 cycles update one temperature */ +} tsense_output_mode_t; + +/** + * @brief Source select + */ +typedef enum +{ + TSENSE_SOURCE_LOSC = 0x0, /**< LOSC */ + TSENSE_SOURCE_LRC = 0x1, /**< LRC */ + TSENSE_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */ + TSENSE_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */ +} tsense_source_sel_t; + + +/** + * @brief TSENSE init structure definition + */ +typedef struct +{ + tsense_update_cycle_t cycle; /**< Temperature update time */ + tsense_output_mode_t mode; /**< Temperature output mode */ + type_func_t ctn; /**< Continue mode */ + uint8_t psc; /**< Perscaler */ +} tsense_init_t; + +/** + * @brief Define callback function type + */ +typedef void (*tsense_cbk)(uint16_t value, ald_status_t status); +/** + * @} + */ + +/** + * @defgroup TSENSE_Private_Macros TSENSE Private Macros + * @{ + */ +#define IS_TSENSE_UPDATE_CYCLE(x) (((x) == TSENSE_UPDATE_CYCLE_3) || \ + ((x) == TSENSE_UPDATE_CYCLE_4) || \ + ((x) == TSENSE_UPDATE_CYCLE_5) || \ + ((x) == TSENSE_UPDATE_CYCLE_6) || \ + ((x) == TSENSE_UPDATE_CYCLE_7)) +#define IS_TSENSE_OUTPUT_MODE(x) (((x) == TSENSE_OUTPUT_MODE_200) || \ + ((x) == TSENSE_OUTPUT_MODE_400) || \ + ((x) == TSENSE_OUTPUT_MODE_800) || \ + ((x) == TSENSE_OUTPUT_MODE_1600) || \ + ((x) == TSENSE_OUTPUT_MODE_3200)) +#define IS_TSENSE_SOURCE_SEL(x) (((x) == TSENSE_SOURCE_LOSC) || \ + ((x) == TSENSE_SOURCE_LRC) || \ + ((x) == TSENSE_SOURCE_HRC_DIV_1M ) || \ + ((x) == TSENSE_SOURCE_HOSC_DIV_1M)) +/** + * @} + */ + +/** @addtogroup TSENSE_Public_Functions + * @{ + */ +/** @addtogroup TSENSE_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +extern void ald_tsense_init(tsense_init_t *init); +extern void ald_tsense_source_select(tsense_source_sel_t sel); +/** + * @} + */ +/** @addtogroup TSENSE_Public_Functions_Group2 + * @{ + */ +/* Control functions */ +extern ald_status_t ald_tsense_get_value(uint16_t *tsense); +extern void ald_tsense_get_value_by_it(tsense_cbk cbk); +extern void ald_tsense_irq_handler(void); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_TSENSE_H__ */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..49cc24d9efb9d72fa7ce911da99613ccd353f702 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h @@ -0,0 +1,478 @@ +/** + ********************************************************************************* + * + * @file ald_uart.h + * @brief Header file of UART module library. + * + * @version V1.0 + * @date 21 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_UART_H__ +#define __ALD_UART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/** + * @defgroup UART_Public_Macros UART Public Macros + * @{ + */ +#define UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK)) +#define UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXEN_MSK)) +#define UART_BRR_WRITE_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK)) +#define UART_BRR_WRITE_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_BRWEN_MSK)) +#define UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK)) +#define UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RTOEN_MSK)) +#define UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK)) +#define UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_MSBFIRST_MSK)) +#define UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK)) +#define UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_DATAINV_MSK)) +#define UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK)) +#define UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_RXINV_MSK)) +#define UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK)) +#define UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_TXINV_MSK)) +#define UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK)) +#define UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCR, UART_LCR_SWAP_MSK)) +#define UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK)) +#define UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_HDSEL_MSK)) +#define UART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_TFRST_MSK)) +#define UART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FCR, UART_FCR_RFRST_MSK)) +#define UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK)) +#define UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_LBEN_MSK)) +#define UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK)) +#define UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCR, UART_MCR_ABREN_MSK)) +#define UART_AUTOBR_RESTART(hperh) (SET_BIT((hperh)->perh->MCR, UART_MCR_ABRRS_MSK)) +#define UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR)) +#define UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS)) +/** + * @} + */ + +/** @defgroup UART_Public_Types UART Public Types + * @{ + */ +/** + * @brief UART word length + */ +typedef enum +{ + UART_WORD_LENGTH_5B = 0x0, /**< 5-bits */ + UART_WORD_LENGTH_6B = 0x1, /**< 6-bits */ + UART_WORD_LENGTH_7B = 0x2, /**< 7-bits */ + UART_WORD_LENGTH_8B = 0x3, /**< 8-bits */ +} uart_word_length_t; + +/** + * @brief UART stop bits + */ +typedef enum +{ + UART_STOP_BITS_1 = 0x0, /**< 1-bits */ + UART_STOP_BITS_2 = 0x1, /**< 2-bits */ + UART_STOP_BITS_0_5 = 0x0, /**< 0.5-bits, using smartcard mode */ + UART_STOP_BITS_1_5 = 0x1, /**< 1.5-bits, using smartcard mode */ +} uart_stop_bits_t; + +/** + * @brief UART parity + */ +typedef enum +{ + UART_PARITY_NONE = 0x0, /**< Not parity */ + UART_PARITY_ODD = 0x1, /**< Odd parity */ + UART_PARITY_EVEN = 0x3, /**< Even parity */ +} uart_parity_t; + +/** + * @brief UART mode + */ +typedef enum +{ + UART_MODE_UART = 0x0, /**< UART */ + UART_MODE_LIN = 0x1, /**< LIN */ + UART_MODE_IrDA = 0x2, /**< IrDA */ + UART_MODE_RS485 = 0x3, /**< RS485 */ + UART_MODE_HDSEL = 0x4, /**< Single-wire half-duplex */ +} uart_mode_t; + +/** + * @brief UART hardware flow control + */ +typedef enum +{ + UART_HW_FLOW_CTL_DISABLE = 0x0, /**< Auto-flow-control disable */ + UART_HW_FLOW_CTL_ENABLE = 0x1, /**< Auto-flow-control enable */ +} uart_hw_flow_ctl_t; + +/** + * @brief ALD UART state + */ +typedef enum +{ + UART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ + UART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + UART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ + UART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ + UART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ + UART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ + UART_STATE_TIMEOUT = 0x03, /**< Timeout state */ + UART_STATE_ERROR = 0x04, /**< Error */ +} uart_state_t; + +/** + * @brief UART error codes + */ +typedef enum +{ + UART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ + UART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ + UART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ + UART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ + UART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ + UART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ +} uart_error_t; + +/** + * @brief UART init structure definition + */ +typedef struct +{ + uint32_t baud; /**< Specifies the uart communication baud rate */ + uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ + uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ + uart_parity_t parity; /**< Specifies the parity mode */ + uart_mode_t mode; /**< Specifies uart mode */ + uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ +} uart_init_t; + +/** + * @brief UART handle structure definition + */ +typedef struct uart_handle_s +{ + UART_TypeDef *perh; /**< UART registers base address */ + uart_init_t init; /**< UART communication parameters */ + uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */ + uint16_t tx_size; /**< UART Tx Transfer size */ + uint16_t tx_count; /**< UART Tx Transfer Counter */ + uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */ + uint16_t rx_size; /**< UART Rx Transfer size */ + uint16_t rx_count; /**< UART Rx Transfer Counter */ +#ifdef ALD_DMA + dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */ + dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */ +#endif + lock_state_t lock; /**< Locking object */ + uart_state_t state; /**< UART communication state */ + uart_error_t err_code; /**< UART Error code */ + + void (*tx_cplt_cbk)(struct uart_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct uart_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct uart_handle_s *arg); /**< error callback */ +} uart_handle_t; + +/** + * @brief UART RS485 configure structure definition + */ +typedef struct +{ + type_func_t normal; /**< Normal mode */ + type_func_t dir; /**< Auto-direction mode */ + type_func_t invert; /**< Address detection invert */ + uint8_t addr; /**< Address for compare */ +} uart_rs485_config_t; + +/** + * @brief LIN detection break length + */ +typedef enum +{ + LIN_BREAK_LEN_10B = 0x0, /**< 10-bit break */ + LIN_BREAK_LEN_11B = 0x1, /**< 11-bit break */ +} uart_lin_break_len_t; + +/** + * @brief UART TXFIFO size + */ +typedef enum +{ + UART_TXFIFO_EMPTY = 0x0, /**< Empty */ + UART_TXFIFO_2BYTE = 0x1, /**< 2-Bytes */ + UART_TXFIFO_4BYTE = 0x2, /**< 4-Bytes */ + UART_TXFIFO_8BYTE = 0x3, /**< 8-Bytes */ +} uart_txfifo_t; + +/** + * @brief UART RXFIFO size + */ +typedef enum +{ + UART_RXFIFO_1BYTE = 0x0, /**< 1-Byte */ + UART_RXFIFO_4BYTE = 0x1, /**< 4-Bytes */ + UART_RXFIFO_8BYTE = 0x2, /**< 8-Bytes */ + UART_RXFIFO_14BYTE = 0x3, /**< 14-Bytes */ +} uart_rxfifo_t; + +/** + * @brief UART auto-baud mode + */ +typedef enum +{ + UART_ABRMOD_1_TO_0 = 0x0, /**< Detect bit0:1, bit1:0 */ + UART_ABRMOD_1 = 0x1, /**< Detect bit0:1 */ + UART_ABRMOD_0_TO_1 = 0x2, /**< Detect bit0:0, bit1:1 */ +} uart_auto_baud_mode_t; + +/** + * @brief UART status types + */ +typedef enum +{ + UART_STATUS_DR = (1U << 0), /**< Data ready */ + UART_STATUS_OE = (1U << 1), /**< Overrun error */ + UART_STATUS_PE = (1U << 2), /**< Parity error */ + UART_STATUS_FE = (1U << 3), /**< Framing error */ + UART_STATUS_BI = (1U << 4), /**< Break interrupt */ + UART_STATUS_TBEM = (1U << 5), /**< Transmit buffer empty */ + UART_STATUS_TEM = (1U << 6), /**< Transmitter empty */ + UART_STATUS_RFE = (1U << 7), /**< Reveiver FIFO data error */ + UART_STATUS_BUSY = (1U << 8), /**< UART busy */ + UART_STATUS_TFNF = (1U << 9), /**< Transmit FIFO not full */ + UART_STATUS_TFEM = (1U << 10), /**< Transmit FIFO not empty */ + UART_STATUS_RFNE = (1U << 11), /**< Receive FIFO not empty */ + UART_STATUS_RFF = (1U << 12), /**< Receive FIFO full */ + UART_STATUS_DCTS = (1U << 14), /**< Delta clear to send */ + UART_STATUS_CTS = (1U << 15), /**< Clear to send */ +} uart_status_t; + +/** + * @brief UART interrupt types + */ +typedef enum +{ + UART_IT_RXRD = (1U << 0), /**< Receive data available */ + UART_IT_TXS = (1U << 1), /**< Tx empty status */ + UART_IT_RXS = (1U << 2), /**< Rx line status */ + UART_IT_MDS = (1U << 3), /**< Modem status */ + UART_IT_RTO = (1U << 4), /**< Receiver timeout */ + UART_IT_BZ = (1U << 5), /**< Busy status */ + UART_IT_ABE = (1U << 6), /**< Auto-baud rate detection end */ + UART_IT_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ + UART_IT_LINBK = (1U << 8), /**< Lin break detection */ + UART_IT_TC = (1U << 9), /**< Transmission complete */ + UART_IT_EOB = (1U << 10), /**< End of block */ + UART_IT_CM = (1U << 11), /**< Character match */ +} uart_it_t; + +/** + * @brief UART flags types + */ +typedef enum +{ + UART_IF_RXRD = (1U << 0), /**< Receive data available */ + UART_IF_TXS = (1U << 1), /**< Tx empty status */ + UART_IF_RXS = (1U << 2), /**< Rx line status */ + UART_IF_MDS = (1U << 3), /**< Modem status */ + UART_IF_RTO = (1U << 4), /**< Receiver timeout */ + UART_IF_BZ = (1U << 5), /**< Busy status */ + UART_IF_ABE = (1U << 6), /**< Auto-baud rate detection end */ + UART_IF_ABTO = (1U << 7), /**< Auto-baud rate detection timeout */ + UART_IF_LINBK = (1U << 8), /**< Lin break detection */ + UART_IF_TC = (1U << 9), /**< Transmission complete */ + UART_IF_EOB = (1U << 10), /**< End of block */ + UART_IF_CM = (1U << 11), /**< Character match */ +} uart_flag_t; +/** + * @} + */ + +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +#define IS_UART_ALL(x) (((x) == UART0) || \ + ((x) == UART1) || \ + ((x) == UART2) || \ + ((x) == UART3)) +#define IS_UART_WORD_LENGTH(x) (((x) == UART_WORD_LENGTH_5B) || \ + ((x) == UART_WORD_LENGTH_6B) || \ + ((x) == UART_WORD_LENGTH_7B) || \ + ((x) == UART_WORD_LENGTH_8B)) +#define IS_UART_STOPBITS(x) (((x) == UART_STOP_BITS_1) || \ + ((x) == UART_STOP_BITS_2) || \ + ((x) == UART_STOP_BITS_0_5) || \ + ((x) == UART_STOP_BITS_1_5)) +#define IS_UART_PARITY(x) (((x) == UART_PARITY_NONE) || \ + ((x) == UART_PARITY_ODD) || \ + ((x) == UART_PARITY_EVEN)) +#define IS_UART_MODE(x) (((x) == UART_MODE_UART) || \ + ((x) == UART_MODE_LIN) || \ + ((x) == UART_MODE_IrDA) || \ + ((x) == UART_MODE_RS485) || \ + ((x) == UART_MODE_HDSEL)) +#define IS_UART_HARDWARE_FLOW_CONTROL(x) \ + (((x) == UART_HW_FLOW_CTL_DISABLE) || \ + ((x) == UART_HW_FLOW_CTL_ENABLE)) +#define IS_UART_LIN_BREAK_LEN(x) (((x) == LIN_BREAK_LEN_10B) || \ + ((x) == LIN_BREAK_LEN_11B)) +#define IS_UART_TXFIFO_TYPE(x) (((x) == UART_TXFIFO_EMPTY) || \ + ((x) == UART_TXFIFO_2BYTE) || \ + ((x) == UART_TXFIFO_4BYTE) || \ + ((x) == UART_TXFIFO_8BYTE)) +#define IS_UART_RXFIFO_TYPE(x) (((x) == UART_RXFIFO_1BYTE) || \ + ((x) == UART_RXFIFO_4BYTE) || \ + ((x) == UART_RXFIFO_8BYTE) || \ + ((x) == UART_RXFIFO_14BYTE)) +#define IS_UART_AUTO_BAUD_MODE(x) (((x) == UART_ABRMOD_1_TO_0) || \ + ((x) == UART_ABRMOD_1) || \ + ((x) == UART_ABRMOD_0_TO_1)) +#define IS_UART_STATUS(x) (((x) == UART_STATUS_DR) || \ + ((x) == UART_STATUS_OE) || \ + ((x) == UART_STATUS_PE) || \ + ((x) == UART_STATUS_FE) || \ + ((x) == UART_STATUS_BI) || \ + ((x) == UART_STATUS_TBEM) || \ + ((x) == UART_STATUS_TEM) || \ + ((x) == UART_STATUS_RFE) || \ + ((x) == UART_STATUS_BUSY) || \ + ((x) == UART_STATUS_TFNF) || \ + ((x) == UART_STATUS_TFEM) || \ + ((x) == UART_STATUS_RFNE) || \ + ((x) == UART_STATUS_RFF) || \ + ((x) == UART_STATUS_DCTS) || \ + ((x) == UART_STATUS_CTS)) +#define IS_UART_IT(x) (((x) == UART_IT_RXRD) || \ + ((x) == UART_IT_TXS) || \ + ((x) == UART_IT_RXS) || \ + ((x) == UART_IT_MDS) || \ + ((x) == UART_IT_RTO) || \ + ((x) == UART_IT_BZ) || \ + ((x) == UART_IT_ABE) || \ + ((x) == UART_IT_ABTO) || \ + ((x) == UART_IT_LINBK) || \ + ((x) == UART_IT_TC) || \ + ((x) == UART_IT_EOB) || \ + ((x) == UART_IT_CM)) +#define IS_UART_IF(x) (((x) == UART_IF_RXRD) || \ + ((x) == UART_IF_TXS) || \ + ((x) == UART_IF_RXS) || \ + ((x) == UART_IF_MDS) || \ + ((x) == UART_IF_RTO) || \ + ((x) == UART_IF_BZ) || \ + ((x) == UART_IF_ABE) || \ + ((x) == UART_IF_ABTO) || \ + ((x) == UART_IF_LINBK) || \ + ((x) == UART_IF_TC) || \ + ((x) == UART_IF_EOB) || \ + ((x) == UART_IF_CM)) +#define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21)) +#define IS_UART_DATA(x) ((x) <= 0x1FF) + +#define UART_STATE_TX_MASK (1U << 4) +#define UART_STATE_RX_MASK (1U << 5) +/** + * @} + */ + +/** @addtogroup UART_Public_Functions + * @{ + */ + +/** @addtogroup UART_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void ald_uart_init(uart_handle_t *hperh); +void ald_uart_reset(uart_handle_t *hperh); +void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); +#ifdef ALD_DMA +ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_uart_dma_pause(uart_handle_t *hperh); +ald_status_t ald_uart_dma_resume(uart_handle_t *hperh); +ald_status_t ald_uart_dma_stop(uart_handle_t *hperh); +#endif +void ald_uart_irq_handler(uart_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group3 + * @{ + */ +/* Peripheral Control functions */ +void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state); +void ald_uart_dma_req_config(uart_handle_t *hperh, type_func_t state); +void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level); +void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level); +void ald_uart_lin_send_break(uart_handle_t *hperh); +void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len); +void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode); +ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout); +it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it); +flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status); +flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag); +flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag); +void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group4 + * @{ + */ +/* Peripheral State and Errors functions */ +uart_state_t ald_uart_get_state(uart_handle_t *hperh); +uint32_t ald_uart_get_error(uart_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_UART_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h similarity index 43% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h index 07aac584f1a16535df2add0a1001ec93bd99d690..62214b2a089d43a973487d3bb104619895f7ce4d 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h @@ -42,8 +42,8 @@ extern "C" { */ typedef enum { - USART_WORD_LENGTH_8B = 0x0, /**< Word length is 8-bits */ - USART_WORD_LENGTH_9B = 0x1, /**< Word length is 9-bits */ + USART_WORD_LENGTH_8B = 0x0, /**< Word length is 8-bits */ + USART_WORD_LENGTH_9B = 0x1, /**< Word length is 9-bits */ } usart_word_length_t; /** @@ -51,10 +51,10 @@ typedef enum */ typedef enum { - USART_STOP_BITS_1 = 0x0, /**< Stop bits is 1-bits */ - USART_STOP_BITS_0_5 = 0x1, /**< Stop bits is 0.5-bits */ - USART_STOP_BITS_2 = 0x2, /**< Stop bits is 2-bits */ - USART_STOP_BITS_1_5 = 0x3, /**< Stop bits is 1.5-bits */ + USART_STOP_BITS_1 = 0x0, /**< Stop bits is 1-bits */ + USART_STOP_BITS_0_5 = 0x1, /**< Stop bits is 0.5-bits */ + USART_STOP_BITS_2 = 0x2, /**< Stop bits is 2-bits */ + USART_STOP_BITS_1_5 = 0x3, /**< Stop bits is 1.5-bits */ } usart_stop_bits_t; /** @@ -62,9 +62,9 @@ typedef enum */ typedef enum { - USART_PARITY_NONE = 0x0, /**< Not parity */ - USART_PARITY_EVEN = 0x2, /**< Even parity */ - USART_PARITY_ODD = 0x3, /**< Odd parity */ + USART_PARITY_NONE = 0x0, /**< Not parity */ + USART_PARITY_EVEN = 0x2, /**< Even parity */ + USART_PARITY_ODD = 0x3, /**< Odd parity */ } usart_parity_t; /** @@ -72,9 +72,9 @@ typedef enum */ typedef enum { - USART_MODE_RX = 0x1, /**< TX mode */ - USART_MODE_TX = 0x2, /**< RX mode */ - USART_MODE_TX_RX = 0x3, /**< TX & RX mode */ + USART_MODE_RX = 0x1, /**< TX mode */ + USART_MODE_TX = 0x2, /**< RX mode */ + USART_MODE_TX_RX = 0x3, /**< TX & RX mode */ } usart_mode_t; /** @@ -82,10 +82,10 @@ typedef enum */ typedef enum { - USART_HW_FLOW_CTL_NONE = 0x0, /**< Not flow control */ - USART_HW_FLOW_CTL_RTS = 0x1, /**< RTS flow control */ - USART_HW_FLOW_CTL_CTS = 0x2, /**< CTS flow control */ - USART_HW_FLOW_CTL_RTS_CTS = 0x3, /**< RTS & CTS flow control */ + USART_HW_FLOW_CTL_NONE = 0x0, /**< Not flow control */ + USART_HW_FLOW_CTL_RTS = 0x1, /**< RTS flow control */ + USART_HW_FLOW_CTL_CTS = 0x2, /**< CTS flow control */ + USART_HW_FLOW_CTL_RTS_CTS = 0x3, /**< RTS & CTS flow control */ } usart_hw_flow_ctl_t; /** @@ -93,8 +93,8 @@ typedef enum */ typedef enum { - USART_CLOCK_DISABLE = 0x0, /**< Disable clock output */ - USART_CLOCK_ENABLE = 0x1, /**< Enable clock output */ + USART_CLOCK_DISABLE = 0x0, /**< Disable clock output */ + USART_CLOCK_ENABLE = 0x1, /**< Enable clock output */ } usart_clock_t; /** @@ -102,8 +102,8 @@ typedef enum */ typedef enum { - USART_CPOL_LOW = 0x0, /**< Clock polarity low */ - USART_CPOL_HIGH = 0x1, /**< Clock polarity high */ + USART_CPOL_LOW = 0x0, /**< Clock polarity low */ + USART_CPOL_HIGH = 0x1, /**< Clock polarity high */ } usart_cpol_t; /** @@ -111,8 +111,8 @@ typedef enum */ typedef enum { - USART_CPHA_1EDGE = 0x0, /**< Clock phase first edge */ - USART_CPHA_2EDGE = 0x1, /**< Clock phase second edge */ + USART_CPHA_1EDGE = 0x0, /**< Clock phase first edge */ + USART_CPHA_2EDGE = 0x1, /**< Clock phase second edge */ } usart_cpha_t; /** @@ -120,8 +120,8 @@ typedef enum */ typedef enum { - USART_LAST_BIT_DISABLE = 0x0, /**< Disable last bit clock output */ - USART_LAST_BIT_ENABLE = 0x1, /**< Enable last bit clock output */ + USART_LAST_BIT_DISABLE = 0x0, /**< Disable last bit clock output */ + USART_LAST_BIT_ENABLE = 0x1, /**< Enable last bit clock output */ } usart_last_bit_t; /** @@ -129,14 +129,14 @@ typedef enum */ typedef enum { - USART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ - USART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - USART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ - USART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ - USART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ - USART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ - USART_STATE_TIMEOUT = 0x03, /**< Timeout state */ - USART_STATE_ERROR = 0x04, /**< Error */ + USART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ + USART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + USART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ + USART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ + USART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ + USART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ + USART_STATE_TIMEOUT = 0x03, /**< Timeout state */ + USART_STATE_ERROR = 0x04, /**< Error */ } usart_state_t; /** @@ -144,12 +144,12 @@ typedef enum */ typedef enum { - USART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ - USART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ - USART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ - USART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ - USART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ - USART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ + USART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ + USART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ + USART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ + USART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ + USART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ + USART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ } usart_error_t; @@ -158,17 +158,17 @@ typedef enum */ typedef struct { - uint32_t baud; /**< This member configures the Usart communication baud rate. */ + uint32_t baud; /**< This member configures the Usart communication baud rate. */ usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */ - usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ - usart_parity_t parity; /**< Specifies the parity mode. - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - usart_mode_t mode; /**< Specifies wether the Receive or Transmit mode is enabled or disabled. */ - usart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled. */ - type_func_t over_sampling; /**< Specifies whether the Over sampling 8 is enabled or disabled. */ + usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */ + usart_parity_t parity; /**< Specifies the parity mode. + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + usart_mode_t mode; /**< Specifies wether the Receive or Transmit mode is enabled or disabled. */ + usart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled. */ + type_func_t over_sampling; /**< Specifies whether the Over sampling 8 is enabled or disabled. */ } usart_init_t; /** @@ -176,26 +176,26 @@ typedef struct */ typedef struct usart_handle_s { - USART_TypeDef *perh; /**< USART registers base address */ - usart_init_t init; /**< USART communication parameters */ - uint8_t *tx_buf; /**< Pointer to USART Tx transfer buffer */ - uint16_t tx_size; /**< USART Tx transfer size */ - uint16_t tx_count; /**< USART Tx transfer counter */ - uint8_t *rx_buf; /**< Pointer to USART Rx transfer buffer */ - uint16_t rx_size; /**< USART Rx Transfer size */ - uint16_t rx_count; /**< USART Rx Transfer Counter */ + USART_TypeDef *perh; /**< USART registers base address */ + usart_init_t init; /**< USART communication parameters */ + uint8_t *tx_buf; /**< Pointer to USART Tx transfer buffer */ + uint16_t tx_size; /**< USART Tx transfer size */ + uint16_t tx_count; /**< USART Tx transfer counter */ + uint8_t *rx_buf; /**< Pointer to USART Rx transfer buffer */ + uint16_t rx_size; /**< USART Rx Transfer size */ + uint16_t rx_count; /**< USART Rx Transfer Counter */ #ifdef ALD_DMA - dma_handle_t hdmatx; /**< USART Tx DMA handle parameters */ - dma_handle_t hdmarx; /**< USART Rx DMA handle parameters */ + dma_handle_t hdmatx; /**< USART Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< USART Rx DMA handle parameters */ #endif - lock_state_t lock; /**< Locking object */ - usart_state_t state; /**< USART communication state */ - uint32_t err_code; /**< USART error code */ - - void (*tx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx completed callback */ - void (*rx_cplt_cbk)(struct usart_handle_s *arg); /**< Rx completed callback */ - void (*tx_rx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx & Rx completed callback */ - void (*error_cbk)(struct usart_handle_s *arg); /**< error callback */ + lock_state_t lock; /**< Locking object */ + usart_state_t state; /**< USART communication state */ + uint32_t err_code; /**< USART error code */ + + void (*tx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct usart_handle_s *arg); /**< Rx completed callback */ + void (*tx_rx_cplt_cbk)(struct usart_handle_s *arg); /**< Tx & Rx completed callback */ + void (*error_cbk)(struct usart_handle_s *arg); /**< error callback */ } usart_handle_t; @@ -204,11 +204,11 @@ typedef struct usart_handle_s */ typedef struct { - usart_clock_t clk; /**< Pecifies whether the USART clock is enable or disable. */ - usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ - usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made. */ - usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. */ + usart_clock_t clk; /**< Pecifies whether the USART clock is enable or disable. */ + usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */ + usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made. */ + usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. */ } usart_clock_init_t; @@ -217,8 +217,8 @@ typedef struct */ typedef enum { - USART_DMA_REQ_TX = (1U << 7), /**< TX dma bit */ - USART_DMA_REQ_RX = (1U << 6), /**< RX dma bit */ + USART_DMA_REQ_TX = (1U << 7), /**< TX dma bit */ + USART_DMA_REQ_RX = (1U << 6), /**< RX dma bit */ } usart_dma_req_t; /** @@ -226,8 +226,8 @@ typedef enum */ typedef enum { - USART_WAKEUP_IDLE = 0x0, /**< Wake up the machine when bus-line is idle */ - USART_WAKEUP_ADDR = 0x1, /**< Wake up the machine when match the address */ + USART_WAKEUP_IDLE = 0x0, /**< Wake up the machine when bus-line is idle */ + USART_WAKEUP_ADDR = 0x1, /**< Wake up the machine when match the address */ } usart_wakeup_t; /** @@ -235,8 +235,8 @@ typedef enum */ typedef enum { - USART_IrDA_MODE_NORMAL = 0x0, /**< Normal IrDA mode */ - USART_IrDA_MODE_LOW_POWER = 0x1, /**< Low-power IrDA mode */ + USART_IrDA_MODE_NORMAL = 0x0, /**< Normal IrDA mode */ + USART_IrDA_MODE_LOW_POWER = 0x1, /**< Low-power IrDA mode */ } usart_IrDA_mode_t; /** @@ -244,16 +244,16 @@ typedef enum */ typedef enum { - USART_IT_PE = ((1U << 8) | (1U << 16)), /**< Parity error */ - USART_IT_TXE = ((1U << 7) | (1U << 16)), /**< Tx empty */ - USART_IT_TC = ((1U << 6) | (1U << 16)), /**< Tx complete */ - USART_IT_RXNE = ((1U << 5) | (1U << 16)), /**< Rx not empty */ - USART_IT_IDLE = ((1U << 4) | (1U << 16)), /**< Idle */ - USART_IT_CTS = ((1U << 10) | (1U << 18)), /**< CTS */ - USART_IT_ERR = ((1U << 0) | (1U << 18)), /**< Error */ - USART_IT_ORE = (1U << 3), /**< Overrun error */ - USART_IT_NE = (1U << 2), /**< Noise error */ - USART_IT_FE = (1U << 0), /**< Frame error */ + USART_IT_PE = ((1U << 8) | (1U << 16)), /**< Parity error */ + USART_IT_TXE = ((1U << 7) | (1U << 16)), /**< Tx empty */ + USART_IT_TC = ((1U << 6) | (1U << 16)), /**< Tx complete */ + USART_IT_RXNE = ((1U << 5) | (1U << 16)), /**< Rx not empty */ + USART_IT_IDLE = ((1U << 4) | (1U << 16)), /**< Idle */ + USART_IT_CTS = ((1U << 10) | (1U << 18)), /**< CTS */ + USART_IT_ERR = ((1U << 0) | (1U << 18)), /**< Error */ + USART_IT_ORE = (1U << 3), /**< Overrun error */ + USART_IT_NE = (1U << 2), /**< Noise error */ + USART_IT_FE = (1U << 0), /**< Frame error */ } usart_it_t; /** @@ -261,15 +261,15 @@ typedef enum */ typedef enum { - USART_FLAG_CTS = (1U << 9), /**< CTS */ - USART_FLAG_TXE = (1U << 7), /**< Tx empty */ - USART_FLAG_TC = (1U << 6), /**< Tx complete */ - USART_FLAG_RXNE = (1U << 5), /**< Rx not empty */ - USART_FLAG_IDLE = (1U << 4), /**< Idle */ - USART_FLAG_ORE = (1U << 3), /**< Overrun error */ - USART_FLAG_NE = (1U << 2), /**< Noise error */ - USART_FLAG_FE = (1U << 1), /**< Frame error */ - USART_FLAG_PE = (1U << 0), /**< Parity error */ + USART_FLAG_CTS = (1U << 9), /**< CTS */ + USART_FLAG_TXE = (1U << 7), /**< Tx empty */ + USART_FLAG_TC = (1U << 6), /**< Tx complete */ + USART_FLAG_RXNE = (1U << 5), /**< Rx not empty */ + USART_FLAG_IDLE = (1U << 4), /**< Idle */ + USART_FLAG_ORE = (1U << 3), /**< Overrun error */ + USART_FLAG_NE = (1U << 2), /**< Noise error */ + USART_FLAG_FE = (1U << 1), /**< Frame error */ + USART_FLAG_PE = (1U << 0), /**< Parity error */ } usart_flag_t; /** @@ -292,13 +292,13 @@ typedef enum /** @defgroup USART_Public_Macros_2 USART clear PE flag * @{ */ -#define USART_CLEAR_PEFLAG(handle) \ -do { \ - __IO uint32_t tmpreg; \ - tmpreg = (handle)->perh->STAT; \ - tmpreg = (handle)->perh->DATA; \ - UNUSED(tmpreg); \ -} while (0) +#define USART_CLEAR_PEFLAG(handle) \ + do { \ + __IO uint32_t tmpreg; \ + tmpreg = (handle)->perh->STAT; \ + tmpreg = (handle)->perh->DATA; \ + UNUSED(tmpreg); \ + } while (0) /** * @} */ @@ -338,7 +338,7 @@ do { \ /** @defgroup USART_Public_Macros_7 USART enable CTS flow control * @{ */ -#define USART_HWCONTROL_CTS_ENABLE(handle) \ +#define USART_HWCONTROL_CTS_ENABLE(handle) \ (SET_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) /** * @} @@ -347,7 +347,7 @@ do { \ /** @defgroup USART_Public_Macros_8 USART disable CTS flow control * @{ */ -#define USART_HWCONTROL_CTS_DISABLE(handle) \ +#define USART_HWCONTROL_CTS_DISABLE(handle) \ (CLEAR_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK)) /** * @} @@ -356,7 +356,7 @@ do { \ /** @defgroup USART_Public_Macros_9 USART enable RTS flow control * @{ */ -#define USART_HWCONTROL_RTS_ENABLE(handle) \ +#define USART_HWCONTROL_RTS_ENABLE(handle) \ (SET_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) /** * @} @@ -365,7 +365,7 @@ do { \ /** @defgroup USART_Public_Macros_10 USART disable RTS flow control * @{ */ -#define USART_HWCONTROL_RTS_DISABLE(handle) \ +#define USART_HWCONTROL_RTS_DISABLE(handle) \ (CLEAR_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK)) /** * @} @@ -374,7 +374,7 @@ do { \ /** @defgroup USART_Public_Macros_11 USART enable * @{ */ -#define USART_ENABLE(handle) (SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) +#define USART_ENABLE(handle) (SET_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) /** * @} */ @@ -382,7 +382,7 @@ do { \ /** @defgroup USART_Public_Macros_12 USART disable * @{ */ -#define USART_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) +#define USART_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK)) /** * @} */ @@ -406,13 +406,13 @@ do { \ ((x) == USART_PARITY_EVEN) || \ ((x) == USART_PARITY_ODD)) #define IS_USART_MODE(x) (((x) == USART_MODE_RX) || \ - ((x) == USART_MODE_TX) || \ - ((x) == USART_MODE_TX_RX)) + ((x) == USART_MODE_TX) || \ + ((x) == USART_MODE_TX_RX)) #define IS_USART_HARDWARE_FLOW_CONTROL(x)\ - (((x) == USART_HW_FLOW_CTL_NONE) || \ - ((x) == USART_HW_FLOW_CTL_RTS) || \ - ((x) == USART_HW_FLOW_CTL_CTS) || \ - ((x) == USART_HW_FLOW_CTL_RTS_CTS)) + (((x) == USART_HW_FLOW_CTL_NONE) || \ + ((x) == USART_HW_FLOW_CTL_RTS) || \ + ((x) == USART_HW_FLOW_CTL_CTS) || \ + ((x) == USART_HW_FLOW_CTL_RTS_CTS)) #define IS_USART_CLOCK(x) (((x) == USART_CLOCK_DISABLE) || \ ((x) == USART_CLOCK_ENABLE)) #define IS_USART_CPOL(x) (((x) == USART_CPOL_LOW) || ((x) == USART_CPOL_HIGH)) @@ -436,7 +436,7 @@ do { \ ((x) == USART_IT_NE) || ((x) == USART_IT_FE) || \ ((x) == USART_IT_ERR)) #define IS_USART_CLEAR_IT(x) (((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \ - ((x) == USART_IT_CTS)) + ((x) == USART_IT_CTS)) #define IS_USART_FLAG(x) (((x) == USART_FLAG_PE) || ((x) == USART_FLAG_TXE) || \ ((x) == USART_FLAG_TC) || ((x) == USART_FLAG_RXNE) || \ @@ -446,12 +446,12 @@ do { \ #define IS_USART_CLEAR_FLAG(x) (((x) == USART_FLAG_CTS) || \ ((x) == USART_FLAG_TC) || \ ((x) == USART_FLAG_RXNE)) -#define IS_USART_BAUDRATE(x) (((x) > 0) && ((x) < 0x0044AA21)) -#define IS_USART_ADDRESS(x) ((x) <= 0xF) -#define IS_USART_DATA(x) ((x) <= 0x1FF) -#define DUMMY_DATA 0xFFFF -#define USART_STATE_TX_MASK (1 << 4) -#define USART_STATE_RX_MASK (1 << 5) +#define IS_USART_BAUDRATE(x) (((x) > 0) && ((x) < 0x0044AA21)) +#define IS_USART_ADDRESS(x) ((x) <= 0xF) +#define IS_USART_DATA(x) ((x) <= 0x1FF) +#define DUMMY_DATA 0xFFFF +#define USART_STATE_TX_MASK (1 << 4) +#define USART_STATE_RX_MASK (1 << 5) /** * @} @@ -465,11 +465,11 @@ do { \ * @{ */ /* Initialization functions */ -void usart_reset(usart_handle_t *hperh); -ald_status_t usart_init(usart_handle_t *hperh); -ald_status_t usart_half_duplex_init(usart_handle_t *hperh); -ald_status_t usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usart_wakeup_t wakeup); -ald_status_t usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init); +void ald_usart_reset(usart_handle_t *hperh); +ald_status_t ald_usart_init(usart_handle_t *hperh); +ald_status_t ald_usart_half_duplex_init(usart_handle_t *hperh); +ald_status_t ald_usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usart_wakeup_t wakeup); +ald_status_t ald_usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init); /** * @} */ @@ -482,14 +482,14 @@ ald_status_t usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init); * @{ */ /* Asynchronization IO operation functions */ -ald_status_t usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size); #ifdef ALD_DMA -ald_status_t usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); #endif /** * @} @@ -499,16 +499,16 @@ ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t siz * @{ */ /* Synchronization IO operation functions */ -ald_status_t usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); -ald_status_t usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); -ald_status_t usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size); -ald_status_t usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size); +ald_status_t ald_usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); +ald_status_t ald_usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size); #ifdef ALD_DMA -ald_status_t usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); -ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); -ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, +ald_status_t ald_usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); +ald_status_t ald_usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); #endif /** @@ -520,11 +520,11 @@ ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, */ /* Utilities functions */ #ifdef ALD_DMA -ald_status_t usart_dma_pause(usart_handle_t *hperh); -ald_status_t usart_dma_resume(usart_handle_t *hperh); -ald_status_t usart_dma_stop(usart_handle_t *hperh); +ald_status_t ald_usart_dma_pause(usart_handle_t *hperh); +ald_status_t ald_usart_dma_resume(usart_handle_t *hperh); +ald_status_t ald_usart_dma_stop(usart_handle_t *hperh); #endif -void usart_irq_handle(usart_handle_t *hperh); +void ald_usart_irq_handler(usart_handle_t *hperh); /** * @} */ @@ -537,15 +537,15 @@ void usart_irq_handle(usart_handle_t *hperh); * @{ */ /* Peripheral control functions */ -ald_status_t usart_multi_processor_enter_mute_mode(usart_handle_t *hperh); -ald_status_t usart_multi_processor_exit_mute_mode(usart_handle_t *hperh); -ald_status_t usart_half_duplex_enable_send(usart_handle_t *hperh); -ald_status_t usart_half_duplex_enable_recv(usart_handle_t *hperh); -void usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_t state); -void usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t state); -flag_status_t usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag); -void usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag); -it_status_t usart_get_it_status(usart_handle_t *hperh, usart_it_t it); +ald_status_t ald_usart_multi_processor_enter_mute_mode(usart_handle_t *hperh); +ald_status_t ald_usart_multi_processor_exit_mute_mode(usart_handle_t *hperh); +ald_status_t ald_usart_half_duplex_enable_send(usart_handle_t *hperh); +ald_status_t ald_usart_half_duplex_enable_recv(usart_handle_t *hperh); +void ald_usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_t state); +void ald_usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t state); +flag_status_t ald_usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag); +void ald_usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag); +it_status_t ald_usart_get_it_status(usart_handle_t *hperh, usart_it_t it); /** * @} */ @@ -555,8 +555,8 @@ it_status_t usart_get_it_status(usart_handle_t *hperh, usart_it_t it); */ /* Peripheral state and error functions */ -usart_state_t usart_get_state(usart_handle_t *hperh); -uint32_t usart_get_error(usart_handle_t *hperh); +usart_state_t ald_usart_get_state(usart_handle_t *hperh); +uint32_t ald_usart_get_error(usart_handle_t *hperh); /** * @} */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h similarity index 66% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h index ee181e3da75d04a882e1a4647c3dd4344df0425a..b2b0e2203ab5cbb3b988f6e8926a3ce60798090f 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h @@ -40,10 +40,10 @@ extern "C" { */ typedef enum { - WWDT_WIN_25 = 0x0, /**< No dog window size: 25% */ - WWDT_WIN_50 = 0x1, /**< No dog window size: 50% */ - WWDT_WIN_75 = 0x2, /**< No dog window size: 75% */ - WWDT_WIN_00 = 0x3, /**< No dog window size: 0% */ + WWDT_WIN_25 = 0x0, /**< No dog window size: 25% */ + WWDT_WIN_50 = 0x1, /**< No dog window size: 50% */ + WWDT_WIN_75 = 0x2, /**< No dog window size: 75% */ + WWDT_WIN_00 = 0x3, /**< No dog window size: 0% */ } wwdt_win_t; /** @@ -71,8 +71,8 @@ typedef enum (x == WWDT_WIN_50) || \ (x == WWDT_WIN_75) || \ (x == WWDT_WIN_00)) -#define IS_FUNC_STATE(x) (((x) == DISABLE) || \ - ((x) == ENABLE)) +#define IS_FUNC_STATE(x) (((x) == DISABLE) || \ + ((x) == ENABLE)) /** * @} */ @@ -80,12 +80,12 @@ typedef enum /** @addtogroup WWDT_Public_Functions * @{ */ -void wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt); -void wwdt_start(void); -uint32_t wwdt_get_value(void); -it_status_t wwdt_get_flag_status(void); -void wwdt_clear_flag_status(void); -void wwdt_feed_dog(void); +void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt); +void ald_wwdt_start(void); +uint32_t ald_wwdt_get_value(void); +it_status_t ald_wwdt_get_flag_status(void); +void ald_wwdt_clear_flag_status(void); +void ald_wwdt_feed_dog(void); /** * @} */ @@ -93,12 +93,12 @@ void wwdt_feed_dog(void); /** @addtogroup IWDT_Public_Functions * @{ */ -void iwdt_init(uint32_t load, type_func_t interrupt); -void iwdt_start(void); -uint32_t iwdt_get_value(void); -it_status_t iwdt_get_flag_status(void); -void iwdt_clear_flag_status(void); -void iwdt_feed_dog(void); +void ald_iwdt_init(uint32_t load, type_func_t interrupt); +void ald_iwdt_start(void); +uint32_t ald_iwdt_get_value(void); +it_status_t ald_iwdt_get_flag_status(void); +void ald_iwdt_clear_flag_status(void); +void ald_iwdt_feed_dog(void); /** * @} */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h similarity index 55% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h index 34303037d93014cbc75655f2914783d4f9547a60..7bf1c1e543558d14b5db019e1cbc96bfef772173 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h @@ -25,11 +25,11 @@ extern "C" { #if defined (__CC_ARM) -#define __INLINE__ __inline -#define __STATIC_INLINE__ static __inline +#define __INLINE__ __inline +#define __STATIC_INLINE__ static __inline #else -#define __INLINE__ inline -#define __STATIC_INLINE__ static inline +#define __INLINE__ inline +#define __STATIC_INLINE__ static inline #endif #define __isr__ @@ -51,7 +51,7 @@ typedef enum DISABLE = 0x0, ENABLE = 0x1, } type_func_t; -#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) +#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) typedef enum { @@ -64,40 +64,40 @@ typedef enum UNLOCK = 0x0, LOCK = 0x1, } lock_state_t; -#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) - - -#define BIT(x) ((1U << (x))) -#define BITS(s, e) ((0xffffffff << (s)) & (0xffffffff >> (31 - (e)))) -#define SET_BIT(reg, bit) ((reg) |= (bit)) -#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit)) -#define READ_BIT(reg, bit) ((reg) & (bit)) -#define READ_BITS(reg, msk, s) (((reg) & (msk)) >> (s)) -#define CLEAR_REG(reg) ((reg) = (0x0)) -#define WRITE_REG(reg, val) ((reg) = (val)) -#define READ_REG(reg) ((reg)) -#define MODIFY_REG(reg, clearmask, setmask) \ +#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) + + +#define BIT(x) ((1U << (x))) +#define BITS(s, e) ((0xffffffff << (s)) & (0xffffffff >> (31 - (e)))) +#define SET_BIT(reg, bit) ((reg) |= (bit)) +#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit)) +#define READ_BIT(reg, bit) ((reg) & (bit)) +#define READ_BITS(reg, msk, s) (((reg) & (msk)) >> (s)) +#define CLEAR_REG(reg) ((reg) = (0x0)) +#define WRITE_REG(reg, val) ((reg) = (val)) +#define READ_REG(reg) ((reg)) +#define MODIFY_REG(reg, clearmask, setmask) \ WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask))) -#define UNUSED(x) ((void)(x)) +#define UNUSED(x) ((void)(x)) #ifdef USE_ASSERT -#define assert_param(x) \ -do { \ - if (!(x)) { \ - __disable_irq(); \ - while (1) \ - ; \ - } \ -} while (0) +#define assert_param(x) \ + do { \ + if (!(x)) { \ + __disable_irq(); \ + while (1) \ + ; \ + } \ + } while (0) #else #define assert_param(x) #endif -#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /* PER base address */ -#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /* RAM base address */ -#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /* Peripheral Address Space bit-band area */ -#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /* SRAM Address Space bit-band area */ +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /* PER base address */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /* RAM base address */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /* Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /* SRAM Address Space bit-band area */ __STATIC_INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val) { @@ -114,10 +114,10 @@ __STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val) #if defined ( __GNUC__ ) #ifndef __weak #define __weak __attribute__((weak)) -#endif /* __weak */ +#endif /* __weak */ #ifndef __packed #define __packed __attribute__((__packed__)) -#endif /* __packed */ +#endif /* __packed */ #endif /* __GNUC__ */ #ifdef __cplusplus diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h similarity index 56% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h index b80d15579004feb1aa1bf356695cb45d19945570..b9041cb62a6ef1903032be1ba0edd4325fd1efa4 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h @@ -59,10 +59,10 @@ typedef enum */ typedef enum { - SYSTICK_INTERVAL_1MS = 1000, /**< Interval is 1ms */ - SYSTICK_INTERVAL_10MS = 100, /**< Interval is 10ms */ - SYSTICK_INTERVAL_100MS = 10, /**< Interval is 100ms */ - SYSTICK_INTERVAL_1000MS = 1, /**< Interval is 1s */ + SYSTICK_INTERVAL_1MS = 1000, /**< Interval is 1ms */ + SYSTICK_INTERVAL_10MS = 100, /**< Interval is 10ms */ + SYSTICK_INTERVAL_100MS = 10, /**< Interval is 100ms */ + SYSTICK_INTERVAL_1000MS = 1, /**< Interval is 1s */ } systick_interval_t; /** * @} @@ -71,24 +71,24 @@ typedef enum /** @defgroup ALD_Public_Macros Public Macros * @{ */ -#define ALD_MAX_DELAY 0xFFFFFFFF - -#define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET) -#define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET) -#define RESET_HANDLE_STATE(x) ((x)->state = 0) -#define __LOCK(x) \ - do { \ - if ((x)->lock == LOCK) { \ - return BUSY; \ - } \ - else { \ - (x)->lock = LOCK; \ - } \ +#define ALD_MAX_DELAY 0xFFFFFFFF + +#define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET) +#define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET) +#define RESET_HANDLE_STATE(x) ((x)->state = 0) +#define __LOCK(x) \ + do { \ + if ((x)->lock == LOCK) { \ + return BUSY; \ + } \ + else { \ + (x)->lock = LOCK; \ + } \ } while (0) -#define __UNLOCK(x) \ - do { \ - (x)->lock = UNLOCK; \ +#define __UNLOCK(x) \ + do { \ + (x)->lock = UNLOCK; \ } while (0) /** @@ -98,8 +98,8 @@ typedef enum /** @defgroup ALD_Private_Macros Private Macros * @{ */ -#define IS_PRIO(x) ((x) < 4) -#define IS_SYSTICK_INTERVAL(x) (((x) == SYSTICK_INTERVAL_1MS) || \ +#define IS_PRIO(x) ((x) < 4) +#define IS_SYSTICK_INTERVAL(x) (((x) == SYSTICK_INTERVAL_1MS) || \ ((x) == SYSTICK_INTERVAL_10MS) || \ ((x) == SYSTICK_INTERVAL_100MS) || \ ((x) == SYSTICK_INTERVAL_1000MS)) @@ -116,9 +116,9 @@ typedef enum */ /* Initialization functions */ -void mcu_ald_init(void); -void __init_tick(uint32_t prio); -void systick_interval_select(systick_interval_t value); +void ald_cmu_init(void); +void ald_tick_init(uint32_t prio); +void ald_systick_interval_select(systick_interval_t value); /** * @} @@ -128,17 +128,18 @@ void systick_interval_select(systick_interval_t value); * @{ */ /* Peripheral Control functions */ -void __inc_tick(void); -void __delay_ms(__IO uint32_t delay); -uint32_t __get_tick(void); -void __suspend_tick(void); -void __resume_tick(void); -void systick_irq_cbk(void); -uint32_t get_ald_version(void); -ald_status_t __wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout); -void mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status); -uint32_t mcu_get_tick(void); -uint32_t mcu_get_cpu_id(void); +void ald_inc_tick_weak(void); +void ald_delay_ms(__IO uint32_t delay); +uint32_t ald_get_tick(void); +void ald_suspend_tick(void); +void ald_resume_tick(void); +void ald_systick_irq_cbk(void); +void ald_inc_tick(void); +uint32_t ald_get_ald_version(void); +ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout); +void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status); +uint32_t ald_mcu_get_tick(void); +uint32_t ald_mcu_get_cpu_id(void); /** * @} diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c similarity index 74% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c index 0ea7a7c0ebbf5cba3b9472230cc6276ecfbef85e..3057d7d2463cd952b6bc0ea6331f4a7d3341b2ef 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c @@ -42,7 +42,7 @@ * the configuration information for the specified ACMP module. * @retval Status, see @ref ald_status_t. */ -ald_status_t acmp_init(acmp_handle_t *hperh) +ald_status_t ald_acmp_init(acmp_handle_t *hperh) { uint32_t tmp = 0; @@ -67,7 +67,7 @@ ald_status_t acmp_init(acmp_handle_t *hperh) tmp = hperh->perh->CON; tmp |= ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) | - (hperh->init.inactval << ACMP_CON_INACTV_POS)); + (hperh->init.inactval << ACMP_CON_INACTV_POS) | (hperh->init.hystsel << ACMP_CON_HYSTSEL_POSS)); hperh->perh->CON = tmp; @@ -85,33 +85,42 @@ ald_status_t acmp_init(acmp_handle_t *hperh) switch (hperh->init.edge) { - case ACMP_EDGE_NONE: - CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; - - case ACMP_EDGE_FALL: - SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; - - case ACMP_EDGE_RISE: - CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; - - case ACMP_EDGE_ALL: - SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); - SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); - break; - - default: - break; + case ACMP_EDGE_NONE: + CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + case ACMP_EDGE_FALL: + SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + case ACMP_EDGE_RISE: + CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + case ACMP_EDGE_ALL: + SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + default: + break; } SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK); - while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0); + tmp = 0; + + while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0) + { + if (tmp++ >= 600000) + { + __UNLOCK(hperh); + return ERROR; + } + } __UNLOCK(hperh); return OK; @@ -136,7 +145,7 @@ ald_status_t acmp_init(acmp_handle_t *hperh) * - DISABLE * @retval Status, see @ref ald_status_t. */ -ald_status_t acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state) +ald_status_t ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state) { assert_param(IS_ACMP_TYPE(hperh->perh)); assert_param(IS_ACMP_IT_TYPE(it)); @@ -154,6 +163,27 @@ ald_status_t acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func return OK; } +/** + * @brief Checks whether the specified ACMP interrupt has set or not. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param it: Specifies the ACMP interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref acmp_it_t. + * @retval it_status_t + * - SET + * - RESET + */ +it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_IT_TYPE(it)); + + if (hperh->perh->IEV & it) + return SET; + else + return RESET; +} + /** * @brief Checks whether the specified ACMP interrupt has occurred or not. * @param hperh: Pointer to a acmp_handle_t structure that contains @@ -164,7 +194,7 @@ ald_status_t acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func * - SET * - RESET */ -it_status_t acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) +it_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) { assert_param(IS_ACMP_TYPE(hperh->perh)); assert_param(IS_ACMP_FLAG_TYPE(flag)); @@ -185,7 +215,7 @@ it_status_t acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) * This parameter can be one of the @ref acmp_it_t. * @retval Status, see @ref ald_status_t. */ -ald_status_t acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) +ald_status_t ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) { assert_param(IS_ACMP_TYPE(hperh->perh)); assert_param(IS_ACMP_FLAG_TYPE(flag)); @@ -225,7 +255,7 @@ ald_status_t acmp_set_it_mask(acmp_handle_t *hperh, acmp_it_t it) * - SET * - RESET */ -flag_status_t acmp_get_status(acmp_handle_t *hperh, acmp_status_t status) +flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status) { assert_param(IS_ACMP_TYPE(hperh->perh)); assert_param(IS_ACMP_STATUS_TYPE(status)); @@ -253,20 +283,22 @@ flag_status_t acmp_get_status(acmp_handle_t *hperh, acmp_status_t status) * the configuration information for the specified ACMP module. * @retval None */ -void acmp_irq_handle(acmp_handle_t *hperh) +void ald_acmp_irq_handler(acmp_handle_t *hperh) { - if (acmp_get_flag_status(hperh, ACMP_FLAG_WARMUP) == SET) + if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_WARMUP) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_WARMUP) == SET)) { if (hperh->acmp_warmup_cplt_cbk) hperh->acmp_warmup_cplt_cbk(hperh); - acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP); + + ald_acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP); } - if (acmp_get_flag_status(hperh, ACMP_FLAG_EDGE) == SET) + if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_EDGE) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_EDGE) == SET)) { if (hperh->acmp_edge_cplt_cbk) hperh->acmp_edge_cplt_cbk(hperh); - acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE); + + ald_acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE); } return; @@ -280,7 +312,7 @@ void acmp_irq_handle(acmp_handle_t *hperh) * the configutation information for acmp output. * @retval Status, see @ref ald_status_t. */ -ald_status_t acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config) +ald_status_t ald_acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config) { if (hperh == NULL) return ERROR; @@ -290,11 +322,9 @@ ald_status_t acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config) assert_param(IS_ACMP_TYPE(hperh->perh)); assert_param(IS_ACMP_INVERT_TYPE(config->gpio_inv)); - assert_param(IS_ACMP_LOCATION_TYPE(config->location)); assert_param(IS_ACMP_OUT_FUNC_TYPE(config->out_func)); __LOCK(hperh); - hperh->perh->PORT = config->location; hperh->perh->CON |= (config->gpio_inv << ACMP_CON_OUTINV_POS); hperh->perh->PORT = config->out_func; __UNLOCK(hperh); @@ -308,7 +338,7 @@ ald_status_t acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config) * the configuration information for the specified ACMP module. * @retval output value. */ -uint8_t acmp_out_result(acmp_handle_t *hperh) +uint8_t ald_acmp_out_result(acmp_handle_t *hperh) { assert_param(IS_ACMP_TYPE(hperh->perh)); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c similarity index 69% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c index 95d707dfdaf61b51adb056e86a4707f45e1e4386..2019e5a948a337a2a9e99769f0f66514bff45faa 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c @@ -71,7 +71,7 @@ * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_init(adc_handle_t *hperh) +ald_status_t ald_adc_init(adc_handle_t *hperh) { ald_status_t tmp_status = OK; @@ -85,20 +85,49 @@ ald_status_t adc_init(adc_handle_t *hperh) assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.neg_ref)); assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.pos_ref)); assert_param(IS_ADC_CONV_RES_TYPE(hperh->init.conv_res)); - assert_param(IS_ADC_NBR_OF_NM_TYPE(hperh->init.conv_nbr)); + assert_param(IS_ADC_NCH_LEN_TYPE(hperh->init.nch_len)); + assert_param(IS_ADC_DISC_MODE_TYPE(hperh->init.disc_mode)); assert_param(IS_ADC_DISC_NBR_TYPE(hperh->init.disc_nbr)); assert_param(IS_FUNC_STATE(hperh->init.cont_mode)); - assert_param(IS_FUNC_STATE(hperh->init.disc_mode)); - assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_mode)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->nm_trig_mode)); + assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_sel)); if (hperh->state == ADC_STATE_RESET) { hperh->error_code = ADC_ERROR_NONE; - hperh->lock = UNLOCK; + hperh->lock = UNLOCK; + } + + if ((hperh->init.pos_ref == ADC_POS_REF_VDD) && (hperh->init.neg_ref == ADC_NEG_REF_VSS)) + { + ADC_ENABLE(hperh); + + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.neg_ref << ADC_CCR_VRNSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.pos_ref << ADC_CCR_VRPSEL_POSS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, 1 << ADC_CCR_VCMBUFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, 1 << ADC_CCR_IREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, 1 << ADC_CCR_VREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, 6 << ADC_CCR_CKDIV_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, ADC_DATAALIGN_RIGHT << ADC_CON1_ALIGN_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, ADC_CONV_RES_12 << ADC_CON0_RSEL_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, DISABLE << ADC_CON1_CM_POS); + MODIFY_REG(hperh->perh->NCHS1, ADC_NCHS1_NS1_MSK, ADC_CHANNEL_18 << ADC_NCHS1_NS1_POSS); + + hperh->perh->SMPT2 = 0x30; + + /* Start adc normal convert */ + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + /* Wait convert finish */ + while (!READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK)); + + hperh->vdd_value = (hperh->perh->NCHDR & 0xfff); + + /* Get calibration VDD value */ + hperh->vdd_value = 2000 * 4096 / hperh->vdd_value; } ADC_DISABLE(hperh); + ald_adc_reset(hperh); hperh->state = ADC_STATE_BUSY_INTERNAL; MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.data_align << ADC_CON1_ALIGN_POS); MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.cont_mode << ADC_CON1_CM_POS); @@ -106,32 +135,28 @@ ald_status_t adc_init(adc_handle_t *hperh) MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.conv_res << ADC_CON0_RSEL_POSS); /* Enable discontinuous mode only if continuous mode is enabled */ - if (hperh->init.disc_mode == ENABLE) + if (hperh->init.disc_mode == ADC_NCH_DISC_EN) { - if (hperh->init.cont_mode == ENABLE) - { - SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); - MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nbr << ADC_CON0_ETRGN_POSS); - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.conv_nbr << ADC_CHSL_NSL_POSS); - } - else - { - hperh->state |= ADC_STATE_ERROR; - hperh->error_code |= ADC_ERROR_INTERNAL; - tmp_status = ERROR; - } + hperh->init.scan_mode = ENABLE; + SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nbr << ADC_CON0_ETRGN_POSS); + } + else if (hperh->init.disc_mode == ADC_ICH_DISC_EN) + { + hperh->init.scan_mode = ENABLE; + SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nbr << ADC_CON0_ETRGN_POSS); } else { CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); } - if (hperh->init.scan_mode == ADC_SCAN_ENABLE) - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.conv_nbr << ADC_CHSL_NSL_POSS); - - if (hperh->init.cont_mode == ENABLE) - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.conv_nbr << ADC_CHSL_NSL_POSS); + if ((hperh->init.scan_mode == ENABLE) || (hperh->init.disc_mode == ADC_NCH_DISC_EN)) + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.nch_len << ADC_CHSL_NSL_POSS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan_mode << ADC_CON0_SCANEN_POS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS); @@ -144,20 +169,17 @@ ald_status_t adc_init(adc_handle_t *hperh) MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.clk_div << ADC_CCR_CKDIV_POSS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.neg_ref << ADC_CCR_VRNSEL_POS); MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.pos_ref << ADC_CCR_VRPSEL_POSS); - MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_mode << ADC_CON1_NCHESEL_POS); - - if (hperh->nm_trig_mode != ADC_TRIG_SOFT) - pis_create(&hperh->reg_pis_handle); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS); if (tmp_status == OK) { hperh->error_code = ADC_ERROR_NONE; - hperh->state |= ADC_STATE_READY; - hperh->state &= ~(ADC_STATE_ERROR | ADC_STATE_NM_BUSY + hperh->state |= ADC_STATE_READY; + hperh->state &= ~(ADC_STATE_ERROR | ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY | ADC_STATE_BUSY_INTERNAL); } - adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE); + ald_adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE); return tmp_status; } @@ -168,7 +190,7 @@ ald_status_t adc_init(adc_handle_t *hperh) * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_reset(adc_handle_t *hperh) +ald_status_t ald_adc_reset(adc_handle_t *hperh) { if (hperh == NULL) return ERROR; @@ -177,12 +199,12 @@ ald_status_t adc_reset(adc_handle_t *hperh) ADC_DISABLE(hperh); - adc_clear_flag_status(hperh, ADC_FLAG_AWD); - adc_clear_flag_status(hperh, ADC_FLAG_NH); - adc_clear_flag_status(hperh, ADC_FLAG_IH); - adc_clear_flag_status(hperh, ADC_FLAG_OVR); - adc_clear_flag_status(hperh, ADC_FLAG_NHS); - adc_clear_flag_status(hperh, ADC_FLAG_IHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_AWD); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_OVR); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); WRITE_REG(hperh->perh->CON0, 0x0); WRITE_REG(hperh->perh->CON1, 0x0); @@ -202,12 +224,6 @@ ald_status_t adc_reset(adc_handle_t *hperh) WRITE_REG(hperh->perh->SMPT2, 0x0); WRITE_REG(hperh->perh->CHSL, 0x0); - if (hperh->nm_trig_mode != ADC_TRIG_SOFT) - pis_destroy(&hperh->reg_pis_handle); - - if (hperh->ist_trig_mode != ADC_TRIG_SOFT) - pis_destroy(&hperh->inj_pis_handle); - hperh->state = ADC_STATE_RESET; hperh->error_code = ADC_ERROR_NONE; return OK; @@ -227,12 +243,11 @@ ald_status_t adc_reset(adc_handle_t *hperh) * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_normal_start(adc_handle_t *hperh) +ald_status_t ald_adc_normal_start(adc_handle_t *hperh) { if (hperh == NULL) return ERROR; - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->nm_trig_mode)); assert_param(IS_ADC_TYPE(hperh->perh)); __LOCK(hperh); @@ -240,10 +255,9 @@ ald_status_t adc_normal_start(adc_handle_t *hperh) hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); hperh->state |= ADC_STATE_NM_BUSY; __UNLOCK(hperh); - adc_clear_flag_status(hperh, ADC_FLAG_NH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); - if (hperh->nm_trig_mode == ADC_TRIG_SOFT) - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); return OK; } @@ -253,14 +267,13 @@ ald_status_t adc_normal_start(adc_handle_t *hperh) * case of auto_injection mode), disable ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on insert group. If insert group is under use, it - * should be preliminarily stopped using adc_insert_stop function. + * should be preliminarily stopped using ald_adc_insert_stop function. * @param hperh: Pointer to a adc_handle_t structure that contains * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_normal_stop(adc_handle_t *hperh) +ald_status_t ald_adc_normal_stop(adc_handle_t *hperh) { - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->nm_trig_mode)); assert_param(IS_ADC_TYPE(hperh->perh)); __LOCK(hperh); @@ -285,18 +298,19 @@ ald_status_t adc_normal_stop(adc_handle_t *hperh) * @param timeout: Timeout value in millisecond. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) +ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) { uint32_t tickstart = 0; assert_param(IS_ADC_TYPE(hperh->perh)); - tickstart = __get_tick(); + tickstart = ald_get_tick(); + while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK))) { if (timeout != ALD_MAX_DELAY) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->state |= ADC_STATE_TIMEOUT; __UNLOCK(hperh); @@ -305,20 +319,19 @@ ald_status_t adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeou } } - adc_clear_flag_status(hperh, ADC_FLAG_NHS); - adc_clear_flag_status(hperh, ADC_FLAG_NH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); hperh->state |= ADC_STATE_NM_EOC; - if ((hperh->nm_trig_mode == ADC_TRIG_SOFT) - && (hperh->init.cont_mode == DISABLE) - && (hperh->init.scan_mode == ADC_SCAN_DISABLE)) + if ((hperh->init.cont_mode == DISABLE) && (hperh->init.scan_mode == DISABLE)) { hperh->state &= ~ADC_STATE_NM_BUSY; if ((hperh->state & ADC_STATE_IST_BUSY) == 0) hperh->state |= ADC_STATE_READY; } + return OK; } @@ -332,20 +345,20 @@ ald_status_t adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeou * @param timeout: Timeout value in millisecond. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout) +ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout) { uint32_t tickstart = 0; assert_param(IS_ADC_TYPE(hperh->perh)); assert_param(IS_ADC_EVENT_TYPE(event_type)); - tickstart = __get_tick(); + tickstart = ald_get_tick(); - while (adc_get_flag_status(hperh, (adc_flag_t)event_type) == RESET) + while (ald_adc_get_flag_status(hperh, (adc_flag_t)event_type) == RESET) { if (timeout != ALD_MAX_DELAY) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->state |= ADC_STATE_TIMEOUT; __UNLOCK(hperh); @@ -367,14 +380,14 @@ ald_status_t adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_normal_start_by_it(adc_handle_t *hperh) +ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); __LOCK(hperh); ADC_ENABLE(hperh); - hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); - hperh->state |= ADC_STATE_NM_BUSY; + hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); + hperh->state |= ADC_STATE_NM_BUSY; hperh->error_code = ADC_ERROR_NONE; if (READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)) @@ -384,11 +397,10 @@ ald_status_t adc_normal_start_by_it(adc_handle_t *hperh) } __UNLOCK(hperh); - adc_clear_flag_status(hperh, ADC_FLAG_NH); - adc_interrupt_config(hperh, ADC_IT_NH, ENABLE); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); + ald_adc_interrupt_config(hperh, ADC_IT_NCH, ENABLE); - if (hperh->nm_trig_mode == ADC_TRIG_SOFT) - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); return OK; } @@ -401,13 +413,13 @@ ald_status_t adc_normal_start_by_it(adc_handle_t *hperh) * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_normal_stop_by_it(adc_handle_t *hperh) +ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); __LOCK(hperh); ADC_DISABLE(hperh); - adc_interrupt_config(hperh, ADC_IT_NH, DISABLE); + ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE); hperh->state |= ADC_STATE_READY; hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); @@ -426,7 +438,7 @@ ald_status_t adc_normal_stop_by_it(adc_handle_t *hperh) * @param channel: The DMA channel * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) { if ((hperh == NULL) || (buf == NULL) || (size == 0) || (channel > 5)) return ERROR; @@ -454,6 +466,7 @@ ald_status_t adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, hperh->state &= ~(ADC_STATE_ERROR); hperh->error_code = ADC_ERROR_NONE; } + __UNLOCK(hperh); if (hperh->hdma.perh == NULL) @@ -464,7 +477,7 @@ ald_status_t adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, hperh->hdma.err_cbk = adc_dma_error; hperh->hdma.err_arg = hperh; - dma_config_struct(&hperh->hdma.config); + ald_dma_config_struct(&hperh->hdma.config); hperh->hdma.config.src = (void *)&hperh->perh->NCHDR; hperh->hdma.config.dst = (void *)buf; hperh->hdma.config.size = size; @@ -474,17 +487,9 @@ ald_status_t adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, hperh->hdma.config.msel = DMA_MSEL_ADC0; hperh->hdma.config.msigsel = DMA_MSIGSEL_ADC; hperh->hdma.config.channel = channel; - dma_config_basic(&hperh->hdma); - - hperh->hpis.init.producer_src = PIS_ADC1_REGULAT; - hperh->hpis.init.producer_clk = PIS_CLK_PCLK2; - hperh->hpis.init.producer_edge = PIS_EDGE_NONE; - hperh->hpis.init.consumer_trig = PIS_CH7_DAC_CH0; - hperh->hpis.init.consumer_clk = PIS_CLK_PCLK1; - pis_create(&hperh->hpis); + ald_dma_config_basic(&hperh->hdma); - if (hperh->nm_trig_mode == ADC_TRIG_SOFT) - SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); return OK; } @@ -503,7 +508,7 @@ ald_status_t adc_stop_dma(adc_handle_t *hperh) __LOCK(hperh); ADC_DISABLE(hperh); - pis_destroy(&hperh->hpis); + ald_pis_destroy(&hperh->hpis); hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); hperh->state |= ADC_STATE_READY; @@ -521,9 +526,10 @@ static void adc_dma_timer_trigger_cplt(void *arg) adc_timer_config_t *hperh = (adc_timer_config_t *)arg; ADC_DISABLE(&hperh->lh_adc); - timer_base_stop(&hperh->lh_timer); + ald_timer_base_stop(&hperh->lh_timer); __UNLOCK(hperh); + if (hperh->lh_adc.adc_reg_cplt_cbk != NULL) hperh->lh_adc.adc_reg_cplt_cbk(&hperh->lh_adc); @@ -536,22 +542,32 @@ static void adc_dma_timer_trigger_cplt(void *arg) * contains the configuration information for the specified function. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) +ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) { __LOCK(config); config->lh_pis.perh = PIS; config->lh_pis.init.producer_clk = PIS_CLK_PCLK1; config->lh_pis.init.producer_edge = PIS_EDGE_NONE; - config->lh_pis.init.consumer_clk = PIS_CLK_PCLK1; + config->lh_pis.init.consumer_clk = PIS_CLK_PCLK2; + +#if defined (ES32F065x) - if (config->p_timer == TIMER0) + if (config->p_timer == AD16C4T0) config->lh_pis.init.producer_src = PIS_TIMER0_UPDATA; - else if (config->p_timer == TIMER1) + +#elif defined(ES32F033x) || defined (ES32F093x) + + if (config->p_timer == GP16C4T0) + config->lh_pis.init.producer_src = PIS_TIMER0_UPDATA; + +#endif + + else if (config->p_timer == BS16T0) config->lh_pis.init.producer_src = PIS_TIMER1_UPDATA; - else if (config->p_timer == TIMER2) + else if (config->p_timer == GP16C2T0) config->lh_pis.init.producer_src = PIS_TIMER2_UPDATA; - else if (config->p_timer == TIMER3) + else if (config->p_timer == GP16C2T1) config->lh_pis.init.producer_src = PIS_TIMER3_UPDATA; else return ERROR; @@ -563,27 +579,27 @@ ald_status_t adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) else return ERROR; - pis_create(&config->lh_pis); + ald_pis_create(&config->lh_pis); /* Initialize TIMER0 */ config->lh_timer.perh = config->p_timer; config->lh_timer.init.prescaler = 0; config->lh_timer.init.mode = TIMER_CNT_MODE_UP; - config->lh_timer.init.period = ((cmu_get_pclk1_clock() / 1000000) * config->time); + config->lh_timer.init.period = ((ald_cmu_get_pclk1_clock() / 1000000) * config->time); config->lh_timer.init.clk_div = TIMER_CLOCK_DIV1; config->lh_timer.init.re_cnt = 0; - timer_base_init(&config->lh_timer); + ald_timer_base_init(&config->lh_timer); config->lh_adc.perh = config->p_adc; config->lh_adc.init.data_align = ADC_DATAALIGN_RIGHT; - config->lh_adc.init.scan_mode = ADC_SCAN_DISABLE; + config->lh_adc.init.scan_mode = DISABLE; config->lh_adc.init.cont_mode = DISABLE; - config->lh_adc.init.conv_nbr = ADC_NM_NBR_1; - config->lh_adc.init.disc_mode = DISABLE; + config->lh_adc.init.nch_len = ADC_NCH_LEN_1; + config->lh_adc.init.disc_mode = ADC_ALL_DISABLE; config->lh_adc.init.disc_nbr = ADC_DISC_NBR_1; config->lh_adc.init.conv_res = ADC_CONV_RES_12; config->lh_adc.init.clk_div = ADC_CKDIV_16; - config->lh_adc.init.nche_mode = ADC_NCHESEL_MODE_ONE; + config->lh_adc.init.nche_sel = ADC_NCHESEL_MODE_ONE; config->lh_adc.init.neg_ref = config->n_ref; config->lh_adc.init.pos_ref = config->p_ref; config->lh_adc.adc_reg_cplt_cbk = config->adc_cplt_cbk; @@ -591,19 +607,19 @@ ald_status_t adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) config->lh_adc.adc_out_of_win_cbk = NULL; config->lh_adc.adc_error_cbk = NULL; config->lh_adc.adc_ovr_cbk = NULL; - adc_init(&config->lh_adc); + ald_adc_init(&config->lh_adc); config->lnm_config.channel = config->adc_ch; - config->lnm_config.rank = ADC_NC_RANK_1; - config->lnm_config.sampling_time = ADC_SAMPLETIME_1; - adc_normal_channel_config(&config->lh_adc, &config->lnm_config); + config->lnm_config.rank = ADC_NCH_RANK_1; + config->lnm_config.samp_time = ADC_SAMPLETIME_1; + ald_adc_normal_channel_config(&config->lh_adc, &config->lnm_config); config->lh_dma.cplt_cbk = adc_dma_timer_trigger_cplt; config->lh_dma.cplt_arg = config; config->lh_dma.err_cbk = adc_dma_error; config->lh_dma.err_arg = &config->lh_adc; - dma_config_struct(&config->lh_dma.config); + ald_dma_config_struct(&config->lh_dma.config); config->lh_dma.perh = DMA0; config->lh_dma.config.src = (void *)&config->lh_adc.perh->NCHDR; config->lh_dma.config.dst = (void *)config->buf; @@ -614,10 +630,10 @@ ald_status_t adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) config->lh_dma.config.msel = config->p_adc == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1; config->lh_dma.config.msigsel = DMA_MSIGSEL_ADC; config->lh_dma.config.channel = config->dma_ch; - dma_config_basic(&config->lh_dma); + ald_dma_config_basic(&config->lh_dma); ADC_ENABLE(&config->lh_adc); - timer_base_start(&config->lh_timer); + ald_timer_base_start(&config->lh_timer); return OK; } @@ -629,7 +645,7 @@ ald_status_t adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) * the configuration information for the specified ADC module. * @retval ADC group normal conversion data */ -uint32_t adc_normal_get_value(adc_handle_t *hperh) +uint32_t ald_adc_normal_get_value(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); @@ -637,6 +653,54 @@ uint32_t adc_normal_get_value(adc_handle_t *hperh) return hperh->perh->NCHDR; } +/** + * @brief The pos reference is VDD and neg reference is VSS, + * get adc normal group result and convert voltage value. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval ADC group normal voltage value,the unit is mV. + */ +uint32_t ald_adc_get_vdd_value(adc_handle_t *hperh) +{ + uint32_t value = 0; + + if ((hperh->init.pos_ref != ADC_POS_REF_VDD) || (hperh->init.neg_ref != ADC_NEG_REF_VSS)) + return 0; + + __LOCK(hperh); + ADC_ENABLE(hperh); + + /* Set adc and measure 2V */ + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, DISABLE << ADC_CCR_VRBUFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFOEN_MSK, DISABLE << ADC_CCR_VREFOEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, ENABLE << ADC_CCR_PWRMODSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, 6 << ADC_CCR_CKDIV_POSS); + MODIFY_REG(hperh->perh->CON0, ADC_CON1_ALIGN_MSK, ADC_DATAALIGN_RIGHT << ADC_CON1_ALIGN_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, ADC_CONV_RES_12 << ADC_CON0_RSEL_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, DISABLE << ADC_CON1_CM_POS); + MODIFY_REG(hperh->perh->NCHS1, ADC_NCHS1_NS1_MSK, ADC_CHANNEL_18 << ADC_NCHS1_NS1_POSS); + + hperh->perh->SMPT2 = 0x30; + /* Start adc normal convert */ + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + /* Wait convert finish */ + while (!READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK)); + + value = (hperh->perh->NCHDR & 0xfff); + /* Get calibration VDD value */ + value = 2000 * 4096 / value; + hperh->vdd_value = value; + + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS); + __UNLOCK(hperh); + + return value; +} + /** * @brief Enables ADC, starts conversion of insert group. * Interruptions enabled in this function: None. @@ -644,10 +708,9 @@ uint32_t adc_normal_get_value(adc_handle_t *hperh) * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_insert_start(adc_handle_t *hperh) +ald_status_t ald_adc_insert_start(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); __LOCK(hperh); ADC_ENABLE(hperh); @@ -658,12 +721,11 @@ ald_status_t adc_insert_start(adc_handle_t *hperh) hperh->error_code = ADC_ERROR_NONE; __UNLOCK(hperh); - adc_clear_flag_status(hperh, ADC_FLAG_IH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) { - if (hperh->ist_trig_mode == ADC_TRIG_SOFT) - SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); } return OK; @@ -673,18 +735,17 @@ ald_status_t adc_insert_start(adc_handle_t *hperh) * @brief Stop conversion of insert channels. Disable ADC peripheral if * no normal conversion is on going. * @note If ADC must be disabled and if conversion is on going on - * normal group, function adc_normal_stop must be used to stop both + * normal group, function ald_adc_normal_stop must be used to stop both * insert and normal groups, and disable the ADC. * @note If insert group mode auto-injection is enabled, - * function adc_normal_stop must be used. + * function ald_adc_normal_stop must be used. * @param hperh: Pointer to a adc_handle_t structure that contains * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_insert_stop(adc_handle_t *hperh) +ald_status_t ald_adc_insert_stop(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); __LOCK(hperh); @@ -713,20 +774,19 @@ ald_status_t adc_insert_stop(adc_handle_t *hperh) * @param timeout: Timeout value in millisecond. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) +ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) { uint32_t tickstart; assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); - tickstart = __get_tick(); + tickstart = ald_get_tick(); while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_ICHE_MSK))) { if (timeout != ALD_MAX_DELAY) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->state |= ADC_STATE_TIMEOUT; __UNLOCK(hperh); @@ -735,18 +795,16 @@ ald_status_t adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeou } } - adc_clear_flag_status(hperh, ADC_FLAG_IHS); - adc_clear_flag_status(hperh, ADC_FLAG_IH); - adc_clear_flag_status(hperh, ADC_FLAG_NH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); hperh->state |= ADC_STATE_IST_EOC; - if (hperh->ist_trig_mode == ADC_TRIG_SOFT) - { - hperh->state &= ~(ADC_STATE_IST_BUSY); - if ((hperh->state & ADC_STATE_NM_BUSY) == 0) - hperh->state |= ADC_STATE_READY; - } + hperh->state &= ~(ADC_STATE_IST_BUSY); + + if ((hperh->state & ADC_STATE_NM_BUSY) == 0) + hperh->state |= ADC_STATE_READY; hperh->state &= ~(ADC_STATE_TIMEOUT); __UNLOCK(hperh); @@ -761,10 +819,9 @@ ald_status_t adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeou * the configuration information for the specified ADC module. * @retval Status, see @ref ald_status_t.. */ -ald_status_t adc_insert_start_by_it(adc_handle_t *hperh) +ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); __LOCK(hperh); ADC_ENABLE(hperh); @@ -775,14 +832,12 @@ ald_status_t adc_insert_start_by_it(adc_handle_t *hperh) hperh->error_code = ADC_ERROR_NONE; __UNLOCK(hperh); - adc_clear_flag_status(hperh, ADC_FLAG_IH); - adc_interrupt_config(hperh, ADC_IT_IH, ENABLE); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, ENABLE); if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) - { - if (hperh->ist_trig_mode == ADC_TRIG_SOFT) - SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); - } + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); + return OK; } @@ -791,18 +846,17 @@ ald_status_t adc_insert_start_by_it(adc_handle_t *hperh) * end-of-conversion. Disable ADC peripheral if no normal conversion * is on going. * @note If ADC must be disabled and if conversion is on going on - * normal group, function adc_normal_stop must be used to stop both + * normal group, function ald_adc_normal_stop must be used to stop both * insert and normal groups, and disable the ADC. * @note If insert group mode auto-injection is enabled, - * function adc_normal_stop must be used. + * function ald_adc_normal_stop must be used. * @param hperh: Pointer to a adc_handle_t structure that contains * the configuration information for the specified ADC module. * @retval None */ -ald_status_t adc_insert_stop_by_it(adc_handle_t *hperh) +ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); __LOCK(hperh); @@ -810,13 +864,13 @@ ald_status_t adc_insert_stop_by_it(adc_handle_t *hperh) && (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))) { ADC_DISABLE(hperh); - adc_interrupt_config(hperh, ADC_IT_IH, DISABLE); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); hperh->state |= ADC_STATE_READY; } else { - adc_interrupt_config(hperh, ADC_IT_IH, DISABLE); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); hperh->state |= ADC_STATE_ERROR; __UNLOCK(hperh); return ERROR; @@ -838,29 +892,33 @@ ald_status_t adc_insert_stop_by_it(adc_handle_t *hperh) * @arg ADC_INJ_RANK_4: insert Channel4 selected * @retval ADC group insert conversion data */ -uint32_t adc_insert_get_value(adc_handle_t *hperh, adc_ih_rank_t ih_rank) +uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_rank_t ih_rank) { uint32_t tmp; assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_IH_RANK_TYPE(ih_rank)); + assert_param(IS_ADC_ICH_RANK_TYPE(ih_rank)); switch (ih_rank) { - case ADC_IH_RANK_1: - tmp = hperh->perh->ICHDR[0]; - break; - case ADC_IH_RANK_2: - tmp = hperh->perh->ICHDR[1]; - break; - case ADC_IH_RANK_3: - tmp = hperh->perh->ICHDR[2]; - break; - case ADC_IH_RANK_4: - tmp = hperh->perh->ICHDR[3]; - break; - default: - break; + case ADC_ICH_RANK_1: + tmp = hperh->perh->ICHDR[0]; + break; + + case ADC_ICH_RANK_2: + tmp = hperh->perh->ICHDR[1]; + break; + + case ADC_ICH_RANK_3: + tmp = hperh->perh->ICHDR[2]; + break; + + case ADC_ICH_RANK_4: + tmp = hperh->perh->ICHDR[3]; + break; + + default: + break; } return tmp; @@ -872,21 +930,18 @@ uint32_t adc_insert_get_value(adc_handle_t *hperh, adc_ih_rank_t ih_rank) * the configuration information for the specified ADC module. * @retval None */ -void adc_irq_handler(adc_handle_t *hperh) +void ald_adc_irq_handler(adc_handle_t *hperh) { assert_param(IS_ADC_TYPE(hperh->perh)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->nm_trig_mode)); - if (adc_get_it_status(hperh, ADC_IT_NH) && adc_get_flag_status(hperh, ADC_FLAG_NH)) + if (ald_adc_get_it_status(hperh, ADC_IT_NCH) && ald_adc_get_flag_status(hperh, ADC_FLAG_NCH)) { if ((hperh->state & ADC_STATE_ERROR) == 0) hperh->state |= ADC_STATE_NM_EOC; - if ((hperh->nm_trig_mode == ADC_TRIG_SOFT) - && (hperh->init.cont_mode == DISABLE)) + if (hperh->init.cont_mode == DISABLE) { - adc_interrupt_config(hperh, ADC_IT_NH, DISABLE); + ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE); hperh->state &= ~(ADC_STATE_NM_BUSY); if ((hperh->state & ADC_STATE_IST_BUSY) == 0) @@ -896,46 +951,45 @@ void adc_irq_handler(adc_handle_t *hperh) if (hperh->adc_reg_cplt_cbk != NULL) hperh->adc_reg_cplt_cbk(hperh); - adc_clear_flag_status(hperh, ADC_FLAG_NHS); - adc_clear_flag_status(hperh, ADC_FLAG_NH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); } - if (adc_get_it_status(hperh, ADC_IT_IH) && adc_get_flag_status(hperh, ADC_FLAG_IH)) + if (ald_adc_get_it_status(hperh, ADC_IT_ICH) && ald_adc_get_flag_status(hperh, ADC_FLAG_ICH)) { if ((hperh->state & ADC_STATE_ERROR) == 0) hperh->state |= ADC_STATE_IST_EOC; - if ((hperh->ist_trig_mode == ADC_TRIG_SOFT) - || ((!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) - && (hperh->nm_trig_mode == ADC_TRIG_SOFT) - && (hperh->init.cont_mode == DISABLE))) + if ((!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + && (hperh->init.cont_mode == DISABLE)) { - adc_interrupt_config(hperh, ADC_IT_IH, DISABLE); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); hperh->state &= ~(ADC_STATE_IST_BUSY); if ((hperh->state & ADC_STATE_NM_BUSY) == 0) hperh->state |= ADC_STATE_READY; } + if (hperh->adc_inj_cplt_cbk != NULL) hperh->adc_inj_cplt_cbk(hperh); - adc_clear_flag_status(hperh, ADC_FLAG_IHS); - adc_clear_flag_status(hperh, ADC_FLAG_IH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); } - if (adc_get_it_status(hperh, ADC_IT_AWD) && adc_get_flag_status(hperh, ADC_FLAG_AWD)) + if (ald_adc_get_it_status(hperh, ADC_IT_AWD) && ald_adc_get_flag_status(hperh, ADC_FLAG_AWD)) { hperh->state |= ADC_STATE_AWD; if (hperh->adc_out_of_win_cbk != NULL) hperh->adc_out_of_win_cbk(hperh); - adc_clear_flag_status(hperh, ADC_FLAG_AWD); + ald_adc_clear_flag_status(hperh, ADC_FLAG_AWD); } - if (adc_get_it_status(hperh, ADC_IT_OVR) && adc_get_flag_status(hperh, ADC_FLAG_OVR)) + if (ald_adc_get_it_status(hperh, ADC_IT_OVR) && ald_adc_get_flag_status(hperh, ADC_FLAG_OVR)) { - adc_clear_flag_status(hperh, ADC_FLAG_OVR); + ald_adc_clear_flag_status(hperh, ADC_FLAG_OVR); hperh->error_code |= ADC_ERROR_OVR; hperh->state |= ADC_STATE_ERROR; @@ -961,26 +1015,26 @@ void adc_irq_handler(adc_handle_t *hperh) * @param config: Structure of ADC channel for normal group. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_normal_channel_config(adc_handle_t *hperh, adc_channel_conf_t *config) +ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config) { assert_param(IS_ADC_TYPE(hperh->perh)); assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); - assert_param(IS_ADC_NC_RANK_TYPE(config->rank)); - assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->sampling_time)); + assert_param(IS_ADC_NCH_RANK_TYPE(config->rank)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp_time)); __LOCK(hperh); - if (config->rank <= ADC_NC_RANK_4) + if (config->rank <= ADC_NCH_RANK_4) { hperh->perh->NCHS1 &= ~(0x1f << ((config->rank - 1) << 3)); hperh->perh->NCHS1 |= (config->channel << ((config->rank - 1) << 3)); } - else if (config->rank <= ADC_NC_RANK_8) + else if (config->rank <= ADC_NCH_RANK_8) { hperh->perh->NCHS2 &= ~(0x1f << ((config->rank - 5) << 3)); hperh->perh->NCHS2 |= (config->channel << ((config->rank - 5) << 3)); } - else if (config->rank <= ADC_NC_RANK_12) + else if (config->rank <= ADC_NCH_RANK_12) { hperh->perh->NCHS3 &= ~(0x1f << ((config->rank - 9) << 3)); hperh->perh->NCHS3 |= (config->channel << ((config->rank - 9) << 3)); @@ -994,12 +1048,12 @@ ald_status_t adc_normal_channel_config(adc_handle_t *hperh, adc_channel_conf_t * if (config->channel <= 15) { hperh->perh->SMPT1 &= ~(0x03 << (config->channel << 1)); - hperh->perh->SMPT1 |= config->sampling_time << (config->channel << 1); + hperh->perh->SMPT1 |= config->samp_time << (config->channel << 1); } else { hperh->perh->SMPT2 &= ~(0x03 << ((config->channel - 16) << 1)); - hperh->perh->SMPT2 |= config->sampling_time << ((config->channel - 16) << 1); + hperh->perh->SMPT2 |= config->samp_time << ((config->channel - 16) << 1); } __UNLOCK(hperh); @@ -1014,51 +1068,53 @@ ald_status_t adc_normal_channel_config(adc_handle_t *hperh, adc_channel_conf_t * * @param config: Structure of ADC channel for insert group. * @retval Status, see @ref ald_status_t. */ -ald_status_t adc_insert_channel_config(adc_handle_t *hperh, adc_ih_conf_t *config) +ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config) { uint8_t tmp1, tmp2; ald_status_t tmp_status = OK; assert_param(IS_ADC_TYPE(hperh->perh)); assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); - assert_param(IS_ADC_IH_RANK_TYPE(config->rank)); + assert_param(IS_ADC_ICH_RANK_TYPE(config->rank)); assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp_time)); assert_param(IS_ADC_IST_OFFSET_TYPE(config->offset)); - assert_param(IS_ADC_NBR_OF_IST_TYPE(config->nbr)); - assert_param(IS_FUNC_STATE(config->disc_mode)); + assert_param(IS_ADC_NBR_OF_IST_TYPE(config->ich_len)); assert_param(IS_FUNC_STATE(config->auto_inj)); - assert_param(IS_ADC_TRIG_MODE_TYPE(hperh->ist_trig_mode)); __LOCK(hperh); - if (hperh->init.scan_mode == ADC_SCAN_DISABLE) + if (hperh->init.scan_mode == DISABLE) { switch (config->rank) { - case ADC_IH_RANK_1: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS1_MSK, config->channel << ADC_ICHS_IS1_POSS); - break; - case ADC_IH_RANK_2: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS2_MSK, config->channel << ADC_ICHS_IS1_POSS); - break; - case ADC_IH_RANK_3: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS3_MSK, config->channel << ADC_ICHS_IS1_POSS); - break; - case ADC_IH_RANK_4: - MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS4_MSK, config->channel << ADC_ICHS_IS1_POSS); - break; - default: - hperh->state |= ADC_STATE_ERROR; - hperh->error_code |= ADC_ERROR_INTERNAL; - tmp_status = ERROR; - break; + case ADC_ICH_RANK_1: + MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS1_MSK, config->channel << ADC_ICHS_IS1_POSS); + break; + + case ADC_ICH_RANK_2: + MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS2_MSK, config->channel << ADC_ICHS_IS2_POSS); + break; + + case ADC_ICH_RANK_3: + MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS3_MSK, config->channel << ADC_ICHS_IS3_POSS); + break; + + case ADC_ICH_RANK_4: + MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS4_MSK, config->channel << ADC_ICHS_IS4_POSS); + break; + + default: + hperh->state |= ADC_STATE_ERROR; + hperh->error_code |= ADC_ERROR_INTERNAL; + tmp_status = ERROR; + break; } } else { - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nbr << ADC_CHSL_ISL_POSS); + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->ich_len << ADC_CHSL_ISL_POSS); tmp1 = config->rank ; - tmp2 = config->nbr; + tmp2 = config->ich_len; if (tmp1 <= tmp2) { @@ -1069,28 +1125,21 @@ ald_status_t adc_insert_channel_config(adc_handle_t *hperh, adc_ih_conf_t *confi else { hperh->perh->ICHS &= ~(0x1f << ((tmp1 - 1) << 3)); + hperh->perh->ICHS |= config->channel + << ((tmp1 - 1) << 3); } } if (config->auto_inj == ENABLE) { - if (hperh->ist_trig_mode == ADC_TRIG_SOFT) - { - SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); - } - else - { - hperh->state |= ADC_STATE_ERROR; - hperh->error_code |= ADC_ERROR_INTERNAL; - tmp_status = ERROR; - } + SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); } - if (config->disc_mode == ENABLE) + if (hperh->init.disc_mode == ADC_ICH_DISC_EN) { if (config->auto_inj == DISABLE) { - MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nbr << ADC_CHSL_ISL_POSS); + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->ich_len << ADC_CHSL_ISL_POSS); SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); } else @@ -1114,24 +1163,25 @@ ald_status_t adc_insert_channel_config(adc_handle_t *hperh, adc_ih_conf_t *confi switch (config->rank) { - case ADC_IH_RANK_1: - hperh->perh->ICHOFF[0] = config->offset; - break; - case ADC_IH_RANK_2: - hperh->perh->ICHOFF[1] = config->offset; - break; - case ADC_IH_RANK_3: - hperh->perh->ICHOFF[2] = config->offset; - break; - case ADC_IH_RANK_4: - hperh->perh->ICHOFF[3] = config->offset; - break; - default: - break; - } + case ADC_ICH_RANK_1: + hperh->perh->ICHOFF[0] = config->offset; + break; - if (hperh->ist_trig_mode != ADC_TRIG_SOFT) - pis_create(&hperh->inj_pis_handle); + case ADC_ICH_RANK_2: + hperh->perh->ICHOFF[1] = config->offset; + break; + + case ADC_ICH_RANK_3: + hperh->perh->ICHOFF[2] = config->offset; + break; + + case ADC_ICH_RANK_4: + hperh->perh->ICHOFF[3] = config->offset; + break; + + default: + break; + } __UNLOCK(hperh); return tmp_status; @@ -1144,7 +1194,7 @@ ald_status_t adc_insert_channel_config(adc_handle_t *hperh, adc_ih_conf_t *confi * @param config: Structure of ADC analog watchdog configuration * @retval ALD status */ -ald_status_t adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config) +ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config) { assert_param(IS_ADC_TYPE(hperh->perh)); @@ -1161,9 +1211,9 @@ ald_status_t adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *c assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); if (config->it_mode == DISABLE) - adc_interrupt_config(hperh, ADC_IT_AWD, DISABLE); + ald_adc_interrupt_config(hperh, ADC_IT_AWD, DISABLE); else - adc_interrupt_config(hperh, ADC_IT_AWD, ENABLE); + ald_adc_interrupt_config(hperh, ADC_IT_AWD, ENABLE); CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHWDTEN_MSK); CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHWDEN_MSK); @@ -1190,7 +1240,7 @@ ald_status_t adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *c * - DISABLE * @retval None */ -void adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state) +void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state) { assert_param(IS_ADC_TYPE(hperh->perh)); assert_param(IS_ADC_IT_TYPE(it)); @@ -1213,7 +1263,7 @@ void adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state) * - SET * - RESET */ -it_status_t adc_get_it_status(adc_handle_t *hperh, adc_it_t it) +it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it) { assert_param(IS_ADC_TYPE(hperh->perh)); assert_param(IS_ADC_IT_TYPE(it)); @@ -1232,7 +1282,7 @@ it_status_t adc_get_it_status(adc_handle_t *hperh, adc_it_t it) * - SET * - RESET */ -flag_status_t adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag) +flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag) { assert_param(IS_ADC_TYPE(hperh->perh)); assert_param(IS_ADC_FLAGS_TYPE(flag)); @@ -1249,7 +1299,7 @@ flag_status_t adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag) * This parameter can be one of the @ref adc_flag_t. * @retval None */ -void adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag) +void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag) { assert_param(IS_ADC_TYPE(hperh->perh)); assert_param(IS_ADC_FLAGS_TYPE(flag)); @@ -1272,7 +1322,7 @@ void adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag) * the configuration information for the specified ADC module. * @retval state */ -uint32_t adc_get_state(adc_handle_t *hperh) +uint32_t ald_adc_get_state(adc_handle_t *hperh) { return hperh->state; } @@ -1283,7 +1333,7 @@ uint32_t adc_get_state(adc_handle_t *hperh) * the configuration information for the specified ADC module. * @retval ADC Error Code */ -uint32_t adc_get_error(adc_handle_t *hperh) +uint32_t ald_adc_get_error(adc_handle_t *hperh) { return hperh->error_code; } diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c similarity index 85% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c index 0a6e766b6aae190bf832b9d59e6574f67d5611b3..7035bc506719ee6d2087ea7f769ff69bc515c95b 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c @@ -40,8 +40,8 @@ ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) bkpc_ldo_config() API can configure LDO in backup field. - (+) bkpc_bor_config() API can configure BOR in backup field. + (+) ald_bkpc_ldo_config() API can configure LDO in backup field. + (+) ald_bkpc_bor_config() API can configure BOR in backup field. @endverbatim * @{ @@ -53,7 +53,7 @@ * @param state: DISABLE/ENABLE. * @retval None */ -void bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state) +void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state) { assert_param(IS_BKPC_LDO_OUTPUT(output)); assert_param(IS_FUNC_STATE(state)); @@ -74,7 +74,7 @@ void bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state) * @param state: DISABLE/ENABLE. * @retval None */ -void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state) +void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state) { assert_param(IS_BKPC_BOR_VOL(vol)); assert_param(IS_FUNC_STATE(state)); @@ -102,8 +102,8 @@ void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state) ##### IO operation functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) bkpc_write_ram() API can write data in backup ram. - (+) bkpc_read_ram() API can read data from backup ram. + (+) ald_bkpc_write_ram() API can write data in backup ram. + (+) ald_bkpc_read_ram() API can read data from backup ram. @endverbatim * @{ @@ -115,7 +115,7 @@ void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state) * @param value: Value which will be written to backup ram. * @retval None */ -void bkpc_write_ram(uint8_t idx, uint32_t value) +void ald_bkpc_write_ram(uint8_t idx, uint32_t value) { assert_param(IS_BKPC_RAM_IDX(idx)); @@ -131,7 +131,7 @@ void bkpc_write_ram(uint8_t idx, uint32_t value) * @param idx: Index of backup word. * @retval The data. */ -uint32_t bkpc_read_ram(uint8_t idx) +uint32_t ald_bkpc_read_ram(uint8_t idx) { assert_param(IS_BKPC_RAM_IDX(idx)); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c similarity index 91% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c index 4ddc9901f9a7ea03496fd00d946f2f5f08e7bc00..26a67f249377d3d27d137bacd4a0af09dd0f10f2 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c @@ -48,9 +48,10 @@ * @param data: The data; * @retval The value of square root. */ -uint32_t calc_sqrt(uint32_t data) +uint32_t ald_calc_sqrt(uint32_t data) { WRITE_REG(CALC->RDCND, data); + while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK)); return READ_REG(CALC->SQRTRES); @@ -63,7 +64,7 @@ uint32_t calc_sqrt(uint32_t data) * @param remainder: The value of the remainder. * @retval The result of division. */ -uint32_t calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder) +uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder) { CLEAR_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); @@ -83,7 +84,7 @@ uint32_t calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder) * @param remainder: The value of the remainder. * @retval The result of division. */ -int32_t calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder) +int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder) { SET_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); @@ -100,7 +101,7 @@ int32_t calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder) * @brief Get the flag of divisor is zero. * @retval The status, SET/RESET. */ -flag_status_t calc_get_dz_status(void) +flag_status_t ald_calc_get_dz_status(void) { if (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_DZ_MSK)) return SET; diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c similarity index 73% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c index cb01604b872918cf9587e7dc2e07dff927bdc65c..cc55f867c5e465bd8c115412c034661e073cde16 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c @@ -24,27 +24,27 @@ (#) CAN pins configuration (++) Enable the clock for the CAN GPIOs; (++) Connect and configure the involved CAN pins using the - following function gpio_init(); - (#) Initialise and configure the CAN using can_init() function. - (#) Transmit the CAN frame using can_send()/can_send_by_it() function. - (#) Receive a CAN frame using can_recv()/can_recv_by_it function. + following function ald_gpio_init(); + (#) Initialise and configure the CAN using ald_can_init() function. + (#) Transmit the CAN frame using ald_can_send()/ald_can_send_by_it() function. + (#) Receive a CAN frame using ald_can_recv()/ald_can_recv_by_it function. *** Polling mode IO operation *** ================================= [..] (+) Start the CAN peripheral transmission and wait the end of this operation - using can_send(), at this stage user can specify the value of timeout + using ald_can_send(), at this stage user can specify the value of timeout according to his end application. (+) Start the CAN peripheral reception and wait the end of this operation - using can_recv(), at this stage user can specify the value of timeout + using ald_can_recv(), at this stage user can specify the value of timeout according to his end application *** Interrupt mode IO operation *** =================================== [..] - (+) Start the CAN peripheral transmission using can_send_by_it() - (+) Start the CAN peripheral reception using can_recv_by_it() - (+) Use can_irq_handler() called under the used CAN Interrupt subroutine + (+) Start the CAN peripheral transmission using ald_can_send_by_it() + (+) Start the CAN peripheral reception using ald_can_recv_by_it() + (+) Use ald_can_irq_handler() called under the used CAN Interrupt subroutine (+) At CAN end of transmission pherh->tx_cplt_cbk() function is executed and user can add his own code by customization of function pointer pherh->tx_cplt_cbk() (+) In case of CAN Error, pherh->rx_cplt_cbk() function is executed and user can @@ -83,7 +83,7 @@ * @{ */ static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num); -static ald_status_t __can_send_by_it(can_handle_t *hperh); +static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err); static ald_status_t __can_recv_by_it(can_handle_t *hperh, uint8_t num); /** * @} @@ -116,7 +116,7 @@ static ald_status_t __can_recv_by_it(can_handle_t *hperh, uint8_t num); * the configuration information for the specified CAN. * @retval Status, see ald_status_t. */ -ald_status_t can_init(can_handle_t *hperh) +ald_status_t ald_can_init(can_handle_t *hperh) { uint32_t tickstart = 0; @@ -137,14 +137,14 @@ ald_status_t can_init(can_handle_t *hperh) hperh->lock = UNLOCK; hperh->state = CAN_STATE_BUSY; - tickstart = __get_tick(); + tickstart = ald_get_tick(); CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); SET_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); while (!READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) { - if ((__get_tick() - tickstart) > CAN_TIMEOUT_VALUE) + if ((ald_get_tick() - tickstart) > CAN_TIMEOUT_VALUE) { hperh->state = CAN_STATE_TIMEOUT; __UNLOCK(hperh); @@ -167,11 +167,11 @@ ald_status_t can_init(can_handle_t *hperh) MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_BPSC_MSK, (hperh->init.psc - 1) << CAN_BTIME_BPSC_POSS); CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); - tickstart = __get_tick(); + tickstart = ald_get_tick(); while (READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) { - if ((__get_tick() - tickstart) > CAN_TIMEOUT_VALUE) + if ((ald_get_tick() - tickstart) > CAN_TIMEOUT_VALUE) { hperh->state = CAN_STATE_TIMEOUT; __UNLOCK(hperh); @@ -194,7 +194,7 @@ ald_status_t can_init(can_handle_t *hperh) * contains the filter configuration information. * @retval Status, see ald_status_t. */ -ald_status_t can_filter_config(can_handle_t *hperh, can_filter_t *config) +ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config) { uint32_t pos; @@ -247,7 +247,7 @@ ald_status_t can_filter_config(can_handle_t *hperh, can_filter_t *config) * @param hperh: pointer to a can_handle_t structure. * @retval None */ -void can_reset(can_handle_t *hperh) +void ald_can_reset(can_handle_t *hperh) { assert_param(IS_CAN_ALL(hperh->perh)); @@ -281,11 +281,11 @@ void can_reset(can_handle_t *hperh) /** * @brief Send a CAN frame message. * @param hperh: pointer to a can_handle_t structure. - * @param msg: message which will be snet. + * @param msg: message which will be sent. * @param timeout: specify Timeout value * @retval Status, see ald_status_t. */ -ald_status_t can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout) +ald_status_t ald_can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout) { uint32_t tick; can_tx_mailbox_t idx; @@ -330,15 +330,16 @@ ald_status_t can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout) MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, ((msg->ext >> 18) & 0x7FF) << CAN_TXID0_STDID_POSS); MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK, (msg->ext & 0x3FFFF) << CAN_TXID0_EXID_POSS); } + MODIFY_REG(hperh->perh->TxMailBox[idx].TXFCON, CAN_TXFCON0_DLEN_MSK, (msg->len & 0xF) << CAN_TXFCON0_DLEN_POSS); WRITE_REG(hperh->perh->TxMailBox[idx].TXDL, msg->data[0] | (msg->data[1] << 8) | (msg->data[2] << 16) | (msg->data[3] << 24)); WRITE_REG(hperh->perh->TxMailBox[idx].TXDH, msg->data[4] | (msg->data[5] << 8) | (msg->data[6] << 16) | (msg->data[7] << 24)); SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); - tick = __get_tick(); + tick = ald_get_tick(); - while (!(can_get_tx_status(hperh, idx))) + while (!(ald_can_get_tx_status(hperh, idx))) { - if ((timeout == 0) || ((__get_tick() - tick) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tick) > timeout)) { hperh->state = CAN_STATE_TIMEOUT; __UNLOCK(hperh); @@ -354,10 +355,10 @@ ald_status_t can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout) /** * @brief Send a CAN frame message using interrupt. * @param hperh: pointer to a can_handle_t structure. - * @param msg: message which will be snet. + * @param msg: message which will be sent. * @retval Status, see ald_status_t. */ -ald_status_t can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg) +ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg) { uint8_t idx = CAN_TX_MAILBOX_NONE; @@ -404,12 +405,12 @@ ald_status_t can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg) SET_BIT(hperh->state, CAN_STATE_TX_MASK); - can_interrupt_config(hperh, CAN_IT_EWG, ENABLE); - can_interrupt_config(hperh, CAN_IT_EPV, ENABLE); - can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); - can_interrupt_config(hperh, CAN_IT_LEC, ENABLE); - can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); - can_interrupt_config(hperh, CAN_IT_TME, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_TXM, ENABLE); SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); return OK; @@ -423,7 +424,7 @@ ald_status_t can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg) * @param timeout: Specify timeout value * @retval Status, see ald_status_t. */ -ald_status_t can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout) +ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout) { uint32_t tick, stid, exid; @@ -432,11 +433,11 @@ ald_status_t can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, __LOCK(hperh); SET_BIT(hperh->state, CAN_STATE_RX_MASK); - tick = __get_tick(); + tick = ald_get_tick(); while (CAN_RX_MSG_PENDING(hperh, num) == 0) { - if ((timeout == 0) || ((__get_tick() - tick) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tick) > timeout)) { hperh->state = CAN_STATE_TIMEOUT; __UNLOCK(hperh); @@ -479,7 +480,7 @@ ald_status_t can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, * @param msg: Storing message. * @retval Status, see ald_status_t. */ -ald_status_t can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg) +ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg) { assert_param(IS_CAN_ALL(hperh->perh)); assert_param(IS_CAN_FIFO(num)); @@ -490,16 +491,16 @@ ald_status_t can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t SET_BIT(hperh->state, CAN_STATE_RX_MASK); hperh->rx_msg = msg; - can_interrupt_config(hperh, CAN_IT_EWG, ENABLE); - can_interrupt_config(hperh, CAN_IT_EPV, ENABLE); - can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); - can_interrupt_config(hperh, CAN_IT_LEC, ENABLE); - can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); if (num == CAN_RX_FIFO0) - can_interrupt_config(hperh, CAN_IT_FMP0, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_FP0, ENABLE); else - can_interrupt_config(hperh, CAN_IT_FMP1, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_FP1, ENABLE); return OK; } @@ -535,7 +536,7 @@ ald_status_t can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t * @param hperh: pointer to a can_handle_t. * @retval Status, see ald_status_t. */ -ald_status_t can_sleep(can_handle_t *hperh) +ald_status_t ald_can_sleep(can_handle_t *hperh) { uint32_t tick; @@ -546,11 +547,11 @@ ald_status_t can_sleep(can_handle_t *hperh) CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); SET_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); - tick = __get_tick(); + tick = ald_get_tick(); while ((!(READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK))) || READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) { - if ((__get_tick() - tick) > CAN_TIMEOUT_VALUE) + if ((ald_get_tick() - tick) > CAN_TIMEOUT_VALUE) { hperh->state = CAN_STATE_TIMEOUT; __UNLOCK(hperh); @@ -570,7 +571,7 @@ ald_status_t can_sleep(can_handle_t *hperh) * @param hperh: pointer to a can_handle_t structure. * @retval Status, see ald_status_t. */ -ald_status_t can_wake_up(can_handle_t *hperh) +ald_status_t ald_can_wake_up(can_handle_t *hperh) { uint32_t tick; @@ -580,11 +581,11 @@ ald_status_t can_wake_up(can_handle_t *hperh) hperh->state = CAN_STATE_BUSY; CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); - tick = __get_tick(); + tick = ald_get_tick(); while (READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK)) { - if ((__get_tick() - tick) > CAN_TIMEOUT_VALUE) + if ((ald_get_tick() - tick) > CAN_TIMEOUT_VALUE) { hperh->state = CAN_STATE_TIMEOUT; __UNLOCK(hperh); @@ -603,71 +604,107 @@ ald_status_t can_wake_up(can_handle_t *hperh) * @param hperh: pointer to a can_handle_t structure. * @retval None */ -void can_irq_handler(can_handle_t *hperh) +void ald_can_irq_handler(can_handle_t *hperh) { - if (can_get_it_status(hperh, CAN_IT_TME)) + if (ald_can_get_it_status(hperh, CAN_IT_TXM)) { - if ((can_get_tx_status(hperh, CAN_TX_MAILBOX_0)) - || (can_get_tx_status(hperh, CAN_TX_MAILBOX_1)) - || (can_get_tx_status(hperh, CAN_TX_MAILBOX_2))) - __can_send_by_it(hperh); + if ((ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_0)) + || (ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_1)) + || (ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_2))) + __can_send_by_it(hperh, 0); + + if (hperh->perh->TXSTAT & CAN_TXSTAT_M0TXERR_MSK) + { + SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M0REQC_MSK); + __can_send_by_it(hperh, 1); + } + + if (hperh->perh->TXSTAT & CAN_TXSTAT_M1TXERR_MSK) + { + SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M1REQC_MSK); + __can_send_by_it(hperh, 1); + } + + if (hperh->perh->TXSTAT & CAN_TXSTAT_M2TXERR_MSK) + { + SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M2REQC_MSK); + __can_send_by_it(hperh, 1); + } } - if ((can_get_it_status(hperh, CAN_IT_FMP0)) + if ((ald_can_get_it_status(hperh, CAN_IT_FP0)) && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO0) != 0)) __can_recv_by_it(hperh, CAN_RX_FIFO0); - if ((can_get_it_status(hperh, CAN_IT_FMP1)) + if ((ald_can_get_it_status(hperh, CAN_IT_FP1)) && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO1) != 0)) __can_recv_by_it(hperh, CAN_RX_FIFO1); - if ((can_get_flag_status(hperh, CAN_FLAG_EWG)) - && (can_get_it_status(hperh, CAN_IT_EWG)) - && (can_get_it_status(hperh, CAN_IT_ERR))) + if ((ald_can_get_flag_status(hperh, CAN_FLAG_WARN)) + && (ald_can_get_it_status(hperh, CAN_IT_WARN)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) hperh->err |= CAN_ERROR_EWG; - if ((can_get_flag_status(hperh, CAN_FLAG_EPV)) - && (can_get_it_status(hperh, CAN_IT_EPV)) - && (can_get_it_status(hperh, CAN_IT_ERR))) + if ((ald_can_get_flag_status(hperh, CAN_FLAG_PERR)) + && (ald_can_get_it_status(hperh, CAN_IT_PERR)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) hperh->err |= CAN_ERROR_EPV; - if ((can_get_flag_status(hperh, CAN_FLAG_BOF)) - && (can_get_it_status(hperh, CAN_IT_BOF)) - && (can_get_it_status(hperh, CAN_IT_ERR))) + if ((ald_can_get_flag_status(hperh, CAN_FLAG_BOF)) + && (ald_can_get_it_status(hperh, CAN_IT_BOF)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) hperh->err |= CAN_ERROR_BOF; if (READ_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK) - && (can_get_it_status(hperh, CAN_IT_LEC)) - && (can_get_it_status(hperh, CAN_IT_ERR))) + && (ald_can_get_it_status(hperh, CAN_IT_PRERR)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) { switch (READ_BITS(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK, CAN_ERRSTAT_PRERRF_POSS)) { - case (1): - hperh->err |= CAN_ERROR_STF; - break; - case (2): - hperh->err |= CAN_ERROR_FOR; - break; - case (3): - hperh->err |= CAN_ERROR_ACK; - break; - case (4): - hperh->err |= CAN_ERROR_BR; - break; - case (5): - hperh->err |= CAN_ERROR_BD; - break; - case (6): - hperh->err |= CAN_ERROR_CRC; - break; - default: - break; + case (1): + hperh->err |= CAN_ERROR_STF; + break; + + case (2): + hperh->err |= CAN_ERROR_FOR; + break; + + case (3): + hperh->err |= CAN_ERROR_ACK; + break; + + case (4): + hperh->err |= CAN_ERROR_BR; + break; + + case (5): + hperh->err |= CAN_ERROR_BD; + break; + + case (6): + hperh->err |= CAN_ERROR_CRC; + break; + + default: + break; } CLEAR_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK); + + if (READ_BIT(hperh->perh->IE, CAN_IE_TXMEIE_MSK)) + ald_can_interrupt_config(hperh, CAN_IT_TXM, DISABLE); + + if (READ_BIT(hperh->perh->IE, CAN_IE_F0PIE_MSK)) + ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE); + + if (READ_BIT(hperh->perh->IE, CAN_IE_F1PIE_MSK)) + ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE); } + if ((ald_can_get_flag_status(hperh, CAN_FLAG_ERR)) && (hperh->err == CAN_ERROR_NONE)) + hperh->err = CAN_ERROR_UNK; + if (hperh->err != CAN_ERROR_NONE) { SET_BIT(hperh->perh->IFC, CAN_IFC_ERRIFC_MSK); @@ -684,45 +721,51 @@ void can_irq_handler(can_handle_t *hperh) * @param box: the index of the mailbox that is used for transmission. * @retval The new status of transmission(TRUE or FALSE). */ -type_bool_t can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box) +type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box) { assert_param(IS_CAN_ALL(hperh->perh)); assert_param(IS_CAN_TX_MAILBOX(box)); switch (box) { - case CAN_TX_MAILBOX_0: - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0REQC_MSK)) - return FALSE; - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0TXC_MSK)) - return FALSE; - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) - return FALSE; - - return TRUE; - - case CAN_TX_MAILBOX_1: - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1REQC_MSK)) - return FALSE; - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1TXC_MSK)) - return FALSE; - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) - return FALSE; - - return TRUE; - - case CAN_TX_MAILBOX_2: - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2REQC_MSK)) - return FALSE; - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2TXC_MSK)) - return FALSE; - if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) - return FALSE; - - return TRUE; - - default: - break; + case CAN_TX_MAILBOX_0: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0REQC_MSK)) + return FALSE; + + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0TXC_MSK)) + return FALSE; + + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) + return FALSE; + + return TRUE; + + case CAN_TX_MAILBOX_1: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1REQC_MSK)) + return FALSE; + + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1TXC_MSK)) + return FALSE; + + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) + return FALSE; + + return TRUE; + + case CAN_TX_MAILBOX_2: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2REQC_MSK)) + return FALSE; + + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2TXC_MSK)) + return FALSE; + + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) + return FALSE; + + return TRUE; + + default: + break; } return FALSE; @@ -734,24 +777,27 @@ type_bool_t can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box) * @param box: the index of the mailbox that is used for transmission. * @retval None */ -void can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box) +void ald_can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box) { assert_param(IS_CAN_ALL(hperh->perh)); assert_param(IS_CAN_TX_MAILBOX(box)); switch (box) { - case CAN_TX_MAILBOX_0: - SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0STPREQ_MSK); - break; - case CAN_TX_MAILBOX_1: - SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1STPREQ_MSK); - break; - case CAN_TX_MAILBOX_2: - SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2STPREQ_MSK); - break; - default: - break; + case CAN_TX_MAILBOX_0: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0STPREQ_MSK); + break; + + case CAN_TX_MAILBOX_1: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1STPREQ_MSK); + break; + + case CAN_TX_MAILBOX_2: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2STPREQ_MSK); + break; + + default: + break; } return; @@ -768,7 +814,7 @@ void can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box) * @arg DISABLE * @retval None */ -void can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state) +void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state) { assert_param(IS_CAN_ALL(hperh->perh)); assert_param(IS_CAN_IT(it)); @@ -791,7 +837,7 @@ void can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state) * - 0: RESET * - 1: SET */ -it_status_t can_get_it_status(can_handle_t *hperh, can_it_t it) +it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it) { assert_param(IS_CAN_ALL(hperh->perh)); assert_param(IS_CAN_IT(it)); @@ -811,7 +857,7 @@ it_status_t can_get_it_status(can_handle_t *hperh, can_it_t it) * - 0: RESET * - 1: SET */ -flag_status_t can_get_flag_status(can_handle_t *hperh, can_flag_t flag) +flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag) { uint32_t idx = (flag >> 20) & 0x7; uint32_t _flag = flag & 0xFF8FFFFF; @@ -820,33 +866,38 @@ flag_status_t can_get_flag_status(can_handle_t *hperh, can_flag_t flag) switch (idx) { - case 0: - if (READ_BIT(hperh->perh->STAT, _flag)) - return SET; - - break; - case 1: - if (READ_BIT(hperh->perh->TXSTAT, _flag)) - return SET; - - break; - case 2: - if (READ_BIT(hperh->perh->RXF0, _flag)) - return SET; - - break; - case 3: - if (READ_BIT(hperh->perh->RXF1, _flag)) - return SET; - - break; - case 4: - if (READ_BIT(hperh->perh->ERRSTAT, _flag)) - return SET; - - break; - default: - break; + case 0: + if (READ_BIT(hperh->perh->STAT, _flag)) + return SET; + + break; + + case 1: + if (READ_BIT(hperh->perh->TXSTAT, _flag)) + return SET; + + break; + + case 2: + if (READ_BIT(hperh->perh->RXF0, _flag)) + return SET; + + break; + + case 3: + if (READ_BIT(hperh->perh->RXF1, _flag)) + return SET; + + break; + + case 4: + if (READ_BIT(hperh->perh->ERRSTAT, _flag)) + return SET; + + break; + + default: + break; } return RESET; @@ -857,7 +908,7 @@ flag_status_t can_get_flag_status(can_handle_t *hperh, can_flag_t flag) * @param flag: specifies the flag to check. * @retval None. */ -void can_clear_flag(can_handle_t *hperh, can_flag_t flag) +void ald_can_clear_flag_status(can_handle_t *hperh, can_flag_t flag) { uint32_t idx = (flag >> 20) & 0x7; uint32_t _flag = flag & 0xFF8FFFFF; @@ -866,20 +917,24 @@ void can_clear_flag(can_handle_t *hperh, can_flag_t flag) switch (idx) { - case 0: - WRITE_REG(hperh->perh->IFC, _flag); - break; - case 1: - WRITE_REG(hperh->perh->TXSTATC, _flag); - break; - case 2: - WRITE_REG(hperh->perh->RXF0C, _flag); - break; - case 3: - WRITE_REG(hperh->perh->RXF1C, _flag); - break; - default: - break; + case 0: + WRITE_REG(hperh->perh->IFC, _flag); + break; + + case 1: + WRITE_REG(hperh->perh->TXSTATC, _flag); + break; + + case 2: + WRITE_REG(hperh->perh->RXF0C, _flag); + break; + + case 3: + WRITE_REG(hperh->perh->RXF1C, _flag); + break; + + default: + break; } return; @@ -908,7 +963,7 @@ void can_clear_flag(can_handle_t *hperh, can_flag_t flag) * @param hperh: pointer to a can_handle_t structure. * @retval Status, see can_state_t. */ -can_state_t can_get_state(can_handle_t *hperh) +can_state_t ald_can_get_state(can_handle_t *hperh) { return hperh->state; } @@ -918,7 +973,7 @@ can_state_t can_get_state(can_handle_t *hperh) * @param hperh: pointer to a can_handle_t structure. * @retval CAN Error Code */ -can_error_t can_get_error(can_handle_t *hperh) +can_error_t ald_can_get_error(can_handle_t *hperh) { return hperh->err; } @@ -953,26 +1008,33 @@ static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num) /** * @brief transmits a CAN frame message using interrupt. * @param hperh: pointer to a can_handle_t structure. + * @param err: Error code, 0 - success, 1 - error. * @retval Status, see ald_status_t. */ -static ald_status_t __can_send_by_it(can_handle_t *hperh) +static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err) { - can_interrupt_config(hperh, CAN_IT_TME, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_TXM, DISABLE); if (hperh->state == CAN_STATE_BUSY_TX) { - can_interrupt_config(hperh, CAN_IT_EWG, DISABLE); - can_interrupt_config(hperh, CAN_IT_EPV, DISABLE); - can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); - can_interrupt_config(hperh, CAN_IT_LEC, DISABLE); - can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); } CLEAR_BIT(hperh->state, CAN_STATE_TX_MASK); - if (hperh->tx_cplt_cbk) + if ((err == 0) && (hperh->tx_cplt_cbk)) hperh->tx_cplt_cbk(hperh); + if ((err) && (hperh->error_cbk != NULL)) + { + hperh->err = CAN_ERROR_UNK; + hperh->error_cbk(hperh); + } + return OK; } @@ -1010,21 +1072,21 @@ static ald_status_t __can_recv_by_it(can_handle_t *hperh, uint8_t num) if (num == CAN_RX_FIFO0) { can_rx_fifo_release(hperh, CAN_RX_FIFO0); - can_interrupt_config(hperh, CAN_IT_FMP0, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE); } else { can_rx_fifo_release(hperh, CAN_RX_FIFO1); - can_interrupt_config(hperh, CAN_IT_FMP1, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE); } if (hperh->state == CAN_STATE_BUSY_RX) { - can_interrupt_config(hperh, CAN_IT_EWG, DISABLE); - can_interrupt_config(hperh, CAN_IT_EPV, DISABLE); - can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); - can_interrupt_config(hperh, CAN_IT_LEC, DISABLE); - can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); } CLEAR_BIT(hperh->state, CAN_STATE_RX_MASK); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c similarity index 71% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c index 88fc71952a31cf7bded0ea0da0aba6efc6387e24..f5a6016d23ce682b856404f17ac3b7f605913c55 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c @@ -20,9 +20,9 @@ *** System clock configure *** ================================= [..] - (+) If you don't change system clock, you can using cmu_clock_config_default() API. + (+) If you don't change system clock, you can using ald_cmu_clock_config_default() API. It will select HRC as system clock. The system clock is 24MHz. - (+) If you want to change system clock, you can using cmu_clock_config() API. + (+) If you want to change system clock, you can using ald_cmu_clock_config() API. You can select one of the following as system clock: @ref CMU_CLOCK_HRC 2MHz or 24MHz @ref CMU_CLOCK_LRC 32768Hz @@ -30,13 +30,13 @@ @ref CMU_CLOCK_PLL1 32MHz, 48MHz or (32768*1024)Hz @ref CMU_CLOCK_HOSC 1MHz -- 24MHz (+) If you select CMU_CLOCK_PLL1 as system clock, it must config the PLL1 - using cmu_pll1_config() API. The input of clock must be 4MHz or PLL2. - (+) If you get current clock, you can using cmu_get_clock() API. + using ald_cmu_pll1_config() API. The input of clock must be 4MHz or PLL2. + (+) If you get system clock, you can using ald_cmu_get_sys_clock() API. *** BUS division control *** =================================== - PLCK sys_clk hclk1 + MCLK sys_clk hclk1 -------DIV_SYS-----------+------DIV_AHB1------------Peripheral(GPIO, CRC, ... etc.) | | pclk1 @@ -46,41 +46,41 @@ +------DIV_APB2------------Peripheral(ADC, WWDT, ... etc.) [..] - (+) Configure the division using cmu_div_config() API. - (+) Get sys_clk using cmu_get_sys_clock() API. - (+) Get hclk1 using cmu_get_hclk1_clock() API. - (+) Get pclk1 using cmu_get_pclk1_clock() API. - (+) Get pclk2 using cmu_get_pclk2_clock() API. + (+) Configure the division using ald_cmu_div_config() API. + (+) Get sys_clk using ald_cmu_get_sys_clock() API. + (+) Get hclk1 using ald_cmu_get_hclk1_clock() API. + (+) Get pclk1 using ald_cmu_get_pclk1_clock() API. + (+) Get pclk2 using ald_cmu_get_pclk2_clock() API. *** Clock safe configure *** =================================== [..] (+) If you select CMU_CLOCK_HOSC as system clock, you need enable - clock safe using cmu_hosc_safe_config() API. It will change + clock safe using ald_cmu_hosc_safe_config() API. It will change CMU_CLOCK_HRC as system clock, when the outer crystal stoped. (+) If you select CMU_CLOCK_LOSC as system clock, you need enable - clock safe using cmu_losc_safe_config() API. It will change + clock safe using ald_cmu_losc_safe_config() API. It will change CMU_CLOCK_LRC as system clock, when the outer crystal stoped. (+) If you select CMU_CLOCK_PLL1 as system clock, you need enable - clock safe using cmu_pll_safe_config() API. It will change + clock safe using ald_cmu_pll_safe_config() API. It will change CMU_CLOCK_HRC as system clock, when the pll1 is lose. - (+) The cmu_irq_cbk() will be invoked, when CMU interrupt has + (+) The ald_cmu_irq_cbk() will be invoked, when CMU interrupt has been occurred. You can overwrite this function in application. *** Clock output configure *** =================================== [..] - (+) Output high-speed clock using cmu_output_high_clock_config() API. - (+) Output low-speed clock using cmu_output_low_clock_config() API. + (+) Output high-speed clock using ald_cmu_output_high_clock_config() API. + (+) Output low-speed clock using ald_cmu_output_low_clock_config() API. *** Peripheral clock configure *** =================================== [..] - (+) Configure buzz clock using cmu_buzz_config() API. - (+) Selected lptim0 clock using cmu_lptim0_clock_select() API. - (+) Selected lpuart clock using cmu_lpuart0_clock_select() API. - (+) Selected lcd clock using cmu_lcd_clock_select() API. - (+) Enable/Disable peripheral clock using cmu_perh_clock_config() API. + (+) Configure buzz clock using ald_cmu_buzz_config() API. + (+) Selected lptim0 clock using ald_cmu_lptim0_clock_select() API. + (+) Selected lpuart clock using ald_cmu_lpuart0_clock_select() API. + (+) Selected lcd clock using ald_cmu_lcd_clock_select() API. + (+) Enable/Disable peripheral clock using ald_cmu_perh_clock_config() API. *** CMU ALD driver macros list *** ============================================= @@ -146,7 +146,7 @@ static void cmu_clock_update(uint32_t clock) __system_clock = clock; if (clock > 1000000) - __init_tick(TICK_INT_PRIORITY); + ald_tick_init(TICK_INT_PRIORITY); return; } @@ -155,7 +155,7 @@ static void cmu_clock_update(uint32_t clock) * @brief CMU module interrupt handler * @retval None */ -void CMU_Handler(void) +void ald_cmu_irq_handler(void) { /* HOSC stop */ if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) @@ -168,7 +168,8 @@ void CMU_Handler(void) && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); - cmu_irq_cbk(CMU_HOSC_STOP); + + ald_cmu_irq_cbk(CMU_HOSC_STOP); } /* HOSC start */ @@ -181,7 +182,8 @@ void CMU_Handler(void) if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))) cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 1000000); - cmu_irq_cbk(CMU_HOSC_START); + + ald_cmu_irq_cbk(CMU_HOSC_START); } /* LOSC stop */ @@ -190,7 +192,7 @@ void CMU_Handler(void) SYSCFG_UNLOCK(); SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); SYSCFG_LOCK(); - cmu_irq_cbk(CMU_LOSC_STOP); + ald_cmu_irq_cbk(CMU_LOSC_STOP); } /* LOSC start */ @@ -199,7 +201,7 @@ void CMU_Handler(void) SYSCFG_UNLOCK(); SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK); SYSCFG_LOCK(); - cmu_irq_cbk(CMU_LOSC_START); + ald_cmu_irq_cbk(CMU_LOSC_START); } /* PLL1 lose */ @@ -213,7 +215,8 @@ void CMU_Handler(void) && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); - cmu_irq_cbk(CMU_PLL1_UNLOCK); + + ald_cmu_irq_cbk(CMU_PLL1_UNLOCK); } return; @@ -249,7 +252,7 @@ void CMU_Handler(void) * enable CMU_CLOCK_LRC(32768Hz). * @retval The status of ALD. */ -ald_status_t cmu_clock_config_default(void) +ald_status_t ald_cmu_clock_config_default(void) { uint32_t cnt = 4000, tmp; @@ -257,6 +260,7 @@ ald_status_t cmu_clock_config_default(void) /* Select HRC */ MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) @@ -265,7 +269,7 @@ ald_status_t cmu_clock_config_default(void) return ERROR; } - CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); /* Select 24Mhz */ + CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); /* Select 24Mhz */ tmp = READ_REG(CMU->CLKENR); /* Enable HRC/LRC/LOSC */ @@ -288,7 +292,7 @@ ald_status_t cmu_clock_config_default(void) * on the parameter of clk. * @retval The status of ALD. */ -ald_status_t cmu_clock_config(cmu_clock_t clk, uint32_t clock) +ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock) { uint32_t cnt = 4000; @@ -297,127 +301,150 @@ ald_status_t cmu_clock_config(cmu_clock_t clk, uint32_t clock) switch (clk) { - case CMU_CLOCK_HRC: - assert_param(clock == 24000000 || clock == 2000000); + case CMU_CLOCK_HRC: + assert_param(clock == 24000000 || clock == 2000000); - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) - { - SYSCFG_LOCK(); - return ERROR; - } + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - if (clock == 24000000) - CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); - else - SET_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) + { + SYSCFG_LOCK(); + return ERROR; + } - SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); + if (clock == 24000000) + CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); + else + SET_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); - for (cnt = 4000; cnt; --cnt); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCACT_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCRDY_MSK))) && (--cnt)); + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); - cmu_clock_update(clock); - break; + for (cnt = 4000; cnt; --cnt); - case CMU_CLOCK_LRC: - /* Close SysTick interrupt in lower clock */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + cnt = 4000; - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCACT_MSK))) && (--cnt)); - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC) - { - SYSCFG_LOCK(); - return ERROR; - } + cnt = 4000; - SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCRDY_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCACT_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt)); + cmu_clock_update(clock); + break; - cmu_clock_update(32768); - break; + case CMU_CLOCK_LRC: + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - case CMU_CLOCK_LOSC: - /* Close SysTick interrupt in lower clock */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS); - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LOSC << CMU_CSR_SYS_CMD_POSS); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC) - { - SYSCFG_LOCK(); - return ERROR; - } + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC) + { + SYSCFG_LOCK(); + return ERROR; + } - SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCACT_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCRDY_MSK))) && (--cnt)); + cnt = 4000; - cmu_clock_update(32768); - break; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCACT_MSK))) && (--cnt)); - case CMU_CLOCK_PLL1: - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + cnt = 4000; - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1) - { - SYSCFG_LOCK(); - return ERROR; - } + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt)); - SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); + cmu_clock_update(32768); + break; - for (cnt = 4000; cnt; --cnt); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1ACT_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); + case CMU_CLOCK_LOSC: + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - cmu_clock_update(clock); - break; + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LOSC << CMU_CSR_SYS_CMD_POSS); - case CMU_CLOCK_HOSC: - assert_param(clock <= 24000000); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); - MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS); - while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC) + { + SYSCFG_LOCK(); + return ERROR; + } - if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC) - { - SYSCFG_LOCK(); - return ERROR; - } + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); - SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); - MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1); + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCRDY_MSK))) && (--cnt)); + + cmu_clock_update(32768); + break; + + case CMU_CLOCK_PLL1: + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS); + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1) + { + SYSCFG_LOCK(); + return ERROR; + } + + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1ACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); + + cmu_clock_update(clock); + break; - for (cnt = 4000; cnt; --cnt); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt)); - cnt = 4000; - while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); + case CMU_CLOCK_HOSC: + assert_param(clock <= 24000000); - cmu_clock_update(clock); - break; + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS); - default: - break; + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC) + { + SYSCFG_LOCK(); + return ERROR; + } + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1); + + for (cnt = 4000; cnt; --cnt); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt)); + + cnt = 4000; + + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); + + cmu_clock_update(clock); + break; + + default: + break; } SYSCFG_LOCK(); @@ -434,7 +461,7 @@ ald_status_t cmu_clock_config(cmu_clock_t clk, uint32_t clock) * CMU_PLL1_OUTPUT_32M, and then the real clock is (32768x1024)Hz. * @retval None */ -void cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output) +void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output) { uint32_t cnt = 4000; @@ -463,7 +490,9 @@ void cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output) SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL1LCKN_MSK)) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); SYSCFG_LOCK(); @@ -471,10 +500,10 @@ void cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output) } /** - * @brief Gets current system clock. - * @retval The value of system clock. + * @brief Gets MCLK clock. + * @retval The value of MCLK clock. */ -uint32_t cmu_get_clock(void) +uint32_t ald_cmu_get_clock(void) { return __system_clock; } @@ -487,7 +516,7 @@ uint32_t cmu_get_clock(void) * - 0 Success * - -1 Failed */ -int32_t cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output_t freq) +int32_t ald_cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output_t freq) { uint32_t cnt = 5000, tmp; @@ -505,7 +534,9 @@ int32_t cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output WRITE_REG(CMU->HRCACR, tmp); while (cnt--); + cnt = 30000; + while ((READ_BIT(CMU->HRCACR, CMU_HRCACR_BUSY_MSK)) && (--cnt)); if (READ_BITS(CMU->HRCACR, CMU_HRCACR_STA_MSK, CMU_HRCACR_STA_POSS) != 1) @@ -534,10 +565,10 @@ int32_t cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output ============================================================================== [..] This section provides functions allowing to: (+) Configure the bus division. - (+) Get ahb1 clock. - (+) Get sys bus clock. - (+) Get apb1 clock. - (+) Get apb2 clock. + (+) Get AHB1 clock. + (+) Get system clock. + (+) Get APB1 clock. + (+) Get APB2 clock. @endverbatim * @{ @@ -553,7 +584,7 @@ int32_t cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output * @param div: The value of divider. * @retval None */ -void cmu_div_config(cmu_bus_t bus, cmu_div_t div) +void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div) { assert_param(IS_CMU_BUS(bus)); assert_param(IS_CMU_DIV(div)); @@ -562,24 +593,35 @@ void cmu_div_config(cmu_bus_t bus, cmu_div_t div) switch (bus) { - case CMU_HCLK_1: - MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS); - break; + case CMU_HCLK_1: + MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS); + break; - case CMU_SYS: - MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); - break; + case CMU_SYS: + MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); - case CMU_PCLK_1: - MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS); - break; + if ((__system_clock >> div) <= 1000000) + { + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + } + else + { + ald_tick_init(TICK_INT_PRIORITY); + } - case CMU_PCLK_2: - MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, div << CMU_CFGR_PCLK2DIV_POSS); - break; + break; + + case CMU_PCLK_1: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS); + break; + + case CMU_PCLK_2: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, div << CMU_CFGR_PCLK2DIV_POSS); + break; - default: - break; + default: + break; } SYSCFG_LOCK(); @@ -590,7 +632,7 @@ void cmu_div_config(cmu_bus_t bus, cmu_div_t div) * @brief Get AHB1 clock. * @retval The value of AHB1 clock. */ -uint32_t cmu_get_hclk1_clock(void) +uint32_t ald_cmu_get_hclk1_clock(void) { uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, CMU_CFGR_HCLK1DIV_POSS); @@ -599,10 +641,10 @@ uint32_t cmu_get_hclk1_clock(void) } /** - * @brief Get SYS clock - * @retval The value of SYS clock + * @brief Get system clock + * @retval The value of system clock */ -uint32_t cmu_get_sys_clock(void) +uint32_t ald_cmu_get_sys_clock(void) { uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); @@ -613,7 +655,7 @@ uint32_t cmu_get_sys_clock(void) * @brief Get APB1 clock. * @retval The value of APB1 clock. */ -uint32_t cmu_get_pclk1_clock(void) +uint32_t ald_cmu_get_pclk1_clock(void) { uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); uint32_t apb1_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, CMU_CFGR_PCLK1DIV_POSS); @@ -625,7 +667,7 @@ uint32_t cmu_get_pclk1_clock(void) * @brief Get APB2 clock. * @retval The value of APB2 clock. */ -uint32_t cmu_get_pclk2_clock(void) +uint32_t ald_cmu_get_pclk2_clock(void) { uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); uint32_t apb2_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, CMU_CFGR_PCLK2DIV_POSS); @@ -659,7 +701,7 @@ uint32_t cmu_get_pclk2_clock(void) * @param status: The new status. * @retval None */ -void cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) +void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) { assert_param(IS_CMU_HOSC_RANGE(clock)); assert_param(IS_FUNC_STATE(status)); @@ -673,7 +715,7 @@ void cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); - mcu_irq_config(CMU_IRQn, 3, ENABLE); + ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); } else { @@ -681,7 +723,7 @@ void cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) - mcu_irq_config(CMU_IRQn, 3, DISABLE); + ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); } SYSCFG_LOCK(); @@ -693,7 +735,7 @@ void cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) * @param status: The new status. * @retval None */ -void cmu_losc_safe_config(type_func_t status) +void ald_cmu_losc_safe_config(type_func_t status) { assert_param(IS_FUNC_STATE(status)); SYSCFG_UNLOCK(); @@ -704,7 +746,7 @@ void cmu_losc_safe_config(type_func_t status) SET_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); - mcu_irq_config(CMU_IRQn, 3, ENABLE); + ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); } else { @@ -712,7 +754,7 @@ void cmu_losc_safe_config(type_func_t status) CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) - mcu_irq_config(CMU_IRQn, 3, DISABLE); + ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); } SYSCFG_LOCK(); @@ -724,7 +766,7 @@ void cmu_losc_safe_config(type_func_t status) * @param status: The new status. * @retval None */ -void cmu_pll_safe_config(type_func_t status) +void ald_cmu_pll_safe_config(type_func_t status) { assert_param(IS_FUNC_STATE(status)); SYSCFG_UNLOCK(); @@ -736,7 +778,7 @@ void cmu_pll_safe_config(type_func_t status) SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); - mcu_irq_config(CMU_IRQn, 3, ENABLE); + ald_mcu_irq_config(CMU_IRQn, 3, ENABLE); } else { @@ -744,7 +786,7 @@ void cmu_pll_safe_config(type_func_t status) CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0) - mcu_irq_config(CMU_IRQn, 3, DISABLE); + ald_mcu_irq_config(CMU_IRQn, 3, DISABLE); } SYSCFG_LOCK(); @@ -756,7 +798,7 @@ void cmu_pll_safe_config(type_func_t status) * @param sr: The state type, see @ref cmu_clock_state_t. * @retval SET/RESET */ -flag_status_t cmu_get_clock_state(cmu_clock_state_t sr) +flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr) { assert_param(IS_CMU_CLOCK_STATE(sr)); @@ -772,7 +814,7 @@ flag_status_t cmu_get_clock_state(cmu_clock_state_t sr) * implementations in user file. * @retval None */ -__weak void cmu_irq_cbk(cmu_security_t se) +__weak void ald_cmu_irq_cbk(cmu_security_t se) { return; } @@ -818,8 +860,8 @@ __weak void cmu_irq_cbk(cmu_security_t se) * @param status: The new status. * @retval None */ -void cmu_output_high_clock_config(cmu_output_high_sel_t sel, - cmu_output_high_div_t div, type_func_t status) +void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, + cmu_output_high_div_t div, type_func_t status) { assert_param(IS_CMU_OUTPUT_HIGH_SEL(sel)); assert_param(IS_CMU_OUTPUT_HIGH_DIV(div)); @@ -853,7 +895,7 @@ void cmu_output_high_clock_config(cmu_output_high_sel_t sel, * @param status: The new status. * @retval None */ -void cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status) +void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status) { assert_param(IS_CMU_OUTPUT_LOW_SEL(sel)); assert_param(IS_FUNC_STATE(status)); @@ -903,7 +945,7 @@ void cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status) * @param status: The new status. * @retval None */ -void cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status) +void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status) { assert_param(IS_CMU_BUZZ_DIV(div)); assert_param(IS_FUNC_STATE(status)); @@ -942,7 +984,7 @@ void cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status) * @arg CMU_LP_PERH_CLOCK_SEL_HOSM * @retval None */ -void cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock) +void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock) { assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); @@ -970,7 +1012,7 @@ void cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock) * @arg CMU_LP_PERH_CLOCK_SEL_HOSM * @retval None */ -void cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock) +void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock) { assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); @@ -992,7 +1034,7 @@ void cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock) * @arg CMU_LCD_SEL_HOSC_1M * @retval None */ -void cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock) +void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock) { assert_param(IS_CMU_LCD_CLOCK_SEL(clock)); @@ -1009,7 +1051,7 @@ void cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock) * @param status: The new status. * @retval None */ -void cmu_perh_clock_config(cmu_perh_t perh, type_func_t status) +void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status) { uint32_t idx, pos; @@ -1044,40 +1086,40 @@ void cmu_perh_clock_config(cmu_perh_t perh, type_func_t status) { switch (idx) { - case 0: - SET_BIT(CMU->AHB1ENR, pos); - break; + case 0: + SET_BIT(CMU->AHB1ENR, pos); + break; - case 1: - SET_BIT(CMU->APB1ENR, pos); - break; + case 1: + SET_BIT(CMU->APB1ENR, pos); + break; - case 2: - SET_BIT(CMU->APB2ENR, pos); - break; + case 2: + SET_BIT(CMU->APB2ENR, pos); + break; - default: - break; + default: + break; } } else { switch (idx) { - case 0: - CLEAR_BIT(CMU->AHB1ENR, pos); - break; + case 0: + CLEAR_BIT(CMU->AHB1ENR, pos); + break; - case 1: - CLEAR_BIT(CMU->APB1ENR, pos); - break; + case 1: + CLEAR_BIT(CMU->APB1ENR, pos); + break; - case 2: - CLEAR_BIT(CMU->APB2ENR, pos); - break; + case 2: + CLEAR_BIT(CMU->APB2ENR, pos); + break; - default: - break; + default: + break; } } diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c similarity index 54% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c index d03a935835fdaedf4b46670023a8771aff2b5fa1..d49b39fe564f2522393158e2de1dbe9be88a49c3 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c @@ -29,7 +29,7 @@ /** @addtogroup CRC_Private_Functions CRC Private Functions * @{ */ -void crc_reset(crc_handle_t *hperh); +void ald_crc_reset(crc_handle_t *hperh); #ifdef ALD_DMA static void crc_dma_calculate_cplt(void *arg); static void crc_dma_error(void *arg); @@ -55,7 +55,7 @@ void crc_reset(crc_handle_t *hperh); * the configuration information for the specified CRC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t crc_init(crc_handle_t *hperh) +ald_status_t ald_crc_init(crc_handle_t *hperh) { uint32_t tmp = 0; @@ -69,7 +69,7 @@ ald_status_t crc_init(crc_handle_t *hperh) assert_param(IS_FUNC_STATE(hperh->init.data_rev)); assert_param(IS_FUNC_STATE(hperh->init.chs_inv)); - crc_reset(hperh); + ald_crc_reset(hperh); __LOCK(hperh); CRC_ENABLE(hperh); @@ -79,7 +79,7 @@ ald_status_t crc_init(crc_handle_t *hperh) tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATREV_POS) | (hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) | (CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) | - (1 << CRC_CR_BYTORD_POS)); + (0 << CRC_CR_BYTORD_POS)); hperh->perh->CR = tmp; hperh->perh->SEED = hperh->init.seed; @@ -101,14 +101,14 @@ ald_status_t crc_init(crc_handle_t *hperh) */ /** - * @brief Calculate the crc value of data. + * @brief Calculate the crc value of data by byte. * @param hperh: Pointer to a crc_handle_t structure that contains * the configuration information for the specified CRC module. * @param buf: Pointer to data buffer * @param size: The size of data to be calculate * @retval result, the result of a amount data */ -uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) +uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) { uint32_t i; uint32_t ret; @@ -119,6 +119,71 @@ uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) return 0; __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); + hperh->state = CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + *((volatile uint8_t *) & (hperh->perh->DATA)) = buf[i]; + + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} + +/** + * @brief Calculate the crc value of data by halfword. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate,width is 2 bytes. + * @retval result, the result of a amount data + */ +uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); + hperh->state = CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + *((volatile uint16_t *) & (hperh->perh->DATA)) = buf[i]; + + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} + +/** + * @brief Calculate the crc value of data by word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate,width is 4 bytes + * @retval result, the result of a amount data + */ +uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); hperh->state = CRC_STATE_BUSY; for (i = 0; i < size; i++) @@ -130,6 +195,7 @@ uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) return ret; } + /** * @} */ @@ -150,7 +216,7 @@ uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) * @param channel: DMA channel as CRC transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel) { if (hperh->state != CRC_STATE_READY) return BUSY; @@ -159,6 +225,7 @@ ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *r return ERROR; __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); hperh->state = CRC_STATE_BUSY; @@ -173,7 +240,7 @@ ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *r hperh->hdma.err_arg = (void *)hperh; hperh->hdma.err_cbk = &crc_dma_error; - dma_config_struct(&(hperh->hdma.config)); + ald_dma_config_struct(&(hperh->hdma.config)); hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE; hperh->hdma.config.src = (void *)buf; hperh->hdma.config.dst = (void *)&hperh->perh->DATA; @@ -183,7 +250,59 @@ ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *r hperh->hdma.config.msel = DMA_MSEL_CRC; hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; hperh->hdma.config.channel = channel; - dma_config_basic(&(hperh->hdma)); + ald_dma_config_basic(&(hperh->hdma)); + + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); + + return OK; +} + +/** + * @brief Calculate an amount of data used dma channel,data width is half-word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to half_word data buffer + * @param res: Pointer to result + * @param size: Amount of half_word data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != CRC_STATE_READY) + return BUSY; + + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); + + hperh->state = CRC_STATE_BUSY; + + hperh->cal_buf = (uint8_t *)buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; + + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; + + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&(hperh->hdma)); __UNLOCK(hperh); CRC_DMA_ENABLE(hperh); @@ -191,13 +310,66 @@ ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *r return OK; } +/** + * @brief Calculate an amount of data used dma channel,data width is word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to word data buffer + * @param res: Pointer to result + * @param size: Amount of word data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != CRC_STATE_READY) + return BUSY; + + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); + + hperh->state = CRC_STATE_BUSY; + + hperh->cal_buf = (uint8_t *)buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; + + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; + + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&(hperh->hdma)); + + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); + + return OK; +} + + /** * @brief Pauses the DMA Transfer. * @param hperh: Pointer to a crc_handle_t structure that contains * the configuration information for the specified CRC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t crc_dma_pause(crc_handle_t *hperh) +ald_status_t ald_crc_dma_pause(crc_handle_t *hperh) { __LOCK(hperh); CRC_DMA_DISABLE(hperh); @@ -212,7 +384,7 @@ ald_status_t crc_dma_pause(crc_handle_t *hperh) * the configuration information for the specified CRC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t crc_dma_resume(crc_handle_t *hperh) +ald_status_t ald_crc_dma_resume(crc_handle_t *hperh) { __LOCK(hperh); CRC_DMA_ENABLE(hperh); @@ -227,7 +399,7 @@ ald_status_t crc_dma_resume(crc_handle_t *hperh) * the configuration information for the specified CRC module. * @retval Status, see @ref ald_status_t. */ -ald_status_t crc_dma_stop(crc_handle_t *hperh) +ald_status_t ald_crc_dma_stop(crc_handle_t *hperh) { __LOCK(hperh); CRC_DMA_DISABLE(hperh); @@ -253,7 +425,7 @@ ald_status_t crc_dma_stop(crc_handle_t *hperh) * the configuration information for the specified CRC module. * @retval CRC state */ -crc_state_t crc_get_state(crc_handle_t *hperh) +crc_state_t ald_crc_get_state(crc_handle_t *hperh) { assert_param(IS_CRC(hperh->perh)); @@ -278,7 +450,7 @@ crc_state_t crc_get_state(crc_handle_t *hperh) * the configuration information for the specified CRC module. * @retval None */ -void crc_reset(crc_handle_t *hperh) +void ald_crc_reset(crc_handle_t *hperh) { hperh->perh->DATA = 0x0; hperh->perh->CR = 0x2; @@ -331,11 +503,11 @@ static void crc_dma_error(void *arg) /** * @} */ +#endif /* ALD_CRC */ /** * @} */ -#endif /* ALD_CRC */ /** * @} diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c similarity index 88% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c index 4cf2f6e5a9f135b041be20d4486dc90cb2814303..30d7f1e3ef8e6d1aed5f9e25f2ed997384684955 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c @@ -3,7 +3,7 @@ * * @file ald_crypt.c * @brief CRYPT module driver. - * This is the common part of the CRYPT initialization + * This is the common part of the CRYPT initialization * * @version V1.0 * @date 7 Dec 2017 @@ -58,7 +58,7 @@ void crypt_reset(crypt_handle_t *hperh); * the configuration information for the specified CRYPT module. * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_init(crypt_handle_t *hperh) +ald_status_t ald_crypt_init(crypt_handle_t *hperh) { uint32_t tmp = 0; @@ -92,7 +92,7 @@ ald_status_t crypt_init(crypt_handle_t *hperh) * @param key: Pointer to key data buffer * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_write_key(crypt_handle_t *hperh, uint32_t *key) +ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t *key) { uint32_t *temp = key; uint32_t i; @@ -123,7 +123,7 @@ ald_status_t crypt_write_key(crypt_handle_t *hperh, uint32_t *key) * @param key: The pointer to the key * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_read_key(crypt_handle_t *hperh, uint32_t *key) +ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t *key) { uint32_t *temp = key; @@ -150,10 +150,11 @@ ald_status_t crypt_read_key(crypt_handle_t *hperh, uint32_t *key) * @param iv: Pointer to iv data buffer * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv) +ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv) { uint32_t *temp = iv; uint32_t i; + if (hperh->state == CRYPT_STATE_BUSY) return BUSY; @@ -181,7 +182,7 @@ ald_status_t crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv) * @param iv: Pointer to iv data buffer * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv) +ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv) { uint32_t *temp = iv; @@ -220,7 +221,7 @@ ald_status_t crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv) * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size) +ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size) { uint32_t count = 0; uint32_t i; @@ -248,7 +249,7 @@ ald_status_t crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t * plain_buf++; } - while (crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); + while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); for (i = 0; i < hperh->step; i++) { @@ -273,7 +274,7 @@ ald_status_t crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t * * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) +ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) { uint32_t count = 0; uint32_t i; @@ -282,7 +283,7 @@ ald_status_t crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t if (hperh->init.mode == CRYPT_MODE_CTR) { - return crypt_encrypt(hperh, cipher_text, plain_text, size); + return ald_crypt_encrypt(hperh, cipher_text, plain_text, size); } if (hperh->state != CRYPT_STATE_READY) @@ -306,7 +307,7 @@ ald_status_t crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t cipher_buf++; } - while (crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); + while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); for (i = 0; i < hperh->step; i++) { @@ -357,7 +358,7 @@ void gcm_mul(uint32_t *res, uint32_t *data, uint32_t *iv) * @param tag: Pointer to authentication tag buffer * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag) +ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag) { uint8_t GCM_HASH_in[0x60] = {0}; uint8_t ecb[16] = {0}; @@ -376,53 +377,65 @@ ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint3 { GCM_HASH_in [i] = * (aadata + i); } + len += alen; + for (i = 0; i < v / 8; i++) { GCM_HASH_in[i + len] = 0; } + len += v / 8; + for (i = 0; i < size; i++) { GCM_HASH_in[i + len] = * (cipher_text + i); } + len += size; + for (i = 0; i < u / 8; i++) { GCM_HASH_in[i + len] = 0; } + len += u / 8; for (i = 0; i < 4; i++) { GCM_HASH_in[i + len] = 0; } + len += 4; for (i = 0; i < 4; i++) { GCM_HASH_in[i + len] = ((alen * 8) >> (8 * i)) & 0xFF; } + len += 4; for (i = 0; i < 4; i++) { GCM_HASH_in[i + len] = 0; } + len += 4; for (i = 0; i < 4; i++) { GCM_HASH_in[i + len] = ((size * 8) >> (8 * i)) & 0xFF; } + len += 4; CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS); CRYPT->CON |= (CRYPT_MODE_ECB << CRYPT_CON_MODE_POSS); - crypt_encrypt(hperh, ecb, ecb, 16); + ald_crypt_encrypt(hperh, ecb, ecb, 16); k = len / 16; + for (i = 0; i < 16; i++) { tag[i] = 0; @@ -430,6 +443,7 @@ ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint3 cipher_text_temp = (uint32_t *)GCM_HASH_in; tag_temp = (uint32_t *)tag; + for (i = 0; i < k; i++) { for (j = 0; j < 4; j++) @@ -445,13 +459,13 @@ ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint3 * T = CIPH_K(J0)^S,J0=IV||0^31||1,CIPH_K is the algorithm of AES in ECB mode */ tag_temp = (uint32_t *)tag; - crypt_init(hperh); + ald_crypt_init(hperh); CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS); CRYPT->CON |= (CRYPT_MODE_CTR << CRYPT_CON_MODE_POSS); - crypt_write_key(hperh, hperh->key); + ald_crypt_write_key(hperh, hperh->key); hperh->iv[3] = 1; - crypt_write_ivr(hperh, hperh->iv); - crypt_encrypt(hperh, tag, tag, 16); + ald_crypt_write_ivr(hperh, hperh->iv); + ald_crypt_encrypt(hperh, tag, tag, 16); return OK; } @@ -466,7 +480,7 @@ ald_status_t crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint3 * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size) +ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size) { uint32_t i; uint32_t *plain_buf = (uint32_t *)plain_text; @@ -486,7 +500,7 @@ ald_status_t crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uin hperh->plain_text = plain_text; hperh->cipher_text = cipher_text; hperh->size = size; - crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); + ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); for (i = 0; i < hperh->step; i++) { @@ -508,14 +522,14 @@ ald_status_t crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uin * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) +ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) { uint32_t i; uint32_t *cipher_buf = (uint32_t *)cipher_text; if (hperh->init.mode == CRYPT_MODE_CTR) { - return crypt_decrypt_by_it(hperh, cipher_text, plain_text, size); + return ald_crypt_decrypt_by_it(hperh, cipher_text, plain_text, size); } if (hperh->state != CRYPT_STATE_READY) @@ -533,7 +547,7 @@ ald_status_t crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, ui hperh->plain_text = plain_text; hperh->cipher_text = cipher_text; hperh->size = size; - crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); + ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); for (i = 0; i < hperh->step; i++) { @@ -558,8 +572,8 @@ ald_status_t crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, ui * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, - uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) +ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, + uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) { if (hperh->state != CRYPT_STATE_READY) return ERROR; @@ -579,6 +593,7 @@ ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, if (hperh->hdma_m2p.perh == NULL) hperh->hdma_m2p.perh = DMA0; + if (hperh->hdma_p2m.perh == NULL) hperh->hdma_p2m.perh = DMA0; @@ -594,7 +609,7 @@ ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); - dma_config_struct(&hperh->hdma_m2p.config); + ald_dma_config_struct(&hperh->hdma_m2p.config); hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; hperh->hdma_m2p.config.src = (void *)hperh->plain_text; hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; @@ -604,9 +619,9 @@ ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; hperh->hdma_m2p.config.channel = channel_m2p; - dma_config_basic(&(hperh->hdma_m2p)); + ald_dma_config_basic(&(hperh->hdma_m2p)); - dma_config_struct(&hperh->hdma_p2m.config); + ald_dma_config_struct(&hperh->hdma_p2m.config); hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; hperh->hdma_p2m.config.dst = (void *)hperh->cipher_text; @@ -616,7 +631,7 @@ ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; hperh->hdma_p2m.config.channel = channel_p2m; - dma_config_basic(&(hperh->hdma_p2m)); + ald_dma_config_basic(&(hperh->hdma_p2m)); CRYPT_DMA_ENABLE(hperh); __UNLOCK(hperh); @@ -636,14 +651,15 @@ ald_status_t crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, * @retval Status, see @ref ald_status_t. * @note the size is multiple of 16(ase) */ -ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, - uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) +ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, + uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) { if (hperh->init.mode == CRYPT_MODE_CTR) - return crypt_decrypt_by_dma(hperh, cipher_text, plain_text, size, channel_m2p, channel_p2m); + return ald_crypt_decrypt_by_dma(hperh, cipher_text, plain_text, size, channel_m2p, channel_p2m); if (hperh->state != CRYPT_STATE_READY) return ERROR; + if (plain_text == NULL || cipher_text == NULL || size == 0) return ERROR; @@ -657,6 +673,7 @@ ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, if (hperh->hdma_m2p.perh == NULL) hperh->hdma_m2p.perh = DMA0; + if (hperh->hdma_p2m.perh == NULL) hperh->hdma_p2m.perh = DMA0; @@ -673,7 +690,7 @@ ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, CRYPT_SETDIR(hperh, CRYPT_DECRYPT); - dma_config_struct(&hperh->hdma_m2p.config); + ald_dma_config_struct(&hperh->hdma_m2p.config); hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; hperh->hdma_m2p.config.src = (void *)hperh->cipher_text; hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; @@ -683,9 +700,9 @@ ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; hperh->hdma_m2p.config.channel = channel_m2p; - dma_config_basic(&(hperh->hdma_m2p)); + ald_dma_config_basic(&(hperh->hdma_m2p)); - dma_config_struct(&hperh->hdma_p2m.config); + ald_dma_config_struct(&hperh->hdma_p2m.config); hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; hperh->hdma_p2m.config.dst = (void *)hperh->plain_text; @@ -695,7 +712,7 @@ ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; hperh->hdma_p2m.config.channel = channel_p2m; - dma_config_basic(&(hperh->hdma_p2m)); + ald_dma_config_basic(&(hperh->hdma_p2m)); CRYPT_DMA_ENABLE(hperh); __UNLOCK(hperh); @@ -718,7 +735,7 @@ ald_status_t crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, * the configuration information for the specified CRYPT module. * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_dma_pause(crypt_handle_t *hperh) +ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh) { __LOCK(hperh); CRYPT_DMA_DISABLE(hperh); @@ -734,7 +751,7 @@ ald_status_t crypt_dma_pause(crypt_handle_t *hperh) * the configuration information for the specified CRYPT module. * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_dma_resume(crypt_handle_t *hperh) +ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh) { __LOCK(hperh); CRYPT_DMA_ENABLE(hperh); @@ -749,7 +766,7 @@ ald_status_t crypt_dma_resume(crypt_handle_t *hperh) * the configuration information for the specified CRYPT module. * @retval Status, see @ref ald_status_t. */ -ald_status_t crypt_dma_stop(crypt_handle_t *hperh) +ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh) { __LOCK(hperh); CRYPT_DMA_DISABLE(hperh); @@ -766,7 +783,7 @@ ald_status_t crypt_dma_stop(crypt_handle_t *hperh) * the configuration information for the specified CRYPT module. * @retval None */ -void crypt_irq_handle(crypt_handle_t *hperh) +void ald_crypt_irq_handler(crypt_handle_t *hperh) { uint32_t i; uint32_t *in_buf; @@ -783,15 +800,16 @@ void crypt_irq_handle(crypt_handle_t *hperh) out_buf = (uint32_t *)hperh->plain_text + hperh->count - hperh->step; } - if (crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET) + if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET) { - crypt_clear_flag_status(hperh, CRYPT_FLAG_AESIF); + ald_crypt_clear_flag_status(hperh, CRYPT_FLAG_AESIF); } for (i = 0; i < hperh->step; i++) *out_buf++ = CRYPT_READ_FIFO(hperh); hperh->count += hperh->step; + if (hperh->count > (hperh->size / 4)) { hperh->count = 0; @@ -829,7 +847,7 @@ void crypt_irq_handle(crypt_handle_t *hperh) * - DISABLE * @retval None */ -void crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state) +void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state) { assert_param(IS_CRYPT(hperh->perh)); @@ -851,7 +869,7 @@ void crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t st * - SET * - RESET */ -flag_status_t crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) +flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) { assert_param(IS_CRYPT(hperh->perh)); assert_param(IS_CRYPT_FLAG(flag)); @@ -871,7 +889,7 @@ flag_status_t crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) * @arg CRYPT_FLAG_DONE: encrypt or decrypt Complete flag. * @retval None */ -void crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) +void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) { assert_param(IS_CRYPT(hperh->perh)); assert_param(IS_CRYPT_FLAG(flag)); @@ -885,13 +903,13 @@ void crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) * @param hperh: Pointer to a crypt_handle_t structure that contains * the configuration information for the specified CRYPT module. * @param it: Specifies the CRYPT interrupt source to check. - * This parameter can be one of the following values: - * @arg crypt_it_t: CRYPT interrupt + * This parameter can be one of the following values: + * @arg crypt_it_t: CRYPT interrupt * @retval Status * - SET * - RESET */ -it_status_t crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it) +it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it) { assert_param(IS_CRYPT_IT(it)); @@ -917,7 +935,7 @@ it_status_t crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it) * the configuration information for the specified CRYPT module. * @retval CRYPT state */ -crypt_state_t crypt_get_state(crypt_handle_t *hperh) +crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh) { assert_param(IS_CRYPT(hperh->perh)); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c similarity index 79% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c index 9a7d04c392bd00d7e312d180d02f157cec59c63b..5847fa627dd02189c59ee19a0fd597cd703c20f6 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c @@ -19,38 +19,38 @@ [..] The DMA driver can be used as follows: - (#) System initialization invokes dma_init(), mcu_ald_init() --> dma_init(). + (#) System initialization invokes ald_dma_init(), ald_cmu_init() --> ald_dma_init(). (#) Declare a dma_handle_t handle structure. (#) Configure the dma_handle_t structure, you can configure the - dma_config_t structure with the help of dma_config_struct(). + dma_config_t structure with the help of ald_dma_config_struct(). (#) Enable the DMA Configure: - (##) Memory -- memory: call dma_config_auto(). - (##) Peripheral -- memory: call dma_config_basic(). - (##) If you want use the dma easily, you can do this: - (+++) Memory -- memory: call dma_config_auto_easy(). - (+++) Peripheral -- memory: call dma_config_basic_easy(). + (##) Memory -- memory: call ald_dma_config_auto(). + (##) Peripheral -- memory: call ald_dma_config_basic(). + (##) If you want use the dma easily, you can do this: + (+++) Memory -- memory: call ald_dma_config_auto_easy(). + (+++) Peripheral -- memory: call ald_dma_config_basic_easy(). (#) Enable the DMA request signal: (##) Memory -- memory: the DMA request signal is request automatic. - (##) Peripheral -- memory: you need enable peripheral request signal. + (##) Peripheral -- memory: you need enable peripheral request signal. (#) If you enable DMA interrupt, the callback will be invoked: (##) When DMA transfer is completed, the cplt_cbk() will be invoked. - (##) When DMA bus occurs error, the err_cbk() will be invoked. + (##) When DMA bus occurs error, the err_cbk() will be invoked. (#) If you don't enable the DMA interrupt, you need do this: - (##) Polling the dma_get_flag_status(), this function's parameter is channel - or DMA_ERR. - (+++) When the function's Parameter is channel, if retval is SET, it means - the DMA transfer is completed. at this moment, you can do something, - and then, you need invoke dma_clear_flag_status() to clear flag. + (##) Polling the ald_dma_get_flag_status(), this function's parameter is channel + or DMA_ERR. + (+++) When the function's Parameter is channel, if retval is SET, it means + the DMA transfer is completed. at this moment, you can do something, + and then, you need invoke ald_dma_clear_flag_status() to clear flag. - (+++) When the function's Parameter is DMA_ERR, if retval is SET, it means - the DMA bus occurs error. at this moment, you can do something, - and then, you need invoke dma_clear_flag_status() to clear flag. + (+++) When the function's Parameter is DMA_ERR, if retval is SET, it means + the DMA bus occurs error. at this moment, you can do something, + and then, you need invoke ald_dma_clear_flag_status() to clear flag. @endverbatim */ @@ -167,7 +167,7 @@ static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config * @brief Handle DMA interrupt * @retval None */ -void DMA_Handler(void) +void ald_dma_irq_handler(void) { uint32_t i, reg = DMA0->IFLAG; @@ -178,13 +178,13 @@ void DMA_Handler(void) if (dma0_cbk[i].cplt_cbk != NULL) dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg); - dma_clear_flag_status(DMA0, i); + ald_dma_clear_flag_status(DMA0, i); } } if (READ_BIT(reg, (1U << DMA_ERR))) { - dma_clear_flag_status(DMA0, DMA_ERR); + ald_dma_clear_flag_status(DMA0, DMA_ERR); for (i = 0; i < DMA_CH_COUNT; ++i) { @@ -193,7 +193,6 @@ void DMA_Handler(void) } } - dma0_irq_cbk(); return; } /** @@ -215,20 +214,20 @@ void DMA_Handler(void) =================================================================== [..] This subsection provides two functions to Initilizate DMA: - (+) dma_reset(): Reset the DMA register. - - (+) dma_init(): Initializate the DMA module. this function is - invoked by mcu_ald_init(). - this function do this: - (++) Initializte private variable dma_ctrl_base and dma_cbk. - (++) Reset DMA register. - (++) Set DMA interrupt priority: preempt_prio=1, sub_priority=1 - (++) Enable DMA interrupt. - (++) Enable DMA bus error interrupt. - (++) Configure CTRLBASE resigter. - (++) Enable DMA module. - - (+) dma_config_struct(): Configure dma_config_t + (+) ald_dma_reset(): Reset the DMA register. + + (+) ald_dma_init(): Initializate the DMA module. this function is + invoked by ald_cmu_init(). + this function do this: + (++) Initializte private variable dma_ctrl_base and dma_cbk. + (++) Reset DMA register. + (++) Set DMA interrupt priority: preempt_prio=1, sub_priority=1 + (++) Enable DMA interrupt. + (++) Enable DMA bus error interrupt. + (++) Configure CTRLBASE resigter. + (++) Enable DMA module. + + (+) ald_dma_config_struct(): Configure dma_config_t structure using default parameter. @endverbatim @@ -240,7 +239,7 @@ void DMA_Handler(void) * @param DMAx: Pointer to DMA peripheral * @retval None */ -void dma_reset(DMA_TypeDef *DMAx) +void ald_dma_reset(DMA_TypeDef *DMAx) { uint32_t i; @@ -264,18 +263,18 @@ void dma_reset(DMA_TypeDef *DMAx) /** * @brief DMA module initialization, this function - * is invoked by mcu_ald_init(). + * is invoked by ald_cmu_init(). * @param DMAx: Pointer to DMA peripheral * @retval None */ -void dma_init(DMA_TypeDef *DMAx) +void ald_dma_init(DMA_TypeDef *DMAx) { assert_param(IS_DMA(DMAx)); memset(dma0_ctrl_base, 0x0, sizeof(dma0_ctrl_base)); memset(dma0_cbk, 0x0, sizeof(dma0_cbk)); - dma_reset(DMAx); + ald_dma_reset(DMAx); NVIC_SetPriority(DMA_IRQn, 2); NVIC_EnableIRQ(DMA_IRQn); SET_BIT(DMAx->IER, DMA_IER_DMAERRIE_MSK); @@ -292,7 +291,7 @@ void dma_init(DMA_TypeDef *DMAx) * @param p: Pointer to dma_config_t structure, see @ref dma_config_t * @retval None */ -void dma_config_struct(dma_config_t *p) +void ald_dma_config_struct(dma_config_t *p) { p->data_width = DMA_DATA_SIZE_BYTE; p->src_inc = DMA_DATA_INC_BYTE; @@ -323,19 +322,19 @@ void dma_config_struct(dma_config_t *p) This subsection provides some functions allowing to configure DMA channel. Include two type DMA transfer: (+) Carry data from memory to memory, this mode APIs are: - (++) dma_config_auto(): Configure DMA channel according to - the specified parameter in the dma_handle_t structure. - (++) dma_restart_auto(): Restart DMA transmitted. - (++) dma_config_auto_easy(): Configure DMA channel according - to the specified parameter. If you want use the dma easily, + (++) ald_dma_config_auto(): Configure DMA channel according to + the specified parameter in the dma_handle_t structure. + (++) ald_dma_restart_auto(): Restart DMA transmitted. + (++) ald_dma_config_auto_easy(): Configure DMA channel according + to the specified parameter. If you want use the dma easily, you can invoke this function. (+) Carry data from peripheral to memory or from memory to peripheral, this mode APIs are: - (++) dma_config_basic(): Configure DMA channel according to - the specified parameter in the dma_handle_t structure. - (++) dma_restart_basic(): Restart DMA transmitted. - (++) dma_config_basic_easy(): Configure DMA channel according - to the specified parameter. If you want use the dma easily, + (++) ald_dma_config_basic(): Configure DMA channel according to + the specified parameter in the dma_handle_t structure. + (++) ald_dma_restart_basic(): Restart DMA transmitted. + (++) ald_dma_config_basic_easy(): Configure DMA channel according + to the specified parameter. If you want use the dma easily, you can invoke this function. @endverbatim @@ -350,7 +349,7 @@ void dma_config_struct(dma_config_t *p) * configuration information for specified DMA channel. * @retval None */ -void dma_config_auto(dma_handle_t *hperh) +void ald_dma_config_auto(dma_handle_t *hperh) { dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; @@ -358,7 +357,7 @@ void dma_config_auto(dma_handle_t *hperh) dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; dma_config_base(hperh->perh, DMA_CYCLE_CTRL_AUTO, &hperh->config); - dma_clear_flag_status(hperh->perh, hperh->config.channel); + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); @@ -375,7 +374,7 @@ void dma_config_auto(dma_handle_t *hperh) * @param size: Size. * @retval None */ -void dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size) +void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size) { dma_descriptor_t *descr; @@ -400,7 +399,7 @@ void dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size) descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width)); } - dma_clear_flag_status(hperh->perh, hperh->config.channel); + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO; descr->ctrl.n_minus_1 = size - 1; WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); @@ -419,19 +418,19 @@ void dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size) * @param src: Source data begin pointer * @param dst: Destination data begin pointer * @param size: The total number of DMA transfers that DMA cycle contains - * @param channel: Channel index which well be used. + * @param channel: Channel index which will be used. * @param cbk: DMA complete callback function * * @retval None */ -void dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, - uint16_t size, uint8_t channel, void (*cbk)(void *arg)) +void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, + uint16_t size, uint8_t channel, void (*cbk)(void *arg)) { dma_handle_t hperh; assert_param(IS_DMA(DMAx)); - dma_config_struct(&hperh.config); + ald_dma_config_struct(&hperh.config); hperh.config.src = src; hperh.config.dst = dst; hperh.config.size = size; @@ -444,8 +443,8 @@ void dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, hperh.cplt_arg = NULL; hperh.err_cbk = NULL; - dma_clear_flag_status(DMAx, channel); - dma_config_auto(&hperh); + ald_dma_clear_flag_status(DMAx, channel); + ald_dma_config_auto(&hperh); return; } @@ -459,14 +458,14 @@ void dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, * configuration information for specified DMA channel. * @retval None */ -void dma_config_basic(dma_handle_t *hperh) +void ald_dma_config_basic(dma_handle_t *hperh) { dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; - dma_clear_flag_status(hperh->perh, hperh->config.channel); + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); dma_config_base(hperh->perh, DMA_CYCLE_CTRL_BASIC, &hperh->config); WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); @@ -483,7 +482,7 @@ void dma_config_basic(dma_handle_t *hperh) * @param size: Size. * @retval None */ -void dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size) +void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size) { dma_descriptor_t *descr; @@ -508,7 +507,7 @@ void dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size) descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width)); } - dma_clear_flag_status(hperh->perh, hperh->config.channel); + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC; descr->ctrl.n_minus_1 = size - 1; WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); @@ -527,19 +526,19 @@ void dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size) * @param size: The total number of DMA transfers that DMA cycle contains * @param msel: Input source to DMA channel @ref dma_msel_t * @param msigsel: Input signal to DMA channel @ref dma_msigsel_t - * @param channel: Channel index which well be used + * @param channel: Channel index which will be used * @param cbk: DMA complete callback function * * @retval None * */ -void dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, - dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) +void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, + dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) { dma_handle_t hperh; assert_param(IS_DMA(DMAx)); - dma_config_struct(&hperh.config); + ald_dma_config_struct(&hperh.config); if (((uint32_t)src) >= 0x40000000) hperh.config.src_inc = DMA_DATA_INC_NONE; @@ -559,8 +558,8 @@ void dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t siz hperh.cplt_arg = NULL; hperh.err_cbk = NULL; - dma_clear_flag_status(DMAx, channel); - dma_config_basic(&hperh); + ald_dma_clear_flag_status(DMAx, channel); + ald_dma_config_basic(&hperh); return; } @@ -580,14 +579,14 @@ void dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t siz =================================================================== [..] This subsection provides some functions allowing to control DMA: - (+) dma_channel_config(): Control DMA channel ENABLE/DISABLE. - (+) dma_interrupt_config(): Control DMA channel interrupt ENABLE or + (+) ald_dma_channel_config(): Control DMA channel ENABLE/DISABLE. + (+) ald_dma_interrupt_config(): Control DMA channel interrupt ENABLE or DISABLE. - (+) dma_get_it_status(): Check whether the specified channel + (+) ald_dma_get_it_status(): Check whether the specified channel interrupt is SET or RESET. - (+) dma_get_flag_status(): Check whether the specified channel + (+) ald_dma_get_flag_status(): Check whether the specified channel flag is SET or RESET. - (+) dma_clear_flag_status(): Clear the specified channel + (+) ald_dma_clear_flag_status(): Clear the specified channel pending flag @endverbatim @@ -604,7 +603,7 @@ void dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t siz * @arg DISABLE: Disable the channel * @retval None */ -void dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) +void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) { dma_descriptor_t *descr, *alt_descr; @@ -642,7 +641,7 @@ void dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) * * @retval None */ -void dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) +void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) { assert_param(IS_DMA(DMAx)); assert_param(IS_DMA_IT_TYPE(channel)); @@ -667,7 +666,7 @@ void dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) * - SET: Channel interrupt is set * - RESET: Channel interrupt is reset */ -it_status_t dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel) +it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel) { assert_param(IS_DMA(DMAx)); assert_param(IS_DMA_IT_TYPE(channel)); @@ -689,7 +688,7 @@ it_status_t dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel) * - SET: Channel flag is set * - RESET: Channel flag is reset */ -flag_status_t dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel) +flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel) { assert_param(IS_DMA(DMAx)); assert_param(IS_DMA_IT_TYPE(channel)); @@ -708,7 +707,7 @@ flag_status_t dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel) * @arg DMA_ERR: DMA bus error * @retval None */ -void dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel) +void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel) { assert_param(IS_DMA(DMAx)); assert_param(IS_DMA_IT_TYPE(channel)); @@ -716,17 +715,6 @@ void dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel) WRITE_REG(DMAx->ICFR, (1 << channel)); return; } - -/** - * @brief Interrupt callback function. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void dma0_irq_cbk(void) -{ - return; -} /** * @} */ diff --git a/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..b7a3e128c93200e3a8dc5c710403900aefbe5be8 --- /dev/null +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c @@ -0,0 +1,222 @@ +/** + ********************************************************************************* + * + * @file ald_flash.c + * @brief FLASH module driver. + * + * @version V1.0 + * @date 20 Nov 2017 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + */ + +#include "ald_flash.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH module driver + * @{ + */ + +#ifdef ALD_FLASH + +#if defined ( __ICCARM__ ) + #define __RAMFUNC __ramfunc +#else + #define __RAMFUNC +#endif + +/** @defgroup Flash_Private_Variables Flash Private Variables + * @{ + */ +/* global variable*/ +static op_cmd_type OP_CMD = OP_FLASH; +/** + * @} + */ + +/** @defgroup Flash_Private_Functions Flash Private Functions + * @brief Flash Private functions + * @{ + */ +/** + * @brief Unlock the flash. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC static ald_status_t flash_unlock(void) +{ + uint16_t i; + uint16_t op_cmd = OP_CMD; + + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + return ERROR; + + FLASH_REG_UNLOCK(); + FLASH_IAP_ENABLE(); + FLASH_REQ(); + + for (i = 0; i < 0xFFFF; i++) + { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)) + break; + } + + return i == 0xFFFF ? ERROR : OK; +} + +/** + * @brief Lock the flash. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC static ald_status_t flash_lock(void) +{ + uint16_t i; + uint16_t op_cmd = OP_CMD; + + FLASH_REG_UNLOCK(); + WRITE_REG(MSC->FLASHCR, 0x0); + + for (i = 0; i < 0xFFFF; i++) + { + if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))) + break; + } + + return i == 0xFFFF ? ERROR : OK; +} + +/** + * @brief Erase one page. + * @param addr: The erased page's address + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC ald_status_t flash_page_erase(uint32_t addr) +{ + uint32_t i; + uint16_t op_cmd = OP_CMD; + + if (flash_unlock() != OK) + goto end; + + if (op_cmd == OP_FLASH) + { + CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); + } + else + { + SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); + } + + WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE); + + for (i = 0; i < 0xFFFF; i++) + { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + continue; + + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK)) + goto end; + + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK)) + goto end; + + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK)) + break; + } + + if (i == 0xFFFF) + goto end; + + if (flash_lock() == ERROR) + goto end; + + return OK; +end: + flash_lock(); + return ERROR; +} + +/** + * @brief Programme a word. + * @param addr: The word's address, it is must word align. + * @param data: The 8 bytes data be write. + * @param len: The number of data be write. + * @param fifo: Choose if use fifo. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo) +{ + uint16_t i; + uint16_t prog_len; + uint32_t *p_data = data; + uint16_t op_cmd = OP_CMD; + + if (flash_unlock() != OK) + goto end; + + if (op_cmd == OP_FLASH) + CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + else + SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS); + MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS); + + for (prog_len = 0; prog_len < len; prog_len++) + { + if (fifo) + { + WRITE_REG(MSC->FLASHFIFO, p_data[0]); + WRITE_REG(MSC->FLASHFIFO, p_data[1]); + } + else + { + WRITE_REG(MSC->FLASHDL, p_data[0]); + WRITE_REG(MSC->FLASHDH, p_data[1]); + WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP); + } + + p_data += 2; + + for (i = 0; i < 0xFFFF; i++) + { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + continue; + + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK)) + break; + } + } + + if (i == 0xFFFF) + goto end; + + if (flash_lock() == ERROR) + goto end; + + return OK; +end: + flash_lock(); + return ERROR; +} +/** + * @} + */ + +#endif + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c similarity index 60% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c index 0b15ad7ca832e9dff8fe51026ca1d94e9c5a8bd6..87595d3ce9af2c9d59bd519618a354a849c231a2 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c @@ -1,11 +1,11 @@ /** ********************************************************************************* * - * @file ald_flash.c + * @file ald_flash_ext.c * @brief FLASH module driver. * * @version V1.0 - * @date 20 Nov 2017 + * @date 15 May 2019 * @author AE Team * @note * @@ -29,22 +29,23 @@ ##### How to use this driver ##### ============================================================================== [..] - (#) programme flash using flash_write(uint32_t addr, uint8_t *buf, uint16_t len) + (#) programme flash using ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len) (++) call the function and supply all the three paraments is needs, addr means the first address to write in this operation, buf is a pointer to the data which - need writing to flash. + need writing to flash. - (#) erase flash using flash_erase(uint32_t addr, uint16_t len) + (#) erase flash using ald_flash_erase(uint32_t addr, uint16_t len) (++) call the function and supply two paraments, addr is the first address to erase, len is the length to erase - (#) read flash using flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) + (#) read flash using ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) (++) read the flash and save to a buffer, ram_addr is the buffer's first address, addr is the start reading address in flash, len is the length need read @endverbatim */ + #include "ald_flash.h" @@ -52,227 +53,25 @@ * @{ */ -/** @defgroup FLASH FLASH - * @brief FLASH module driver +/** @addtogroup FLASH * @{ */ #ifdef ALD_FLASH -/** @addtogroup FLASH_Private_Types +/** @addtogroup Flash_Private_Variables * @{ */ - -/* opration buffer, global variable*/ +/* opration buffer*/ static uint8_t write_buf[FLASH_PAGE_SIZE]; -static op_cmd_type OP_CMD = OP_FLASH; - -#if defined ( __ICCARM__ ) - #define __RAMFUNC __ramfunc -#else - #define __RAMFUNC -#endif - /** * @} */ -/** @defgroup Flash_Private_Functions Flash Private Functions - * @brief Flash Private functions +/** @addtogroup Flash_Private_Functions * @{ */ -/** - * @brief Unlock the flash. - * @retval Status, see @ref ald_status_t. - */ -__RAMFUNC static ald_status_t flash_unlock(void) -{ - uint16_t i; - uint16_t op_cmd = OP_CMD; - - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) - return ERROR; - - FLASH_REG_UNLOCK(); - FLASH_IAP_ENABLE(); - FLASH_REQ(); - - for (i = 0; i < 0xFFFF; i++) - { - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)) - break; - } - - return i == 0xFFFF ? ERROR : OK; -} - -/** - * @brief Lock the flash. - * @retval Status, see @ref ald_status_t. - */ -__RAMFUNC static ald_status_t flash_lock(void) -{ - uint16_t i; - uint16_t op_cmd = OP_CMD; - - FLASH_REG_UNLOCK(); - WRITE_REG(MSC->FLASHCR, 0x0); - - for (i = 0; i < 0xFFFF; i++) - { - if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))) - break; - } - - return i == 0xFFFF ? ERROR : OK; -} - -/** - * @brief Erase one page. - * @param addr: The erased page's address - * @retval Status, see @ref ald_status_t. - */ -__RAMFUNC static ald_status_t flash_page_erase(uint32_t addr) -{ - uint32_t i; - uint16_t op_cmd = OP_CMD; - - __disable_irq(); - if (flash_unlock() != OK) - goto end; - - if (op_cmd == OP_FLASH) - { - CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); - } - else - { - SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); - } - - WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE); - - for (i = 0; i < 0xFFFF; i++) - { - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) - continue; - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK)) - goto end; - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK)) - goto end; - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK)) - break; - } - - if (i == 0xFFFF) - goto end; - - if (flash_lock() == ERROR) - goto end; - - __enable_irq(); - return OK; -end: - - if (flash_lock() == ERROR) - while (1); - - __enable_irq(); - return ERROR; -} - -/** - * @brief Programme a word. - * @param addr: The word's address, it is must word align. - * @param data: The 8 bytes data be write. - * @param len: The number of data be write. - * @param fifo: Choose if use fifo. - * @retval Status, see @ref ald_status_t. - */ -__RAMFUNC static ald_status_t flash_word_program(uint32_t addr, uint32_t data[], uint32_t len, uint32_t fifo) -{ - uint16_t i; - uint16_t prog_len; - uint32_t *p_data = data; - uint16_t op_cmd = OP_CMD; - - __disable_irq(); - if (flash_unlock() != OK) - goto end; - - if (op_cmd == OP_FLASH) - CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - else - SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); - - MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS); - MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS); - - for (prog_len = 0; prog_len < len; prog_len++) - { - if (fifo) - { - WRITE_REG(MSC->FLASHFIFO, p_data[0]); - WRITE_REG(MSC->FLASHFIFO, p_data[1]); - } - else - { - WRITE_REG(MSC->FLASHDL, p_data[0]); - WRITE_REG(MSC->FLASHDH, p_data[1]); - WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP); - } - - p_data += 2; - - for (i = 0; i < 0xFFFF; i++) - { - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) - continue; - if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK)) - break; - } - } - if (i == 0xFFFF) - goto end; - - if (flash_lock() == ERROR) - goto end; - - __enable_irq(); - return OK; -end: - if (flash_lock() == ERROR) - while (1); - - __enable_irq(); - return ERROR; -} - -/** - * @brief Read data from flash, and store in buffer. - * @param ram_addr: The stored buffer's address. - * @param addr: The start address in flash to read. - * @param len: The length of byte to read. - * @retval Status, see @ref ald_status_t. - */ -__RAMFUNC static ald_status_t __flash_read(uint32_t ram_addr[], uint32_t addr, uint32_t len) -{ - uint32_t i; - - if (!len) - return ERROR; - - for (i = 0; i < len; i++) - { - ram_addr[i] = ((uint32_t *)addr)[i]; - } - - return OK; -} - /** * @brief Check whether the flash between the given address section * have been writen, if it have been writen, return TRUE, else @@ -283,7 +82,7 @@ __RAMFUNC static ald_status_t __flash_read(uint32_t ram_addr[], uint32_t addr, u * - TRUE * - FALSE */ -__RAMFUNC static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr) +static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr) { uint8_t *addr_to_read; uint8_t value; @@ -310,15 +109,14 @@ __RAMFUNC static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_ return value == 0xFF ? FALSE : TRUE; } - /** * @} */ -/** @defgroup FLASH_Exported_Functions FLASH Exported Functions +/** @defgroup Flash_Public_Functions Flash Public Functions * @verbatim =============================================================================== - ##### Flash oprate functions ##### + ##### Flash operation functions ##### =============================================================================== [..] This section provides functions allowing to operate flash, such as read and write. @@ -327,6 +125,35 @@ __RAMFUNC static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_ * @{ */ +/** + * @brief read the specified length bytes from flash, and store to the specified area. + * @param ram_addr: the specified area to store the reading bytes. + * @param addr: the start address. + * @param len: the length to read. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) +{ + uint32_t i; + uint32_t temp; + + assert_param(IS_4BYTES_ALIGN(ram_addr)); + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + + temp = (uint32_t)ram_addr; + + if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0)) + return ERROR; + + for (i = 0; i < len; i++) + { + ram_addr[i] = ((uint32_t *)addr)[i]; + } + + return OK; +} + /** * @brief Write the give bytes to the given address section. * @param addr: The start address to write. @@ -335,7 +162,7 @@ __RAMFUNC static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_ * @retval Status, see @ref ald_status_t. */ -__RAMFUNC ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len) +ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len) { uint32_t index = 0; uint32_t para = 0; @@ -353,6 +180,8 @@ __RAMFUNC ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len) len_to_write = len; + __disable_irq(); + while (len_to_write > 0) { need_erase_page = FALSE; @@ -369,12 +198,18 @@ __RAMFUNC ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len) if (need_erase_page) { - if (ERROR == __flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr), - FLASH_PAGE_SIZE >> 2)) + if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr), + FLASH_PAGE_SIZE >> 2)) + { + __enable_irq(); return ERROR; + } if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr))) + { + __enable_irq(); return ERROR; + } para = end_write_addr & (FLASH_PAGE_SIZE - 1); index = start_write_addr & (FLASH_PAGE_SIZE - 1); @@ -405,11 +240,15 @@ __RAMFUNC ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len) } if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO)) + { + __enable_irq(); return ERROR; + } len_to_write = len_to_write - (end_write_addr - start_write_addr + 1); } + __enable_irq(); return OK; } @@ -419,9 +258,9 @@ __RAMFUNC ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len) * @param len: The length to erase. * @retval Status, see @ref ald_status_t. */ -__RAMFUNC ald_status_t flash_erase(uint32_t addr, uint16_t len) +ald_status_t ald_flash_erase(uint32_t addr, uint16_t len) { - int32_t index; + int32_t index; int32_t para; int32_t start_erase_addr; int32_t end_erase_addr; @@ -434,6 +273,8 @@ __RAMFUNC ald_status_t flash_erase(uint32_t addr, uint16_t len) len_not_erase = len; + __disable_irq(); + while (len_not_erase > 0) { page_need_save = FALSE; @@ -448,6 +289,7 @@ __RAMFUNC ald_status_t flash_erase(uint32_t addr, uint16_t len) if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1))) page_need_save = TRUE; } + if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) { if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr))) @@ -456,8 +298,8 @@ __RAMFUNC ald_status_t flash_erase(uint32_t addr, uint16_t len) if (page_need_save) { - if (ERROR == __flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr), - FLASH_PAGE_SIZE >> 2)) + if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr), + FLASH_PAGE_SIZE >> 2)) { __enable_irq(); return ERROR; @@ -480,45 +322,25 @@ __RAMFUNC ald_status_t flash_erase(uint32_t addr, uint16_t len) index = FLASH_PAGE_ADDR(start_erase_addr); len_index = FLASH_PAGE_SIZE; + if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) { __enable_irq(); return ERROR; } } + len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1); } + __enable_irq(); return OK; } - -/** - * @brief read the specified length bytes from flash, and store to the specified area. - * @param ram_addr: the specified area to store the reading bytes. - * @param addr: the start address. - * @param len: the length to read. - * @retval Status, see @ref ald_status_t. - */ -__RAMFUNC ald_status_t flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) -{ - uint32_t temp; - - assert_param(IS_4BYTES_ALIGN(ram_addr)); - assert_param(IS_FLASH_ADDRESS(addr)); - assert_param(IS_FLASH_ADDRESS(addr + len - 1)); - - temp = (uint32_t)ram_addr; - - if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0)) - return ERROR; - - return __flash_read(ram_addr, addr, len) == ERROR ? ERROR : OK; -} - /** * @} */ + #endif /** diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c similarity index 91% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c index e1d95dca31ef0da890e22931b7bc5d89234cfb46..17b4464ac161953b72512091f191abb41915731f 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_gpio.c @@ -72,7 +72,7 @@ [..] (#) Enable the GPIO clock. - (#) Configure the GPIO pin(s) using gpio_init(). + (#) Configure the GPIO pin(s) using ald_gpio_init(). (++) Configure the IO mode using "mode" member from gpio_init_t structure (++) Activate Pull-up, Pull-down resistor using "pupd" member from gpio_init_t structure. @@ -87,7 +87,7 @@ (++) Analog mode is required when a pin is to be used as ADC channel or DAC output. - (#) Configure the GPIO pin(s) using gpio_init_default(). + (#) Configure the GPIO pin(s) using ald_gpio_init_default(). (++) Configure GPIO pin using default param: init.mode = GPIO_MODE_OUTPUT; init.odos = GPIO_PUSH_PULL; @@ -98,8 +98,8 @@ init.func = GPIO_FUNC_1; (#) In case of external interrupt/event mode selection, user need invoke - gpio_exti_init() to configure some param. And then invoke - gpio_exti_interrupt_config() to enable/disable external interrupt/event. + ald_gpio_exti_init() to configure some param. And then invoke + ald_gpio_exti_interrupt_config() to enable/disable external interrupt/event. (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority mapped to the EXTI line using NVIC_SetPriority() and enable it using @@ -108,17 +108,17 @@ (#) To get the level of a pin configured in input mode use GPIO_read_pin(). (#) To set/reset the level of a pin configured in output mode use - gpio_write_pin()/gpio_toggle_pin(). + ald_gpio_write_pin()/ald_gpio_toggle_pin(). - (#) To lock pin configuration until next reset use gpio_lock_pin(). + (#) To lock pin configuration until next reset use ald_gpio_lock_pin(). (#) Configure external interrupt mode and enable/disable using - gpio_exti_interrupt_config(). + ald_gpio_exti_interrupt_config(). - (#) Get external interrupt flag status using gpio_exti_get_flag_status(). + (#) Get external interrupt flag status using ald_gpio_exti_get_flag_status(). (#) Clear pending external interrupt flag status using - gpio_exti_clear_flag_status(). + ald_gpio_exti_clear_flag_status(). @endverbatim */ @@ -166,7 +166,7 @@ * the configuration information for the specified parameters. * @retval None */ -void gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) +void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) { uint32_t i, pos, mask, tmp; @@ -247,7 +247,7 @@ void gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) * @param pin: The pin which need to initialize. * @retval None */ -void gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) +void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) { gpio_init_t init; @@ -260,7 +260,7 @@ void gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) init.type = GPIO_TYPE_CMOS; init.func = GPIO_FUNC_1; - gpio_init(GPIOx, pin, &init); + ald_gpio_init(GPIOx, pin, &init); return; } @@ -269,7 +269,7 @@ void gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. * @retval None */ -void gpio_func_default(GPIO_TypeDef *GPIOx) +void ald_gpio_func_default(GPIO_TypeDef *GPIOx) { WRITE_REG(GPIOx->FUNC0, 0x00); WRITE_REG(GPIOx->FUNC1, 0x00); @@ -286,7 +286,7 @@ void gpio_func_default(GPIO_TypeDef *GPIOx) * the configuration information for the specified parameters. * @retval None */ -void gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init) +void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init) { uint8_t i; uint8_t port; @@ -376,7 +376,7 @@ void gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init) * - BIT_SET * - BIT_RESET */ -uint8_t gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) { assert_param(IS_GPIO_PORT(GPIOx)); assert_param(IS_GPIO_PIN(pin)); @@ -395,7 +395,7 @@ uint8_t gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) * @param val: The specifies value to be written. * @retval None */ -void gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) +void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) { assert_param(IS_GPIO_PORT(GPIOx)); assert_param(IS_GPIO_PIN(pin)); @@ -414,7 +414,7 @@ void gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) * @param pin: Specifies the pin to turn over. * @retval None */ -void gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin) { assert_param(IS_GPIO_PORT(GPIOx)); assert_param(IS_GPIO_PIN(pin)); @@ -429,7 +429,7 @@ void gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin) * @param pin: Specifies the pin to turn over. * @retval None */ -void gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin) +void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin) { uint32_t i, pos, mask, tmp, value; @@ -477,7 +477,7 @@ void gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin) * @param pin: The specified Pin to be written. * @retval None */ -void gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin) { assert_param(IS_GPIO_PORT(GPIOx)); assert_param(IS_GPIO_PIN(pin)); @@ -493,7 +493,7 @@ void gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin) * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. * @retval The value; */ -uint16_t gpio_read_port(GPIO_TypeDef *GPIOx) +uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx) { assert_param(IS_GPIO_PORT(GPIOx)); @@ -506,7 +506,7 @@ uint16_t gpio_read_port(GPIO_TypeDef *GPIOx) * @param val: The specifies value to be written. * @retval None */ -void gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) +void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) { assert_param(IS_GPIO_PORT(GPIOx)); @@ -543,7 +543,7 @@ void gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) * @arg DISABLE * @retval None */ -void gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status) +void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status) { assert_param(IS_GPIO_PIN(pin)); assert_param(IS_TRIGGER_STYLE(style)); @@ -605,7 +605,7 @@ void gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_f * - SET * - RESET */ -flag_status_t gpio_exti_get_flag_status(uint16_t pin) +flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin) { assert_param(IS_GPIO_PIN(pin)); @@ -620,7 +620,7 @@ flag_status_t gpio_exti_get_flag_status(uint16_t pin) * @param pin: The pin which belong to external interrupt. * @retval None */ -void gpio_exti_clear_flag_status(uint16_t pin) +void ald_gpio_exti_clear_flag_status(uint16_t pin) { assert_param(IS_GPIO_PIN(pin)); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c similarity index 85% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c index e285872cf23ffc9a842faadcb67ecbd98c9e646d..1e5f32cde1248511f4c36ffcf1eb78c308aaac10 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_i2c.c @@ -24,24 +24,24 @@ (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, Dual Addressing mode, Own Address2, General call and Nostretch mode in the hperh init structure. - (#) Initialize the I2C registers by calling the i2c_init(). - (#) To check if target device is ready for communication, use the function i2c_is_device_ready() + (#) Initialize the I2C registers by calling the ald_i2c_init(). + (#) To check if target device is ready for communication, use the function ald_i2c_is_device_ready() (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : *** Polling mode IO operation *** ================================= [..] - (+) Transmit in master mode an amount of data in blocking mode using i2c_master_send() - (+) Receive in master mode an amount of data in blocking mode using i2c_master_recv() - (+) Transmit in slave mode an amount of data in blocking mode using i2c_slave_send() - (+) Receive in slave mode an amount of data in blocking mode using i2c_slave_recv() + (+) Transmit in master mode an amount of data in blocking mode using ald_i2c_master_send() + (+) Receive in master mode an amount of data in blocking mode using ald_i2c_master_recv() + (+) Transmit in slave mode an amount of data in blocking mode using ald_i2c_slave_send() + (+) Receive in slave mode an amount of data in blocking mode using ald_i2c_slave_recv() *** Polling mode IO MEM operation *** ===================================== [..] - (+) Write an amount of data in blocking mode to a specific memory address using i2c_mem_write() - (+) Read an amount of data in blocking mode from a specific memory address using i2c_mem_read() + (+) Write an amount of data in blocking mode to a specific memory address using ald_i2c_mem_write() + (+) Read an amount of data in blocking mode from a specific memory address using ald_i2c_mem_read() *** Interrupt mode IO operation *** @@ -49,16 +49,16 @@ [..] (+) The I2C interrupts should have the highest priority in the application in order to make them uninterruptible. - (+) Transmit in master mode an amount of data in non-blocking mode using i2c_master_send_by_it() + (+) Transmit in master mode an amount of data in non-blocking mode using ald_i2c_master_send_by_it() (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->master_tx_cplt_cbk() - (+) Receive in master mode an amount of data in non-blocking mode using i2c_master_recv_by_it() + (+) Receive in master mode an amount of data in non-blocking mode using ald_i2c_master_recv_by_it() (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->master_rx_cplt_cbk() - (+) Transmit in slave mode an amount of data in non-blocking mode using i2c_slave_send_by_it() + (+) Transmit in slave mode an amount of data in non-blocking mode using ald_i2c_slave_send_by_it() (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->slave_tx_cplt_cbk() - (+) Receive in slave mode an amount of data in non-blocking mode using i2c_slave_recv_by_it() + (+) Receive in slave mode an amount of data in non-blocking mode using ald_i2c_slave_recv_by_it() (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->slave_rx_cplt_cbk() (+) In case of transfer Error, hperh->error_callback() function is executed and user can @@ -70,11 +70,11 @@ (+) The I2C interrupts should have the highest priority in the application in order to make them uninterruptible. (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - i2c_mem_write_by_it() + ald_i2c_mem_write_by_it() (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->mem_tx_cplt_cbk() (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - i2c_mem_read_by_it() + ald_i2c_mem_read_by_it() (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->mem_rx_cplt_cbk() (+) In case of transfer Error, hperh->error_callback() function is executed and user can @@ -84,19 +84,19 @@ ============================== [..] (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - i2c_master_send_by_dma() + ald_i2c_master_send_by_dma() (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->master_tx_cplt_cbk() (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - i2c_master_recv_by_dma() + ald_i2c_master_recv_by_dma() (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->master_rx_cplt_cbk() (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - i2c_slave_send_by_dma() + ald_i2c_slave_send_by_dma() (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->slave_tx_cplt_cbk() (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - i2c_slave_recv_by_dma() + ald_i2c_slave_recv_by_dma() (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->slave_rx_cplt_cbk() (+) In case of transfer Error, hperh->error_callback() function is executed and user can @@ -106,11 +106,11 @@ ================================= [..] (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - i2c_mem_write_by_dma() + ald_i2c_mem_write_by_dma() (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->mem_tx_cplt_cbk() (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - i2c_mem_read_by_dma() + ald_i2c_mem_read_by_dma() (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->mem_rx_cplt_cbk() (+) In case of transfer Error, hperh->error_callback() function is executed and user can @@ -144,7 +144,7 @@ supported by the slave. (##) Data valid time (tVD;DAT) violated without the OVR flag being set: Workaround: If the slave device allows it, use the clock stretching mechanism - by programming no_stretch = I2C_NOSTRETCH_DISABLE in i2c_init. + by programming no_stretch = I2C_NOSTRETCH_DISABLE in ald_i2c_init. @endverbatim ********************************************************************************* @@ -229,7 +229,7 @@ static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk); [..] This subsection provides a set of functions allowing to initialize and de-initialiaze the I2Cx peripheral: - (+) Call the function i2c_init() to configure the selected device with + (+) Call the function ald_i2c_init() to configure the selected device with the selected configuration: (++) Communication Speed (++) Duty cycle @@ -240,7 +240,7 @@ static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk); (++) General call mode (++) Nostretch mode - (+) Call the function i2c_reset() to restore the default configuration + (+) Call the function ald_i2c_reset() to restore the default configuration of the selected I2Cx periperal. @endverbatim @@ -254,7 +254,7 @@ static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk); * the configuration information for the specified I2C. * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_init(i2c_handle_t *hperh) +ald_status_t ald_i2c_init(i2c_handle_t *hperh) { uint32_t freqrange = 0; uint32_t pclk1 = 0; @@ -278,7 +278,7 @@ ald_status_t i2c_init(i2c_handle_t *hperh) hperh->lock = UNLOCK; hperh->state = I2C_STATE_BUSY; - pclk1 = cmu_get_pclk1_clock(); + pclk1 = ald_cmu_get_pclk1_clock(); I2C_DISABLE(hperh); freqrange = I2C_FREQ_RANGE(pclk1); @@ -305,7 +305,7 @@ ald_status_t i2c_init(i2c_handle_t *hperh) * the configuration information for the specified I2C. * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_reset(i2c_handle_t *hperh) +ald_status_t ald_i2c_reset(i2c_handle_t *hperh) { if (hperh == NULL) return ERROR; @@ -349,29 +349,29 @@ ald_status_t i2c_reset(i2c_handle_t *hperh) using DMA mode. (#) Blocking mode functions are : - (++) i2c_master_send() - (++) i2c_master_recv() - (++) i2c_slave_send() - (++) i2c_slave_recv() - (++) i2c_mem_write() - (++) i2c_mem_read() - (++) i2c_is_device_ready() + (++) ald_i2c_master_send() + (++) ald_i2c_master_recv() + (++) ald_i2c_slave_send() + (++) ald_i2c_slave_recv() + (++) ald_i2c_mem_write() + (++) ald_i2c_mem_read() + (++) ald_i2c_is_device_ready() (#) No-Blocking mode functions with Interrupt are : - (++) i2c_master_send_by_it() - (++) i2c_master_recv_by_it() - (++) i2c_slave_send_by_it() - (++) i2c_slave_recv_by_it() - (++) i2c_mem_write_by_it() - (++) i2c_mem_read_by_it() + (++) ald_i2c_master_send_by_it() + (++) ald_i2c_master_recv_by_it() + (++) ald_i2c_slave_send_by_it() + (++) ald_i2c_slave_recv_by_it() + (++) ald_i2c_mem_write_by_it() + (++) ald_i2c_mem_read_by_it() (#) No-Blocking mode functions with DMA are : - (++) i2c_master_send_by_dma() - (++) i2c_master_recv_by_dma() - (++) i2c_slave_send_by_dma() - (++) i2c_slave_recv_by_dma() - (++) i2c_mem_write_by_dma() - (++) i2c_mem_read_by_dma() + (++) ald_i2c_master_send_by_dma() + (++) ald_i2c_master_recv_by_dma() + (++) ald_i2c_slave_send_by_dma() + (++) ald_i2c_slave_recv_by_dma() + (++) ald_i2c_mem_write_by_dma() + (++) ald_i2c_mem_read_by_dma() (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) hperh->mem_tx_cplt_cbk() @@ -396,8 +396,8 @@ ald_status_t i2c_reset(i2c_handle_t *hperh) * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint32_t timeout) +ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint16_t size, uint32_t timeout) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -453,7 +453,7 @@ ald_status_t i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *bu hperh->perh->DATA = (*buf++); --size; - if ((i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) + if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { hperh->perh->DATA = (*buf++); --size; @@ -492,8 +492,8 @@ ald_status_t i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *bu * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint32_t timeout) +ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint16_t size, uint32_t timeout) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -568,7 +568,7 @@ ald_status_t i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *bu (*buf++) = hperh->perh->DATA; --size; - if (i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) { (*buf++) = hperh->perh->DATA; --size; @@ -577,64 +577,64 @@ ald_status_t i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *bu switch (size) { - case 1: - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_TIMEOUT) + case 1: + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { - __UNLOCK(hperh); - return TIMEOUT; + if (hperh->error_code == I2C_ERROR_TIMEOUT) + { + __UNLOCK(hperh); + return TIMEOUT; + } + else + { + __UNLOCK(hperh); + return ERROR; + } } - else + + (*buf++) = hperh->perh->DATA; + break; + + case 2: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { __UNLOCK(hperh); - return ERROR; + return TIMEOUT; } - } - - (*buf++) = hperh->perh->DATA; - break; - case 2: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } + __disable_irq(); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; + __enable_irq(); + (*buf++) = hperh->perh->DATA; + break; - __disable_irq(); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; + case 3: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } - case 3: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __disable_irq(); + (*buf++) = hperh->perh->DATA; - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __disable_irq(); - (*buf++) = hperh->perh->DATA; + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) + { + __UNLOCK(hperh); + __enable_irq(); + return TIMEOUT; + } - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; __enable_irq(); - return TIMEOUT; - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; + (*buf++) = hperh->perh->DATA; + break; - default : - break; + default : + break; } hperh->state = I2C_STATE_READY; @@ -652,7 +652,7 @@ ald_status_t i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *bu * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -713,7 +713,7 @@ ald_status_t i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, ui hperh->perh->DATA = (*buf++); --size; - if ((i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) + if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { hperh->perh->DATA = (*buf++); --size; @@ -726,7 +726,7 @@ ald_status_t i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, ui return TIMEOUT; } - i2c_clear_flag_status(hperh, I2C_FLAG_AF); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); hperh->state = I2C_STATE_READY; @@ -744,7 +744,7 @@ ald_status_t i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, ui * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -794,7 +794,7 @@ ald_status_t i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, ui (*buf++) = hperh->perh->DATA; --size; - if ((i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) + if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { (*buf++) = hperh->perh->DATA; --size; @@ -804,6 +804,7 @@ ald_status_t i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, ui if (i2c_wait_stop_to_timeout(hperh, I2C_TIMEOUT_FLAG) != OK) { CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + if (hperh->error_code == I2C_ERROR_AF) { __UNLOCK(hperh); @@ -833,7 +834,7 @@ ald_status_t i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, ui * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size) +ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -877,9 +878,9 @@ ald_status_t i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8 /* Note : The I2C interrupts must be enabled after unlocking current process * to avoid the risk of I2C interrupt handle execution before current * process unlock */ - i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); return OK; } @@ -892,7 +893,7 @@ ald_status_t i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8 * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size) +ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -952,9 +953,9 @@ ald_status_t i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8 /* Note : The I2C interrupts must be enabled after unlocking current process * to avoid the risk of I2C interrupt handle execution before current * process unlock */ - i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); return OK; } @@ -966,7 +967,7 @@ ald_status_t i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8 * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -994,9 +995,9 @@ ald_status_t i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t si /* Note : The I2C interrupts must be enabled after unlocking current process * to avoid the risk of I2C interrupt handle execution before current * process unlock */ - i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); return OK; } @@ -1009,7 +1010,7 @@ ald_status_t i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t si * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1037,9 +1038,9 @@ ald_status_t i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t si /* Note : The I2C interrupts must be enabled after unlocking current process * to avoid the risk of I2C interrupt handle execution before current * process unlock */ - i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); return OK; } @@ -1055,8 +1056,8 @@ ald_status_t i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t si * @param channel: DMA channel as I2C transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint8_t channel) +ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint16_t size, uint8_t channel) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1087,7 +1088,7 @@ ald_status_t i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint hperh->hdmatx.err_cbk = i2c_dma_error; hperh->hdmatx.err_arg = hperh; - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; hperh->hdmatx.config.size = size; @@ -1097,7 +1098,7 @@ ald_status_t i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; hperh->hdmatx.config.channel = channel; - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); if (i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) { @@ -1129,8 +1130,8 @@ ald_status_t i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint * @param channel: DMA channel as I2C receive * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, - uint16_t size, uint8_t channel) +ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint16_t size, uint8_t channel) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1161,7 +1162,7 @@ ald_status_t i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint hperh->hdmarx.err_cbk = i2c_dma_error; hperh->hdmarx.err_arg = (void *)hperh; - dma_config_struct(&hperh->hdmarx.config); + ald_dma_config_struct(&hperh->hdmarx.config); hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)buf; hperh->hdmarx.config.size = size; @@ -1171,7 +1172,7 @@ ald_status_t i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; hperh->hdmarx.config.channel = channel; - dma_config_basic(&hperh->hdmarx); + ald_dma_config_basic(&hperh->hdmarx); if (i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) != OK) { @@ -1207,7 +1208,7 @@ ald_status_t i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint * @param channel: DMA channel as I2C Transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1238,7 +1239,7 @@ ald_status_t i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t s hperh->hdmatx.err_cbk = i2c_dma_error; hperh->hdmatx.err_arg = hperh; - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; hperh->hdmatx.config.size = size; @@ -1248,7 +1249,7 @@ ald_status_t i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t s hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; hperh->hdmatx.config.channel = channel; - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); @@ -1290,7 +1291,7 @@ ald_status_t i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t s * @param channel: DMA channel as I2C receive * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1321,7 +1322,7 @@ ald_status_t i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t s hperh->hdmarx.err_cbk = i2c_dma_error; hperh->hdmarx.err_arg = (void *)hperh; - dma_config_struct(&hperh->hdmarx.config); + ald_dma_config_struct(&hperh->hdmarx.config); hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)buf; hperh->hdmarx.config.size = size; @@ -1331,7 +1332,7 @@ ald_status_t i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t s hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; hperh->hdmarx.config.channel = channel; - dma_config_basic(&hperh->hdmarx); + ald_dma_config_basic(&hperh->hdmarx); SET_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); SET_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); @@ -1360,8 +1361,8 @@ ald_status_t i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t s * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1416,7 +1417,7 @@ ald_status_t i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_ hperh->perh->DATA = (*buf++); --size; - if ((i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) + if ((ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) && (size != 0)) { hperh->perh->DATA = (*buf++); --size; @@ -1441,7 +1442,7 @@ ald_status_t i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_ SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); hperh->state = I2C_STATE_READY; hperh->mode = I2C_MODE_NONE; - __delay_ms(10); + ald_delay_ms(10); __UNLOCK(hperh); return OK; } @@ -1458,8 +1459,8 @@ ald_status_t i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_ * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint32_t timeout) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1535,7 +1536,7 @@ ald_status_t i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_a (*buf++) = hperh->perh->DATA; --size; - if (i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == SET) { (*buf++) = hperh->perh->DATA; --size; @@ -1544,64 +1545,64 @@ ald_status_t i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_a switch (size) { - case 1: - if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) - { - if (hperh->error_code == I2C_ERROR_TIMEOUT) + case 1: + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) { - __UNLOCK(hperh); - return TIMEOUT; + if (hperh->error_code == I2C_ERROR_TIMEOUT) + { + __UNLOCK(hperh); + return TIMEOUT; + } + else + { + __UNLOCK(hperh); + return ERROR; + } } - else + + (*buf++) = hperh->perh->DATA; + break; + + case 2: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) { __UNLOCK(hperh); - return ERROR; + return TIMEOUT; } - } - - (*buf++) = hperh->perh->DATA; - break; - case 2: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } + __disable_irq(); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; + __enable_irq(); + (*buf++) = hperh->perh->DATA; + break; - __disable_irq(); - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; + case 3: + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) + { + __UNLOCK(hperh); + return TIMEOUT; + } - case 3: - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); - return TIMEOUT; - } + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); + __disable_irq(); + (*buf++) = hperh->perh->DATA; - CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); - __disable_irq(); - (*buf++) = hperh->perh->DATA; + if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) + { + __UNLOCK(hperh); + __enable_irq(); + return TIMEOUT; + } - if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BTF, RESET, timeout) != OK) - { - __UNLOCK(hperh); + SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + (*buf++) = hperh->perh->DATA; __enable_irq(); - return TIMEOUT; - } - - SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - (*buf++) = hperh->perh->DATA; - __enable_irq(); - (*buf++) = hperh->perh->DATA; - break; + (*buf++) = hperh->perh->DATA; + break; - default: - break; + default: + break; } hperh->state = I2C_STATE_READY; @@ -1621,8 +1622,8 @@ ald_status_t i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_a * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) +ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1665,9 +1666,9 @@ ald_status_t i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_ /* Note : The I2C interrupts must be enabled after unlocking current process * to avoid the risk of I2C interrupt handle execution before current * process unlock */ - i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); return OK; } @@ -1683,8 +1684,8 @@ ald_status_t i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_ * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, - i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) +ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint16_t size) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1745,9 +1746,9 @@ ald_status_t i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t /* Note : The I2C interrupts must be enabled after unlocking current process * to avoid the risk of I2C interrupt handle execution before current * process unlock */ - i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, ENABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, ENABLE); return OK; } @@ -1765,8 +1766,8 @@ ald_status_t i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t * @param channel: DMA channel * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint8_t channel) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1797,7 +1798,7 @@ ald_status_t i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16 hperh->hdmatx.cplt_arg = hperh; hperh->hdmatx.err_cbk = i2c_dma_error; hperh->hdmatx.err_arg = hperh; - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; @@ -1808,7 +1809,7 @@ ald_status_t i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16 hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; hperh->hdmatx.config.channel = channel; - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { @@ -1841,8 +1842,8 @@ ald_status_t i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16 * @param channel: DMA channel * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, - uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint16_t size, uint8_t channel) { if (hperh->state != I2C_STATE_READY) return BUSY; @@ -1873,7 +1874,7 @@ ald_status_t i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_ hperh->hdmarx.cplt_arg = (void *)hperh; hperh->hdmarx.err_cbk = i2c_dma_error; hperh->hdmarx.err_arg = (void *)hperh; - dma_config_struct(&hperh->hdmarx.config); + ald_dma_config_struct(&hperh->hdmarx.config); hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)buf; @@ -1884,7 +1885,7 @@ ald_status_t i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_ hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; hperh->hdmarx.config.channel = channel; - dma_config_basic(&hperh->hdmarx); + ald_dma_config_basic(&hperh->hdmarx); if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { @@ -1922,7 +1923,7 @@ ald_status_t i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_ * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout) +ald_status_t ald_i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout) { uint32_t tickstart = 0; uint32_t tmp1 = 0; @@ -1955,23 +1956,24 @@ ald_status_t i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_ } hperh->perh->DATA = I2C_7BIT_ADD_WRITE(dev_addr); - tickstart = __get_tick(); - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_ADDR); - tmp2 = i2c_get_flag_status(hperh, I2C_FLAG_AF); + tickstart = ald_get_tick(); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); + tmp2 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); tmp3 = hperh->state; while ((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != I2C_STATE_TIMEOUT)) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) hperh->state = I2C_STATE_TIMEOUT; - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_ADDR); - tmp2 = i2c_get_flag_status(hperh, I2C_FLAG_AF); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); + tmp2 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); tmp3 = hperh->state; } + hperh->state = I2C_STATE_READY; - if (i2c_get_flag_status(hperh, I2C_FLAG_ADDR) == SET) + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR) == SET) { SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); I2C_CLEAR_ADDRFLAG(hperh); @@ -1990,7 +1992,7 @@ ald_status_t i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_ else { SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - i2c_clear_flag_status(hperh, I2C_FLAG_AF); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) @@ -2036,7 +2038,7 @@ ald_status_t i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_ * @arg DISABLE * @retval None */ -void i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state) +void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state) { assert_param(IS_I2C_TYPE(hperh->perh)); assert_param(IS_I2C_IT_TYPE(it)); @@ -2059,7 +2061,7 @@ void i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t s * - 0: RESET * - 1: SET */ -flag_status_t i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) +flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) { flag_status_t state = RESET; @@ -2089,7 +2091,7 @@ flag_status_t i2c_get_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) * - 0: RESET * - 1: SET */ -flag_status_t i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it) +flag_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it) { assert_param(IS_I2C_TYPE(hperh->perh)); assert_param(IS_I2C_IT_TYPE(it)); @@ -2107,7 +2109,7 @@ flag_status_t i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it) * This parameter can be one of the @ref uart_flag_t. * @retval None */ -void i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) +void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) { assert_param(IS_I2C_TYPE(hperh->perh)); assert_param(IS_I2C_FLAG(flag)); @@ -2127,7 +2129,7 @@ void i2c_clear_flag_status(i2c_handle_t *hperh, i2c_flag_t flag) * the configuration information for the specified I2C. * @retval ald_status_t state */ -i2c_state_t i2c_get_state(i2c_handle_t *hperh) +i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh) { return hperh->state; } @@ -2138,7 +2140,7 @@ i2c_state_t i2c_get_state(i2c_handle_t *hperh) * the configuration information for the specified I2C. * @retval I2C Error Code */ -uint32_t i2c_get_error(i2c_handle_t *hperh) +uint32_t ald_i2c_get_error(i2c_handle_t *hperh) { return hperh->error_code; } @@ -2156,7 +2158,7 @@ uint32_t i2c_get_error(i2c_handle_t *hperh) * the configuration information for the specified I2C. * @retval None */ -void i2c_ev_irq_handler(i2c_handle_t *hperh) +void ald_i2c_ev_irq_handler(i2c_handle_t *hperh) { uint32_t tmp1 = 0; uint32_t tmp2 = 0; @@ -2165,12 +2167,12 @@ void i2c_ev_irq_handler(i2c_handle_t *hperh) if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) { - if (i2c_get_flag_status(hperh, I2C_FLAG_TRA) == SET) + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_TRA) == SET) { - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_TXE); - tmp2 = i2c_get_it_status(hperh, I2C_IT_BUF); - tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_BTF); - tmp4 = i2c_get_it_status(hperh, I2C_IT_EVT); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_BUF); + tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF); + tmp4 = ald_i2c_get_it_status(hperh, I2C_IT_EVT); if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) i2c_master_send_txe(hperh); @@ -2181,10 +2183,10 @@ void i2c_ev_irq_handler(i2c_handle_t *hperh) /* I2C in mode Receiver */ else { - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_RXNE); - tmp2 = i2c_get_it_status(hperh, I2C_IT_BUF); - tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_BTF); - tmp4 = i2c_get_it_status(hperh, I2C_IT_EVT); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_BUF); + tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF); + tmp4 = ald_i2c_get_it_status(hperh, I2C_IT_EVT); if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) i2c_master_recv_rxne(hperh); @@ -2196,10 +2198,10 @@ void i2c_ev_irq_handler(i2c_handle_t *hperh) /* Slave mode selected */ else { - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_ADDR); - tmp2 = i2c_get_it_status(hperh, (I2C_IT_EVT)); - tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_STOPF); - tmp4 = i2c_get_flag_status(hperh, I2C_FLAG_TRA); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ADDR); + tmp2 = ald_i2c_get_it_status(hperh, (I2C_IT_EVT)); + tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF); + tmp4 = ald_i2c_get_flag_status(hperh, I2C_FLAG_TRA); if ((tmp1 == SET) && (tmp2 == SET)) { @@ -2213,10 +2215,10 @@ void i2c_ev_irq_handler(i2c_handle_t *hperh) /* I2C in mode Transmitter */ else if (tmp4 == SET) { - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_TXE); - tmp2 = i2c_get_it_status(hperh, I2C_IT_BUF); - tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_BTF); - tmp4 = i2c_get_it_status(hperh, I2C_IT_EVT); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_BUF); + tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF); + tmp4 = ald_i2c_get_it_status(hperh, I2C_IT_EVT); if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) i2c_slave_send_txe(hperh); @@ -2227,10 +2229,10 @@ void i2c_ev_irq_handler(i2c_handle_t *hperh) /* I2C in mode Receiver */ else { - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_RXNE); - tmp2 = i2c_get_it_status(hperh, I2C_IT_BUF); - tmp3 = i2c_get_flag_status(hperh, I2C_FLAG_BTF); - tmp4 = i2c_get_it_status(hperh, I2C_IT_EVT); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_BUF); + tmp3 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF); + tmp4 = ald_i2c_get_it_status(hperh, I2C_IT_EVT); if ((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) i2c_slave_recv_rxne(hperh); @@ -2246,35 +2248,35 @@ void i2c_ev_irq_handler(i2c_handle_t *hperh) * the configuration information for I2C module * @retval NONE */ -void i2c_er_irq_handler(i2c_handle_t *hperh) +void ald_i2c_er_irq_handler(i2c_handle_t *hperh) { uint32_t tmp1 = 0; uint32_t tmp2 = 0; uint32_t tmp3 = 0; - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_BERR); - tmp2 = i2c_get_it_status(hperh, I2C_IT_ERR); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_BERR); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); /* I2C Bus error interrupt occurred */ if ((tmp1 == SET) && (tmp2 == SET)) { hperh->error_code |= I2C_ERROR_BERR; - i2c_clear_flag_status(hperh, I2C_FLAG_BERR); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_BERR); SET_BIT(hperh->perh->CON1, I2C_CON1_SRST); } - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_ARLO); - tmp2 = i2c_get_it_status(hperh, I2C_IT_ERR); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_ARLO); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); /* I2C Arbitration Loss error interrupt occurred */ if ((tmp1 == SET) && (tmp2 == SET)) { hperh->error_code |= I2C_ERROR_ARLO; - i2c_clear_flag_status(hperh, I2C_FLAG_ARLO); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_ARLO); } - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_AF); - tmp2 = i2c_get_it_status(hperh, I2C_IT_ERR); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_AF); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); /* I2C Acknowledge failure error interrupt occurred */ if ((tmp1 == SET) && (tmp2 == SET)) @@ -2282,6 +2284,7 @@ void i2c_er_irq_handler(i2c_handle_t *hperh) tmp1 = hperh->mode; tmp2 = hperh->xfer_count; tmp3 = hperh->state; + if ((tmp1 == I2C_MODE_SLAVE) && (tmp2 == 0) && \ (tmp3 == I2C_STATE_BUSY_TX)) { @@ -2291,24 +2294,25 @@ void i2c_er_irq_handler(i2c_handle_t *hperh) { hperh->error_code |= I2C_ERROR_AF; SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - i2c_clear_flag_status(hperh, I2C_FLAG_AF); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); } } - tmp1 = i2c_get_flag_status(hperh, I2C_FLAG_OVR); - tmp2 = i2c_get_it_status(hperh, I2C_IT_ERR); + tmp1 = ald_i2c_get_flag_status(hperh, I2C_FLAG_OVR); + tmp2 = ald_i2c_get_it_status(hperh, I2C_IT_ERR); /* I2C Over-Run/Under-Run interrupt occurred */ if ((tmp1 == SET) && (tmp2 == SET)) { hperh->error_code |= I2C_ERROR_OVR; - i2c_clear_flag_status(hperh, I2C_FLAG_OVR); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_OVR); } if (hperh->error_code != I2C_ERROR_NONE) { hperh->state = I2C_STATE_READY; CLEAR_BIT(hperh->perh->CON1, I2C_CON1_POSAP); + if (hperh->error_callback) hperh->error_callback(hperh); } @@ -2335,7 +2339,7 @@ static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh) { if (hperh->xfer_count == 0) { - i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); } else { @@ -2361,23 +2365,27 @@ static ald_status_t i2c_master_send_btf(i2c_handle_t *hperh) } else { - i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); + if (hperh->mode == I2C_MODE_MEM) { hperh->state = I2C_STATE_READY; + if (hperh->mem_tx_cplt_cbk) hperh->mem_tx_cplt_cbk(hperh); } else { hperh->state = I2C_STATE_READY; + if (hperh->master_tx_cplt_cbk) hperh->master_tx_cplt_cbk(hperh); } } + return OK; } @@ -2392,6 +2400,7 @@ static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh) uint32_t tmp = 0; tmp = hperh->xfer_count; + if (tmp > 3) { (*hperh->p_buff++) = hperh->perh->DATA; @@ -2399,29 +2408,32 @@ static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh) } else if ((tmp == 2) || (tmp == 3)) { - i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); } else { - i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); (*hperh->p_buff++) = hperh->perh->DATA; hperh->xfer_count--; if (hperh->mode == I2C_MODE_MEM) { hperh->state = I2C_STATE_READY; + if (hperh->mem_rx_cplt_cbk) hperh->mem_rx_cplt_cbk(hperh); } else { hperh->state = I2C_STATE_READY; + if (hperh->master_rx_cplt_cbk) hperh->master_rx_cplt_cbk(hperh); } } + return OK; } @@ -2441,8 +2453,8 @@ static ald_status_t i2c_master_recv_btf(i2c_handle_t *hperh) } else if (hperh->xfer_count == 2) { - i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); (*hperh->p_buff++) = hperh->perh->DATA; --hperh->xfer_count; @@ -2453,12 +2465,14 @@ static ald_status_t i2c_master_recv_btf(i2c_handle_t *hperh) if (hperh->mode == I2C_MODE_MEM) { hperh->state = I2C_STATE_READY; + if (hperh->mem_rx_cplt_cbk) hperh->mem_rx_cplt_cbk(hperh); } else { hperh->state = I2C_STATE_READY; + if (hperh->master_rx_cplt_cbk) hperh->master_rx_cplt_cbk(hperh); } @@ -2468,6 +2482,7 @@ static ald_status_t i2c_master_recv_btf(i2c_handle_t *hperh) (*hperh->p_buff++) = hperh->perh->DATA; --hperh->xfer_count; } + return OK; } @@ -2484,6 +2499,7 @@ static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh) hperh->perh->DATA = (*hperh->p_buff++); --hperh->xfer_count; } + return OK; } @@ -2500,6 +2516,7 @@ static ald_status_t i2c_slave_send_btf(i2c_handle_t *hperh) hperh->perh->DATA = (*hperh->p_buff++); --hperh->xfer_count; } + return OK; } @@ -2516,6 +2533,7 @@ static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh) (*hperh->p_buff++) = hperh->perh->DATA; --hperh->xfer_count; } + return OK; } @@ -2532,6 +2550,7 @@ static ald_status_t i2c_slave_recv_btf(i2c_handle_t *hperh) (*hperh->p_buff++) = hperh->perh->DATA; --hperh->xfer_count; } + return OK; } @@ -2562,9 +2581,9 @@ static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh) --hperh->xfer_count; } - i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); __I2C_CLEAR_STOPFLAG(hperh); CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); @@ -2584,10 +2603,10 @@ static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh) */ static ald_status_t i2c_slave_af(i2c_handle_t *hperh) { - i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); - i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); - i2c_clear_flag_status(hperh, I2C_FLAG_AF); + ald_i2c_interrupt_config(hperh, I2C_IT_EVT, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_BUF, DISABLE); + ald_i2c_interrupt_config(hperh, I2C_IT_ERR, DISABLE); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); hperh->state = I2C_STATE_READY; @@ -2643,6 +2662,7 @@ static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, else return TIMEOUT; } + return OK; } @@ -2669,6 +2689,7 @@ static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, else { hperh->perh->DATA = I2C_10BIT_HEADER_WRITE(dev_addr); + if (i2c_wait_master_addr_to_timeout(hperh, I2C_FLAG_ADD10, timeout) != OK) { if (hperh->error_code == I2C_ERROR_AF) @@ -2759,6 +2780,7 @@ static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, ui else { hperh->perh->DATA = I2C_MEM_ADD_MSB(mem_addr); + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { if (hperh->error_code == I2C_ERROR_AF) @@ -2771,6 +2793,7 @@ static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, ui return TIMEOUT; } } + hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); } @@ -2840,6 +2863,7 @@ static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uin return TIMEOUT; } } + hperh->perh->DATA = I2C_MEM_ADD_LSB(mem_addr); } @@ -2918,7 +2942,7 @@ static void i2c_dma_slave_send_cplt(void *argv) if (i2c_wait_flag_to_timeout(hperh, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != OK) hperh->error_code |= I2C_ERROR_TIMEOUT; - i2c_clear_flag_status(hperh, I2C_FLAG_AF); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); CLEAR_BIT(hperh->perh->CON1, I2C_CON1_ACKEN); CLEAR_BIT(hperh->perh->CON2, I2C_CON2_DMAEN); @@ -3083,6 +3107,7 @@ static uint32_t i2c_configure_speed(i2c_handle_t *hperh, uint32_t i2c_clk) if (hperh->init.clk_speed <= I2C_STANDARD_MODE_MAX_CLK) { tmp1 = (i2c_clk / (hperh->init.clk_speed << 1)); + if ((tmp1 & I2C_CKCFG_CLKSET) < 4) return 4; else @@ -3139,13 +3164,13 @@ static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t fla { uint32_t tickstart = 0; - tickstart = __get_tick(); + tickstart = ald_get_tick(); if (status == RESET) { - while (i2c_get_flag_status(hperh, flag) == RESET) + while (ald_i2c_get_flag_status(hperh, flag) == RESET) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->state = I2C_STATE_READY; __UNLOCK(hperh); @@ -3155,9 +3180,9 @@ static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t fla } else { - while (i2c_get_flag_status(hperh, flag) != RESET) + while (ald_i2c_get_flag_status(hperh, flag) != RESET) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->state = I2C_STATE_READY; __UNLOCK(hperh); @@ -3165,6 +3190,7 @@ static ald_status_t i2c_wait_flag_to_timeout(i2c_handle_t *hperh, i2c_flag_t fla } } } + return OK; } @@ -3180,13 +3206,14 @@ static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_fla { uint32_t tickstart = 0; - tickstart = __get_tick(); - while (i2c_get_flag_status(hperh, flag) == RESET) + tickstart = ald_get_tick(); + + while (ald_i2c_get_flag_status(hperh, flag) == RESET) { - if (i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) { SET_BIT(hperh->perh->CON1, I2C_CON1_STOP); - i2c_clear_flag_status(hperh, I2C_FLAG_AF); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); hperh->error_code = I2C_ERROR_AF; hperh->state = I2C_STATE_READY; @@ -3196,7 +3223,7 @@ static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_fla if (timeout != I2C_MAX_DELAY) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->state = I2C_STATE_READY; __UNLOCK(hperh); @@ -3204,6 +3231,7 @@ static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_fla } } } + return OK; } @@ -3216,16 +3244,16 @@ static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, i2c_fla */ static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart = __get_tick(); + uint32_t tickstart = ald_get_tick(); - while (i2c_get_flag_status(hperh, I2C_FLAG_TXE) == RESET) + while (ald_i2c_get_flag_status(hperh, I2C_FLAG_TXE) == RESET) { if (i2c_is_ack_failed(hperh) != OK) return ERROR; if (timeout != I2C_MAX_DELAY) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->error_code |= I2C_ERROR_TIMEOUT; hperh->state = I2C_STATE_READY; @@ -3234,6 +3262,7 @@ static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeou } } } + return OK; } @@ -3246,9 +3275,9 @@ static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeou */ static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeout) { - uint32_t tickstart = __get_tick(); + uint32_t tickstart = ald_get_tick(); - while (i2c_get_flag_status(hperh, I2C_FLAG_BTF) == RESET) + while (ald_i2c_get_flag_status(hperh, I2C_FLAG_BTF) == RESET) { if (i2c_is_ack_failed(hperh) != OK) { @@ -3257,7 +3286,7 @@ static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeou if (timeout != I2C_MAX_DELAY) { - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->error_code |= I2C_ERROR_TIMEOUT; hperh->state = I2C_STATE_READY; @@ -3266,6 +3295,7 @@ static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeou } } } + return OK; } @@ -3279,14 +3309,14 @@ static ald_status_t i2c_wait_btf_to_timeout(i2c_handle_t *hperh, uint32_t timeou static ald_status_t i2c_wait_stop_to_timeout(i2c_handle_t *hperh, uint32_t timeout) { uint32_t tickstart = 0x00; - tickstart = __get_tick(); + tickstart = ald_get_tick(); - while (i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == RESET) + while (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == RESET) { if (i2c_is_ack_failed(hperh) != OK) return ERROR; - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->error_code |= I2C_ERROR_TIMEOUT; hperh->state = I2C_STATE_READY; @@ -3294,6 +3324,7 @@ static ald_status_t i2c_wait_stop_to_timeout(i2c_handle_t *hperh, uint32_t timeo return TIMEOUT; } } + return OK; } @@ -3307,20 +3338,20 @@ static ald_status_t i2c_wait_stop_to_timeout(i2c_handle_t *hperh, uint32_t timeo static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout) { uint32_t tickstart = 0x00; - tickstart = __get_tick(); + tickstart = ald_get_tick(); - while (i2c_get_flag_status(hperh, I2C_FLAG_RXNE) == RESET) + while (ald_i2c_get_flag_status(hperh, I2C_FLAG_RXNE) == RESET) { - if (i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == SET) + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_STOPF) == SET) { - i2c_clear_flag_status(hperh, I2C_FLAG_STOPF); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_STOPF); hperh->error_code = I2C_ERROR_NONE; hperh->state = I2C_STATE_READY; __UNLOCK(hperh); return ERROR; } - if ((timeout == 0) || ((__get_tick() - tickstart) > timeout)) + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { hperh->error_code |= I2C_ERROR_TIMEOUT; hperh->state = I2C_STATE_READY; @@ -3328,6 +3359,7 @@ static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeo return TIMEOUT; } } + return OK; } @@ -3339,9 +3371,9 @@ static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeo */ static ald_status_t i2c_is_ack_failed(i2c_handle_t *hperh) { - if (i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) + if (ald_i2c_get_flag_status(hperh, I2C_FLAG_AF) == SET) { - i2c_clear_flag_status(hperh, I2C_FLAG_AF); + ald_i2c_clear_flag_status(hperh, I2C_FLAG_AF); hperh->error_code = I2C_ERROR_AF; hperh->state = I2C_STATE_READY; __UNLOCK(hperh); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c similarity index 92% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c index 842e40938f624201d9a3f11dd7602f4042c4e6de..81b933d6c78acd5a98fc6d6f5a7369c7540c3250 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_iap.c @@ -49,7 +49,7 @@ * - 0: SUCCESS * - 1: ERROR */ -uint32_t iap_erase_page(uint32_t addr) +uint32_t ald_iap_erase_page(uint32_t addr) { uint32_t status; IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR); @@ -70,7 +70,7 @@ uint32_t iap_erase_page(uint32_t addr) * - 0: SUCCESS * - 1: ERROR */ -uint32_t iap_program_word(uint32_t addr, uint32_t data) +uint32_t ald_iap_program_word(uint32_t addr, uint32_t data) { uint32_t status; IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR); @@ -95,7 +95,7 @@ uint32_t iap_program_word(uint32_t addr, uint32_t data) * - 0: SUCCESS * - 1: ERROR */ -uint32_t iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h) +uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h) { uint32_t status; IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR); @@ -122,7 +122,7 @@ uint32_t iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h) * - 0: SUCCESS * - 1: ERROR */ -uint32_t iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase) +uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase) { uint32_t status; IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c similarity index 58% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c index f15053cd6d8d90bba44fe3f961edeb32cc087031..0966ea26a28a0794cb8a096e00b92e8ac9dd8cd7 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pis.c @@ -42,7 +42,7 @@ * the configuration information for the specified PIS module. * @retval Status, see @ref ald_status_t. */ -ald_status_t pis_create(pis_handle_t *hperh) +ald_status_t ald_pis_create(pis_handle_t *hperh) { pis_divide_t temp; uint8_t clock_menu = 0; @@ -81,32 +81,39 @@ ald_status_t pis_create(pis_handle_t *hperh) /* configure sync clock, judging by producer clock with consumer clock */ switch (clock_menu) { - case 0x00: - case 0x11: - case 0x22: - case 0x33: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 0 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x01: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 5 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x02: - case 0x12: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 6 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x21: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 4 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x30: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 1 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x31: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 2 << PIS_CH0_CON_SYNCSEL_POSS); - break; - case 0x32: - MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 3 << PIS_CH0_CON_SYNCSEL_POSS); - default: - break; + case 0x00: + case 0x11: + case 0x22: + case 0x33: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 0 << PIS_CH0_CON_SYNCSEL_POSS); + break; + + case 0x01: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 5 << PIS_CH0_CON_SYNCSEL_POSS); + break; + + case 0x02: + case 0x12: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 6 << PIS_CH0_CON_SYNCSEL_POSS); + break; + + case 0x21: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 4 << PIS_CH0_CON_SYNCSEL_POSS); + break; + + case 0x30: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 1 << PIS_CH0_CON_SYNCSEL_POSS); + break; + + case 0x31: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 2 << PIS_CH0_CON_SYNCSEL_POSS); + break; + + case 0x32: + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 3 << PIS_CH0_CON_SYNCSEL_POSS); + + default: + break; } MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS); @@ -116,14 +123,16 @@ ald_status_t pis_create(pis_handle_t *hperh) /* enable consumer bit, switch pin of consumer */ switch (hperh->consumer_con) { - case PIS_CON_0: - PIS->TAR_CON0 |= hperh->consumer_pos; - break; - case PIS_CON_1: - PIS->TAR_CON1 |= hperh->consumer_pos; - break; - default: - break; + case PIS_CON_0: + PIS->TAR_CON0 |= hperh->consumer_pos; + break; + + case PIS_CON_1: + PIS->TAR_CON1 |= hperh->consumer_pos; + break; + + default: + break; } __UNLOCK(hperh); @@ -137,7 +146,7 @@ ald_status_t pis_create(pis_handle_t *hperh) * the configuration information for the specified PIS module. * @retval Status, see @ref ald_status_t. */ -ald_status_t pis_destroy(pis_handle_t *hperh) +ald_status_t ald_pis_destroy(pis_handle_t *hperh) { assert_param(IS_PIS(hperh->perh)); @@ -151,14 +160,16 @@ ald_status_t pis_destroy(pis_handle_t *hperh) switch (hperh->consumer_con) { - case PIS_CON_0: - PIS->TAR_CON0 &= ~(hperh->consumer_pos); - break; - case PIS_CON_1: - PIS->TAR_CON1 &= ~(hperh->consumer_pos); - break; - default: - break; + case PIS_CON_0: + PIS->TAR_CON0 &= ~(hperh->consumer_pos); + break; + + case PIS_CON_1: + PIS->TAR_CON1 &= ~(hperh->consumer_pos); + break; + + default: + break; } hperh->state = PIS_STATE_RESET; @@ -180,14 +191,14 @@ ald_status_t pis_destroy(pis_handle_t *hperh) * @param hperh: Pointer to a pis_handle_t structure that contains * the configuration information for the specified PIS module. * @param ch: The PIS channel enable output - * This parameter can be one of the following values: - * @arg PIS_OUT_CH_0 - * @arg PIS_OUT_CH_1 - * @arg PIS_OUT_CH_2 - * @arg PIS_OUT_CH_3 + * This parameter can be one of the following values: + * @arg PIS_OUT_CH_0 + * @arg PIS_OUT_CH_1 + * @arg PIS_OUT_CH_2 + * @arg PIS_OUT_CH_3 * @retval Status, see @ref ald_status_t. */ -ald_status_t pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch) +ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch) { assert_param(IS_PIS(hperh->perh)); assert_param(IS_PIS_OUPUT_CH(ch)); @@ -203,14 +214,14 @@ ald_status_t pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch) * @param hperh: Pointer to a pis_handle_t structure that contains * the configuration information for the specified PIS module. * @param ch: The PIS channel disable output - * This parameter can be one of the following values: - * @arg PIS_OUT_CH_0 - * @arg PIS_OUT_CH_1 - * @arg PIS_OUT_CH_2 - * @arg PIS_OUT_CH_3 + * This parameter can be one of the following values: + * @arg PIS_OUT_CH_0 + * @arg PIS_OUT_CH_1 + * @arg PIS_OUT_CH_2 + * @arg PIS_OUT_CH_3 * @retval Status, see @ref ald_status_t. */ -ald_status_t pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch) +ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch) { assert_param(IS_PIS(hperh->perh)); assert_param(IS_PIS_OUPUT_CH(ch)); @@ -235,7 +246,7 @@ ald_status_t pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch) * the configuration information for the specified PIS module. * @retval ALD state */ -pis_state_t pis_get_state(pis_handle_t *hperh) +pis_state_t ald_pis_get_state(pis_handle_t *hperh) { assert_param(IS_PIS(hperh->perh)); return hperh->state; @@ -259,7 +270,7 @@ pis_state_t pis_get_state(pis_handle_t *hperh) * LPUART0) how to modulate the target output signal. * @retval Status, see @ref ald_status_t. */ -ald_status_t pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config) +ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config) { assert_param(IS_PIS(hperh->perh)); assert_param(IS_PIS_MODU_TARGET(config->target)); @@ -270,38 +281,38 @@ ald_status_t pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config) switch (config->target) { - case PIS_UART0_TX: - MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_UART1_TX: - MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_UART2_TX: - MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_UART3_TX: - MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - case PIS_LPUART0_TX: - MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); - MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); - MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); - break; - - default: - break; + case PIS_UART0_TX: + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART1_TX: + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART2_TX: + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART3_TX: + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + case PIS_LPUART0_TX: + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS); + break; + + default: + break; } __UNLOCK(hperh); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c similarity index 75% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c index f959aa300143c6fd108515fcbec6e2a25f0d1ac3..0c488304a17925b8c25566eb42dcc9fc240126eb 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_pmu.c @@ -37,13 +37,12 @@ * @brief PMU module interrupt handler * @retval None */ -void LVD_Handler(void) +void ald_lvd_irq_handler(void) { SYSCFG_UNLOCK(); SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); SYSCFG_LOCK(); - lvd_irq_cbk(); return; } /** @@ -64,7 +63,6 @@ void LVD_Handler(void) [..] This section provides functions allowing to: (+) Enter stop1 mode. (+) Enter stop2 mode. - (+) Enter standby mode. (+) Get wakeup status. (+) Clear wakeup status. @@ -76,7 +74,7 @@ void LVD_Handler(void) * @brief Enter stop1 mode * @retval None */ -void pmu_stop1_enter(void) +void ald_pmu_stop1_enter(void) { SYSCFG_UNLOCK(); MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP1 << PMU_CR_LPM_POSS); @@ -94,9 +92,10 @@ void pmu_stop1_enter(void) * @brief Enter stop2 mode * @retval None */ -void pmu_stop2_enter(void) +void ald_pmu_stop2_enter(void) { SYSCFG_UNLOCK(); + SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP2 << PMU_CR_LPM_POSS); SYSCFG_LOCK(); @@ -105,38 +104,6 @@ void pmu_stop2_enter(void) __WFI(); SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; - return; - -} - -/** - * @brief Enter standby mode - * @param port: The port whick wake up the standby mode. - * @retval None - */ -void pmu_standby_enter(pmu_standby_wakeup_sel_t port) -{ - assert_param(IS_PMU_STANDBY_PORT_SEL(port)); - - if (port != PMU_STANDBY_PORT_NONE) - { - BKPC_UNLOCK(); - MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS); - SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK); - BKPC_LOCK(); - - SYSCFG_UNLOCK(); - MODIFY_REG(PMU->CR, PMU_CR_WKPS_MSK, port << PMU_CR_WKPS_POSS); - SET_BIT(PMU->CR, PMU_CR_WKPEN_MSK); - MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STANDBY << PMU_CR_LPM_POSS); - SYSCFG_LOCK(); - } - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __WFI(); - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; - return; } @@ -145,7 +112,7 @@ void pmu_standby_enter(pmu_standby_wakeup_sel_t port) * @param sr: Status bit. * @retval Status. */ -flag_status_t pmu_get_status(pmu_status_t sr) +flag_status_t ald_pmu_get_status(pmu_status_t sr) { assert_param(IS_PMU_STATUS(sr)); @@ -160,7 +127,7 @@ flag_status_t pmu_get_status(pmu_status_t sr) * @param sr: Status bit. * @retval None */ -void pmu_clear_status(pmu_status_t sr) +void ald_pmu_clear_status(pmu_status_t sr) { assert_param(IS_PMU_STATUS(sr)); SYSCFG_UNLOCK(); @@ -201,7 +168,7 @@ void pmu_clear_status(pmu_status_t sr) * @param state: New state, ENABLE/DISABLE; * @retval None */ -void pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state) +void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state) { assert_param(IS_FUNC_STATE(state)); SYSCFG_UNLOCK(); @@ -228,17 +195,6 @@ void pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type SYSCFG_LOCK(); return; } - -/** - * @brief Interrupt callback function. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void lvd_irq_cbk(void) -{ - return; -} /** * @} */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c similarity index 78% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c index 5b8efcad02ae03ccc754c98f289e1a43b6d971bf..b896bcf104e7325a1d30f190a0669391a39c40dd 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rmu.c @@ -38,7 +38,7 @@ * @param state: The new status: ENABLE/DISABLE. * @retval None */ -void rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state) +void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state) { assert_param(IS_FUNC_STATE(state)); @@ -67,7 +67,7 @@ void rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state) * @param state: Speicifies the type of the reset, * @retval The status: SET/RESET. */ -flag_status_t rmu_get_reset_status(rmu_state_t state) +flag_status_t ald_rmu_get_reset_status(rmu_state_t state) { assert_param(IS_RMU_STATE(state)); @@ -82,7 +82,7 @@ flag_status_t rmu_get_reset_status(rmu_state_t state) * @param state: Specifies the type of the reset, * @retval None */ -void rmu_clear_reset_status(rmu_state_t state) +void ald_rmu_clear_reset_status(rmu_state_t state) { assert_param(IS_RMU_STATE_CLEAR(state)); @@ -97,7 +97,7 @@ void rmu_clear_reset_status(rmu_state_t state) * @param perh: The peripheral device, * @retval None */ -void rmu_reset_periperal(rmu_peripheral_t perh) +void ald_rmu_reset_periperal(rmu_peripheral_t perh) { uint32_t idx, pos; @@ -109,24 +109,24 @@ void rmu_reset_periperal(rmu_peripheral_t perh) switch (idx) { - case 0: - WRITE_REG(RMU->AHB1RSTR, pos); - break; + case 0: + WRITE_REG(RMU->AHB1RSTR, pos); + break; - case 1: - WRITE_REG(RMU->AHB2RSTR, pos); - break; + case 1: + WRITE_REG(RMU->AHB2RSTR, pos); + break; - case 2: - WRITE_REG(RMU->APB1RSTR, pos); - break; + case 2: + WRITE_REG(RMU->APB1RSTR, pos); + break; - case 4: - WRITE_REG(RMU->APB2RSTR, pos); - break; + case 4: + WRITE_REG(RMU->APB2RSTR, pos); + break; - default: - break; + default: + break; } SYSCFG_LOCK(); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c similarity index 84% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c index 913a095bd2b065148ff53917b7642553dfcfde09..c8294d3ab7d4472daa7ab7e6949501d4757ed4a1 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_rtc.c @@ -27,48 +27,48 @@ (+) Enable the RTC controller interface clock. (+) Select the RTC source clock(default LOSC). (+) Configure the RTC asynchronous prescaler, synchronous prescaler and hour - format using the rtc_init() function. + format using the ald_rtc_init() function. *** Time and date operation *** ================================= [..] - (+) To configure the time use the rtc_set_time() function. - (+) To configure the date use the rtc_set_date() function. - (+) To read the time use the rtc_get_time() function. - (+) To read the date use the rtc_get_date() function. + (+) To configure the time use the ald_rtc_set_time() function. + (+) To configure the date use the ald_rtc_set_date() function. + (+) To read the time use the ald_rtc_get_time() function. + (+) To read the date use the ald_rtc_get_date() function. *** Alarm operation *** =================================== [..] - (+) To configure the alarm use rtc_set_alarm() function - (+) To read the alarm use rtc_get_alarm() function - (+) To cancel the alarm use rtc_alarm_cmd() function + (+) To configure the alarm use ald_rtc_set_alarm() function + (+) To read the alarm use ald_rtc_get_alarm() function + (+) To cancel the alarm use ald_rtc_alarm_cmd() function *** Time stamp operation *** =================================== [..] - (+) To configure the time stamp use rtc_set_time_stamp() function - (+) To read the time stamp use rtc_get_time_stamp() function - (+) To cancel the time stamp use rtc_cancel_time_stamp() function + (+) To configure the time stamp use ald_rtc_set_time_stamp() function + (+) To read the time stamp use ald_rtc_get_time_stamp() function + (+) To cancel the time stamp use ald_rtc_cancel_time_stamp() function *** Tamper operation *** =================================== [..] - (+) To configure the tamper use rtc_set_tamper() function - (+) To cancel the tamper use rtc_alarm_cmd() function + (+) To configure the tamper use ald_rtc_set_tamper() function + (+) To cancel the tamper use ald_rtc_alarm_cmd() function *** Wake-up operation *** =================================== [..] - (+) To configure the wake-up parameters use rtc_set_wakeup() function - (+) To read the re-load register value use rtc_get_wakeup_timer_value() function - (+) To cancel the wake-up use rtc_cancel_wakeup() function + (+) To configure the wake-up parameters use ald_rtc_set_wakeup() function + (+) To read the re-load register value use ald_rtc_get_wakeup_timer_value() function + (+) To cancel the wake-up use ald_rtc_cancel_wakeup() function *** Output clock operation *** =================================== [..] - (+) To configure the clock output type use rtc_set_clock_output() function - (+) To cancel the clock output use rtc_cancel_clock_output() function + (+) To configure the clock output type use ald_rtc_set_clock_output() function + (+) To cancel the clock output use ald_rtc_cancel_clock_output() function *** Control functions *** =================================== @@ -118,7 +118,7 @@ #include "ald_rtc.h" #include "ald_bkpc.h" -#include "ald_temp.h" +#include "ald_tsense.h" #include "ald_syscfg.h" @@ -170,14 +170,19 @@ static int32_t rtc_consistency_check(rtc_time_t *t_last, { if (t_last->second != time->second) return 0; + if (t_last->minute != time->minute) return 0; + if (t_last->hour != time->hour) return 0; + if (d_last->day != date->day) return 0; + if (d_last->month != date->month) return 0; + if (d_last->year != date->year) return 0; @@ -217,7 +222,7 @@ static int32_t rtc_consistency_check(rtc_time_t *t_last, * @brief Reset RTC register. * @retval None */ -void rtc_reset(void) +void ald_rtc_reset(void) { RTC_UNLOCK(); @@ -237,13 +242,13 @@ void rtc_reset(void) * the configuration parameters. * @retval None */ -void rtc_init(rtc_init_t *init) +void ald_rtc_init(rtc_init_t *init) { assert_param(IS_RTC_HOUR_FORMAT(init->hour_format)); assert_param(IS_RTC_OUTPUT_SEL(init->output)); assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity)); - rtc_reset(); + ald_rtc_reset(); RTC_UNLOCK(); MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS); @@ -262,7 +267,7 @@ void rtc_init(rtc_init_t *init) * @param sel: RTC source type. * @retval None */ -void rtc_source_selcet(rtc_source_sel_t sel) +void ald_rtc_source_select(rtc_source_sel_t sel) { assert_param(IS_RTC_SOURCE_SEL(sel)); @@ -299,10 +304,10 @@ void rtc_source_selcet(rtc_source_sel_t sel) [..] This section provides functions allowing: [#] - (+) To configure the time use the rtc_set_time() function. - (+) To configure the date use the rtc_set_date() function. - (+) To read the time use the rtc_get_time() function. - (+) To read the date use the rtc_get_date() function. + (+) To configure the time use the ald_rtc_set_time() function. + (+) To configure the date use the ald_rtc_set_date() function. + (+) To read the time use the ald_rtc_get_time() function. + (+) To read the date use the ald_rtc_get_date() function. @endverbatim * @{ @@ -314,7 +319,7 @@ void rtc_source_selcet(rtc_source_sel_t sel) * @param format: Data format. * @retval ALD status. */ -ald_status_t rtc_set_time(rtc_time_t *time, rtc_format_t format) +ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format) { uint32_t tmp; @@ -344,11 +349,11 @@ ald_status_t rtc_set_time(rtc_time_t *time, rtc_format_t format) WRITE_REG(RTC->SSEC, time->sub_sec); RTC_LOCK(); - tmp = __get_tick(); + tmp = ald_get_tick(); while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) { - if ((__get_tick() - tmp) > RTC_TIMEOUT_VALUE) + if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) return TIMEOUT; } @@ -361,7 +366,7 @@ ald_status_t rtc_set_time(rtc_time_t *time, rtc_format_t format) * @param format: Data format. * @retval ALD status. */ -ald_status_t rtc_set_date(rtc_date_t *date, rtc_format_t format) +ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format) { uint32_t tmp; @@ -392,11 +397,11 @@ ald_status_t rtc_set_date(rtc_date_t *date, rtc_format_t format) WRITE_REG(RTC->DATE, tmp); RTC_LOCK(); - tmp = __get_tick(); + tmp = ald_get_tick(); while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) { - if ((__get_tick() - tmp) > RTC_TIMEOUT_VALUE) + if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) return TIMEOUT; } @@ -409,7 +414,7 @@ ald_status_t rtc_set_date(rtc_date_t *date, rtc_format_t format) * @param format: Data format. * @retval None */ -void rtc_get_time(rtc_time_t *time, rtc_format_t format) +void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format) { uint32_t tmp; @@ -441,7 +446,7 @@ void rtc_get_time(rtc_time_t *time, rtc_format_t format) * @param format: Data format. * @retval None */ -void rtc_get_date(rtc_date_t *date, rtc_format_t format) +void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format) { uint32_t tmp = RTC->DATE; @@ -475,7 +480,7 @@ void rtc_get_date(rtc_date_t *date, rtc_format_t format) * 0 - Consistency * -1 - Not consistency */ -int32_t rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format) +int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format) { int32_t nr = 3; rtc_date_t d_last; @@ -483,10 +488,10 @@ int32_t rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t forma while (nr--) { - rtc_get_time(&t_last, format); - rtc_get_date(&d_last, format); - rtc_get_time(time, format); - rtc_get_date(date, format); + ald_rtc_get_time(&t_last, format); + ald_rtc_get_date(&d_last, format); + ald_rtc_get_time(time, format); + ald_rtc_get_date(date, format); if (rtc_consistency_check(&t_last, &d_last, time, date)) return 0; @@ -508,8 +513,8 @@ int32_t rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t forma [..] This section provides functions allowing: [#] - (+) To configure the alarm use rtc_set_alarm() function - (+) To read the alarm use rtc_get_alarm() function + (+) To configure the alarm use ald_rtc_set_alarm() function + (+) To read the alarm use ald_rtc_get_alarm() function @endverbatim * @{ @@ -521,7 +526,7 @@ int32_t rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t forma * @param format: Data format. * @retval None */ -void rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format) +void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format) { unsigned int tmp, ss_tmp; @@ -607,7 +612,7 @@ void rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format) * @param format: Data format. * @retval None */ -void rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) +void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) { uint8_t week; uint32_t tmp, ss_tmp; @@ -633,29 +638,36 @@ void rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) switch (week) { - case 1: - alarm->week = 0; - break; - case 2: - alarm->week = 1; - break; - case 4: - alarm->week = 2; - break; - case 8: - alarm->week = 3; - break; - case 16: - alarm->week = 4; - break; - case 32: - alarm->week = 5; - break; - case 64: - alarm->week = 6; - break; - default: - break; + case 1: + alarm->week = 0; + break; + + case 2: + alarm->week = 1; + break; + + case 4: + alarm->week = 2; + break; + + case 8: + alarm->week = 3; + break; + + case 16: + alarm->week = 4; + break; + + case 32: + alarm->week = 5; + break; + + case 64: + alarm->week = 6; + break; + + default: + break; } } else @@ -701,9 +713,9 @@ void rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) [..] This section provides functions allowing: [#] - (+) To configure the time stamp use rtc_set_time_stamp() function - (+) To read the time stamp use rtc_get_time_stamp() function - (+) To cancel the time stamp use rtc_cancel_time_stamp() function + (+) To configure the time stamp use ald_rtc_set_time_stamp() function + (+) To read the time stamp use ald_rtc_get_time_stamp() function + (+) To cancel the time stamp use ald_rtc_cancel_time_stamp() function @endverbatim * @{ @@ -719,7 +731,7 @@ void rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) * @arg RTC_TS_FALLING_EDGE * @retval None */ -void rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style) +void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style) { assert_param(IS_RTC_TS_SIGNAL(sel)); assert_param(IS_RTC_TS_STYLE(style)); @@ -739,7 +751,7 @@ void rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style) * @brief Cancel time stamp. * @retval None */ -void rtc_cancel_time_stamp(void) +void ald_rtc_cancel_time_stamp(void) { RTC_UNLOCK(); CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); @@ -755,7 +767,7 @@ void rtc_cancel_time_stamp(void) * @param format: Data format. * @retval None */ -void rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format) +void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format) { uint32_t tmp0, tmp1; @@ -804,8 +816,8 @@ void rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t f [..] This section provides functions allowing: [#] - (+) To configure the tamper use rtc_set_tamper() function - (+) To cancel the tamper use rtc_alarm_cmd() function + (+) To configure the tamper use ald_rtc_set_tamper() function + (+) To cancel the tamper use ald_rtc_alarm_cmd() function @endverbatim * @{ @@ -815,7 +827,7 @@ void rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t f * @param tamper: pointer to rtc_tamper_t structure. * @retval None */ -void rtc_set_tamper(rtc_tamper_t *tamper) +void ald_rtc_set_tamper(rtc_tamper_t *tamper) { assert_param(IS_RTC_TAMPER(tamper->idx)); assert_param(IS_RTC_TAMPER_TRIGGER(tamper->trig)); @@ -850,7 +862,7 @@ void rtc_set_tamper(rtc_tamper_t *tamper) * @arg RTC_TAMPER_1 * @retval None */ -void rtc_cancel_tamper(rtc_tamper_idx_t idx) +void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx) { assert_param(IS_RTC_TAMPER(idx)); @@ -878,9 +890,9 @@ void rtc_cancel_tamper(rtc_tamper_idx_t idx) [..] This section provides functions allowing: [#] - (+) To configure the wake-up parameters use rtc_set_wakeup() function - (+) To read the re-load register value use rtc_get_wakeup_timer_value() function - (+) To cancel the wake-up use rtc_cancel_wakeup() function + (+) To configure the wake-up parameters use ald_rtc_set_wakeup() function + (+) To read the re-load register value use ald_rtc_get_wakeup_timer_value() function + (+) To cancel the wake-up use ald_rtc_cancel_wakeup() function @endverbatim * @{ @@ -891,7 +903,7 @@ void rtc_cancel_tamper(rtc_tamper_idx_t idx) * @param value: re-load value. * @retval None */ -void rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value) +void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value) { assert_param(IS_RTC_WAKEUP_CLOCK(clock)); @@ -908,7 +920,7 @@ void rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value) * @brief Cancel wake-up. * @retval None */ -void rtc_cancel_wakeup(void) +void ald_rtc_cancel_wakeup(void) { RTC_UNLOCK(); CLEAR_BIT(RTC->CON, RTC_CON_WUTE_MSK); @@ -921,7 +933,7 @@ void rtc_cancel_wakeup(void) * @brief Get wake-up re-load register value. * @retval Value of re-load register. */ -uint16_t rtc_get_wakeup_timer_value(void) +uint16_t ald_rtc_get_wakeup_timer_value(void) { return RTC->WUMAT & 0xFFFF; } @@ -939,8 +951,8 @@ uint16_t rtc_get_wakeup_timer_value(void) [..] This section provides functions allowing: [#] - (+) To configure the clock output type use rtc_set_clock_output() function - (+) To cancel the clock output use rtc_cancel_clock_output() function + (+) To configure the clock output type use ald_rtc_set_clock_output() function + (+) To cancel the clock output use ald_rtc_cancel_clock_output() function @endverbatim * @{ @@ -950,7 +962,7 @@ uint16_t rtc_get_wakeup_timer_value(void) * @param clock: pointer to rtc_clock_output_t structure. * @retval ALD status. */ -ald_status_t rtc_set_clock_output(rtc_clock_output_t clock) +ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock) { uint32_t cnt = 4000; assert_param(IS_RTC_CLOCK_OUTPUT(clock)); @@ -960,8 +972,11 @@ ald_status_t rtc_set_clock_output(rtc_clock_output_t clock) if (clock == RTC_CLOCK_OUTPUT_EXA_1) { SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2LCKN_MSK)) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL2RDY_MSK))) && (--cnt)); } else @@ -982,7 +997,7 @@ ald_status_t rtc_set_clock_output(rtc_clock_output_t clock) * @brief Cancel clock output. * @retval None */ -void rtc_cancel_clock_output(void) +void ald_rtc_cancel_clock_output(void) { RTC_UNLOCK(); CLEAR_BIT(RTC->CON, RTC_CON_CKOE_MSK); @@ -1025,7 +1040,7 @@ void rtc_cancel_clock_output(void) * @arg DISABLE * @retval None */ -void rtc_interrupt_config(rtc_it_t it, type_func_t state) +void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state) { assert_param(IS_RTC_IT(it)); assert_param(IS_FUNC_STATE(state)); @@ -1051,7 +1066,7 @@ void rtc_interrupt_config(rtc_it_t it, type_func_t state) * @arg DISABLE * @retval None */ -void rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state) +void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state) { assert_param(IS_RTC_ALARM(idx)); assert_param(IS_FUNC_STATE(state)); @@ -1073,7 +1088,7 @@ void rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state) * @param sub_ss: value of sub-sconde. * @retval ALD status. */ -ald_status_t rtc_set_shift(type_func_t add_1s, uint16_t sub_ss) +ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss) { uint32_t tick; @@ -1085,11 +1100,11 @@ ald_status_t rtc_set_shift(type_func_t add_1s, uint16_t sub_ss) MODIFY_REG(RTC->SSECTR, RTC_SSECTR_INC_MSK, add_1s << RTC_SSECTR_INC_POS); RTC_LOCK(); - tick = __get_tick(); + tick = ald_get_tick(); while (READ_BIT(RTC->CON, RTC_CON_SSEC_MSK)) { - if ((__get_tick() - tick) > RTC_TIMEOUT_VALUE) + if ((ald_get_tick() - tick) > RTC_TIMEOUT_VALUE) return TIMEOUT; } @@ -1101,7 +1116,7 @@ ald_status_t rtc_set_shift(type_func_t add_1s, uint16_t sub_ss) * @param config: pointer to rtc_cali_t structure. * @retval None */ -void rtc_set_cali(rtc_cali_t *config) +void ald_rtc_set_cali(rtc_cali_t *config) { assert_param(IS_RTC_CALI_FREQ(config->cali_freq)); assert_param(IS_RTC_CALI_TC(config->tc)); @@ -1129,7 +1144,7 @@ void rtc_set_cali(rtc_cali_t *config) * @brief Cancel calibration * @retval None */ -void rtc_cancel_cali(void) +void ald_rtc_cancel_cali(void) { RTC_CALI_UNLOCK(); CLEAR_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); @@ -1142,7 +1157,7 @@ void rtc_cancel_cali(void) * @brief Get calibration status. * @retval ALD status. */ -ald_status_t rtc_get_cali_status(void) +ald_status_t ald_rtc_get_cali_status(void) { if (READ_BIT(RTC->CALCON, RTC_CALCON_ERR_MSK)) return ERROR; @@ -1155,7 +1170,7 @@ ald_status_t rtc_get_cali_status(void) * @param temp: the value of temperature. * @retval None */ -void rtc_write_temp(uint16_t temp) +void ald_rtc_write_temp(uint16_t temp) { RTC_CALI_UNLOCK(); MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, temp << RTC_TEMPR_VAL_POSS); @@ -1172,7 +1187,7 @@ void rtc_write_temp(uint16_t temp) * - 0: RESET * - 1: SET */ -it_status_t rtc_get_it_status(rtc_it_t it) +it_status_t ald_rtc_get_it_status(rtc_it_t it) { assert_param(IS_RTC_IT(it)); @@ -1190,7 +1205,7 @@ it_status_t rtc_get_it_status(rtc_it_t it) * - 0: RESET * - 1: SET */ -flag_status_t rtc_get_flag_status(rtc_flag_t flag) +flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag) { assert_param(IS_RTC_IF(flag)); @@ -1204,7 +1219,7 @@ flag_status_t rtc_get_flag_status(rtc_flag_t flag) * @param flag: specifies the flag to check. * @retval None. */ -void rtc_clear_flag_status(rtc_flag_t flag) +void ald_rtc_clear_flag_status(rtc_flag_t flag) { assert_param(IS_RTC_IF(flag)); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c similarity index 83% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c index 79f2af9ac702c03a43db332593e04d64eb6143dd..e7d1f466223fe4b7e4cbd7414e8d89912ede3827 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_smartcard.c @@ -29,12 +29,12 @@ (##) SMARTCARD pins configuration: (+++) Enable the clock for the SMARTCARD GPIOs. (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). - (##) NVIC configuration if you need to use interrupt process (smartcard_send_by_it() - and smartcard_recv_by_it() APIs): + (##) NVIC configuration if you need to use interrupt process (ald_smartcard_send_by_it() + and ald_smartcard_recv_by_it() APIs): (+++) Configure the USARTx interrupt priority. (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (smartcard_send_by_dma() - and smartcard_recv_by_dma() APIs): + (##) DMA Configuration if you need to use DMA process (ald_smartcard_send_by_dma() + and ald_smartcard_recv_by_dma() APIs): (+++) Declare a DMA handle structure for the Tx/Rx channel. (+++) Enable the DMAx interface clock. (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. @@ -47,23 +47,23 @@ (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure. - (#) Initialize the SMARTCARD registers by calling the smartcard_init() API. + (#) Initialize the SMARTCARD registers by calling the ald_smartcard_init() API. (#) Three operation modes are available within this driver : *** Polling mode IO operation *** ================================= [..] - (+) Send an amount of data in blocking mode using smartcard_send() - (+) Receive an amount of data in blocking mode using smartcard_recv() + (+) Send an amount of data in blocking mode using ald_smartcard_send() + (+) Receive an amount of data in blocking mode using ald_smartcard_recv() *** Interrupt mode IO operation *** =================================== [..] - (+) Send an amount of data in non blocking mode using smartcard_send_by_it() + (+) Send an amount of data in non blocking mode using ald_smartcard_send_by_it() (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode using smartcard_recv_by_it() + (+) Receive an amount of data in non blocking mode using ald_smartcard_recv_by_it() (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->rx_cplt_cbk() (+) In case of transfer Error, hperh->error_cbk() function is executed and user can @@ -72,10 +72,10 @@ *** DMA mode IO operation *** ============================== [..] - (+) Send an amount of data in non blocking mode (DMA) using smartcard_send_by_dma() + (+) Send an amount of data in non blocking mode (DMA) using ald_smartcard_send_by_dma() (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode (DMA) using smartcard_recv_by_dma() + (+) Receive an amount of data in non blocking mode (DMA) using ald_smartcard_recv_by_dma() (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->rx_cplt_cbk() (+) In case of transfer Error, hperh->error_cbk()() function is executed and user can @@ -180,7 +180,7 @@ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t to use 1.5 stop bits for both transmitting and receiving to avoid switching between the two configurations. [..] - The smartcard_init() function follows the USART SmartCard configuration procedure. + The ald_smartcard_init() function follows the USART SmartCard configuration procedure. @endverbatim * @{ @@ -202,7 +202,7 @@ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t * the configuration information for the specified SMARTCARD module. * @retval Status, see @ref ald_status_t. */ -ald_status_t smartcard_init(smartcard_handle_t *hperh) +ald_status_t ald_smartcard_init(smartcard_handle_t *hperh) { assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); assert_param(IS_USART_STOPBITS(hperh->init.stop_bits)); @@ -239,7 +239,7 @@ ald_status_t smartcard_init(smartcard_handle_t *hperh) * the configuration information for the specified SMARTCARD module. * @retval Status, see @ref ald_status_t. */ -ald_status_t smartcard_reset(smartcard_handle_t *hperh) +ald_status_t ald_smartcard_reset(smartcard_handle_t *hperh) { assert_param(IS_USART(hperh->perh)); @@ -295,17 +295,17 @@ ald_status_t smartcard_reset(smartcard_handle_t *hperh) error is detected. (#) Blocking mode APIs are : - (++) smartcard_send() - (++) smartcard_recv() + (++) ald_smartcard_send() + (++) ald_smartcard_recv() (#) Non Blocking mode APIs with Interrupt are : - (++) smartcard_send_by_it() - (++) smartcard_recv_by_it() - (++) smartcard_irq_handle() + (++) ald_smartcard_send_by_it() + (++) ald_smartcard_recv_by_it() + (++) ald_smartcard_irq_handler() (#) Non Blocking mode functions with DMA are : - (++) smartcard_send_by_dma() - (++) smartcard_recv_by_dma() + (++) ald_smartcard_send_by_dma() + (++) ald_smartcard_recv_by_dma() * @endverbatim * @{ @@ -320,10 +320,11 @@ ald_status_t smartcard_reset(smartcard_handle_t *hperh) * @param timeout: Specify timeout value * @retval Status, see @ref ald_status_t. */ -ald_status_t smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) return BUSY; + if ((buf == NULL) || (size == 0)) return ERROR; @@ -368,10 +369,11 @@ ald_status_t smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t si * @param timeout: Specify timeout value * @retval Status, see @ref ald_status_t. */ -ald_status_t smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) return BUSY; + if ((buf == NULL) || (size == 0)) return ERROR; @@ -408,10 +410,11 @@ ald_status_t smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t si * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size) { if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) return BUSY; + if ((buf == NULL) || (size == 0)) return ERROR; @@ -424,8 +427,8 @@ ald_status_t smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint1 hperh->err_code = SMARTCARD_ERROR_NONE; __UNLOCK(hperh); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, ENABLE); return OK; } @@ -438,10 +441,11 @@ ald_status_t smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint1 * @param size: Amount of data to be received * @retval Status, see @ref ald_status_t. */ -ald_status_t smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size) { if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) return BUSY; + if ((buf == NULL) || (size == 0)) return ERROR; @@ -454,9 +458,9 @@ ald_status_t smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint1 hperh->err_code = SMARTCARD_ERROR_NONE; __UNLOCK(hperh); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, ENABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, ENABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE); return OK; } @@ -471,10 +475,11 @@ ald_status_t smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint1 * @param channel: DMA channel as USART transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX)) return BUSY; + if ((buf == NULL) || (size == 0)) return ERROR; @@ -494,7 +499,7 @@ ald_status_t smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint hperh->hdmatx.err_cbk = smartcard_dma_error; hperh->hdmatx.err_arg = (void *)hperh; - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; hperh->hdmatx.config.size = size; @@ -503,11 +508,11 @@ ald_status_t smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint hperh->hdmatx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY; hperh->hdmatx.config.channel = channel; - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); - usart_clear_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); + ald_usart_clear_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); __UNLOCK(hperh); - usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, ENABLE); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, ENABLE); return OK; } @@ -522,10 +527,11 @@ ald_status_t smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint * @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit. * @retval Status, see @ref ald_status_t. */ -ald_status_t smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX)) return BUSY; + if ((buf == NULL) || (size == 0)) return ERROR; @@ -545,7 +551,7 @@ ald_status_t smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint hperh->hdmarx.err_cbk = smartcard_dma_error; hperh->hdmarx.err_arg = (void *)hperh; - dma_config_struct(&hperh->hdmarx.config); + ald_dma_config_struct(&hperh->hdmarx.config); hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)buf; hperh->hdmarx.config.size = size; @@ -554,10 +560,10 @@ ald_status_t smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint hperh->hdmarx.config.msel = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1; hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR; hperh->hdmarx.config.channel = channel; - dma_config_basic(&hperh->hdmarx); + ald_dma_config_basic(&hperh->hdmarx); __UNLOCK(hperh); - usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, ENABLE); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, ENABLE); return OK; } @@ -569,48 +575,55 @@ ald_status_t smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint * the configuration information for the specified SMARTCARD module. * @retval None */ -void smartcard_irq_handle(smartcard_handle_t *hperh) +void ald_smartcard_irq_handler(smartcard_handle_t *hperh) { uint32_t flag; uint32_t source; /* Handle parity error */ - flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_PE); - source = usart_get_it_status((usart_handle_t *)hperh, USART_IT_PE); + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_PE); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_PE); + if ((flag != RESET) && (source != RESET)) hperh->err_code |= SMARTCARD_ERROR_PE; /* Handle frame error */ - flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_FE); - source = usart_get_it_status((usart_handle_t *)hperh, USART_IT_ERR); + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_FE); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_ERR); + if ((flag != RESET) && (source != RESET)) hperh->err_code |= SMARTCARD_ERROR_FE; /* Handle noise error */ - flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_NE); + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_NE); + if ((flag != RESET) && (source != RESET)) hperh->err_code |= SMARTCARD_ERROR_NE; /* Handle overrun error */ - flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_ORE); + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_ORE); + if ((flag != RESET) && (source != RESET)) hperh->err_code |= SMARTCARD_ERROR_ORE; /* Handle receive */ - flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_RXNE); - source = usart_get_it_status((usart_handle_t *)hperh, USART_IT_RXNE); + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_RXNE); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_RXNE); + if ((flag != RESET) && (source != RESET)) __smartcard_recv_by_it(hperh); /* Handle transmit */ - flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TXE); - source = usart_get_it_status((usart_handle_t *)hperh, USART_IT_TXE); + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TXE); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TXE); + if ((flag != RESET) && (source != RESET)) __smartcard_send_by_it(hperh); /* Handle transmit complete */ - flag = usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); - source = usart_get_it_status((usart_handle_t *)hperh, USART_IT_TC); + flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TC); + source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TC); + if ((flag != RESET) && (source != RESET)) __smartcard_end_send_by_it(hperh); @@ -638,9 +651,9 @@ void smartcard_irq_handle(smartcard_handle_t *hperh) [..] This subsection provides a set of functions allowing to return the State of SmartCard communication process and also return Peripheral Errors occurred during communication process - (+) smartcard_get_state() API can be helpful to check in run-time the state + (+) ald_smartcard_get_state() API can be helpful to check in run-time the state of the SMARTCARD peripheral. - (+) smartcard_get_error() check in run-time errors that could be occurred during + (+) ald_smartcard_get_error() check in run-time errors that could be occurred during communication. @endverbatim @@ -653,7 +666,7 @@ void smartcard_irq_handle(smartcard_handle_t *hperh) * the configuration information for the specified SMARTCARD module. * @retval ALD state */ -smartcard_state_t smartcard_get_state(smartcard_handle_t *hperh) +smartcard_state_t ald_smartcard_get_state(smartcard_handle_t *hperh) { return hperh->state; } @@ -664,7 +677,7 @@ smartcard_state_t smartcard_get_state(smartcard_handle_t *hperh) * the configuration information for the specified SMARTCARD module. * @retval SMARTCARD Error Code */ -uint32_t smartcard_get_error(smartcard_handle_t *hperh) +uint32_t ald_smartcard_get_error(smartcard_handle_t *hperh) { return hperh->err_code; } @@ -694,8 +707,8 @@ static void smartcard_dma_send_cplt(void *arg) smartcard_handle_t *hperh = (smartcard_handle_t *)arg; hperh->tx_count = 0; - usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); return; } @@ -711,7 +724,7 @@ static void smartcard_dma_recv_cplt(void *arg) smartcard_handle_t *hperh = (smartcard_handle_t *)arg; hperh->rx_count = 0; - usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); if (hperh->rx_cplt_cbk) @@ -735,8 +748,8 @@ static void smartcard_dma_error(void *arg) hperh->err_code = SMARTCARD_ERROR_DMA; hperh->state = SMARTCARD_STATE_READY; - usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); - usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE); + ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE); if (hperh->error_cbk) hperh->error_cbk(hperh); @@ -761,16 +774,16 @@ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t if (timeout == 0) return OK; - tick = __get_tick(); + tick = ald_get_tick(); - while ((usart_get_flag_status((usart_handle_t *)hperh, flag)) != status) + while ((ald_usart_get_flag_status((usart_handle_t *)hperh, flag)) != status) { - if (((__get_tick()) - tick) > timeout) + if (((ald_get_tick()) - tick) > timeout) { - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); return TIMEOUT; } @@ -784,7 +797,7 @@ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t * @param hperh: Pointer to a smartcard_handle_t structure that contains * the configuration information for the specified SMARTCARD module. * Function called under interruption only, once - * interruptions have been enabled by smartcard_send_by_it() + * interruptions have been enabled by ald_smartcard_send_by_it() * @retval Status, see @ref ald_status_t. */ static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh) @@ -796,8 +809,8 @@ static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh) if (--hperh->tx_count == 0) { - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE); } return OK; @@ -812,11 +825,11 @@ static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh) */ static ald_status_t __smartcard_end_send_by_it(smartcard_handle_t *hperh) { - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, DISABLE); CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); if (hperh->state == SMARTCARD_STATE_READY) - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); if (hperh->tx_cplt_cbk) hperh->tx_cplt_cbk(hperh); @@ -840,9 +853,9 @@ static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh) if (--hperh->rx_count == 0) { - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); - usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE); CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); if (hperh->rx_cplt_cbk) @@ -901,13 +914,14 @@ static void smartcard_set_config(smartcard_handle_t *hperh) if (READ_BIT(hperh->perh->CON0, (1 << 15))) { /* Integer part computing in case Oversampling mode is 8 Samples */ - integer = ((25 * cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); + integer = ((25 * ald_cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); } else { /* Integer part computing in case Oversampling mode is 16 Samples */ - integer = ((25 * cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); + integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); } + tmp = (integer / 100) << 4; /* Determine the fractional part */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c similarity index 83% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c index 45e24960f8e15802b4dc128d575664c15403315b..9ab99c71a543b0a0d5c353ce8e1850b5d80c29d2 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_spi.c @@ -34,16 +34,16 @@ (+++) Enable the clock for the SPI GPIOs (+++) Configure these SPI pins as push-pull (##) NVIC configuration if you need to use interrupt process - by implementing the mcu_irq_config() API. - Invoked spi_irq_handle() function in SPI-IRQ function + by implementing the ald_mcu_irq_config() API. + Invoked ald_spi_irq_handler() function in SPI-IRQ function (##) DMA Configuration if you need to use DMA process (+++) Define ALD_DMA in ald_conf.h - (+++) Enable the DMAx clock + (+++) Enable the DMAx clock (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. - (#) Initialize the SPI module by invoking the spi_init() API. + (#) Initialize the SPI module by invoking the ald_spi_init() API. [..] Circular mode restriction: @@ -51,7 +51,7 @@ (##) Master 2Lines RxOnly (##) Master 1Line Rx (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs - the spi_dma_pause()/ spi_dma_stop(). + the ald_spi_dma_pause()/ ald_spi_dma_stop(). * @endverbatim */ @@ -104,7 +104,7 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status); (+) User must configure all related peripherals resources (CLOCK, GPIO, DMA, NVIC). - (+) Call the function spi_init() to configure the selected device with + (+) Call the function ald_spi_init() to configure the selected device with the selected configuration: (++) Mode (++) Direction @@ -117,7 +117,7 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status); (++) CRC Calculation (++) CRC Polynomial if CRC enabled - (+) Call the function spi_reset() to reset the selected SPIx periperal. + (+) Call the function ald_spi_reset() to reset the selected SPIx periperal. @endverbatim * @{ @@ -129,7 +129,7 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status); * the configuration information for the specified SPI module. * @retval None */ -void spi_reset(spi_handle_t *hperh) +void ald_spi_reset(spi_handle_t *hperh) { hperh->perh->CON1 = 0x0; hperh->perh->CON2 = 0x0; @@ -148,7 +148,7 @@ void spi_reset(spi_handle_t *hperh) * the configuration information for the specified SPI module. * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_init(spi_handle_t *hperh) +ald_status_t ald_spi_init(spi_handle_t *hperh) { uint32_t tmp = 0; @@ -166,7 +166,7 @@ ald_status_t spi_init(spi_handle_t *hperh) if (hperh == NULL) return ERROR; - spi_reset(hperh); + ald_spi_reset(hperh); tmp = hperh->perh->CON1; @@ -251,37 +251,63 @@ ald_status_t spi_init(spi_handle_t *hperh) * - 0 Success * - -1 Failed */ -int32_t spi_send_byte_fast(spi_handle_t *hperh, uint8_t data) +int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data) { uint16_t cnt = 2000, temp; hperh->perh->DATA = data; + while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); - while ((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0); + cnt = 2000; + + while ((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0 && (--cnt)); + temp = hperh->perh->DATA; UNUSED(temp); return cnt == 0 ? -1 : 0; } +/** + * @brief transmit one byte fast in blocking mode(1line). + * @param hperh: Pointer to a spi_handle_t structure. + * @param data: Data to be sent + * @retval status: + * - 0 Success + * - -1 Failed + */ +int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data) +{ + uint16_t cnt = 2000; + + hperh->perh->DATA = data; + + while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); + + return cnt == 0 ? -1 : 0; +} + /** * @brief Receive one byte fast in blocking mode. * @param hperh: Pointer to a spi_handle_t structure. * @retval Data. */ -uint8_t spi_recv_byte_fast(spi_handle_t *hperh) +uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh) { uint16_t cnt = 2000; if (hperh->init.mode == SPI_MODE_MASTER) { hperh->perh->DATA = 0xFF; + while (((hperh->perh->STAT & (1 << SPI_STAT_TXBE_POS)) == 0) && (--cnt)); } cnt = 2000; + while (((hperh->perh->STAT & (1 << SPI_STAT_RXBNE_POS)) == 0) && (--cnt)); + return (uint8_t)hperh->perh->DATA; } @@ -293,12 +319,13 @@ uint8_t spi_recv_byte_fast(spi_handle_t *hperh) * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY) return BUSY; + if (buf == NULL || size == 0) return ERROR; @@ -316,8 +343,10 @@ ald_status_t spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t if (hperh->init.crc_calc) SPI_CRC_RESET(hperh); + if (hperh->init.dir == SPI_DIRECTION_1LINE) SPI_1LINE_TX(hperh); + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) SPI_ENABLE(hperh); @@ -378,7 +407,7 @@ ald_status_t spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t } if (hperh->init.dir == SPI_DIRECTION_2LINES) - spi_clear_flag_status(hperh, SPI_IF_OVE); + ald_spi_clear_flag_status(hperh, SPI_IF_OVE); hperh->state = SPI_STATE_READY; __UNLOCK(hperh); @@ -394,13 +423,14 @@ ald_status_t spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { uint16_t temp; assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY) return BUSY; + if (buf == NULL || size == 0) return ERROR; @@ -417,6 +447,7 @@ ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t if (hperh->init.crc_calc) SPI_CRC_RESET(hperh); + if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) SPI_1LINE_RX(hperh); @@ -424,7 +455,7 @@ ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t { __UNLOCK(hperh); hperh->state = SPI_STATE_READY; - return spi_send_recv(hperh, buf, buf, size, timeout); + return ald_spi_send_recv(hperh, buf, buf, size, timeout); } if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) @@ -498,11 +529,11 @@ ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t UNUSED(temp); } - if ((hperh->init.crc_calc) && (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { hperh->err_code |= SPI_ERROR_CRC; SPI_CRC_RESET(hperh); - spi_clear_flag_status(hperh, SPI_IF_CRCERR); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); hperh->state = SPI_STATE_READY; __UNLOCK(hperh); return ERROR; @@ -523,7 +554,7 @@ ald_status_t spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) +ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) { uint16_t temp; @@ -531,8 +562,10 @@ ald_status_t spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf if (hperh->state != SPI_STATE_READY) return BUSY; + if (hperh->init.dir != SPI_DIRECTION_2LINES) return ERROR; + if (tx_buf == NULL || rx_buf == NULL || size == 0) return ERROR; @@ -701,11 +734,11 @@ ald_status_t spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf return TIMEOUT; } - if ((hperh->init.crc_calc) && (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { hperh->err_code |= SPI_ERROR_CRC; SPI_CRC_RESET(hperh); - spi_clear_flag_status(hperh, SPI_IF_CRCERR); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); hperh->state = SPI_STATE_READY; __UNLOCK(hperh); @@ -725,12 +758,13 @@ ald_status_t spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) { assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY) return BUSY; + if (buf == NULL || size == 0) return ERROR; @@ -754,12 +788,12 @@ ald_status_t spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) if (hperh->init.dir == SPI_DIRECTION_2LINES) { - spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); } else { - spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); - spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); } if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) @@ -775,16 +809,18 @@ ald_status_t spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) { assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY) return BUSY; + if (buf == NULL || size == 0) return ERROR; + if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) - return ERROR; /* Please call spi_send_recv_by_it() */ + return ERROR; /* Please call ald_spi_send_recv_by_it() */ __LOCK(hperh); hperh->state = SPI_STATE_BUSY_RX; @@ -804,8 +840,8 @@ ald_status_t spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) if (hperh->init.crc_calc == ENABLE) SPI_CRC_RESET(hperh); - spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); - spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) SPI_ENABLE(hperh); @@ -822,12 +858,13 @@ ald_status_t spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) +ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) { assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY) return BUSY; + if (tx_buf == NULL || rx_buf == NULL || size == 0) return ERROR; @@ -846,9 +883,9 @@ ald_status_t spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t * if (hperh->init.crc_calc) SPI_CRC_RESET(hperh); - spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); - spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); - spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, ENABLE); return OK; } @@ -862,12 +899,13 @@ ald_status_t spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t * * @param channel: DMA channel as SPI transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY) return BUSY; + if (buf == NULL || size == 0) return ERROR; @@ -884,6 +922,7 @@ ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, u if (hperh->init.dir == SPI_DIRECTION_1LINE) SPI_1LINE_TX(hperh); + if (hperh->init.crc_calc) SPI_CRC_RESET(hperh); @@ -896,7 +935,7 @@ ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, u hperh->hdmatx.err_cbk = spi_dma_error; /* Configure SPI DMA transmit */ - dma_config_struct(&(hperh->hdmatx.config)); + ald_dma_config_struct(&(hperh->hdmatx.config)); hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; @@ -906,10 +945,10 @@ ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, u hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; hperh->hdmatx.config.channel = channel; - dma_config_basic(&(hperh->hdmatx)); + ald_dma_config_basic(&(hperh->hdmatx)); __UNLOCK(hperh); - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) SPI_ENABLE(hperh); @@ -925,12 +964,13 @@ ald_status_t spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, u * @param channel: DMA channel as SPI transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY) return BUSY; + if (buf == NULL || size == 0) return ERROR; @@ -947,11 +987,13 @@ ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, u if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) SPI_1LINE_RX(hperh); + if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) { __UNLOCK(hperh); - return ERROR; /* Please use spi_send_recv_by_dma() */ + return ERROR; /* Please use ald_spi_send_recv_by_dma() */ } + if (hperh->init.crc_calc) SPI_CRC_RESET(hperh); @@ -964,7 +1006,7 @@ ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, u hperh->hdmarx.err_cbk = spi_dma_error; /* Configure DMA Receive */ - dma_config_struct(&(hperh->hdmarx.config)); + ald_dma_config_struct(&(hperh->hdmarx.config)); hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)buf; @@ -974,10 +1016,10 @@ ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, u hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; hperh->hdmarx.config.channel = channel; - dma_config_basic(&(hperh->hdmarx)); + ald_dma_config_basic(&(hperh->hdmarx)); __UNLOCK(hperh); - spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) SPI_ENABLE(hperh); @@ -995,12 +1037,13 @@ ald_status_t spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, u * @param rx_channel: DMA channel as SPI receive * @retval Status, see @ref ald_status_t. */ -ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) +ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) { assert_param(IS_SPI(hperh->perh)); if (hperh->state != SPI_STATE_READY && hperh->state != SPI_STATE_BUSY_RX) return BUSY; + if (tx_buf == NULL || rx_buf == NULL || size == 0) return ERROR; @@ -1017,6 +1060,7 @@ ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t if (hperh->hdmatx.perh == NULL) hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) hperh->hdmarx.perh = DMA0; @@ -1033,7 +1077,7 @@ ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t SPI_CRC_RESET(hperh); /* Configure SPI DMA transmit */ - dma_config_struct(&(hperh->hdmatx.config)); + ald_dma_config_struct(&(hperh->hdmatx.config)); hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; hperh->hdmatx.config.src = (void *)tx_buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; @@ -1043,10 +1087,10 @@ ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; hperh->hdmatx.config.channel = tx_channel; - dma_config_basic(&(hperh->hdmatx)); + ald_dma_config_basic(&(hperh->hdmatx)); /* Configure DMA Receive */ - dma_config_struct(&(hperh->hdmarx.config)); + ald_dma_config_struct(&(hperh->hdmarx.config)); hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)rx_buf; @@ -1056,11 +1100,11 @@ ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; hperh->hdmarx.config.channel = rx_channel; - dma_config_basic(&(hperh->hdmarx)); + ald_dma_config_basic(&(hperh->hdmarx)); __UNLOCK(hperh); - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); - spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); return OK; } @@ -1070,13 +1114,13 @@ ald_status_t spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t * @param hperh: Pointer to a spi_handle_t structure. * @retval Status */ -ald_status_t spi_dma_pause(spi_handle_t *hperh) +ald_status_t ald_spi_dma_pause(spi_handle_t *hperh) { assert_param(IS_SPI(hperh->perh)); __LOCK(hperh); - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); __UNLOCK(hperh); return OK; @@ -1087,13 +1131,13 @@ ald_status_t spi_dma_pause(spi_handle_t *hperh) * @param hperh: Pointer to a spi_handle_t structure. * @retval Status */ -ald_status_t spi_dma_resume(spi_handle_t *hperh) +ald_status_t ald_spi_dma_resume(spi_handle_t *hperh) { assert_param(IS_SPI(hperh->perh)); __LOCK(hperh); - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); - spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); __UNLOCK(hperh); return OK; @@ -1104,13 +1148,13 @@ ald_status_t spi_dma_resume(spi_handle_t *hperh) * @param hperh: Pointer to a spi_handle_t structure. * @retval Status */ -ald_status_t spi_dma_stop(spi_handle_t *hperh) +ald_status_t ald_spi_dma_stop(spi_handle_t *hperh) { assert_param(IS_SPI(hperh->perh)); __LOCK(hperh); - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); __UNLOCK(hperh); hperh->state = SPI_STATE_READY; @@ -1130,7 +1174,7 @@ ald_status_t spi_dma_stop(spi_handle_t *hperh) =============================================================================== [..] This subsection provides a set of functions allowing to control the SPI. - (+) Handle interrupt about SPI module. The spi_irq_handle() function must + (+) Handle interrupt about SPI module. The ald_spi_irq_handler() function must be invoked by SPI-IRQ function. (+) Configure the interrupt DISABLE/ENABLE. (+) Configure the DMA request. @@ -1147,14 +1191,14 @@ ald_status_t spi_dma_stop(spi_handle_t *hperh) * @param hperh: Pointer to a spi_handle_t structure. * @retval None */ -void spi_irq_handle(spi_handle_t *hperh) +void ald_spi_irq_handler(spi_handle_t *hperh) { if ((hperh->state == SPI_STATE_BUSY_RX) || (hperh->state == SPI_STATE_BUSY_TX)) { - if ((spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) + if ((ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) __spi_recv_by_it(hperh); - if ((spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) + if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) __spi_send_by_it(hperh); } @@ -1162,43 +1206,45 @@ void spi_irq_handle(spi_handle_t *hperh) { if (hperh->tx_size == hperh->tx_count) { - if ((spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) + if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET)) __spi_send_recv_by_it(hperh, SPI_SR_TXBE); } else { - if ((spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET) - && (spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) + if ((ald_spi_get_it_status(hperh, SPI_IT_TXBE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXBE) != RESET) + && (ald_spi_get_it_status(hperh, SPI_IT_RXBNE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXBNE) != RESET)) __spi_send_recv_by_it(hperh, SPI_SR_TXBE_RXBNE); } } - if ((spi_get_it_status(hperh, SPI_IT_ERR) != RESET)) + if ((ald_spi_get_it_status(hperh, SPI_IT_ERR) != RESET)) { - if (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) { hperh->err_code |= SPI_ERROR_CRC; - spi_clear_flag_status(hperh, SPI_IF_CRCERR); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); } - if (spi_get_flag_status(hperh, SPI_IF_MODF) != RESET) + + if (ald_spi_get_flag_status(hperh, SPI_IF_MODF) != RESET) { hperh->err_code |= SPI_ERROR_MODF; - spi_clear_flag_status(hperh, SPI_IF_MODF); + ald_spi_clear_flag_status(hperh, SPI_IF_MODF); } - if (spi_get_flag_status(hperh, SPI_IF_OVE) != RESET) + + if (ald_spi_get_flag_status(hperh, SPI_IF_OVE) != RESET) { if (hperh->state != SPI_STATE_BUSY_TX) { hperh->err_code |= SPI_ERROR_OVE; - spi_clear_flag_status(hperh, SPI_IF_OVE); + ald_spi_clear_flag_status(hperh, SPI_IF_OVE); } } if (hperh->err_code != SPI_ERROR_NONE) { - spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); hperh->state = SPI_STATE_READY; if (hperh->err_cbk) @@ -1219,7 +1265,7 @@ void spi_irq_handle(spi_handle_t *hperh) * - DISABLE * @retval None */ -void spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state) +void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state) { assert_param(IS_SPI(hperh->perh)); assert_param(IS_SPI_IT(it)); @@ -1240,7 +1286,7 @@ void spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state) * This parameter can be one of the @ref spi_baud_t. * @retval None */ -void spi_speed_config(spi_handle_t *hperh, spi_baud_t speed) +void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed) { uint32_t tmp = 0; assert_param(IS_SPI(hperh->perh)); @@ -1263,7 +1309,7 @@ void spi_speed_config(spi_handle_t *hperh, spi_baud_t speed) * - DISABLE * @retval None */ -void spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state) +void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state) { assert_param(IS_SPI(hperh->perh)); assert_param(IS_SPI_DMA_REQ(req)); @@ -1287,6 +1333,25 @@ void spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t stat return; } +/** @brief Check whether the specified SPI state flag is set or not. + * @param hperh: Pointer to a spi_handle_t structure. + * @param status: specifies the flag to check. + * This parameter can be one of the @ref spi_status_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_STATUS(status)); + + if (hperh->perh->STAT & status) + return SET; + + return RESET; +} + /** * @brief Checks whether the specified SPI interrupt has occurred or not. * @param hperh: Pointer to a spi_handle_t structure. @@ -1296,7 +1361,7 @@ void spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t stat * - SET * - RESET */ -it_status_t spi_get_it_status(spi_handle_t *hperh, spi_it_t it) +it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it) { assert_param(IS_SPI(hperh->perh)); assert_param(IS_SPI_IT(it)); @@ -1315,7 +1380,7 @@ it_status_t spi_get_it_status(spi_handle_t *hperh, spi_it_t it) * - SET * - RESET */ -flag_status_t spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag) +flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag) { assert_param(IS_SPI(hperh->perh)); assert_param(IS_SPI_IF(flag)); @@ -1332,7 +1397,7 @@ flag_status_t spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag) * This parameter can be one of the @ref spi_flag_t. * @retval None */ -void spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) +void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) { uint32_t temp; @@ -1344,6 +1409,7 @@ void spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) SET_BIT(hperh->perh->STAT, SPI_STAT_CRCERR_MSK); return; } + if (flag == SPI_IF_OVE) { temp = hperh->perh->DATA; @@ -1351,6 +1417,7 @@ void spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) UNUSED(temp); return; } + if (flag == SPI_IF_MODF) { temp = hperh->perh->STAT; @@ -1372,17 +1439,17 @@ void spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) */ static ald_status_t spi_wait_flag(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout) { - uint32_t tick = __get_tick(); + uint32_t tick = ald_get_tick(); assert_param(timeout > 0); - while ((spi_get_flag_status(hperh, flag)) != status) + while ((ald_spi_get_flag_status(hperh, flag)) != status) { - if (((__get_tick()) - tick) > timeout) + if (((ald_get_tick()) - tick) > timeout) { - spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); return TIMEOUT; } } @@ -1402,14 +1469,14 @@ static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag { assert_param(timeout > 0); - while (((spi_get_flag_status(hperh, flag)) != status) && (--timeout)); + while (((ald_spi_get_flag_status(hperh, flag)) != status) && (--timeout)); if (timeout) return OK; - spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); return TIMEOUT; } @@ -1427,8 +1494,8 @@ static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag =============================================================================== [..] This subsection provides a set of functions allowing to control the SPI. - (+) spi_get_state() API can check in run-time the state of the SPI peripheral - (+) spi_get_error() check in run-time Errors occurring during communication + (+) ald_spi_get_state() API can check in run-time the state of the SPI peripheral + (+) ald_spi_get_error() check in run-time Errors occurring during communication @endverbatim * @{ @@ -1439,7 +1506,7 @@ static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag * @param hperh: Pointer to a spi_handle_t structure. * @retval ALD state */ -spi_state_t spi_get_state(spi_handle_t *hperh) +spi_state_t ald_spi_get_state(spi_handle_t *hperh) { assert_param(IS_SPI(hperh->perh)); return hperh->state; @@ -1450,7 +1517,7 @@ spi_state_t spi_get_state(spi_handle_t *hperh) * @param hperh: Pointer to a spi_handle_t structure. * @retval SPI Error Code */ -uint32_t spi_get_error(spi_handle_t *hperh) +uint32_t ald_spi_get_error(spi_handle_t *hperh) { assert_param(IS_SPI(hperh->perh)); return hperh->err_code; @@ -1477,11 +1544,11 @@ static void __spi_send_by_it(spi_handle_t *hperh) { if (hperh->tx_count == 0) { - spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); hperh->state = SPI_STATE_READY; if (hperh->init.dir == SPI_DIRECTION_2LINES) - spi_clear_flag_status(hperh, SPI_IF_OVE); + ald_spi_clear_flag_status(hperh, SPI_IF_OVE); if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) { @@ -1507,6 +1574,7 @@ static void __spi_send_by_it(spi_handle_t *hperh) hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; hperh->tx_buf += 2; } + --hperh->tx_count; if (hperh->tx_count == 0) @@ -1526,6 +1594,7 @@ static void __spi_send_by_it(spi_handle_t *hperh) static void __spi_recv_by_it(spi_handle_t *hperh) { uint16_t temp; + if (hperh->init.data_size == SPI_DATA_SIZE_8) { *hperh->rx_buf = hperh->perh->DATA; @@ -1536,6 +1605,7 @@ static void __spi_recv_by_it(spi_handle_t *hperh) *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; hperh->rx_buf += 2; } + --hperh->rx_count; if ((hperh->rx_count == 1) && (hperh->init.crc_calc)) @@ -1543,13 +1613,13 @@ static void __spi_recv_by_it(spi_handle_t *hperh) if (hperh->rx_count == 0) { - spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); hperh->state = SPI_STATE_READY; - if ((hperh->init.crc_calc) && (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { hperh->err_code |= SPI_ERROR_CRC; - spi_clear_flag_status(hperh, SPI_IF_CRCERR); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); if (hperh->err_cbk) hperh->err_cbk(hperh); @@ -1638,7 +1708,8 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status) { if (hperh->init.crc_calc) SPI_CRCNEXT_ENABLE(hperh); - spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); } } } @@ -1646,15 +1717,15 @@ static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status) if (hperh->rx_count == 0) { - spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); - spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); - spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXBE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXBNE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_ERR, DISABLE); hperh->state = SPI_STATE_READY; - if ((hperh->init.crc_calc) && (spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { hperh->err_code |= SPI_ERROR_CRC; - spi_clear_flag_status(hperh, SPI_IF_CRCERR); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); if (hperh->err_cbk) hperh->err_cbk(hperh); @@ -1682,11 +1753,11 @@ static void spi_dma_send_cplt(void *arg) spi_handle_t *hperh = (spi_handle_t *)arg; hperh->tx_count = 0; - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); hperh->state = SPI_STATE_READY; if (hperh->init.dir == SPI_DIRECTION_2LINES) - spi_clear_flag_status(hperh, SPI_IF_OVE); + ald_spi_clear_flag_status(hperh, SPI_IF_OVE); if ((spi_wait_flag_irq(hperh, SPI_IF_BUSY, RESET, 5000)) != OK) hperh->err_code |= SPI_ERROR_FLAG; @@ -1718,8 +1789,8 @@ static void spi_dma_recv_cplt(void *arg) spi_handle_t *hperh = (spi_handle_t *)arg; hperh->rx_count = 0; - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); hperh->state = SPI_STATE_READY; if (hperh->init.crc_calc) @@ -1730,11 +1801,11 @@ static void spi_dma_recv_cplt(void *arg) tmp = hperh->perh->DATA; UNUSED(tmp); - if (spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) { SET_BIT(hperh->err_code, SPI_ERROR_CRC); SPI_CRC_RESET(hperh); - spi_clear_flag_status(hperh, SPI_IF_CRCERR); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); } } @@ -1771,10 +1842,10 @@ static void spi_dma_send_recv_cplt(void *arg) tmp = hperh->perh->DATA; UNUSED(tmp); - if (spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) { SET_BIT(hperh->err_code, SPI_ERROR_CRC); - spi_clear_flag_status(hperh, SPI_IF_CRCERR); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); } } @@ -1783,8 +1854,8 @@ static void spi_dma_send_recv_cplt(void *arg) for (delay = 0; delay < 3000; delay++); - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); hperh->tx_count = 0; hperh->rx_count = 0; hperh->state = SPI_STATE_READY; @@ -1813,8 +1884,8 @@ static void spi_dma_error(void *arg) { spi_handle_t *hperh = (spi_handle_t *)arg; - spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); - spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); SET_BIT(hperh->err_code, SPI_ERROR_DMA); hperh->tx_count = 0; diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c similarity index 66% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c index d4419ebdec171548e971864828de07f3afeca44f..677bbdcf86eabab4b48eed0542015e6234580949 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_timer.c @@ -3,7 +3,7 @@ * * @file ald_timer.c * @brief TIMER module driver. - * This is the common part of the TIMER initialization + * This is the common part of the TIMER initialization * * @version V1.0 * @date 06 Nov 2017 @@ -57,6 +57,7 @@ static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t * static void timer_dma_capture_cplt(void *arg); static void timer_dma_period_elapse_cplt(void *arg); static void timer_dma_error(void *arg); + static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config); #endif /** * @} @@ -93,7 +94,7 @@ static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t * * @param hperh: TIMER base handle * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_base_init(timer_handle_t *hperh) +ald_status_t ald_timer_base_init(timer_handle_t *hperh) { if (hperh == NULL) return ERROR; @@ -117,7 +118,7 @@ ald_status_t timer_base_init(timer_handle_t *hperh) * @param hperh: TIMER base handle * @retval Status, see @ref ald_status_t. */ -void timer_base_reset(timer_handle_t *hperh) +void ald_timer_base_reset(timer_handle_t *hperh) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); @@ -134,7 +135,7 @@ void timer_base_reset(timer_handle_t *hperh) * @param hperh: TIMER handle * @retval None */ -void timer_base_start(timer_handle_t *hperh) +void ald_timer_base_start(timer_handle_t *hperh) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); @@ -150,7 +151,7 @@ void timer_base_start(timer_handle_t *hperh) * @param hperh: TIMER handle * @retval None */ -void timer_base_stop(timer_handle_t *hperh) +void ald_timer_base_stop(timer_handle_t *hperh) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); @@ -166,11 +167,11 @@ void timer_base_stop(timer_handle_t *hperh) * @param hperh: TIMER handle * @retval None */ -void timer_base_start_by_it(timer_handle_t *hperh) +void ald_timer_base_start_by_it(timer_handle_t *hperh) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); - timer_interrupt_config(hperh, TIMER_IT_UPDATE, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, ENABLE); TIMER_ENABLE(hperh); return; @@ -181,11 +182,11 @@ void timer_base_start_by_it(timer_handle_t *hperh) * @param hperh: TIMER handle * @retval None */ -void timer_base_stop_by_it(timer_handle_t *hperh) +void ald_timer_base_stop_by_it(timer_handle_t *hperh) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); - timer_interrupt_config(hperh, TIMER_IT_UPDATE, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, DISABLE); TIMER_DISABLE(hperh); return; @@ -201,13 +202,14 @@ void timer_base_stop_by_it(timer_handle_t *hperh) * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + uint16_t *buf, uint32_t len, uint8_t dma_ch) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); if ((hperh->state == TIMER_STATE_BUSY)) return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { if (((uint32_t)buf == 0) || (len == 0)) @@ -224,7 +226,7 @@ ald_status_t timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, hdma->err_cbk = timer_dma_error; hdma->err_arg = (void *)hperh; - dma_config_struct(&hdma->config); + ald_dma_config_struct(&hdma->config); hdma->config.src = (void *)buf; hdma->config.dst = (void *)&hperh->perh->AR; hdma->config.size = len; @@ -234,27 +236,9 @@ ald_status_t timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, hdma->config.msigsel = DMA_MSIGSEL_TIMER_UPDATE; hdma->config.channel = dma_ch; - if (hperh->perh == TIMER0) - hdma->config.msel = DMA_MSEL_TIMER0; - else if (hperh->perh == TIMER1) - hdma->config.msel = DMA_MSEL_TIMER1; - else if (hperh->perh == TIMER2) - hdma->config.msel = DMA_MSEL_TIMER2; - else if (hperh->perh == TIMER3) - hdma->config.msel = DMA_MSEL_TIMER3; - else if (hperh->perh == TIMER4) - hdma->config.msel = DMA_MSEL_TIMER4; - else if (hperh->perh == TIMER5) - hdma->config.msel = DMA_MSEL_TIMER5; - else if (hperh->perh == TIMER6) - hdma->config.msel = DMA_MSEL_TIMER6; - else if (hperh->perh == TIMER7) - hdma->config.msel = DMA_MSEL_TIMER7; - else - ; - - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_UPDATE, ENABLE); + timer_dma_msel(hperh->perh, &hdma->config); + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, ENABLE); TIMER_ENABLE(hperh); return OK; @@ -265,11 +249,11 @@ ald_status_t timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, * @param hperh: TIMER handle * @retval None */ -void timer_base_stop_by_dma(timer_handle_t *hperh) +void ald_timer_base_stop_by_dma(timer_handle_t *hperh) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); - timer_dma_req_config(hperh, TIMER_DMA_UPDATE, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, DISABLE); TIMER_DISABLE(hperh); hperh->state = TIMER_STATE_READY; @@ -306,9 +290,9 @@ void timer_base_stop_by_dma(timer_handle_t *hperh) * @param hperh: TIMER handle * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_oc_init(timer_handle_t *hperh) +ald_status_t ald_timer_oc_init(timer_handle_t *hperh) { - return timer_base_init(hperh); + return ald_timer_base_init(hperh); } /** @@ -322,7 +306,7 @@ ald_status_t timer_oc_init(timer_handle_t *hperh) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_oc_start(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); @@ -346,7 +330,7 @@ void timer_oc_start(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); @@ -371,30 +355,30 @@ void timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; - case TIMER_CHANNEL_2: - timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; - case TIMER_CHANNEL_3: - timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); - break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; - case TIMER_CHANNEL_4: - timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); - break; + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); + break; - default: - break; + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); @@ -417,30 +401,30 @@ void timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; - case TIMER_CHANNEL_2: - timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; - case TIMER_CHANNEL_3: - timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); - break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; - case TIMER_CHANNEL_4: - timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); - break; + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); + break; - default: - break; + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); @@ -453,29 +437,34 @@ void timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) return; } + + + + #ifdef ALD_DMA /** * @brief Starts the TIMER Output Compare signal generation in DMA mode. * @param hperh: TIMER handle * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @param hdma: Pointer to dma_handle_t. * @param buf: The source Buffer address. * @param len: The length of buffer to be transferred from memory to TIMER peripheral * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); if ((hperh->state == TIMER_STATE_BUSY)) return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { if (((uint32_t)buf == 0) || (len == 0)) @@ -492,7 +481,7 @@ ald_status_t timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, hdma->err_cbk = timer_dma_error; hdma->err_arg = (void *)hperh; - dma_config_struct(&hdma->config); + ald_dma_config_struct(&hdma->config); hdma->config.src = (void *)buf; hdma->config.size = len; hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; @@ -500,61 +489,45 @@ ald_status_t timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, hdma->config.dst_inc = DMA_DATA_INC_NONE; hdma->config.channel = dma_ch; - if (hperh->perh == TIMER0) - hdma->config.msel = DMA_MSEL_TIMER0; - else if (hperh->perh == TIMER1) - hdma->config.msel = DMA_MSEL_TIMER1; - else if (hperh->perh == TIMER2) - hdma->config.msel = DMA_MSEL_TIMER2; - else if (hperh->perh == TIMER3) - hdma->config.msel = DMA_MSEL_TIMER3; - else if (hperh->perh == TIMER4) - hdma->config.msel = DMA_MSEL_TIMER4; - else if (hperh->perh == TIMER5) - hdma->config.msel = DMA_MSEL_TIMER5; - else if (hperh->perh == TIMER6) - hdma->config.msel = DMA_MSEL_TIMER6; - else if (hperh->perh == TIMER7) - hdma->config.msel = DMA_MSEL_TIMER7; - else - ;//do nothing + + timer_dma_msel(hperh->perh, &hdma->config); switch (ch) { - case TIMER_CHANNEL_1: - hdma->config.dst = (void *)&hperh->perh->CCVAL1; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - break; - - case TIMER_CHANNEL_2: - hdma->config.dst = (void *)&hperh->perh->CCVAL2; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - break; - - case TIMER_CHANNEL_3: - hdma->config.dst = (void *)&hperh->perh->CCVAL3; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - break; - - case TIMER_CHANNEL_4: - hdma->config.dst = (void *)&hperh->perh->CCVAL4; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_4; - break; - - default: - break; + case TIMER_CHANNEL_1: + hdma->config.dst = (void *)&hperh->perh->CCVAL1; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hdma->config.dst = (void *)&hperh->perh->CCVAL2; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hdma->config.dst = (void *)&hperh->perh->CCVAL3; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + case TIMER_CHANNEL_4: + hdma->config.dst = (void *)&hperh->perh->CCVAL4; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + break; + + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); @@ -570,37 +543,37 @@ ald_status_t timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, * @brief Stops the TIMER Output Compare signal generation in DMA mode. * @param hperh: TIMER handle * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; - case TIMER_CHANNEL_2: - timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; - case TIMER_CHANNEL_3: - timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); - break; + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; - case TIMER_CHANNEL_4: - timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); - break; + case TIMER_CHANNEL_4: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); + break; - default: - break; + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); @@ -621,18 +594,18 @@ void timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @brief TIMER PWM functions * * @verbatim - ============================================================================== - ##### Time PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIMER PWM. - (+) Start the Time PWM. - (+) Stop the Time PWM. - (+) Start the Time PWM and enable interrupt. - (+) Stop the Time PWM and disable interrupt. - (+) Start the Time PWM and enable DMA transfer. - (+) Stop the Time PWM and disable DMA transfer. + ============================================================================== + ##### Time PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER PWM. + (+) Start the Time PWM. + (+) Stop the Time PWM. + (+) Start the Time PWM and enable interrupt. + (+) Stop the Time PWM and disable interrupt. + (+) Start the Time PWM and enable DMA transfer. + (+) Stop the Time PWM and disable DMA transfer. @endverbatim * @{ @@ -643,25 +616,25 @@ void timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @param hperh: TIMER handle * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_pwm_init(timer_handle_t *hperh) +ald_status_t ald_timer_pwm_init(timer_handle_t *hperh) { - return timer_base_init(hperh); + return ald_timer_base_init(hperh); } /** * @brief Starts the PWM signal generation. * @param hperh: TIMER handle * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch) { - timer_oc_start(hperh, ch); + ald_timer_oc_start(hperh, ch); return; } @@ -669,16 +642,16 @@ void timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch) * @brief Stops the PWM signal generation. * @param hperh: TIMER handle * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch) { - timer_oc_stop(hperh, ch); + ald_timer_oc_stop(hperh, ch); return; } @@ -686,16 +659,16 @@ void timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch) * @brief Starts the PWM signal generation in interrupt mode. * @param hperh: TIMER handle * @param ch: TIMER Channel to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - timer_oc_start_by_it(hperh, ch); + ald_timer_oc_start_by_it(hperh, ch); return; } @@ -703,16 +676,16 @@ void timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch) * @brief Stops the PWM signal generation in interrupt mode. * @param hperh: TIMER handle * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - timer_oc_stop_by_it(hperh, ch); + ald_timer_oc_stop_by_it(hperh, ch); return; } @@ -721,37 +694,37 @@ void timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @brief Starts the TIMER PWM signal generation in DMA mode. * @param hperh: TIMER handle * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @param hdma: Pointer to dma_handle_t. * @param buf: The source Buffer address. * @param len: The length of buffer to be transferred from memory to TIMER peripheral * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) { - return timer_oc_start_by_dma(hperh, ch, hdma, buf, len, dma_ch); + return ald_timer_oc_start_by_dma(hperh, ch, hdma, buf, len, dma_ch); } /** * @brief Stops the TIMER PWM signal generation in DMA mode. * @param hperh: TIMER handle * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { - timer_oc_stop_by_dma(hperh, ch); + ald_timer_oc_stop_by_dma(hperh, ch); return; } #endif @@ -761,9 +734,9 @@ void timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @param freq: PWM freq to set * @retval None */ -void timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq) +void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq) { - uint32_t _arr = cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1; + uint32_t _arr = ald_cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1; WRITE_REG(hperh->perh->AR, _arr); hperh->init.period = _arr; @@ -773,15 +746,15 @@ void timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq) * @brief Set the PWM duty. * @param hperh: TIMER handle * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @param duty: PWM duty to set * @retval None */ -void timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty) +void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty) { uint32_t tmp = (hperh->init.period + 1) * duty / 100 - 1; @@ -803,40 +776,43 @@ void timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty * @brief Set capture the PWM. * @param hperh: TIMER handle * @param ch: TIMER Channels to be captured the PWM - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_PWM_INPUT_INSTANCE(hperh->perh, ch)); CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + switch (ch) { - case TIMER_CHANNEL_1: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); - break; - case TIMER_CHANNEL_2: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); - break; - default: - break; + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + + default: + break; } SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); @@ -874,9 +850,9 @@ void timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch) * @param hperh: TIMER handle * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_ic_init(timer_handle_t *hperh) +ald_status_t ald_timer_ic_init(timer_handle_t *hperh) { - return timer_base_init(hperh); + return ald_timer_base_init(hperh); } /** @@ -890,7 +866,7 @@ ald_status_t timer_ic_init(timer_handle_t *hperh) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_ic_start(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); @@ -910,7 +886,7 @@ void timer_ic_start(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); @@ -930,26 +906,30 @@ void timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; - case TIMER_CHANNEL_2: - timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; - case TIMER_CHANNEL_3: - timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); - break; - case TIMER_CHANNEL_4: - timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); - break; - default: - break; + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); + break; + + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); @@ -968,26 +948,30 @@ void timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; - case TIMER_CHANNEL_2: - timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - case TIMER_CHANNEL_3: - timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); - break; - case TIMER_CHANNEL_4: - timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); - break; - default: - break; + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); + break; + + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); @@ -1000,24 +984,25 @@ void timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @brief Starts the TIMER Input Capture measurement in DMA mode. * @param hperh: TIMER handle * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @param hdma: Pointer to dma_handle_t. * @param buf: The destination Buffer address. * @param len: The length of buffer to be transferred TIMER peripheral to memory * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); if ((hperh->state == TIMER_STATE_BUSY)) return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { if (((uint32_t)buf == 0) || (len == 0)) @@ -1034,7 +1019,7 @@ ald_status_t timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, hdma->err_cbk = timer_dma_error; hdma->err_arg = (void *)hperh; - dma_config_struct(&hdma->config); + ald_dma_config_struct(&hdma->config); hdma->config.dst = (void *)buf; hdma->config.size = len; hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; @@ -1042,61 +1027,44 @@ ald_status_t timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, hdma->config.dst_inc = DMA_DATA_INC_HALFWORD; hdma->config.channel = dma_ch; - if (hperh->perh == TIMER0) - hdma->config.msel = DMA_MSEL_TIMER0; - else if (hperh->perh == TIMER1) - hdma->config.msel = DMA_MSEL_TIMER1; - else if (hperh->perh == TIMER2) - hdma->config.msel = DMA_MSEL_TIMER2; - else if (hperh->perh == TIMER3) - hdma->config.msel = DMA_MSEL_TIMER3; - else if (hperh->perh == TIMER4) - hdma->config.msel = DMA_MSEL_TIMER4; - else if (hperh->perh == TIMER5) - hdma->config.msel = DMA_MSEL_TIMER5; - else if (hperh->perh == TIMER6) - hdma->config.msel = DMA_MSEL_TIMER6; - else if (hperh->perh == TIMER7) - hdma->config.msel = DMA_MSEL_TIMER7; - else - ;/* do nothing */ + timer_dma_msel(hperh->perh, &hdma->config); switch (ch) { - case TIMER_CHANNEL_1: - hdma->config.src = (void *)&hperh->perh->CCVAL1; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - break; - - case TIMER_CHANNEL_2: - hdma->config.src = (void *)&hperh->perh->CCVAL2; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - break; - - case TIMER_CHANNEL_3: - hdma->config.src = (void *)&hperh->perh->CCVAL3; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - break; - - case TIMER_CHANNEL_4: - hdma->config.src = (void *)&hperh->perh->CCVAL4; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_4; - break; - - default: - break; + case TIMER_CHANNEL_1: + hdma->config.src = (void *)&hperh->perh->CCVAL1; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hdma->config.src = (void *)&hperh->perh->CCVAL2; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hdma->config.src = (void *)&hperh->perh->CCVAL3; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + case TIMER_CHANNEL_4: + hdma->config.src = (void *)&hperh->perh->CCVAL4; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + break; + + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); @@ -1108,33 +1076,37 @@ ald_status_t timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, * @brief Stops the TIMER Input Capture measurement in DMA mode. * @param hperh: TIMER handle * @param ch: TIMER Channels to be disabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval None */ -void timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; - case TIMER_CHANNEL_2: - timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - case TIMER_CHANNEL_3: - timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); - break; - case TIMER_CHANNEL_4: - timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); - break; - default: - break; + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + + case TIMER_CHANNEL_4: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); + break; + + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); @@ -1177,7 +1149,7 @@ void timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_OP_MODE_REPEAT: Repetitive pulses wil be generated. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode) +ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode) { if (hperh == NULL) return ERROR; @@ -1207,7 +1179,7 @@ ald_status_t timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode) * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch) +void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch) { /* Enable the Capture compare and the Input Capture channels * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) @@ -1233,7 +1205,7 @@ void timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch) * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch) +void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch) { timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); @@ -1254,7 +1226,7 @@ void timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch) * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) +void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) { /* Enable the Capture compare and the Input Capture channels * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) @@ -1262,8 +1234,8 @@ void timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_ * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together */ - timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); @@ -1282,10 +1254,10 @@ void timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_ * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) +void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) { - timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); @@ -1303,18 +1275,18 @@ void timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t * @brief TIMER Encoder functions * * @verbatim - ============================================================================== - ##### Time Encoder functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIMER Encoder. - (+) Start the Time Encoder. - (+) Stop the Time Encoder. - (+) Start the Time Encoder and enable interrupt. - (+) Stop the Time Encoder and disable interrupt. - (+) Start the Time Encoder and enable DMA transfer. - (+) Stop the Time Encoder and disable DMA transfer. + ============================================================================== + ##### Time Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Encoder. + (+) Start the Time Encoder. + (+) Stop the Time Encoder. + (+) Start the Time Encoder and enable interrupt. + (+) Stop the Time Encoder and disable interrupt. + (+) Start the Time Encoder and enable DMA transfer. + (+) Stop the Time Encoder and disable DMA transfer. * @endverbatim * @{ @@ -1325,7 +1297,7 @@ void timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t * @param config: TIMER Encoder Interface configuration structure * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config) +ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config) { if (hperh == NULL) return ERROR; @@ -1374,22 +1346,24 @@ ald_status_t timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *co * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected * @retval None */ -void timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); switch (ch) { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - break; - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - break; - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - break; + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + break; + + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + break; + + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + break; } TIMER_ENABLE(hperh); @@ -1406,22 +1380,24 @@ void timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected * @retval None */ -void timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); switch (ch) { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - break; - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - break; - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - break; + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + break; + + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + break; + + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + break; } TIMER_DISABLE(hperh); @@ -1438,26 +1414,28 @@ void timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected * @retval None */ -void timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); switch (ch) { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; } TIMER_ENABLE(hperh); @@ -1474,26 +1452,28 @@ void timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected * @retval None */ -void timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); switch (ch) { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; } TIMER_DISABLE(hperh); @@ -1519,14 +1499,15 @@ void timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @param dma_ch2: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, - uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2) +ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, + uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); if ((hperh->state == TIMER_STATE_BUSY)) return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { if (((uint32_t)buf1 == 0) || ((uint32_t)buf2 == 0) || (len == 0)) @@ -1535,6 +1516,7 @@ ald_status_t timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t c if (hdma1->perh == NULL) hdma1->perh = DMA0; + if (hdma2->perh == NULL) hdma2->perh = DMA0; @@ -1544,80 +1526,63 @@ ald_status_t timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t c hdma1->err_cbk = timer_dma_error; hdma1->err_arg = (void *)hperh; - dma_config_struct(&hdma1->config); + ald_dma_config_struct(&hdma1->config); hdma1->config.size = len; hdma1->config.data_width = DMA_DATA_SIZE_HALFWORD; hdma1->config.src_inc = DMA_DATA_INC_NONE; hdma1->config.dst_inc = DMA_DATA_INC_HALFWORD; - if (hperh->perh == TIMER0) - hdma1->config.msel = DMA_MSEL_TIMER0; - else if (hperh->perh == TIMER1) - hdma1->config.msel = DMA_MSEL_TIMER1; - else if (hperh->perh == TIMER2) - hdma1->config.msel = DMA_MSEL_TIMER2; - else if (hperh->perh == TIMER3) - hdma1->config.msel = DMA_MSEL_TIMER3; - else if (hperh->perh == TIMER4) - hdma1->config.msel = DMA_MSEL_TIMER4; - else if (hperh->perh == TIMER5) - hdma1->config.msel = DMA_MSEL_TIMER5; - else if (hperh->perh == TIMER6) - hdma1->config.msel = DMA_MSEL_TIMER6; - else if (hperh->perh == TIMER7) - hdma1->config.msel = DMA_MSEL_TIMER7; - else - ;/* do nothing */ + timer_dma_msel(hperh->perh, &hdma1->config); switch (ch) { - case TIMER_CHANNEL_1: - hdma1->config.src = (void *)&hperh->perh->CCVAL1; - hdma1->config.dst = (void *)buf1; - hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - hdma1->config.channel = dma_ch1; - dma_config_basic(hdma1); - timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - TIMER_ENABLE(hperh); - break; - - case TIMER_CHANNEL_2: - hdma1->config.src = (void *)&hperh->perh->CCVAL2; - hdma1->config.dst = (void *)buf2; - hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - hdma1->config.channel = dma_ch2; - dma_config_basic(hdma1); - timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - TIMER_ENABLE(hperh); - break; - - default: - hdma2->cplt_cbk = timer_dma_capture_cplt; - hdma2->cplt_arg = (void *)hperh; - hdma2->err_cbk = timer_dma_error; - hdma2->err_arg = (void *)hperh; - memcpy(&hdma2->config, &hdma1->config, sizeof(dma_config_t)); - - hdma1->config.src = (void *)&hperh->perh->CCVAL1; - hdma1->config.dst = (void *)buf1; - hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - hdma1->config.channel = dma_ch1; - dma_config_basic(hdma1); - timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - - hdma2->config.src = (void *)&hperh->perh->CCVAL2; - hdma2->config.dst = (void *)buf2; - hdma2->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - hdma2->config.channel = dma_ch2; - dma_config_basic(hdma2); - timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); - TIMER_ENABLE(hperh); - break; + case TIMER_CHANNEL_1: + hdma1->config.src = (void *)&hperh->perh->CCVAL1; + hdma1->config.dst = (void *)buf1; + hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hdma1->config.channel = dma_ch1; + ald_dma_config_basic(hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); + break; + + case TIMER_CHANNEL_2: + hdma1->config.src = (void *)&hperh->perh->CCVAL2; + hdma1->config.dst = (void *)buf2; + hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + hdma1->config.channel = dma_ch2; + ald_dma_config_basic(hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + TIMER_ENABLE(hperh); + break; + + default: + hdma2->cplt_cbk = timer_dma_capture_cplt; + hdma2->cplt_arg = (void *)hperh; + hdma2->err_cbk = timer_dma_error; + hdma2->err_arg = (void *)hperh; + memcpy(&hdma2->config, &hdma1->config, sizeof(dma_config_t)); + + hdma1->config.src = (void *)&hperh->perh->CCVAL1; + hdma1->config.dst = (void *)buf1; + hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hdma1->config.channel = dma_ch1; + ald_dma_config_basic(hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + + hdma2->config.src = (void *)&hperh->perh->CCVAL2; + hdma2->config.dst = (void *)buf2; + hdma2->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + hdma2->config.channel = dma_ch2; + ald_dma_config_basic(hdma2); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + TIMER_ENABLE(hperh); + break; } return OK; @@ -1633,26 +1598,28 @@ ald_status_t timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t c * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected * @retval None */ -void timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); switch (ch) { - case TIMER_CHANNEL_1: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; - case TIMER_CHANNEL_2: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - default: - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); - timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; } TIMER_DISABLE(hperh); @@ -1668,18 +1635,18 @@ void timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @brief TIMER Hall Sensor functions * * @verbatim - ============================================================================== - ##### Time Hall Sensor functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIMER hall sensor. - (+) Start the hall sensor. - (+) Stop the hall sensor. - (+) Start the hall sensor and enable interrupt. - (+) Stop the hall sensor and disable interrupt. - (+) Start the hall sensor and enable DMA transfer. - (+) Stop the hal sensor and disable DMA transfer. + ============================================================================== + ##### Time Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER hall sensor. + (+) Start the hall sensor. + (+) Stop the hall sensor. + (+) Start the hall sensor and enable interrupt. + (+) Stop the hall sensor and disable interrupt. + (+) Start the hall sensor and enable DMA transfer. + (+) Stop the hal sensor and disable DMA transfer. * @endverbatim * @{ @@ -1690,7 +1657,7 @@ void timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @param config: TIMER Encoder Interface configuration structure * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config) +ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config) { timer_oc_init_t oc; @@ -1730,7 +1697,7 @@ ald_status_t timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_in * @param hperh: TIMER handle * @retval None */ -void timer_hall_sensor_start(timer_handle_t *hperh) +void ald_timer_hall_sensor_start(timer_handle_t *hperh) { assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); @@ -1745,7 +1712,7 @@ void timer_hall_sensor_start(timer_handle_t *hperh) * @param hperh: TIMER handle * @retval None */ -void timer_hall_sensor_stop(timer_handle_t *hperh) +void ald_timer_hall_sensor_stop(timer_handle_t *hperh) { assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); @@ -1760,11 +1727,11 @@ void timer_hall_sensor_stop(timer_handle_t *hperh) * @param hperh: TIMER handle * @retval None */ -void timer_hall_sensor_start_by_it(timer_handle_t *hperh) +void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh) { assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); TIMER_ENABLE(hperh); @@ -1776,12 +1743,12 @@ void timer_hall_sensor_start_by_it(timer_handle_t *hperh) * @param hperh: TIMER handle * @retval None */ -void timer_hall_sensor_stop_by_it(timer_handle_t *hperh) +void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh) { assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); - timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); TIMER_DISABLE(hperh); return; @@ -1797,13 +1764,14 @@ void timer_hall_sensor_stop_by_it(timer_handle_t *hperh) * @param dma_ch: Channel of DMA. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, +ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) { assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); if ((hperh->state == TIMER_STATE_BUSY)) return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { if (((uint32_t)buf == 0) || (len == 0)) @@ -1819,25 +1787,20 @@ ald_status_t timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t hdma->err_cbk = timer_dma_error; hdma->err_arg = (void *)hperh; - dma_config_struct(&hdma->config); + ald_dma_config_struct(&hdma->config); hdma->config.size = len; hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; hdma->config.src_inc = DMA_DATA_INC_NONE; hdma->config.dst_inc = DMA_DATA_INC_HALFWORD; - if (hperh->perh == TIMER0) - hdma->config.msel = DMA_MSEL_TIMER0; - else if (hperh->perh == TIMER6) - hdma->config.msel = DMA_MSEL_TIMER6; - else - ;/* do nothing */ + timer_dma_msel(hperh->perh, &hdma->config); hdma->config.src = (void *)&hperh->perh->CCVAL1; hdma->config.dst = (void *)buf; hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; hdma->config.channel = dma_ch; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); TIMER_ENABLE(hperh); @@ -1848,11 +1811,11 @@ ald_status_t timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t * @param hperh: TIMER handle * @retval None */ -void timer_hall_sensor_stop_by_dma(timer_handle_t *hperh) +void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh) { assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); - timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); TIMER_DISABLE(hperh); @@ -1867,17 +1830,17 @@ void timer_hall_sensor_stop_by_dma(timer_handle_t *hperh) * @brief TIMER complementary output compare functions * * @verbatim - ============================================================================== - ##### Time complementary output compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Time complementary output compare. - (+) Stop the Time complementary output compare. - (+) Start the Time complementary output compare and enable interrupt. - (+) Stop the Time complementary output compare and disable interrupt. - (+) Start the Time complementary output compare and enable DMA transfer. - (+) Stop the Time complementary output compare and disable DMA transfer. + ============================================================================== + ##### Time complementary output compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary output compare. + (+) Stop the Time complementary output compare. + (+) Start the Time complementary output compare and enable interrupt. + (+) Stop the Time complementary output compare and disable interrupt. + (+) Start the Time complementary output compare and enable DMA transfer. + (+) Stop the Time complementary output compare and disable DMA transfer. * @endverbatim * @{ @@ -1893,7 +1856,7 @@ void timer_hall_sensor_stop_by_dma(timer_handle_t *hperh) * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); @@ -1914,7 +1877,7 @@ void timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); @@ -1936,28 +1899,29 @@ void timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); - break; - - case TIMER_CHANNEL_2: - timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); - break; - - case TIMER_CHANNEL_3: - timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); - break; - default: - break; + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + + default: + break; } - timer_interrupt_config(hperh, TIMER_IT_BREAK, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, ENABLE); timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); TIMER_MOE_ENABLE(hperh); TIMER_ENABLE(hperh); @@ -1976,32 +1940,33 @@ void timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); - break; - - case TIMER_CHANNEL_2: - timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); - break; - - case TIMER_CHANNEL_3: - timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); - break; - default: - break; + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + + default: + break; } if ((!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1NEN_MSK))) && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2NEN_MSK))) && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC3NEN_MSK)))) { - timer_interrupt_config(hperh, TIMER_IT_BREAK, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, DISABLE); } timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); @@ -2027,13 +1992,14 @@ void timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @param dma_ch: Channel of DMA. * @retval None */ -ald_status_t timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) { assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); if ((hperh->state == TIMER_STATE_BUSY)) return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { if (((uint32_t)buf == 0) || (len == 0)) @@ -2050,7 +2016,7 @@ ald_status_t timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, hdma->err_cbk = timer_dma_error; hdma->err_arg = (void *)hperh; - dma_config_struct(&hdma->config); + ald_dma_config_struct(&hdma->config); hdma->config.src = (void *)buf; hdma->config.size = len; hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; @@ -2061,32 +2027,32 @@ ald_status_t timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, switch (ch) { - case TIMER_CHANNEL_1: - hdma->config.dst = (void *)&hperh->perh->CCVAL1; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_1; - break; - - case TIMER_CHANNEL_2: - hdma->config.dst = (void *)&hperh->perh->CCVAL2; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_2; - break; - - case TIMER_CHANNEL_3: - hdma->config.dst = (void *)&hperh->perh->CCVAL3; - hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; - dma_config_basic(hdma); - timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); - hperh->ch = TIMER_ACTIVE_CHANNEL_3; - break; - - default: - break; + case TIMER_CHANNEL_1: + hdma->config.dst = (void *)&hperh->perh->CCVAL1; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hdma->config.dst = (void *)&hperh->perh->CCVAL2; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hdma->config.dst = (void *)&hperh->perh->CCVAL3; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + default: + break; } timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); @@ -2107,25 +2073,26 @@ ald_status_t timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); switch (ch) { - case TIMER_CHANNEL_1: - timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); - break; - - case TIMER_CHANNEL_2: - timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); - break; - - case TIMER_CHANNEL_3: - timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); - break; - default: - break; + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + + default: + break; } timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); @@ -2143,17 +2110,17 @@ void timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @brief TIMER complementary PWM functions * * @verbatim - ============================================================================== - ##### Time complementary PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Time complementary PWM. - (+) Stop the Time complementary PWM. - (+) Start the Time complementary PWM and enable interrupt. - (+) Stop the Time complementary PWM and disable interrupt. - (+) Start the Time complementary PWM and enable DMA transfer. - (+) Stop the Time complementary PWM and disable DMA transfer. + ============================================================================== + ##### Time complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary PWM. + (+) Stop the Time complementary PWM. + (+) Start the Time complementary PWM and enable interrupt. + (+) Stop the Time complementary PWM and disable interrupt. + (+) Start the Time complementary PWM and enable DMA transfer. + (+) Stop the Time complementary PWM and disable DMA transfer. * @endverbatim * @{ @@ -2169,9 +2136,9 @@ void timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_start(hperh, ch); + ald_timer_ocn_start(hperh, ch); } /** @@ -2184,9 +2151,9 @@ void timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_stop(hperh, ch); + ald_timer_ocn_stop(hperh, ch); } /** @@ -2200,9 +2167,9 @@ void timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_start_by_it(hperh, ch); + ald_timer_ocn_start_by_it(hperh, ch); } /** @@ -2216,9 +2183,9 @@ void timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_stop_by_it(hperh, ch); + ald_timer_ocn_stop_by_it(hperh, ch); } #ifdef ALD_DMA @@ -2237,10 +2204,10 @@ void timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @param dma_ch: Channel of DMA. * @retval None */ -ald_status_t timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) { - return timer_ocn_start_by_dma(hperh, hdma, ch, buf, len, dma_ch); + return ald_timer_ocn_start_by_dma(hperh, hdma, ch, buf, len, dma_ch); } /** @@ -2254,9 +2221,9 @@ ald_status_t timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected * @retval None */ -void timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_stop_by_dma(hperh, ch); + ald_timer_ocn_stop_by_dma(hperh, ch); } #endif /** @@ -2267,15 +2234,15 @@ void timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @brief TIMER complementary one pulse functions * * @verbatim - ============================================================================== - ##### Time complementary one pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Time complementary one pulse. - (+) Stop the Time complementary one pulse. - (+) Start the Time complementary one pulse and enable interrupt. - (+) Stop the Time complementary one pulse and disable interrupt. + ============================================================================== + ##### Time complementary one pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary one pulse. + (+) Stop the Time complementary one pulse. + (+) Start the Time complementary one pulse and enable interrupt. + (+) Stop the Time complementary one pulse and disable interrupt. * @endverbatim * @{ @@ -2290,9 +2257,9 @@ void timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_start(hperh, ch); + ald_timer_ocn_start(hperh, ch); } /** @@ -2304,9 +2271,9 @@ void timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_stop(hperh, ch); + ald_timer_ocn_stop(hperh, ch); } /** @@ -2319,9 +2286,9 @@ void timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_start_by_it(hperh, ch); + ald_timer_ocn_start_by_it(hperh, ch); } /** @@ -2334,9 +2301,9 @@ void timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @retval None */ -void timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) { - timer_ocn_stop_by_it(hperh, ch); + ald_timer_ocn_stop_by_it(hperh, ch); } /** * @} @@ -2371,14 +2338,14 @@ void timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) * @param hperh: TIMER handle * @param config: TIMER Output Compare configuration structure * @param ch: TIMER Channels to be enabled - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected - * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected - * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected - * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch) +ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch) { assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); assert_param(IS_TIMER_OC_MODE(config->oc_mode)); @@ -2389,24 +2356,24 @@ ald_status_t timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *con switch (ch) { - case TIMER_CHANNEL_1: - timer_oc1_set_config(hperh->perh, config); - break; + case TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, config); + break; - case TIMER_CHANNEL_2: - timer_oc2_set_config(hperh->perh, config); - break; + case TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, config); + break; - case TIMER_CHANNEL_3: - timer_oc3_set_config(hperh->perh, config); - break; + case TIMER_CHANNEL_3: + timer_oc3_set_config(hperh->perh, config); + break; - case TIMER_CHANNEL_4: - timer_oc4_set_config(hperh->perh, config); - break; + case TIMER_CHANNEL_4: + timer_oc4_set_config(hperh->perh, config); + break; - default: - break; + default: + break; } hperh->state = TIMER_STATE_READY; @@ -2427,7 +2394,7 @@ ald_status_t timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *con * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch) +ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); assert_param(IS_TIMER_IC_POLARITY(config->polarity)); @@ -2440,28 +2407,28 @@ ald_status_t timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *con switch (ch) { - case TIMER_CHANNEL_1: - timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); - break; - - case TIMER_CHANNEL_2: - timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS); - break; - - case TIMER_CHANNEL_3: - timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS); - break; - - case TIMER_CHANNEL_4: - timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS); - break; - - default: - break; + case TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); + break; + + case TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS); + break; + + case TIMER_CHANNEL_3: + timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS); + break; + + case TIMER_CHANNEL_4: + timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS); + break; + + default: + break; } hperh->state = TIMER_STATE_READY; @@ -2484,7 +2451,7 @@ ald_status_t timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *con * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, +ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, timer_channel_t ch_out, timer_channel_t ch_in) { timer_oc_init_t tmp; @@ -2514,33 +2481,36 @@ ald_status_t timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pul switch (ch_out) { - case TIMER_CHANNEL_1: - timer_oc1_set_config(hperh->perh, &tmp); - break; - case TIMER_CHANNEL_2: - timer_oc2_set_config(hperh->perh, &tmp); - break; - default: - break; + case TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, &tmp); + break; + + case TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, &tmp); + break; + + default: + break; } switch (ch_in) { - case TIMER_CHANNEL_1: - timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); - CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_CHANNEL_2: - timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); - CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); - break; - default: - break; + case TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + + default: + break; } hperh->state = TIMER_STATE_READY; @@ -2561,7 +2531,7 @@ ald_status_t timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pul * @arg TIMER_CHANNEL_4: TIMER Channel 4 * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch) +ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); assert_param(IS_FUNC_STATE(config->state)); @@ -2582,26 +2552,26 @@ ald_status_t timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_ switch (ch) { - case TIMER_CHANNEL_1: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS); - break; - - case TIMER_CHANNEL_2: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS); - break; - - case TIMER_CHANNEL_3: - assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS); - break; - - case TIMER_CHANNEL_4: - assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS); - break; - - default: - break; + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS); + break; + + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS); + break; + + case TIMER_CHANNEL_3: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS); + break; + + case TIMER_CHANNEL_4: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS); + break; + + default: + break; } return OK; @@ -2614,7 +2584,7 @@ ald_status_t timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_ * contains the clock source information for the TIMER peripheral. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config) +ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_CLOCK_SOURCE(config->source)); @@ -2628,60 +2598,61 @@ ald_status_t timer_config_clock_source(timer_handle_t *hperh, timer_clock_config switch (config->source) { - case TIMER_SRC_INTER: - CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); - break; - - case TIMER_SRC_ETRMODE1: - timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ETRMODE2: - timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); - SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK); - break; - - case TIMER_SRC_TI1: - timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_TI2: - timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_TI1ED: - timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR0: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR1: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR2: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - - case TIMER_SRC_ITR3: - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS); - MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); - break; - default: - break; + case TIMER_SRC_INTER: + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + break; + + case TIMER_SRC_ETRMODE1: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ETRMODE2: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK); + break; + + case TIMER_SRC_TI1: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_TI2: + timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_TI1ED: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR0: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR1: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR2: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR3: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + default: + break; } hperh->state = TIMER_STATE_READY; @@ -2701,7 +2672,7 @@ ald_status_t timer_config_clock_source(timer_handle_t *hperh, timer_clock_config * pins are connected to the TI1 input (XOR combination) * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select) +ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); @@ -2718,7 +2689,7 @@ ald_status_t timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select) * mode (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config) +ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_SLAVE_MODE(config->mode)); @@ -2731,8 +2702,8 @@ ald_status_t timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t hperh->state = TIMER_STATE_BUSY; timer_slave_set_config(hperh, config); - timer_interrupt_config(hperh, TIMER_IT_TRIGGER, DISABLE); - timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); hperh->state = TIMER_STATE_READY; __UNLOCK(hperh); @@ -2748,7 +2719,7 @@ ald_status_t timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t * mode (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config) +ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_SLAVE_MODE(config->mode)); @@ -2761,8 +2732,8 @@ ald_status_t timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_co hperh->state = TIMER_STATE_BUSY; timer_slave_set_config(hperh, config); - timer_interrupt_config(hperh, TIMER_IT_TRIGGER, ENABLE); - timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, ENABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); hperh->state = TIMER_STATE_READY; __UNLOCK(hperh); @@ -2775,7 +2746,7 @@ ald_status_t timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_co * @param event: specifies the event source. * @retval Status, see @ref ald_status_t. */ -ald_status_t timer_generate_event(timer_handle_t *hperh, timer_event_source_t event) +ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_t event) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_EVENT_SOURCE(event)); @@ -2800,7 +2771,7 @@ ald_status_t timer_generate_event(timer_handle_t *hperh, timer_event_source_t ev * @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected * @retval Captured value */ -uint32_t timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) +uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) { uint32_t tmp; @@ -2809,20 +2780,24 @@ uint32_t timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) switch (ch) { - case TIMER_CHANNEL_1: - tmp = hperh->perh->CCVAL1; - break; - case TIMER_CHANNEL_2: - tmp = hperh->perh->CCVAL2; - break; - case TIMER_CHANNEL_3: - tmp = hperh->perh->CCVAL3; - break; - case TIMER_CHANNEL_4: - tmp = hperh->perh->CCVAL4; - break; - default: - break; + case TIMER_CHANNEL_1: + tmp = hperh->perh->CCVAL1; + break; + + case TIMER_CHANNEL_2: + tmp = hperh->perh->CCVAL2; + break; + + case TIMER_CHANNEL_3: + tmp = hperh->perh->CCVAL3; + break; + + case TIMER_CHANNEL_4: + tmp = hperh->perh->CCVAL4; + break; + + default: + break; } hperh->state = TIMER_STATE_READY; @@ -2842,7 +2817,7 @@ uint32_t timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) * @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected * @retval None */ -void timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch) +void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch) { assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); assert_param(IS_TIMER_OC_MODE(mode)); @@ -2850,20 +2825,24 @@ void timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_ch switch (ch) { - case TIMER_CHANNEL_1: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS); - break; - case TIMER_CHANNEL_2: - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS); - break; - case TIMER_CHANNEL_3: - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS); - break; - case TIMER_CHANNEL_4: - MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS); - break; - default: - break; + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS); + break; + + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS); + break; + + case TIMER_CHANNEL_3: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS); + break; + + case TIMER_CHANNEL_4: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS); + break; + + default: + break; } return; @@ -2875,7 +2854,7 @@ void timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_ch * @param config: Parameters of the channel. * @retval None */ -void timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config) +void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config) { uint32_t cm1, cm2, cce; @@ -2932,7 +2911,7 @@ void timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t * * @arg DISABLE: Commutation event source is set by software using the COMG bit * @retval None */ -void timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) +void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) { assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); assert_param(IS_TIMER_TS(ts)); @@ -2961,10 +2940,10 @@ void timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t tr * @arg DISABLE: Commutation event source is set by software using the COMG bit * @retval None */ -void timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) +void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) { - timer_com_event_config(hperh, ts, trgi); - timer_interrupt_config(hperh, TIMER_IT_COM, ENABLE); + ald_timer_com_event_config(hperh, ts, trgi); + ald_timer_interrupt_config(hperh, TIMER_IT_COM, ENABLE); } /** @@ -2973,7 +2952,7 @@ void timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t * @param config: Pointer to the timer_break_dead_timere_t structure. * @retval None */ -void timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config) +void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config) { uint32_t tmp; @@ -3006,7 +2985,7 @@ void timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t * @param config: Pointer to the timer_master_config_t structure. * @retval None */ -void timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config) +void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_MASTER_MODE_SEL(config->sel)); @@ -3025,14 +3004,14 @@ void timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *conf * @param hperh: TIMER handle * @retval None */ -void timer_irq_handle(timer_handle_t *hperh) +void ald_timer_irq_handler(timer_handle_t *hperh) { uint32_t reg = hperh->perh->IFM; /* Capture or compare 1 event */ if (READ_BIT(reg, TIMER_FLAG_CC1)) { - timer_clear_flag_status(hperh, TIMER_FLAG_CC1); + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC1); hperh->ch = TIMER_ACTIVE_CHANNEL_1; /* Input capture event */ @@ -3041,20 +3020,22 @@ void timer_irq_handle(timer_handle_t *hperh) if (hperh->capture_cbk) hperh->capture_cbk(hperh); } - else /* Output compare event */ + else /* Output compare event */ { if (hperh->delay_elapse_cbk) hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) hperh->pwm_pulse_finish_cbk(hperh); } hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; } + /* Capture or compare 2 event */ if (READ_BIT(reg, TIMER_FLAG_CC2)) { - timer_clear_flag_status(hperh, TIMER_FLAG_CC2); + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC2); hperh->ch = TIMER_ACTIVE_CHANNEL_2; /* Input capture event */ @@ -3063,20 +3044,22 @@ void timer_irq_handle(timer_handle_t *hperh) if (hperh->capture_cbk) hperh->capture_cbk(hperh); } - else /* Output compare event */ + else /* Output compare event */ { if (hperh->delay_elapse_cbk) hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) hperh->pwm_pulse_finish_cbk(hperh); } hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; } + /* Capture or compare 3 event */ if (READ_BIT(reg, TIMER_FLAG_CC3)) { - timer_clear_flag_status(hperh, TIMER_FLAG_CC3); + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC3); hperh->ch = TIMER_ACTIVE_CHANNEL_3; /* Input capture event */ @@ -3085,20 +3068,22 @@ void timer_irq_handle(timer_handle_t *hperh) if (hperh->capture_cbk) hperh->capture_cbk(hperh); } - else /* Output compare event */ + else /* Output compare event */ { if (hperh->delay_elapse_cbk) hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) hperh->pwm_pulse_finish_cbk(hperh); } hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; } + /* Capture or compare 4 event */ if (READ_BIT(reg, TIMER_FLAG_CC4)) { - timer_clear_flag_status(hperh, TIMER_FLAG_CC4); + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC4); hperh->ch = TIMER_ACTIVE_CHANNEL_4; /* Input capture event */ @@ -3107,10 +3092,11 @@ void timer_irq_handle(timer_handle_t *hperh) if (hperh->capture_cbk) hperh->capture_cbk(hperh); } - else /* Output compare event */ + else /* Output compare event */ { if (hperh->delay_elapse_cbk) hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) hperh->pwm_pulse_finish_cbk(hperh); } @@ -3121,7 +3107,7 @@ void timer_irq_handle(timer_handle_t *hperh) /* TIMER Update event */ if (READ_BIT(reg, TIMER_FLAG_UPDATE)) { - timer_clear_flag_status(hperh, TIMER_FLAG_UPDATE); + ald_timer_clear_flag_status(hperh, TIMER_FLAG_UPDATE); if (hperh->period_elapse_cbk) hperh->period_elapse_cbk(hperh); @@ -3130,7 +3116,7 @@ void timer_irq_handle(timer_handle_t *hperh) /* TIMER Break input event */ if (READ_BIT(reg, TIMER_FLAG_BREAK)) { - timer_clear_flag_status(hperh, TIMER_FLAG_BREAK); + ald_timer_clear_flag_status(hperh, TIMER_FLAG_BREAK); if (hperh->break_cbk) hperh->break_cbk(hperh); @@ -3139,7 +3125,7 @@ void timer_irq_handle(timer_handle_t *hperh) /* TIMER Trigger detection event */ if (READ_BIT(reg, TIMER_FLAG_TRIGGER)) { - timer_clear_flag_status(hperh, TIMER_FLAG_TRIGGER); + ald_timer_clear_flag_status(hperh, TIMER_FLAG_TRIGGER); if (hperh->trigger_cbk) hperh->trigger_cbk(hperh); @@ -3148,7 +3134,7 @@ void timer_irq_handle(timer_handle_t *hperh) /* TIMER commutation event */ if (READ_BIT(reg, TIMER_FLAG_COM)) { - timer_clear_flag_status(hperh, TIMER_FLAG_COM); + ald_timer_clear_flag_status(hperh, TIMER_FLAG_COM); if (hperh->com_cbk) hperh->com_cbk(hperh); @@ -3164,7 +3150,7 @@ void timer_irq_handle(timer_handle_t *hperh) * @param state: New state of the specified DMA request. * @retval None */ -void timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state) +void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_DMA_REQ(req)); @@ -3189,7 +3175,7 @@ void timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_ * @arg DISABLE * @retval None */ -void timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state) +void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_IT(it)); @@ -3212,7 +3198,7 @@ void timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t st * - 0: RESET * - 1: SET */ -it_status_t timer_get_it_status(timer_handle_t *hperh, timer_it_t it) +it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_IT(it)); @@ -3232,7 +3218,7 @@ it_status_t timer_get_it_status(timer_handle_t *hperh, timer_it_t it) * - 0: RESET * - 1: SET */ -flag_status_t timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag) +flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_FLAG(flag)); @@ -3250,7 +3236,7 @@ flag_status_t timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag) * This parameter can be one of the @ref timer_flag_t. * @retval None */ -void timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag) +void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag) { assert_param(IS_TIMER_INSTANCE(hperh->perh)); assert_param(IS_TIMER_FLAG(flag)); @@ -3282,7 +3268,7 @@ void timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag) * @param hperh: TIMER handle * @retval TIMER peripheral state */ -timer_state_t timer_get_state(timer_handle_t *hperh) +timer_state_t ald_timer_get_state(timer_handle_t *hperh) { return hperh->state; } @@ -3359,6 +3345,7 @@ void timer_dma_error(void *arg) timer_handle_t *hperh = (timer_handle_t *)arg; hperh->state = TIMER_STATE_READY; + if (hperh->error_cbk) hperh->error_cbk(hperh); @@ -3525,11 +3512,11 @@ static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_conf * @brief Enables or disables the TIMER Capture Compare Channel x. * @param TIMERx: Select the TIMER peripheral * @param ch: specifies the TIMER Channel - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 - * @arg TIMER_CHANNEL_2: TIMER Channel 2 - * @arg TIMER_CHANNEL_3: TIMER Channel 3 - * @arg TIMER_CHANNEL_4: TIMER Channel 4 + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @arg TIMER_CHANNEL_4: TIMER Channel 4 * @param state: specifies the TIMER Channel CCxE bit new state. * @retval None */ @@ -3540,34 +3527,34 @@ static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, typ switch (ch) { - case TIMER_CHANNEL_1: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS); - break; + case TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS); + break; - case TIMER_CHANNEL_2: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS); - break; + case TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS); + break; - case TIMER_CHANNEL_3: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS); - break; + case TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS); + break; - case TIMER_CHANNEL_4: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS); - break; + case TIMER_CHANNEL_4: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS); + break; - default: - break; + default: + break; } } /** * @brief Enables or disables the TIMER Capture Compare Channel xN. * @param TIMERx: Select the TIMER peripheral * @param ch: specifies the TIMER Channel - * This parameter can be one of the following values: - * @arg TIMER_CHANNEL_1: TIMER Channel 1 - * @arg TIMER_CHANNEL_2: TIMER Channel 2 - * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 * @param state: specifies the TIMER Channel CCxNE bit new state. * @retval None */ @@ -3575,20 +3562,20 @@ static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, ty { switch (ch) { - case TIMER_CHANNEL_1: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK, state << TIMER_CCEP_CC1NEN_POS); - break; + case TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK, state << TIMER_CCEP_CC1NEN_POS); + break; - case TIMER_CHANNEL_2: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK, state << TIMER_CCEP_CC2NEN_POS); - break; + case TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK, state << TIMER_CCEP_CC2NEN_POS); + break; - case TIMER_CHANNEL_3: - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK, state << TIMER_CCEP_CC3NEN_POS); - break; + case TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK, state << TIMER_CCEP_CC3NEN_POS); + break; - default: - break; + default: + break; } } @@ -3608,8 +3595,7 @@ static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, sel << TIMER_CHMR1_CC1SSEL_POSS); MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); return; } @@ -3625,8 +3611,8 @@ static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter) { MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC1POL_POS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); + return; } @@ -3646,8 +3632,8 @@ static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, sel << TIMER_CHMR1_CC2SSEL_POSS); MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); + return; } @@ -3663,8 +3649,7 @@ static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter) { MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC2POL_POS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); return; } @@ -3683,8 +3668,7 @@ static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, sel << TIMER_CHMR2_CC3SSEL_POSS); MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, filter << TIMER_CHMR2_I3FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC3POL_POS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, ((polarity >> 1) & 0x1) << TIMER_CCEP_CC3NPOL_POS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, polarity << TIMER_CCEP_CC3POL_POS); return; } @@ -3704,8 +3688,7 @@ static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t pola CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, sel << TIMER_CHMR2_CC4SSEL_POSS); MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, filter << TIMER_CHMR2_I4FLT_POSS); - MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, (polarity & 0x1) << TIMER_CCEP_CC4POL_POS); - + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, polarity << TIMER_CCEP_CC4POL_POS); return; } @@ -3741,27 +3724,78 @@ static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t * switch (config->input) { - case TIMER_TS_ETRF: - timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); - break; + case TIMER_TS_ETRF: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + break; - case TIMER_TS_TI1F_ED: - CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); - MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS); - break; + case TIMER_TS_TI1F_ED: + CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS); + break; - case TIMER_TS_TI1FP1: - timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - break; + case TIMER_TS_TI1FP1: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + break; - case TIMER_TS_TI2FP2: - timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); - break; + case TIMER_TS_TI2FP2: + timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + break; - default: - break; + default: + break; } } + +#ifdef ALD_DMA + +/** + * @brief Timer DMA msel signal configuration + * @param hperh: pointer to a timer_handle_t structure that contains + * the configuration information for TIMER module. + * @param config: DMA configuration structure + * @retval None + */ +static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config) +{ +#if defined (ES32F065x) + + if (hperh == AD16C4T0) + config->msel = DMA_MSEL_TIMER0; + + if (hperh == GP16C4T0) + config->msel = DMA_MSEL_TIMER6; + +#elif defined (ES32F033x) || defined (ES32F093x) + + if (hperh == GP16C4T0) + config->msel = DMA_MSEL_TIMER0; + + if (hperh == GP16C4T1) + config->msel = DMA_MSEL_TIMER6; + +#endif + + if (hperh == GP16C2T0) + config->msel = DMA_MSEL_TIMER2; + + if (hperh == GP16C2T1) + config->msel = DMA_MSEL_TIMER3; + + if (hperh == BS16T0) + config->msel = DMA_MSEL_TIMER1; + + if (hperh == BS16T1) + config->msel = DMA_MSEL_TIMER4; + + if (hperh == BS16T2) + config->msel = DMA_MSEL_TIMER5; + + if (hperh == BS16T3) + config->msel = DMA_MSEL_TIMER7; +} + +#endif + /** * @} */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c similarity index 43% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c index 5a682f91950a36724243b155b54b62647f334dd7..85539e815a0131bfe4fc4ace236de042e51dbc2b 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_trng.c @@ -27,6 +27,14 @@ */ #ifdef ALD_TRNG +/** @addtogroup CRYPT_Private_Functions CRYPT Private Functions + * @{ + */ +void trng_reset(trng_handle_t *hperh); +/** + * @} + */ + /** @defgroup TRNG_Public_Functions TRNG Public Functions * @{ */ @@ -54,35 +62,46 @@ /** * @brief Initializes the TRNG according to the specified * parameters in the trng_init_t. - * @param init: Pointer to a trng_init_t structure that contains - * the configuration information. - * @retval None + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @retval Status, see @ref ald_status_t. */ -void trng_init(trng_init_t *init) +ald_status_t ald_trng_init(trng_handle_t *hperh) { - assert_param(IS_TRNG_DATA_WIDTH(init->data_width)); - assert_param(IS_TRNG_SEED_TYPE(init->seed_type)); - assert_param(IS_TRNG_ADJC(init->adjc)); + uint32_t tmp = 0; - SET_BIT(TRNG->CR, TRNG_CR_TRNGSEL_MSK); - MODIFY_REG(TRNG->CR, TRNG_CR_DSEL_MSK, (init->data_width) << TRNG_CR_DSEL_POSS); - MODIFY_REG(TRNG->CR, TRNG_CR_SDSEL_MSK, (init->seed_type) << TRNG_CR_SDSEL_POSS); - MODIFY_REG(TRNG->CR, TRNG_CR_ADJC_MSK, (init->adjc) << TRNG_CR_ADJC_POSS); + if (hperh == NULL) + return ERROR; - if (init->adjc == 0) - { - MODIFY_REG(TRNG->CR, TRNG_CR_ADJC_MSK, (0) << TRNG_CR_ADJC_POSS); - } + assert_param(IS_TRNG_DATA_WIDTH(hperh->init.data_width)); + assert_param(IS_TRNG_SEED_TYPE(hperh->init.seed_type)); + assert_param(IS_TRNG_ADJC(hperh->init.adjc)); + + __LOCK(hperh); + trng_reset(hperh); + + if (hperh->state == TRNG_STATE_RESET) + __UNLOCK(hperh); + + tmp = TRNG->CR; + + if (hperh->init.adjc == 0) + tmp = (0 << TRNG_CR_ADJM_POS); else - { - MODIFY_REG(TRNG->CR, TRNG_CR_ADJC_MSK, (1) << TRNG_CR_ADJC_POSS); - } + tmp = (1 << TRNG_CR_ADJM_POS); - WRITE_REG(TRNG->SEED, init->seed); - MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (init->t_start) << TRNG_CFGR_TSTART_POSS); - MODIFY_REG(TRNG->CR, TRNG_CR_POSTEN_MSK, (init->posten) << TRNG_CR_POSTEN_MSK); + tmp |= ((1 << TRNG_CR_TRNGSEL_POS) | (hperh->init.data_width << TRNG_CR_DSEL_POSS) | + (hperh->init.seed_type << TRNG_CR_SDSEL_POSS) | (hperh->init.adjc << TRNG_CR_ADJC_POSS) | + (hperh->init.posten << TRNG_CR_POSTEN_MSK)); - return; + TRNG->CR = tmp; + + WRITE_REG(TRNG->SEED, hperh->init.seed); + MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (hperh->init.t_start) << TRNG_CFGR_TSTART_POSS); + + hperh->state = TRNG_STATE_READY; + __UNLOCK(hperh); + return OK; } /** * @} @@ -96,12 +115,12 @@ void trng_init(trng_init_t *init) ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) trng_get_result() API can Get the result. - (+) trng_interrupt_config() API can be helpful to configure TRNG interrupt source. - (+) trng_get_it_status() API can get the status of interrupt source. - (+) trng_get_status() API can get the status of SR register. - (+) trng_get_flag_status() API can get the status of interrupt flag. - (+) trng_clear_flag_status() API can clear interrupt flag. + (+) ald_trng_get_result() API can Get the result. + (+) ald_trng_interrupt_config() API can be helpful to configure TRNG interrupt source. + (+) ald_trng_get_it_status() API can get the status of interrupt source. + (+) ald_trng_get_status() API can get the status of SR register. + (+) ald_trng_get_flag_status() API can get the status of interrupt flag. + (+) ald_trng_clear_flag_status() API can clear interrupt flag. @endverbatim * @{ @@ -109,15 +128,21 @@ void trng_init(trng_init_t *init) /** * @brief Get the result. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. * @retval The resultl */ -uint32_t trng_get_result(void) +uint32_t ald_trng_get_result(trng_handle_t *hperh) { - return (uint32_t)TRNG->DR; + hperh->state = TRNG_STATE_READY; + hperh->data = hperh->perh->DR; + return (uint32_t)hperh->perh->DR; } /** * @brief Enable/disable the specified interrupts. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. * @param it: Specifies the interrupt sources to be enabled or disabled. * This parameter can be one of the @ref trng_it_t. * @param state: New state of the specified interrupts. @@ -126,32 +151,34 @@ uint32_t trng_get_result(void) * @arg DISABLE * @retval None */ -void trng_interrupt_config(trng_it_t it, type_func_t state) +void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state) { assert_param(IS_TRNG_IT(it)); assert_param(IS_FUNC_STATE(state)); if (state) - SET_BIT(TRNG->IER, it); + SET_BIT(hperh->perh->IER, it); else - CLEAR_BIT(TRNG->IER, it); + CLEAR_BIT(hperh->perh->IER, it); return; } /** * @brief Get the status of SR register. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. * @param status: Specifies the TRNG status type. * This parameter can be one of the @ref trng_status_t. * @retval Status: * - 0: RESET * - 1: SET */ -flag_status_t trng_get_status(trng_status_t status) +flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status) { assert_param(IS_TRNG_STATUS(status)); - if (READ_BIT(TRNG->SR, status)) + if (READ_BIT(hperh->perh->SR, status)) return SET; return RESET; @@ -159,17 +186,19 @@ flag_status_t trng_get_status(trng_status_t status) /** * @brief Get the status of interrupt source. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. * @param it: Specifies the interrupt source. * This parameter can be one of the @ref trng_it_t. * @retval Status: * - 0: RESET * - 1: SET */ -it_status_t trng_get_it_status(trng_it_t it) +it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it) { assert_param(IS_TRNG_IT(it)); - if (READ_BIT(TRNG->IER, it)) + if (READ_BIT(hperh->perh->IER, it)) return SET; return RESET; @@ -177,17 +206,19 @@ it_status_t trng_get_it_status(trng_it_t it) /** * @brief Get the status of interrupt flag. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. * @param flag: Specifies the interrupt flag. * This parameter can be one of the @ref trng_flag_t. * @retval Status: * - 0: RESET * - 1: SET */ -flag_status_t trng_get_flag_status(trng_flag_t flag) +flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag) { assert_param(IS_TRNG_FLAG(flag)); - if (READ_BIT(TRNG->IFR, flag)) + if (READ_BIT(hperh->perh->IFR, flag)) return SET; return RESET; @@ -195,17 +226,78 @@ flag_status_t trng_get_flag_status(trng_flag_t flag) /** * @brief Clear the interrupt flag. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. * @param flag: Specifies the interrupt flag. * This parameter can be one of the @ref trng_flag_t. * @retval None */ -void trng_clear_flag_status(trng_flag_t flag) +void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag) { assert_param(IS_TRNG_FLAG(flag)); - WRITE_REG(TRNG->IFCR, flag); + WRITE_REG(hperh->perh->IFCR, flag); return; } + +/** + * @brief Reset the TRNG peripheral. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @retval None + */ +void trng_reset(trng_handle_t *hperh) +{ + TRNG->CR = 0; + TRNG->SEED = 0; + TRNG->CFGR = 0x1FF0707; + TRNG->IER = 0; + TRNG->IFCR = 0xFFFFFFFF; + + hperh->state = TRNG_STATE_READY; + __UNLOCK(hperh); + return; +} + +/** + * @brief This function handles TRNG interrupt request. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @retval None + */ +void ald_trng_irq_handler(trng_handle_t *hperh) +{ + if (ald_trng_get_flag_status(hperh, TRNG_IF_SERR) == SET) + { + hperh->state = TRNG_STATE_ERROR; + ald_trng_clear_flag_status(hperh, TRNG_IF_SERR); + + if (hperh->err_cplt_cbk) + hperh->err_cplt_cbk(hperh); + + return; + } + + if (ald_trng_get_flag_status(hperh, TRNG_IF_DAVLD) == SET) + { + hperh->data = hperh->perh->DR; + hperh->state = TRNG_STATE_READY; + ald_trng_clear_flag_status(hperh, TRNG_IF_DAVLD); + + if (hperh->trng_cplt_cbk) + hperh->trng_cplt_cbk(hperh); + } + + if (ald_trng_get_flag_status(hperh, TRNG_IF_START) == SET) + { + hperh->state = TRNG_STATE_BUSY; + ald_trng_clear_flag_status(hperh, TRNG_IF_START); + + if (hperh->init_cplt_cbk) + hperh->init_cplt_cbk(hperh); + } +} + /** * @} */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_temp.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c similarity index 40% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_temp.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c index 4f311d1285362794aba74e534ce6534b002e2522..b31d5084cb5e0a7b114a0553bfdadcb7667c9de5 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_temp.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_tsense.c @@ -1,8 +1,8 @@ /** ********************************************************************************* * - * @file ald_temp.c - * @brief TEMP module driver. + * @file ald_tsense.c + * @brief TSENSE module driver. * * @version V1.0 * @date 15 Dec 2017 @@ -14,7 +14,7 @@ ********************************************************************************* */ -#include "ald_temp.h" +#include "ald_tsense.h" #include "ald_bkpc.h" @@ -22,82 +22,84 @@ * @{ */ -/** @defgroup TEMP TEMP - * @brief TEMP module driver +/** @defgroup TSENSE TSENSE + * @brief TSENSE module driver * @{ */ -#ifdef ALD_TEMP +#ifdef ALD_TSENSE -/** @defgroup TEMP_Private_Variables TEMP Private Variables +/** @defgroup TSENSE_Private_Variables TSENSE Private Variables * @{ */ -temp_cbk __temp_cbk; +tsense_cbk __tsense_cbk; /** * @} */ -/** @defgroup TEMP_Public_Functions TEMP Public Functions +/** @defgroup TSENSE_Public_Functions TSENSE Public Functions * @{ */ -/** @addtogroup TEMP_Public_Functions_Group1 Initialization functions +/** @addtogroup TSENSE_Public_Functions_Group1 Initialization functions * @brief Initialization functions * * @verbatim ============================================================================== ##### Initialization functions ##### ============================================================================== - [..] This section provides functions allowing to initialize the TEMP: + [..] This section provides functions allowing to initialize the TSENSE: (+) This parameters can be configured: (++) Update Cycle (++) Output Mode (++) Perscaler - (+) Select TEMP source clock(default LOSC) + (+) Select TSENSE source clock(default LOSC) @endverbatim * @{ */ /** - * @brief Initializes the TEMP according to the specified - * parameters in the temp_init_t. - * @param init: Pointer to a temp_init_t structure that contains + * @brief Initializes the TSENSE according to the specified + * parameters in the tsense_init_t. + * @param init: Pointer to a tsense_init_t structure that contains * the configuration information. * @retval None */ -void temp_init(temp_init_t *init) +void ald_tsense_init(tsense_init_t *init) { - assert_param(IS_TEMP_UPDATE_CYCLE(init->cycle)); - assert_param(IS_TEMP_OUTPUT_MODE(init->mode)); + assert_param(IS_TSENSE_UPDATE_CYCLE(init->cycle)); + assert_param(IS_TSENSE_OUTPUT_MODE(init->mode)); - TEMP_UNLOCK(); - MODIFY_REG(TEMP->CR, TEMP_CR_TSU_MSK, init->cycle << TEMP_CR_TSU_POSS); - MODIFY_REG(TEMP->CR, TEMP_CR_TOM_MSK, init->mode << TEMP_CR_TOM_POSS); - MODIFY_REG(TEMP->CR, TEMP_CR_CTN_MSK, init->ctn << TEMP_CR_CTN_POS); - MODIFY_REG(TEMP->PSR, TEMP_PSR_PRS_MSK, init->psc << TEMP_PSR_PRS_POSS); - TEMP_LOCK(); + TSENSE_UNLOCK(); + TSENSE->CR = 0; + + MODIFY_REG(TSENSE->CR, TSENSE_CR_TSU_MSK, init->cycle << TSENSE_CR_TSU_POSS); + MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, init->mode << TSENSE_CR_TOM_POSS); + MODIFY_REG(TSENSE->CR, TSENSE_CR_CTN_MSK, init->ctn << TSENSE_CR_CTN_POS); + MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, init->psc << TSENSE_PSR_PRS_POSS); + TSENSE_LOCK(); return; } /** - * @brief Configure the TEMP source. - * @param sel: TEMP source type. + * @brief Configure the TSENSE source. + * @param sel: TSENSE source type. * @retval None */ -void temp_source_selcet(temp_source_sel_t sel) +void ald_tsense_source_select(tsense_source_sel_t sel) { - assert_param(IS_TEMP_SOURCE_SEL(sel)); + assert_param(IS_TSENSE_SOURCE_SEL(sel)); BKPC_UNLOCK(); - MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TEMPCS_MSK, sel << BKPC_PCCR_TEMPCS_POSS); + MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, sel << BKPC_PCCR_TSENSECS_POSS); - if (sel == TEMP_SOURCE_LOSC) + if (sel == TSENSE_SOURCE_LOSC) { SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); } - else if (sel == TEMP_SOURCE_LRC) + else if (sel == TSENSE_SOURCE_LRC) { SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); } @@ -113,7 +115,7 @@ void temp_source_selcet(temp_source_sel_t sel) * @} */ -/** @addtogroup TEMP_Public_Functions_Group2 Peripheral Control functions +/** @addtogroup TSENSE_Public_Functions_Group2 Peripheral Control functions * @brief Peripheral Control functions * * @verbatim @@ -121,9 +123,9 @@ void temp_source_selcet(temp_source_sel_t sel) ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) temp_get_value() API can get the current temperature. - (+) temp_get_value_by_it() API can get the current temperature by interrupt. - (+) temp_irq_handle() API can handle the interrupt request. + (+) ald_tsense_get_value() API can get the current temperature. + (+) ald_tsense_get_value_by_it() API can get the current temperature by interrupt. + (+) ald_tsense_irq_handler() API can handle the interrupt request. @endverbatim * @{ @@ -131,28 +133,33 @@ void temp_source_selcet(temp_source_sel_t sel) /** * @brief Get the current temperature - * @param temp: The value of current temperature. + * @param tsense: The value of current temperature. * @retval ALD status: * @arg @ref OK The value is valid * @arg @ref ERROR The value is invalid */ -ald_status_t temp_get_value(uint16_t *temp) +ald_status_t ald_tsense_get_value(uint16_t *tsense) { - TEMP_UNLOCK(); - SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK); - SET_BIT(TEMP->CR, TEMP_CR_EN_MSK); - TEMP_LOCK(); + uint32_t tmp = 0; + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + + while ((!(READ_BIT(TSENSE->IF, TSENSE_IF_TSENSE_MSK))) && (tmp++ < 1000000)); - while (!(READ_BIT(TEMP->IF, TEMP_IF_TEMP_MSK))); + if (tmp >= 1000000) + return TIMEOUT; - TEMP_UNLOCK(); - SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK); - TEMP_LOCK(); + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + TSENSE_LOCK(); - if (READ_BIT(TEMP->DR, TEMP_DR_ERR_MSK)) + if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) return ERROR; - *temp = READ_BITS(TEMP->DR, TEMP_DR_DATA_MSK, TEMP_DR_DATA_POSS); + *tsense = READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS); return OK; } @@ -161,40 +168,43 @@ ald_status_t temp_get_value(uint16_t *temp) * @param cbk: The callback function * @retval None */ -void temp_get_value_by_it(temp_cbk cbk) +void ald_tsense_get_value_by_it(tsense_cbk cbk) { - __temp_cbk = cbk; + __tsense_cbk = cbk; - TEMP_UNLOCK(); - SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK); - SET_BIT(TEMP->IE, TEMP_IE_TEMP_MSK); - SET_BIT(TEMP->CR, TEMP_CR_EN_MSK); - TEMP_LOCK(); + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + SET_BIT(TSENSE->IE, TSENSE_IE_TSENSE_MSK); + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); return; } /** - * @brief This function handles TEMP interrupt request. + * @brief This function handles TSENSE interrupt request. * @retval None */ -void temp_irq_handle(void) +void ald_tsense_irq_handler(void) { - TEMP_UNLOCK(); - SET_BIT(TEMP->IFCR, TEMP_IFCR_TEMP_MSK); - TEMP_LOCK(); + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + TSENSE_LOCK(); - if (__temp_cbk == NULL) + if (__tsense_cbk == NULL) return; - if (READ_BIT(TEMP->DR, TEMP_DR_ERR_MSK)) + if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) { - __temp_cbk(0, ERROR); + __tsense_cbk(0, ERROR); return; } - __temp_cbk(READ_BITS(TEMP->DR, TEMP_DR_DATA_MSK, TEMP_DR_DATA_POSS), OK); + __tsense_cbk(READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS), OK); + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + TSENSE_LOCK(); return; } /** @@ -203,7 +213,7 @@ void temp_irq_handle(void) /** * @} */ -#endif /* ALD_TEMP */ +#endif /* ALD_TSENSE */ /** * @} */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c similarity index 82% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c index 32cdbe143fd1c0b0903441cc9df439428ab10a61..ee0751ad8d07847a8406b11a7f8f0036fae5036a 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_uart.c @@ -32,19 +32,19 @@ (##) UART pins configuration: (+++) Enable the clock for the UART GPIOs. (+++) Configure the UART pins (TX as alternate function pull-up, RX as alternate function Input). - (##) NVIC configuration if you need to use interrupt process (uart_send_by_it() - and uart_recv_by_it() APIs): + (##) NVIC configuration if you need to use interrupt process (ald_uart_send_by_it() + and ald_uart_recv_by_it() APIs): (+++) Configure the uart interrupt priority. (+++) Enable the NVIC UART IRQ handle. - (##) DMA Configuration if you need to use DMA process (uart_send_by_dma() - and uart_recv_by_dma() APIs): + (##) DMA Configuration if you need to use DMA process (ald_uart_send_by_dma() + and ald_uart_recv_by_dma() APIs): (+++) Select the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware flow control and Mode(Receiver/Transmitter) in the hperh Init structure. - (#) Initialize the UART registers by calling the uart_init() API. + (#) Initialize the UART registers by calling the ald_uart_init() API. [..] Three operation modes are available within this driver: @@ -52,16 +52,16 @@ *** Polling mode IO operation *** ================================= [..] - (+) Send an amount of data in blocking mode using uart_send() - (+) Receive an amount of data in blocking mode using uart_recv() + (+) Send an amount of data in blocking mode using ald_uart_send() + (+) Receive an amount of data in blocking mode using ald_uart_recv() *** Interrupt mode IO operation *** =================================== [..] - (+) Send an amount of data in non blocking mode using uart_send_by_it() + (+) Send an amount of data in non blocking mode using ald_uart_send_by_it() (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode using uart_recv_by_it() + (+) Receive an amount of data in non blocking mode using ald_uart_recv_by_it() (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->rx_cplt_cbk() (+) In case of transfer Error, hperh->error_cbk() function is executed and user can @@ -70,17 +70,17 @@ *** DMA mode IO operation *** ============================== [..] - (+) Send an amount of data in non blocking mode (DMA) using uart_send_by_dma() + (+) Send an amount of data in non blocking mode (DMA) using ald_uart_send_by_dma() (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode (DMA) using uart_recv_by_dma() + (+) Receive an amount of data in non blocking mode (DMA) using ald_uart_recv_by_dma() (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->rx_cplt_cbk() (+) In case of transfer Error, hperh->error_cbk() function is executed and user can add his own code by customization of function pointer hperh->error_cbk() - (+) Pause the DMA Transfer using uart_dma_pause() - (+) Resume the DMA Transfer using uart_dma_resume() - (+) Stop the DMA Transfer using uart_dma_stop() + (+) Pause the DMA Transfer using ald_uart_dma_pause() + (+) Resume the DMA Transfer using ald_uart_dma_resume() + (+) Stop the DMA Transfer using ald_uart_dma_stop() @endverbatim ****************************************************************************** @@ -115,10 +115,10 @@ static void uart_dma_send_cplt(void *arg) uart_handle_t *hperh = (uart_handle_t *)arg; if (hperh->state == UART_STATE_BUSY_TX) - uart_dma_req_config(hperh, DISABLE); + ald_uart_dma_req_config(hperh, DISABLE); hperh->tx_count = 0; - uart_interrupt_config(hperh, UART_IT_TC, ENABLE); + ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); return; } @@ -132,7 +132,7 @@ static void uart_dma_recv_cplt(void *arg) uart_handle_t *hperh = (uart_handle_t *)arg; if (hperh->state == UART_STATE_BUSY_RX) - uart_dma_req_config(hperh, DISABLE); + ald_uart_dma_req_config(hperh, DISABLE); hperh->rx_count = 0; CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); @@ -156,7 +156,7 @@ static void uart_dma_error(void *arg) hperh->tx_count = 0; hperh->state = UART_STATE_READY; hperh->err_code |= UART_ERROR_DMA; - uart_dma_req_config(hperh, DISABLE); + ald_uart_dma_req_config(hperh, DISABLE); if (hperh->error_cbk) hperh->error_cbk(hperh); @@ -180,12 +180,12 @@ static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, fla if (timeout == 0) return ERROR; - tick = __get_tick(); + tick = ald_get_tick(); /* Waiting for flag */ - while ((uart_get_status(hperh, flag)) != status) + while ((ald_uart_get_status(hperh, flag)) != status) { - if (((__get_tick()) - tick) > timeout) + if (((ald_get_tick()) - tick) > timeout) return TIMEOUT; } @@ -206,9 +206,9 @@ static ald_status_t __uart_send_by_it(uart_handle_t *hperh) if (--hperh->tx_count == 0) { - uart_clear_flag_status(hperh, UART_IF_TC); - uart_interrupt_config(hperh, UART_IT_TXS, DISABLE); - uart_interrupt_config(hperh, UART_IT_TC, ENABLE); + ald_uart_clear_flag_status(hperh, UART_IF_TC); + ald_uart_interrupt_config(hperh, UART_IT_TXS, DISABLE); + ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); } return OK; @@ -224,8 +224,9 @@ static ald_status_t __uart_end_send_by_it(uart_handle_t *hperh) if (!(READ_BIT(hperh->perh->SR, UART_SR_TEM_MSK))) return OK; - uart_interrupt_config(hperh, UART_IT_TC, DISABLE); + ald_uart_interrupt_config(hperh, UART_IT_TC, DISABLE); CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + if (hperh->tx_cplt_cbk) hperh->tx_cplt_cbk(hperh); @@ -246,7 +247,7 @@ static ald_status_t __uart_recv_by_it(uart_handle_t *hperh) if (--hperh->rx_count == 0) { - uart_interrupt_config(hperh, UART_IT_RXRD, DISABLE); + ald_uart_interrupt_config(hperh, UART_IT_RXRD, DISABLE); CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); if (hperh->rx_cplt_cbk) @@ -280,11 +281,11 @@ static ald_status_t __uart_recv_by_it(uart_handle_t *hperh) (++) Parity (++) Hardware flow control (+) For RS485 mode, user also need configure some parameters by - uart_rs485_config(): + ald_uart_rs485_config(): (++) Enable/disable normal point mode - (++) Enable/disable auto-direction - (++) Enable/disable address detection invert - (++) Enable/disable address for compare + (++) Enable/disable auto-direction + (++) Enable/disable address detection invert + (++) Enable/disable address for compare @endverbatim * @{ @@ -296,7 +297,7 @@ static ald_status_t __uart_recv_by_it(uart_handle_t *hperh) * the configuration information for the specified uart module. * @retval None */ -void uart_reset(uart_handle_t *hperh) +void ald_uart_reset(uart_handle_t *hperh) { assert_param(IS_UART_ALL(hperh->perh)); @@ -322,7 +323,7 @@ void uart_reset(uart_handle_t *hperh) * the configuration information for the specified UART module. * @retval None */ -void uart_init(uart_handle_t *hperh) +void ald_uart_init(uart_handle_t *hperh) { uint32_t tmp; @@ -334,7 +335,7 @@ void uart_init(uart_handle_t *hperh) assert_param(IS_UART_MODE(hperh->init.mode)); assert_param(IS_UART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); - uart_reset(hperh); + ald_uart_reset(hperh); tmp = READ_REG(hperh->perh->LCR); MODIFY_REG(tmp, UART_LCR_DLS_MSK, hperh->init.word_length << UART_LCR_DLS_POSS); @@ -344,7 +345,7 @@ void uart_init(uart_handle_t *hperh) WRITE_REG(hperh->perh->LCR, tmp); MODIFY_REG(hperh->perh->MCR, UART_MCR_AFCEN_MSK, hperh->init.fctl << UART_MCR_AFCEN_POS); SET_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK); - WRITE_REG(hperh->perh->BRR, cmu_get_pclk1_clock() / hperh->init.baud); + WRITE_REG(hperh->perh->BRR, ald_cmu_get_pclk1_clock() / hperh->init.baud); CLEAR_BIT(hperh->perh->LCR, UART_LCR_BRWEN_MSK); SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK); @@ -366,6 +367,7 @@ void uart_init(uart_handle_t *hperh) if (hperh->init.fctl) SET_BIT(hperh->perh->MCR, UART_MCR_RTSCTRL_MSK); + if (hperh->init.mode == UART_MODE_IrDA) SET_BIT(hperh->perh->LCR, UART_LCR_RXINV_MSK); @@ -382,7 +384,7 @@ void uart_init(uart_handle_t *hperh) * @param config: Specifies the RS485 parameters. * @retval None */ -void uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config) +void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_FUNC_STATE(config->normal)); @@ -424,20 +426,20 @@ void uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config) a communication error is detected. (#) Blocking mode APIs are: - (++) uart_send() - (++) uart_recv() + (++) ald_uart_send() + (++) ald_uart_recv() (#) Non Blocking mode APIs with Interrupt are: - (++) uart_send_by_it() - (++) uart_recv_by_it() - (++) uart_irq_handle() + (++) ald_uart_send_by_it() + (++) ald_uart_recv_by_it() + (++) ald_uart_irq_handler() (#) Non Blocking mode functions with DMA are: - (++) uart_send_by_dma() - (++) uart_recv_by_dma() - (++) uart_dma_pause() - (++) uart_dma_resume() - (++) uart_dma_stop() + (++) ald_uart_send_by_dma() + (++) ald_uart_recv_by_dma() + (++) ald_uart_dma_pause() + (++) ald_uart_dma_resume() + (++) ald_uart_dma_stop() (#) A set of transfer complete callbacks are provided in non blocking mode: (++) hperh->tx_cplt_cbk() @@ -456,7 +458,7 @@ void uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config) * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { assert_param(IS_UART_ALL(hperh->perh)); @@ -506,7 +508,7 @@ ald_status_t uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32 * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { assert_param(IS_UART_ALL(hperh->perh)); @@ -549,7 +551,7 @@ ald_status_t uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32 * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) { assert_param(IS_UART_ALL(hperh->perh)); @@ -568,8 +570,8 @@ ald_status_t uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) SET_BIT(hperh->state, UART_STATE_TX_MASK); __UNLOCK(hperh); - if (((uart_get_status(hperh, UART_STATUS_TBEM)) == SET) - && ((uart_get_flag_status(hperh, UART_IF_TXS)) == RESET)) + if (((ald_uart_get_status(hperh, UART_STATUS_TBEM)) == SET) + && ((ald_uart_get_flag_status(hperh, UART_IF_TXS)) == RESET)) { WRITE_REG(hperh->perh->TBR, (*hperh->tx_buf++ & 0xFF)); --hperh->tx_count; @@ -577,11 +579,11 @@ ald_status_t uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) if (hperh->tx_count == 0) { - uart_interrupt_config(hperh, UART_IT_TC, ENABLE); + ald_uart_interrupt_config(hperh, UART_IT_TC, ENABLE); return OK; } - uart_interrupt_config(hperh, UART_IT_TXS, ENABLE); + ald_uart_interrupt_config(hperh, UART_IT_TXS, ENABLE); return OK; } @@ -592,7 +594,7 @@ ald_status_t uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) * @param size: Amount of data to be received * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) { assert_param(IS_UART_ALL(hperh->perh)); @@ -610,7 +612,7 @@ ald_status_t uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) SET_BIT(hperh->state, UART_STATE_RX_MASK); __UNLOCK(hperh); - uart_interrupt_config(hperh, UART_IT_RXRD, ENABLE); + ald_uart_interrupt_config(hperh, UART_IT_RXRD, ENABLE); return OK; } #ifdef ALD_DMA @@ -622,7 +624,7 @@ ald_status_t uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) * @param channel: DMA channel as UART transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { assert_param(IS_UART_ALL(hperh->perh)); @@ -648,7 +650,7 @@ ald_status_t uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, hperh->hdmatx.err_cbk = uart_dma_error; hperh->hdmatx.err_arg = (void *)hperh; - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->TBR; hperh->hdmatx.config.size = size; @@ -673,13 +675,13 @@ ald_status_t uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, else if (hperh->perh == UART3) hperh->hdmatx.config.msel = DMA_MSEL_UART3; else - ; /* do nothing */ + ; /* do nothing */ - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); __UNLOCK(hperh); - uart_clear_flag_status(hperh, UART_IF_TC); - uart_dma_req_config(hperh, ENABLE); + ald_uart_clear_flag_status(hperh, UART_IF_TC); + ald_uart_dma_req_config(hperh, ENABLE); return OK; } @@ -692,7 +694,7 @@ ald_status_t uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, * @param channel: DMA channel as UART receive * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { assert_param(IS_UART_ALL(hperh->perh)); @@ -717,7 +719,7 @@ ald_status_t uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, hperh->hdmarx.err_cbk = uart_dma_error; hperh->hdmarx.err_arg = (void *)hperh; - dma_config_struct(&hperh->hdmarx.config); + ald_dma_config_struct(&hperh->hdmarx.config); hperh->hdmarx.config.src = (void *)&hperh->perh->RBR; hperh->hdmarx.config.dst = (void *)buf; hperh->hdmarx.config.size = size; @@ -744,9 +746,9 @@ ald_status_t uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, else ; - dma_config_basic(&hperh->hdmarx); + ald_dma_config_basic(&hperh->hdmarx); __UNLOCK(hperh); - uart_dma_req_config(hperh, ENABLE); + ald_uart_dma_req_config(hperh, ENABLE); return OK; } @@ -756,11 +758,11 @@ ald_status_t uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, * @param hperh: Pointer to a uart_handle_t structure. * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_dma_pause(uart_handle_t *hperh) +ald_status_t ald_uart_dma_pause(uart_handle_t *hperh) { assert_param(IS_UART_ALL(hperh->perh)); - uart_dma_req_config(hperh, DISABLE); + ald_uart_dma_req_config(hperh, DISABLE); return OK; } @@ -769,11 +771,11 @@ ald_status_t uart_dma_pause(uart_handle_t *hperh) * @param hperh: Pointer to a uart_handle_t structure. * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_dma_resume(uart_handle_t *hperh) +ald_status_t ald_uart_dma_resume(uart_handle_t *hperh) { assert_param(IS_UART_ALL(hperh->perh)); - uart_dma_req_config(hperh, ENABLE); + ald_uart_dma_req_config(hperh, ENABLE); return OK; } @@ -782,11 +784,11 @@ ald_status_t uart_dma_resume(uart_handle_t *hperh) * @param hperh: Pointer to a uart_handle_t structure. * @retval Status, see @ref ald_status_t. */ -ald_status_t uart_dma_stop(uart_handle_t *hperh) +ald_status_t ald_uart_dma_stop(uart_handle_t *hperh) { assert_param(IS_UART_ALL(hperh->perh)); - uart_dma_req_config(hperh, DISABLE); + ald_uart_dma_req_config(hperh, DISABLE); hperh->state = UART_STATE_READY; return OK; } @@ -797,40 +799,40 @@ ald_status_t uart_dma_stop(uart_handle_t *hperh) * @param hperh: Pointer to a uart_handle_t structure. * @retval None */ -void uart_irq_handle(uart_handle_t *hperh) +void ald_uart_irq_handler(uart_handle_t *hperh) { assert_param(IS_UART_ALL(hperh->perh)); /* Handle parity error */ - if ((uart_get_status(hperh, UART_STATUS_PE)) != RESET) + if ((ald_uart_get_status(hperh, UART_STATUS_PE)) != RESET) hperh->err_code |= UART_ERROR_PE; /* Handle frame error */ - if ((uart_get_status(hperh, UART_STATUS_FE)) != RESET) + if ((ald_uart_get_status(hperh, UART_STATUS_FE)) != RESET) hperh->err_code |= UART_ERROR_FE; /* Handle overflow error */ - if ((uart_get_status(hperh, UART_STATUS_OE)) != RESET) + if ((ald_uart_get_status(hperh, UART_STATUS_OE)) != RESET) hperh->err_code |= UART_ERROR_ORE; /* Receive */ - if ((uart_get_mask_flag_status(hperh, UART_IF_RXRD)) != RESET) + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RXRD)) != RESET) { - uart_clear_flag_status(hperh, UART_IF_RXRD); + ald_uart_clear_flag_status(hperh, UART_IF_RXRD); __uart_recv_by_it(hperh); } - /* Transmite */ - if ((uart_get_mask_flag_status(hperh, UART_IF_TXS)) != RESET) + /* Transmit */ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TXS)) != RESET) { - uart_clear_flag_status(hperh, UART_IF_TXS); + ald_uart_clear_flag_status(hperh, UART_IF_TXS); __uart_send_by_it(hperh); } - /* End Transmite */ - if ((uart_get_mask_flag_status(hperh, UART_IF_TC)) != RESET) + /* End Transmit */ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TC)) != RESET) { - uart_clear_flag_status(hperh, UART_IF_TC); + ald_uart_clear_flag_status(hperh, UART_IF_TC); __uart_end_send_by_it(hperh); } @@ -856,18 +858,18 @@ void uart_irq_handle(uart_handle_t *hperh) ============================================================================== [..] This subsection provides a set of functions allowing to control the UART: - (+) uart_interrupt_config() API can be helpful to configure UART interrupt source. - (+) uart_dma_req_config() API can be helpful to configure UART DMA request. - (+) uart_tx_fifo_config() API can be helpful to configure UART TX FIFO paramters. - (+) uart_rx_fifo_config() API can be helpful to configure UART RX FIFO paramters. - (+) uart_lin_send_break() API can send a frame of break in LIN mode. - (+) uart_lin_detect_break_len_config() API can be helpful to configure the length of break frame. - (+) uart_auto_baud_config() API can be helpful to configure detection data mode. - (+) uart_get_it_status() API can get the status of interrupt source. - (+) uart_get_status() API can get the status of UART_SR register. - (+) uart_get_flag_status() API can get the status of UART flag. - (+) uart_get_mask_flag_status() API can get status os flag and interrupt source. - (+) uart_clear_flag_status() API can clear UART flag. + (+) ald_uart_interrupt_config() API can be helpful to configure UART interrupt source. + (+) ald_uart_dma_req_config() API can be helpful to configure UART DMA request. + (+) ald_uart_tx_fifo_config() API can be helpful to configure UART TX FIFO paramters. + (+) ald_uart_rx_fifo_config() API can be helpful to configure UART RX FIFO paramters. + (+) ald_uart_lin_send_break() API can send a frame of break in LIN mode. + (+) ald_uart_lin_detect_break_len_config() API can be helpful to configure the length of break frame. + (+) ald_uart_auto_baud_config() API can be helpful to configure detection data mode. + (+) ald_uart_get_it_status() API can get the status of interrupt source. + (+) ald_uart_get_status() API can get the status of UART_SR register. + (+) ald_uart_get_flag_status() API can get the status of UART flag. + (+) ald_uart_get_mask_flag_status() API can get status os flag and interrupt source. + (+) ald_uart_clear_flag_status() API can clear UART flag. @endverbatim * @{ @@ -884,7 +886,7 @@ void uart_irq_handle(uart_handle_t *hperh) * @arg DISABLE * @retval None */ -void uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state) +void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_IT(it)); @@ -907,7 +909,7 @@ void uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state * @arg DISABLE * @retval None */ -void uart_dma_req_config(uart_handle_t *hperh, type_func_t state) +void ald_uart_dma_req_config(uart_handle_t *hperh, type_func_t state) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_FUNC_STATE(state)); @@ -927,7 +929,7 @@ void uart_dma_req_config(uart_handle_t *hperh, type_func_t state) * @param level: Transmit fifo level. * @retval None */ -void uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level) +void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_TXFIFO_TYPE(config)); @@ -947,7 +949,7 @@ void uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t lev * @param level: Receive fifo level. * @retval None */ -void uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level) +void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_RXFIFO_TYPE(config)); @@ -965,7 +967,7 @@ void uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t lev * @param hperh: Pointer to a uart_handle_t structure. * @retval None */ -void uart_lin_send_break(uart_handle_t *hperh) +void ald_uart_lin_send_break(uart_handle_t *hperh) { assert_param(IS_UART_ALL(hperh->perh)); @@ -981,7 +983,7 @@ void uart_lin_send_break(uart_handle_t *hperh) * @arg LIN_BREAK_LEN_11B * @retval None */ -void uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len) +void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_LIN_BREAK_LEN(len)); @@ -999,7 +1001,7 @@ void uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t * @arg UART_ABRMOD_0_TO_1 * @retval None */ -void uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode) +void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_AUTO_BAUD_MODE(mode)); @@ -1016,7 +1018,7 @@ void uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode) * @param timeout: Timeout duration * @retval The ALD status. */ -ald_status_t uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout) +ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout) { assert_param(IS_UART_ALL(hperh->perh)); @@ -1053,7 +1055,7 @@ ald_status_t uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t * - 0: RESET * - 1: SET */ -it_status_t uart_get_it_status(uart_handle_t *hperh, uart_it_t it) +it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_IT(it)); @@ -1073,7 +1075,7 @@ it_status_t uart_get_it_status(uart_handle_t *hperh, uart_it_t it) * - 0: RESET * - 1: SET */ -flag_status_t uart_get_status(uart_handle_t *hperh, uart_status_t status) +flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_STATUS(status)); @@ -1094,7 +1096,7 @@ flag_status_t uart_get_status(uart_handle_t *hperh, uart_status_t status) * - 0: RESET * - 1: SET */ -flag_status_t uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag) +flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_IF(flag)); @@ -1114,7 +1116,7 @@ flag_status_t uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag) * - 0: RESET * - 1: SET */ -flag_status_t uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag) +flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_IF(flag)); @@ -1132,7 +1134,7 @@ flag_status_t uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag) * This parameter can be one of the @ref uart_flag_t. * @retval None */ -void uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag) +void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag) { assert_param(IS_UART_ALL(hperh->perh)); assert_param(IS_UART_IF(flag)); @@ -1155,8 +1157,8 @@ void uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag) This subsection provides a set of functions allowing to return the State of UART communication process, return Peripheral Errors occurred during communication process - (+) uart_get_state() API can be helpful to check in run-time the state of the UART peripheral. - (+) uart_get_error() check in run-time errors that could be occurred during communication. + (+) ald_uart_get_state() API can be helpful to check in run-time the state of the UART peripheral. + (+) ald_uart_get_error() check in run-time errors that could be occurred during communication. @endverbatim * @{ @@ -1167,7 +1169,7 @@ void uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag) * @param hperh: Pointer to a uart_handle_t structure. * @retval ALD state */ -uart_state_t uart_get_state(uart_handle_t *hperh) +uart_state_t ald_uart_get_state(uart_handle_t *hperh) { return hperh->state; } @@ -1177,7 +1179,7 @@ uart_state_t uart_get_state(uart_handle_t *hperh) * @param hperh: Pointer to a uart_handle_t structure. * @retval UART Error Code */ -uint32_t uart_get_error(uart_handle_t *hperh) +uint32_t ald_uart_get_error(uart_handle_t *hperh) { return hperh->err_code; } diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c similarity index 85% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c index 69641cb0600130cfcf36c4a9445bf553b346df72..18672dd07e84908f68354d78175bd40443cc26e1 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_usart.c @@ -32,12 +32,12 @@ (##) USART pins configuration: (+++) Enable the clock for the USART GPIOs. (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). - (##) NVIC configuration if you need to use interrupt process (usart_send_by_it() - and usart_recv_by_it() APIs): + (##) NVIC configuration if you need to use interrupt process (ald_usart_send_by_it() + and ald_usart_recv_by_it() APIs): (+++) Configure the USARTx interrupt priority. (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (usart_send_by_dma() - and usart_recv_by_dma() APIs): + (##) DMA Configuration if you need to use DMA process (ald_usart_send_by_dma() + and ald_usart_recv_by_dma() APIs): (+++) Declare a DMA handle structure for the Tx/Rx channel. (+++) Enable the DMAx interface clock. (+++) Configure the declared DMA handle structure with the required @@ -49,20 +49,20 @@ flow control and mode(Receiver/Transmitter) in the hperh Init structure. (#) For the USART asynchronous mode, initialize the USART registers by calling - the usart_init() API. + the ald_usart_init() API. (#) For the USART Half duplex mode, initialize the USART registers by calling - the usart_half_duplex_init() API. + the ald_usart_half_duplex_init() API. (#) For the LIN mode, initialize the USART registers by calling the usart_lin_init() API. (#) For the Multi-Processor mode, initialize the USART registers by calling - the usart_multi_processor_init() API. + the ald_usart_multi_processor_init() API. [..] (@) The specific USART interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the function - usart_interrupt_config inside the transmit and receive process. + ald_usart_interrupt_config inside the transmit and receive process. [..] Three operation modes are available within this driver : @@ -70,17 +70,17 @@ *** Polling mode IO operation *** ================================= [..] Asynchronous: - (+) Send an amount of data in blocking mode using usart_send() - (+) Receive an amount of data in blocking mode using usart_recv() + (+) Send an amount of data in blocking mode using ald_usart_send() + (+) Receive an amount of data in blocking mode using ald_usart_recv() [..] Synchronous: - (+) Send an amount of data in blocking mode using usart_send_sync() - (+) Receive an amount of data in blocking mode using usart_recv_sync() + (+) Send an amount of data in blocking mode using ald_usart_send_sync() + (+) Receive an amount of data in blocking mode using ald_usart_recv_sync() *** Interrupt mode IO operation *** =================================== [..] Asynchronous: - (+) Send an amount of data in non blocking mode using usart_send_by_it() + (+) Send an amount of data in non blocking mode using ald_usart_send_by_it() (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->tx_cplt_cbk() (+) Receive an amount of data in non blocking mode using USART_recv_by_it() @@ -89,7 +89,7 @@ (+) In case of transfer Error, hperh->error_cbk() function is executed and user can add his own code by customization of function pointer hperh->error_cbk() [..] Synchronous: - (+) Send an amount of data in non blocking mode using usart_send_by_it_sync() + (+) Send an amount of data in non blocking mode using ald_usart_send_by_it_sync() (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->tx_cplt_cbk() (+) Receive an amount of data in non blocking mode using USART_recv_by_it_sync() @@ -101,27 +101,27 @@ *** DMA mode IO operation *** ============================== [..] Asynchronous: - (+) Send an amount of data in non blocking mode (DMA) using usart_send_by_dma() + (+) Send an amount of data in non blocking mode (DMA) using ald_usart_send_by_dma() (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode (DMA) using usart_recv_by_dma() + (+) Receive an amount of data in non blocking mode (DMA) using ald_usart_recv_by_dma() (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->rx_cplt_cbk() (+) In case of transfer Error, hperh->error_cbk()() function is executed and user can add his own code by customization of function pointer hperh->error_cbk() [..] Synchronous: - (+) Send an amount of data in non blocking mode (DMA) using usart_send_by_dma_sync() + (+) Send an amount of data in non blocking mode (DMA) using ald_usart_send_by_dma_sync() (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->tx_cplt_cbk() - (+) Receive an amount of data in non blocking mode (DMA) using usart_recv_by_dma_sync() + (+) Receive an amount of data in non blocking mode (DMA) using ald_usart_recv_by_dma_sync() (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can add his own code by customization of function pointer hperh->rx_cplt_cbk() (+) In case of transfer Error, hperh->error_cbk()() function is executed and user can add his own code by customization of function pointer hperh->error_cbk() [..] Utilities: - (+) Pause the DMA Transfer using usart_dma_pause() - (+) Resume the DMA Transfer using usart_dma_resume() - (+) Stop the DMA Transfer using usart_dma_stop() + (+) Pause the DMA Transfer using ald_usart_dma_pause() + (+) Resume the DMA Transfer using ald_usart_dma_resume() + (+) Stop the DMA Transfer using ald_usart_dma_stop() *** USART ALD driver macros list *** ============================================= @@ -212,8 +212,8 @@ static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, fl (++) Hardware flow control (++) Receiver/transmitter modes [..] - The usart_init(), usart_half_duplex_init(), usart_lin_init(), usart_multi_processor_init() - and usart_clock_init() APIs follow respectively the USART asynchronous, USART Half duplex, + The ald_usart_init(), ald_usart_half_duplex_init(), usart_lin_init(), ald_usart_multi_processor_init() + and ald_usart_clock_init() APIs follow respectively the USART asynchronous, USART Half duplex, LIN, Multi-Processor and synchronous configuration procedures. @endverbatim @@ -245,7 +245,7 @@ static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, fl * the configuration information for the specified USART module. * @retval None */ -void usart_reset(usart_handle_t *hperh) +void ald_usart_reset(usart_handle_t *hperh) { assert_param(IS_USART(hperh->perh)); @@ -270,14 +270,14 @@ void usart_reset(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_init(usart_handle_t *hperh) +ald_status_t ald_usart_init(usart_handle_t *hperh) { assert_param(IS_USART(hperh->perh)); assert_param(IS_USART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); - usart_reset(hperh); + ald_usart_reset(hperh); hperh->state = USART_STATE_BUSY; USART_DISABLE(hperh); usart_set_config(hperh); @@ -305,13 +305,13 @@ ald_status_t usart_init(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_half_duplex_init(usart_handle_t *hperh) +ald_status_t ald_usart_half_duplex_init(usart_handle_t *hperh) { assert_param(IS_USART(hperh->perh)); assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); - usart_reset(hperh); + ald_usart_reset(hperh); hperh->state = USART_STATE_BUSY; USART_DISABLE(hperh); usart_set_config(hperh); @@ -343,7 +343,7 @@ ald_status_t usart_half_duplex_init(usart_handle_t *hperh) * @arg USART_WAKEUP_ADDR: Wakeup by an address mark * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usart_wakeup_t wakeup) +ald_status_t ald_usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usart_wakeup_t wakeup) { assert_param(IS_USART(hperh->perh)); assert_param(IS_USART_WAKEUP(wakeup)); @@ -351,7 +351,7 @@ ald_status_t usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usa assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); - usart_reset(hperh); + ald_usart_reset(hperh); hperh->state = USART_STATE_BUSY; USART_DISABLE(hperh); usart_set_config(hperh); @@ -381,13 +381,13 @@ ald_status_t usart_multi_processor_init(usart_handle_t *hperh, uint8_t addr, usa * @param init: USART Clock Init Structure. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init) +ald_status_t ald_usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init) { assert_param(IS_USART(hperh->perh)); assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length)); assert_param(IS_FUNC_STATE(hperh->init.over_sampling)); - usart_reset(hperh); + ald_usart_reset(hperh); hperh->state = USART_STATE_BUSY; USART_DISABLE(hperh); usart_set_config(hperh); @@ -445,20 +445,20 @@ ald_status_t usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init) a communication error is detected. (#) Blocking mode APIs are: - (++) usart_send() - (++) usart_recv() + (++) ald_usart_send() + (++) ald_usart_recv() (#) Non Blocking mode APIs with Interrupt are: - (++) usart_send_by_it() - (++) usart_recv_by_it() + (++) ald_usart_send_by_it() + (++) ald_usart_recv_by_it() (++) urart_irq_handle() (#) Non Blocking mode functions with DMA are: - (++) usart_send_by_dma() - (++) usart_recv_by_dma() - (++) usart_dma_pause() - (++) usart_dma_resume() - (++) usart_dma_stop() + (++) ald_usart_send_by_dma() + (++) ald_usart_recv_by_dma() + (++) ald_usart_dma_pause() + (++) ald_usart_dma_resume() + (++) ald_usart_dma_stop() (#) A set of Transfer Complete Callbacks are provided in non blocking mode: (++) hperh->tx_cplt_cbk() @@ -483,7 +483,7 @@ ald_status_t usart_clock_init(usart_handle_t *hperh, usart_clock_init_t *init) * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) return BUSY; @@ -547,7 +547,7 @@ ald_status_t usart_send(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) return BUSY; @@ -607,7 +607,7 @@ ald_status_t usart_recv(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint * @param size: Amount of data to be sent * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) return BUSY; @@ -624,7 +624,7 @@ ald_status_t usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size hperh->err_code = USART_ERROR_NONE; __UNLOCK(hperh); - usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); return OK; } @@ -637,7 +637,7 @@ ald_status_t usart_send_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size * @param size: Amount of data to be received * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) return BUSY; @@ -654,9 +654,9 @@ ald_status_t usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size hperh->err_code = USART_ERROR_NONE; __UNLOCK(hperh); - usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); return OK; } @@ -669,7 +669,7 @@ ald_status_t usart_recv_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size * @param size: Maximum amount of data to be received * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) return BUSY; @@ -686,9 +686,9 @@ ald_status_t usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_ hperh->err_code = USART_ERROR_NONE; __UNLOCK(hperh); - usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); __frame_mode = 1; return OK; @@ -704,7 +704,7 @@ ald_status_t usart_recv_frame_by_it(usart_handle_t *hperh, uint8_t *buf, uint16_ * @param channel: DMA channel as USART transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_RX)) return BUSY; @@ -730,7 +730,7 @@ ald_status_t usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t siz hperh->hdmatx.err_arg = (void *)hperh; /* Configure USART DMA transmit */ - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; hperh->hdmatx.config.size = size; @@ -747,10 +747,10 @@ ald_status_t usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t siz hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; } - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); __UNLOCK(hperh); - usart_clear_flag_status(hperh, USART_FLAG_TC); + ald_usart_clear_flag_status(hperh, USART_FLAG_TC); SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); return OK; @@ -767,7 +767,7 @@ ald_status_t usart_send_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t siz * the parity bit (MSB position) * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { if ((hperh->state != USART_STATE_READY) && (hperh->state != USART_STATE_BUSY_TX)) return BUSY; @@ -792,7 +792,7 @@ ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t siz hperh->hdmarx.err_arg = (void *)hperh; /* Configure DMA Receive */ - dma_config_struct(&hperh->hdmarx.config); + ald_dma_config_struct(&hperh->hdmarx.config); hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)buf; hperh->hdmarx.config.size = size; @@ -809,7 +809,7 @@ ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t siz hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; } - dma_config_basic(&hperh->hdmarx); + ald_dma_config_basic(&hperh->hdmarx); __UNLOCK(hperh); SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); @@ -847,27 +847,27 @@ ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t siz using DMA mode. The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() and hperh->tx_rx_cplt_cbk() user callbacks will be executed respectively at the end of the transmit - or Receive process. The hperh->error_cbk() user callback will be - executed when a communication error is detected + or Receive process. The hperh->error_cbk() user callback will be + executed when a communication error is detected (#) Blocking mode APIs are : - (++) usart_send_sync() in simplex mode - (++) usart_recv_sync() in full duplex receive only - (++) usart_send_recv_sync() in full duplex mode + (++) ald_usart_send_sync() in simplex mode + (++) ald_usart_recv_sync() in full duplex receive only + (++) ald_usart_send_recv_sync() in full duplex mode (#) Non Blocking mode APIs with Interrupt are : - (++) usart_send_by_it_sync()in simplex mode - (++) usart_recv_by_it_sync() in full duplex receive only - (++) usart_send_recv_by_it_sync() in full duplex mode - (++) usart_irq_handle() + (++) ald_usart_send_by_it_sync()in simplex mode + (++) ald_usart_recv_by_it_sync() in full duplex receive only + (++) ald_usart_send_recv_by_it_sync() in full duplex mode + (++) ald_usart_irq_handler() (#) Non Blocking mode functions with DMA are : - (++) usart_send_by_dma_sync()in simplex mode - (++) usart_recv_by_dma_sync() in full duplex receive only + (++) ald_usart_send_by_dma_sync()in simplex mode + (++) ald_usart_recv_by_dma_sync() in full duplex receive only (++) usart_send_recv_by_dma_symc() in full duplex mode - (++) usart_dma_pause() - (++) usart_dma_resume() - (++) usart_dma_stop() + (++) ald_usart_dma_pause() + (++) ald_usart_dma_resume() + (++) ald_usart_dma_stop() (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) hperh->tx_cplt_cbk() @@ -888,7 +888,7 @@ ald_status_t usart_recv_by_dma(usart_handle_t *hperh, uint8_t *buf, uint16_t siz * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { if (hperh->state != USART_STATE_READY) return BUSY; @@ -945,7 +945,7 @@ ald_status_t usart_send_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +ald_status_t ald_usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) { if (hperh->state != USART_STATE_READY) return BUSY; @@ -1024,7 +1024,7 @@ ald_status_t usart_recv_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, * @param timeout: Timeout duration * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) +ald_status_t ald_usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) { if (hperh->state != USART_STATE_READY) return BUSY; @@ -1114,7 +1114,7 @@ ald_status_t usart_send_recv_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_ * @retval Status, see @ref ald_status_t. * @note The USART errors are not managed to avoid the overrun error. */ -ald_status_t usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { if (hperh->state != USART_STATE_READY) return BUSY; @@ -1140,7 +1140,7 @@ ald_status_t usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t */ __UNLOCK(hperh); - usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); return OK; } @@ -1153,7 +1153,7 @@ ald_status_t usart_send_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t * @param size: Amount of data to be received * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size) +ald_status_t ald_usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size) { if (hperh->state != USART_STATE_READY) return BUSY; @@ -1170,9 +1170,9 @@ ald_status_t usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t hperh->state = USART_STATE_BUSY_RX; __UNLOCK(hperh); - usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); - usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); WRITE_REG(hperh->perh->DATA, (DUMMY_DATA & (uint16_t)0x01FF)); return OK; @@ -1187,7 +1187,7 @@ ald_status_t usart_recv_by_it_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t * @param size: Amount of data to be received * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) +ald_status_t ald_usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) { if (hperh->state != USART_STATE_READY) return BUSY; @@ -1207,10 +1207,10 @@ ald_status_t usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, hperh->state = USART_STATE_BUSY_TX_RX; __UNLOCK(hperh); - usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); - usart_interrupt_config(hperh, USART_IT_PE, ENABLE); - usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); - usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_TXE, ENABLE); return OK; } @@ -1225,7 +1225,7 @@ ald_status_t usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_buf, * @param channel: DMA channel as USART transmit * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +ald_status_t ald_usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) { if (hperh->state != USART_STATE_READY) return BUSY; @@ -1251,7 +1251,7 @@ ald_status_t usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_ hperh->hdmatx.err_arg = (void *)hperh; /* Configure DMA transmit */ - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; hperh->hdmatx.config.size = size; @@ -1268,10 +1268,10 @@ ald_status_t usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_ hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; } - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); __UNLOCK(hperh); - usart_clear_flag_status(hperh, USART_FLAG_TC); + ald_usart_clear_flag_status(hperh, USART_FLAG_TC); SET_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); return OK; @@ -1289,7 +1289,7 @@ ald_status_t usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_ * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. */ -ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) +ald_status_t ald_usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) { if (hperh->state != USART_STATE_READY) return BUSY; @@ -1308,6 +1308,7 @@ ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_ if (hperh->hdmatx.perh == NULL) hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) hperh->hdmarx.perh = DMA0; @@ -1318,7 +1319,7 @@ ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_ hperh->hdmarx.err_arg = (void *)hperh; /* Configure DMA receive*/ - dma_config_struct(&hperh->hdmarx.config); + ald_dma_config_struct(&hperh->hdmarx.config); hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)buf; hperh->hdmarx.config.size = size; @@ -1335,13 +1336,13 @@ ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_ hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; } - dma_config_basic(&hperh->hdmarx); + ald_dma_config_basic(&hperh->hdmarx); /* Enable the USART transmit DMA channel: the transmit channel is used in order * to generate in the non-blocking mode the clock to the slave device, * this mode isn't a simplex receive mode but a full-duplex receive one */ - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; hperh->hdmatx.config.size = size; @@ -1358,7 +1359,7 @@ ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_ hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; } - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); USART_CLEAR_OREFLAG(hperh); __UNLOCK(hperh); @@ -1380,7 +1381,7 @@ ald_status_t usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_ * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, +ald_status_t ald_usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) { if (hperh->state != USART_STATE_READY) @@ -1400,6 +1401,7 @@ ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, if (hperh->hdmatx.perh == NULL) hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) hperh->hdmarx.perh = DMA0; @@ -1414,7 +1416,7 @@ ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, hperh->hdmarx.err_arg = (void *)hperh; /* Configure DMA receive */ - dma_config_struct(&hperh->hdmarx.config); + ald_dma_config_struct(&hperh->hdmarx.config); hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; hperh->hdmarx.config.dst = (void *)rx_buf; hperh->hdmarx.config.size = size; @@ -1431,10 +1433,10 @@ ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; } - dma_config_basic(&hperh->hdmarx); + ald_dma_config_basic(&hperh->hdmarx); /* Configure DMA transmit*/ - dma_config_struct(&hperh->hdmatx.config); + ald_dma_config_struct(&hperh->hdmatx.config); hperh->hdmatx.config.src = (void *)tx_buf; hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; hperh->hdmatx.config.size = size; @@ -1451,9 +1453,9 @@ ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; } - dma_config_basic(&hperh->hdmatx); + ald_dma_config_basic(&hperh->hdmatx); - usart_clear_flag_status(hperh, USART_FLAG_TC); + ald_usart_clear_flag_status(hperh, USART_FLAG_TC); USART_CLEAR_OREFLAG(hperh); __UNLOCK(hperh); SET_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); @@ -1477,7 +1479,7 @@ ald_status_t usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf, * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_dma_pause(usart_handle_t *hperh) +ald_status_t ald_usart_dma_pause(usart_handle_t *hperh) { __LOCK(hperh); @@ -1510,7 +1512,7 @@ ald_status_t usart_dma_pause(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_dma_resume(usart_handle_t *hperh) +ald_status_t ald_usart_dma_resume(usart_handle_t *hperh) { __LOCK(hperh); @@ -1545,7 +1547,7 @@ ald_status_t usart_dma_resume(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_dma_stop(usart_handle_t *hperh) +ald_status_t ald_usart_dma_stop(usart_handle_t *hperh) { CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); CLEAR_BIT(hperh->perh->CON2, USART_CON2_RXDMAEN_MSK); @@ -1560,36 +1562,41 @@ ald_status_t usart_dma_stop(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval None */ -void usart_irq_handle(usart_handle_t *hperh) +void ald_usart_irq_handler(usart_handle_t *hperh) { uint32_t flag; uint32_t source; /* Handle parity error */ - flag = usart_get_flag_status(hperh, USART_FLAG_PE); - source = usart_get_it_status(hperh, USART_IT_PE); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_PE); + source = ald_usart_get_it_status(hperh, USART_IT_PE); + if ((flag != RESET) && (source != RESET)) hperh->err_code |= USART_ERROR_PE; /* Handle frame error */ - flag = usart_get_flag_status(hperh, USART_FLAG_FE); - source = usart_get_it_status(hperh, USART_IT_ERR); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_FE); + source = ald_usart_get_it_status(hperh, USART_IT_ERR); + if ((flag != RESET) && (source != RESET)) hperh->err_code |= USART_ERROR_FE; /* Handle noise error */ - flag = usart_get_flag_status(hperh, USART_FLAG_NE); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_NE); + if ((flag != RESET) && (source != RESET)) hperh->err_code |= USART_ERROR_NE; /* Handle overrun error */ - flag = usart_get_flag_status(hperh, USART_FLAG_ORE); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_ORE); + if ((flag != RESET) && (source != RESET)) hperh->err_code |= USART_ERROR_ORE; /* Handle idle error */ - flag = usart_get_flag_status(hperh, USART_FLAG_IDLE); - source = usart_get_it_status(hperh, USART_IT_IDLE); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_IDLE); + source = ald_usart_get_it_status(hperh, USART_IT_IDLE); + if ((flag != RESET) && (source != RESET)) __usart_recv_frame_cplt(hperh); @@ -1597,22 +1604,25 @@ void usart_irq_handle(usart_handle_t *hperh) if (READ_BIT(hperh->perh->CON1, USART_CON1_SCKEN_MSK) == 0) { /* Receiver */ - flag = usart_get_flag_status(hperh, USART_FLAG_RXNE); - source = usart_get_it_status(hperh, USART_IT_RXNE); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_RXNE); + source = ald_usart_get_it_status(hperh, USART_IT_RXNE); + if ((flag != RESET) && (source != RESET)) __usart_recv_by_it(hperh); /* Transmitter */ - flag = usart_get_flag_status(hperh, USART_FLAG_TXE); - source = usart_get_it_status(hperh, USART_IT_TXE); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_TXE); + source = ald_usart_get_it_status(hperh, USART_IT_TXE); + if ((flag != RESET) && (source != RESET)) __usart_send_by_it(hperh); } - else /* Handle synchronous */ + else /* Handle synchronous */ { /* Receiver */ - flag = usart_get_flag_status(hperh, USART_FLAG_RXNE); - source = usart_get_it_status(hperh, USART_IT_RXNE); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_RXNE); + source = ald_usart_get_it_status(hperh, USART_IT_RXNE); + if ((flag != RESET) && (source != RESET)) { if (hperh->state == USART_STATE_BUSY_RX) @@ -1622,8 +1632,9 @@ void usart_irq_handle(usart_handle_t *hperh) } /* Transmitter */ - flag = usart_get_flag_status(hperh, USART_FLAG_TXE); - source = usart_get_it_status(hperh, USART_IT_TXE); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_TXE); + source = ald_usart_get_it_status(hperh, USART_IT_TXE); + if ((flag != RESET) && (source != RESET)) { if (hperh->state == USART_STATE_BUSY_TX) @@ -1634,8 +1645,9 @@ void usart_irq_handle(usart_handle_t *hperh) } /* Handle transmitter end */ - flag = usart_get_flag_status(hperh, USART_FLAG_TC); - source = usart_get_it_status(hperh, USART_IT_TC); + flag = ald_usart_get_flag_status(hperh, USART_FLAG_TC); + source = ald_usart_get_it_status(hperh, USART_IT_TC); + if ((flag != RESET) && (source != RESET)) __usart_end_send_by_it(hperh); @@ -1668,14 +1680,14 @@ void usart_irq_handle(usart_handle_t *hperh) [..] This subsection provides a set of functions allowing to control the USART: (+) usart_lin_send_break() API can be helpful to transmit the break character. - (+) usart_multi_processor_enter_mute_mode() API can be helpful to enter the USART in mute mode. - (+) usart_multi_processor_exit_mute_mode() API can be helpful to exit the USART mute mode by software. - (+) usart_half_duplex_enable_send() API to enable the USART transmitter and disables the USART receiver in Half Duplex mode - (+) usart_half_duplex_enable_recv() API to enable the USART receiver and disables the USART transmitter in Half Duplex mode - (+) usart_interrupt_config() API to Enables/Disables the specified USART interrupts - (+) usart_get_flag_status() API to get USART flag status - (+) usart_clear_flag_status() API to clear USART flag status - (+) usart_get_it_status() API to Checks whether the specified USART interrupt has occurred or not + (+) ald_usart_multi_processor_enter_mute_mode() API can be helpful to enter the USART in mute mode. + (+) ald_usart_multi_processor_exit_mute_mode() API can be helpful to exit the USART mute mode by software. + (+) ald_usart_half_duplex_enable_send() API to enable the USART transmitter and disables the USART receiver in Half Duplex mode + (+) ald_usart_half_duplex_enable_recv() API to enable the USART receiver and disables the USART transmitter in Half Duplex mode + (+) ald_usart_interrupt_config() API to Enables/Disables the specified USART interrupts + (+) ald_usart_get_flag_status() API to get USART flag status + (+) ald_usart_clear_flag_status() API to clear USART flag status + (+) ald_usart_get_it_status() API to Checks whether the specified USART interrupt has occurred or not @endverbatim * @{ @@ -1687,7 +1699,7 @@ void usart_irq_handle(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_multi_processor_enter_mute_mode(usart_handle_t *hperh) +ald_status_t ald_usart_multi_processor_enter_mute_mode(usart_handle_t *hperh) { assert_param(IS_USART(hperh->perh)); @@ -1707,7 +1719,7 @@ ald_status_t usart_multi_processor_enter_mute_mode(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_multi_processor_exit_mute_mode(usart_handle_t *hperh) +ald_status_t ald_usart_multi_processor_exit_mute_mode(usart_handle_t *hperh) { assert_param(IS_USART(hperh->perh)); @@ -1727,7 +1739,7 @@ ald_status_t usart_multi_processor_exit_mute_mode(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_half_duplex_enable_send(usart_handle_t *hperh) +ald_status_t ald_usart_half_duplex_enable_send(usart_handle_t *hperh) { __LOCK(hperh); @@ -1746,7 +1758,7 @@ ald_status_t usart_half_duplex_enable_send(usart_handle_t *hperh) * the configuration information for the specified USART module. * @retval Status, see @ref ald_status_t. */ -ald_status_t usart_half_duplex_enable_recv(usart_handle_t *hperh) +ald_status_t ald_usart_half_duplex_enable_recv(usart_handle_t *hperh) { __LOCK(hperh); @@ -1764,14 +1776,14 @@ ald_status_t usart_half_duplex_enable_recv(usart_handle_t *hperh) * @param hperh: Pointer to a usart_handle_t structure that contains * the configuration information for the specified USART module. * @param req: specifies the DMA request. - * @arg USART_dma_req_tx: USART DMA transmit request - * @arg USART_dma_req_rx: USART DMA receive request + * @arg USART_dma_req_tx: USART DMA transmit request + * @arg USART_dma_req_rx: USART DMA receive request * @param state: New state of the DMA Request sources. - * @arg ENABLE + * @arg ENABLE * @arg DISABLE * @return: None */ -void usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_t state) +void ald_usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_t state) { assert_param(IS_USART(hperh->perh)); assert_param(IS_USART_DMAREQ(req)); @@ -1804,7 +1816,7 @@ void usart_dma_req_config(usart_handle_t *hperh, usart_dma_req_t req, type_func_ * - DISABLE * @retval None */ -void usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t state) +void ald_usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t state) { uint8_t idx; @@ -1850,7 +1862,7 @@ void usart_interrupt_config(usart_handle_t *hperh, usart_it_t it, type_func_t st * - SET * - RESET */ -flag_status_t usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag) +flag_status_t ald_usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag) { flag_status_t status = RESET; @@ -1880,7 +1892,7 @@ flag_status_t usart_get_flag_status(usart_handle_t *hperh, usart_flag_t flag) * @note TXE flag is cleared only by a write to the USART_DR register. * @retval None */ -void usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag) +void ald_usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag) { assert_param(IS_USART(hperh->perh)); assert_param(IS_USART_CLEAR_FLAG(flag)); @@ -1893,22 +1905,22 @@ void usart_clear_flag_status(usart_handle_t *hperh, usart_flag_t flag) * @param hperh: Pointer to a usart_handle_t structure that contains * the configuration information for the specified USART module. * @param it: Specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ORE: OverRun Error interrupt - * @arg USART_IT_NE: Noise Error interrupt - * @arg USART_IT_FE: Framing Error interrupt - * @arg USART_IT_PE: Parity Error interrupt + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ORE: OverRun Error interrupt + * @arg USART_IT_NE: Noise Error interrupt + * @arg USART_IT_FE: Framing Error interrupt + * @arg USART_IT_PE: Parity Error interrupt * @retval Status * - SET * - RESET */ -it_status_t usart_get_it_status(usart_handle_t *hperh, usart_it_t it) +it_status_t ald_usart_get_it_status(usart_handle_t *hperh, usart_it_t it) { uint8_t idx; it_status_t status = RESET; @@ -1963,8 +1975,8 @@ it_status_t usart_get_it_status(usart_handle_t *hperh, usart_it_t it) This subsection provides a set of functions allowing to return the State of USART communication process, return Peripheral Errors occurred during communication process - (+) usart_get_state() API can be helpful to check in run-time the state of the USART peripheral. - (+) usart_get_error() check in run-time errors that could be occurred during communication. + (+) ald_usart_get_state() API can be helpful to check in run-time the state of the USART peripheral. + (+) ald_usart_get_error() check in run-time errors that could be occurred during communication. @endverbatim * @{ @@ -1976,7 +1988,7 @@ it_status_t usart_get_it_status(usart_handle_t *hperh, usart_it_t it) * the configuration information for the specified USART module. * @retval USART state */ -usart_state_t usart_get_state(usart_handle_t *hperh) +usart_state_t ald_usart_get_state(usart_handle_t *hperh) { return hperh->state; } @@ -1987,7 +1999,7 @@ usart_state_t usart_get_state(usart_handle_t *hperh) * the configuration information for the specified USART. * @retval USART Error Code */ -uint32_t usart_get_error(usart_handle_t *hperh) +uint32_t ald_usart_get_error(usart_handle_t *hperh) { return hperh->err_code; } @@ -2017,7 +2029,7 @@ static void usart_dma_send_cplt(void *arg) hperh->tx_count = 0; CLEAR_BIT(hperh->perh->CON2, USART_CON2_TXDMAEN_MSK); - usart_interrupt_config(hperh, USART_IT_TC, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_TC, ENABLE); } /** @@ -2076,16 +2088,16 @@ static ald_status_t usart_wait_flag(usart_handle_t *hperh, usart_flag_t flag, fl if (timeout == 0) return OK; - tick = __get_tick(); + tick = ald_get_tick(); - while ((usart_get_flag_status(hperh, flag)) != status) + while ((ald_usart_get_flag_status(hperh, flag)) != status) { - if (((__get_tick()) - tick) > timeout) + if (((ald_get_tick()) - tick) > timeout) { - usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); - usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); return TIMEOUT; } @@ -2117,8 +2129,8 @@ static ald_status_t __usart_send_by_it(usart_handle_t *hperh) if (--hperh->tx_count == 0) { - usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); - usart_interrupt_config(hperh, USART_IT_TC, ENABLE); + ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_TC, ENABLE); } return OK; @@ -2133,7 +2145,7 @@ static ald_status_t __usart_send_by_it(usart_handle_t *hperh) */ static ald_status_t __usart_end_send_by_it(usart_handle_t *hperh) { - usart_interrupt_config(hperh, USART_IT_TC, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_TC, DISABLE); CLEAR_BIT(hperh->state, USART_STATE_TX_MASK); if (hperh->tx_cplt_cbk != NULL) @@ -2173,19 +2185,19 @@ static ald_status_t __usart_recv_by_it(usart_handle_t *hperh) *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0x7F); } - if (__frame_mode && ((usart_get_it_status(hperh, USART_IT_IDLE)) == RESET)) - usart_interrupt_config(hperh, USART_IT_IDLE, ENABLE); + if (__frame_mode && ((ald_usart_get_it_status(hperh, USART_IT_IDLE)) == RESET)) + ald_usart_interrupt_config(hperh, USART_IT_IDLE, ENABLE); if (--hperh->rx_count == 0) { - usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); __frame_mode = 0; if (hperh->state == USART_STATE_READY) { - usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); } if (hperh->rx_cplt_cbk != NULL) @@ -2206,8 +2218,8 @@ static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh) if ((hperh->state != USART_STATE_BUSY_RX) && (hperh->state != USART_STATE_BUSY_TX_RX)) return BUSY; - usart_interrupt_config(hperh, USART_IT_IDLE, DISABLE); - usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_IDLE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); CLEAR_BIT(hperh->state, USART_STATE_RX_MASK); __frame_mode = 0; @@ -2215,8 +2227,8 @@ static ald_status_t __usart_recv_frame_cplt(usart_handle_t *hperh) if (hperh->state == USART_STATE_READY) { - usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); } if (hperh->rx_cplt_cbk != NULL) @@ -2267,9 +2279,9 @@ static ald_status_t __usart_recv_by_it_sync(usart_handle_t *hperh) if (hperh->rx_count == 0) { - usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); hperh->state = USART_STATE_READY; if (hperh->rx_cplt_cbk != NULL) @@ -2292,7 +2304,7 @@ static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh) if (hperh->tx_count != 0) { - if (usart_get_flag_status(hperh, USART_FLAG_TXE) != RESET) + if (ald_usart_get_flag_status(hperh, USART_FLAG_TXE) != RESET) { if (hperh->init.word_length == USART_WORD_LENGTH_9B) { @@ -2312,13 +2324,13 @@ static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh) } if (--hperh->tx_count == 0) - usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_TXE, DISABLE); } } if (hperh->rx_count != 0) { - if (usart_get_flag_status(hperh, USART_FLAG_RXNE) != RESET) + if (ald_usart_get_flag_status(hperh, USART_FLAG_RXNE) != RESET) { if (hperh->init.word_length == USART_WORD_LENGTH_9B) { @@ -2346,9 +2358,9 @@ static ald_status_t __usart_send_recv_by_it_sync(usart_handle_t *hperh) if (hperh->rx_count == 0) { - usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); - usart_interrupt_config(hperh, USART_IT_PE, DISABLE); - usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_RXNE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_PE, DISABLE); + ald_usart_interrupt_config(hperh, USART_IT_ERR, DISABLE); hperh->state = USART_STATE_READY; @@ -2407,13 +2419,14 @@ static void usart_set_config(usart_handle_t *hperh) if (READ_BIT(hperh->perh->CON0, (1 << 15))) { /* Integer part computing in case Oversampling mode is 8 Samples */ - integer = ((25 * cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); + integer = ((25 * ald_cmu_get_pclk1_clock()) / (2 * (hperh->init.baud))); } else { /* Integer part computing in case Oversampling mode is 16 Samples */ - integer = ((25 * cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); + integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud))); } + tmp = (integer / 100) << 4; /* Determine the fractional part */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c similarity index 88% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c index cbe2921ee939947cf972ed3c48a6172138e76e66..acf092a2788b3ff79ca0e9ede781eeb8985f1077 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_wdt.c @@ -44,7 +44,7 @@ * @param interrupt: Enable or disable interrupt. * @retval None */ -void wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt) +void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt) { assert_param(IS_WWDT_WIN_TYPE(win)); assert_param(IS_FUNC_STATE(interrupt)); @@ -64,7 +64,7 @@ void wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt) * @brief Start the WWDT * @retval None */ -void wwdt_start(void) +void ald_wwdt_start(void) { WWDT_UNLOCK(); SET_BIT(WWDT->CON, WWDT_CON_EN_MSK); @@ -77,7 +77,7 @@ void wwdt_start(void) * @brief Get the free-running downcounter value * @retval Value */ -uint32_t wwdt_get_value(void) +uint32_t ald_wwdt_get_value(void) { return WWDT->VALUE; } @@ -86,7 +86,7 @@ uint32_t wwdt_get_value(void) * @brief Get interrupt state * @retval Value */ -it_status_t wwdt_get_flag_status(void) +it_status_t ald_wwdt_get_flag_status(void) { if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK)) return SET; @@ -98,7 +98,7 @@ it_status_t wwdt_get_flag_status(void) * @brief Clear interrupt state * @retval None */ -void wwdt_clear_flag_status(void) +void ald_wwdt_clear_flag_status(void) { WRITE_REG(WWDT->INTCLR, 1); return; @@ -108,7 +108,7 @@ void wwdt_clear_flag_status(void) * @brief Refreshes the WWDT * @retval None */ -void wwdt_feed_dog(void) +void ald_wwdt_feed_dog(void) { WWDT_UNLOCK(); WRITE_REG(WWDT->INTCLR, 0x1); @@ -130,7 +130,7 @@ void wwdt_feed_dog(void) * @param interrupt: Enable or disable interrupt. * @retval None */ -void iwdt_init(uint32_t load, type_func_t interrupt) +void ald_iwdt_init(uint32_t load, type_func_t interrupt) { assert_param(IS_FUNC_STATE(interrupt)); @@ -148,7 +148,7 @@ void iwdt_init(uint32_t load, type_func_t interrupt) * @brief Start the IWDT * @retval None */ -void iwdt_start(void) +void ald_iwdt_start(void) { IWDT_UNLOCK(); SET_BIT(IWDT->CON, IWDT_CON_EN_MSK); @@ -161,7 +161,7 @@ void iwdt_start(void) * @brief Get the free-running downcounter value * @retval Value */ -uint32_t iwdt_get_value(void) +uint32_t ald_iwdt_get_value(void) { return IWDT->VALUE; } @@ -170,7 +170,7 @@ uint32_t iwdt_get_value(void) * @brief Get interrupt state * @retval Value */ -it_status_t iwdt_get_flag_status(void) +it_status_t ald_iwdt_get_flag_status(void) { if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK)) return SET; @@ -182,7 +182,7 @@ it_status_t iwdt_get_flag_status(void) * @brief Clear interrupt state * @retval None */ -void iwdt_clear_flag_status(void) +void ald_iwdt_clear_flag_status(void) { WRITE_REG(IWDT->INTCLR, 1); return; @@ -192,7 +192,7 @@ void iwdt_clear_flag_status(void) * @brief Refreshes the WWDT * @retval None */ -void iwdt_feed_dog(void) +void ald_iwdt_feed_dog(void) { IWDT_UNLOCK(); WRITE_REG(IWDT->INTCLR, 1); diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c similarity index 78% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c rename to bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c index 24c6bfdf45b724b9dbc87c6dc178b4d758266ee8..596bc38fbf686078a559693810e977ca37da7955 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c +++ b/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/utils.c @@ -37,14 +37,14 @@ /** * @brief ALD version number */ -#define __ALD_VERSION_MAIN (0x01) /**< [31:24] main version */ -#define __ALD_VERSION_SUB1 (0x00) /**< [23:16] sub1 version */ -#define __ALD_VERSION_SUB2 (0x00) /**< [15:8] sub2 version */ -#define __ALD_VERSION_RC (0x00) /**< [7:0] release candidate */ -#define __ALD_VERSION ((__ALD_VERSION_MAIN << 24) | \ - (__ALD_VERSION_SUB1 << 16) | \ - (__ALD_VERSION_SUB2 << 8 ) | \ - (__ALD_VERSION_RC)) +#define __ALD_VERSION_MAIN (0x01) /**< [31:24] main version */ +#define __ALD_VERSION_SUB1 (0x00) /**< [23:16] sub1 version */ +#define __ALD_VERSION_SUB2 (0x00) /**< [15:8] sub2 version */ +#define __ALD_VERSION_RC (0x00) /**< [7:0] release candidate */ +#define __ALD_VERSION ((__ALD_VERSION_MAIN << 24) | \ + (__ALD_VERSION_SUB1 << 16) | \ + (__ALD_VERSION_SUB2 << 8 ) | \ + (__ALD_VERSION_RC)) /** * @} */ @@ -82,11 +82,11 @@ uint32_t __systick_interval = SYSTICK_INTERVAL_1MS; can eventually implement his proper time base source (a general purpose timer for example or other time source), keeping in mind that Time base duration should be kept 1ms. - (++) Time base configuration function (__init_tick()) is called automatically - at the beginning of the program after reset by mcu_ald_init() or at - any time when clock is configured. + (++) Time base configuration function (ald_tick_init()) is called automatically + at the beginning of the program after reset by ald_cmu_init() or at + any time when clock is configured. (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if __delay_ms() is called from a + time intervals. Care must be taken if ald_delay_ms() is called from a peripheral ISR process, the Tick interrupt line must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. @@ -108,12 +108,12 @@ uint32_t __systick_interval = SYSTICK_INTERVAL_1MS; * The tick variable is incremented each 1ms in its ISR. * @retval None */ -void mcu_ald_init(void) +void ald_cmu_init(void) { - cmu_clock_config_default(); - __init_tick(TICK_INT_PRIORITY); + ald_cmu_clock_config_default(); + ald_tick_init(TICK_INT_PRIORITY); #ifdef ALD_DMA - dma_init(DMA0); + ald_dma_init(DMA0); #endif return; } @@ -124,7 +124,7 @@ void mcu_ald_init(void) * Tick interrupt priority. * @note In the default implementation, SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals. - * Care must be taken if __delay_ms() is called from a peripheral ISR process, + * Care must be taken if ald_delay_ms() is called from a peripheral ISR process, * The SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __weak to be overwritten in case of other @@ -132,10 +132,10 @@ void mcu_ald_init(void) * @param prio: Tick interrupt priority. * @retval None */ -__weak void __init_tick(uint32_t prio) +__weak void ald_tick_init(uint32_t prio) { /* Configure the SysTick IRQ */ - SysTick_Config(cmu_get_clock() / SYSTICK_INTERVAL_1MS); + SysTick_Config(ald_cmu_get_sys_clock() / SYSTICK_INTERVAL_1MS); if (prio != 3) NVIC_SetPriority(SysTick_IRQn, prio); @@ -152,11 +152,11 @@ __weak void __init_tick(uint32_t prio) * @arg @ref SYSTICK_INTERVAL_1000MS 1 second * @retval None */ -void systick_interval_select(systick_interval_t value) +void ald_systick_interval_select(systick_interval_t value) { assert_param(IS_SYSTICK_INTERVAL(value)); - SysTick_Config(cmu_get_clock() / value); + SysTick_Config(ald_cmu_get_sys_clock() / value); __systick_interval = value; if (TICK_INT_PRIORITY != 3) @@ -198,7 +198,7 @@ void systick_interval_select(systick_interval_t value) * implementations in user file. * @retval None */ -__weak void __inc_tick(void) +__weak void ald_inc_tick_weak(void) { ++lib_tick; } @@ -209,7 +209,7 @@ __weak void __inc_tick(void) * other implementations in user file. * @retval None */ -__weak void systick_irq_cbk(void) +__weak void ald_systick_irq_cbk(void) { /* do nothing */ return; @@ -219,10 +219,10 @@ __weak void systick_irq_cbk(void) * @brief This function invoked by Systick ISR each 1ms. * @retval None */ -__isr__ void SysTick_Handler(void) +__isr__ void ald_inc_tick(void) { - __inc_tick(); - systick_irq_cbk(); + ald_inc_tick_weak(); + ald_systick_irq_cbk(); return; } @@ -233,7 +233,7 @@ __isr__ void SysTick_Handler(void) * implementations in user file. * @retval tick value */ -__weak uint32_t __get_tick(void) +__weak uint32_t ald_get_tick(void) { return lib_tick; } @@ -249,37 +249,37 @@ __weak uint32_t __get_tick(void) * @param delay: specifies the delay time length, in milliseconds. * @retval None */ -__weak void __delay_ms(__IO uint32_t delay) +__weak void ald_delay_ms(__IO uint32_t delay) { uint32_t tick, __delay; switch (__systick_interval) { - case SYSTICK_INTERVAL_1MS: - __delay = delay; - break; + case SYSTICK_INTERVAL_1MS: + __delay = delay; + break; - case SYSTICK_INTERVAL_10MS: - __delay = delay / 10; - break; + case SYSTICK_INTERVAL_10MS: + __delay = delay / 10; + break; - case SYSTICK_INTERVAL_100MS: - __delay = delay / 100; - break; + case SYSTICK_INTERVAL_100MS: + __delay = delay / 100; + break; - case SYSTICK_INTERVAL_1000MS: - __delay = delay / 1000; - break; + case SYSTICK_INTERVAL_1000MS: + __delay = delay / 1000; + break; - default: - __delay = delay; - break; + default: + __delay = delay; + break; } - tick = __get_tick(); + tick = ald_get_tick(); __delay = __delay == 0 ? 1 : __delay; - while ((__get_tick() - tick) < __delay) + while ((ald_get_tick() - tick) < __delay) ; } @@ -287,13 +287,13 @@ __weak void __delay_ms(__IO uint32_t delay) * @brief Suspend Tick increment. * @note In the default implementation, SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals. - * Once __suspend_tick() is called, the the SysTick interrupt + * Once ald_suspend_tick() is called, the the SysTick interrupt * will be disabled and so Tick increment is suspended. * @note This function is declared as __weak to be overwritten * in case of other implementations in user file. * @retval None */ -__weak void __suspend_tick(void) +__weak void ald_suspend_tick(void) { CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } @@ -302,13 +302,13 @@ __weak void __suspend_tick(void) * @brief Resume Tick increment. * @note In the default implementation, SysTick timer is the source of * time base. It is used to generate interrupts at regular time - * intervals. Once __resume_tick() is called, the the SysTick + * intervals. Once ald_resume_tick() is called, the the SysTick * interrupt will be enabled and so Tick increment is resumed. * @note This function is declared as __weak to be overwritten * in case of other implementations in user file. * @retval None */ -__weak void __resume_tick(void) +__weak void ald_resume_tick(void) { SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } @@ -317,7 +317,7 @@ __weak void __resume_tick(void) * @brief This method returns the ALD revision * @retval version: 0xXYZR (8bits for each decimal, R for RC) */ -uint32_t get_ald_version(void) +uint32_t ald_get_ald_version(void) { return __ALD_VERSION; } @@ -330,9 +330,9 @@ uint32_t get_ald_version(void) * @param timeout: Timeout duration. * @retval Status, see @ref ald_status_t. */ -ald_status_t __wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout) +ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout) { - uint32_t tick = __get_tick(); + uint32_t tick = ald_get_tick(); assert_param(timeout > 0); @@ -340,7 +340,7 @@ ald_status_t __wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint { while (!(IS_BIT_SET(*reg, bit))) { - if (((__get_tick()) - tick) > timeout) + if (((ald_get_tick()) - tick) > timeout) return TIMEOUT; } } @@ -348,7 +348,7 @@ ald_status_t __wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint { while ((IS_BIT_SET(*reg, bit))) { - if (((__get_tick()) - tick) > timeout) + if (((ald_get_tick()) - tick) > timeout) return TIMEOUT; } } @@ -365,7 +365,7 @@ ald_status_t __wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint * @arg DISABLE * @retval None */ -void mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status) +void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status) { assert_param(IS_FUNC_STATE(status)); assert_param(IS_PRIO(prio)); @@ -387,7 +387,7 @@ void mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status) * @brief Get the system tick. * @retval The value of current tick. */ -uint32_t mcu_get_tick(void) +uint32_t ald_mcu_get_tick(void) { uint32_t load = SysTick->LOAD; uint32_t val = SysTick->VAL; @@ -399,7 +399,7 @@ uint32_t mcu_get_tick(void) * @brief Get the CPU ID. * @retval CPU ID. */ -uint32_t mcu_get_cpu_id(void) +uint32_t ald_mcu_get_cpu_id(void) { return SCB->CPUID; } diff --git a/bsp/es32f0654/libraries/SConscript b/bsp/essemi/es32f0654/libraries/SConscript similarity index 96% rename from bsp/es32f0654/libraries/SConscript rename to bsp/essemi/es32f0654/libraries/SConscript index 6da75a02629767c304c912112f550f5771f0bfd9..04d2eae28bb8174139ab3648b61ab67275534d0b 100644 --- a/bsp/es32f0654/libraries/SConscript +++ b/bsp/essemi/es32f0654/libraries/SConscript @@ -22,6 +22,6 @@ path = [cwd + '/CMSIS/Device/EastSoft/ES32F065x/Include', cwd + '/CMSIS/Include', cwd + '/ES32F065x_ALD_StdPeriph_Driver/Include'] -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = ['ES32F065x']) Return('group') diff --git a/bsp/es32f0654/project.uvoptx b/bsp/essemi/es32f0654/project.uvoptx similarity index 100% rename from bsp/es32f0654/project.uvoptx rename to bsp/essemi/es32f0654/project.uvoptx diff --git a/bsp/es32f0654/project.uvprojx b/bsp/essemi/es32f0654/project.uvprojx similarity index 90% rename from bsp/es32f0654/project.uvprojx rename to bsp/essemi/es32f0654/project.uvprojx index e51102987c94bb8681c99b7cfd05d1b09d715ff2..724ef242af1bedcc7be2d89e261205f5ba19420a 100644 --- a/bsp/es32f0654/project.uvprojx +++ b/bsp/essemi/es32f0654/project.uvprojx @@ -330,9 +330,9 @@ 0 - + ES32F065x - .;..\..\include;applications;.;drivers;libraries\CMSIS\Device\EastSoft\ES32F065x\Include;libraries\CMSIS\Include;libraries\ES32F065x_ALD_StdPeriph_Driver\Include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\common + .;..\..\..\include;applications;.;drivers;libraries\CMSIS\Device\EastSoft\ES32F065x\Include;libraries\CMSIS\Include;libraries\ES32F065x_ALD_StdPeriph_Driver\Include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common @@ -379,105 +379,98 @@ clock.c 1 - ..\..\src\clock.c + ..\..\..\src\clock.c components.c 1 - ..\..\src\components.c - - - - - cpu.c - 1 - ..\..\src\cpu.c + ..\..\..\src\components.c device.c 1 - ..\..\src\device.c + ..\..\..\src\device.c idle.c 1 - ..\..\src\idle.c + ..\..\..\src\idle.c ipc.c 1 - ..\..\src\ipc.c + ..\..\..\src\ipc.c irq.c 1 - ..\..\src\irq.c + ..\..\..\src\irq.c kservice.c 1 - ..\..\src\kservice.c + ..\..\..\src\kservice.c mem.c 1 - ..\..\src\mem.c + ..\..\..\src\mem.c mempool.c 1 - ..\..\src\mempool.c + ..\..\..\src\mempool.c object.c 1 - ..\..\src\object.c + ..\..\..\src\object.c scheduler.c 1 - ..\..\src\scheduler.c + ..\..\..\src\scheduler.c signal.c 1 - ..\..\src\signal.c + ..\..\..\src\signal.c thread.c 1 - ..\..\src\thread.c + ..\..\..\src\thread.c timer.c 1 - ..\..\src\timer.c + ..\..\..\src\timer.c @@ -587,6 +580,13 @@ libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash.c + + + ald_flash_ext.c + 1 + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + + ald_gpio.c @@ -652,23 +652,23 @@ - ald_temp.c + ald_timer.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_temp.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_timer.c - ald_timer.c + ald_trng.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_timer.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_trng.c - ald_trng.c + ald_tsense.c 1 - libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_trng.c + libraries\ES32F065x_ALD_StdPeriph_Driver\Source\ald_tsense.c @@ -713,35 +713,35 @@ backtrace.c 1 - ..\..\libcpu\arm\common\backtrace.c + ..\..\..\libcpu\arm\common\backtrace.c div0.c 1 - ..\..\libcpu\arm\common\div0.c + ..\..\..\libcpu\arm\common\div0.c showmem.c 1 - ..\..\libcpu\arm\common\showmem.c + ..\..\..\libcpu\arm\common\showmem.c cpuport.c 1 - ..\..\libcpu\arm\cortex-m0\cpuport.c + ..\..\..\libcpu\arm\cortex-m0\cpuport.c context_rvds.S 2 - ..\..\libcpu\arm\cortex-m0\context_rvds.S + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S @@ -751,63 +751,63 @@ pin.c 1 - ..\..\components\drivers\misc\pin.c + ..\..\..\components\drivers\misc\pin.c serial.c 1 - ..\..\components\drivers\serial\serial.c + ..\..\..\components\drivers\serial\serial.c completion.c 1 - ..\..\components\drivers\src\completion.c + ..\..\..\components\drivers\src\completion.c dataqueue.c 1 - ..\..\components\drivers\src\dataqueue.c + ..\..\..\components\drivers\src\dataqueue.c pipe.c 1 - ..\..\components\drivers\src\pipe.c + ..\..\..\components\drivers\src\pipe.c ringblk_buf.c 1 - ..\..\components\drivers\src\ringblk_buf.c + ..\..\..\components\drivers\src\ringblk_buf.c ringbuffer.c 1 - ..\..\components\drivers\src\ringbuffer.c + ..\..\..\components\drivers\src\ringbuffer.c waitqueue.c 1 - ..\..\components\drivers\src\waitqueue.c + ..\..\..\components\drivers\src\waitqueue.c workqueue.c 1 - ..\..\components\drivers\src\workqueue.c + ..\..\..\components\drivers\src\workqueue.c @@ -817,21 +817,21 @@ shell.c 1 - ..\..\components\finsh\shell.c + ..\..\..\components\finsh\shell.c cmd.c 1 - ..\..\components\finsh\cmd.c + ..\..\..\components\finsh\cmd.c msh.c 1 - ..\..\components\finsh\msh.c + ..\..\..\components\finsh\msh.c diff --git a/bsp/es32f0654/rtconfig.h b/bsp/essemi/es32f0654/rtconfig.h similarity index 95% rename from bsp/es32f0654/rtconfig.h rename to bsp/essemi/es32f0654/rtconfig.h index 61cd5f891d7dff921be4cbcce1685f2f1768a515..ab25a2d01bb306cf3e2e58e9be2d2783045171c4 100644 --- a/bsp/es32f0654/rtconfig.h +++ b/bsp/essemi/es32f0654/rtconfig.h @@ -39,7 +39,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart2" -#define RT_VER_NUM 0x40001 +#define RT_VER_NUM 0x40002 /* RT-Thread Components */ @@ -78,9 +78,6 @@ #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN -/* Using WiFi */ - - /* Using USB */ @@ -92,10 +89,10 @@ /* Socket abstraction layer */ -/* light weight TCP/IP stack */ +/* Network interface device */ -/* Modbus master and slave stack */ +/* light weight TCP/IP stack */ /* AT commands */ @@ -144,13 +141,8 @@ /* miscellaneous packages */ -/* sample package */ - /* samples: kernel and components samples */ - -/* example package: hello */ - #define SOC_ES32F0654LT /* Hardware Drivers Config */ diff --git a/bsp/essemi/es32f0654/rtconfig.py b/bsp/essemi/es32f0654/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..eb371bf3a7199a3b5530611d6fb7f0dc26bf5600 --- /dev/null +++ b/bsp/essemi/es32f0654/rtconfig.py @@ -0,0 +1,135 @@ +import os +import sys + +# toolchains options +CROSS_TOOL = 'keil' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# device options +ARCH = 'arm' +CPU = 'cortex-m0' + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': # not support gcc yet + PLATFORM = 'gcc' + EXEC_PATH = 'C:/GCC' + +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil' + +elif CROSS_TOOL == 'iar': # not support iar yet + PLATFORM = 'iar' + EXEC_PATH = 'C:/IAR' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --device DARMSTM' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + LFLAGS = ' --config "drivers\linker_scripts\link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS += ' --entry __iar_program_start' + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/es32f0654/template.uvoptx b/bsp/essemi/es32f0654/template.uvoptx similarity index 100% rename from bsp/es32f0654/template.uvoptx rename to bsp/essemi/es32f0654/template.uvoptx diff --git a/bsp/es32f0654/template.uvprojx b/bsp/essemi/es32f0654/template.uvprojx similarity index 100% rename from bsp/es32f0654/template.uvprojx rename to bsp/essemi/es32f0654/template.uvprojx diff --git a/bsp/essemi/es32f369x/.config b/bsp/essemi/es32f369x/.config new file mode 100644 index 0000000000000000000000000000000000000000..87c4c09d7c540275ee348698bd538c71e205c874 --- /dev/null +++ b/bsp/essemi/es32f369x/.config @@ -0,0 +1,434 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x40002 +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +CONFIG_RT_USING_CAN=y +# CONFIG_RT_CAN_USING_HDR is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_USING_I2C_BITOPS is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_LIBC_USING_TIME is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +CONFIG_SOC_ES32F3696LT=y + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y + +# +# UART Drivers +# +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set + +# +# SPI Drivers +# +# CONFIG_BSP_USING_SPI0 is not set +# CONFIG_BSP_USING_SPI1 is not set +# CONFIG_BSP_USING_SPI2 is not set + +# +# I2C Drivers +# +# CONFIG_BSP_USING_I2C0 is not set +# CONFIG_BSP_USING_I2C1 is not set + +# +# CAN Drivers +# +# CONFIG_BSP_USING_CAN is not set + +# +# Onboard Peripheral Drivers +# + +# +# Offboard Peripheral Drivers +# diff --git a/bsp/essemi/es32f369x/Kconfig b/bsp/essemi/es32f369x/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..b9233eeb6c77e4fec6bee708b91e53eeddd72268 --- /dev/null +++ b/bsp/essemi/es32f369x/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_ES32F3696LT + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "drivers/Kconfig" diff --git a/bsp/essemi/es32f369x/README.md b/bsp/essemi/es32f369x/README.md new file mode 100644 index 0000000000000000000000000000000000000000..5b20eacc33adcda6e92760f5bd96793335b1192f --- /dev/null +++ b/bsp/essemi/es32f369x/README.md @@ -0,0 +1,98 @@ +# ES-PDS-ES32F369x 开发板 BSP 说明 +标签： EastSoft、国产MCU、Cortex-M3、ES32F3696LT + +## 1. 简介 + +本文档为上海东软载波微电子开发团队为 ES-PDS-ES32F369x 开发板提供的 BSP (板级支持包) 说明。 +通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +### 1.1 开发板介绍 + +主要内容如下： +ES-PDS-ES32F369x 是东软载波微电子官方推出的一款基于 ARM Cortex-M3 内核的开发板，最高主频为 96MHz，可满足基础功能测试及高端功能扩展等开发需求。 + +开发板外观如下图所示： + +ES-PDS-ES32F369x-V1.2 + +![ES32F0654](figures/ES-PDS-ES32F369x-V1.2.jpg) + +该开发板常用 **板载资源** 如下： + +- MCU：ES32F3696LT，主频 96MHz，96KB SRAM，512KB FLASH，50 GPIOs +- 外部模块：SPI FLASH (MX25L64，8MB)、I2C EEPROM (M24C04，512B) +- 常用外设 + - 可调电阻：1个(PA05) + - LED：2个，(PF00/PF01) + - 按键：6个，PB02、PB12、PC10、PC11、PC12、RESET(MRST) +- 常用接口：GPIO、UART、SPI、I2C、CAN +- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载 + +外设支持: + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------- | :----------: | :--------------- | +| SPI FLASH | 支持 | SPI0 | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | 50 GPIOs | +| UART | 支持 | UART0/1/2/3/4/5 | +| SPI | 支持 | SPI0/1/2 | +| I2C | 支持 | I2C0/1 | +| CAN | 支持 | CAN0 | + +### 1.2 注意事项 + +更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/) + +## 2. 快速上手 + +本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +### 硬件连接 + +使用 ESLinkⅡ (自带 CDC 串口)或 Jlink 等调试工具连接开发板到 PC，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 UART0_TX(PB10)、UART0_RX(PB11)、GND 接到串口工具上。 + +使用ESlinkⅡ(mini)连接开发板如下图所示： + +ESLinkⅡ(mini) + ES-PDS-ES32F369x-V1.2 + +![ESLinkII](figures/ESLinkII-mini.jpg) + +### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。 + +### 运行结果 + +下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。 +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build Jan 23 2020 + 2006 - 2019 Copyright by rt-thread team +msh> +``` +## 3. 进阶使用 + +此 BSP 默认只开启了 GPIO 和 uart0 的功能，如果需使用更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/) + +## 4. 联系人信息 + +- [wangyongquan](https://github.com/wangyq2018) + +## 5. 参考 + +- [ EastSoft 官网](http://www.essemi.com) + diff --git a/bsp/essemi/es32f369x/SConscript b/bsp/essemi/es32f369x/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..468297b6a99ab9c400a87ed01dcdedc3d60da45d --- /dev/null +++ b/bsp/essemi/es32f369x/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +objs = [] +cwd = str(Dir('#')) +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/synopsys/emsk_em9d/SConstruct b/bsp/essemi/es32f369x/SConstruct similarity index 42% rename from bsp/synopsys/emsk_em9d/SConstruct rename to bsp/essemi/es32f369x/SConstruct index d8e88ebeea97b4e8fbc0f501432d5ad72af89e2a..e75d75371b9d36fe3c5bd73b14db2d5f0fa5a95b 100644 --- a/bsp/synopsys/emsk_em9d/SConstruct +++ b/bsp/essemi/es32f369x/SConstruct @@ -8,7 +8,6 @@ else: RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] - try: from building import * except: @@ -16,38 +15,26 @@ except: print(RTT_ROOT) exit(-1) -TARGET = 'rtthread_snps_emsk_em9d.' + rtconfig.TARGET_EXT - -# use scons --gdb to debug emsk -AddOption('--gdb', - dest = 'gdb', - action = 'store_true', - default = False, - help = 'use gdb to debug the elf') - -if GetOption('gdb'): - if os.path.isfile(rtconfig.TARGET): - os.system(rtconfig.DBG + rtconfig.DBG_HW_FLAGS + rtconfig.TARGET) - else: - print rtconfig.TARGET + 'not exist, please build first!!' - exit(0) +TARGET = 'rtthread.' + rtconfig.TARGET_EXT DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + Export('RTT_ROOT') Export('rtconfig') # prepare building environment -objs = PrepareBuilding(env, RTT_ROOT) - -# if the linker script changed, relink the target -Depends(TARGET, rtconfig.LINK_SCRIPT) +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) # make a building DoBuilding(TARGET, objs) diff --git a/bsp/essemi/es32f369x/applications/SConscript b/bsp/essemi/es32f369x/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..e0c84e8f1426ab2abb2c870cea377371a7c752f3 --- /dev/null +++ b/bsp/essemi/es32f369x/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = os.path.join(str(Dir('#')), 'applications') +src = Glob('*.c') + +CPPPATH = [cwd, str(Dir('#'))] +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/essemi/es32f369x/applications/main.c b/bsp/essemi/es32f369x/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..c8068e94d679303f15969d7fd1400669dbb03ff0 --- /dev/null +++ b/bsp/essemi/es32f369x/applications/main.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + */ + +#include +#include + +#define LED_PIN 18 + +int main(void) +{ + int count = 1; + /* set PF00 pin mode to output */ + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + + while (count++) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + return RT_EOK; +} diff --git a/bsp/essemi/es32f369x/drivers/Kconfig b/bsp/essemi/es32f369x/drivers/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..c96785cbeaaa1d6d51a7b82c7fab8657e686f433 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/Kconfig @@ -0,0 +1,93 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menu "UART Drivers" + config BSP_USING_UART0 + bool "Enable UART0 PB10/PB11(T/R)" + select RT_USING_SERIAL + default n + + config BSP_USING_UART1 + bool "Enable UART1 PC10/PC11(T/R)" + select RT_USING_SERIAL + default n + + config BSP_USING_UART2 + bool "Enable UART2 PC12/PD02(T/R)" + select RT_USING_SERIAL + default y + depends on !BSP_USING_HWTIMER1 + + config BSP_USING_UART3 + bool "Enable UART3 PC04/PC05(T/R)" + select RT_USING_SERIAL + default n + depends on !BSP_USING_HWTIMER2 + + + config BSP_USING_UART4 + bool "Enable UART4 PB06/PB07(T/R)" + select RT_USING_SERIAL + default n + depends on !BSP_USING_I2C0 + + config BSP_USING_UART5 + bool "Enable UART5 PB09/PB08(T/R)" + select RT_USING_SERIAL + default n + endmenu + + menu "SPI Drivers" + config BSP_USING_SPI0 + bool "Enable SPI0 BUS PB03/PB04/PB05(CLK/MISO/MOSI)" + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI1 + bool "Enable SPI1 BUS PC01/PC02/PC03(CLK/MISO/MOSI)" + select RT_USING_SPI + select RT_USING_PIN + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS PC05/PB00/PB01(CLK/MISO/MOSI)" + select RT_USING_SPI + select RT_USING_PIN + default n + endmenu + + menu "I2C Drivers" + config BSP_USING_I2C0 + bool "Enable I2C0 BUS PB08/PB09(SCL/SDA)" + select RT_USING_I2C + default n + + config BSP_USING_I2C1 + bool "Enable I2C1 BUS PB10/PB11(SCL/SDA)" + select RT_USING_I2C + default n + endmenu + + menu "CAN Drivers" + config BSP_USING_CAN + bool "Enable CAN BUS PB08/PB09(RX/TX)" + select RT_USING_CAN + default n + endmenu + endmenu + + menu "Onboard Peripheral Drivers" + + endmenu + + menu "Offboard Peripheral Drivers" + + endmenu + +endmenu diff --git a/bsp/essemi/es32f369x/drivers/SConscript b/bsp/essemi/es32f369x/drivers/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..db84e20b610b9d8d9ca80a9f28d6c4c21f280dc8 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/SConscript @@ -0,0 +1,34 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(''' +board.c +''') + +# add gpio code +if GetDepend('RT_USING_PIN'): + src += ['drv_gpio.c'] + +# add serial driver code +if GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3') or \ + GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5'): + src += ['drv_uart.c'] + +# add spi driver code +if GetDepend('BSP_USING_SPI0') or GetDepend('BSP_USING_SPI1') or GetDepend('BSP_USING_SPI2'): + src += ['drv_spi.c'] + +# add i2c driver code +if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'): + src += ['drv_i2c.c'] + +# add can driver code +if GetDepend('BSP_USING_CAN'): + src += ['drv_can.c'] + +CPPPATH = [cwd] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/essemi/es32f369x/drivers/board.c b/bsp/essemi/es32f369x/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..1c2b8341777a197223aafef8165684c7c81d5189 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/board.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + */ + +#include +#include +#include "board.h" +#include "drv_uart.h" +#include "drv_gpio.h" +#include +#include + +/** + * @addtogroup es32f3 + */ + +/*@{*/ + +/******************************************************************************* +* Function Name : NVIC_Configuration +* Description : Configures Vector Table base location. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void NVIC_Configuration(void) +{ +} + +/******************************************************************************* + * Function Name : SystemClock_Configuration + * Description : Configures the System Clock. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SystemClock_Config(void) +{ + /* hosc 12MHz, from hosc/3 pll to 96MHz */ + ald_cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_96M); + /* SYSCLK 96MHz */ + ald_cmu_clock_config(CMU_CLOCK_PLL1, 96000000); + ald_cmu_perh_clock_config(CMU_PERH_ALL, ENABLE); +} + +/******************************************************************************* + * Function Name : SysTick_Configuration + * Description : Configures the SysTick for OS tick. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SysTick_Configuration(void) +{ + /* ticks = sysclk / RT_TICK_PER_SECOND */ + SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_tick_increase(); + /* leave interrupt */ + rt_interrupt_leave(); +} + +/*@}*/ +/** + * This function will initial ES32F3 board. + */ +void rt_hw_board_init(void) +{ + /* NVIC Configuration */ + NVIC_Configuration(); + /*System Clock Configuration */ + SystemClock_Config(); + /* Configure the SysTick */ + SysTick_Configuration(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} + +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + unsigned int start, now, delta, reload, us_tick; + start = SysTick->VAL; + reload = SysTick->LOAD; + us_tick = ald_cmu_get_sys_clock() / 1000000UL; + do + { + now = SysTick->VAL; + delta = start > now ? start - now : reload + start - now; + } + while (delta < us_tick * us); +} diff --git a/bsp/essemi/es32f369x/drivers/board.h b/bsp/essemi/es32f369x/drivers/board.h new file mode 100644 index 0000000000000000000000000000000000000000..7df17f16714ac01337d12cbebe1708a1148bfb31 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/board.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#define ES32F3_SRAM_SIZE 0x80000 +#define ES32F3_SRAM_END (0x20000000 + ES32F3_SRAM_SIZE) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ + #pragma section="HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern int __bss_end; + #define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END ES32F3_SRAM_END + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_can.c b/bsp/essemi/es32f369x/drivers/drv_can.c new file mode 100644 index 0000000000000000000000000000000000000000..6a887b719be321a97a36f28a37858fa4e30270bc --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_can.c @@ -0,0 +1,625 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + */ + +#include "drv_can.h" + +#ifdef BSP_USING_CAN + +static struct es32f3_can can; + +/* attention !!! baud calculation example: Pclk / ((sjw + seg1 + seg2) * psc) 48 / ((1 + 3 + 2) * 8) = 1MHz */ +static const struct es32f3_baud_rate_tab can_baud_rate_tab[] = +{ + {CAN1MBaud, 8}, + {CAN800kBaud, 10}, + {CAN500kBaud, 16}, + {CAN250kBaud, 32}, + {CAN125kBaud, 64}, + {CAN100kBaud, 80}, + {CAN50kBaud, 160}, + {CAN20kBaud, 400}, + {CAN10kBaud, 800} +}; + +static rt_uint32_t get_can_baud_index(rt_uint32_t baud) +{ + rt_uint32_t len, index; + + len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]); + for (index = 0; index < len; index++) + { + if (can_baud_rate_tab[index].baud_rate == baud) + return index; + } + + return 0; /* default baud is CAN1MBaud */ +} + +static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configure *cfg) +{ + struct es32f3_can *drv_can; + rt_uint32_t baud_index; + + RT_ASSERT(can_device); + RT_ASSERT(cfg); + drv_can = (struct es32f3_can *)can_device->parent.user_data; + RT_ASSERT(drv_can); + + drv_can->CanHandle.perh = CAN0; + drv_can->CanHandle.init.ttcm = DISABLE; + drv_can->CanHandle.init.abom = ENABLE; + drv_can->CanHandle.init.awk = DISABLE; + drv_can->CanHandle.init.artx = DISABLE; + drv_can->CanHandle.init.rfom = DISABLE; + drv_can->CanHandle.init.txmp = ENABLE; + + switch (cfg->mode) + { + case RT_CAN_MODE_NORMAL: + drv_can->CanHandle.init.mode = CAN_MODE_NORMAL; + break; + case RT_CAN_MODE_LISEN: + drv_can->CanHandle.init.mode = CAN_MODE_SILENT; + break; + case RT_CAN_MODE_LOOPBACK: + drv_can->CanHandle.init.mode = CAN_MODE_LOOPBACK; + break; + case RT_CAN_MODE_LOOPBACKANLISEN: + drv_can->CanHandle.init.mode = CAN_MODE_SILENT_LOOPBACK; + break; + } + + baud_index = get_can_baud_index(cfg->baud_rate); + drv_can->CanHandle.init.sjw = CAN_SJW_1; + drv_can->CanHandle.init.seg1 = CAN_SEG1_3; + drv_can->CanHandle.init.seg2 = CAN_SEG2_2; + drv_can->CanHandle.init.psc = can_baud_rate_tab[baud_index].config_data; + /* init can */ + if (ald_can_init(&drv_can->CanHandle) != OK) + { + return -RT_ERROR; + } + /* default filter config */ + ald_can_filter_config(&drv_can->CanHandle, &drv_can->FilterConfig); + + return RT_EOK; +} + +static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *arg) +{ + rt_uint32_t argval; + struct es32f3_can *drv_can; + struct rt_can_filter_config *filter_cfg; + + RT_ASSERT(can_device != RT_NULL); + drv_can = (struct es32f3_can *)can_device->parent.user_data; + RT_ASSERT(drv_can != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + argval = (rt_uint32_t) arg; + if (argval == RT_DEVICE_FLAG_INT_RX) + { + ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FF0 | CAN_IT_FOV0 | + CAN_IT_FP1 | CAN_IT_FF1 | CAN_IT_FOV1), DISABLE); + } + else if (argval == RT_DEVICE_FLAG_INT_TX) + { + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_TXM, DISABLE); + } + else if (argval == RT_DEVICE_CAN_INT_ERR) + { + ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF | + CAN_IT_PRERR | CAN_IT_ERR), DISABLE); + } + break; + case RT_DEVICE_CTRL_SET_INT: + argval = (rt_uint32_t) arg; + if (argval == RT_DEVICE_FLAG_INT_RX) + { + NVIC_SetPriority(CAN0_RX0_IRQn, 1); + NVIC_EnableIRQ(CAN0_RX0_IRQn); + + NVIC_SetPriority(CAN0_RX0_IRQn, 1); + NVIC_EnableIRQ(CAN0_RX0_IRQn); + + ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FF0 | CAN_IT_FOV0 | + CAN_IT_FP1 | CAN_IT_FF1 | CAN_IT_FOV1), ENABLE); + } + else if (argval == RT_DEVICE_FLAG_INT_TX) + { + NVIC_SetPriority(CAN0_TX_IRQn, 1); + NVIC_EnableIRQ(CAN0_TX_IRQn); + + ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_TXM, ENABLE); + } + else if (argval == RT_DEVICE_CAN_INT_ERR) + { + NVIC_SetPriority(CAN0_EXCEPTION_IRQn, 1); + NVIC_EnableIRQ(CAN0_EXCEPTION_IRQn); + + ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF | + CAN_IT_PRERR | CAN_IT_ERR), ENABLE); + } + break; + case RT_CAN_CMD_SET_FILTER: + if (RT_NULL == arg) + { + /* default filter config */ + ald_can_filter_config(&drv_can->CanHandle, &drv_can->FilterConfig); + } + else + { + filter_cfg = (struct rt_can_filter_config *)arg; + /* get default filter */ + for (int i = 0; i < filter_cfg->count; i++) + { + drv_can->FilterConfig.number = filter_cfg->items[i].hdr; + drv_can->FilterConfig.id_high = (filter_cfg->items[i].id >> 13) & 0xFFFF; + drv_can->FilterConfig.id_low = ((filter_cfg->items[i].id << 3) | + (filter_cfg->items[i].ide << 2) | + (filter_cfg->items[i].rtr << 1)) & 0xFFFF; + drv_can->FilterConfig.mask_id_high = (filter_cfg->items[i].mask >> 16) & 0xFFFF; + drv_can->FilterConfig.mask_id_low = filter_cfg->items[i].mask & 0xFFFF; + drv_can->FilterConfig.mode = (can_filter_mode_t)filter_cfg->items[i].mode; + /* Filter conf */ + ald_can_filter_config(&drv_can->CanHandle, &drv_can->FilterConfig); + } + } + break; + case RT_CAN_CMD_SET_MODE: + argval = (rt_uint32_t) arg; + if (argval != RT_CAN_MODE_NORMAL && + argval != RT_CAN_MODE_LISEN && + argval != RT_CAN_MODE_LOOPBACK && + argval != RT_CAN_MODE_LOOPBACKANLISEN) + { + return -RT_ERROR; + } + if (argval != drv_can->device.config.mode) + { + drv_can->device.config.mode = argval; + return _can_config(&drv_can->device, &drv_can->device.config); + } + break; + case RT_CAN_CMD_SET_BAUD: + argval = (rt_uint32_t) arg; + if (argval != CAN1MBaud && + argval != CAN800kBaud && + argval != CAN500kBaud && + argval != CAN250kBaud && + argval != CAN125kBaud && + argval != CAN100kBaud && + argval != CAN50kBaud && + argval != CAN20kBaud && + argval != CAN10kBaud) + { + return -RT_ERROR; + } + if (argval != drv_can->device.config.baud_rate) + { + drv_can->device.config.baud_rate = argval; + return _can_config(&drv_can->device, &drv_can->device.config); + } + break; + case RT_CAN_CMD_SET_PRIV: + argval = (rt_uint32_t) arg; + if (argval != RT_CAN_MODE_PRIV && + argval != RT_CAN_MODE_NOPRIV) + { + return -RT_ERROR; + } + if (argval != drv_can->device.config.privmode) + { + drv_can->device.config.privmode = argval; + return _can_config(&drv_can->device, &drv_can->device.config); + } + break; + case RT_CAN_CMD_GET_STATUS: + { + rt_uint32_t errtype; + errtype = drv_can->CanHandle.perh->ERRSTAT; + drv_can->device.status.rcverrcnt = errtype >> 24; + drv_can->device.status.snderrcnt = (errtype >> 16 & 0xFF); + drv_can->device.status.lasterrtype = errtype & 0x70; + drv_can->device.status.errcode = errtype & 0x07; + + rt_memcpy(arg, &drv_can->device.status, sizeof(drv_can->device.status)); + } + break; + } + + return RT_EOK; +} + +static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num) +{ + can_handle_t *h_can; + h_can = &((struct es32f3_can *) can->parent.user_data)->CanHandle; + struct rt_can_msg *pmsg = (struct rt_can_msg *) buf; + can_tx_msg_t txheader = {0}; + can_state_t state = h_can->state; + + /* Check the parameters */ + RT_ASSERT(IS_CAN_DATA_LEN(pmsg->len)); + + if ((state == CAN_STATE_READY) || + (state == CAN_STATE_BUSY_RX)) + { + /*check select mailbox is empty */ + switch (1 << box_num) + { + case CAN_TX_MAILBOX_0: + if (ald_can_get_flag_status(h_can, CAN_FLAG_TXM0) != SET) + { + /* Change CAN state */ + h_can->state = CAN_STATE_ERROR; + /* Return function status */ + return -RT_ERROR; + } + break; + case CAN_TX_MAILBOX_1: + if (ald_can_get_flag_status(h_can, CAN_FLAG_TXM1) != SET) + { + /* Change CAN state */ + h_can->state = CAN_STATE_ERROR; + /* Return function status */ + return -RT_ERROR; + } + break; + case CAN_TX_MAILBOX_2: + if (ald_can_get_flag_status(h_can, CAN_FLAG_TXM2) != SET) + { + /* Change CAN state */ + h_can->state = CAN_STATE_ERROR; + /* Return function status */ + return -RT_ERROR; + } + break; + default: + RT_ASSERT(0); + break; + } + + if (RT_CAN_STDID == pmsg->ide) + { + txheader.type = CAN_ID_STD; + RT_ASSERT(IS_CAN_STDID(pmsg->id)); + txheader.std = pmsg->id; + } + else + { + txheader.type = CAN_ID_EXT; + RT_ASSERT(IS_CAN_EXTID(pmsg->id)); + txheader.ext = pmsg->id; + } + + if (RT_CAN_DTR == pmsg->rtr) + { + txheader.rtr = CAN_RTR_DATA; + } + else + { + txheader.rtr = CAN_RTR_REMOTE; + } + /* clear TIR */ + h_can->perh->TxMailBox[box_num].TXID &= CAN_TXID0_TXMREQ_MSK; + /* Set up the Id */ + if (RT_CAN_STDID == pmsg->ide) + { + h_can->perh->TxMailBox[box_num].TXID |= (txheader.std << CAN_TXID0_STDID_POSS) | txheader.rtr; + } + else + { + h_can->perh->TxMailBox[box_num].TXID |= (txheader.ext << CAN_TXID0_EXID_POSS) | txheader.type | txheader.rtr; + } + /* Set up the DLC */ + h_can->perh->TxMailBox[box_num].TXFCON = pmsg->len & 0x0FU; + /* Set up the data field */ + WRITE_REG(h_can->perh->TxMailBox[box_num].TXDH, + ((uint32_t)pmsg->data[7] << CAN_TXDH0_BYTE7_POSS) | + ((uint32_t)pmsg->data[6] << CAN_TXDH0_BYTE6_POSS) | + ((uint32_t)pmsg->data[5] << CAN_TXDH0_BYTE5_POSS) | + ((uint32_t)pmsg->data[4] << CAN_TXDH0_BYTE4_POSS)); + WRITE_REG(h_can->perh->TxMailBox[box_num].TXDL, + ((uint32_t)pmsg->data[3] << CAN_TXDL0_BYTE3_POSS) | + ((uint32_t)pmsg->data[2] << CAN_TXDL0_BYTE2_POSS) | + ((uint32_t)pmsg->data[1] << CAN_TXDL0_BYTE1_POSS) | + ((uint32_t)pmsg->data[0] << CAN_TXDL0_BYTE0_POSS)); + /* Request transmission */ + SET_BIT(h_can->perh->TxMailBox[box_num].TXID, CAN_TXID0_TXMREQ_MSK); + + return RT_EOK; + } + else + { + /* Update error code */ + h_can->err |= 0x00040000U; + + return -RT_ERROR; + } +} + +static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) +{ + can_handle_t *h_can; + struct rt_can_msg *pmsg; + can_rx_msg_t rxheader = {0}; + + RT_ASSERT(can); + + h_can = &((struct es32f3_can *)can->parent.user_data)->CanHandle; + pmsg = (struct rt_can_msg *) buf; + + /* get data */ + if (ald_can_recv(h_can, (can_rx_fifo_t)fifo, &rxheader, 0xFFFF) != OK) + return -RT_ERROR; + pmsg->data[0] = rxheader.data[0]; + pmsg->data[1] = rxheader.data[1]; + pmsg->data[2] = rxheader.data[2]; + pmsg->data[3] = rxheader.data[3]; + pmsg->data[4] = rxheader.data[4]; + pmsg->data[5] = rxheader.data[5]; + pmsg->data[6] = rxheader.data[6]; + pmsg->data[7] = rxheader.data[7]; + + /* get id */ + if (CAN_ID_STD == rxheader.type) + { + pmsg->ide = RT_CAN_STDID; + pmsg->id = rxheader.std; + } + else + { + pmsg->ide = RT_CAN_EXTID; + pmsg->id = rxheader.ext; + } + /* get type */ + if (CAN_RTR_DATA == rxheader.rtr) + { + pmsg->rtr = RT_CAN_DTR; + } + else + { + pmsg->rtr = RT_CAN_RTR; + } + /* get len */ + pmsg->len = rxheader.len; + /* get hdr */ + pmsg->hdr = (rxheader.fmi + 1) >> 1; + + return RT_EOK; +} + + +static const struct rt_can_ops _can_ops = +{ + _can_config, + _can_control, + _can_sendmsg, + _can_recvmsg, +}; + +static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo) +{ + can_handle_t *h_can; + RT_ASSERT(can); + h_can = &((struct es32f3_can *) can->parent.user_data)->CanHandle; + + switch (fifo) + { + case CAN_RX_FIFO0: + /* Check Overrun flag for FIFO0 */ + if (ald_can_get_flag_status(h_can, CAN_FLAG_FOV0) && ald_can_get_it_status(h_can, CAN_IT_FOV0)) + { + /* Clear FIFO0 Overrun Flag */ + ald_can_clear_flag_status(h_can, CAN_FLAG_FOV0); + rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8); + } + /* RX interrupt */ + else + { + /* save to user list */ + rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + /* Clear FIFO0 rx Flag */ + SET_BIT(h_can->perh->RXF0, CAN_RXF0_FREE_MSK); + } + break; + case CAN_RX_FIFO1: + /* Check Overrun flag for FIFO1 */ + if (ald_can_get_flag_status(h_can, CAN_FLAG_FOV1) && ald_can_get_it_status(h_can, CAN_IT_FOV1)) + { + /* Clear FIFO1 Overrun Flag */ + ald_can_clear_flag_status(h_can, CAN_FLAG_FOV1); + rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8); + } + /* RX interrupt */ + else + { + /* save to user list */ + rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8); + /* Clear FIFO0 rx Flag */ + SET_BIT(h_can->perh->RXF1, CAN_RXF1_FREE_MSK); + } + break; + } +} + +/** + * @brief This function handles CAN0 TX interrupts. transmit fifo0/1/2 is empty can trigger this interrupt + */ +void CAN0_TX_Handler(void) +{ + rt_interrupt_enter(); + can_handle_t *h_can; + h_can = &can.CanHandle; + + /* TX interrupt. transmit fifo0/1/2 is empty can trigger this interrupt */ + if (ald_can_get_flag_status(h_can, CAN_FLAG_M0REQC) && ald_can_get_it_status(h_can, CAN_IT_TXM)) + { + if (ald_can_get_flag_status(h_can, CAN_FLAG_M0TXC)) + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_DONE | 0 << 8); + } + else + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 0 << 8); + } + /* Clear transmission status flag M0REQC */ + ald_can_clear_flag_status(h_can, CAN_FLAG_M0REQC); + } + else if (ald_can_get_flag_status(h_can, CAN_FLAG_M1REQC) && ald_can_get_it_status(h_can, CAN_IT_TXM)) + { + if (ald_can_get_flag_status(h_can, CAN_FLAG_M1TXC)) + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_DONE | 1 << 8); + } + else + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 1 << 8); + } + ald_can_clear_flag_status(h_can, CAN_FLAG_M1REQC); + } + else if (ald_can_get_flag_status(h_can, CAN_FLAG_M2REQC) && ald_can_get_it_status(h_can, CAN_IT_TXM)) + { + if (ald_can_get_flag_status(h_can, CAN_FLAG_M2REQC)) + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_DONE | 2 << 8); + } + else + { + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 2 << 8); + } + ald_can_clear_flag_status(h_can, CAN_FLAG_M2REQC); + } + + rt_interrupt_leave(); +} + +/** + * @brief This function handles CAN0 RX0 interrupts. + */ +void CAN0_RX0_Handler(void) +{ + rt_interrupt_enter(); + _can_rx_isr(&can.device, CAN_RX_FIFO0); + rt_interrupt_leave(); +} + +/** + * @brief This function handles CAN0 RX1 interrupts. + */ +void CAN0_RX1_Handler(void) +{ + rt_interrupt_enter(); + _can_rx_isr(&can.device, CAN_RX_FIFO1); + rt_interrupt_leave(); +} + +/** + * @brief This function handles CAN interrupts. + */ +void CAN0_EXCEPTION_Handler(void) +{ + rt_interrupt_enter(); + + rt_uint32_t errtype; + can_handle_t *h_can; + + h_can = &can.CanHandle; + errtype = h_can->perh->ERRSTAT; + + switch ((errtype & 0x70) >> 4) + { + case RT_CAN_BUS_BIT_PAD_ERR: + can.device.status.bitpaderrcnt++; + break; + case RT_CAN_BUS_FORMAT_ERR: + can.device.status.formaterrcnt++; + break; + case RT_CAN_BUS_ACK_ERR:/* attention !!! test ack err's unit is transmit unit */ + can.device.status.ackerrcnt++; + if (!READ_BIT(can.CanHandle.perh->TXSTAT, CAN_FLAG_M0TXC)) + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 0 << 8); + else if (!READ_BIT(can.CanHandle.perh->TXSTAT, CAN_FLAG_M0TXC)) + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 1 << 8); + else if (!READ_BIT(can.CanHandle.perh->TXSTAT, CAN_FLAG_M0TXC)) + rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 2 << 8); + break; + case RT_CAN_BUS_IMPLICIT_BIT_ERR: + case RT_CAN_BUS_EXPLICIT_BIT_ERR: + can.device.status.biterrcnt++; + break; + case RT_CAN_BUS_CRC_ERR: + can.device.status.crcerrcnt++; + break; + } + + can.device.status.lasterrtype = errtype & 0x70; + can.device.status.rcverrcnt = errtype >> 24; + can.device.status.snderrcnt = (errtype >> 16 & 0xFF); + can.device.status.errcode = errtype & 0x07; + h_can->perh->IFC |= CAN_IFC_ERRIFC_MSK; + + rt_interrupt_leave(); +} + +int rt_hw_can_init(void) +{ + gpio_init_t h_gpio; + struct can_configure config = CANDEFAULTCONFIG; + + config.privmode = RT_CAN_MODE_NOPRIV; + config.ticks = 50; +#ifdef RT_CAN_USING_HDR + config.maxhdr = 14; +#endif + + /* Initialize can common pin */ + h_gpio.odos = GPIO_PUSH_PULL; + h_gpio.pupd = GPIO_PUSH_UP; + h_gpio.podrv = GPIO_OUT_DRIVE_1; + h_gpio.nodrv = GPIO_OUT_DRIVE_0_1; + h_gpio.flt = GPIO_FILTER_DISABLE; + h_gpio.type = GPIO_TYPE_TTL; + h_gpio.func = GPIO_FUNC_3; + + /* Initialize can rx pin */ + h_gpio.mode = GPIO_MODE_INPUT; + ald_gpio_init(GPIOB, GPIO_PIN_8, &h_gpio); + + /* Initialize can tx pin */ + h_gpio.mode = GPIO_MODE_OUTPUT; + ald_gpio_init(GPIOB, GPIO_PIN_9, &h_gpio); + + /* config default filter */ + can_filter_t filter = {0}; + filter.id_high = 0x0000; + filter.id_low = 0x0000; + filter.mask_id_high = 0x0000; + filter.mask_id_low = 0x0000; + filter.fifo = CAN_FILTER_FIFO0; + filter.number = 0; + filter.mode = CAN_FILTER_MODE_MASK; + filter.scale = CAN_FILTER_SCALE_32; + filter.active = ENABLE; + filter.bank_number = 14; + + can.FilterConfig = filter; + can.device.config = config; + /* register CAN1 device */ + rt_hw_can_register(&can.device, "can", &_can_ops, &can); + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_can_init); + +#endif /* BSP_USING_CAN */ diff --git a/bsp/essemi/es32f369x/drivers/drv_can.h b/bsp/essemi/es32f369x/drivers/drv_can.h new file mode 100644 index 0000000000000000000000000000000000000000..cffe4b81b0c530259c067b89511e3fe8f868451b --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_can.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + */ + +#ifndef DRV_CAN_H__ +#define DRV_CAN_H__ + +#include +#include +#include + +#include +#include + +struct es32f3_baud_rate_tab +{ + rt_uint32_t baud_rate; + rt_uint32_t config_data; +}; + +/* es32f3 can device */ +struct es32f3_can +{ + can_handle_t CanHandle; + can_filter_t FilterConfig; + struct rt_can_device device; /* inherit from can device */ +}; + +int rt_hw_can_init(void); + +#endif /*DRV_CAN_H__ */ diff --git a/bsp/essemi/es32f369x/drivers/drv_gpio.c b/bsp/essemi/es32f369x/drivers/drv_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..c9bf1c946a10bfff93c6c3adc67acaf74a49cfb6 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_gpio.c @@ -0,0 +1,562 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + */ + +#include +#include +#include "board.h" +#include "drv_gpio.h" +#include +#include + +#ifdef RT_USING_PIN + +#define __ES32F0_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index} +#define __ES32F0_PIN_DEFAULT {-1, 0, 0} + +/* ES32F0 GPIO driver */ +struct pin_index +{ + int index; + GPIO_TypeDef *gpio; + uint32_t pin; +}; + +static const struct pin_index pins[] = +{ + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(2, C, 13), + __ES32F0_PIN(3, C, 14), + __ES32F0_PIN(4, C, 15), + __ES32F0_PIN(5, H, 0), + __ES32F0_PIN(6, H, 1), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(8, C, 0), + __ES32F0_PIN(9, C, 1), + __ES32F0_PIN(10, C, 2), + __ES32F0_PIN(11, C, 3), + __ES32F0_PIN(12, H, 3), + __ES32F0_PIN(13, H, 4), + __ES32F0_PIN(14, A, 0), + __ES32F0_PIN(15, A, 1), + __ES32F0_PIN(16, A, 2), + __ES32F0_PIN(17, A, 3), + __ES32F0_PIN(18, F, 0), + __ES32F0_PIN(19, F, 1), + __ES32F0_PIN(20, A, 4), + __ES32F0_PIN(21, A, 5), + __ES32F0_PIN(22, A, 6), + __ES32F0_PIN(23, A, 7), + __ES32F0_PIN(24, C, 4), + __ES32F0_PIN(25, C, 5), + __ES32F0_PIN(26, B, 0), + __ES32F0_PIN(27, B, 1), + __ES32F0_PIN(28, B, 2), + __ES32F0_PIN(29, B, 10), + __ES32F0_PIN(30, B, 11), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(33, B, 12), + __ES32F0_PIN(34, B, 13), + __ES32F0_PIN(35, B, 14), + __ES32F0_PIN(36, B, 15), + __ES32F0_PIN(37, C, 6), + __ES32F0_PIN(38, C, 7), + __ES32F0_PIN(39, C, 8), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(46, A, 13), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN(49, A, 14), + __ES32F0_PIN(50, A, 15), + __ES32F0_PIN(51, C, 10), + __ES32F0_PIN(52, C, 11), + __ES32F0_PIN(53, C, 12), + __ES32F0_PIN(54, D, 2), + __ES32F0_PIN(55, B, 3), + __ES32F0_PIN(56, B, 4), + __ES32F0_PIN(57, B, 5), + __ES32F0_PIN(58, B, 6), + __ES32F0_PIN(59, B, 7), + __ES32F0_PIN(60, H, 2), + __ES32F0_PIN(61, B, 8), + __ES32F0_PIN(62, B, 9), + __ES32F0_PIN_DEFAULT, + __ES32F0_PIN_DEFAULT, +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; +static const struct pin_irq_map pin_irq_map[] = +{ + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI5_IRQn}, + {GPIO_PIN_6, EXTI6_IRQn}, + {GPIO_PIN_7, EXTI7_IRQn}, + {GPIO_PIN_8, EXTI8_IRQn}, + {GPIO_PIN_9, EXTI9_IRQn}, + {GPIO_PIN_10, EXTI10_IRQn}, + {GPIO_PIN_11, EXTI11_IRQn}, + {GPIO_PIN_12, EXTI12_IRQn}, + {GPIO_PIN_13, EXTI13_IRQn}, + {GPIO_PIN_14, EXTI14_IRQn}, + {GPIO_PIN_15, EXTI15_IRQn}, +}; + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, + { -1, 0, RT_NULL, RT_NULL}, +}; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + return index; +}; + +void es32f3_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + ald_gpio_write_pin(index->gpio, index->pin, value); +} + +int es32f3_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + value = PIN_LOW; + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + value = ald_gpio_read_pin(index->gpio, index->pin); + return value; +} + +void es32f3_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + gpio_init_t gpio_initstruct; + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* Configure GPIO_InitStructure */ + gpio_initstruct.mode = GPIO_MODE_OUTPUT; + gpio_initstruct.func = GPIO_FUNC_1; + gpio_initstruct.podrv = GPIO_OUT_DRIVE_1; + gpio_initstruct.nodrv = GPIO_OUT_DRIVE_0_1; + gpio_initstruct.type = GPIO_TYPE_CMOS; + gpio_initstruct.pupd = GPIO_FLOATING; + gpio_initstruct.odos = GPIO_PUSH_PULL; + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + gpio_initstruct.mode = GPIO_MODE_OUTPUT; + gpio_initstruct.pupd = GPIO_FLOATING; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + gpio_initstruct.mode = GPIO_MODE_INPUT; + gpio_initstruct.pupd = GPIO_FLOATING; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + gpio_initstruct.mode = GPIO_MODE_INPUT; + gpio_initstruct.pupd = GPIO_PUSH_UP; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + gpio_initstruct.mode = GPIO_MODE_INPUT; + gpio_initstruct.pupd = GPIO_PUSH_DOWN; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + gpio_initstruct.mode = GPIO_MODE_OUTPUT; + gpio_initstruct.pupd = GPIO_FLOATING; + gpio_initstruct.odos = GPIO_OPEN_DRAIN; + } + ald_gpio_init(index->gpio, index->pin, &gpio_initstruct); +} + +rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin) +{ + rt_int32_t mapindex = gpio_pin & 0x00FF; + if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; + +rt_err_t es32f3_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + /* pin no. convert to dec no. */ + for (irqindex = 0; irqindex < 16; irqindex++) + { + if ((0x01 << irqindex) == index->pin) + { + break; + } + } + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +rt_err_t es32f3_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = index->pin & 0x00FF; + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +rt_err_t es32f3_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + /* Configure GPIO_InitStructure & EXTI_InitStructure */ + gpio_init_t gpio_initstruct; + exti_init_t exti_initstruct; + exti_initstruct.filter = DISABLE; + exti_initstruct.cks = EXTI_FILTER_CLOCK_10K; + exti_initstruct.filter_time = 0x0; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + if (enabled == PIN_IRQ_ENABLE) + { + /* pin no. convert to dec no. */ + for (irqindex = 0; irqindex < 16; irqindex++) + { + if ((0x01 << irqindex) == index->pin) + { + break; + } + } + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + irqmap = &pin_irq_map[irqindex]; + ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct); + /* Configure GPIO_InitStructure */ + gpio_initstruct.mode = GPIO_MODE_INPUT; + gpio_initstruct.func = GPIO_FUNC_1; + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + gpio_initstruct.pupd = GPIO_PUSH_DOWN; + ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE); + break; + case PIN_IRQ_MODE_FALLING: + gpio_initstruct.pupd = GPIO_PUSH_UP; + ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE); + break; + case PIN_IRQ_MODE_RISING_FALLING: + gpio_initstruct.pupd = GPIO_FLOATING; + ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE); + break; + } + ald_gpio_init(index->gpio, index->pin, &gpio_initstruct); + NVIC_EnableIRQ(irqmap->irqno); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return RT_ENOSYS; + } + NVIC_DisableIRQ(irqmap->irqno); + } + else + { + return RT_ENOSYS; + } + return RT_EOK; +} + +const static struct rt_pin_ops _es32f3_pin_ops = +{ + es32f3_pin_mode, + es32f3_pin_write, + es32f3_pin_read, + es32f3_pin_attach_irq, + es32f3_pin_detach_irq, + es32f3_pin_irq_enable, +}; + +int rt_hw_pin_init(void) +{ + int result; + ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE); + result = rt_device_pin_register("pin", &_es32f3_pin_ops, RT_NULL); + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +rt_inline void pin_irq_hdr(uint16_t GPIO_Pin) +{ + uint16_t irqno; + /* pin no. convert to dec no. */ + for (irqno = 0; irqno < 16; irqno++) + { + if ((0x01 << irqno) == GPIO_Pin) + { + break; + } + } + if (irqno == 16) + return; + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +void GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + if (ald_gpio_exti_get_flag_status(GPIO_Pin) != RESET) + { + ald_gpio_exti_clear_flag_status(GPIO_Pin); + pin_irq_hdr(GPIO_Pin); + } +} + +void EXTI0_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_0); + rt_interrupt_leave(); +} + +void EXTI1_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_1); + rt_interrupt_leave(); +} + +void EXTI2_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_2); + rt_interrupt_leave(); +} + +void EXTI3_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_3); + rt_interrupt_leave(); +} + +void EXTI4_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_4); + rt_interrupt_leave(); +} + +void EXTI5_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_5); + rt_interrupt_leave(); +} + +void EXTI6_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_6); + rt_interrupt_leave(); +} + +void EXTI7_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_7); + rt_interrupt_leave(); +} + +void EXTI8_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_8); + rt_interrupt_leave(); +} + +void EXTI9_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_9); + rt_interrupt_leave(); +} + +void EXTI10_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_10); + rt_interrupt_leave(); +} + +void EXTI11_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_11); + rt_interrupt_leave(); +} + +void EXTI12_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_12); + rt_interrupt_leave(); +} + +void EXTI13_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_13); + rt_interrupt_leave(); +} + +void EXTI14_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_14); + rt_interrupt_leave(); +} + +void EXTI15_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_Callback(GPIO_PIN_15); + rt_interrupt_leave(); +} + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_gpio.h b/bsp/essemi/es32f369x/drivers/drv_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..fef8fb84876f61de96c09aad0bd1b38bafde6257 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_gpio.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + */ + +#ifndef DRV_GPIO_H__ +#define DRV_GPIO_H__ + +int rt_hw_pin_init(void); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_i2c.c b/bsp/essemi/es32f369x/drivers/drv_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..4cf0a7b03166854346c74967172d11caa21ed294 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_i2c.c @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + * 2019-11-01 wangyq update libraries + */ + +#include +#include +#include +#include "board.h" +#include "drv_i2c.h" +#include +#include + +#ifdef RT_USING_I2C + +#define TIMEOUT 0x0FFF + +/* I2C struct definition */ +#ifdef BSP_USING_I2C0 + static i2c_handle_t _h_i2c0; +#endif + +#ifdef BSP_USING_I2C1 + static i2c_handle_t _h_i2c1; +#endif + +static void _i2c_init(void) +{ + gpio_init_t gpio_instruct; + + /* Initialize I2C Pin */ + gpio_instruct.mode = GPIO_MODE_OUTPUT; + gpio_instruct.odos = GPIO_PUSH_PULL; + gpio_instruct.pupd = GPIO_PUSH_UP; + gpio_instruct.podrv = GPIO_OUT_DRIVE_1; + gpio_instruct.nodrv = GPIO_OUT_DRIVE_0_1; + gpio_instruct.flt = GPIO_FILTER_DISABLE; + gpio_instruct.type = GPIO_TYPE_CMOS; + gpio_instruct.func = GPIO_FUNC_5; + +#ifdef BSP_USING_I2C0 + /* Initialize I2C Function */ + _h_i2c0.perh = I2C0; + _h_i2c0.init.clk_speed = 100000; + _h_i2c0.init.own_addr1 = 0x0A; + _h_i2c0.init.addr_mode = I2C_ADDR_7BIT; + _h_i2c0.init.general_call = I2C_GENERALCALL_DISABLE; + _h_i2c0.init.no_stretch = I2C_NOSTRETCH_ENABLE; + + ald_i2c_reset(&_h_i2c0); + ald_i2c_init(&_h_i2c0); + /* PB8->I2C0_SCL, PB9->I2C0_SDA */ + ald_gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct); +#endif + +#ifdef BSP_USING_I2C1 + /* Initialize i2c function */ + _h_i2c1.perh = I2C1; + _h_i2c1.init.clk_speed = 100000; + _h_i2c1.init.own_addr1 = 0xA0; + _h_i2c1.init.addr_mode = I2C_ADDR_7BIT; + _h_i2c1.init.general_call = I2C_GENERALCALL_DISABLE; + _h_i2c1.init.no_stretch = I2C_NOSTRETCH_ENABLE; + + ald_i2c_reset(&_h_i2c1); + ald_i2c_init(&_h_i2c1); + /* PA05->I2C1_SCL, PA06->I2C1_SDA */ + ald_gpio_init(GPIOA, GPIO_PIN_5 | GPIO_PIN_6, &gpio_instruct); +#endif +} + +static rt_size_t es32f3_master_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + struct rt_i2c_msg *msg; + rt_uint32_t i; + rt_err_t ret = RT_ERROR; + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + if (msg->flags & RT_I2C_RD) + { + if (ald_i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) + { + i2c_dbg("i2c bus write failed,i2c bus stop!\n"); + goto out; + } + } + else + { + if (ald_i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0) + { + i2c_dbg("i2c bus write failed,i2c bus stop!\n"); + goto out; + } + } + } + + ret = i; + +out: + i2c_dbg("send stop condition\n"); + + return ret; +} + +const struct rt_i2c_bus_device_ops es32f3_i2c_ops = +{ + es32f3_master_xfer, + RT_NULL, + RT_NULL, +}; + +int rt_hw_i2c_init(void) +{ + int result = RT_EOK; + + _i2c_init(); + +#ifdef BSP_USING_I2C0 + /* define i2c Instance */ + static struct rt_i2c_bus_device _i2c_device0; + rt_memset((void *)&_i2c_device0, 0, sizeof(struct rt_i2c_bus_device)); + + _i2c_device0.ops = &es32f3_i2c_ops; + _i2c_device0.priv = &_h_i2c0; + result = rt_i2c_bus_device_register(&_i2c_device0, "i2c0"); + if (result != RT_EOK) + { + return result; + } +#endif + +#ifdef BSP_USING_I2C1 + /* define i2c Instance */ + static struct rt_i2c_bus_device _i2c_device1; + rt_memset((void *)&_i2c_device1, 0, sizeof(struct rt_i2c_bus_device)); + + _i2c_device1.ops = &es32f3_i2c_ops; + _i2c_device1.priv = &_h_i2c1; + rt_i2c_bus_device_register(&_i2c_device1, "i2c1"); + if (result != RT_EOK) + { + return result; + } +#endif + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_i2c.h b/bsp/essemi/es32f369x/drivers/drv_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..d7c2410682e02dcc0c4243c1901519bb80a3df61 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_i2c.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + */ + +#ifndef DRV_I2C_H__ +#define DRV_I2C_H__ + +int rt_hw_i2c_init(void); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_spi.c b/bsp/essemi/es32f369x/drivers/drv_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..3bd56e18dea20f1a70188651f27bbc66718edec5 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_spi.c @@ -0,0 +1,341 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + * 2019-11-01 wangyq update libraries + */ + +#include +#include +#include +#include +#include "board.h" +#include "drv_spi.h" +#include +#include +#include + +#ifdef RT_USING_SPI + +#define SPITIMEOUT 0xFFFF + +rt_err_t spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *cfg) +{ + spi_handle_t *hspi; + hspi = (spi_handle_t *)device->bus->parent.user_data; + + /* config spi mode */ + if (cfg->mode & RT_SPI_SLAVE) + { + hspi->init.mode = SPI_MODE_SLAVER; + } + else + { + hspi->init.mode = SPI_MODE_MASTER; + } + if (cfg->mode & RT_SPI_3WIRE) + { + hspi->init.dir = SPI_DIRECTION_1LINE; + } + else + { + hspi->init.dir = SPI_DIRECTION_2LINES; + } + if (cfg->data_width == 8) + { + hspi->init.data_size = SPI_DATA_SIZE_8; + } + else if (cfg->data_width == 16) + { + hspi->init.data_size = SPI_DATA_SIZE_16; + } + + if (cfg->mode & RT_SPI_CPHA) + { + hspi->init.phase = SPI_CPHA_SECOND; + } + else + { + hspi->init.phase = SPI_CPHA_FIRST; + } + if (cfg->mode & RT_SPI_CPOL) + { + hspi->init.polarity = SPI_CPOL_HIGH; + } + else + { + hspi->init.polarity = SPI_CPOL_LOW; + } + if (cfg->mode & RT_SPI_NO_CS) + { + hspi->init.ss_en = DISABLE; + } + else + { + hspi->init.ss_en = ENABLE; + } + + /* config spi clock */ + if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 2) + { + /* pclk1 max speed 48MHz, spi master max speed 10MHz */ + if (ald_cmu_get_pclk1_clock() / 2 <= 10000000) + { + hspi->init.baud = SPI_BAUD_2; + } + else if (ald_cmu_get_pclk1_clock() / 4 <= 10000000) + { + hspi->init.baud = SPI_BAUD_4; + } + else + { + hspi->init.baud = SPI_BAUD_8; + } + } + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 4) + { + /* pclk1 max speed 48MHz, spi master max speed 10MHz */ + if (ald_cmu_get_pclk1_clock() / 4 <= 10000000) + { + hspi->init.baud = SPI_BAUD_4; + } + else + { + hspi->init.baud = SPI_BAUD_8; + } + } + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 8) + { + hspi->init.baud = SPI_BAUD_8; + } + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 16) + { + hspi->init.baud = SPI_BAUD_16; + } + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 32) + { + hspi->init.baud = SPI_BAUD_32; + } + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 64) + { + hspi->init.baud = SPI_BAUD_64; + } + else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 128) + { + hspi->init.baud = SPI_BAUD_128; + } + else + { + hspi->init.baud = SPI_BAUD_256; + } + hspi->init.ss_en = DISABLE; + hspi->init.crc_calc = DISABLE; + ald_spi_init(hspi); + return RT_EOK; +} + +static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + rt_err_t res; + spi_handle_t *hspi; + struct es32f3_hw_spi_cs *cs; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL); + + hspi = (spi_handle_t *)device->bus->parent.user_data; + cs = device->parent.user_data; + + /* send & receive */ + if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL)) + { + if (message->cs_take) + { + rt_pin_write(cs->pin, 0); + } + res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, + (rt_int32_t)message->length, SPITIMEOUT); + if (message->cs_release) + { + rt_pin_write(cs->pin, 1); + } + if (res != RT_EOK) + return RT_ERROR; + } + else + { + /* only send data */ + if (message->recv_buf == RT_NULL) + { + if (message->cs_take) + { + rt_pin_write(cs->pin, 0); + } + res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT); + if (message->cs_release) + { + rt_pin_write(cs->pin, 1); + } + if (res != RT_EOK) + return RT_ERROR; + } + /* only receive data */ + if (message->send_buf == RT_NULL) + { + if (message->cs_take) + { + rt_pin_write(cs->pin, 0); + } + res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT); + if (message->cs_release) + { + rt_pin_write(cs->pin, 1); + } + if (res != RT_EOK) + return RT_ERROR; + } + } + + return message->length; +} + +const struct rt_spi_ops es32f3_spi_ops = +{ + spi_configure, + spixfer, +}; + +rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name) +{ + /* define spi Instance */ + struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + struct es32f3_hw_spi_cs *cs_pin = (struct es32f3_hw_spi_cs *)rt_malloc(sizeof(struct es32f3_hw_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + cs_pin->pin = pin; + rt_pin_mode(pin, PIN_MODE_OUTPUT); + rt_pin_write(pin, 1); + return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); +} + +#ifdef BSP_USING_SPI0 + static struct rt_spi_bus _spi_bus0; + static spi_handle_t _spi0; +#endif + +#ifdef BSP_USING_SPI1 + static struct rt_spi_bus _spi_bus1; + static spi_handle_t _spi1; +#endif + +#ifdef BSP_USING_SPI2 + static struct rt_spi_bus _spi_bus2; + static spi_handle_t _spi2; +#endif + +int rt_hw_spi_init(void) +{ + int result = RT_EOK; + + struct rt_spi_bus *spi_bus; + spi_handle_t *spi; + gpio_init_t gpio_instruct; + +#ifdef BSP_USING_SPI0 + _spi0.perh = SPI0; + spi_bus = &_spi_bus0; + spi = &_spi0; + + /* SPI0 gpio init */ + gpio_instruct.mode = GPIO_MODE_OUTPUT; + gpio_instruct.odos = GPIO_PUSH_PULL; + gpio_instruct.podrv = GPIO_OUT_DRIVE_1; + gpio_instruct.nodrv = GPIO_OUT_DRIVE_1; + gpio_instruct.func = GPIO_FUNC_4; + gpio_instruct.type = GPIO_TYPE_TTL; + gpio_instruct.flt = GPIO_FILTER_DISABLE; + + /* PB3->SPI0_SCK, PB5->SPI0_MOSI */ + ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct); + + /* PB4->SPI0_MISO */ + gpio_instruct.mode = GPIO_MODE_INPUT; + ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct); + + spi_bus->parent.user_data = spi; + result = rt_spi_bus_register(spi_bus, "spi0", &es32f3_spi_ops); + if (result != RT_EOK) + { + return result; + } +#endif + +#ifdef BSP_USING_SPI1 + _spi1.perh = SPI1; + spi_bus = &_spi_bus1; + spi = &_spi1; + + /* SPI1 gpio init */ + gpio_instruct.mode = GPIO_MODE_OUTPUT; + gpio_instruct.odos = GPIO_PUSH_PULL; + gpio_instruct.podrv = GPIO_OUT_DRIVE_1; + gpio_instruct.nodrv = GPIO_OUT_DRIVE_1; + gpio_instruct.func = GPIO_FUNC_4; + gpio_instruct.type = GPIO_TYPE_TTL; + gpio_instruct.flt = GPIO_FILTER_DISABLE; + + /* PC01->SPI1_SCK, PC03->SPI1_MOSI */ + ald_gpio_init(GPIOC, GPIO_PIN_1 | GPIO_PIN_3, &gpio_instruct); + + /* PC02->SPI1_MISO */ + gpio_instruct.mode = GPIO_MODE_INPUT; + ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_instruct); + + spi_bus->parent.user_data = spi; + result = rt_spi_bus_register(spi_bus, "spi1", &es32f3_spi_ops); + if (result != RT_EOK) + { + return result; + } +#endif + +#ifdef BSP_USING_SPI2 + _spi1.perh = SPI2; + spi_bus = &_spi_bus2; + spi = &_spi2; + + /* SPI2 gpio init */ + gpio_instruct.mode = GPIO_MODE_OUTPUT; + gpio_instruct.odos = GPIO_PUSH_PULL; + gpio_instruct.podrv = GPIO_OUT_DRIVE_1; + gpio_instruct.nodrv = GPIO_OUT_DRIVE_1; + gpio_instruct.func = GPIO_FUNC_5; + gpio_instruct.type = GPIO_TYPE_TTL; + gpio_instruct.flt = GPIO_FILTER_DISABLE; + + /* PC05->SPI1_SCK, PB01->SPI1_MOSI */ + ald_gpio_init(GPIOC, GPIO_PIN_5 | GPIO_PIN_1, &gpio_instruct); + + /* PB00->SPI1_MISO */ + gpio_instruct.mode = GPIO_MODE_INPUT; + ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_instruct); + + spi_bus->parent.user_data = spi; + result = rt_spi_bus_register(spi_bus, "spi2", &es32f3_spi_ops); + if (result != RT_EOK) + { + return result; + } +#endif + return result; +} +INIT_BOARD_EXPORT(rt_hw_spi_init); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_spi.h b/bsp/essemi/es32f369x/drivers/drv_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..832d1a58b1fa76eeaa6966d927afd49c2bb6b87e --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_spi.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + */ + +#ifndef DRV_SPI_H__ +#define DRV_SPI_H__ + +#include +#include +#include + +struct es32f3_hw_spi_cs +{ + rt_uint32_t pin; +}; + +/* cannot be used before completion init */ +rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name); +int rt_hw_spi_init(void); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_uart.c b/bsp/essemi/es32f369x/drivers/drv_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..b60ad32aa3a848722934d9e91dd7323c39f1570a --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_uart.c @@ -0,0 +1,431 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + */ + +#include +#include +#include +#include "board.h" +#include "drv_uart.h" +#include +#include +#include + +#ifdef RT_USING_SERIAL + +/* es32 uart driver */ +struct es32_uart +{ + uart_handle_t huart; + IRQn_Type irq; +}; + +static rt_err_t es32f3x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + gpio_init_t gpio_initstructure; + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + /* Initialize tx pin */ + gpio_initstructure.mode = GPIO_MODE_OUTPUT; + gpio_initstructure.odos = GPIO_PUSH_PULL; + gpio_initstructure.pupd = GPIO_PUSH_UP; + gpio_initstructure.podrv = GPIO_OUT_DRIVE_1; + gpio_initstructure.nodrv = GPIO_OUT_DRIVE_0_1; + gpio_initstructure.flt = GPIO_FILTER_DISABLE; + gpio_initstructure.type = GPIO_TYPE_TTL; + +#ifdef BSP_USING_UART0 + gpio_initstructure.func = GPIO_FUNC_3; + ald_gpio_init(GPIOB, GPIO_PIN_10, &gpio_initstructure); + + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + ald_gpio_init(GPIOB, GPIO_PIN_11, &gpio_initstructure); + + ald_cmu_perh_clock_config(CMU_PERH_UART0, ENABLE); +#endif /* uart0 gpio init */ + +#ifdef BSP_USING_UART1 + gpio_initstructure.func = GPIO_FUNC_3; + ald_gpio_init(GPIOC, GPIO_PIN_10, &gpio_initstructure); + + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + ald_gpio_init(GPIOC, GPIO_PIN_11, &gpio_initstructure); + + ald_cmu_perh_clock_config(CMU_PERH_UART1, ENABLE); +#endif /* uart1 gpio init */ + +#ifdef BSP_USING_UART2 + gpio_initstructure.func = GPIO_FUNC_5; + ald_gpio_init(GPIOC, GPIO_PIN_12, &gpio_initstructure); + + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + ald_gpio_init(GPIOD, GPIO_PIN_2, &gpio_initstructure); + + ald_cmu_perh_clock_config(CMU_PERH_UART2, ENABLE); +#endif /* uart2 gpio init */ + +#ifdef BSP_USING_UART3 + gpio_initstructure.func = GPIO_FUNC_4; + ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstructure); + + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstructure); + + ald_cmu_perh_clock_config(CMU_PERH_UART3, ENABLE); +#endif /* uart3 gpio init */ + +#ifdef BSP_USING_UART4 + gpio_initstructure.func = GPIO_FUNC_3; + ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure); + + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure); + + ald_cmu_perh_clock_config(CMU_PERH_UART4, ENABLE); +#endif /* uart4 gpio init */ + +#ifdef BSP_USING_UART5 + gpio_initstructure.func = GPIO_FUNC_4; + ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure); + + /* Initialize rx pin ,the same as txpin except mode */ + gpio_initstructure.mode = GPIO_MODE_INPUT; + ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure); + + ald_cmu_perh_clock_config(CMU_PERH_UART5, ENABLE); +#endif /* uart5 gpio init */ + + ald_uart_tx_fifo_config(&uart->huart, UART_TXFIFO_EMPTY, 1); + ald_uart_rx_fifo_config(&uart->huart, UART_RXFIFO_1BYTE, 1); + + uart->huart.init.mode = UART_MODE_UART; + uart->huart.init.baud = cfg->baud_rate; + uart->huart.init.word_length = (uart_word_length_t)(8 - cfg->data_bits); + uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity); + uart->huart.init.fctl = UART_HW_FLOW_CTL_DISABLE; + ald_uart_init(&uart->huart); + + if (cfg->bit_order == BIT_ORDER_MSB) + { + UART_MSB_FIRST_ENABLE(&uart->huart); + } + else + { + UART_MSB_FIRST_DISABLE(&uart->huart); + } + + if (cfg->invert == NRZ_INVERTED) + { + UART_DATA_INV_ENABLE(&uart->huart); + } + else + { + UART_DATA_INV_DISABLE(&uart->huart); + } + + return RT_EOK; +} + +static rt_err_t es32f3x_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + + uart = (struct es32_uart *)serial->parent.user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irq); + /* disable interrupt */ + ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, DISABLE); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irq); + /* enable interrupt */ + ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, ENABLE); + break; + } + + return RT_EOK; +} + +static int es32f3x_putc(struct rt_serial_device *serial, char c) +{ + struct es32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + while (ald_uart_get_status(&uart->huart, UART_STATUS_TFEMPTY) == RESET) + ; + WRITE_REG(uart->huart.perh->TXBUF, c); + + return 1; +} + +static int es32f3x_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct es32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct es32_uart *)serial->parent.user_data; + + if (ald_uart_get_status(&uart->huart, UART_STATUS_RFTH)) + { + ch = (uint8_t)(uart->huart.perh->RXBUF & 0xFF); + } + + return ch; +} + +static const struct rt_uart_ops es32f3x_uart_ops = +{ + es32f3x_configure, + es32f3x_control, + es32f3x_putc, + es32f3x_getc, +}; + +#ifdef BSP_USING_UART0 +/* UART0 device driver structure */ +struct es32_uart uart0 = +{ + {UART0}, + UART0_IRQn +}; + +struct rt_serial_device serial0; + +void UART0_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if ((ald_uart_get_mask_flag_status(&uart0.huart, UART_IF_RFTH)) != RESET) + { + ald_uart_clear_flag_status(&uart0.huart, UART_IF_RFTH); + rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART0 */ + +#ifdef BSP_USING_UART1 +/* UART1 device driver structure */ +struct es32_uart uart1 = +{ + {UART1}, + UART1_IRQn +}; + +struct rt_serial_device serial1; + +void UART1_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if ((ald_uart_get_mask_flag_status(&uart1.huart, UART_IF_RFTH)) != RESET) + { + ald_uart_clear_flag_status(&uart1.huart, UART_IF_RFTH); + rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 +/* UART2 device driver structure */ +struct es32_uart uart2 = +{ + {UART2}, + UART2_IRQn +}; + +struct rt_serial_device serial2; + +void UART2_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if ((ald_uart_get_mask_flag_status(&uart2.huart, UART_IF_RFTH)) != RESET) + { + ald_uart_clear_flag_status(&uart2.huart, UART_IF_RFTH); + rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#ifdef BSP_USING_UART3 +/* UART3 device driver structure */ +struct es32_uart uart3 = +{ + {UART3}, + UART3_IRQn +}; + +struct rt_serial_device serial3; + +void UART3_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if ((ald_uart_get_mask_flag_status(&uart3.huart, UART_IF_RFTH)) != RESET) + { + ald_uart_clear_flag_status(&uart3.huart, UART_IF_RFTH); + rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +#ifdef BSP_USING_UART4 +/* UART4 device driver structure */ +struct es32_uart uart4 = +{ + {UART4}, + UART4_IRQn +}; + +struct rt_serial_device serial4; + +void UART4_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if ((ald_uart_get_mask_flag_status(&uart4.huart, UART_IF_RFTH)) != RESET) + { + ald_uart_clear_flag_status(&uart4.huart, UART_IF_RFTH); + rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART4 */ + +#ifdef BSP_USING_UART5 +/* UART5 device driver structure */ +struct es32_uart uart5 = +{ + {UART5}, + UART5_IRQn +}; + +struct rt_serial_device serial5; + +void UART5_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if ((ald_uart_get_mask_flag_status(&uart5.huart, UART_IF_RFTH)) != RESET) + { + ald_uart_clear_flag_status(&uart5.huart, UART_IF_RFTH); + rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART5 */ + +int rt_hw_uart_init(void) +{ + struct es32_uart *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + +#ifdef BSP_USING_UART0 + uart = &uart0; + serial0.ops = &es32f3x_uart_ops; + serial0.config = config; + + /* register UART0 device */ + rt_hw_serial_register(&serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART0 */ + +#ifdef BSP_USING_UART1 + uart = &uart1; + serial1.ops = &es32f3x_uart_ops; + serial1.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 + uart = &uart2; + serial2.ops = &es32f3x_uart_ops; + serial2.config = config; + + /* register UART2 device */ + rt_hw_serial_register(&serial2, "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART2 */ + +#ifdef BSP_USING_UART3 + uart = &uart3; + serial3.ops = &es32f3x_uart_ops; + serial3.config = config; + + /* register UART3 device */ + rt_hw_serial_register(&serial3, "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART3 */ + +#ifdef BSP_USING_UART4 + uart = &uart4; + serial4.ops = &es32f3x_uart_ops; + serial4.config = config; + + /* register UART4 device */ + rt_hw_serial_register(&serial4, "uart4", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART4 */ + +#ifdef BSP_USING_UART5 + uart = &uart5; + serial5.ops = &es32f3x_uart_ops; + serial5.config = config; + + /* register UART5 device */ + rt_hw_serial_register(&serial5, "uart5", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* BSP_USING_UART5 */ + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/drv_uart.h b/bsp/essemi/es32f369x/drivers/drv_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..fed318408096e44038eceb030655ec15b5eff2e4 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/drv_uart.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-14 wangyq the first version + */ + +#ifndef DRV_UART_H__ +#define DRV_UART_H__ + +int rt_hw_uart_init(void); + +#endif diff --git a/bsp/essemi/es32f369x/drivers/linker_scripts/link.sct b/bsp/essemi/es32f369x/drivers/linker_scripts/link.sct new file mode 100644 index 0000000000000000000000000000000000000000..c93ceefd3383685e42a1447333dc2117c92f2378 --- /dev/null +++ b/bsp/essemi/es32f369x/drivers/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00080000 { ; load region size_region + ER_IROM1 0x00000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00018000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/essemi/es32f369x/figures/ES-PDS-ES32F369x-V1.2.jpg b/bsp/essemi/es32f369x/figures/ES-PDS-ES32F369x-V1.2.jpg new file mode 100644 index 0000000000000000000000000000000000000000..e95b74a5e23562a4b14a647e42aecc8a5c76dc9c Binary files /dev/null and b/bsp/essemi/es32f369x/figures/ES-PDS-ES32F369x-V1.2.jpg differ diff --git a/bsp/essemi/es32f369x/figures/ESLinkII-mini.jpg b/bsp/essemi/es32f369x/figures/ESLinkII-mini.jpg new file mode 100644 index 0000000000000000000000000000000000000000..63026a89e10db8751ca5ec1c7b596b4431ba2ccb Binary files /dev/null and b/bsp/essemi/es32f369x/figures/ESLinkII-mini.jpg differ diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h new file mode 100644 index 0000000000000000000000000000000000000000..dcb4caf65c36cd860f93d736d0a63591e18dfc39 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h @@ -0,0 +1,9160 @@ +/** + ********************************************************************************* + * + * @file es32f36xx.h + * @brief ES32F36xx Device Head File + * + * @version V1.0 + * @date 18 Dec 2018 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ES32F36XX_H__ +#define __ES32F36XX_H__ + +#define __I volatile const /* defines 'read only' permissions */ +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +#define __CHECK_DEVICE_DEFINES +#define __NVIC_PRIO_BITS 4U +#define __CM3_REV 0x0200U +#define __MPU_PRESENT 0x1 +#define __Vendor_SysTickConfig 0U + +typedef enum IRQn { + /* Cortex-M3 processor cxceptions index */ + Reset_IRQn = -15, + NMI_IRQn = -14, + HardFault_IRQn = -13, + MemManage_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + /* es32f36xx specific interrupt index */ + WWDG_IRQn = 0, + IWDG_IRQn = 1, + LVD_IRQn = 2, + RTC_IRQn = 3, + CMU_IRQn = 6, + ADC0_IRQn = 7, + CAN0_TX_IRQn = 8, + CAN0_RX0_IRQn = 9, + CAN0_RX1_IRQn = 10, + CAN0_EXCEPTION_IRQn = 11, + AD16C4T0_BRK_IRQn = 12, + AD16C4T0_UP_IRQn = 13, + AD16C4T0_TRIG_COM_IRQn = 14, + AD16C4T0_CC_IRQn = 15, + AD16C4T1_BRK_IRQn = 16, + AD16C4T1_UP_IRQn = 17, + AD16C4T1_TRIG_COM_IRQn = 18, + AD16C4T1_CC_IRQn = 19, + GP32C4T0_IRQn = 20, + GP32C4T1_IRQn = 21, + BS16T0_IRQn = 22, + BS16T1_IRQn = 23, + GP16C4T0_IRQn = 24, + GP16C4T1_IRQn = 25, + DAC0_CH0_IRQn = 27, + I2C0_EV_IRQn = 28, + I2C0_ERR_IRQn = 29, + I2C1_EV_IRQn = 30, + I2C1_ERR_IRQn = 31, + SPI0_I2S0_IRQn = 32, + SPI1_I2S1_IRQn = 33, + UART0_IRQn = 34, + UART1_IRQn = 35, + UART2_IRQn = 36, + UART3_IRQn = 37, + UART4_IRQn = 38, + UART5_IRQn = 39, + CRYPT_IRQn = 42, + ACMP0_IRQn = 43, + ACMP1_IRQn = 44, + SPI2_I2S2_IRQn = 45, + EBI_IRQn = 47, + TRNG_IRQn = 48, + TSENSE_IRQn = 49, + EXTI0_IRQn = 50, + EXTI1_IRQn = 51, + EXTI2_IRQn = 52, + EXTI3_IRQn = 53, + EXTI4_IRQn = 54, + EXTI5_IRQn = 55, + EXTI6_IRQn = 56, + EXTI7_IRQn = 57, + EXTI8_IRQn = 58, + EXTI9_IRQn = 59, + EXTI10_IRQn = 60, + EXTI11_IRQn = 61, + EXTI12_IRQn = 62, + EXTI13_IRQn = 63, + EXTI14_IRQn = 64, + EXTI15_IRQn = 65, + DMA_IRQn = 66, + ADC1_IRQn = 67, + DAC0_CH1_IRQn = 68, + QSPI_IRQn = 69, + USB_INT_IRQn = 70, + USB_DMA_IRQn = 71, + ACMP2_IRQn = 72, +} IRQn_Type; + + +#include +#include "core_cm3.h" + +#if defined (__CC_ARM) +#pragma anon_unions +#endif + +/* Peripheral register define */ + +/****************** Bit definition for SYSCFG_PROT register ************************/ + +#define SYSCFG_PROT_KEY_POSS 0U +#define SYSCFG_PROT_KEY_POSE 31U +#define SYSCFG_PROT_KEY_MSK BITS(SYSCFG_PROT_KEY_POSS,SYSCFG_PROT_KEY_POSE) + +#define SYSCFG_PROT_PROT_POS 0U +#define SYSCFG_PROT_PROT_MSK BIT(SYSCFG_PROT_PROT_POS) + +/****************** Bit definition for SYSCFG_MEMRMP register ************************/ + +#define SYSCFG_MEMRMP_BFRMPEN_POS 8U +#define SYSCFG_MEMRMP_BFRMPEN_MSK BIT(SYSCFG_MEMRMP_BFRMPEN_POS) + +#define SYSCFG_MEMRMP_BRRMPEN_POS 0U +#define SYSCFG_MEMRMP_BRRMPEN_MSK BIT(SYSCFG_MEMRMP_BRRMPEN_POS) + +/****************** Bit definition for SYSCFG_USBCFG register ************************/ + +#define SYSCFG_USBCFG_CLKRDY_POS 26U +#define SYSCFG_USBCFG_CLKRDY_MSK BIT(SYSCFG_USBCFG_CLKRDY_POS) + +#define SYSCFG_USBCFG_CLKRDYBP_POS 25U +#define SYSCFG_USBCFG_CLKRDYBP_MSK BIT(SYSCFG_USBCFG_CLKRDYBP_POS) + +#define SYSCFG_USBCFG_CKSEL_POS 24U +#define SYSCFG_USBCFG_CKSEL_MSK BIT(SYSCFG_USBCFG_CKSEL_POS) + +#define SYSCFG_USBCFG_ITRM_POSS 22U +#define SYSCFG_USBCFG_ITRM_POSE 23U +#define SYSCFG_USBCFG_ITRM_MSK BITS(SYSCFG_USBCFG_ITRM_POSS,SYSCFG_USBCFG_ITRM_POSE) + +#define SYSCFG_USBCFG_CKDIVN_POSS 16U +#define SYSCFG_USBCFG_CKDIVN_POSE 21U +#define SYSCFG_USBCFG_CKDIVN_MSK BITS(SYSCFG_USBCFG_CKDIVN_POSS,SYSCFG_USBCFG_CKDIVN_POSE) + +#define SYSCFG_USBCFG_CKDIVM_POSS 8U +#define SYSCFG_USBCFG_CKDIVM_POSE 11U +#define SYSCFG_USBCFG_CKDIVM_MSK BITS(SYSCFG_USBCFG_CKDIVM_POSS,SYSCFG_USBCFG_CKDIVM_POSE) + +#define SYSCFG_USBCFG_HSDRV_POSS 2U +#define SYSCFG_USBCFG_HSDRV_POSE 3U +#define SYSCFG_USBCFG_HSDRV_MSK BITS(SYSCFG_USBCFG_HSDRV_POSS,SYSCFG_USBCFG_HSDRV_POSE) + +#define SYSCFG_USBCFG_TXHBSE_POS 1U +#define SYSCFG_USBCFG_TXHBSE_MSK BIT(SYSCFG_USBCFG_TXHBSE_POS) + +#define SYSCFG_USBCFG_TXLBSE_POS 0U +#define SYSCFG_USBCFG_TXLBSE_MSK BIT(SYSCFG_USBCFG_TXLBSE_POS) + +/****************** Bit definition for SYSCFG_TBKCFG register ************************/ + +#define SYSCFG_TBKCFG_CLUBKE_POS 2U +#define SYSCFG_TBKCFG_CLUBKE_MSK BIT(SYSCFG_TBKCFG_CLUBKE_POS) + +#define SYSCFG_TBKCFG_LVDBKE_POS 1U +#define SYSCFG_TBKCFG_LVDBKE_MSK BIT(SYSCFG_TBKCFG_LVDBKE_POS) + +#define SYSCFG_TBKCFG_CSSBKE_POS 0U +#define SYSCFG_TBKCFG_CSSBKE_MSK BIT(SYSCFG_TBKCFG_CSSBKE_POS) + +typedef struct +{ + __IO uint32_t PROT; + __IO uint32_t MEMRMP; + uint32_t rsv0; + __IO uint32_t USBCFG; + __IO uint32_t TBKCFG; + uint32_t rsv1[59]; + __IO uint32_t TESTKEY; + uint32_t rsv2[7]; + __IO uint32_t USBTEST; +} SYSCFG_TypeDef; + +/****************** Bit definition for MSC_FLASHKEY register ************************/ + +#define MSC_FLASHKEY_STATUS_POSS 0U +#define MSC_FLASHKEY_STATUS_POSE 1U +#define MSC_FLASHKEY_STATUS_MSK BITS(MSC_FLASHKEY_STATUS_POSS,MSC_FLASHKEY_STATUS_POSE) + +/****************** Bit definition for MSC_INFOKEY register ************************/ + +#define MSC_INFOKEY_STATUS_POSS 0U +#define MSC_INFOKEY_STATUS_POSE 1U +#define MSC_INFOKEY_STATUS_MSK BITS(MSC_INFOKEY_STATUS_POSS,MSC_INFOKEY_STATUS_POSE) + +/****************** Bit definition for MSC_FLASHADDR register ************************/ + +#define MSC_FLASHADDR_IFREN_POS 18U +#define MSC_FLASHADDR_IFREN_MSK BIT(MSC_FLASHADDR_IFREN_POS) + +#define MSC_FLASHADDR_ADDR_POSS 0U +#define MSC_FLASHADDR_ADDR_POSE 17U +#define MSC_FLASHADDR_ADDR_MSK BITS(MSC_FLASHADDR_ADDR_POSS,MSC_FLASHADDR_ADDR_POSE) + +/****************** Bit definition for MSC_FLASHFIFO register ************************/ + +#define MSC_FLASHFIFO_FIFO_POSS 0U +#define MSC_FLASHFIFO_FIFO_POSE 31U +#define MSC_FLASHFIFO_FIFO_MSK BITS(MSC_FLASHFIFO_FIFO_POSS,MSC_FLASHFIFO_FIFO_POSE) + +/****************** Bit definition for MSC_FLASHDL register ************************/ + +#define MSC_FLASHDL_DATAL_POSS 0U +#define MSC_FLASHDL_DATAL_POSE 31U +#define MSC_FLASHDL_DATAL_MSK BITS(MSC_FLASHDL_DATAL_POSS,MSC_FLASHDL_DATAL_POSE) + +/****************** Bit definition for MSC_FLASHDH register ************************/ + +#define MSC_FLASHDH_DATAH_POSS 0U +#define MSC_FLASHDH_DATAH_POSE 31U +#define MSC_FLASHDH_DATAH_MSK BITS(MSC_FLASHDH_DATAH_POSS,MSC_FLASHDH_DATAH_POSE) + +/****************** Bit definition for MSC_FLASHCMD register ************************/ + +#define MSC_FLASHCMD_CMD_POSS 0U +#define MSC_FLASHCMD_CMD_POSE 31U +#define MSC_FLASHCMD_CMD_MSK BITS(MSC_FLASHCMD_CMD_POSS,MSC_FLASHCMD_CMD_POSE) + +/****************** Bit definition for MSC_FLASHCR register ************************/ + +#define MSC_FLASHCR_FIFOEN_POS 5U +#define MSC_FLASHCR_FIFOEN_MSK BIT(MSC_FLASHCR_FIFOEN_POS) + +#define MSC_FLASHCR_FLASHREQ_POS 4U +#define MSC_FLASHCR_FLASHREQ_MSK BIT(MSC_FLASHCR_FLASHREQ_POS) + +#define MSC_FLASHCR_IAPRST_POS 1U +#define MSC_FLASHCR_IAPRST_MSK BIT(MSC_FLASHCR_IAPRST_POS) + +#define MSC_FLASHCR_IAPEN_POS 0U +#define MSC_FLASHCR_IAPEN_MSK BIT(MSC_FLASHCR_IAPEN_POS) + +/****************** Bit definition for MSC_FLASHSR register ************************/ + +#define MSC_FLASHSR_TIMEOUT_POS 7U +#define MSC_FLASHSR_TIMEOUT_MSK BIT(MSC_FLASHSR_TIMEOUT_POS) + +#define MSC_FLASHSR_PROG_POS 6U +#define MSC_FLASHSR_PROG_MSK BIT(MSC_FLASHSR_PROG_POS) + +#define MSC_FLASHSR_SERA_POS 5U +#define MSC_FLASHSR_SERA_MSK BIT(MSC_FLASHSR_SERA_POS) + +#define MSC_FLASHSR_MASE_POS 4U +#define MSC_FLASHSR_MASE_MSK BIT(MSC_FLASHSR_MASE_POS) + +#define MSC_FLASHSR_ADDR_OV_POS 3U +#define MSC_FLASHSR_ADDR_OV_MSK BIT(MSC_FLASHSR_ADDR_OV_POS) + +#define MSC_FLASHSR_WRP_FLAG_POS 2U +#define MSC_FLASHSR_WRP_FLAG_MSK BIT(MSC_FLASHSR_WRP_FLAG_POS) + +#define MSC_FLASHSR_BUSY_POS 1U +#define MSC_FLASHSR_BUSY_MSK BIT(MSC_FLASHSR_BUSY_POS) + +#define MSC_FLASHSR_FLASHACK_POS 0U +#define MSC_FLASHSR_FLASHACK_MSK BIT(MSC_FLASHSR_FLASHACK_POS) + +/****************** Bit definition for MSC_FLASHPL register ************************/ + +#define MSC_FLASHPL_PROG_LEN_POSS 0U +#define MSC_FLASHPL_PROG_LEN_POSE 15U +#define MSC_FLASHPL_PROG_LEN_MSK BITS(MSC_FLASHPL_PROG_LEN_POSS,MSC_FLASHPL_PROG_LEN_POSE) + +/****************** Bit definition for MSC_MEMWAIT register ************************/ + +#define MSC_MEMWAIT_SRAM_W_POSS 8U +#define MSC_MEMWAIT_SRAM_W_POSE 9U +#define MSC_MEMWAIT_SRAM_W_MSK BITS(MSC_MEMWAIT_SRAM_W_POSS,MSC_MEMWAIT_SRAM_W_POSE) + +#define MSC_MEMWAIT_FLASH_W_POSS 0U +#define MSC_MEMWAIT_FLASH_W_POSE 3U +#define MSC_MEMWAIT_FLASH_W_MSK BITS(MSC_MEMWAIT_FLASH_W_POSS,MSC_MEMWAIT_FLASH_W_POSE) + +typedef struct +{ + __IO uint32_t FLASHKEY; + __IO uint32_t INFOKEY; + __IO uint32_t FLASHADDR; + __O uint32_t FLASHFIFO; + __IO uint32_t FLASHDL; + __IO uint32_t FLASHDH; + __O uint32_t FLASHCMD; + __IO uint32_t FLASHCR; + __I uint32_t FLASHSR; + __IO uint32_t FLASHPL; + __IO uint32_t MEMWAIT; +} MSC_TypeDef; + +/****************** Bit definition for BKPC_PROT register ************************/ + +#define BKPC_PROT_KEY_POSS 1U +#define BKPC_PROT_KEY_POSE 31U +#define BKPC_PROT_KEY_MSK BITS(BKPC_PROT_KEY_POSS,BKPC_PROT_KEY_POSE) + +#define BKPC_PROT_PROT_POS 0U +#define BKPC_PROT_PROT_MSK BIT(BKPC_PROT_PROT_POS) + +/****************** Bit definition for BKPC_CR register ************************/ + +#define BKPC_CR_WKPOL_POS 12U +#define BKPC_CR_WKPOL_MSK BIT(BKPC_CR_WKPOL_POS) + +#define BKPC_CR_WKPS_POSS 9U +#define BKPC_CR_WKPS_POSE 11U +#define BKPC_CR_WKPS_MSK BITS(BKPC_CR_WKPS_POSS,BKPC_CR_WKPS_POSE) + +#define BKPC_CR_WKPEN_POS 8U +#define BKPC_CR_WKPEN_MSK BIT(BKPC_CR_WKPEN_POS) + +#define BKPC_CR_MRST_WKPEN_POS 7U +#define BKPC_CR_MRST_WKPEN_MSK BIT(BKPC_CR_MRST_WKPEN_POS) + +#define BKPC_CR_LRCEN_POS 2U +#define BKPC_CR_LRCEN_MSK BIT(BKPC_CR_LRCEN_POS) + +#define BKPC_CR_LOSMEN_POS 1U +#define BKPC_CR_LOSMEN_MSK BIT(BKPC_CR_LOSMEN_POS) + +#define BKPC_CR_LOSCEN_POS 0U +#define BKPC_CR_LOSCEN_MSK BIT(BKPC_CR_LOSCEN_POS) + +/****************** Bit definition for BKPC_PCCR register ************************/ + +#define BKPC_PCCR_CLKEN_POS 16U +#define BKPC_PCCR_CLKEN_MSK BIT(BKPC_PCCR_CLKEN_POS) + +#define BKPC_PCCR_TSENSECS_POSS 4U +#define BKPC_PCCR_TSENSECS_POSE 5U +#define BKPC_PCCR_TSENSECS_MSK BITS(BKPC_PCCR_TSENSECS_POSS,BKPC_PCCR_TSENSECS_POSE) + +#define BKPC_PCCR_RTCCS_POSS 0U +#define BKPC_PCCR_RTCCS_POSE 1U +#define BKPC_PCCR_RTCCS_MSK BITS(BKPC_PCCR_RTCCS_POSS,BKPC_PCCR_RTCCS_POSE) + +/****************** Bit definition for BKPC_PDCR register ************************/ + +#define BKPC_PDCR_ISOLATE_POS 0U +#define BKPC_PDCR_ISOLATE_MSK BIT(BKPC_PDCR_ISOLATE_POS) + +#define BKPC_PDCR_PWRDOWN_POS 0U +#define BKPC_PDCR_PWRDOWN_MSK BIT(BKPC_PDCR_PWRDOWN_POS) + +typedef struct +{ + __IO uint32_t PROT; + __IO uint32_t CR; + __IO uint32_t PCCR; + __IO uint32_t PCR; +} BKPC_TypeDef; + +/****************** Bit definition for PMU_CR0 register ************************/ + +#define PMU_CR0_MTSTOP_POS 21U +#define PMU_CR0_MTSTOP_MSK BIT(PMU_CR0_MTSTOP_POS) + +#define PMU_CR0_LPSTOP_POS 20U +#define PMU_CR0_LPSTOP_MSK BIT(PMU_CR0_LPSTOP_POS) + +#define PMU_CR0_LPRUN_POS 19U +#define PMU_CR0_LPRUN_MSK BIT(PMU_CR0_LPRUN_POS) + +#define PMU_CR0_LPVS_POSS 16U +#define PMU_CR0_LPVS_POSE 17U +#define PMU_CR0_LPVS_MSK BITS(PMU_CR0_LPVS_POSS,PMU_CR0_LPVS_POSE) + +#define PMU_CR0_SFPD_POS 15U +#define PMU_CR0_SFPD_MSK BIT(PMU_CR0_SFPD_POS) + +#define PMU_CR0_CSTANDBYF_POS 3U +#define PMU_CR0_CSTANDBYF_MSK BIT(PMU_CR0_CSTANDBYF_POS) + +#define PMU_CR0_CWUF_POS 2U +#define PMU_CR0_CWUF_MSK BIT(PMU_CR0_CWUF_POS) + +#define PMU_CR0_LPM_POSS 0U +#define PMU_CR0_LPM_POSE 1U +#define PMU_CR0_LPM_MSK BITS(PMU_CR0_LPM_POSS,PMU_CR0_LPM_POSE) + +/****************** Bit definition for PMU_CR1 register ************************/ + +#define PMU_CR1_LDO18RDY_POS 15U +#define PMU_CR1_LDO18RDY_MSK BIT(PMU_CR1_LDO18RDY_POS) + +#define PMU_CR1_LDO18PRM_POS 2U +#define PMU_CR1_LDO18PRM_MSK BIT(PMU_CR1_LDO18PRM_POS) + +#define PMU_CR1_LDO18MOD_POSS 0U +#define PMU_CR1_LDO18MOD_POSE 1U +#define PMU_CR1_LDO18MOD_MSK BITS(PMU_CR1_LDO18MOD_POSS,PMU_CR1_LDO18MOD_POSE) + +/****************** Bit definition for PMU_SR register ************************/ + +#define PMU_SR_RSTAT_POS 3U +#define PMU_SR_RSTAT_MSK BIT(PMU_SR_RSTAT_POS) + +#define PMU_SR_USBRDY_POS 2U +#define PMU_SR_USBRDY_MSK BIT(PMU_SR_USBRDY_POS) + +#define PMU_SR_STANDBYF_POS 1U +#define PMU_SR_STANDBYF_MSK BIT(PMU_SR_STANDBYF_POS) + +#define PMU_SR_WUF_POS 0U +#define PMU_SR_WUF_MSK BIT(PMU_SR_WUF_POS) + +/****************** Bit definition for PMU_LVDCR register ************************/ + +#define PMU_LVDCR_LVDO_POS 15U +#define PMU_LVDCR_LVDO_MSK BIT(PMU_LVDCR_LVDO_POS) + +#define PMU_LVDCR_LVDFLT_POS 11U +#define PMU_LVDCR_LVDFLT_MSK BIT(PMU_LVDCR_LVDFLT_POS) + +#define PMU_LVDCR_LVIFS_POSS 8U +#define PMU_LVDCR_LVIFS_POSE 10U +#define PMU_LVDCR_LVIFS_MSK BITS(PMU_LVDCR_LVIFS_POSS,PMU_LVDCR_LVIFS_POSE) + +#define PMU_LVDCR_LVDS_POSS 4U +#define PMU_LVDCR_LVDS_POSE 7U +#define PMU_LVDCR_LVDS_MSK BITS(PMU_LVDCR_LVDS_POSS,PMU_LVDCR_LVDS_POSE) + +#define PMU_LVDCR_LVDCIF_POS 3U +#define PMU_LVDCR_LVDCIF_MSK BIT(PMU_LVDCR_LVDCIF_POS) + +#define PMU_LVDCR_LVDIF_POS 2U +#define PMU_LVDCR_LVDIF_MSK BIT(PMU_LVDCR_LVDIF_POS) + +#define PMU_LVDCR_LVDIE_POS 1U +#define PMU_LVDCR_LVDIE_MSK BIT(PMU_LVDCR_LVDIE_POS) + +#define PMU_LVDCR_LVDEN_POS 0U +#define PMU_LVDCR_LVDEN_MSK BIT(PMU_LVDCR_LVDEN_POS) + +/****************** Bit definition for PMU_PWRCR register ************************/ + +#define PMU_PWRCR_ROM_POS 12U +#define PMU_PWRCR_ROM_MSK BIT(PMU_PWRCR_ROM_POS) + +#define PMU_PWRCR_USB_POS 11U +#define PMU_PWRCR_USB_MSK BIT(PMU_PWRCR_USB_POS) + +#define PMU_PWRCR_QSPI_POS 10U +#define PMU_PWRCR_QSPI_MSK BIT(PMU_PWRCR_QSPI_POS) + +#define PMU_PWRCR_BXCAN_POS 8U +#define PMU_PWRCR_BXCAN_MSK BIT(PMU_PWRCR_BXCAN_POS) + +#define PMU_PWRCR_SRAM_POSS 0U +#define PMU_PWRCR_SRAM_POSE 5U +#define PMU_PWRCR_SRAM_MSK BITS(PMU_PWRCR_SRAM_POSS,PMU_PWRCR_SRAM_POSE) + +/****************** Bit definition for PMU_VREFCR register ************************/ + +#define PMU_VREFCR_VREFEN_POS 0U +#define PMU_VREFCR_VREFEN_MSK BIT(PMU_VREFCR_VREFEN_POS) + +typedef struct +{ + __IO uint32_t CR0; + __IO uint32_t CR1; + __I uint32_t SR; + __IO uint32_t LVDCR; + __IO uint32_t PWRCR; + uint32_t RESERVED0[3] ; + __IO uint32_t VREFCR; +} PMU_TypeDef; + +/****************** Bit definition for RMU_CR register ************************/ + +#define RMU_CR_BORVS_POSS 4U +#define RMU_CR_BORVS_POSE 7U +#define RMU_CR_BORVS_MSK BITS(RMU_CR_BORVS_POSS,RMU_CR_BORVS_POSE) + +#define RMU_CR_BORFLT_POSS 1U +#define RMU_CR_BORFLT_POSE 3U +#define RMU_CR_BORFLT_MSK BITS(RMU_CR_BORFLT_POSS,RMU_CR_BORFLT_POSE) + +#define RMU_CR_BOREN_POS 0U +#define RMU_CR_BOREN_MSK BIT(RMU_CR_BOREN_POS) + +/****************** Bit definition for RMU_RSTSR register ************************/ + +#define RMU_RSTSR_CFGERR_POS 16U +#define RMU_RSTSR_CFGERR_MSK BIT(RMU_RSTSR_CFGERR_POS) + +#define RMU_RSTSR_CFG_POS 10U +#define RMU_RSTSR_CFG_MSK BIT(RMU_RSTSR_CFG_POS) + +#define RMU_RSTSR_CPU_POS 9U +#define RMU_RSTSR_CPU_MSK BIT(RMU_RSTSR_CPU_POS) + +#define RMU_RSTSR_MCU_POS 8U +#define RMU_RSTSR_MCU_MSK BIT(RMU_RSTSR_MCU_POS) + +#define RMU_RSTSR_CHIP_POS 7U +#define RMU_RSTSR_CHIP_MSK BIT(RMU_RSTSR_CHIP_POS) + +#define RMU_RSTSR_LOCKUP_POS 6U +#define RMU_RSTSR_LOCKUP_MSK BIT(RMU_RSTSR_LOCKUP_POS) + +#define RMU_RSTSR_WWDT_POS 5U +#define RMU_RSTSR_WWDT_MSK BIT(RMU_RSTSR_WWDT_POS) + +#define RMU_RSTSR_IWDT_POS 4U +#define RMU_RSTSR_IWDT_MSK BIT(RMU_RSTSR_IWDT_POS) + +#define RMU_RSTSR_NMRST_POS 3U +#define RMU_RSTSR_NMRST_MSK BIT(RMU_RSTSR_NMRST_POS) + +#define RMU_RSTSR_BOR_POS 2U +#define RMU_RSTSR_BOR_MSK BIT(RMU_RSTSR_BOR_POS) + +#define RMU_RSTSR_WAKEUP_POS 1U +#define RMU_RSTSR_WAKEUP_MSK BIT(RMU_RSTSR_WAKEUP_POS) + +#define RMU_RSTSR_POR_POS 0U +#define RMU_RSTSR_POR_MSK BIT(RMU_RSTSR_POR_POS) + +/****************** Bit definition for RMU_CRSTSR register ************************/ + +#define RMU_CRSTSR_CFG_POS 10U +#define RMU_CRSTSR_CFG_MSK BIT(RMU_CRSTSR_CFG_POS) + +#define RMU_CRSTSR_CPU_POS 9U +#define RMU_CRSTSR_CPU_MSK BIT(RMU_CRSTSR_CPU_POS) + +#define RMU_CRSTSR_MCU_POS 8U +#define RMU_CRSTSR_MCU_MSK BIT(RMU_CRSTSR_MCU_POS) + +#define RMU_CRSTSR_CHIP_POS 7U +#define RMU_CRSTSR_CHIP_MSK BIT(RMU_CRSTSR_CHIP_POS) + +#define RMU_CRSTSR_LOCKUP_POS 6U +#define RMU_CRSTSR_LOCKUP_MSK BIT(RMU_CRSTSR_LOCKUP_POS) + +#define RMU_CRSTSR_WWDT_POS 5U +#define RMU_CRSTSR_WWDT_MSK BIT(RMU_CRSTSR_WWDT_POS) + +#define RMU_CRSTSR_IWDT_POS 4U +#define RMU_CRSTSR_IWDT_MSK BIT(RMU_CRSTSR_IWDT_POS) + +#define RMU_CRSTSR_NMRST_POS 3U +#define RMU_CRSTSR_NMRST_MSK BIT(RMU_CRSTSR_NMRST_POS) + +#define RMU_CRSTSR_BOR_POS 2U +#define RMU_CRSTSR_BOR_MSK BIT(RMU_CRSTSR_BOR_POS) + +#define RMU_CRSTSR_WAKEUP_POS 1U +#define RMU_CRSTSR_WAKEUP_MSK BIT(RMU_CRSTSR_WAKEUP_POS) + +#define RMU_CRSTSR_POR_POS 0U +#define RMU_CRSTSR_POR_MSK BIT(RMU_CRSTSR_POR_POS) + +/****************** Bit definition for RMU_AHB1RSTR register ************************/ + +#define RMU_AHB1RSTR_ECCRST_POS 11U +#define RMU_AHB1RSTR_ECCRST_MSK BIT(RMU_AHB1RSTR_ECCRST_POS) + +#define RMU_AHB1RSTR_USBRST_POS 10U +#define RMU_AHB1RSTR_USBRST_MSK BIT(RMU_AHB1RSTR_USBRST_POS) + +#define RMU_AHB1RSTR_TRNGRST_POS 4U +#define RMU_AHB1RSTR_TRNGRST_MSK BIT(RMU_AHB1RSTR_TRNGRST_POS) + +#define RMU_AHB1RSTR_PISRST_POS 5U +#define RMU_AHB1RSTR_PISRST_MSK BIT(RMU_AHB1RSTR_PISRST_POS) + +#define RMU_AHB1RSTR_TRNGRST_POS 4U +#define RMU_AHB1RSTR_TRNGRST_MSK BIT(RMU_AHB1RSTR_TRNGRST_POS) + +#define RMU_AHB1RSTR_CRYPTRST_POS 3U +#define RMU_AHB1RSTR_CRYPTRST_MSK BIT(RMU_AHB1RSTR_CRYPTRST_POS) + +#define RMU_AHB1RSTR_CALCRST_POS 2U +#define RMU_AHB1RSTR_CALCRST_MSK BIT(RMU_AHB1RSTR_CALCRST_POS) + +#define RMU_AHB1RSTR_CRCRST_POS 1U +#define RMU_AHB1RSTR_CRCRST_MSK BIT(RMU_AHB1RSTR_CRCRST_POS) + +#define RMU_AHB1RSTR_GPIORST_POS 0U +#define RMU_AHB1RSTR_GPIORST_MSK BIT(RMU_AHB1RSTR_GPIORST_POS) + +/****************** Bit definition for RMU_AHB2RSTR register ************************/ + +#define RMU_AHB2RSTR_EBIRST_POS 8U +#define RMU_AHB2RSTR_EBIRST_MSK BIT(RMU_AHB2RSTR_EBIRST_POS) + +#define RMU_AHB2RSTR_CPURST_POS 1U +#define RMU_AHB2RSTR_CPURST_MSK BIT(RMU_AHB2RSTR_CPURST_POS) + +#define RMU_AHB2RSTR_CHIPRST_POS 0U +#define RMU_AHB2RSTR_CHIPRST_MSK BIT(RMU_AHB2RSTR_CHIPRST_POS) + +/****************** Bit definition for RMU_APB1RSTR register ************************/ + +#define RMU_APB1RSTR_QSPIRST_POS 25U +#define RMU_APB1RSTR_QSPIRST_MSK BIT(RMU_APB1RSTR_QSPIRST_POS) + +#define RMU_APB1RSTR_CAN0RST_POS 24U +#define RMU_APB1RSTR_CAN0RST_MSK BIT(RMU_APB1RSTR_CAN0RST_POS) + +#define RMU_APB1RSTR_I2C1RST_POS 21U +#define RMU_APB1RSTR_I2C1RST_MSK BIT(RMU_APB1RSTR_I2C1RST_POS) + +#define RMU_APB1RSTR_I2C0RST_POS 20U +#define RMU_APB1RSTR_I2C0RST_MSK BIT(RMU_APB1RSTR_I2C0RST_POS) + +#define RMU_APB1RSTR_SPI2RST_POS 18U +#define RMU_APB1RSTR_SPI2RST_MSK BIT(RMU_APB1RSTR_SPI2RST_POS) + +#define RMU_APB1RSTR_SPI1RST_POS 17U +#define RMU_APB1RSTR_SPI1RST_MSK BIT(RMU_APB1RSTR_SPI1RST_POS) + +#define RMU_APB1RSTR_SPI0RST_POS 16U +#define RMU_APB1RSTR_SPI0RST_MSK BIT(RMU_APB1RSTR_SPI0RST_POS) + +#define RMU_APB1RSTR_UART5RST_POS 13U +#define RMU_APB1RSTR_UART5RST_MSK BIT(RMU_APB1RSTR_UART5RST_POS) + +#define RMU_APB1RSTR_UART4RST_POS 12U +#define RMU_APB1RSTR_UART4RST_MSK BIT(RMU_APB1RSTR_UART4RST_POS) + +#define RMU_APB1RSTR_UART3RST_POS 11U +#define RMU_APB1RSTR_UART3RST_MSK BIT(RMU_APB1RSTR_UART3RST_POS) + +#define RMU_APB1RSTR_UART2RST_POS 10U +#define RMU_APB1RSTR_UART2RST_MSK BIT(RMU_APB1RSTR_UART2RST_POS) + +#define RMU_APB1RSTR_UART1RST_POS 9U +#define RMU_APB1RSTR_UART1RST_MSK BIT(RMU_APB1RSTR_UART1RST_POS) + +#define RMU_APB1RSTR_UART0RST_POS 8U +#define RMU_APB1RSTR_UART0RST_MSK BIT(RMU_APB1RSTR_UART0RST_POS) + +#define RMU_APB1RSTR_TIM7RST_POS 7U +#define RMU_APB1RSTR_TIM7RST_MSK BIT(RMU_APB1RSTR_TIM7RST_POS) + +#define RMU_APB1RSTR_TIM6RST_POS 6U +#define RMU_APB1RSTR_TIM6RST_MSK BIT(RMU_APB1RSTR_TIM6RST_POS) + +#define RMU_APB1RSTR_TIM5RST_POS 5U +#define RMU_APB1RSTR_TIM5RST_MSK BIT(RMU_APB1RSTR_TIM5RST_POS) + +#define RMU_APB1RSTR_TIM4RST_POS 4U +#define RMU_APB1RSTR_TIM4RST_MSK BIT(RMU_APB1RSTR_TIM4RST_POS) + +#define RMU_APB1RSTR_TIM3RST_POS 3U +#define RMU_APB1RSTR_TIM3RST_MSK BIT(RMU_APB1RSTR_TIM3RST_POS) + +#define RMU_APB1RSTR_TIM2RST_POS 2U +#define RMU_APB1RSTR_TIM2RST_MSK BIT(RMU_APB1RSTR_TIM2RST_POS) + +#define RMU_APB1RSTR_TIM1RST_POS 1U +#define RMU_APB1RSTR_TIM1RST_MSK BIT(RMU_APB1RSTR_TIM1RST_POS) + +#define RMU_APB1RSTR_TIM0RST_POS 0U +#define RMU_APB1RSTR_TIM0RST_MSK BIT(RMU_APB1RSTR_TIM0RST_POS) + +/****************** Bit definition for RMU_APB2RSTR register ************************/ + +#define RMU_APB2RSTR_BKPRAMRST_POS 18U +#define RMU_APB2RSTR_BKPRAMRST_MSK BIT(RMU_APB2RSTR_BKPRAMRST_POS) + +#define RMU_APB2RSTR_BKPCRST_POS 17U +#define RMU_APB2RSTR_BKPCRST_MSK BIT(RMU_APB2RSTR_BKPCRST_POS) + +#define RMU_APB2RSTR_TSENSERST_POS 16U +#define RMU_APB2RSTR_TSENSERST_MSK BIT(RMU_APB2RSTR_TSENSERST_POS) + +#define RMU_APB2RSTR_RTCRST_POS 15U +#define RMU_APB2RSTR_RTCRST_MSK BIT(RMU_APB2RSTR_RTCRST_POS) + +#define RMU_APB2RSTR_IWDTRST_POS 14U +#define RMU_APB2RSTR_IWDTRST_MSK BIT(RMU_APB2RSTR_IWDTRST_POS) + +#define RMU_APB2RSTR_LCDRST_POS 13U +#define RMU_APB2RSTR_LCDRST_MSK BIT(RMU_APB2RSTR_LCDRST_POS) + +#define RMU_APB2RSTR_WWDTRST_POS 12U +#define RMU_APB2RSTR_WWDTRST_MSK BIT(RMU_APB2RSTR_WWDTRST_POS) + +#define RMU_APB2RSTR_ACMP2RST_POS 11U +#define RMU_APB2RSTR_ACMP2RST_MSK BIT(RMU_APB2RSTR_DACRST_POS) + +#define RMU_APB2RSTR_DACRST_POS 9U +#define RMU_APB2RSTR_DACRST_MSK BIT(RMU_APB2RSTR_DACRST_POS) + +#define RMU_APB2RSTR_OPAMPRST_POS 8U +#define RMU_APB2RSTR_OPAMPRST_MSK BIT(RMU_APB2RSTR_OPAMPRST_POS) + +#define RMU_APB2RSTR_ACMP1RST_POS 7U +#define RMU_APB2RSTR_ACMP1RST_MSK BIT(RMU_APB2RSTR_ACMP1RST_POS) + +#define RMU_APB2RSTR_ACMP0RST_POS 6U +#define RMU_APB2RSTR_ACMP0RST_MSK BIT(RMU_APB2RSTR_ACMP0RST_POS) + +#define RMU_APB2RSTR_ADC1RST_POS 5U +#define RMU_APB2RSTR_ADC1RST_MSK BIT(RMU_APB2RSTR_ADC1RST_POS) + +#define RMU_APB2RSTR_ADC0RST_POS 4U +#define RMU_APB2RSTR_ADC0RST_MSK BIT(RMU_APB2RSTR_ADC0RST_POS) + +#define RMU_APB2RSTR_LPUART0RST_POS 2U +#define RMU_APB2RSTR_LPUART0RST_MSK BIT(RMU_APB2RSTR_LPUART0RST_POS) + +#define RMU_APB2RSTR_LPTIM0RST_POS 0U +#define RMU_APB2RSTR_LPTIM0RST_MSK BIT(RMU_APB2RSTR_LPTIM0RST_POS) + +typedef struct +{ + __IO uint32_t CR; + uint32_t RESERVED0[3] ; + __I uint32_t RSTSR; + __O uint32_t CRSTSR; + uint32_t RESERVED1[2] ; + __O uint32_t AHB1RSTR; + __O uint32_t AHB2RSTR; + uint32_t RESERVED2[2] ; + __O uint32_t APB1RSTR; + __O uint32_t APB2RSTR; +} RMU_TypeDef; + +/****************** Bit definition for CMU_CSR register ************************/ + +#define CMU_CSR_CFT_RDYN_POS 25U +#define CMU_CSR_CFT_RDYN_MSK BIT(CMU_CSR_CFT_RDYN_POS) + +#define CMU_CSR_CFT_STU_POS 24U +#define CMU_CSR_CFT_STU_MSK BIT(CMU_CSR_CFT_STU_POS) + +#define CMU_CSR_CFT_CMD_POSS 16U +#define CMU_CSR_CFT_CMD_POSE 23U +#define CMU_CSR_CFT_CMD_MSK BITS(CMU_CSR_CFT_CMD_POSS,CMU_CSR_CFT_CMD_POSE) + +#define CMU_CSR_SYS_RDYN_POS 12U +#define CMU_CSR_SYS_RDYN_MSK BIT(CMU_CSR_SYS_RDYN_POS) + +#define CMU_CSR_SYS_STU_POSS 8U +#define CMU_CSR_SYS_STU_POSE 10U +#define CMU_CSR_SYS_STU_MSK BITS(CMU_CSR_SYS_STU_POSS,CMU_CSR_SYS_STU_POSE) + +#define CMU_CSR_SYS_CMD_POSS 0U +#define CMU_CSR_SYS_CMD_POSE 2U +#define CMU_CSR_SYS_CMD_MSK BITS(CMU_CSR_SYS_CMD_POSS,CMU_CSR_SYS_CMD_POSE) + +/****************** Bit definition for CMU_CFGR register ************************/ + +#define CMU_CFGR_HRCFCS_POS 26U +#define CMU_CFGR_HRCFCS_MSK BIT(CMU_CFGR_HRCFCS_POS) + +#define CMU_CFGR_HRCFST_POS 25U +#define CMU_CFGR_HRCFST_MSK BIT(CMU_CFGR_HRCFST_POS) + +#define CMU_CFGR_HRCFSW_POS 24U +#define CMU_CFGR_HRCFSW_MSK BIT(CMU_CFGR_HRCFSW_POS) + +#define CMU_CFGR_PCLK2DIV_POSS 20U +#define CMU_CFGR_PCLK2DIV_POSE 23U +#define CMU_CFGR_PCLK2DIV_MSK BITS(CMU_CFGR_PCLK2DIV_POSS,CMU_CFGR_PCLK2DIV_POSE) + +#define CMU_CFGR_PCLK1DIV_POSS 16U +#define CMU_CFGR_PCLK1DIV_POSE 19U +#define CMU_CFGR_PCLK1DIV_MSK BITS(CMU_CFGR_PCLK1DIV_POSS,CMU_CFGR_PCLK1DIV_POSE) + +#define CMU_CFGR_SYSDIV_POSS 12U +#define CMU_CFGR_SYSDIV_POSE 15U +#define CMU_CFGR_SYSDIV_MSK BITS(CMU_CFGR_SYSDIV_POSS,CMU_CFGR_SYSDIV_POSE) + +#define CMU_CFGR_HCLK2DIV_POSS 4U +#define CMU_CFGR_HCLK2DIV_POSE 7U +#define CMU_CFGR_HCLK2DIV_MSK BITS(CMU_CFGR_HCLK2DIV_POSS,CMU_CFGR_HCLK2DIV_POSE) + +#define CMU_CFGR_HCLK1DIV_POSS 0U +#define CMU_CFGR_HCLK1DIV_POSE 3U +#define CMU_CFGR_HCLK1DIV_MSK BITS(CMU_CFGR_HCLK1DIV_POSS,CMU_CFGR_HCLK1DIV_POSE) + +/****************** Bit definition for CMU_CLKENR register ************************/ + +#define CMU_CLKENR_HOSC1MEN_POS 17U +#define CMU_CLKENR_HOSC1MEN_MSK BIT(CMU_CLKENR_HOSC1MEN_POS) + +#define CMU_CLKENR_HRC1MEN_POS 16U +#define CMU_CLKENR_HRC1MEN_MSK BIT(CMU_CLKENR_HRC1MEN_POS) + +#define CMU_CLKENR_PLL2EN_POS 9U +#define CMU_CLKENR_PLL2EN_MSK BIT(CMU_CLKENR_PLL2EN_POS) + +#define CMU_CLKENR_PLL1EN_POS 8U +#define CMU_CLKENR_PLL1EN_MSK BIT(CMU_CLKENR_PLL1EN_POS) + +#define CMU_CLKENR_ULRCEN_POS 4U +#define CMU_CLKENR_ULRCEN_MSK BIT(CMU_CLKENR_ULRCEN_POS) + +#define CMU_CLKENR_LRCEN_POS 3U +#define CMU_CLKENR_LRCEN_MSK BIT(CMU_CLKENR_LRCEN_POS) + +#define CMU_CLKENR_HRCEN_POS 2U +#define CMU_CLKENR_HRCEN_MSK BIT(CMU_CLKENR_HRCEN_POS) + +#define CMU_CLKENR_LOSCEN_POS 1U +#define CMU_CLKENR_LOSCEN_MSK BIT(CMU_CLKENR_LOSCEN_POS) + +#define CMU_CLKENR_HOSCEN_POS 0U +#define CMU_CLKENR_HOSCEN_MSK BIT(CMU_CLKENR_HOSCEN_POS) + +/****************** Bit definition for CMU_CLKSR register ************************/ + +#define CMU_CLKSR_PLL2RDY_POS 25U +#define CMU_CLKSR_PLL2RDY_MSK BIT(CMU_CLKSR_PLL2RDY_POS) + +#define CMU_CLKSR_PLL1RDY_POS 24U +#define CMU_CLKSR_PLL1RDY_MSK BIT(CMU_CLKSR_PLL1RDY_POS) + +#define CMU_CLKSR_LRCRDY_POS 19U +#define CMU_CLKSR_LRCRDY_MSK BIT(CMU_CLKSR_LRCRDY_POS) + +#define CMU_CLKSR_HRCRDY_POS 18U +#define CMU_CLKSR_HRCRDY_MSK BIT(CMU_CLKSR_HRCRDY_POS) + +#define CMU_CLKSR_LOSCRDY_POS 17U +#define CMU_CLKSR_LOSCRDY_MSK BIT(CMU_CLKSR_LOSCRDY_POS) + +#define CMU_CLKSR_HOSCRDY_POS 16U +#define CMU_CLKSR_HOSCRDY_MSK BIT(CMU_CLKSR_HOSCRDY_POS) + +#define CMU_CLKSR_PLL2ACT_POS 9U +#define CMU_CLKSR_PLL2ACT_MSK BIT(CMU_CLKSR_PLL2ACT_POS) + +#define CMU_CLKSR_PLL1ACT_POS 8U +#define CMU_CLKSR_PLL1ACT_MSK BIT(CMU_CLKSR_PLL1ACT_POS) + +#define CMU_CLKSR_ULRCACT_POS 4U +#define CMU_CLKSR_ULRCACT_MSK BIT(CMU_CLKSR_ULRCACT_POS) + +#define CMU_CLKSR_LRCACT_POS 3U +#define CMU_CLKSR_LRCACT_MSK BIT(CMU_CLKSR_LRCACT_POS) + +#define CMU_CLKSR_HRCACT_POS 2U +#define CMU_CLKSR_HRCACT_MSK BIT(CMU_CLKSR_HRCACT_POS) + +#define CMU_CLKSR_LOSCACT_POS 1U +#define CMU_CLKSR_LOSCACT_MSK BIT(CMU_CLKSR_LOSCACT_POS) + +#define CMU_CLKSR_HOSCACT_POS 0U +#define CMU_CLKSR_HOSCACT_MSK BIT(CMU_CLKSR_HOSCACT_POS) + +/****************** Bit definition for CMU_PLLCFG register ************************/ + +#define CMU_PLLCFG_PLL2LCKN_POS 17U +#define CMU_PLLCFG_PLL2LCKN_MSK BIT(CMU_PLLCFG_PLL2LCKN_POS) + +#define CMU_PLLCFG_PLL1LCKN_POS 16U +#define CMU_PLLCFG_PLL1LCKN_MSK BIT(CMU_PLLCFG_PLL1LCKN_POS) + +#define CMU_PLLCFG_PLL2RFS_POSS 8U +#define CMU_PLLCFG_PLL2RFS_POSE 9U +#define CMU_PLLCFG_PLL2RFS_MSK BITS(CMU_PLLCFG_PLL2RFS_POSS,CMU_PLLCFG_PLL2RFS_POSE) + +#define CMU_PLLCFG_PLL1OS_POSS 4U +#define CMU_PLLCFG_PLL1OS_POSE 5U +#define CMU_PLLCFG_PLL1OS_MSK BITS(CMU_PLLCFG_PLL1OS_POSS,CMU_PLLCFG_PLL1OS_POSE) + +#define CMU_PLLCFG_PLL1RFS_POSS 0U +#define CMU_PLLCFG_PLL1RFS_POSE 2U +#define CMU_PLLCFG_PLL1RFS_MSK BITS(CMU_PLLCFG_PLL1RFS_POSS,CMU_PLLCFG_PLL1RFS_POSE) + +/****************** Bit definition for CMU_HOSCCFG register ************************/ + +#define CMU_HOSCCFG_FREQ_POSS 0U +#define CMU_HOSCCFG_FREQ_POSE 4U +#define CMU_HOSCCFG_FREQ_MSK BITS(CMU_HOSCCFG_FREQ_POSS,CMU_HOSCCFG_FREQ_POSE) + +/****************** Bit definition for CMU_HOSMCR register ************************/ + +#define CMU_HOSMCR_NMIE_POS 20U +#define CMU_HOSMCR_NMIE_MSK BIT(CMU_HOSMCR_NMIE_POS) + +#define CMU_HOSMCR_STPIF_POS 19U +#define CMU_HOSMCR_STPIF_MSK BIT(CMU_HOSMCR_STPIF_POS) + +#define CMU_HOSMCR_STRIF_POS 18U +#define CMU_HOSMCR_STRIF_MSK BIT(CMU_HOSMCR_STRIF_POS) + +#define CMU_HOSMCR_STPIE_POS 17U +#define CMU_HOSMCR_STPIE_MSK BIT(CMU_HOSMCR_STPIE_POS) + +#define CMU_HOSMCR_STRIE_POS 16U +#define CMU_HOSMCR_STRIE_MSK BIT(CMU_HOSMCR_STRIE_POS) + +#define CMU_HOSMCR_FRQS_POSS 8U +#define CMU_HOSMCR_FRQS_POSE 10U +#define CMU_HOSMCR_FRQS_MSK BITS(CMU_HOSMCR_FRQS_POSS,CMU_HOSMCR_FRQS_POSE) + +#define CMU_HOSMCR_CLKS_POS 1U +#define CMU_HOSMCR_CLKS_MSK BIT(CMU_HOSMCR_CLKS_POS) + +#define CMU_HOSMCR_EN_POS 0U +#define CMU_HOSMCR_EN_MSK BIT(CMU_HOSMCR_EN_POS) + +/****************** Bit definition for CMU_LOSMCR register ************************/ + +#define CMU_LOSMCR_NMIE_POS 20U +#define CMU_LOSMCR_NMIE_MSK BIT(CMU_LOSMCR_NMIE_POS) + +#define CMU_LOSMCR_STPIF_POS 19U +#define CMU_LOSMCR_STPIF_MSK BIT(CMU_LOSMCR_STPIF_POS) + +#define CMU_LOSMCR_STRIF_POS 18U +#define CMU_LOSMCR_STRIF_MSK BIT(CMU_LOSMCR_STRIF_POS) + +#define CMU_LOSMCR_STPIE_POS 17U +#define CMU_LOSMCR_STPIE_MSK BIT(CMU_LOSMCR_STPIE_POS) + +#define CMU_LOSMCR_STRIE_POS 16U +#define CMU_LOSMCR_STRIE_MSK BIT(CMU_LOSMCR_STRIE_POS) + +#define CMU_LOSMCR_CLKS_POS 1U +#define CMU_LOSMCR_CLKS_MSK BIT(CMU_LOSMCR_CLKS_POS) + +#define CMU_LOSMCR_EN_POS 0U +#define CMU_LOSMCR_EN_MSK BIT(CMU_LOSMCR_EN_POS) + +/****************** Bit definition for CMU_PULMCR register ************************/ + +#define CMU_PULMCR_NMIE_POS 20U +#define CMU_PULMCR_NMIE_MSK BIT(CMU_PULMCR_NMIE_POS) + +#define CMU_PULMCR_ULKIF_POS 19U +#define CMU_PULMCR_ULKIF_MSK BIT(CMU_PULMCR_ULKIF_POS) + +#define CMU_PULMCR_LCKIF_POS 18U +#define CMU_PULMCR_LCKIF_MSK BIT(CMU_PULMCR_LCKIF_POS) + +#define CMU_PULMCR_ULKIE_POS 17U +#define CMU_PULMCR_ULKIE_MSK BIT(CMU_PULMCR_ULKIE_POS) + +#define CMU_PULMCR_LCKIE_POS 16U +#define CMU_PULMCR_LCKIE_MSK BIT(CMU_PULMCR_LCKIE_POS) + +#define CMU_PULMCR_MODE_POSS 8U +#define CMU_PULMCR_MODE_POSE 9U +#define CMU_PULMCR_MODE_MSK BITS(CMU_PULMCR_MODE_POSS,CMU_PULMCR_MODE_POSE) + +#define CMU_PULMCR_CLKS_POS 1U +#define CMU_PULMCR_CLKS_MSK BIT(CMU_PULMCR_CLKS_POS) + +#define CMU_PULMCR_EN_POS 0U +#define CMU_PULMCR_EN_MSK BIT(CMU_PULMCR_EN_POS) + +/****************** Bit definition for CMU_CLKOCR register ************************/ + +#define CMU_CLKOCR_LSCOS_POSS 24U +#define CMU_CLKOCR_LSCOS_POSE 26U +#define CMU_CLKOCR_LSCOS_MSK BITS(CMU_CLKOCR_LSCOS_POSS,CMU_CLKOCR_LSCOS_POSE) + +#define CMU_CLKOCR_LSCOEN_POS 16U +#define CMU_CLKOCR_LSCOEN_MSK BIT(CMU_CLKOCR_LSCOEN_POS) + +#define CMU_CLKOCR_HSCODIV_POSS 12U +#define CMU_CLKOCR_HSCODIV_POSE 14U +#define CMU_CLKOCR_HSCODIV_MSK BITS(CMU_CLKOCR_HSCODIV_POSS,CMU_CLKOCR_HSCODIV_POSE) + +#define CMU_CLKOCR_HSCOS_POSS 8U +#define CMU_CLKOCR_HSCOS_POSE 10U +#define CMU_CLKOCR_HSCOS_MSK BITS(CMU_CLKOCR_HSCOS_POSS,CMU_CLKOCR_HSCOS_POSE) + +#define CMU_CLKOCR_HSCOEN_POS 0U +#define CMU_CLKOCR_HSCOEN_MSK BIT(CMU_CLKOCR_HSCOEN_POS) + +/****************** Bit definition for CMU_BUZZCR register ************************/ + +#define CMU_BUZZCR_DAT_POSS 16U +#define CMU_BUZZCR_DAT_POSE 31U +#define CMU_BUZZCR_DAT_MSK BITS(CMU_BUZZCR_DAT_POSS,CMU_BUZZCR_DAT_POSE) + +#define CMU_BUZZCR_DIV_POSS 8U +#define CMU_BUZZCR_DIV_POSE 10U +#define CMU_BUZZCR_DIV_MSK BITS(CMU_BUZZCR_DIV_POSS,CMU_BUZZCR_DIV_POSE) + +#define CMU_BUZZCR_EN_POS 0U +#define CMU_BUZZCR_EN_MSK BIT(CMU_BUZZCR_EN_POS) + +/****************** Bit definition for CMU_AHB1ENR register ************************/ + +#define CMU_AHB1ENR_ECCEN_POS 11U +#define CMU_AHB1ENR_ECCEN_MSK BIT(CMU_AHB1ENR_ECCEN_POS) + +#define CMU_AHB1ENR_USBEN_POS 10U +#define CMU_AHB1ENR_USBEN_MSK BIT(CMU_AHB1ENR_USBEN_POS) + +#define CMU_AHB1ENR_DMAEN_POS 8U +#define CMU_AHB1ENR_DMAEN_MSK BIT(CMU_AHB1ENR_DMAEN_POS) + +#define CMU_AHB1ENR_QSPIEN_POS 7U +#define CMU_AHB1ENR_QSPIEN_MSK BIT(CMU_AHB1ENR_QSPIEN_POS) + +#define CMU_AHB1ENR_EBIEN_POS 6U +#define CMU_AHB1ENR_EBIEN_MSK BIT(CMU_AHB1ENR_EBIEN_POS) + +#define CMU_AHB1ENR_PISEN_POS 5U +#define CMU_AHB1ENR_PISEN_MSK BIT(CMU_AHB1ENR_PISEN_POS) + +#define CMU_AHB1ENR_TRNGEN_POS 4U +#define CMU_AHB1ENR_TRNGEN_MSK BIT(CMU_AHB1ENR_TRNGEN_POS) + +#define CMU_AHB1ENR_CRYPTEN_POS 3U +#define CMU_AHB1ENR_CRYPTEN_MSK BIT(CMU_AHB1ENR_CRYPTEN_POS) + +#define CMU_AHB1ENR_CALCEN_POS 2U +#define CMU_AHB1ENR_CALCEN_MSK BIT(CMU_AHB1ENR_CALCEN_POS) + +#define CMU_AHB1ENR_CRCEN_POS 1U +#define CMU_AHB1ENR_CRCEN_MSK BIT(CMU_AHB1ENR_CRCEN_POS) + +#define CMU_AHB1ENR_GPIOEN_POS 0U +#define CMU_AHB1ENR_GPIOEN_MSK BIT(CMU_AHB1ENR_GPIOEN_POS) + +/****************** Bit definition for CMU_APB1ENR register ************************/ + +#define CMU_APB1ENR_QSPIEN_POS 25U +#define CMU_APB1ENR_QSPIEN_MSK BIT(CMU_APB1ENR_QSPIEN_POS) + +#define CMU_APB1ENR_CAN0EN_POS 24U +#define CMU_APB1ENR_CAN0EN_MSK BIT(CMU_APB1ENR_CAN0EN_POS) + +#define CMU_APB1ENR_I2C1EN_POS 21U +#define CMU_APB1ENR_I2C1EN_MSK BIT(CMU_APB1ENR_I2C1EN_POS) + +#define CMU_APB1ENR_I2C0EN_POS 20U +#define CMU_APB1ENR_I2C0EN_MSK BIT(CMU_APB1ENR_I2C0EN_POS) + +#define CMU_APB1ENR_SPI2EN_POS 18U +#define CMU_APB1ENR_SPI2EN_MSK BIT(CMU_APB1ENR_SPI2EN_POS) + +#define CMU_APB1ENR_SPI1EN_POS 17U +#define CMU_APB1ENR_SPI1EN_MSK BIT(CMU_APB1ENR_SPI1EN_POS) + +#define CMU_APB1ENR_SPI0EN_POS 16U +#define CMU_APB1ENR_SPI0EN_MSK BIT(CMU_APB1ENR_SPI0EN_POS) + +#define CMU_APB1ENR_UART5EN_POS 13U +#define CMU_APB1ENR_UART5EN_MSK BIT(CMU_APB1ENR_UART5EN_POS) + +#define CMU_APB1ENR_UART4EN_POS 12U +#define CMU_APB1ENR_UART4EN_MSK BIT(CMU_APB1ENR_UART4EN_POS) + +#define CMU_APB1ENR_UART3EN_POS 11U +#define CMU_APB1ENR_UART3EN_MSK BIT(CMU_APB1ENR_UART3EN_POS) + +#define CMU_APB1ENR_UART2EN_POS 10U +#define CMU_APB1ENR_UART2EN_MSK BIT(CMU_APB1ENR_UART2EN_POS) + +#define CMU_APB1ENR_UART1EN_POS 9U +#define CMU_APB1ENR_UART1EN_MSK BIT(CMU_APB1ENR_UART1EN_POS) + +#define CMU_APB1ENR_UART0EN_POS 8U +#define CMU_APB1ENR_UART0EN_MSK BIT(CMU_APB1ENR_UART0EN_POS) + +#define CMU_APB1ENR_TIM7EN_POS 7U +#define CMU_APB1ENR_TIM7EN_MSK BIT(CMU_APB1ENR_TIM7EN_POS) + +#define CMU_APB1ENR_TIM6EN_POS 6U +#define CMU_APB1ENR_TIM6EN_MSK BIT(CMU_APB1ENR_TIM6EN_POS) + +#define CMU_APB1ENR_TIM5EN_POS 5U +#define CMU_APB1ENR_TIM5EN_MSK BIT(CMU_APB1ENR_TIM5EN_POS) + +#define CMU_APB1ENR_TIM4EN_POS 4U +#define CMU_APB1ENR_TIM4EN_MSK BIT(CMU_APB1ENR_TIM4EN_POS) + +#define CMU_APB1ENR_TIM3EN_POS 3U +#define CMU_APB1ENR_TIM3EN_MSK BIT(CMU_APB1ENR_TIM3EN_POS) + +#define CMU_APB1ENR_TIM2EN_POS 2U +#define CMU_APB1ENR_TIM2EN_MSK BIT(CMU_APB1ENR_TIM2EN_POS) + +#define CMU_APB1ENR_TIM1EN_POS 1U +#define CMU_APB1ENR_TIM1EN_MSK BIT(CMU_APB1ENR_TIM1EN_POS) + +#define CMU_APB1ENR_TIM0EN_POS 0U +#define CMU_APB1ENR_TIM0EN_MSK BIT(CMU_APB1ENR_TIM0EN_POS) + +/****************** Bit definition for CMU_APB2ENR register ************************/ + +#define CMU_APB2ENR_DBGCEN_POS 19U +#define CMU_APB2ENR_DBGCEN_MSK BIT(CMU_APB2ENR_DBGCEN_POS) + +#define CMU_APB2ENR_BKPCEN_POS 17U +#define CMU_APB2ENR_BKPCEN_MSK BIT(CMU_APB2ENR_BKPCEN_POS) + +#define CMU_APB2ENR_TSENSEEN_POS 16U +#define CMU_APB2ENR_TSENSEEN_MSK BIT(CMU_APB2ENR_TSENSEEN_POS) + +#define CMU_APB2ENR_RTCEN_POS 15U +#define CMU_APB2ENR_RTCEN_MSK BIT(CMU_APB2ENR_RTCEN_POS) + +#define CMU_APB2ENR_IWDTEN_POS 14U +#define CMU_APB2ENR_IWDTEN_MSK BIT(CMU_APB2ENR_IWDTEN_POS) + +#define CMU_APB2ENR_LCDEN_POS 13U +#define CMU_APB2ENR_LCDEN_MSK BIT(CMU_APB2ENR_LCDEN_POS) + +#define CMU_APB2ENR_WWDTEN_POS 12U +#define CMU_APB2ENR_WWDTEN_MSK BIT(CMU_APB2ENR_WWDTEN_POS) + +#define CMU_APB2ENR_ACMP2EN_POS 11U +#define CMU_APB2ENR_ACMP2EN_MSK BIT(CMU_APB2ENR_ACMP2EN_POS) + +#define CMU_APB2ENR_DAC0EN_POS 9U +#define CMU_APB2ENR_DAC0EN_MSK BIT(CMU_APB2ENR_DAC0EN_POS) + +#define CMU_APB2ENR_OPAMPEN_POS 8U +#define CMU_APB2ENR_OPAMPEN_MSK BIT(CMU_APB2ENR_OPAMPEN_POS) + +#define CMU_APB2ENR_ACMP1EN_POS 7U +#define CMU_APB2ENR_ACMP1EN_MSK BIT(CMU_APB2ENR_ACMP1EN_POS) + +#define CMU_APB2ENR_ACMP0EN_POS 6U +#define CMU_APB2ENR_ACMP0EN_MSK BIT(CMU_APB2ENR_ACMP0EN_POS) + +#define CMU_APB2ENR_ADC1EN_POS 5U +#define CMU_APB2ENR_ADC1EN_MSK BIT(CMU_APB2ENR_ADC1EN_POS) + +#define CMU_APB2ENR_ADC0EN_POS 4U +#define CMU_APB2ENR_ADC0EN_MSK BIT(CMU_APB2ENR_ADC0EN_POS) + +#define CMU_APB2ENR_LPUART0EN_POS 2U +#define CMU_APB2ENR_LPUART0EN_MSK BIT(CMU_APB2ENR_LPUART0EN_POS) + +#define CMU_APB2ENR_LPTIM0EN_POS 0U +#define CMU_APB2ENR_LPTIM0EN_MSK BIT(CMU_APB2ENR_LPTIM0EN_POS) + +/****************** Bit definition for CMU_LPENR register ************************/ + +#define CMU_LPENR_STOP1CS_POSS 16U +#define CMU_LPENR_STOP1CS_POSE 18U +#define CMU_LPENR_STOP1CS_MSK BITS(CMU_LPENR_STOP1CS_POSS,CMU_LPENR_STOP1CS_POSE) + +#define CMU_LPENR_HOSCEN_POS 3U +#define CMU_LPENR_HOSCEN_MSK BIT(CMU_LPENR_HOSCEN_POS) + +#define CMU_LPENR_HRCEN_POS 2U +#define CMU_LPENR_HRCEN_MSK BIT(CMU_LPENR_HRCEN_POS) + +#define CMU_LPENR_LOSCEN_POS 1U +#define CMU_LPENR_LOSCEN_MSK BIT(CMU_LPENR_LOSCEN_POS) + +#define CMU_LPENR_LRCEN_POS 0U +#define CMU_LPENR_LRCEN_MSK BIT(CMU_LPENR_LRCEN_POS) + +/****************** Bit definition for CMU_PERICR register ************************/ + +#define CMU_PERICR_USBPHYCS_POSS 28U +#define CMU_PERICR_USBPHYCS_POSE 30U +#define CMU_PERICR_USBPHYCS_MSK BITS(CMU_PERICR_USBPHYCS_POSS,CMU_PERICR_USBPHYCS_POSE) + +#define CMU_PERICR_QSPICS_POSS 24U +#define CMU_PERICR_QSPICS_POSE 26U +#define CMU_PERICR_QSPICS_MSK BITS(CMU_PERICR_QSPICS_POSS,CMU_PERICR_QSPICS_POSE) + +#define CMU_PERICR_LCD_POSS 16U +#define CMU_PERICR_LCD_POSE 18U +#define CMU_PERICR_LCD_MSK BITS(CMU_PERICR_LCD_POSS,CMU_PERICR_LCD_POSE) + +#define CMU_PERICR_LPUART0_POSS 8U +#define CMU_PERICR_LPUART0_POSE 11U +#define CMU_PERICR_LPUART0_MSK BITS(CMU_PERICR_LPUART0_POSS,CMU_PERICR_LPUART0_POSE) + +#define CMU_PERICR_LPTIM0_POSS 0U +#define CMU_PERICR_LPTIM0_POSE 3U +#define CMU_PERICR_LPTIM0_MSK BITS(CMU_PERICR_LPTIM0_POSS,CMU_PERICR_LPTIM0_POSE) + +/****************** Bit definition for CMU_PERIDIVR register ************************/ + +#define CMU_PERIDIVR_USBPHYDIV_POSS 28U +#define CMU_PERIDIVR_USBPHYDIV_POSE 31U +#define CMU_PERIDIVR_USBPHYDIV_MSK BITS(CMU_PERIDIVR_USBPHYDIV_POSS,CMU_PERIDIVR_USBPHYDIV_POSE) + +typedef struct +{ + __O uint32_t CSR; + __IO uint32_t CFGR; + uint32_t RESERVED0[2] ; + __IO uint32_t CLKENR; + __I uint32_t CLKSR; + __IO uint32_t PLLCFG; + __IO uint32_t HOSCCFG; + __IO uint32_t HOSMCR; + __IO uint32_t LOSMCR; + __IO uint32_t PULMCR; + uint32_t RESERVED1 ; + __IO uint32_t CLKOCR; + __IO uint32_t BUZZCR; + uint32_t RESERVED2[2] ; + __IO uint32_t AHB1ENR; + uint32_t RESERVED3[3] ; + __IO uint32_t APB1ENR; + __IO uint32_t APB2ENR; + uint32_t RESERVED4[2] ; + __IO uint32_t LPENR; + uint32_t RESERVED5[7] ; + __IO uint32_t PERICR; + uint32_t RESERVED6 ; + __IO uint32_t PERIDIVR; +} CMU_TypeDef; + +/****************** Bit definition for DMA_STATUS register ************************/ + +#define DMA_STATUS_STATUS_POSS 4U +#define DMA_STATUS_STATUS_POSE 7U +#define DMA_STATUS_STATUS_MSK BITS(DMA_STATUS_STATUS_POSS,DMA_STATUS_STATUS_POSE) + +#define DMA_STATUS_MASTER_ENABLE_POS 0U +#define DMA_STATUS_MASTER_ENABLE_MSK BIT(DMA_STATUS_MASTER_ENABLE_POS) + +/****************** Bit definition for DMA_CFG register ************************/ + +#define DMA_CFG_CHNL_PROT_CTRL_POSS 5U +#define DMA_CFG_CHNL_PROT_CTRL_POSE 7U +#define DMA_CFG_CHNL_PROT_CTRL_MSK BITS(DMA_CFG_CHNL_PROT_CTRL_POSS,DMA_CFG_CHNL_PROT_CTRL_POSE) + +#define DMA_CFG_MASTER_ENABLE_POS 0U +#define DMA_CFG_MASTER_ENABLE_MSK BIT(DMA_CFG_MASTER_ENABLE_POS) + +/****************** Bit definition for DMA_CTRLBASE register ************************/ + +#define DMA_CTRLBASE_CTRL_BASE_PTR_POSS 9U +#define DMA_CTRLBASE_CTRL_BASE_PTR_POSE 31U +#define DMA_CTRLBASE_CTRL_BASE_PTR_MSK BITS(DMA_CTRLBASE_CTRL_BASE_PTR_POSS,DMA_CTRLBASE_CTRL_BASE_PTR_POSE) + +/****************** Bit definition for DMA_ALTCTRLBASE register ************************/ + +#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSS 0U +#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSE 31U +#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_MSK BITS(DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSS,DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSE) + +/****************** Bit definition for DMA_CHWAITSTATUS register ************************/ + +#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS 0U +#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE 31U +#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_MSK BITS(DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS,DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE) + +/****************** Bit definition for DMA_CHSWREQ register ************************/ + +#define DMA_CHSWREQ_CHSWREQ_POSS 0U +#define DMA_CHSWREQ_CHSWREQ_POSE 31U +#define DMA_CHSWREQ_CHSWREQ_MSK BITS(DMA_CHSWREQ_CHSWREQ_POSS,DMA_CHSWREQ_CHSWREQ_POSE) + +/****************** Bit definition for DMA_CHUSEBURSTSET register ************************/ + +#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS 0U +#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE 31U +#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_MSK BITS(DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS,DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE) + +/****************** Bit definition for DMA_CHUSEBURSTCLR register ************************/ + +#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS 0U +#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE 31U +#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_MSK BITS(DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS,DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE) + +/****************** Bit definition for DMA_CHREQMASKSET register ************************/ + +#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS 0U +#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE 31U +#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_MSK BITS(DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS,DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE) + +/****************** Bit definition for DMA_CHREQMASKCLR register ************************/ + +#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS 0U +#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE 31U +#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_MSK BITS(DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS,DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE) + +/****************** Bit definition for DMA_CHENSET register ************************/ + +#define DMA_CHENSET_CHNL_ENABLE_SET_POSS 0U +#define DMA_CHENSET_CHNL_ENABLE_SET_POSE 31U +#define DMA_CHENSET_CHNL_ENABLE_SET_MSK BITS(DMA_CHENSET_CHNL_ENABLE_SET_POSS,DMA_CHENSET_CHNL_ENABLE_SET_POSE) + +/****************** Bit definition for DMA_CHENCLR register ************************/ + +#define DMA_CHENCLR_CHNL_ENABLE_CLR_POSS 0U +#define DMA_CHENCLR_CHNL_ENABLE_CLR_POSE 31U +#define DMA_CHENCLR_CHNL_ENABLE_CLR_MSK BITS(DMA_CHENCLR_CHNL_ENABLE_CLR_POSS,DMA_CHENCLR_CHNL_ENABLE_CLR_POSE) + +/****************** Bit definition for DMA_CHPRIALTSET register ************************/ + +#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS 0U +#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE 31U +#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_MSK BITS(DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS,DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE) + +/****************** Bit definition for DMA_CHPRIALTCLR register ************************/ + +#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS 0U +#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE 31U +#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_MSK BITS(DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS,DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE) + +/****************** Bit definition for DMA_CHPRSET register ************************/ + +#define DMA_CHPRSET_CHNL_PRIORITY_SET_POSS 0U +#define DMA_CHPRSET_CHNL_PRIORITY_SET_POSE 31U +#define DMA_CHPRSET_CHNL_PRIORITY_SET_MSK BITS(DMA_CHPRSET_CHNL_PRIORITY_SET_POSS,DMA_CHPRSET_CHNL_PRIORITY_SET_POSE) + +/****************** Bit definition for DMA_CHPRCLR register ************************/ + +#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS 0U +#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE 31U +#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_MSK BITS(DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS,DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE) + +/****************** Bit definition for DMA_ERRCLR register ************************/ + +#define DMA_ERRCLR_ERR_CLR_POS 0U +#define DMA_ERRCLR_ERR_CLR_MSK BIT(DMA_ERRCLR_ERR_CLR_POS) + +/****************** Bit definition for DMA_IFLAG register ************************/ + +#define DMA_IFLAG_DMAERRIF_POS 31U +#define DMA_IFLAG_DMAERRIF_MSK BIT(DMA_IFLAG_DMAERRIF_POS) + +#define DMA_IFLAG_CH11DONEIF_POS 11U +#define DMA_IFLAG_CH11DONEIF_MSK BIT(DMA_IFLAG_CH11DONEIF_POS) + +#define DMA_IFLAG_CH10DONEIF_POS 10U +#define DMA_IFLAG_CH10DONEIF_MSK BIT(DMA_IFLAG_CH10DONEIF_POS) + +#define DMA_IFLAG_CH9DONEIF_POS 9U +#define DMA_IFLAG_CH9DONEIF_MSK BIT(DMA_IFLAG_CH9DONEIF_POS) + +#define DMA_IFLAG_CH8DONEIF_POS 8U +#define DMA_IFLAG_CH8DONEIF_MSK BIT(DMA_IFLAG_CH8DONEIF_POS) + +#define DMA_IFLAG_CH7DONEIF_POS 7U +#define DMA_IFLAG_CH7DONEIF_MSK BIT(DMA_IFLAG_CH7DONEIF_POS) + +#define DMA_IFLAG_CH6DONEIF_POS 6U +#define DMA_IFLAG_CH6DONEIF_MSK BIT(DMA_IFLAG_CH6DONEIF_POS) + +#define DMA_IFLAG_CH5DONEIF_POS 5U +#define DMA_IFLAG_CH5DONEIF_MSK BIT(DMA_IFLAG_CH5DONEIF_POS) + +#define DMA_IFLAG_CH4DONEIF_POS 4U +#define DMA_IFLAG_CH4DONEIF_MSK BIT(DMA_IFLAG_CH4DONEIF_POS) + +#define DMA_IFLAG_CH3DONEIF_POS 3U +#define DMA_IFLAG_CH3DONEIF_MSK BIT(DMA_IFLAG_CH3DONEIF_POS) + +#define DMA_IFLAG_CH2DONEIF_POS 2U +#define DMA_IFLAG_CH2DONEIF_MSK BIT(DMA_IFLAG_CH2DONEIF_POS) + +#define DMA_IFLAG_CH1DONEIF_POS 1U +#define DMA_IFLAG_CH1DONEIF_MSK BIT(DMA_IFLAG_CH1DONEIF_POS) + +#define DMA_IFLAG_CH0DONEIF_POS 0U +#define DMA_IFLAG_CH0DONEIF_MSK BIT(DMA_IFLAG_CH0DONEIF_POS) + +/****************** Bit definition for DMA_ICFR register ************************/ + +#define DMA_ICFR_DMAERRC_POS 31U +#define DMA_ICFR_DMAERRC_MSK BIT(DMA_ICFR_DMAERRC_POS) + +#define DMA_ICFR_CH11DONEC_POS 11U +#define DMA_ICFR_CH11DONEC_MSK BIT(DMA_ICFR_CH11DONEC_POS) + +#define DMA_ICFR_CH10DONEC_POS 10U +#define DMA_ICFR_CH10DONEC_MSK BIT(DMA_ICFR_CH10DONEC_POS) + +#define DMA_ICFR_CH9DONEC_POS 9U +#define DMA_ICFR_CH9DONEC_MSK BIT(DMA_ICFR_CH9DONEC_POS) + +#define DMA_ICFR_CH8DONEC_POS 8U +#define DMA_ICFR_CH8DONEC_MSK BIT(DMA_ICFR_CH8DONEC_POS) + +#define DMA_ICFR_CH7DONEC_POS 7U +#define DMA_ICFR_CH7DONEC_MSK BIT(DMA_ICFR_CH7DONEC_POS) + +#define DMA_ICFR_CH6DONEC_POS 6U +#define DMA_ICFR_CH6DONEC_MSK BIT(DMA_ICFR_CH6DONEC_POS) + +#define DMA_ICFR_CH5DONEC_POS 5U +#define DMA_ICFR_CH5DONEC_MSK BIT(DMA_ICFR_CH5DONEC_POS) + +#define DMA_ICFR_CH4DONEC_POS 4U +#define DMA_ICFR_CH4DONEC_MSK BIT(DMA_ICFR_CH4DONEC_POS) + +#define DMA_ICFR_CH3DONEC_POS 3U +#define DMA_ICFR_CH3DONEC_MSK BIT(DMA_ICFR_CH3DONEC_POS) + +#define DMA_ICFR_CH2DONEC_POS 2U +#define DMA_ICFR_CH2DONEC_MSK BIT(DMA_ICFR_CH2DONEC_POS) + +#define DMA_ICFR_CH1DONEC_POS 1U +#define DMA_ICFR_CH1DONEC_MSK BIT(DMA_ICFR_CH1DONEC_POS) + +#define DMA_ICFR_CH0DONEC_POS 0U +#define DMA_ICFR_CH0DONEC_MSK BIT(DMA_ICFR_CH0DONEC_POS) + +/****************** Bit definition for DMA_IER register ************************/ + +#define DMA_IER_DMAERRIE_POS 31U +#define DMA_IER_DMAERRIE_MSK BIT(DMA_IER_DMAERRIE_POS) + +#define DMA_IER_CH11DONEIE_POS 11U +#define DMA_IER_CH11DONEIE_MSK BIT(DMA_IER_CH11DONEIE_POS) + +#define DMA_IER_CH10DONEIE_POS 10U +#define DMA_IER_CH10DONEIE_MSK BIT(DMA_IER_CH10DONEIE_POS) + +#define DMA_IER_CH9DONEIE_POS 9U +#define DMA_IER_CH9DONEIE_MSK BIT(DMA_IER_CH9DONEIE_POS) + +#define DMA_IER_CH8DONEIE_POS 8U +#define DMA_IER_CH8DONEIE_MSK BIT(DMA_IER_CH8DONEIE_POS) + +#define DMA_IER_CH7DONEIE_POS 7U +#define DMA_IER_CH7DONEIE_MSK BIT(DMA_IER_CH7DONEIE_POS) + +#define DMA_IER_CH6DONEIE_POS 6U +#define DMA_IER_CH6DONEIE_MSK BIT(DMA_IER_CH6DONEIE_POS) + +#define DMA_IER_CH5DONEIE_POS 5U +#define DMA_IER_CH5DONEIE_MSK BIT(DMA_IER_CH5DONEIE_POS) + +#define DMA_IER_CH4DONEIE_POS 4U +#define DMA_IER_CH4DONEIE_MSK BIT(DMA_IER_CH4DONEIE_POS) + +#define DMA_IER_CH3DONEIE_POS 3U +#define DMA_IER_CH3DONEIE_MSK BIT(DMA_IER_CH3DONEIE_POS) + +#define DMA_IER_CH2DONEIE_POS 2U +#define DMA_IER_CH2DONEIE_MSK BIT(DMA_IER_CH2DONEIE_POS) + +#define DMA_IER_CH1DONEIE_POS 1U +#define DMA_IER_CH1DONEIE_MSK BIT(DMA_IER_CH1DONEIE_POS) + +#define DMA_IER_CH0DONEIE_POS 0U +#define DMA_IER_CH0DONEIE_MSK BIT(DMA_IER_CH0DONEIE_POS) + +/****************** Bit definition for DMA_CH0_SELCON register ************************/ + +#define DMA_CH0_SELCON_MSEL_POSS 8U +#define DMA_CH0_SELCON_MSEL_POSE 13U +#define DMA_CH0_SELCON_MSEL_MSK BITS(DMA_CH0_SELCON_MSEL_POSS,DMA_CH0_SELCON_MSEL_POSE) + +#define DMA_CH0_SELCON_MSIGSEL_POSS 0U +#define DMA_CH0_SELCON_MSIGSEL_POSE 3U +#define DMA_CH0_SELCON_MSIGSEL_MSK BITS(DMA_CH0_SELCON_MSIGSEL_POSS,DMA_CH0_SELCON_MSIGSEL_POSE) + +typedef struct +{ + __I uint32_t STATUS; + __IO uint32_t CFG; + __IO uint32_t CTRLBASE; + __I uint32_t ALTCTRLBASE; + __I uint32_t CHWAITSTATUS; + __IO uint32_t CHSWREQ; + __IO uint32_t CHUSEBURSTSET; + __O uint32_t CHUSEBURSTCLR; + __IO uint32_t CHREQMASKSET; + __O uint32_t CHREQMASKCLR; + __IO uint32_t CHENSET; + __O uint32_t CHENCLR; + __IO uint32_t CHPRIALTSET; + __O uint32_t CHPRIALTCLR; + __IO uint32_t CHPRSET; + __O uint32_t CHPRCLR; + uint32_t RESERVED0[3] ; + __IO uint32_t ERRCLR; + uint32_t RESERVED1[1004] ; + __I uint32_t IFLAG; + uint32_t RESERVED2 ; + __O uint32_t ICFR; + __IO uint32_t IER; + uint32_t RESERVED3[60] ; + __IO uint32_t CH_SELCON[12]; +} DMA_TypeDef; + +/****************** Bit definition for ECC_AREG(x = 1 .. 64) register ************************/ +#define ECC_AREGx_VAL_POSS 0U +#define ECC_AREGx_VAL_POSE 31U +#define ECC_AREGx_VAL_MSK BITS(ECC_AREG1_VAL_POSS,ECC_AREG1_VAL_POSE) + +/****************** Bit definition for ECC_NREG register ************************/ +#define ECC_NREGx_VAL_POSS 0U +#define ECC_NREGx_VAL_POSE 31U +#define ECC_NREGx_VAL_MSK BITS(ECC_AREG1_VAL_POSS,ECC_AREG1_VAL_POSE) + +/****************** Bit definition for ECC_CON register ************************/ + +#define ECC_CON_SINGST_POS 31U +#define ECC_CON_SINGST_MSK BIT(ECC_CON_SINGST_POS) + +#define ECC_CON_COMBST_POS 30U +#define ECC_CON_COMBST_MSK BIT(ECC_CON_COMBST_POS) + +#define ECC_CON_REMAP_POS 29U +#define ECC_CON_REMAP_MSK BIT(ECC_CON_REMAP_POS) + +#define ECC_CON_COMBMD_POSS 27U +#define ECC_CON_COMBMD_POSE 28U +#define ECC_CON_COMBMD_MSK BITS(ECC_CON_COMBMD_POSS,ECC_CON_COMBMD_POSE) + +#define ECC_CON_OPL_POSS 10U +#define ECC_CON_OPL_POSE 12U +#define ECC_CON_OPL_MSK BITS(ECC_CON_OPL_POSS,ECC_CON_OPL_POSE) + +#define ECC_CON_OPR_POSS 7U +#define ECC_CON_OPR_POSE 9U +#define ECC_CON_OPR_MSK BITS(ECC_CON_OPR_POSS,ECC_CON_OPR_POSE) + +#define ECC_CON_RES_POSS 4U +#define ECC_CON_RES_POSE 6U +#define ECC_CON_RES_MSK BITS(ECC_CON_RES_POSS,ECC_CON_RES_POSE) + +#define ECC_CON_MODE_POSS 1U +#define ECC_CON_MODE_POSE 3U +#define ECC_CON_MODE_MSK BITS(ECC_CON_MODE_POSS,ECC_CON_MODE_POSE) + +#define ECC_CON_IE_POS 0U +#define ECC_CON_IE_MSK BIT(ECC_CON_IE_POS) + +/****************** Bit definition for ECC_STAT register ************************/ + +#define ECC_STAT_ERR_POS 2U +#define ECC_STAT_ERR_MSK BIT(ECC_STAT_ERR_POS) + +#define ECC_STAT_DONE_POS 1U +#define ECC_STAT_DONE_MSK BIT(ECC_STAT_DONE_POS) + +#define ECC_STAT_BUSY_POS 0U +#define ECC_STAT_BUSY_MSK BIT(ECC_STAT_BUSY_POS) + +/****************** Bit definition for ECC_PARA register ************************/ + +#define ECC_PARA_VAL_POSS 0U +#define ECC_PARA_VAL_POSE 31U +#define ECC_PARA_VAL_MSK BITS(ECC_PARA_VAL_POSS,ECC_PARA_VAL_POSE) + +typedef struct +{ + __IO uint32_t AREG[64]; + __IO uint32_t NREG[8]; + uint32_t RESERVED0[120]; + __IO uint32_t CON; + __IO uint32_t STAT; + __IO uint32_t PARA; +} ECC_TypeDef; + +/****************** Bit definition for PIS_CH0_CON register ************************/ + +#define PIS_CH0_CON_SYNCSEL_POSS 24U +#define PIS_CH0_CON_SYNCSEL_POSE 26U +#define PIS_CH0_CON_SYNCSEL_MSK BITS(PIS_CH0_CON_SYNCSEL_POSS,PIS_CH0_CON_SYNCSEL_POSE) + +#define PIS_CH0_CON_PULCK_POSS 18U +#define PIS_CH0_CON_PULCK_POSE 19U +#define PIS_CH0_CON_PULCK_MSK BITS(PIS_CH0_CON_PULCK_POSS,PIS_CH0_CON_PULCK_POSE) + +#define PIS_CH0_CON_EDGS_POSS 16U +#define PIS_CH0_CON_EDGS_POSE 17U +#define PIS_CH0_CON_EDGS_MSK BITS(PIS_CH0_CON_EDGS_POSS,PIS_CH0_CON_EDGS_POSE) + +#define PIS_CH0_CON_SRCS_POSS 8U +#define PIS_CH0_CON_SRCS_POSE 13U +#define PIS_CH0_CON_SRCS_MSK BITS(PIS_CH0_CON_SRCS_POSS,PIS_CH0_CON_SRCS_POSE) + +#define PIS_CH0_CON_MSIGS_POSS 0U +#define PIS_CH0_CON_MSIGS_POSE 3U +#define PIS_CH0_CON_MSIGS_MSK BITS(PIS_CH0_CON_MSIGS_POSS,PIS_CH0_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH1_CON register ************************/ + +#define PIS_CH1_CON_SYNCSEL_POSS 24U +#define PIS_CH1_CON_SYNCSEL_POSE 26U +#define PIS_CH1_CON_SYNCSEL_MSK BITS(PIS_CH1_CON_SYNCSEL_POSS,PIS_CH1_CON_SYNCSEL_POSE) + +#define PIS_CH1_CON_PULCK_POSS 18U +#define PIS_CH1_CON_PULCK_POSE 19U +#define PIS_CH1_CON_PULCK_MSK BITS(PIS_CH1_CON_PULCK_POSS,PIS_CH1_CON_PULCK_POSE) + +#define PIS_CH1_CON_EDGS_POSS 16U +#define PIS_CH1_CON_EDGS_POSE 17U +#define PIS_CH1_CON_EDGS_MSK BITS(PIS_CH1_CON_EDGS_POSS,PIS_CH1_CON_EDGS_POSE) + +#define PIS_CH1_CON_SRCS_POSS 8U +#define PIS_CH1_CON_SRCS_POSE 13U +#define PIS_CH1_CON_SRCS_MSK BITS(PIS_CH1_CON_SRCS_POSS,PIS_CH1_CON_SRCS_POSE) + +#define PIS_CH1_CON_MSIGS_POSS 0U +#define PIS_CH1_CON_MSIGS_POSE 3U +#define PIS_CH1_CON_MSIGS_MSK BITS(PIS_CH1_CON_MSIGS_POSS,PIS_CH1_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH2_CON register ************************/ + +#define PIS_CH2_CON_SYNCSEL_POSS 24U +#define PIS_CH2_CON_SYNCSEL_POSE 26U +#define PIS_CH2_CON_SYNCSEL_MSK BITS(PIS_CH2_CON_SYNCSEL_POSS,PIS_CH2_CON_SYNCSEL_POSE) + +#define PIS_CH2_CON_PULCK_POSS 18U +#define PIS_CH2_CON_PULCK_POSE 19U +#define PIS_CH2_CON_PULCK_MSK BITS(PIS_CH2_CON_PULCK_POSS,PIS_CH2_CON_PULCK_POSE) + +#define PIS_CH2_CON_EDGS_POSS 16U +#define PIS_CH2_CON_EDGS_POSE 17U +#define PIS_CH2_CON_EDGS_MSK BITS(PIS_CH2_CON_EDGS_POSS,PIS_CH2_CON_EDGS_POSE) + +#define PIS_CH2_CON_SRCS_POSS 8U +#define PIS_CH2_CON_SRCS_POSE 13U +#define PIS_CH2_CON_SRCS_MSK BITS(PIS_CH2_CON_SRCS_POSS,PIS_CH2_CON_SRCS_POSE) + +#define PIS_CH2_CON_MSIGS_POSS 0U +#define PIS_CH2_CON_MSIGS_POSE 3U +#define PIS_CH2_CON_MSIGS_MSK BITS(PIS_CH2_CON_MSIGS_POSS,PIS_CH2_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH3_CON register ************************/ + +#define PIS_CH3_CON_SYNCSEL_POSS 24U +#define PIS_CH3_CON_SYNCSEL_POSE 26U +#define PIS_CH3_CON_SYNCSEL_MSK BITS(PIS_CH3_CON_SYNCSEL_POSS,PIS_CH3_CON_SYNCSEL_POSE) + +#define PIS_CH3_CON_PULCK_POSS 18U +#define PIS_CH3_CON_PULCK_POSE 19U +#define PIS_CH3_CON_PULCK_MSK BITS(PIS_CH3_CON_PULCK_POSS,PIS_CH3_CON_PULCK_POSE) + +#define PIS_CH3_CON_EDGS_POSS 16U +#define PIS_CH3_CON_EDGS_POSE 17U +#define PIS_CH3_CON_EDGS_MSK BITS(PIS_CH3_CON_EDGS_POSS,PIS_CH3_CON_EDGS_POSE) + +#define PIS_CH3_CON_SRCS_POSS 8U +#define PIS_CH3_CON_SRCS_POSE 13U +#define PIS_CH3_CON_SRCS_MSK BITS(PIS_CH3_CON_SRCS_POSS,PIS_CH3_CON_SRCS_POSE) + +#define PIS_CH3_CON_MSIGS_POSS 0U +#define PIS_CH3_CON_MSIGS_POSE 3U +#define PIS_CH3_CON_MSIGS_MSK BITS(PIS_CH3_CON_MSIGS_POSS,PIS_CH3_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH4_CON register ************************/ + +#define PIS_CH4_CON_SYNCSEL_POSS 24U +#define PIS_CH4_CON_SYNCSEL_POSE 26U +#define PIS_CH4_CON_SYNCSEL_MSK BITS(PIS_CH4_CON_SYNCSEL_POSS,PIS_CH4_CON_SYNCSEL_POSE) + +#define PIS_CH4_CON_PULCK_POSS 18U +#define PIS_CH4_CON_PULCK_POSE 19U +#define PIS_CH4_CON_PULCK_MSK BITS(PIS_CH4_CON_PULCK_POSS,PIS_CH4_CON_PULCK_POSE) + +#define PIS_CH4_CON_EDGS_POSS 16U +#define PIS_CH4_CON_EDGS_POSE 17U +#define PIS_CH4_CON_EDGS_MSK BITS(PIS_CH4_CON_EDGS_POSS,PIS_CH4_CON_EDGS_POSE) + +#define PIS_CH4_CON_SRCS_POSS 8U +#define PIS_CH4_CON_SRCS_POSE 13U +#define PIS_CH4_CON_SRCS_MSK BITS(PIS_CH4_CON_SRCS_POSS,PIS_CH4_CON_SRCS_POSE) + +#define PIS_CH4_CON_MSIGS_POSS 0U +#define PIS_CH4_CON_MSIGS_POSE 3U +#define PIS_CH4_CON_MSIGS_MSK BITS(PIS_CH4_CON_MSIGS_POSS,PIS_CH4_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH5_CON register ************************/ + +#define PIS_CH5_CON_SYNCSEL_POSS 24U +#define PIS_CH5_CON_SYNCSEL_POSE 26U +#define PIS_CH5_CON_SYNCSEL_MSK BITS(PIS_CH5_CON_SYNCSEL_POSS,PIS_CH5_CON_SYNCSEL_POSE) + +#define PIS_CH5_CON_PULCK_POSS 18U +#define PIS_CH5_CON_PULCK_POSE 19U +#define PIS_CH5_CON_PULCK_MSK BITS(PIS_CH5_CON_PULCK_POSS,PIS_CH5_CON_PULCK_POSE) + +#define PIS_CH5_CON_EDGS_POSS 16U +#define PIS_CH5_CON_EDGS_POSE 17U +#define PIS_CH5_CON_EDGS_MSK BITS(PIS_CH5_CON_EDGS_POSS,PIS_CH5_CON_EDGS_POSE) + +#define PIS_CH5_CON_SRCS_POSS 8U +#define PIS_CH5_CON_SRCS_POSE 13U +#define PIS_CH5_CON_SRCS_MSK BITS(PIS_CH5_CON_SRCS_POSS,PIS_CH5_CON_SRCS_POSE) + +#define PIS_CH5_CON_MSIGS_POSS 0U +#define PIS_CH5_CON_MSIGS_POSE 3U +#define PIS_CH5_CON_MSIGS_MSK BITS(PIS_CH5_CON_MSIGS_POSS,PIS_CH5_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH6_CON register ************************/ + +#define PIS_CH6_CON_SYNCSEL_POSS 24U +#define PIS_CH6_CON_SYNCSEL_POSE 26U +#define PIS_CH6_CON_SYNCSEL_MSK BITS(PIS_CH6_CON_SYNCSEL_POSS,PIS_CH6_CON_SYNCSEL_POSE) + +#define PIS_CH6_CON_PULCK_POSS 18U +#define PIS_CH6_CON_PULCK_POSE 19U +#define PIS_CH6_CON_PULCK_MSK BITS(PIS_CH6_CON_PULCK_POSS,PIS_CH6_CON_PULCK_POSE) + +#define PIS_CH6_CON_EDGS_POSS 16U +#define PIS_CH6_CON_EDGS_POSE 17U +#define PIS_CH6_CON_EDGS_MSK BITS(PIS_CH6_CON_EDGS_POSS,PIS_CH6_CON_EDGS_POSE) + +#define PIS_CH6_CON_SRCS_POSS 8U +#define PIS_CH6_CON_SRCS_POSE 13U +#define PIS_CH6_CON_SRCS_MSK BITS(PIS_CH6_CON_SRCS_POSS,PIS_CH6_CON_SRCS_POSE) + +#define PIS_CH6_CON_MSIGS_POSS 0U +#define PIS_CH6_CON_MSIGS_POSE 3U +#define PIS_CH6_CON_MSIGS_MSK BITS(PIS_CH6_CON_MSIGS_POSS,PIS_CH6_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH7_CON register ************************/ + +#define PIS_CH7_CON_SYNCSEL_POSS 24U +#define PIS_CH7_CON_SYNCSEL_POSE 26U +#define PIS_CH7_CON_SYNCSEL_MSK BITS(PIS_CH7_CON_SYNCSEL_POSS,PIS_CH7_CON_SYNCSEL_POSE) + +#define PIS_CH7_CON_PULCK_POSS 18U +#define PIS_CH7_CON_PULCK_POSE 19U +#define PIS_CH7_CON_PULCK_MSK BITS(PIS_CH7_CON_PULCK_POSS,PIS_CH7_CON_PULCK_POSE) + +#define PIS_CH7_CON_EDGS_POSS 16U +#define PIS_CH7_CON_EDGS_POSE 17U +#define PIS_CH7_CON_EDGS_MSK BITS(PIS_CH7_CON_EDGS_POSS,PIS_CH7_CON_EDGS_POSE) + +#define PIS_CH7_CON_SRCS_POSS 8U +#define PIS_CH7_CON_SRCS_POSE 13U +#define PIS_CH7_CON_SRCS_MSK BITS(PIS_CH7_CON_SRCS_POSS,PIS_CH7_CON_SRCS_POSE) + +#define PIS_CH7_CON_MSIGS_POSS 0U +#define PIS_CH7_CON_MSIGS_POSE 3U +#define PIS_CH7_CON_MSIGS_MSK BITS(PIS_CH7_CON_MSIGS_POSS,PIS_CH7_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH8_CON register ************************/ + +#define PIS_CH8_CON_SYNCSEL_POSS 24U +#define PIS_CH8_CON_SYNCSEL_POSE 26U +#define PIS_CH8_CON_SYNCSEL_MSK BITS(PIS_CH8_CON_SYNCSEL_POSS,PIS_CH8_CON_SYNCSEL_POSE) + +#define PIS_CH8_CON_PULCK_POSS 18U +#define PIS_CH8_CON_PULCK_POSE 19U +#define PIS_CH8_CON_PULCK_MSK BITS(PIS_CH8_CON_PULCK_POSS,PIS_CH8_CON_PULCK_POSE) + +#define PIS_CH8_CON_EDGS_POSS 16U +#define PIS_CH8_CON_EDGS_POSE 17U +#define PIS_CH8_CON_EDGS_MSK BITS(PIS_CH8_CON_EDGS_POSS,PIS_CH8_CON_EDGS_POSE) + +#define PIS_CH8_CON_SRCS_POSS 8U +#define PIS_CH8_CON_SRCS_POSE 13U +#define PIS_CH8_CON_SRCS_MSK BITS(PIS_CH8_CON_SRCS_POSS,PIS_CH8_CON_SRCS_POSE) + +#define PIS_CH8_CON_MSIGS_POSS 0U +#define PIS_CH8_CON_MSIGS_POSE 3U +#define PIS_CH8_CON_MSIGS_MSK BITS(PIS_CH8_CON_MSIGS_POSS,PIS_CH8_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH9_CON register ************************/ + +#define PIS_CH9_CON_SYNCSEL_POSS 24U +#define PIS_CH9_CON_SYNCSEL_POSE 26U +#define PIS_CH9_CON_SYNCSEL_MSK BITS(PIS_CH9_CON_SYNCSEL_POSS,PIS_CH9_CON_SYNCSEL_POSE) + +#define PIS_CH9_CON_PULCK_POSS 18U +#define PIS_CH9_CON_PULCK_POSE 19U +#define PIS_CH9_CON_PULCK_MSK BITS(PIS_CH9_CON_PULCK_POSS,PIS_CH9_CON_PULCK_POSE) + +#define PIS_CH9_CON_EDGS_POSS 16U +#define PIS_CH9_CON_EDGS_POSE 17U +#define PIS_CH9_CON_EDGS_MSK BITS(PIS_CH9_CON_EDGS_POSS,PIS_CH9_CON_EDGS_POSE) + +#define PIS_CH9_CON_SRCS_POSS 8U +#define PIS_CH9_CON_SRCS_POSE 13U +#define PIS_CH9_CON_SRCS_MSK BITS(PIS_CH9_CON_SRCS_POSS,PIS_CH9_CON_SRCS_POSE) + +#define PIS_CH9_CON_MSIGS_POSS 0U +#define PIS_CH9_CON_MSIGS_POSE 3U +#define PIS_CH9_CON_MSIGS_MSK BITS(PIS_CH9_CON_MSIGS_POSS,PIS_CH9_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH10_CON register ************************/ + +#define PIS_CH10_CON_SYNCSEL_POSS 24U +#define PIS_CH10_CON_SYNCSEL_POSE 26U +#define PIS_CH10_CON_SYNCSEL_MSK BITS(PIS_CH10_CON_SYNCSEL_POSS,PIS_CH10_CON_SYNCSEL_POSE) + +#define PIS_CH10_CON_PULCK_POSS 18U +#define PIS_CH10_CON_PULCK_POSE 19U +#define PIS_CH10_CON_PULCK_MSK BITS(PIS_CH10_CON_PULCK_POSS,PIS_CH10_CON_PULCK_POSE) + +#define PIS_CH10_CON_EDGS_POSS 16U +#define PIS_CH10_CON_EDGS_POSE 17U +#define PIS_CH10_CON_EDGS_MSK BITS(PIS_CH10_CON_EDGS_POSS,PIS_CH10_CON_EDGS_POSE) + +#define PIS_CH10_CON_SRCS_POSS 8U +#define PIS_CH10_CON_SRCS_POSE 13U +#define PIS_CH10_CON_SRCS_MSK BITS(PIS_CH10_CON_SRCS_POSS,PIS_CH10_CON_SRCS_POSE) + +#define PIS_CH10_CON_MSIGS_POSS 0U +#define PIS_CH10_CON_MSIGS_POSE 3U +#define PIS_CH10_CON_MSIGS_MSK BITS(PIS_CH10_CON_MSIGS_POSS,PIS_CH10_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH11_CON register ************************/ + +#define PIS_CH11_CON_SYNCSEL_POSS 24U +#define PIS_CH11_CON_SYNCSEL_POSE 26U +#define PIS_CH11_CON_SYNCSEL_MSK BITS(PIS_CH11_CON_SYNCSEL_POSS,PIS_CH11_CON_SYNCSEL_POSE) + +#define PIS_CH11_CON_PULCK_POSS 18U +#define PIS_CH11_CON_PULCK_POSE 19U +#define PIS_CH11_CON_PULCK_MSK BITS(PIS_CH11_CON_PULCK_POSS,PIS_CH11_CON_PULCK_POSE) + +#define PIS_CH11_CON_EDGS_POSS 16U +#define PIS_CH11_CON_EDGS_POSE 17U +#define PIS_CH11_CON_EDGS_MSK BITS(PIS_CH11_CON_EDGS_POSS,PIS_CH11_CON_EDGS_POSE) + +#define PIS_CH11_CON_SRCS_POSS 8U +#define PIS_CH11_CON_SRCS_POSE 13U +#define PIS_CH11_CON_SRCS_MSK BITS(PIS_CH11_CON_SRCS_POSS,PIS_CH11_CON_SRCS_POSE) + +#define PIS_CH11_CON_MSIGS_POSS 0U +#define PIS_CH11_CON_MSIGS_POSE 3U +#define PIS_CH11_CON_MSIGS_MSK BITS(PIS_CH11_CON_MSIGS_POSS,PIS_CH11_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH12_CON register ************************/ + +#define PIS_CH12_CON_SYNCSEL_POSS 24U +#define PIS_CH12_CON_SYNCSEL_POSE 26U +#define PIS_CH12_CON_SYNCSEL_MSK BITS(PIS_CH12_CON_SYNCSEL_POSS,PIS_CH12_CON_SYNCSEL_POSE) + +#define PIS_CH12_CON_PULCK_POSS 18U +#define PIS_CH12_CON_PULCK_POSE 19U +#define PIS_CH12_CON_PULCK_MSK BITS(PIS_CH12_CON_PULCK_POSS,PIS_CH12_CON_PULCK_POSE) + +#define PIS_CH12_CON_EDGS_POSS 16U +#define PIS_CH12_CON_EDGS_POSE 17U +#define PIS_CH12_CON_EDGS_MSK BITS(PIS_CH12_CON_EDGS_POSS,PIS_CH12_CON_EDGS_POSE) + +#define PIS_CH12_CON_SRCS_POSS 8U +#define PIS_CH12_CON_SRCS_POSE 13U +#define PIS_CH12_CON_SRCS_MSK BITS(PIS_CH12_CON_SRCS_POSS,PIS_CH12_CON_SRCS_POSE) + +#define PIS_CH12_CON_MSIGS_POSS 0U +#define PIS_CH12_CON_MSIGS_POSE 3U +#define PIS_CH12_CON_MSIGS_MSK BITS(PIS_CH12_CON_MSIGS_POSS,PIS_CH12_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH13_CON register ************************/ + +#define PIS_CH13_CON_SYNCSEL_POSS 24U +#define PIS_CH13_CON_SYNCSEL_POSE 26U +#define PIS_CH13_CON_SYNCSEL_MSK BITS(PIS_CH13_CON_SYNCSEL_POSS,PIS_CH13_CON_SYNCSEL_POSE) + +#define PIS_CH13_CON_PULCK_POSS 18U +#define PIS_CH13_CON_PULCK_POSE 19U +#define PIS_CH13_CON_PULCK_MSK BITS(PIS_CH13_CON_PULCK_POSS,PIS_CH13_CON_PULCK_POSE) + +#define PIS_CH13_CON_EDGS_POSS 16U +#define PIS_CH13_CON_EDGS_POSE 17U +#define PIS_CH13_CON_EDGS_MSK BITS(PIS_CH13_CON_EDGS_POSS,PIS_CH13_CON_EDGS_POSE) + +#define PIS_CH13_CON_SRCS_POSS 8U +#define PIS_CH13_CON_SRCS_POSE 13U +#define PIS_CH13_CON_SRCS_MSK BITS(PIS_CH13_CON_SRCS_POSS,PIS_CH13_CON_SRCS_POSE) + +#define PIS_CH13_CON_MSIGS_POSS 0U +#define PIS_CH13_CON_MSIGS_POSE 3U +#define PIS_CH13_CON_MSIGS_MSK BITS(PIS_CH13_CON_MSIGS_POSS,PIS_CH13_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH14_CON register ************************/ + +#define PIS_CH14_CON_SYNCSEL_POSS 24U +#define PIS_CH14_CON_SYNCSEL_POSE 26U +#define PIS_CH14_CON_SYNCSEL_MSK BITS(PIS_CH14_CON_SYNCSEL_POSS,PIS_CH14_CON_SYNCSEL_POSE) + +#define PIS_CH14_CON_PULCK_POSS 18U +#define PIS_CH14_CON_PULCK_POSE 19U +#define PIS_CH14_CON_PULCK_MSK BITS(PIS_CH14_CON_PULCK_POSS,PIS_CH14_CON_PULCK_POSE) + +#define PIS_CH14_CON_EDGS_POSS 16U +#define PIS_CH14_CON_EDGS_POSE 17U +#define PIS_CH14_CON_EDGS_MSK BITS(PIS_CH14_CON_EDGS_POSS,PIS_CH14_CON_EDGS_POSE) + +#define PIS_CH14_CON_SRCS_POSS 8U +#define PIS_CH14_CON_SRCS_POSE 13U +#define PIS_CH14_CON_SRCS_MSK BITS(PIS_CH14_CON_SRCS_POSS,PIS_CH14_CON_SRCS_POSE) + +#define PIS_CH14_CON_MSIGS_POSS 0U +#define PIS_CH14_CON_MSIGS_POSE 3U +#define PIS_CH14_CON_MSIGS_MSK BITS(PIS_CH14_CON_MSIGS_POSS,PIS_CH14_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH15_CON register ************************/ + +#define PIS_CH15_CON_SYNCSEL_POSS 24U +#define PIS_CH15_CON_SYNCSEL_POSE 26U +#define PIS_CH15_CON_SYNCSEL_MSK BITS(PIS_CH15_CON_SYNCSEL_POSS,PIS_CH15_CON_SYNCSEL_POSE) + +#define PIS_CH15_CON_PULCK_POSS 18U +#define PIS_CH15_CON_PULCK_POSE 19U +#define PIS_CH15_CON_PULCK_MSK BITS(PIS_CH15_CON_PULCK_POSS,PIS_CH15_CON_PULCK_POSE) + +#define PIS_CH15_CON_EDGS_POSS 16U +#define PIS_CH15_CON_EDGS_POSE 17U +#define PIS_CH15_CON_EDGS_MSK BITS(PIS_CH15_CON_EDGS_POSS,PIS_CH15_CON_EDGS_POSE) + +#define PIS_CH15_CON_SRCS_POSS 8U +#define PIS_CH15_CON_SRCS_POSE 13U +#define PIS_CH15_CON_SRCS_MSK BITS(PIS_CH15_CON_SRCS_POSS,PIS_CH15_CON_SRCS_POSE) + +#define PIS_CH15_CON_MSIGS_POSS 0U +#define PIS_CH15_CON_MSIGS_POSE 3U +#define PIS_CH15_CON_MSIGS_MSK BITS(PIS_CH15_CON_MSIGS_POSS,PIS_CH15_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH_OER register ************************/ + +#define PIS_CH_OER_CH3OE_POS 3U +#define PIS_CH_OER_CH3OE_MSK BIT(PIS_CH_OER_CH3OE_POS) + +#define PIS_CH_OER_CH2OE_POS 2U +#define PIS_CH_OER_CH2OE_MSK BIT(PIS_CH_OER_CH2OE_POS) + +#define PIS_CH_OER_CH1OE_POS 1U +#define PIS_CH_OER_CH1OE_MSK BIT(PIS_CH_OER_CH1OE_POS) + +#define PIS_CH_OER_CH0OE_POS 0U +#define PIS_CH_OER_CH0OE_MSK BIT(PIS_CH_OER_CH0OE_POS) + +/****************** Bit definition for PIS_TAR_CON0 register ************************/ + +#define PIS_TAR_CON0_TIM3_CH4IN_SEL_POS 27U +#define PIS_TAR_CON0_TIM3_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH3IN_SEL_POS 26U +#define PIS_TAR_CON0_TIM3_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH2IN_SEL_POS 25U +#define PIS_TAR_CON0_TIM3_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH1IN_SEL_POS 24U +#define PIS_TAR_CON0_TIM3_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH4IN_SEL_POS 19U +#define PIS_TAR_CON0_TIM2_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH3IN_SEL_POS 18U +#define PIS_TAR_CON0_TIM2_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH2IN_SEL_POS 17U +#define PIS_TAR_CON0_TIM2_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH1IN_SEL_POS 16U +#define PIS_TAR_CON0_TIM2_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_BRKIN_SEL_POS 12U +#define PIS_TAR_CON0_TIM1_BRKIN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_BRKIN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_CH4IN_SEL_POS 11U +#define PIS_TAR_CON0_TIM1_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_CH3IN_SEL_POS 10U +#define PIS_TAR_CON0_TIM1_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_CH2IN_SEL_POS 9U +#define PIS_TAR_CON0_TIM1_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_CH1IN_SEL_POS 8U +#define PIS_TAR_CON0_TIM1_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_BRKIN_SEL_POS 4U +#define PIS_TAR_CON0_TIM0_BRKIN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_BRKIN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH4IN_SEL_POS 3U +#define PIS_TAR_CON0_TIM0_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH3IN_SEL_POS 2U +#define PIS_TAR_CON0_TIM0_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH2IN_SEL_POS 1U +#define PIS_TAR_CON0_TIM0_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH1IN_SEL_POS 0U +#define PIS_TAR_CON0_TIM0_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH1IN_SEL_POS) + +/****************** Bit definition for PIS_TAR_CON1 register ************************/ + +#define PIS_TAR_CON1_SPI1_CLK_SEL_POS 15U +#define PIS_TAR_CON1_SPI1_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI1_CLK_SEL_POS) + +#define PIS_TAR_CON1_SPI1_RX_SEL_POS 14U +#define PIS_TAR_CON1_SPI1_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI1_RX_SEL_POS) + +#define PIS_TAR_CON1_SPI0_CLK_SEL_POS 13U +#define PIS_TAR_CON1_SPI0_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI0_CLK_SEL_POS) + +#define PIS_TAR_CON1_SPI0_RX_SEL_POS 12U +#define PIS_TAR_CON1_SPI0_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI0_RX_SEL_POS) + +#define PIS_TAR_CON1_LPUART0_RXD_SEL_POS 8U +#define PIS_TAR_CON1_LPUART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_LPUART0_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART5_RXD_SEL_POS 7U +#define PIS_TAR_CON1_UART5_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART5_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART4_RXD_SEL_POS 6U +#define PIS_TAR_CON1_UART4_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART4_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART3_RXD_SEL_POS 3U +#define PIS_TAR_CON1_UART3_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART3_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART2_RXD_SEL_POS 2U +#define PIS_TAR_CON1_UART2_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART2_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART1_RXD_SEL_POS 1U +#define PIS_TAR_CON1_UART1_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART1_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART0_RXD_SEL_POS 0U +#define PIS_TAR_CON1_UART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART0_RXD_SEL_POS) + +/****************** Bit definition for PIS_UART0_TXMCR register ************************/ + +#define PIS_UART0_TXMCR_TXMLVLS_POS 8U +#define PIS_UART0_TXMCR_TXMLVLS_MSK BIT(PIS_UART0_TXMCR_TXMLVLS_POS) + +#define PIS_UART0_TXMCR_TXMSS_POSS 4U +#define PIS_UART0_TXMCR_TXMSS_POSE 7U +#define PIS_UART0_TXMCR_TXMSS_MSK BITS(PIS_UART0_TXMCR_TXMSS_POSS,PIS_UART0_TXMCR_TXMSS_POSE) + +#define PIS_UART0_TXMCR_TXSIGS_POSS 0U +#define PIS_UART0_TXMCR_TXSIGS_POSE 3U +#define PIS_UART0_TXMCR_TXSIGS_MSK BITS(PIS_UART0_TXMCR_TXSIGS_POSS,PIS_UART0_TXMCR_TXSIGS_POSE) + +/****************** Bit definition for PIS_UART1_TXMCR register ************************/ + +#define PIS_UART1_TXMCR_TXMLVLS_POS 8U +#define PIS_UART1_TXMCR_TXMLVLS_MSK BIT(PIS_UART1_TXMCR_TXMLVLS_POS) + +#define PIS_UART1_TXMCR_TXMSS_POSS 4U +#define PIS_UART1_TXMCR_TXMSS_POSE 7U +#define PIS_UART1_TXMCR_TXMSS_MSK BITS(PIS_UART1_TXMCR_TXMSS_POSS,PIS_UART1_TXMCR_TXMSS_POSE) + +#define PIS_UART1_TXMCR_TXSIGS_POSS 0U +#define PIS_UART1_TXMCR_TXSIGS_POSE 3U +#define PIS_UART1_TXMCR_TXSIGS_MSK BITS(PIS_UART1_TXMCR_TXSIGS_POSS,PIS_UART1_TXMCR_TXSIGS_POSE) + +/****************** Bit definition for PIS_UART2_TXMCR register ************************/ + +#define PIS_UART2_TXMCR_TXMLVLS_POS 8U +#define PIS_UART2_TXMCR_TXMLVLS_MSK BIT(PIS_UART2_TXMCR_TXMLVLS_POS) + +#define PIS_UART2_TXMCR_TXMSS_POSS 4U +#define PIS_UART2_TXMCR_TXMSS_POSE 7U +#define PIS_UART2_TXMCR_TXMSS_MSK BITS(PIS_UART2_TXMCR_TXMSS_POSS,PIS_UART2_TXMCR_TXMSS_POSE) + +#define PIS_UART2_TXMCR_TXSIGS_POSS 0U +#define PIS_UART2_TXMCR_TXSIGS_POSE 3U +#define PIS_UART2_TXMCR_TXSIGS_MSK BITS(PIS_UART2_TXMCR_TXSIGS_POSS,PIS_UART2_TXMCR_TXSIGS_POSE) + +/****************** Bit definition for PIS_UART3_TXMCR register ************************/ + +#define PIS_UART3_TXMCR_TXMLVLS_POS 8U +#define PIS_UART3_TXMCR_TXMLVLS_MSK BIT(PIS_UART3_TXMCR_TXMLVLS_POS) + +#define PIS_UART3_TXMCR_TXMSS_POSS 4U +#define PIS_UART3_TXMCR_TXMSS_POSE 7U +#define PIS_UART3_TXMCR_TXMSS_MSK BITS(PIS_UART3_TXMCR_TXMSS_POSS,PIS_UART3_TXMCR_TXMSS_POSE) + +#define PIS_UART3_TXMCR_TXSIGS_POSS 0U +#define PIS_UART3_TXMCR_TXSIGS_POSE 3U +#define PIS_UART3_TXMCR_TXSIGS_MSK BITS(PIS_UART3_TXMCR_TXSIGS_POSS,PIS_UART3_TXMCR_TXSIGS_POSE) + +/****************** Bit definition for PIS_LPUART0_TXMCR register ************************/ + +#define PIS_LPUART0_TXMCR_TXMLVLS_POS 8U +#define PIS_LPUART0_TXMCR_TXMLVLS_MSK BIT(PIS_LPUART0_TXMCR_TXMLVLS_POS) + +#define PIS_LPUART0_TXMCR_TXMSS_POSS 4U +#define PIS_LPUART0_TXMCR_TXMSS_POSE 7U +#define PIS_LPUART0_TXMCR_TXMSS_MSK BITS(PIS_LPUART0_TXMCR_TXMSS_POSS,PIS_LPUART0_TXMCR_TXMSS_POSE) + +#define PIS_LPUART0_TXMCR_TXSIGS_POSS 0U +#define PIS_LPUART0_TXMCR_TXSIGS_POSE 3U +#define PIS_LPUART0_TXMCR_TXSIGS_MSK BITS(PIS_LPUART0_TXMCR_TXSIGS_POSS,PIS_LPUART0_TXMCR_TXSIGS_POSE) + +typedef struct +{ + __IO uint32_t CH_CON[16]; + __IO uint32_t CH_OER; + __IO uint32_t TAR_CON0; + __IO uint32_t TAR_CON1; + uint32_t RESERVED0[5] ; + __IO uint32_t UART0_TXMCR; + __IO uint32_t UART1_TXMCR; + __IO uint32_t UART2_TXMCR; + __IO uint32_t UART3_TXMCR; + __IO uint32_t LPUART0_TXMCR; +} PIS_TypeDef; + + +/****************** Bit definition for GPIO_DIN register ************************/ + +#define GPIO_DIN_DIN_POSS 0U +#define GPIO_DIN_DIN_POSE 15U +#define GPIO_DIN_DIN_MSK BITS(GPIO_DIN_DIN_POSS,GPIO_DIN_DIN_POSE) + +/****************** Bit definition for GPIO_DOUT register ************************/ + +#define GPIO_DOUT_DOUT_POSS 0U +#define GPIO_DOUT_DOUT_POSE 15U +#define GPIO_DOUT_DOUT_MSK BITS(GPIO_DOUT_DOUT_POSS,GPIO_DOUT_DOUT_POSE) + +/****************** Bit definition for GPIO_BSRR register ************************/ + +#define GPIO_BSRR_BRR_POSS 16U +#define GPIO_BSRR_BRR_POSE 31U +#define GPIO_BSRR_BRR_MSK BITS(GPIO_BSRR_BRR_POSS,GPIO_BSRR_BRR_POSE) + +#define GPIO_BSRR_BSR_POSS 0U +#define GPIO_BSRR_BSR_POSE 15U +#define GPIO_BSRR_BSR_MSK BITS(GPIO_BSRR_BSR_POSS,GPIO_BSRR_BSR_POSE) + +/****************** Bit definition for GPIO_BIR register ************************/ + +#define GPIO_BIR_BIR_POSS 0U +#define GPIO_BIR_BIR_POSE 15U +#define GPIO_BIR_BIR_MSK BITS(GPIO_BIR_BIR_POSS,GPIO_BIR_BIR_POSE) + +/****************** Bit definition for GPIO_MODE register ************************/ + +#define GPIO_MODE_MODE_POSS 0U +#define GPIO_MODE_MODE_POSE 31U +#define GPIO_MODE_MODE_MSK BITS(GPIO_MODE_MODE_POSS,GPIO_MODE_MODE_POSE) + +/****************** Bit definition for GPIO_ODOS register ************************/ + +#define GPIO_ODOS_ODOS_POSS 0U +#define GPIO_ODOS_ODOS_POSE 31U +#define GPIO_ODOS_ODOS_MSK BITS(GPIO_ODOS_ODOS_POSS,GPIO_ODOS_ODOS_POSE) + +/****************** Bit definition for GPIO_PUPD register ************************/ + +#define GPIO_PUPD_PUPD_POSS 0U +#define GPIO_PUPD_PUPD_POSE 31U +#define GPIO_PUPD_PUPD_MSK BITS(GPIO_PUPD_PUPD_POSS,GPIO_PUPD_PUPD_POSE) + +/****************** Bit definition for GPIO_PODRV register ************************/ + +#define GPIO_PODRV_PODRV_POSS 0U +#define GPIO_PODRV_PODRV_POSE 31U +#define GPIO_PODRV_PODRV_MSK BITS(GPIO_PODRV_PODRV_POSS,GPIO_PODRV_PODRV_POSE) + +/****************** Bit definition for GPIO_NODRV register ************************/ + +#define GPIO_NODRV_NODRV_POSS 0U +#define GPIO_NODRV_NODRV_POSE 31U +#define GPIO_NODRV_NODRV_MSK BITS(GPIO_NODRV_NODRV_POSS,GPIO_NODRV_NODRV_POSE) + +/****************** Bit definition for GPIO_FLT register ************************/ + +#define GPIO_FLT_FLT_POSS 0U +#define GPIO_FLT_FLT_POSE 15U +#define GPIO_FLT_FLT_MSK BITS(GPIO_FLT_FLT_POSS,GPIO_FLT_FLT_POSE) + +/****************** Bit definition for GPIO_TYPE register ************************/ + +#define GPIO_TYPE_TYPE_POSS 0U +#define GPIO_TYPE_TYPE_POSE 15U +#define GPIO_TYPE_TYPE_MSK BITS(GPIO_TYPE_TYPE_POSS,GPIO_TYPE_TYPE_POSE) + +/****************** Bit definition for GPIO_FUNC0 register ************************/ + +#define GPIO_FUNC0_FSEL_IO7_POSS 28U +#define GPIO_FUNC0_FSEL_IO7_POSE 31U +#define GPIO_FUNC0_FSEL_IO7_MSK BITS(GPIO_FUNC0_FSEL_IO7_POSS,GPIO_FUNC0_FSEL_IO7_POSE) + +#define GPIO_FUNC0_FSEL_IO6_POSS 24U +#define GPIO_FUNC0_FSEL_IO6_POSE 27U +#define GPIO_FUNC0_FSEL_IO6_MSK BITS(GPIO_FUNC0_FSEL_IO6_POSS,GPIO_FUNC0_FSEL_IO6_POSE) + +#define GPIO_FUNC0_FSEL_IO5_POSS 20U +#define GPIO_FUNC0_FSEL_IO5_POSE 23U +#define GPIO_FUNC0_FSEL_IO5_MSK BITS(GPIO_FUNC0_FSEL_IO5_POSS,GPIO_FUNC0_FSEL_IO5_POSE) + +#define GPIO_FUNC0_FSEL_IO4_POSS 16U +#define GPIO_FUNC0_FSEL_IO4_POSE 19U +#define GPIO_FUNC0_FSEL_IO4_MSK BITS(GPIO_FUNC0_FSEL_IO4_POSS,GPIO_FUNC0_FSEL_IO4_POSE) + +#define GPIO_FUNC0_FSEL_IO3_POSS 12U +#define GPIO_FUNC0_FSEL_IO3_POSE 15U +#define GPIO_FUNC0_FSEL_IO3_MSK BITS(GPIO_FUNC0_FSEL_IO3_POSS,GPIO_FUNC0_FSEL_IO3_POSE) + +#define GPIO_FUNC0_FSEL_IO2_POSS 8U +#define GPIO_FUNC0_FSEL_IO2_POSE 11U +#define GPIO_FUNC0_FSEL_IO2_MSK BITS(GPIO_FUNC0_FSEL_IO2_POSS,GPIO_FUNC0_FSEL_IO2_POSE) + +#define GPIO_FUNC0_FSEL_IO1_POSS 4U +#define GPIO_FUNC0_FSEL_IO1_POSE 7U +#define GPIO_FUNC0_FSEL_IO1_MSK BITS(GPIO_FUNC0_FSEL_IO1_POSS,GPIO_FUNC0_FSEL_IO1_POSE) + +#define GPIO_FUNC0_FSEL_IO0_POSS 0U +#define GPIO_FUNC0_FSEL_IO0_POSE 3U +#define GPIO_FUNC0_FSEL_IO0_MSK BITS(GPIO_FUNC0_FSEL_IO0_POSS,GPIO_FUNC0_FSEL_IO0_POSE) + +/****************** Bit definition for GPIO_FUNC1 register ************************/ + +#define GPIO_FUNC1_FSEL_IO15_POSS 28U +#define GPIO_FUNC1_FSEL_IO15_POSE 31U +#define GPIO_FUNC1_FSEL_IO15_MSK BITS(GPIO_FUNC1_FSEL_IO15_POSS,GPIO_FUNC1_FSEL_IO15_POSE) + +#define GPIO_FUNC1_FSEL_IO14_POSS 24U +#define GPIO_FUNC1_FSEL_IO14_POSE 27U +#define GPIO_FUNC1_FSEL_IO14_MSK BITS(GPIO_FUNC1_FSEL_IO14_POSS,GPIO_FUNC1_FSEL_IO14_POSE) + +#define GPIO_FUNC1_FSEL_IO13_POSS 20U +#define GPIO_FUNC1_FSEL_IO13_POSE 23U +#define GPIO_FUNC1_FSEL_IO13_MSK BITS(GPIO_FUNC1_FSEL_IO13_POSS,GPIO_FUNC1_FSEL_IO13_POSE) + +#define GPIO_FUNC1_FSEL_IO12_POSS 16U +#define GPIO_FUNC1_FSEL_IO12_POSE 19U +#define GPIO_FUNC1_FSEL_IO12_MSK BITS(GPIO_FUNC1_FSEL_IO12_POSS,GPIO_FUNC1_FSEL_IO12_POSE) + +#define GPIO_FUNC1_FSEL_IO11_POSS 12U +#define GPIO_FUNC1_FSEL_IO11_POSE 15U +#define GPIO_FUNC1_FSEL_IO11_MSK BITS(GPIO_FUNC1_FSEL_IO11_POSS,GPIO_FUNC1_FSEL_IO11_POSE) + +#define GPIO_FUNC1_FSEL_IO10_POSS 8U +#define GPIO_FUNC1_FSEL_IO10_POSE 11U +#define GPIO_FUNC1_FSEL_IO10_MSK BITS(GPIO_FUNC1_FSEL_IO10_POSS,GPIO_FUNC1_FSEL_IO10_POSE) + +#define GPIO_FUNC1_FSEL_IO9_POSS 4U +#define GPIO_FUNC1_FSEL_IO9_POSE 7U +#define GPIO_FUNC1_FSEL_IO9_MSK BITS(GPIO_FUNC1_FSEL_IO9_POSS,GPIO_FUNC1_FSEL_IO9_POSE) + +#define GPIO_FUNC1_FSEL_IO8_POSS 0U +#define GPIO_FUNC1_FSEL_IO8_POSE 3U +#define GPIO_FUNC1_FSEL_IO8_MSK BITS(GPIO_FUNC1_FSEL_IO8_POSS,GPIO_FUNC1_FSEL_IO8_POSE) + +/****************** Bit definition for GPIO_LOCK register ************************/ + +#define GPIO_LOCK_KEY_POSS 16U +#define GPIO_LOCK_KEY_POSE 31U +#define GPIO_LOCK_KEY_MSK BITS(GPIO_LOCK_KEY_POSS,GPIO_LOCK_KEY_POSE) + +#define GPIO_LOCK_LOCK_POSS 0U +#define GPIO_LOCK_LOCK_POSE 15U +#define GPIO_LOCK_LOCK_MSK BITS(GPIO_LOCK_LOCK_POSS,GPIO_LOCK_LOCK_POSE) + +typedef struct +{ + __I uint32_t DIN; + __IO uint32_t DOUT; + __O uint32_t BSRR; + __O uint32_t BIR; + __IO uint32_t MODE; + __IO uint32_t ODOS; + __IO uint32_t PUPD; + __IO uint32_t PODRV; + __IO uint32_t NODRV; + __IO uint32_t FLT; + __IO uint32_t TYPE; + __IO uint32_t FUNC0; + __IO uint32_t FUNC1; + __IO uint32_t LOCK; +} GPIO_TypeDef; + +/****************** Bit definition for GPIO_EXTIRER register ************************/ + +#define GPIO_EXTIRER_EXTIRER_POSS 0U +#define GPIO_EXTIRER_EXTIRER_POSE 15U +#define GPIO_EXTIRER_EXTIRER_MSK BITS(GPIO_EXTIRER_EXTIRER_POSS,GPIO_EXTIRER_EXTIRER_POSE) + +/****************** Bit definition for GPIO_EXTIFER register ************************/ + +#define GPIO_EXTIFER_EXTIFER_POSS 0U +#define GPIO_EXTIFER_EXTIFER_POSE 15U +#define GPIO_EXTIFER_EXTIFER_MSK BITS(GPIO_EXTIFER_EXTIFER_POSS,GPIO_EXTIFER_EXTIFER_POSE) + +/****************** Bit definition for GPIO_EXTIEN register ************************/ + +#define GPIO_EXTIEN_EXTIEN_POSS 0U +#define GPIO_EXTIEN_EXTIEN_POSE 15U +#define GPIO_EXTIEN_EXTIEN_MSK BITS(GPIO_EXTIEN_EXTIEN_POSS,GPIO_EXTIEN_EXTIEN_POSE) + +/****************** Bit definition for GPIO_EXTIFLAG register ************************/ + +#define GPIO_EXTIFLAG_EXTIFLAG_POSS 0U +#define GPIO_EXTIFLAG_EXTIFLAG_POSE 15U +#define GPIO_EXTIFLAG_EXTIFLAG_MSK BITS(GPIO_EXTIFLAG_EXTIFLAG_POSS,GPIO_EXTIFLAG_EXTIFLAG_POSE) + +/****************** Bit definition for GPIO_EXTISFR register ************************/ + +#define GPIO_EXTISFR_EXTISFR_POSS 0U +#define GPIO_EXTISFR_EXTISFR_POSE 15U +#define GPIO_EXTISFR_EXTISFR_MSK BITS(GPIO_EXTISFR_EXTISFR_POSS,GPIO_EXTISFR_EXTISFR_POSE) + +/****************** Bit definition for GPIO_EXTICFR register ************************/ + +#define GPIO_EXTICFR_EXTICFR_POSS 0U +#define GPIO_EXTICFR_EXTICFR_POSE 15U +#define GPIO_EXTICFR_EXTICFR_MSK BITS(GPIO_EXTICFR_EXTICFR_POSS,GPIO_EXTICFR_EXTICFR_POSE) + +/****************** Bit definition for GPIO_EXTIPSR0 register ************************/ + +#define GPIO_EXTIPSR0_EXTIS7_POSS 28U +#define GPIO_EXTIPSR0_EXTIS7_POSE 30U +#define GPIO_EXTIPSR0_EXTIS7_MSK BITS(GPIO_EXTIPSR0_EXTIS7_POSS,GPIO_EXTIPSR0_EXTIS7_POSE) + +#define GPIO_EXTIPSR0_EXTIS6_POSS 24U +#define GPIO_EXTIPSR0_EXTIS6_POSE 26U +#define GPIO_EXTIPSR0_EXTIS6_MSK BITS(GPIO_EXTIPSR0_EXTIS6_POSS,GPIO_EXTIPSR0_EXTIS6_POSE) + +#define GPIO_EXTIPSR0_EXTIS5_POSS 20U +#define GPIO_EXTIPSR0_EXTIS5_POSE 22U +#define GPIO_EXTIPSR0_EXTIS5_MSK BITS(GPIO_EXTIPSR0_EXTIS5_POSS,GPIO_EXTIPSR0_EXTIS5_POSE) + +#define GPIO_EXTIPSR0_EXTIS4_POSS 16U +#define GPIO_EXTIPSR0_EXTIS4_POSE 18U +#define GPIO_EXTIPSR0_EXTIS4_MSK BITS(GPIO_EXTIPSR0_EXTIS4_POSS,GPIO_EXTIPSR0_EXTIS4_POSE) + +#define GPIO_EXTIPSR0_EXTIS3_POSS 12U +#define GPIO_EXTIPSR0_EXTIS3_POSE 14U +#define GPIO_EXTIPSR0_EXTIS3_MSK BITS(GPIO_EXTIPSR0_EXTIS3_POSS,GPIO_EXTIPSR0_EXTIS3_POSE) + +#define GPIO_EXTIPSR0_EXTIS2_POSS 8U +#define GPIO_EXTIPSR0_EXTIS2_POSE 10U +#define GPIO_EXTIPSR0_EXTIS2_MSK BITS(GPIO_EXTIPSR0_EXTIS2_POSS,GPIO_EXTIPSR0_EXTIS2_POSE) + +#define GPIO_EXTIPSR0_EXTIS1_POSS 4U +#define GPIO_EXTIPSR0_EXTIS1_POSE 6U +#define GPIO_EXTIPSR0_EXTIS1_MSK BITS(GPIO_EXTIPSR0_EXTIS1_POSS,GPIO_EXTIPSR0_EXTIS1_POSE) + +#define GPIO_EXTIPSR0_EXTIS0_POSS 0U +#define GPIO_EXTIPSR0_EXTIS0_POSE 2U +#define GPIO_EXTIPSR0_EXTIS0_MSK BITS(GPIO_EXTIPSR0_EXTIS0_POSS,GPIO_EXTIPSR0_EXTIS0_POSE) + +/****************** Bit definition for GPIO_EXTIPSR1 register ************************/ + +#define GPIO_EXTIPSR1_EXTIS15_POSS 28U +#define GPIO_EXTIPSR1_EXTIS15_POSE 30U +#define GPIO_EXTIPSR1_EXTIS15_MSK BITS(GPIO_EXTIPSR1_EXTIS15_POSS,GPIO_EXTIPSR1_EXTIS15_POSE) + +#define GPIO_EXTIPSR1_EXTIS14_POSS 24U +#define GPIO_EXTIPSR1_EXTIS14_POSE 26U +#define GPIO_EXTIPSR1_EXTIS14_MSK BITS(GPIO_EXTIPSR1_EXTIS14_POSS,GPIO_EXTIPSR1_EXTIS14_POSE) + +#define GPIO_EXTIPSR1_EXTIS13_POSS 20U +#define GPIO_EXTIPSR1_EXTIS13_POSE 22U +#define GPIO_EXTIPSR1_EXTIS13_MSK BITS(GPIO_EXTIPSR1_EXTIS13_POSS,GPIO_EXTIPSR1_EXTIS13_POSE) + +#define GPIO_EXTIPSR1_EXTIS12_POSS 16U +#define GPIO_EXTIPSR1_EXTIS12_POSE 18U +#define GPIO_EXTIPSR1_EXTIS12_MSK BITS(GPIO_EXTIPSR1_EXTIS12_POSS,GPIO_EXTIPSR1_EXTIS12_POSE) + +#define GPIO_EXTIPSR1_EXTIS11_POSS 12U +#define GPIO_EXTIPSR1_EXTIS11_POSE 14U +#define GPIO_EXTIPSR1_EXTIS11_MSK BITS(GPIO_EXTIPSR1_EXTIS11_POSS,GPIO_EXTIPSR1_EXTIS11_POSE) + +#define GPIO_EXTIPSR1_EXTIS10_POSS 8U +#define GPIO_EXTIPSR1_EXTIS10_POSE 10U +#define GPIO_EXTIPSR1_EXTIS10_MSK BITS(GPIO_EXTIPSR1_EXTIS10_POSS,GPIO_EXTIPSR1_EXTIS10_POSE) + +#define GPIO_EXTIPSR1_EXTIS9_POSS 4U +#define GPIO_EXTIPSR1_EXTIS9_POSE 6U +#define GPIO_EXTIPSR1_EXTIS9_MSK BITS(GPIO_EXTIPSR1_EXTIS9_POSS,GPIO_EXTIPSR1_EXTIS9_POSE) + +#define GPIO_EXTIPSR1_EXTIS8_POSS 0U +#define GPIO_EXTIPSR1_EXTIS8_POSE 2U +#define GPIO_EXTIPSR1_EXTIS8_MSK BITS(GPIO_EXTIPSR1_EXTIS8_POSS,GPIO_EXTIPSR1_EXTIS8_POSE) + +/****************** Bit definition for GPIO_EXTIFLTCR register ************************/ + +#define GPIO_EXTIFLTCR_FLTCKS_POSS 24U +#define GPIO_EXTIFLTCR_FLTCKS_POSE 25U +#define GPIO_EXTIFLTCR_FLTCKS_MSK BITS(GPIO_EXTIFLTCR_FLTCKS_POSS,GPIO_EXTIFLTCR_FLTCKS_POSE) + +#define GPIO_EXTIFLTCR_FLTSEL_POSS 16U +#define GPIO_EXTIFLTCR_FLTSEL_POSE 23U +#define GPIO_EXTIFLTCR_FLTSEL_MSK BITS(GPIO_EXTIFLTCR_FLTSEL_POSS,GPIO_EXTIFLTCR_FLTSEL_POSE) + +#define GPIO_EXTIFLTCR_FLTEN_POSS 0U +#define GPIO_EXTIFLTCR_FLTEN_POSE 15U +#define GPIO_EXTIFLTCR_FLTEN_MSK BITS(GPIO_EXTIFLTCR_FLTEN_POSS,GPIO_EXTIFLTCR_FLTEN_POSE) + +typedef struct +{ + __IO uint32_t EXTIRER; + uint32_t RESERVED0 ; + __IO uint32_t EXTIFER; + uint32_t RESERVED1 ; + __IO uint32_t EXTIEN; + uint32_t RESERVED2 ; + __I uint32_t EXTIFLAG; + uint32_t RESERVED3 ; + __O uint32_t EXTISFR; + uint32_t RESERVED4 ; + __O uint32_t EXTICFR; + uint32_t RESERVED5 ; + __IO uint32_t EXTIPSR0; + __IO uint32_t EXTIPSR1; + uint32_t RESERVED6[2] ; + __IO uint32_t EXTIFLTCR; +} EXTI_TypeDef; + +/****************** Bit definition for RTC_WPR register ************************/ + +#define RTC_WPR_WP_POS 0U +#define RTC_WPR_WP_MSK BIT(RTC_WPR_WP_POS) + +/****************** Bit definition for RTC_CON register ************************/ + +#define RTC_CON_SSEC_POS 25U +#define RTC_CON_SSEC_MSK BIT(RTC_CON_SSEC_POS) + +#define RTC_CON_BUSY_POS 24U +#define RTC_CON_BUSY_MSK BIT(RTC_CON_BUSY_POS) + +#define RTC_CON_POL_POS 22U +#define RTC_CON_POL_MSK BIT(RTC_CON_POL_POS) + +#define RTC_CON_EOS_POSS 20U +#define RTC_CON_EOS_POSE 21U +#define RTC_CON_EOS_MSK BITS(RTC_CON_EOS_POSS,RTC_CON_EOS_POSE) + +#define RTC_CON_CKOS_POSS 17U +#define RTC_CON_CKOS_POSE 19U +#define RTC_CON_CKOS_MSK BITS(RTC_CON_CKOS_POSS,RTC_CON_CKOS_POSE) + +#define RTC_CON_CKOE_POS 16U +#define RTC_CON_CKOE_MSK BIT(RTC_CON_CKOE_POS) + +#define RTC_CON_WUCKS_POSS 13U +#define RTC_CON_WUCKS_POSE 15U +#define RTC_CON_WUCKS_MSK BITS(RTC_CON_WUCKS_POSS,RTC_CON_WUCKS_POSE) + +#define RTC_CON_WUTE_POS 12U +#define RTC_CON_WUTE_MSK BIT(RTC_CON_WUTE_POS) + +#define RTC_CON_DSTS_POS 10U +#define RTC_CON_DSTS_MSK BIT(RTC_CON_DSTS_POS) + +#define RTC_CON_SUB1H_POS 9U +#define RTC_CON_SUB1H_MSK BIT(RTC_CON_SUB1H_POS) + +#define RTC_CON_ADD1H_POS 8U +#define RTC_CON_ADD1H_MSK BIT(RTC_CON_ADD1H_POS) + +#define RTC_CON_TSPIN_POS 7U +#define RTC_CON_TSPIN_MSK BIT(RTC_CON_TSPIN_POS) + +#define RTC_CON_TSSEL_POS 6U +#define RTC_CON_TSSEL_MSK BIT(RTC_CON_TSSEL_POS) + +#define RTC_CON_TSEN_POS 5U +#define RTC_CON_TSEN_MSK BIT(RTC_CON_TSEN_POS) + +#define RTC_CON_SHDBP_POS 4U +#define RTC_CON_SHDBP_MSK BIT(RTC_CON_SHDBP_POS) + +#define RTC_CON_HFM_POS 3U +#define RTC_CON_HFM_MSK BIT(RTC_CON_HFM_POS) + +#define RTC_CON_ALMBEN_POS 2U +#define RTC_CON_ALMBEN_MSK BIT(RTC_CON_ALMBEN_POS) + +#define RTC_CON_ALMAEN_POS 1U +#define RTC_CON_ALMAEN_MSK BIT(RTC_CON_ALMAEN_POS) + +#define RTC_CON_GO_POS 0U +#define RTC_CON_GO_MSK BIT(RTC_CON_GO_POS) + +/****************** Bit definition for RTC_PSR register ************************/ + +#define RTC_PSR_APRS_POSS 16U +#define RTC_PSR_APRS_POSE 22U +#define RTC_PSR_APRS_MSK BITS(RTC_PSR_APRS_POSS,RTC_PSR_APRS_POSE) + +#define RTC_PSR_SPRS_POSS 0U +#define RTC_PSR_SPRS_POSE 14U +#define RTC_PSR_SPRS_MSK BITS(RTC_PSR_SPRS_POSS,RTC_PSR_SPRS_POSE) + +/****************** Bit definition for RTC_TAMPCON register ************************/ + +#define RTC_TAMPCON_TAMPFLT_POSS 20U +#define RTC_TAMPCON_TAMPFLT_POSE 21U +#define RTC_TAMPCON_TAMPFLT_MSK BITS(RTC_TAMPCON_TAMPFLT_POSS,RTC_TAMPCON_TAMPFLT_POSE) + +#define RTC_TAMPCON_TAMPCKS_POSS 17U +#define RTC_TAMPCON_TAMPCKS_POSE 19U +#define RTC_TAMPCON_TAMPCKS_MSK BITS(RTC_TAMPCON_TAMPCKS_POSS,RTC_TAMPCON_TAMPCKS_POSE) + +#define RTC_TAMPCON_TAMPTS_POS 16U +#define RTC_TAMPCON_TAMPTS_MSK BIT(RTC_TAMPCON_TAMPTS_POS) + +#define RTC_TAMPCON_TAMP2LV_POS 9U +#define RTC_TAMPCON_TAMP2LV_MSK BIT(RTC_TAMPCON_TAMP2LV_POS) + +#define RTC_TAMPCON_TAMP2EN_POS 8U +#define RTC_TAMPCON_TAMP2EN_MSK BIT(RTC_TAMPCON_TAMP2EN_POS) + +#define RTC_TAMPCON_TAMP1LV_POS 1U +#define RTC_TAMPCON_TAMP1LV_MSK BIT(RTC_TAMPCON_TAMP1LV_POS) + +#define RTC_TAMPCON_TAMP1EN_POS 0U +#define RTC_TAMPCON_TAMP1EN_MSK BIT(RTC_TAMPCON_TAMP1EN_POS) + +/****************** Bit definition for RTC_TIME register ************************/ + +#define RTC_TIME_PM_POS 22U +#define RTC_TIME_PM_MSK BIT(RTC_TIME_PM_POS) + +#define RTC_TIME_HRT_POSS 20U +#define RTC_TIME_HRT_POSE 21U +#define RTC_TIME_HRT_MSK BITS(RTC_TIME_HRT_POSS,RTC_TIME_HRT_POSE) + +#define RTC_TIME_HRU_POSS 16U +#define RTC_TIME_HRU_POSE 19U +#define RTC_TIME_HRU_MSK BITS(RTC_TIME_HRU_POSS,RTC_TIME_HRU_POSE) + +#define RTC_TIME_MINT_POSS 12U +#define RTC_TIME_MINT_POSE 14U +#define RTC_TIME_MINT_MSK BITS(RTC_TIME_MINT_POSS,RTC_TIME_MINT_POSE) + +#define RTC_TIME_MINU_POSS 8U +#define RTC_TIME_MINU_POSE 11U +#define RTC_TIME_MINU_MSK BITS(RTC_TIME_MINU_POSS,RTC_TIME_MINU_POSE) + +#define RTC_TIME_SECT_POSS 4U +#define RTC_TIME_SECT_POSE 6U +#define RTC_TIME_SECT_MSK BITS(RTC_TIME_SECT_POSS,RTC_TIME_SECT_POSE) + +#define RTC_TIME_SECU_POSS 0U +#define RTC_TIME_SECU_POSE 3U +#define RTC_TIME_SECU_MSK BITS(RTC_TIME_SECU_POSS,RTC_TIME_SECU_POSE) + +/****************** Bit definition for RTC_DATE register ************************/ + +#define RTC_DATE_WD_POSS 24U +#define RTC_DATE_WD_POSE 26U +#define RTC_DATE_WD_MSK BITS(RTC_DATE_WD_POSS,RTC_DATE_WD_POSE) + +#define RTC_DATE_YRT_POSS 20U +#define RTC_DATE_YRT_POSE 23U +#define RTC_DATE_YRT_MSK BITS(RTC_DATE_YRT_POSS,RTC_DATE_YRT_POSE) + +#define RTC_DATE_YRU_POSS 16U +#define RTC_DATE_YRU_POSE 19U +#define RTC_DATE_YRU_MSK BITS(RTC_DATE_YRU_POSS,RTC_DATE_YRU_POSE) + +#define RTC_DATE_MONT_POS 12U +#define RTC_DATE_MONT_MSK BIT(RTC_DATE_MONT_POS) + +#define RTC_DATE_MONU_POSS 8U +#define RTC_DATE_MONU_POSE 11U +#define RTC_DATE_MONU_MSK BITS(RTC_DATE_MONU_POSS,RTC_DATE_MONU_POSE) + +#define RTC_DATE_DAYT_POSS 4U +#define RTC_DATE_DAYT_POSE 5U +#define RTC_DATE_DAYT_MSK BITS(RTC_DATE_DAYT_POSS,RTC_DATE_DAYT_POSE) + +#define RTC_DATE_DAYU_POSS 0U +#define RTC_DATE_DAYU_POSE 3U +#define RTC_DATE_DAYU_MSK BITS(RTC_DATE_DAYU_POSS,RTC_DATE_DAYU_POSE) + +/****************** Bit definition for RTC_SSEC register ************************/ + +#define RTC_SSEC_VAL_POSS 0U +#define RTC_SSEC_VAL_POSE 15U +#define RTC_SSEC_VAL_MSK BITS(RTC_SSEC_VAL_POSS,RTC_SSEC_VAL_POSE) + +/****************** Bit definition for RTC_WUMAT register ************************/ + +#define RTC_WUMAT_VAL_POSS 0U +#define RTC_WUMAT_VAL_POSE 15U +#define RTC_WUMAT_VAL_MSK BITS(RTC_WUMAT_VAL_POSS,RTC_WUMAT_VAL_POSE) + +/****************** Bit definition for RTC_ALMA register ************************/ + +#define RTC_ALMA_WDS_POS 31U +#define RTC_ALMA_WDS_MSK BIT(RTC_ALMA_WDS_POS) + +#define RTC_ALMA_DAWD_POSS 24U +#define RTC_ALMA_DAWD_POSE 30U +#define RTC_ALMA_DAWD_MSK BITS(RTC_ALMA_DAWD_POSS,RTC_ALMA_DAWD_POSE) + +#define RTC_ALMA_DAYMSK_POS 30U +#define RTC_ALMA_DAYMSK_MSK BIT(RTC_ALMA_DAYMSK_POS) + +#define RTC_ALMA_DAWD_DAYT_POSS 28U +#define RTC_ALMA_DAWD_DAYT_POSE 29U +#define RTC_ALMA_DAWD_DAYT_MSK BITS(RTC_ALMA_DAWD_DAYT_POSS, RTC_ALMA_DAWD_DAYT_POSE) + +#define RTC_ALMA_DAWD_DAYU_POSS 24U +#define RTC_ALMA_DAWD_DAYU_POSE 27U +#define RTC_ALMA_DAWD_DAYU_MSK BITS(RTC_ALMA_DAWD_DAYU_POSS, RTC_ALMA_DAWD_DAYU_POSE) + +#define RTC_ALMA_HRMSK_POS 23U +#define RTC_ALMA_HRMSK_MSK BIT(RTC_ALMA_HRMSK_POS) + +#define RTC_ALMA_PM_POS 22U +#define RTC_ALMA_PM_MSK BIT(RTC_ALMA_PM_POS) + +#define RTC_ALMA_HRT_POSS 20U +#define RTC_ALMA_HRT_POSE 21U +#define RTC_ALMA_HRT_MSK BITS(RTC_ALMA_HRT_POSS,RTC_ALMA_HRT_POSE) + +#define RTC_ALMA_HRU_POSS 16U +#define RTC_ALMA_HRU_POSE 19U +#define RTC_ALMA_HRU_MSK BITS(RTC_ALMA_HRU_POSS,RTC_ALMA_HRU_POSE) + +#define RTC_ALMA_MINMSK_POS 15U +#define RTC_ALMA_MINMSK_MSK BIT(RTC_ALMA_MINMSK_POS) + +#define RTC_ALMA_MINT_POSS 12U +#define RTC_ALMA_MINT_POSE 14U +#define RTC_ALMA_MINT_MSK BITS(RTC_ALMA_MINT_POSS,RTC_ALMA_MINT_POSE) + +#define RTC_ALMA_MINU_POSS 8U +#define RTC_ALMA_MINU_POSE 11U +#define RTC_ALMA_MINU_MSK BITS(RTC_ALMA_MINU_POSS,RTC_ALMA_MINU_POSE) + +#define RTC_ALMA_SECMSK_POS 7U +#define RTC_ALMA_SECMSK_MSK BIT(RTC_ALMA_SECMSK_POS) + +#define RTC_ALMA_SECT_POSS 4U +#define RTC_ALMA_SECT_POSE 6U +#define RTC_ALMA_SECT_MSK BITS(RTC_ALMA_SECT_POSS,RTC_ALMA_SECT_POSE) + +#define RTC_ALMA_SECU_POSS 0U +#define RTC_ALMA_SECU_POSE 3U +#define RTC_ALMA_SECU_MSK BITS(RTC_ALMA_SECU_POSS,RTC_ALMA_SECU_POSE) + +/****************** Bit definition for RTC_ALMB register ************************/ + +#define RTC_ALMB_WDS_POS 31U +#define RTC_ALMB_WDS_MSK BIT(RTC_ALMB_WDS_POS) + +#define RTC_ALMB_DAWD_POSS 24U +#define RTC_ALMB_DAWD_POSE 30U +#define RTC_ALMB_DAWD_MSK BITS(RTC_ALMB_DAWD_POSS,RTC_ALMB_DAWD_POSE) + +#define RTC_ALMB_DAYMSK_POS 30U +#define RTC_ALMB_DAYMSK_MSK BIT(RTC_ALMB_DAYMSK_POS) + +#define RTC_ALMB_DAWD_DAYT_POSS 28U +#define RTC_ALMB_DAWD_DAYT_POSE 29U +#define RTC_ALMB_DAWD_DAYT_MSK BITS(RTC_ALMB_DAWD_DAYT_POSS, RTC_ALMB_DAWD_DAYT_POSE) + +#define RTC_ALMB_DAWD_DAYU_POSS 24U +#define RTC_ALMB_DAWD_DAYU_POSE 27U +#define RTC_ALMB_DAWD_DAYU_MSK BITS(RTC_ALMB_DAWD_DAYU_POSS, RTC_ALMB_DAWD_DAYU_POSE) + +#define RTC_ALMB_HRMSK_POS 23U +#define RTC_ALMB_HRMSK_MSK BIT(RTC_ALMB_HRMSK_POS) + +#define RTC_ALMB_PM_POS 22U +#define RTC_ALMB_PM_MSK BIT(RTC_ALMB_PM_POS) + +#define RTC_ALMB_HRT_POSS 20U +#define RTC_ALMB_HRT_POSE 21U +#define RTC_ALMB_HRT_MSK BITS(RTC_ALMB_HRT_POSS,RTC_ALMB_HRT_POSE) + +#define RTC_ALMB_HRU_POSS 16U +#define RTC_ALMB_HRU_POSE 19U +#define RTC_ALMB_HRU_MSK BITS(RTC_ALMB_HRU_POSS,RTC_ALMB_HRU_POSE) + +#define RTC_ALMB_MINMSK_POS 15U +#define RTC_ALMB_MINMSK_MSK BIT(RTC_ALMB_MINMSK_POS) + +#define RTC_ALMB_MINT_POSS 12U +#define RTC_ALMB_MINT_POSE 14U +#define RTC_ALMB_MINT_MSK BITS(RTC_ALMB_MINT_POSS,RTC_ALMB_MINT_POSE) + +#define RTC_ALMB_MINU_POSS 8U +#define RTC_ALMB_MINU_POSE 11U +#define RTC_ALMB_MINU_MSK BITS(RTC_ALMB_MINU_POSS,RTC_ALMB_MINU_POSE) + +#define RTC_ALMB_SECMSK_POS 7U +#define RTC_ALMB_SECMSK_MSK BIT(RTC_ALMB_SECMSK_POS) + +#define RTC_ALMB_SECT_POSS 4U +#define RTC_ALMB_SECT_POSE 6U +#define RTC_ALMB_SECT_MSK BITS(RTC_ALMB_SECT_POSS,RTC_ALMB_SECT_POSE) + +#define RTC_ALMB_SECU_POSS 0U +#define RTC_ALMB_SECU_POSE 3U +#define RTC_ALMB_SECU_MSK BITS(RTC_ALMB_SECU_POSS,RTC_ALMB_SECU_POSE) + +/****************** Bit definition for RTC_ALMASSEC register ************************/ + +#define RTC_ALMASSEC_SSECM_POSS 24U +#define RTC_ALMASSEC_SSECM_POSE 27U +#define RTC_ALMASSEC_SSECM_MSK BITS(RTC_ALMASSEC_SSECM_POSS,RTC_ALMASSEC_SSECM_POSE) + +#define RTC_ALMASSEC_SSEC_POSS 0U +#define RTC_ALMASSEC_SSEC_POSE 14U +#define RTC_ALMASSEC_SSEC_MSK BITS(RTC_ALMASSEC_SSEC_POSS,RTC_ALMASSEC_SSEC_POSE) + +/****************** Bit definition for RTC_ALMBSSEC register ************************/ + +#define RTC_ALMBSSEC_SSECM_POSS 24U +#define RTC_ALMBSSEC_SSECM_POSE 27U +#define RTC_ALMBSSEC_SSECM_MSK BITS(RTC_ALMBSSEC_SSECM_POSS,RTC_ALMBSSEC_SSECM_POSE) + +#define RTC_ALMBSSEC_SSEC_POSS 0U +#define RTC_ALMBSSEC_SSEC_POSE 14U +#define RTC_ALMBSSEC_SSEC_MSK BITS(RTC_ALMBSSEC_SSEC_POSS,RTC_ALMBSSEC_SSEC_POSE) + +/****************** Bit definition for RTC_TSTIME register ************************/ + +#define RTC_TSTIME_PM_POS 22U +#define RTC_TSTIME_PM_MSK BIT(RTC_TSTIME_PM_POS) + +#define RTC_TSTIME_HRT_POSS 20U +#define RTC_TSTIME_HRT_POSE 21U +#define RTC_TSTIME_HRT_MSK BITS(RTC_TSTIME_HRT_POSS,RTC_TSTIME_HRT_POSE) + +#define RTC_TSTIME_HRU_POSS 16U +#define RTC_TSTIME_HRU_POSE 19U +#define RTC_TSTIME_HRU_MSK BITS(RTC_TSTIME_HRU_POSS,RTC_TSTIME_HRU_POSE) + +#define RTC_TSTIME_MINT_POSS 12U +#define RTC_TSTIME_MINT_POSE 14U +#define RTC_TSTIME_MINT_MSK BITS(RTC_TSTIME_MINT_POSS,RTC_TSTIME_MINT_POSE) + +#define RTC_TSTIME_MINU_POSS 8U +#define RTC_TSTIME_MINU_POSE 11U +#define RTC_TSTIME_MINU_MSK BITS(RTC_TSTIME_MINU_POSS,RTC_TSTIME_MINU_POSE) + +#define RTC_TSTIME_SECT_POSS 4U +#define RTC_TSTIME_SECT_POSE 6U +#define RTC_TSTIME_SECT_MSK BITS(RTC_TSTIME_SECT_POSS,RTC_TSTIME_SECT_POSE) + +#define RTC_TSTIME_SECU_POSS 0U +#define RTC_TSTIME_SECU_POSE 3U +#define RTC_TSTIME_SECU_MSK BITS(RTC_TSTIME_SECU_POSS,RTC_TSTIME_SECU_POSE) + +/****************** Bit definition for RTC_TSDATE register ************************/ + +#define RTC_TSDATE_WD_POSS 24U +#define RTC_TSDATE_WD_POSE 26U +#define RTC_TSDATE_WD_MSK BITS(RTC_TSDATE_WD_POSS,RTC_TSDATE_WD_POSE) + +#define RTC_TSDATE_YRT_POSS 20U +#define RTC_TSDATE_YRT_POSE 23U +#define RTC_TSDATE_YRT_MSK BITS(RTC_TSDATE_YRT_POSS,RTC_TSDATE_YRT_POSE) + +#define RTC_TSDATE_YRU_POSS 16U +#define RTC_TSDATE_YRU_POSE 19U +#define RTC_TSDATE_YRU_MSK BITS(RTC_TSDATE_YRU_POSS,RTC_TSDATE_YRU_POSE) + +#define RTC_TSDATE_MONT_POS 12U +#define RTC_TSDATE_MONT_MSK BIT(RTC_TSDATE_MONT_POS) + +#define RTC_TSDATE_MONU_POSS 8U +#define RTC_TSDATE_MONU_POSE 11U +#define RTC_TSDATE_MONU_MSK BITS(RTC_TSDATE_MONU_POSS,RTC_TSDATE_MONU_POSE) + +#define RTC_TSDATE_DAYT_POSS 4U +#define RTC_TSDATE_DAYT_POSE 5U +#define RTC_TSDATE_DAYT_MSK BITS(RTC_TSDATE_DAYT_POSS,RTC_TSDATE_DAYT_POSE) + +#define RTC_TSDATE_DAYU_POSS 0U +#define RTC_TSDATE_DAYU_POSE 3U +#define RTC_TSDATE_DAYU_MSK BITS(RTC_TSDATE_DAYU_POSS,RTC_TSDATE_DAYU_POSE) + +/****************** Bit definition for RTC_TSSSEC register ************************/ + +#define RTC_TSSSEC_SSEC_POSS 0U +#define RTC_TSSSEC_SSEC_POSE 15U +#define RTC_TSSSEC_SSEC_MSK BITS(RTC_TSSSEC_SSEC_POSS,RTC_TSSSEC_SSEC_POSE) + +/****************** Bit definition for RTC_SSECTR register ************************/ + +#define RTC_SSECTR_INC_POS 31U +#define RTC_SSECTR_INC_MSK BIT(RTC_SSECTR_INC_POS) + +#define RTC_SSECTR_TRIM_POSS 0U +#define RTC_SSECTR_TRIM_POSE 14U +#define RTC_SSECTR_TRIM_MSK BITS(RTC_SSECTR_TRIM_POSS,RTC_SSECTR_TRIM_POSE) + +/****************** Bit definition for RTC_IER register ************************/ + +#define RTC_IER_TCE_POS 25U +#define RTC_IER_TCE_MSK BIT(RTC_IER_TCE_POS) + +#define RTC_IER_TCC_POS 24U +#define RTC_IER_TCC_MSK BIT(RTC_IER_TCC_POS) + +#define RTC_IER_WU_POS 18U +#define RTC_IER_WU_MSK BIT(RTC_IER_WU_POS) + +#define RTC_IER_SSTC_POS 17U +#define RTC_IER_SSTC_MSK BIT(RTC_IER_SSTC_POS) + +#define RTC_IER_RSC_POS 16U +#define RTC_IER_RSC_MSK BIT(RTC_IER_RSC_POS) + +#define RTC_IER_TAMP2_POS 13U +#define RTC_IER_TAMP2_MSK BIT(RTC_IER_TAMP2_POS) + +#define RTC_IER_TAMP1_POS 12U +#define RTC_IER_TAMP1_MSK BIT(RTC_IER_TAMP1_POS) + +#define RTC_IER_TSOV_POS 11U +#define RTC_IER_TSOV_MSK BIT(RTC_IER_TSOV_POS) + +#define RTC_IER_TS_POS 10U +#define RTC_IER_TS_MSK BIT(RTC_IER_TS_POS) + +#define RTC_IER_ALMB_POS 9U +#define RTC_IER_ALMB_MSK BIT(RTC_IER_ALMB_POS) + +#define RTC_IER_ALMA_POS 8U +#define RTC_IER_ALMA_MSK BIT(RTC_IER_ALMA_POS) + +#define RTC_IER_YR_POS 5U +#define RTC_IER_YR_MSK BIT(RTC_IER_YR_POS) + +#define RTC_IER_MON_POS 4U +#define RTC_IER_MON_MSK BIT(RTC_IER_MON_POS) + +#define RTC_IER_DAY_POS 3U +#define RTC_IER_DAY_MSK BIT(RTC_IER_DAY_POS) + +#define RTC_IER_HR_POS 2U +#define RTC_IER_HR_MSK BIT(RTC_IER_HR_POS) + +#define RTC_IER_MIN_POS 1U +#define RTC_IER_MIN_MSK BIT(RTC_IER_MIN_POS) + +#define RTC_IER_SEC_POS 0U +#define RTC_IER_SEC_MSK BIT(RTC_IER_SEC_POS) + +/****************** Bit definition for RTC_IFR register ************************/ + +#define RTC_IFR_TCEF_POS 25U +#define RTC_IFR_TCEF_MSK BIT(RTC_IFR_TCEF_POS) + +#define RTC_IFR_TCCF_POS 24U +#define RTC_IFR_TCCF_MSK BIT(RTC_IFR_TCCF_POS) + +#define RTC_IFR_WUF_POS 18U +#define RTC_IFR_WUF_MSK BIT(RTC_IFR_WUF_POS) + +#define RTC_IFR_SSTCF_POS 17U +#define RTC_IFR_SSTCF_MSK BIT(RTC_IFR_SSTCF_POS) + +#define RTC_IFR_RSCF_POS 16U +#define RTC_IFR_RSCF_MSK BIT(RTC_IFR_RSCF_POS) + +#define RTC_IFR_TAMP2F_POS 13U +#define RTC_IFR_TAMP2F_MSK BIT(RTC_IFR_TAMP2F_POS) + +#define RTC_IFR_TAMP1F_POS 12U +#define RTC_IFR_TAMP1F_MSK BIT(RTC_IFR_TAMP1F_POS) + +#define RTC_IFR_TSOVF_POS 11U +#define RTC_IFR_TSOVF_MSK BIT(RTC_IFR_TSOVF_POS) + +#define RTC_IFR_TSF_POS 10U +#define RTC_IFR_TSF_MSK BIT(RTC_IFR_TSF_POS) + +#define RTC_IFR_ALMBF_POS 9U +#define RTC_IFR_ALMBF_MSK BIT(RTC_IFR_ALMBF_POS) + +#define RTC_IFR_ALMAF_POS 8U +#define RTC_IFR_ALMAF_MSK BIT(RTC_IFR_ALMAF_POS) + +#define RTC_IFR_YRF_POS 5U +#define RTC_IFR_YRF_MSK BIT(RTC_IFR_YRF_POS) + +#define RTC_IFR_MONF_POS 4U +#define RTC_IFR_MONF_MSK BIT(RTC_IFR_MONF_POS) + +#define RTC_IFR_DAYF_POS 3U +#define RTC_IFR_DAYF_MSK BIT(RTC_IFR_DAYF_POS) + +#define RTC_IFR_HRF_POS 2U +#define RTC_IFR_HRF_MSK BIT(RTC_IFR_HRF_POS) + +#define RTC_IFR_MINF_POS 1U +#define RTC_IFR_MINF_MSK BIT(RTC_IFR_MINF_POS) + +#define RTC_IFR_SECF_POS 0U +#define RTC_IFR_SECF_MSK BIT(RTC_IFR_SECF_POS) + +/****************** Bit definition for RTC_IFCR register ************************/ + +#define RTC_IFCR_TCEFC_POS 25U +#define RTC_IFCR_TCEFC_MSK BIT(RTC_IFCR_TCEFC_POS) + +#define RTC_IFCR_TCCFC_POS 24U +#define RTC_IFCR_TCCFC_MSK BIT(RTC_IFCR_TCCFC_POS) + +#define RTC_IFCR_WUFC_POS 18U +#define RTC_IFCR_WUFC_MSK BIT(RTC_IFCR_WUFC_POS) + +#define RTC_IFCR_SSTCFC_POS 17U +#define RTC_IFCR_SSTCFC_MSK BIT(RTC_IFCR_SSTCFC_POS) + +#define RTC_IFCR_RSCFC_POS 16U +#define RTC_IFCR_RSCFC_MSK BIT(RTC_IFCR_RSCFC_POS) + +#define RTC_IFCR_TAMP2FC_POS 13U +#define RTC_IFCR_TAMP2FC_MSK BIT(RTC_IFCR_TAMP2FC_POS) + +#define RTC_IFCR_TAMP1FC_POS 12U +#define RTC_IFCR_TAMP1FC_MSK BIT(RTC_IFCR_TAMP1FC_POS) + +#define RTC_IFCR_TSOVFC_POS 11U +#define RTC_IFCR_TSOVFC_MSK BIT(RTC_IFCR_TSOVFC_POS) + +#define RTC_IFCR_TSSTC_POS 10U +#define RTC_IFCR_TSSTC_MSK BIT(RTC_IFCR_TSSTC_POS) + +#define RTC_IFCR_ALMBFC_POS 9U +#define RTC_IFCR_ALMBFC_MSK BIT(RTC_IFCR_ALMBFC_POS) + +#define RTC_IFCR_ALMAFC_POS 8U +#define RTC_IFCR_ALMAFC_MSK BIT(RTC_IFCR_ALMAFC_POS) + +#define RTC_IFCR_YRFC_POS 5U +#define RTC_IFCR_YRFC_MSK BIT(RTC_IFCR_YRFC_POS) + +#define RTC_IFCR_MONFC_POS 4U +#define RTC_IFCR_MONFC_MSK BIT(RTC_IFCR_MONFC_POS) + +#define RTC_IFCR_DAYFC_POS 3U +#define RTC_IFCR_DAYFC_MSK BIT(RTC_IFCR_DAYFC_POS) + +#define RTC_IFCR_HRFC_POS 2U +#define RTC_IFCR_HRFC_MSK BIT(RTC_IFCR_HRFC_POS) + +#define RTC_IFCR_MINFC_POS 1U +#define RTC_IFCR_MINFC_MSK BIT(RTC_IFCR_MINFC_POS) + +#define RTC_IFCR_SECFC_POS 0U +#define RTC_IFCR_SECFC_MSK BIT(RTC_IFCR_SECFC_POS) + +/****************** Bit definition for RTC_ISR register ************************/ + +#define RTC_ISR_TCEF_POS 25U +#define RTC_ISR_TCEF_MSK BIT(RTC_ISR_TCEF_POS) + +#define RTC_ISR_TCCF_POS 24U +#define RTC_ISR_TCCF_MSK BIT(RTC_ISR_TCCF_POS) + +#define RTC_ISR_WUF_POS 18U +#define RTC_ISR_WUF_MSK BIT(RTC_ISR_WUF_POS) + +#define RTC_ISR_SSTCF_POS 17U +#define RTC_ISR_SSTCF_MSK BIT(RTC_ISR_SSTCF_POS) + +#define RTC_ISR_RSCF_POS 16U +#define RTC_ISR_RSCF_MSK BIT(RTC_ISR_RSCF_POS) + +#define RTC_ISR_TAMP2F_POS 13U +#define RTC_ISR_TAMP2F_MSK BIT(RTC_ISR_TAMP2F_POS) + +#define RTC_ISR_TAMP1F_POS 12U +#define RTC_ISR_TAMP1F_MSK BIT(RTC_ISR_TAMP1F_POS) + +#define RTC_ISR_TSOVF_POS 11U +#define RTC_ISR_TSOVF_MSK BIT(RTC_ISR_TSOVF_POS) + +#define RTC_ISR_TSF_POS 10U +#define RTC_ISR_TSF_MSK BIT(RTC_ISR_TSF_POS) + +#define RTC_ISR_ALMBF_POS 9U +#define RTC_ISR_ALMBF_MSK BIT(RTC_ISR_ALMBF_POS) + +#define RTC_ISR_ALMAF_POS 8U +#define RTC_ISR_ALMAF_MSK BIT(RTC_ISR_ALMAF_POS) + +#define RTC_ISR_YRF_POS 5U +#define RTC_ISR_YRF_MSK BIT(RTC_ISR_YRF_POS) + +#define RTC_ISR_MONF_POS 4U +#define RTC_ISR_MONF_MSK BIT(RTC_ISR_MONF_POS) + +#define RTC_ISR_DAYF_POS 3U +#define RTC_ISR_DAYF_MSK BIT(RTC_ISR_DAYF_POS) + +#define RTC_ISR_HRF_POS 2U +#define RTC_ISR_HRF_MSK BIT(RTC_ISR_HRF_POS) + +#define RTC_ISR_MINF_POS 1U +#define RTC_ISR_MINF_MSK BIT(RTC_ISR_MINF_POS) + +#define RTC_ISR_SECF_POS 0U +#define RTC_ISR_SECF_MSK BIT(RTC_ISR_SECF_POS) + +/****************** Bit definition for RTC_CALWPR register ************************/ + +#define RTC_CALWPR_WP_POS 0U +#define RTC_CALWPR_WP_MSK BIT(RTC_CALWPR_WP_POS) + +/****************** Bit definition for RTC_CALCON register ************************/ + +#define RTC_CALCON_DCMACC_POS 24U +#define RTC_CALCON_DCMACC_MSK BIT(RTC_CALCON_DCMACC_POS) + +#define RTC_CALCON_ALG_POS 23U +#define RTC_CALCON_ALG_MSK BIT(RTC_CALCON_ALG_POS) + +#define RTC_CALCON_TCP_POSS 20U +#define RTC_CALCON_TCP_POSE 22U +#define RTC_CALCON_TCP_MSK BITS(RTC_CALCON_TCP_POSS,RTC_CALCON_TCP_POSE) + +#define RTC_CALCON_ERR_POS 19U +#define RTC_CALCON_ERR_MSK BIT(RTC_CALCON_ERR_POS) + +#define RTC_CALCON_BUSY_POS 18U +#define RTC_CALCON_BUSY_MSK BIT(RTC_CALCON_BUSY_POS) + +#define RTC_CALCON_TCM_POSS 16U +#define RTC_CALCON_TCM_POSE 17U +#define RTC_CALCON_TCM_MSK BITS(RTC_CALCON_TCM_POSS,RTC_CALCON_TCM_POSE) + +#define RTC_CALCON_CALP_POSS 1U +#define RTC_CALCON_CALP_POSE 3U +#define RTC_CALCON_CALP_MSK BITS(RTC_CALCON_CALP_POSS,RTC_CALCON_CALP_POSE) + +#define RTC_CALCON_CALEN_POS 0U +#define RTC_CALCON_CALEN_MSK BIT(RTC_CALCON_CALEN_POS) + +/****************** Bit definition for RTC_CALDR register ************************/ + +#define RTC_CALDR_DATA_POSS 16U +#define RTC_CALDR_DATA_POSE 31U +#define RTC_CALDR_DATA_MSK BITS(RTC_CALDR_DATA_POSS,RTC_CALDR_DATA_POSE) + +#define RTC_CALDR_VAL_POSS 0U +#define RTC_CALDR_VAL_POSE 15U +#define RTC_CALDR_VAL_MSK BITS(RTC_CALDR_VAL_POSS,RTC_CALDR_VAL_POSE) + +/****************** Bit definition for RTC_TEMPR register ************************/ + +#define RTC_TEMPR_DATA_POSS 16U +#define RTC_TEMPR_DATA_POSE 31U +#define RTC_TEMPR_DATA_MSK BITS(RTC_TEMPR_DATA_POSS,RTC_TEMPR_DATA_POSE) + +#define RTC_TEMPR_VAL_POSS 0U +#define RTC_TEMPR_VAL_POSE 15U +#define RTC_TEMPR_VAL_MSK BITS(RTC_TEMPR_VAL_POSS,RTC_TEMPR_VAL_POSE) + +/****************** Bit definition for RTC_TEMPBDR register ************************/ + +#define RTC_TEMPBDR_VAL_POSS 0U +#define RTC_TEMPBDR_VAL_POSE 15U +#define RTC_TEMPBDR_VAL_MSK BITS(RTC_TEMPBDR_VAL_POSS,RTC_TEMPBDR_VAL_POSE) + +/****************** Bit definition for RTC_BKP register ************************/ + +#define RTC_BKP_BKP_POSS 0U +#define RTC_BKP_BKP_POSE 31U +#define RTC_BKP_BKP_MSK BITS(RTC_BKP_BKP_POSS,RTC_BKP_BKP_POSE) + +typedef struct +{ + __IO uint32_t WPR; + __IO uint32_t CON; + __IO uint32_t PSR; + __IO uint32_t TAMPCON; + __IO uint32_t TIME; + __IO uint32_t DATE; + __IO uint32_t SSEC; + __IO uint32_t WUMAT; + __IO uint32_t ALMA; + __IO uint32_t ALMB; + __IO uint32_t ALMASSEC; + __IO uint32_t ALMBSSEC; + __I uint32_t TSTIME; + __I uint32_t TSDATE; + __I uint32_t TSSSEC; + __O uint32_t SSECTR; + __IO uint32_t IER; + __I uint32_t IFR; + __O uint32_t IFCR; + __I uint32_t ISR; + __IO uint32_t CALWPR; + __IO uint32_t CALCON; + __IO uint32_t CALDR; + __IO uint32_t TEMPR; + __IO uint32_t LTCAR; + __IO uint32_t LTCBR; + __IO uint32_t LTCCR; + __IO uint32_t LTCDR; + __IO uint32_t LTCER; + __IO uint32_t HTCAR; + __IO uint32_t HTCBR; + __IO uint32_t HTCCR; + __IO uint32_t HTCDR; + __IO uint32_t HTCER; + __IO uint32_t TEMPBDR; + __IO uint32_t LTAXR; + __IO uint32_t HTAXR; + uint32_t RESERVED0[27] ; + __IO uint32_t BKPR[32]; +} RTC_TypeDef; + +/****************** Bit definition for TIMER_CON1 register ************************/ + +#define TIMER_CON1_DBGSEL_POSS 15U +#define TIMER_CON1_DBGSEL_MSK BIT(TIMER_CON1_DBGSEL_POSS) + +#define TIMER_CON1_OCCISS_POSS 11U +#define TIMER_CON1_OCCISS_POSE 13U +#define TIMER_CON1_OCCISS_MSK BITS(TIMER_CON1_OCCISS_POSS,TIMER_CON1_OCCISS_POSE) + +#define TIMER_CON1_OCCISP_POSS 10U +#define TIMER_CON1_OCCISP_MSK BIT(TIMER_CON1_OCCISP_POSS) + +#define TIMER_CON1_DFCKSEL_POSS 8U +#define TIMER_CON1_DFCKSEL_POSE 9U +#define TIMER_CON1_DFCKSEL_MSK BITS(TIMER_CON1_DFCKSEL_POSS,TIMER_CON1_DFCKSEL_POSE) + +#define TIMER_CON1_ARPEN_POS 7U +#define TIMER_CON1_ARPEN_MSK BIT(TIMER_CON1_ARPEN_POS) + +#define TIMER_CON1_CMSEL_POSS 5U +#define TIMER_CON1_CMSEL_POSE 6U +#define TIMER_CON1_CMSEL_MSK BITS(TIMER_CON1_CMSEL_POSS,TIMER_CON1_CMSEL_POSE) + +#define TIMER_CON1_DIRSEL_POS 4U +#define TIMER_CON1_DIRSEL_MSK BIT(TIMER_CON1_DIRSEL_POS) + +#define TIMER_CON1_SPMEN_POS 3U +#define TIMER_CON1_SPMEN_MSK BIT(TIMER_CON1_SPMEN_POS) + +#define TIMER_CON1_UERSEL_POS 2U +#define TIMER_CON1_UERSEL_MSK BIT(TIMER_CON1_UERSEL_POS) + +#define TIMER_CON1_DISUE_POS 1U +#define TIMER_CON1_DISUE_MSK BIT(TIMER_CON1_DISUE_POS) + +#define TIMER_CON1_CNTEN_POS 0U +#define TIMER_CON1_CNTEN_MSK BIT(TIMER_CON1_CNTEN_POS) + +/****************** Bit definition for TIMER_CON2 register ************************/ + +#define TIMER_CON2_OISS4_POS 14U +#define TIMER_CON2_OISS4_MSK BIT(TIMER_CON2_OISS4_POS) + +#define TIMER_CON2_OISS3N_POS 13U +#define TIMER_CON2_OISS3N_MSK BIT(TIMER_CON2_OISS3N_POS) + +#define TIMER_CON2_OISS3_POS 12U +#define TIMER_CON2_OISS3_MSK BIT(TIMER_CON2_OISS3_POS) + +#define TIMER_CON2_OISS2N_POS 11U +#define TIMER_CON2_OISS2N_MSK BIT(TIMER_CON2_OISS2N_POS) + +#define TIMER_CON2_OISS2_POS 10U +#define TIMER_CON2_OISS2_MSK BIT(TIMER_CON2_OISS2_POS) + +#define TIMER_CON2_OISS1N_POS 9U +#define TIMER_CON2_OISS1N_MSK BIT(TIMER_CON2_OISS1N_POS) + +#define TIMER_CON2_OISS1_POS 8U +#define TIMER_CON2_OISS1_MSK BIT(TIMER_CON2_OISS1_POS) + +#define TIMER_CON2_I1FSEL_POS 7U +#define TIMER_CON2_I1FSEL_MSK BIT(TIMER_CON2_I1FSEL_POS) + +#define TIMER_CON2_TRGOSEL_POSS 4U +#define TIMER_CON2_TRGOSEL_POSE 6U +#define TIMER_CON2_TRGOSEL_MSK BITS(TIMER_CON2_TRGOSEL_POSS,TIMER_CON2_TRGOSEL_POSE) + +#define TIMER_CON2_CCDMASEL_POS 3U +#define TIMER_CON2_CCDMASEL_MSK BIT(TIMER_CON2_CCDMASEL_POS) + +#define TIMER_CON2_CCUSEL_POS 2U +#define TIMER_CON2_CCUSEL_MSK BIT(TIMER_CON2_CCUSEL_POS) + +#define TIMER_CON2_CCPCEN_POS 0U +#define TIMER_CON2_CCPCEN_MSK BIT(TIMER_CON2_CCPCEN_POS) + +/****************** Bit definition for TIMER_SMCON register ************************/ + +#define TIMER_SMCON_ETPOL_POS 15U +#define TIMER_SMCON_ETPOL_MSK BIT(TIMER_SMCON_ETPOL_POS) + +#define TIMER_SMCON_ECM2EN_POS 14U +#define TIMER_SMCON_ECM2EN_MSK BIT(TIMER_SMCON_ECM2EN_POS) + +#define TIMER_SMCON_ETPSEL_POSS 12U +#define TIMER_SMCON_ETPSEL_POSE 13U +#define TIMER_SMCON_ETPSEL_MSK BITS(TIMER_SMCON_ETPSEL_POSS,TIMER_SMCON_ETPSEL_POSE) + +#define TIMER_SMCON_ETFLT_POSS 8U +#define TIMER_SMCON_ETFLT_POSE 11U +#define TIMER_SMCON_ETFLT_MSK BITS(TIMER_SMCON_ETFLT_POSS,TIMER_SMCON_ETFLT_POSE) + +#define TIMER_SMCON_MSCFG_POS 7U +#define TIMER_SMCON_MSCFG_MSK BIT(TIMER_SMCON_MSCFG_POS) + +#define TIMER_SMCON_TSSEL_POSS 4U +#define TIMER_SMCON_TSSEL_POSE 6U +#define TIMER_SMCON_TSSEL_MSK BITS(TIMER_SMCON_TSSEL_POSS,TIMER_SMCON_TSSEL_POSE) + +#define TIMER_SMCON_CHCSEL_POS 3U +#define TIMER_SMCON_CHCSEL_MASK BIT(TIMER_SMCON_CHCSEL_POS) + +#define TIMER_SMCON_SMODS_POSS 0U +#define TIMER_SMCON_SMODS_POSE 2U +#define TIMER_SMCON_SMODS_MSK BITS(TIMER_SMCON_SMODS_POSS,TIMER_SMCON_SMODS_POSE) + +/****************** Bit definition for TIMER_IER register ************************/ + +#define TIMER_IER_BRKIT_POS 7U +#define TIMER_IER_BRKIT_MSK BIT(TIMER_IER_BRKIT_POS) + +#define TIMER_IER_TRGIT_POS 6U +#define TIMER_IER_TRGIT_MSK BIT(TIMER_IER_TRGIT_POS) + +#define TIMER_IER_COMIT_POS 5U +#define TIMER_IER_COMIT_MSK BIT(TIMER_IER_COMIT_POS) + +#define TIMER_IER_CC4IT_POS 4U +#define TIMER_IER_CC4IT_MSK BIT(TIMER_IER_CC4IT_POS) + +#define TIMER_IER_CC3IT_POS 3U +#define TIMER_IER_CC3IT_MSK BIT(TIMER_IER_CC3IT_POS) + +#define TIMER_IER_CC2IT_POS 2U +#define TIMER_IER_CC2IT_MSK BIT(TIMER_IER_CC2IT_POS) + +#define TIMER_IER_CC1IT_POS 1U +#define TIMER_IER_CC1IT_MSK BIT(TIMER_IER_CC1IT_POS) + +#define TIMER_IER_UIT_POS 0U +#define TIMER_IER_UIT_MSK BIT(TIMER_IER_UIT_POS) + +/****************** Bit definition for TIMER_IDR register ************************/ +#define TIMER_IDR_BRKI_POS 7U +#define TIMER_IDR_BRKI_MSK BIT(TIMER_IDR_BRKI_POS) + +#define TIMER_IDR_TRGI_POS 6U +#define TIMER_IDR_TRGI_MSK BIT(TIMER_IDR_TRGI_POS) + +#define TIMER_IDR_COMI_POS 5U +#define TIMER_IDR_COMI_MSK BIT(TIMER_IDR_COMI_POS) + +#define TIMER_IDR_CC4I_POS 4U +#define TIMER_IDR_CC4I_MSK BIT(TIMER_IDR_CC4I_POS) + +#define TIMER_IDR_CC3I_POS 3U +#define TIMER_IDR_CC3I_MSK BIT(TIMER_IDR_CC3I_POS) + +#define TIMER_IDR_CC2I_POS 2U +#define TIMER_IDR_CC2I_MSK BIT(TIMER_IDR_CC2I_POS) + +#define TIMER_IDR_CC1I_POS 1U +#define TIMER_IDR_CC1I_MSK BIT(TIMER_IDR_CC1I_POS) + +#define TIMER_IDR_UI_POS 0U +#define TIMER_IDR_UI_MSK BIT(TIMER_IDR_UI_POS) + +/****************** Bit definition for TIMER_IVS register ************************/ + +#define TIMER_IVS_BKI_POS 7U +#define TIMER_IVS_BKI_MSK BIT(TIMER_IVS_BKI_POS) + +#define TIMER_IVS_TRGI_POS 6U +#define TIMER_IVS_TRGI_MSK BIT(TIMER_IVS_TRGI_POS) + +#define TIMER_IVS_COMI_POS 5U +#define TIMER_IVS_COMI_MSK BIT(TIMER_IVS_COMI_POS) + +#define TIMER_IVS_CC4I_POS 4U +#define TIMER_IVS_CC4I_MSK BIT(TIMER_IVS_CC4I_POS) + +#define TIMER_IVS_CC3I_POS 3U +#define TIMER_IVS_CC3I_MSK BIT(TIMER_IVS_CC3I_POS) + +#define TIMER_IVS_CC2I_POS 2U +#define TIMER_IVS_CC2I_MSK BIT(TIMER_IVS_CC2I_POS) + +#define TIMER_IVS_CC1I_POS 1U +#define TIMER_IVS_CC1I_MSK BIT(TIMER_IVS_CC1I_POS) + +#define TIMER_IVS_UEI_POS 0U +#define TIMER_IVS_UEI_MSK BIT(TIMER_IVS_UEI_POS) + +/****************** Bit definition for TIMER_RIF register ************************/ + +#define TIMER_RIF_CH4OVIF_POS 12U +#define TIMER_RIF_CH4OVIF_MSK BIT(TIMER_RIF_CH4OVIF_POS) + +#define TIMER_RIF_CH3OVIF_POS 11U +#define TIMER_RIF_CH3OVIF_MSK BIT(TIMER_RIF_CH3OVIF_POS) + +#define TIMER_RIF_CH2OVIF_POS 10U +#define TIMER_RIF_CH2OVIF_MSK BIT(TIMER_RIF_CH2OVIF_POS) + +#define TIMER_RIF_CH1OVIF_POS 9U +#define TIMER_RIF_CH1OVIF_MSK BIT(TIMER_RIF_CH1OVIF_POS) + +#define TIMER_RIF_BRKIF_POS 7U +#define TIMER_RIF_BRKIF_MSK BIT(TIMER_RIF_BRKIF_POS) + +#define TIMER_RIF_TRGIF_POS 6U +#define TIMER_RIF_TRGIF_MSK BIT(TIMER_RIF_TRGIF_POS) + +#define TIMER_RIF_COMIF_POS 5U +#define TIMER_RIF_COMIF_MSK BIT(TIMER_RIF_COMIF_POS) + +#define TIMER_RIF_CH4IF_POS 4U +#define TIMER_RIF_CH4IF_MSK BIT(TIMER_RIF_CH4IF_POS) + +#define TIMER_RIF_CH3IF_POS 3U +#define TIMER_RIF_CH3IF_MSK BIT(TIMER_RIF_CH3IF_POS) + +#define TIMER_RIF_CH2IF_POS 2U +#define TIMER_RIF_CH2IF_MSK BIT(TIMER_RIF_CH2IF_POS) + +#define TIMER_RIF_CH1IF_POS 1U +#define TIMER_RIF_CH1IF_MSK BIT(TIMER_RIF_CH1IF_POS) + +#define TIMER_RIF_UEVTIF_POS 0U +#define TIMER_RIF_UEVTIF_MSK BIT(TIMER_RIF_UEVTIF_POS) + +/****************** Bit definition for TIMER_IFM register ************************/ + +#define TIMER_IFM_BRKIM_POS 7U +#define TIMER_IFM_BRKIM_MSK BIT(TIMER_IFM_BRKIM_POS) + +#define TIMER_IFM_TRGI_POS 6U +#define TIMER_IFM_TRGI_MSK BIT(TIMER_IFM_TRGI_POS) + +#define TIMER_IFM_COMI_POS 5U +#define TIMER_IFM_COMI_MSK BIT(TIMER_IFM_COMI_POS) + +#define TIMER_IFM_CH4CCI_POS 4U +#define TIMER_IFM_CH4CCI_MSK BIT(TIMER_IFM_CH4CCI_POS) + +#define TIMER_IFM_CH3CCI_POS 3U +#define TIMER_IFM_CH3CCI_MSK BIT(TIMER_IFM_CH3CCI_POS) + +#define TIMER_IFM_CH2CCI_POS 2U +#define TIMER_IFM_CH2CCI_MSK BIT(TIMER_IFM_CH2CCI_POS) + +#define TIMER_IFM_CH1CCI_POS 1U +#define TIMER_IFM_CH1CCI_MSK BIT(TIMER_IFM_CH1CCI_POS) + +#define TIMER_IFM_UEI_POS 0U +#define TIMER_IFM_UEI_MSK BIT(TIMER_IFM_UEI_POS) + +/****************** Bit definition for TIMER_ICR register ************************/ + +#define TIMER_ICR_BRKIC_POS 7U +#define TIMER_ICR_BRKIC_MSK BIT(TIMER_ICR_BRKIC_POS) + +#define TIMER_ICR_TRGIC_POS 6U +#define TIMER_ICR_TRGIC_MSK BIT(TIMER_ICR_TRGIC_POS) + +#define TIMER_ICR_COMIC_POS 5U +#define TIMER_ICR_COMIC_MSK BIT(TIMER_ICR_COMIC_POS) + +#define TIMER_ICR_CH4CCIC_POS 4U +#define TIMER_ICR_CH4CCIC_MSK BIT(TIMER_ICR_CH4CCIC_POS) + +#define TIMER_ICR_CH3CCIC_POS 3U +#define TIMER_ICR_CH3CCIC_MSK BIT(TIMER_ICR_CH3CCIC_POS) + +#define TIMER_ICR_CH2CCIC_POS 2U +#define TIMER_ICR_CH2CCIC_MSK BIT(TIMER_ICR_CH2CCIC_POS) + +#define TIMER_ICR_CH1CCIC_POS 1U +#define TIMER_ICR_CH1CCIC_MSK BIT(TIMER_ICR_CH1CCIC_POS) + +#define TIMER_ICR_UEIC_POS 0U +#define TIMER_ICR_UEIC_MSK BIT(TIMER_ICR_UEIC_POS) + +/****************** Bit definition for TIMER_SGE register ************************/ + +#define TIMER_SGE_SGBRK_POS 7U +#define TIMER_SGE_SGBRK_MSK BIT(TIMER_SGE_SGBRK_POS) + +#define TIMER_SGE_SGTRG_POS 6U +#define TIMER_SGE_SGTRG_MSK BIT(TIMER_SGE_SGTRG_POS) + +#define TIMER_SGE_SGCOM_POS 5U +#define TIMER_SGE_SGCOM_MSK BIT(TIMER_SGE_SGCOM_POS) + +#define TIMER_SGE_SGCC4E_POS 4U +#define TIMER_SGE_SGCC4E_MSK BIT(TIMER_SGE_SGCC4E_POS) + +#define TIMER_SGE_SGCC3E_POS 3U +#define TIMER_SGE_SGCC3E_MSK BIT(TIMER_SGE_SGCC3E_POS) + +#define TIMER_SGE_SGCC2E_POS 2U +#define TIMER_SGE_SGCC2E_MSK BIT(TIMER_SGE_SGCC2E_POS) + +#define TIMER_SGE_SGCC1E_POS 1U +#define TIMER_SGE_SGCC1E_MSK BIT(TIMER_SGE_SGCC1E_POS) + +#define TIMER_SGE_SGU_POS 0U +#define TIMER_SGE_SGU_MSK BIT(TIMER_SGE_SGU_POS) + +/****************** Bit definition for TIMER_CHMR1 register ************************/ +/* Output */ +#define TIMER_CHMR1_CH2OCLREN_POS 15U +#define TIMER_CHMR1_CH2OCLREN_MSK BIT(TIMER_CHMR1_CH2OCLREN_POS) + +#define TIMER_CHMR1_CH2OMOD_POSS 12U +#define TIMER_CHMR1_CH2OMOD_POSE 14U +#define TIMER_CHMR1_CH2OMOD_MSK BITS(TIMER_CHMR1_CH2OMOD_POSS,TIMER_CHMR1_CH2OMOD_POSE) + +#define TIMER_CHMR1_CH2OPEN_POS 11U +#define TIMER_CHMR1_CH2OPEN_MSK BIT(TIMER_CHMR1_CH2OPEN_POS) + +#define TIMER_CHMR1_CH2OFEN_POS 10U +#define TIMER_CHMR1_CH2OFEN_MSK BIT(TIMER_CHMR1_CH2OFEN_POS) + +#define TIMER_CHMR1_CC2SSEL_POSS 8U +#define TIMER_CHMR1_CC2SSEL_POSE 9U +#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) + +#define TIMER_CHMR1_CH1OCLREN_POS 7U +#define TIMER_CHMR1_CH1OCLREN_MSK BIT(TIMER_CHMR1_CH1OCLREN_POS) + +#define TIMER_CHMR1_CH1OMOD_POSS 4U +#define TIMER_CHMR1_CH1OMOD_POSE 6U +#define TIMER_CHMR1_CH1OMOD_MSK BITS(TIMER_CHMR1_CH1OMOD_POSS,TIMER_CHMR1_CH1OMOD_POSE) + +#define TIMER_CHMR1_CH1OPREN_POS 3U +#define TIMER_CHMR1_CH1OPREN_MSK BIT(TIMER_CHMR1_CH1OPREN_POS) + +#define TIMER_CHMR1_CH1OHSEN_POS 2U +#define TIMER_CHMR1_CH1OHSEN_MSK BIT(TIMER_CHMR1_CH1OHSEN_POS) + +#define TIMER_CHMR1_CC1SSEL_POSS 0U +#define TIMER_CHMR1_CC1SSEL_POSE 1U +#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) + +/* Input */ +#define TIMER_CHMR1_I2FLT_POSS 12U +#define TIMER_CHMR1_I2FLT_POSE 15U +#define TIMER_CHMR1_I2FLT_MSK BITS(TIMER_CHMR1_I2FLT_POSS,TIMER_CHMR1_I2FLT_POSE) + +#define TIMER_CHMR1_IC2PRES_POSS 10U +#define TIMER_CHMR1_IC2PRES_POSE 11U +#define TIMER_CHMR1_IC2PRES_MSK BITS(TIMER_CHMR1_IC2PRES_POSS,TIMER_CHMR1_IC2PRES_POSE) + +#define TIMER_CHMR1_CC2SSEL_POSS 8U +#define TIMER_CHMR1_CC2SSEL_POSE 9U +#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) + +#define TIMER_CHMR1_I1FLT_POSS 4U +#define TIMER_CHMR1_I1FLT_POSE 7U +#define TIMER_CHMR1_I1FLT_MSK BITS(TIMER_CHMR1_I1FLT_POSS,TIMER_CHMR1_I1FLT_POSE) + +#define TIMER_CHMR1_IC1PRES_POSS 2U +#define TIMER_CHMR1_IC1PRES_POSE 3U +#define TIMER_CHMR1_IC1PRES_MSK BITS(TIMER_CHMR1_IC1PRES_POSS,TIMER_CHMR1_IC1PRES_POSE) + +#define TIMER_CHMR1_CC1SSEL_POSS 0U +#define TIMER_CHMR1_CC1SSEL_POSE 1U +#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) + +/****************** Bit definition for TIMER_CHMR2 register ************************/ +/* Output */ +#define TIMER_CHMR2_CH4OCLREN_POS 15U +#define TIMER_CHMR2_CH4OCLREN_MSK BIT(TIMER_CHMR2_CH4OCLREN_POS) + +#define TIMER_CHMR2_CH4OMOD_POSS 12U +#define TIMER_CHMR2_CH4OMOD_POSE 14U +#define TIMER_CHMR2_CH4OMOD_MSK BITS(TIMER_CHMR2_CH4OMOD_POSS,TIMER_CHMR2_CH4OMOD_POSE) + +#define TIMER_CHMR2_CH4OPEN_POS 11U +#define TIMER_CHMR2_CH4OPEN_MSK BIT(TIMER_CHMR2_CH4OPEN_POS) + +#define TIMER_CHMR2_CH4OHSEN_POS 10U +#define TIMER_CHMR2_CH4OHSEN_MSK BIT(TIMER_CHMR2_CH4OHSEN_POS) + +#define TIMER_CHMR2_CC4SSEL_POSS 8U +#define TIMER_CHMR2_CC4SSEL_POSE 9U +#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) + +#define TIMER_CHMR2_CH3OCLREN_POS 7U +#define TIMER_CHMR2_CH3OCLREN_MSK BIT(TIMER_CHMR2_CH3OCLREN_POS) + +#define TIMER_CHMR2_CH3OMOD_POSS 4U +#define TIMER_CHMR2_CH3OMOD_POSE 6U +#define TIMER_CHMR2_CH3OMOD_MSK BITS(TIMER_CHMR2_CH3OMOD_POSS,TIMER_CHMR2_CH3OMOD_POSE) + +#define TIMER_CHMR2_CH3OPEN_POS 3U +#define TIMER_CHMR2_CH3OPEN_MSK BIT(TIMER_CHMR2_CH3OPEN_POS) + +#define TIMER_CHMR2_CH3OFEN_POS 2U +#define TIMER_CHMR2_CH3OFEN_MSK BIT(TIMER_CHMR2_CH3OFEN_POS) + +#define TIMER_CHMR2_CC3SSEL_POSS 0U +#define TIMER_CHMR2_CC3SSEL_POSE 1U +#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) + +/* Input */ +#define TIMER_CHMR2_I4FLT_POSS 12U +#define TIMER_CHMR2_I4FLT_POSE 15U +#define TIMER_CHMR2_I4FLT_MSK BITS(TIMER_CHMR2_I4FLT_POSS,TIMER_CHMR2_I4FLT_POSE) + +#define TIMER_CHMR2_IC4PRES_POSS 10U +#define TIMER_CHMR2_IC4PRES_POSE 11U +#define TIMER_CHMR2_IC4PRES_MSK BITS(TIMER_CHMR2_IC4PRES_POSS,TIMER_CHMR2_IC4PRES_POSE) + +#define TIMER_CHMR2_CC4SSEL_POSS 8U +#define TIMER_CHMR2_CC4SSEL_POSE 9U +#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) + +#define TIMER_CHMR2_I3FLT_POSS 4U +#define TIMER_CHMR2_I3FLT_POSE 7U +#define TIMER_CHMR2_I3FLT_MSK BITS(TIMER_CHMR2_I3FLT_POSS,TIMER_CHMR2_I3FLT_POSE) + +#define TIMER_CHMR2_IC3PRES_POSS 2U +#define TIMER_CHMR2_IC3PRES_POSE 3U +#define TIMER_CHMR2_IC3PRES_MSK BITS(TIMER_CHMR2_IC3PRES_POSS,TIMER_CHMR2_IC3PRES_POSE) + +#define TIMER_CHMR2_CC3SSEL_POSS 0U +#define TIMER_CHMR2_CC3SSEL_POSE 1U +#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) + +/****************** Bit definition for TIMER_CCEP register ************************/ + +#define TIMER_CCEP_CC4POL_POS 13U +#define TIMER_CCEP_CC4POL_MSK BIT(TIMER_CCEP_CC4POL_POS) + +#define TIMER_CCEP_CC4EN_POS 12U +#define TIMER_CCEP_CC4EN_MSK BIT(TIMER_CCEP_CC4EN_POS) + +#define TIMER_CCEP_CC3NPOL_POS 11U +#define TIMER_CCEP_CC3NPOL_MSK BIT(TIMER_CCEP_CC3NPOL_POS) + +#define TIMER_CCEP_CC3NEN_POS 10U +#define TIMER_CCEP_CC3NEN_MSK BIT(TIMER_CCEP_CC3NEN_POS) + +#define TIMER_CCEP_CC3POL_POS 9U +#define TIMER_CCEP_CC3POL_MSK BIT(TIMER_CCEP_CC3POL_POS) + +#define TIMER_CCEP_CC3EN_POS 8U +#define TIMER_CCEP_CC3EN_MSK BIT(TIMER_CCEP_CC3EN_POS) + +#define TIMER_CCEP_CC2NPOL_POS 7U +#define TIMER_CCEP_CC2NPOL_MSK BIT(TIMER_CCEP_CC2NPOL_POS) + +#define TIMER_CCEP_CC2NEN_POS 6U +#define TIMER_CCEP_CC2NEN_MSK BIT(TIMER_CCEP_CC2NEN_POS) + +#define TIMER_CCEP_CC2POL_POS 5U +#define TIMER_CCEP_CC2POL_MSK BIT(TIMER_CCEP_CC2POL_POS) + +#define TIMER_CCEP_CC2EN_POS 4U +#define TIMER_CCEP_CC2EN_MSK BIT(TIMER_CCEP_CC2EN_POS) + +#define TIMER_CCEP_CC1NPOL_POS 3U +#define TIMER_CCEP_CC1NPOL_MSK BIT(TIMER_CCEP_CC1NPOL_POS) + +#define TIMER_CCEP_CC1NEN_POS 2U +#define TIMER_CCEP_CC1NEN_MSK BIT(TIMER_CCEP_CC1NEN_POS) + +#define TIMER_CCEP_CC1POL_POS 1U +#define TIMER_CCEP_CC1POL_MSK BIT(TIMER_CCEP_CC1POL_POS) + +#define TIMER_CCEP_CC1EN_POS 0U +#define TIMER_CCEP_CC1EN_MSK BIT(TIMER_CCEP_CC1EN_POS) + +/****************** Bit definition for TIMER_COUNT register ************************/ + +#define TIMER_COUNT_CNTV_POSS 0U +#define TIMER_COUNT_CNTV_POSE 15U +#define TIMER_COUNT_CNTV_MSK BITS(TIMER_COUNT_CNTV_POSS,TIMER_COUNT_CNTV_POSE) + +/****************** Bit definition for TIMER_PRES register ************************/ + +#define TIMER_PRES_PSCV_POSS 0U +#define TIMER_PRES_PSCV_POSE 15U +#define TIMER_PRES_PSCV_MSK BITS(TIMER_PRES_PSCV_POSS,TIMER_PRES_PSCV_POSE) + +/****************** Bit definition for TIMER_AR register ************************/ + +#define TIMER_AR_ARRV_POSS 0U +#define TIMER_AR_ARRV_POSE 15U +#define TIMER_AR_ARRV_MSK BITS(TIMER_AR_ARRV_POSS,TIMER_AR_ARRV_POSE) + +/****************** Bit definition for TIMER_REPAR register ************************/ + +#define TIMER_REPAR_REPV_POSS 0U +#define TIMER_REPAR_REPV_POSE 7U +#define TIMER_REPAR_REPV_MSK BITS(TIMER_REPAR_REPV_POSS,TIMER_REPAR_REPV_POSE) + +/****************** Bit definition for TIMER_CCVAL1 register ************************/ + +#define TIMER_CCVAL1_CCRV1_POSS 0U +#define TIMER_CCVAL1_CCRV1_POSE 15U +#define TIMER_CCVAL1_CCRV1_MSK BITS(TIMER_CCVAL1_CCRV1_POSS,TIMER_CCVAL1_CCRV1_POSE) + +/****************** Bit definition for TIMER_CCVAL2 register ************************/ + +#define TIMER_CCVAL2_CCRV2_POSS 0U +#define TIMER_CCVAL2_CCRV2_POSE 15U +#define TIMER_CCVAL2_CCRV2_MSK BITS(TIMER_CCVAL2_CCRV2_POSS,TIMER_CCVAL2_CCRV2_POSE) + +/****************** Bit definition for TIMER_CCVAL3 register ************************/ + +#define TIMER_CCVAL3_CCRV3_POSS 0U +#define TIMER_CCVAL3_CCRV3_POSE 15U +#define TIMER_CCVAL3_CCRV3_MSK BITS(TIMER_CCVAL3_CCRV3_POSS,TIMER_CCVAL3_CCRV3_POSE) + +/****************** Bit definition for TIMER_CCVAL4 register ************************/ + +#define TIMER_CCVAL4_CCRV4_POSS 0U +#define TIMER_CCVAL4_CCRV4_POSE 15U +#define TIMER_CCVAL4_CCRV4_MSK BITS(TIMER_CCVAL4_CCRV4_POSS,TIMER_CCVAL4_CCRV4_POSE) + +/****************** Bit definition for TIMER_BDCFG register ************************/ + +#define TIMER_BDCFG_GOEN_POS 15U +#define TIMER_BDCFG_GOEN_MSK BIT(TIMER_BDCFG_GOEN_POS) + +#define TIMER_BDCFG_AOEN_POS 14U +#define TIMER_BDCFG_AOEN_MSK BIT(TIMER_BDCFG_AOEN_POS) + +#define TIMER_BDCFG_BRKP_POS 13U +#define TIMER_BDCFG_BRKP_MSK BIT(TIMER_BDCFG_BRKP_POS) + +#define TIMER_BDCFG_BRKEN_POS 12U +#define TIMER_BDCFG_BRKEN_MSK BIT(TIMER_BDCFG_BRKEN_POS) + +#define TIMER_BDCFG_OFFSSR_POS 11U +#define TIMER_BDCFG_OFFSSR_MSK BIT(TIMER_BDCFG_OFFSSR_POS) + +#define TIMER_BDCFG_OFFSSI_POS 10U +#define TIMER_BDCFG_OFFSSI_MSK BIT(TIMER_BDCFG_OFFSSI_POS) + +#define TIMER_BDCFG_LOCKLVL_POSS 8U +#define TIMER_BDCFG_LOCKLVL_POSE 9U +#define TIMER_BDCFG_LOCKLVL_MSK BITS(TIMER_BDCFG_LOCKLVL_POSS,TIMER_BDCFG_LOCKLVL_POSE) + +#define TIMER_BDCFG_DT_POSS 0U +#define TIMER_BDCFG_DT_POSE 7U +#define TIMER_BDCFG_DT_MSK BITS(TIMER_BDCFG_DT_POSS,TIMER_BDCFG_DT_POSE) + +/****************** Bit definition for TIMER_DMAEN register ************************/ + +#define TIMER_DMAEN_TRGDMA_POS 6U +#define TIMER_DMAEN_TRGDMA_MSK BIT(TIMER_DMAEN_TRGDMA_POS) + +#define TIMER_DMAEN_COMD_POS 5U +#define TIMER_DMAEN_COMD_MSK BIT(TIMER_DMAEN_COMD_POS) + +#define TIMER_DMAEN_CC4D_POS 4U +#define TIMER_DMAEN_CC4D_MSK BIT(TIMER_DMAEN_CC4D_POS) + +#define TIMER_DMAEN_CC3D_POS 3U +#define TIMER_DMAEN_CC3D_MSK BIT(TIMER_DMAEN_CC3D_POS) + +#define TIMER_DMAEN_CC2D_POS 2U +#define TIMER_DMAEN_CC2D_MSK BIT(TIMER_DMAEN_CC2D_POS) + +#define TIMER_DMAEN_CC1D_POS 1U +#define TIMER_DMAEN_CC1D_MSK BIT(TIMER_DMAEN_CC1D_POS) + +#define TIMER_DMAEN_UD_POS 0U +#define TIMER_DMAEN_UD_MSK BIT(TIMER_DMAEN_UD_POS) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t SMCON; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + __O uint32_t SGE; + __IO uint32_t CHMR1; + __IO uint32_t CHMR2; + __IO uint32_t CCEP; + __IO uint32_t COUNT; + __IO uint32_t PRES; + __IO uint32_t AR; + __IO uint32_t REPAR; + __IO uint32_t CCVAL1; + __IO uint32_t CCVAL2; + __IO uint32_t CCVAL3; + __IO uint32_t CCVAL4; + __IO uint32_t BDCFG; + __IO uint32_t DMAEN; +} TIMER_TypeDef; + +#ifdef ES32F36xx +#define TIMER0 AD16C4T0 +#define TIMER1 AD16C4T1 +#define TIMER2 GP32C4T0 +#define TIMER3 GP32C4T1 +#define TIMER4 BS16T0 +#define TIMER5 BS16T1 +#define TIMER6 GP16C4T0 +#define TIMER7 GP16C4T1 +#else +#define TIMER0 GP16C4T0 +#define TIMER1 GP16C4T1 +#define TIMER2 GP32C4T0 +#define TIMER3 GP32C4T1 +#define TIMER4 BS16T0 +#define TIMER5 BS16T1 +#define TIMER6 GP16C4T2 +#define TIMER7 GP16C4T3 +#endif + +/****************** Bit definition for USART_STAT register ************************/ + +#define USART_STAT_CTSIF_POS 9U +#define USART_STAT_CTSIF_MSK BIT(USART_STAT_CTSIF_POS) + +#define USART_STAT_TXEMPIF_POS 7U +#define USART_STAT_TXEMPIF_MSK BIT(USART_STAT_TXEMPIF_POS) + +#define USART_STAT_TXCIF_POS 6U +#define USART_STAT_TXCIF_MSK BIT(USART_STAT_TXCIF_POS) + +#define USART_STAT_RXNEIF_POS 5U +#define USART_STAT_RXNEIF_MSK BIT(USART_STAT_RXNEIF_POS) + +#define USART_STAT_IDLEIF_POS 4U +#define USART_STAT_IDLEIF_MSK BIT(USART_STAT_IDLEIF_POS) + +#define USART_STAT_OVRIF_POS 3U +#define USART_STAT_OVRIF_MSK BIT(USART_STAT_OVRIF_POS) + +#define USART_STAT_NDETIF_POS 2U +#define USART_STAT_NDETIF_MSK BIT(USART_STAT_NDETIF_POS) + +#define USART_STAT_FERRIF_POS 1U +#define USART_STAT_FERRIF_MSK BIT(USART_STAT_FERRIF_POS) + +#define USART_STAT_PERRIF_POS 0U +#define USART_STAT_PERRIF_MSK BIT(USART_STAT_PERRIF_POS) + +/****************** Bit definition for USART_DATA register ************************/ + +#define USART_DATA_VAL_POSS 0U +#define USART_DATA_VAL_POSE 8U +#define USART_DATA_VAL_MSK BITS(USART_DATA_VAL_POSS,USART_DATA_VAL_POSE) + +/****************** Bit definition for USART_BAUDCON register ************************/ + +#define USART_BAUDCON_DIV_M_POSS 4U +#define USART_BAUDCON_DIV_M_POSE 15U +#define USART_BAUDCON_DIV_M_MSK BITS(USART_BAUDCON_DIV_M_POSS,USART_BAUDCON_DIV_M_POSE) + +#define USART_BAUDCON_DIV_F_POSS 0U +#define USART_BAUDCON_DIV_F_POSE 3U +#define USART_BAUDCON_DIV_F_MSK BITS(USART_BAUDCON_DIV_F_POSS,USART_BAUDCON_DIV_F_POSE) + +/****************** Bit definition for USART_CON0 register ************************/ + +#define USART_CON0_EN_POS 13U +#define USART_CON0_EN_MSK BIT(USART_CON0_EN_POS) + +#define USART_CON0_DLEN_POS 12U +#define USART_CON0_DLEN_MSK BIT(USART_CON0_DLEN_POS) + +#define USART_CON0_WKMOD_POS 11U +#define USART_CON0_WKMOD_MSK BIT(USART_CON0_WKMOD_POS) + +#define USART_CON0_PEN_POS 10U +#define USART_CON0_PEN_MSK BIT(USART_CON0_PEN_POS) + +#define USART_CON0_PSEL_POS 9U +#define USART_CON0_PSEL_MSK BIT(USART_CON0_PSEL_POS) + +#define USART_CON0_PERRIE_POS 8U +#define USART_CON0_PERRIE_MSK BIT(USART_CON0_PERRIE_POS) + +#define USART_CON0_TXEMPIE_POS 7U +#define USART_CON0_TXEMPIE_MSK BIT(USART_CON0_TXEMPIE_POS) + +#define USART_CON0_TXCIE_POS 6U +#define USART_CON0_TXCIE_MSK BIT(USART_CON0_TXCIE_POS) + +#define USART_CON0_RXNEIE_POS 5U +#define USART_CON0_RXNEIE_MSK BIT(USART_CON0_RXNEIE_POS) + +#define USART_CON0_IDLEIE_POS 4U +#define USART_CON0_IDLEIE_MSK BIT(USART_CON0_IDLEIE_POS) + +#define USART_CON0_TXEN_POS 3U +#define USART_CON0_TXEN_MSK BIT(USART_CON0_TXEN_POS) + +#define USART_CON0_RXEN_POS 2U +#define USART_CON0_RXEN_MSK BIT(USART_CON0_RXEN_POS) + +#define USART_CON0_RXWK_POS 1U +#define USART_CON0_RXWK_MSK BIT(USART_CON0_RXWK_POS) + +/****************** Bit definition for USART_CON1 register ************************/ + +#define USART_CON1_STPLEN_POSS 12U +#define USART_CON1_STPLEN_POSE 13U +#define USART_CON1_STPLEN_MSK BITS(USART_CON1_STPLEN_POSS,USART_CON1_STPLEN_POSE) + +#define USART_CON1_SCKEN_POS 11U +#define USART_CON1_SCKEN_MSK BIT(USART_CON1_SCKEN_POS) + +#define USART_CON1_SCKPOL_POS 10U +#define USART_CON1_SCKPOL_MSK BIT(USART_CON1_SCKPOL_POS) + +#define USART_CON1_SCKPHA_POS 9U +#define USART_CON1_SCKPHA_MSK BIT(USART_CON1_SCKPHA_POS) + +#define USART_CON1_LBCP_POS 8U +#define USART_CON1_LBCP_MSK BIT(USART_CON1_LBCP_POS) + +#define USART_CON1_ADDR_POSS 0U +#define USART_CON1_ADDR_POSE 3U +#define USART_CON1_ADDR_MSK BITS(USART_CON1_ADDR_POSS,USART_CON1_ADDR_POSE) + +/****************** Bit definition for USART_CON2 register ************************/ + +#define USART_CON2_CTSIE_POS 10U +#define USART_CON2_CTSIE_MSK BIT(USART_CON2_CTSIE_POS) + +#define USART_CON2_CTSEN_POS 9U +#define USART_CON2_CTSEN_MSK BIT(USART_CON2_CTSEN_POS) + +#define USART_CON2_RTSEN_POS 8U +#define USART_CON2_RTSEN_MSK BIT(USART_CON2_RTSEN_POS) + +#define USART_CON2_TXDMAEN_POS 7U +#define USART_CON2_TXDMAEN_MSK BIT(USART_CON2_TXDMAEN_POS) + +#define USART_CON2_RXDMAEN_POS 6U +#define USART_CON2_RXDMAEN_MSK BIT(USART_CON2_RXDMAEN_POS) + +#define USART_CON2_SMARTEN_POS 5U +#define USART_CON2_SMARTEN_MSK BIT(USART_CON2_SMARTEN_POS) + +#define USART_CON2_NACK_POS 4U +#define USART_CON2_NACK_MSK BIT(USART_CON2_NACK_POS) + +#define USART_CON2_HDPSEL_POS 3U +#define USART_CON2_HDPSEL_MSK BIT(USART_CON2_HDPSEL_POS) + +#define USART_CON2_IREN_POS 1U +#define USART_CON2_IREN_MSK BIT(USART_CON2_IREN_POS) + +#define USART_CON2_ERRIE_POS 0U +#define USART_CON2_ERRIE_MSK BIT(USART_CON2_ERRIE_POS) + +/****************** Bit definition for USART_GP register ************************/ + +#define USART_GP_GTVAL_POSS 8U +#define USART_GP_GTVAL_POSE 15U +#define USART_GP_GTVAL_MSK BITS(USART_GP_GTVAL_POSS,USART_GP_GTVAL_POSE) + +#define USART_GP_PSC_POSS 0U +#define USART_GP_PSC_POSE 7U +#define USART_GP_PSC_MSK BITS(USART_GP_PSC_POSS,USART_GP_PSC_POSE) + +typedef struct +{ + __IO uint32_t STAT; + __IO uint32_t DATA; + __IO uint32_t BAUDCON; + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t GP; +} USART_TypeDef; + +/****************** Bit definition for UART_RXBUF register ************************/ + +#define UART_RXBUF_RXBUF_POSS 0U +#define UART_RXBUF_RXBUF_POSE 8U +#define UART_RXBUF_RXBUF_MSK BITS(UART_RXBUF_RXBUF_POSS,UART_RXBUF_RXBUF_POSE) + +/****************** Bit definition for UART_TXBUF register ************************/ + +#define UART_TXBUF_TXBUF_POSS 0U +#define UART_TXBUF_TXBUF_POSE 8U +#define UART_TXBUF_TXBUF_MSK BITS(UART_TXBUF_TXBUF_POSS,UART_TXBUF_TXBUF_POSE) + +/****************** Bit definition for UART_BRR register ************************/ + +#define UART_BRR_BRR_POSS 0U +#define UART_BRR_BRR_POSE 15U +#define UART_BRR_BRR_MSK BITS(UART_BRR_BRR_POSS,UART_BRR_BRR_POSE) + +/****************** Bit definition for UART_LCON register ************************/ + +#define UART_LCON_TXEN_POS 15U +#define UART_LCON_TXEN_MSK BIT(UART_LCON_TXEN_POS) + +#define UART_LCON_RXEN_POS 14U +#define UART_LCON_RXEN_MSK BIT(UART_LCON_RXEN_POS) + +#define UART_LCON_DBCEN_POS 13U +#define UART_LCON_DBCEN_MSK BIT(UART_LCON_DBCEN_POS) + +#define UART_LCON_BREAK_POS 10U +#define UART_LCON_BREAK_MSK BIT(UART_LCON_BREAK_POS) + +#define UART_LCON_SWAP_POS 9U +#define UART_LCON_SWAP_MSK BIT(UART_LCON_SWAP_POS) + +#define UART_LCON_TXINV_POS 8U +#define UART_LCON_TXINV_MSK BIT(UART_LCON_TXINV_POS) + +#define UART_LCON_RXINV_POS 7U +#define UART_LCON_RXINV_MSK BIT(UART_LCON_RXINV_POS) + +#define UART_LCON_DATAINV_POS 6U +#define UART_LCON_DATAINV_MSK BIT(UART_LCON_DATAINV_POS) + +#define UART_LCON_MSB_POS 5U +#define UART_LCON_MSB_MSK BIT(UART_LCON_MSB_POS) + +#define UART_LCON_PS_POS 4U +#define UART_LCON_PS_MSK BIT(UART_LCON_PS_POS) + +#define UART_LCON_PE_POS 3U +#define UART_LCON_PE_MSK BIT(UART_LCON_PE_POS) + +#define UART_LCON_STOP_POS 2U +#define UART_LCON_STOP_MSK BIT(UART_LCON_STOP_POS) + +#define UART_LCON_DLS_POSS 0U +#define UART_LCON_DLS_POSE 1U +#define UART_LCON_DLS_MSK BITS(UART_LCON_DLS_POSS,UART_LCON_DLS_POSE) + +/****************** Bit definition for UART_MCON register ************************/ + +#define UART_MCON_TXDMAEN_POS 15U +#define UART_MCON_TXDMAEN_MSK BIT(UART_MCON_TXDMAEN_POS) + +#define UART_MCON_RXDMAEN_POS 14U +#define UART_MCON_RXDMAEN_MSK BIT(UART_MCON_RXDMAEN_POS) + +#define UART_MCON_ABRREPT_POS 11U +#define UART_MCON_ABRREPT_MSK BIT(UART_MCON_ABRREPT_POS) + +#define UART_MCON_ABRMOD_POSS 9U +#define UART_MCON_ABRMOD_POSE 10U +#define UART_MCON_ABRMOD_MSK BITS(UART_MCON_ABRMOD_POSS,UART_MCON_ABRMOD_POSE) + +#define UART_MCON_ABREN_POS 8U +#define UART_MCON_ABREN_MSK BIT(UART_MCON_ABREN_POS) + +#define UART_MCON_BKREQ_POS 5U +#define UART_MCON_BKREQ_MSK BIT(UART_MCON_BKREQ_POS) + +#define UART_MCON_HDEN_POS 4U +#define UART_MCON_HDEN_MSK BIT(UART_MCON_HDEN_POS) + +#define UART_MCON_IREN_POS 3U +#define UART_MCON_IREN_MSK BIT(UART_MCON_IREN_POS) + +#define UART_MCON_AFCEN_POS 2U +#define UART_MCON_AFCEN_MSK BIT(UART_MCON_AFCEN_POS) + +#define UART_MCON_RTSSET_POS 1U +#define UART_MCON_RTSSET_MSK BIT(UART_MCON_RTSSET_POS) + +#define UART_MCON_LPBKEN_POS 0U +#define UART_MCON_LPBKEN_MSK BIT(UART_MCON_LPBKEN_POS) + +/****************** Bit definition for UART_RS485 register ************************/ + +#define UART_RS485_DLY_POSS 16U +#define UART_RS485_DLY_POSE 23U +#define UART_RS485_DLY_MSK BITS(UART_RS485_DLY_POSS,UART_RS485_DLY_POSE) + +#define UART_RS485_ADDR_POSS 8U +#define UART_RS485_ADDR_POSE 15U +#define UART_RS485_ADDR_MSK BITS(UART_RS485_ADDR_POSS,UART_RS485_ADDR_POSE) + +#define UART_RS485_AADINV_POS 3U +#define UART_RS485_AADINV_MSK BIT(UART_RS485_AADINV_POS) + +#define UART_RS485_AADACEN_POS 2U +#define UART_RS485_AADACEN_MSK BIT(UART_RS485_AADACEN_POS) + +#define UART_RS485_AADNEN_POS 1U +#define UART_RS485_AADNEN_MSK BIT(UART_RS485_AADNEN_POS) + +#define UART_RS485_AADEN_POS 0U +#define UART_RS485_AADEN_MSK BIT(UART_RS485_AADEN_POS) + +/****************** Bit definition for UART_SCARD register ************************/ + +#define UART_SCARD_BLEN_POSS 24U +#define UART_SCARD_BLEN_POSE 31U +#define UART_SCARD_BLEN_MSK BITS(UART_SCARD_BLEN_POSS,UART_SCARD_BLEN_POSE) + +#define UART_SCARD_GT_POSS 16U +#define UART_SCARD_GT_POSE 23U +#define UART_SCARD_GT_MSK BITS(UART_SCARD_GT_POSS,UART_SCARD_GT_POSE) + +#define UART_SCARD_PSC_POSS 8U +#define UART_SCARD_PSC_POSE 15U +#define UART_SCARD_PSC_MSK BITS(UART_SCARD_PSC_POSS,UART_SCARD_PSC_POSE) + +#define UART_SCARD_SCCNT_POSS 3U +#define UART_SCARD_SCCNT_POSE 5U +#define UART_SCARD_SCCNT_MSK BITS(UART_SCARD_SCCNT_POSS,UART_SCARD_SCCNT_POSE) + +#define UART_SCARD_SCLKEN_POS 2U +#define UART_SCARD_SCLKEN_MSK BIT(UART_SCARD_SCLKEN_POS) + +#define UART_SCARD_SCNACK_POS 1U +#define UART_SCARD_SCNACK_MSK BIT(UART_SCARD_SCNACK_POS) + +#define UART_SCARD_SCEN_POS 0U +#define UART_SCARD_SCEN_MSK BIT(UART_SCARD_SCEN_POS) + +/****************** Bit definition for UART_LIN register ************************/ + +#define UART_LIN_LINBKREQ_POS 2U +#define UART_LIN_LINBKREQ_MSK BIT(UART_LIN_LINBKREQ_POS) + +#define UART_LIN_LINBDL_POS 1U +#define UART_LIN_LINBDL_MSK BIT(UART_LIN_LINBDL_POS) + +#define UART_LIN_LINEN_POS 0U +#define UART_LIN_LINEN_MSK BIT(UART_LIN_LINEN_POS) + +/****************** Bit definition for UART_RTOR register ************************/ + +#define UART_RTOR_RTOEN_POS 24U +#define UART_RTOR_RTOEN_MSK BIT(UART_RTOR_RTOEN_POS) + +#define UART_RTOR_RTO_POSS 0U +#define UART_RTOR_RTO_POSE 23U +#define UART_RTOR_RTO_MSK BITS(UART_RTOR_RTO_POSS,UART_RTOR_RTO_POSE) + +/****************** Bit definition for UART_FCON register ************************/ + +#define UART_FCON_TXFL_POSS 11U +#define UART_FCON_TXFL_POSE 15U +#define UART_FCON_TXFL_MSK BITS(UART_FCON_TXFL_POSS,UART_FCON_TXFL_POSE) + +#define UART_FCON_TXTH_POSS 9U +#define UART_FCON_TXTH_POSE 10U +#define UART_FCON_TXTH_MSK BITS(UART_FCON_TXTH_POSS,UART_FCON_TXTH_POSE) + +#define UART_FCON_TFRST_POS 8U +#define UART_FCON_TFRST_MSK BIT(UART_FCON_TFRST_POS) + +#define UART_FCON_RXFL_POSS 3U +#define UART_FCON_RXFL_POSE 7U +#define UART_FCON_RXFL_MSK BITS(UART_FCON_RXFL_POSS,UART_FCON_RXFL_POSE) + +#define UART_FCON_RXTH_POSS 1U +#define UART_FCON_RXTH_POSE 2U +#define UART_FCON_RXTH_MSK BITS(UART_FCON_RXTH_POSS,UART_FCON_RXTH_POSE) + +#define UART_FCON_RFRST_POS 0U +#define UART_FCON_RFRST_MSK BIT(UART_FCON_RFRST_POS) + +/****************** Bit definition for UART_STAT register ************************/ + +#define UART_STAT_TFOERR_POS 18U +#define UART_STAT_TFOERR_MSK BIT(UART_STAT_TFOERR_POS) + +#define UART_STAT_TFFULL_POS 17U +#define UART_STAT_TFFULL_MSK BIT(UART_STAT_TFFULL_POS) + +#define UART_STAT_TFEMPTY_POS 16U +#define UART_STAT_TFEMPTY_MSK BIT(UART_STAT_TFEMPTY_POS) + +#define UART_STAT_TFTH_POS 15U +#define UART_STAT_TFTH_MSK BIT(UART_STAT_TFTH_POS) + +#define UART_STAT_TSBUSY_POS 14U +#define UART_STAT_TSBUSY_MSK BIT(UART_STAT_TSBUSY_POS) + +#define UART_STAT_RFUERR_POS 13U +#define UART_STAT_RFUERR_MSK BIT(UART_STAT_RFUERR_POS) + +#define UART_STAT_RFOERR_POS 12U +#define UART_STAT_RFOERR_MSK BIT(UART_STAT_RFOERR_POS) + +#define UART_STAT_RFFULL_POS 11U +#define UART_STAT_RFFULL_MSK BIT(UART_STAT_RFFULL_POS) + +#define UART_STAT_RFEMPTY_POS 10U +#define UART_STAT_RFEMPTY_MSK BIT(UART_STAT_RFEMPTY_POS) + +#define UART_STAT_RFTH_POS 9U +#define UART_STAT_RFTH_MSK BIT(UART_STAT_RFTH_POS) + +#define UART_STAT_RSBUSY_POS 8U +#define UART_STAT_RSBUSY_MSK BIT(UART_STAT_RSBUSY_POS) + +#define UART_STAT_CTSSTA_POS 3U +#define UART_STAT_CTSSTA_MSK BIT(UART_STAT_CTSSTA_POS) + +#define UART_STAT_BKERR_POS 2U +#define UART_STAT_BKERR_MSK BIT(UART_STAT_BKERR_POS) + +#define UART_STAT_FERR_POS 1U +#define UART_STAT_FERR_MSK BIT(UART_STAT_FERR_POS) + +#define UART_STAT_PERR_POS 0U +#define UART_STAT_PERR_MSK BIT(UART_STAT_PERR_POS) + +/****************** Bit definition for UART_IER register ************************/ + +#define UART_IER_TFOVER_POS 18U +#define UART_IER_TFOVER_MSK BIT(UART_IER_TFOVER_POS) + +#define UART_IER_TFEMPTY_POS 16U +#define UART_IER_TFEMPTY_MSK BIT(UART_IER_TFEMPTY_POS) + +#define UART_IER_TFTH_POS 15U +#define UART_IER_TFTH_MSK BIT(UART_IER_TFTH_POS) + +#define UART_IER_TBC_POS 14U +#define UART_IER_TBC_MSK BIT(UART_IER_TBC_POS) + +#define UART_IER_RFUERR_POS 13U +#define UART_IER_RFUERR_MSK BIT(UART_IER_RFUERR_POS) + +#define UART_IER_RFOERR_POS 12U +#define UART_IER_RFOERR_MSK BIT(UART_IER_RFOERR_POS) + +#define UART_IER_RFFULL_POS 11U +#define UART_IER_RFFULL_MSK BIT(UART_IER_RFFULL_POS) + +#define UART_IER_RFTH_POS 9U +#define UART_IER_RFTH_MSK BIT(UART_IER_RFTH_POS) + +#define UART_IER_NOISE_POS 8U +#define UART_IER_NOISE_MSK BIT(UART_IER_NOISE_POS) + +#define UART_IER_EOB_POS 7U +#define UART_IER_EOB_MSK BIT(UART_IER_EOB_POS) + +#define UART_IER_LINBK_POS 6U +#define UART_IER_LINBK_MSK BIT(UART_IER_LINBK_POS) + +#define UART_IER_ADDRM_POS 5U +#define UART_IER_ADDRM_MSK BIT(UART_IER_ADDRM_POS) + +#define UART_IER_RXTO_POS 4U +#define UART_IER_RXTO_MSK BIT(UART_IER_RXTO_POS) + +#define UART_IER_DCTS_POS 3U +#define UART_IER_DCTS_MSK BIT(UART_IER_DCTS_POS) + +#define UART_IER_ABTO_POS 2U +#define UART_IER_ABTO_MSK BIT(UART_IER_ABTO_POS) + +#define UART_IER_ABEND_POS 1U +#define UART_IER_ABEND_MSK BIT(UART_IER_ABEND_POS) + +#define UART_IER_RXBERR_POS 0U +#define UART_IER_RXBERR_MSK BIT(UART_IER_RXBERR_POS) + +/****************** Bit definition for UART_IDR register ************************/ + +#define UART_IDR_TFOVER_POS 18U +#define UART_IDR_TFOVER_MSK BIT(UART_IDR_TFOVER_POS) + +#define UART_IDR_TFEMPTY_POS 16U +#define UART_IDR_TFEMPTY_MSK BIT(UART_IDR_TFEMPTY_POS) + +#define UART_IDR_TFTH_POS 15U +#define UART_IDR_TFTH_MSK BIT(UART_IDR_TFTH_POS) + +#define UART_IDR_TBC_POS 14U +#define UART_IDR_TBC_MSK BIT(UART_IDR_TBC_POS) + +#define UART_IDR_RFUERR_POS 13U +#define UART_IDR_RFUERR_MSK BIT(UART_IDR_RFUERR_POS) + +#define UART_IDR_RFOERR_POS 12U +#define UART_IDR_RFOERR_MSK BIT(UART_IDR_RFOERR_POS) + +#define UART_IDR_RFFULL_POS 11U +#define UART_IDR_RFFULL_MSK BIT(UART_IDR_RFFULL_POS) + +#define UART_IDR_RFTH_POS 9U +#define UART_IDR_RFTH_MSK BIT(UART_IDR_RFTH_POS) + +#define UART_IDR_NOISE_POS 8U +#define UART_IDR_NOISE_MSK BIT(UART_IDR_NOISE_POS) + +#define UART_IDR_EOB_POS 7U +#define UART_IDR_EOB_MSK BIT(UART_IDR_EOB_POS) + +#define UART_IDR_LINBK_POS 6U +#define UART_IDR_LINBK_MSK BIT(UART_IDR_LINBK_POS) + +#define UART_IDR_ADDRM_POS 5U +#define UART_IDR_ADDRM_MSK BIT(UART_IDR_ADDRM_POS) + +#define UART_IDR_RXTO_POS 4U +#define UART_IDR_RXTO_MSK BIT(UART_IDR_RXTO_POS) + +#define UART_IDR_DCTS_POS 3U +#define UART_IDR_DCTS_MSK BIT(UART_IDR_DCTS_POS) + +#define UART_IDR_ABTO_POS 2U +#define UART_IDR_ABTO_MSK BIT(UART_IDR_ABTO_POS) + +#define UART_IDR_ABEND_POS 1U +#define UART_IDR_ABEND_MSK BIT(UART_IDR_ABEND_POS) + +#define UART_IDR_RXBERR_POS 0U +#define UART_IDR_RXBERR_MSK BIT(UART_IDR_RXBERR_POS) + +/****************** Bit definition for UART_IVS register ************************/ + +#define UART_IVS_TFOVER_POS 18U +#define UART_IVS_TFOVER_MSK BIT(UART_IVS_TFOVER_POS) + +#define UART_IVS_TFEMPTY_POS 16U +#define UART_IVS_TFEMPTY_MSK BIT(UART_IVS_TFEMPTY_POS) + +#define UART_IVS_TFTH_POS 15U +#define UART_IVS_TFTH_MSK BIT(UART_IVS_TFTH_POS) + +#define UART_IVS_TBC_POS 14U +#define UART_IVS_TBC_MSK BIT(UART_IVS_TBC_POS) + +#define UART_IVS_RFUERR_POS 13U +#define UART_IVS_RFUERR_MSK BIT(UART_IVS_RFUERR_POS) + +#define UART_IVS_RFOERR_POS 12U +#define UART_IVS_RFOERR_MSK BIT(UART_IVS_RFOERR_POS) + +#define UART_IVS_RFFULL_POS 11U +#define UART_IVS_RFFULL_MSK BIT(UART_IVS_RFFULL_POS) + +#define UART_IVS_RFTH_POS 9U +#define UART_IVS_RFTH_MSK BIT(UART_IVS_RFTH_POS) + +#define UART_IVS_NOISE_POS 8U +#define UART_IVS_NOISE_MSK BIT(UART_IVS_NOISE_POS) + +#define UART_IVS_EOB_POS 7U +#define UART_IVS_EOB_MSK BIT(UART_IVS_EOB_POS) + +#define UART_IVS_LINBK_POS 6U +#define UART_IVS_LINBK_MSK BIT(UART_IVS_LINBK_POS) + +#define UART_IVS_ADDRM_POS 5U +#define UART_IVS_ADDRM_MSK BIT(UART_IVS_ADDRM_POS) + +#define UART_IVS_RXTO_POS 4U +#define UART_IVS_RXTO_MSK BIT(UART_IVS_RXTO_POS) + +#define UART_IVS_DCTS_POS 3U +#define UART_IVS_DCTS_MSK BIT(UART_IVS_DCTS_POS) + +#define UART_IVS_ABTO_POS 2U +#define UART_IVS_ABTO_MSK BIT(UART_IVS_ABTO_POS) + +#define UART_IVS_ABEND_POS 1U +#define UART_IVS_ABEND_MSK BIT(UART_IVS_ABEND_POS) + +#define UART_IVS_RXBERR_POS 0U +#define UART_IVS_RXBERR_MSK BIT(UART_IVS_RXBERR_POS) + +/****************** Bit definition for UART_RIF register ************************/ + +#define UART_RIF_TFOVER_POS 18U +#define UART_RIF_TFOVER_MSK BIT(UART_RIF_TFOVER_POS) + +#define UART_RIF_TFEMPTY_POS 16U +#define UART_RIF_TFEMPTY_MSK BIT(UART_RIF_TFEMPTY_POS) + +#define UART_RIF_TFTH_POS 15U +#define UART_RIF_TFTH_MSK BIT(UART_RIF_TFTH_POS) + +#define UART_RIF_TBC_POS 14U +#define UART_RIF_TBC_MSK BIT(UART_RIF_TBC_POS) + +#define UART_RIF_RFUERR_POS 13U +#define UART_RIF_RFUERR_MSK BIT(UART_RIF_RFUERR_POS) + +#define UART_RIF_RFOERR_POS 12U +#define UART_RIF_RFOERR_MSK BIT(UART_RIF_RFOERR_POS) + +#define UART_RIF_RFFULL_POS 11U +#define UART_RIF_RFFULL_MSK BIT(UART_RIF_RFFULL_POS) + +#define UART_RIF_RFTH_POS 9U +#define UART_RIF_RFTH_MSK BIT(UART_RIF_RFTH_POS) + +#define UART_RIF_NOISE_POS 8U +#define UART_RIF_NOISE_MSK BIT(UART_RIF_NOISE_POS) + +#define UART_RIF_EOB_POS 7U +#define UART_RIF_EOB_MSK BIT(UART_RIF_EOB_POS) + +#define UART_RIF_LINBK_POS 6U +#define UART_RIF_LINBK_MSK BIT(UART_RIF_LINBK_POS) + +#define UART_RIF_ADDRM_POS 5U +#define UART_RIF_ADDRM_MSK BIT(UART_RIF_ADDRM_POS) + +#define UART_RIF_RXTO_POS 4U +#define UART_RIF_RXTO_MSK BIT(UART_RIF_RXTO_POS) + +#define UART_RIF_DCTS_POS 3U +#define UART_RIF_DCTS_MSK BIT(UART_RIF_DCTS_POS) + +#define UART_RIF_ABTO_POS 2U +#define UART_RIF_ABTO_MSK BIT(UART_RIF_ABTO_POS) + +#define UART_RIF_ABEND_POS 1U +#define UART_RIF_ABEND_MSK BIT(UART_RIF_ABEND_POS) + +#define UART_RIF_RXBERR_POS 0U +#define UART_RIF_RXBERR_MSK BIT(UART_RIF_RXBERR_POS) + +/****************** Bit definition for UART_IFM register ************************/ + +#define UART_IFM_TFOVER_POS 18U +#define UART_IFM_TFOVER_MSK BIT(UART_IFM_TFOVER_POS) + +#define UART_IFM_TFEMPTY_POS 16U +#define UART_IFM_TFEMPTY_MSK BIT(UART_IFM_TFEMPTY_POS) + +#define UART_IFM_TFTH_POS 15U +#define UART_IFM_TFTH_MSK BIT(UART_IFM_TFTH_POS) + +#define UART_IFM_TBC_POS 14U +#define UART_IFM_TBC_MSK BIT(UART_IFM_TBC_POS) + +#define UART_IFM_RFUERR_POS 13U +#define UART_IFM_RFUERR_MSK BIT(UART_IFM_RFUERR_POS) + +#define UART_IFM_RFOERR_POS 12U +#define UART_IFM_RFOERR_MSK BIT(UART_IFM_RFOERR_POS) + +#define UART_IFM_RFFULL_POS 11U +#define UART_IFM_RFFULL_MSK BIT(UART_IFM_RFFULL_POS) + +#define UART_IFM_RFTH_POS 9U +#define UART_IFM_RFTH_MSK BIT(UART_IFM_RFTH_POS) + +#define UART_IFM_NOISE_POS 8U +#define UART_IFM_NOISE_MSK BIT(UART_IFM_NOISE_POS) + +#define UART_IFM_EOB_POS 7U +#define UART_IFM_EOB_MSK BIT(UART_IFM_EOB_POS) + +#define UART_IFM_LINBK_POS 6U +#define UART_IFM_LINBK_MSK BIT(UART_IFM_LINBK_POS) + +#define UART_IFM_ADDRM_POS 5U +#define UART_IFM_ADDRM_MSK BIT(UART_IFM_ADDRM_POS) + +#define UART_IFM_RXTO_POS 4U +#define UART_IFM_RXTO_MSK BIT(UART_IFM_RXTO_POS) + +#define UART_IFM_DCTS_POS 3U +#define UART_IFM_DCTS_MSK BIT(UART_IFM_DCTS_POS) + +#define UART_IFM_ABTO_POS 2U +#define UART_IFM_ABTO_MSK BIT(UART_IFM_ABTO_POS) + +#define UART_IFM_ABEND_POS 1U +#define UART_IFM_ABEND_MSK BIT(UART_IFM_ABEND_POS) + +#define UART_IFM_RXBERR_POS 0U +#define UART_IFM_RXBERR_MSK BIT(UART_IFM_RXBERR_POS) + +/****************** Bit definition for UART_ICR register ************************/ + +#define UART_ICR_TFOVER_POS 18U +#define UART_ICR_TFOVER_MSK BIT(UART_ICR_TFOVER_POS) + +#define UART_ICR_TFEMPTY_POS 16U +#define UART_ICR_TFEMPTY_MSK BIT(UART_ICR_TFEMPTY_POS) + +#define UART_ICR_TFTH_POS 15U +#define UART_ICR_TFTH_MSK BIT(UART_ICR_TFTH_POS) + +#define UART_ICR_TBC_POS 14U +#define UART_ICR_TBC_MSK BIT(UART_ICR_TBC_POS) + +#define UART_ICR_RFUERR_POS 13U +#define UART_ICR_RFUERR_MSK BIT(UART_ICR_RFUERR_POS) + +#define UART_ICR_RFOERR_POS 12U +#define UART_ICR_RFOERR_MSK BIT(UART_ICR_RFOERR_POS) + +#define UART_ICR_RFFULL_POS 11U +#define UART_ICR_RFFULL_MSK BIT(UART_ICR_RFFULL_POS) + +#define UART_ICR_RFTH_POS 9U +#define UART_ICR_RFTH_MSK BIT(UART_ICR_RFTH_POS) + +#define UART_ICR_NOISE_POS 8U +#define UART_ICR_NOISE_MSK BIT(UART_ICR_NOISE_POS) + +#define UART_ICR_EOB_POS 7U +#define UART_ICR_EOB_MSK BIT(UART_ICR_EOB_POS) + +#define UART_ICR_LINBK_POS 6U +#define UART_ICR_LINBK_MSK BIT(UART_ICR_LINBK_POS) + +#define UART_ICR_ADDRM_POS 5U +#define UART_ICR_ADDRM_MSK BIT(UART_ICR_ADDRM_POS) + +#define UART_ICR_RXTO_POS 4U +#define UART_ICR_RXTO_MSK BIT(UART_ICR_RXTO_POS) + +#define UART_ICR_DCTS_POS 3U +#define UART_ICR_DCTS_MSK BIT(UART_ICR_DCTS_POS) + +#define UART_ICR_ABTO_POS 2U +#define UART_ICR_ABTO_MSK BIT(UART_ICR_ABTO_POS) + +#define UART_ICR_ABEND_POS 1U +#define UART_ICR_ABEND_MSK BIT(UART_ICR_ABEND_POS) + +#define UART_ICR_RXBERR_POS 0U +#define UART_ICR_RXBERR_MSK BIT(UART_ICR_RXBERR_POS) + +typedef struct +{ + __I uint32_t RXBUF; + __IO uint32_t TXBUF; + __IO uint32_t BRR; + __IO uint32_t LCON; + __IO uint32_t MCON; + __IO uint32_t RS485; + __IO uint32_t SCARD; + __IO uint32_t LIN; + __IO uint32_t RTOR; + __O uint32_t FCON; + __I uint32_t STAT; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} UART_TypeDef; + +/****************** Bit definition for SPI_CON1 register ************************/ + +#define SPI_CON1_BIDEN_POS 15U +#define SPI_CON1_BIDEN_MSK BIT(SPI_CON1_BIDEN_POS) + +#define SPI_CON1_BIDOEN_POS 14U +#define SPI_CON1_BIDOEN_MSK BIT(SPI_CON1_BIDOEN_POS) + +#define SPI_CON1_CRCEN_POS 13U +#define SPI_CON1_CRCEN_MSK BIT(SPI_CON1_CRCEN_POS) + +#define SPI_CON1_NXTCRC_POS 12U +#define SPI_CON1_NXTCRC_MSK BIT(SPI_CON1_NXTCRC_POS) + +#define SPI_CON1_FLEN_POS 11U +#define SPI_CON1_FLEN_MSK BIT(SPI_CON1_FLEN_POS) + +#define SPI_CON1_RXO_POS 10U +#define SPI_CON1_RXO_MSK BIT(SPI_CON1_RXO_POS) + +#define SPI_CON1_SSEN_POS 9U +#define SPI_CON1_SSEN_MSK BIT(SPI_CON1_SSEN_POS) + +#define SPI_CON1_SSOUT_POS 8U +#define SPI_CON1_SSOUT_MSK BIT(SPI_CON1_SSOUT_POS) + +#define SPI_CON1_LSBFST_POS 7U +#define SPI_CON1_LSBFST_MSK BIT(SPI_CON1_LSBFST_POS) + +#define SPI_CON1_SPIEN_POS 6U +#define SPI_CON1_SPIEN_MSK BIT(SPI_CON1_SPIEN_POS) + +#define SPI_CON1_BAUD_POSS 3U +#define SPI_CON1_BAUD_POSE 5U +#define SPI_CON1_BAUD_MSK BITS(SPI_CON1_BAUD_POSS,SPI_CON1_BAUD_POSE) + +#define SPI_CON1_MSTREN_POS 2U +#define SPI_CON1_MSTREN_MSK BIT(SPI_CON1_MSTREN_POS) + +#define SPI_CON1_CPOL_POS 1U +#define SPI_CON1_CPOL_MSK BIT(SPI_CON1_CPOL_POS) + +#define SPI_CON1_CPHA_POS 0U +#define SPI_CON1_CPHA_MSK BIT(SPI_CON1_CPHA_POS) + +/****************** Bit definition for SPI_CON2 register ************************/ + +#define SPI_CON2_RXFTH_POSS 14U +#define SPI_CON2_RXFTH_POSE 15U +#define SPI_CON2_RXFTH_MSK BITS(SPI_CON2_RXFTH_POSS,SPI_CON2_RXFTH_POSE) + +#define SPI_CON2_TXFTH_POSS 12U +#define SPI_CON2_TXFTH_POSE 13U +#define SPI_CON2_TXFTH_MSK BITS(SPI_CON2_TXFTH_POSS,SPI_CON2_TXFTH_POSE) + +#define SPI_CON2_FRF_POS 4U +#define SPI_CON2_FRF_MSK BIT(SPI_CON2_FRF_POS) + +#define SPI_CON2_NSSP_POS 3U +#define SPI_CON2_NSSP_MSK BIT(SPI_CON2_NSSP_POS) + +#define SPI_CON2_NSSOE_POS 2U +#define SPI_CON2_NSSOE_MSK BIT(SPI_CON2_NSSOE_POS) + +#define SPI_CON2_TXDMA_POS 1U +#define SPI_CON2_TXDMA_MSK BIT(SPI_CON2_TXDMA_POS) + +#define SPI_CON2_RXDMA_POS 0U +#define SPI_CON2_RXDMA_MSK BIT(SPI_CON2_RXDMA_POS) + +/****************** Bit definition for SPI_STAT register ************************/ + +#define SPI_STAT_RXFLV_POSS 24U +#define SPI_STAT_RXFLV_POSE 28U +#define SPI_STAT_RXFLV_MSK BITS(SPI_STAT_RXFLV_POSS,SPI_STAT_RXFLV_POSE) + +#define SPI_STAT_TXFLV_POSS 16U +#define SPI_STAT_TXFLV_POSE 20U +#define SPI_STAT_TXFLV_MSK BITS(SPI_STAT_TXFLV_POSS,SPI_STAT_TXFLV_POSE) + +#define SPI_STAT_BUSY_POS 15U +#define SPI_STAT_BUSY_MSK BIT(SPI_STAT_BUSY_POS) + +#define SPI_STAT_CHSIDE_POS 14U +#define SPI_STAT_CHSIDE_MSK BIT(SPI_STAT_CHSIDE_POS) + +#define SPI_STAT_RXTH_POS 12U +#define SPI_STAT_RXTH_MSK BIT(SPI_STAT_RXTH_POS) + +#define SPI_STAT_RXUD_POS 11U +#define SPI_STAT_RXUD_MSK BIT(SPI_STAT_RXUD_POS) + +#define SPI_STAT_RXOV_POS 10U +#define SPI_STAT_RXOV_MSK BIT(SPI_STAT_RXOV_POS) + +#define SPI_STAT_RXF_POS 9U +#define SPI_STAT_RXF_MSK BIT(SPI_STAT_RXF_POS) + +#define SPI_STAT_RXE_POS 8U +#define SPI_STAT_RXE_MSK BIT(SPI_STAT_RXE_POS) + +#define SPI_STAT_TXTH_POS 4U +#define SPI_STAT_TXTH_MSK BIT(SPI_STAT_TXTH_POS) + +#define SPI_STAT_TXUD_POS 3U +#define SPI_STAT_TXUD_MSK BIT(SPI_STAT_TXUD_POS) + +#define SPI_STAT_TXOV_POS 2U +#define SPI_STAT_TXOV_MSK BIT(SPI_STAT_TXOV_POS) + +#define SPI_STAT_TXF_POS 1U +#define SPI_STAT_TXF_MSK BIT(SPI_STAT_TXF_POS) + +#define SPI_STAT_TXE_POS 0U +#define SPI_STAT_TXE_MSK BIT(SPI_STAT_TXE_POS) + +/****************** Bit definition for SPI_DATA register ************************/ + +#define SPI_DATA_DATA_POSS 0U +#define SPI_DATA_DATA_POSE 15U +#define SPI_DATA_DATA_MSK BITS(SPI_DATA_DATA_POSS,SPI_DATA_DATA_POSE) + +/****************** Bit definition for SPI_CRCPOLY register ************************/ + +#define SPI_CRCPOLY_CRCPOLY_POSS 0U +#define SPI_CRCPOLY_CRCPOLY_POSE 15U +#define SPI_CRCPOLY_CRCPOLY_MSK BITS(SPI_CRCPOLY_CRCPOLY_POSS,SPI_CRCPOLY_CRCPOLY_POSE) + +/****************** Bit definition for SPI_RXCRC register ************************/ + +#define SPI_RXCRC_RXCRC_POSS 0U +#define SPI_RXCRC_RXCRC_POSE 15U +#define SPI_RXCRC_RXCRC_MSK BITS(SPI_RXCRC_RXCRC_POSS,SPI_RXCRC_RXCRC_POSE) + +/****************** Bit definition for SPI_TXCRC register ************************/ + +#define SPI_TXCRC_TXCRC_POSS 0U +#define SPI_TXCRC_TXCRC_POSE 15U +#define SPI_TXCRC_TXCRC_MSK BITS(SPI_TXCRC_TXCRC_POSS,SPI_TXCRC_TXCRC_POSE) + +/****************** Bit definition for SPI_I2SCFG register ************************/ + +#define SPI_I2SCFG_I2SMOD_POS 11U +#define SPI_I2SCFG_I2SMOD_MSK BIT(SPI_I2SCFG_I2SMOD_POS) + +#define SPI_I2SCFG_I2SE_POS 10U +#define SPI_I2SCFG_I2SE_MSK BIT(SPI_I2SCFG_I2SE_POS) + +#define SPI_I2SCFG_I2SCFG_POSS 8U +#define SPI_I2SCFG_I2SCFG_POSE 9U +#define SPI_I2SCFG_I2SCFG_MSK BITS(SPI_I2SCFG_I2SCFG_POSS,SPI_I2SCFG_I2SCFG_POSE) + +#define SPI_I2SCFG_PCMSYNC_POS 7U +#define SPI_I2SCFG_PCMSYNC_MSK BIT(SPI_I2SCFG_PCMSYNC_POS) + +#define SPI_I2SCFG_I2SSTD_POSS 4U +#define SPI_I2SCFG_I2SSTD_POSE 5U +#define SPI_I2SCFG_I2SSTD_MSK BITS(SPI_I2SCFG_I2SSTD_POSS,SPI_I2SCFG_I2SSTD_POSE) + +#define SPI_I2SCFG_CKPOL_POS 3U +#define SPI_I2SCFG_CKPOL_MSK BIT(SPI_I2SCFG_CKPOL_POS) + +#define SPI_I2SCFG_DATLEN_POSS 1U +#define SPI_I2SCFG_DATLEN_POSE 2U +#define SPI_I2SCFG_DATLEN_MSK BITS(SPI_I2SCFG_DATLEN_POSS,SPI_I2SCFG_DATLEN_POSE) + +#define SPI_I2SCFG_CHLEN_POS 0U +#define SPI_I2SCFG_CHLEN_MSK BIT(SPI_I2SCFG_CHLEN_POS) + +/****************** Bit definition for SPI_I2SPR register ************************/ + +#define SPI_I2SPR_EXTCKEN_POS 10U +#define SPI_I2SPR_EXTCKEN_MSK BIT(SPI_I2SPR_EXTCKEN_POS) + +#define SPI_I2SPR_MCKOE_POS 9U +#define SPI_I2SPR_MCKOE_MSK BIT(SPI_I2SPR_MCKOE_POS) + +#define SPI_I2SPR_ODD_POS 8U +#define SPI_I2SPR_ODD_MSK BIT(SPI_I2SPR_ODD_POS) + +#define SPI_I2SPR_I2SDIV_POSS 0U +#define SPI_I2SPR_I2SDIV_POSE 7U +#define SPI_I2SPR_I2SDIV_MSK BITS(SPI_I2SPR_I2SDIV_POSS,SPI_I2SPR_I2SDIV_POSE) + +/****************** Bit definition for SPI_IER register ************************/ + +#define SPI_IER_FREIE_POS 18U +#define SPI_IER_FREIE_MSK BIT(SPI_IER_FREIE_POS) + +#define SPI_IER_MODFIE_POS 17U +#define SPI_IER_MODFIE_MSK BIT(SPI_IER_MODFIE_POS) + +#define SPI_IER_CRCERRIE_POS 16U +#define SPI_IER_CRCERRIE_MSK BIT(SPI_IER_CRCERRIE_POS) + +#define SPI_IER_RXTHIE_POS 12U +#define SPI_IER_RXTHIE_MSK BIT(SPI_IER_RXTHIE_POS) + +#define SPI_IER_RXUDIE_POS 11U +#define SPI_IER_RXUDIE_MSK BIT(SPI_IER_RXUDIE_POS) + +#define SPI_IER_RXOVIE_POS 10U +#define SPI_IER_RXOVIE_MSK BIT(SPI_IER_RXOVIE_POS) + +#define SPI_IER_RXFIE_POS 9U +#define SPI_IER_RXFIE_MSK BIT(SPI_IER_RXFIE_POS) + +#define SPI_IER_TXTHIE_POS 4U +#define SPI_IER_TXTHIE_MSK BIT(SPI_IER_TXTHIE_POS) + +#define SPI_IER_TXUDIE_POS 3U +#define SPI_IER_TXUDIE_MSK BIT(SPI_IER_TXUDIE_POS) + +#define SPI_IER_TXOVIE_POS 2U +#define SPI_IER_TXOVIE_MSK BIT(SPI_IER_TXOVIE_POS) + +#define SPI_IER_TXEIE_POS 0U +#define SPI_IER_TXEIE_MSK BIT(SPI_IER_TXEIE_POS) + +/****************** Bit definition for SPI_IDR register ************************/ + +#define SPI_IDR_FREID_POS 18U +#define SPI_IDR_FREID_MSK BIT(SPI_IDR_FREID_POS) + +#define SPI_IDR_MODFID_POS 17U +#define SPI_IDR_MODFID_MSK BIT(SPI_IDR_MODFID_POS) + +#define SPI_IDR_CRCERRID_POS 16U +#define SPI_IDR_CRCERRID_MSK BIT(SPI_IDR_CRCERRID_POS) + +#define SPI_IDR_RXTHID_POS 12U +#define SPI_IDR_RXTHID_MSK BIT(SPI_IDR_RXTHID_POS) + +#define SPI_IDR_RXUDID_POS 11U +#define SPI_IDR_RXUDID_MSK BIT(SPI_IDR_RXUDID_POS) + +#define SPI_IDR_RXOVID_POS 10U +#define SPI_IDR_RXOVID_MSK BIT(SPI_IDR_RXOVID_POS) + +#define SPI_IDR_RXFID_POS 9U +#define SPI_IDR_RXFID_MSK BIT(SPI_IDR_RXFID_POS) + +#define SPI_IDR_TXTHID_POS 4U +#define SPI_IDR_TXTHID_MSK BIT(SPI_IDR_TXTHID_POS) + +#define SPI_IDR_TXUDID_POS 3U +#define SPI_IDR_TXUDID_MSK BIT(SPI_IDR_TXUDID_POS) + +#define SPI_IDR_TXOVID_POS 2U +#define SPI_IDR_TXOVID_MSK BIT(SPI_IDR_TXOVID_POS) + +#define SPI_IDR_TXEID_POS 0U +#define SPI_IDR_TXEID_MSK BIT(SPI_IDR_TXEID_POS) + +/****************** Bit definition for SPI_IVS register ************************/ + +#define SPI_IVS_FREIV_POS 18U +#define SPI_IVS_FREIV_MSK BIT(SPI_IVS_FREIV_POS) + +#define SPI_IVS_MODFIV_POS 17U +#define SPI_IVS_MODFIV_MSK BIT(SPI_IVS_MODFIV_POS) + +#define SPI_IVS_CRCERRIV_POS 16U +#define SPI_IVS_CRCERRIV_MSK BIT(SPI_IVS_CRCERRIV_POS) + +#define SPI_IVS_RXTHIV_POS 12U +#define SPI_IVS_RXTHIV_MSK BIT(SPI_IVS_RXTHIV_POS) + +#define SPI_IVS_RXUDIV_POS 11U +#define SPI_IVS_RXUDIV_MSK BIT(SPI_IVS_RXUDIV_POS) + +#define SPI_IVS_RXOVIV_POS 10U +#define SPI_IVS_RXOVIV_MSK BIT(SPI_IVS_RXOVIV_POS) + +#define SPI_IVS_RXFIV_POS 9U +#define SPI_IVS_RXFIV_MSK BIT(SPI_IVS_RXFIV_POS) + +#define SPI_IVS_TXTHIV_POS 4U +#define SPI_IVS_TXTHIV_MSK BIT(SPI_IVS_TXTHIV_POS) + +#define SPI_IVS_TXUDIV_POS 3U +#define SPI_IVS_TXUDIV_MSK BIT(SPI_IVS_TXUDIV_POS) + +#define SPI_IVS_TXOVIV_POS 2U +#define SPI_IVS_TXOVIV_MSK BIT(SPI_IVS_TXOVIV_POS) + +#define SPI_IVS_TXEIV_POS 0U +#define SPI_IVS_TXEIV_MSK BIT(SPI_IVS_TXEIV_POS) + +/****************** Bit definition for SPI_RIF register ************************/ + +#define SPI_RIF_FRERI_POS 18U +#define SPI_RIF_FRERI_MSK BIT(SPI_RIF_FRERI_POS) + +#define SPI_RIF_MODFRI_POS 17U +#define SPI_RIF_MODFRI_MSK BIT(SPI_RIF_MODFRI_POS) + +#define SPI_RIF_CRCERRRI_POS 16U +#define SPI_RIF_CRCERRRI_MSK BIT(SPI_RIF_CRCERRRI_POS) + +#define SPI_RIF_RXTHRI_POS 12U +#define SPI_RIF_RXTHRI_MSK BIT(SPI_RIF_RXTHRI_POS) + +#define SPI_RIF_RXUDRI_POS 11U +#define SPI_RIF_RXUDRI_MSK BIT(SPI_RIF_RXUDRI_POS) + +#define SPI_RIF_RXOVRI_POS 10U +#define SPI_RIF_RXOVRI_MSK BIT(SPI_RIF_RXOVRI_POS) + +#define SPI_RIF_RXFRI_POS 9U +#define SPI_RIF_RXFRI_MSK BIT(SPI_RIF_RXFRI_POS) + +#define SPI_RIF_TXTHRI_POS 4U +#define SPI_RIF_TXTHRI_MSK BIT(SPI_RIF_TXTHRI_POS) + +#define SPI_RIF_TXUDRI_POS 3U +#define SPI_RIF_TXUDRI_MSK BIT(SPI_RIF_TXUDRI_POS) + +#define SPI_RIF_TXOVRI_POS 2U +#define SPI_RIF_TXOVRI_MSK BIT(SPI_RIF_TXOVRI_POS) + +#define SPI_RIF_TXERI_POS 0U +#define SPI_RIF_TXERI_MSK BIT(SPI_RIF_TXERI_POS) + +/****************** Bit definition for SPI_IFM register ************************/ + +#define SPI_IFM_FREFM_POS 18U +#define SPI_IFM_FREFM_MSK BIT(SPI_IFM_FREFM_POS) + +#define SPI_IFM_MODFFM_POS 17U +#define SPI_IFM_MODFFM_MSK BIT(SPI_IFM_MODFFM_POS) + +#define SPI_IFM_CRCERRFM_POS 16U +#define SPI_IFM_CRCERRFM_MSK BIT(SPI_IFM_CRCERRFM_POS) + +#define SPI_IFM_RXTHFM_POS 12U +#define SPI_IFM_RXTHFM_MSK BIT(SPI_IFM_RXTHFM_POS) + +#define SPI_IFM_RXUDFM_POS 11U +#define SPI_IFM_RXUDFM_MSK BIT(SPI_IFM_RXUDFM_POS) + +#define SPI_IFM_RXOVFM_POS 10U +#define SPI_IFM_RXOVFM_MSK BIT(SPI_IFM_RXOVFM_POS) + +#define SPI_IFM_RXFFM_POS 9U +#define SPI_IFM_RXFFM_MSK BIT(SPI_IFM_RXFFM_POS) + +#define SPI_IFM_TXTHFM_POS 4U +#define SPI_IFM_TXTHFM_MSK BIT(SPI_IFM_TXTHFM_POS) + +#define SPI_IFM_TXUDFM_POS 3U +#define SPI_IFM_TXUDFM_MSK BIT(SPI_IFM_TXUDFM_POS) + +#define SPI_IFM_TXOVFM_POS 2U +#define SPI_IFM_TXOVFM_MSK BIT(SPI_IFM_TXOVFM_POS) + +#define SPI_IFM_TXEFM_POS 0U +#define SPI_IFM_TXEFM_MSK BIT(SPI_IFM_TXEFM_POS) + +/****************** Bit definition for SPI_ICR register ************************/ + +#define SPI_ICR_FREIC_POS 18U +#define SPI_ICR_FREIC_MSK BIT(SPI_ICR_FREIC_POS) + +#define SPI_ICR_MODFIC_POS 17U +#define SPI_ICR_MODFIC_MSK BIT(SPI_ICR_MODFIC_POS) + +#define SPI_ICR_CRCERRIC_POS 16U +#define SPI_ICR_CRCERRIC_MSK BIT(SPI_ICR_CRCERRIC_POS) + +#define SPI_ICR_RXTHIC_POS 12U +#define SPI_ICR_RXTHIC_MSK BIT(SPI_ICR_RXTHIC_POS) + +#define SPI_ICR_RXUDIC_POS 11U +#define SPI_ICR_RXUDIC_MSK BIT(SPI_ICR_RXUDIC_POS) + +#define SPI_ICR_RXOVIC_POS 10U +#define SPI_ICR_RXOVIC_MSK BIT(SPI_ICR_RXOVIC_POS) + +#define SPI_ICR_RXFIC_POS 9U +#define SPI_ICR_RXFIC_MSK BIT(SPI_ICR_RXFIC_POS) + +#define SPI_ICR_TXTHIC_POS 4U +#define SPI_ICR_TXTHIC_MSK BIT(SPI_ICR_TXTHIC_POS) + +#define SPI_ICR_TXUDIC_POS 3U +#define SPI_ICR_TXUDIC_MSK BIT(SPI_ICR_TXUDIC_POS) + +#define SPI_ICR_TXOVIC_POS 2U +#define SPI_ICR_TXOVIC_MSK BIT(SPI_ICR_TXOVIC_POS) + +#define SPI_ICR_TXEIC_POS 0U +#define SPI_ICR_TXEIC_MSK BIT(SPI_ICR_TXEIC_POS) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __I uint32_t STAT; + __IO uint32_t DATA; + __IO uint32_t CRCPOLY; + __I uint32_t RXCRC; + __I uint32_t TXCRC; + __IO uint32_t I2SCFG; + __IO uint32_t I2SPR; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} SPI_I2S_TypeDef; + +/****************** Bit definition for I2C_CON1 register ************************/ + +#define I2C_CON1_PECEN_POS 23U +#define I2C_CON1_PECEN_MSK BIT(I2C_CON1_PECEN_POS) + +#define I2C_CON1_ALERTEN_POS 22U +#define I2C_CON1_ALERTEN_MSK BIT(I2C_CON1_ALERTEN_POS) + +#define I2C_CON1_SMBDEN_POS 21U +#define I2C_CON1_SMBDEN_MSK BIT(I2C_CON1_SMBDEN_POS) + +#define I2C_CON1_SMBHEN_POS 20U +#define I2C_CON1_SMBHEN_MSK BIT(I2C_CON1_SMBHEN_POS) + +#define I2C_CON1_GCEN_POS 19U +#define I2C_CON1_GCEN_MSK BIT(I2C_CON1_GCEN_POS) + +#define I2C_CON1_NOSTRETCH_POS 17U +#define I2C_CON1_NOSTRETCH_MSK BIT(I2C_CON1_NOSTRETCH_POS) + +#define I2C_CON1_SBC_POS 16U +#define I2C_CON1_SBC_MSK BIT(I2C_CON1_SBC_POS) + +#define I2C_CON1_RXDMAEN_POS 15U +#define I2C_CON1_RXDMAEN_MSK BIT(I2C_CON1_RXDMAEN_POS) + +#define I2C_CON1_TXDMAEN_POS 14U +#define I2C_CON1_TXDMAEN_MSK BIT(I2C_CON1_TXDMAEN_POS) + +#define I2C_CON1_DNF_POSS 8U +#define I2C_CON1_DNF_POSE 11U +#define I2C_CON1_DNF_MSK BITS(I2C_CON1_DNF_POSS,I2C_CON1_DNF_POSE) + +#define I2C_CON1_PE_POS 0U +#define I2C_CON1_PE_MSK BIT(I2C_CON1_PE_POS) + +/****************** Bit definition for I2C_CON2 register ************************/ + +#define I2C_CON2_ACK_UPD_POS 29U +#define I2C_CON2_ACK_UPD_MSK BIT(I2C_CON2_ACK_UPD_POS) + +#define I2C_CON2_HOLDACK_POS 28U +#define I2C_CON2_HOLDACK_MSK BIT(I2C_CON2_HOLDACK_POS) + +#define I2C_CON2_PECBYTE_POS 26U +#define I2C_CON2_PECBYTE_MSK BIT(I2C_CON2_PECBYTE_POS) + +#define I2C_CON2_AUTOEND_POS 25U +#define I2C_CON2_AUTOEND_MSK BIT(I2C_CON2_AUTOEND_POS) + +#define I2C_CON2_RELOAD_POS 24U +#define I2C_CON2_RELOAD_MSK BIT(I2C_CON2_RELOAD_POS) + +#define I2C_CON2_NBYTES_POSS 16U +#define I2C_CON2_NBYTES_POSE 23U +#define I2C_CON2_NBYTES_MSK BITS(I2C_CON2_NBYTES_POSS,I2C_CON2_NBYTES_POSE) + +#define I2C_CON2_NACK_POS 15U +#define I2C_CON2_NACK_MSK BIT(I2C_CON2_NACK_POS) + +#define I2C_CON2_STOP_POS 14U +#define I2C_CON2_STOP_MSK BIT(I2C_CON2_STOP_POS) + +#define I2C_CON2_START_POS 13U +#define I2C_CON2_START_MSK BIT(I2C_CON2_START_POS) + +#define I2C_CON2_HEAD10R_POS 12U +#define I2C_CON2_HEAD10R_MSK BIT(I2C_CON2_HEAD10R_POS) + +#define I2C_CON2_ADD10_POS 11U +#define I2C_CON2_ADD10_MSK BIT(I2C_CON2_ADD10_POS) + +#define I2C_CON2_RD_WRN_POS 10U +#define I2C_CON2_RD_WRN_MSK BIT(I2C_CON2_RD_WRN_POS) + +#define I2C_CON2_SADD_POSS 0U +#define I2C_CON2_SADD_POSE 9U +#define I2C_CON2_SADD_MSK BITS(I2C_CON2_SADD_POSS,I2C_CON2_SADD_POSE) + +/****************** Bit definition for I2C_ADDR1 register ************************/ + +#define I2C_ADDR1_OA1EN_POS 15U +#define I2C_ADDR1_OA1EN_MSK BIT(I2C_ADDR1_OA1EN_POS) + +#define I2C_ADDR1_OA1MODE_POS 10U +#define I2C_ADDR1_OA1MODE_MSK BIT(I2C_ADDR1_OA1MODE_POS) + +#define I2C_ADDR1_OA1_POSS 0U +#define I2C_ADDR1_OA1_POSE 9U +#define I2C_ADDR1_OA1_MSK BITS(I2C_ADDR1_OA1_POSS,I2C_ADDR1_OA1_POSE) + +/****************** Bit definition for I2C_ADDR2 register ************************/ + +#define I2C_ADDR2_OA2EN_POS 15U +#define I2C_ADDR2_OA2EN_MSK BIT(I2C_ADDR2_OA2EN_POS) + +#define I2C_ADDR2_OA2MSK_POSS 8U +#define I2C_ADDR2_OA2MSK_POSE 10U +#define I2C_ADDR2_OA2MSK_MSK BITS(I2C_ADDR2_OA2MSK_POSS,I2C_ADDR2_OA2MSK_POSE) + +#define I2C_ADDR2_OA2_POSS 1U +#define I2C_ADDR2_OA2_POSE 7U +#define I2C_ADDR2_OA2_MSK BITS(I2C_ADDR2_OA2_POSS,I2C_ADDR2_OA2_POSE) + +/****************** Bit definition for I2C_TIMINGR register ************************/ + +#define I2C_TIMINGR_PRESC_POSS 28U +#define I2C_TIMINGR_PRESC_POSE 31U +#define I2C_TIMINGR_PRESC_MSK BITS(I2C_TIMINGR_PRESC_POSS,I2C_TIMINGR_PRESC_POSE) + +#define I2C_TIMINGR_SCLDEL_POSS 20U +#define I2C_TIMINGR_SCLDEL_POSE 23U +#define I2C_TIMINGR_SCLDEL_MSK BITS(I2C_TIMINGR_SCLDEL_POSS,I2C_TIMINGR_SCLDEL_POSE) + +#define I2C_TIMINGR_SDADEL_POSS 16U +#define I2C_TIMINGR_SDADEL_POSE 19U +#define I2C_TIMINGR_SDADEL_MSK BITS(I2C_TIMINGR_SDADEL_POSS,I2C_TIMINGR_SDADEL_POSE) + +#define I2C_TIMINGR_SCLH_POSS 8U +#define I2C_TIMINGR_SCLH_POSE 15U +#define I2C_TIMINGR_SCLH_MSK BITS(I2C_TIMINGR_SCLH_POSS,I2C_TIMINGR_SCLH_POSE) + +#define I2C_TIMINGR_SCLL_POSS 0U +#define I2C_TIMINGR_SCLL_POSE 7U +#define I2C_TIMINGR_SCLL_MSK BITS(I2C_TIMINGR_SCLL_POSS,I2C_TIMINGR_SCLL_POSE) + +/****************** Bit definition for I2C_TIMEOUTR register ************************/ + +#define I2C_TIMEOUTR_TEXTEN_POS 31U +#define I2C_TIMEOUTR_TEXTEN_MSK BIT(I2C_TIMEOUTR_TEXTEN_POS) + +#define I2C_TIMEOUTR_TIMEOUTB_POSS 16U +#define I2C_TIMEOUTR_TIMEOUTB_POSE 27U +#define I2C_TIMEOUTR_TIMEOUTB_MSK BITS(I2C_TIMEOUTR_TIMEOUTB_POSS,I2C_TIMEOUTR_TIMEOUTB_POSE) + +#define I2C_TIMEOUTR_TIMEOUTEN_POS 15U +#define I2C_TIMEOUTR_TIMEOUTEN_MSK BIT(I2C_TIMEOUTR_TIMEOUTEN_POS) + +#define I2C_TIMEOUTR_TIDLE_POS 12U +#define I2C_TIMEOUTR_TIDLE_MSK BIT(I2C_TIMEOUTR_TIDLE_POS) + +#define I2C_TIMEOUTR_TIMEOUTA_POSS 0U +#define I2C_TIMEOUTR_TIMEOUTA_POSE 11U +#define I2C_TIMEOUTR_TIMEOUTA_MSK BITS(I2C_TIMEOUTR_TIMEOUTA_POSS,I2C_TIMEOUTR_TIMEOUTA_POSE) + +/****************** Bit definition for I2C_STAT register ************************/ + +#define I2C_STAT_ADDCODE_POSS 17U +#define I2C_STAT_ADDCODE_POSE 23U +#define I2C_STAT_ADDCODE_MSK BITS(I2C_STAT_ADDCODE_POSS,I2C_STAT_ADDCODE_POSE) + +#define I2C_STAT_DIR_POS 16U +#define I2C_STAT_DIR_MSK BIT(I2C_STAT_DIR_POS) + +#define I2C_STAT_BUSY_POS 15U +#define I2C_STAT_BUSY_MSK BIT(I2C_STAT_BUSY_POS) + +#define I2C_STAT_TCR_POS 11U +#define I2C_STAT_TCR_MSK BIT(I2C_STAT_TCR_POS) + +#define I2C_STAT_TC_POS 10U +#define I2C_STAT_TC_MSK BIT(I2C_STAT_TC_POS) + +#define I2C_STAT_RXTH_POS 9U +#define I2C_STAT_RXTH_MSK BIT(I2C_STAT_RXTH_POS) + +#define I2C_STAT_RXUD_POS 8U +#define I2C_STAT_RXUD_MSK BIT(I2C_STAT_RXUD_POS) + +#define I2C_STAT_RXOV_POS 7U +#define I2C_STAT_RXOV_MSK BIT(I2C_STAT_RXOV_POS) + +#define I2C_STAT_RXF_POS 6U +#define I2C_STAT_RXF_MSK BIT(I2C_STAT_RXF_POS) + +#define I2C_STAT_RXE_POS 5U +#define I2C_STAT_RXE_MSK BIT(I2C_STAT_RXE_POS) + +#define I2C_STAT_TXTH_POS 4U +#define I2C_STAT_TXTH_MSK BIT(I2C_STAT_TXTH_POS) + +#define I2C_STAT_TXUD_POS 3U +#define I2C_STAT_TXUD_MSK BIT(I2C_STAT_TXUD_POS) + +#define I2C_STAT_TXOV_POS 2U +#define I2C_STAT_TXOV_MSK BIT(I2C_STAT_TXOV_POS) + +#define I2C_STAT_TXF_POS 1U +#define I2C_STAT_TXF_MSK BIT(I2C_STAT_TXF_POS) + +#define I2C_STAT_TXE_POS 0U +#define I2C_STAT_TXE_MSK BIT(I2C_STAT_TXE_POS) + +/****************** Bit definition for I2C_FCON register ************************/ + +#define I2C_FCON_RXFTH_POSS 14U +#define I2C_FCON_RXFTH_POSE 15U +#define I2C_FCON_RXFTH_MSK BITS(I2C_FCON_RXFTH_POSS,I2C_FCON_RXFTH_POSE) + +#define I2C_FCON_RXFRST_POS 13U +#define I2C_FCON_RXFRST_MSK BIT(I2C_FCON_RXFRST_POS) + +#define I2C_FCON_RXFLV_POSS 8U +#define I2C_FCON_RXFLV_POSE 12U +#define I2C_FCON_RXFLV_MSK BITS(I2C_FCON_RXFLV_POSS,I2C_FCON_RXFLV_POSE) + +#define I2C_FCON_TXFTH_POSS 6U +#define I2C_FCON_TXFTH_POSE 7U +#define I2C_FCON_TXFTH_MSK BITS(I2C_FCON_TXFTH_POSS,I2C_FCON_TXFTH_POSE) + +#define I2C_FCON_TXFRST_POS 5U +#define I2C_FCON_TXFRST_MSK BIT(I2C_FCON_TXFRST_POS) + +#define I2C_FCON_TXFLV_POSS 0U +#define I2C_FCON_TXFLV_POSE 4U +#define I2C_FCON_TXFLV_MSK BITS(I2C_FCON_TXFLV_POSS,I2C_FCON_TXFLV_POSE) + +/****************** Bit definition for I2C_PECR register ************************/ + +#define I2C_PECR_PEC_POSS 0U +#define I2C_PECR_PEC_POSE 7U +#define I2C_PECR_PEC_MSK BITS(I2C_PECR_PEC_POSS,I2C_PECR_PEC_POSE) + +/****************** Bit definition for I2C_RXDATA register ************************/ + +#define I2C_RXDATA_RXDATA_POSS 0U +#define I2C_RXDATA_RXDATA_POSE 7U +#define I2C_RXDATA_RXDATA_MSK BITS(I2C_RXDATA_RXDATA_POSS,I2C_RXDATA_RXDATA_POSE) + +/****************** Bit definition for I2C_TXDATA register ************************/ + +#define I2C_TXDATA_TXDATA_POSS 0U +#define I2C_TXDATA_TXDATA_POSE 7U +#define I2C_TXDATA_TXDATA_MSK BITS(I2C_TXDATA_TXDATA_POSS,I2C_TXDATA_TXDATA_POSE) + +/****************** Bit definition for I2C_IER register ************************/ + +#define I2C_IER_ALERTIE_POS 20U +#define I2C_IER_ALERTIE_MSK BIT(I2C_IER_ALERTIE_POS) + +#define I2C_IER_TOUTIE_POS 19U +#define I2C_IER_TOUTIE_MSK BIT(I2C_IER_TOUTIE_POS) + +#define I2C_IER_PECEIE_POS 18U +#define I2C_IER_PECEIE_MSK BIT(I2C_IER_PECEIE_POS) + +#define I2C_IER_ARLOIE_POS 17U +#define I2C_IER_ARLOIE_MSK BIT(I2C_IER_ARLOIE_POS) + +#define I2C_IER_BERRIE_POS 16U +#define I2C_IER_BERRIE_MSK BIT(I2C_IER_BERRIE_POS) + +#define I2C_IER_STOPIE_POS 14U +#define I2C_IER_STOPIE_MSK BIT(I2C_IER_STOPIE_POS) + +#define I2C_IER_NACKIE_POS 13U +#define I2C_IER_NACKIE_MSK BIT(I2C_IER_NACKIE_POS) + +#define I2C_IER_ADDRIE_POS 12U +#define I2C_IER_ADDRIE_MSK BIT(I2C_IER_ADDRIE_POS) + +#define I2C_IER_TCRIE_POS 11U +#define I2C_IER_TCRIE_MSK BIT(I2C_IER_TCRIE_POS) + +#define I2C_IER_TCIE_POS 10U +#define I2C_IER_TCIE_MSK BIT(I2C_IER_TCIE_POS) + +#define I2C_IER_RXTHIE_POS 9U +#define I2C_IER_RXTHIE_MSK BIT(I2C_IER_RXTHIE_POS) + +#define I2C_IER_RXUDIE_POS 8U +#define I2C_IER_RXUDIE_MSK BIT(I2C_IER_RXUDIE_POS) + +#define I2C_IER_RXOVIE_POS 7U +#define I2C_IER_RXOVIE_MSK BIT(I2C_IER_RXOVIE_POS) + +#define I2C_IER_RXFIE_POS 6U +#define I2C_IER_RXFIE_MSK BIT(I2C_IER_RXFIE_POS) + +#define I2C_IER_TXTHIE_POS 4U +#define I2C_IER_TXTHIE_MSK BIT(I2C_IER_TXTHIE_POS) + +#define I2C_IER_TXUDIE_POS 3U +#define I2C_IER_TXUDIE_MSK BIT(I2C_IER_TXUDIE_POS) + +#define I2C_IER_TXOVIE_POS 2U +#define I2C_IER_TXOVIE_MSK BIT(I2C_IER_TXOVIE_POS) + +#define I2C_IER_TXEIE_POS 0U +#define I2C_IER_TXEIE_MSK BIT(I2C_IER_TXEIE_POS) + +/****************** Bit definition for I2C_IDR register ************************/ + +#define I2C_IDR_ALERTID_POS 20U +#define I2C_IDR_ALERTID_MSK BIT(I2C_IDR_ALERTID_POS) + +#define I2C_IDR_TOUTID_POS 19U +#define I2C_IDR_TOUTID_MSK BIT(I2C_IDR_TOUTID_POS) + +#define I2C_IDR_PECEID_POS 18U +#define I2C_IDR_PECEID_MSK BIT(I2C_IDR_PECEID_POS) + +#define I2C_IDR_ARLOID_POS 17U +#define I2C_IDR_ARLOID_MSK BIT(I2C_IDR_ARLOID_POS) + +#define I2C_IDR_BERRID_POS 16U +#define I2C_IDR_BERRID_MSK BIT(I2C_IDR_BERRID_POS) + +#define I2C_IDR_STOPID_POS 14U +#define I2C_IDR_STOPID_MSK BIT(I2C_IDR_STOPID_POS) + +#define I2C_IDR_NACKID_POS 13U +#define I2C_IDR_NACKID_MSK BIT(I2C_IDR_NACKID_POS) + +#define I2C_IDR_ADDRID_POS 12U +#define I2C_IDR_ADDRID_MSK BIT(I2C_IDR_ADDRID_POS) + +#define I2C_IDR_TCRID_POS 11U +#define I2C_IDR_TCRID_MSK BIT(I2C_IDR_TCRID_POS) + +#define I2C_IDR_TCID_POS 10U +#define I2C_IDR_TCID_MSK BIT(I2C_IDR_TCID_POS) + +#define I2C_IDR_RXTHID_POS 9U +#define I2C_IDR_RXTHID_MSK BIT(I2C_IDR_RXTHID_POS) + +#define I2C_IDR_RXUDID_POS 8U +#define I2C_IDR_RXUDID_MSK BIT(I2C_IDR_RXUDID_POS) + +#define I2C_IDR_RXOVID_POS 7U +#define I2C_IDR_RXOVID_MSK BIT(I2C_IDR_RXOVID_POS) + +#define I2C_IDR_RXFID_POS 6U +#define I2C_IDR_RXFID_MSK BIT(I2C_IDR_RXFID_POS) + +#define I2C_IDR_TXTHID_POS 4U +#define I2C_IDR_TXTHID_MSK BIT(I2C_IDR_TXTHID_POS) + +#define I2C_IDR_TXUDID_POS 3U +#define I2C_IDR_TXUDID_MSK BIT(I2C_IDR_TXUDID_POS) + +#define I2C_IDR_TXOVID_POS 2U +#define I2C_IDR_TXOVID_MSK BIT(I2C_IDR_TXOVID_POS) + +#define I2C_IDR_TXEID_POS 0U +#define I2C_IDR_TXEID_MSK BIT(I2C_IDR_TXEID_POS) + +/****************** Bit definition for I2C_IVS register ************************/ + +#define I2C_IVS_ALERTIV_POS 20U +#define I2C_IVS_ALERTIV_MSK BIT(I2C_IVS_ALERTIV_POS) + +#define I2C_IVS_TOUTIV_POS 19U +#define I2C_IVS_TOUTIV_MSK BIT(I2C_IVS_TOUTIV_POS) + +#define I2C_IVS_PECEIV_POS 18U +#define I2C_IVS_PECEIV_MSK BIT(I2C_IVS_PECEIV_POS) + +#define I2C_IVS_ARLOIV_POS 17U +#define I2C_IVS_ARLOIV_MSK BIT(I2C_IVS_ARLOIV_POS) + +#define I2C_IVS_BERRIV_POS 16U +#define I2C_IVS_BERRIV_MSK BIT(I2C_IVS_BERRIV_POS) + +#define I2C_IVS_STOPIV_POS 14U +#define I2C_IVS_STOPIV_MSK BIT(I2C_IVS_STOPIV_POS) + +#define I2C_IVS_NACKIV_POS 13U +#define I2C_IVS_NACKIV_MSK BIT(I2C_IVS_NACKIV_POS) + +#define I2C_IVS_ADDRIV_POS 12U +#define I2C_IVS_ADDRIV_MSK BIT(I2C_IVS_ADDRIV_POS) + +#define I2C_IVS_TCRIV_POS 11U +#define I2C_IVS_TCRIV_MSK BIT(I2C_IVS_TCRIV_POS) + +#define I2C_IVS_TCIV_POS 10U +#define I2C_IVS_TCIV_MSK BIT(I2C_IVS_TCIV_POS) + +#define I2C_IVS_RXTHIV_POS 9U +#define I2C_IVS_RXTHIV_MSK BIT(I2C_IVS_RXTHIV_POS) + +#define I2C_IVS_RXUDIV_POS 8U +#define I2C_IVS_RXUDIV_MSK BIT(I2C_IVS_RXUDIV_POS) + +#define I2C_IVS_RXOVIV_POS 7U +#define I2C_IVS_RXOVIV_MSK BIT(I2C_IVS_RXOVIV_POS) + +#define I2C_IVS_RXFIV_POS 6U +#define I2C_IVS_RXFIV_MSK BIT(I2C_IVS_RXFIV_POS) + +#define I2C_IVS_TXTHIV_POS 4U +#define I2C_IVS_TXTHIV_MSK BIT(I2C_IVS_TXTHIV_POS) + +#define I2C_IVS_TXUDIV_POS 3U +#define I2C_IVS_TXUDIV_MSK BIT(I2C_IVS_TXUDIV_POS) + +#define I2C_IVS_TXOVIV_POS 2U +#define I2C_IVS_TXOVIV_MSK BIT(I2C_IVS_TXOVIV_POS) + +#define I2C_IVS_TXEIV_POS 0U +#define I2C_IVS_TXEIV_MSK BIT(I2C_IVS_TXEIV_POS) + +/****************** Bit definition for I2C_RIF register ************************/ + +#define I2C_RIF_ALERTRI_POS 20U +#define I2C_RIF_ALERTRI_MSK BIT(I2C_RIF_ALERTRI_POS) + +#define I2C_RIF_TOUTRI_POS 19U +#define I2C_RIF_TOUTRI_MSK BIT(I2C_RIF_TOUTRI_POS) + +#define I2C_RIF_PECERI_POS 18U +#define I2C_RIF_PECERI_MSK BIT(I2C_RIF_PECERI_POS) + +#define I2C_RIF_ARLORI_POS 17U +#define I2C_RIF_ARLORI_MSK BIT(I2C_RIF_ARLORI_POS) + +#define I2C_RIF_BERRRI_POS 16U +#define I2C_RIF_BERRRI_MSK BIT(I2C_RIF_BERRRI_POS) + +#define I2C_RIF_STOPRI_POS 14U +#define I2C_RIF_STOPRI_MSK BIT(I2C_RIF_STOPRI_POS) + +#define I2C_RIF_NACKRI_POS 13U +#define I2C_RIF_NACKRI_MSK BIT(I2C_RIF_NACKRI_POS) + +#define I2C_RIF_ADDRRI_POS 12U +#define I2C_RIF_ADDRRI_MSK BIT(I2C_RIF_ADDRRI_POS) + +#define I2C_RIF_TCRRI_POS 11U +#define I2C_RIF_TCRRI_MSK BIT(I2C_RIF_TCRRI_POS) + +#define I2C_RIF_TCRI_POS 10U +#define I2C_RIF_TCRI_MSK BIT(I2C_RIF_TCRI_POS) + +#define I2C_RIF_RXTHRI_POS 9U +#define I2C_RIF_RXTHRI_MSK BIT(I2C_RIF_RXTHRI_POS) + +#define I2C_RIF_RXUDRI_POS 8U +#define I2C_RIF_RXUDRI_MSK BIT(I2C_RIF_RXUDRI_POS) + +#define I2C_RIF_RXOVRI_POS 7U +#define I2C_RIF_RXOVRI_MSK BIT(I2C_RIF_RXOVRI_POS) + +#define I2C_RIF_RXFRI_POS 6U +#define I2C_RIF_RXFRI_MSK BIT(I2C_RIF_RXFRI_POS) + +#define I2C_RIF_TXTHRI_POS 4U +#define I2C_RIF_TXTHRI_MSK BIT(I2C_RIF_TXTHRI_POS) + +#define I2C_RIF_TXUDRI_POS 3U +#define I2C_RIF_TXUDRI_MSK BIT(I2C_RIF_TXUDRI_POS) + +#define I2C_RIF_TXOVRI_POS 2U +#define I2C_RIF_TXOVRI_MSK BIT(I2C_RIF_TXOVRI_POS) + +#define I2C_RIF_TXERI_POS 0U +#define I2C_RIF_TXERI_MSK BIT(I2C_RIF_TXERI_POS) + +/****************** Bit definition for I2C_IFM register ************************/ + +#define I2C_IFM_ALERTFM_POS 20U +#define I2C_IFM_ALERTFM_MSK BIT(I2C_IFM_ALERTFM_POS) + +#define I2C_IFM_TOUTFM_POS 19U +#define I2C_IFM_TOUTFM_MSK BIT(I2C_IFM_TOUTFM_POS) + +#define I2C_IFM_PECEFM_POS 18U +#define I2C_IFM_PECEFM_MSK BIT(I2C_IFM_PECEFM_POS) + +#define I2C_IFM_ARLOFM_POS 17U +#define I2C_IFM_ARLOFM_MSK BIT(I2C_IFM_ARLOFM_POS) + +#define I2C_IFM_BERRFM_POS 16U +#define I2C_IFM_BERRFM_MSK BIT(I2C_IFM_BERRFM_POS) + +#define I2C_IFM_STOPFM_POS 14U +#define I2C_IFM_STOPFM_MSK BIT(I2C_IFM_STOPFM_POS) + +#define I2C_IFM_NACKFM_POS 13U +#define I2C_IFM_NACKFM_MSK BIT(I2C_IFM_NACKFM_POS) + +#define I2C_IFM_ADDRFM_POS 12U +#define I2C_IFM_ADDRFM_MSK BIT(I2C_IFM_ADDRFM_POS) + +#define I2C_IFM_TCRFM_POS 11U +#define I2C_IFM_TCRFM_MSK BIT(I2C_IFM_TCRFM_POS) + +#define I2C_IFM_TCFM_POS 10U +#define I2C_IFM_TCFM_MSK BIT(I2C_IFM_TCFM_POS) + +#define I2C_IFM_RXTHFM_POS 9U +#define I2C_IFM_RXTHFM_MSK BIT(I2C_IFM_RXTHFM_POS) + +#define I2C_IFM_RXUDFM_POS 8U +#define I2C_IFM_RXUDFM_MSK BIT(I2C_IFM_RXUDFM_POS) + +#define I2C_IFM_RXOVFM_POS 7U +#define I2C_IFM_RXOVFM_MSK BIT(I2C_IFM_RXOVFM_POS) + +#define I2C_IFM_RXFFM_POS 6U +#define I2C_IFM_RXFFM_MSK BIT(I2C_IFM_RXFFM_POS) + +#define I2C_IFM_TXTHFM_POS 4U +#define I2C_IFM_TXTHFM_MSK BIT(I2C_IFM_TXTHFM_POS) + +#define I2C_IFM_TXUDFM_POS 3U +#define I2C_IFM_TXUDFM_MSK BIT(I2C_IFM_TXUDFM_POS) + +#define I2C_IFM_TXOVFM_POS 2U +#define I2C_IFM_TXOVFM_MSK BIT(I2C_IFM_TXOVFM_POS) + +#define I2C_IFM_TXEFM_POS 0U +#define I2C_IFM_TXEFM_MSK BIT(I2C_IFM_TXEFM_POS) + +/****************** Bit definition for I2C_ICR register ************************/ + +#define I2C_ICR_ALERTIC_POS 20U +#define I2C_ICR_ALERTIC_MSK BIT(I2C_ICR_ALERTIC_POS) + +#define I2C_ICR_TOUTIC_POS 19U +#define I2C_ICR_TOUTIC_MSK BIT(I2C_ICR_TOUTIC_POS) + +#define I2C_ICR_PECEIC_POS 18U +#define I2C_ICR_PECEIC_MSK BIT(I2C_ICR_PECEIC_POS) + +#define I2C_ICR_ARLOIC_POS 17U +#define I2C_ICR_ARLOIC_MSK BIT(I2C_ICR_ARLOIC_POS) + +#define I2C_ICR_BERRIC_POS 16U +#define I2C_ICR_BERRIC_MSK BIT(I2C_ICR_BERRIC_POS) + +#define I2C_ICR_STOPIC_POS 14U +#define I2C_ICR_STOPIC_MSK BIT(I2C_ICR_STOPIC_POS) + +#define I2C_ICR_NACKIC_POS 13U +#define I2C_ICR_NACKIC_MSK BIT(I2C_ICR_NACKIC_POS) + +#define I2C_ICR_ADDRIC_POS 12U +#define I2C_ICR_ADDRIC_MSK BIT(I2C_ICR_ADDRIC_POS) + +#define I2C_ICR_TCRIC_POS 11U +#define I2C_ICR_TCRIC_MSK BIT(I2C_ICR_TCRIC_POS) + +#define I2C_ICR_TCIC_POS 10U +#define I2C_ICR_TCIC_MSK BIT(I2C_ICR_TCIC_POS) + +#define I2C_ICR_RXTHIC_POS 9U +#define I2C_ICR_RXTHIC_MSK BIT(I2C_ICR_RXTHIC_POS) + +#define I2C_ICR_RXUDIC_POS 8U +#define I2C_ICR_RXUDIC_MSK BIT(I2C_ICR_RXUDIC_POS) + +#define I2C_ICR_RXOVIC_POS 7U +#define I2C_ICR_RXOVIC_MSK BIT(I2C_ICR_RXOVIC_POS) + +#define I2C_ICR_RXFIC_POS 6U +#define I2C_ICR_RXFIC_MSK BIT(I2C_ICR_RXFIC_POS) + +#define I2C_ICR_TXTHIC_POS 4U +#define I2C_ICR_TXTHIC_MSK BIT(I2C_ICR_TXTHIC_POS) + +#define I2C_ICR_TXUDIC_POS 3U +#define I2C_ICR_TXUDIC_MSK BIT(I2C_ICR_TXUDIC_POS) + +#define I2C_ICR_TXOVIC_POS 2U +#define I2C_ICR_TXOVIC_MSK BIT(I2C_ICR_TXOVIC_POS) + +#define I2C_ICR_TXEIC_POS 0U +#define I2C_ICR_TXEIC_MSK BIT(I2C_ICR_TXEIC_POS) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t ADDR1; + __IO uint32_t ADDR2; + __IO uint32_t TIMINGR; + __IO uint32_t TIMEOUTR; + __I uint32_t STAT; + __IO uint32_t FCON; + __I uint32_t PECR; + __I uint32_t RXDATA; + __O uint32_t TXDATA; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} I2C_TypeDef; + +/****************** Bit definition for CAN_CON register ************************/ + +#define CAN_CON_DBGSTP_POS 16U +#define CAN_CON_DBGSTP_MSK BIT(CAN_CON_DBGSTP_POS) + +#define CAN_CON_RST_POS 15U +#define CAN_CON_RST_MSK BIT(CAN_CON_RST_POS) + +#define CAN_CON_TTCEN_POS 7U +#define CAN_CON_TTCEN_MSK BIT(CAN_CON_TTCEN_POS) + +#define CAN_CON_ABOFFEN_POS 6U +#define CAN_CON_ABOFFEN_MSK BIT(CAN_CON_ABOFFEN_POS) + +#define CAN_CON_AWKEN_POS 5U +#define CAN_CON_AWKEN_MSK BIT(CAN_CON_AWKEN_POS) + +#define CAN_CON_ARTXDIS_POS 4U +#define CAN_CON_ARTXDIS_MSK BIT(CAN_CON_ARTXDIS_POS) + +#define CAN_CON_RXFOPM_POS 3U +#define CAN_CON_RXFOPM_MSK BIT(CAN_CON_RXFOPM_POS) + +#define CAN_CON_TXMP_POS 2U +#define CAN_CON_TXMP_MSK BIT(CAN_CON_TXMP_POS) + +#define CAN_CON_SLPREQ_POS 1U +#define CAN_CON_SLPREQ_MSK BIT(CAN_CON_SLPREQ_POS) + +#define CAN_CON_INIREQ_POS 0U +#define CAN_CON_INIREQ_MSK BIT(CAN_CON_INIREQ_POS) + +/****************** Bit definition for CAN_STAT register ************************/ + +#define CAN_STAT_RX_POS 11U +#define CAN_STAT_RX_MSK BIT(CAN_STAT_RX_POS) + +#define CAN_STAT_PRESMP_POS 10U +#define CAN_STAT_PRESMP_MSK BIT(CAN_STAT_PRESMP_POS) + +#define CAN_STAT_RXSTAT_POS 9U +#define CAN_STAT_RXSTAT_MSK BIT(CAN_STAT_RXSTAT_POS) + +#define CAN_STAT_TXSTAT_POS 8U +#define CAN_STAT_TXSTAT_MSK BIT(CAN_STAT_TXSTAT_POS) + +#define CAN_STAT_SLPIF_POS 4U +#define CAN_STAT_SLPIF_MSK BIT(CAN_STAT_SLPIF_POS) + +#define CAN_STAT_WKIF_POS 3U +#define CAN_STAT_WKIF_MSK BIT(CAN_STAT_WKIF_POS) + +#define CAN_STAT_ERRIF_POS 2U +#define CAN_STAT_ERRIF_MSK BIT(CAN_STAT_ERRIF_POS) + +#define CAN_STAT_SLPSTAT_POS 1U +#define CAN_STAT_SLPSTAT_MSK BIT(CAN_STAT_SLPSTAT_POS) + +#define CAN_STAT_INISTAT_POS 0U +#define CAN_STAT_INISTAT_MSK BIT(CAN_STAT_INISTAT_POS) + +/****************** Bit definition for CAN_IFC register ************************/ + +#define CAN_IFC_SLPIFC_POS 4U +#define CAN_IFC_SLPIFC_MSK BIT(CAN_IFC_SLPIFC_POS) + +#define CAN_IFC_WKIFC_POS 3U +#define CAN_IFC_WKIFC_MSK BIT(CAN_IFC_WKIFC_POS) + +#define CAN_IFC_ERRIFC_POS 2U +#define CAN_IFC_ERRIFC_MSK BIT(CAN_IFC_ERRIFC_POS) + +/****************** Bit definition for CAN_TXSTAT register ************************/ + +#define CAN_TXSTAT_TXM2LPF_POS 31U +#define CAN_TXSTAT_TXM2LPF_MSK BIT(CAN_TXSTAT_TXM2LPF_POS) + +#define CAN_TXSTAT_TXM1LPF_POS 30U +#define CAN_TXSTAT_TXM1LPF_MSK BIT(CAN_TXSTAT_TXM1LPF_POS) + +#define CAN_TXSTAT_TXM0LPF_POS 29U +#define CAN_TXSTAT_TXM0LPF_MSK BIT(CAN_TXSTAT_TXM0LPF_POS) + +#define CAN_TXSTAT_TXM2EF_POS 28U +#define CAN_TXSTAT_TXM2EF_MSK BIT(CAN_TXSTAT_TXM2EF_POS) + +#define CAN_TXSTAT_TXM1EF_POS 27U +#define CAN_TXSTAT_TXM1EF_MSK BIT(CAN_TXSTAT_TXM1EF_POS) + +#define CAN_TXSTAT_TXM0EF_POS 26U +#define CAN_TXSTAT_TXM0EF_MSK BIT(CAN_TXSTAT_TXM0EF_POS) + +#define CAN_TXSTAT_CODE_POSS 24U +#define CAN_TXSTAT_CODE_POSE 25U +#define CAN_TXSTAT_CODE_MSK BITS(CAN_TXSTAT_CODE_POSS,CAN_TXSTAT_CODE_POSE) + +#define CAN_TXSTAT_M2STPREQ_POS 23U +#define CAN_TXSTAT_M2STPREQ_MSK BIT(CAN_TXSTAT_M2STPREQ_POS) + +#define CAN_TXSTAT_M2TXERR_POS 19U +#define CAN_TXSTAT_M2TXERR_MSK BIT(CAN_TXSTAT_M2TXERR_POS) + +#define CAN_TXSTAT_M2ARBLST_POS 18U +#define CAN_TXSTAT_M2ARBLST_MSK BIT(CAN_TXSTAT_M2ARBLST_POS) + +#define CAN_TXSTAT_M2TXC_POS 17U +#define CAN_TXSTAT_M2TXC_MSK BIT(CAN_TXSTAT_M2TXC_POS) + +#define CAN_TXSTAT_M2REQC_POS 16U +#define CAN_TXSTAT_M2REQC_MSK BIT(CAN_TXSTAT_M2REQC_POS) + +#define CAN_TXSTAT_M1STPREQ_POS 15U +#define CAN_TXSTAT_M1STPREQ_MSK BIT(CAN_TXSTAT_M1STPREQ_POS) + +#define CAN_TXSTAT_M1TXERR_POS 11U +#define CAN_TXSTAT_M1TXERR_MSK BIT(CAN_TXSTAT_M1TXERR_POS) + +#define CAN_TXSTAT_M1ARBLST_POS 10U +#define CAN_TXSTAT_M1ARBLST_MSK BIT(CAN_TXSTAT_M1ARBLST_POS) + +#define CAN_TXSTAT_M1TXC_POS 9U +#define CAN_TXSTAT_M1TXC_MSK BIT(CAN_TXSTAT_M1TXC_POS) + +#define CAN_TXSTAT_M1REQC_POS 8U +#define CAN_TXSTAT_M1REQC_MSK BIT(CAN_TXSTAT_M1REQC_POS) + +#define CAN_TXSTAT_M0STPREQ_POS 7U +#define CAN_TXSTAT_M0STPREQ_MSK BIT(CAN_TXSTAT_M0STPREQ_POS) + +#define CAN_TXSTAT_M0TXERR_POS 3U +#define CAN_TXSTAT_M0TXERR_MSK BIT(CAN_TXSTAT_M0TXERR_POS) + +#define CAN_TXSTAT_M0ARBLST_POS 2U +#define CAN_TXSTAT_M0ARBLST_MSK BIT(CAN_TXSTAT_M0ARBLST_POS) + +#define CAN_TXSTAT_M0TXC_POS 1U +#define CAN_TXSTAT_M0TXC_MSK BIT(CAN_TXSTAT_M0TXC_POS) + +#define CAN_TXSTAT_M0REQC_POS 0U +#define CAN_TXSTAT_M0REQC_MSK BIT(CAN_TXSTAT_M0REQC_POS) + +/****************** Bit definition for CAN_TXSTATC register ************************/ + +#define CAN_TXSTATC_M2TXERR_POS 19U +#define CAN_TXSTATC_M2TXERR_MSK BIT(CAN_TXSTATC_M2TXERR_POS) + +#define CAN_TXSTATC_M2ARBLST_POS 18U +#define CAN_TXSTATC_M2ARBLST_MSK BIT(CAN_TXSTATC_M2ARBLST_POS) + +#define CAN_TXSTATC_M2TXC_POS 17U +#define CAN_TXSTATC_M2TXC_MSK BIT(CAN_TXSTATC_M2TXC_POS) + +#define CAN_TXSTATC_M2REQC_POS 16U +#define CAN_TXSTATC_M2REQC_MSK BIT(CAN_TXSTATC_M2REQC_POS) + +#define CAN_TXSTATC_M1TXERR_POS 11U +#define CAN_TXSTATC_M1TXERR_MSK BIT(CAN_TXSTATC_M1TXERR_POS) + +#define CAN_TXSTATC_M1ARBLST_POS 10U +#define CAN_TXSTATC_M1ARBLST_MSK BIT(CAN_TXSTATC_M1ARBLST_POS) + +#define CAN_TXSTATC_M1TXC_POS 9U +#define CAN_TXSTATC_M1TXC_MSK BIT(CAN_TXSTATC_M1TXC_POS) + +#define CAN_TXSTATC_M1REQC_POS 8U +#define CAN_TXSTATC_M1REQC_MSK BIT(CAN_TXSTATC_M1REQC_POS) + +#define CAN_TXSTATC_M0TXERR_POS 3U +#define CAN_TXSTATC_M0TXERR_MSK BIT(CAN_TXSTATC_M0TXERR_POS) + +#define CAN_TXSTATC_M0ARBLST_POS 2U +#define CAN_TXSTATC_M0ARBLST_MSK BIT(CAN_TXSTATC_M0ARBLST_POS) + +#define CAN_TXSTATC_M0TXC_POS 1U +#define CAN_TXSTATC_M0TXC_MSK BIT(CAN_TXSTATC_M0TXC_POS) + +#define CAN_TXSTATC_M0REQC_POS 0U +#define CAN_TXSTATC_M0REQC_MSK BIT(CAN_TXSTATC_M0REQC_POS) + +/****************** Bit definition for CAN_RXF0 register ************************/ + +#define CAN_RXF0_FREE_POS 5U +#define CAN_RXF0_FREE_MSK BIT(CAN_RXF0_FREE_POS) + +#define CAN_RXF0_OVR_POS 4U +#define CAN_RXF0_OVR_MSK BIT(CAN_RXF0_OVR_POS) + +#define CAN_RXF0_FULL_POS 3U +#define CAN_RXF0_FULL_MSK BIT(CAN_RXF0_FULL_POS) + +#define CAN_RXF0_PEND_POSS 0U +#define CAN_RXF0_PEND_POSE 1U +#define CAN_RXF0_PEND_MSK BITS(CAN_RXF0_PEND_POSS,CAN_RXF0_PEND_POSE) + +/****************** Bit definition for CAN_RXF0C register ************************/ + +#define CAN_RXF0C_OVRC_POS 4U +#define CAN_RXF0C_OVRC_MSK BIT(CAN_RXF0C_OVRC_POS) + +#define CAN_RXF0C_FULLC_POS 3U +#define CAN_RXF0C_FULLC_MSK BIT(CAN_RXF0C_FULLC_POS) + +/****************** Bit definition for CAN_RXF1 register ************************/ + +#define CAN_RXF1_FREE_POS 5U +#define CAN_RXF1_FREE_MSK BIT(CAN_RXF1_FREE_POS) + +#define CAN_RXF1_OVR_POS 4U +#define CAN_RXF1_OVR_MSK BIT(CAN_RXF1_OVR_POS) + +#define CAN_RXF1_FULL_POS 3U +#define CAN_RXF1_FULL_MSK BIT(CAN_RXF1_FULL_POS) + +#define CAN_RXF1_PEND_POSS 0U +#define CAN_RXF1_PEND_POSE 1U +#define CAN_RXF1_PEND_MSK BITS(CAN_RXF1_PEND_POSS,CAN_RXF1_PEND_POSE) + +/****************** Bit definition for CAN_RXF1C register ************************/ + +#define CAN_RXF1C_OVRC_POS 4U +#define CAN_RXF1C_OVRC_MSK BIT(CAN_RXF1C_OVRC_POS) + +#define CAN_RXF1C_FULLC_POS 3U +#define CAN_RXF1C_FULLC_MSK BIT(CAN_RXF1C_FULLC_POS) + +/****************** Bit definition for CAN_IE register ************************/ + +#define CAN_IE_SLPIE_POS 17U +#define CAN_IE_SLPIE_MSK BIT(CAN_IE_SLPIE_POS) + +#define CAN_IE_WKIE_POS 16U +#define CAN_IE_WKIE_MSK BIT(CAN_IE_WKIE_POS) + +#define CAN_IE_ERRIE_POS 15U +#define CAN_IE_ERRIE_MSK BIT(CAN_IE_ERRIE_POS) + +#define CAN_IE_PRERRIE_POS 11U +#define CAN_IE_PRERRIE_MSK BIT(CAN_IE_PRERRIE_POS) + +#define CAN_IE_BOFFIE_POS 10U +#define CAN_IE_BOFFIE_MSK BIT(CAN_IE_BOFFIE_POS) + +#define CAN_IE_PERRIE_POS 9U +#define CAN_IE_PERRIE_MSK BIT(CAN_IE_PERRIE_POS) + +#define CAN_IE_WARNIE_POS 8U +#define CAN_IE_WARNIE_MSK BIT(CAN_IE_WARNIE_POS) + +#define CAN_IE_F1OVRIE_POS 6U +#define CAN_IE_F1OVRIE_MSK BIT(CAN_IE_F1OVRIE_POS) + +#define CAN_IE_F1FULIE_POS 5U +#define CAN_IE_F1FULIE_MSK BIT(CAN_IE_F1FULIE_POS) + +#define CAN_IE_F1PIE_POS 4U +#define CAN_IE_F1PIE_MSK BIT(CAN_IE_F1PIE_POS) + +#define CAN_IE_F0OVRIE_POS 3U +#define CAN_IE_F0OVRIE_MSK BIT(CAN_IE_F0OVRIE_POS) + +#define CAN_IE_F0FULIE_POS 2U +#define CAN_IE_F0FULIE_MSK BIT(CAN_IE_F0FULIE_POS) + +#define CAN_IE_F0PIE_POS 1U +#define CAN_IE_F0PIE_MSK BIT(CAN_IE_F0PIE_POS) + +#define CAN_IE_TXMEIE_POS 0U +#define CAN_IE_TXMEIE_MSK BIT(CAN_IE_TXMEIE_POS) + +/****************** Bit definition for CAN_ERRSTAT register ************************/ + +#define CAN_ERRSTAT_RXERRC_POSS 24U +#define CAN_ERRSTAT_RXERRC_POSE 31U +#define CAN_ERRSTAT_RXERRC_MSK BITS(CAN_ERRSTAT_RXERRC_POSS,CAN_ERRSTAT_RXERRC_POSE) + +#define CAN_ERRSTAT_TXERRC_POSS 16U +#define CAN_ERRSTAT_TXERRC_POSE 23U +#define CAN_ERRSTAT_TXERRC_MSK BITS(CAN_ERRSTAT_TXERRC_POSS,CAN_ERRSTAT_TXERRC_POSE) + +#define CAN_ERRSTAT_PRERRF_POSS 4U +#define CAN_ERRSTAT_PRERRF_POSE 6U +#define CAN_ERRSTAT_PRERRF_MSK BITS(CAN_ERRSTAT_PRERRF_POSS,CAN_ERRSTAT_PRERRF_POSE) + +#define CAN_ERRSTAT_BOFF_POS 2U +#define CAN_ERRSTAT_BOFF_MSK BIT(CAN_ERRSTAT_BOFF_POS) + +#define CAN_ERRSTAT_PERRF_POS 1U +#define CAN_ERRSTAT_PERRF_MSK BIT(CAN_ERRSTAT_PERRF_POS) + +#define CAN_ERRSTAT_WARNF_POS 0U +#define CAN_ERRSTAT_WARNF_MSK BIT(CAN_ERRSTAT_WARNF_POS) + +/****************** Bit definition for CAN_BTIME register ************************/ + +#define CAN_BTIME_SILENT_POS 31U +#define CAN_BTIME_SILENT_MSK BIT(CAN_BTIME_SILENT_POS) + +#define CAN_BTIME_LOOP_POS 30U +#define CAN_BTIME_LOOP_MSK BIT(CAN_BTIME_LOOP_POS) + +#define CAN_BTIME_RESJW_POSS 24U +#define CAN_BTIME_RESJW_POSE 25U +#define CAN_BTIME_RESJW_MSK BITS(CAN_BTIME_RESJW_POSS,CAN_BTIME_RESJW_POSE) + +#define CAN_BTIME_SEG2_POSS 20U +#define CAN_BTIME_SEG2_POSE 22U +#define CAN_BTIME_SEG2_MSK BITS(CAN_BTIME_SEG2_POSS,CAN_BTIME_SEG2_POSE) + +#define CAN_BTIME_SEG1_POSS 16U +#define CAN_BTIME_SEG1_POSE 19U +#define CAN_BTIME_SEG1_MSK BITS(CAN_BTIME_SEG1_POSS,CAN_BTIME_SEG1_POSE) + +#define CAN_BTIME_BPSC_POSS 0U +#define CAN_BTIME_BPSC_POSE 9U +#define CAN_BTIME_BPSC_MSK BITS(CAN_BTIME_BPSC_POSS,CAN_BTIME_BPSC_POSE) + +/****************** Bit definition for CAN_TXID0 register ************************/ + +#define CAN_TXID0_STDID_POSS 21U +#define CAN_TXID0_STDID_POSE 31U +#define CAN_TXID0_STDID_MSK BITS(CAN_TXID0_STDID_POSS,CAN_TXID0_STDID_POSE) + +#define CAN_TXID0_EXID_POSS 3U +#define CAN_TXID0_EXID_POSE 20U +#define CAN_TXID0_EXID_MSK BITS(CAN_TXID0_EXID_POSS,CAN_TXID0_EXID_POSE) + +#define CAN_TXID0_IDE_POS 2U +#define CAN_TXID0_IDE_MSK BIT(CAN_TXID0_IDE_POS) + +#define CAN_TXID0_RTR_POS 1U +#define CAN_TXID0_RTR_MSK BIT(CAN_TXID0_RTR_POS) + +#define CAN_TXID0_TXMREQ_POS 0U +#define CAN_TXID0_TXMREQ_MSK BIT(CAN_TXID0_TXMREQ_POS) + +/****************** Bit definition for CAN_TXFCON0 register ************************/ + +#define CAN_TXFCON0_STAMP_POSS 16U +#define CAN_TXFCON0_STAMP_POSE 31U +#define CAN_TXFCON0_STAMP_MSK BITS(CAN_TXFCON0_STAMP_POSS,CAN_TXFCON0_STAMP_POSE) + +#define CAN_TXFCON0_TXGT_POS 8U +#define CAN_TXFCON0_TXGT_MSK BIT(CAN_TXFCON0_TXGT_POS) + +#define CAN_TXFCON0_DLEN_POSS 0U +#define CAN_TXFCON0_DLEN_POSE 3U +#define CAN_TXFCON0_DLEN_MSK BITS(CAN_TXFCON0_DLEN_POSS,CAN_TXFCON0_DLEN_POSE) + +/****************** Bit definition for CAN_TXDL0 register ************************/ + +#define CAN_TXDL0_BYTE3_POSS 24U +#define CAN_TXDL0_BYTE3_POSE 31U +#define CAN_TXDL0_BYTE3_MSK BITS(CAN_TXDL0_BYTE3_POSS,CAN_TXDL0_BYTE3_POSE) + +#define CAN_TXDL0_BYTE2_POSS 16U +#define CAN_TXDL0_BYTE2_POSE 23U +#define CAN_TXDL0_BYTE2_MSK BITS(CAN_TXDL0_BYTE2_POSS,CAN_TXDL0_BYTE2_POSE) + +#define CAN_TXDL0_BYTE1_POSS 8U +#define CAN_TXDL0_BYTE1_POSE 15U +#define CAN_TXDL0_BYTE1_MSK BITS(CAN_TXDL0_BYTE1_POSS,CAN_TXDL0_BYTE1_POSE) + +#define CAN_TXDL0_BYTE0_POSS 0U +#define CAN_TXDL0_BYTE0_POSE 7U +#define CAN_TXDL0_BYTE0_MSK BITS(CAN_TXDL0_BYTE0_POSS,CAN_TXDL0_BYTE0_POSE) + +/****************** Bit definition for CAN_TXDH0 register ************************/ + +#define CAN_TXDH0_BYTE7_POSS 24U +#define CAN_TXDH0_BYTE7_POSE 31U +#define CAN_TXDH0_BYTE7_MSK BITS(CAN_TXDH0_BYTE7_POSS,CAN_TXDH0_BYTE7_POSE) + +#define CAN_TXDH0_BYTE6_POSS 16U +#define CAN_TXDH0_BYTE6_POSE 23U +#define CAN_TXDH0_BYTE6_MSK BITS(CAN_TXDH0_BYTE6_POSS,CAN_TXDH0_BYTE6_POSE) + +#define CAN_TXDH0_BYTE5_POSS 8U +#define CAN_TXDH0_BYTE5_POSE 15U +#define CAN_TXDH0_BYTE5_MSK BITS(CAN_TXDH0_BYTE5_POSS,CAN_TXDH0_BYTE5_POSE) + +#define CAN_TXDH0_BYTE4_POSS 0U +#define CAN_TXDH0_BYTE4_POSE 7U +#define CAN_TXDH0_BYTE4_MSK BITS(CAN_TXDH0_BYTE4_POSS,CAN_TXDH0_BYTE4_POSE) + +/****************** Bit definition for CAN_TXID1 register ************************/ + +#define CAN_TXID1_STDID_POSS 21U +#define CAN_TXID1_STDID_POSE 31U +#define CAN_TXID1_STDID_MSK BITS(CAN_TXID1_STDID_POSS,CAN_TXID1_STDID_POSE) + +#define CAN_TXID1_EXID_POSS 3U +#define CAN_TXID1_EXID_POSE 20U +#define CAN_TXID1_EXID_MSK BITS(CAN_TXID1_EXID_POSS,CAN_TXID1_EXID_POSE) + +#define CAN_TXID1_IDE_POS 2U +#define CAN_TXID1_IDE_MSK BIT(CAN_TXID1_IDE_POS) + +#define CAN_TXID1_RTR_POS 1U +#define CAN_TXID1_RTR_MSK BIT(CAN_TXID1_RTR_POS) + +#define CAN_TXID1_TXMREQ_POS 0U +#define CAN_TXID1_TXMREQ_MSK BIT(CAN_TXID1_TXMREQ_POS) + +/****************** Bit definition for CAN_TXFCON1 register ************************/ + +#define CAN_TXFCON1_STAMP_POSS 16U +#define CAN_TXFCON1_STAMP_POSE 31U +#define CAN_TXFCON1_STAMP_MSK BITS(CAN_TXFCON1_STAMP_POSS,CAN_TXFCON1_STAMP_POSE) + +#define CAN_TXFCON1_TXGT_POS 8U +#define CAN_TXFCON1_TXGT_MSK BIT(CAN_TXFCON1_TXGT_POS) + +#define CAN_TXFCON1_DLEN_POSS 0U +#define CAN_TXFCON1_DLEN_POSE 3U +#define CAN_TXFCON1_DLEN_MSK BITS(CAN_TXFCON1_DLEN_POSS,CAN_TXFCON1_DLEN_POSE) + +/****************** Bit definition for CAN_TXDL1 register ************************/ + +#define CAN_TXDL1_BYTE3_POSS 24U +#define CAN_TXDL1_BYTE3_POSE 31U +#define CAN_TXDL1_BYTE3_MSK BITS(CAN_TXDL1_BYTE3_POSS,CAN_TXDL1_BYTE3_POSE) + +#define CAN_TXDL1_BYTE2_POSS 16U +#define CAN_TXDL1_BYTE2_POSE 23U +#define CAN_TXDL1_BYTE2_MSK BITS(CAN_TXDL1_BYTE2_POSS,CAN_TXDL1_BYTE2_POSE) + +#define CAN_TXDL1_BYTE1_POSS 8U +#define CAN_TXDL1_BYTE1_POSE 15U +#define CAN_TXDL1_BYTE1_MSK BITS(CAN_TXDL1_BYTE1_POSS,CAN_TXDL1_BYTE1_POSE) + +#define CAN_TXDL1_BYTE0_POSS 0U +#define CAN_TXDL1_BYTE0_POSE 7U +#define CAN_TXDL1_BYTE0_MSK BITS(CAN_TXDL1_BYTE0_POSS,CAN_TXDL1_BYTE0_POSE) + +/****************** Bit definition for CAN_TXDH1 register ************************/ + +#define CAN_TXDH1_BYTE7_POSS 24U +#define CAN_TXDH1_BYTE7_POSE 31U +#define CAN_TXDH1_BYTE7_MSK BITS(CAN_TXDH1_BYTE7_POSS,CAN_TXDH1_BYTE7_POSE) + +#define CAN_TXDH1_BYTE6_POSS 16U +#define CAN_TXDH1_BYTE6_POSE 23U +#define CAN_TXDH1_BYTE6_MSK BITS(CAN_TXDH1_BYTE6_POSS,CAN_TXDH1_BYTE6_POSE) + +#define CAN_TXDH1_BYTE5_POSS 8U +#define CAN_TXDH1_BYTE5_POSE 15U +#define CAN_TXDH1_BYTE5_MSK BITS(CAN_TXDH1_BYTE5_POSS,CAN_TXDH1_BYTE5_POSE) + +#define CAN_TXDH1_BYTE4_POSS 0U +#define CAN_TXDH1_BYTE4_POSE 7U +#define CAN_TXDH1_BYTE4_MSK BITS(CAN_TXDH1_BYTE4_POSS,CAN_TXDH1_BYTE4_POSE) + +/****************** Bit definition for CAN_TXID2 register ************************/ + +#define CAN_TXID2_STDID_POSS 21U +#define CAN_TXID2_STDID_POSE 31U +#define CAN_TXID2_STDID_MSK BITS(CAN_TXID2_STDID_POSS,CAN_TXID2_STDID_POSE) + +#define CAN_TXID2_EXID_POSS 3U +#define CAN_TXID2_EXID_POSE 20U +#define CAN_TXID2_EXID_MSK BITS(CAN_TXID2_EXID_POSS,CAN_TXID2_EXID_POSE) + +#define CAN_TXID2_IDE_POS 2U +#define CAN_TXID2_IDE_MSK BIT(CAN_TXID2_IDE_POS) + +#define CAN_TXID2_RTR_POS 1U +#define CAN_TXID2_RTR_MSK BIT(CAN_TXID2_RTR_POS) + +#define CAN_TXID2_TXMREQ_POS 0U +#define CAN_TXID2_TXMREQ_MSK BIT(CAN_TXID2_TXMREQ_POS) + +/****************** Bit definition for CAN_TXFCON2 register ************************/ + +#define CAN_TXFCON2_STAMP_POSS 16U +#define CAN_TXFCON2_STAMP_POSE 31U +#define CAN_TXFCON2_STAMP_MSK BITS(CAN_TXFCON2_STAMP_POSS,CAN_TXFCON2_STAMP_POSE) + +#define CAN_TXFCON2_TXGT_POS 8U +#define CAN_TXFCON2_TXGT_MSK BIT(CAN_TXFCON2_TXGT_POS) + +#define CAN_TXFCON2_DLEN_POSS 0U +#define CAN_TXFCON2_DLEN_POSE 3U +#define CAN_TXFCON2_DLEN_MSK BITS(CAN_TXFCON2_DLEN_POSS,CAN_TXFCON2_DLEN_POSE) + +/****************** Bit definition for CAN_TXDL2 register ************************/ + +#define CAN_TXDL2_BYTE3_POSS 24U +#define CAN_TXDL2_BYTE3_POSE 31U +#define CAN_TXDL2_BYTE3_MSK BITS(CAN_TXDL2_BYTE3_POSS,CAN_TXDL2_BYTE3_POSE) + +#define CAN_TXDL2_BYTE2_POSS 16U +#define CAN_TXDL2_BYTE2_POSE 23U +#define CAN_TXDL2_BYTE2_MSK BITS(CAN_TXDL2_BYTE2_POSS,CAN_TXDL2_BYTE2_POSE) + +#define CAN_TXDL2_BYTE1_POSS 8U +#define CAN_TXDL2_BYTE1_POSE 15U +#define CAN_TXDL2_BYTE1_MSK BITS(CAN_TXDL2_BYTE1_POSS,CAN_TXDL2_BYTE1_POSE) + +#define CAN_TXDL2_BYTE0_POSS 0U +#define CAN_TXDL2_BYTE0_POSE 7U +#define CAN_TXDL2_BYTE0_MSK BITS(CAN_TXDL2_BYTE0_POSS,CAN_TXDL2_BYTE0_POSE) + +/****************** Bit definition for CAN_TXDH2 register ************************/ + +#define CAN_TXDH2_BYTE7_POSS 24U +#define CAN_TXDH2_BYTE7_POSE 31U +#define CAN_TXDH2_BYTE7_MSK BITS(CAN_TXDH2_BYTE7_POSS,CAN_TXDH2_BYTE7_POSE) + +#define CAN_TXDH2_BYTE6_POSS 16U +#define CAN_TXDH2_BYTE6_POSE 23U +#define CAN_TXDH2_BYTE6_MSK BITS(CAN_TXDH2_BYTE6_POSS,CAN_TXDH2_BYTE6_POSE) + +#define CAN_TXDH2_BYTE5_POSS 8U +#define CAN_TXDH2_BYTE5_POSE 15U +#define CAN_TXDH2_BYTE5_MSK BITS(CAN_TXDH2_BYTE5_POSS,CAN_TXDH2_BYTE5_POSE) + +#define CAN_TXDH2_BYTE4_POSS 0U +#define CAN_TXDH2_BYTE4_POSE 7U +#define CAN_TXDH2_BYTE4_MSK BITS(CAN_TXDH2_BYTE4_POSS,CAN_TXDH2_BYTE4_POSE) + +/****************** Bit definition for CAN_RXF0ID register ************************/ + +#define CAN_RXF0ID_STDID_POSS 21U +#define CAN_RXF0ID_STDID_POSE 31U +#define CAN_RXF0ID_STDID_MSK BITS(CAN_RXF0ID_STDID_POSS,CAN_RXF0ID_STDID_POSE) + +#define CAN_RXF0ID_EXID_POSS 3U +#define CAN_RXF0ID_EXID_POSE 20U +#define CAN_RXF0ID_EXID_MSK BITS(CAN_RXF0ID_EXID_POSS,CAN_RXF0ID_EXID_POSE) + +#define CAN_RXF0ID_IDE_POS 2U +#define CAN_RXF0ID_IDE_MSK BIT(CAN_RXF0ID_IDE_POS) + +#define CAN_RXF0ID_RTR_POS 1U +#define CAN_RXF0ID_RTR_MSK BIT(CAN_RXF0ID_RTR_POS) + +/****************** Bit definition for CAN_RXF0INF register ************************/ + +#define CAN_RXF0INF_STAMP_POSS 16U +#define CAN_RXF0INF_STAMP_POSE 31U +#define CAN_RXF0INF_STAMP_MSK BITS(CAN_RXF0INF_STAMP_POSS,CAN_RXF0INF_STAMP_POSE) + +#define CAN_RXF0INF_FLTIDX_POSS 8U +#define CAN_RXF0INF_FLTIDX_POSE 15U +#define CAN_RXF0INF_FLTIDX_MSK BITS(CAN_RXF0INF_FLTIDX_POSS,CAN_RXF0INF_FLTIDX_POSE) + +#define CAN_RXF0INF_DLEN_POSS 0U +#define CAN_RXF0INF_DLEN_POSE 3U +#define CAN_RXF0INF_DLEN_MSK BITS(CAN_RXF0INF_DLEN_POSS,CAN_RXF0INF_DLEN_POSE) + +/****************** Bit definition for CAN_RXF0DL register ************************/ + +#define CAN_RXF0DL_BYTE3_POSS 24U +#define CAN_RXF0DL_BYTE3_POSE 31U +#define CAN_RXF0DL_BYTE3_MSK BITS(CAN_RXF0DL_BYTE3_POSS,CAN_RXF0DL_BYTE3_POSE) + +#define CAN_RXF0DL_BYTE2_POSS 16U +#define CAN_RXF0DL_BYTE2_POSE 23U +#define CAN_RXF0DL_BYTE2_MSK BITS(CAN_RXF0DL_BYTE2_POSS,CAN_RXF0DL_BYTE2_POSE) + +#define CAN_RXF0DL_BYTE1_POSS 8U +#define CAN_RXF0DL_BYTE1_POSE 15U +#define CAN_RXF0DL_BYTE1_MSK BITS(CAN_RXF0DL_BYTE1_POSS,CAN_RXF0DL_BYTE1_POSE) + +#define CAN_RXF0DL_BYTE0_POSS 0U +#define CAN_RXF0DL_BYTE0_POSE 7U +#define CAN_RXF0DL_BYTE0_MSK BITS(CAN_RXF0DL_BYTE0_POSS,CAN_RXF0DL_BYTE0_POSE) + +/****************** Bit definition for CAN_RXF0DH register ************************/ + +#define CAN_RXF0DH_BYTE7_POSS 24U +#define CAN_RXF0DH_BYTE7_POSE 31U +#define CAN_RXF0DH_BYTE7_MSK BITS(CAN_RXF0DH_BYTE7_POSS,CAN_RXF0DH_BYTE7_POSE) + +#define CAN_RXF0DH_BYTE6_POSS 16U +#define CAN_RXF0DH_BYTE6_POSE 23U +#define CAN_RXF0DH_BYTE6_MSK BITS(CAN_RXF0DH_BYTE6_POSS,CAN_RXF0DH_BYTE6_POSE) + +#define CAN_RXF0DH_BYTE5_POSS 8U +#define CAN_RXF0DH_BYTE5_POSE 15U +#define CAN_RXF0DH_BYTE5_MSK BITS(CAN_RXF0DH_BYTE5_POSS,CAN_RXF0DH_BYTE5_POSE) + +#define CAN_RXF0DH_BYTE4_POSS 0U +#define CAN_RXF0DH_BYTE4_POSE 7U +#define CAN_RXF0DH_BYTE4_MSK BITS(CAN_RXF0DH_BYTE4_POSS,CAN_RXF0DH_BYTE4_POSE) + +/****************** Bit definition for CAN_RXF1ID register ************************/ + +#define CAN_RXF1ID_STDID_POSS 21U +#define CAN_RXF1ID_STDID_POSE 31U +#define CAN_RXF1ID_STDID_MSK BITS(CAN_RXF1ID_STDID_POSS,CAN_RXF1ID_STDID_POSE) + +#define CAN_RXF1ID_EXID_POSS 3U +#define CAN_RXF1ID_EXID_POSE 20U +#define CAN_RXF1ID_EXID_MSK BITS(CAN_RXF1ID_EXID_POSS,CAN_RXF1ID_EXID_POSE) + +#define CAN_RXF1ID_IDE_POS 2U +#define CAN_RXF1ID_IDE_MSK BIT(CAN_RXF1ID_IDE_POS) + +#define CAN_RXF1ID_RTR_POS 1U +#define CAN_RXF1ID_RTR_MSK BIT(CAN_RXF1ID_RTR_POS) + +/****************** Bit definition for CAN_RXF1INF register ************************/ + +#define CAN_RXF1INF_STAMP_POSS 16U +#define CAN_RXF1INF_STAMP_POSE 31U +#define CAN_RXF1INF_STAMP_MSK BITS(CAN_RXF1INF_STAMP_POSS,CAN_RXF1INF_STAMP_POSE) + +#define CAN_RXF1INF_FLTIDX_POSS 8U +#define CAN_RXF1INF_FLTIDX_POSE 15U +#define CAN_RXF1INF_FLTIDX_MSK BITS(CAN_RXF1INF_FLTIDX_POSS,CAN_RXF1INF_FLTIDX_POSE) + +#define CAN_RXF1INF_DLEN_POSS 0U +#define CAN_RXF1INF_DLEN_POSE 3U +#define CAN_RXF1INF_DLEN_MSK BITS(CAN_RXF1INF_DLEN_POSS,CAN_RXF1INF_DLEN_POSE) + +/****************** Bit definition for CAN_RXF1DL register ************************/ + +#define CAN_RXF1DL_BYTE3_POSS 24U +#define CAN_RXF1DL_BYTE3_POSE 31U +#define CAN_RXF1DL_BYTE3_MSK BITS(CAN_RXF1DL_BYTE3_POSS,CAN_RXF1DL_BYTE3_POSE) + +#define CAN_RXF1DL_BYTE2_POSS 16U +#define CAN_RXF1DL_BYTE2_POSE 23U +#define CAN_RXF1DL_BYTE2_MSK BITS(CAN_RXF1DL_BYTE2_POSS,CAN_RXF1DL_BYTE2_POSE) + +#define CAN_RXF1DL_BYTE1_POSS 8U +#define CAN_RXF1DL_BYTE1_POSE 15U +#define CAN_RXF1DL_BYTE1_MSK BITS(CAN_RXF1DL_BYTE1_POSS,CAN_RXF1DL_BYTE1_POSE) + +#define CAN_RXF1DL_BYTE0_POSS 0U +#define CAN_RXF1DL_BYTE0_POSE 7U +#define CAN_RXF1DL_BYTE0_MSK BITS(CAN_RXF1DL_BYTE0_POSS,CAN_RXF1DL_BYTE0_POSE) + +/****************** Bit definition for CAN_RXF1DH register ************************/ + +#define CAN_RXF1DH_BYTE7_POSS 24U +#define CAN_RXF1DH_BYTE7_POSE 31U +#define CAN_RXF1DH_BYTE7_MSK BITS(CAN_RXF1DH_BYTE7_POSS,CAN_RXF1DH_BYTE7_POSE) + +#define CAN_RXF1DH_BYTE6_POSS 16U +#define CAN_RXF1DH_BYTE6_POSE 23U +#define CAN_RXF1DH_BYTE6_MSK BITS(CAN_RXF1DH_BYTE6_POSS,CAN_RXF1DH_BYTE6_POSE) + +#define CAN_RXF1DH_BYTE5_POSS 8U +#define CAN_RXF1DH_BYTE5_POSE 15U +#define CAN_RXF1DH_BYTE5_MSK BITS(CAN_RXF1DH_BYTE5_POSS,CAN_RXF1DH_BYTE5_POSE) + +#define CAN_RXF1DH_BYTE4_POSS 0U +#define CAN_RXF1DH_BYTE4_POSE 7U +#define CAN_RXF1DH_BYTE4_MSK BITS(CAN_RXF1DH_BYTE4_POSS,CAN_RXF1DH_BYTE4_POSE) + +/****************** Bit definition for CAN_FLTCON register ************************/ + +#define CAN_FLTCON_FLTINI_POS 0U +#define CAN_FLTCON_FLTINI_MSK BIT(CAN_FLTCON_FLTINI_POS) + +/****************** Bit definition for CAN_FLTM register ************************/ + +#define CAN_FLTM_MOD_POSS 0U +#define CAN_FLTM_MOD_POSE 13U +#define CAN_FLTM_MOD_MSK BITS(CAN_FLTM_MOD_POSS,CAN_FLTM_MOD_POSE) + +/****************** Bit definition for CAN_FLTWS register ************************/ + +#define CAN_FLTWS_SEL_POSS 0U +#define CAN_FLTWS_SEL_POSE 13U +#define CAN_FLTWS_SEL_MSK BITS(CAN_FLTWS_SEL_POSS,CAN_FLTWS_SEL_POSE) + +/****************** Bit definition for CAN_FLTAS register ************************/ + +#define CAN_FLTAS_ASSIGN_POSS 0U +#define CAN_FLTAS_ASSIGN_POSE 13U +#define CAN_FLTAS_ASSIGN_MSK BITS(CAN_FLTAS_ASSIGN_POSS,CAN_FLTAS_ASSIGN_POSE) + +/****************** Bit definition for CAN_FLTGO register ************************/ + +#define CAN_FLTGO_GO_POSS 0U +#define CAN_FLTGO_GO_POSE 13U +#define CAN_FLTGO_GO_MSK BITS(CAN_FLTGO_GO_POSS,CAN_FLTGO_GO_POSE) + +typedef struct { + __IO uint32_t TXID; + __IO uint32_t TXFCON; + __IO uint32_t TXDL; + __IO uint32_t TXDH; +} CAN_TxMailBox_Typedef; + +typedef struct { + __IO uint32_t RXFID; + __IO uint32_t RXFINF; + __IO uint32_t RXFDL; + __IO uint32_t RXFDH; +} CAN_RxFIFO_Typedef; + +typedef struct { + __IO uint32_t FLT1; + __IO uint32_t FLT2; +} CAN_Filter_Typedef; + +typedef struct +{ + __IO uint32_t CON; + __I uint32_t STAT; + __O uint32_t IFC; + __IO uint32_t TXSTAT; + __O uint32_t TXSTATC; + __IO uint32_t RXF0; + __O uint32_t RXF0C; + __IO uint32_t RXF1; + __O uint32_t RXF1C; + __IO uint32_t IE; + __IO uint32_t ERRSTAT; + __IO uint32_t BTIME; + uint32_t RESERVED0[84] ; + CAN_TxMailBox_Typedef TxMailBox[3]; + CAN_RxFIFO_Typedef RxFIFO[2]; + uint32_t RESERVED1[12] ; + __IO uint32_t FLTCON; + __IO uint32_t FLTM; + uint32_t RESERVED2 ; + __IO uint32_t FLTWS; + uint32_t RESERVED3 ; + __IO uint32_t FLTAS; + uint32_t RESERVED4 ; + __IO uint32_t FLTGO; + uint32_t RESERVED5[8] ; + CAN_Filter_Typedef Filter[14]; +} CAN_TypeDef; + +/****************** Bit definition for CRC_CR register ************************/ +#define CRC_CR_BYTORD_POS 24U +#define CRC_CR_BYTORD_MSK BIT(CRC_CR_BYTORD_POS) + +#define CRC_CR_DATLEN_POSS 22U +#define CRC_CR_DATLEN_POSE 23U +#define CRC_CR_DATLEN_MSK BITS(CRC_CR_DATLEN_POSS,CRC_CR_DATLEN_POSE) + +#define CRC_CR_MODE_POSS 20U +#define CRC_CR_MODE_POSE 21U +#define CRC_CR_MODE_MSK BITS(CRC_CR_MODE_POSS,CRC_CR_MODE_POSE) + +#define CRC_CR_CHSINV_POS 19U +#define CRC_CR_CHSINV_MSK BIT(CRC_CR_CHSINV_POS) + +#define CRC_CR_DATINV_POS 18U +#define CRC_CR_DATINV_MSK BIT(CRC_CR_DATINV_POS) + +#define CRC_CR_CHSREV_POS 17U +#define CRC_CR_CHSREV_MSK BIT(CRC_CR_CHSREV_POS) + +#define CRC_CR_DATREV_POS 16U +#define CRC_CR_DATREV_MSK BIT(CRC_CR_DATREV_POS) + +#define CRC_CR_DMAEN_POS 4U +#define CRC_CR_DMAEN_MSK BIT(CRC_CR_DMAEN_POS) + +#define CRC_CR_CWERR_POS 3U +#define CRC_CR_CWERR_MSK BIT(CRC_CR_CWERR_POS) + +#define CRC_CR_WERR_POS 2U +#define CRC_CR_WERR_MSK BIT(CRC_CR_WERR_POS) + +#define CRC_CR_RST_POS 1U +#define CRC_CR_RST_MSK BIT(CRC_CR_RST_POS) + +#define CRC_CR_EN_POS 0U +#define CRC_CR_EN_MSK BIT(CRC_CR_EN_POS) + +/****************** Bit definition for CRC_DATA register ************************/ + +#define CRC_DATA_DATA_POSS 0U +#define CRC_DATA_DATA_POSE 31U +#define CRC_DATA_DATA_MSK BITS(CRC_DATA_DATA_POSS,CRC_DATA_DATA_POSE) + +/****************** Bit definition for CRC_SEED register ************************/ + +#define CRC_SEED_SEED_POSS 0U +#define CRC_SEED_SEED_POSE 31U +#define CRC_SEED_SEED_MSK BITS(CRC_SEED_SEED_POSS,CRC_SEED_SEED_POSE) + +/****************** Bit definition for CRC_CHECKSUM register ************************/ + +#define CRC_CHECKSUM_CHECKSUM_POSS 0U +#define CRC_CHECKSUM_CHECKSUM_POSE 31U +#define CRC_CHECKSUM_CHECKSUM_MSK BITS(CRC_CHECKSUM_CHECKSUM_POSS,CRC_CHECKSUM_CHECKSUM_POSE) + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t DATA; + __IO uint32_t SEED; + __I uint32_t CHECKSUM; +} CRC_TypeDef; + +/****************** Bit definition for CRYPT_CON register ************************/ + +#define CRYPT_CON_CRYSEL_POS 31U +#define CRYPT_CON_CRYSEL_MSK BIT(CRYPT_CON_CRYSEL_POS) + +#define CRYPT_CON_RESCLR_POS 15U +#define CRYPT_CON_RESCLR_MSK BIT(CRYPT_CON_RESCLR_POS) + +#define CRYPT_CON_DMAEN_POS 14U +#define CRYPT_CON_DMAEN_MSK BIT(CRYPT_CON_DMAEN_POS) + +#define CRYPT_CON_FIFOODR_POS 13U +#define CRYPT_CON_FIFOODR_MSK BIT(CRYPT_CON_FIFOODR_POS) + +#define CRYPT_CON_FIFOEN_POS 12U +#define CRYPT_CON_FIFOEN_MSK BIT(CRYPT_CON_FIFOEN_POS) + +#define CRYPT_CON_DESKS_POS 11U +#define CRYPT_CON_DESKS_MSK BIT(CRYPT_CON_DESKS_POS) + +#define CRYPT_CON_TDES_POS 10U +#define CRYPT_CON_TDES_MSK BIT(CRYPT_CON_TDES_POS) + +#define CRYPT_CON_TYPE_POSS 8U +#define CRYPT_CON_TYPE_POSE 9U +#define CRYPT_CON_TYPE_MSK BITS(CRYPT_CON_TYPE_POSS,CRYPT_CON_TYPE_POSE) + +#define CRYPT_CON_IE_POS 7U +#define CRYPT_CON_IE_MSK BIT(CRYPT_CON_IE_POS) + +#define CRYPT_CON_IVEN_POS 6U +#define CRYPT_CON_IVEN_MSK BIT(CRYPT_CON_IVEN_POS) + +#define CRYPT_CON_MODE_POSS 4U +#define CRYPT_CON_MODE_POSE 5U +#define CRYPT_CON_MODE_MSK BITS(CRYPT_CON_MODE_POSS,CRYPT_CON_MODE_POSE) + +#define CRYPT_CON_AESKS_POSS 2U +#define CRYPT_CON_AESKS_POSE 3U +#define CRYPT_CON_AESKS_MSK BITS(CRYPT_CON_AESKS_POSS,CRYPT_CON_AESKS_POSE) + +#define CRYPT_CON_ENCS_POS 1U +#define CRYPT_CON_ENCS_MSK BIT(CRYPT_CON_ENCS_POS) + +#define CRYPT_CON_GO_POS 0U +#define CRYPT_CON_GO_MSK BIT(CRYPT_CON_GO_POS) + +/****************** Bit definition for CRYPT_IF register ************************/ + +#define CRYPT_IF_DONE_POS 8U +#define CRYPT_IF_DONE_MSK BIT(CRYPT_IF_DONE_POS) + +#define CRYPT_IF_MULTHIF_POS 2U +#define CRYPT_IF_MULTHIF_MSK BIT(CRYPT_IF_MULTHIF_POS) + +#define CRYPT_IF_DESIF_POS 1U +#define CRYPT_IF_DESIF_MSK BIT(CRYPT_IF_DESIF_POS) + +#define CRYPT_IF_AESIF_POS 0U +#define CRYPT_IF_AESIF_MSK BIT(CRYPT_IF_AESIF_POS) + +/****************** Bit definition for CRYPT_IFC register ************************/ + +#define CRYPT_IFC_MULTHIFC_POS 2U +#define CRYPT_IFC_MULTHIFC_MSK BIT(CRYPT_IFC_MULTHIFC_POS) + +#define CRYPT_IFC_DESIFC_POS 1U +#define CRYPT_IFC_DESIFC_MSK BIT(CRYPT_IFC_DESIFC_POS) + +#define CRYPT_IFC_AESIFC_POS 0U +#define CRYPT_IFC_AESIFC_MSK BIT(CRYPT_IFC_AESIFC_POS) + +/****************** Bit definition for CRYPT_FIFO register ************************/ + +#define CRYPT_FIFO_FIFO_POSS 0U +#define CRYPT_FIFO_FIFO_POSE 31U +#define CRYPT_FIFO_FIFO_MSK BITS(CRYPT_FIFO_FIFO_POSS,CRYPT_FIFO_FIFO_POSE) + +typedef struct +{ + __IO uint32_t DATA[4]; + __IO uint32_t KEY[8]; + __IO uint32_t IV[4]; + __I uint32_t RES[4]; + __IO uint32_t CON; + __I uint32_t IF; + __O uint32_t IFC; + __IO uint32_t FIFO; +} CRYPT_TypeDef; + +/****************** Bit definition for ADC_STAT register ************************/ + +#define ADC_STAT_ICHS_POS 9U +#define ADC_STAT_ICHS_MSK BIT(ADC_STAT_ICHS_POS) + +#define ADC_STAT_NCHS_POS 8U +#define ADC_STAT_NCHS_MSK BIT(ADC_STAT_NCHS_POS) + +#define ADC_STAT_OVR_POS 3U +#define ADC_STAT_OVR_MSK BIT(ADC_STAT_OVR_POS) + +#define ADC_STAT_ICHE_POS 2U +#define ADC_STAT_ICHE_MSK BIT(ADC_STAT_ICHE_POS) + +#define ADC_STAT_NCHE_POS 1U +#define ADC_STAT_NCHE_MSK BIT(ADC_STAT_NCHE_POS) + +#define ADC_STAT_AWDF_POS 0U +#define ADC_STAT_AWDF_MSK BIT(ADC_STAT_AWDF_POS) + +/****************** Bit definition for ADC_CLR register ************************/ + +#define ADC_CLR_ICHS_POS 9U +#define ADC_CLR_ICHS_MSK BIT(ADC_CLR_ICHS_POS) + +#define ADC_CLR_NCHS_POS 8U +#define ADC_CLR_NCHS_MSK BIT(ADC_CLR_NCHS_POS) + +#define ADC_CLR_OVR_POS 3U +#define ADC_CLR_OVR_MSK BIT(ADC_CLR_OVR_POS) + +#define ADC_CLR_ICHE_POS 2U +#define ADC_CLR_ICHE_MSK BIT(ADC_CLR_ICHE_POS) + +#define ADC_CLR_NCHE_POS 1U +#define ADC_CLR_NCHE_MSK BIT(ADC_CLR_NCHE_POS) + +#define ADC_CLR_AWDF_POS 0U +#define ADC_CLR_AWDF_MSK BIT(ADC_CLR_AWDF_POS) + +/****************** Bit definition for ADC_CON0 register ************************/ + +#define ADC_CON0_OVRIE_POS 26U +#define ADC_CON0_OVRIE_MSK BIT(ADC_CON0_OVRIE_POS) + +#define ADC_CON0_RSEL_POSS 24U +#define ADC_CON0_RSEL_POSE 25U +#define ADC_CON0_RSEL_MSK BITS(ADC_CON0_RSEL_POSS,ADC_CON0_RSEL_POSE) + +#define ADC_CON0_NCHWDEN_POS 23U +#define ADC_CON0_NCHWDEN_MSK BIT(ADC_CON0_NCHWDEN_POS) + +#define ADC_CON0_ICHWDTEN_POS 22U +#define ADC_CON0_ICHWDTEN_MSK BIT(ADC_CON0_ICHWDTEN_POS) + +#define ADC_CON0_ETRGN_POSS 13U +#define ADC_CON0_ETRGN_POSE 15U +#define ADC_CON0_ETRGN_MSK BITS(ADC_CON0_ETRGN_POSS,ADC_CON0_ETRGN_POSE) + +#define ADC_CON0_ICHDCEN_POS 12U +#define ADC_CON0_ICHDCEN_MSK BIT(ADC_CON0_ICHDCEN_POS) + +#define ADC_CON0_NCHDCEN_POS 11U +#define ADC_CON0_NCHDCEN_MSK BIT(ADC_CON0_NCHDCEN_POS) + +#define ADC_CON0_IAUTO_POS 10U +#define ADC_CON0_IAUTO_MSK BIT(ADC_CON0_IAUTO_POS) + +#define ADC_CON0_AWDSGL_POS 9U +#define ADC_CON0_AWDSGL_MSK BIT(ADC_CON0_AWDSGL_POS) + +#define ADC_CON0_SCANEN_POS 8U +#define ADC_CON0_SCANEN_MSK BIT(ADC_CON0_SCANEN_POS) + +#define ADC_CON0_ICHEIE_POS 7U +#define ADC_CON0_ICHEIE_MSK BIT(ADC_CON0_ICHEIE_POS) + +#define ADC_CON0_AWDIE_POS 6U +#define ADC_CON0_AWDIE_MSK BIT(ADC_CON0_AWDIE_POS) + +#define ADC_CON0_NCHEIE_POS 5U +#define ADC_CON0_NCHEIE_MSK BIT(ADC_CON0_NCHEIE_POS) + +#define ADC_CON0_AWDCH_POSS 0U +#define ADC_CON0_AWDCH_POSE 4U +#define ADC_CON0_AWDCH_MSK BITS(ADC_CON0_AWDCH_POSS,ADC_CON0_AWDCH_POSE) + +/****************** Bit definition for ADC_CON1 register ************************/ + +#define ADC_CON1_NCHTRG_POS 30U +#define ADC_CON1_NCHTRG_MSK BIT(ADC_CON1_NCHTRG_POS) + +#define ADC_CON1_NETS_POSS 28U +#define ADC_CON1_NETS_POSE 29U +#define ADC_CON1_NETS_MSK BITS(ADC_CON1_NETS_POSS,ADC_CON1_NETS_POSE) + +#define ADC_CON1_ICHTRG_POS 22U +#define ADC_CON1_ICHTRG_MSK BIT(ADC_CON1_ICHTRG_POS) + +#define ADC_CON1_IETS_POSS 20U +#define ADC_CON1_IETS_POSE 21U +#define ADC_CON1_IETS_MSK BITS(ADC_CON1_IETS_POSS,ADC_CON1_IETS_POSE) + +#define ADC_CON1_ALIGN_POS 11U +#define ADC_CON1_ALIGN_MSK BIT(ADC_CON1_ALIGN_POS) + +#define ADC_CON1_NCHESEL_POS 10U +#define ADC_CON1_NCHESEL_MSK BIT(ADC_CON1_NCHESEL_POS) + +#define ADC_CON1_DMA_POS 8U +#define ADC_CON1_DMA_MSK BIT(ADC_CON1_DMA_POS) + +#define ADC_CON1_CM_POS 1U +#define ADC_CON1_CM_MSK BIT(ADC_CON1_CM_POS) + +#define ADC_CON1_ADCEN_POS 0U +#define ADC_CON1_ADCEN_MSK BIT(ADC_CON1_ADCEN_POS) + +/****************** Bit definition for ADC_SMPT1 register ************************/ + +#define ADC_SMPT1_CHT_POSS 0U +#define ADC_SMPT1_CHT_POSE 31U +#define ADC_SMPT1_CHT_MSK BITS(ADC_SMPT1_CHT_POSS,ADC_SMPT1_CHT_POSE) + +/****************** Bit definition for ADC_SMPT2 register ************************/ + +#define ADC_SMPT2_CHT_POSS 0U +#define ADC_SMPT2_CHT_POSE 31U +#define ADC_SMPT2_CHT_MSK BITS(ADC_SMPT2_CHT_POSS,ADC_SMPT2_CHT_POSE) + +/****************** Bit definition for ADC_SMPT3 register ************************/ + +#define ADC_SMPT3_SMP_POSS 0U +#define ADC_SMPT3_SMP_POSE 31U +#define ADC_SMPT3_SMP_MSK BITS(ADC_SMPT3_SMP_POSS,ADC_SMPT3_SMP_POSE) + +/****************** Bit definition for ADC_ICHOFF1 register ************************/ + +#define ADC_ICHOFF1_IOFF_POSS 0U +#define ADC_ICHOFF1_IOFF_POSE 11U +#define ADC_ICHOFF1_IOFF_MSK BITS(ADC_ICHOFF1_IOFF_POSS,ADC_ICHOFF1_IOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF2 register ************************/ + +#define ADC_ICHOFF2_IOFF_POSS 0U +#define ADC_ICHOFF2_IOFF_POSE 11U +#define ADC_ICHOFF2_IOFF_MSK BITS(ADC_ICHOFF2_IOFF_POSS,ADC_ICHOFF2_IOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF3 register ************************/ + +#define ADC_ICHOFF3_IOFF_POSS 0U +#define ADC_ICHOFF3_IOFF_POSE 11U +#define ADC_ICHOFF3_IOFF_MSK BITS(ADC_ICHOFF3_IOFF_POSS,ADC_ICHOFF3_IOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF4 register ************************/ + +#define ADC_ICHOFF4_IOFF_POSS 0U +#define ADC_ICHOFF4_IOFF_POSE 11U +#define ADC_ICHOFF4_IOFF_MSK BITS(ADC_ICHOFF4_IOFF_POSS,ADC_ICHOFF4_IOFF_POSE) + +/****************** Bit definition for ADC_NCHS1 register ************************/ + +#define ADC_NCHS1_NS4_POSS 24U +#define ADC_NCHS1_NS4_POSE 28U +#define ADC_NCHS1_NS4_MSK BITS(ADC_NCHS1_NS4_POSS,ADC_NCHS1_NS4_POSE) + +#define ADC_NCHS1_NS3_POSS 16U +#define ADC_NCHS1_NS3_POSE 20U +#define ADC_NCHS1_NS3_MSK BITS(ADC_NCHS1_NS3_POSS,ADC_NCHS1_NS3_POSE) + +#define ADC_NCHS1_NS2_POSS 8U +#define ADC_NCHS1_NS2_POSE 12U +#define ADC_NCHS1_NS2_MSK BITS(ADC_NCHS1_NS2_POSS,ADC_NCHS1_NS2_POSE) + +#define ADC_NCHS1_NS1_POSS 0U +#define ADC_NCHS1_NS1_POSE 4U +#define ADC_NCHS1_NS1_MSK BITS(ADC_NCHS1_NS1_POSS,ADC_NCHS1_NS1_POSE) + +/****************** Bit definition for ADC_NCHS2 register ************************/ + +#define ADC_NCHS2_NS8_POSS 24U +#define ADC_NCHS2_NS8_POSE 28U +#define ADC_NCHS2_NS8_MSK BITS(ADC_NCHS2_NS8_POSS,ADC_NCHS2_NS8_POSE) + +#define ADC_NCHS2_NS7_POSS 16U +#define ADC_NCHS2_NS7_POSE 20U +#define ADC_NCHS2_NS7_MSK BITS(ADC_NCHS2_NS7_POSS,ADC_NCHS2_NS7_POSE) + +#define ADC_NCHS2_NS6_POSS 8U +#define ADC_NCHS2_NS6_POSE 12U +#define ADC_NCHS2_NS6_MSK BITS(ADC_NCHS2_NS6_POSS,ADC_NCHS2_NS6_POSE) + +#define ADC_NCHS2_NS5_POSS 0U +#define ADC_NCHS2_NS5_POSE 4U +#define ADC_NCHS2_NS5_MSK BITS(ADC_NCHS2_NS5_POSS,ADC_NCHS2_NS5_POSE) + +/****************** Bit definition for ADC_NCHS3 register ************************/ + +#define ADC_NCHS3_NS12_POSS 24U +#define ADC_NCHS3_NS12_POSE 28U +#define ADC_NCHS3_NS12_MSK BITS(ADC_NCHS3_NS12_POSS,ADC_NCHS3_NS12_POSE) + +#define ADC_NCHS3_NS11_POSS 16U +#define ADC_NCHS3_NS11_POSE 20U +#define ADC_NCHS3_NS11_MSK BITS(ADC_NCHS3_NS11_POSS,ADC_NCHS3_NS11_POSE) + +#define ADC_NCHS3_NS10_POSS 8U +#define ADC_NCHS3_NS10_POSE 12U +#define ADC_NCHS3_NS10_MSK BITS(ADC_NCHS3_NS10_POSS,ADC_NCHS3_NS10_POSE) + +#define ADC_NCHS3_NS9_POSS 0U +#define ADC_NCHS3_NS9_POSE 4U +#define ADC_NCHS3_NS9_MSK BITS(ADC_NCHS3_NS9_POSS,ADC_NCHS3_NS9_POSE) + +/****************** Bit definition for ADC_NCHS4 register ************************/ + +#define ADC_NCHS4_NS16_POSS 24U +#define ADC_NCHS4_NS16_POSE 28U +#define ADC_NCHS4_NS16_MSK BITS(ADC_NCHS4_NS16_POSS,ADC_NCHS4_NS16_POSE) + +#define ADC_NCHS4_NS15_POSS 16U +#define ADC_NCHS4_NS15_POSE 20U +#define ADC_NCHS4_NS15_MSK BITS(ADC_NCHS4_NS15_POSS,ADC_NCHS4_NS15_POSE) + +#define ADC_NCHS4_NS14_POSS 8U +#define ADC_NCHS4_NS14_POSE 12U +#define ADC_NCHS4_NS14_MSK BITS(ADC_NCHS4_NS14_POSS,ADC_NCHS4_NS14_POSE) + +#define ADC_NCHS4_NS13_POSS 0U +#define ADC_NCHS4_NS13_POSE 4U +#define ADC_NCHS4_NS13_MSK BITS(ADC_NCHS4_NS13_POSS,ADC_NCHS4_NS13_POSE) + +/****************** Bit definition for ADC_ICHS register ************************/ + +#define ADC_ICHS_IS4_POSS 24U +#define ADC_ICHS_IS4_POSE 28U +#define ADC_ICHS_IS4_MSK BITS(ADC_ICHS_IS4_POSS,ADC_ICHS_IS4_POSE) + +#define ADC_ICHS_IS3_POSS 16U +#define ADC_ICHS_IS3_POSE 20U +#define ADC_ICHS_IS3_MSK BITS(ADC_ICHS_IS3_POSS,ADC_ICHS_IS3_POSE) + +#define ADC_ICHS_IS2_POSS 8U +#define ADC_ICHS_IS2_POSE 12U +#define ADC_ICHS_IS2_MSK BITS(ADC_ICHS_IS2_POSS,ADC_ICHS_IS2_POSE) + +#define ADC_ICHS_IS1_POSS 0U +#define ADC_ICHS_IS1_POSE 4U +#define ADC_ICHS_IS1_MSK BITS(ADC_ICHS_IS1_POSS,ADC_ICHS_IS1_POSE) + +/****************** Bit definition for ADC_CHSL register ************************/ + +#define ADC_CHSL_ISL_POSS 8U +#define ADC_CHSL_ISL_POSE 9U +#define ADC_CHSL_ISL_MSK BITS(ADC_CHSL_ISL_POSS,ADC_CHSL_ISL_POSE) + +#define ADC_CHSL_NSL_POSS 0U +#define ADC_CHSL_NSL_POSE 3U +#define ADC_CHSL_NSL_MSK BITS(ADC_CHSL_NSL_POSS,ADC_CHSL_NSL_POSE) + +/****************** Bit definition for ADC_WDTH register ************************/ + +#define ADC_WDTH_HT_POSS 0U +#define ADC_WDTH_HT_POSE 11U +#define ADC_WDTH_HT_MSK BITS(ADC_WDTH_HT_POSS,ADC_WDTH_HT_POSE) + +/****************** Bit definition for ADC_WDTL register ************************/ + +#define ADC_WDTL_LT_POSS 0U +#define ADC_WDTL_LT_POSE 11U +#define ADC_WDTL_LT_MSK BITS(ADC_WDTL_LT_POSS,ADC_WDTL_LT_POSE) + +/****************** Bit definition for ADC_ICHDR1 register ************************/ + +#define ADC_ICHDR1_VAL_POSS 0U +#define ADC_ICHDR1_VAL_POSE 15U +#define ADC_ICHDR1_VAL_MSK BITS(ADC_ICHDR1_VAL_POSS,ADC_ICHDR1_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR2 register ************************/ + +#define ADC_ICHDR2_VAL_POSS 0U +#define ADC_ICHDR2_VAL_POSE 15U +#define ADC_ICHDR2_VAL_MSK BITS(ADC_ICHDR2_VAL_POSS,ADC_ICHDR2_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR3 register ************************/ + +#define ADC_ICHDR3_VAL_POSS 0U +#define ADC_ICHDR3_VAL_POSE 15U +#define ADC_ICHDR3_VAL_MSK BITS(ADC_ICHDR3_VAL_POSS,ADC_ICHDR3_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR4 register ************************/ + +#define ADC_ICHDR4_VAL_POSS 0U +#define ADC_ICHDR4_VAL_POSE 15U +#define ADC_ICHDR4_VAL_MSK BITS(ADC_ICHDR4_VAL_POSS,ADC_ICHDR4_VAL_POSE) + +/****************** Bit definition for ADC_NCHDR register ************************/ + +#define ADC_NCHDR_VAL_POSS 0U +#define ADC_NCHDR_VAL_POSE 15U +#define ADC_NCHDR_VAL_MSK BITS(ADC_NCHDR_VAL_POSS,ADC_NCHDR_VAL_POSE) + +/****************** Bit definition for ADC_CCR register ************************/ + +#define ADC_CCR_ADCH_PBUF_EN_POS 31U +#define ADC_CCR_ADCH_PBUF_EN_MSK BIT(ADC_CCR_ADCH_PBUF_EN_POS) + +#define ADC_CCR_ADCH_NBUF_EN_POS 30U +#define ADC_CCR_ADCH_NBUF_EN_MSK BIT(ADC_CCR_ADCH_NBUF_EN_POS) + +#define ADC_CCR_ADCH_INBUF_CALEN_POS 29U +#define ADC_CCR_ADCH_INBUF_CALEN_MSK BIT(ADC_CCR_ADCH_INBUF_CALEN_POS) + +#define ADC_CCR_TRMEN_POS 28U +#define ADC_CCR_TRMEN_MSK BIT(ADC_CCR_TRMEN_POS) + +#define ADC_CCR_GAINCALEN_POS 25U +#define ADC_CCR_GAINCALEN_MSK BIT(ADC_CCR_GAINCALEN_POS) + +#define ADC_CCR_OFFCALEN_POS 24U +#define ADC_CCR_OFFCALEN_MSK BIT(ADC_CCR_OFFCALEN_POS) + +#define ADC_CCR_VREFOEN_POS 19U +#define ADC_CCR_VREFOEN_MSK BIT(ADC_CCR_VREFOEN_POS) + +#define ADC_CCR_VRNSEL_POS 18U +#define ADC_CCR_VRNSEL_MSK BIT(ADC_CCR_VRNSEL_POS) + +#define ADC_CCR_VRPSEL_POSS 16U +#define ADC_CCR_VRPSEL_POSE 17U +#define ADC_CCR_VRPSEL_MSK BITS(ADC_CCR_VRPSEL_POSS,ADC_CCR_VRPSEL_POSE) + +#define ADC_CCR_PWRMODSEL_POS 15U +#define ADC_CCR_PWRMODSEL_MSK BIT(ADC_CCR_PWRMODSEL_POS) + +#define ADC_CCR_DIFFEN_POS 12U +#define ADC_CCR_DIFFEN_MSK BIT(ADC_CCR_DIFFEN_POS) + +#define ADC_CCR_IREFEN_POS 11U +#define ADC_CCR_IREFEN_MSK BIT(ADC_CCR_IREFEN_POS) + +#define ADC_CCR_VRBUFEN_POS 10U +#define ADC_CCR_VRBUFEN_MSK BIT(ADC_CCR_VRBUFEN_POS) + +#define ADC_CCR_VCMBUFEN_POS 9U +#define ADC_CCR_VCMBUFEN_MSK BIT(ADC_CCR_VCMBUFEN_POS) + +#define ADC_CCR_VREFEN_POS 8U +#define ADC_CCR_VREFEN_MSK BIT(ADC_CCR_VREFEN_POS) + +#define ADC_CCR_CKDIV_POSS 0U +#define ADC_CCR_CKDIV_POSE 2U +#define ADC_CCR_CKDIV_MSK BITS(ADC_CCR_CKDIV_POSS,ADC_CCR_CKDIV_POSE) + +typedef struct +{ + __I uint32_t STAT; + __O uint32_t CLR; + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t SMPT1; + __IO uint32_t SMPT2; + __IO uint32_t SMPT3; + __IO uint32_t RESERVED; + __IO uint32_t ICHOFF1; + __IO uint32_t ICHOFF2; + __IO uint32_t ICHOFF3; + __IO uint32_t ICHOFF4; + __IO uint32_t NCHS1; + __IO uint32_t NCHS2; + __IO uint32_t NCHS3; + __IO uint32_t NCHS4; + __IO uint32_t ICHS; + __IO uint32_t CHSL; + __IO uint32_t WDTH; + __IO uint32_t WDTL; + __I uint32_t ICHDR1; + __I uint32_t ICHDR2; + __I uint32_t ICHDR3; + __I uint32_t ICHDR4; + __I uint32_t NCHDR; + __IO uint32_t CCR; +} ADC_TypeDef; + +/****************** Bit definition for ACMP_CON register ************************/ + +#define ACMP_CON_FALLEN_POS 17U +#define ACMP_CON_FALLEN_MSK BIT(ACMP_CON_FALLEN_POS) + +#define ACMP_CON_RISEEN_POS 16U +#define ACMP_CON_RISEEN_MSK BIT(ACMP_CON_RISEEN_POS) + +#define ACMP_CON_MODSEL_POSS 14U +#define ACMP_CON_MODSEL_POSE 15U +#define ACMP_CON_MODSEL_MSK BITS(ACMP_CON_MODSEL_POSS,ACMP_CON_MODSEL_POSE) + +#define ACMP_CON_WARMUPT_POSS 8U +#define ACMP_CON_WARMUPT_POSE 10U +#define ACMP_CON_WARMUPT_MSK BITS(ACMP_CON_WARMUPT_POSS,ACMP_CON_WARMUPT_POSE) + +#define ACMP_CON_HYSTSEL_POSS 4U +#define ACMP_CON_HYSTSEL_POSE 6U +#define ACMP_CON_HYSTSEL_MSK BITS(ACMP_CON_HYSTSEL_POSS,ACMP_CON_HYSTSEL_POSE) + +#define ACMP_CON_OUTINV_POS 3U +#define ACMP_CON_OUTINV_MSK BIT(ACMP_CON_OUTINV_POS) + +#define ACMP_CON_INACTV_POS 2U +#define ACMP_CON_INACTV_MSK BIT(ACMP_CON_INACTV_POS) + +#define ACMP_CON_EN_POS 0U +#define ACMP_CON_EN_MSK BIT(ACMP_CON_EN_POS) + +/****************** Bit definition for ACMP_INPUTSEL register ************************/ + +#define ACMP_INPUTSEL_VDDLVL_POSS 8U +#define ACMP_INPUTSEL_VDDLVL_POSE 13U +#define ACMP_INPUTSEL_VDDLVL_MSK BITS(ACMP_INPUTSEL_VDDLVL_POSS,ACMP_INPUTSEL_VDDLVL_POSE) + +#define ACMP_INPUTSEL_NSEL_POSS 4U +#define ACMP_INPUTSEL_NSEL_POSE 7U +#define ACMP_INPUTSEL_NSEL_MSK BITS(ACMP_INPUTSEL_NSEL_POSS,ACMP_INPUTSEL_NSEL_POSE) + +#define ACMP_INPUTSEL_PSEL_POSS 0U +#define ACMP_INPUTSEL_PSEL_POSE 2U +#define ACMP_INPUTSEL_PSEL_MSK BITS(ACMP_INPUTSEL_PSEL_POSS,ACMP_INPUTSEL_PSEL_POSE) + +/****************** Bit definition for ACMP_STAT register ************************/ + +#define ACMP_STAT_OUT_POS 1U +#define ACMP_STAT_OUT_MSK BIT(ACMP_STAT_OUT_POS) + +#define ACMP_STAT_ACT_POS 0U +#define ACMP_STAT_ACT_MSK BIT(ACMP_STAT_ACT_POS) + +/****************** Bit definition for ACMP_IES register ************************/ + +#define ACMP_IES_WARMUP_POS 1U +#define ACMP_IES_WARMUP_MSK BIT(ACMP_IES_WARMUP_POS) + +#define ACMP_IES_EDGE_POS 0U +#define ACMP_IES_EDGE_MSK BIT(ACMP_IES_EDGE_POS) + +/****************** Bit definition for ACMP_IEV register ************************/ + +#define ACMP_IEV_WARMUP_POS 1U +#define ACMP_IEV_WARMUP_MSK BIT(ACMP_IEV_WARMUP_POS) + +#define ACMP_IEV_EDGE_POS 0U +#define ACMP_IEV_EDGE_MSK BIT(ACMP_IEV_EDGE_POS) + +/****************** Bit definition for ACMP_IEC register ************************/ + +#define ACMP_IEC_WARMUP_POS 1U +#define ACMP_IEC_WARMUP_MSK BIT(ACMP_IEC_WARMUP_POS) + +#define ACMP_IEC_EDGE_POS 0U +#define ACMP_IEC_EDGE_MSK BIT(ACMP_IEC_EDGE_POS) + +/****************** Bit definition for ACMP_RIF register ************************/ + +#define ACMP_RIF_WARMUP_POS 1U +#define ACMP_RIF_WARMUP_MSK BIT(ACMP_RIF_WARMUP_POS) + +#define ACMP_RIF_EDGE_POS 0U +#define ACMP_RIF_EDGE_MSK BIT(ACMP_RIF_EDGE_POS) + +/****************** Bit definition for ACMP_IFM register ************************/ + +#define ACMP_IFM_WARMUP_POS 1U +#define ACMP_IFM_WARMUP_MSK BIT(ACMP_IFM_WARMUP_POS) + +#define ACMP_IFM_EDGE_POS 0U +#define ACMP_IFM_EDGE_MSK BIT(ACMP_IFM_EDGE_POS) + +/****************** Bit definition for ACMP_IFC register ************************/ + +#define ACMP_IFC_WARMUP_POS 1U +#define ACMP_IFC_WARMUP_MSK BIT(ACMP_IFC_WARMUP_POS) + +#define ACMP_IFC_EDGE_POS 0U +#define ACMP_IFC_EDGE_MSK BIT(ACMP_IFC_EDGE_POS) + +/****************** Bit definition for ACMP_PORT register ************************/ + +#define ACMP_PORT_PEN_POS 0U +#define ACMP_PORT_PEN_MSK BIT(ACMP_PORT_PEN_POS) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t INPUTSEL; + __I uint32_t STAT; + __O uint32_t IES; + __O uint32_t IEC; + __I uint32_t IEV; + __I uint32_t RIF; + __O uint32_t IFM; + __O uint32_t IFC; + __IO uint32_t PORT; +} ACMP_TypeDef; + +/****************** Bit definition for CALC_SQRTSR register ************************/ + +#define CALC_SQRTSR_BUSY_POS 0U +#define CALC_SQRTSR_BUSY_MSK BIT(CALC_SQRTSR_BUSY_POS) + +/****************** Bit definition for CALC_RDCND register ************************/ + +#define CALC_RDCND_RADICAND_POSS 0U +#define CALC_RDCND_RADICAND_POSE 31U +#define CALC_RDCND_RADICAND_MSK BITS(CALC_RDCND_RADICAND_POSS,CALC_RDCND_RADICAND_POSE) + +/****************** Bit definition for CALC_SQRTRES register ************************/ + +#define CALC_SQRTRES_RESULT_POSS 0U +#define CALC_SQRTRES_RESULT_POSE 15U +#define CALC_SQRTRES_RESULT_MSK BITS(CALC_SQRTRES_RESULT_POSS,CALC_SQRTRES_RESULT_POSE) + +/****************** Bit definition for CALC_DIVDR register ************************/ + +#define CALC_DIVDR_DIVD_POSS 0U +#define CALC_DIVDR_DIVD_POSE 31U +#define CALC_DIVDR_DIVD_MSK BITS(CALC_DIVDR_DIVD_POSS,CALC_DIVDR_DIVD_POSE) + +/****************** Bit definition for CALC_DIVSR register ************************/ + +#define CALC_DIVSR_DIVS_POSS 0U +#define CALC_DIVSR_DIVS_POSE 31U +#define CALC_DIVSR_DIVS_MSK BITS(CALC_DIVSR_DIVS_POSS,CALC_DIVSR_DIVS_POSE) + +/****************** Bit definition for CALC_DIVQR register ************************/ + +#define CALC_DIVQR_DIVQ_POSS 0U +#define CALC_DIVQR_DIVQ_POSE 31U +#define CALC_DIVQR_DIVQ_MSK BITS(CALC_DIVQR_DIVQ_POSS,CALC_DIVQR_DIVQ_POSE) + +/****************** Bit definition for CALC_DIVRR register ************************/ + +#define CALC_DIVRR_DIVS_POSS 0U +#define CALC_DIVRR_DIVS_POSE 31U +#define CALC_DIVRR_DIVS_MSK BITS(CALC_DIVRR_DIVS_POSS,CALC_DIVRR_DIVS_POSE) + +/****************** Bit definition for CALC_DIVCSR register ************************/ + +#define CALC_DIVCSR_TRM_POS 9U +#define CALC_DIVCSR_TRM_MSK BIT(CALC_DIVCSR_TRM_POS) + +#define CALC_DIVCSR_SIGN_POS 8U +#define CALC_DIVCSR_SIGN_MSK BIT(CALC_DIVCSR_SIGN_POS) + +#define CALC_DIVCSR_DZ_POS 1U +#define CALC_DIVCSR_DZ_MSK BIT(CALC_DIVCSR_DZ_POS) + +#define CALC_DIVCSR_BUSY_POS 0U +#define CALC_DIVCSR_BUSY_MSK BIT(CALC_DIVCSR_BUSY_POS) + +typedef struct +{ + __I uint32_t SQRTSR; + __IO uint32_t RDCND; + __I uint32_t SQRTRES; + uint32_t RESERVED0[5] ; + __IO uint32_t DIVDR; + __IO uint32_t DIVSR; + __I uint32_t DIVQR; + __I uint32_t DIVRR; + __IO uint32_t DIVCSR; +} CALC_TypeDef; + +/****************** Bit definition for TRNG_CR register ************************/ + +#define TRNG_CR_ADJC_POSS 16U +#define TRNG_CR_ADJC_POSE 17U +#define TRNG_CR_ADJC_MSK BITS(TRNG_CR_ADJC_POSS,TRNG_CR_ADJC_POSE) + +#define TRNG_CR_SDSEL_POSS 10U +#define TRNG_CR_SDSEL_POSE 11U +#define TRNG_CR_SDSEL_MSK BITS(TRNG_CR_SDSEL_POSS,TRNG_CR_SDSEL_POSE) + +#define TRNG_CR_DSEL_POSS 8U +#define TRNG_CR_DSEL_POSE 9U +#define TRNG_CR_DSEL_MSK BITS(TRNG_CR_DSEL_POSS,TRNG_CR_DSEL_POSE) + +#define TRNG_CR_POSTEN_POS 3U +#define TRNG_CR_POSTEN_MSK BIT(TRNG_CR_POSTEN_POS) + +#define TRNG_CR_TRNGSEL_POS 2U +#define TRNG_CR_TRNGSEL_MSK BIT(TRNG_CR_TRNGSEL_POS) + +#define TRNG_CR_ADJM_POS 1U +#define TRNG_CR_ADJM_MSK BIT(TRNG_CR_ADJM_POS) + +#define TRNG_CR_TRNGEN_POS 0U +#define TRNG_CR_TRNGEN_MSK BIT(TRNG_CR_TRNGEN_POS) + +/****************** Bit definition for TRNG_SR register ************************/ + +#define TRNG_SR_OVER_POS 3U +#define TRNG_SR_OVER_MSK BIT(TRNG_SR_OVER_POS) + +#define TRNG_SR_SERR_POS 2U +#define TRNG_SR_SERR_MSK BIT(TRNG_SR_SERR_POS) + +#define TRNG_SR_DAVLD_POS 1U +#define TRNG_SR_DAVLD_MSK BIT(TRNG_SR_DAVLD_POS) + +#define TRNG_SR_START_POS 0U +#define TRNG_SR_START_MSK BIT(TRNG_SR_START_POS) + +/****************** Bit definition for TRNG_DR register ************************/ + +#define TRNG_DR_DATA_POSS 0U +#define TRNG_DR_DATA_POSE 31U +#define TRNG_DR_DATA_MSK BITS(TRNG_DR_DATA_POSS,TRNG_DR_DATA_POSE) + +/****************** Bit definition for TRNG_SEED register ************************/ + +#define TRNG_SEED_SEED_POSS 0U +#define TRNG_SEED_SEED_POSE 31U +#define TRNG_SEED_SEED_MSK BITS(TRNG_SEED_SEED_POSS,TRNG_SEED_SEED_POSE) + +/****************** Bit definition for TRNG_CFGR register ************************/ + +#define TRNG_CFGR_TOPLMT_POSS 16U +#define TRNG_CFGR_TOPLMT_POSE 24U +#define TRNG_CFGR_TOPLMT_MSK BITS(TRNG_CFGR_TOPLMT_POSS,TRNG_CFGR_TOPLMT_POSE) + +#define TRNG_CFGR_CKDIV_POSS 8U +#define TRNG_CFGR_CKDIV_POSE 11U +#define TRNG_CFGR_CKDIV_MSK BITS(TRNG_CFGR_CKDIV_POSS,TRNG_CFGR_CKDIV_POSE) + +#define TRNG_CFGR_TSTART_POSS 0U +#define TRNG_CFGR_TSTART_POSE 2U +#define TRNG_CFGR_TSTART_MSK BITS(TRNG_CFGR_TSTART_POSS,TRNG_CFGR_TSTART_POSE) + +/****************** Bit definition for TRNG_IER register ************************/ + +#define TRNG_IER_SERR_POS 2U +#define TRNG_IER_SERR_MSK BIT(TRNG_IER_SERR_POS) + +#define TRNG_IER_DAVLD_POS 1U +#define TRNG_IER_DAVLD_MSK BIT(TRNG_IER_DAVLD_POS) + +#define TRNG_IER_START_POS 0U +#define TRNG_IER_START_MSK BIT(TRNG_IER_START_POS) + +/****************** Bit definition for TRNG_IFR register ************************/ + +#define TRNG_IFR_SERR_POS 2U +#define TRNG_IFR_SERR_MSK BIT(TRNG_IFR_SERR_POS) + +#define TRNG_IFR_DAVLD_POS 1U +#define TRNG_IFR_DAVLD_MSK BIT(TRNG_IFR_DAVLD_POS) + +#define TRNG_IFR_START_POS 0U +#define TRNG_IFR_START_MSK BIT(TRNG_IFR_START_POS) + +/****************** Bit definition for TRNG_IFCR register ************************/ + +#define TRNG_IFCR_SERRC_POS 2U +#define TRNG_IFCR_SERRC_MSK BIT(TRNG_IFCR_SERRC_POS) + +#define TRNG_IFCR_DAVLDC_POS 1U +#define TRNG_IFCR_DAVLDC_MSK BIT(TRNG_IFCR_DAVLDC_POS) + +#define TRNG_IFCR_STARTC_POS 0U +#define TRNG_IFCR_STARTC_MSK BIT(TRNG_IFCR_STARTC_POS) + +/****************** Bit definition for TRNG_ISR register ************************/ + +#define TRNG_ISR_SERR_POS 2U +#define TRNG_ISR_SERR_MSK BIT(TRNG_ISR_SERR_POS) + +#define TRNG_ISR_DAVLD_POS 1U +#define TRNG_ISR_DAVLD_MSK BIT(TRNG_ISR_DAVLD_POS) + +#define TRNG_ISR_START_POS 0U +#define TRNG_ISR_START_MSK BIT(TRNG_ISR_START_POS) + +typedef struct +{ + __IO uint32_t CR; + __I uint32_t SR; + __I uint32_t DR; + __IO uint32_t SEED; + __IO uint32_t CFGR; + __IO uint32_t IER; + __I uint32_t IFR; + __O uint32_t IFCR; + __I uint32_t ISR; +} TRNG_TypeDef; + +/****************** Bit definition for TSENSE_WPR register ************************/ + +#define TSENSE_WPR_WP_POS 0U +#define TSENSE_WPR_WP_MSK BIT(TSENSE_WPR_WP_POS) + +/****************** Bit definition for TSENSE_CR register ************************/ + +#define TSENSE_CR_TSU_POSS 12U +#define TSENSE_CR_TSU_POSE 14U +#define TSENSE_CR_TSU_MSK BITS(TSENSE_CR_TSU_POSS,TSENSE_CR_TSU_POSE) + +#define TSENSE_CR_TOM_POSS 8U +#define TSENSE_CR_TOM_POSE 10U +#define TSENSE_CR_TOM_MSK BITS(TSENSE_CR_TOM_POSS,TSENSE_CR_TOM_POSE) + +#define TSENSE_CR_CTN_POS 4U +#define TSENSE_CR_CTN_MSK BIT(TSENSE_CR_CTN_POS) + +#define TSENSE_CR_RST_POS 3U +#define TSENSE_CR_RST_MSK BIT(TSENSE_CR_RST_POS) + +#define TSENSE_CR_ENS_POS 2U +#define TSENSE_CR_ENS_MSK BIT(TSENSE_CR_ENS_POS) + +#define TSENSE_CR_REQEN_POS 1U +#define TSENSE_CR_REQEN_MSK BIT(TSENSE_CR_REQEN_POS) + +#define TSENSE_CR_EN_POS 0U +#define TSENSE_CR_EN_MSK BIT(TSENSE_CR_EN_POS) + +/****************** Bit definition for TSENSE_DR register ************************/ + +#define TSENSE_DR_ERR_POS 31U +#define TSENSE_DR_ERR_MSK BIT(TSENSE_DR_ERR_POS) + +#define TSENSE_DR_DATA_POSS 0U +#define TSENSE_DR_DATA_POSE 15U +#define TSENSE_DR_DATA_MSK BITS(TSENSE_DR_DATA_POSS,TSENSE_DR_DATA_POSE) + +/****************** Bit definition for TSENSE_PSR register ************************/ + +#define TSENSE_PSR_PRS_POSS 0U +#define TSENSE_PSR_PRS_POSE 7U +#define TSENSE_PSR_PRS_MSK BITS(TSENSE_PSR_PRS_POSS,TSENSE_PSR_PRS_POSE) + +/****************** Bit definition for TSENSE_IE register ************************/ + +#define TSENSE_IE_TSENSE_POS 0U +#define TSENSE_IE_TSENSE_MSK BIT(TSENSE_IE_TSENSE_POS) + +/****************** Bit definition for TSENSE_IF register ************************/ + +#define TSENSE_IF_TSENSE_POS 0U +#define TSENSE_IF_TSENSE_MSK BIT(TSENSE_IF_TSENSE_POS) + +/****************** Bit definition for TSENSE_IFCR register ************************/ + +#define TSENSE_IFCR_TSENSE_POS 0U +#define TSENSE_IFCR_TSENSE_MSK BIT(TSENSE_IFCR_TSENSE_POS) + +/****************** Bit definition for TSENSE_LTGR register ************************/ + +#define TSENSE_LTGR_LTG_POSS 0U +#define TSENSE_LTGR_LTG_POSE 20U +#define TSENSE_LTGR_LTG_MSK BITS(TSENSE_LTGR_LTG_POSS,TSENSE_LTGR_LTG_POSE) + +/****************** Bit definition for TSENSE_HTGR register ************************/ + +#define TSENSE_HTGR_HTG_POSS 0U +#define TSENSE_HTGR_HTG_POSE 20U +#define TSENSE_HTGR_HTG_MSK BITS(TSENSE_HTGR_HTG_POSS,TSENSE_HTGR_HTG_POSE) + +/****************** Bit definition for TSENSE_TBDR register ************************/ + +#define TSENSE_TBDR_TBD_POSS 0U +#define TSENSE_TBDR_TBD_POSE 15U +#define TSENSE_TBDR_TBD_MSK BITS(TSENSE_TBDR_TBD_POSS,TSENSE_TBDR_TBD_POSE) + +/****************** Bit definition for TSENSE_TCALBDR register ************************/ + +#define TSENSE_TCALBDR_TCAL_POSS 0U +#define TSENSE_TCALBDR_TCAL_POSE 16U +#define TSENSE_TCALBDR_TCAL_MSK BITS(TSENSE_TCALBDR_TCAL_POSS,TSENSE_TCALBDR_TCAL_POSE) + +/****************** Bit definition for TSENSE_SR register ************************/ + +#define TSENSE_SR_TSOUT_POS 31U +#define TSENSE_SR_TSOUT_MSK BIT(TSENSE_SR_TSOUT_POS) + +#define TSENSE_SR_NVLD_POS 25U +#define TSENSE_SR_NVLD_MSK BIT(TSENSE_SR_NVLD_POS) + +#define TSENSE_SR_TCAL_POSS 0U +#define TSENSE_SR_TCAL_POSE 24U +#define TSENSE_SR_TCAL_MSK BITS(TSENSE_SR_TCAL_POSS,TSENSE_SR_TCAL_POSE) + +typedef struct +{ + __IO uint32_t WPR; + __IO uint32_t CR; + __I uint32_t DR; + __IO uint32_t PSR; + __IO uint32_t IE; + __I uint32_t IF; + __IO uint32_t IFCR; + __IO uint32_t LTGR; + __IO uint32_t HTGR; + __IO uint32_t TBDR; + __IO uint32_t TCALBDR; + __I uint32_t SR; +} TSENSE_TypeDef; + +/****************** Bit definition for IWDT_LOAD register ************************/ + +#define IWDT_LOAD_LOAD_POSS 0U +#define IWDT_LOAD_LOAD_POSE 31U +#define IWDT_LOAD_LOAD_MSK BITS(IWDT_LOAD_LOAD_POSS,IWDT_LOAD_LOAD_POSE) + +/****************** Bit definition for IWDT_VALUE register ************************/ + +#define IWDT_VALUE_VALUE_POSS 0U +#define IWDT_VALUE_VALUE_POSE 31U +#define IWDT_VALUE_VALUE_MSK BITS(IWDT_VALUE_VALUE_POSS,IWDT_VALUE_VALUE_POSE) + +/****************** Bit definition for IWDT_CON register ************************/ + +#define IWDT_CON_CLKS_POS 3U +#define IWDT_CON_CLKS_MSK BIT(IWDT_CON_CLKS_POS) + +#define IWDT_CON_RSTEN_POS 2U +#define IWDT_CON_RSTEN_MSK BIT(IWDT_CON_RSTEN_POS) + +#define IWDT_CON_IE_POS 1U +#define IWDT_CON_IE_MSK BIT(IWDT_CON_IE_POS) + +#define IWDT_CON_EN_POS 0U +#define IWDT_CON_EN_MSK BIT(IWDT_CON_EN_POS) + +/****************** Bit definition for IWDT_INTCLR register ************************/ + +#define IWDT_INTCLR_INTCLR_POSS 0U +#define IWDT_INTCLR_INTCLR_POSE 31U +#define IWDT_INTCLR_INTCLR_MSK BITS(IWDT_INTCLR_INTCLR_POSS,IWDT_INTCLR_INTCLR_POSE) + +/****************** Bit definition for IWDT_RIS register ************************/ + +#define IWDT_RIS_WDTIF_POS 0U +#define IWDT_RIS_WDTIF_MSK BIT(IWDT_RIS_WDTIF_POS) + +/****************** Bit definition for IWDT_LOCK register ************************/ + +#define IWDT_LOCK_LOCK_POS 0U +#define IWDT_LOCK_LOCK_MSK BIT(IWDT_LOCK_LOCK_POS) + +typedef struct +{ + __O uint32_t LOAD; + __I uint32_t VALUE; + __IO uint32_t CON; + __O uint32_t INTCLR; + __I uint32_t RIS; + uint32_t RESERVED0[59] ; + __IO uint32_t LOCK; +} IWDT_TypeDef; + +/****************** Bit definition for WWDT_LOAD register ************************/ + +#define WWDT_LOAD_LOAD_POSS 0U +#define WWDT_LOAD_LOAD_POSE 31U +#define WWDT_LOAD_LOAD_MSK BITS(WWDT_LOAD_LOAD_POSS,WWDT_LOAD_LOAD_POSE) + +/****************** Bit definition for WWDT_VALUE register ************************/ + +#define WWDT_VALUE_VALUE_POSS 0U +#define WWDT_VALUE_VALUE_POSE 31U +#define WWDT_VALUE_VALUE_MSK BITS(WWDT_VALUE_VALUE_POSS,WWDT_VALUE_VALUE_POSE) + +/****************** Bit definition for WWDT_CON register ************************/ + +#define WWDT_CON_WWDTWIN_POSS 4U +#define WWDT_CON_WWDTWIN_POSE 5U +#define WWDT_CON_WWDTWIN_MSK BITS(WWDT_CON_WWDTWIN_POSS,WWDT_CON_WWDTWIN_POSE) + +#define WWDT_CON_CLKS_POS 3U +#define WWDT_CON_CLKS_MSK BIT(WWDT_CON_CLKS_POS) + +#define WWDT_CON_RSTEN_POS 2U +#define WWDT_CON_RSTEN_MSK BIT(WWDT_CON_RSTEN_POS) + +#define WWDT_CON_IE_POS 1U +#define WWDT_CON_IE_MSK BIT(WWDT_CON_IE_POS) + +#define WWDT_CON_EN_POS 0U +#define WWDT_CON_EN_MSK BIT(WWDT_CON_EN_POS) + +/****************** Bit definition for WWDT_INTCLR register ************************/ + +#define WWDT_INTCLR_INTCLR_POSS 0U +#define WWDT_INTCLR_INTCLR_POSE 31U +#define WWDT_INTCLR_INTCLR_MSK BITS(WWDT_INTCLR_INTCLR_POSS,WWDT_INTCLR_INTCLR_POSE) + +/****************** Bit definition for WWDT_RIS register ************************/ + +#define WWDT_RIS_WWDTIF_POS 0U +#define WWDT_RIS_WWDTIF_MSK BIT(WWDT_RIS_WWDTIF_POS) + +/****************** Bit definition for WWDT_LOCK register ************************/ + +#define WWDT_LOCK_LOCK_POS 0U +#define WWDT_LOCK_LOCK_MSK BIT(WWDT_LOCK_LOCK_POS) + +typedef struct +{ + __O uint32_t LOAD; + __I uint32_t VALUE; + __IO uint32_t CON; + __O uint32_t INTCLR; + __I uint32_t RIS; + uint32_t RESERVED0[59]; + __IO uint32_t LOCK; +} WWDT_TypeDef; + +/****************** Bit definition for QSPI_CR register ************************/ + +#define QSPI_CR_IDLES_POS 31U +#define QSPI_CR_IDLES_MSK BIT(QSPI_CR_IDLES_POS) +#define QSPI_CR_IDLES QSPI_CR_IDLES_MSK + + +#define QSPI_CR_DTRM_POS 24U +#define QSPI_CR_DTRM_MSK BIT(QSPI_CR_DTRM_POS) + +#define QSPI_CR_ADEN_POS 23U +#define QSPI_CR_ADEN_MSK BIT(QSPI_CR_ADEN_POS) + +#define QSPI_CR_BAUD_POSS 19U +#define QSPI_CR_BAUD_POSE 22U +#define QSPI_CR_BAUD_MSK BITS(QSPI_CR_BAUD_POSS,QSPI_CR_BAUD_POSE) + +#define QSPI_CR_XIPIM_POS 18U +#define QSPI_CR_XIPIM_MSK BIT(QSPI_CR_XIPIM_POS) + +#define QSPI_CR_XIPNX_POS 17U +#define QSPI_CR_XIPNX_MSK BIT(QSPI_CR_XIPNX_POS) + +#define QSPI_CR_AREN_POS 16U +#define QSPI_CR_AREN_MSK BIT(QSPI_CR_AREN_POS) + +#define QSPI_CR_DMAEN_POS 15U +#define QSPI_CR_DMAEN_MSK BIT(QSPI_CR_DMAEN_POS) + +#define QSPI_CR_SWPP_POS 14U +#define QSPI_CR_SWPP_MSK BIT(QSPI_CR_SWPP_POS) + +#define QSPI_CR_PSL_POSS 10U +#define QSPI_CR_PSL_POSE 13U +#define QSPI_CR_PSL_MSK BITS(QSPI_CR_PSL_POSS,QSPI_CR_PSL_POSE) + +#define QSPI_CR_PSD_POS 9U +#define QSPI_CR_PSD_MSK BIT(QSPI_CR_PSD_POS) + +#define QSPI_CR_LIMEN_POS 8U +#define QSPI_CR_LIMEN_MSK BIT(QSPI_CR_LIMEN_POS) + +#define QSPI_CR_DACEN_POS 7U +#define QSPI_CR_DACEN_MSK BIT(QSPI_CR_DACEN_POS) + +#define QSPI_CR_CPHA_POS 2U +#define QSPI_CR_CPHA_MSK BIT(QSPI_CR_CPHA_POS) +#define QSPI_CR_CPHA QSPI_CR_CPHA_MSK + +#define QSPI_CR_CPOL_POS 1U +#define QSPI_CR_CPOL_MSK BIT(QSPI_CR_CPOL_POS) +#define QSPI_CR_CPOL QSPI_CR_CPOL_MSK + +#define QSPI_CR_EN_POS 0U +#define QSPI_CR_EN_MSK BIT(QSPI_CR_EN_POS) + +/****************** Bit definition for QSPI_DRIR register ************************/ + +#define QSPI_DRIR_DCYC_POSS 24U +#define QSPI_DRIR_DCYC_POSE 28U +#define QSPI_DRIR_DCYC_MSK BITS(QSPI_DRIR_DCYC_POSS,QSPI_DRIR_DCYC_POSE) + +#define QSPI_DRIR_MBEN_POS 20U +#define QSPI_DRIR_MBEN_MSK BIT(QSPI_DRIR_MBEN_POS) + +#define QSPI_DRIR_DMODE_POSS 16U +#define QSPI_DRIR_DMODE_POSE 17U +#define QSPI_DRIR_DMODE_MSK BITS(QSPI_DRIR_DMODE_POSS,QSPI_DRIR_DMODE_POSE) + +#define QSPI_DRIR_ADMODE_POSS 12U +#define QSPI_DRIR_ADMODE_POSE 13U +#define QSPI_DRIR_ADMODE_MSK BITS(QSPI_DRIR_ADMODE_POSS,QSPI_DRIR_ADMODE_POSE) + +#define QSPI_DRIR_DDRM_POS 10U +#define QSPI_DRIR_DDRM_MSK BIT(QSPI_DRIR_DDRM_POS) + +#define QSPI_DRIR_IMODE_POSS 8U +#define QSPI_DRIR_IMODE_POSE 9U +#define QSPI_DRIR_IMODE_MSK BITS(QSPI_DRIR_IMODE_POSS,QSPI_DRIR_IMODE_POSE) + +#define QSPI_DRIR_RINST_POSS 0U +#define QSPI_DRIR_RINST_POSE 7U +#define QSPI_DRIR_RINST_MSK BITS(QSPI_DRIR_RINST_POSS,QSPI_DRIR_RINST_POSE) + +/****************** Bit definition for QSPI_DWIR register ************************/ + +#define QSPI_DWIR_DCYC_POSS 24U +#define QSPI_DWIR_DCYC_POSE 28U +#define QSPI_DWIR_DCYC_MSK BITS(QSPI_DWIR_DCYC_POSS,QSPI_DWIR_DCYC_POSE) + +#define QSPI_DWIR_DMODE_POSS 16U +#define QSPI_DWIR_DMODE_POSE 17U +#define QSPI_DWIR_DMODE_MSK BITS(QSPI_DWIR_DMODE_POSS,QSPI_DWIR_DMODE_POSE) + +#define QSPI_DWIR_ADMODE_POSS 12U +#define QSPI_DWIR_ADMODE_POSE 13U +#define QSPI_DWIR_ADMODE_MSK BITS(QSPI_DWIR_ADMODE_POSS,QSPI_DWIR_ADMODE_POSE) + +#define QSPI_DWIR_WELD_POS 8U +#define QSPI_DWIR_WELD_MSK BIT(QSPI_DWIR_WELD_POS) + +#define QSPI_DWIR_WINST_POSS 0U +#define QSPI_DWIR_WINST_POSE 7U +#define QSPI_DWIR_WINST_MSK BITS(QSPI_DWIR_WINST_POSS,QSPI_DWIR_WINST_POSE) + +/****************** Bit definition for QSPI_DDLR register ************************/ + +#define QSPI_DDLR_CSDA_POSS 24U +#define QSPI_DDLR_CSDA_POSE 31U +#define QSPI_DDLR_CSDA_MSK BITS(QSPI_DDLR_CSDA_POSS,QSPI_DDLR_CSDA_POSE) + +#define QSPI_DDLR_CSDADS_POSS 16U +#define QSPI_DDLR_CSDADS_POSE 23U +#define QSPI_DDLR_CSDADS_MSK BITS(QSPI_DDLR_CSDADS_POSS,QSPI_DDLR_CSDADS_POSE) + +#define QSPI_DDLR_CSEOT_POSS 8U +#define QSPI_DDLR_CSEOT_POSE 15U +#define QSPI_DDLR_CSEOT_MSK BITS(QSPI_DDLR_CSEOT_POSS,QSPI_DDLR_CSEOT_POSE) + +#define QSPI_DDLR_CSSOT_POSS 0U +#define QSPI_DDLR_CSSOT_POSE 7U +#define QSPI_DDLR_CSSOT_MSK BITS(QSPI_DDLR_CSSOT_POSS,QSPI_DDLR_CSSOT_POSE) + +/****************** Bit definition for QSPI_RDCR register ************************/ + +#define QSPI_RDCR_DLYT_POSS 16U +#define QSPI_RDCR_DLYT_POSE 19U +#define QSPI_RDCR_DLYT_MSK BITS(QSPI_RDCR_DLYT_POSS,QSPI_RDCR_DLYT_POSE) + +#define QSPI_RDCR_SMES_POS 5U +#define QSPI_RDCR_SMES_MSK BIT(QSPI_RDCR_SMES_POS) + +#define QSPI_RDCR_DLYR_POSS 1U +#define QSPI_RDCR_DLYR_POSE 4U +#define QSPI_RDCR_DLYR_MSK BITS(QSPI_RDCR_DLYR_POSS,QSPI_RDCR_DLYR_POSE) + +#define QSPI_RDCR_BYLPC_POS 0U +#define QSPI_RDCR_BYLPC_MSK BIT(QSPI_RDCR_BYLPC_POS) + +/****************** Bit definition for QSPI_DSCR register ************************/ + +#define QSPI_DSCR_CS3SIZE_POSS 27U +#define QSPI_DSCR_CS3SIZE_POSE 28U +#define QSPI_DSCR_CS3SIZE_MSK BITS(QSPI_DSCR_CS3SIZE_POSS,QSPI_DSCR_CS3SIZE_POSE) + +#define QSPI_DSCR_CS2SIZE_POSS 25U +#define QSPI_DSCR_CS2SIZE_POSE 26U +#define QSPI_DSCR_CS2SIZE_MSK BITS(QSPI_DSCR_CS2SIZE_POSS,QSPI_DSCR_CS2SIZE_POSE) + +#define QSPI_DSCR_CS1SIZE_POSS 23U +#define QSPI_DSCR_CS1SIZE_POSE 24U +#define QSPI_DSCR_CS1SIZE_MSK BITS(QSPI_DSCR_CS1SIZE_POSS,QSPI_DSCR_CS1SIZE_POSE) + +#define QSPI_DSCR_CS0SIZE_POSS 21U +#define QSPI_DSCR_CS0SIZE_POSE 22U +#define QSPI_DSCR_CS0SIZE_MSK BITS(QSPI_DSCR_CS0SIZE_POSS,QSPI_DSCR_CS0SIZE_POSE) + +#define QSPI_DSCR_BKSIZE_POSS 16U +#define QSPI_DSCR_BKSIZE_POSE 20U +#define QSPI_DSCR_BKSIZE_MSK BITS(QSPI_DSCR_BKSIZE_POSS,QSPI_DSCR_BKSIZE_POSE) + +#define QSPI_DSCR_PASIZE_POSS 4U +#define QSPI_DSCR_PASIZE_POSE 15U +#define QSPI_DSCR_PASIZE_MSK BITS(QSPI_DSCR_PASIZE_POSS,QSPI_DSCR_PASIZE_POSE) + +#define QSPI_DSCR_ADSIZE_POSS 0U +#define QSPI_DSCR_ADSIZE_POSE 3U +#define QSPI_DSCR_ADSIZE_MSK BITS(QSPI_DSCR_ADSIZE_POSS,QSPI_DSCR_ADSIZE_POSE) + +/****************** Bit definition for QSPI_SPR register ************************/ + +#define QSPI_SPR_SRAMPS_POSS 0U +#define QSPI_SPR_SRAMPS_POSE 7U +#define QSPI_SPR_SRAMPS_MSK BITS(QSPI_SPR_SRAMPS_POSS,QSPI_SPR_SRAMPS_POSE) + +/****************** Bit definition for QSPI_IATR register ************************/ + +#define QSPI_IATR_INDTAD_POSS 0U +#define QSPI_IATR_INDTAD_POSE 31U +#define QSPI_IATR_INDTAD_MSK BITS(QSPI_IATR_INDTAD_POSS,QSPI_IATR_INDTAD_POSE) + +/****************** Bit definition for QSPI_DMACR register ************************/ + +#define QSPI_DMACR_BNUMB_POSS 8U +#define QSPI_DMACR_BNUMB_POSE 11U +#define QSPI_DMACR_BNUMB_MSK BITS(QSPI_DMACR_BNUMB_POSS,QSPI_DMACR_BNUMB_POSE) + +#define QSPI_DMACR_SNUMB_POSS 0U +#define QSPI_DMACR_SNUMB_POSE 3U +#define QSPI_DMACR_SNUMB_MSK BITS(QSPI_DMACR_SNUMB_POSS,QSPI_DMACR_SNUMB_POSE) + +/****************** Bit definition for QSPI_RAR register ************************/ + +#define QSPI_RAR_READDR_POSS 0U +#define QSPI_RAR_READDR_POSE 31U +#define QSPI_RAR_READDR_MSK BITS(QSPI_RAR_READDR_POSS,QSPI_RAR_READDR_POSE) + +/****************** Bit definition for QSPI_MBR register ************************/ + +#define QSPI_MBR_MODEB_POSS 0U +#define QSPI_MBR_MODEB_POSE 7U +#define QSPI_MBR_MODEB_MSK BITS(QSPI_MBR_MODEB_POSS,QSPI_MBR_MODEB_POSE) + +/****************** Bit definition for QSPI_SFLR register ************************/ + +#define QSPI_SFLR_INDWSFL_POSS 16U +#define QSPI_SFLR_INDWSFL_POSE 21U +#define QSPI_SFLR_INDWSFL_MSK BITS(QSPI_SFLR_INDWSFL_POSS,QSPI_SFLR_INDWSFL_POSE) + +#define QSPI_SFLR_INDRSFL_POSS 0U +#define QSPI_SFLR_INDRSFL_POSE 5U +#define QSPI_SFLR_INDRSFL_MSK BITS(QSPI_SFLR_INDRSFL_POSS,QSPI_SFLR_INDRSFL_POSE) + +/****************** Bit definition for QSPI_TXHR register ************************/ + +#define QSPI_TXHR_TXTH_POSS 0U +#define QSPI_TXHR_TXTH_POSE 4U +#define QSPI_TXHR_TXTH_MSK BITS(QSPI_TXHR_TXTH_POSS,QSPI_TXHR_TXTH_POSE) + +/****************** Bit definition for QSPI_RXHR register ************************/ + +#define QSPI_RXHR_RXTH_POSS 0U +#define QSPI_RXHR_RXTH_POSE 4U +#define QSPI_RXHR_RXTH_MSK BITS(QSPI_RXHR_RXTH_POSS,QSPI_RXHR_RXTH_POSE) + +/****************** Bit definition for QSPI_WCR register ************************/ + +#define QSPI_WCR_PREPD_POSS 24U +#define QSPI_WCR_PREPD_POSE 31U +#define QSPI_WCR_PREPD_MSK BITS(QSPI_WCR_PREPD_POSS,QSPI_WCR_PREPD_POSE) + +#define QSPI_WCR_PCNT_POSS 16U +#define QSPI_WCR_PCNT_POSE 23U +#define QSPI_WCR_PCNT_MSK BITS(QSPI_WCR_PCNT_POSS,QSPI_WCR_PCNT_POSE) + +#define QSPI_WCR_PDIS_POS 14U +#define QSPI_WCR_PDIS_MSK BIT(QSPI_WCR_PDIS_POS) + +#define QSPI_WCR_PPLT_POS 13U +#define QSPI_WCR_PPLT_MSK BIT(QSPI_WCR_PPLT_POS) + +#define QSPI_WCR_PBIND_POSS 8U +#define QSPI_WCR_PBIND_POSE 10U +#define QSPI_WCR_PBIND_MSK BITS(QSPI_WCR_PBIND_POSS,QSPI_WCR_PBIND_POSE) + +#define QSPI_WCR_OPCODE_POSS 0U +#define QSPI_WCR_OPCODE_POSE 7U +#define QSPI_WCR_OPCODE_MSK BITS(QSPI_WCR_OPCODE_POSS,QSPI_WCR_OPCODE_POSE) + +/****************** Bit definition for QSPI_PER register ************************/ + +#define QSPI_PER_PCYCN_POSS 0U +#define QSPI_PER_PCYCN_POSE 31U +#define QSPI_PER_PCYCN_MSK BITS(QSPI_PER_PCYCN_POSS,QSPI_PER_PCYCN_POSE) + +/****************** Bit definition for QSPI_IFR register ************************/ + +#define QSPI_IFR_POLLF_POS 13U +#define QSPI_IFR_POLLF_MSK BIT(QSPI_IFR_POLLF_POS) +#define QSPI_IFR_POLLF QSPI_IFR_POLLF_MSK + +#define QSPI_IFR_INDRSFF_POS 12U +#define QSPI_IFR_INDRSFF_MSK BIT(QSPI_IFR_INDRSFF_POS) +#define QSPI_IFR_INDRSFF QSPI_IFR_INDRSFF_MSK + +#define QSPI_IFR_SRFFF_POS 11U +#define QSPI_IFR_SRFFF_MSK BIT(QSPI_IFR_SRFFF_POS) +#define QSPI_IFR_SRFFF QSPI_IFR_SRFFF_MSK + +#define QSPI_IFR_SRFNEF_POS 10U +#define QSPI_IFR_SRFNEF_MSK BIT(QSPI_IFR_SRFNEF_POS) +#define QSPI_IFR_SRFNEF QSPI_IFR_SRFNEF_MSK + +#define QSPI_IFR_STFFF_POS 9U +#define QSPI_IFR_STFFF_MSK BIT(QSPI_IFR_STFFF_POS) +#define QSPI_IFR_STFFF QSPI_IFR_STFFF_MSK + +#define QSPI_IFR_STFNFF_POS 8U +#define QSPI_IFR_STFNFF_MSK BIT(QSPI_IFR_STFNFF_POS) +#define QSPI_IFR_STFNFF QSPI_IFR_STFNFF_MSK + +#define QSPI_IFR_ROVF_POS 7U +#define QSPI_IFR_ROVF_MSK BIT(QSPI_IFR_ROVF_POS) +#define QSPI_IFR_ROVF QSPI_IFR_ROVF_MSK + +#define QSPI_IFR_INDTWF_POS 6U +#define QSPI_IFR_INDTWF_MSK BIT(QSPI_IFR_INDTWF_POS) +#define QSIP_IFR_INDTWF QSPI_IFR_INDTWF_MSK + +#define QSPI_IFR_AHBAEF_POS 5U +#define QSPI_IFR_AHBAEF_MSK BIT(QSPI_IFR_AHBAEF_POS) +#define QSPI_IFR_AHBAEF QSPI_IFR_AHBAEF_MSK + +#define QSPI_IFR_WPAF_POS 4U +#define QSPI_IFR_WPAF_MSK BIT(QSPI_IFR_WPAF_POS) +#define QSPI_IFR_WPAF QSPI_IFR_WPAF_MSK + +#define QSPI_IFR_INDRRF_POS 3U +#define QSPI_IFR_INDRRF_MSK BIT(QSPI_IFR_INDRRF_POS) +#define QSIP_IFR_INDRRF QSPI_IFR_INDRRF_MSK + +#define QSPI_IFR_INDCF_POS 2U +#define QSPI_IFR_INDCF_MSK BIT(QSPI_IFR_INDCF_POS) +#define QSPI_IFR_INDCF QSPI_IFR_INDCF_MSK + +#define QSPI_IFR_UDFF_POS 1U +#define QSPI_IFR_UDFF_MSK BIT(QSPI_IFR_UDFF_POS) +#define QSPI_IFR_UDFF QSPI_IFR_UDFF_MSK + +#define QSPI_IFR_MODFF_POS 0U +#define QSPI_IFR_MODFF_MSK BIT(QSPI_IFR_MODFF_POS) +#define QSPI_IFR_MODFF QSPI_IFR_MODFF_MSK + +/****************** Bit definition for QSPI_IMR register ************************/ + +#define QSPI_IMR_INTEN_POSS 0U +#define QSPI_IMR_INTEN_POSE 13U +#define QSPI_IMR_INTEN_MSK BITS(QSPI_IMR_INTEN_POSS,QSPI_IMR_INTEN_POSE) + +/****************** Bit definition for QSPI_WPLR register ************************/ + +#define QSPI_WPLR_LBLKNUM_POSS 0U +#define QSPI_WPLR_LBLKNUM_POSE 31U +#define QSPI_WPLR_LBLKNUM_MSK BITS(QSPI_WPLR_LBLKNUM_POSS,QSPI_WPLR_LBLKNUM_POSE) + +/****************** Bit definition for QSPI_WPHR register ************************/ + +#define QSPI_WPHR_HBLKNUM_POSS 0U +#define QSPI_WPHR_HBLKNUM_POSE 31U +#define QSPI_WPHR_HBLKNUM_MSK BITS(QSPI_WPHR_HBLKNUM_POSS,QSPI_WPHR_HBLKNUM_POSE) + +/****************** Bit definition for QSPI_WPCR register ************************/ + +#define QSPI_WPCR_WPEN_POS 1U +#define QSPI_WPCR_WPEN_MSK BIT(QSPI_WPCR_WPEN_POS) + +#define QSPI_WPCR_WPINV_POS 0U +#define QSPI_WPCR_WPINV_MSK BIT(QSPI_WPCR_WPINV_POS) + +/****************** Bit definition for QSPI_IRTR register ************************/ + +#define QSPI_IRTR_INDRNUM_POSS 6U +#define QSPI_IRTR_INDRNUM_POSE 7U +#define QSPI_IRTR_INDRNUM_MSK BITS(QSPI_IRTR_INDRNUM_POSS,QSPI_IRTR_INDRNUM_POSE) + +#define QSPI_IRTR_RDCS_POS 5U +#define QSPI_IRTR_RDCS_MSK BIT(QSPI_IRTR_RDCS_POS) + +#define QSPI_IRTR_RDQS_POS 4U +#define QSPI_IRTR_RDQS_MSK BIT(QSPI_IRTR_RDQS_POS) + +#define QSPI_IRTR_SRAMFS_POS 3U +#define QSPI_IRTR_SRAMFS_MSK BIT(QSPI_IRTR_SRAMFS_POS) + +#define QSPI_IRTR_RDPS_POS 2U +#define QSPI_IRTR_RDPS_MSK BIT(QSPI_IRTR_RDPS_POS) + +#define QSPI_IRTR_RDDIS_POS 1U +#define QSPI_IRTR_RDDIS_MSK BIT(QSPI_IRTR_RDDIS_POS) + +#define QSPI_IRTR_RDST_POS 0U +#define QSPI_IRTR_RDST_MSK BIT(QSPI_IRTR_RDST_POS) + +/****************** Bit definition for QSPI_IRTWR register ************************/ + +#define QSPI_IRTWR_VAULE_POSS 0U +#define QSPI_IRTWR_VAULE_POSE 31U +#define QSPI_IRTWR_VAULE_MSK BITS(QSPI_IRTWR_VAULE_POSS,QSPI_IRTWR_VAULE_POSE) + +/****************** Bit definition for QSPI_IRTSAR register ************************/ + +#define QSPI_IRTSAR_ADDR_POSS 0U +#define QSPI_IRTSAR_ADDR_POSE 31U +#define QSPI_IRTSAR_ADDR_MSK BITS(QSPI_IRTSAR_ADDR_POSS,QSPI_IRTSAR_ADDR_POSE) + +/****************** Bit definition for QSPI_IRTNR register ************************/ + +#define QSPI_IRTNR_NUM_POSS 0U +#define QSPI_IRTNR_NUM_POSE 31U +#define QSPI_IRTNR_NUM_MSK BITS(QSPI_IRTNR_NUM_POSS,QSPI_IRTNR_NUM_POSE) + +/****************** Bit definition for QSPI_IWTR register ************************/ + +#define QSPI_IWTR_INDWNUM_POSS 6U +#define QSPI_IWTR_INDWNUM_POSE 7U +#define QSPI_IWTR_INDWNUM_MSK BITS(QSPI_IWTR_INDWNUM_POSS,QSPI_IWTR_INDWNUM_POSE) + +#define QSPI_IWTR_WRCS_POS 5U +#define QSPI_IWTR_WRCS_MSK BIT(QSPI_IWTR_WRCS_POS) + +#define QSPI_IWTR_WRQS_POS 4U +#define QSPI_IWTR_WRQS_MSK BIT(QSPI_IWTR_WRQS_POS) + +#define QSPI_IWTR_WRPS_POS 2U +#define QSPI_IWTR_WRPS_MSK BIT(QSPI_IWTR_WRPS_POS) + +#define QSPI_IWTR_WRDIS_POS 1U +#define QSPI_IWTR_WRDIS_MSK BIT(QSPI_IWTR_WRDIS_POS) + +#define QSPI_IWTR_WRST_POS 0U +#define QSPI_IWTR_WRST_MSK BIT(QSPI_IWTR_WRST_POS) + +/****************** Bit definition for QSPI_IWTWR register ************************/ + +#define QSPI_IWTWR_VAULE_POSS 0U +#define QSPI_IWTWR_VAULE_POSE 31U +#define QSPI_IWTWR_VAULE_MSK BITS(QSPI_IWTWR_VAULE_POSS,QSPI_IWTWR_VAULE_POSE) + +/****************** Bit definition for QSPI_IWTSAR register ************************/ + +#define QSPI_IWTSAR_ADDR_POSS 0U +#define QSPI_IWTSAR_ADDR_POSE 31U +#define QSPI_IWTSAR_ADDR_MSK BITS(QSPI_IWTSAR_ADDR_POSS,QSPI_IWTSAR_ADDR_POSE) + +/****************** Bit definition for QSPI_IWTNR register ************************/ + +#define QSPI_IWTNR_NUM_POSS 0U +#define QSPI_IWTNR_NUM_POSE 31U +#define QSPI_IWTNR_NUM_MSK BITS(QSPI_IWTNR_NUM_POSS,QSPI_IWTNR_NUM_POSE) + +/****************** Bit definition for QSPI_ITARR register ************************/ + +#define QSPI_ITARR_RNGW_POSS 0U +#define QSPI_ITARR_RNGW_POSE 3U +#define QSPI_ITARR_RNGW_MSK BITS(QSPI_ITARR_RNGW_POSS,QSPI_ITARR_RNGW_POSE) + +/****************** Bit definition for QSPI_FCR register ************************/ + +#define QSPI_FCR_OPCODE_POSS 24U +#define QSPI_FCR_OPCODE_POSE 31U +#define QSPI_FCR_OPCODE_MSK BITS(QSPI_FCR_OPCODE_POSS,QSPI_FCR_OPCODE_POSE) + +#define QSPI_FCR_RDEN_POS 23U +#define QSPI_FCR_RDEN_MSK BIT(QSPI_FCR_RDEN_POS) + +#define QSPI_FCR_RDNUM_POSS 20U +#define QSPI_FCR_RDNUM_POSE 22U +#define QSPI_FCR_RDNUM_MSK BITS(QSPI_FCR_RDNUM_POSS,QSPI_FCR_RDNUM_POSE) + +#define QSPI_FCR_ADDREN_POS 19U +#define QSPI_FCR_ADDREN_MSK BIT(QSPI_FCR_ADDREN_POS) + +#define QSPI_FCR_MODBEN_POS 18U +#define QSPI_FCR_MODBEN_MSK BIT(QSPI_FCR_MODBEN_POS) + +#define QSPI_FCR_ADNUM_POSS 16U +#define QSPI_FCR_ADNUM_POSE 17U +#define QSPI_FCR_ADNUM_MSK BITS(QSPI_FCR_ADNUM_POSS,QSPI_FCR_ADNUM_POSE) + +#define QSPI_FCR_WREN_POS 15U +#define QSPI_FCR_WREN_MSK BIT(QSPI_FCR_WREN_POS) + +#define QSPI_FCR_WDNUM_POSS 12U +#define QSPI_FCR_WDNUM_POSE 14U +#define QSPI_FCR_WDNUM_MSK BITS(QSPI_FCR_WDNUM_POSS,QSPI_FCR_WDNUM_POSE) + +#define QSPI_FCR_DUMNUM_POSS 7U +#define QSPI_FCR_DUMNUM_POSE 11U +#define QSPI_FCR_DUMNUM_MSK BITS(QSPI_FCR_DUMNUM_POSS,QSPI_FCR_DUMNUM_POSE) + +#define QSPI_FCR_CMDS_POS 1U +#define QSPI_FCR_CMDS_MSK BIT(QSPI_FCR_CMDS_POS) + +#define QSPI_FCR_CMDT_POS 0U +#define QSPI_FCR_CMDT_MSK BIT(QSPI_FCR_CMDT_POS) + +/****************** Bit definition for QSPI_FCAR register ************************/ + +#define QSPI_FCAR_CMDADR_POSS 0U +#define QSPI_FCAR_CMDADR_POSE 31U +#define QSPI_FCAR_CMDADR_MSK BITS(QSPI_FCAR_CMDADR_POSS,QSPI_FCAR_CMDADR_POSE) + +/****************** Bit definition for QSPI_FCRLR register ************************/ + +#define QSPI_FCRLR_CMDDL_POSS 0U +#define QSPI_FCRLR_CMDDL_POSE 31U +#define QSPI_FCRLR_CMDDL_MSK BITS(QSPI_FCRLR_CMDDL_POSS,QSPI_FCRLR_CMDDL_POSE) + +/****************** Bit definition for QSPI_FCRHR register ************************/ + +#define QSPI_FCRHR_CMDDH_POSS 0U +#define QSPI_FCRHR_CMDDH_POSE 31U +#define QSPI_FCRHR_CMDDH_MSK BITS(QSPI_FCRHR_CMDDH_POSS,QSPI_FCRHR_CMDDH_POSE) + +/****************** Bit definition for QSPI_FCWLR register ************************/ + +#define QSPI_FCWLR_CMDDL_POSS 0U +#define QSPI_FCWLR_CMDDL_POSE 31U +#define QSPI_FCWLR_CMDDL_MSK BITS(QSPI_FCWLR_CMDDL_POSS,QSPI_FCWLR_CMDDL_POSE) + +/****************** Bit definition for QSPI_FCWHR register ************************/ + +#define QSPI_FCWHR_CMDDH_POSS 0U +#define QSPI_FCWHR_CMDDH_POSE 31U +#define QSPI_FCWHR_CMDDH_MSK BITS(QSPI_FCWHR_CMDDH_POSS,QSPI_FCWHR_CMDDH_POSE) + +/****************** Bit definition for QSPI_PFSR register ************************/ + +#define QSPI_PFSR_PSV_POS 8U +#define QSPI_PFSR_PSV_MSK BIT(QSPI_PFSR_PSV_POS) + +#define QSPI_PFSR_FLSS_POSS 0U +#define QSPI_PFSR_FLSS_POSE 7U +#define QSPI_PFSR_FLSS_MSK BITS(QSPI_PFSR_FLSS_POSS,QSPI_PFSR_FLSS_POSE) + +/****************** Bit definition for QSPI_MIDR register ************************/ + +#define QSPI_MIDR_ID1_POSS 24U +#define QSPI_MIDR_ID1_POSE 31U +#define QSPI_MIDR_ID1_MSK BITS(QSPI_MIDR_ID1_POSS,QSPI_MIDR_ID1_POSE) + +#define QSPI_MIDR_ID0_POSS 0U +#define QSPI_MIDR_ID0_POSE 23U +#define QSPI_MIDR_ID0_MSK BITS(QSPI_MIDR_ID0_POSS,QSPI_MIDR_ID0_POSE) + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t DRIR; + __IO uint32_t DWIR; + __IO uint32_t DDLR; + __IO uint32_t RDCR; + __IO uint32_t DSCR; + __IO uint32_t SPR; + __IO uint32_t IATR; + __IO uint32_t DMACR; + __IO uint32_t RAR; + __IO uint32_t MBR; + __I uint32_t SFLR; + __IO uint32_t TXHR; + __IO uint32_t RXHR; + __IO uint32_t WCR; + __IO uint32_t PER; + __IO uint32_t IFR; + __IO uint32_t IMR; + uint32_t RESERVED0[2] ; + __IO uint32_t WPLR; + __IO uint32_t WPHR; + __IO uint32_t WPCR; + uint32_t RESERVED1 ; + __O uint32_t IRTR; + __IO uint32_t IRTWR; + __IO uint32_t IRTSAR; + __IO uint32_t IRTNR; + __O uint32_t IWTR; + __IO uint32_t IWTWR; + __IO uint32_t IWTSAR; + __IO uint32_t IWTNR; + __IO uint32_t ITARR; + uint32_t RESERVED2[3] ; + __O uint32_t FCR; + __IO uint32_t FCAR; + uint32_t RESERVED3[2] ; + __I uint32_t FCRLR; + __I uint32_t FCRHR; + __IO uint32_t FCWLR; + __IO uint32_t FCWHR; + __I uint32_t PFSR; + uint32_t RESERVED4[18] ; + __I uint32_t MIDR; +} QSPI_TypeDef; + +/****************** Bit definition for EBI_BCTRLRx(x= 1..3) register ************************/ + +#define EBI_BCTRLRx_RWCBURSTEN_POS 19U +#define EBI_BCTRLRx_RWCBURSTEN_MSK BIT(EBI_BCTRLRx_RWCBURSTEN_POS) + +#define EBI_BCTRLRx_CPAGESIZE_POSS 16U +#define EBI_BCTRLRx_CPAGESIZE_POSE 18U +#define EBI_BCTRLRx_CPAGESIZE_MSK BITS(EBI_BCTRLRx_CPAGESIZE_POSS,EBI_BCTRLRx_CPAGESIZE_POSE) + +#define EBI_BCTRLRx_ASYNCWAIT_POS 15U +#define EBI_BCTRLRx_ASYNCWAIT_MSK BIT(EBI_BCTRLRx_ASYNCWAIT_POS) + +#define EBI_BCTRLRx_EXTMODEN_POS 14U +#define EBI_BCTRLRx_EXTMODEN_MSK BIT(EBI_BCTRLRx_EXTMODEN_POS) + +#define EBI_BCTRLRx_WAITEN_POS 13U +#define EBI_BCTRLRx_WAITEN_MSK BIT(EBI_BCTRLRx_WAITEN_POS) + +#define EBI_BCTRLRx_WREN_POS 12U +#define EBI_BCTRLRx_WREN_MSK BIT(EBI_BCTRLRx_WREN_POS) + +#define EBI_BCTRLRx_WAITCFG_POS 11U +#define EBI_BCTRLRx_WAITCFG_MSK BIT(EBI_BCTRLRx_WAITCFG_POS) + +#define EBI_BCTRLRx_WRAPMODE_POS 10U +#define EBI_BCTRLRx_WRAPMODE_MSK BIT(EBI_BCTRLRx_WRAPMODE_POS) + +#define EBI_BCTRLRx_WAITPOL_POS 9U +#define EBI_BCTRLRx_WAITPOL_MSK BIT(EBI_BCTRLRx_WAITPOL_POS) + +#define EBI_BCTRLRx_BURSTEN_POS 8U +#define EBI_BCTRLRx_BURSTEN_MSK BIT(EBI_BCTRLRx_BURSTEN_POS) + +#define EBI_BCTRLRx_FLASHACCEN_POS 6U +#define EBI_BCTRLRx_FLASHACCEN_MSK BIT(EBI_BCTRLRx_FLASHACCEN_POS) + +#define EBI_BCTRLRx_MEMWID_POSS 4U +#define EBI_BCTRLRx_MEMWID_POSE 5U +#define EBI_BCTRLRx_MEMWID_MSK BITS(EBI_BCTRLRx_MEMWID_POSS,EBI_BCTRLRx_MEMWID_POSE) +#define EBI_BCTRLRx_MEMWID_0 (0x1U << EBI_BCTRLRx_MEMWID_POSS) +#define EBI_BCTRLRx_MEMWID_1 (0x2U << EBI_BCTRLRx_MEMWID_POSS) + +#define EBI_BCTRLRx_MEMTYP_POSS 2U +#define EBI_BCTRLRx_MEMTYP_POSE 3U +#define EBI_BCTRLRx_MEMTYP_MSK BITS(EBI_BCTRLRx_MEMTYP_POSS,EBI_BCTRLRx_MEMTYP_POSE) +#define EBI_BCTRLRx_MEMTYP_0 (0x1U << EBI_BCTRLRx_MEMTYP_POSS) +#define EBI_BCTRLRx_MEMTYP_1 (0x2U << EBI_BCTRLRx_MEMTYP_POSS) + +#define EBI_BCTRLRx_MUXEN_POS 1U +#define EBI_BCTRLRx_MUXEN_MSK BIT(EBI_BCTRLRx_MUXEN_POS) + +#define EBI_BCTRLRx_MEMBKEN_POS 0U +#define EBI_BCTRLRx_MEMBKEN_MSK BIT(EBI_BCTRLRx_MEMBKEN_POS) + +/****************** Bit definition for EBI_BTRx(x= 1..3) register ************************/ + +#define EBI_BTRx_ACCMODE_POSS 28U +#define EBI_BTRx_ACCMODE_POSE 29U +#define EBI_BTRx_ACCMODE_MSK BITS(EBI_BTRx_ACCMODE_POSS,EBI_BTRx_ACCMODE_POSE) +#define EBI_BTRx_ACCMODE_0 (0x1U << EBI_BTRx_ACCMODE_POSS) +#define EBI_BTRx_ACCMODE_1 (0x2U << EBI_BTRx_ACCMODE_POSS) + +#define EBI_BTRx_DATALAT_POSS 24U +#define EBI_BTRx_DATALAT_POSE 27U +#define EBI_BTRx_DATALAT_MSK BITS(EBI_BTRx_DATALAT_POSS,EBI_BTRx_DATALAT_POSE) + +#define EBI_BTRx_CLKDIV_POSS 20U +#define EBI_BTRx_CLKDIV_POSE 23U +#define EBI_BTRx_CLKDIV_MSK BITS(EBI_BTRx_CLKDIV_POSS,EBI_BTRx_CLKDIV_POSE) + +#define EBI_BTRx_BUSTURN_POSS 16U +#define EBI_BTRx_BUSTURN_POSE 19U +#define EBI_BTRx_BUSTURN_MSK BITS(EBI_BTRx_BUSTURN_POSS,EBI_BTRx_BUSTURN_POSE) + +#define EBI_BTRx_DATAHOLD_POSS 8U +#define EBI_BTRx_DATAHOLD_POSE 15U +#define EBI_BTRx_DATAHOLD_MSK BITS(EBI_BTRx_DATAHOLD_POSS,EBI_BTRx_DATAHOLD_POSE) + +#define EBI_BTRx_ADDHOLD_POSS 4U +#define EBI_BTRx_ADDHOLD_POSE 7U +#define EBI_BTRx_ADDHOLD_MSK BITS(EBI_BTRx_ADDHOLD_POSS,EBI_BTRx_ADDHOLD_POSE) + +#define EBI_BTRx_ADDATASETUP_POSS 0U +#define EBI_BTRx_ADDATASETUP_POSE 3U +#define EBI_BTRx_ADDATASETUP_MSK BITS(EBI_BTRx_ADDATASETUP_POSS,EBI_BTRx_ADDATASETUP_POSE) + +/****************** Bit definition for EBI_BWRTRx(x= 1..3) register ************************/ + +#define EBI_BWRTRx_ACCMODE_POSS 28U +#define EBI_BWRTRx_ACCMODE_POSE 29U +#define EBI_BWRTRx_ACCMODE_MSK BITS(EBI_BWRTRx_ACCMODE_POSS,EBI_BWRTRx_ACCMODE_POSE) + +#define EBI_BWRTRx_BUSTURN_POSS 16U +#define EBI_BWRTRx_BUSTURN_POSE 19U +#define EBI_BWRTRx_BUSTURN_MSK BITS(EBI_BWRTRx_BUSTURN_POSS,EBI_BWRTRx_BUSTURN_POSE) + +#define EBI_BWRTRx_DATAHOLD_POSS 8U +#define EBI_BWRTRx_DATAHOLD_POSE 15U +#define EBI_BWRTRx_DATAHOLD_MSK BITS(EBI_BWRTRx_DATAHOLD_POSS,EBI_BWRTRx_DATAHOLD_POSE) + +#define EBI_BWRTRx_ADDHOLD_POSS 4U +#define EBI_BWRTRx_ADDHOLD_POSE 7U +#define EBI_BWRTRx_ADDHOLD_MSK BITS(EBI_BWRTRx_ADDHOLD_POSS,EBI_BWRTRx_ADDHOLD_POSE) + +#define EBI_BWRTRx_ADDATASETUP_POSS 0U +#define EBI_BWRTRx_ADDATASETUP_POSE 3U +#define EBI_BWRTRx_ADDATASETUP_MSK BITS(EBI_BWRTRx_ADDATASETUP_POSS,EBI_BWRTRx_ADDATASETUP_POSE) + +/****************** Bit definition for EBI_LCDCTRLx(x= 1..3) register ************************/ + +#define EBI_LCDCTRLx_HSYNCPOL_POS 29U +#define EBI_LCDCTRLx_HSYNCPOL_MSK BIT(EBI_LCDCTRLx_HSYNCPOL_POS) + +#define EBI_LCDCTRLx_VSYNCPOL_POS 28U +#define EBI_LCDCTRLx_VSYNCPOL_MSK BIT(EBI_LCDCTRLx_VSYNCPOL_POS) + +#define EBI_LCDCTRLx_DENPOL_POS 27U +#define EBI_LCDCTRLx_DENPOL_MSK BIT(EBI_LCDCTRLx_DENPOL_POS) + +#define EBI_LCDCTRLx_LCDEN_POS 26U +#define EBI_LCDCTRLx_LCDEN_MSK BIT(EBI_LCDCTRLx_LCDEN_POS) + +#define EBI_LCDCTRLx_LCDINT_POS 25U +#define EBI_LCDCTRLx_LCDINT_MSK BIT(EBI_LCDCTRLx_LCDINT_POS) + +#define EBI_LCDCTRLx_DCLKPOL_POS 24U +#define EBI_LCDCTRLx_DCLKPOL_MSK BIT(EBI_LCDCTRLx_DCLKPOL_POS) + +#define EBI_LCDCTRLx_DATASETUP_POSS 16U +#define EBI_LCDCTRLx_DATASETUP_POSE 23U +#define EBI_LCDCTRLx_DATASETUP_MSK BITS(EBI_LCDCTRLx_DATASETUP_POSS,EBI_LCDCTRLx_DATASETUP_POSE) + +#define EBI_LCDCTRLx_VSYNCWID_POSS 8U +#define EBI_LCDCTRLx_VSYNCWID_POSE 15U +#define EBI_LCDCTRLx_VSYNCWID_MSK BITS(EBI_LCDCTRLx_VSYNCWID_POSS,EBI_LCDCTRLx_VSYNCWID_POSE) + +#define EBI_LCDCTRLx_HSYNCWID_POSS 0U +#define EBI_LCDCTRLx_HSYNCWID_POSE 7U +#define EBI_LCDCTRLx_HSYNCWID_MSK BITS(EBI_LCDCTRLx_HSYNCWID_POSS,EBI_LCDCTRLx_HSYNCWID_POSE) + +/****************** Bit definition for EBI_LCDCFGx(x= 1..4) register ************************/ + +#define EBI_LCDCFGx_LINENUM_POSS 16U +#define EBI_LCDCFGx_LINENUM_POSE 31U +#define EBI_LCDCFGx_LINENUM_MSK BITS(EBI_LCDCFGx_LINENUM_POSS,EBI_LCDCFGx_LINENUM_POSE) + +#define EBI_LCDCFGx_PXLNUM_POSS 0U +#define EBI_LCDCFGx_PXLNUM_POSE 15U +#define EBI_LCDCFGx_PXLNUM_MSK BITS(EBI_LCDCFGx_PXLNUM_POSS,EBI_LCDCFGx_PXLNUM_POSE) + +/****************** Bit definition for EBI_LCDSTx(x= 1..3) register ************************/ + +#define EBI_LCDSTx_LINECNT_POSS 16U +#define EBI_LCDSTx_LINECNT_POSE 31U +#define EBI_LCDSTx_LINECNT_MSK BITS(EBI_LCDSTx_LINECNT_POSS,EBI_LCDSTx_LINECNT_POSE) + +#define EBI_LCDSTx_PXLCNT_POSS 0U +#define EBI_LCDSTx_PXLCNT_POSE 15U +#define EBI_LCDSTx_PXLCNT_MSK BITS(EBI_LCDSTx_PXLCNT_POSS,EBI_LCDSTx_PXLCNT_POSE) + +/****************** Bit definition for EBI_PCTRLRx(x = 2..3) register ************************/ + +#define EBI_PCTRLRx_ECCPSIZE_POSS 17U +#define EBI_PCTRLRx_ECCPSIZE_POSE 19U +#define EBI_PCTRLRx_ECCPSIZE_MSK BITS(EBI_PCTRLRx_ECCPSIZE_POSS,EBI_PCTRLRx_ECCPSIZE_POSE) +#define EBI_PCTRLRx_ECCPS_0 (0x1U << EBI_PCTRLRx_ECCPSIZE_POSS) +#define EBI_PCTRLRx_ECCPS_1 (0x2U << EBI_PCTRLRx_ECCPSIZE_POSS) +#define EBI_PCTRLRx_ECCPS_2 (0x4U << EBI_PCTRLRx_ECCPSIZE_POSS) + +#define EBI_PCTRLRx_ARDLY_POSS 13U +#define EBI_PCTRLRx_ARDLY_POSE 16U +#define EBI_PCTRLRx_ARDLY_MSK BITS(EBI_PCTRLRx_ARDLY_POSS,EBI_PCTRLRx_ARDLY_POSE) + +#define EBI_PCTRLRx_CRDLY_POSS 9U +#define EBI_PCTRLRx_CRDLY_POSE 12U +#define EBI_PCTRLRx_CRDLY_MSK BITS(EBI_PCTRLRx_CRDLY_POSS,EBI_PCTRLRx_CRDLY_POSE) + +#define EBI_PCTRLRx_TFUNSEL_POS 8U +#define EBI_PCTRLRx_TFUNSEL_MSK BIT(EBI_PCTRLRx_TFUNSEL_POS) + +#define EBI_PCTRLRx_ECCEN_POS 6U +#define EBI_PCTRLRx_ECCEN_MSK BIT(EBI_PCTRLRx_ECCEN_POS) + +#define EBI_PCTRLRx_DATBUSWID_POSS 4U +#define EBI_PCTRLRx_DATBUSWID_POSE 5U +#define EBI_PCTRLRx_DATBUSWID_MSK BITS(EBI_PCTRLRx_DATBUSWID_POSS,EBI_PCTRLRx_DATBUSWID_POSE) + +#define EBI_PCTRLRx_MEMTYP_POS 3U +#define EBI_PCTRLRx_MEMTYP_MSK BIT(EBI_PCTRLRx_MEMTYP_POS) + +#define EBI_PCTRLRx_MEMBKEN_POS 2U +#define EBI_PCTRLRx_MEMBKEN_MSK BIT(EBI_PCTRLRx_MEMBKEN_POS) + +#define EBI_PCTRLRx_WAITEN_POS 1U +#define EBI_PCTRLRx_WAITEN_MSK BIT(EBI_PCTRLRx_WAITEN_POS) + +/****************** Bit definition for EBI_STARx(x = 2..3) register ************************/ + +#define EBI_STARx_FIFOEMPT_POS 6U +#define EBI_STARx_FIFOEMPT_MSK BIT(EBI_STARx_FIFOEMPT_POS) + +#define EBI_STARx_IFALLEN_POS 5U +#define EBI_STARx_IFALLEN_MSK BIT(EBI_STARx_IFALLEN_POS) + +#define EBI_STARx_IHILEN_POS 4U +#define EBI_STARx_IHILEN_MSK BIT(EBI_STARx_IHILEN_POS) + +#define EBI_STARx_IRISEEN_POS 3U +#define EBI_STARx_IRISEEN_MSK BIT(EBI_STARx_IRISEEN_POS) + +#define EBI_STARx_IFALLS_POS 2U +#define EBI_STARx_IFALLS_MSK BIT(EBI_STARx_IFALLS_POS) + +#define EBI_STARx_IHILS_POS 1U +#define EBI_STARx_IHILS_MSK BIT(EBI_STARx_IHILS_POS) + +#define EBI_STARx_IRISES_POS 0U +#define EBI_STARx_IRISES_MSK BIT(EBI_STARx_IRISES_POS) + +/****************** Bit definition for EBI_PMEMRx(x = 2..3) register ************************/ + +#define EBI_PMEMRx_MEMHIZT_POSS 24U +#define EBI_PMEMRx_MEMHIZT_POSE 31U +#define EBI_PMEMRx_MEMHIZT_MSK BITS(EBI_PMEMRx_MEMHIZT_POSS,EBI_PMEMRx_MEMHIZT_POSE) + +#define EBI_PMEMRx_MEMHOLD_POSS 16U +#define EBI_PMEMRx_MEMHOLD_POSE 23U +#define EBI_PMEMRx_MEMHOLD_MSK BITS(EBI_PMEMRx_MEMHOLD_POSS,EBI_PMEMRx_MEMHOLD_POSE) + +#define EBI_PMEMRx_MEMWAIT_POSS 8U +#define EBI_PMEMRx_MEMWAIT_POSE 15U +#define EBI_PMEMRx_MEMWAIT_MSK BITS(EBI_PMEMRx_MEMWAIT_POSS,EBI_PMEMRx_MEMWAIT_POSE) + +#define EBI_PMEMRx_MEMSETUP_POSS 0U +#define EBI_PMEMRx_MEMSETUP_POSE 7U +#define EBI_PMEMRx_MEMSETUP_MSK BITS(EBI_PMEMRx_MEMSETUP_POSS,EBI_PMEMRx_MEMSETUP_POSE) + +/****************** Bit definition for EBI_PATTRx(x = 2..3) register ************************/ + +#define EBI_PATTRx_ATTHIZT_POSS 24U +#define EBI_PATTRx_ATTHIZT_POSE 31U +#define EBI_PATTRx_ATTHIZT_MSK BITS(EBI_PATTRx_ATTHIZT_POSS,EBI_PATTRx_ATTHIZT_POSE) + +#define EBI_PATTRx_ATTHOLD_POSS 16U +#define EBI_PATTRx_ATTHOLD_POSE 23U +#define EBI_PATTRx_ATTHOLD_MSK BITS(EBI_PATTRx_ATTHOLD_POSS,EBI_PATTRx_ATTHOLD_POSE) + +#define EBI_PATTRx_ATTWAIT_POSS 8U +#define EBI_PATTRx_ATTWAIT_POSE 15U +#define EBI_PATTRx_ATTWAIT_MSK BITS(EBI_PATTRx_ATTWAIT_POSS,EBI_PATTRx_ATTWAIT_POSE) + +#define EBI_PATTRx_ATTSETUP_POSS 0U +#define EBI_PATTRx_ATTSETUP_POSE 7U +#define EBI_PATTRx_ATTSETUP_MSK BITS(EBI_PATTRx_ATTSETUP_POSS,EBI_PATTRx_ATTSETUP_POSE) + +/****************** Bit definition for EBI_ECCRESULTx(x = 2..3) register ************************/ + +#define EBI_ECCRESULTx_ECCRESULT_POSS 0U +#define EBI_ECCRESULTx_ECCRESULT_POSE 31U +#define EBI_ECCRESULTx_ECCRESULT_MSK BITS(EBI_ECCRESULTx_ECCRESULT_POSS,EBI_ECCRESULTx_ECCRESULT_POSE) + +typedef struct +{ + __IO uint32_t BTCR[8]; +} EBI_Bank1_TypeDef; + +typedef struct +{ + __IO uint32_t BWTR[7]; +} EBI_Bank1E_TypeDef; + +typedef struct +{ + __IO uint32_t PCTRLR2; + __IO uint32_t STAR2; + __IO uint32_t PMEMR2; + __IO uint32_t PATTR2; + uint32_t RESERVED0; + __IO uint32_t ECCRESULT2; + uint32_t RESERVED1; + uint32_t RESERVED2; + __IO uint32_t PCTRLR3; + __IO uint32_t STAR3; + __IO uint32_t PMEMR3; + __IO uint32_t PATTR3; + uint32_t RESERVED3; + __IO uint32_t ECCRESULT3; +} EBI_Bank2_3_TypeDef; + +typedef struct +{ + __IO uint32_t LCDCRCFGS[15]; + +} EBI_Bank1_LCD_TypeDef; + + +/****************** Bit definition for USB_FADDR register ************************/ + +#define USB_FADDR_FADDR_POSS 0U +#define USB_FADDR_FADDR_POSE 6U +#define USB_FADDR_FADDR_MSK BITS(USB_FADDR_FADDR_POSS,USB_FADDR_FADDR_POSE) + +/****************** Bit definition for USB_POWER register ************************/ + +#define USB_POWER_ISOUPDATA_POS 7U +#define USB_POWER_ISOUPDATA_MSK BIT(USB_POWER_ISOUPDATA_POS) + +#define USB_POWER_SOFTCONN_POS 6U +#define USB_POWER_SOFTCONN_MSK BIT(USB_POWER_SOFTCONN_POS) + +#define USB_POWER_HS_EN_POS 5U +#define USB_POWER_HS_EN_MSK BIT(USB_POWER_HS_EN_POS) + +#define USB_POWER_HS_M_POS 4U +#define USB_POWER_HS_M_MSK BIT(USB_POWER_HS_M_POS) + +#define USB_POWER_RESET_POS 3U +#define USB_POWER_RESET_MSK BIT(USB_POWER_RESET_POS) + +#define USB_POWER_RESUME_POS 2U +#define USB_POWER_RESUME_MSK BIT(USB_POWER_RESUME_POS) + +#define USB_POWER_SUSPEND_POS 1U +#define USB_POWER_SUSPEND_MSK BIT(USB_POWER_SUSPEND_POS) + +#define USB_POWER_EN_SPDM_POS 0U +#define USB_POWER_EN_SPDM_MSK BIT(USB_POWER_EN_SPDM_POS) + +/****************** Bit definition for USB_TXIS register ************************/ + +#define USB_TXIS_EP7TX_IF_POS 7U +#define USB_TXIS_EP7TX_IF_MSK BIT(USB_TXIS_EP7TX_IF_POS) + +#define USB_TXIS_EP6TX_IF_POS 6U +#define USB_TXIS_EP6TX_IF_MSK BIT(USB_TXIS_EP6TX_IF_POS) + +#define USB_TXIS_EP5TX_IF_POS 5U +#define USB_TXIS_EP5TX_IF_MSK BIT(USB_TXIS_EP5TX_IF_POS) + +#define USB_TXIS_EP4TX_IF_POS 4U +#define USB_TXIS_EP4TX_IF_MSK BIT(USB_TXIS_EP4TX_IF_POS) + +#define USB_TXIS_EP3TX_IF_POS 3U +#define USB_TXIS_EP3TX_IF_MSK BIT(USB_TXIS_EP3TX_IF_POS) + +#define USB_TXIS_EP2TX_IF_POS 2U +#define USB_TXIS_EP2TX_IF_MSK BIT(USB_TXIS_EP2TX_IF_POS) + +#define USB_TXIS_EP1TX_IF_POS 1U +#define USB_TXIS_EP1TX_IF_MSK BIT(USB_TXIS_EP1TX_IF_POS) + +#define USB_TXIS_EP0_IF_POS 0U +#define USB_TXIS_EP0_IF_MSK BIT(USB_TXIS_EP0_IF_POS) + +/****************** Bit definition for USB_RXIS register ************************/ + +#define USB_RXIS_EP7RX_IF_POS 7U +#define USB_RXIS_EP7RX_IF_MSK BIT(USB_RXIS_EP7RX_IF_POS) + +#define USB_RXIS_EP6RX_IF_POS 6U +#define USB_RXIS_EP6RX_IF_MSK BIT(USB_RXIS_EP6RX_IF_POS) + +#define USB_RXIS_EP5RX_IF_POS 5U +#define USB_RXIS_EP5RX_IF_MSK BIT(USB_RXIS_EP5RX_IF_POS) + +#define USB_RXIS_EP4RX_IF_POS 4U +#define USB_RXIS_EP4RX_IF_MSK BIT(USB_RXIS_EP4RX_IF_POS) + +#define USB_RXIS_EP3RX_IF_POS 3U +#define USB_RXIS_EP3RX_IF_MSK BIT(USB_RXIS_EP3RX_IF_POS) + +#define USB_RXIS_EP2RX_IF_POS 2U +#define USB_RXIS_EP2RX_IF_MSK BIT(USB_RXIS_EP2RX_IF_POS) + +#define USB_RXIS_EP1RX_IF_POS 1U +#define USB_RXIS_EP1RX_IF_MSK BIT(USB_RXIS_EP1RX_IF_POS) + +/****************** Bit definition for USB_TXIE register ************************/ + +#define USB_TXIE_EP7TX_IE_POS 7U +#define USB_TXIE_EP7TX_IE_MSK BIT(USB_TXIE_EP7TX_IE_POS) + +#define USB_TXIE_EP6TX_IE_POS 6U +#define USB_TXIE_EP6TX_IE_MSK BIT(USB_TXIE_EP6TX_IE_POS) + +#define USB_TXIE_EP5TX_IE_POS 5U +#define USB_TXIE_EP5TX_IE_MSK BIT(USB_TXIE_EP5TX_IE_POS) + +#define USB_TXIE_EP4TX_IE_POS 4U +#define USB_TXIE_EP4TX_IE_MSK BIT(USB_TXIE_EP4TX_IE_POS) + +#define USB_TXIE_EP3TX_IE_POS 3U +#define USB_TXIE_EP3TX_IE_MSK BIT(USB_TXIE_EP3TX_IE_POS) + +#define USB_TXIE_EP2TX_IE_POS 2U +#define USB_TXIE_EP2TX_IE_MSK BIT(USB_TXIE_EP2TX_IE_POS) + +#define USB_TXIE_EP1TX_IE_POS 1U +#define USB_TXIE_EP1TX_IE_MSK BIT(USB_TXIE_EP1TX_IE_POS) + +#define USB_TXIE_EP0_IE_POS 0U +#define USB_TXIE_EP0_IE_MSK BIT(USB_TXIE_EP0_IE_POS) + +/****************** Bit definition for USB_RXIE register ************************/ + +#define USB_RXIE_EP7RX_IE_POS 7U +#define USB_RXIE_EP7RX_IE_MSK BIT(USB_RXIE_EP7RX_IE_POS) + +#define USB_RXIE_EP6RX_IE_POS 6U +#define USB_RXIE_EP6RX_IE_MSK BIT(USB_RXIE_EP6RX_IE_POS) + +#define USB_RXIE_EP5RX_IE_POS 5U +#define USB_RXIE_EP5RX_IE_MSK BIT(USB_RXIE_EP5RX_IE_POS) + +#define USB_RXIE_EP4RX_IE_POS 4U +#define USB_RXIE_EP4RX_IE_MSK BIT(USB_RXIE_EP4RX_IE_POS) + +#define USB_RXIE_EP3RX_IE_POS 3U +#define USB_RXIE_EP3RX_IE_MSK BIT(USB_RXIE_EP3RX_IE_POS) + +#define USB_RXIE_EP2RX_IE_POS 2U +#define USB_RXIE_EP2RX_IE_MSK BIT(USB_RXIE_EP2RX_IE_POS) + +#define USB_RXIE_EP1RX_IE_POS 1U +#define USB_RXIE_EP1RX_IE_MSK BIT(USB_RXIE_EP1RX_IE_POS) + +/****************** Bit definition for USB_USBIS register ************************/ + +#define USB_USBIS_DISCON_IF_POS 5U +#define USB_USBIS_DISCON_IF_MSK BIT(USB_USBIS_DISCON_IF_POS) + +#define USB_USBIS_SOF_IF_POS 3U +#define USB_USBIS_SOF_IF_MSK BIT(USB_USBIS_SOF_IF_POS) + +#define USB_USBIS_RESET_IF_POS 2U +#define USB_USBIS_RESET_IF_MSK BIT(USB_USBIS_RESET_IF_POS) + +#define USB_USBIS_RESUME_IF_POS 1U +#define USB_USBIS_RESUME_IF_MSK BIT(USB_USBIS_RESUME_IF_POS) + +#define USB_USBIS_SUSPEND_IF_POS 0U +#define USB_USBIS_SUSPEND_IF_MSK BIT(USB_USBIS_SUSPEND_IF_POS) + +/****************** Bit definition for USB_USBIE register ************************/ + +#define USB_USBIE_DISCON_IE_POS 5U +#define USB_USBIE_DISCON_IE_MSK BIT(USB_USBIE_DISCON_IE_POS) + +#define USB_USBIE_SOF_IE_POS 3U +#define USB_USBIE_SOF_IE_MSK BIT(USB_USBIE_SOF_IE_POS) + +#define USB_USBIE_RESET_IE_POS 2U +#define USB_USBIE_RESET_IE_MSK BIT(USB_USBIE_RESET_IE_POS) + +#define USB_USBIE_RESUME_IE_POS 1U +#define USB_USBIE_RESUME_IE_MSK BIT(USB_USBIE_RESUME_IE_POS) + +#define USB_USBIE_SUSPEND_IE_POS 0U +#define USB_USBIE_SUSPEND_IE_MSK BIT(USB_USBIE_SUSPEND_IE_POS) + +/****************** Bit definition for USB_FRAME register ************************/ + +#define USB_FRAME_FRAME_POSS 0U +#define USB_FRAME_FRAME_POSE 10U +#define USB_FRAME_FRAME_MSK BITS(USB_FRAME_FRAME_POSS,USB_FRAME_FRAME_POSE) + +/****************** Bit definition for USB_INDEX register ************************/ + +#define USB_INDEX_EP_INDEX_POSS 0U +#define USB_INDEX_EP_INDEX_POSE 3U +#define USB_INDEX_EP_INDEX_MSK BITS(USB_INDEX_EP_INDEX_POSS,USB_INDEX_EP_INDEX_POSE) + +/****************** Bit definition for USB_TEST register ************************/ + +#define USB_TEST_FORCE_HST_POS 7U +#define USB_TEST_FORCE_HST_MSK BIT(USB_TEST_FORCE_HST_POS) + +#define USB_TEST_FIFO_ACS_POS 6U +#define USB_TEST_FIFO_ACS_MSK BIT(USB_TEST_FIFO_ACS_POS) + +#define USB_TEST_FORCE_FS_POS 5U +#define USB_TEST_FORCE_FS_MSK BIT(USB_TEST_FORCE_FS_POS) + +#define USB_TEST_FORCE_HS_POS 4U +#define USB_TEST_FORCE_HS_MSK BIT(USB_TEST_FORCE_HS_POS) + +#define USB_TEST_TEST_PKT_POS 3U +#define USB_TEST_TEST_PKT_MSK BIT(USB_TEST_TEST_PKT_POS) + +#define USB_TEST_TEST_K_POS 2U +#define USB_TEST_TEST_K_MSK BIT(USB_TEST_TEST_K_POS) + +#define USB_TEST_TEST_J_POS 1U +#define USB_TEST_TEST_J_MSK BIT(USB_TEST_TEST_J_POS) + +#define USB_TEST_TEST_SENA_POS 0U +#define USB_TEST_TEST_SENA_MSK BIT(USB_TEST_TEST_SENA_POS) + +typedef union { + uint8_t Byte[4]; + uint16_t HalfWord[2]; + uint32_t Word; +} USB_FIFO_Typedef; + +/****************** Bit definition for USB_DEVCTL register ************************/ + +#define USB_DEVCTL_BDEVICE_POS 7U +#define USB_DEVCTL_BDEVICE_MSK BIT(USB_DEVCTL_BDEVICE_POS) + +#define USB_DEVCTL_FSDEV_POS 6U +#define USB_DEVCTL_FSDEV_MSK BIT(USB_DEVCTL_FSDEV_POS) + +#define USB_DEVCTL_LSDEV_POS 5U +#define USB_DEVCTL_LSDEV_MSK BIT(USB_DEVCTL_LSDEV_POS) + +#define USB_DEVCTL_VBUS_POSS 3U +#define USB_DEVCTL_VBUS_POSE 4U +#define USB_DEVCTL_VBUS_MSK BITS(USB_DEVCTL_VBUS_POSS,USB_DEVCTL_VBUS_POSE) + +#define USB_DEVCTL_HOSTMODE_POS 2U +#define USB_DEVCTL_HOSTMODE_MSK BIT(USB_DEVCTL_HOSTMODE_POS) + +#define USB_DEVCTL_HOSTREQ_POS 1U +#define USB_DEVCTL_HOSTREQ_MSK BIT(USB_DEVCTL_HOSTREQ_POS) + +#define USB_DEVCTL_SESSION_POS 0U +#define USB_DEVCTL_SESSION_MSK BIT(USB_DEVCTL_SESSION_POS) + +/****************** Bit definition for USB_TXFIFOSIZE register ************************/ + +#define USB_TXFIFOSIZE_DPB_POS 4U +#define USB_TXFIFOSIZE_DPB_MSK BIT(USB_TXFIFOSIZE_DPB_POS) + +#define USB_TXFIFOSIZE_TXFIFOSIZE_POSS 0U +#define USB_TXFIFOSIZE_TXFIFOSIZE_POSE 3U +#define USB_TXFIFOSIZE_TXFIFOSIZE_MSK BITS(USB_TXFIFOSIZE_TXFIFOSIZE_POSS,USB_TXFIFOSIZE_TXFIFOSIZE_POSE) + +/****************** Bit definition for USB_RXFIFOSIZE register ************************/ + +#define USB_RXFIFOSIZE_DPB_POS 4U +#define USB_RXFIFOSIZE_DPB_MSK BIT(USB_RXFIFOSIZE_DPB_POS) + +#define USB_RXFIFOSIZE_RXFIFOSIZE_POSS 0U +#define USB_RXFIFOSIZE_RXFIFOSIZE_POSE 3U +#define USB_RXFIFOSIZE_RXFIFOSIZE_MSK BITS(USB_RXFIFOSIZE_RXFIFOSIZE_POSS,USB_RXFIFOSIZE_RXFIFOSIZE_POSE) + +/****************** Bit definition for USB_TXFIFOADD register ************************/ + +#define USB_TXFIFOADD_ADDR_POSS 0U +#define USB_TXFIFOADD_ADDR_POSE 8U +#define USB_TXFIFOADD_ADDR_MSK BITS(USB_TXFIFOADD_ADDR_POSS,USB_TXFIFOADD_ADDR_POSE) + +/****************** Bit definition for USB_RXFIFOADD register ************************/ + +#define USB_RXFIFOADD_ADDR_POSS 0U +#define USB_RXFIFOADD_ADDR_POSE 8U +#define USB_RXFIFOADD_ADDR_MSK BITS(USB_RXFIFOADD_ADDR_POSS,USB_RXFIFOADD_ADDR_POSE) + +/****************** Bit definition for USB_LINKINFO register ************************/ + +#define USB_LINKINFO_WTCON_POSS 4U +#define USB_LINKINFO_WTCON_POSE 7U +#define USB_LINKINFO_WTCON_MSK BITS(USB_LINKINFO_WTCON_POSS,USB_LINKINFO_WTCON_POSE) + +#define USB_LINKINFO_WTID_POSS 0U +#define USB_LINKINFO_WTID_POSE 3U +#define USB_LINKINFO_WTID_MSK BITS(USB_LINKINFO_WTID_POSS,USB_LINKINFO_WTID_POSE) + +/****************** Bit definition for USB_VPLEN register ************************/ + +#define USB_VPLEN_VPLEN_POSS 0U +#define USB_VPLEN_VPLEN_POSE 7U +#define USB_VPLEN_VPLEN_MSK BITS(USB_VPLEN_VPLEN_POSS,USB_VPLEN_VPLEN_POSE) + +/****************** Bit definition for USB_HS_EOF1 register ************************/ + +#define USB_HS_EOF1_HSEOF1_POSS 0U +#define USB_HS_EOF1_HSEOF1_POSE 7U +#define USB_HS_EOF1_HSEOF1_MSK BITS(USB_HS_EOF1_HSEOF1_POSS,USB_HS_EOF1_HSEOF1_POSE) + +/****************** Bit definition for USB_FS_EOF1 register ************************/ + +#define USB_FS_EOF1_FSEOF1_POSS 0U +#define USB_FS_EOF1_FSEOF1_POSE 7U +#define USB_FS_EOF1_FSEOF1_MSK BITS(USB_FS_EOF1_FSEOF1_POSS,USB_FS_EOF1_FSEOF1_POSE) + +/****************** Bit definition for USB_LS_EOF1 register ************************/ + +#define USB_LS_EOF1_LSEOF1_POSS 0U +#define USB_LS_EOF1_LSEOF1_POSE 7U +#define USB_LS_EOF1_LSEOF1_MSK BITS(USB_LS_EOF1_LSEOF1_POSS,USB_LS_EOF1_LSEOF1_POSE) + +/****************** Bit definition for TXxFUNCADDR register ************************/ + +#define USB_TXxFUNCADDR_ADDR_POSS 0U +#define USB_TXxFUNCADDR_ADDR_POSE 6U +#define USB_TXxFUNCADDR_ADDR_MSK BITS(USB_TXxFUNCADDR_ADDR_POSS,USB_TXxFUNCADDR_ADDR_POSE) + +/****************** Bit definition for TXxHUBADDR register ************************/ + +#define USB_TXxHUBADDR_ADDR_POSS 0U +#define USB_TXxHUBADDR_ADDR_POSE 6U +#define USB_TXxHUBADDR_ADDR_MSK BITS(USB_TXxHUBADDR_ADDR_POSS,USB_TXxHUBADDR_ADDR_POSE) + +#define USB_TXxHUBADDR_MULTTRAN_POS 7U +#define USB_TXxHUBADDR_MULTTRAN_MSK BIT(USB_TXxHUBADDR_MULTTRAN_POS) + +/****************** Bit definition for TXxHUBPORT register ************************/ + +#define USB_TXxHUBPORT_HUBPORT_POSS 0U +#define USB_TXxHUBPORT_HUBPORT_POSE 6U +#define USB_TXxHUBPORT_HUBPORT_MSK BITS(USB_TXxHUBPORT_HUBPORT_POSS,USB_TXxHUBPORT_HUBPORT_POSE) + +/****************** Bit definition for RXxFUNCADDR register ************************/ + +#define USB_RXxFUNCADDR_ADDR_POSS 0U +#define USB_RXxFUNCADDR_ADDR_POSE 6U +#define USB_RXxFUNCADDR_ADDR_MSK BITS(USB_RXxFUNCADDR_ADDR_POSS,USB_RXxFUNCADDR_ADDR_POSE) + +/****************** Bit definition for RXxHUBADDR register ************************/ + +#define USB_RXxHUBADDR_ADDR_POSS 0U +#define USB_RXxHUBADDR_ADDR_POSE 6U +#define USB_RXxHUBADDR_ADDR_MSK BITS(USB_RXxHUBADDR_ADDR_POSS,USB_RXxHUBADDR_ADDR_POSE) + +#define USB_RXxHUBADDR_MULTTRAN_POS 7U +#define USB_RXxHUBADDR_MULTTRAN_MSK BIT(USB_RXxHUBADDR_MULTTRAN_POS) + +/****************** Bit definition for RXxHUBPORT register ************************/ + +#define USB_RXxHUBPORT_HUBPORT_POSS 0U +#define USB_RXxHUBPORT_HUBPORT_POSE 6U +#define USB_RXxHUBPORT_HUBPORT_MSK BITS(USB_RXxHUBPORT_HUBPORT_POSS,USB_RXxHUBPORT_HUBPORT_POSE) + +typedef struct { + __IO uint8_t TXxFUNCADDR; + uint8_t rsv0; + __IO uint8_t TXxHUBADDR; + __IO uint8_t TXxHUBPORT; + __IO uint8_t RXxFUNCADDR; + uint8_t rsv1; + __IO uint8_t RXxHUBADDR; + __IO uint8_t RXxHUBPORT; +} USB_ADDR_Typedef; + +typedef struct{ + __IO uint16_t TXxMAXP; + __IO uint8_t TXxCSRL; + __IO uint8_t TXxCSRH; + __IO uint16_t RXxMAXP; + __IO uint8_t RXxCSRL; + __IO uint8_t RXxCSRH; + __I uint16_t RXxCOUNT; + __IO uint8_t TXxTYPE; + __IO uint8_t TXxINTERVAL; + __IO uint8_t RXxTYPE; + __IO uint8_t RXxINTERVAL; + uint8_t rsv0[2]; +} USB_CSRx_Typedef; + +/****************** Bit definition for DMA_INTR register ************************/ + +#define USB_DMA_INTR_CH0_POS 0U +#define USB_DMA_INTR_CH0_MSK BIT(USB_DMA_INTR_CH0_POS) + +#define USB_DMA_INTR_CH1_POS 1U +#define USB_DMA_INTR_CH1_MSK BIT(USB_DMA_INTR_CH1_POS) + +#define USB_DMA_INTR_CH2_POS 2U +#define USB_DMA_INTR_CH2_MSK BIT(USB_DMA_INTR_CH2_POS) + +#define USB_DMA_INTR_CH3_POS 3U +#define USB_DMA_INTR_CH3_MSK BIT(USB_DMA_INTR_CH3_POS) + +/****************** Bit definition for DMA_CNTL register ************************/ + +#define USB_DMA_CNTL_EN_POS 0U +#define USB_DMA_CNTL_EN_MSK BIT(USB_DMA_CNTL_EN_POS) + +#define USB_DMA_CNTL_DIR_POS 1U +#define USB_DMA_CNTL_DIR_MSK BIT(USB_DMA_CNTL_DIR_POS) + +#define USB_DMA_CNTL_MODE_POS 2U +#define USB_DMA_CNTL_MODE_MSK BIT(USB_DMA_CNTL_MODE_POS) + +#define USB_DMA_CNTL_IE_POS 3U +#define USB_DMA_CNTL_IE_MSK BIT(USB_DMA_CNTL_IE_POS) + +#define USB_DMA_CNTL_EP_POSS 4U +#define USB_DMA_CNTL_EP_POSE 7U +#define USB_DMA_CNTL_EP_MSK BITS(USB_DMA_CNTL_EP_POSS,USB_DMA_CNTL_EP_POSE) + +#define USB_DMA_CNTL_ERR_POS 8U +#define USB_DMA_CNTL_ERR_MSK BIT(USB_DMA_CNTL_ERR_POS) + +#define USB_DMA_CNTL_BRSTM_POSS 9U +#define USB_DMA_CNTL_BRSTM_POSE 10U +#define USB_DMA_CNTL_BRSTM_MSK BITS(USB_DMA_CNTL_BRSTM_POSS,USB_DMA_CNTL_BRSTM_POSE) + +typedef struct{ + __IO uint32_t DMA_CNTL; + __IO uint32_t DMA_ADDR; + __IO uint32_t DMA_COUNT; + uint32_t rsv; +} USB_DMA_CHx_Typedef; + +/****************** Bit definition for USB_RXDPKTBUFDIS register ************************/ + +#define USB_RXDPKTBUFDIS_EP7_POS 7U +#define USB_RXDPKTBUFDIS_EP7_MSK BIT(USB_RXDPKTBUFDIS_EP7_POS) + +#define USB_RXDPKTBUFDIS_EP6_POS 6U +#define USB_RXDPKTBUFDIS_EP6_MSK BIT(USB_RXDPKTBUFDIS_EP6_POS) + +#define USB_RXDPKTBUFDIS_EP5_POS 5U +#define USB_RXDPKTBUFDIS_EP5_MSK BIT(USB_RXDPKTBUFDIS_EP5_POS) + +#define USB_RXDPKTBUFDIS_EP4_POS 4U +#define USB_RXDPKTBUFDIS_EP4_MSK BIT(USB_RXDPKTBUFDIS_EP4_POS) + +#define USB_RXDPKTBUFDIS_EP3_POS 3U +#define USB_RXDPKTBUFDIS_EP3_MSK BIT(USB_RXDPKTBUFDIS_EP3_POS) + +#define USB_RXDPKTBUFDIS_EP2_POS 2U +#define USB_RXDPKTBUFDIS_EP2_MSK BIT(USB_RXDPKTBUFDIS_EP2_POS) + +#define USB_RXDPKTBUFDIS_EP1_POS 1U +#define USB_RXDPKTBUFDIS_EP1_MSK BIT(USB_RXDPKTBUFDIS_EP1_POS) + +/****************** Bit definition for USB_TXDPKTBUFDIS register ************************/ + +#define USB_TXDPKTBUFDIS_EP7_POS 7U +#define USB_TXDPKTBUFDIS_EP7_MSK BIT(USB_TXDPKTBUFDIS_EP7_POS) + +#define USB_TXDPKTBUFDIS_EP6_POS 6U +#define USB_TXDPKTBUFDIS_EP6_MSK BIT(USB_TXDPKTBUFDIS_EP6_POS) + +#define USB_TXDPKTBUFDIS_EP5_POS 5U +#define USB_TXDPKTBUFDIS_EP5_MSK BIT(USB_TXDPKTBUFDIS_EP5_POS) + +#define USB_TXDPKTBUFDIS_EP4_POS 4U +#define USB_TXDPKTBUFDIS_EP4_MSK BIT(USB_TXDPKTBUFDIS_EP4_POS) + +#define USB_TXDPKTBUFDIS_EP3_POS 3U +#define USB_TXDPKTBUFDIS_EP3_MSK BIT(USB_TXDPKTBUFDIS_EP3_POS) + +#define USB_TXDPKTBUFDIS_EP2_POS 2U +#define USB_TXDPKTBUFDIS_EP2_MSK BIT(USB_TXDPKTBUFDIS_EP2_POS) + +#define USB_TXDPKTBUFDIS_EP1_POS 1U +#define USB_TXDPKTBUFDIS_EP1_MSK BIT(USB_TXDPKTBUFDIS_EP1_POS) + +/****************** Bit definition for USB_LPM_ATTR register ************************/ + +#define USB_LPM_ATTR_ENDPNT_POSS 12U +#define USB_LPM_ATTR_ENDPNT_POSE 15U +#define USB_LPM_ATTR_ENDPNT_MSK BITS(USB_LPM_ATTR_ENDPNT_POSS,USB_LPM_ATTR_ENDPNT_POSE) + +#define USB_LPM_ATTR_RMTWAK_POS 8U +#define USB_LPM_ATTR_RMTWAK_MSK BIT(USB_LPM_ATTR_RMTWAK_POS) + +#define USB_LPM_ATTR_HIRD_POSS 4U +#define USB_LPM_ATTR_HIRD_POSE 7U +#define USB_LPM_ATTR_HIRD_MSK BITS(USB_LPM_ATTR_HIRD_POSS,USB_LPM_ATTR_HIRD_POSE) + +#define USB_LPM_ATTR_LINKSTATE_POSS 0U +#define USB_LPM_ATTR_LINKSTATE_POSE 3U +#define USB_LPM_ATTR_LINKSTATE_MSK BITS(USB_LPM_ATTR_LINKSTATE_POSS,USB_LPM_ATTR_LINKSTATE_POSE) + +/****************** Bit definition for USB_LPM_CNTRL register ************************/ + +#define USB_LPM_CNTRL_LPMNACK_POS 4U +#define USB_LPM_CNTRL_LPMNACK_MSK BIT(USB_LPM_CNTRL_LPMNACK_POS) + +#define USB_LPM_CNTRL_LPMEN_POSS 2U +#define USB_LPM_CNTRL_LPMEN_POSE 3U +#define USB_LPM_CNTRL_LPMEN_MSK BITS(USB_LPM_CNTRL_LPMEN_POSS,USB_LPM_CNTRL_LPMEN_POSE) + +#define USB_LPM_CNTRL_LPMRES_POS 1U +#define USB_LPM_CNTRL_LPMRES_MSK BIT(USB_LPM_CNTRL_LPMRES_POS) + +#define USB_LPM_CNTRL_LPMXMT_POS 0U +#define USB_LPM_CNTRL_LPMXMT_MSK BIT(USB_LPM_CNTRL_LPMXMT_POS) + +/****************** Bit definition for USB_LPM_INTREN register ************************/ + +#define USB_LPM_INTREN_LPMERREN_POS 5U +#define USB_LPM_INTREN_LPMERREN_MSK BIT(USB_LPM_INTREN_LPMERREN_POS) + +#define USB_LPM_INTREN_LPMRESEN_POS 4U +#define USB_LPM_INTREN_LPMRESEN_MSK BIT(USB_LPM_INTREN_LPMRESEN_POS) + +#define USB_LPM_INTREN_LPMNCEN_POS 3U +#define USB_LPM_INTREN_LPMNCEN_MSK BIT(USB_LPM_INTREN_LPMNCEN_POS) + +#define USB_LPM_INTREN_LPMACKEN_POS 2U +#define USB_LPM_INTREN_LPMACKEN_MSK BIT(USB_LPM_INTREN_LPMACKEN_POS) + +#define USB_LPM_INTREN_LPMNYEN_POS 1U +#define USB_LPM_INTREN_LPMNYEN_MSK BIT(USB_LPM_INTREN_LPMNYEN_POS) + +#define USB_LPM_INTREN_LPMSTEN_POS 0U +#define USB_LPM_INTREN_LPMSTEN_MSK BIT(USB_LPM_INTREN_LPMSTEN_POS) + +/****************** Bit definition for USB_LPM_INTR register ************************/ + +#define USB_LPM_INTR_LPMERR_POS 5U +#define USB_LPM_INTR_LPMERR_MSK BIT(USB_LPM_INTR_LPMERR_POS) + +#define USB_LPM_INTR_LPMRES_POS 4U +#define USB_LPM_INTR_LPMRES_MSK BIT(USB_LPM_INTR_LPMRES_POS) + +#define USB_LPM_INTR_LPMNC_POS 3U +#define USB_LPM_INTR_LPMNC_MSK BIT(USB_LPM_INTR_LPMNC_POS) + +#define USB_LPM_INTR_LPMACK_POS 2U +#define USB_LPM_INTR_LPMACK_MSK BIT(USB_LPM_INTR_LPMACK_POS) + +#define USB_LPM_INTR_LPMNY_POS 1U +#define USB_LPM_INTR_LPMNY_MSK BIT(USB_LPM_INTR_LPMNY_POS) + +#define USB_LPM_INTR_LPMST_POS 0U +#define USB_LPM_INTR_LPMST_MSK BIT(USB_LPM_INTR_LPMST_POS) + +/****************** Bit definition for USB_LPM_FADDR register ************************/ + +#define USB_LPM_FADDR_LPMFADDR_POSS 0U +#define USB_LPM_FADDR_LPMFADDR_POSE 6U +#define USB_LPM_FADDR_LPMFADDR_MSK BITS(USB_LPM_FADDR_LPMFADDR_POSS,USB_LPM_FADDR_LPMFADDR_POSE) + +typedef struct { + __IO uint8_t FADDR; + __IO uint8_t POWER; + __I uint8_t TXIS; + uint8_t rsv0; + __I uint8_t RXIS; + uint8_t rsv1; + __IO uint8_t TXIE; + uint8_t rsv2; + __IO uint8_t RXIE; + uint8_t rsv3; + __I uint8_t USBIS; + __IO uint8_t USBIE; + __I uint16_t FRAME; + __IO uint8_t INDEX; + __IO uint8_t TEST; + uint32_t rsv4[4]; + __IO USB_FIFO_Typedef FIFO[8]; + uint32_t rsv5[8]; + __IO uint8_t DEVCTL; + uint8_t rsv6; + __IO uint8_t TXFIFOSIZE; + __IO uint8_t RXFIFOSIZE; + __IO uint16_t TXFIFOADD; + __IO uint16_t RXFIFOADD; + uint8_t rsv7[18]; + __IO uint8_t LINKINFO; + __IO uint8_t VPLEN; + __IO uint8_t HS_EOF1; + __IO uint8_t FS_EOF1; + __IO uint8_t LS_EOF1; + uint8_t rsv8; + USB_ADDR_Typedef ADDR[8]; + uint32_t rsv9[16]; + uint8_t rsv10[2]; + __IO uint8_t CSR0L; + __IO uint8_t CSR0H; + uint8_t rsv11[4]; + __I uint8_t COUNT0; + uint8_t rsv12; + __IO uint8_t TYPE0; + __IO uint8_t NACK; + uint8_t rsv13[3]; + __I uint8_t CONFIG0; + USB_CSRx_Typedef CSR[7]; + uint32_t rsv14[32]; + __IO uint8_t DMA_INTR; + uint8_t rsv15[3]; + USB_DMA_CHx_Typedef DMA_CH[8]; + uint32_t rsv16[32]; + __IO uint32_t EP_RQPKTCOUNT[7]; + uint32_t rsv17[8]; + __IO uint16_t RXDPKTBUFDIS; + __IO uint16_t TXDPKTBUFDIS; + uint32_t rsv18[7]; + __IO uint16_t LPM_ATTR; + __IO uint8_t LPM_CNTRL; + __IO uint8_t LPM_INTREN; + __IO uint8_t LPM_INTR; + __IO uint8_t LPM_FADDR; +} USB_TypeDef; + +/****************** Bit definition for DBGC_IDCODE register ************************/ + +#define DBGC_IDCODE_REV_ID_POSS 16U +#define DBGC_IDCODE_REV_ID_POSE 31U +#define DBGC_IDCODE_REV_ID_MSK BITS(DBGC_IDCODE_REV_ID_POSS,DBGC_IDCODE_REV_ID_POSE) + +#define DBGC_IDCODE_CORE_ID_POSS 12U +#define DBGC_IDCODE_CORE_ID_POSE 15U +#define DBGC_IDCODE_CORE_ID_MSK BITS(DBGC_IDCODE_CORE_ID_POSS,DBGC_IDCODE_CORE_ID_POSE) + +#define DBGC_IDCODE_DEV_ID_POSS 0U +#define DBGC_IDCODE_DEV_ID_POSE 11U +#define DBGC_IDCODE_DEV_ID_MSK BITS(DBGC_IDCODE_DEV_ID_POSS,DBGC_IDCODE_DEV_ID_POSE) + +/****************** Bit definition for DBGC_CR register ************************/ + +#define DBGC_CR_DBG_STANDBY_POS 3U +#define DBGC_CR_DBG_STANDBY_MSK BIT(DBGC_CR_DBG_STANDBY_POS) + +#define DBGC_CR_DBG_STOP2_POS 2U +#define DBGC_CR_DBG_STOP2_MSK BIT(DBGC_CR_DBG_STOP2_POS) + +#define DBGC_CR_DBG_STOP1_POS 1U +#define DBGC_CR_DBG_STOP1_MSK BIT(DBGC_CR_DBG_STOP1_POS) + +#define DBGC_CR_DBG_SLEEP_POS 0U +#define DBGC_CR_DBG_SLEEP_MSK BIT(DBGC_CR_DBG_SLEEP_POS) + +/****************** Bit definition for DBGC_APB1FZ register ************************/ + +#define DBGC_APB1FZ_CAN_STOP_POS 12U +#define DBGC_APB1FZ_CAN_STOP_MSK BIT(DBGC_APB1FZ_CAN_STOP_POS) + +#define DBGC_APB1FZ_I2C1_SMBUS_TO_POS 9U +#define DBGC_APB1FZ_I2C1_SMBUS_TO_MSK BIT(DBGC_APB1FZ_I2C1_SMBUS_TO_POS) + +#define DBGC_APB1FZ_I2C0_SMBUS_TO_POS 8U +#define DBGC_APB1FZ_I2C0_SMBUS_TO_MSK BIT(DBGC_APB1FZ_I2C0_SMBUS_TO_POS) + +#define DBGC_APB1FZ_TIM7_STOP_POS 7U +#define DBGC_APB1FZ_TIM7_STOP_MSK BIT(DBGC_APB1FZ_TIM7_STOP_POS) + +#define DBGC_APB1FZ_TIM6_STOP_POS 6U +#define DBGC_APB1FZ_TIM6_STOP_MSK BIT(DBGC_APB1FZ_TIM6_STOP_POS) + +#define DBGC_APB1FZ_TIM5_STOP_POS 5U +#define DBGC_APB1FZ_TIM5_STOP_MSK BIT(DBGC_APB1FZ_TIM5_STOP_POS) + +#define DBGC_APB1FZ_TIM4_STOP_POS 4U +#define DBGC_APB1FZ_TIM4_STOP_MSK BIT(DBGC_APB1FZ_TIM4_STOP_POS) + +#define DBGC_APB1FZ_TIM3_STOP_POS 3U +#define DBGC_APB1FZ_TIM3_STOP_MSK BIT(DBGC_APB1FZ_TIM3_STOP_POS) + +#define DBGC_APB1FZ_TIM2_STOP_POS 2U +#define DBGC_APB1FZ_TIM2_STOP_MSK BIT(DBGC_APB1FZ_TIM2_STOP_POS) + +#define DBGC_APB1FZ_TIM1_STOP_POS 1U +#define DBGC_APB1FZ_TIM1_STOP_MSK BIT(DBGC_APB1FZ_TIM1_STOP_POS) + +#define DBGC_APB1FZ_TIM0_STOP_POS 0U +#define DBGC_APB1FZ_TIM0_STOP_MSK BIT(DBGC_APB1FZ_TIM0_STOP_POS) + +/****************** Bit definition for DBGC_APB2FZ register ************************/ + +#define DBGC_APB2FZ_RTC_STOP_POS 10U +#define DBGC_APB2FZ_RTC_STOP_MSK BIT(DBGC_APB2FZ_RTC_STOP_POS) + +#define DBGC_APB2FZ_WWDT_STOP_POS 9U +#define DBGC_APB2FZ_WWDT_STOP_MSK BIT(DBGC_APB2FZ_WWDT_STOP_POS) + +#define DBGC_APB2FZ_IWDT_STOP_POS 8U +#define DBGC_APB2FZ_IWDT_STOP_MSK BIT(DBGC_APB2FZ_IWDT_STOP_POS) + +#define DBGC_APB2FZ_LPTIM0_STOP_POS 0U +#define DBGC_APB2FZ_LPTIM0_STOP_MSK BIT(DBGC_APB2FZ_LPTIM0_STOP_POS) + +typedef struct +{ + __I uint32_t IDCODE; + __IO uint32_t CR; + __IO uint32_t APB1FZ; + __IO uint32_t APB2FZ; +} DBGC_TypeDef; + +/****************** Bit definition for DAC_CON register ************************/ + +#define DAC_CON_RCYCLSEL_POSS 20U +#define DAC_CON_RCYCLSEL_POSE 21U +#define DAC_CON_RCYCLSEL_MSK BITS(DAC_CON_RCYCLSEL_POSS,DAC_CON_RCYCLSEL_POSE) + +#define DAC_CON_PRES_POSS 16U +#define DAC_CON_PRES_POSE 18U +#define DAC_CON_PRES_MSK BITS(DAC_CON_PRES_POSS,DAC_CON_PRES_POSE) + +#define DAC_CON_CH0PRESRST_POS 7U +#define DAC_CON_CH0PRESRST_MSK BIT(DAC_CON_CH0PRESRST_POS) + +#define DAC_CON_OUTENPIS_POS 6U +#define DAC_CON_OUTENPIS_MSK BIT(DAC_CON_OUTENPIS_POS) + +#define DAC_CON_OUTMD_POSS 4U +#define DAC_CON_OUTMD_POSE 5U +#define DAC_CON_OUTMD_MSK BITS(DAC_CON_OUTMD_POSS,DAC_CON_OUTMD_POSE) + +#define DAC_CON_CONVMD_POSS 2U +#define DAC_CON_CONVMD_POSE 3U +#define DAC_CON_CONVMD_MSK BITS(DAC_CON_CONVMD_POSS,DAC_CON_CONVMD_POSE) + +#define DAC_CON_SINEMD_POS 1U +#define DAC_CON_SINEMD_MSK BIT(DAC_CON_SINEMD_POS) + +#define DAC_CON_DIFEN_POS 0U +#define DAC_CON_DIFEN_MSK BIT(DAC_CON_DIFEN_POS) + +/****************** Bit definition for DAC_STAT register ************************/ + +#define DAC_STAT_CH1BSY_POS 1U +#define DAC_STAT_CH1BSY_MSK BIT(DAC_STAT_CH1BSY_POS) + +#define DAC_STAT_CH0BSY_POS 0U +#define DAC_STAT_CH0BSY_MSK BIT(DAC_STAT_CH0BSY_POS) + +/****************** Bit definition for DAC_CH0CTRL register ************************/ + +#define DAC_CH0CTRL_PISSEL_POSS 4U +#define DAC_CH0CTRL_PISSEL_POSE 7U +#define DAC_CH0CTRL_PISSEL_MSK BITS(DAC_CH0CTRL_PISSEL_POSS,DAC_CH0CTRL_PISSEL_POSE) + +#define DAC_CH0CTRL_PISEN_POS 2U +#define DAC_CH0CTRL_PISEN_MSK BIT(DAC_CH0CTRL_PISEN_POS) + +#define DAC_CH0CTRL_RCYCLEN_POS 1U +#define DAC_CH0CTRL_RCYCLEN_MSK BIT(DAC_CH0CTRL_RCYCLEN_POS) + +#define DAC_CH0CTRL_EN_POS 0U +#define DAC_CH0CTRL_EN_MSK BIT(DAC_CH0CTRL_EN_POS) + +/****************** Bit definition for DAC_CH1CTRL register ************************/ + +#define DAC_CH1CTRL_PISSEL_POSS 4U +#define DAC_CH1CTRL_PISSEL_POSE 7U +#define DAC_CH1CTRL_PISSEL_MSK BITS(DAC_CH1CTRL_PISSEL_POSS,DAC_CH1CTRL_PISSEL_POSE) + +#define DAC_CH1CTRL_PISEN_POS 2U +#define DAC_CH1CTRL_PISEN_MSK BIT(DAC_CH1CTRL_PISEN_POS) + +#define DAC_CH1CTRL_RCYCLEN_POS 1U +#define DAC_CH1CTRL_RCYCLEN_MSK BIT(DAC_CH1CTRL_RCYCLEN_POS) + +#define DAC_CH1CTRL_EN_POS 0U +#define DAC_CH1CTRL_EN_MSK BIT(DAC_CH1CTRL_EN_POS) + +/****************** Bit definition for DAC_IES register ************************/ + +#define DAC_IES_CH1UDF_POS 5U +#define DAC_IES_CH1UDF_MSK BIT(DAC_IES_CH1UDF_POS) + +#define DAC_IES_CH0UDF_POS 4U +#define DAC_IES_CH0UDF_MSK BIT(DAC_IES_CH0UDF_POS) + +#define DAC_IES_CH1_POS 1U +#define DAC_IES_CH1_MSK BIT(DAC_IES_CH1_POS) + +#define DAC_IES_CH0_POS 0U +#define DAC_IES_CH0_MSK BIT(DAC_IES_CH0_POS) + +/****************** Bit definition for DAC_IEC register ************************/ + +#define DAC_IEC_CH1UDF_POS 5U +#define DAC_IEC_CH1UDF_MSK BIT(DAC_IEC_CH1UDF_POS) + +#define DAC_IEC_CH0UDF_POS 4U +#define DAC_IEC_CH0UDF_MSK BIT(DAC_IEC_CH0UDF_POS) + +#define DAC_IEC_CH1_POS 1U +#define DAC_IEC_CH1_MSK BIT(DAC_IEC_CH1_POS) + +#define DAC_IEC_CH0_POS 0U +#define DAC_IEC_CH0_MSK BIT(DAC_IEC_CH0_POS) + +/****************** Bit definition for DAC_IEV register ************************/ + +#define DAC_IEV_CH1UDF_POS 5U +#define DAC_IEV_CH1UDF_MSK BIT(DAC_IEV_CH1UDF_POS) + +#define DAC_IEV_CH0UDF_POS 4U +#define DAC_IEV_CH0UDF_MSK BIT(DAC_IEV_CH0UDF_POS) + +#define DAC_IEV_CH1_POS 1U +#define DAC_IEV_CH1_MSK BIT(DAC_IEV_CH1_POS) + +#define DAC_IEV_CH0_POS 0U +#define DAC_IEV_CH0_MSK BIT(DAC_IEV_CH0_POS) + +/****************** Bit definition for DAC_RIF register ************************/ + +#define DAC_RIF_CH1UDF_POS 5U +#define DAC_RIF_CH1UDF_MSK BIT(DAC_RIF_CH1UDF_POS) + +#define DAC_RIF_CH0UDF_POS 4U +#define DAC_RIF_CH0UDF_MSK BIT(DAC_RIF_CH0UDF_POS) + +#define DAC_RIF_CH1_POS 1U +#define DAC_RIF_CH1_MSK BIT(DAC_RIF_CH1_POS) + +#define DAC_RIF_CH0_POS 0U +#define DAC_RIF_CH0_MSK BIT(DAC_RIF_CH0_POS) + +/****************** Bit definition for DAC_IFM register ************************/ + +#define DAC_IFM_CH1UDF_POS 5U +#define DAC_IFM_CH1UDF_MSK BIT(DAC_IFM_CH1UDF_POS) + +#define DAC_IFM_CH0UDF_POS 4U +#define DAC_IFM_CH0UDF_MSK BIT(DAC_IFM_CH0UDF_POS) + +#define DAC_IFM_CH1_POS 1U +#define DAC_IFM_CH1_MSK BIT(DAC_IFM_CH1_POS) + +#define DAC_IFM_CH0_POS 0U +#define DAC_IFM_CH0_MSK BIT(DAC_IFM_CH0_POS) + +/****************** Bit definition for DAC_IFC register ************************/ + +#define DAC_IFC_CH1UDF_POS 5U +#define DAC_IFC_CH1UDF_MSK BIT(DAC_IFC_CH1UDF_POS) + +#define DAC_IFC_CH0UDF_POS 4U +#define DAC_IFC_CH0UDF_MSK BIT(DAC_IFC_CH0UDF_POS) + +#define DAC_IFC_CH1_POS 1U +#define DAC_IFC_CH1_MSK BIT(DAC_IFC_CH1_POS) + +#define DAC_IFC_CH0_POS 0U +#define DAC_IFC_CH0_MSK BIT(DAC_IFC_CH0_POS) + +/****************** Bit definition for DAC_CH0DATA register ************************/ + +#define DAC_CH0DATA_VAL_POSS 0U +#define DAC_CH0DATA_VAL_POSE 11U +#define DAC_CH0DATA_VAL_MSK BITS(DAC_CH0DATA_VAL_POSS,DAC_CH0DATA_VAL_POSE) + +/****************** Bit definition for DAC_CH1DATA register ************************/ + +#define DAC_CH1DATA_VAL_POSS 0U +#define DAC_CH1DATA_VAL_POSE 11U +#define DAC_CH1DATA_VAL_MSK BITS(DAC_CH1DATA_VAL_POSS,DAC_CH1DATA_VAL_POSE) + +/****************** Bit definition for DAC_COMBDATA register ************************/ + +#define DAC_COMBDATA_CH1VAL_POSS 16U +#define DAC_COMBDATA_CH1VAL_POSE 27U +#define DAC_COMBDATA_CH1VAL_MSK BITS(DAC_COMBDATA_CH1VAL_POSS,DAC_COMBDATA_CH1VAL_POSE) + +#define DAC_COMBDATA_CH0VAL_POSS 0U +#define DAC_COMBDATA_CH0VAL_POSE 11U +#define DAC_COMBDATA_CH0VAL_MSK BITS(DAC_COMBDATA_CH0VAL_POSS,DAC_COMBDATA_CH0VAL_POSE) + +/****************** Bit definition for DAC_CAL register ************************/ + +#define DAC_CAL_SELF_CALEN_POS 31U +#define DAC_CAL_SELF_CALEN_MSK BIT(DAC_CAL_SELF_CALEN_POS) + +typedef struct +{ + __IO uint32_t CON; + __I uint32_t STAT; + __IO uint32_t CH0CTRL; + __IO uint32_t CH1CTRL; + __O uint32_t IES; + __O uint32_t IEC; + __I uint32_t IEV; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t IFC; + __IO uint32_t CH0DATA; + __IO uint32_t CH1DATA; + __O uint32_t COMBDATA; + __IO uint32_t CAL; +} DAC_TypeDef; + + +/* Base addresses */ +#define SRAM_BASE (0x20000000UL) +#define APB1_BASE (0x40000000UL) +#define APB2_BASE (0x40040000UL) +#define AHB_BASE (0x40080000UL) +#define EBI_BASE (0x60000000UL) +#define EBI_R_BASE (0xA0000000UL) + + +/* APB1 peripherals Base Address */ +#define AD16C4T0_BASE (APB1_BASE + 0x0000) +#define AD16C4T1_BASE (APB1_BASE + 0x0400) +#define GP32C4T0_BASE (APB1_BASE + 0x0800) +#define GP32C4T1_BASE (APB1_BASE + 0x0C00) +#define BS16T0_BASE (APB1_BASE + 0x1000) +#define BS16T1_BASE (APB1_BASE + 0x1400) +#define GP16C4T0_BASE (APB1_BASE + 0x1800) +#define GP16C4T1_BASE (APB1_BASE + 0x1C00) +#define UART0_BASE (APB1_BASE + 0x4000) +#define UART1_BASE (APB1_BASE + 0x4400) +#define UART2_BASE (APB1_BASE + 0x4800) +#define UART3_BASE (APB1_BASE + 0x4C00) +#define UART4_BASE (APB1_BASE + 0x5000) +#define UART5_BASE (APB1_BASE + 0x5400) +#define SPI0_I2S0_BASE (APB1_BASE + 0x6000) +#define SPI1_I2S1_BASE (APB1_BASE + 0x6400) +#define SPI2_I2S2_BASE (APB1_BASE + 0x6800) +#define I2C0_BASE (APB1_BASE + 0x8000) +#define I2C1_BASE (APB1_BASE + 0x8400) +#define CAN0_BASE (APB1_BASE + 0xB000) +#define DMA0_BASE (APB1_BASE + 0xC000) +#define QSPI_BASE (APB1_BASE + 0xD400) + +/* APB2 peripherals Base Address */ +#define LPTIM0_BASE (APB2_BASE + 0x0000) +#define LPUART0_BASE (APB2_BASE + 0x1000) +#define ADC0_BASE (APB2_BASE + 0x2000) +#define ADC1_BASE (APB2_BASE + 0x2400) +#define ACMP0_BASE (APB2_BASE + 0x3000) +#define ACMP1_BASE (APB2_BASE + 0x3400) +#define ACMP2_BASE (APB2_BASE + 0x3800) +#define OPAMP_BASE (APB2_BASE + 0x4000) +#define DAC0_BASE (APB2_BASE + 0x5000) +#define WWDT_BASE (APB2_BASE + 0x6000) +#define IWDT_BASE (APB2_BASE + 0x6400) +#define LCD_BASE (APB2_BASE + 0x7000) +#define BKPC_BASE (APB2_BASE + 0x8000) +#define RTC_BASE (APB2_BASE + 0x8400) +#define TSENSE_BASE (APB2_BASE + 0x8800) +#define DBGC_BASE (APB2_BASE + 0xA000) + +/* AHB peripherals Base Address */ +#define SYSTEM_BASE (AHB_BASE + 0x0000) +#define CMU_BASE (AHB_BASE + 0x0400) +#define RMU_BASE (AHB_BASE + 0x0800) +#define PMU_BASE (AHB_BASE + 0x0C00) +#define MSC_BASE (AHB_BASE + 0x1000) +#define GPIOA_BASE (AHB_BASE + 0x4000) +#define GPIOB_BASE (AHB_BASE + 0x4040) +#define GPIOC_BASE (AHB_BASE + 0x4080) +#define GPIOD_BASE (AHB_BASE + 0x40C0) +#define GPIOE_BASE (AHB_BASE + 0x4100) +#define GPIOF_BASE (AHB_BASE + 0x4140) +#define GPIOG_BASE (AHB_BASE + 0x4180) +#define GPIOH_BASE (AHB_BASE + 0x41C0) +#define EXTI_BASE (AHB_BASE + 0x4300) +#define CRC_BASE (AHB_BASE + 0x5000) +#define CALC_BASE (AHB_BASE + 0x5400) +#define CRYPT_BASE (AHB_BASE + 0x5800) +#define TRNG_BASE (AHB_BASE + 0x5C00) +#define PIS_BASE (AHB_BASE + 0x6000) +#define USB0_BASE (AHB_BASE + 0x6400) +#define ECC_BASE (AHB_BASE + 0x6800) + +/* EBI Base Address */ +#define EBI_BANK1 (EBI_BASE) +#define EBI_BANK1_1 (EBI_BANK1) +#define EBI_BANK1_2 (EBI_BANK1 + 0x04000000UL) +#define EBI_BANK1_3 (EBI_BANK1 + 0x08000000UL) +#define EBI_BANK1_4 (EBI_BANK1 + 0x0C000000UL) +#define EBI_BANK2 (EBI_BASE + 0x10000000UL) +#define EBI_BANK3 (EBI_BASE + 0x20000000UL) +#define EBI_BANK1_R_BASE (EBI_R_BASE + 0x0000) +#define EBI_BANK1E_R_BASE (EBI_R_BASE + 0x0104) +#define EBI_BANK2_3_R_BASE (EBI_R_BASE + 0x0060) +#define EBI_BANK1_LCD_R_BASE (EBI_R_BASE + 0X0200) + +/* APB1 peripherals */ +#define AD16C4T0 ((TIMER_TypeDef *)AD16C4T0_BASE) +#define AD16C4T1 ((TIMER_TypeDef *)AD16C4T1_BASE) +#define GP32C4T0 ((TIMER_TypeDef *)GP32C4T0_BASE) +#define GP32C4T1 ((TIMER_TypeDef *)GP32C4T1_BASE) +#define BS16T0 ((TIMER_TypeDef *)BS16T0_BASE) +#define BS16T1 ((TIMER_TypeDef *)BS16T1_BASE) +#define GP16C4T0 ((TIMER_TypeDef *)GP16C4T0_BASE) +#define GP16C4T1 ((TIMER_TypeDef *)GP16C4T1_BASE) +#define UART0 ((UART_TypeDef *)UART0_BASE) +#define UART1 ((UART_TypeDef *)UART1_BASE) +#define UART2 ((UART_TypeDef *)UART2_BASE) +#define UART3 ((UART_TypeDef *)UART3_BASE) +#define UART4 ((UART_TypeDef *)UART4_BASE) +#define UART5 ((UART_TypeDef *)UART5_BASE) +#define SPI0 ((SPI_I2S_TypeDef *)SPI0_I2S0_BASE) +#define SPI1 ((SPI_I2S_TypeDef *)SPI1_I2S1_BASE) +#define SPI2 ((SPI_I2S_TypeDef *)SPI2_I2S2_BASE) +#define I2S0 ((SPI_I2S_TypeDef *)SPI0_I2S0_BASE) +#define I2S1 ((SPI_I2S_TypeDef *)SPI1_I2S1_BASE) +#define I2S2 ((SPI_I2S_TypeDef *)SPI2_I2S2_BASE) +#define I2C0 ((I2C_TypeDef *)I2C0_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define CAN0 ((CAN_TypeDef *)CAN0_BASE) +#define DMA0 ((DMA_TypeDef *)DMA0_BASE) +#define QSPI ((QSPI_TypeDef *)QSPI_BASE) + +/* APB2 peripherals */ +#define LPTIM0 ((LPTIM_TypeDef *)LPTIM0_BASE) +#define LPUART0 ((LPUART_TypeDef *)LPUART0_BASE) +#define ADC0 ((ADC_TypeDef *)ADC0_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) +#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) +#define ACMP2 ((ACMP_TypeDef *)ACMP2_BASE) +#define OPAMP ((OPAMP_TypeDef *)OPAMP_BASE) +#define DAC0 ((DAC_TypeDef *)DAC0_BASE) +#define WWDT ((WWDT_TypeDef *)WWDT_BASE) +#define IWDT ((IWDT_TypeDef *)IWDT_BASE) +#define LCD ((LCD_TypeDef *)LCD_BASE) +#define BKPC ((BKPC_TypeDef *)BKPC_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define TSENSE ((TSENSE_TypeDef *)TSENSE_BASE) +#define DBGC ((DBGC_TypeDef *)DBGC_BASE) + +/* AHB peripherals */ +#define SYSCFG ((SYSCFG_TypeDef *)SYSTEM_BASE) +#define CMU ((CMU_TypeDef *)CMU_BASE) +#define RMU ((RMU_TypeDef *)RMU_BASE) +#define PMU ((PMU_TypeDef *)PMU_BASE) +#define MSC ((MSC_TypeDef *)MSC_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *)GPIOH_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define CALC ((CALC_TypeDef *)CALC_BASE) +#define CRYPT ((CRYPT_TypeDef *)CRYPT_BASE) +#define TRNG ((TRNG_TypeDef *)TRNG_BASE) +#define PIS ((PIS_TypeDef *)PIS_BASE) +#define USB0 ((USB_TypeDef *)USB0_BASE) +#define ECC ((ECC_TypeDef *)ECC_BASE) + +/* EBI peripherals */ +#define EBI_Bank1 ((EBI_Bank1_TypeDef *)EBI_BANK1_R_BASE) +#define EBI_Bank1E ((EBI_Bank1E_TypeDef *)EBI_BANK1E_R_BASE) +#define EBI_Bank2_3 ((EBI_Bank2_3_TypeDef *)EBI_BANK2_3_R_BASE) +#define EBI_Bank1_LCD ((EBI_Bank1_LCD_TypeDef *)EBI_BANK1_LCD_R_BASE) + +#endif diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/iar/startup_es32f36xx.s b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/iar/startup_es32f36xx.s new file mode 100644 index 0000000000000000000000000000000000000000..5e43634bd947a736f929813ae55a49a797948869 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/iar/startup_es32f36xx.s @@ -0,0 +1,502 @@ +;******************************************************************************* +; file : startup_es32f36xx.s +; description: es32f36xx Device Startup File +; author : AE Team +; data : 04 Jul 2019 +; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. +;******************************************************************************* + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ;0, load top of stack + DCD RESET_Handler ;1, reset handler + DCD NMI_Handler ;2, nmi handler + DCD HardFault_Handler ;3, hard fault handler + DCD MemManage_Handler ;4, MPU Fault Handler + DCD BusFault_Handler ;5, Bus Fault Handler + DCD UsageFault_Handler ;6, Usage Fault Handler + DCD 0 ;7, Reserved + DCD 0 ;8, Reserved + DCD 0 ;9, Reserved + DCD 0 ;10, Reserved + DCD SVC_Handler ;11, svcall handler + DCD DebugMon_Handler ;12, Debug Monitor Handler + DCD 0 ;13, Reserved + DCD PendSV_Handler ;14, pendsv handler + DCD SysTick_Handler ;15, systick handler + DCD WWDG_Handler ;16, irq0 WWDG handler + DCD IWDG_Handler ;17, irq1 IWDG handler + DCD LVD_Handler ;18, irq2 LVD handler + DCD RTC_Handler ;19, irq3 RTC handler + DCD 0 ;20, irq4 Reserved + DCD 0 ;21, irq5 Reserved + DCD CMU_Handler ;22, irq6 CMU handler + DCD ADC0_Handler ;23, irq7 ADC0 handler + DCD CAN0_TX_Handler ;24, irq8 CAN0_TX handler + DCD CAN0_RX0_Handler ;25, irq9 CAN0_RX0 handler + DCD CAN0_RX1_Handler ;26, irq10 CAN0_RX1 handler + DCD CAN0_EXCEPTION_Handler ;27, irq11 CAN0_EXCEPTION handler + DCD AD16C4T0_BRK_Handler ;28, irq12 AD16C4T0_BRK handler + DCD AD16C4T0_UP_Handler ;29, irq13 AD16C4T0_UP handler + DCD AD16C4T0_TRIG_COM_Handler ;30, irq14 AD16C4T0_TRIG_COM handler + DCD AD16C4T0_CC_Handler ;31, irq15 AD16C4T0_CC handler + DCD AD16C4T1_BRK_Handler ;32, irq16 AD16C4T1_BRK handler + DCD AD16C4T1_UP_Handler ;33, irq17 AD16C4T1_UP handler + DCD AD16C4T1_TRIG_COM_Handler ;34, irq18 AD16C4T1_TRIG_COM handler + DCD AD16C4T1_CC_Handler ;35, irq19 AD16C4T1_CC handler + DCD GP32C4T0_Handler ;36, irq20 GP32C4T0 handler + DCD GP32C4T1_Handler ;37, irq21 GP32C4T1 handler + DCD BS16T0_Handler ;38, irq22 BS16T0 handler + DCD BS16T1_Handler ;39, irq23 BS16T1 handler + DCD GP16C4T0_Handler ;40, irq24 GP16C4T0 handler + DCD GP16C4T1_Handler ;41, irq25 GP16C4T1 handler + DCD 0 ;42, irq26 Reserved + DCD DAC0_CH0_Handler ;43, irq27 DAC0_CH0 handler + DCD I2C0_EV_Handler ;44, irq28 I2C0_EV handler + DCD I2C0_ERR_Handler ;45, irq29 I2C0_ERR handler + DCD I2C1_EV_Handler ;46, irq30 I2C1_EV handler + DCD I2C1_ERR_Handler ;47, irq31 I2C1_ERR handler + DCD SPI0_I2S0_Handler ;48, irq32 SPI0_I2S0 handler + DCD SPI1_I2S1_Handler ;49, irq33 SPI1_I2S1 handler + DCD UART0_Handler ;50, irq34 UART0 handler + DCD UART1_Handler ;51, irq35 UART1 handler + DCD UART2_Handler ;52, irq36 UART2 handler + DCD UART3_Handler ;53, irq37 UART3 handler + DCD UART4_Handler ;54, irq38 UART4 handler + DCD UART5_Handler ;55, irq39 UART5 handler + DCD 0 ;56, irq40 Reserved + DCD 0 ;57, irq41 Reserved + DCD CRYPT_Handler ;58, irq42 CRYPT handler + DCD ACMP0_Handler ;59, irq43 ACMP0 handler + DCD ACMP1_Handler ;60, irq44 ACMP1 handler + DCD SPI2_I2S2_Handler ;61, irq45 SPI2_I2S2 handler + DCD 0 ;62, irq46 Reserved + DCD EBI_Handler ;63, irq47 EBI handler + DCD TRNG_Handler ;64, irq48 TRNG handler + DCD TSENSE_Handler ;65, irq49 TSENSE handler + DCD EXTI0_Handler ;66, irq50 EXTI0 handler + DCD EXTI1_Handler ;67, irq51 EXTI1 handler + DCD EXTI2_Handler ;68, irq52 EXTI2 handler + DCD EXTI3_Handler ;69, irq53 EXTI3 handler + DCD EXTI4_Handler ;70, irq54 EXTI4 handler + DCD EXTI5_Handler ;71, irq55 EXTI5 handler + DCD EXTI6_Handler ;72, irq56 EXTI6 handler + DCD EXTI7_Handler ;73, irq57 EXTI7 handler + DCD EXTI8_Handler ;74, irq58 EXTI8 handler + DCD EXTI9_Handler ;75, irq59 EXTI9 handler + DCD EXTI10_Handler ;76, irq60 EXTI10 handler + DCD EXTI11_Handler ;77, irq61 EXTI11 handler + DCD EXTI12_Handler ;78, irq62 EXTI12 handler + DCD EXTI13_Handler ;79, irq63 EXTI13 handler + DCD EXTI14_Handler ;80, irq64 EXTI14 handler + DCD EXTI15_Handler ;81, irq65 EXTI15 handler + DCD DMA_Handler ;82, irq66 DMA handler + DCD ADC1_Handler ;83, irq67 ADC1 handler + DCD DAC0_CH1_Handler ;84, irq68 DAC0_CH1 handler + DCD QSPI_Handler ;85, irq69 QSPI handler + DCD USB_INT_Handler ;86, irq70 USB_INT handler + DCD USB_DMA_Handler ;87, irq71 USB_DMA handler + DCD ACMP2_Handler ;88, irq72 ACMP2 handler + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK RESET_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +RESET_Handler + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_Handler + B WWDG_Handler + + PUBWEAK IWDG_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IWDG_Handler + B IWDG_Handler + + PUBWEAK LVD_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_Handler + B LVD_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Handler + B RTC_Handler + + PUBWEAK CMU_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CMU_Handler + B CMU_Handler + + PUBWEAK ADC0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC0_Handler + B ADC0_Handler + + PUBWEAK CAN0_TX_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_TX_Handler + B CAN0_TX_Handler + + PUBWEAK CAN0_RX0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX0_Handler + B CAN0_RX0_Handler + + PUBWEAK CAN0_RX1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX1_Handler + B CAN0_RX1_Handler + + PUBWEAK CAN0_EXCEPTION_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_EXCEPTION_Handler + B CAN0_EXCEPTION_Handler + + PUBWEAK AD16C4T0_BRK_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T0_BRK_Handler + B AD16C4T0_BRK_Handler + + PUBWEAK AD16C4T0_UP_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T0_UP_Handler + B AD16C4T0_UP_Handler + + PUBWEAK AD16C4T0_TRIG_COM_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T0_TRIG_COM_Handler + B AD16C4T0_TRIG_COM_Handler + + PUBWEAK AD16C4T0_CC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T0_CC_Handler + B AD16C4T0_CC_Handler + + PUBWEAK AD16C4T1_BRK_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T1_BRK_Handler + B AD16C4T1_BRK_Handler + + PUBWEAK AD16C4T1_UP_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T1_UP_Handler + B AD16C4T1_UP_Handler + + PUBWEAK AD16C4T1_TRIG_COM_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T1_TRIG_COM_Handler + B AD16C4T1_TRIG_COM_Handler + + PUBWEAK AD16C4T1_CC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T1_CC_Handler + B AD16C4T1_CC_Handler + + PUBWEAK GP32C4T0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +GP32C4T0_Handler + B GP32C4T0_Handler + + PUBWEAK GP32C4T1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +GP32C4T1_Handler + B GP32C4T1_Handler + + PUBWEAK BS16T0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BS16T0_Handler + B BS16T0_Handler + + PUBWEAK BS16T1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BS16T1_Handler + B BS16T1_Handler + + PUBWEAK GP16C4T0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C4T0_Handler + B GP16C4T0_Handler + + PUBWEAK GP16C4T1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C4T1_Handler + B GP16C4T1_Handler + + PUBWEAK DAC0_CH0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DAC0_CH0_Handler + B DAC0_CH0_Handler + + PUBWEAK I2C0_EV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_Handler + B I2C0_EV_Handler + + PUBWEAK I2C0_ERR_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ERR_Handler + B I2C0_ERR_Handler + + PUBWEAK I2C1_EV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_Handler + B I2C1_EV_Handler + + PUBWEAK I2C1_ERR_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ERR_Handler + B I2C1_ERR_Handler + + PUBWEAK SPI0_I2S0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_I2S0_Handler + B SPI0_I2S0_Handler + + PUBWEAK SPI1_I2S1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_I2S1_Handler + B SPI1_I2S1_Handler + + PUBWEAK UART0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_Handler + B UART0_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_Handler + B UART1_Handler + + PUBWEAK UART2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_Handler + B UART2_Handler + + PUBWEAK UART3_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_Handler + B UART3_Handler + + PUBWEAK UART4_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_Handler + B UART4_Handler + + PUBWEAK UART5_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_Handler + B UART5_Handler + + PUBWEAK CRYPT_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYPT_Handler + B CRYPT_Handler + + PUBWEAK ACMP0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ACMP0_Handler + B ACMP0_Handler + + PUBWEAK ACMP1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ACMP1_Handler + B ACMP1_Handler + + PUBWEAK SPI2_I2S2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_I2S2_Handler + B SPI2_I2S2_Handler + + PUBWEAK EBI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EBI_Handler + B EBI_Handler + + PUBWEAK TRNG_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TRNG_Handler + B TRNG_Handler + + PUBWEAK TSENSE_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TSENSE_Handler + B TSENSE_Handler + + PUBWEAK EXTI0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_Handler + B EXTI0_Handler + + PUBWEAK EXTI1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_Handler + B EXTI1_Handler + + PUBWEAK EXTI2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_Handler + B EXTI2_Handler + + PUBWEAK EXTI3_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_Handler + B EXTI3_Handler + + PUBWEAK EXTI4_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_Handler + B EXTI4_Handler + + PUBWEAK EXTI5_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_Handler + B EXTI5_Handler + + PUBWEAK EXTI6_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI6_Handler + B EXTI6_Handler + + PUBWEAK EXTI7_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI7_Handler + B EXTI7_Handler + + PUBWEAK EXTI8_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI8_Handler + B EXTI8_Handler + + PUBWEAK EXTI9_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_Handler + B EXTI9_Handler + + PUBWEAK EXTI10_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_Handler + B EXTI10_Handler + + PUBWEAK EXTI11_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI11_Handler + B EXTI11_Handler + + PUBWEAK EXTI12_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI12_Handler + B EXTI12_Handler + + PUBWEAK EXTI13_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI13_Handler + B EXTI13_Handler + + PUBWEAK EXTI14_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI14_Handler + B EXTI14_Handler + + PUBWEAK EXTI15_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_Handler + B EXTI15_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_Handler + B DMA_Handler + + PUBWEAK ADC1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_Handler + B ADC1_Handler + + PUBWEAK DAC0_CH1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DAC0_CH1_Handler + B DAC0_CH1_Handler + + PUBWEAK QSPI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +QSPI_Handler + B QSPI_Handler + + PUBWEAK USB_INT_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_INT_Handler + B USB_INT_Handler + + PUBWEAK USB_DMA_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_DMA_Handler + B USB_DMA_Handler + + PUBWEAK ACMP2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ACMP2_Handler + B ACMP2_Handler + + END diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s new file mode 100644 index 0000000000000000000000000000000000000000..362c8483fe3de6d21c9d101bf225258a74bfd4b4 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s @@ -0,0 +1,619 @@ +;******************************************************************************* +; file : startup_es32f36xx.s +; description: es32f36xx Device Startup File +; author : AE Team +; data : 23 Jan 2019 +; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. +;******************************************************************************* + +;Stack Configuration------------------------------------------------------------ +Stack_Size EQU 0x00000800 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp +;------------------------------------------------------------------------------- + +;Heap Configuration------------------------------------------------------------- +Heap_Size EQU 0x00000000 + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit +;------------------------------------------------------------------------------- + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset------------------------------------- + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ;0, load top of stack + DCD RESET_Handler ;1, reset handler + DCD NMI_Handler ;2, nmi handler + DCD HardFault_Handler ;3, hard fault handler + DCD MemManage_Handler ;4, MPU Fault Handler + DCD BusFault_Handler ;5, Bus Fault Handler + DCD UsageFault_Handler ;6, Usage Fault Handler + DCD 0 ;7, Reserved + DCD 0 ;8, Reserved + DCD 0 ;9, Reserved + DCD 0 ;10, Reserved + DCD SVC_Handler ;11, svcall handler + DCD DebugMon_Handler ;12, Debug Monitor Handler + DCD 0 ;13, Reserved + DCD PendSV_Handler ;14, pendsv handler + DCD SysTick_Handler ;15, systick handler + DCD WWDG_Handler ;16, irq0 WWDG handler + DCD IWDG_Handler ;17, irq1 IWDG handler + DCD LVD_Handler ;18, irq2 LVD handler + DCD RTC_Handler ;19, irq3 RTC handler + DCD 0 ;20, irq4 Reserved + DCD 0 ;21, irq5 Reserved + DCD CMU_Handler ;22, irq6 CMU handler + DCD ADC0_Handler ;23, irq7 ADC0 handler + DCD CAN0_TX_Handler ;24, irq8 CAN0_TX handler + DCD CAN0_RX0_Handler ;25, irq9 CAN0_RX0 handler + DCD CAN0_RX1_Handler ;26, irq10 CAN0_RX1 handler + DCD CAN0_EXCEPTION_Handler ;27, irq11 CAN0_EXCEPTION handler + DCD AD16C4T0_BRK_Handler ;28, irq12 AD16C4T0_BRK handler + DCD AD16C4T0_UP_Handler ;29, irq13 AD16C4T0_UP handler + DCD AD16C4T0_TRIG_COM_Handler ;30, irq14 AD16C4T0_TRIG_COM handler + DCD AD16C4T0_CC_Handler ;31, irq15 AD16C4T0_CC handler + DCD AD16C4T1_BRK_Handler ;32, irq16 AD16C4T1_BRK handler + DCD AD16C4T1_UP_Handler ;33, irq17 AD16C4T1_UP handler + DCD AD16C4T1_TRIG_COM_Handler ;34, irq18 AD16C4T1_TRIG_COM handler + DCD AD16C4T1_CC_Handler ;35, irq19 AD16C4T1_CC handler + DCD GP32C4T0_Handler ;36, irq20 GP32C4T0 handler + DCD GP32C4T1_Handler ;37, irq21 GP32C4T1 handler + DCD BS16T0_Handler ;38, irq22 BS16T0 handler + DCD BS16T1_Handler ;39, irq23 BS16T1 handler + DCD GP16C4T0_Handler ;40, irq24 GP16C4T0 handler + DCD GP16C4T1_Handler ;41, irq25 GP16C4T1 handler + DCD 0 ;42, irq26 Reserved + DCD DAC0_CH0_Handler ;43, irq27 DAC0_CH0 handler + DCD I2C0_EV_Handler ;44, irq28 I2C0_EV handler + DCD I2C0_ERR_Handler ;45, irq29 I2C0_ERR handler + DCD I2C1_EV_Handler ;46, irq30 I2C1_EV handler + DCD I2C1_ERR_Handler ;47, irq31 I2C1_ERR handler + DCD SPI0_I2S0_Handler ;48, irq32 SPI0_I2S0 handler + DCD SPI1_I2S1_Handler ;49, irq33 SPI1_I2S1 handler + DCD UART0_Handler ;50, irq34 UART0 handler + DCD UART1_Handler ;51, irq35 UART1 handler + DCD UART2_Handler ;52, irq36 UART2 handler + DCD UART3_Handler ;53, irq37 UART3 handler + DCD UART4_Handler ;54, irq38 UART4 handler + DCD UART5_Handler ;55, irq39 UART5 handler + DCD 0 ;56, irq40 Reserved + DCD 0 ;57, irq41 Reserved + DCD CRYPT_Handler ;58, irq42 CRYPT handler + DCD ACMP0_Handler ;59, irq43 ACMP0 handler + DCD ACMP1_Handler ;60, irq44 ACMP1 handler + DCD SPI2_I2S2_Handler ;61, irq45 SPI2_I2S2 handler + DCD 0 ;62, irq46 Reserved + DCD EBI_Handler ;63, irq47 EBI handler + DCD TRNG_Handler ;64, irq48 TRNG handler + DCD TSENSE_Handler ;65, irq49 TSENSE handler + DCD EXTI0_Handler ;66, irq50 EXTI0 handler + DCD EXTI1_Handler ;67, irq51 EXTI1 handler + DCD EXTI2_Handler ;68, irq52 EXTI2 handler + DCD EXTI3_Handler ;69, irq53 EXTI3 handler + DCD EXTI4_Handler ;70, irq54 EXTI4 handler + DCD EXTI5_Handler ;71, irq55 EXTI5 handler + DCD EXTI6_Handler ;72, irq56 EXTI6 handler + DCD EXTI7_Handler ;73, irq57 EXTI7 handler + DCD EXTI8_Handler ;74, irq58 EXTI8 handler + DCD EXTI9_Handler ;75, irq59 EXTI9 handler + DCD EXTI10_Handler ;76, irq60 EXTI10 handler + DCD EXTI11_Handler ;77, irq61 EXTI11 handler + DCD EXTI12_Handler ;78, irq62 EXTI12 handler + DCD EXTI13_Handler ;79, irq63 EXTI13 handler + DCD EXTI14_Handler ;80, irq64 EXTI14 handler + DCD EXTI15_Handler ;81, irq65 EXTI15 handler + DCD DMA_Handler ;82, irq66 DMA handler + DCD ADC1_Handler ;83, irq67 ADC1 handler + DCD DAC0_CH1_Handler ;84, irq68 DAC0_CH1 handler + DCD QSPI_Handler ;85, irq69 QSPI handler + DCD USB_INT_Handler ;86, irq70 USB_INT handler + DCD USB_DMA_Handler ;87, irq71 USB_DMA handler + DCD ACMP2_Handler ;88, irq72 ACMP2 handler + +;------------------------------------------------------------------------------- + AREA INT, CODE, READONLY ;code begin + +;Reset Handler---------------------------------------------- +RESET_Handler PROC + EXPORT RESET_Handler [WEAK] + IMPORT __main + LDR R0, =__main + BX R0 + NOP + ALIGN + ENDP + +;system int------------------------------------------------- +NMI_Handler PROC ;int 2 + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler \ + PROC ;int3 + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler \ + PROC ;int4 + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler \ + PROC ;int5 + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler \ + PROC ;int6 + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler \ + PROC ;int11 + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler \ + PROC ;int12 + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler \ + PROC ;int14 + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler \ + PROC ;int15 + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +;peripheral module int ----------------------------------------------- +WWDG_Handler \ + PROC ;int16 + EXPORT WWDG_Handler [WEAK] + B . + ENDP + +IWDG_Handler \ + PROC ;int17 + EXPORT IWDG_Handler [WEAK] + B . + ENDP + +LVD_Handler \ + PROC ;int18 + EXPORT LVD_Handler [WEAK] + B . + ENDP + +RTC_Handler \ + PROC ;int19 + EXPORT RTC_Handler [WEAK] + B . + ENDP + +FLASH_Handler \ + PROC ;int21 + EXPORT FLASH_Handler [WEAK] + B . + ENDP + +CMU_Handler \ + PROC ;int22 + EXPORT CMU_Handler [WEAK] + B . + ENDP + +ADC0_Handler \ + PROC ;int23 + EXPORT ADC0_Handler [WEAK] + B . + ENDP + +CAN0_TX_Handler \ + PROC ;int24 + EXPORT CAN0_TX_Handler [WEAK] + B . + ENDP + +CAN0_RX0_Handler \ + PROC ;int25 + EXPORT CAN0_RX0_Handler [WEAK] + B . + ENDP + +CAN0_RX1_Handler \ + PROC ;int26 + EXPORT CAN0_RX1_Handler [WEAK] + B . + ENDP + +CAN0_EXCEPTION_Handler \ + PROC ;int27 + EXPORT CAN0_EXCEPTION_Handler [WEAK] + B . + ENDP + +AD16C4T0_BRK_Handler \ + PROC ;int28 + EXPORT AD16C4T0_BRK_Handler [WEAK] + B . + ENDP + +AD16C4T0_UP_Handler \ + PROC ;int29 + EXPORT AD16C4T0_UP_Handler [WEAK] + B . + ENDP + +AD16C4T0_TRIG_COM_Handler \ + PROC ;int30 + EXPORT AD16C4T0_TRIG_COM_Handler [WEAK] + B . + ENDP + +AD16C4T0_CC_Handler \ + PROC ;int31 + EXPORT AD16C4T0_CC_Handler [WEAK] + B . + ENDP + +AD16C4T1_BRK_Handler \ + PROC ;int32 + EXPORT AD16C4T1_BRK_Handler [WEAK] + B . + ENDP + +AD16C4T1_UP_Handler \ + PROC ;int33 + EXPORT AD16C4T1_UP_Handler [WEAK] + B . + ENDP + +AD16C4T1_TRIG_COM_Handler \ + PROC ;int34 + EXPORT AD16C4T1_TRIG_COM_Handler [WEAK] + B . + ENDP + +AD16C4T1_CC_Handler \ + PROC ;int35 + EXPORT AD16C4T1_CC_Handler [WEAK] + B . + ENDP + +GP32C4T0_Handler \ + PROC ;int36 + EXPORT GP32C4T0_Handler [WEAK] + B . + ENDP + +GP32C4T1_Handler \ + PROC ;int37 + EXPORT GP32C4T1_Handler [WEAK] + B . + ENDP + +BS16T0_Handler \ + PROC ;int38 + EXPORT BS16T0_Handler [WEAK] + B . + ENDP + +BS16T1_Handler \ + PROC ;int39 + EXPORT BS16T1_Handler [WEAK] + B . + ENDP + +GP16C4T0_Handler \ + PROC ;int40 + EXPORT GP16C4T0_Handler [WEAK] + B . + ENDP + +GP16C4T1_Handler \ + PROC ;int41 + EXPORT GP16C4T1_Handler [WEAK] + B . + ENDP + +DAC0_CH0_Handler \ + PROC ;int43 + EXPORT DAC0_CH0_Handler [WEAK] + B . + ENDP + +I2C0_EV_Handler \ + PROC ;int44 + EXPORT I2C0_EV_Handler [WEAK] + B . + ENDP + +I2C0_ERR_Handler \ + PROC ;int45 + EXPORT I2C0_ERR_Handler [WEAK] + B . + ENDP + +I2C1_EV_Handler \ + PROC ;int46 + EXPORT I2C1_EV_Handler [WEAK] + B . + ENDP + +I2C1_ERR_Handler \ + PROC ;int47 + EXPORT I2C1_ERR_Handler [WEAK] + B . + ENDP + +SPI0_I2S0_Handler \ + PROC ;int48 + EXPORT SPI0_I2S0_Handler [WEAK] + B . + ENDP + +SPI1_I2S1_Handler \ + PROC ;int49 + EXPORT SPI1_I2S1_Handler [WEAK] + B . + ENDP + +UART0_Handler \ + PROC ;int50 + EXPORT UART0_Handler [WEAK] + B . + ENDP + +UART1_Handler \ + PROC ;int51 + EXPORT UART1_Handler [WEAK] + B . + ENDP + +UART2_Handler \ + PROC ;int52 + EXPORT UART2_Handler [WEAK] + B . + ENDP + +UART3_Handler \ + PROC ;int53 + EXPORT UART3_Handler [WEAK] + B . + ENDP + +UART4_Handler \ + PROC ;int54 + EXPORT UART4_Handler [WEAK] + B . + ENDP + +UART5_Handler \ + PROC ;int55 + EXPORT UART5_Handler [WEAK] + B . + ENDP + +CRYPT_Handler \ + PROC ;int58 + EXPORT CRYPT_Handler [WEAK] + B . + ENDP + +ACMP0_Handler \ + PROC ;int59 + EXPORT ACMP0_Handler [WEAK] + B . + ENDP + +ACMP1_Handler \ + PROC ;int60 + EXPORT ACMP1_Handler [WEAK] + B . + ENDP + +SPI2_I2S2_Handler \ + PROC ;int61 + EXPORT SPI2_I2S2_Handler [WEAK] + B . + ENDP + +EBI_Handler \ + PROC ;int63 + EXPORT EBI_Handler [WEAK] + B . + ENDP + +TRNG_Handler \ + PROC ;int64 + EXPORT TRNG_Handler [WEAK] + B . + ENDP + +TSENSE_Handler \ + PROC ;int65 + EXPORT TSENSE_Handler [WEAK] + B . + ENDP + +EXTI0_Handler \ + PROC ;int66 + EXPORT EXTI0_Handler [WEAK] + B . + ENDP + +EXTI1_Handler \ + PROC ;int67 + EXPORT EXTI1_Handler [WEAK] + B . + ENDP + +EXTI2_Handler \ + PROC ;int68 + EXPORT EXTI2_Handler [WEAK] + B . + ENDP + +EXTI3_Handler \ + PROC ;int69 + EXPORT EXTI3_Handler [WEAK] + B . + ENDP + +EXTI4_Handler \ + PROC ;int70 + EXPORT EXTI4_Handler [WEAK] + B . + ENDP + +EXTI5_Handler \ + PROC ;int71 + EXPORT EXTI5_Handler [WEAK] + B . + ENDP + +EXTI6_Handler \ + PROC ;int72 + EXPORT EXTI6_Handler [WEAK] + B . + ENDP + +EXTI7_Handler \ + PROC ;int73 + EXPORT EXTI7_Handler [WEAK] + B . + ENDP + +EXTI8_Handler \ + PROC ;int74 + EXPORT EXTI8_Handler [WEAK] + B . + ENDP + +EXTI9_Handler \ + PROC ;int75 + EXPORT EXTI9_Handler [WEAK] + B . + ENDP + +EXTI10_Handler \ + PROC ;int76 + EXPORT EXTI10_Handler [WEAK] + B . + ENDP + +EXTI11_Handler \ + PROC ;int77 + EXPORT EXTI11_Handler [WEAK] + B . + ENDP + +EXTI12_Handler \ + PROC ;int78 + EXPORT EXTI12_Handler [WEAK] + B . + ENDP + +EXTI13_Handler \ + PROC ;int79 + EXPORT EXTI13_Handler [WEAK] + B . + ENDP + +EXTI14_Handler \ + PROC ;int80 + EXPORT EXTI14_Handler [WEAK] + B . + ENDP + +EXTI15_Handler \ + PROC ;int81 + EXPORT EXTI15_Handler [WEAK] + B . + ENDP + +DMA_Handler \ + PROC ;int82 + EXPORT DMA_Handler [WEAK] + B . + ENDP + +ADC1_Handler \ + PROC ;int83 + EXPORT ADC1_Handler [WEAK] + B . + ENDP + +DAC0_CH1_Handler \ + PROC ;int84 + EXPORT DAC0_CH1_Handler [WEAK] + B . + ENDP + +QSPI_Handler \ + PROC ;int85 + EXPORT QSPI_Handler [WEAK] + B . + ENDP + +USB_INT_Handler \ + PROC ;int86 + EXPORT USB_INT_Handler [WEAK] + B . + ENDP + +USB_DMA_Handler \ + PROC ;int87 + EXPORT USB_DMA_Handler [WEAK] + B . + ENDP + +ACMP2_Handler \ + PROC ;int88 + EXPORT ACMP2_Handler [WEAK] + B . + ENDP + +; User Initial Stack & Heap----------------------------------------------------- + ALIGN + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/System/system_es32f36xx.c b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/System/system_es32f36xx.c new file mode 100644 index 0000000000000000000000000000000000000000..5e9a57c41bd1487ef3efb0d5b771972d145fa479 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/System/system_es32f36xx.c @@ -0,0 +1,28 @@ +/** + ********************************************************************************* + * + * @file system_es32f3xx.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer + * + * @version V1.0 + * @date 24 Dec 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "utils.h" + + +/** + * @brief Configuring system clock before startup. + * @note This function must be used after reset. + * @retval None + */ +void system_init (void) +{ + /* do nothing */ +} \ No newline at end of file diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Include/arm_common_tables.h b/bsp/essemi/es32f369x/libraries/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000000000000000000000000000000000000..dfea7460e9a79e5b20670d947e6a52a894b29801 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Include/arm_const_structs.h b/bsp/essemi/es32f369x/libraries/CMSIS/Include/arm_const_structs.h new file mode 100644 index 0000000000000000000000000000000000000000..80a3e8bbe72b8c54f34a0f40aa1e01f2bfb3308f --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Include/arm_math.h b/bsp/essemi/es32f369x/libraries/CMSIS/Include/arm_math.h new file mode 100644 index 0000000000000000000000000000000000000000..ea9dd26aa8110a0a90babc7b297c5bc6d5eb4216 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Include/arm_math.h @@ -0,0 +1,7157 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP LibraryU + * @version V1.5.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library + * on Armv8-M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * + *
    + * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
    + * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 Arm Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
    + *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
    + * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
    + *     pData[i*numCols + j]
+ *
    + * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
    + * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
    + * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
    + *     ARM_MATH_SIZE_MISMATCH
+ *
    + * Otherwise the functions return + * 
    + *     ARM_MATH_SUCCESS
+ *
    + * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
    + *     ARM_MATH_MATRIX_CHECK
+ *
    + * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
    +   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
    + * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
    +   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
    + * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
    +   *      x1 = x0 - f(x0)/f'(x0)
+   *
    + * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
    +   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
    + */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
    +   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
    + * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
    +   *     XF = floor(x)
+   *     YF = floor(y)
+   *
    + * \par + * The interpolated output point is computed as: + * 
    +   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
    + * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_armcc.h b/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000000000000000000000000000000000..093d35b9e5cfe6477ce7a71c842af5f35dabf5c8 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,870 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_armclang.h b/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000000000000000000000000000000000000..5c4c20e8777bf1177e03acbb6fca4b80f9b61362 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1877 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_compiler.h b/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000000000000000000000000000000000000..94212eb87a94d11bb8346c6fff99d5fbf838c0ac --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_gcc.h b/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..5d0f07e8accbfdd00dbace8fdf02f98825cfb6f9 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2088 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.3 + * @date 16. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_iccarm.h b/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000000000000000000000000000000000000..edcaee3d4ab1e4026b53858e06930dd53d71f038 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,913 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.5 + * @date 10. January 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_version.h b/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000000000000000000000000000000000000..660f612aa31fe2a71cc786af5cac407e41fdd144 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Include/core_armv8mbl.h b/bsp/essemi/es32f369x/libraries/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000000000000000000000000000000000000..47a39893aced51da4790b504c92a3bde53204a19 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1896 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Include/core_armv8mml.h b/bsp/essemi/es32f369x/libraries/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000000000000000000000000000000000000..0951a1f78126b48bf8279a71ecdafbbe4fc50f11 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2960 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Include/core_cm3.h b/bsp/essemi/es32f369x/libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000000000000000000000000000000000..a2c0d0805729739413b170af6a47410f89d854de --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1933 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Include/mpu_armv7.h b/bsp/essemi/es32f369x/libraries/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000000000000000000000000000000000000..aa180c9e5967841134fa5b37a488fa3e5e3f2f2f --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,197 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) + +#define ARM_MPU_AP_NONE 0U +#define ARM_MPU_AP_PRIV 1U +#define ARM_MPU_AP_URO 2U +#define ARM_MPU_AP_FULL 3U +#define ARM_MPU_AP_PRO 5U +#define ARM_MPU_AP_RO 6U + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (MPU_RASR_ENABLE_Msk)) + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Include/mpu_armv8.h b/bsp/essemi/es32f369x/libraries/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000000000000000000000000000000000000..0ccfc74fe5b640ec5703495996872a5b6bcf1270 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Pos) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/essemi/es32f369x/libraries/CMSIS/Include/tz_context.h b/bsp/essemi/es32f369x/libraries/CMSIS/Include/tz_context.h new file mode 100644 index 0000000000000000000000000000000000000000..0d09749f3a5066f0e061783a1e67972b72ab61a7 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/EASTSOFT_ES32F36xx_ALD.chm b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/EASTSOFT_ES32F36xx_ALD.chm new file mode 100644 index 0000000000000000000000000000000000000000..2e2e54d9f7400d51fabd7152af218e5d81371e2c Binary files /dev/null and b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/EASTSOFT_ES32F36xx_ALD.chm differ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h new file mode 100644 index 0000000000000000000000000000000000000000..ab1140e97b5e5d2f75907ce20a646adaed8075a9 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_acmp.h @@ -0,0 +1,301 @@ +/** + ********************************************************************************* + * + * @file ald_acmp.h + * @brief Header file of ACMP module driver. + * + * @version V1.0 + * @date 26 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_ACMP_H__ +#define __ALD_ACMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup ACMP + * @{ + */ + +/** @defgroup ACMP_Public_Types ACMP Public Types + * @{ + */ + +/** + * @brief ACMP interrupt + */ +typedef enum { + ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */ + ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */ +} acmp_it_t; + +/** + * @brief ACMP interrupt flag + */ +typedef enum { + ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */ + ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */ +} acmp_flag_t; + +/** + * @brief ACMP status flag + */ +typedef enum { + ACMP_STATUS_ACT = (1U << 0), /**< Edge status flag */ + ACMP_STATUS_OUT = (1U << 1), /**< Warm up status flag */ +} acmp_status_t; + +/** + * @brief ACMP positive input + */ +typedef enum { + ACMP_POS_CH0 = 0x0, /**< Channel 0 as positive input */ + ACMP_POS_CH1 = 0x1, /**< Channel 1 as positive input */ + ACMP_POS_CH2 = 0x2, /**< Channel 2 as positive input */ + ACMP_POS_CH3 = 0x3, /**< Channel 3 as positive input */ + ACMP_POS_CH4 = 0x4, /**< Channel 4 as positive input */ + ACMP_POS_CH5 = 0x5, /**< Channel 5 as positive input */ + ACMP_POS_CH6 = 0x6, /**< Channel 6 as positive input */ + ACMP_POS_CH7 = 0x7, /**< Channel 7 as positive input */ +} acmp_pos_input_t; + +/** + * @brief ACMP negative input + */ +typedef enum { + ACMP_NEG_CH0 = 0x0, /**< Channel 0 as negative input */ + ACMP_NEG_CH1 = 0x1, /**< Channel 1 as negative input */ + ACMP_NEG_CH2 = 0x2, /**< Channel 2 as negative input */ + ACMP_NEG_CH3 = 0x3, /**< Channel 3 as negative input */ + ACMP_NEG_CH4 = 0x4, /**< Channel 4 as negative input */ + ACMP_NEG_CH5 = 0x5, /**< Channel 5 as negative input */ + ACMP_NEG_CH6 = 0x6, /**< Channel 6 as negative input */ + ACMP_NEG_CH7 = 0x7, /**< Channel 7 as negative input */ + ACMP_NEG_1V25 = 0x8, /**< 1.25v as negative input */ + ACMP_NEG_2V5 = 0x9, /**< 2.5v as negative input */ + ACMP_NEG_VDD = 0xA, /**< VDD as negative input */ +} acmp_neg_input_t; + +/** + * @brief ACMP mode + */ +typedef enum { + ACMP_ULTRA_LOW_POWER = 0x0, /**< Ultra low power mode */ + ACMP_LOW_POWER = 0x1, /**< Low power mode */ + ACMP_MIDDLE_POWER = 0x2, /**< Middle power mode */ + ACMP_HIGH_POWER = 0x3, /**< High power mode */ +} acmp_mode_t; + +/** + * @brief ACMP warm-up time + */ +typedef enum { + ACMP_4_PCLK = 0x0, /**< 4 hfperclk cycles */ + ACMP_8_PCLK = 0x1, /**< 4 hfperclk cycles */ + ACMP_16_PCLK = 0x2, /**< 4 hfperclk cycles */ + ACMP_32_PCLK = 0x3, /**< 4 hfperclk cycles */ + ACMP_64_PCLK = 0x4, /**< 4 hfperclk cycles */ + ACMP_128_PCLK = 0x5, /**< 4 hfperclk cycles */ + ACMP_256_PCLK = 0x6, /**< 4 hfperclk cycles */ + ACMP_512_PCLK = 0x7, /**< 4 hfperclk cycles */ +} acmp_warm_time_t; + +/** + * @brief ACMP hysteresis level + */ +typedef enum { + ACMP_HYST_0 = 0x0, /**< No hysteresis */ + ACMP_HYST_15 = 0x1, /**< 15mV hysteresis */ + ACMP_HYST_22 = 0x2, /**< 22mV hysteresis */ + ACMP_HYST_29 = 0x3, /**< 29mV hysteresis */ + ACMP_HYST_36 = 0x4, /**< 36mV hysteresis */ + ACMP_HYST_43 = 0x5, /**< 43mV hysteresis */ + ACMP_HYST_50 = 0x6, /**< 50mV hysteresis */ + ACMP_HYST_57 = 0x7, /**< 57mV hysteresis */ +} acmp_hystsel_t; + +/** + * @brief ACMP inactive state + */ +typedef enum { + ACMP_INACTVAL_LOW = 0x0, /**< The inactive value is 0 */ + ACMP_INACTVAL_HIGH = 0x1, /**< The inactive value is 1 */ +} acmp_inactval_t; + +/** + * @brief which edges set up interrupt + */ +typedef enum { + ACMP_EDGE_NONE = 0x0, /**< Disable EDGE interrupt */ + ACMP_EDGE_FALL = 0x1, /**< Falling edges set EDGE interrupt */ + ACMP_EDGE_RISE = 0x2, /**< rise edges set EDGE interrupt */ + ACMP_EDGE_ALL = 0x3, /**< Falling edges and rise edges set EDGE interrupt */ +} acmp_edge_t; + +/** + * @brief ACMP output function + */ +typedef enum { + ACMP_OUT_DISABLE = 0x0, /**< Disable acmp output */ + ACMP_OUT_ENABLE = 0x1, /**< Enable acmp output */ +} acmp_out_func_t; + +/** + * @brief ACMP init structure definition + */ +typedef struct { + acmp_mode_t mode; /**< ACMP operation mode */ + acmp_warm_time_t warm_time; /**< ACMP warm up time */ + acmp_hystsel_t hystsel; /**< ACMP hysteresis level */ + acmp_pos_input_t p_port; /**< ACMP positive port select */ + acmp_neg_input_t n_port; /**< ACMP negative port select */ + acmp_inactval_t inactval; /**< ACMP inavtive output value */ + type_func_t out_inv; /**< ACMP output inverse */ + acmp_edge_t edge; /**< Select edges to set interrupt flag */ + uint8_t vdd_level; /**< Select scaling factor for CDD reference level, MAX is 63 */ +} acmp_init_t; + +/** + * @brief ACMP Handle Structure definition + */ +typedef struct acmp_handle_s { + ACMP_TypeDef *perh; /**< Register base address */ + acmp_init_t init; /**< ACMP required parameters */ + lock_state_t lock; /**< Locking object */ + + void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< ACMP warm-up complete callback */ + void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< ACMP edge trigger callback */ +} acmp_handle_t; +/** + * @} + */ + +/** @defgroup ACMP_Public_Macros ACMP Public Macros + * @{ + */ +#define ACMP_ENABLE(handle) (SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK)) +#define ACMP_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK)) +/** + * @} + */ + +/** @defgroup ACMP_Private_Macros ACMP Private Macros + * @{ + */ +#define IS_ACMP_TYPE(x) (((x) == ACMP0) || \ + ((x) == ACMP1) || \ + ((x) == ACMP2)) +#define IS_ACMP_MODE_TYPE(x) (((x) == ACMP_ULTRA_LOW_POWER) || \ + ((x) == ACMP_LOW_POWER) || \ + ((x) == ACMP_MIDDLE_POWER) || \ + ((x) == ACMP_HIGH_POWER)) +#define IS_ACMP_IT_TYPE(x) (((x) == ACMP_IT_EDGE) || \ + ((x) == ACMP_IT_WARMUP)) +#define IS_ACMP_FLAG_TYPE(x) (((x) == ACMP_FLAG_EDGE) || \ + ((x) == ACMP_FLAG_WARMUP)) +#define IS_ACMP_STATUS_TYPE(x) (((x) == ACMP_STATUS_ACT) || \ + ((x) == ACMP_STATUS_OUT)) +#define IS_ACMP_POS_INPUT_TYPE(x) (((x) == ACMP_POS_CH0) || \ + ((x) == ACMP_POS_CH1) || \ + ((x) == ACMP_POS_CH2) || \ + ((x) == ACMP_POS_CH3) || \ + ((x) == ACMP_POS_CH4) || \ + ((x) == ACMP_POS_CH5) || \ + ((x) == ACMP_POS_CH6) || \ + ((x) == ACMP_POS_CH7)) +#define IS_ACMP_NEG_INPUT_TYPE(x) (((x) == ACMP_NEG_CH0) || \ + ((x) == ACMP_NEG_CH1) || \ + ((x) == ACMP_NEG_CH2) || \ + ((x) == ACMP_NEG_CH3) || \ + ((x) == ACMP_NEG_CH4) || \ + ((x) == ACMP_NEG_CH5) || \ + ((x) == ACMP_NEG_CH6) || \ + ((x) == ACMP_NEG_CH7) || \ + ((x) == ACMP_NEG_1V25) || \ + ((x) == ACMP_NEG_2V5) || \ + ((x) == ACMP_NEG_VDD)) +#define IS_ACMP_WARM_UP_TIME_TYPE(x) (((x) == ACMP_4_PCLK) || \ + ((x) == ACMP_8_PCLK) || \ + ((x) == ACMP_16_PCLK) || \ + ((x) == ACMP_32_PCLK) || \ + ((x) == ACMP_64_PCLK) || \ + ((x) == ACMP_128_PCLK) || \ + ((x) == ACMP_256_PCLK) || \ + ((x) == ACMP_512_PCLK)) +#define IS_ACMP_HYSTSEL_TYPE(x) (((x) == ACMP_HYST_0) || \ + ((x) == ACMP_HYST_15) || \ + ((x) == ACMP_HYST_22) || \ + ((x) == ACMP_HYST_29) || \ + ((x) == ACMP_HYST_36) || \ + ((x) == ACMP_HYST_43) || \ + ((x) == ACMP_HYST_50) || \ + ((x) == ACMP_HYST_57)) +#define IS_ACMP_INACTVAL_TYPE(x) (((x) == ACMP_INACTVAL_LOW) || \ + ((x) == ACMP_INACTVAL_HIGH)) +#define IS_ACMP_EDGE_TYPE(x) (((x) == ACMP_EDGE_NONE) || \ + ((x) == ACMP_EDGE_FALL) || \ + ((x) == ACMP_EDGE_RISE) || \ + ((x) == ACMP_EDGE_ALL)) +/** + * @} + */ + +/** @addtogroup ACMP_Public_Functions + * @{ + */ + +/** @addtogroup ACMP_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_acmp_init(acmp_handle_t *hperh); +/** + * @} + */ +/** @addtogroup ACMP_Public_Functions_Group2 + * @{ + */ +void ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state); +it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it); +flag_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag); +flag_status_t ald_acmp_get_mask_flag_status(acmp_handle_t *hperh, acmp_flag_t flag); +void ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag); +/** + * @} + */ +/** @addtogroup ACMP_Public_Functions_Group3 + * @{ + */ +void ald_acmp_irq_handler(acmp_handle_t *hperh); +void ald_acmp_out_config(acmp_handle_t *hperh, type_func_t state); +uint8_t ald_acmp_out_result(acmp_handle_t *hperh); +flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +extern "C" } +#endif +#endif diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..cfadf6af80e988c592b65a707d97ee378d89ea51 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_adc.h @@ -0,0 +1,559 @@ +/** + ****************************************************************************** + * @file ald_adc.h + * @brief Header file of ADC Module library. + * + * @version V1.0 + * @date 28 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ****************************************************************************** + */ + +#ifndef __ALD_ADC_H__ +#define __ALD_ADC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" +#include "ald_pis.h" +#include "ald_timer.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Pubulic_Types ADC Pubulic Types + * @{ + */ + +/** + * @brief ADC State structures definition + */ +typedef enum { + ADC_STATE_RESET = 0x0, /**< ADC not yet initialized or disabled */ + ADC_STATE_READY = 0x1, /**< ADC peripheral ready for use */ + ADC_STATE_BUSY_INTERNAL = 0x2, /**< ADC is busy to internal process */ + ADC_STATE_TIMEOUT = 0x4, /**< TimeOut occurrence */ + ADC_STATE_ERROR = 0x10, /**< Internal error occurrence */ + ADC_STATE_NM_BUSY = 0x100, /**< Conversion on group normal is ongoing or can occur */ + ADC_STATE_NM_EOC = 0x200, /**< Conversion data available on group normal */ + ADC_STATE_IST_BUSY = 0x1000, /**< Conversion on group insert is ongoing or can occur */ + ADC_STATE_IST_EOC = 0x2000, /**< Conversion data available on group insert */ + ADC_STATE_AWD = 0x10000, /**< Out-of-window occurrence of analog watchdog */ +} adc_state_t; + +/** + *@brief ADC Error Code + */ +typedef enum { + ADC_ERROR_NONE = 0x0, /**< No error */ + ADC_ERROR_INTERNAL = 0x1, /**< ADC IP internal error*/ + ADC_ERROR_OVR = 0x2, /**< Overrun error */ + ADC_ERROR_DMA = 0x4, /**< DMA transfer error */ +} adc_error_t; + +/** + *@brief ADC data alignment + */ +typedef enum { + ADC_DATAALIGN_RIGHT = 0x0, /**< ADC data alignment right */ + ADC_DATAALIGN_LEFT = 0x1, /**< ADC data alignment left */ +} adc_align_t; + +/** + *@brief ADC config hannal trigger the EOC IT mode + */ +typedef enum { + ADC_NCHESEL_MODE_ALL = 0x0, /**< ADC set RCHE after convert sequence finish */ + ADC_NCHESEL_MODE_ONE = 0x1, /**< ADC set RCHE after one convert finish */ +} adc_nchesel_t; + +/** + *@brief ADC channels + */ +typedef enum { + ADC_CHANNEL_0 = 0x0, /**< ADC channel 0 */ + ADC_CHANNEL_1 = 0x1, /**< ADC channel 1 */ + ADC_CHANNEL_2 = 0x2, /**< ADC channel 2 */ + ADC_CHANNEL_3 = 0x3, /**< ADC channel 3 */ + ADC_CHANNEL_4 = 0x4, /**< ADC channel 4 */ + ADC_CHANNEL_5 = 0x5, /**< ADC channel 5 */ + ADC_CHANNEL_6 = 0x6, /**< ADC channel 6 */ + ADC_CHANNEL_7 = 0x7, /**< ADC channel 7 */ + ADC_CHANNEL_8 = 0x8, /**< ADC channel 8 */ + ADC_CHANNEL_9 = 0x9, /**< ADC channel 9 */ + ADC_CHANNEL_10 = 0xA, /**< ADC channel 10 */ + ADC_CHANNEL_11 = 0xB, /**< ADC channel 11 */ + ADC_CHANNEL_12 = 0xC, /**< ADC channel 12 */ + ADC_CHANNEL_13 = 0xD, /**< ADC channel 13 */ + ADC_CHANNEL_14 = 0xE, /**< ADC channel 14 */ + ADC_CHANNEL_15 = 0xF, /**< ADC channel 15 */ + ADC_CHANNEL_16 = 0x10, /**< ADC channel 16 */ + ADC_CHANNEL_17 = 0x11, /**< ADC channel 17 */ + ADC_CHANNEL_18 = 0x12, /**< ADC channel 18 */ +} adc_channel_t; + +/** + *@brief ADC sampling times + */ +typedef enum { + ADC_SAMPLETIME_1 = 0x0, /**< ADC sampling times 1 clk */ + ADC_SAMPLETIME_2 = 0x1, /**< ADC sampling times 2 clk */ + ADC_SAMPLETIME_4 = 0x2, /**< ADC sampling times 4 clk */ + ADC_SAMPLETIME_15 = 0x3, /**< ADC sampling times 15 clk */ +} adc_samp_t; + +/** + *@brief ADC rank into normal group + */ +typedef enum { + ADC_NCH_RANK_1 = 0x1, /**< ADC normal channel rank 1 */ + ADC_NCH_RANK_2 = 0x2, /**< ADC normal channel rank 2 */ + ADC_NCH_RANK_3 = 0x3, /**< ADC normal channel rank 3 */ + ADC_NCH_RANK_4 = 0x4, /**< ADC normal channel rank 4 */ + ADC_NCH_RANK_5 = 0x5, /**< ADC normal channel rank 5 */ + ADC_NCH_RANK_6 = 0x6, /**< ADC normal channel rank 6 */ + ADC_NCH_RANK_7 = 0x7, /**< ADC normal channel rank 7 */ + ADC_NCH_RANK_8 = 0x8, /**< ADC normal channel rank 8 */ + ADC_NCH_RANK_9 = 0x9, /**< ADC normal channel rank 9 */ + ADC_NCH_RANK_10 = 0xA, /**< ADC normal channel rank 10 */ + ADC_NCH_RANK_11 = 0xB, /**< ADC normal channel rank 11 */ + ADC_NCH_RANK_12 = 0xC, /**< ADC normal channel rank 12 */ + ADC_NCH_RANK_13 = 0xD, /**< ADC normal channel rank 13 */ + ADC_NCH_RANK_14 = 0xE, /**< ADC normal channel rank 14 */ + ADC_NCH_RANK_15 = 0xF, /**< ADC normal channel rank 15 */ + ADC_NCH_RANK_16 = 0x10, /**< ADC normal channel rank 16 */ +} adc_nch_rank_t; + +/** + * @brief ADC rank into insert group + */ +typedef enum { + ADC_ICH_RANK_1 = 0x1, /**< ADC insert channel rank 1 */ + ADC_ICH_RANK_2 = 0x2, /**< ADC insert channel rank 2 */ + ADC_ICH_RANK_3 = 0x3, /**< ADC insert channel rank 3 */ + ADC_ICH_RANK_4 = 0x4, /**< ADC insert channel rank 4 */ +} adc_ich_rank_t; + +/** + * @brief ADC analog watchdog mode + */ +typedef enum { + ADC_ANAWTD_NONE = 0x0, /**< No watch dog */ + ADC_ANAWTD_SING_NM = 0x800200, /**< One normal channel watch dog */ + ADC_ANAWTD_SING_IST = 0x400200, /**< One inset channel Injec watch dog */ + ADC_ANAWTD_SING_NMIST = 0xC00200, /**< One normal and inset channel watch dog */ + ADC_ANAWTD_ALL_NM = 0x800000, /**< All normal channel watch dog */ + ADC_ANAWTD_ALL_IST = 0x400000, /**< All inset channel watch dog */ + ADC_ANAWTD_ALL_NMIST = 0xC00000, /**< All normal and inset channel watch dog */ +} adc_ana_wtd_t; + +/** + * @brief ADC Event type + */ +typedef enum { + ADC_AWD_EVENT = (1U << 0), /**< ADC analog watch dog event */ +} adc_event_type_t; + +/** + * @brief ADC interrupts definition + */ +typedef enum { + ADC_IT_NCH = (1U << 5), /**< ADC it normal */ + ADC_IT_AWD = (1U << 6), /**< ADC it awd */ + ADC_IT_ICH = (1U << 7), /**< ADC it insert */ + ADC_IT_OVR = (1U << 26), /**< ADC it overring */ +} adc_it_t; + +/** + * @brief ADC flags definition + */ +typedef enum { + ADC_FLAG_AWD = (1U << 0), /**perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK)) +#define ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK)) +#define ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET) +#define ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ADC_NETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, (mode) << ADC_CON1_NETS_POSS)) +#define ADC_IETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, (mode) << ADC_CON1_IETS_POSS)) +#define ADC_NETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, 0 << ADC_CON1_NETS_POSS)) +#define ADC_IETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, 0 << ADC_CON1_IETS_POSS)) +/** + * @} + */ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +#define IS_ADC_ICH_RANK_TYPE(x) ((x) <= ADC_ICH_RANK_4) +#define IS_ADC_NCH_RANK_TYPE(x) ((x) <= ADC_NCH_RANK_16) +#define IS_ADC_SAMPLING_TIMES_TYPE(x) (((x) == ADC_SAMPLETIME_1) || \ + ((x) == ADC_SAMPLETIME_2) || \ + ((x) == ADC_SAMPLETIME_4) || \ + ((x) == ADC_SAMPLETIME_15)) +#define IS_ADC_CHANNELS_TYPE(x) ((x) <= ADC_CHANNEL_18) +#define IS_ADC_SCAN_MODE_TYPE(x) (((x) == DISABLE) || \ + ((x) == ENABLE)) +#define IS_ADC_DATA_ALIGN_TYPE(x) (((x) == ADC_DATAALIGN_RIGHT) || \ + ((x) == ADC_DATAALIGN_LEFT)) +#define IS_ADC_ANALOG_WTD_MODE_TYPE(x) (((x) == ADC_ANAWTD_NONE) || \ + ((x) == ADC_ANAWTD_SING_NM) || \ + ((x) == ADC_ANAWTD_SING_IST) || \ + ((x) == ADC_ANAWTD_SING_NMIST) || \ + ((x) == ADC_ANAWTD_ALL_NM) || \ + ((x) == ADC_ANAWTD_ALL_IST) || \ + ((x) == ADC_ANAWTD_ALL_NMIST)) +#define IS_ADC_IT_TYPE(x) (((x) == ADC_IT_NCH) || \ + ((x) == ADC_IT_AWD) || \ + ((x) == ADC_IT_ICH) || \ + ((x) == ADC_IT_OVR )) +#define IS_ADC_FLAGS_TYPE(x) (((x) == ADC_FLAG_AWD) || \ + ((x) == ADC_FLAG_NCH) || \ + ((x) == ADC_FLAG_ICH) || \ + ((x) == ADC_FLAG_OVR) || \ + ((x) == ADC_FLAG_NCHS) || \ + ((x) == ADC_FLAG_ICHS)) +#define IS_ADC_CLK_DIV_TYPE(x) (((x) == ADC_CKDIV_1) || \ + ((x) == ADC_CKDIV_2) || \ + ((x) == ADC_CKDIV_4) || \ + ((x) == ADC_CKDIV_8) || \ + ((x) == ADC_CKDIV_16) || \ + ((x) == ADC_CKDIV_32) || \ + ((x) == ADC_CKDIV_64) || \ + ((x) == ADC_CKDIV_128)) +#define IS_ADC_NEG_REF_VOLTAGE_TYPE(x) (((x) == ADC_NEG_REF_VSS ) || \ + ((x) == ADC_NEG_REF_VREFN )) +#define IS_POS_REF_VOLTAGE_TYPE(x) (((x) == ADC_POS_REF_VDD) || \ + ((x) == ADC_POS_REF_2_V) || \ + ((x) == ADC_POS_REF_VREEFP) || \ + ((x) == ADC_POS_REF_VREEFP_BUF)) +#define IS_ADC_NCH_LEN_TYPE(x) ((x) <= ADC_NCH_LEN_16) +#define IS_ADC_NBR_OF_IST_TYPE(x) ((x) <= ADC_ICH_LEN_4) +#define IS_ADC_DISC_NBR_TYPE(x) ((x) <= ADC_DISC_NBR_8) +#define IS_ADC_CONV_RES_TYPE(x) (((x) == ADC_CONV_RES_12) || \ + ((x) == ADC_CONV_RES_6) || \ + ((x) == ADC_CONV_RES_8) || \ + ((x) == ADC_CONV_RES_10)) +#define IS_ADC_TYPE(x) (((x) == ADC0) || \ + ((x) == ADC1)) +#define IS_ADC_NCHESEL_MODE_TYPE(x) (((x) == ADC_NCHESEL_MODE_ALL) || \ + ((x) == ADC_NCHESEL_MODE_ONE)) +#define IS_ADC_EVENT_TYPE(x) ((x) == ADC_AWD_EVENT) +#define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xfff) +#define IS_HTR_TYPE(x) ((x) <= 0xfff) +#define IS_LTR_TYPE(x) ((x) <= 0xfff) +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions + * @{ + */ + +/** @addtogroup ADC_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_adc_init(adc_handle_t *hperh); +ald_status_t ald_adc_reset(adc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_adc_normal_start(adc_handle_t *hperh); +ald_status_t ald_adc_normal_stop(adc_handle_t *hperh); +ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); +ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout); +ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh); +ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh); +#ifdef ALD_DMA +ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh); +ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config); +#endif +uint32_t ald_adc_normal_get_value(adc_handle_t *hperh); +ald_status_t ald_adc_insert_start(adc_handle_t *hperh); +ald_status_t ald_adc_insert_stop(adc_handle_t *hperh); +ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); +ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh); +ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh); +uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_rank_t ih_rank); +void ald_adc_irq_handler(adc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group3 + * @{ + */ +ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config); +ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config); +ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config); +void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state); +it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it); +flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag); +void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group4 + * @{ + */ +uint32_t ald_adc_get_state(adc_handle_t *hperh); +uint32_t ald_adc_get_error(adc_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus + extern "C" } +#endif + +#endif /* __ALD_ADC_H */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h new file mode 100644 index 0000000000000000000000000000000000000000..700385cdbc2eb7e4212488756bdcf3999b5db3c5 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_bkpc.h @@ -0,0 +1,194 @@ +/** + ********************************************************************************* + * + * @file ald_bkpc.h + * @brief Header file of BKPC module driver. + * + * @version V1.0 + * @date 15 Dec 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_BKPC_H__ +#define __ALD_BKPC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup BKPC + * @{ + */ + +/** @defgroup BKPC_Public_Macros BKPC Public Macros + * @{ + */ +#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0)) +#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55)) +#define BKPC_LRC_ENABLE() \ +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ + BKPC_LOCK(); \ +} while (0) +#define BKPC_LRC_DISABLE() \ +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ + BKPC_LOCK(); \ +} while (0) +#define BKPC_LOSM_ENABLE() \ +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \ + BKPC_LOCK(); \ +} while (0) +#define BKPC_LOSM_DISABLE() \ +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\ + BKPC_LOCK(); \ +} while (0) +#define BKPC_LOSC_ENABLE() \ +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \ + BKPC_LOCK(); \ +} while (0) +#define BKPC_LOSC_DISABLE() \ +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\ + BKPC_LOCK(); \ +} while (0) + + +#define BKPC_MRST_WAKEUP_ENABLE() \ +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK); \ + BKPC_LOCK(); \ +} while (0) +#define BKPC_MRST_WAKEUP_DISABLE() \ +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK); \ + BKPC_LOCK(); \ +} while (0) + +/** + * @} + */ + +/** @defgroup BKPC_Public_Types BKPC Public Types + * @{ + */ +/** + * @brief BKPC preipheral clock select. + */ +typedef enum { + BKPC_PREH_CLK_LOSM = 0x0, /**< LOSM */ + BKPC_PREH_CLK_LRC = 0x1, /**< LRC */ + BKPC_PREH_CLK_HRC_1M = 0x2, /**< HRC down to 1MHz */ + BKPC_PREH_CLK_HOSC_1M = 0x3, /**< HOSC down to 1MHz */ +} bkpc_preh_clk_t; + +/** + * @brief Standby wakeup port select + */ +typedef enum { + PMU_STANDBY_PORT_SEL_PA0 = 0x0, /**< PA0 */ + PMU_STANDBY_PORT_SEL_PA1 = 0x1, /**< PA1 */ + PMU_STANDBY_PORT_SEL_PA2 = 0x2, /**< PA2 */ + PMU_STANDBY_PORT_SEL_PA3 = 0x3, /**< PA3 */ + PMU_STANDBY_PORT_SEL_PA4 = 0x4, /**< PA4 */ + PMU_STANDBY_PORT_SEL_PA5 = 0x5, /**< PA5 */ + PMU_STANDBY_PORT_SEL_PA6 = 0x6, /**< PA6 */ + PMU_STANDBY_PORT_SEL_PA7 = 0x7, /**< PA7 */ +} bkpc_wakeup_port_t; + +/** + * @brief Standby wakeup level + */ +typedef enum { + PMU_STANDBY_LEVEL_HIGH = 0x0, /**< PA0 */ + PMU_STANDBY_LEVEL_LOW = 0x1, /**< PA1 */ +} bkpc_wakeup_level_t; + +/** + * @} + */ + +/** + * @defgroup BKPC_Private_Macros BKPC Private Macros + * @{ + */ +#define IS_BKPC_WAKEUP_PORT(x) (((x) == PMU_STANDBY_PORT_SEL_PA0) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA1) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA2) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA3) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA4) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA5) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA6) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA7)) +#define IS_BKPC_WAKEUP_LEVEL(x) (((x) == PMU_STANDBY_LEVEL_HIGH) || \ + ((x) == PMU_STANDBY_LEVEL_LOW)) +#define IS_BKPC_PREH_CLOCK(x) (((x) == BKPC_PREH_CLK_LOSM) || \ + ((x) == BKPC_PREH_CLK_LRC) || \ + ((x) == BKPC_PREH_CLK_HRC_1M) || \ + ((x) == BKPC_PREH_CLK_HOSC_1M)) +#define IS_BKPC_RAM_IDX(x) ((x) < 32) +/** + * @} + */ + +/** @addtogroup BKPC_Public_Functions + * @{ + */ +/** @addtogroup BKPC_Public_Functions_Group1 + * @{ + */ +/* control functions */ +extern void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level); +extern void ald_bkpc_rtc_clock_config(bkpc_preh_clk_t clock); +extern void ald_bkpc_tsense_clock_config(bkpc_preh_clk_t clock); +/** + * @} + */ +/** @addtogroup BKPC_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +extern void ald_bkpc_write_ram(uint8_t idx, uint32_t value); +extern uint32_t ald_bkpc_read_ram(uint8_t idx); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_BKPC_H__ */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h new file mode 100644 index 0000000000000000000000000000000000000000..9375b835a8201e4d807409549c5a1e8cf371de92 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h @@ -0,0 +1,57 @@ +/** + ********************************************************************************* + * + * @file ald_calc.h + * @brief Header file of CALC module driver. + * + * @version V1.0 + * @date 26 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_CALC_H__ +#define __ALD_CALC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CALC + * @{ + */ + +/** @addtogroup CALC_Public_Functions + * @{ + */ +extern uint32_t ald_calc_sqrt(uint32_t data); +extern uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder); +extern int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder); +extern flag_status_t ald_calc_get_dz_status(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_CALC_H__ */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h new file mode 100644 index 0000000000000000000000000000000000000000..9999ccd675b0d0bdb9ccdd93c75ae6c9945bb03e --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_can.h @@ -0,0 +1,471 @@ +/** + ****************************************************************************** + * @file ald_can.h + * @brief Header file of CAN Module driver. + * + * @version V1.0 + * @date 16 Apr 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ****************************************************************************** + */ + +#ifndef __ALD_CAN_H +#define __ALD_CAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/** @defgroup CAN_Public_Types CAN Public Types + * @{ + */ +/** + * @brief ALD State structures definition + */ +typedef enum { + CAN_STATE_RESET = 0x00, /**< CAN not yet initialized or disabled */ + CAN_STATE_READY = 0x01, /**< CAN initialized and ready for use */ + CAN_STATE_BUSY = 0x02, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX = 0x11, /**< CAN process is ongoing */ + CAN_STATE_BUSY_RX = 0x21, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX_RX = 0x31, /**< CAN process is ongoing */ + CAN_STATE_TIMEOUT = 0x03, /**< CAN in Timeout state */ + CAN_STATE_ERROR = 0x04, /**< CAN error state */ +} can_state_t; + +/** + * @brief CAN Error Code + */ +typedef enum { + CAN_ERROR_NONE = 0x00, /**< No error */ + CAN_ERROR_EWG = 0x01, /**< EWG error */ + CAN_ERROR_EPV = 0x02, /**< EPV error */ + CAN_ERROR_BOF = 0x04, /**< BOF error */ + CAN_ERROR_STF = 0x08, /**< Stuff error */ + CAN_ERROR_FOR = 0x10, /**< Form error */ + CAN_ERROR_ACK = 0x20, /**< Acknowledgment error */ + CAN_ERROR_BR = 0x40, /**< Bit recessive */ + CAN_ERROR_BD = 0x80, /**< LEC dominant */ + CAN_ERROR_CRC = 0x100, /**< LEC transfer error */ + CAN_ERROR_UNK = 0x200, /**< Unknown error */ +} can_error_t; + +/** + * @brief CAN Operating Mode + */ + typedef enum { + CAN_MODE_NORMAL = 0x00, /**< Normal mode */ + CAN_MODE_LOOPBACK = 0x01, /**< Loopback mode */ + CAN_MODE_SILENT = 0x02, /**< Silent mode */ + CAN_MODE_SILENT_LOOPBACK = 0x03, /**< Loopback combined with silent mode */ +} can_operate_mode_t; + +/** + * @brief CAN Synchronization Jump Width + */ +typedef enum { + CAN_SJW_1 = 0x0, /**< 1 time quantum */ + CAN_SJW_2 = 0x1, /**< 2 time quantum */ + CAN_SJW_3 = 0x2, /**< 3 time quantum */ + CAN_SJW_4 = 0x3, /**< 4 time quantum */ +} can_sjw_t; + +/** + * @brief CAN Time Quantum in Bit Segment 1 + */ +typedef enum { + CAN_SEG1_1 = 0x0, /**< 1 time quantum */ + CAN_SEG1_2 = 0x1, /**< 2 time quantum */ + CAN_SEG1_3 = 0x2, /**< 3 time quantum */ + CAN_SEG1_4 = 0x3, /**< 4 time quantum */ + CAN_SEG1_5 = 0x4, /**< 5 time quantum */ + CAN_SEG1_6 = 0x5, /**< 6 time quantum */ + CAN_SEG1_7 = 0x6, /**< 7 time quantum */ + CAN_SEG1_8 = 0x7, /**< 8 time quantum */ + CAN_SEG1_9 = 0x8, /**< 9 time quantum */ + CAN_SEG1_10 = 0x9, /**< 10 time quantum */ + CAN_SEG1_11 = 0xA, /**< 11 time quantum */ + CAN_SEG1_12 = 0xB, /**< 12 time quantum */ + CAN_SEG1_13 = 0xC, /**< 13 time quantum */ + CAN_SEG1_14 = 0xD, /**< 14 time quantum */ + CAN_SEG1_15 = 0xE, /**< 15 time quantum */ + CAN_SEG1_16 = 0xF, /**< 16 time quantum */ +} can_seg1_t; + +/** + * @brief CAN Time Quantum in Bit Segment 2 + */ +typedef enum { + CAN_SEG2_1 = 0x0, /**< 1 time quantum */ + CAN_SEG2_2 = 0x1, /**< 2 time quantum */ + CAN_SEG2_3 = 0x2, /**< 3 time quantum */ + CAN_SEG2_4 = 0x3, /**< 4 time quantum */ + CAN_SEG2_5 = 0x4, /**< 5 time quantum */ + CAN_SEG2_6 = 0x5, /**< 6 time quantum */ + CAN_SEG2_7 = 0x6, /**< 7 time quantum */ + CAN_SEG2_8 = 0x7, /**< 8 time quantum */ +} can_seg2_t; + +/** + * @brief CAN Filter Mode + */ +typedef enum { + CAN_FILTER_MODE_MASK = 0x0, /**< Identifier mask mode */ + CAN_FILTER_MODE_LIST = 0x1, /**< Identifier list mode */ +} can_filter_mode_t; + +/** + * @brief CAN Filter Scale + */ +typedef enum { + CAN_FILTER_SCALE_16 = 0x0, /**< Two 16-bit filters */ + CAN_FILTER_SCALE_32 = 0x1, /**< One 32-bit filter */ +} can_filter_scale_t; + +/** + * @brief CAN Filter fifo + */ +typedef enum { + CAN_FILTER_FIFO0 = 0x0, /**< FIFO 0 assignment for filter */ + CAN_FILTER_FIFO1 = 0x1, /**< FIFO 1 assignment for filter */ +} can_filter_fifo_t; + +/** + * @brief CAN Identifier Type + */ +typedef enum { + CAN_ID_STD = 0x0, /**< Standard Id */ + CAN_ID_EXT = 0x1, /**< Extended Id */ +} can_id_type_t; + +/** + * @brief CAN Remote Transmission Request + */ +typedef enum { + CAN_RTR_DATA = 0x0, /**< Data frame */ + CAN_RTR_REMOTE = 0x1, /**< Remote frame */ +} can_remote_req_t; + +/** + * @brief CAN Transmit Constants + */ +typedef enum { + CAN_TX_MAILBOX_0 = 0x0, /**< TX mailbox index 0 */ + CAN_TX_MAILBOX_1 = 0x1, /**< TX mailbox index 1 */ + CAN_TX_MAILBOX_2 = 0x2, /**< TX mailbox index 2 */ + CAN_TX_MAILBOX_NONE = 0x3, /**< MailBox can't be used */ +} can_tx_mailbox_t; + +/** + * @brief CAN Receive fifo Number + */ +typedef enum { + CAN_RX_FIFO0 = 0x0, /**< CAN fifo 0 used to receive */ + CAN_RX_FIFO1 = 0x1, /**< CAN fifo 1 used to receive */ +} can_rx_fifo_t; + +/** + * @brief CAN Flags + */ +typedef enum { + CAN_FLAG_SLPS = (1U << 1), /**< Sleep acknowledge flag */ + CAN_FLAG_ERR = (1U << 2), /**< Error flag*/ + CAN_FLAG_WK = (1U << 3), /**< Wake up flag */ + CAN_FLAG_SLP = (1U << 4), /**< Sleep acknowledge flag */ + CAN_FLAG_M0REQC = (1U << 20) | (1U << 0), /**< Request MailBox0 flag */ + CAN_FLAG_M0TXC = (1U << 20) | (1U << 1), /**< Transmission OK MailBox0 flag */ + CAN_FLAG_M1REQC = (1U << 20) | (1U << 8), /**< Request MailBox1 flag */ + CAN_FLAG_M1TXC = (1U << 20) | (1U << 9), /**< Transmission OK MailBox1 flag */ + CAN_FLAG_M2REQC = (1U << 20) | (1U << 16), /**< Request MailBox2 flag */ + CAN_FLAG_M2TXC = (1U << 20) | (1U << 17), /**< Transmission OK MailBox2 flag */ + CAN_FLAG_TXM0 = (1U << 20) | (1U << 26), /**< Transmit mailbox 0 empty flag */ + CAN_FLAG_TXM1 = (1U << 20) | (1U << 27), /**< Transmit mailbox 1 empty flag */ + CAN_FLAG_TXM2 = (1U << 20) | (1U << 28), /**< Transmit mailbox 2 empty flag */ + CAN_FLAG_FF0 = (2U << 20) | (1U << 3), /**< FIFO 0 Full flag */ + CAN_FLAG_FOV0 = (2U << 20) | (1U << 4), /**< FIFO 0 Overrun flag */ + CAN_FLAG_FF1 = (3U << 20) | (1U << 3), /**< FIFO 1 Full flag */ + CAN_FLAG_FOV1 = (3U << 20) | (1U << 4), /**< FIFO 1 Overrun flag */ + CAN_FLAG_WARN = (4U << 20) | (1U << 0), /**< Error warning flag */ + CAN_FLAG_PERR = (4U << 20) | (1U << 1), /**< Error passive flag */ + CAN_FLAG_BOF = (4U << 20) | (1U << 2), /**< Bus-Off flag */ +} can_flag_t; + +/** + * @brief CAN Interrupts + */ +typedef enum { + CAN_IT_TXM = (1U << 0), /**< Transmit mailbox empty interrupt bit */ + CAN_IT_FP0 = (1U << 1), /**< FIFO0 message pending interrupt bit */ + CAN_IT_FF0 = (1U << 2), /**< FIFO0 full interrupt bit */ + CAN_IT_FOV0 = (1U << 3), /**< FIFO0 overrun interrupt bit */ + CAN_IT_FP1 = (1U << 4), /**< FIFO1 message pending interrupt bit */ + CAN_IT_FF1 = (1U << 5), /**< FIFO1 full interrupt bit */ + CAN_IT_FOV1 = (1U << 6), /**< FIFO1 overrun interrupt bit */ + CAN_IT_WARN = (1U << 8), /**< Error warning interrupt bit */ + CAN_IT_PERR = (1U << 9), /**< Error passive interrupt bit */ + CAN_IT_BOF = (1U << 10), /**< Bus-off interrupt bit */ + CAN_IT_PRERR = (1U << 11), /**< Last error code interrupt bit */ + CAN_IT_ERR = (1U << 15), /**< Error interrupt bit */ + CAN_IT_WK = (1U << 16), /**< wake-up interrupt bit */ + CAN_IT_SLP = (1U << 17), /**< sleep interrupt bit */ +} can_it_t; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct { + uint32_t id_high; /**< Specifies the filter identification number */ + uint32_t id_low; /**< Specifies the filter identification number */ + uint32_t mask_id_high; /**< Specifies the filter mask number or identification number */ + uint32_t mask_id_low; /**< Specifies the filter mask number or identification number */ + can_filter_fifo_t fifo; /**< Specifies the fifo (0 or 1) which will be assigned to the filter. */ + uint32_t number; /**< Specifies the filter which will be initialized. */ + can_filter_mode_t mode; /**< Specifies the filter mode to be initialized. */ + can_filter_scale_t scale; /**< Specifies the filter scale. */ + type_func_t active; /**< Enable or disable the filter. */ + uint32_t bank_number; /**< Select the start slave bank filter. */ +} can_filter_t; + +/** + * @brief CAN init structure definition + */ +typedef struct { + uint32_t psc; /**< Specifies the length of a time quantum. */ + can_operate_mode_t mode; /**< Specifies the CAN operating mode. */ + can_sjw_t sjw; /**< Specifies the maximum number of time quanta the CAN hardware is + allowed to lengthen or shorten a bit to perform resynchronization. */ + can_seg1_t seg1; /**< Specifies the number of time quanta in Bit Segment 1. */ + can_seg2_t seg2; /**< Specifies the number of time quanta in Bit Segment 2. */ + type_func_t ttcm; /**< Enable or disable the time triggered communication mode. */ + type_func_t abom; /**< Enable or disable the automatic bus-off management. */ + type_func_t awk; /**< Enable or disable the automatic wake-up mode. */ + type_func_t artx; /**< Enable or disable the non-automatic retransmission mode. */ + type_func_t rfom; /**< Enable or disable the Receive fifo Locked mode. */ + type_func_t txmp; /**< Enable or disable the transmit fifo priority. */ +} can_init_t; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct { + uint32_t std; /**< Specifies the standard identifier. */ + uint32_t ext; /**< Specifies the extended identifier. */ + can_id_type_t type; /**< Specifies the type of identifier for the message that will be transmitted. */ + can_remote_req_t rtr; /**< Specifies the type of frame for the message that will be transmitted. */ + uint32_t len; /**< Specifies the length of the frame that will be transmitted. */ + uint8_t data[8]; /**< Contains the data to be transmitted. */ +} can_tx_msg_t; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct { + uint32_t std; /**< Specifies the standard identifier. */ + uint32_t ext; /**< Specifies the extended identifier. */ + can_id_type_t type; /**< Specifies the type of identifier for the message that will be received. */ + can_remote_req_t rtr; /**< Specifies the type of frame for the received message. */ + uint32_t len; /**< Specifies the length of the frame that will be received. */ + uint8_t data[8]; /**< Contains the data to be received. */ + uint32_t fmi; /**< Specifies the index of the filter the message stored in the mailbox passes through. */ + can_rx_fifo_t num; /**< Specifies the receive fifo number. */ +} can_rx_msg_t; + +/** + * @brief CAN handle Structure definition + */ +typedef struct can_handle_s { + CAN_TypeDef *perh; /**< Register base address */ + can_init_t init; /**< CAN required parameters */ + can_rx_msg_t *rx_msg; /**< Pointer to receive message */ + lock_state_t lock; /**< CAN locking object */ + can_state_t state; /**< CAN communication state */ + can_error_t err; /**< CAN Error code */ + + void (*tx_cplt_cbk)(struct can_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct can_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct can_handle_s *arg); /**< error callback */ +} can_handle_t; +/** + * @} + */ + +/** @defgroup CAN_Public_Macro CAN Public Macros + * @{ + */ +#define CAN_RESET_HANDLE_STATE(x) ((x)->state = CAN_STATE_RESET) +#define CAN_RX_MSG_PENDING(x, y) (((y) == CAN_RX_FIFO0) ? \ + (READ_BIT((x)->perh->RXF0, CAN_RXF0_PEND_MSK)) : (READ_BIT((x)->perh->RXF1, CAN_RXF1_PEND_MSK))) +#define CAN_DBG_FREEZE(x, y) (MODIFY_REG((x)->perh->CON, CAN_CON_DBGSTP_MSK, (y) << CAN_CON_DBGSTP_POS)) +#define CAN_TX_STAMP_ENABLE(x) (SET_BIT(hperh->perh->TxMailBox[(x)].TXFCON, CAN_TXFCON0_TXGT_MSK)) +#define CAN_TX_STAMP_DISABLE(x) (CLEAR_BIT(hperh->perh->TxMailBox[(x)].TXFCON, CAN_TXFCON0_TXGT_MSK)) +/** + * @} + */ + +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ +#define IS_CAN_ALL(x) ((x) == CAN0) +#define IS_CAN_FILTER_NUMBER(x) ((x) <= 13) +#define IS_CAN_MODE(x) (((x) == CAN_MODE_NORMAL) || \ + ((x) == CAN_MODE_LOOPBACK) || \ + ((x) == CAN_MODE_SILENT) || \ + ((x) == CAN_MODE_SILENT_LOOPBACK)) +#define IS_CAN_SJW(x) (((x) == CAN_SJW_1) || \ + ((x) == CAN_SJW_2) || \ + ((x) == CAN_SJW_3) || \ + ((x) == CAN_SJW_4)) +#define IS_CAN_BS1(x) ((x) <= CAN_SEG1_16) +#define IS_CAN_BS2(x) ((x) <= CAN_SEG2_8) +#define IS_CAN_FILTER_MODE(x) (((x) == CAN_FILTER_MODE_MASK) || \ + ((x) == CAN_FILTER_MODE_LIST)) +#define IS_CAN_FILTER_SCALE(x) (((x) == CAN_FILTER_SCALE_16) || \ + ((x) == CAN_FILTER_SCALE_32)) +#define IS_CAN_FILTER_FIFO(x) (((x) == CAN_FILTER_FIFO0) || \ + ((x) == CAN_FILTER_FIFO1)) +#define IS_CAN_IDTYPE(x) (((x) == CAN_ID_STD) || \ + ((x) == CAN_ID_EXT)) +#define IS_CAN_RTR(x) (((x) == CAN_RTR_DATA) || ((x) == CAN_RTR_REMOTE)) +#define IS_CAN_FIFO(x) (((x) == CAN_RX_FIFO0) || ((x) == CAN_RX_FIFO1)) +#define IS_CAN_BANKNUMBER(x) ((x) <= 28) +#define IS_CAN_TX_MAILBOX(x) ((x) <= CAN_TX_MAILBOX_NONE) +#define IS_CAN_STDID(x) ((x) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(x) ((x) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DATA_LEN(x) ((x) <= ((uint8_t)0x08)) +#define IS_CAN_PRESCALER(x) (((x) >= 1) && ((x) <= 1024)) +#define IS_CAN_GET_FLAG(x) (((x) == CAN_FLAG_SLPS) || \ + ((x) == CAN_FLAG_ERR) || \ + ((x) == CAN_FLAG_WK) || \ + ((x) == CAN_FLAG_SLP) || \ + ((x) == CAN_FLAG_M0REQC) || \ + ((x) == CAN_FLAG_M0TXC) || \ + ((x) == CAN_FLAG_M1REQC) || \ + ((x) == CAN_FLAG_M1TXC) || \ + ((x) == CAN_FLAG_M2REQC) || \ + ((x) == CAN_FLAG_M2TXC) || \ + ((x) == CAN_FLAG_TXM0) || \ + ((x) == CAN_FLAG_TXM1) || \ + ((x) == CAN_FLAG_TXM2) || \ + ((x) == CAN_FLAG_FF0) || \ + ((x) == CAN_FLAG_FOV0) || \ + ((x) == CAN_FLAG_FF1) || \ + ((x) == CAN_FLAG_FOV1) || \ + ((x) == CAN_FLAG_WARN) || \ + ((x) == CAN_FLAG_PERR) || \ + ((x) == CAN_FLAG_BOF)) +#define IS_CAN_CLEAR_FLAG(x) (((x) == CAN_FLAG_ERR) || \ + ((x) == CAN_FLAG_WK) || \ + ((x) == CAN_FLAG_SLP) || \ + ((x) == CAN_FLAG_M0REQC) || \ + ((x) == CAN_FLAG_M1REQC) || \ + ((x) == CAN_FLAG_M2REQC) || \ + ((x) == CAN_FLAG_FF0) || \ + ((x) == CAN_FLAG_FOV0) || \ + ((x) == CAN_FLAG_FF1) || \ + ((x) == CAN_FLAG_FOV1)) +#define IS_CAN_IT(x) (((x) == CAN_IT_TXM) || \ + ((x) == CAN_IT_FP0) || \ + ((x) == CAN_IT_FF0) || \ + ((x) == CAN_IT_FOV0) || \ + ((x) == CAN_IT_FP1) || \ + ((x) == CAN_IT_FF1) || \ + ((x) == CAN_IT_FOV1) || \ + ((x) == CAN_IT_WARN) || \ + ((x) == CAN_IT_PERR) || \ + ((x) == CAN_IT_BOF) || \ + ((x) == CAN_IT_PRERR) || \ + ((x) == CAN_IT_ERR) || \ + ((x) == CAN_IT_WK) || \ + ((x) == CAN_IT_SLP)) +#define CAN_TIMEOUT_VALUE 100 +#define CAN_STATE_TX_MASK (1U << 4) +#define CAN_STATE_RX_MASK (1U << 5) +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions + * @{ + */ + +/** @addtogroup CAN_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void ald_can_reset(can_handle_t *hperh); +ald_status_t ald_can_init(can_handle_t *hperh); +ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config); +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +ald_status_t ald_can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout); +ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg); +ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout); +ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg); +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions_Group3 + * @{ + */ +/* Control function */ +ald_status_t ald_can_sleep(can_handle_t *hperh); +ald_status_t ald_can_wake_up(can_handle_t *hperh); +void ald_can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box); +void ald_can_irq_handler(can_handle_t *hperh); +type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box); +void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state); +it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it); +flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag); +void ald_can_clear_flag_status(can_handle_t *hperh, can_flag_t flag); +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions_Group4 + * @{ + */ +/* State and Error functions */ +can_state_t ald_can_get_state(can_handle_t *hperh); +can_error_t ald_can_get_error(can_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_CAN_H */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h similarity index 35% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h rename to bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h index ced2976ea8b7b119657182e32fd0e3357b6046c0..3096ee23f46aa445745c2c84bc1c75204ddab327 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_cmu.h @@ -5,7 +5,7 @@ * @brief Header file of CMU module driver. * * @version V1.0 - * @date 22 Nov 2017 + * @date 22 Nov 2019 * @author AE Team * @note * @@ -36,91 +36,127 @@ extern "C" { /** @defgroup CMU_Public_Macros CMU Public Macros * @{ */ -#define CMU_LOSC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ +#define CMU_HRC_SEL_BY_SW() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CFGR, CMU_CFGR_HRCFCS_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define CMU_LOSC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ +#define CMU_HRC_SEL_BY_CFGW() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFCS_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define CMU_LRC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ +#define CMU_HRC_DIV_1MHZ_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC1MEN_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define CMU_LRC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ +#define CMU_HRC_DIV_1MHZ_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HRC1MEN_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define CMU_ULRC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ - SYSCFG_LOCK(); \ +#define CMU_HOSC_DIV_1MHZ_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSC1MEN_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define CMU_ULRC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ - SYSCFG_LOCK(); \ +#define CMU_HOSC_DIV_1MHZ_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSC1MEN_MSK);\ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LOSC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LOSC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LRC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LRC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_ULRC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_ULRC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ + SYSCFG_LOCK(); \ } while (0) /* Low power mode control */ -#define CMU_LP_LRC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ +#define CMU_LP_LRC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define CMU_LP_LRC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ - SYSCFG_LOCK(); \ +#define CMU_LP_LRC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define CMU_LP_LOSC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ +#define CMU_LP_LOSC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define CMU_LP_LOSC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ - SYSCFG_LOCK(); \ +#define CMU_LP_LOSC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define CMU_LP_HRC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ - SYSCFG_LOCK(); \ +#define CMU_LP_HRC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define CMU_LP_HRC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ - SYSCFG_LOCK(); \ +#define CMU_LP_HRC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define CMU_LP_HOSC_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ - SYSCFG_LOCK(); \ +#define CMU_LP_HOSC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define CMU_LP_HOSC_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ - SYSCFG_LOCK(); \ +#define CMU_LP_HOSC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ + SYSCFG_LOCK(); \ } while (0) /** * @} @@ -133,268 +169,321 @@ do { \ /** * @brief CMU state structure definition */ -typedef enum -{ - CMU_CLOCK_HRC = 0x1, /**< HRC */ - CMU_CLOCK_LRC = 0x2, /**< LRC */ - CMU_CLOCK_LOSC = 0x3, /**< LOSC */ - CMU_CLOCK_PLL1 = 0x4, /**< PLL1 */ - CMU_CLOCK_HOSC = 0x5, /**< HOSC */ +typedef enum { + CMU_CLOCK_HRC = 0x1, /**< HRC */ + CMU_CLOCK_LRC = 0x2, /**< LRC */ + CMU_CLOCK_LOSC = 0x3, /**< LOSC */ + CMU_CLOCK_PLL1 = 0x4, /**< PLL1 */ + CMU_CLOCK_HOSC = 0x5, /**< HOSC */ } cmu_clock_t; /** * @brief PLL1 output clock */ -typedef enum -{ - CMU_PLL1_OUTPUT_32M = 0x0, /**< x8 (32MHz) */ - CMU_PLL1_OUTPUT_48M = 0x1, /**< x12 (48MHz) */ +typedef enum { + CMU_PLL1_OUTPUT_36M = 0x0, /**< x9 (36MHz) */ + CMU_PLL1_OUTPUT_48M = 0x1, /**< x12 (48MHz) */ +#if defined(ES32F36xx) || defined(ES32F39xx) + CMU_PLL1_OUTPUT_72M = 0x2, /**< x18 (72MHz) */ + CMU_PLL1_OUTPUT_96M = 0x3, /**< x24 (96MHz) */ +#endif } cmu_pll1_output_t; /** * @brief PLL1 referance clock */ -typedef enum -{ - CMU_PLL1_INPUT_HRC_6 = 0x0, /**< HRC / 6 */ - CMU_PLL1_INPUT_PLL2 = 0x1, /**< PLL2 */ - CMU_PLL1_INPUT_HOSC = 0x2, /**< HOSC / 1 */ - CMU_PLL1_INPUT_HOSC_2 = 0x3, /**< HOSC / 2 */ - CMU_PLL1_INPUT_HOSC_3 = 0x4, /**< HOSC / 3 */ - CMU_PLL1_INPUT_HOSC_4 = 0x5, /**< HOSC / 4 */ - CMU_PLL1_INPUT_HOSC_5 = 0x6, /**< HOSC / 5 */ - CMU_PLL1_INPUT_HOSC_6 = 0x7, /**< HOSC / 6 */ +typedef enum { + CMU_PLL1_INPUT_HRC_6 = 0x0, /**< HRC / 6 */ + CMU_PLL1_INPUT_PLL2 = 0x1, /**< PLL2 */ + CMU_PLL1_INPUT_HOSC = 0x2, /**< HOSC / 1 */ + CMU_PLL1_INPUT_HOSC_2 = 0x3, /**< HOSC / 2 */ + CMU_PLL1_INPUT_HOSC_3 = 0x4, /**< HOSC / 3 */ + CMU_PLL1_INPUT_HOSC_4 = 0x5, /**< HOSC / 4 */ + CMU_PLL1_INPUT_HOSC_5 = 0x6, /**< HOSC / 5 */ + CMU_PLL1_INPUT_HOSC_6 = 0x7, /**< HOSC / 6 */ } cmu_pll1_input_t; /** * @brief HOSC range */ -typedef enum -{ - CMU_HOSC_2M = 0x0, - CMU_HOSC_4M = 0x1, - CMU_HOSC_8M = 0x2, - CMU_HOSC_16M = 0x3, - CMU_HOSC_24M = 0x4, +typedef enum { + CMU_HOSC_2M = 0x0, /**< 0~2MHz */ + CMU_HOSC_4M = 0x1, /**< 2~4MHz */ + CMU_HOSC_8M = 0x2, /**< 4~8MHz */ + CMU_HOSC_16M = 0x3, /**< 8~16MHz */ + CMU_HOSC_24M = 0x4, /**< 16~24MHz */ } cmu_hosc_range_t; /** * @brief Auto-calibrate input */ -typedef enum -{ - CMU_AUTO_CALIB_INPUT_LOSE = 0x0, - CMU_AUTO_CALIB_INPUT_HOSE = 0x1, +typedef enum { + CMU_AUTO_CALIB_INPUT_LOSE = 0x0, /**< LOSC */ + CMU_AUTO_CALIB_INPUT_HOSE = 0x1, /**< HOSC */ } cmu_auto_calib_input_t; /** * @brief Auto-calibrate output */ -typedef enum -{ - CMU_AUTO_CALIB_OUTPUT_24M = 0x0, - CMU_AUTO_CALIB_OUTPUT_2M = 0x1, +typedef enum { + CMU_AUTO_CALIB_OUTPUT_24M = 0x0, /**< 2MHz */ + CMU_AUTO_CALIB_OUTPUT_2M = 0x1, /**< 2MHz */ } cmu_auto_calib_output_t; /** * @brief Frequency division select bit */ -typedef enum -{ - CMU_DIV_1 = 0x0, /**< Division by 1 */ - CMU_DIV_2 = 0x1, /**< Division by 2 */ - CMU_DIV_4 = 0x2, /**< Division by 4 */ - CMU_DIV_8 = 0x3, /**< Division by 8 */ - CMU_DIV_16 = 0x4, /**< Division by 16 */ - CMU_DIV_32 = 0x5, /**< Division by 32 */ - CMU_DIV_64 = 0x6, /**< Division by 64 */ - CMU_DIV_128 = 0x7, /**< Division by 128 */ - CMU_DIV_256 = 0x8, /**< Division by 256 */ - CMU_DIV_512 = 0x9, /**< Division by 512 */ - CMU_DIV_1024 = 0xA, /**< Division by 1024 */ - CMU_DIV_2048 = 0xB, /**< Division by 2048 */ - CMU_DIV_4096 = 0xC, /**< Division by 4096 */ +typedef enum { + CMU_DIV_1 = 0x0, /**< Division by 1 */ + CMU_DIV_2 = 0x1, /**< Division by 2 */ + CMU_DIV_4 = 0x2, /**< Division by 4 */ + CMU_DIV_8 = 0x3, /**< Division by 8 */ + CMU_DIV_16 = 0x4, /**< Division by 16 */ + CMU_DIV_32 = 0x5, /**< Division by 32 */ + CMU_DIV_64 = 0x6, /**< Division by 64 */ + CMU_DIV_128 = 0x7, /**< Division by 128 */ + CMU_DIV_256 = 0x8, /**< Division by 256 */ + CMU_DIV_512 = 0x9, /**< Division by 512 */ + CMU_DIV_1024 = 0xA, /**< Division by 1024 */ + CMU_DIV_2048 = 0xB, /**< Division by 2048 */ + CMU_DIV_4096 = 0xC, /**< Division by 4096 */ } cmu_div_t; /** * @brief Bus type */ -typedef enum -{ - CMU_HCLK_1 = 0x0, /**< AHB1 bus */ - CMU_SYS = 0x1, /**< SYS bus */ - CMU_PCLK_1 = 0x2, /**< APB1 bus */ - CMU_PCLK_2 = 0x3, /**< APB2 bus */ +typedef enum { + CMU_HCLK_1 = 0x0, /**< AHB1 bus */ + CMU_HCLK_2 = 0x1, /**< AHB2 bus */ + CMU_SYS = 0x2, /**< SYS bus */ + CMU_PCLK_1 = 0x3, /**< APB1 bus */ + CMU_PCLK_2 = 0x4, /**< APB2 bus */ } cmu_bus_t; /** * @brief Output high clock select */ -typedef enum -{ - CMU_OUTPUT_HIGH_SEL_HOSC = 0x0, /**< Select HOSC */ - CMU_OUTPUT_HIGH_SEL_LOSC = 0x1, /**< Select LOSC */ - CMU_OUTPUT_HIGH_SEL_HRC = 0x2, /**< Select HRC */ - CMU_OUTPUT_HIGH_SEL_LRC = 0x3, /**< Select LRC */ - CMU_OUTPUT_HIGH_SEL_HOSM = 0x4, /**< Select HOSM */ - CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5, /**< Select PLL1 */ - CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6, /**< Select PLL2 */ - CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7, /**< Select SYSCLK */ +typedef enum { + CMU_OUTPUT_HIGH_SEL_HOSC = 0x0, /**< Select HOSC */ + CMU_OUTPUT_HIGH_SEL_LOSC = 0x1, /**< Select LOSC */ + CMU_OUTPUT_HIGH_SEL_HRC = 0x2, /**< Select HRC */ + CMU_OUTPUT_HIGH_SEL_LRC = 0x3, /**< Select LRC */ + CMU_OUTPUT_HIGH_SEL_HOSM = 0x4, /**< Select HOSM */ + CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5, /**< Select PLL1 */ + CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6, /**< Select PLL2 */ + CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7, /**< Select SYSCLK */ } cmu_output_high_sel_t; /** * @brief Output frequency division */ -typedef enum -{ - CMU_OUTPUT_DIV_1 = 0x0, /**< Division by 1 */ - CMU_OUTPUT_DIV_2 = 0x1, /**< Division by 2 */ - CMU_OUTPUT_DIV_4 = 0x2, /**< Division by 4 */ - CMU_OUTPUT_DIV_8 = 0x3, /**< Division by 8 */ - CMU_OUTPUT_DIV_16 = 0x4, /**< Division by 16 */ - CMU_OUTPUT_DIV_32 = 0x5, /**< Division by 32 */ - CMU_OUTPUT_DIV_64 = 0x6, /**< Division by 64 */ - CMU_OUTPUT_DIV_128 = 0x7, /**< Division by 128 */ +typedef enum { + CMU_OUTPUT_DIV_1 = 0x0, /**< Division by 1 */ + CMU_OUTPUT_DIV_2 = 0x1, /**< Division by 2 */ + CMU_OUTPUT_DIV_4 = 0x2, /**< Division by 4 */ + CMU_OUTPUT_DIV_8 = 0x3, /**< Division by 8 */ + CMU_OUTPUT_DIV_16 = 0x4, /**< Division by 16 */ + CMU_OUTPUT_DIV_32 = 0x5, /**< Division by 32 */ + CMU_OUTPUT_DIV_64 = 0x6, /**< Division by 64 */ + CMU_OUTPUT_DIV_128 = 0x7, /**< Division by 128 */ } cmu_output_high_div_t; /** * @brief Output low clock select */ -typedef enum -{ - CMU_OUTPUT_LOW_SEL_LOSC = 0x0, /**< Select LOSC */ - CMU_OUTPUT_LOW_SEL_LRC = 0x1, /**< Select LRC */ - CMU_OUTPUT_LOW_SEL_LOSM = 0x2, /**< Select LOSM */ - CMU_OUTPUT_LOW_SEL_BUZZ = 0x3, /**< Select BUZZ */ - CMU_OUTPUT_LOW_SEL_ULRC = 0x4, /**< Select ULRC */ +typedef enum { + CMU_OUTPUT_LOW_SEL_LOSC = 0x0, /**< Select LOSC */ + CMU_OUTPUT_LOW_SEL_LRC = 0x1, /**< Select LRC */ + CMU_OUTPUT_LOW_SEL_LOSM = 0x2, /**< Select LOSM */ + CMU_OUTPUT_LOW_SEL_BUZZ = 0x3, /**< Select BUZZ */ + CMU_OUTPUT_LOW_SEL_ULRC = 0x4, /**< Select ULRC */ } cmu_output_low_sel_t; /** * @brief BUZZ frequency division */ -typedef enum -{ - CMU_BUZZ_DIV_2 = 0x0, /**< Division by 2 */ - CMU_BUZZ_DIV_4 = 0x1, /**< Division by 4 */ - CMU_BUZZ_DIV_8 = 0x2, /**< Division by 8 */ - CMU_BUZZ_DIV_16 = 0x3, /**< Division by 16 */ - CMU_BUZZ_DIV_32 = 0x4, /**< Division by 32 */ - CMU_BUZZ_DIV_64 = 0x5, /**< Division by 64 */ - CMU_BUZZ_DIV_128 = 0x6, /**< Division by 128 */ - CMU_BUZZ_DIV_256 = 0x7, /**< Division by 256 */ +typedef enum { + CMU_BUZZ_DIV_2 = 0x0, /**< Division by 2 */ + CMU_BUZZ_DIV_4 = 0x1, /**< Division by 4 */ + CMU_BUZZ_DIV_8 = 0x2, /**< Division by 8 */ + CMU_BUZZ_DIV_16 = 0x3, /**< Division by 16 */ + CMU_BUZZ_DIV_32 = 0x4, /**< Division by 32 */ + CMU_BUZZ_DIV_64 = 0x5, /**< Division by 64 */ + CMU_BUZZ_DIV_128 = 0x6, /**< Division by 128 */ + CMU_BUZZ_DIV_256 = 0x7, /**< Division by 256 */ } cmu_buzz_div_t; /** * @brief Low power peripheral clock select */ -typedef enum -{ - CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0, /**< Select PCLK2 */ - CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1, /**< Select PLL1 */ - CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2, /**< Select PLL2 */ - CMU_LP_PERH_CLOCK_SEL_HRC = 0x3, /**< Select HRC */ - CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4, /**< Select HOSC */ - CMU_LP_PERH_CLOCK_SEL_LRC = 0x5, /**< Select LRC */ - CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6, /**< Select LOSC */ - CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7, /**< Select ULRC */ - CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8, /**< Select HRC down to 1MHz */ - CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9, /**< Select HOSC down to 1MHz */ - CMU_LP_PERH_CLOCK_SEL_LOSM = 0xA, /**< Select LOSM */ - CMU_LP_PERH_CLOCK_SEL_HOSM = 0xB, /**< Select HOSM */ +typedef enum { + CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0, /**< Select PCLK2 */ + CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1, /**< Select PLL1 */ + CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2, /**< Select PLL2 */ + CMU_LP_PERH_CLOCK_SEL_HRC = 0x3, /**< Select HRC */ + CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4, /**< Select HOSC */ + CMU_LP_PERH_CLOCK_SEL_LRC = 0x5, /**< Select LRC */ + CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6, /**< Select LOSC */ + CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7, /**< Select ULRC */ + CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8, /**< Select HRC down to 1MHz */ + CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9, /**< Select HOSC down to 1MHz */ + CMU_LP_PERH_CLOCK_SEL_LOSM = 0xA, /**< Select LOSM */ + CMU_LP_PERH_CLOCK_SEL_HOSM = 0xB, /**< Select HOSM */ } cmu_lp_perh_clock_sel_t; /** * @brief LCD clock select */ -typedef enum -{ - CMU_LCD_SEL_LOSM = 0x0, /**< Select LOSM */ - CMU_LCD_SEL_LOSC = 0x1, /**< Select LOSC */ - CMU_LCD_SEL_LRC = 0x2, /**< Select LRC */ - CMU_LCD_SEL_ULRC = 0x3, /**< Select ULRC */ - CMU_LCD_SEL_HRC_1M = 0x4, /**< Select HRC down to 1MHz */ - CMU_LCD_SEL_HOSC_1M = 0x5, /**< Select HOSC down to 1MHz */ +typedef enum { + CMU_LCD_SEL_LOSM = 0x0, /**< Select LOSM */ + CMU_LCD_SEL_LOSC = 0x1, /**< Select LOSC */ + CMU_LCD_SEL_LRC = 0x2, /**< Select LRC */ + CMU_LCD_SEL_ULRC = 0x3, /**< Select ULRC */ + CMU_LCD_SEL_HRC_1M = 0x4, /**< Select HRC down to 1MHz */ + CMU_LCD_SEL_HOSC_1M = 0x5, /**< Select HOSC down to 1MHz */ } cmu_lcd_clock_sel_t; +/** + * @brief QSPI clock select + */ +typedef enum { + CMU_QSPI_CLOCK_SEL_PCLK1 = 0x0, /**< Select PCLK1 */ + CMU_QSPI_CLOCK_SEL_HCLK2 = 0x1, /**< Select HCLK2 */ + CMU_QSPI_CLOCK_SEL_HRC = 0x2, /**< Select HRC */ + CMU_QSPI_CLOCK_SEL_HOSC = 0x3, /**< Select HOSC */ + CMU_QSPI_CLOCK_SEL_PLL1 = 0x4, /**< Select PLL1 */ + CMU_QSPI_CLOCK_SEL_HOSM = 0x5, /**< Select HOSC security management */ +} cmu_qspi_clock_sel_t; + +/** + * @brief USB clock select + */ +typedef enum { + CMU_USB_CLOCK_SEL_HOSC = 0x0, /**< Select HOSC */ + CMU_USB_CLOCK_SEL_HRC = 0x1, /**< Select HRC */ + CMU_USB_CLOCK_SEL_PCLK1 = 0x2, /**< Select PCLK1 */ + CMU_USB_CLOCK_SEL_PLL1 = 0x3, /**< Select PLL1 */ + CMU_USB_CLOCK_SEL_HOSM = 0x4, /**< Select HOSC security management */ +} cmu_usb_clock_sel_t; + +/** + * @brief USB clock division + */ +typedef enum { + CMU_USB_DIV_1 = 0x0, /**< Division by 1 */ + CMU_USB_DIV_2 = 0x1, /**< Division by 2 */ + CMU_USB_DIV_4 = 0x2, /**< Division by 4 */ + CMU_USB_DIV_8 = 0x3, /**< Division by 8 */ + CMU_USB_DIV_16 = 0x4, /**< Division by 16 */ + CMU_USB_DIV_32 = 0x5, /**< Division by 32 */ + CMU_USB_DIV_64 = 0x6, /**< Division by 64 */ + CMU_USB_DIV_128 = 0x7, /**< Division by 128 */ + CMU_USB_DIV_256 = 0x8, /**< Division by 256 */ + CMU_USB_DIV_512 = 0x9, /**< Division by 512 */ + CMU_USB_DIV_1024 = 0xA, /**< Division by 1024 */ + CMU_USB_DIV_2048 = 0xB, /**< Division by 2048 */ + CMU_USB_DIV_4096 = 0xC, /**< Division by 4096 */ +} cmu_usb_div_t; + /** * @brief Peripheral clock enable/disable */ -typedef enum -{ - CMU_PERH_GPIO = (1U << 0), /**< GPIO */ - CMU_PERH_CRC = (1U << 1), /**< CRC */ - CMU_PERH_CALC = (1U << 2), /**< CALC */ - CMU_PERH_CRYPT = (1U << 3), /**< CRYPT */ - CMU_PERH_TRNG = (1U << 4), /**< TRNG */ - CMU_PERH_PIS = (1U << 5), /**< PIS */ - CMU_PERH_TIM0 = (1U << 0) | (1U << 27), /**< TIM0 */ - CMU_PERH_TIM1 = (1U << 1) | (1U << 27), /**< TIM1 */ - CMU_PERH_TIM2 = (1U << 2) | (1U << 27), /**< TIM2 */ - CMU_PERH_TIM3 = (1U << 3) | (1U << 27), /**< TIM3 */ - CMU_PERH_TIM4 = (1U << 4) | (1U << 27), /**< TIM4 */ - CMU_PERH_TIM5 = (1U << 5) | (1U << 27), /**< TIM5 */ - CMU_PERH_TIM6 = (1U << 6) | (1U << 27), /**< TIM6 */ - CMU_PERH_TIM7 = (1U << 7) | (1U << 27), /**< TIM7 */ - CMU_PERH_UART0 = (1U << 8) | (1U << 27), /**< UART0 */ - CMU_PERH_UART1 = (1U << 9) | (1U << 27), /**< UART1 */ - CMU_PERH_UART2 = (1U << 10) | (1U << 27), /**< UART2 */ - CMU_PERH_UART3 = (1U << 11) | (1U << 27), /**< UART3 */ - CMU_PERH_USART0 = (1U << 12) | (1U << 27), /**< USART0 */ - CMU_PERH_USART1 = (1U << 13) | (1U << 27), /**< USART1 */ - CMU_PERH_SPI0 = (1U << 16) | (1U << 27), /**< SPI0 */ - CMU_PERH_SPI1 = (1U << 17) | (1U << 27), /**< SPI1 */ - CMU_PERH_SPI2 = (1U << 18) | (1U << 27), /**< SPI2 */ - CMU_PERH_I2C0 = (1U << 20) | (1U << 27), /**< I2C0 */ - CMU_PERH_I2C1 = (1U << 21) | (1U << 27), /**< I2C1 */ - CMU_PERH_CAN = (1U << 24) | (1U << 27), /**< CAN */ - CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28), /**< LPTIM0 */ - CMU_PERH_LPUART0 = (1U << 2) | (1U << 28), /**< LPUART0 */ - CMU_PERH_ADC0 = (1U << 4) | (1U << 28), /**< ADC0 */ - CMU_PERH_ADC1 = (1U << 5) | (1U << 28), /**< ADC1 */ - CMU_PERH_ACMP0 = (1U << 6) | (1U << 28), /**< ACMP0 */ - CMU_PERH_ACMP1 = (1U << 7) | (1U << 28), /**< ACMP1 */ - CMU_PERH_OPAMP = (1U << 8) | (1U << 28), /**< OPAMP */ - CMU_PERH_DAC0 = (1U << 9) | (1U << 28), /**< DAC0 */ - CMU_PERH_WWDT = (1U << 12) | (1U << 28), /**< WWDT */ - CMU_PERH_LCD = (1U << 13) | (1U << 28), /**< LCD */ - CMU_PERH_IWDT = (1U << 14) | (1U << 28), /**< IWDT */ - CMU_PERH_RTC = (1U << 15) | (1U << 28), /**< RTC */ - CMU_PERH_TEMP = (1U << 16) | (1U << 28), /**< TEMP */ - CMU_PERH_BKPC = (1U << 17) | (1U << 28), /**< BKPC */ - CMU_PERH_BKRPAM = (1U << 18) | (1U << 28), /**< BKPRAM */ - CMU_PERH_DBGC = (1U << 19) | (1U << 28), /**< DBGC */ - CMU_PERH_ALL = (0x7FFFFFFF), /**< ALL */ +typedef enum { + CMU_PERH_GPIO = (1U << 0), /**< GPIO */ + CMU_PERH_CRC = (1U << 1), /**< CRC */ + CMU_PERH_CALC = (1U << 2), /**< CALC */ + CMU_PERH_CRYPT = (1U << 3), /**< CRYPT */ + CMU_PERH_TRNG = (1U << 4), /**< TRNG */ + CMU_PERH_PIS = (1U << 5), /**< PIS */ + CMU_PERH_EBI = (1U << 6), /**< EBI */ + CMU_PERH_QSPI_H = (1U << 7), /**< QSPI AHB */ + CMU_PERH_DMA = (1U << 8), /**< DMA */ + CMU_PERH_USB = (1U << 10), /**< USB */ + CMU_PERH_ECC = (1U << 11), /**< ECC */ + CMU_PERH_TIM0 = (1U << 0) | (1U << 27), /**< TIM0 */ + CMU_PERH_TIM1 = (1U << 1) | (1U << 27), /**< TIM1 */ + CMU_PERH_TIM2 = (1U << 2) | (1U << 27), /**< TIM2 */ + CMU_PERH_TIM3 = (1U << 3) | (1U << 27), /**< TIM3 */ + CMU_PERH_TIM4 = (1U << 4) | (1U << 27), /**< TIM4 */ + CMU_PERH_TIM5 = (1U << 5) | (1U << 27), /**< TIM5 */ + CMU_PERH_TIM6 = (1U << 6) | (1U << 27), /**< TIM6 */ + CMU_PERH_TIM7 = (1U << 7) | (1U << 27), /**< TIM7 */ + CMU_PERH_UART0 = (1U << 8) | (1U << 27), /**< UART0 */ + CMU_PERH_UART1 = (1U << 9) | (1U << 27), /**< UART1 */ + CMU_PERH_UART2 = (1U << 10) | (1U << 27), /**< UART2 */ + CMU_PERH_UART3 = (1U << 11) | (1U << 27), /**< UART3 */ + CMU_PERH_UART4 = (1U << 12) | (1U << 27), /**< UART4 */ + CMU_PERH_UART5 = (1U << 13) | (1U << 27), /**< UART5 */ + CMU_PERH_SPI0 = (1U << 16) | (1U << 27), /**< SPI0 */ + CMU_PERH_SPI1 = (1U << 17) | (1U << 27), /**< SPI1 */ + CMU_PERH_SPI2 = (1U << 18) | (1U << 27), /**< SPI2 */ + CMU_PERH_I2C0 = (1U << 20) | (1U << 27), /**< I2C0 */ + CMU_PERH_I2C1 = (1U << 21) | (1U << 27), /**< I2C1 */ + CMU_PERH_CAN = (1U << 24) | (1U << 27), /**< CAN */ + CMU_PERH_QSPI_P = (1U << 25) | (1U << 27), /**< QSPI APB */ + CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28), /**< LPTIM0 */ + CMU_PERH_LPUART0 = (1U << 2) | (1U << 28), /**< LPUART0 */ + CMU_PERH_ADC0 = (1U << 4) | (1U << 28), /**< ADC0 */ + CMU_PERH_ADC1 = (1U << 5) | (1U << 28), /**< ADC1 */ + CMU_PERH_ACMP0 = (1U << 6) | (1U << 28), /**< ACMP0 */ + CMU_PERH_ACMP1 = (1U << 7) | (1U << 28), /**< ACMP1 */ + CMU_PERH_OPAMP = (1U << 8) | (1U << 28), /**< OPAMP */ + CMU_PERH_DAC0 = (1U << 9) | (1U << 28), /**< DAC0 */ + CMU_PERH_ACMP2 = (1U << 11) | (1U << 28), /**< ACMP2 */ + CMU_PERH_WWDT = (1U << 12) | (1U << 28), /**< WWDT */ + CMU_PERH_LCD = (1U << 13) | (1U << 28), /**< LCD */ + CMU_PERH_IWDT = (1U << 14) | (1U << 28), /**< IWDT */ + CMU_PERH_RTC = (1U << 15) | (1U << 28), /**< RTC */ + CMU_PERH_TSENSE = (1U << 16) | (1U << 28), /**< TSENSE */ + CMU_PERH_BKPC = (1U << 17) | (1U << 28), /**< BKPC */ + CMU_PERH_BKRPAM = (1U << 18) | (1U << 28), /**< BKPRAM */ + CMU_PERH_DBGC = (1U << 19) | (1U << 28), /**< DBGC */ + CMU_PERH_ALL = (0x7FFFFFFF), /**< ALL */ } cmu_perh_t; /** * @brief CMU interrupt type */ -typedef enum -{ - CMU_LOSC_STOP = 0x0, /**< LOSC STOP INTERRUPT */ - CMU_HOSC_STOP = 0x1, /**< HOSC STOP INTERRUPT */ - CMU_PLL1_UNLOCK = 0x2, /**< PLL1 UNLOCK INTERRUPT */ - CMU_LOSC_START = 0x3, /**< LOSC START INTERRUPT */ - CMU_HOSC_START = 0x4, /**< HOSC START INTERRUPT */ +typedef enum { + CMU_LOSC_STOP = 0x0, /**< LOSC STOP INTERRUPT */ + CMU_HOSC_STOP = 0x1, /**< HOSC STOP INTERRUPT */ + CMU_PLL1_UNLOCK = 0x2, /**< PLL1 UNLOCK INTERRUPT */ + CMU_LOSC_START = 0x3, /**< LOSC START INTERRUPT */ + CMU_HOSC_START = 0x4, /**< HOSC START INTERRUPT */ } cmu_security_t; /** * @brief CMU clock state type */ -typedef enum -{ - CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */ - CMU_CLOCK_STATE_LOSCACT = (1U << 1), /**< LOSC active */ - CMU_CLOCK_STATE_HRCACT = (1U << 2), /**< HRC active */ - CMU_CLOCK_STATE_LRCACT = (1U << 3), /**< LRC active */ - CMU_CLOCK_STATE_ULRCACT = (1U << 4), /**< ULRC active */ - CMU_CLOCK_STATE_PLLACT = (1U << 8), /**< PLL active */ - CMU_CLOCK_STATE_HOSCRDY = (1U << 16), /**< HOSC ready */ - CMU_CLOCK_STATE_LOSCRDY = (1U << 17), /**< LOSC ready */ - CMU_CLOCK_STATE_HRCRDY = (1U << 18), /**< HRC ready */ - CMU_CLOCK_STATE_LRCRDY = (1U << 19), /**< LRC ready */ - CMU_CLOCK_STATE_PLLRDY = (1U << 24), /**< PLL ready */ +typedef enum { + CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */ + CMU_CLOCK_STATE_LOSCACT = (1U << 1), /**< LOSC active */ + CMU_CLOCK_STATE_HRCACT = (1U << 2), /**< HRC active */ + CMU_CLOCK_STATE_LRCACT = (1U << 3), /**< LRC active */ + CMU_CLOCK_STATE_ULRCACT = (1U << 4), /**< ULRC active */ + CMU_CLOCK_STATE_PLL1ACT = (1U << 8), /**< PLL1 active */ + CMU_CLOCK_STATE_PLL2ACT = (1U << 9), /**< PLL2 active */ + CMU_CLOCK_STATE_HOSCRDY = (1U << 16), /**< HOSC ready */ + CMU_CLOCK_STATE_LOSCRDY = (1U << 17), /**< LOSC ready */ + CMU_CLOCK_STATE_HRCRDY = (1U << 18), /**< HRC ready */ + CMU_CLOCK_STATE_LRCRDY = (1U << 19), /**< LRC ready */ + CMU_CLOCK_STATE_PLL1RDY = (1U << 24), /**< PLL1 ready */ + CMU_CLOCK_STATE_PLL2RDY = (1U << 25), /**< PLL2 ready */ } cmu_clock_state_t; + +/** + * @brief Stop1 clock select type + */ +typedef enum { + CMU_STOP1_CLOCK_LRC = 0x0, /**< LRC */ + CMU_STOP1_CLOCK_HRC_24M = 0x1, /**< HRC 24MHz */ + CMU_STOP1_CLOCK_HRC_2M = 0x2, /**< HRC 2MHz */ + CMU_STOP1_CLOCK_HRC_1M = 0x3, /**< HRC divides to 1MHz */ + CMU_STOP1_CLOCK_HOSC = 0x4, /**< HOSC */ + CMU_STOP1_CLOCK_HOSC_1M = 0x5, /**< HOSC divides to 1MHz */ + CMU_STOP1_CLOCK_HOSCM = 0x6, /**< HOSC security management */ +} cmu_stop1_clock_t; + /** * @} */ @@ -403,14 +492,16 @@ typedef enum * @defgroup CMU_Private_Macros CMU Private Macros * @{ */ -#define IS_CMU_CLOCK(x) (((x) == CMU_CLOCK_HRC) || \ +#define IS_CMU_CLOCK(x) (((x) == CMU_CLOCK_HRC) || \ ((x) == CMU_CLOCK_LRC) || \ ((x) == CMU_CLOCK_LOSC) || \ ((x) == CMU_CLOCK_PLL1) || \ ((x) == CMU_CLOCK_HOSC)) -#define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_32M) || \ - ((x) == CMU_PLL1_OUTPUT_48M)) -#define IS_CMU_PLL1_INPUT(x) (((x) == CMU_PLL1_INPUT_HRC_6) || \ +#define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_36M) || \ + ((x) == CMU_PLL1_OUTPUT_48M) || \ + ((x) == CMU_PLL1_OUTPUT_72M) || \ + ((x) == CMU_PLL1_OUTPUT_96M)) +#define IS_CMU_PLL1_INPUT(x) (((x) == CMU_PLL1_INPUT_HRC_6) || \ ((x) == CMU_PLL1_INPUT_PLL2) || \ ((x) == CMU_PLL1_INPUT_HOSC) || \ ((x) == CMU_PLL1_INPUT_HOSC_2) || \ @@ -418,12 +509,12 @@ typedef enum ((x) == CMU_PLL1_INPUT_HOSC_4) || \ ((x) == CMU_PLL1_INPUT_HOSC_5) || \ ((x) == CMU_PLL1_INPUT_HOSC_6)) -#define IS_CMU_HOSC_RANGE(x) (((x) == CMU_HOSC_2M) || \ +#define IS_CMU_HOSC_RANGE(x) (((x) == CMU_HOSC_2M) || \ ((x) == CMU_HOSC_4M) || \ ((x) == CMU_HOSC_8M) || \ ((x) == CMU_HOSC_16M) || \ ((x) == CMU_HOSC_24M)) -#define IS_CMU_DIV(x) (((x) == CMU_DIV_1) || \ +#define IS_CMU_DIV(x) (((x) == CMU_DIV_1) || \ ((x) == CMU_DIV_2) || \ ((x) == CMU_DIV_4) || \ ((x) == CMU_DIV_8) || \ @@ -436,11 +527,12 @@ typedef enum ((x) == CMU_DIV_1024) || \ ((x) == CMU_DIV_2048) || \ ((x) == CMU_DIV_4096)) -#define IS_CMU_BUS(x) (((x) == CMU_HCLK_1) || \ +#define IS_CMU_BUS(x) (((x) == CMU_HCLK_1) || \ + ((x) == CMU_HCLK_2) || \ ((x) == CMU_SYS) || \ ((x) == CMU_PCLK_1) || \ ((x) == CMU_PCLK_2)) -#define IS_CMU_OUTPUT_HIGH_SEL(x) (((x) == CMU_OUTPUT_HIGH_SEL_HOSC) || \ +#define IS_CMU_OUTPUT_HIGH_SEL(x) (((x) == CMU_OUTPUT_HIGH_SEL_HOSC) || \ ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \ ((x) == CMU_OUTPUT_HIGH_SEL_HRC) || \ ((x) == CMU_OUTPUT_HIGH_SEL_LRC) || \ @@ -448,7 +540,7 @@ typedef enum ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \ ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \ ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK)) -#define IS_CMU_OUTPUT_HIGH_DIV(x) (((x) == CMU_OUTPUT_DIV_1) || \ +#define IS_CMU_OUTPUT_HIGH_DIV(x) (((x) == CMU_OUTPUT_DIV_1) || \ ((x) == CMU_OUTPUT_DIV_2) || \ ((x) == CMU_OUTPUT_DIV_4) || \ ((x) == CMU_OUTPUT_DIV_8) || \ @@ -456,16 +548,16 @@ typedef enum ((x) == CMU_OUTPUT_DIV_32) || \ ((x) == CMU_OUTPUT_DIV_64) || \ ((x) == CMU_OUTPUT_DIV_128)) -#define IS_CMU_OUTPUT_LOW_SEL(x) (((x) == CMU_OUTPUT_LOW_SEL_LOSC) || \ +#define IS_CMU_OUTPUT_LOW_SEL(x) (((x) == CMU_OUTPUT_LOW_SEL_LOSC) || \ ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \ ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \ ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \ ((x) == CMU_OUTPUT_LOW_SEL_ULRC)) -#define IS_CMU_AUTO_CALIB_INPUT(x) (((x) == CMU_AUTO_CALIB_INPUT_LOSE) || \ +#define IS_CMU_AUTO_CALIB_INPUT(x) (((x) == CMU_AUTO_CALIB_INPUT_LOSE) || \ ((x) == CMU_AUTO_CALIB_INPUT_HOSE)) -#define IS_CMU_AUTO_CALIB_OUTPUT(x) (((x) == CMU_AUTO_CALIB_OUTPUT_24M) || \ +#define IS_CMU_AUTO_CALIB_OUTPUT(x) (((x) == CMU_AUTO_CALIB_OUTPUT_24M) || \ ((x) == CMU_AUTO_CALIB_OUTPUT_2M)) -#define IS_CMU_BUZZ_DIV(x) (((x) == CMU_BUZZ_DIV_2) || \ +#define IS_CMU_BUZZ_DIV(x) (((x) == CMU_BUZZ_DIV_2) || \ ((x) == CMU_BUZZ_DIV_4) || \ ((x) == CMU_BUZZ_DIV_8) || \ ((x) == CMU_BUZZ_DIV_16) || \ @@ -473,7 +565,7 @@ typedef enum ((x) == CMU_BUZZ_DIV_64) || \ ((x) == CMU_BUZZ_DIV_128) || \ ((x) == CMU_BUZZ_DIV_256)) -#define IS_CMU_LP_PERH_CLOCK_SEL(x) (((x) == CMU_LP_PERH_CLOCK_SEL_PCLK2) || \ +#define IS_CMU_LP_PERH_CLOCK_SEL(x) (((x) == CMU_LP_PERH_CLOCK_SEL_PCLK2) || \ ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1) || \ ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2) || \ ((x) == CMU_LP_PERH_CLOCK_SEL_HRC) || \ @@ -485,18 +577,47 @@ typedef enum ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \ ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM) || \ ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM)) -#define IS_CMU_LCD_CLOCK_SEL(x) (((x) == CMU_LCD_SEL_LOSM) || \ +#define IS_CMU_LCD_CLOCK_SEL(x) (((x) == CMU_LCD_SEL_LOSM) || \ ((x) == CMU_LCD_SEL_LOSC) || \ ((x) == CMU_LCD_SEL_LRC) || \ ((x) == CMU_LCD_SEL_ULRC) || \ ((x) == CMU_LCD_SEL_HRC_1M) || \ ((x) == CMU_LCD_SEL_HOSC_1M)) -#define IS_CMU_PERH(x) (((x) == CMU_PERH_GPIO) || \ +#define IS_CMU_QSPI_CLOCK_SEL(x) (((x) == CMU_QSPI_CLOCK_SEL_PCLK1) || \ + ((x) == CMU_QSPI_CLOCK_SEL_HCLK2) || \ + ((x) == CMU_QSPI_CLOCK_SEL_HRC) || \ + ((x) == CMU_QSPI_CLOCK_SEL_HOSC) || \ + ((x) == CMU_QSPI_CLOCK_SEL_PLL1) || \ + ((x) == CMU_QSPI_CLOCK_SEL_HOSM)) +#define IS_CMU_USB_CLOCK_SEL(x) (((x) == CMU_USB_CLOCK_SEL_HOSC) || \ + ((x) == CMU_USB_CLOCK_SEL_HRC) || \ + ((x) == CMU_USB_CLOCK_SEL_PCLK1) || \ + ((x) == CMU_USB_CLOCK_SEL_PLL1) || \ + ((x) == CMU_USB_CLOCK_SEL_HOSM)) +#define IS_CMU_USB_DIV(x) (((x) == CMU_USB_DIV_1) || \ + ((x) == CMU_USB_DIV_2) || \ + ((x) == CMU_USB_DIV_4) || \ + ((x) == CMU_USB_DIV_8) || \ + ((x) == CMU_USB_DIV_16) || \ + ((x) == CMU_USB_DIV_32) || \ + ((x) == CMU_USB_DIV_64) || \ + ((x) == CMU_USB_DIV_128) || \ + ((x) == CMU_USB_DIV_256) || \ + ((x) == CMU_USB_DIV_512) || \ + ((x) == CMU_USB_DIV_1024) || \ + ((x) == CMU_USB_DIV_2048) || \ + ((x) == CMU_USB_DIV_4096)) +#define IS_CMU_PERH(x) (((x) == CMU_PERH_GPIO) || \ ((x) == CMU_PERH_CRC) || \ ((x) == CMU_PERH_CALC) || \ ((x) == CMU_PERH_CRYPT) || \ ((x) == CMU_PERH_TRNG) || \ ((x) == CMU_PERH_PIS) || \ + ((x) == CMU_PERH_EBI) || \ + ((x) == CMU_PERH_QSPI_H) || \ + ((x) == CMU_PERH_DMA) || \ + ((x) == CMU_PERH_USB) || \ + ((x) == CMU_PERH_ECC) || \ ((x) == CMU_PERH_TIM0) || \ ((x) == CMU_PERH_TIM1) || \ ((x) == CMU_PERH_TIM2) || \ @@ -509,14 +630,15 @@ typedef enum ((x) == CMU_PERH_UART1) || \ ((x) == CMU_PERH_UART2) || \ ((x) == CMU_PERH_UART3) || \ - ((x) == CMU_PERH_USART0) || \ - ((x) == CMU_PERH_USART1) || \ + ((x) == CMU_PERH_UART4) || \ + ((x) == CMU_PERH_UART5) || \ ((x) == CMU_PERH_SPI0) || \ ((x) == CMU_PERH_SPI1) || \ ((x) == CMU_PERH_SPI2) || \ ((x) == CMU_PERH_I2C0) || \ ((x) == CMU_PERH_I2C1) || \ ((x) == CMU_PERH_CAN) || \ + ((x) == CMU_PERH_QSPI_P) || \ ((x) == CMU_PERH_LPTIM0) || \ ((x) == CMU_PERH_LPUART0) || \ ((x) == CMU_PERH_ADC0) || \ @@ -525,26 +647,36 @@ typedef enum ((x) == CMU_PERH_ACMP1) || \ ((x) == CMU_PERH_OPAMP) || \ ((x) == CMU_PERH_DAC0) || \ + ((x) == CMU_PERH_ACMP2) || \ ((x) == CMU_PERH_WWDT) || \ ((x) == CMU_PERH_LCD) || \ ((x) == CMU_PERH_IWDT) || \ ((x) == CMU_PERH_RTC) || \ - ((x) == CMU_PERH_TEMP) || \ + ((x) == CMU_PERH_TSENSE) || \ ((x) == CMU_PERH_BKPC) || \ ((x) == CMU_PERH_BKRPAM ) || \ ((x) == CMU_PERH_DBGC) || \ ((x) == CMU_PERH_ALL)) -#define IS_CMU_CLOCK_STATE(x) (((x) == CMU_CLOCK_STATE_HOSCACT) || \ +#define IS_CMU_CLOCK_STATE(x) (((x) == CMU_CLOCK_STATE_HOSCACT) || \ ((x) == CMU_CLOCK_STATE_LOSCACT) || \ - ((x) == CMU_CLOCK_STATE_HRCACT) || \ - ((x) == CMU_CLOCK_STATE_LRCACT) || \ - ((x) == CMU_CLOCK_STATE_ULRCACT) || \ - ((x) == CMU_CLOCK_STATE_PLLACT) || \ - ((x) == CMU_CLOCK_STATE_HOSCRDY) || \ - ((x) == CMU_CLOCK_STATE_LOSCRDY) || \ - ((x) == CMU_CLOCK_STATE_HRCRDY) || \ - ((x) == CMU_CLOCK_STATE_LRCRDY) || \ - ((x) == CMU_CLOCK_STATE_PLLRDY)) + ((x) == CMU_CLOCK_STATE_HRCACT) || \ + ((x) == CMU_CLOCK_STATE_LRCACT) || \ + ((x) == CMU_CLOCK_STATE_ULRCACT) || \ + ((x) == CMU_CLOCK_STATE_PLL1ACT) || \ + ((x) == CMU_CLOCK_STATE_PLL2ACT) || \ + ((x) == CMU_CLOCK_STATE_HOSCRDY) || \ + ((x) == CMU_CLOCK_STATE_LOSCRDY) || \ + ((x) == CMU_CLOCK_STATE_HRCRDY) || \ + ((x) == CMU_CLOCK_STATE_LRCRDY) || \ + ((x) == CMU_CLOCK_STATE_PLL1RDY) || \ + ((x) == CMU_CLOCK_STATE_PLL2RDY)) +#define IS_CMU_STOP1_CLOCK(x) (((x) == CMU_STOP1_CLOCK_LRC) || \ + ((x) == CMU_STOP1_CLOCK_HRC_24M) || \ + ((x) == CMU_STOP1_CLOCK_HRC_2M) || \ + ((x) == CMU_STOP1_CLOCK_HRC_1M) || \ + ((x) == CMU_STOP1_CLOCK_HOSC) || \ + ((x) == CMU_STOP1_CLOCK_HOSC_1M) || \ + ((x) == CMU_STOP1_CLOCK_HOSCM)) /** * @} */ @@ -556,11 +688,10 @@ typedef enum * @{ */ /* System clock configure */ -ald_status_t cmu_clock_config_default(void); -ald_status_t cmu_clock_config(cmu_clock_t clk, uint32_t clock); -void cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output); -uint32_t cmu_get_clock(void); -int32_t cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output_t freq); +ald_status_t ald_cmu_clock_config_default(void); +ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock); +void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output); +uint32_t ald_cmu_get_clock(void); /** * @} */ @@ -569,11 +700,11 @@ int32_t cmu_auto_calib_clock(cmu_auto_calib_input_t input, cmu_auto_calib_output * @{ */ /* BUS division control */ -void cmu_div_config(cmu_bus_t bus, cmu_div_t div); -uint32_t cmu_get_hclk1_clock(void); -uint32_t cmu_get_sys_clock(void); -uint32_t cmu_get_pclk1_clock(void); -uint32_t cmu_get_pclk2_clock(void); +void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div); +uint32_t ald_cmu_get_hclk1_clock(void); +uint32_t ald_cmu_get_sys_clock(void); +uint32_t ald_cmu_get_pclk1_clock(void); +uint32_t ald_cmu_get_pclk2_clock(void); /** * @} */ @@ -582,11 +713,12 @@ uint32_t cmu_get_pclk2_clock(void); * @{ */ /* Clock safe configure */ -void cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status); -void cmu_losc_safe_config(type_func_t status); -void cmu_pll_safe_config(type_func_t status); -flag_status_t cmu_get_clock_state(cmu_clock_state_t sr); -void cmu_irq_cbk(cmu_security_t se); +void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status); +void ald_cmu_losc_safe_config(type_func_t status); +void ald_cmu_pll_safe_config(type_func_t status); +flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr); +void ald_cmu_irq_handler(void); +void ald_cmu_irq_cbk(cmu_security_t se); /** * @} */ @@ -595,9 +727,9 @@ void cmu_irq_cbk(cmu_security_t se); * @{ */ /* Clock output configure */ -void cmu_output_high_clock_config(cmu_output_high_sel_t sel, - cmu_output_high_div_t div, type_func_t status); -void cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status); +void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, + cmu_output_high_div_t div, type_func_t status); +void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status); /** * @} */ @@ -606,11 +738,14 @@ void cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status); * @{ */ /* Peripheral Clock configure */ -void cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status); -void cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock); -void cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock); -void cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock); -void cmu_perh_clock_config(cmu_perh_t perh, type_func_t status); +void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status); +void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock); +void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock); +void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock); +void ald_cmu_qspi_clock_select(cmu_qspi_clock_sel_t clock); +void ald_cmu_usb_clock_config(cmu_usb_clock_sel_t clock, cmu_usb_div_t div); +void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status); +void ald_cmu_stop1_clock_sel(cmu_stop1_clock_t clock); /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_conf.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_conf.h new file mode 100644 index 0000000000000000000000000000000000000000..1ee5597055dcfe314d81a470f332ed9d36ba74a2 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_conf.h @@ -0,0 +1,64 @@ +/** + ********************************************************************************* + * + * @file ald_conf.h + * @brief Enable/Disable the peripheral module. + * + * @version V1.0 + * @date 01 Jul 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + + +#ifndef __ALD_CONF_H__ +#define __ALD_CONF_H__ + + +#define ALD_DMA +#define ALD_GPIO +#define ALD_UART +#define ALD_LPUART +#define ALD_I2C +#define ALD_CMU +#define ALD_RMU +#define ALD_PMU +#define ALD_WDT +#define ALD_LCD +#define ALD_RTC +#define ALD_CAN +#define ALD_FLASH +#define ALD_ADC +#define ALD_CRC +#define ALD_CRYPT +#define ALD_TIMER +#define ALD_LPTIM +#define ALD_PIS +#define ALD_SPI +#define ALD_CALC +#define ALD_ACMP +#define ALD_OPAMP +#define ALD_TRNG +#define ALD_TSENSE +#define ALD_BKPC +#define ALD_DAC +#define ALD_IAP +#define ALD_I2S +#define ALD_ECC +#define ALD_NAND +#define ALD_QSPI +#define ALD_NOR +#define ALD_SRAM +#define ALD_USB + +#if defined(ALD_NAND) || defined(ALD_NOR) || defined(ALD_SRAM) +#define ALD_EBI +#endif + +#define TICK_INT_PRIORITY 3 + +#endif diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..f38e08f598eb7c56687450036e9decaa88c40573 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crc.h @@ -0,0 +1,196 @@ +/** + ********************************************************************************* + * + * @file ald_crc.h + * @brief Header file of CRC module driver. + * + * @version V1.0 + * @date 18 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_CRC_H__ +#define __ALD_CRC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @defgroup CRC_Public_Types CRC Public Types + * @{ + */ + +/** + * @brief CRC mode + */ +typedef enum { + CRC_MODE_CCITT = 0, /**< Ccitt */ + CRC_MODE_8 = 1, /**< Crc8 */ + CRC_MODE_16 = 2, /**< Crc16 */ + CRC_MODE_32 = 3, /**< Crc32 */ +} crc_mode_t; + +/** + * @brief CRC input length + */ +typedef enum { + CRC_LEN_AUTO = 0, /**< Auto */ + CRC_DATASIZE_8 = 1, /**< Byte */ + CRC_DATASIZE_16 = 2, /**< Half word */ + CRC_DATASIZE_32 = 3, /**< Word */ +} crc_datasize_t; + +/** + * @brief CRC whether write error or no + */ +typedef enum { + CRC_WERR_NO = 0, /**< No error */ + CRC_WERR_ERR = 1, /**< Error */ +} crc_werr_t; + +/** + * @brief CRC state structures definition + */ +typedef enum { + CRC_STATE_RESET = 0x0, /**< Peripheral is not initialized */ + CRC_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ + CRC_STATE_BUSY = 0x2, /**< An internal process is ongoing */ + CRC_STATE_ERROR = 0x4, /**< Error */ +} crc_state_t; + +/** + * @brief CRC init structure definition + */ +typedef struct { + crc_mode_t mode; /**< CRC mode */ + type_func_t data_rev; /**< CRC data reverse or no */ + type_func_t data_inv; /**< CRC data inverse or no */ + type_func_t chs_rev; /**< CRC check sum reverse or no */ + type_func_t chs_inv; /**< CRC check sum inverse or no */ + uint32_t seed; /**< CRC seed */ +} crc_init_t; + +/** + * @brief CRC Handle Structure definition + */ +typedef struct crc_handle_s { + CRC_TypeDef *perh; /**< Register base address */ + crc_init_t init; /**< CRC required parameters */ + uint8_t *cal_buf; /**< The pointer of preparing buffer */ + uint32_t *cal_res; /**< The pointer of result */ +#ifdef ALD_DMA + dma_handle_t hdma; /**< CRC DMA handle parameters */ +#endif + lock_state_t lock; /**< Locking object */ + crc_state_t state; /**< CRC operation state */ + + void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */ + void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */ +} crc_handle_t; +/** + * @} + */ + +/** @defgroup CRC_Public_Macros CRC Public Macros + * @{ + */ +#define CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) +#define CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) +#define CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK)) +#define CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) +#define CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) +#define CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK)) +/** + * @} + */ + +/** @defgroup CRC_Private_Macros CRC Private Macros + * @{ + */ +#define IS_CRC(x) ((x) == CRC) +#define IS_CRC_MODE(x) (((x) == CRC_MODE_CCITT) || \ + ((x) == CRC_MODE_8) || \ + ((x) == CRC_MODE_16) || \ + ((x) == CRC_MODE_32)) +/** + * @} + */ + +/** @addtogroup CRC_Public_Functions + * @{ + */ + +/** @addtogroup CRC_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_crc_init(crc_handle_t *hperh); +void ald_crc_reset(crc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup CRC_Public_Functions_Group2 + * @{ + */ +uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size); +uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size); +uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size); +/** + * @} + */ + +#ifdef ALD_DMA +/** @addtogroup CRC_Public_Functions_Group3 + * @{ + */ +ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_dma_pause(crc_handle_t *hperh); +ald_status_t ald_crc_dma_resume(crc_handle_t *hperh); +ald_status_t ald_crc_dma_stop(crc_handle_t *hperh); +/** + * @} + */ +#endif +/** @addtogroup CRC_Public_Functions_Group4 + * @{ + */ +crc_state_t ald_crc_get_state(crc_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_CRC_H__ */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h new file mode 100644 index 0000000000000000000000000000000000000000..9ba0fc438509d469330a653c0329abeecca668bf --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_crypt.h @@ -0,0 +1,326 @@ +/** + ********************************************************************************* + * + * @file ald_crypt.h + * @brief Header file of CRYPT module driver. + * + * @version V1.0 + * @date 19 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_CRYPT_H__ +#define __ALD_CRYPT_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CRYPT + * @{ + */ + +/** @defgroup CRYPT_Public_Types CRYPT Public Types + * @{ + */ + +/** + * @brief CRYPT encrypt or decrypt select + */ +typedef enum { + CRYPT_DECRYPT = 0, /**< Decrypt */ + CRYPT_ENCRYPT = 1, /**< Encrypt */ +} crypt_encs_t; + +/** + * @brief CRYPT aes key select + */ +typedef enum { + CRYPT_BITS_128 = 0, /**< 128bit key for aes */ + CRYPT_BITS_192 = 1, /**< 192bit key for aes */ + CRYPT_BITS_256 = 2, /**< 256bit key for aes */ +} crypt_aesks_t; + +/** + * @brief CRYPT mode select + */ +typedef enum { + CRYPT_MODE_ECB = 0, /**< ECB */ + CRYPT_MODE_CBC = 1, /**< CBC */ + CRYPT_MODE_CTR = 2, /**< CTR */ +} crypt_mode_t; + +/** + * @brief CRYPT data type + */ +typedef enum { + CRYPT_DATA_CHANGE_NO = 0, /**< No exchange */ + CRYPT_DATA_CHANGE_16 = 1, /**< 16bit exchange */ + CRYPT_DATA_CHANGE_8 = 2, /**< 8bit exchange */ + CRYPT_DATA_CHANGE_1 = 3, /**< 1bit exchange */ +} crypt_datatype_t; + +/** + * @brief CRYPT des key select + */ +typedef enum { + CRYPT_KEYS_2 = 0, /**< 2 key for des */ + CRYPT_KEYS_3 = 1, /**< 3 key for des */ + CRYPT_KEYS_1 = 2, /**< 1 key for des */ +} crypt_desks_t; + +/** + * @brief CRYPT crypt select + */ +typedef enum { + CRYPT_CRYSEL_AES = 0, /**< AES */ + CRYPT_CRYSEL_DES = 1, /**< DES */ +} crypt_crysel_t; + +/** + * @brief CRYPT interrupt + */ +typedef enum { + CRYPT_IT_IT = 0x80, /**< Interrupt */ +} crypt_it_t; + +/** + * @brief CRYPT interrupt flag + */ +typedef enum { + CRYPT_FLAG_AESIF = 0x1, /**< Aes flag */ + CRYPT_FLAG_DESIF = 0x2, /**< Des flag */ + CRYPT_FLAG_DONE = 0x100, /**< Complete flag */ +} crypt_flag_t; + +/** + * @brief CRYPT key select + */ +typedef enum { + CRYPT_AES_BITS_128 = 0x4, /**< 128bit key of aes */ + CRYPT_AES_BITS_192 = 0x6, /**< 192bit key of aes */ + CRYPT_AES_BITS_256 = 0x8, /**< 192bit key of ase */ + CRYPT_DES_KEYS_1 = 0x12, /**< 1 key of des */ + CRYPT_DES_KEYS_2 = 0x14, /**< 2 key of des */ + CRYPT_DES_KEYS_3 = 0x16, /**< 3 key of des */ +} crypt_ks_t; + +/** + * @brief CRYPT state structures definition + */ +typedef enum { + CRYPT_STATE_RESET = 0x0, /**< Peripheral is not initialized */ + CRYPT_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ + CRYPT_STATE_BUSY = 0x2, /**< An internal process is ongoing */ + CRYPT_STATE_ERROR = 0x4, /**< Error */ +} crypt_state_t; + +/** + * @brief CRYPT key length + */ +typedef enum { + KEY_2_LEN = 2, /**< Key's lenth is 2 */ + KEY_4_LEN = 4, /**< Key's lenth is 4 */ + KEY_6_LEN = 6, /**< Key's lenth is 6 */ + KEY_8_LEN = 8, /**< Key's lenth is 8 */ +} crypt_key_len_t; + +/** + * @brief CRYPT iv length + */ +typedef enum { + IV_2_LEN = 2, /**< iv's lenth is 2 */ + IV_4_LEN = 4, /**< iv's lenth is 4 */ +} crypt_ivr_len_t; + +/** + * @brief CRYPT data type + */ +typedef enum { + DATA_32_BIT = 0, /**< 32 bit data,don't swap */ + DATA_16_BIT = 1, /**< 16 bit data,swap */ + DATA_8_BIT = 2, /**< 8 bit data,swap */ + DATA_1_BIT = 3, /**< 1 bit data, swap */ +} crypt_data_t; + +/** + * @brief CRYPT init structure definition + */ +typedef struct { + crypt_mode_t mode; /**< Crypt mode */ + crypt_data_t type; /**< Data type select */ + crypt_ks_t key; /**< Key select */ +} crypt_init_t; + +/** + * @brief CRYPT Handle Structure definition + */ +typedef struct crypt_handle_s { + CRYPT_TypeDef *perh; /**< Register base address */ + crypt_init_t init; /**< CRYPT required parameters */ +#ifdef ALD_DMA + dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */ + dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */ +#endif + uint8_t *plain_text; /**< Pointer to plain text */ + uint8_t *cipher_text; /**< Pointer to cipher text */ + uint32_t size; /**< The size of crypt data buf */ + uint32_t count; /**< The count of crypt data buf */ + uint32_t step; /**< The step of once crypt 2(des) or 4(aes) */ + uint32_t dir; /**< ENCRYPT or DECRYPT */ + uint32_t iv[4]; /**< The iv of crypt */ + uint32_t iv_size; /**< The iv size */ + uint32_t key[8]; /**< The key of crypt */ + uint32_t key_size; /**< The key size */ + lock_state_t lock; /**< Locking object */ + crypt_state_t state; /**< CRYPT operation state */ + + void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */ + void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */ +} crypt_handle_t; +/** + * @} + */ + +/** @defgroup CRYPT_Public_Macros CRYPT Public Macros + * @{ + */ +#define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK)) +#define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) +#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT(handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) +#define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) +#define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) +#define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) +#define CRYPT_IE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) +#define CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) +#define CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) +#define CRYPT_SETDIR(handle, dir) do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS); \ + (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0) +#define CRYPT_WRITE_FIFO(handle, data) ((handle)->perh->FIFO = (data)) +#define CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO) +/** + * @} + */ + +/** @defgroup CRYPT_Private_Macros CRYPT Private Macros + * @{ + */ +#define IS_CRYPT(x) ((x) == CRYPT) +#define IS_CRYPT_MODE(x) (((x) == CRYPT_MODE_ECB) || \ + ((x) == CRYPT_MODE_CBC) || \ + ((x) == CRYPT_MODE_CTR)) +#define IS_CRYPT_KS(x) (((x) == CRYPT_AES_BITS_128) || \ + ((x) == CRYPT_AES_BITS_192) || \ + ((x) == CRYPT_AES_BITS_256) || \ + ((x) == CRYPT_DES_KEYS_1) || \ + ((x) == CRYPT_DES_KEYS_2) || \ + ((x) == CRYPT_DES_KEYS_3)) +#define IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT) +#define IS_CRYPT_FLAG(x) (((x) == CRYPT_FLAG_AESIF) || \ + ((x) == CRYPT_FLAG_DESIF) || \ + ((x) == CRYPT_FLAG_DONE)) +#define IS_CRYPT_IV_LEN(x) (((x) == IV_2_LEN) || \ + ((x) == IV_4_LEN)) +#define IS_CRYPT_KEY_LEN(x) (((x) == KEY_2_LEN) || \ + ((x) == KEY_4_LEN) || \ + ((x) == KEY_6_LEN) || \ + ((x) == KEY_8_LEN)) +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions + * @{ + */ + +/** @addtogroup CRYPT_Public_Functions_Group1 + * @{ + */ +extern ald_status_t ald_crypt_init(crypt_handle_t *hperh); +extern ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t * key, crypt_key_len_t len); +extern ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t * key, crypt_key_len_t len); +extern ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t * iv, crypt_ivr_len_t len); +extern ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t * iv, crypt_ivr_len_t len); +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions_Group2 + * @{ + */ +extern ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t * plain_text, uint8_t * cipher_text, uint32_t size); +extern ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t * cipher_text, uint8_t * plain_text, uint32_t size); +extern ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag); +extern ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size); +extern ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size); +#ifdef ALD_DMA +extern ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t * plain_text, + uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); +extern ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t * cipher_text, + uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); +#endif +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions_Group3 + * @{ + */ +#ifdef ALD_DMA +extern ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh); +extern ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh); +extern ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh); +#endif +extern void ald_crypt_irq_handler(crypt_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions_Group4 + * @{ + */ +extern void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state); +extern flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag); +extern void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag); +extern it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it); +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions_Group5 + * @{ + */ +extern crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h new file mode 100644 index 0000000000000000000000000000000000000000..a70273076e55d00b93da4b3dfabaccc165e27bf9 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dac.h @@ -0,0 +1,307 @@ +/** + ****************************************************************************** + * @file ald_dac.h + * @brief Header file of DAC Module library. + * + * @version V1.0 + * @date 28 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ****************************************************************************** + */ + +#ifndef __ALD_DAC_H__ +#define __ALD_DAC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" +#include "ald_pis.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Pubulic_Types DAC Pubulic Types + * @{ + */ +/** + * @brief ADC channel + */ +typedef enum { + DAC_CHANNEL_0 = 1, /**< ADC channel 0 */ + DAC_CHANNEL_1 = 2, /**< ADC channel 1 */ + DAC_CHANNEL_COMB = 3, /**< ADC channel 0 and 1 */ +} dac_channel_t; + +/** + * @brief Dac convert mode + */ +typedef enum { + DAC_CONV_MODE_CONTINUOUS = 0, /**< ADC set in continuous mode */ + DAC_CONV_MODE_SAMPLEHOLD = 1, /**< ADC set in sample/hold mode */ + DAC_CONV_MODE_SAMPLEOFF = 2, /**< ADC set in sample/shut off mode */ +} dac_conv_mode_t; + +/** + * @brief ADC out mode + */ +typedef enum { + DAC_OUTPUT_DISABLE = 0, /**< ADC output disable */ + DAC_OUTPUT_PIN = 1, /**< ADC output to pin enable */ + DAC_OUTPUT_ADC = 2, /**< ADC output to adc and acmp enable */ + DAC_OUTPUT_PIN_ADC = 3, /**< ADC output to pin, adc and acmp enable */ +} dac_out_mode_t; + +/** + * @brief ADC prs input channel + */ +typedef enum { + DAC_PIS_CH_0 = 0, /**< PIS channel 0 triggers ADC channel conversion */ + DAC_PIS_CH_1 = 1, /**< PIS channel 1 triggers ADC channel conversion */ + DAC_PIS_CH_2 = 2, /**< PIS channel 2 triggers ADC channel conversion */ + DAC_PIS_CH_3 = 3, /**< PIS channel 3 triggers ADC channel conversion */ + DAC_PIS_CH_4 = 4, /**< PIS channel 4 triggers ADC channel conversion */ + DAC_PIS_CH_5 = 5, /**< PIS channel 5 triggers ADC channel conversion */ + DAC_PIS_CH_6 = 6, /**< PIS channel 6 triggers ADC channel conversion */ + DAC_PIS_CH_7 = 7, /**< PIS channel 7 triggers ADC channel conversion */ + DAC_PIS_CH_8 = 8, /**< PIS channel 8 triggers ADC channel conversion */ + DAC_PIS_CH_9 = 9, /**< PIS channel 9 triggers ADC channel conversion */ + DAC_PIS_CH_10 = 10, /**< PIS channel 10 triggers ADC channel conversion */ + DAC_PIS_CH_11 = 11, /**< PIS channel 11 triggers ADC channel conversion */ +} dac_pissel_t; + +/** + * @brief ADC negative reference voltage definition + */ +typedef enum { + DAC_NEG_REF_VSS = 0x0, /**< DAC negative regerence voltage vss */ + DAC_NEG_REF_VREFN = 0x1, /**< DAC negative regerence voltage vrefn */ +} dac_neg_ref_t; + +/** + * @brief ADC positive reference voltage definition + */ +typedef enum { + DAC_POS_REF_VDD = 0x0, /**< DAC posotove reference is VDD */ + DAC_POS_REF_2V = 0x1, /**< DAC posotove reference is internal 2V */ + DAC_POS_REF_VREEFP = 0x2, /**< DAC posotove reference is VREEFP */ + DAC_POS_REF_VREEFP_BUF = 0x3, /**< DAC posotove reference is VREEFP BUFFER */ +} dac_pos_ref_t; + +/** + * @brief Refresh interval select + */ +typedef enum { + DAC_REFRESH_8 = 0, /**< Channel refreshed every 8 cycles */ + DAC_REFRESH_16 = 1, /**< Channel refreshed every 16 cycles */ + DAC_REFRESH_32 = 2, /**< Channel refreshed every 32 cycles */ + DAC_REFRESH_64 = 3, /**< Channel refreshed every 64 cycles */ +} dac_refresh_t; + +/** + * @brief Dac prescale + */ +typedef enum { + DAC_PRES_DIV_1 = 0, /**< No division */ + DAC_PRES_DIV_2 = 1, /**< 2 clock division */ + DAC_PRES_DIV_4 = 2, /**< 4 clock division */ + DAC_PRES_DIV_8 = 3, /**< 8 clock division */ + DAC_PRES_DIV_16 = 4, /**< 16 clock division */ + DAC_PRES_DIV_32 = 5, /**< 32 clock division */ + DAC_PRES_DIV_64 = 6, /**< 64 clock division */ + DAC_PRES_DIV_128 = 7, /**< 128 clock division */ +} dac_prescale_div_t; + +/** + * @brief Dac output trigger select + */ +typedef enum { + DAC_TRIGGER_BY_DATA = 0, /**< Channel is triggered by CHxDATA or COMBDATA write */ + DAC_TRIGGER_BY_PIS = 1, /**< Channel is triggered by PIS input */ +} dac_trigger_t; + +/** + * @brief Dac interrupt type + */ +typedef enum { + DAC_IT_CH0 = (1U << 0), /**< Channel 0 conversion complete interrupt */ + DAC_IT_CH1 = (1U << 1), /**< Channel 1 conversion complete interrupt */ + DAC_IT_CH0_UF = (1U << 4), /**< Channel 0 data underflow interrupt */ + DAC_IT_CH1_UF = (1U << 5), /**< Channel 1 data underflow interrupt */ +} dac_it_t; + +/** + * @brief Dac interrupt flag type + */ +typedef enum { + DAC_FLAG_CH0 = (1U << 0), /**< Channel 0 conversion complete interrupt flag */ + DAC_FLAG_CH1 = (1U << 1), /**< Channel 1 conversion complete interrupt flag */ + DAC_FLAG_CH0_UF = (1U << 4), /**< Channel 0 data underflow interrupt flag */ + DAC_FLAG_CH1_UF = (1U << 5), /**< Channel 1 data underflow interrupt flag */ +} dac_flag_t; + +/** + * @brief Dac state flag + */ +typedef enum { + DAC_CH0_BSY = (1U << 0), /**< Channel_0 is BUSY */ + DAC_CH1_BSY = (1U << 1), /**< Channel_1 is BUSY */ +} dac_status_t; + +/** + * @brief Dac init structure definition + */ +typedef struct { + dac_conv_mode_t conv_mode; /**< Conversion mode */ + dac_out_mode_t out_mode; /**< Select output mode */ + dac_refresh_t refresh; /**< Refresh interval select */ + dac_prescale_div_t div; /**< Prescaler setting */ + type_func_t ch0_reset; /**< Select if prescaler is reset on channel 0 start */ + type_func_t o_ctrl_pis; /**< Enable pis control of dac output enable */ + type_func_t sine; /**< Sine mode enable/disable */ + type_func_t diff; /**< Differential mode enable/disable */ + dac_neg_ref_t n_ref; /**< The negative reference voltage select */ + dac_pos_ref_t p_ref; /**< The positive reference voltage select */ +} dac_init_t; + +/** + * @brief Dac channel initialize structure definition + */ +typedef struct { + type_func_t enable; /**< Dac channel output enable/disable */ + dac_trigger_t trigger; /**< Select channel conversion trigger */ + type_func_t refresh_en; /**< Set automatic refresh of channel function */ + dac_pissel_t pis_ch; /**< Select channel pis input channel */ +} dac_channel_config_t; + +/** + * @brief Dac handle Structure definition + */ +typedef struct dac_handle_s { + DAC_TypeDef *perh; /**< Register base address */ + dac_init_t init; /**< Dac initialize parameters */ + lock_state_t lock; /**< Locking object */ + + void (*cbk)(struct dac_handle_s *arg, uint32_t event); /**< DAC event callback */ +} dac_handle_t; +/** + * @} + */ + +/** @defgroup DAC_Public_Macros DAC Public Macros + * @{ + */ +#define DAC_CH0_ENABLE() (SET_BIT(DAC0->CH0CTRL, DAC_CH0CTRL_EN_MSK)) +#define DAC_CH1_ENABLE() (SET_BIT(DAC0->CH1CTRL, DAC_CH1CTRL_EN_MSK)) +#define DAC_CH0_DISABLE() (CLEAR_BIT(DAC0->CH0CTRL, DAC_CH0CTRL_EN_MSK)) +#define DAC_CH1_DISABLE() (CLEAR_BIT(DAC0->CH1CTRL, DAC_CH1CTRL_EN_MSK)) + +#define DAC_EVENT_CH0_CPLT 0x0 +#define DAC_EVENT_CH1_CPLT 0x1 +#define DAC_EVENT_CH0_UF 0x2 +#define DAC_EVENT_CH1_UF 0x3 +/** + * @} + */ + +/** @defgroup DAC_Private_Macros DAC Private Macros + * @{ + */ +#define IS_DAC_TYPE(x) ((x) == DAC0) +#define IS_DAC_CONVERT_TYPE(x) (((x) == DAC_CONV_MODE_CONTINUOUS) || \ + ((x) == DAC_CONV_MODE_SAMPLEHOLD) || \ + ((x) == DAC_CONV_MODE_SAMPLEOFF)) +#define IS_DAC_OUTPUT_TYPE(x) (((x) == DAC_OUTPUT_DISABLE) || \ + ((x) == DAC_OUTPUT_PIN) || \ + ((x) == DAC_OUTPUT_ADC) || \ + ((x) == DAC_OUTPUT_PIN_ADC)) +#define IS_DAC_NEG_REFRESH_TYPE(x) (((x) == DAC_NEG_REF_VSS) || \ + ((x) == DAC_NEG_REF_VREFN)) +#define IS_DAC_POS_REFRESH_TYPE(x) (((x) == DAC_POS_REF_VDD) || \ + ((x) == DAC_POS_REF_2V) || \ + ((x) == DAC_POS_REF_VREEFP) || \ + ((x) == DAC_POS_REF_VREEFP_BUF)) +#define IS_DAC_REFRESH_TYPE(x) (((x) == DAC_REFRESH_8) || \ + ((x) == DAC_REFRESH_16) || \ + ((x) == DAC_REFRESH_32) || \ + ((x) == DAC_REFRESH_64)) +#define IS_DAC_CHANNEL_TYPE(x) (((x) == DAC_CHANNEL_0) || \ + ((x) == DAC_CHANNEL_1) || \ + ((x) == DAC_CHANNEL_COMB)) +#define IS_DAC_PRESCALE_TYPE(x) (((x) == DAC_PRES_DIV_1) || \ + ((x) == DAC_PRES_DIV_2) || \ + ((x) == DAC_PRES_DIV_4) || \ + ((x) == DAC_PRES_DIV_8) || \ + ((x) == DAC_PRES_DIV_16) || \ + ((x) == DAC_PRES_DIV_32) || \ + ((x) == DAC_PRES_DIV_64) || \ + ((x) == DAC_PRES_DIV_128)) +#define IS_DAC_INTERRUPT_TYPE(x) (((x) == DAC_IT_CH0) || \ + ((x) == DAC_IT_CH1) || \ + ((x) == DAC_IT_CH0_UF) || \ + ((x) == DAC_IT_CH1_UF)) +#define IS_DAC_FLAG_TYPE(x) (((x) == DAC_FLAG_CH0) || \ + ((x) == DAC_FLAG_CH1) || \ + ((x) == DAC_FLAG_CH0_UF) || \ + ((x) == DAC_FLAG_CH1_UF)) +#define IS_DAC_PISSEL_CH_TYPE(x) (((x) == DAC_PIS_CH_0) || \ + ((x) == DAC_PIS_CH_1) || \ + ((x) == DAC_PIS_CH_2) || \ + ((x) == DAC_PIS_CH_3) || \ + ((x) == DAC_PIS_CH_4) || \ + ((x) == DAC_PIS_CH_5) || \ + ((x) == DAC_PIS_CH_6) || \ + ((x) == DAC_PIS_CH_7) || \ + ((x) == DAC_PIS_CH_8) || \ + ((x) == DAC_PIS_CH_9) || \ + ((x) == DAC_PIS_CH_10) || \ + ((x) == DAC_PIS_CH_11)) +#define IS_DAC_STATUS_TYPE(x) (((x) == DAC_CH0_BSY) || \ + ((x) == DAC_CH1_BSY)) +#define IS_DAC_TRIGGER_TYPE(x) (((x) == DAC_TRIGGER_BY_DATA) || \ + ((x) == DAC_TRIGGER_BY_PIS)) +/** + * @} + */ + +/** @addtogroup DAC_Public_Functions + * @{ + */ +ald_status_t ald_dac_reset(dac_handle_t *hperh); +ald_status_t ald_dac_init(dac_handle_t *hperh); +ald_status_t ald_dac_channel_config(dac_handle_t *hperh, dac_channel_config_t *config, dac_channel_t ch); +void ald_dac_output_set(dac_handle_t *hperh, dac_channel_t ch, uint32_t value); +flag_status_t ald_dac_get_status(dac_handle_t *hperh, dac_status_t status); +void ald_dac_interrupt_config(dac_handle_t *hperh, dac_it_t it, type_func_t state); +it_status_t ald_dac_get_it_status(dac_handle_t *hperh, dac_it_t it); +flag_status_t ald_dac_get_flag_status(dac_handle_t *hperh, dac_flag_t flag); +flag_status_t ald_dac_get_mask_flag_status(dac_handle_t *hperh, dac_flag_t flag); +void ald_dac_clear_flag_status(dac_handle_t *hperh, dac_flag_t flag); +void ald_dac_irq_handler(dac_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus + extern "C" } +#endif + +#endif /* __ALD_DAC_H */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h new file mode 100644 index 0000000000000000000000000000000000000000..c1230e694ecc5fd6cc507957b0f2c95be8269a91 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dbgc.h @@ -0,0 +1,156 @@ +/** + ********************************************************************************* + * + * @file ald_dbgc.h + * @brief DEBUGCON module driver. + * + * @version V1.0 + * @date 04 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_DBGC_H__ +#define __ALD_DBGC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup DBGC DBGC + * @brief DBGC module driver + * @{ + */ + + + +/** @defgroup DBGC_Public_Types DBGC Public Types + * @{ + */ +/** + * @brief Debug mode select + */ +typedef enum { + DEBC_MODE_SLEEP = (1u << 0), /**< Sleep mode */ + DEBC_MODE_STOP1 = (1u << 1), /**< STOP1 mode */ + DEBC_MODE_STOP2 = (1u << 2), /**< STOP2 mode */ + DEBC_MODE_STANDBY = (1u << 3), /**< Standby mode */ +} dbgc_mode_t; + +/** + * @brief Debug peripheral select + */ +typedef enum { + DEBC_PERH_TIMER0 = (1u << 0), /**< AD16C4T0 */ + DEBC_PERH_TIMER1 = (1u << 1), /**< BS16T0 */ + DEBC_PERH_TIMER2 = (1u << 2), /**< GP16C2T0 */ + DEBC_PERH_TIMER3 = (1u << 3), /**< GP16C2T1 */ + DEBC_PERH_TIMER4 = (1u << 4), /**< BS16T1 */ + DEBC_PERH_TIMER5 = (1u << 5), /**< BS16T2 */ + DEBC_PERH_TIMER6 = (1u << 6), /**< GP16C4T0 */ + DEBC_PERH_TIMER7 = (1u << 7), /**< BS16T3 */ + DEBC_PERH_I2C0 = (1u << 8), /**< I2C0 SMBUS */ + DEBC_PERH_I2C1 = (1u << 9), /**< I2C1 SMBUS */ + DEBC_PERH_CAN = (1u << 12), /**< CAN */ + DEBC_PERH_LPTIM0 = (1u << 0) | (1u << 16), /**< LPTIM0 */ + DEBC_PERH_IWDT = (1u << 8) | (1u << 16), /**< IWDT */ + DEBC_PERH_WWDT = (1u << 9) | (1u << 16), /**< WWDT */ + DEBC_PERH_RTC = (1u << 10) | (1u << 16), /**< RTC */ +} dbgc_perh_t; +/** + * @} + */ + +/** @defgroup DBGC_Public_Functions DBGC Public Functions + * @{ + */ +/** + * @brief Gets version. + * @retval Version + */ +__INLINE uint32_t ald_dbgc_get_rev_id(void) +{ + return (DBGC->IDCODE >> 16); +} + +/** + * @brief Gets core id. + * @retval Core id + */ +__INLINE uint32_t ald_dbgc_get_core_id(void) +{ + return (DBGC->IDCODE >> 12) & 0xF; +} + +/** + * @brief Gets device id + * @retval device id + */ +__INLINE uint32_t ald_dbgc_get_device_id(void) +{ + return DBGC->IDCODE & 0xFFF; +} + +/** + * @brief Configures low power debug mode + * @param mode: The mode of low power. + * @param state: ENABLE/DISABLE + * @retval None + */ +__INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state) +{ + if (state) + SET_BIT(DBGC->CR, mode); + else + CLEAR_BIT(DBGC->CR, mode); +} + +/** + * @brief Configures peripheral debug mode + * @param perh: The peripheral. + * @param state: ENABLE/DISABLE + * @retval None + */ +__INLINE void ald_dbgc_perh_config(dbgc_perh_t perh, type_func_t state) +{ + if ((perh >> 16) & 0x1) { + if (state) + SET_BIT(DBGC->APB2FZ, perh); + else + CLEAR_BIT(DBGC->APB2FZ, perh); + } + else { + if (state) + SET_BIT(DBGC->APB1FZ, perh); + else + CLEAR_BIT(DBGC->APB1FZ, perh); + } +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..736e5b68be37178fe62beb4376949f9e5c1b1b5f --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_dma.h @@ -0,0 +1,405 @@ +/** + ********************************************************************************* + * + * @file ald_dma.h + * @brief DMA module Library. + * + * @version V1.0 + * @date 09 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_DMA_H__ +#define __ALD_DMA_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** + * @defgroup DMA_Public_Macros DMA Public Macros + * @{ + */ +#define DMA_CH_COUNT 12 +#define DMA_ERR 31 +/** + * @} + */ + +/** + * @defgroup DMA_Public_Types DMA Public Types + * @{ + */ + +/** + * @brief Input source to DMA channel + * @note + * ES32F36xx + * AD16C4T0 TIMER0 + * AD16C4T1 TIMER1 + * GP32C4T0 TIMER2 + * GP32C4T1 TIMER3 + * BS16T0 TIMER4 + * BS16T1 TIMER5 + * GP16C4T0 TIMER6 + * GP16C4T1 TIMER7 + * + * ES32F393x/ES32F336x/ES32F392x + * GP16C4T0 TIMER0 + * GP16C4T1 TIMER1 + * GP32C4T0 TIMER2 + * GP32C4T1 TIMER3 + * BS16T0 TIMER4 + * BS16T1 TIMER5 + * GP16C4T2 TIMER6 + * GP16C4T3 TIMER7 + */ +typedef enum { + DMA_MSEL_NONE = 0x0, /**< NONE */ + DMA_MSEL_GPIO = 0x1, /**< GPIO */ + DMA_MSEL_CRYPT = 0x2, /**< CRYPT */ + DMA_MSEL_DAC0 = 0x4, /**< DAC0 */ + DMA_MSEL_ADC0 = 0x6, /**< ADC0 */ + DMA_MSEL_CRC = 0x7, /**< CRC */ + DMA_MSEL_UART0 = 0x8, /**< UART0 */ + DMA_MSEL_UART1 = 0x9, /**< UART1 */ + DMA_MSEL_UART2 = 0xA, /**< UART2 */ + DMA_MSEL_UART3 = 0xB, /**< UART3 */ + DMA_MSEL_UART4 = 0xC, /**< UART4 */ + DMA_MSEL_UART5 = 0xD, /**< UART5 */ + DMA_MSEL_SPI0 = 0xE, /**< SPI0 */ + DMA_MSEL_SPI1 = 0xF, /**< SPI1 */ + DMA_MSEL_I2C0 = 0x10, /**< I2C0 */ + DMA_MSEL_I2C1 = 0x11, /**< I2C1 */ + DMA_MSEL_TIMER0 = 0x12, /**< TIMER0 */ + DMA_MSEL_TIMER1 = 0x13, /**< TIMER1 */ + DMA_MSEL_TIMER2 = 0x14, /**< TIMER2 */ + DMA_MSEL_TIMER3 = 0x15, /**< TIMER3 */ + DMA_MSEL_LPUART0 = 0x18, /**< LPUART0 */ + DMA_MSEL_SPI2 = 0x1A, /**< SPI2 */ + DMA_MSEL_TIMER4 = 0x1B, /**< TIMER4 */ + DMA_MSEL_TIMER5 = 0x1C, /**< TIMER5 */ + DMA_MSEL_TIMER6 = 0x1D, /**< TIMER6 */ + DMA_MSEL_TIMER7 = 0x1E, /**< TIMER7 */ + DMA_MSEL_ADC1 = 0x1F, /**< ADC1 */ + DMA_MSEL_PIS = 0x20, /**< PIS */ + DMA_MSEL_TRNG = 0x21, /**< TRNG */ + DMA_MSEL_QSPI = 0x22, /**< QSPI */ + DMA_MSEL_USB = 0x23, /**< USB */ +} dma_msel_t; + +/** + * @brief Input signal to DMA channel + */ +typedef enum { + DMA_MSIGSEL_NONE = 0x0, /**< NONE */ + DMA_MSIGSEL_EXTI_0 = 0x0, /**< External interrupt 0 */ + DMA_MSIGSEL_EXTI_1 = 0x1, /**< External interrupt 1 */ + DMA_MSIGSEL_EXTI_2 = 0x2, /**< External interrupt 2 */ + DMA_MSIGSEL_EXTI_3 = 0x3, /**< External interrupt 3 */ + DMA_MSIGSEL_EXTI_4 = 0x4, /**< External interrupt 4 */ + DMA_MSIGSEL_EXTI_5 = 0x5, /**< External interrupt 5 */ + DMA_MSIGSEL_EXTI_6 = 0x6, /**< External interrupt 6 */ + DMA_MSIGSEL_EXTI_7 = 0x7, /**< External interrupt 7 */ + DMA_MSIGSEL_EXTI_8 = 0x8, /**< External interrupt 8 */ + DMA_MSIGSEL_EXTI_9 = 0x9, /**< External interrupt 9 */ + DMA_MSIGSEL_EXTI_10 = 0xA, /**< External interrupt 10 */ + DMA_MSIGSEL_EXTI_11 = 0xB, /**< External interrupt 11 */ + DMA_MSIGSEL_EXTI_12 = 0xC, /**< External interrupt 12 */ + DMA_MSIGSEL_EXTI_13 = 0xD, /**< External interrupt 13 */ + DMA_MSIGSEL_EXTI_14 = 0xE, /**< External interrupt 14 */ + DMA_MSIGSEL_EXTI_15 = 0xF, /**< External interrupt 15 */ + DMA_MSIGSEL_CRYPT_WRITE = 0x0, /**< CRYPT write mode */ + DMA_MSIGSEL_CRYPT_READ = 0x1, /**< CRYPT read mode */ + DMA_MSIGSEL_DAC0_CH0 = 0x0, /**< DAC0 channel 0 complete */ + DMA_MSIGSEL_DAC0_CH1 = 0x1, /**< DAC0 channel 1 complete */ + DMA_MSIGSEL_ADC = 0x0, /**< ADC mode */ + DMA_MSIGSEL_UART_TXEMPTY = 0x0, /**< UART0/UART1/UART2/UART3 transmit */ + DMA_MSIGSEL_UART_RNR = 0x1, /**< UART0/UART1/UART2/UART3 receive */ + DMA_MSIGSEL_UART45_RNR = 0x0, /**< UART4/UART5 reveive */ + DMA_MSIGSEL_UART45_TXEMPTY = 0x1, /**< UART4/UART5 transmit */ + DMA_MSIGSEL_SPI_RNR = 0x0, /**< SPI receive */ + DMA_MSIGSEL_SPI_TXEMPTY = 0x1, /**< SPI transmit */ + DMA_MSIGSEL_I2C_RNR = 0x0, /**< I2C receive */ + DMA_MSIGSEL_I2C_TXEMPTY = 0x1, /**< I2C transmit */ + DMA_MSIGSEL_TIMER_CH1 = 0x0, /**< TIM channal 1 */ + DMA_MSIGSEL_TIMER_CH2 = 0x1, /**< TIM channal 2 */ + DMA_MSIGSEL_TIMER_CH3 = 0x2, /**< TIM channal 3 */ + DMA_MSIGSEL_TIMER_CH4 = 0x3, /**< TIM channal 4 */ + DMA_MSIGSEL_TIMER_TRI = 0x4, /**< TIM trigger */ + DMA_MSIGSEL_TIMER_COMP = 0x5, /**< TIM compare */ + DMA_MSIGSEL_TIMER_UPDATE = 0x6, /**< TIM update */ + DMA_MSIGSEL_LPUART_RNR = 0x0, /**< LPUART receive */ + DMA_MSIGSEL_LPUART_TXEMPTY = 0x1, /**< LPUART transmit */ + DMA_MSIGSEL_PIS_CH0 = 0x0, /**< PIS channal 0 */ + DMA_MSIGSEL_PIS_CH1 = 0x1, /**< PIS channal 1 */ + DMA_MSIGSEL_PIS_CH2 = 0x2, /**< PIS channal 2 */ + DMA_MSIGSEL_PIS_CH3 = 0x3, /**< PIS channal 3 */ + DMA_MSIGSEL_PIS_CH4 = 0x4, /**< PIS channal 4 */ + DMA_MSIGSEL_PIS_CH5 = 0x5, /**< PIS channal 5 */ + DMA_MSIGSEL_PIS_CH6 = 0x6, /**< PIS channal 6 */ + DMA_MSIGSEL_PIS_CH7 = 0x7, /**< PIS channal 7 */ + DMA_MSIGSEL_PIS_CH8 = 0x8, /**< PIS channal 8 */ + DMA_MSIGSEL_PIS_CH9 = 0x9, /**< PIS channal 9 */ + DMA_MSIGSEL_PIS_CH10 = 0xA, /**< PIS channal 10 */ + DMA_MSIGSEL_PIS_CH11 = 0xB, /**< PIS channal 11 */ + DMA_MSIGSEL_PIS_CH12 = 0xC, /**< PIS channal 12 */ + DMA_MSIGSEL_PIS_CH13 = 0xD, /**< PIS channal 13 */ + DMA_MSIGSEL_PIS_CH14 = 0xE, /**< PIS channal 14 */ + DMA_MSIGSEL_PIS_CH15 = 0xF, /**< PIS channal 15 */ + DMA_MSIGSEL_QSPI_WRITE = 0x0, /**< QSPI Write */ + DMA_MSIGSEL_QSPI_READ = 0x1, /**< QSPI Read */ + DMA_MSIGSEL_EP_TX1 = 0x0, /**< USB TX Endport 0 */ + DMA_MSIGSEL_EP_TX2 = 0x1, /**< USB TX Endport 1 */ + DMA_MSIGSEL_EP_TX3 = 0x2, /**< USB TX Endport 2 */ + DMA_MSIGSEL_EP_TX4 = 0x3, /**< USB TX Endport 3 */ + DMA_MSIGSEL_EP_TX5 = 0x4, /**< USB TX Endport 4 */ + DMA_MSIGSEL_EP_RX1 = 0x8, /**< USB RX Endport 0 */ + DMA_MSIGSEL_EP_RX2 = 0x9, /**< USB RX Endport 1 */ + DMA_MSIGSEL_EP_RX3 = 0xA, /**< USB RX Endport 2 */ + DMA_MSIGSEL_EP_RX4 = 0xB, /**< USB RX Endport 3 */ + DMA_MSIGSEL_EP_RX5 = 0xC, /**< USB RX Endport 4 */ +} dma_msigsel_t; + +/** + * @brief DMA Descriptor control type + */ +typedef union { + struct { + uint32_t cycle_ctrl :3; /**< DMA operating mode @ref dma_cycle_ctrl_t */ + uint32_t next_useburst :1; /**< Uses the alternate data structure when complete a DMA cycle */ + uint32_t n_minus_1 :10; /**< Represent the total number of DMA transfers that DMA cycle contains. */ + uint32_t R_power :4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ + uint32_t src_prot_ctrl :3; /**< Control the state of HPROT when reads the source data. */ + uint32_t dst_prot_ctrl :3; /**< Control the state of HPROT when writes the destination data */ + uint32_t src_size :2; /**< Source data size @ref dma_data_size_t */ + uint32_t src_inc :2; /**< Control the source address increment. @ref dma_data_inc_t */ + uint32_t dst_size :2; /**< Destination data size. @ref dma_data_size_t */ + uint32_t dst_inc :2; /**< Destination address increment. @ref dma_data_inc_t */ + }; + uint32_t word; +} dma_ctrl_t; + +/** + * @brief Channel control data structure + */ +typedef struct { + void *src; /**< Source data end pointer */ + void *dst; /**< Destination data end pointer */ + dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */ + uint32_t use; /**< Reserve for user */ +} dma_descriptor_t; + +/** + * @brief data increment + */ +typedef enum { + DMA_DATA_INC_BYTE = 0x0, /**< Address increment by byte */ + DMA_DATA_INC_HALFWORD = 0x1, /**< Address increment by halfword */ + DMA_DATA_INC_WORD = 0x2, /**< Address increment by word */ + DMA_DATA_INC_NONE = 0x3, /**< No increment */ +} dma_data_inc_t; + +/** + * @brief Data size + */ +typedef enum { + DMA_DATA_SIZE_BYTE = 0x0, /**< Byte */ + DMA_DATA_SIZE_HALFWORD = 0x1, /**< Halfword */ + DMA_DATA_SIZE_WORD = 0x2, /**< Word */ +} dma_data_size_t; + +/** + * @brief The operating mode of the DMA cycle + */ +typedef enum { + DMA_CYCLE_CTRL_NONE = 0x0, /**< Stop */ + DMA_CYCLE_CTRL_BASIC = 0x1, /**< Basic */ + DMA_CYCLE_CTRL_AUTO = 0x2, /**< Auto-request */ + DMA_CYCLE_CTRL_PINGPONG = 0x3, /**< Ping-pong */ + DMA_CYCLE_CTRL_MEM_SCATTER_GATHER = 0x4, /**< Memory scatter/gather */ + DMA_CYCLE_CTRL_PER_SCATTER_GATHER = 0x6, /**< Peripheral scatter/gather */ +} dma_cycle_ctrl_t; + +/** + * @brief Control how many DMA transfers can occur + * before the controller re-arbitrates + */ +typedef enum { + DMA_R_POWER_1 = 0x0, /**< Arbitrates after each DMA transfer */ + DMA_R_POWER_2 = 0x1, /**< Arbitrates after 2 DMA transfer */ + DMA_R_POWER_4 = 0x2, /**< Arbitrates after 4 DMA transfer */ + DMA_R_POWER_8 = 0x3, /**< Arbitrates after 8 DMA transfer */ + DMA_R_POWER_16 = 0x4, /**< Arbitrates after 16 DMA transfer */ + DMA_R_POWER_32 = 0x5, /**< Arbitrates after 32 DMA transfer */ + DMA_R_POWER_64 = 0x6, /**< Arbitrates after 64 DMA transfer */ + DMA_R_POWER_128 = 0x7, /**< Arbitrates after 128 DMA transfer */ + DMA_R_POWER_256 = 0x8, /**< Arbitrates after 256 DMA transfer */ + DMA_R_POWER_512 = 0x9, /**< Arbitrates after 512 DMA transfer */ + DMA_R_POWER_1024 = 0xA, /**< Arbitrates after 1024 DMA transfer */ +} dma_arbiter_config_t; + +/** + * @brief Callback function pointer and param + */ +typedef struct { + void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*err_cbk)(void* arg); /**< DMA occurs error callback */ + void *cplt_arg; /**< The parameter of cplt_cbk() */ + void *err_arg; /**< The parameter of err_cbk() */ +} dma_call_back_t; + +/** + * @brief DMA channal configure structure + */ +typedef struct { + void *src; /**< Source data begin pointer */ + void *dst; /**< Destination data begin pointer */ + uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ + dma_data_size_t data_width; /**< Data width, @ref dma_data_size_t */ + dma_data_inc_t src_inc; /**< Source increment type. @ref dma_data_inc_t */ + dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */ + dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ + type_func_t primary; /**< Use primary descriptor or alternate descriptor */ + type_func_t burst; /**< Uses the alternate data structure when complete a DMA cycle */ + type_func_t high_prio; /**< High priority or default priority */ + type_func_t iterrupt; /**< Enable/disable interrupt */ + dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */ + dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */ + uint8_t channel; /**< Channel index */ +} dma_config_t; + +/** + * @brief DMA handle structure definition + */ +typedef struct { + DMA_TypeDef *perh; /**< DMA registers base address */ + dma_config_t config; /**< Channel configure structure. @ref dma_config_t */ + void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*err_cbk)(void *arg); /**< DMA bus occurs error callback */ + void *cplt_arg; /**< The parameter of cplt_cbk() */ + void *err_arg; /**< The parameter of err_cbk() */ +} dma_handle_t; +/** + * @} + */ + +/** + * @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ +#define IS_DMA_MSEL_TYPE(x) ((x) <= DMA_MSEL_USB) +#define IS_DMA_MSIGSEL_TYPE(x) ((x) <= 0xF) +#define IS_DMA_DATAINC_TYPE(x) (((x) == DMA_DATA_INC_BYTE) || \ + ((x) == DMA_DATA_INC_HALFWORD) || \ + ((x) == DMA_DATA_INC_WORD) || \ + ((x) == DMA_DATA_INC_NONE)) +#define IS_DMA_DATASIZE_TYPE(x) (((x) == DMA_DATA_SIZE_BYTE) || \ + ((x) == DMA_DATA_SIZE_HALFWORD) || \ + ((x) == DMA_DATA_SIZE_WORD)) +#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \ + ((x) == DMA_CYCLE_CTRL_BASIC) || \ + ((x) == DMA_CYCLE_CTRL_AUTO) || \ + ((x) == DMA_CYCLE_CTRL_PINGPONG) || \ + ((x) == DMA_CYCLE_CTRL_MEM_SCATTER_GATHER) || \ + ((x) == DMA_CYCLE_CTRL_PER_SCATTER_GATHER)) +#define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \ + ((x) == DMA_R_POWER_2) || \ + ((x) == DMA_R_POWER_4) || \ + ((x) == DMA_R_POWER_8) || \ + ((x) == DMA_R_POWER_16) || \ + ((x) == DMA_R_POWER_32) || \ + ((x) == DMA_R_POWER_64) || \ + ((x) == DMA_R_POWER_128) || \ + ((x) == DMA_R_POWER_256) || \ + ((x) == DMA_R_POWER_512) || \ + ((x) == DMA_R_POWER_1024)) +#define IS_DMA(x) ((x) == DMA0) +#define IS_DMA_CHANNEL(x) ((x) <= 11) +#define IS_DMA_DATA_SIZE(x) ((x) <= 1024) +#define IS_DMA_IT_TYPE(x) (((x) <= 11) || ((x) == 31)) +/** + * @} + */ + +/** + * @addtogroup DMA_Public_Functions + * @{ + */ + +/** @addtogroup DMA_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +extern void ald_dma_reset(DMA_TypeDef *DMAx); +extern void ald_dma_init(DMA_TypeDef *DMAx); +extern void ald_dma_config_struct(dma_config_t *p); +/** + * @} + */ + + +/** @addtogroup DMA_Public_Functions_Group2 + * @{ + */ +/* Configure DMA channel functions */ +extern void ald_dma_config_auto(dma_handle_t *hperh); +extern void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size); +extern void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, + uint16_t size, uint8_t channel, void (*cbk)(void *arg)); +extern void ald_dma_config_basic(dma_handle_t *hperh); +extern void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size); +extern void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, + dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); +/** + * @} + */ + +/** @addtogroup DMA_Public_Functions_Group3 + * @{ + */ +/* DMA control functions */ +extern void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); +extern void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); +extern it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel); +extern flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel); +extern void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel); +void ald_dma_irq_handler(void); +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__ALD_DMA_H__ */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h new file mode 100644 index 0000000000000000000000000000000000000000..11e8035923f16fe5e31f001c113285a200b8731a --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_ebi.h @@ -0,0 +1,586 @@ +/** + ********************************************************************************* + * + * @file ald_ebi.h + * @brief Header file of EBI module driver. + * + * @version V1.0 + * @date 20 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + + +#ifndef __ALD_EBI_H__ +#define __ALD_EBI_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup EBI + * @{ + */ + +/** + * @defgroup EBI_Public_Macros EBI Public Macros + * @{ + */ +#define EBI_NOR_SRAM_TypeDef EBI_Bank1_TypeDef +#define EBI_NOR_SRAM_EXTENDED_TypeDef EBI_Bank1E_TypeDef +#define EBI_NAND_TypeDef EBI_Bank2_3_TypeDef +#define EBI_LCD_TypeDef EBI_Bank1_LCD_TypeDef +#define EBI_NOR_SRAM_DEVICE EBI_Bank1 +#define EBI_NOR_SRAM_EXTENDED_DEVICE EBI_Bank1E +#define EBI_NAND_DEVICE EBI_Bank2_3 +#define EBI_LCD_DEVICE EBI_Bank1_LCD +#define EBI_NAND_BANK2 0x00000010U +#define EBI_NAND_BANK3 0x00000100U + +/* PCTRLR register clear mask */ +#define PCTRLR_CLEAR_MASK ((uint32_t)(EBI_PCTRLRx_WAITEN_MSK | EBI_PCTRLRx_MEMBKEN_MSK | \ + EBI_PCTRLRx_MEMTYP_MSK | EBI_PCTRLRx_DATBUSWID_MSK | \ + EBI_PCTRLRx_ECCEN_MSK | EBI_PCTRLRx_CRDLY_MSK | \ + EBI_PCTRLRx_ARDLY_MSK | EBI_PCTRLRx_ECCPSIZE_MSK)) + +/* PMEMR register clear mask */ +#define PMEMR_CLEAR_MASK ((uint32_t)(EBI_PMEMRx_MEMSETUP_MSK | EBI_PMEMRx_MEMWAIT_MSK | \ + EBI_PMEMRx_MEMHOLD_MSK | EBI_PMEMRx_MEMHIZT_MSK)) + +/* PATTR register clear mask */ +#define PATTR_CLEAR_MASK ((uint32_t)(EBI_PATTRx_ATTSETUP_MSK | EBI_PATTRx_ATTWAIT_MSK | \ + EBI_PATTRx_ATTHOLD_MSK | EBI_PATTRx_ATTHIZT_MSK)) + +/* BCTRLR register clear mask */ +#define BCTRLR_CLEAR_MASK ((uint32_t)(EBI_BCTRLRx_FLASHACCEN_MSK | EBI_BCTRLRx_MUXEN_MSK | \ + EBI_BCTRLRx_MEMTYP_MSK | EBI_BCTRLRx_MEMWID_MSK | \ + EBI_BCTRLRx_BURSTEN_MSK | EBI_BCTRLRx_WAITPOL_MSK | \ + EBI_BCTRLRx_WRAPMODE_MSK | EBI_BCTRLRx_WAITCFG_MSK | \ + EBI_BCTRLRx_WREN_MSK | EBI_BCTRLRx_WAITEN_MSK | \ + EBI_BCTRLRx_EXTMODEN_MSK | EBI_BCTRLRx_ASYNCWAIT_MSK | \ + EBI_BCTRLRx_RWCBURSTEN_MSK)) +/* BTR register clear mask */ +#define BTR_CLEAR_MASK ((uint32_t)(EBI_BTRx_ADDATASETUP_MSK | EBI_BTRx_ADDHOLD_MSK | \ + EBI_BTRx_DATAHOLD_MSK | EBI_BTRx_BUSTURN_MSK | \ + EBI_BTRx_CLKDIV_MSK | EBI_BTRx_DATALAT_MSK | \ + EBI_BTRx_ACCMODE_MSK)) + +/* BWRTR register clear mask */ +#define BWTR_CLEAR_MASK ((uint32_t)(EBI_BWRTRx_ADDATASETUP_MSK | EBI_BWRTRx_ADDHOLD_MSK | \ + EBI_BWRTRx_DATAHOLD_MSK | EBI_BWRTRx_BUSTURN_MSK | \ + EBI_BWRTRx_ACCMODE_MSK)) + +#define LCDCTRL_CLEAR_MASK ((uint32_t)(EBI_LCDCTRLx_HSYNCPOL_POS | EBI_LCDCTRLx_VSYNCPOL_MSK | \ + EBI_LCDCTRLx_DENPOL_MSK | EBI_LCDCTRLx_LCDEN_MSK | \ + EBI_LCDCTRLx_LCDINT_MSK | EBI_LCDCTRLx_DCLKPOL_MSK | \ + EBI_LCDCTRLx_DATASETUP_MSK)) +/** + * @} + */ + +/** @defgroup EBI_Public_Types EBI Public Types + * @{ + */ + +/** + * @brief EBI Access Mode + */ +typedef enum { + EBI_ACCESS_MODE_A = 0x0, /**< EBI access mode A */ + EBI_ACCESS_MODE_B = (0x1U << 28), /**< EBI access mode B */ + EBI_ACCESS_MODE_C = (0x2U << 28), /**< EBI access mode C */ + EBI_ACCESS_MODE_D = (0x3U << 28), /**< EBI access mode D */ +} ebi_access_mode_t; + +/** + * @brief EBI NORSRAM Timing parameters structure definition + */ +typedef struct { + uint32_t addr_setup; /**< Address setup HCLK cycles number, the value between 0 and 15 */ + uint32_t addr_hold; /**< Address hold HCLK cycles number, the value between 0 and 15 */ + uint32_t data_setup; /**< Data setup HCLK cycles number, the value between 1 and 255 */ + uint32_t bus_dur; /**< Bus turnaround duration HCLK cycles, the value between 0 and 15 */ + uint32_t div; /**< Defines the period of CLK clock signal, the value between 2 and 16 */ + uint32_t latency; /**< Issue clock cycles before getting the first data, the value between 2 and 17 */ + ebi_access_mode_t mode; /**< Specifies the asynchronous access mode */ +} ald_ebi_nor_sram_timing_t; + +/** + * @brief EBI_Wait_feature EBI Wait feature + */ +typedef enum { + EBI_NAND_WAIT_FEATURE_DISABLE = 0x0, /**< NAND wait feature disable */ + EBI_NAND_WAIT_FEATURE_ENABLE = (0x1U << 1), /**< NAND wait feature enable */ +} ebi_nand_wait_feature_t; + +/** + * @brief EBI NAND Data Width + */ +typedef enum { + EBI_NAND_MEM_BUS_WIDTH_8 = 0x0, /**< NAND mem bus width 8-bits */ + EBI_NAND_MEM_BUS_WIDTH_16 = (0x3U << 4), /**< NAND mem bus width 16-bits */ +} ebi_nand_mem_bus_width_t; + +/** + * @brief EBI NAND ECC STATE + */ +typedef enum { + EBI_NAND_ECC_DISABLE = 0, /**< NAND ecc disable */ + EBI_NAND_ECC_ENABLE = (0x1U << 6), /**< NAND ecc enable */ +} ebi_nand_ecc_t; + +/** + * @brief EBI ECC Page Size + */ +typedef enum { + EBI_NAND_ECC_PAGE_SIZE_256BYTE = 0, /**< NAND ecc page size 256 bytes */ + EBI_NAND_ECC_PAGE_SIZE_512BYTE = (0x1U << 17), /**< NAND ecc page size 512 bytes */ + EBI_NAND_ECC_PAGE_SIZE_1024BYTE = (0x2U << 17), /**< NAND ecc page size 1024 bytes */ + EBI_NAND_ECC_PAGE_SIZE_2048BYTE = (0x3U << 17), /**< NAND ecc page size 2048 bytes */ + EBI_NAND_ECC_PAGE_SIZE_4096BYTE = (0x4U << 17), /**< NAND ecc page size 4096 bytes */ + EBI_NAND_ECC_PAGE_SIZE_8192BYTE = (0x5U << 17), /**< NAND ecc page size 8192 bytes */ +} ebi_md_ecc_page_size_t; + +/** + * @brief EBI NAND Configuration Structure definition + */ +typedef struct { + uint32_t bank; /**< Specifies the NAND memory device that will be used */ + ebi_nand_wait_feature_t wait; /**< Enables or disables the Wait feature for the NAND Memory device */ + ebi_nand_mem_bus_width_t width; /**< Specifies the external memory device width */ + ebi_nand_ecc_t ecc; /**< Enables or disables the ECC computation */ + ebi_md_ecc_page_size_t size; /**< Defines the page size for the extended ECC */ + uint32_t cle_time; /**< Number of HCLK cycles between CLE low and RE low, the value between 0 and 255 */ + uint32_t ale_time; /**< Number of HCLK cycles between ALE low and RE low */ +} ald_ebi_nand_init_t; + +/** + * @brief EBI NAND Timing parameters structure definition + */ +typedef struct { + uint32_t time; /**< Number of cycles to setup address, the value between 0 and 255 */ + uint32_t wait_time; /**< Number of HCLK cycles to assert the command ,the value between 0 and 255 */ + uint32_t hold_time; /**< Number of HCLK cycles to hold address or data, the value between 0 and 255 */ + uint32_t hiz_time; /**< Number of HCLK cycles data bus is kept in HiZ, the value between 0 and 255 */ +} ald_ebi_nand_timing_t; + +/** + * @brief EBI Data Address Bus Multiplexing + */ +typedef enum { + EBI_DATA_ADDRESS_MUX_DISABLE = 0x0, /**< Data address mux disable */ + EBI_DATA_ADDRESS_MUX_ENABLE = (0x1U << 1), /**< Data address mux enable */ +} ebi_data_address_mux_t; + +/** + * @brief EBI NOR/SRAM Bank + */ +typedef enum { + EBI_NORSRAM_BANK1 = 0x0, /**< Norsram bank 1 */ + EBI_NORSRAM_BANK2 = 0x2, /**< Norsram bank 2 */ + EBI_NORSRAM_BANK3 = 0x4, /**< Norsram bank 3 */ + EBI_NORSRAM_BANK4 = 0x6, /**< Norsram bank 4 */ +} ebi_norsram_bank_t; + +/** + * @brief EBI Memory Type + */ +typedef enum { + EBI_MEMORY_TYPE_SRAM = 0x0, /**< Memory tyepe SRAM */ + EBI_MEMORY_TYPE_PSRAM = (0x1U << 2), /**< Memory tyepe PSRAM */ + EBI_MEMORY_TYPE_NOR = (0x2U << 2), /**< Memory tyepe NOR */ +} ebi_memory_type_t; + +/** + * @brief EBI NOR/SRAM Data Width + */ +typedef enum { + EBI_NORSRAM_MEM_BUS_WIDTH_8 = 0x0, /**< Norsram Memory width 8-bits */ + EBI_NORSRAM_MEM_BUS_WIDTH_16 = (0x1U << 4), /**< Norsram Memory width 16-bits */ + EBI_NORSRAM_MEM_BUS_WIDTH_32 = (0x2U << 4), /**< Norsram Memory width 32-bits */ +} ebi_norsram_mem_bus_width_t; + +/** + * @brief EBI NOR/SRAM Flash Access + */ +typedef enum { + EBI_NORSRAM_FLASH_ACCESS_DISABLE = 0x0, /**< Norsram flash access disable */ + EBI_NORSRAM_FLASH_ACCESS_ENABLE = (0x1U << 6), /**< Norsram flash access enable */ +} ebi_norsram_flash_access_t; + +/** + * @brief EBI Burst Access Mode + */ +typedef enum { + EBI_BURST_ACCESS_MODE_DISABLE = 0x0, /**< Burst access disable */ + EBI_BURST_ACCESS_MODE_ENABLE = (0x1U << 8), /**< Burst access enable */ +} ebi_burst_access_mode_t; + +/** + * @brief EBI Wait Signal Polarity + */ +typedef enum { + EBI_WAIT_SIGNAL_POLARITY_LOW = 0x0, /**< Wait signal polarity low */ + EBI_WAIT_SIGNAL_POLARITY_HIGH = (0x1U << 9), /**< Wait signal polarity high */ +} ebi_wait_signal_polarity_t; + +/** + * @brief EBI Wrap Mode + */ +typedef enum { + EBI_WRAP_MODE_DISABLE = 0x0, /**< Wrap mode disable */ + EBI_WRAP_MODE_ENABLE = (0x1U << 10), /**< Wrap mode enable */ +} ebi_wrap_mode_t; + +/** + * @brief EBI Wait Timing + */ +typedef enum { + EBI_WAIT_TIMING_BEFORE_WS = 0x0, /**< Wait timing before ws */ + EBI_WAIT_TIMING_DURING_WS = (0x1U << 11), /**< Wait timing during ws */ +} ebi_wait_timing_t; + +/** + * @brief EBI Write Operation State + */ +typedef enum { + EBI_WRITE_OPERATION_DISABLE = 0x0, /**< Write operation disable */ + EBI_WRITE_OPERATION_ENABLE = (0x1U << 12), /**< Write operation enable */ +} ebi_write_operation_t; + +/** + * @brief EBI Wait Signal + */ +typedef enum { + EBI_WAIT_SIGNAL_DISABLE = 0x0, /**< Wait signal disable */ + EBI_WAIT_SIGNAL_ENABLE = (0x1U << 13), /**< Wait signal enable */ +} ebi_wait_signal_t; + +/** + * @brief EBI Extended Mode + */ +typedef enum { + EBI_EXTENDED_MODE_DISABLE = 0x0, /**< EBI extended mode disable */ + EBI_EXTENDED_MODE_ENABLE = (0x1U << 14), /**< EBI extended mode enable */ +} ebi_extended_mode_t; + +/** + * @brief EBI Asynchronous Wait + */ +typedef enum { + EBI_ASYNCHRONOUS_WAIT_DISABLE = 0x0, /**< Asynchronous wait disable */ + EBI_ASYNCHRONOUS_WAIT_ENABLE = (0x1U << 15), /**< Asynchronous wait enable */ +} ebi_asynchronous_wait_t; + +/** + * @brief EBI Write Burst + */ +typedef enum { + EBI_WRITE_BURST_DISABLE = 0x0, /**< Write burst disable */ + EBI_WRITE_BURST_ENABLE = (0x1U << 19), /**< Write burst enable */ +} ebi_write_burst_t; + +/** + * @brief EBI PCR Memory Type + */ +typedef enum { + EBI_PCTRLR_MEMORY_TYPE_None = 0x0, /**< PCR memory type none */ + EBI_PCTRLR_MEMORY_TYPE_NAND = (0x1U << 3), /**< PCR memory type nand */ +} ebi_pctrlr_memory_type_t; + +/** + * @brief EBI Interrupt definition + */ +typedef enum { + EBI_IT_RISING_EDGE = (1U << 3), /**< Rising edge trigger interrupt */ + EBI_IT_LEVEL = (1U << 4), /**< Level trigger interrupt */ + EBI_IT_FALLING_EDGE = (1U << 5), /**< Falling edge trigger interrupt */ +} ebi_it_t; + +/** + * @brief EBI Flag definition + */ +typedef enum { + EBI_FLAG_RISING_EDGE = (1U << 0), /**< Rising edge flag */ + EBI_FLAG_LEVEL = (1U << 1), /**< Level flag */ + EBI_FLAG_FALLING_EDGE = (1U << 2), /**< Falling edge flag */ + EBI_FLAG_FEMPT = (1U << 6), /**< Rising edge trigger interrupt */ +} ebi_flag_t; + +/** + * @brief EBI LCD_Horizontal Synch Polarity definition + */ +typedef enum { + EBI_LCD_HSYNCPOL_LOW = 0x0, /**< Horizontal synch polarity low */ + EBI_LCD_HSYNCPOL_HIGH = (0x1U << 29), /**< Horizontal synch polarity high */ +} ebi_lcd_hsyncpol_t; + +/** + * @brief EBI LCD Vertical Synch Polarity definition + */ +typedef enum { + EBI_LCD_VSYNCPOL_LOW = 0x0, /**< Vertical synch polarity low */ + EBI_LCD_VSYNCPOL_HIGH = (0x1U << 28), /**< Vertical synch polarity high */ +} ebi_lcd_vsyncpol_t; + +/** + * @brief EBI LCD Data Enable Polarity definition + */ +typedef enum { + EBI_LCD_DENPOL_LOW = 0x0, /**< LCD data enable polarity low */ + EBI_LCD_DENPOL_HIGH = (0x1U << 27), /**< LCD data enable polarity high */ +} ebi_lcd_denpol_t; + +/** + * @brief EBI LCD Enable definition + */ +typedef enum { + EBI_LCD_LCDEN_DISABLE = 0x0, /**< LCD disable */ + EBI_LCD_LCDEN_ENABLE = (0x1U << 26), /**< LCD data enable polarity low */ +} ebi_lcd_lcden_t; + +/** + * @brief EBI LCD Init Enable definition + */ +typedef enum { + EBI_LCD_LCDINT_DISABLE = 0x0, /**< LCD init disable */ + EBI_LCD_LCDINT_ENABLE = (0x1 << 25), /**< LCD init enable */ +} ebi_lcd_lcdint_t; + +/** + * @brief EBI LCD Data Clock definition + */ +typedef enum { + EBI_LCD_DCLKPOL_FALLING = 0x0, /**< LCD data clock falling edge */ + EBI_LCD_DCLKPOL_RISING = (0x1U << 24), /**< LCD data clock rising edge */ +} ebi_lcd_dclkpol_t; + +/** + * @brief EBI LCD parameters structure definition + */ +typedef struct { + uint8_t bank; /**< Specifies the NORSRAM memory device */ + ebi_lcd_hsyncpol_t h_polarity; /**< Horizontal sync polarity */ + ebi_lcd_vsyncpol_t v_polarity; /**< Vertical sync polarity */ + ebi_lcd_denpol_t data_polarity; /**< Data enable polarity */ + ebi_lcd_lcden_t enable; /**< LCD enable */ + ebi_lcd_dclkpol_t clk_polarity; /**< Data clock polarity */ + ebi_lcd_lcdint_t reset; /**< LCD Reset */ + uint8_t setup; /**< Data setup time */ + uint8_t v_width; /**< Vsync pulse width */ + uint8_t h_width; /**< Hsync puluse width */ + uint16_t nr_line; /**< Frame line number */ + uint16_t nr_pixel; /**< Frame pixel number */ +} ebi_lcd_init_t; + +/** + * @brief NOR LCD handle Structure definition + */ +typedef struct { + EBI_LCD_TypeDef *inst; + ebi_lcd_init_t init; +} ebi_lcd_handle_t; + +/** + * @brief EBI NORSRAM Configuration Structure definition + */ +typedef struct { + uint32_t bank; /**< Specifies the NORSRAM memory device, the value can be one of 0 ~ 3 */ + ebi_data_address_mux_t mux; /**< Address and data values are multiplexed or not */ + ebi_memory_type_t type; /**< Specifies the type of external memory */ + ebi_norsram_mem_bus_width_t width; /**< Specifies the external memory device width */ + ebi_burst_access_mode_t acc_mode; /**< Enables or disables the burst access mode for Flash memory */ + ebi_wait_signal_polarity_t polarity; /**< Wait signal polarity, valid only in burst mode */ + ebi_wrap_mode_t wrap_mode; /**< Enables or disables the Wrapped burst access mode, only in burst mode */ + ebi_wait_timing_t active; /**< Specifies if the wait signal is asserted, only in burst mode */ + ebi_write_operation_t write; /**< Enables or disables the write operation */ + ebi_wait_signal_t signal; /**< Enables or disables the wait state insertion, only in burst mode */ + ebi_extended_mode_t ext_mode; /**< Enables or disables the extended mode */ + ebi_asynchronous_wait_t wait; /**< Enables or disables wait signal during asynchronous transfers */ + ebi_write_burst_t burst; /**< Enables or disables the write burst operation */ +} ald_ebi_nor_sram_init_t; + +/** + * @} + */ + +/** @defgroup EBI_Private_Macros EBI Private Macros + * @{ + */ +#define IS_EBI_NORSRAM_BANK(x) (((x) == EBI_NORSRAM_BANK1) || \ + ((x) == EBI_NORSRAM_BANK2) || \ + ((x) == EBI_NORSRAM_BANK3) || \ + ((x) == EBI_NORSRAM_BANK4)) +#define IS_EBI_MUX(x) (((x) == EBI_DATA_ADDRESS_MUX_DISABLE) || \ + ((x) == EBI_DATA_ADDRESS_MUX_ENABLE)) +#define IS_EBI_MEMORY(x) (((x) == EBI_MEMORY_TYPE_SRAM) || \ + ((x) == EBI_MEMORY_TYPE_PSRAM) || \ + ((x) == EBI_MEMORY_TYPE_NOR)) +#define IS_EBI_NORSRAM_MEMORY_WIDTH(x) (((x) == EBI_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((x) == EBI_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((x) == EBI_NORSRAM_MEM_BUS_WIDTH_32)) +#define IS_EBI_WRITE_BURST(x) (((x) == EBI_WRITE_BURST_DISABLE) || \ + ((x) == EBI_WRITE_BURST_ENABLE)) +#define IS_EBI_ACCESS_MODE(x) (((x) == EBI_ACCESS_MODE_A) || \ + ((x) == EBI_ACCESS_MODE_B) || \ + ((x) == EBI_ACCESS_MODE_C) || \ + ((x) == EBI_ACCESS_MODE_D)) +#define IS_EBI_NAND_BANK(x) (((x) == EBI_NAND_BANK2) || \ + ((x) == EBI_NAND_BANK3)) +#define IS_EBI_WAIT_FEATURE(x) (((x) == EBI_NAND_WAIT_FEATURE_DISABLE) || \ + ((x) == EBI_NAND_WAIT_FEATURE_ENABLE)) +#define IS_EBI_NAND_MEMORY_WIDTH(x) (((x) == EBI_NAND_MEM_BUS_WIDTH_8) || \ + ((x) == EBI_NAND_MEM_BUS_WIDTH_16)) +#define IS_EBI_ECC_STATE(x) (((x) == EBI_NAND_ECC_DISABLE) || \ + ((x) == EBI_NAND_ECC_ENABLE)) +#define IS_EBI_ECCPAGE_SIZE(x) (((x) == EBI_NAND_ECC_PAGE_SIZE_256BYTE) || \ + ((x) == EBI_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((x) == EBI_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((x) == EBI_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((x) == EBI_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((x) == EBI_NAND_ECC_PAGE_SIZE_8192BYTE)) +#define IS_EBI_LCD_DEVICE(x) ((x) == EBI_LCD_DEVICE) +#define IS_EBI_HORIZONTAL_SYNCH(x) (((x) == EBI_LCD_HSYNCPOL_LOW) || \ + ((x) == EBI_LCD_HSYNCPOL_HIGH)) +#define IS_EBI_VERTICAL_SYNCH(x) (((x) == EBI_LCD_VSYNCPOL_LOW) || \ + ((x) == EBI_LCD_VSYNCPOL_HIGH)) +#define IS_EBI_DATA_ENABLE(x) (((x) == EBI_LCD_DENPOL_LOW) || \ + ((x) == EBI_LCD_DENPOL_HIGH)) +#define IS_EBI_LCD_ENABLE(x) (((x) == EBI_LCD_LCDEN_DISABLE) || \ + ((x) == EBI_LCD_LCDEN_ENABLE)) +#define IS_EBI_LCD_RESET(x) (((x) == EBI_LCD_LCDINT_DISABLE) || \ + ((x) == EBI_LCD_LCDINT_ENABLE)) +#define IS_EBI_DATA_CLOCK(x) (((x) == EBI_LCD_DCLKPOL_FALLING) || \ + ((x) == EBI_LCD_DCLKPOL_RISING)) +#define IS_EBI_LCD_DATASETUP_TIME(x) ((x) < 255U) +#define IS_EBI_HYSNC_PULSE_WIDTH(x) ((x) < 255U) +#define IS_EBI_VSYNC_PULSE_WIDTH(x) ((x) < 255U) +#define IS_EBI_FRAME_LINE_NUMBER(x) (((x) >= 1U) && ((x) < 65535)) +#define IS_EBI_FRAME_PIXEL_NUMBER(x) (((x) >= 1U) && ((x) < 65535)) + +#define IS_EBI_TCLR_TIME(x) ((x) <= 255U) +#define IS_EBI_TAR_TIME(x) ((x) <= 255U) +#define IS_EBI_SETUP_TIME(x) ((x) <= 255U) +#define IS_EBI_WAIT_TIME(x) ((x) <= 255U) +#define IS_EBI_HOLD_TIME(x) ((x) <= 255U) +#define IS_EBI_HIZ_TIME(x) ((x) <= 255U) +#define IS_EBI_NORSRAM_DEVICE(x) ((x) == EBI_NOR_SRAM_DEVICE) +#define IS_EBI_NORSRAM_EXTENDED_DEVICE(x) ((x) == EBI_NOR_SRAM_EXTENDED_DEVICE) +#define IS_EBI_NAND_DEVICE(x) ((x) == EBI_NAND_DEVICE) +#define IS_EBI_BURSTMODE(x) (((x) == EBI_BURST_ACCESS_MODE_DISABLE) || \ + ((x) == EBI_BURST_ACCESS_MODE_ENABLE)) +#define IS_EBI_WAIT_POLARITY(x) (((x) == EBI_WAIT_SIGNAL_POLARITY_LOW) || \ + ((x) == EBI_WAIT_SIGNAL_POLARITY_HIGH)) +#define IS_EBI_WRAP_MODE(x) (((x) == EBI_WRAP_MODE_DISABLE) || \ + ((x) == EBI_WRAP_MODE_ENABLE)) +#define IS_EBI_WAIT_SIGNAL_ACTIVE(x) (((x) == EBI_WAIT_TIMING_BEFORE_WS) || \ + ((x) == EBI_WAIT_TIMING_DURING_WS)) +#define IS_EBI_WRITE_OPERATION(x) (((x) == EBI_WRITE_OPERATION_DISABLE) || \ + ((x) == EBI_WRITE_OPERATION_ENABLE)) +#define IS_EBI_WAITE_SIGNAL(x) (((x) == EBI_WAIT_SIGNAL_DISABLE) || \ + ((x) == EBI_WAIT_SIGNAL_ENABLE)) +#define IS_EBI_EXTENDED_MODE(x) (((x) == EBI_EXTENDED_MODE_DISABLE) || \ + ((x) == EBI_EXTENDED_MODE_ENABLE)) +#define IS_EBI_ASYNWAIT(x) (((x) == EBI_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((x) == EBI_ASYNCHRONOUS_WAIT_ENABLE)) +#define IS_EBI_CLK_DIV(x) (((x) >= 1U) && ((x) <= 16U)) +#define IS_EBI_DATA_LATENCY(x) (((x) >= 1U) && ((x) <= 17U)) +#define IS_EBI_ADDRESS_SETUP_TIME(x) ((x) <= 15U) +#define IS_EBI_ADDRESS_HOLD_TIME(x) (((x) > 0U) && ((x) <= 15U)) +#define IS_EBI_DATASETUP_TIME(x) (((x) > 0U) && ((x) <= 255U)) +#define IS_EBI_TURNAROUND_TIME(x) ((x) <= 15U) +#define IS_EBI_BANK_NUMBER(x) (((x) > 0U) && ((x) <= 4U)) +/** + * @} + */ + +/** @addtogroup EBI_Public_Functions + * @{ + */ + +/** @addtogroup EBI_Public_Functions_Group1 + * @{ + */ +/* NOR-FLASH SRAM initialize functions */ +void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init); +void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank); +void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode); +ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank); +/** + * @} + */ + +/** @addtogroup EBI_Public_Functions_Group2 + * @{ + */ +/* NOR/SRAM Control functions */ +void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank); +void ald_ebi_nor_sram_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank); +void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank); +void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank); +/** + * @} + */ + +/** @addtogroup EBI_Public_Functions_Group3 + * @{ + */ +/* NAND-FLASH initialize functions */ +void ald_ebi_nand_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init); +void ald_ebi_nand_comm_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank); +void ald_ebi_nand_attr_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank); +void ald_ebi_nand_deinit(EBI_NAND_TypeDef *dev, uint32_t bank); +/** + * @} + */ + +/** @addtogroup EBI_Public_Functions_Group4 + * @{ + */ +/* NAND-FLASH control functions */ +void ald_ebi_nand_enable(EBI_NAND_TypeDef *dev, uint32_t bank); +void ald_ebi_nand_disable(EBI_NAND_TypeDef *dev, uint32_t bank); +void ald_ebi_nand_enable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it); +void ald_ebi_nand_disable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it); +void ald_ebi_nand_ecc_enable(EBI_NAND_TypeDef *dev, uint32_t bank); +void ald_ebi_nand_ecc_disable(EBI_NAND_TypeDef *dev, uint32_t bank); +ald_status_t ald_ebi_nand_get_ecc(EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout); +flag_status_t ald_ebi_nand_get_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag); +void ald_ebi_nand_clear_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag); +/** + * @} + */ + +/** @addtogroup EBI_Public_Functions_Group5 + * @{ + */ +void ald_ebi_lcd_init(ebi_lcd_handle_t *hlcd); +void ald_ebi_lcd_reset(ebi_lcd_handle_t *hlcd); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_EBI_H__ */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h new file mode 100644 index 0000000000000000000000000000000000000000..13c8940a2ef09c7b4e38d09f59b803b3e7881d6e --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_flash.h @@ -0,0 +1,130 @@ +/** + ********************************************************************************* + * + * @file ald_flash.h + * @brief Header file of FLASH driver + * + * @version V1.0 + * @date 17 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_FLASH_H__ +#define __ALD_FLASH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** + * @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ +#define FLASH_REG_UNLOCK() \ +do { \ + if (op_cmd == OP_FLASH) { \ + WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \ + WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \ + } \ + else { \ + WRITE_REG(MSC->INFOKEY, 0x7153BFD9); \ + WRITE_REG(MSC->INFOKEY, 0x0642CEA8); \ + } \ +} while (0) +#define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) +#define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) +#define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) +#define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) +#define FLASH_BASE_ADDR 0x00000000 +#define FLASH_PAGE_SIZE 1024UL +#define FLASH_WORD_SIZE 8UL +#define FLASH_TOTAL_SIZE 512UL +#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) +#define FLASH_WORD_MASK (FLASH_WORD_SIZE - 1) +#define IS_FLASH_ADDRESS(ADDR) ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE)) +#define IS_4BYTES_ALIGN(ADDR) (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0) +#define FLASH_PAGE_ADDR(ADDR) ((ADDR) & (~FLASH_PAGE_MASK)) +#define FLASH_PAGEEND_ADDR(ADDR) ((ADDR) | FLASH_PAGE_MASK) +#define FLASH_WORD_ADDR(ADDR) ((ADDR) & (~FLASH_WORD_MASK)) +#define FLASH_WORDEND_ADDR(ADDR) ((ADDR) | FLASH_WORD_MASK) +#define INFO_PAGE_SIZE 1024UL +#define INFO_PAGE_MASK (INFO_PAGE_SIZE - 1) +#define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK)) + +#ifdef USE_FLASH_FIFO + #define FLASH_FIFO 1 +#else + #define FLASH_FIFO 0 +#endif +/** + * @} + */ + +/** @defgroup FLASH_Private_Types FLASH Private Types + * @{ + */ +typedef enum { + FLASH_CMD_AE = 0x000051AE, /**< Program area erase all */ + FLASH_CMD_PE = 0x00005EA1, /**< Page erase */ + FLASH_CMD_WP = 0x00005DA2, /**< Word program */ + FLASH_CMD_WP_FAST = 0x00005CA3, /**< Flash quickly program */ + FLASH_CMD_DATAPE = 0x00005BA4, /**< Data flash page page erase */ + FLASH_CMD_DATAWP = 0x00005AA5, /**< Data flash word program */ + FLASH_CMD_DATAWP_FAST = 0x000059A6, /**< Data flash quickly program */ + FLASH_CMD_NP_AE = 0x000050AF, /**< No-private area erase all */ +} flash_cmd_type; + +typedef enum { + OP_FLASH = 0, /**< Operate Pragram area */ + OP_INFO = 1, /**< Operate info area */ +} op_cmd_type; + +/** + * @} + */ +/** @addtogroup Flash_Private_Functions + * @{ + */ +ald_status_t flash_page_erase(uint32_t addr); +ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo); +/** + * @} + */ + +/** @addtogroup Flash_Public_Functions + * @{ + */ +ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len); +ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len); +ald_status_t ald_flash_erase(uint32_t addr, uint16_t len); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_FLASH_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h similarity index 33% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h rename to bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h index 7e93a9575181ab372a6318ab5385074f966889c0..8b35b0908e0d571ce7b2b9f37bc90018067d63a5 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_gpio.h @@ -5,7 +5,7 @@ * @brief Header file of GPIO module driver * * @version V1.0 - * @date 07 Nov 2017 + * @date 07 Nov 2019 * @author AE Team * @note * @@ -18,7 +18,7 @@ #define __ALD_GPIO_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -36,23 +36,23 @@ extern "C" { * @defgroup GPIO_Public_Macros GPIO Public Macros * @{ */ -#define GPIO_PIN_0 (1U << 0) -#define GPIO_PIN_1 (1U << 1) -#define GPIO_PIN_2 (1U << 2) -#define GPIO_PIN_3 (1U << 3) -#define GPIO_PIN_4 (1U << 4) -#define GPIO_PIN_5 (1U << 5) -#define GPIO_PIN_6 (1U << 6) -#define GPIO_PIN_7 (1U << 7) -#define GPIO_PIN_8 (1U << 8) -#define GPIO_PIN_9 (1U << 9) -#define GPIO_PIN_10 (1U << 10) -#define GPIO_PIN_11 (1U << 11) -#define GPIO_PIN_12 (1U << 12) -#define GPIO_PIN_13 (1U << 13) -#define GPIO_PIN_14 (1U << 14) -#define GPIO_PIN_15 (1U << 15) -#define GPIO_PIN_ALL (0xFFFF) +#define GPIO_PIN_0 (1U << 0) +#define GPIO_PIN_1 (1U << 1) +#define GPIO_PIN_2 (1U << 2) +#define GPIO_PIN_3 (1U << 3) +#define GPIO_PIN_4 (1U << 4) +#define GPIO_PIN_5 (1U << 5) +#define GPIO_PIN_6 (1U << 6) +#define GPIO_PIN_7 (1U << 7) +#define GPIO_PIN_8 (1U << 8) +#define GPIO_PIN_9 (1U << 9) +#define GPIO_PIN_10 (1U << 10) +#define GPIO_PIN_11 (1U << 11) +#define GPIO_PIN_12 (1U << 12) +#define GPIO_PIN_13 (1U << 13) +#define GPIO_PIN_14 (1U << 14) +#define GPIO_PIN_15 (1U << 15) +#define GPIO_PIN_ALL (0xFFFF) /** * @} */ @@ -65,125 +65,118 @@ extern "C" { /** * @brief GPIO mode */ -typedef enum -{ - GPIO_MODE_CLOSE = 0x0, /**< Digital close Analog open */ - GPIO_MODE_INPUT = 0x1, /**< Input */ - GPIO_MODE_OUTPUT = 0x2, /**< Output */ +typedef enum { + GPIO_MODE_CLOSE = 0x0, /**< Digital close Analog open */ + GPIO_MODE_INPUT = 0x1, /**< Input */ + GPIO_MODE_OUTPUT = 0x2, /**< Output */ } gpio_mode_t; /** * @brief GPIO open-drain or push-pull */ -typedef enum -{ - GPIO_PUSH_PULL = 0x0, /**< Push-Pull */ - GPIO_OPEN_DRAIN = 0x2, /**< Open-Drain */ - GPIO_OPEN_SOURCE = 0x3, /**< Open-Source */ +typedef enum { + GPIO_PUSH_PULL = 0x0, /**< Push-Pull */ + GPIO_OPEN_DRAIN = 0x2, /**< Open-Drain */ + GPIO_OPEN_SOURCE = 0x3, /**< Open-Source */ } gpio_odos_t; /** * @brief GPIO push-up or push-down */ -typedef enum -{ - GPIO_FLOATING = 0x0,/**< Floating */ - GPIO_PUSH_UP = 0x1,/**< Push-Up */ - GPIO_PUSH_DOWN = 0x2,/**< Push-Down */ - GPIO_PUSH_UP_DOWN = 0x3,/**< Push-Up and Push-Down */ +typedef enum { + GPIO_FLOATING = 0x0,/**< Floating */ + GPIO_PUSH_UP = 0x1,/**< Push-Up */ + GPIO_PUSH_DOWN = 0x2,/**< Push-Down */ + GPIO_PUSH_UP_DOWN = 0x3,/**< Push-Up and Push-Down */ } gpio_push_t; /** * @brief GPIO output drive */ -typedef enum -{ - GPIO_OUT_DRIVE_NORMAL = 0x0, /**< Normal current flow */ - GPIO_OUT_DRIVE_STRONG = 0x1, /**< Strong current flow */ +typedef enum { + GPIO_OUT_DRIVE_0_1 = 0x0, /**< 0.1mA */ + GPIO_OUT_DRIVE_1 = 0x1, /**< 1mA */ + GPIO_OUT_DRIVE_6 = 0x2, /**< 6mA */ + GPIO_OUT_DRIVE_20 = 0x3, /**< 20mA */ } gpio_out_drive_t; /** * @brief GPIO filter */ -typedef enum -{ - GPIO_FILTER_DISABLE = 0x0, /**< Disable filter */ - GPIO_FILTER_ENABLE = 0x1, /**< Enable filter */ +typedef enum { + GPIO_FILTER_DISABLE = 0x0, /**< Disable filter */ + GPIO_FILTER_ENABLE = 0x1, /**< Enable filter */ } gpio_filter_t; /** * @brief GPIO type */ -typedef enum -{ - GPIO_TYPE_CMOS = 0x0, /**< CMOS Type */ - GPIO_TYPE_TTL = 0x1, /**< TTL Type */ +typedef enum { + GPIO_TYPE_CMOS = 0x0, /**< CMOS Type */ + GPIO_TYPE_TTL = 0x1, /**< TTL Type */ } gpio_type_t; /** * @brief GPIO functions */ -typedef enum -{ - GPIO_FUNC_0 = 0, /**< function #0 */ - GPIO_FUNC_1 = 1, /**< function #1 */ - GPIO_FUNC_2 = 2, /**< function #2 */ - GPIO_FUNC_3 = 3, /**< function #3 */ - GPIO_FUNC_4 = 4, /**< function #4 */ - GPIO_FUNC_5 = 5, /**< function #5 */ - GPIO_FUNC_6 = 6, /**< function #6 */ - GPIO_FUNC_7 = 7, /**< function #7 */ +typedef enum { + GPIO_FUNC_0 = 0, /**< function #0 */ + GPIO_FUNC_1 = 1, /**< function #1 */ + GPIO_FUNC_2 = 2, /**< function #2 */ + GPIO_FUNC_3 = 3, /**< function #3 */ + GPIO_FUNC_4 = 4, /**< function #4 */ + GPIO_FUNC_5 = 5, /**< function #5 */ + GPIO_FUNC_6 = 6, /**< function #6 */ + GPIO_FUNC_7 = 7, /**< function #7 */ } gpio_func_t; /** * @brief GPIO Init Structure definition */ -typedef struct -{ - gpio_mode_t mode; /**< Specifies the operating mode for the selected pins. - This parameter can be any value of @ref gpio_mode_t */ - gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins. - This parameter can be a value of @ref gpio_odos_t */ - gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins. - This parameter can be a value of @ref gpio_push_t */ - gpio_out_drive_t odrv; /**< Specifies the output driver for the selected pins. - This parameter can be a value of @ref gpio_out_drive_t */ - gpio_filter_t flt; /**< Specifies the input filter for the selected pins. - This parameter can be a value of @ref gpio_filter_t */ - gpio_type_t type; /**< Specifies the type for the selected pins. - This parameter can be a value of @ref gpio_type_t */ - gpio_func_t func; /**< Specifies the function for the selected pins. - This parameter can be a value of @ref gpio_func_t */ +typedef struct { + gpio_mode_t mode; /**< Specifies the operating mode for the selected pins. + This parameter can be any value of @ref gpio_mode_t */ + gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins. + This parameter can be a value of @ref gpio_odos_t */ + gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins. + This parameter can be a value of @ref gpio_push_t */ + gpio_out_drive_t podrv; /**< Specifies the output P-MOS driver for the selected pins. + This parameter can be a value of @ref gpio_out_drive_t */ + gpio_out_drive_t nodrv; /**< Specifies the output N-MOS driver for the selected pins. + This parameter can be a value of @ref gpio_out_drive_t */ + gpio_filter_t flt; /**< Specifies the input filter for the selected pins. + This parameter can be a value of @ref gpio_filter_t */ + gpio_type_t type; /**< Specifies the type for the selected pins. + This parameter can be a value of @ref gpio_type_t */ + gpio_func_t func; /**< Specifies the function for the selected pins. + This parameter can be a value of @ref gpio_func_t */ } gpio_init_t; /** * @brief EXTI trigger style */ -typedef enum -{ - EXTI_TRIGGER_RISING_EDGE = 0, /**< Rising edge trigger */ - EXTI_TRIGGER_TRAILING_EDGE = 1, /**< Trailing edge trigger */ - EXTI_TRIGGER_BOTH_EDGE = 2, /**< Rising and trailing edge trigger */ +typedef enum { + EXTI_TRIGGER_RISING_EDGE = 0, /**< Rising edge trigger */ + EXTI_TRIGGER_TRAILING_EDGE = 1, /**< Trailing edge trigger */ + EXTI_TRIGGER_BOTH_EDGE = 2, /**< Rising and trailing edge trigger */ } exti_trigger_style_t; /** * @brief EXTI filter clock select */ -typedef enum -{ - EXTI_FILTER_CLOCK_10K = 0, /**< cks = 10KHz */ - EXTI_FILTER_CLOCK_32K = 1, /**< cks = 32KHz */ +typedef enum { + EXTI_FILTER_CLOCK_10K = 0, /**< cks = 10KHz */ + EXTI_FILTER_CLOCK_32K = 1, /**< cks = 32KHz */ } exti_filter_clock_t; /** * @brief EXTI Init Structure definition */ -typedef struct -{ - type_func_t filter; /**< Enable filter. */ - exti_filter_clock_t cks; /**< Filter clock select. */ - uint8_t filter_time; /**< Filter duration */ +typedef struct { + type_func_t filter; /**< Enable filter. */ + exti_filter_clock_t cks; /**< Filter clock select. */ + uint8_t filter_time; /**< Filter duration */ } exti_init_t; /** * @} @@ -193,40 +186,42 @@ typedef struct * @defgroup GPIO_Private_Macros GPIO Private Macros * @{ */ -#define PIN_MASK 0xFFFF -#define UNLOCK_KEY 0x55AA +#define PIN_MASK 0xFFFF +#define UNLOCK_KEY 0x55AA -#define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0)) -#define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \ - (GPIOx == GPIOB) || \ - (GPIOx == GPIOC) || \ - (GPIOx == GPIOD) || \ - (GPIOx == GPIOE) || \ - (GPIOx == GPIOF) || \ - (GPIOx == GPIOG) || \ - (GPIOx == GPIOH)) -#define IS_GPIO_MODE(x) (((x) == GPIO_MODE_CLOSE) || \ +#define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0)) +#define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \ + (GPIOx == GPIOB) || \ + (GPIOx == GPIOC) || \ + (GPIOx == GPIOD) || \ + (GPIOx == GPIOE) || \ + (GPIOx == GPIOF) || \ + (GPIOx == GPIOG) || \ + (GPIOx == GPIOH)) +#define IS_GPIO_MODE(x) (((x) == GPIO_MODE_CLOSE) || \ ((x) == GPIO_MODE_INPUT) || \ ((x) == GPIO_MODE_OUTPUT)) -#define IS_GPIO_ODOS(x) (((x) == GPIO_PUSH_PULL) || \ +#define IS_GPIO_ODOS(x) (((x) == GPIO_PUSH_PULL) || \ ((x) == GPIO_OPEN_DRAIN) || \ ((x) == GPIO_OPEN_SOURCE)) -#define IS_GPIO_PUPD(x) (((x) == GPIO_FLOATING) || \ +#define IS_GPIO_PUPD(x) (((x) == GPIO_FLOATING) || \ ((x) == GPIO_PUSH_UP) || \ ((x) == GPIO_PUSH_DOWN) || \ ((x) == GPIO_PUSH_UP_DOWN)) -#define IS_GPIO_ODRV(x) (((x) == GPIO_OUT_DRIVE_NORMAL) || \ - ((x) == GPIO_OUT_DRIVE_STRONG)) -#define IS_GPIO_FLT(x) (((x) == GPIO_FILTER_DISABLE) || \ +#define IS_GPIO_ODRV(x) (((x) == GPIO_OUT_DRIVE_0_1) || \ + ((x) == GPIO_OUT_DRIVE_1) || \ + ((x) == GPIO_OUT_DRIVE_6) || \ + ((x) == GPIO_OUT_DRIVE_20)) +#define IS_GPIO_FLT(x) (((x) == GPIO_FILTER_DISABLE) || \ ((x) == GPIO_FILTER_ENABLE)) -#define IS_GPIO_TYPE(x) (((x) == GPIO_TYPE_TTL) || \ +#define IS_GPIO_TYPE(x) (((x) == GPIO_TYPE_TTL) || \ ((x) == GPIO_TYPE_CMOS)) -#define IS_TRIGGER_STYLE(x) (((x) == EXTI_TRIGGER_RISING_EDGE) || \ +#define IS_TRIGGER_STYLE(x) (((x) == EXTI_TRIGGER_RISING_EDGE) || \ ((x) == EXTI_TRIGGER_TRAILING_EDGE) || \ ((x) == EXTI_TRIGGER_BOTH_EDGE)) -#define IS_EXTI_FLTCKS_TYPE(x) (((x) == EXTI_FILTER_CLOCK_10K) || \ +#define IS_EXTI_FLTCKS_TYPE(x) (((x) == EXTI_FILTER_CLOCK_10K) || \ ((x) == EXTI_FILTER_CLOCK_32K)) -#define IS_GPIO_FUNC(x) ((x) <= 7) +#define IS_GPIO_FUNC(x) ((x) <= 7) /** * @} */ @@ -238,10 +233,10 @@ typedef struct /** @addtogroup GPIO_Public_Functions_Group1 * @{ */ -void gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init); -void gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin); -void gpio_func_default(GPIO_TypeDef *GPIOx); -void gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init); +void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init); +void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_func_default(GPIO_TypeDef *GPIOx); +void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init); /** * @} */ @@ -249,13 +244,13 @@ void gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init); /** @addtogroup GPIO_Public_Functions_Group2 * @{ */ -uint8_t gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin); -void gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val); -void gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin); -void gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin); -void gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin); -uint16_t gpio_read_port(GPIO_TypeDef *GPIOx); -void gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val); +uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val); +void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx); +void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val); /** * @} */ @@ -263,9 +258,9 @@ void gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val); /** @addtogroup GPIO_Public_Functions_Group3 * @{ */ -void gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status); -flag_status_t gpio_exti_get_flag_status(uint16_t pin); -void gpio_exti_clear_flag_status(uint16_t pin); +void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status); +flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin); +void ald_gpio_exti_clear_flag_status(uint16_t pin); /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..1a3705a37c5dc755e75fb74fd27663abda790370 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2c.h @@ -0,0 +1,453 @@ +/** + ********************************************************************************* + * + * @file ald_i2c.h + * @brief Header file of I2C driver + * + * @version V1.0 + * @date 15 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_I2C_H__ +#define __ALD_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" +#include "ald_cmu.h" +#include + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Public_Types I2C Public Types + * @{ + */ +/** + * @brief I2C Error Code + */ +typedef enum { + I2C_ERROR_NONE = 0x0, /**< No error */ + I2C_ERROR_BERR = 0x1, /**< Berr error */ + I2C_ERROR_ARLO = 0x2, /**< Arlo error */ + I2C_ERROR_RUD = 0x4, /**< Rx underflow error */ + I2C_ERROR_AF = 0x8, /**< Af error */ + I2C_ERROR_ROV = 0x10, /**< Rx overflow error */ + I2C_ERROR_RF = 0x20, /**< Rx full error */ + I2C_ERROR_TUD = 0x40, /**< Tx underflow error */ + I2C_ERROR_TOV = 0x80, /**< Tx overflow error */ + I2C_ERROR_TE = 0x100, /**< Tx empty error */ + I2C_ERROR_DMA = 0x200, /**< Dma error */ + I2C_ERROR_TIMEOUT = 0x400 /**< Timeout error */ +} i2c_error_t; + +/** + * @brief I2C state structure definition + */ +typedef enum { + I2C_STATE_RESET = 0x0, /**< Peripheral is not yet Initialized */ + I2C_STATE_READY = 0x20, /**< Peripheral Initialized and ready for use */ + I2C_STATE_BUSY = 0x24, /**< An internal process is ongoing */ + I2C_STATE_BUSY_TX = 0x21, /**< Data Transmission process is ongoing */ + I2C_STATE_BUSY_RX = 0x22, /**< Data Reception process is ongoing */ + I2C_STATE_TIMEOUT = 0xA0, /**< timeout state */ + I2C_STATE_ERROR = 0xE0 /**< Error */ +} i2c_state_t; + +/** + * @brief I2C Addressing Mode + */ +typedef enum { + I2C_ADDR_7BIT = 0x0, /**< 7 bit address */ + I2C_ADDR_10BIT = 0x1, /**< 10 bit address */ +} i2c_addr_t; + +/** + * @brief I2C Dual Addressing Mode + */ +typedef enum { + I2C_DUALADDR_DISABLE = 0x0, /**< dual address is disable */ + I2C_DUALADDR_ENABLE = 0x1 /**< dual address is enable */ +} i2c_dual_addr_t; + +/** + * @brief I2C General Call Addressing mode + */ +typedef enum { + I2C_GENERALCALL_DISABLE = 0x0, /**< general call address is disable */ + I2C_GENERALCALL_ENABLE = 0x1 /**< general call address is enable */ +} i2c_general_addr_t; + +/** + * @brief I2C Nostretch Mode + */ +typedef enum { + I2C_NOSTRETCH_DISABLE = 0x0, /**< Nostretch disable */ + I2C_NOSTRETCH_ENABLE = 0x1 /**< Nostretch enable */ +} i2c_nostretch_t; + +/** + * @brief I2C Memory Address Size + */ +typedef enum { + I2C_MEMADD_SIZE_8BIT = 0x8, /**< 8 bit memory address size */ + I2C_MEMADD_SIZE_16BIT = 0x10 /**< 10 bit memory address size */ +} i2c_addr_size_t; + +/** + * @brief I2C mode structure definition + */ +typedef enum +{ + I2C_MODE_NONE = 0x0, /**< No I2C communication on going */ + I2C_MODE_MASTER = 0x10, /**< I2C communication is in Master mode */ + I2C_MODE_SLAVE = 0x20, /**< I2C communication is in Slave mode */ + I2C_MODE_MEM = 0x40 /**< I2C communication is in Memory mode */ +} i2c_mode_t; + +/** + * @brief I2C Clock + */ +typedef enum { + I2C_STANDARD_MODE_MAX_CLK = 100000, /**< Standard mode clock */ + I2C_FAST_MODE_MAX_CLK = 400000, /**< Fast mode clock */ + I2C_EXTREME_FAST_MODE_MAX_CLK = 1000000, /**< Extreme mode clock */ +} i2c_clock_t; + +/** + * @brief I2C OAR2 Register + */ +typedef enum { + I2C_OAR2_ENDUAL = (1U << 0), /**< ENDUAL BIT */ + I2C_OAR2_ADD2 = (1U << 1) /**< ADD2 BIT */ +} i2c_oar2_t; + +/** + * @brief I2C CON1 Register + */ +typedef enum { + I2C_CON1_PE = (1U << 0), /**< Peripheral enable BIT */ + I2C_CON1_TXDMA = (1U << 14), /**< Transmit DMA BIT */ + I2C_CON1_RXDMA = (1U << 15), /**< Receive DMA BIT */ + I2C_CON1_SBC = (1U << 16), /**< Receive DMA BIT */ + I2C_CON1_NOSTRETCH = (1U << 17), /**< Slave bytes control BIT */ + I2C_CON1_GCEN = (1U << 19), /**< General call BIT */ + I2C_CON1_SMBHEN = (1U << 20), /**< SMBus slave device enable BIT */ + I2C_CON1_SMBDEN = (1U << 21), /**< SMBus master device enable BIT */ + I2C_CON1_ALERTEN = (1U << 22), /**< SMBus alert device enable BIT */ + I2C_CON1_PECEN = (1U << 23), /**< PEC enable BIT */ +} i2c_con1_t; + +/** + * @brief I2C CON2 Register + */ +typedef enum { + I2C_CON2_RD_WRN = (1U << 10), /**< Master R/W control BIT */ + I2C_CON2_ADD10 = (1U << 11), /**< 10bit address control BIT */ + I2C_CON2_HEAD10R = (1U << 12), /**< 10bit address master Receive control BIT */ + I2C_CON2_START = (1U << 13), /**< Master start singal control BIT */ + I2C_CON2_STOP = (1U << 14), /**< Master stop singal control BIT */ + I2C_CON2_NACK = (1U << 15), /**< Master Nack control BIT */ + I2C_CON2_RELOAD = (1U << 24), /**< Master communication reload control BIT */ + I2C_CON2_AUTOEND = (1U << 25), /**< Master Autoend control BIT */ + I2C_CON2_PECBYTE = (1U << 26), /**< PEC control BIT */ + I2C_CON2_HOLDACK = (1U << 28), /**< Hold ack control BIT */ +} i2c_con2_t; + +/** + * @brief I2C ADDR1 Register + */ +typedef enum { + I2C_OA1MODE = (1U << 10), /**< Addr1 bits choose BIT */ + I2C_OA1EN = (1U << 15), /**< Addr1 enable BIT */ +} i2c_addr1_t; + +/** + * @brief I2C ADDR2 Register + */ +typedef enum { + I2C_OA2EN = (1U << 15), /**< Addr2 enable BIT */ +} i2c_addr2_t; + +/** + * @brief I2C TIMEOUTR Register + */ +typedef enum { + I2C_TIMEOUTR_TIDLE = (1U << 12), /**< SCL idle check enable BIT */ + I2C_TIMEOUTR_TIMEOUTEN = (1U << 15), /**< Timeout enable BIT */ +} i2c_timoutr_t; + +/** + * @brief I2C peripherals module + */ +typedef enum { + I2C_MODULE_MASTER = (1U << 0), /**< Master module */ + I2C_MODULE_SLAVE = (1U << 1) /**< Slave module */ +} i2c_module_t; + +/** + * @brief I2C STAT Register + */ +typedef enum { + I2C_STAT_TXE = (1U << 0), /**< Transmit FIFO empty flag */ + I2C_STAT_TXF = (1U << 1), /**< Transmit FIFO full flag */ + I2C_STAT_TXOV = (1U << 2), /**< Transmit FIFO overrun flag */ + I2C_STAT_TXUD = (1U << 3), /**< Transmit FIFO underrun flag*/ + I2C_STAT_THTH = (1U << 4), /**< Transmit FIFO threshold flag */ + I2C_STAT_RXE = (1U << 5), /**< Receive FIFO empty flag*/ + I2C_STAT_RXF = (1U << 6), /**< Receive FIFO full flag*/ + I2C_STAT_RXOV = (1U << 7), /**< Receive FIFO overrun flag */ + I2C_STAT_RXUD = (1U << 8), /**< Receive FIFO underrun flag */ + I2C_STAT_RXTH = (1U << 9), /**< Receive FIFO threshold flag */ + I2C_STAT_TC = (1U << 10), /**< Transmit completed flag */ + I2C_STAT_TCR = (1U << 11), /**< Transmit and reload completed flag */ + I2C_STAT_BUSY = (1U << 15), /**< Bus status busy flag */ + I2C_STAT_DIR = (1U << 16), /**< Slave R/W flag */ +} i2c_stat_t; + +/** + * @brief Interrupt Configuration Definition + */ +typedef enum { + I2C_IT_TXE = (1U << 0), /**< Transmit FIFO empty interrupt */ + I2C_IT_TXOV = (1U << 2), /**< Transmit FIFO overrun interrupt */ + I2C_IT_TXUD = (1U << 3), /**< Transmit FIFO underrun interrupt*/ + I2C_IT_TXTH = (1U << 4), /**< Transmit FIFO threshold interrupt */ + I2C_IT_RXF = (1U << 6), /**< Receive FIFO full interrupt*/ + I2C_IT_RXOV = (1U << 7), /**< Receive FIFO overrun interrupt */ + I2C_IT_RXUD = (1U << 8), /**< Receive FIFO underrun interrupt */ + I2C_IT_RXTH = (1U << 9), /**< Receive FIFO threshold interrupt */ + I2C_IT_TC = (1U << 10), /**< Transmit completed interrupt */ + I2C_IT_TCR = (1U << 11), /**< Transmit and reload completed interrupt */ + I2C_IT_ADDR = (1U << 12), /**< Address matching interrupt */ + I2C_IT_NACK = (1U << 13), /**< NACK interrupt */ + I2C_IT_STOP = (1U << 14), /**< Stop detection interrupt */ + I2C_IT_BERR = (1U << 16), /**< Bus error interrupt */ + I2C_IT_ARLO = (1U << 17), /**< Arbitration loss interrupt */ + I2C_IT_PECE = (1U << 18), /**< PEC error interrupt */ + I2C_IT_TOUT = (1U << 19), /**< Timeout interrupt */ + I2C_IT_ALERT = (1U << 20), /**< SMBus Alert interrupt */ +} i2c_interrupt_t; + +/** + * @brief I2C TRISE Register + */ +typedef enum { + I2C_TRISE_TRISE = 0x3F, /**< TRISE BITS */ +} i2c_trise_t; + +/** + * @brief I2C Configuration Structure definition + */ +typedef struct { + i2c_module_t module; /**< Specifies the communication module */ + uint32_t clk_speed; /**< Specifies the clock frequency */ + uint32_t own_addr1; /**< Specifies the first device own address */ + i2c_addr_t addr_mode; /**< Specifies addressing mode */ + i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ + uint32_t own_addr2; /**< Specifies the second device own address */ + i2c_general_addr_t general_call;/**< Specifies if general call mode is selected */ + i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ +} i2c_init_t; + +/** + * @brief I2C handle Structure definition + */ +typedef struct i2c_handle_s { + I2C_TypeDef *perh; /**< I2C registers base address */ + i2c_init_t init; /**< I2C communication parameters */ + uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ + uint16_t xfer_size; /**< I2C transfer size */ + __IO uint16_t xfer_count; /**< I2C transfer counter */ +#ifdef ALD_DMA + dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ +#endif + lock_state_t lock; /**< I2C locking object */ + __IO i2c_state_t state; /**< I2C communication state */ + __IO i2c_mode_t mode; /**< I2C communication mode */ + __IO uint32_t error_code; /**< I2C Error code */ + + void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Tx completed callback */ + void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Rx completed callback */ + void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Tx completed callback */ + void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Rx completed callback */ + void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Tx to Memory completed callback */ + void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Rx from Memory completed callback */ + void (*error_callback)(struct i2c_handle_s *arg); /**< Error callback */ +} i2c_handle_t; + +/** + * @} + */ + +/** @defgroup I2C_Public_Macro I2C Public Macros + * @{ + */ +#define I2C_FLAG_MASK (0xFFFFFFFF) +#define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET) +#define I2C_ENABLE_IT(x, y) (SET_BIT((x)->perh->IER, (y))) +#define I2C_DISABLE_IT(x, y) (SET_BIT((x)->perh->IDR, (y))) +#define I2C_CLEAR_IT(x, y) (SET_BIT((x)->perh->ICR, (y))) +#define I2C_GET_IT_FLAG(x, y) (READ_BIT((x)->perh->RIF, (y))) +#define I2C_GET_IT_SOURCE(x, y) ((((x)->perh->IFM & (y)) == (y)) ? SET : RESET) +#define I2C_GET_FLAG(x, y) ((((x)->perh->STAT) & ((y) & I2C_FLAG_MASK)) != RESET) +#define I2C_MASTER_GET_DIR(x) (READ_BIT(((x)->perh->CON2), I2C_CON2_RD_WRN_MSK)) +#define I2C_SLAVE_GET_DIR(x) (READ_BIT(hperh->perh->STAT, I2C_STAT_DIR_MSK)) +#define I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PE_MSK)) +#define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PE_MSK)) +/** + * @} + */ + +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ +#define IS_I2C_TYPE(x) (((x) == I2C0) || ((x) == I2C1)) +#define IS_I2C_MODULE(x) (((x) == I2C_MODULE_MASTER) || ((x) == I2C_MODULE_SLAVE)) +#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDR_7BIT) || \ + ((ADDRESS) == I2C_ADDR_10BIT)) +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDR_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDR_ENABLE)) +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) +#define IS_I2C_MEMADD_size(size) (((size) == I2C_MEMADD_SIZE_8BIT) || \ + ((size) == I2C_MEMADD_SIZE_16BIT)) +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= I2C_EXTREME_FAST_MODE_MAX_CLK) ) +#define I2C_FREQ_RANGE(__PCLK__) ((__PCLK__) / 1000000) +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) &\ + (uint16_t)(0xFF00))) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) +#define IS_I2C_IT(x) (((x) == I2C_IT_TXE) || \ + ((x) == I2C_IT_TXOV) || \ + ((x) == I2C_IT_TXUD) || \ + ((x) == I2C_IT_TXTH) || \ + ((x) == I2C_IT_RXF) || \ + ((x) == I2C_IT_RXOV) || \ + ((x) == I2C_IT_RXUD) || \ + ((x) == I2C_IT_RXTH) || \ + ((x) == I2C_IT_TC) || \ + ((x) == I2C_IT_TCR) || \ + ((x) == I2C_IT_ADDR) || \ + ((x) == I2C_IT_NACK) || \ + ((x) == I2C_IT_STOP) || \ + ((x) == I2C_IT_BERR) || \ + ((x) == I2C_IT_ARLO) || \ + ((x) == I2C_IT_PECE) || \ + ((x) == I2C_IT_TOUT) || \ + ((x) == I2C_IT_ALERT)) +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions + * @{ + */ + +/** @addtogroup I2C_Public_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +ald_status_t ald_i2c_init(i2c_handle_t *hperh); +ald_status_t ald_i2c_reset(i2c_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group2 Input and Output operation functions + * @{ + */ + /** Blocking mode: Polling */ +ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout); + + /** Non-Blocking mode: Interrupt */ +ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint32_t size); + +#ifdef ALD_DMA + /** Non-Blocking mode: DMA */ +ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint8_t size, uint8_t channel); +ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint8_t size, uint8_t channel); +ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel); +ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel); +ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint8_t size, uint8_t channel); +ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint8_t size, uint8_t channel); +#endif +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group3 Peripheral state and Errors functions + * @{ + */ +i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh); +uint32_t ald_i2c_get_error(i2c_handle_t *hperh); +void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag); +flag_status_t ald_i2c_get_mask_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag); +flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag); +it_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it); +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group4 IRQ Handler and Callbacks + * @{ + */ +void ald_i2c_ev_irq_handler(i2c_handle_t *hperh); +void ald_i2c_er_irq_handler(i2c_handle_t *hperh); +void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_I2C_H__ */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h new file mode 100644 index 0000000000000000000000000000000000000000..94fedffd23c97839afe5ee56a19666a31a7c0396 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_i2s.h @@ -0,0 +1,393 @@ +/** + ********************************************************************************* + * + * @file ald_i2s.c + * @brief Header file of I2S module driver. + * + * @version V1.0 + * @date 13 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_I2S_H__ +#define __ALD_I2S_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + +/** @defgroup I2S_Public_Types I2S Public Types + * @{ + */ + +/** + * @brief Channel length + */ +typedef enum { + I2S_WIDE_16 = 0, /**< Channel length is 16 */ + I2S_WIDE_32 = 1, /**< Channel length is 32 */ +} i2s_chlen_t; + +/** + * @brief Data length + */ +typedef enum { + I2S_LEN_16 = 0, /**< Data length is 16 */ + I2S_LEN_24 = 1, /**< Data length is 24 */ + I2S_LEN_32 = 2, /**< Data length is 32 */ +} i2s_datalen_t; + +/** + * @brief Inactive state clock polarity + */ +typedef enum { + I2S_INACTIVE_LOW = 0, /**< Inactive state is low */ + I2S_INACTIVE_HIGH = 1, /**< Inactive state is high */ +} i2s_cpol_t; + +/** + * @brief I2s standard + */ +typedef enum { + I2S_PHILIPS_STANDARD = 0, /**< Philips standard */ + I2S_MSB_JUSTIFIED_STANDARD = 1, /**< MSB standard */ + I2S_LSB_JUSTIFIED_STANDARD = 2, /**< LSB standard */ + I2S_PCM_STANDARD = 3, /**< PCM standard */ +} i2s_standard_t; + +/** + * @brief I2s configuration mode + */ +typedef enum { + I2S_SLAVE_TRANSMIT = 0, /**< I2S slaver transmit mode */ + I2S_SLAVE_RECEIVE = 1, /**< I2S slaver receive mode */ + I2S_MASTER_TRANSMIT = 2, /**< I2S master transmit mode */ + I2S_MASTER_RECEIVE = 3, /**< I2S master receive mode */ +} i2s_cfg_t; + +/** + * @brief Pcm frame synchronization + */ +typedef enum { + I2S_SHORT_FRAME = 0, /**< I2S PCM short frame */ + I2S_LONG_FRAME = 1, /**< I2S PCM long frame */ +} i2s_pcms_t; + +/** + * @brief Odd factor for prescaler + */ +typedef enum { + I2S_ODD_0 = 0, /**< Odd factor 0 */ + I2S_ODD_1 = 1, /**< Odd factor 1 */ +} i2s_odd_t; + +/** + * @brief I2S error status + */ +typedef enum { + I2S_ERROR_NONE = 0, /**< none */ + I2S_ERROR_MODF = 1, /**< mode fault */ + I2S_ERROR_DMA = 2, /**< crc error */ + I2S_ERROR_FRE = 4, /**< frame error */ + I2S_ERROR_RXOV = 8, /**< receive over error */ + I2S_ERROR_TXOV = 0x10, /**< dma error */ + I2S_ERROR_FLAG = 0x20, /**< interrupt flag error */ +} i2s_error_t; + +/** + * @brief interrupt control + */ +typedef enum { + I2S_IT_TXE = (1U << 0), /**< Transmit fifo empty interrupt */ + I2S_IT_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt */ + I2S_IT_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt */ + I2S_IT_RXF = (1U << 9), /**< Receive fifo full interrupt */ + I2S_IT_RXOV = (1U << 10), /**< Receive fifo overflow interrupt */ + I2S_IT_RXUD = (1U << 11), /**< Receive fifo underflow interrupt */ + I2S_IT_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt */ + I2S_IT_CRCERR = (1U << 16), /**< Crc error interrupt */ + I2S_IT_MODF = (1U << 17), /**< Mode error interrupt */ + I2S_IT_FRE = (1U << 18), /**< Frame error interrupt */ +} i2s_it_t; + +/** + * @brief I2S dma request definition + */ +typedef enum { + I2S_DMA_REQ_TX = 0, /**< TX dma request */ + I2S_DMA_REQ_RX = 1, /**< RX dma request */ +} i2s_dma_req_t; + +/** + * @brief interrupt flag + */ +typedef enum { + I2S_IF_TXE = (1U << 0), /**< Transmit fifo empty interrupt flag */ + I2S_IF_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt flag */ + I2S_IF_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt flag */ + I2S_IF_RXF = (1U << 9), /**< Receive fifo full interrupt flag */ + I2S_IF_RXOV = (1U << 10), /**< Receive fifo overflow interrupt flag */ + I2S_IF_RXUD = (1U << 11), /**< Receive fifo underflow interrupt flag */ + I2S_IF_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt flag */ + I2S_IF_FRE = (1U << 18), /**< Frame error interrupt flag */ +} i2s_flag_t; + +/** + * @brief I2S state structures definition + */ +typedef enum { + I2S_STATE_RESET = 0x00, /**< Peripheral is not initialized */ + I2S_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + I2S_STATE_BUSY = 0x02, /**< an internal process is ongoing */ + I2S_STATE_BUSY_TX = 0x11, /**< transmit is ongoing */ + I2S_STATE_BUSY_RX = 0x21, /**< receive is ongoing */ + I2S_STATE_BUSY_TX_RX = 0x31, /**< transmit and receive are ongoing */ + I2S_STATE_TIMEOUT = 0x03, /**< Timeout state */ + I2S_STATE_ERROR = 0x04, /**< Error */ +} i2s_state_t; + +/** + * @brief I2S status definition + */ +typedef enum { + I2S_STATUS_TXE = (1U << 0), /**< Transmit fifo empty status */ + I2S_STATUS_TXF = (1U << 1), /**< Transmit fifo full status */ + I2S_STATUS_TXOV = (1U << 2), /**< Transmit fifo overflow status */ + I2S_STATUS_TXUD = (1U << 3), /**< Transmit fifo underflow status */ + I2S_STATUS_RXE = (1U << 8), /**< Receive fifo empty status */ + I2S_STATUS_RXF = (1U << 9), /**< Receive fifo full status */ + I2S_STATUS_RXOV = (1U << 10), /**< Receive fifo overflow status */ + I2S_STATUS_RXUD = (1U << 11), /**< Receive fifo underflow status */ + I2S_STATUS_CHSIDE = (1U << 14), /**< Sound channel status */ + I2S_STATUS_BUSY = (1U << 15), /**< BUSY status */ +} i2s_status_t; + +/** + * @brief Channel side + */ +typedef enum { + I2S_LEFT_SIDE = 0, /**< Sound channel is left */ + I2S_RIGHT_SIDE = 1 /**< Sound channel is right */ +} i2s_ch_side_t; + +/** + * @brief I2S TXE/RXNE status definition + */ +typedef enum { + I2S_SR_TXE = 0, /**< STAT TXE set */ + I2S_SR_RXNE = 1, /**< STAT RXTH set */ + I2S_SR_TXE_RXNE = 2, /**< STAT TXE and RXTH set */ +} i2s_sr_status_t; + + +/** + * @brief I2S init structure definition + */ +typedef struct { + i2s_chlen_t ch_len; /**< Channel length choose */ + i2s_datalen_t data_len; /**< Data length choose */ + i2s_cpol_t polarity; /**< Inactive clock polarity */ + i2s_standard_t standard; /**< Standard choose */ + i2s_pcms_t pcm_frame; /**< PCM frame synchronization */ + type_func_t ext_ck; /**< External clock choose */ + type_func_t mck_en; /**< Main clock output function */ + i2s_odd_t odd; /**< Odd frame choose */ + uint8_t div; /**< Clock divide */ +} i2s_init_t; + +/** + * @brief I2S handle structure definition + */ +typedef struct i2s_handle_s { + SPI_I2S_TypeDef *perh; /**< I2S registers base address */ + i2s_init_t init; /**< I2S communication parameters */ + uint16_t *tx_buf; /**< Pointer to I2S Tx transfer buffer */ + uint16_t tx_size; /**< I2S Tx transfer size */ + uint16_t tx_count; /**< I2S Tx transfer counter */ + uint16_t *rx_buf; /**< Pointer to I2S Rx transfer buffer */ + uint16_t rx_size; /**< I2S Rx Transfer size */ + uint16_t rx_count; /**< I2S Rx Transfer Counter */ +#ifdef ALD_DMA + dma_handle_t hdma; /**< I2S DMA handle parameters */ +#endif + lock_state_t lock; /**< Locking object */ + i2s_state_t state; /**< I2S communication state */ + uint8_t side; /**< I2S channel side */ + uint32_t err_code; /**< I2S error code */ + + void (*tx_cplt_cbk)(struct i2s_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct i2s_handle_s *arg); /**< Rx completed callback */ + void (*err_cbk)(struct i2s_handle_s *arg); /**< error callback */ +} i2s_handle_t; +/** + * @} + */ + +/** @defgroup I2S_Public_Macros I2S Public Macros + * @{ + */ +#define I2S_RESET_HANDLE_STATE(x) ((x)->state = I2S_STATE_RESET) +#define I2S_ENABLE(x) (SET_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK)) +#define I2S_DISABLE(x) (CLEAR_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK)) +/** + * @} + */ + +/** @defgroup I2S_Private_Macros I2S Private Macros + * @{ + */ +#define IS_I2S(x) (((x) == I2S0) || \ + ((x) == I2S1) || \ + ((x) == I2S2)) +#define IS_I2S_CH_LEN(x) (((x) == I2S_WIDE_16) || \ + ((x) == I2S_WIDE_32)) +#define IS_I2S_DATE_LEN(x) (((x) == I2S_LEN_16) || \ + ((x) == I2S_LEN_24) || \ + ((x) == I2S_LEN_32)) +#define IS_I2S_CPOL(x) (((x) == I2S_INACTIVE_LOW) || \ + ((x) == I2S_INACTIVE_HIGH)) +#define IS_I2S_STANDARD(x) (((x) == I2S_PHILIPS_STANDARD) || \ + ((x) == I2S_MSB_JUSTIFIED_STANDARD) || \ + ((x) == I2S_LSB_JUSTIFIED_STANDARD) || \ + ((x) == I2S_PCM_STANDARD)) +#define IS_I2S_PCMS(x) (((x) == I2S_SHORT_FRAME) || \ + ((x) == I2S_LONG_FRAME)) +#define IS_I2S_ODD(x) (((x) == I2S_ODD_0) || \ + ((x) == I2S_ODD_1)) +#define IS_I2S_DIV(x) ((x) >= 2) +#define IS_I2S_IT(x) (((x) == I2S_IT_TXE) || \ + ((x) == I2S_IT_TXOV) || \ + ((x) == I2S_IT_TXUD) || \ + ((x) == I2S_IT_RXF) || \ + ((x) == I2S_IT_RXOV) || \ + ((x) == I2S_IT_RXUD) || \ + ((x) == I2S_IT_RXTH) || \ + ((x) == I2S_IT_CRCERR) || \ + ((x) == I2S_IT_MODF) || \ + ((x) == I2S_IT_FRE)) +#define IS_I2S_IF(x) (((x) == I2S_IF_TXE) || \ + ((x) == I2S_IF_TXOV) || \ + ((x) == I2S_IF_TXUD) || \ + ((x) == I2S_IF_RXF) || \ + ((x) == I2S_IF_RXOV) || \ + ((x) == I2S_IF_RXUD) || \ + ((x) == I2S_IF_RXTH) || \ + ((x) == I2S_IF_FRE)) +#define IS_I2S_FLAG(x) (((x) == I2S_FLAG_TXE) || \ + ((x) == I2S_FLAG_TXF) || \ + ((x) == I2S_FLAG_TXOV) || \ + ((x) == I2S_FLAG_TXUD) || \ + ((x) == I2S_FLAG_RXE) || \ + ((x) == I2S_FLAG_RXF) || \ + ((x) == I2S_FLAG_RXOV) || \ + ((x) == I2S_FLAG_RXUD) || \ + ((x) == I2S_FLAG_CHSIDE) || \ + ((x) == I2S_FLAG_BSY)) +#define IS_I2S_STATUS(x) (((x) == I2S_STATUS_TXE) || \ + ((x) == I2S_STATUS_TXF) || \ + ((x) == I2S_STATUS_TXOV) || \ + ((x) == I2S_STATUS_TXUD) || \ + ((x) == I2S_STATUS_RXE) || \ + ((x) == I2S_STATUS_RXF) || \ + ((x) == I2S_STATUS_RXOV) || \ + ((x) == I2S_STATUS_RXUD) || \ + ((x) == I2S_STATUS_CHSIDE) || \ + ((x) == I2S_STATUS_BUSY)) +#define IS_I2S_DMA_REQ(x) (((x) == I2S_DMA_REQ_TX) || \ + ((x) == I2S_DMA_REQ_RX)) +/** + * @} + */ + +/** @addtogroup I2S_Public_Functions + * @{ + */ + +/** @addtogroup I2S_Public_Functions_Group1 + * @{ + */ + +ald_status_t ald_i2s_init(i2s_handle_t *hperh); +void ald_i2s_reset(i2s_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup I2S_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_i2s_master_send(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_i2s_master_recv(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_i2s_slave_send(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_i2s_slave_recv(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_i2s_master_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16_t size); +ald_status_t ald_i2s_master_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16_t size); +ald_status_t ald_i2s_slave_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16_t size); +ald_status_t ald_i2s_slave_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16_t size); +#ifdef ALD_DMA +ald_status_t ald_i2s_master_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2s_master_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2s_slave_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2s_slave_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_i2s_dma_pause(i2s_handle_t *hperh); +ald_status_t ald_i2s_dma_resume(i2s_handle_t *hperh); +ald_status_t ald_i2s_dma_stop(i2s_handle_t *hperh); +#endif +/** + * @} + */ + +/** @addtogroup I2S_Public_Functions_Group3 + * @{ + */ +void ald_i2s_irq_handler(i2s_handle_t *hperh); +void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state); +void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state); +flag_status_t ald_i2s_get_flag_status(i2s_handle_t *hperh, i2s_flag_t flag); +it_status_t ald_i2s_get_it_status(i2s_handle_t *hperh, i2s_it_t it); +flag_status_t ald_i2s_get_it_flag_status(i2s_handle_t *hperh, i2s_flag_t flag); +void ald_i2s_clear_flag_status(i2s_handle_t *hperh, i2s_flag_t flag); +/** + * @} + */ + +/** @addtogroup I2S_Public_Functions_Group4 + * @{ + */ +i2s_state_t ald_i2s_get_state(i2s_handle_t *hperh); +uint32_t ald_i2s_get_error(i2s_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h new file mode 100644 index 0000000000000000000000000000000000000000..1f15f0851d9bc15fdbe4f78d7887659eb6fb8d86 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_iap.h @@ -0,0 +1,80 @@ +/** + ********************************************************************************* + * + * @file ald_iap.h + * @brief Header file of IAP module driver. + * + * @version V1.0 + * @date 04 Dec 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_IAP_H__ +#define __ALD_IAP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup IAP + * @{ + */ + +/** + * @defgroup IAP_Private_Macros IAP Private Macros + * @{ + */ +#define IAP_WSP_ADDR 0x10000000 +#define IAP_PE_ADDR 0x10000004 +#define IAP_WP_ADDR 0x10000008 +#define IAP_DWP_ADDR 0x1000000c +/** + * @} + */ + +/** @defgroup IAP_Private_Types IAP Private Types + * @{ + */ +typedef uint32_t (*IAP_PE)(uint32_t addr); +typedef uint32_t (*IAP_WP)(uint32_t addr, uint32_t data); +typedef uint32_t (*IAP_DWP)(uint32_t addr, uint32_t data_l, uint32_t data_h); +typedef uint32_t (*IAP_WSP)(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase); +/** + * @} + */ + +/** @addtogroup IAP_Public_Functions + * @{ + */ +uint32_t ald_iap_erase_page(uint32_t addr); +uint32_t ald_iap_program_word(uint32_t addr, uint32_t data); +uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h); +uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_IAP_H__ */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h new file mode 100644 index 0000000000000000000000000000000000000000..91dd22f9efce036ece3313f048907f4fefd9094c --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nand.h @@ -0,0 +1,206 @@ +/** + ********************************************************************************* + * + * @file ald_nand.h + * @brief Header file of EBI_NAND module driver + * + * @version V1.0 + * @date 07 Dec 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_NAND_H_ +#define __ALD_NAND_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ald_ebi.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup NAND + * @{ + */ + +/** @defgroup NAND_Public_Types NAND Public Types + * @{ + */ + +/** + * @brief NAND State structures definition + */ +typedef enum { + ALD_NAND_STATE_RESET = 0x00U, /**< NAND not yet initialized or disabled */ + ALD_NAND_STATE_READY = 0x01U, /**< NAND initialized and ready for use */ + ALD_NAND_STATE_BUSY = 0x02U, /**< NAND internal process is ongoing */ + ALD_NAND_STATE_ERROR = 0x03U /**< NAND error state */ +} ald_nand_state_t; + +/** + * @brief NAND Memory electronic signature Structure definition + */ +typedef struct { + uint8_t maker_id; /**< Maker id */ + uint8_t device_id; /**< Device id */ + uint8_t third_id; /**< Third id */ + uint8_t fourth_id; /**< Fourth id */ +} nand_id_t; + +/** + * @brief NAND Memory address Structure definition + */ +typedef struct +{ + uint16_t page; /**< NAND memory Page address */ + uint16_t plane; /**< NAND memory Plane address */ + uint16_t block; /**< NAND memory Block address */ +} nand_address_t; + +/** + * @brief NAND Memory info Structure definition + */ +typedef struct +{ + uint32_t page_size; /**< NAND memory page (without spare area) size measured in bytes */ + uint32_t spare_size; /**< NAND memory spare area size measured in bytes */ + uint32_t block_size; /**< NAND memory block size measured in number of pages */ + uint32_t block_nbr; /**< NAND memory number of total block */ + uint32_t plane_nbr; /**< NAND memory number of planes */ + uint32_t plane_size; /**< NAND memory plane size measured in number of blocks */ + type_func_t extra_cmd; /**< NAND extra command needed for Page reading mode */ +} nand_device_cfg_t; + +/** + * @brief NAND handle Structure definition + */ +typedef struct +{ + EBI_NAND_TypeDef *instance; /**< Register base address */ + ald_ebi_nand_init_t init; /**< NAND device control configuration parameters */ + lock_state_t lock; /**< NAND locking object */ + __IO ald_nand_state_t state; /**< NAND device access state */ + nand_device_cfg_t config; /**< NAND phusical characteristic information structure */ +} nand_handle_t; + +/** + * @} + */ + +/** + * @defgroup Nand_Private_Constants Nand Private Constants + * @{ + */ + +#define NAND_DEVICE1 EBI_BANK2 +#define NAND_DEVICE2 EBI_BANK3 +#define NAND_WRITE_TIMEOUT 1000U +#define CMD_AREA (1U<<16U) /* A16 = CLE high */ +#define ADDR_AREA (1U<<17U) /* A17 = ALE high */ +#define NAND_CMD_AREA_A ((uint8_t)0x00) +#define NAND_CMD_AREA_B ((uint8_t)0x01) +#define NAND_CMD_AREA_C ((uint8_t)0x50) +#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) +#define NAND_CMD_WRITE0 ((uint8_t)0x80) +#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) +#define NAND_CMD_ERASE0 ((uint8_t)0x60) +#define NAND_CMD_ERASE1 ((uint8_t)0xD0) +#define NAND_CMD_READID ((uint8_t)0x90) +#define NAND_CMD_STATUS ((uint8_t)0x70) +#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) +#define NAND_CMD_RESET ((uint8_t)0xFF) +/* NAND memory status */ +#define NAND_VALID_ADDRESS 0x00000100U +#define NAND_INVALID_ADDRESS 0x00000200U +#define NAND_TIMEOUT_ERROR 0x00000400U +#define NAND_BUSY 0x00000000U +#define NAND_ERROR 0x00000001U +#define NAND_READY 0x00000040U +/** + * @} + */ + +/** @defgroup Nand_Private_Macros Nand Private Macros + * @{ + */ +#define ARRAY_ADDRESS(x , y) ((x)->page + \ + (((x)->block + (((x)->plane) * \ + ((y)->config.plane_size))) * ((y)->config.block_size))) +#define COLUMN_ADDRESS( x) ((x)->config.page_size) +#define ADDR_1ST_CYCLE(x) (uint8_t)(x) /* 1st addressing cycle */ +#define ADDR_2ND_CYCLE(x) (uint8_t)((x) >> 8U) /* 2nd addressing cycle */ +#define ADDR_3RD_CYCLE(x) (uint8_t)((x) >> 16U) /* 3rd addressing cycle */ +#define ADDR_4TH_CYCLE(x) (uint8_t)((x) >> 24U) /* 4th addressing cycle */ +#define COLUMN_1ST_CYCLE(x) (uint8_t)(x) /* 1st Column addressing cycle */ +#define COLUMN_2ND_CYCLE(x) (uint8_t)((x) >> 8U) /* 2nd Column addressing cycle */ +/** + * @} + */ + +/** @addtogroup Nand_Public_Functions + * @{ + */ +/** @addtogroup Nand_Public_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions */ +ald_status_t ald_nand_init(nand_handle_t *hperh, ald_ebi_nand_timing_t *ctiming, ald_ebi_nand_timing_t *atiming); +ald_status_t ald_nand_deinit(nand_handle_t *hperh); +ald_status_t ald_nand_reset(nand_handle_t *hperh); +void nand_config_device(nand_handle_t *hperh, nand_device_cfg_t *pdcfg); +/** + * @} + */ +/** @addtogroup Nand_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +ald_status_t ald_nand_read_id(nand_handle_t *hperh, nand_id_t *id); +ald_status_t ald_nand_read_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr); +ald_status_t ald_nand_write_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr); +ald_status_t ald_nand_read_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr); +ald_status_t ald_nand_write_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr); +ald_status_t ald_nand_read_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr); +ald_status_t ald_nand_write_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr); +ald_status_t ald_nand_read_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr); +ald_status_t ald_nand_write_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr); +ald_status_t ald_nand_erase_block(nand_handle_t *hperh, nand_address_t *addr); +/** + * @} + */ +/** @addtogroup Nand_Public_Functions_Group3 + * @{ + */ +/* NAND Control functions */ +void ald_nand_irq_handler(nand_handle_t *hperh); +void ald_nand_irq_cbk(nand_handle_t *hperh); +uint32_t ald_nand_address_inc(nand_handle_t *hperh, nand_address_t *addr); +uint32_t ald_nand_read_status(nand_handle_t *hperh); +ald_nand_state_t ald_nand_get_state(nand_handle_t *hperh); +ald_status_t ald_nand_ecc_enable(nand_handle_t *hperh); +ald_status_t ald_nand_ecc_disable(nand_handle_t *hperh); +ald_status_t ald_nand_get_ecc(nand_handle_t *hperh, uint32_t *val, uint32_t timeout); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h new file mode 100644 index 0000000000000000000000000000000000000000..425b28042b2f1f673cd89f64c49a4d908a4149f2 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_nor_lcd.h @@ -0,0 +1,220 @@ +/** + ********************************************************************************* + * + * @file ald_nor_lcd.h + * @brief Header file of EBI_NOR_LCD module driver + * + * @version V1.0 + * @date 07 Dec 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_NOR_LCD_H_ +#define __ALD_NOR_LCD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ald_ebi.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup NOR_LCD + * @{ + */ + +/** + * @defgroup NOR_LCD_Private_Constants NOR LCD Private Constants + * @{ + */ + +/* NOR device IDs addresses */ +#define MC_ADDRESS ((uint16_t)0x0000) +#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) +#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) +#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) + +/* NOR CFI IDs addresses */ +#define CFI1_ADDRESS ((uint16_t)0x10) +#define CFI2_ADDRESS ((uint16_t)0x11) +#define CFI3_ADDRESS ((uint16_t)0x12) +#define CFI4_ADDRESS ((uint16_t)0x13) + +/* NOR operation wait timeout */ +#define NOR_TMEOUT ((uint16_t)0xFFFF) + +/* NOR memory data width */ +#define NOR_MEMORY_8B ((uint8_t)0x0) +#define NOR_MEMORY_16B ((uint8_t)0x1) + +/* NOR memory device read/write start address */ +#define NOR_MEMORY_ADRESS1 EBI_BANK1_1 +#define NOR_MEMORY_ADRESS2 EBI_BANK1_2 +#define NOR_MEMORY_ADRESS3 EBI_BANK1_3 +#define NOR_MEMORY_ADRESS4 EBI_BANK1_4 + +#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555 +#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055 +#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA +#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555 +#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555 +#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA +#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555 + +#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0 +#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA +#define NOR_CMD_DATA_SECOND (uint16_t)0x0055 +#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090 +#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0 +#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080 +#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA +#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055 +#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010 +#define NOR_CMD_DATA_CFI (uint16_t)0x0098 +#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25 +#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29 +#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30 +#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020 +#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040 +/** + * @} + */ + +/** @defgroup NOR_LCD_Private_Macros NOR_LCD Private Macros + * @{ + */ +#define NOR_ADDR_SHIFT(NOR_ADDR, NOR_MEMORY_WIDTH_, ADDRESS) \ + ((uint32_t)(((NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B) ? \ + ((uint32_t)((NOR_ADDR) + (2U * (ADDRESS)))): \ + ((uint32_t)((NOR_ADDR) + (ADDRESS))))) +#define NOR_WRITE(ADDR, DATA) (*(__IO uint16_t *)((uint32_t)(ADDR)) = (DATA)) +/** + * @} + */ + +/** @defgroup NOR_LCD_Public_Types NOR_LCD Public Types + * @{ + */ +/** + * @brief ALD SRAM State structures definition + */ +typedef enum { + ALD_NOR_STATE_RESET = 0x00U, /**< NOR not yet initialized or disabled */ + ALD_NOR_STATE_READY = 0x01U, /**< NOR initialized and ready for use */ + ALD_NOR_STATE_BUSY = 0x02U, /**< NOR internal processing is ongoing */ + ALD_NOR_STATE_ERROR = 0x03U, /**< NOR error state */ + ALD_NOR_STATE_PROTECTED = 0x04U /**< NOR NORSRAM device write protected */ +} ald_nor_state_t; + +/** + * @brief EBI NOR Status typedef + */ +typedef enum { + ALD_NOR_STATUS_SUCCESS = 0, /**< NOR status success */ + ALD_NOR_STATUS_ONGOING, /**< NOR status ongoing */ + ALD_NOR_STATUS_ERROR, /**< NOR status error */ + ALD_NOR_STATUS_TIMEOUT, /**< NOR status timeout */ +} nor_status_t; + +/** + * @brief EBI NOR ID typedef + */ +typedef struct { + uint16_t m_code; /**< Defines the device's manufacturer code used to identify the memory */ + uint16_t device_code1; /**< DEVICE_CODE1_ADDR code1 */ + uint16_t device_code2; /**< DEVICE_CODE1_ADDR code2 */ + uint16_t device_code3; /**< DEVICE_CODE1_ADDR code3 */ +} nor_id_t; + +/** + * @brief EBI NOR CFI typedef + */ +typedef struct { + uint16_t cfi_1; /**< NOR CFI 1 */ + uint16_t cfi_2; /**< NOR CFI 2 */ + uint16_t cfi_3; /**< NOR CFI 3 */ + uint16_t cfi_4; /**< NOR CFI 4 */ +} nor_cfi_t; + +/** + * @brief NOR handle Structure definition + */ +typedef struct { + EBI_NOR_SRAM_TypeDef *instance; /**< Register base address */ + EBI_NOR_SRAM_EXTENDED_TypeDef *ext; /**< Extended mode register base address */ + ald_ebi_nor_sram_init_t init; /**< NOR device control configuration parameters */ + lock_state_t lock; /**< NOR locking object */ + __IO ald_nor_state_t state; /**< NOR device access state */ +} nor_handle_t; +/** + * @} + */ + +/** @addtogroup NOR_Public_Functions + * @{ + */ +/** @addtogroup NOR_Public_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions */ +ald_status_t ald_nor_init(nor_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing); +ald_status_t ald_nor_deinit(nor_handle_t *hperh); +/** + * @} + */ +/** @addtogroup NOR_LCD_Public_Functions_Group2 + * @{ + */ +/* I/O operation functions */ +ald_status_t ald_nor_read_id(nor_handle_t *hperh, nor_id_t *id); +ald_status_t ald_nor_return_readmode(nor_handle_t *hperh); +ald_status_t ald_nor_read(nor_handle_t *hperh, uint32_t *addr, uint16_t *data); +ald_status_t ald_nor_program(nor_handle_t *hperh, uint32_t *addr, uint16_t *data); +ald_status_t ald_nor_read_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size); +ald_status_t ald_nor_program_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size); +ald_status_t ald_nor_erase_block(nor_handle_t *hperh, uint32_t blkaddr, uint32_t addr); +ald_status_t ald_nor_erase_chip(nor_handle_t *hperh); +ald_status_t ald_nor_read_cfi(nor_handle_t *hperh, nor_cfi_t *cfi); +/** + * @} + */ +/** @addtogroup NOR_LCD_Public_Functions_Group3 + * @{ + */ +/* Control functions */ +ald_status_t ald_nor_write_enable(nor_handle_t *hperh); +ald_status_t ald_nor_write_disable(nor_handle_t *hperh); +/** + * @} + */ +/** @addtogroup NOR_LCD_Public_Functions_Group4 + * @{ + */ +/* State functions */ +ald_nor_state_t ald_nor_get_state(nor_handle_t *hperh); +nor_status_t ald_nor_get_status(nor_handle_t *hperh, uint32_t addr, uint32_t timeout); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_NOR_LCD_H__ */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h new file mode 100644 index 0000000000000000000000000000000000000000..bc47731ea16dfd6e9acf2fc5c9075b49165e6479 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pis.h @@ -0,0 +1,699 @@ +/** + ********************************************************************************* + * + * @file ald_pis.h + * @brief Header file of PIS driver. + * + * @version V1.0 + * @date 27 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_PIS_H__ +#define __ALD_PIS_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup PIS + * @{ + */ + +/** @defgroup PIS_Public_Types PIS Public Types + * @{ + */ + +/** + * @brief Producer entry + * @note + * ES32F36xx + * AD16C4T0 TIMER0 + * AD16C4T1 TIMER1 + * GP32C4T0 TIMER2 + * GP32C4T1 TIMER3 + * BS16T0 TIMER4 + * BS16T1 TIMER5 + * GP16C4T0 TIMER6 + * GP16C4T1 TIMER7 + * + * ES32F393x/ES32F336x/ES32F392x + * GP16C4T0 TIMER0 + * GP16C4T1 TIMER1 + * GP32C4T0 TIMER2 + * GP32C4T1 TIMER3 + * BS16T0 TIMER4 + * BS16T1 TIMER5 + * GP16C4T2 TIMER6 + * GP16C4T3 TIMER7 + */ +typedef enum { + PIS_NON = 0x0, /**< No async */ + PIS_GPIO_PIN0 = 0x10, /**< Pin0, level,support async */ + PIS_GPIO_PIN1 = 0x11, /**< Pin1, level,support async */ + PIS_GPIO_PIN2 = 0x12, /**< Pin2, level,support async */ + PIS_GPIO_PIN3 = 0x13, /**< Pin3, level,support async */ + PIS_GPIO_PIN4 = 0x14, /**< Pin4, level,support async */ + PIS_GPIO_PIN5 = 0x15, /**< Pin5, level,support async */ + PIS_GPIO_PIN6 = 0x16, /**< Pin6, level,support async */ + PIS_GPIO_PIN7 = 0x17, /**< Pin7, level,support async */ + PIS_GPIO_PIN8 = 0x18, /**< Pin8, level,support async */ + PIS_GPIO_PIN9 = 0x19, /**< Pin9, level,support async */ + PIS_GPIO_PIN10 = 0x1a, /**< Pin10, level,support async */ + PIS_GPIO_PIN11 = 0x1b, /**< Pin11, level,support async */ + PIS_GPIO_PIN12 = 0x1c, /**< Pin12, level,support async */ + PIS_GPIO_PIN13 = 0x1d, /**< Pin13, level,support async */ + PIS_GPIO_PIN14 = 0x1e, /**< Pin14, level,support async */ + PIS_GPIO_PIN15 = 0x1f, /**< Pin15, level,support async */ + PIS_ACMP_OUT0 = 0x30, /**< Acmp0 output, level,support async */ + PIS_ACMP_OUT1 = 0x31, /**< Acmp1 output, level,support async */ + PIS_DAC0_CH0 = 0x40, /**< Dac0 channel 0, pclk2 pulse,support async */ + PIS_DAC0_CH1 = 0x41, /**< Dac0 channel 1, pclk2 pulse,support async */ + PIS_ADC0_INJECT = 0x60, /**< Adc0 inject, pclk2 pulse,support async */ + PIS_ADC0_REGULAT = 0x61, /**< Adc0 regulat, pclk2 pulse,support async */ + PIS_ADC0_RESERVE = 0x62, /**< Adc0 reserve */ + PIS_LVD = 0x70, /**< Lvd, level,support async */ + PIS_UART0_RESERVE0 = 0x80, /**< Uart0 reserve bit 0 */ + PIS_UART0_RESERVE1 = 0x81, /**< Uart0 reserve bit 1*/ + PIS_UART0_IRDAOUT = 0x82, /**< Uart0 irdaout, level,support async */ + PIS_UART0_RTSOUT = 0x83, /**< Uart0 rtsout, level,support async */ + PIS_UART0_TXOUT = 0x84, /**< Uart0 txout, level,support async */ + PIS_UART0_SYN_SEND = 0x85, /**< Uart0 syn send, pulse,support async */ + PIS_UART0_SYN_RECV = 0x86, /**< Uart0 syn recv, pulse,support async */ + PIS_UART1_RESERVE0 = 0x90, /**< Uart1 reserve bit 0 */ + PIS_UART1_RESERVE1 = 0x91, /**< Uart1 reserve bit 1*/ + PIS_UART1_IRDA = 0x92, /**< Uart1 irdaout, level,support async */ + PIS_UART1_RTS = 0x93, /**< Uart1 rtsout, level,support async */ + PIS_UART1_TXOUT = 0x94, /**< Uart1 txout, level,support async */ + PIS_UART1_SYN_SEND = 0x95, /**< Uart1 syn send, pulse,support async */ + PIS_UART1_SYN_RECV = 0x96, /**< Uart1 syn recv, pulse,support async */ + PIS_UART2_RESERVE0 = 0xa0, /**< Uart2 reserve bit 0 */ + PIS_UART2_RESERVE1 = 0xa1, /**< Uart2 reserve bit 1*/ + PIS_UART2_IRDA = 0xa2, /**< Uart2 irdaout, level,support async */ + PIS_UART2_RTS = 0xa3, /**< Uart2 rtsout, level,support async */ + PIS_UART2_TXOUT = 0xa4, /**< Uart2 txout, level,support async */ + PIS_UART2_SYN_SEND = 0xa5, /**< Uart2 syn send, pulse,support async */ + PIS_UART2_SYN_RECV = 0xa6, /**< Uart2 syn recv, pulse,support async */ + PIS_UART3_RESERVE0 = 0xb1, /**< Uart3 reserve bit 0 */ + PIS_UART3_RESERVE1 = 0xb2, /**< Uart3 reserve bit 1*/ + PIS_UART3_IRDA = 0xb3, /**< Uart3 irdaout, level,support async */ + PIS_UART3_RTS = 0xb4, /**< Uart3 rtsout, level,support async */ + PIS_UART3_TXOUT = 0xb5, /**< Uart3 txout, level,support async */ + PIS_UART3_SYN_SEND = 0xb6, /**< Uart3 syn send, pulse,support async */ + PIS_UART3_SYN_RECV = 0xb7, /**< Uart3 syn recv, pulse,support async */ + PIS_UART4_RECV = 0xc0, /**< uart4 recv, plck1 pulse */ + PIS_UART4_SEND = 0xc1, /**< uart4 send, plck1 pulse */ + PIS_UART4_TXOUT = 0xc2, /**< uart4 txout, plck1 level */ + PIS_UART5_RECV = 0xd0, /**< uart5 recv, plck1 pulse */ + PIS_UART5_SEND = 0xd1, /**< uart5 send, plck1 pulse */ + PIS_UART5_TXOUT = 0xd2, /**< uart5 txout, plck1 level */ + PIS_SPI0_RECV = 0xe0, /**< Spi0 recv, plck1 pulse */ + PIS_SPI0_SEND = 0xe1, /**< Spi0 send, plck1 pulse */ + PIS_SPI0_NE = 0xe2, /**< Spi0 ne, plck1 level */ + PIS_SPI1_RECV = 0xf0, /**< Spi1 recv, plck1 pulse */ + PIS_SPI1_SEND = 0xf1, /**< Spi1 send, plck1 pulse */ + PIS_SPI1_NE = 0xf2, /**< Spi1 ne, plck1 level */ + PIS_I2C0_RECV = 0x100, /**< I2c0 recv, plck1 level */ + PIS_I2C0_SEND = 0x101, /**< I2c0 send, plck1 level */ + PIS_I2C1_RECV = 0x110, /**< I2c1 recv, plck1 level */ + PIS_I2C1_SEND = 0x111, /**< I2c1 send, plck1 level */ + PIS_TIMER0_UPDATA = 0x120, /**< Timer0 updata, plck1 pulse */ + PIS_TIMER0_TRIG = 0x121, /**< Timer0 trig, plck1 pulse */ + PIS_TIMER0_INPUT_1 = 0x122, /**< Timer0 chan1 input catch, plck1 pulse */ + PIS_TIMER0_OUTPUT_1 = 0x123, /**< Timer0 chan1 output compare, plck1 pulse */ + PIS_TIMER0_INPUT_2 = 0x124, /**< Timer0 chan2 input catch, plck1 pulse */ + PIS_TIMER0_OUTPUT_2 = 0x125, /**< Timer0 chan2 output compare, plck1 pulse */ + PIS_TIMER0_INPUT_3 = 0x126, /**< Timer0 chan3 input catch, plck1 pulse */ + PIS_TIMER0_OUTPUT_3 = 0x127, /**< Timer0 chan3 output compare, plck1 pulse */ + PIS_TIMER0_INPUT_4 = 0x128, /**< Timer0 chan4 input catch, plck1 pulse */ + PIS_TIMER0_OUTPUT_4 = 0x129, /**< Timer0 chan4 output compare, plck1 pulse */ + PIS_TIMER1_UPDATA = 0x130, /**< Timer1 updata, plck1 pulse */ + PIS_TIMER1_TRIG = 0x131, /**< Timer1 trig, plck1 pulse */ + PIS_TIMER1_INPUT_1 = 0x132, /**< Timer1 chan1 input catch, plck1 pulse */ + PIS_TIMER1_OUTPUT_1 = 0x133, /**< Timer1 chan1 output compare, plck1 pulse */ + PIS_TIMER1_INPUT_2 = 0x134, /**< Timer1 chan2 input catch, plck1 pulse */ + PIS_TIMER1_OUTPUT_2 = 0x135, /**< Timer1 chan2 output compare, plck1 pulse */ + PIS_TIMER1_INPUT_3 = 0x136, /**< Timer1 chan3 input catch, plck1 pulse */ + PIS_TIMER1_OUTPUT_3 = 0x137, /**< Timer1 chan3 output compare, plck1 pulse */ + PIS_TIMER1_INPUT_4 = 0x138, /**< Timer1 chan4 input catch, plck1 pulse */ + PIS_TIMER1_OUTPUT_4 = 0x139, /**< Timer1 chan4 output compare, plck1 pulse */ + PIS_TIMER2_UPDATA = 0x140, /**< Timer2 updata, plck1 pulse */ + PIS_TIMER2_TRIG = 0x141, /**< Timer2 trig, plck1 pulse */ + PIS_TIMER2_INPUT_1 = 0x142, /**< Timer2 chan1 input catch, plck1 pulse */ + PIS_TIMER2_OUTPUT_1 = 0x143, /**< Timer2 chan1 output compare, plck1 pulse */ + PIS_TIMER2_INPUT_2 = 0x144, /**< Timer2 chan2 input catch, plck1 pulse */ + PIS_TIMER2_OUTPUT_2 = 0x145, /**< Timer2 chan2 output compare, plck1 pulse */ + PIS_TIMER2_INPUT_3 = 0x146, /**< Timer2 chan3 input catch, plck1 pulse */ + PIS_TIMER2_OUTPUT_3 = 0x147, /**< Timer2 chan3 output compare, plck1 pulse */ + PIS_TIMER2_INPUT_4 = 0x148, /**< Timer2 chan4 input catch, plck1 pulse */ + PIS_TIMER2_OUTPUT_4 = 0x149, /**< Timer2 chan4 output compare, plck1 pulse */ + PIS_TIMER3_UPDATA = 0x150, /**< Timer3 updata, plck1 pulse */ + PIS_TIMER3_TRIG = 0x151, /**< Timer3 trig, plck1 pulse */ + PIS_TIMER3_INPUT_1 = 0x152, /**< Timer3 chan1 input catch, plck1 pulse */ + PIS_TIMER3_OUTPUT_1 = 0x153, /**< Timer3 chan1 output compare, plck1 pulse */ + PIS_TIMER3_INPUT_2 = 0x154, /**< Timer3 chan2 input catch, plck1 pulse */ + PIS_TIMER3_OUTPUT_2 = 0x155, /**< Timer3 chan2 output compare, plck1 pulse */ + PIS_TIMER3_INPUT_3 = 0x156, /**< Timer3 chan3 input catch, plck1 pulse */ + PIS_TIMER3_OUTPUT_3 = 0x157, /**< Timer3 chan3 output compare, plck1 pulse */ + PIS_TIMER3_INPUT_4 = 0x158, /**< Timer3 chan4 input catch, plck1 pulse */ + PIS_TIMER3_OUTPUT_4 = 0x159, /**< Timer3 chan4 output compare, plck1 pulse */ + PIS_RTC_CLOCK = 0x160, /**< Rtc clock, pulse,support async */ + PIS_RTC_ALARM = 0x161, /**< Rtc alarm, pulse,support async */ + PIS_LPTIMER0_SYN_UPDATA = 0x170, /**< Lptimer0 syn updata, pulse,support async */ + PIS_LPTIMER0_ASY_UPDATA = 0x171, /**< Lptimer0 asy updata, pulse,support async */ + PIS_LPUART0_ASY_RECV = 0x180, /**< Lpuart0 asy recv, pulse,support async */ + PIS_LPUART0_ASY_SEND = 0x181, /**< Lpuart0 asy send, pulse,support async */ + PIS_LPUART0_SYN_RECV = 0x182, /**< Lpuart0 syn recv, pulse,support async */ + PIS_LPUART0_SYN_SEND = 0x183, /**< Lpuart0 syn recv, pulse,support async */ + PIS_DMA = 0x190, /**< Dma, pulse,support async */ + PIS_ADC1_INJECT = 0x1a0, /**< Adc1 inject, pclk2 pulse,support async */ + PIS_ADC1_REGULAT = 0x1a1, /**< Adc1 regulat, pclk2 pulse,support async */ + PIS_ADC1_RESERVE = 0x1a2, /**< Adc1 reserve */ +} pis_src_t; + +/** + * @brief Consumer entry + */ +typedef enum { + PIS_CH12_TIMER0_ITR0 = 0x003C, /** Tim0 internal input chan0 */ + PIS_CH13_TIMER0_ITR1 = 0x003D, /** Tim0 internal input chan1 */ + PIS_CH14_TIMER0_ITR2 = 0x003E, /** Tim0 internal input chan2 */ + PIS_CH15_TIMER0_ITR3 = 0x003F, /** Tim0 internal input chan3 */ + PIS_CH12_TIMER1_ITR0 = 0x003C, /** Tim1 internal input chan0 */ + PIS_CH13_TIMER1_ITR1 = 0x003D, /** Tim1 internal input chan1 */ + PIS_CH14_TIMER1_ITR2 = 0x003E, /** Tim1 internal input chan2 */ + PIS_CH15_TIMER1_ITR3 = 0x003F, /** Tim1 internal input chan3 */ + PIS_CH12_TIMER2_ITR0 = 0x003C, /** Tim2 internal input chan0 */ + PIS_CH13_TIMER2_ITR1 = 0x003D, /** Tim2 internal input chan1 */ + PIS_CH14_TIMER2_ITR2 = 0x003E, /** Tim2 internal input chan2 */ + PIS_CH15_TIMER2_ITR3 = 0x003F, /** Tim2 internal input chan3 */ + PIS_CH12_TIMER3_ITR0 = 0x003C, /** Tim3 internal input chan0 */ + PIS_CH13_TIMER3_ITR1 = 0x003D, /** Tim3 internal input chan1 */ + PIS_CH14_TIMER3_ITR2 = 0x003E, /** Tim3 internal input chan2 */ + PIS_CH15_TIMER3_ITR3 = 0x003F, /** Tim3 internal input chan3 */ + PIS_CH6_ADC0_REGULAT = 0x0036, /** ADC0 regulat transform */ + PIS_CH7_ADC0_INJECT = 0x0037, /** ADC0 inject transform */ + PIS_CH0_LPTIM0_EXT0 = 0x0030, /** Lptim0 external trigger 0 */ + PIS_CH1_LPTIM0_EXT1 = 0x0031, /** Lptim0 external trigger 1 */ + PIS_CH2_LPTIM0_EXT2 = 0x0032, /** Lptim0 external trigger 2 */ + PIS_CH3_LPTIM0_EXT3 = 0x0033, /** Lptim0 external trigger 3 */ + PIS_CH4_LPTIM0_EXT4 = 0x0034, /** Lptim0 external trigger 4 */ + PIS_CH5_LPTIM0_EXT5 = 0x0035, /** Lptim0 external trigger 5 */ + PIS_CH6_LPTIM0_EXT6 = 0x0036, /** Lptim0 external trigger 6 */ + PIS_CH7_LPTIM0_EXT7 = 0x0037, /** Lptim0 external trigger 7 */ + PIS_CH7_DMA_REQUEST = 0x0037, /** DMA request 7 */ + PIS_CH15_LPUART0_RXD = 0x081F, /**< Lpuart Rx data */ + PIS_CH14_UART5_RXD = 0x071E, /**< Uart5 Rx data */ + PIS_CH13_UART4_RXD = 0x061D, /**< Uart4 Rx data */ + PIS_CH12_UART3_RXD = 0x031C, /**< Uart3 Rx data */ + PIS_CH11_UART2_RXD = 0x021B, /**< Uart2 Rx data */ + PIS_CH10_UART1_RXD = 0x011A, /**< Uart1 Rx data */ + PIS_CH9_UART0_RXD = 0x0019, /**< Uart0 Rx data */ + PIS_CH8_TIMER3_CH4IN = 0x1B08, /**< Tim3 input chan4 */ + PIS_CH8_TIMER2_CH4IN = 0x1308, /**< Tim2 input chan4 */ + PIS_CH8_SPI1_CLK = 0x0F18, /**< Spi1 clk */ + PIS_CH7_TIMER3_CH3IN = 0x1A07, /**< Tim3 input chan3 */ + PIS_CH7_TIMER2_CH3IN = 0x1207, /**< Tim2 input chan3 */ + PIS_CH7_SPI1_RX = 0x0E17, /**< Spi1 rx */ + PIS_CH6_TIMER3_CH2IN = 0x1906, /**< Tim3 input chan2 */ + PIS_CH6_TIMER2_CH2IN = 0x1106, /**< Tim2 input chan2 */ + PIS_CH6_SPI0_CLK = 0x0D16, /**< SPI0 CLK */ + PIS_CH5_TIMER3_CH1IN = 0x1805, /**< Tim3 input chan1 */ + PIS_CH5_TIMER2_CH1IN = 0x1005, /**< Tim2 input chan1 */ + PIS_CH5_SPI0_RX = 0x0C15, /**< SPI0 RX */ + PIS_CH4_TIMER1_CH4IN = 0x0B04, /**< Tim1 input chan4 */ + PIS_CH4_TIMER0_CH4IN = 0x0304, /**< Tim0 input chan4 */ + PIS_CH3_TIMER1_CH3IN = 0x0A03, /**< Tim1 input chan3 */ + PIS_CH3_TIMER0_CH3IN = 0x0203, /**< Tim0 input chan3 */ + PIS_CH2_TIMER1_CH2IN = 0x0902, /**< Tim1 input chan2 */ + PIS_CH2_TIMER0_CH2IN = 0x0102, /**< Tim0 input chan2 */ + PIS_CH1_TIMER1_CH1IN = 0x0801, /**< Tim1 input chan1 */ + PIS_CH0_TIMER0_CH1IN = 0x0000, /**< Tim0 input chan1 */ + PIS_CH0_TIMER0_BRKIN = 0x0400, /**< Tim0 break in */ + PIS_CH0_TIMER1_BRKIN = 0x0C00, /**< Tim1 break in */ + PIS_TRIG_RESERVE = 0xFFFF, /**< Other Consumer */ +} pis_trig_t; + +/** + * @brief Clock select + */ +typedef enum { + PIS_CLK_PCLK1 = 0, /**< APB1 peripherals clock */ + PIS_CLK_PCLK2 = 1, /**< APB2 peripherals clock */ + PIS_CLK_SYS = 2, /**< AHB peripherals clock */ + PIS_CLK_RESERVE = 3, /**< reserve clock */ +} pis_clock_t; + +/** + * @brief Level select + */ +typedef enum { + PIS_EDGE_NONE = 0, /**< None edge */ + PIS_EDGE_UP = 1, /**< Up edge */ + PIS_EDGE_DOWN = 2, /**< Down edge */ + PIS_EDGE_UP_DOWN = 3, /**< Up and down edge */ +} pis_edge_t; + +/** + * @brief Output style + */ +typedef enum { + PIS_OUT_LEVEL = 0, /**< Level */ + PIS_OUT_PULSE = 1, /**< Pulse */ +} pis_output_t; +/** + * @brief Sync select + */ +typedef enum { + PIS_SYN_DIRECT = 0, /**< Direct */ + PIS_SYN_LEVEL_ASY_APB1 = 1, /**< Producer level signal and Consumer in APB1 */ + PIS_SYN_LEVEL_ASY_APB2 = 2, /**< Producer level signal and Consumer in APB2 */ + PIS_SYN_LEVEL_ASY_AHB = 3, /**< Producer level signal and Consumer in AHB */ + PIS_SYN_PULSE_ASY_APB1 = 4, /**< Producer Pulse signal and Consumer in APB1 */ + PIS_SYN_PULSE_ASY_APB2 = 5, /**< Producer Pulse signal and Consumer in APB2 */ + PIS_SYN_PULSE_ASY_AHB = 6, /**< Producer Pulse signal and Consumer in AHB */ +} pis_syncsel_t; + +/** + * @brief Pis channel + */ +typedef enum { + PIS_CH_0 = 0, /**< Channel 0 */ + PIS_CH_1 = 1, /**< Channel 1 */ + PIS_CH_2 = 2, /**< Channel 2 */ + PIS_CH_3 = 3, /**< Channel 3 */ + PIS_CH_4 = 4, /**< Channel 4 */ + PIS_CH_5 = 5, /**< Channel 5 */ + PIS_CH_6 = 6, /**< Channel 6 */ + PIS_CH_7 = 7, /**< Channel 7 */ + PIS_CH_8 = 8, /**< Channel 8 */ + PIS_CH_9 = 9, /**< Channel 9 */ + PIS_CH_10 = 10, /**< Channel 10 */ + PIS_CH_11 = 11, /**< Channel 11 */ + PIS_CH_12 = 12, /**< Channel 12 */ + PIS_CH_13 = 13, /**< Channel 13 */ + PIS_CH_14 = 14, /**< Channel 14 */ + PIS_CH_15 = 15, /**< Channel 15 */ +} pis_ch_t; + +/** + * @brief Pis output channel + */ +typedef enum { + PIS_OUT_CH_0 = 0, /**< Channel 0 */ + PIS_OUT_CH_1 = 1, /**< Channel 1 */ + PIS_OUT_CH_2 = 2, /**< Channel 2 */ + PIS_OUT_CH_3 = 3, /**< Channel 3 */ +} pis_out_ch_t; + +/** + * @brief Indirect value,no care of it. + */ +typedef enum { + PIS_CON_0 = 0, /**< Con 0 */ + PIS_CON_1 = 1, /**< Con 1 */ + PIS_CON_NONE = 2, /**< None */ +} pis_con_t; + +/** + * @brief Indirect value,no care of it. + */ +typedef union { + struct { + uint8_t ch :4; /**< Channel */ + uint8_t con :4; /**< Contorl */ + uint8_t shift :8; /**< Shift */ + }; + uint16_t HalfWord; +} pis_divide_t; + +/** + * @brief PIS state structures definition + */ +typedef enum { + PIS_STATE_RESET = 0x00, /**< Peripheral is not initialized */ + PIS_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + PIS_STATE_BUSY = 0x02, /**< An internal process is ongoing */ + PIS_STATE_TIMEOUT = 0x03, /**< Timeout state */ + PIS_STATE_ERROR = 0x04, /**< Error */ +} pis_state_t; + +/** + * @brief PIS modulate target + */ +typedef enum { + PIS_UART0_TX = 0, /**< Modulate uart0 tx */ + PIS_UART1_TX = 1, /**< Modulate uart1 tx */ + PIS_UART2_TX = 2, /**< Modulate uart2 tx */ + PIS_UART3_TX = 3, /**< Modulate uart3 tx */ + PIS_LPUART0_TX = 4, /**< Modulate lpuart0 tx */ +} pis_modu_targ_t; + +/** + * @brief PIS modulate level + */ +typedef enum { + PIS_LOW_LEVEL = 0, /**< Modulate low level */ + PIS_HIGH_LEVEL = 1, /**< Modulate high level */ +} pis_modu_level_t; + +/** + * @brief PIS modulate source + */ +typedef enum { + PIS_SRC_NONE = 0, /**< Stop modulate */ + PIS_SRC_TIMER0 = 1, /**< Modulate source is TIMER0 */ + PIS_SRC_TIMER1 = 2, /**< Modulate source is TIMER1 */ + PIS_SRC_TIMER2 = 3, /**< Modulate source is TIMER2 */ + PIS_SRC_TIMER3 = 4, /**< Modulate source is TIMER3 */ + PIS_SRC_TIMER6 = 5, /**< Modulate source is TIMER6 */ + PIS_SRC_TIMER7 = 6, /**< Modulate source is TIMER7 */ + PIS_SRC_LPTIM0 = 7, /**< Modulate source is LPTIM0 */ + PIS_SRC_BUZ = 8, /**< Modulate source is buz */ +} pis_modu_src_t; + +/** + * @brief PIS modulate channel + */ +typedef enum { + PIS_TIMER_CH1 = 0, /**< Src is TIMERx and choose channel 1 */ + PIS_TIMER_CH2 = 1, /**< Src is TIMERx and choose channel 2 */ + PIS_TIMER_CH3 = 2, /**< Src is TIMERx and choose channel 3 */ + PIS_TIMER_CH4 = 3, /**< Src is TIMERx and choose channel 4 */ +} pis_modu_channel_t; + +/** + * @brief PIS input channel chose + */ +typedef enum { + PIS_NONE_INPUT = 0, /**< Consumer input none */ + PIS_PORT_INPUT = 1, /**< Consumer input choose external port */ + PIS_CHAN_INPUT = 2 /**< Consumer input choose pis channel */ +} pis_input_sel_t; + +/** + * @brief PIS init structure definition + */ +typedef struct { + pis_src_t producer_src; /**< Producer entry */ + pis_output_t producer_signal; /**< Producer signal mode */ + pis_clock_t producer_clk; /**< Producer module clock */ + pis_edge_t producer_edge; /**< Producer module pin output edge */ + pis_trig_t consumer_trig; /**< Consumer entry */ + pis_clock_t consumer_clk; /**< Consumer clock */ + pis_input_sel_t input_chan; /**< Consumer input channel */ +} pis_init_t; + +/** + * @brief PIS modulate config structure definition + */ +typedef struct { + pis_modu_targ_t target; /**< Modulate target */ + pis_modu_level_t level; /**< Modulate level */ + pis_modu_src_t src; /**< Modulate src */ + pis_modu_channel_t channel; /**< Modulate channel */ +} pis_modulate_config_t; + +/** + * @brief PIS Handle Structure definition + */ +typedef struct pis_handle_s { + PIS_TypeDef *perh; /**< Register base address */ + pis_init_t init; /**< PIS required parameters */ + pis_ch_t consumer_ch; /**< Indirect value, no care of it */ + pis_con_t consumer_con; /**< Indirect value, no care of it */ + uint8_t consumer_pos; /**< Indirect value, no care of it */ + uint32_t check_info; /**< When destroy a handle ,user need check whether is right that ready to destroy */ + lock_state_t lock; /**< Locking object */ + pis_state_t state; /**< PIS operation state */ +} pis_handle_t; +/** + * @} + */ + + +/** @defgroup PIS_Private_Macros PIS Private Macros + * @{ + */ +#define IS_PIS(x) (((x) == PIS)) +#define IS_PIS_SRC(x) (((x) == PIS_NON) || \ + ((x) == PIS_GPIO_PIN0) || \ + ((x) == PIS_GPIO_PIN1) || \ + ((x) == PIS_GPIO_PIN2) || \ + ((x) == PIS_GPIO_PIN3) || \ + ((x) == PIS_GPIO_PIN4) || \ + ((x) == PIS_GPIO_PIN5) || \ + ((x) == PIS_GPIO_PIN6) || \ + ((x) == PIS_GPIO_PIN7) || \ + ((x) == PIS_GPIO_PIN8) || \ + ((x) == PIS_GPIO_PIN9) || \ + ((x) == PIS_GPIO_PIN10) || \ + ((x) == PIS_GPIO_PIN11) || \ + ((x) == PIS_GPIO_PIN12) || \ + ((x) == PIS_GPIO_PIN13) || \ + ((x) == PIS_GPIO_PIN14) || \ + ((x) == PIS_GPIO_PIN15) || \ + ((x) == PIS_ACMP_OUT0) || \ + ((x) == PIS_ACMP_OUT1) || \ + ((x) == PIS_DAC0_CH0) || \ + ((x) == PIS_DAC0_CH1) || \ + ((x) == PIS_ADC0_INJECT) || \ + ((x) == PIS_ADC0_REGULAT) || \ + ((x) == PIS_ADC0_RESERVE) || \ + ((x) == PIS_LVD) || \ + ((x) == PIS_UART0_RESERVE0) || \ + ((x) == PIS_UART0_RESERVE1) || \ + ((x) == PIS_UART0_IRDAOUT) || \ + ((x) == PIS_UART0_RTSOUT) || \ + ((x) == PIS_UART0_TXOUT) || \ + ((x) == PIS_UART0_SYN_SEND) || \ + ((x) == PIS_UART0_SYN_RECV) || \ + ((x) == PIS_UART1_RESERVE0) || \ + ((x) == PIS_UART1_RESERVE1) || \ + ((x) == PIS_UART1_IRDA) || \ + ((x) == PIS_UART1_RTS) || \ + ((x) == PIS_UART1_TXOUT) || \ + ((x) == PIS_UART1_SYN_SEND) || \ + ((x) == PIS_UART1_SYN_RECV) || \ + ((x) == PIS_UART2_RESERVE0) || \ + ((x) == PIS_UART2_RESERVE1) || \ + ((x) == PIS_UART2_IRDA) || \ + ((x) == PIS_UART2_RTS) || \ + ((x) == PIS_UART2_TXOUT) || \ + ((x) == PIS_UART2_SYN_SEND) || \ + ((x) == PIS_UART2_SYN_RECV) || \ + ((x) == PIS_UART3_RESERVE0) || \ + ((x) == PIS_UART3_RESERVE1) || \ + ((x) == PIS_UART3_IRDA) || \ + ((x) == PIS_UART3_RTS) || \ + ((x) == PIS_UART3_TXOUT) || \ + ((x) == PIS_UART3_SYN_SEND) || \ + ((x) == PIS_UART3_SYN_RECV) || \ + ((x) == PIS_UART4_RECV) || \ + ((x) == PIS_UART4_SEND) || \ + ((x) == PIS_UART4_TXOUT) || \ + ((x) == PIS_UART5_RECV) || \ + ((x) == PIS_UART5_SEND) || \ + ((x) == PIS_UART5_TXOUT) || \ + ((x) == PIS_SPI0_RECV) || \ + ((x) == PIS_SPI0_SEND) || \ + ((x) == PIS_SPI0_NE) || \ + ((x) == PIS_SPI1_RECV) || \ + ((x) == PIS_SPI1_SEND) || \ + ((x) == PIS_SPI1_NE) || \ + ((x) == PIS_I2C0_RECV) || \ + ((x) == PIS_I2C0_SEND) || \ + ((x) == PIS_I2C1_RECV) || \ + ((x) == PIS_I2C1_SEND) || \ + ((x) == PIS_TIMER0_UPDATA) || \ + ((x) == PIS_TIMER0_TRIG) || \ + ((x) == PIS_TIMER0_INPUT_1) || \ + ((x) == PIS_TIMER0_OUTPUT_1) || \ + ((x) == PIS_TIMER0_INPUT_2) || \ + ((x) == PIS_TIMER0_OUTPUT_2) || \ + ((x) == PIS_TIMER0_INPUT_3) || \ + ((x) == PIS_TIMER0_OUTPUT_3) || \ + ((x) == PIS_TIMER0_INPUT_4) || \ + ((x) == PIS_TIMER0_OUTPUT_4) || \ + ((x) == PIS_TIMER1_UPDATA) || \ + ((x) == PIS_TIMER1_TRIG) || \ + ((x) == PIS_TIMER1_INPUT_1) || \ + ((x) == PIS_TIMER1_OUTPUT_1) || \ + ((x) == PIS_TIMER1_INPUT_2) || \ + ((x) == PIS_TIMER1_OUTPUT_2) || \ + ((x) == PIS_TIMER1_INPUT_3) || \ + ((x) == PIS_TIMER1_OUTPUT_3) || \ + ((x) == PIS_TIMER1_INPUT_4) || \ + ((x) == PIS_TIMER1_OUTPUT_4) || \ + ((x) == PIS_TIMER2_UPDATA) || \ + ((x) == PIS_TIMER2_TRIG) || \ + ((x) == PIS_TIMER2_INPUT_1) || \ + ((x) == PIS_TIMER2_OUTPUT_1) || \ + ((x) == PIS_TIMER2_INPUT_2) || \ + ((x) == PIS_TIMER2_OUTPUT_2) || \ + ((x) == PIS_TIMER2_INPUT_3) || \ + ((x) == PIS_TIMER2_OUTPUT_3)) +#define IS_PIS_TRIG(x) (((x) == PIS_CH12_TIMER0_ITR0) || \ + ((x) == PIS_CH13_TIMER0_ITR1) || \ + ((x) == PIS_CH14_TIMER0_ITR2) || \ + ((x) == PIS_CH15_TIMER0_ITR3) || \ + ((x) == PIS_CH12_TIMER1_ITR0) || \ + ((x) == PIS_CH13_TIMER1_ITR1) || \ + ((x) == PIS_CH14_TIMER1_ITR2) || \ + ((x) == PIS_CH15_TIMER1_ITR3) || \ + ((x) == PIS_CH12_TIMER2_ITR0) || \ + ((x) == PIS_CH13_TIMER2_ITR1) || \ + ((x) == PIS_CH14_TIMER2_ITR2) || \ + ((x) == PIS_CH15_TIMER2_ITR3) || \ + ((x) == PIS_CH12_TIMER3_ITR0) || \ + ((x) == PIS_CH13_TIMER3_ITR1) || \ + ((x) == PIS_CH14_TIMER3_ITR2) || \ + ((x) == PIS_CH15_TIMER3_ITR3) || \ + ((x) == PIS_CH6_ADC0_REGULAT) || \ + ((x) == PIS_CH7_ADC0_INJECT) || \ + ((x) == PIS_CH0_LPTIM0_EXT0) || \ + ((x) == PIS_CH1_LPTIM0_EXT1) || \ + ((x) == PIS_CH2_LPTIM0_EXT2) || \ + ((x) == PIS_CH3_LPTIM0_EXT3) || \ + ((x) == PIS_CH4_LPTIM0_EXT4) || \ + ((x) == PIS_CH5_LPTIM0_EXT5) || \ + ((x) == PIS_CH6_LPTIM0_EXT6) || \ + ((x) == PIS_CH7_LPTIM0_EXT7) || \ + ((x) == PIS_CH7_DMA_REQUEST) || \ + ((x) == PIS_CH15_LPUART0_RXD) || \ + ((x) == PIS_CH14_UART5_RXD) || \ + ((x) == PIS_CH13_UART4_RXD) || \ + ((x) == PIS_CH12_UART3_RXD) || \ + ((x) == PIS_CH11_UART2_RXD) || \ + ((x) == PIS_CH10_UART1_RXD) || \ + ((x) == PIS_CH9_UART0_RXD) || \ + ((x) == PIS_CH8_TIMER3_CH4IN) || \ + ((x) == PIS_CH8_TIMER2_CH4IN) || \ + ((x) == PIS_CH8_SPI1_CLK) || \ + ((x) == PIS_CH7_TIMER3_CH3IN) || \ + ((x) == PIS_CH7_TIMER2_CH3IN) || \ + ((x) == PIS_CH7_SPI1_RX) || \ + ((x) == PIS_CH6_TIMER3_CH2IN) || \ + ((x) == PIS_CH6_TIMER2_CH2IN) || \ + ((x) == PIS_CH6_SPI0_CLK) || \ + ((x) == PIS_CH5_TIMER3_CH1IN) || \ + ((x) == PIS_CH5_TIMER2_CH1IN) || \ + ((x) == PIS_CH5_SPI0_RX) || \ + ((x) == PIS_CH4_TIMER1_CH4IN) || \ + ((x) == PIS_CH4_TIMER0_CH4IN) || \ + ((x) == PIS_CH3_TIMER1_CH3IN) || \ + ((x) == PIS_CH3_TIMER0_CH3IN) || \ + ((x) == PIS_CH2_TIMER1_CH2IN) || \ + ((x) == PIS_CH2_TIMER0_CH2IN) || \ + ((x) == PIS_CH1_TIMER1_CH1IN) || \ + ((x) == PIS_CH0_TIMER0_CH1IN) || \ + ((x) == PIS_CH0_TIMER0_BRKIN) || \ + ((x) == PIS_CH0_TIMER1_BRKIN) || \ + ((x) == PIS_TRIG_RESERVE) || \ + ((x) == PIS_CH8_SPI1_CLK)) +#define IS_PIS_CLOCK(x) (((x) == PIS_CLK_PCLK1) || \ + ((x) == PIS_CLK_PCLK2) || \ + ((x) == PIS_CLK_SYS)) +#define IS_PIS_SIGNAL_MODE(x) (((x) == PIS_OUT_LEVEL) || \ + ((x) == PIS_OUT_PULSE)) +#define IS_PIS_EDGE(x) (((x) == PIS_EDGE_NONE) || \ + ((x) == PIS_EDGE_UP) || \ + ((x) == PIS_EDGE_DOWN) || \ + ((x) == PIS_EDGE_UP_DOWN)) +#define IS_PIS_OUTPUT(x) (((x) == PIS_OUT_LEVEL) || \ + ((x) == PIS_OUT_PULSE)) +#define IS_PIS_OUPUT_CH(x) (((x) == PIS_OUT_CH_0) || \ + ((x) == PIS_OUT_CH_1) || \ + ((x) == PIS_OUT_CH_2) || \ + ((x) == PIS_OUT_CH_3)) +#define IS_PIS_MODU_TARGET(x) (((x) == PIS_UART0_TX) || \ + ((x) == PIS_UART1_TX) || \ + ((x) == PIS_UART2_TX) || \ + ((x) == PIS_UART3_TX) || \ + ((x) == PIS_LPUART0_TX)) +#define IS_PIS_MODU_LEVEL(x) (((x) == PIS_LOW_LEVEL) || \ + ((x) == PIS_HIGH_LEVEL)) +#define IS_PIS_MODU_SRC(x) (((x) == PIS_SRC_NONE) || \ + ((x) == PIS_SRC_TIMER0) || \ + ((x) == PIS_SRC_TIMER1) || \ + ((x) == PIS_SRC_TIMER2) || \ + ((x) == PIS_SRC_TIMER3) || \ + ((x) == PIS_SRC_TIMER6) || \ + ((x) == PIS_SRC_TIMER7) || \ + ((x) == PIS_SRC_LPTIM0) || \ + ((x) == PIS_SRC_BUZ)) +#define IS_PIS_MODU_CHANNEL(x) (((x) == PIS_TIMER_CH1) || \ + ((x) == PIS_TIMER_CH2) || \ + ((x) == PIS_TIMER_CH3) || \ + ((x) == PIS_TIMER_CH4)) +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions + * @{ + */ + +/** @addtogroup PIS_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_pis_create(pis_handle_t *hperh); +ald_status_t ald_pis_destroy(pis_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch); +ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group3 + * @{ + */ +pis_state_t ald_pis_get_state(pis_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group4 + * @{ + */ +ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_PIS_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h similarity index 35% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h rename to bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h index c7e3327e59d01baf9da61025daab5627c2ce01b5..79f644b55953611cef62e1b9294d6deaddb63ffb 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_pmu.h @@ -5,7 +5,7 @@ * @brief Header file of PMU module driver. * * @version V1.0 - * @date 04 Dec 2017 + * @date 04 Dec 2019 * @author AE Team * @note * @@ -23,6 +23,7 @@ extern "C" { #include "utils.h" #include "ald_syscfg.h" +#include "ald_bkpc.h" /** @addtogroup ES32FXXX_ALD @@ -36,44 +37,44 @@ extern "C" { /** @defgroup PMU_Public_Macros PMU Public Macros * @{ */ -#define PMU_SRAM0_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS)); \ - SYSCFG_LOCK(); \ +#define PMU_LPSTOP_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define PMU_SRAM0_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\ - SYSCFG_LOCK(); \ +#define PMU_LPSTOP_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define PMU_SRAM1_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE)); \ - SYSCFG_LOCK(); \ +#define PMU_MTSTOP_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define PMU_SRAM1_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\ - SYSCFG_LOCK(); \ +#define PMU_MTSTOP_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define PMU_BXCAN_ENABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ - SYSCFG_LOCK(); \ +#define PMU_VREF_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->VREFCR, PMU_VREFCR_VREFEN_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define PMU_BXCAN_DISABLE() \ -do { \ - SYSCFG_UNLOCK(); \ - CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \ - SYSCFG_LOCK(); \ +#define PMU_VREF_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->VREFCR, PMU_VREFCR_VREFEN_MSK); \ + SYSCFG_LOCK(); \ } while (0) -#define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS)) +#define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS)) /** * @} */ @@ -82,69 +83,77 @@ do { \ /** @defgroup PMU_Public_Types PMU Public Types * @{ */ -/** - * @brief Standby wakeup port select - */ -typedef enum -{ - PMU_STANDBY_PORT_SEL_PA0 = 0x0, /**< PA0 */ - PMU_STANDBY_PORT_SEL_PA1 = 0x1, /**< PA1 */ - PMU_STANDBY_PORT_SEL_PA2 = 0x2, /**< PA2 */ - PMU_STANDBY_PORT_SEL_PA3 = 0x3, /**< PA3 */ - PMU_STANDBY_PORT_SEL_PA4 = 0x4, /**< PA4 */ - PMU_STANDBY_PORT_SEL_PA5 = 0x5, /**< PA5 */ - PMU_STANDBY_PORT_SEL_PA6 = 0x6, /**< PA6 */ - PMU_STANDBY_PORT_SEL_PA7 = 0x7, /**< PA7 */ - PMU_STANDBY_PORT_NONE = 0xF, /**< NONE */ -} pmu_standby_wakeup_sel_t; - /** * @brief Low power mode */ -typedef enum -{ - PMU_LP_STOP1 = 0x0, /**< Stop1 */ - PMU_LP_STOP2 = 0x1, /**< Stop2 */ - PMU_LP_STANDBY = 0x2, /**< Standby */ +typedef enum { + PMU_LP_STOP1 = 0x0, /**< Stop1 */ + PMU_LP_STOP2 = 0x1, /**< Stop2 */ + PMU_LP_STANDBY = 0x2, /**< Standby */ } pmu_lp_mode_t; -typedef enum -{ - PMU_SR_WUF = (1U << 0), - PMU_SR_STANDBYF = (1U << 1), +typedef enum { + PMU_SR_WUF = (1U << 0), /**< WakeUp status */ + PMU_SR_STANDBYF = (1U << 1), /**< Standby status */ + PMU_SR_USBRDY = (1U << 2), /**< USB Readby status */ + PMU_SR_RSTAT = (1U << 3), /**< RUN/LPRUAN status */ } pmu_status_t; /** * @brief LVD voltage select */ -typedef enum -{ - PMU_LVD_VOL_SEL_2_0 = 0x0, /**< 2.0V ~ 2.05V */ - PMU_LVD_VOL_SEL_2_1 = 0x1, /**< 2.1V ~ 2.15V */ - PMU_LVD_VOL_SEL_2_2 = 0x2, /**< 2.2V ~ 2.25V */ - PMU_LVD_VOL_SEL_2_4 = 0x3, /**< 2.4V ~ 2.45V */ - PMU_LVD_VOL_SEL_2_6 = 0x4, /**< 2.6V ~ 2.65V */ - PMU_LVD_VOL_SEL_2_8 = 0x5, /**< 2.8V ~ 2.85V */ - PMU_LVD_VOL_SEL_3_0 = 0x6, /**< 3.0V ~ 3.05V */ - PMU_LVD_VOL_SEL_3_6 = 0x7, /**< 3.6V ~ 3.65V */ - PMU_LVD_VOL_SEL_4_0 = 0x8, /**< 4.0V ~ 4.05V */ - PMU_LVD_VOL_SEL_4_6 = 0x9, /**< 4.6V ~ 4.65V */ - PMU_LVD_VOL_SEL_2_3 = 0xA, /**< 2.3V ~ 2.35V */ - PMU_LVD_VOL_SEL_EXT = 0xF, /**< Select external input. It must be 1.2V */ +typedef enum { + PMU_LVD_VOL_SEL_2_2 = 0x0, /**< 2.2V ~ 2.25V */ + PMU_LVD_VOL_SEL_2_4 = 0x1, /**< 2.4V ~ 2.45V */ + PMU_LVD_VOL_SEL_2_6 = 0x2, /**< 2.6V ~ 2.65V */ + PMU_LVD_VOL_SEL_2_8 = 0x3, /**< 2.8V ~ 2.85V */ + PMU_LVD_VOL_SEL_3_0 = 0x4, /**< 3.0V ~ 3.05V */ + PMU_LVD_VOL_SEL_3_2 = 0x5, /**< 3.2V ~ 3.25V */ + PMU_LVD_VOL_SEL_3_4 = 0x6, /**< 3.4V ~ 3.45V */ + PMU_LVD_VOL_SEL_3_6 = 0x7, /**< 3.6V ~ 3.65V */ + PMU_LVD_VOL_SEL_3_8 = 0x8, /**< 3.8V ~ 3.85V */ + PMU_LVD_VOL_SEL_4_0 = 0x9, /**< 4.0V ~ 4.05V */ + PMU_LVD_VOL_SEL_4_2 = 0x9, /**< 4.2V ~ 4.25V */ + PMU_LVD_VOL_SEL_4_4 = 0x9, /**< 4.4V ~ 4.45V */ + PMU_LVD_VOL_SEL_4_6 = 0x9, /**< 4.6V ~ 4.65V */ + PMU_LVD_VOL_SEL_4_8 = 0x9, /**< 4.8V ~ 4.85V */ + PMU_LVD_VOL_SEL_EXT = 0xF, /**< Select external input. It must be 1.2V */ } pmu_lvd_voltage_sel_t; /** * @brief LVD trigger mode */ -typedef enum -{ - PMU_LVD_TRIGGER_RISING_EDGE = 0x0, /**< Rising edge */ - PMU_LVD_TRIGGER_FALLING_EDGE = 0x1, /**< Falling edge */ - PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2, /**< High level */ - PMU_LVD_TRIGGER_LOW_LEVEL = 0x3, /**< Low level */ - PMU_LVD_TRIGGER_RISING_FALLING = 0x4, /**< Rising and falling edge */ +typedef enum { + PMU_LVD_TRIGGER_RISING_EDGE = 0x0, /**< Rising edge */ + PMU_LVD_TRIGGER_FALLING_EDGE = 0x1, /**< Falling edge */ + PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2, /**< High level */ + PMU_LVD_TRIGGER_LOW_LEVEL = 0x3, /**< Low level */ + PMU_LVD_TRIGGER_RISING_FALLING = 0x4, /**< Rising and falling edge */ } pmu_lvd_trigger_mode_t; +/** + * @brief LDO output voltage selest in low power mode + */ +typedef enum { + PMU_LDO_LPMODE_OUTPUT_0_9 = 0x0, /**< 0.9V */ + PMU_LDO_LPMODE_OUTPUT_1_0 = 0x1, /**< 1.0V */ + PMU_LDO_LPMODE_OUTPUT_1_1 = 0x2, /**< 1.1V */ + PMU_LDO_LPMODE_OUTPUT_1_2 = 0x3, /**< 1.2V */ +} pmu_ldo_lpmode_output_t; + +typedef enum { + PMU_POWER_SRAM0 = 0x1, /**< SRAM0 */ + PMU_POWER_SRAM1 = 0x2, /**< SRAM1 */ + PMU_POWER_SRAM2 = 0x4, /**< SRAM2 */ + PMU_POWER_SRAM3 = 0x8, /**< SRAM3 */ + PMU_POWER_SRAM4 = 0x10, /**< SRAM4 */ + PMU_POWER_SRAM5 = 0x20, /**< SRAM5 */ + PMU_POWER_CAN = 0x100, /**< CAN */ + PMU_POWER_QSPI = 0x400, /**< QSPI */ + PMU_POWER_USB = 0x800, /**< USB */ + PMU_POWER_ROM = 0x1000, /**< ROM */ +} pmu_perh_power_t; + /** * @} */ @@ -153,37 +162,48 @@ typedef enum * @defgroup PMU_Private_Macros PMU Private Macros * @{ */ -#define IS_PMU_STANDBY_PORT_SEL(x) (((x) == PMU_STANDBY_PORT_SEL_PA0) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA1) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA2) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA3) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA4) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA5) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA6) || \ - ((x) == PMU_STANDBY_PORT_SEL_PA7) || \ - ((x) == PMU_STANDBY_PORT_NONE)) -#define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \ +#define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \ ((x) == PMU_LP_STOP2) || \ ((x) == PMU_LP_STANDBY)) -#define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || \ - ((x) == PMU_SR_STANDBYF)) -#define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_0) || \ - ((x) == PMU_LVD_VOL_SEL_2_1) || \ - ((x) == PMU_LVD_VOL_SEL_2_2) || \ +#define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || \ + ((x) == PMU_SR_STANDBYF) || \ + ((x) == PMU_SR_USBRDY) || \ + ((x) == PMU_SR_RSTAT)) +#define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_2) || \ ((x) == PMU_LVD_VOL_SEL_2_4) || \ ((x) == PMU_LVD_VOL_SEL_2_6) || \ ((x) == PMU_LVD_VOL_SEL_2_8) || \ ((x) == PMU_LVD_VOL_SEL_3_0) || \ + ((x) == PMU_LVD_VOL_SEL_3_2) || \ + ((x) == PMU_LVD_VOL_SEL_3_4) || \ ((x) == PMU_LVD_VOL_SEL_3_6) || \ + ((x) == PMU_LVD_VOL_SEL_3_8) || \ ((x) == PMU_LVD_VOL_SEL_4_0) || \ + ((x) == PMU_LVD_VOL_SEL_4_2) || \ + ((x) == PMU_LVD_VOL_SEL_4_4) || \ ((x) == PMU_LVD_VOL_SEL_4_6) || \ - ((x) == PMU_LVD_VOL_SEL_2_3) || \ + ((x) == PMU_LVD_VOL_SEL_4_8) || \ ((x) == PMU_LVD_VOL_SEL_EXT)) -#define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \ +#define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \ ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \ ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \ ((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \ ((x) == PMU_LVD_TRIGGER_RISING_FALLING)) +#define IS_PMU_LDO_LPMODE_OUTPUT(x) (((x) == PMU_LDO_LPMODE_OUTPUT_0_9) || \ + ((x) == PMU_LDO_LPMODE_OUTPUT_1_0) || \ + ((x) == PMU_LDO_LPMODE_OUTPUT_1_1) || \ + ((x) == PMU_LDO_LPMODE_OUTPUT_1_2)) +#define IS_PMU_PERH_POWER(x) (((x) == PMU_POWER_SRAM0) || \ + ((x) == PMU_POWER_SRAM1) || \ + ((x) == PMU_POWER_SRAM2) || \ + ((x) == PMU_POWER_SRAM3) || \ + ((x) == PMU_POWER_SRAM4) || \ + ((x) == PMU_POWER_SRAM5) || \ + ((x) == PMU_POWER_CAN) || \ + ((x) == PMU_POWER_QSPI) || \ + ((x) == PMU_POWER_USB) || \ + ((x) == PMU_POWER_ROM)) + /** * @} */ @@ -195,22 +215,24 @@ typedef enum * @{ */ /* Low power mode select */ -__STATIC_INLINE__ void __sleep() +__STATIC_INLINE__ void ald_pmu_sleep() { - __WFI(); + __WFI(); } -__STATIC_INLINE__ void __sleep_deep() +__STATIC_INLINE__ void ald_pmu_sleep_deep() { - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - __WFI(); + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); } -void pmu_stop1_enter(void); -void pmu_stop2_enter(void); -void pmu_standby_enter(pmu_standby_wakeup_sel_t port); -flag_status_t pmu_get_status(pmu_status_t sr); -void pmu_clear_status(pmu_status_t sr); +void ald_pmu_stop1_enter(void); +void ald_pmu_stop2_enter(void); +void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level); +void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state); +flag_status_t ald_pmu_get_status(pmu_status_t sr); +void ald_pmu_clear_status(pmu_status_t sr); +void ald_pmu_perh_power_config(pmu_perh_power_t perh, type_func_t state); /** * @} */ @@ -218,8 +240,8 @@ void pmu_clear_status(pmu_status_t sr); * @{ */ /* LVD configure */ -void pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state); -void lvd_irq_cbk(void); +void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state); +void ald_lvd_irq_handler(void); /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h new file mode 100644 index 0000000000000000000000000000000000000000..a8a2a500cc2a7101bd3435257e11341071e460c3 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_qspi.h @@ -0,0 +1,542 @@ +/***************************************************************************//** + * @file ald_qspi.h + * @brief Header file of QSPI module driver. + * @version V1.0 + * @date 09 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_QSPI_H_ +#define __ALD_QSPI_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup QSPI + * @{ + */ +/** @defgroup QSPI_Public_Types QSPI Public Types + * @{ + */ +/** + * @brief ALD QSPI state + */ +typedef enum { + QSPI_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ + QSPI_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ +} qspi_state_t; + +/** + * @brief QSPI Instruction Transfer Type + */ +typedef enum { + QSPI_XFER_SINGLE = 0x00, /**< Instruction shifted on DQ0 only*/ + QSPI_XFER_DUAL = 0x01, /**< Instruction,Address and data sent on DQ0 and DQ1*/ + QSPI_XFER_QUAD = 0x02, /**< Instruction,Address and data sent on DQ0,DQ1 and DQ2*/ +} qspi_xfer_t; + +/** + * @brief QSPI Indirect Access SRAM fill level + */ +typedef enum { + QSPI_SRAM_RD = 0, /**< SRAM fill level(indirect write partition)in units of words(4bytes)*/ + QSPI_SRAM_WR = 1, /**< SRAM fill level(indirect read partition)in units of words(4bytes)*/ +} qspi_sram_t; + +/** + * @brief QSPI Clock Phase + */ +typedef enum { + QSPI_CPHA_1E = 0, /**< First edge*/ + QSPI_CPHA_2E = 1, /**< Second edge*/ +} qspi_cpha_t; + +/** + * @brief QSPI_Clock_Polarity QSPI Clock Polarity + */ +typedef enum { + QSPI_CPOL_L = 0, /**< QSPI clock polarity low */ + QSPI_CPOL_H = 1, /**< QSPI clock polarity high */ +} qspi_cpol_t; + +/** + * @brief QSPI peripheral select decode + */ +typedef enum { + QSPI_SINGLE_CHIP = 0x0, /**< Only 1 of 4 selects n_ss_out[3:0] is active */ + QSPI_MULTI_CHIP = 0x1, /**< Allow external 4-to-16 decode */ +} qspi_nss_decode_t; + +/** + * @brief QSPI_Baud_Rate_Clock_Prescaler QSPI Baud Rate Clock Prescaler + */ +typedef enum { + QSPI_DIV_2 = 0x0, /**< Master mode baud rate dibisor 2*/ + QSPI_DIV_4 = 0x1, /**< Master mode baud rate dibisor 4*/ + QSPI_DIV_6 = 0x2, /**< Master mode baud rate dibisor 6*/ + QSPI_DIV_8 = 0x3, /**< Master mode baud rate dibisor 8*/ + QSPI_DIV_10 = 0x4, /**< Master mode baud rate dibisor 10*/ + QSPI_DIV_12 = 0x5, /**< Master mode baud rate dibisor 12*/ + QSPI_DIV_14 = 0x6, /**< Master mode baud rate dibisor 14*/ + QSPI_DIV_16 = 0x7, /**< Master mode baud rate dibisor 16*/ + QSPI_DIV_18 = 0x8, /**< Master mode baud rate dibisor 18*/ + QSPI_DIV_20 = 0x9, /**< Master mode baud rate dibisor 20*/ + QSPI_DIV_22 = 0xA, /**< Master mode baud rate dibisor 22*/ + QSPI_DIV_24 = 0xB, /**< Master mode baud rate dibisor 24*/ + QSPI_DIV_26 = 0xC, /**< Master mode baud rate dibisor 26*/ + QSPI_DIV_28 = 0xD, /**< Master mode baud rate dibisor 28*/ + QSPI_DIV_30 = 0xE, /**< Master mode baud rate dibisor 30*/ + QSPI_DIV_32 = 0xF, /**< Master mode baud rate dibisor 32*/ +} qspi_clk_div_t; + +/** + * @brief QSPI Peripheral chip select decode + */ +typedef enum { + QSPI_CS_NSS0 = 0x0, /**< NSS0 active*/ + QSPI_CS_NSS1 = 0x1, /**< NSS1 active*/ + QSPI_CS_NSS2 = 0x3, /**< NSS2 active*/ + QSPI_CS_NSS3 = 0x7, /**< NSS3 active*/ +} qspi_nss_t; + +/** + *@brief Size of flash connected to CS[x](x = 0 ~ 3)pin + */ +typedef enum { + QSPI_NSS_512M = 0x0, /**< size of 512Mb*/ + QSPI_NSS_1G = 0x1, /**< size of 1Gb*/ + QSPI_NSS_2G = 0x2, /**< size of 2Gb*/ + QSPI_NSS_4G = 0x3, /**< size of 3Gb*/ +} qspi_nss_size_t; + +/** + *@brief Qspi external flash device configuration + */ +typedef struct { + uint8_t addr; /**< Peripheral address */ + uint16_t page; /**< Flash page size */ + uint16_t blk; /**< Flash block size */ + qspi_nss_size_t cs0; /**< NSS0 flash size */ + qspi_nss_size_t cs1; /**< NSS1 flash size */ + qspi_nss_size_t cs2; /**< NSS2 flash size */ + qspi_nss_size_t cs3; /**< NSS3 flash size */ +} qspi_device_size_t; + +/** + * @brief QSPI Sample Edge Selection + */ +typedef enum { + QSPI_FALLING_E = 0x0, /**< Data outputs from flash are sampled on falling edge of the ref_clk*/ + QSPI_RISING_E = 0x1, /**< Data outputs from flash are sampled on rising edge of the ref_clk*/ +} qspi_data_sampled_t; + +/** + * @brief Flash write-protected blocks configuration. + */ +typedef struct { + uint32_t lowblk; /**< the lower block in the range of blocks that is to be locked from writing*/ + uint32_t upblk; /**< upper block in the range of blocks that is to be locked from writing*/ +} qspi_wr_protect_t; + +/** + * @brief QSPI STIG Command Structure. + */ +typedef struct { + uint32_t code; /**< command op-code*/ + uint32_t rd_len; /**< Number of Read Data Bytes*/ + uint32_t addr_len; /**< Number of Address Bytes*/ + uint32_t wr_len; /**< Number of Write Data Bytes*/ + uint32_t d_sycle; /**< Number of dummy cycles*/ + type_func_t mode_bit; /**< Mode Bit Configuration register are sent following the address bytes*/ + type_func_t op_addr; /**< If opcde requires an address*/ + uint32_t val; /**< Mode bits,sent to device following the address*/ + uint32_t addr; /**< Flash opcde address*/ + void *rd_buf; /**< Buffer for read data*/ + void *wr_buf; /**< Buffer with data to write*/ +} qspi_stig_cmd_t; + +/** + * @brief QSPI base initialization structure. + */ +typedef struct { + qspi_clk_div_t clkdiv; /**< QSPI Baud Rate Clock Prescaler*/ + type_func_t wrppin; /**< QSPI Set Write Protect Pin*/ + qspi_nss_decode_t nssdcode; /**< QSPI Peripheral Select Decode*/ + qspi_nss_t chipsel; /**< QSPI Peripheral Select Line*/ + qspi_cpol_t cpol; /**< QSPI polarity */ + qspi_cpha_t chpa; /**< QSPI phase */ +} qspi_init_t; + +/** + * @brief QSPI legacy initialization structure. + */ +typedef struct { + uint8_t tx_thrd; /**< Tx FIFO threshhold */ + uint8_t rx_thrd; /**< Rx FIFO threshhold */ +} qspi_legacy_cfg_t; + +/** + * @brief QSPI Device Read Instruction Configuration structure. + */ +typedef struct { + uint8_t rdcde; /**< Read opcode in non-xip mode*/ + uint8_t dcyles; /**< Number of dummy read clock cycles*/ + uint8_t mbitval; /**< Mode bits,sent to device following the address bytes*/ + type_func_t ddrbit; /**< Opcode from bit 7 to 0 is compliant with DDR command*/ + type_func_t modebit; /**< Enable mode bit*/ + qspi_xfer_t addxfer; /**< Transfer type used for address*/ + qspi_xfer_t datxfer; /**< Transfer type used for data*/ + qspi_xfer_t instxfer; /**< Transfer type used for instruction*/ +} qspi_read_cfg_t; + +/** + * @brief QSPI Device Write Instruction Configuration structure. + */ +typedef struct { + uint8_t wrcde; /**< Write opcode*/ + uint8_t dcyles; /**< Number of dummy read clock cycles*/ + qspi_xfer_t addxfer; /**< Transfer type used for address*/ + qspi_xfer_t datxfer; /**< Transfer type used for data*/ + qspi_xfer_t instxfer; /**< Transfer type used for instruction*/ + type_func_t autowel; /**< Turn off automatic*/ +} qspi_write_cfg_t; + +/** + * @brief QSPI Indirect Configuration structure.involatile parameters + */ +typedef struct { + uint32_t saddr; /**< Flash start address, commence write operation*/ + uint32_t wrlen; /**< Number of indirect write bytes*/ +} qspi_indac_wr_cfg_t; + +typedef struct { + uint32_t saddr; /**< FLASH start address, commence read operation*/ + uint32_t rdlen; /**< Number of indirect read bytes*/ +} qspi_indac_rd_cfg_t; + +typedef struct { + uint32_t srampt; /**< Defines the size of the indirect read partion in the SRAM*/ + uint32_t trgaddr; /**< Indirect trigger address which is used by AHB controller*/ + uint32_t trgrng; /**< The offset of indirect trigger address*/ + uint32_t wrwmark; /**< Maximum fill level of SRAM before a DMA, 0xFFFFFFFF disable the function*/ + uint32_t rdwmark; /**< Fill level passes watermark, an interrupt generated*/ +} qspi_indac_cfg_t; + +/** + * @brief QSPI DAC configuration. + */ +typedef struct { + type_func_t dtrprtcol; /**< DTR protocol*/ + type_func_t ahbdecoder; /**< AHB decoder, direct access mode only*/ + type_func_t xipimmed; /**< QSPI Enter XIP Immediately*/ + type_func_t xipnextrd; /**< QSPI Enter XIP Next Read*/ + type_func_t addrremap; /**< Enable AHB address re-mapping*/ + uint32_t remapaddr; /**< Remap incoming AHB address to different address*/ + type_func_t dmaperh; /**< QSPI dma interface*/ + qspi_read_cfg_t rdinit; /**< QSPI read instruction configuration*/ + qspi_write_cfg_t wrinit; /**< QSPI write instruction configuration*/ +} qspi_dac_cfg_t; + +/** + * @brief QSPI Handle Structure definition + */ +typedef struct { + QSPI_TypeDef *perh; /**< QSPI registers base address*/ + qspi_init_t init; /**< QSPI communication parameters*/ + uint8_t *tx_buf; /**< Pointer to QSPI transfer buffer */ + uint16_t tx_size; /**< QSPI transfer size */ + uint16_t tx_cnt; /**< QSPI transfer counter */ + uint8_t *rx_buf; /**< Pointer to QSPI receive buffer */ + uint16_t rx_size; /**< QSPI receive size */ + uint16_t rx_cnt; /**< QSPI receive counter */ +#ifdef ALD_DMA + dma_handle_t hdma; /**< QSPI Rx/Tx DMA Handle parameters*/ +#endif + qspi_state_t state; /**< QSPI communication state */ + __IO lock_state_t lock; /**< Locking object*/ +} qspi_handle_t; + +/** + * @brief Defines command to be executed using STIG mechanism. + */ +typedef struct { + uint32_t ccsot; /**< range [0 ~ 255]*/ + uint32_t cseot; /**< range [0 ~ 255]*/ + uint32_t csdads; /**< range [0 ~ 255]*/ + uint32_t csda; /**< range [0 ~ 255]*/ +} qspi_dly_cfg_t; + +/** + * @brief QSPI Read Data Capture Configuration. + */ +typedef struct { + uint32_t dlytd; /**< Delay transmitted data [0 ~ 15]*/ + uint32_t dlydcl; /**< Delay the read data capturing logic [0 ~ 15]*/ + type_func_t bypsalcc; /**< Bypass of the adapted loopback clock circuit @ref type_func_t*/ + qspi_data_sampled_t smpledge; /**< Sample edge selection(of the flash data outputs) @ref qspi_data_sampled_t*/ +} qspi_data_capture_cfg_t; + +/** + * @brief QSPI Indirect Write Progress Status. + */ +typedef enum { + QSPI_INDWR_PROGRESS = (1U << 2), /**< Indirect write operation in progress*/ + QSPI_INDWR_CPLT = (1U << 5), /**< Indirect write completion*/ +} qspi_indwr_status_t; + +/** + * @brief QSPI Indirect Read Progress Status. + */ +typedef enum { + QSPI_INDRD_PROGRESS = (1U << 2), /**< Indirect read operation in progress*/ + QSPI_RD_CPLT = (1U << 5), /**< Indirect read completion*/ +} qspi_indrd_flag_t; + +/** + * @brief QSPI Auto Poll Configuration Struction. + */ +typedef struct { + uint32_t opcode; /**< Automatically poll operation code */ + uint32_t indx; /**< Polling bit index */ + uint32_t polarity; /**< Defines polling polarity */ + uint32_t validcnt; /**< Expect true result times */ + uint32_t repdly; /**< Defines additional delay for maintain de-assert during auto-polling phase */ + uint32_t polexpcnt; /**< Poll cycles,which polling expiration interrupt is generated*/ +} qspi_auto_poll_t; + +/** + *@brief QSPI_Interrupt_definition QSPI Interrupt Definition + */ +typedef enum { + QSPI_IT_POLLF = (1U << 13), /**< Programmed polls cycles expired flag */ + QSPI_IT_INDRSFF = (1U << 12), /**< Indirect read partition of SRAM is full flag */ + QSPI_IT_SRFFF = (1U << 11), /**< Small rx FIFO full flag */ + QSPI_IT_SRFNEF = (1U << 10), /**< Small rx FIFO not empty flag */ + QSPI_IT_STFFF = (1U << 9), /**< Small tx FIFO full flag */ + QSPI_IT_STFNFF = (1U << 8), /**< Small tx FIFO not full flag */ + QSPI_IT_ROVF = (1U << 7), /**< Receive overflow flag */ + QSPI_IT_INDTWF = (1U << 6), /**< Indirect transfer watermark level breached flag */ + QSPI_IT_AHBAEF = (1U << 5), /**< Illegal AHB access detected flag */ + QSPI_IT_WPAF = (1U << 4), /**< Write to protected area was rejected flag */ + QSPI_IT_INDRRF = (1U << 3), /**< Indirect operation could not be accepted flag */ + QSPI_IT_INDCF = (1U << 2), /**< Controller has completed last triggered indirect operation flag */ + QSPI_IT_UDFF = (1U << 1), /**< Underflow detected flag */ + QSPI_IT_MODFF = (1U << 0), /**< Mode fail M flag */ +} qspi_it_t; +/** + * @brief QSPI_Flag_definition QSPI Flag Definition + */ +typedef enum { + QSPI_IF_POLLF = (1U << 13), /**< Programmed polls cycles expired flag */ + QSPI_IF_INDRSFF = (1U << 12), /**< Indirect read partition of SRAM is full flag */ + QSPI_IF_SRFFF = (1U << 11), /**< Small rx FIFO full flag */ + QSPI_IF_SRFNEF = (1U << 10), /**< Small rx FIFO not empty flag */ + QSPI_IF_STFFF = (1U << 9), /**< Small tx FIFO full flag */ + QSPI_IF_STFNFF = (1U << 8), /**< Small tx FIFO not full flag */ + QSPI_IF_ROVF = (1U << 7), /**< Receive overflow flag */ + QSPI_IF_INDTWF = (1U << 6), /**< Indirect transfer watermark level breached flag */ + QSPI_IF_AHBAEF = (1U << 5), /**< Illegal AHB access detected flag */ + QSPI_IF_WPAF = (1U << 4), /**< Write to protected area was rejected flag */ + QSPI_IF_INDRRF = (1U << 3), /**< Indirect operation could not be accepted flag */ + QSPI_IF_INDCF = (1U << 2), /**< Controller has completed last triggered indirect operation flag */ + QSPI_IF_UDFF = (1U << 1), /**< Underflow detected flag */ + QSPI_IF_MODFF = (1U << 0), /**< Mode fail M flag */ +} qspi_flag_t; +/** + * @} + */ + +/** @defgroup QSPI_Private_Macros QSPI Private Macros + * @{ + */ +#define IS_QSPI_SRAM_PARTITION(x) ((x) < 255) +#define IS_QSPI_INDIRECT_TRIGGER_RANGE(x) (((x) < 16)) +#define IS_QSPI_INDIRECT_READ_WATERMARK(x) ((x) < 512) +#define IS_QSPI_INDIRECT_SRAM_FILL_TYPE(x) (((x) == QSPI_SRAM_RD) || ((x) == QSPI_SRAM_WR)) +#define IS_QSPI_INDIRECT_READ_STATUS(x) (((x) == QSPI_INDRD_PROGRESS) || ((x) == QSPI_RD_CPLT)) +#define IS_QSPI_INDIRECT_WRITE_STATUS(x) (((x) == QSPI_INDWR_PROGRESS) || ((x) == QSPI_INDWR_CPLT)) +#define IS_QSPI_DEVICE_DELAY_CCSOT(x) ((x) < 256) +#define IS_QSPI_DEVICE_DELAY_CSEOT(x) ((x) < 256) +#define IS_QSPI_DEVICE_DELAY_CSDADS(x) ((x) < 256) +#define IS_QSPI_DEVICE_DELAY_CSDA(x) ((x) < 256) + +#define IS_QSPI_READ_DATA_CAPTURE_DELAY_READ(x) ((x) < 16) +#define IS_QSPI_READ_DATA_SAMPLE_EDGE(x) (((x) == QSPI_FALLING_E) || \ + ((x) == QSPI_RISING_E)) +#define IS_QSPI_READ_DATA_DELAY_TRANSMIT(x) ((x) < 16) +#define IS_QSPI_ALL(x) ((x) == QSPI) +#define IS_QSPI_DCYLES(x) ((x) <= 31) + +#define IS_QSPI_ADDR_SIZE(x) ((x) <= 15) +#define IS_QSPI_PAGE_SIZE(x) ((x) <= 0xfff) +#define IS_QSPI_BLOCK_SIZE(x) ((x) <= 0x1f) +#define IS_QSPI_NSS_SIZE(x) ((x) <= 3) + +#define IS_QSPI_XFER_TYPE(x) (((x) == QSPI_XFER_SINGLE) || \ + ((x) == QSPI_XFER_DUAL) || \ + ((x) == QSPI_XFER_QUAD)) +#define IS_QSPI_DDR_BIT_ENABLE(x) (((x) == QSPI_READ_DDR_BIT_DISABLE) || \ + ((x) == QSPI_READ_DDR_BIT_ENABLE)) +#define IS_QSPI_MODE_BIT_ENABLE(x) (((x) == QSPI_READ_INST_MODE_BIT_DISABLE) || \ + ((x) == QSPI_READ_INST_MODE_BIT_ENABLE)) +#define IS_QSPI_RD_OPCODE(x) (((x) < 0xFF)) +#define IS_QSPI_WR_OPCODE(x) (((x) < 0xFF)) +#define IS_QSPI_CLOCK_PRESCALER(x) (((x) == QSPI_DIV_2) || \ + ((x) == QSPI_DIV_4) || \ + ((x) == QSPI_DIV_6) || \ + ((x) == QSPI_DIV_8) || \ + ((x) == QSPI_DIV_10) || \ + ((x) == QSPI_DIV_12) || \ + ((x) == QSPI_DIV_14) || \ + ((x) == QSPI_DIV_16) || \ + ((x) == QSPI_DIV_18) || \ + ((x) == QSPI_DIV_20) || \ + ((x) == QSPI_DIV_22) || \ + ((x) == QSPI_DIV_24) || \ + ((x) == QSPI_DIV_26) || \ + ((x) == QSPI_DIV_28) || \ + ((x) == QSPI_DIV_30) || \ + ((x) == QSPI_DIV_32)) +#define IS_QSPI_CLOCK_PHASE(x) (((x) == QSPI_CPHA_1E) || \ + ((x) == QSPI_CPHA_2E)) +#define IS_QSPI_CLOCK_POLARITY(x) (((x) == QSPI_CPOL_L) || \ + ((x) == QSPI_CPOL_H)) +#define IS_QSPI_IF(x) (((x) == QSPI_IF_POLLF) || \ + ((x) == QSPI_IF_INDRSFF) || \ + ((x) == QSPI_IF_SRFFF) || \ + ((x) == QSPI_IF_SRFNEF) || \ + ((x) == QSPI_IF_STFFF) || \ + ((x) == QSPI_IF_STFNFF) || \ + ((x) == QSPI_IF_ROVF) || \ + ((x) == QSPI_IF_INDTWF) || \ + ((x) == QSPI_IF_AHBAEF) || \ + ((x) == QSPI_IF_WPAF) || \ + ((x) == QSPI_IF_INDRRF) || \ + ((x) == QSPI_IF_INDCF) || \ + ((x) == QSPI_IF_UDFF) || \ + ((x) == QSPI_IF_MODFF)) +#define IS_QSPI_IT(x) (((x) == QSPI_IT_POLLF) || \ + ((x) == QSPI_IT_INDRSFF) || \ + ((x) == QSPI_IT_SRFFF) || \ + ((x) == QSPI_IT_SRFNEF) || \ + ((x) == QSPI_IT_STFFF) || \ + ((x) == QSPI_IT_STFNFF) || \ + ((x) == QSPI_IT_ROVF) || \ + ((x) == QSPI_IT_INDTWF) || \ + ((x) == QSPI_IT_AHBAEF) || \ + ((x) == QSPI_IT_WPAF) || \ + ((x) == QSPI_IT_INDRRF) || \ + ((x) == QSPI_IT_INDCF) || \ + ((x) == QSPI_IT_UDFF) || \ + ((x) == QSPI_IT_MODFF)) + +/** + * @} + */ + +/** + * @defgroup QSPI_Public_Macros QSPI Public Macros + * @{ + */ +#define QSPI_MEMORY_ADDRESS 0x90000000 +#define QSPI_SRAM_SIZE 255 +#define QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5s */ +#define QSPI_SRAM_DEPTH 0xFF +#define QSPI_DAC_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK) +#define QSPI_DAC_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK) +#define QSPI_LEGACY_SPI_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK) +#define QSPI_LEGACY_SPI_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK) +#define QSPI_WRITE_PROTECT_ENABLE(hperh) SET_BIT((hperh)->perh->WPCR, QSPI_WPCR_WPEN_MSK); +#define QSPI_WRITE_PROTECT_DISABLE(hperh) CLEAR_BIT((hperh)->perh->WPCR, QSPI_WPCR_WPEN_MSK); +#define QSPI_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_EN_MSK) +#define QSPI_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_EN_MSK) +#define QSPI_AUTO_POLL_ENABLE(hperh) CLEAR_BIT((hperh)->perh->WCR, QSPI_WCR_PDIS_MSK) +#define QSPI_AUTO_POLL_DISABLE(hperh) SET_BIT((hperh)->perh->WCR, QSPI_WCR_PDIS_MSK) +#define QSPI_DMA_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_DMAEN_MSK) +#define QSPI_DMA_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DMAEN_MSK) +#define QSPI_CANCEL_INDIRECT_READ(hperh) SET_BIT((hperh)->perh->IRTR, QSPI_IRTR_RDDIS_MSK) +/** + * @} + */ + +/** @addtogroup QSPI_Public_Functions + * @{ + */ + +/** @addtogroup QSPI_Public_Functions_Group1 + * @{ + */ +/* QSPI basic execution functions */ +void ald_qspi_init(qspi_handle_t *hperh); +uint32_t ald_qspi_dac_rd(uint32_t addr); +void ald_qspi_dac_wr(uint32_t addr, uint32_t dat); +ald_status_t ald_qspi_read_config(qspi_handle_t* hperh, const qspi_read_cfg_t * rdcfg); +ald_status_t ald_qspi_write_config(qspi_handle_t* hperh, const qspi_write_cfg_t * wrcfg); +ald_status_t ald_qspi_device_delay_config(qspi_handle_t * hperh, qspi_dly_cfg_t *dlycfg); +ald_status_t ald_qspi_read_data_capture_config(qspi_handle_t * hperh, qspi_data_capture_cfg_t *dtcptcfg); +ald_status_t ald_qspi_device_size_config(qspi_handle_t *hperh, qspi_device_size_t * devcfg); +ald_status_t qspi_dac_config(qspi_handle_t * hperh, qspi_dac_cfg_t * dcfg); +/** + * @} + */ +/** @addtogroup QSPI_Public_Functions_Group2 + * @{ + */ +/* QSPI indirect and stig access execution functions */ +ald_status_t ald_qspi_indac_config(qspi_handle_t * hperh, qspi_indac_cfg_t *indcfg); +ald_status_t ald_qspi_indac_transmit_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size); +ald_status_t ald_qspi_indac_transmit_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size); +ald_status_t ald_qspi_indac_read_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size); +ald_status_t ald_qspi_indac_read_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size); +ald_status_t ald_qspi_execute_stig_cmd(qspi_handle_t* hperh, const qspi_stig_cmd_t * scmd); +#ifdef ALD_DMA +ald_status_t ald_qspi_indac_transmit_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *psrc, uint16_t size); +ald_status_t ald_qspi_indac_read_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *pdbuf, uint16_t size); +#endif +/** + * @} + */ +/** @addtogroup QSPI_Public_Functions_Group3 + * @{ + */ +/* QSPI status functions */ +flag_status_t qspi_get_flag_status(qspi_handle_t *hperh, qspi_flag_t flag); +void ald_qspi_clear_it_flag(qspi_handle_t *hperh, qspi_flag_t flag); +uint16_t qspi_read_sram_fill_level(qspi_handle_t * hperh, qspi_sram_t srt); +void ald_qspi_write_proect_config(qspi_handle_t * hperh, qspi_wr_protect_t* wpcfg); +void ald_qspi_write_proect_inverse(qspi_handle_t * hperh, type_func_t state); +ald_status_t ald_qspi_auto_poll(qspi_handle_t *hperh, qspi_auto_poll_t* apcfg); +void ald_qspi_irq_handler(qspi_handle_t *hperh); +void ald_qspi_interrupt_config(qspi_handle_t *hperh, qspi_it_t it, type_func_t state); +void ald_qspi_legacy_config(qspi_handle_t* hperh, const qspi_legacy_cfg_t *config); +flag_status_t qspi_indwr_get_status(qspi_handle_t *hperh, qspi_indwr_status_t status); +ald_status_t qspi_indwr_wait_flag(qspi_handle_t *hperh, qspi_indwr_status_t flag, flag_status_t status, uint32_t timeout); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif /* __ALD_QSPI_H__ */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h similarity index 45% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h rename to bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h index 22b8fd21a13eb044fb73c67268a2cbcea857dc3b..3aaf0116928321000f525147290f405c2dd9468e 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rmu.h @@ -5,7 +5,7 @@ * @brief Header file of RMU module driver. * * @version V1.0 - * @date 04 Dec 2017 + * @date 04 Dec 2019 * @author AE Team * @note * @@ -37,107 +37,108 @@ extern "C" { /** * @brief RMU BOR fliter */ -typedef enum -{ - RMU_BORFLT_1 = 0x1, /**< 1 cycle */ - RMU_BORFLT_2 = 0x2, /**< 2 cycles */ - RMU_BORFLT_3 = 0x3, /**< 3 cycles */ - RMU_BORFLT_4 = 0x4, /**< 4 cycles */ - RMU_BORFLT_5 = 0x5, /**< 5 cycles */ - RMU_BORFLT_6 = 0x6, /**< 6 cycles */ - RMU_BORFLT_7 = 0x7, /**< 7 cycles */ +typedef enum { + RMU_BORFLT_1 = 0x1, /**< 1 cycle */ + RMU_BORFLT_2 = 0x2, /**< 2 cycles */ + RMU_BORFLT_3 = 0x3, /**< 3 cycles */ + RMU_BORFLT_4 = 0x4, /**< 4 cycles */ + RMU_BORFLT_5 = 0x5, /**< 5 cycles */ + RMU_BORFLT_6 = 0x6, /**< 6 cycles */ + RMU_BORFLT_7 = 0x7, /**< 7 cycles */ } rmu_bor_filter_t; /** * @brief RMU BOR voltage */ -typedef enum -{ - RMU_VOL_1_7 = 0x0, /**< 1.7V */ - RMU_VOL_2_0 = 0x1, /**< 2.0V */ - RMU_VOL_2_1 = 0x2, /**< 2.1V */ - RMU_VOL_2_2 = 0x3, /**< 2.2V */ - RMU_VOL_2_3 = 0x4, /**< 2.3V */ - RMU_VOL_2_4 = 0x5, /**< 2.4V */ - RMU_VOL_2_5 = 0x6, /**< 2.5V */ - RMU_VOL_2_6 = 0x7, /**< 2.6V */ - RMU_VOL_2_8 = 0x8, /**< 2.8V */ - RMU_VOL_3_0 = 0x9, /**< 3.0V */ - RMU_VOL_3_1 = 0xA, /**< 3.1V */ - RMU_VOL_3_3 = 0xB, /**< 3.3V */ - RMU_VOL_3_6 = 0xC, /**< 3.6V */ - RMU_VOL_3_7 = 0xD, /**< 3.7V */ - RMU_VOL_4_0 = 0xE, /**< 4.0V */ - RMU_VOL_4_3 = 0xF, /**< 4.3V */ +typedef enum { + RMU_VOL_NONE = 0x0, /**< Disable */ + RMU_VOL_2_0 = 0x1, /**< 2.0V */ + RMU_VOL_2_2 = 0x2, /**< 2.2V */ + RMU_VOL_2_4 = 0x3, /**< 2.4V */ + RMU_VOL_2_6 = 0x4, /**< 2.6V */ + RMU_VOL_2_8 = 0x5, /**< 2.8V */ + RMU_VOL_3_0 = 0x6, /**< 3.0V */ + RMU_VOL_3_2 = 0x7, /**< 3.2V */ + RMU_VOL_3_4 = 0x8, /**< 3.4V */ + RMU_VOL_3_6 = 0x9, /**< 3.6V */ + RMU_VOL_3_8 = 0xA, /**< 3.8V */ + RMU_VOL_4_0 = 0xB, /**< 4.0V */ + RMU_VOL_4_2 = 0xC, /**< 4.2V */ + RMU_VOL_4_4 = 0xD, /**< 4.4V */ + RMU_VOL_4_6 = 0xE, /**< 4.6V */ + RMU_VOL_4_8 = 0xF, /**< 4.8V */ } rmu_bor_vol_t; /** * @brief RMU reset status */ -typedef enum -{ - RMU_RST_POR = (1U << 0), /**< POR */ - RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */ - RMU_RST_BOR = (1U << 2), /**< BOR */ - RMU_RST_NMRST = (1U << 3), /**< NMRST */ - RMU_RST_IWDT = (1U << 4), /**< IWDT */ - RMU_RST_WWDT = (1U << 5), /**< WWDT */ - RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */ - RMU_RST_CHIP = (1U << 7), /**< CHIP */ - RMU_RST_MCU = (1U << 8), /**< MCU */ - RMU_RST_CPU = (1U << 9), /**< CPU */ - RMU_RST_CFG = (1U << 10), /**< CFG */ - RMU_RST_CFGERR = (1U << 16), /**< CFG Error */ +typedef enum { + RMU_RST_POR = (1U << 0), /**< POR */ + RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */ + RMU_RST_BOR = (1U << 2), /**< BOR */ + RMU_RST_NMRST = (1U << 3), /**< NMRST */ + RMU_RST_IWDT = (1U << 4), /**< IWDT */ + RMU_RST_WWDT = (1U << 5), /**< WWDT */ + RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */ + RMU_RST_CHIP = (1U << 7), /**< CHIP */ + RMU_RST_MCU = (1U << 8), /**< MCU */ + RMU_RST_CPU = (1U << 9), /**< CPU */ + RMU_RST_CFG = (1U << 10), /**< CFG */ + RMU_RST_CFGERR = (1U << 16), /**< CFG Error */ } rmu_state_t; /** * @brief RMU periperal select bit */ -typedef enum -{ - RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */ - RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */ - RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */ - RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */ - RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */ - RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */ - RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */ - RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */ - RMU_PERH_TIM0 = (1U << 0) | (1U << 28), /**< APB1: TIM0 */ - RMU_PERH_TIM1 = (1U << 1) | (1U << 28), /**< APB1: TIM1 */ - RMU_PERH_TIM2 = (1U << 2) | (1U << 28), /**< APB1: TIM2 */ - RMU_PERH_TIM3 = (1U << 3) | (1U << 28), /**< APB1: TIM3 */ - RMU_PERH_TIM4 = (1U << 4) | (1U << 28), /**< APB1: TIM4 */ - RMU_PERH_TIM5 = (1U << 5) | (1U << 28), /**< APB1: TIM5 */ - RMU_PERH_TIM6 = (1U << 6) | (1U << 28), /**< APB1: TIM6 */ - RMU_PERH_TIM7 = (1U << 7) | (1U << 28), /**< APB1: TIM7 */ - RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */ - RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */ - RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */ - RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */ - RMU_PERH_USART0 = (1U << 12) | (1U << 28), /**< APB1: EUART0 */ - RMU_PERH_USART1 = (1U << 13) | (1U << 28), /**< APB1: EUART1 */ - RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */ - RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */ - RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */ - RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */ - RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */ - RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */ - RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */ - RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */ - RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */ - RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */ - RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */ - RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */ - RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */ - RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */ - RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */ - RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */ - RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */ - RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */ - RMU_PERH_TEMP = (1U << 16) | (1U << 29), /**< APB2: TEMP */ - RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */ - RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */ +typedef enum { + RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */ + RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */ + RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */ + RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */ + RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */ + RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */ + RMU_PERH_USB = (1U << 10), /**< AHB1: USB */ + RMU_PERH_ECC = (1U << 11), /**< AHB1: ECC */ + RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */ + RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */ + RMU_PERH_EBI = (1U << 8) | (1U << 27), /**< AHB2: EBI */ + RMU_PERH_TIMER0 = (1U << 0) | (1U << 28), /**< APB1: TIMER0 */ + RMU_PERH_TIMER1 = (1U << 1) | (1U << 28), /**< APB1: TIMER1 */ + RMU_PERH_TIMER2 = (1U << 2) | (1U << 28), /**< APB1: TIMER2 */ + RMU_PERH_TIMER3 = (1U << 3) | (1U << 28), /**< APB1: TIMER3 */ + RMU_PERH_TIMER4 = (1U << 4) | (1U << 28), /**< APB1: TIMER4 */ + RMU_PERH_TIMER5 = (1U << 5) | (1U << 28), /**< APB1: TIMER5 */ + RMU_PERH_TIMER6 = (1U << 6) | (1U << 28), /**< APB1: TIMER6 */ + RMU_PERH_TIMER7 = (1U << 7) | (1U << 28), /**< APB1: TIMER7 */ + RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */ + RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */ + RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */ + RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */ + RMU_PERH_UART4 = (1U << 12) | (1U << 28), /**< APB1: UART4 */ + RMU_PERH_UART5 = (1U << 13) | (1U << 28), /**< APB1: UART5 */ + RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */ + RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */ + RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */ + RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */ + RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */ + RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */ + RMU_PERH_QSPI = (1U << 25) | (1U << 28), /**< APB1: QSPI */ + RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */ + RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */ + RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */ + RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */ + RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */ + RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */ + RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */ + RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */ + RMU_PERH_ACMP2 = (1U << 11) | (1U << 29), /**< APB2: WWDT */ + RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */ + RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */ + RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */ + RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */ + RMU_PERH_TSENSE = (1U << 16) | (1U << 29), /**< APB2: TSENSE */ + RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */ + RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */ } rmu_peripheral_t; /** * @} @@ -147,30 +148,30 @@ typedef enum * @defgroup RMU_Private_Macros RMU Private Macros * @{ */ -#define IS_RMU_BORFLT(x) (((x) == RMU_BORFLT_1) || \ +#define IS_RMU_BORFLT(x) (((x) == RMU_BORFLT_1) || \ ((x) == RMU_BORFLT_2) || \ ((x) == RMU_BORFLT_3) || \ ((x) == RMU_BORFLT_4) || \ ((x) == RMU_BORFLT_5) || \ ((x) == RMU_BORFLT_6) || \ ((x) == RMU_BORFLT_7)) -#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_7) || \ +#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_NONE) || \ ((x) == RMU_VOL_2_0) || \ - ((x) == RMU_VOL_2_1) || \ ((x) == RMU_VOL_2_2) || \ - ((x) == RMU_VOL_2_3) || \ ((x) == RMU_VOL_2_4) || \ - ((x) == RMU_VOL_2_5) || \ ((x) == RMU_VOL_2_6) || \ ((x) == RMU_VOL_2_8) || \ ((x) == RMU_VOL_3_0) || \ - ((x) == RMU_VOL_3_1) || \ - ((x) == RMU_VOL_3_3) || \ + ((x) == RMU_VOL_3_2) || \ + ((x) == RMU_VOL_3_4) || \ ((x) == RMU_VOL_3_6) || \ - ((x) == RMU_VOL_3_7) || \ + ((x) == RMU_VOL_3_8) || \ ((x) == RMU_VOL_4_0) || \ - ((x) == RMU_VOL_4_3)) -#define IS_RMU_STATE(x) (((x) == RMU_RST_POR) || \ + ((x) == RMU_VOL_4_2) || \ + ((x) == RMU_VOL_4_4) || \ + ((x) == RMU_VOL_4_6) || \ + ((x) == RMU_VOL_4_8)) +#define IS_RMU_STATE(x) (((x) == RMU_RST_POR) || \ ((x) == RMU_RST_WAKEUP) || \ ((x) == RMU_RST_BOR) || \ ((x) == RMU_RST_NMRST) || \ @@ -182,7 +183,7 @@ typedef enum ((x) == RMU_RST_CPU) || \ ((x) == RMU_RST_CFG) || \ ((x) == RMU_RST_CFGERR)) -#define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \ +#define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \ ((x) == RMU_RST_WAKEUP) || \ ((x) == RMU_RST_BOR) || \ ((x) == RMU_RST_NMRST) || \ @@ -193,34 +194,38 @@ typedef enum ((x) == RMU_RST_MCU) || \ ((x) == RMU_RST_CPU) || \ ((x) == RMU_RST_CFG)) -#define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \ +#define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \ ((x) == RMU_PERH_CRC) || \ ((x) == RMU_PERH_CALC) || \ ((x) == RMU_PERH_CRYPT) || \ ((x) == RMU_PERH_TRNG) || \ ((x) == RMU_PERH_PIS) || \ + ((x) == RMU_PERH_USB) || \ + ((x) == RMU_PERH_ECC) || \ ((x) == RMU_PERH_CHIP) || \ ((x) == RMU_PERH_CPU) || \ - ((x) == RMU_PERH_TIM0) || \ - ((x) == RMU_PERH_TIM1) || \ - ((x) == RMU_PERH_TIM2) || \ - ((x) == RMU_PERH_TIM3) || \ - ((x) == RMU_PERH_TIM4) || \ - ((x) == RMU_PERH_TIM5) || \ - ((x) == RMU_PERH_TIM6) || \ - ((x) == RMU_PERH_TIM7) || \ + ((x) == RMU_PERH_EBI) || \ + ((x) == RMU_PERH_TIMER0) || \ + ((x) == RMU_PERH_TIMER1) || \ + ((x) == RMU_PERH_TIMER2) || \ + ((x) == RMU_PERH_TIMER3) || \ + ((x) == RMU_PERH_TIMER4) || \ + ((x) == RMU_PERH_TIMER5) || \ + ((x) == RMU_PERH_TIMER6) || \ + ((x) == RMU_PERH_TIMER7) || \ ((x) == RMU_PERH_UART0) || \ ((x) == RMU_PERH_UART1) || \ ((x) == RMU_PERH_UART2) || \ ((x) == RMU_PERH_UART3) || \ - ((x) == RMU_PERH_USART0) || \ - ((x) == RMU_PERH_USART1) || \ + ((x) == RMU_PERH_UART4) || \ + ((x) == RMU_PERH_UART5) || \ ((x) == RMU_PERH_SPI0) || \ ((x) == RMU_PERH_SPI1) || \ ((x) == RMU_PERH_SPI2) || \ ((x) == RMU_PERH_I2C0) || \ ((x) == RMU_PERH_I2C1) || \ ((x) == RMU_PERH_CAN0) || \ + ((x) == RMU_PERH_QSPI) || \ ((x) == RMU_PERH_LPTIM0) || \ ((x) == RMU_PERH_LPUART0) || \ ((x) == RMU_PERH_ADC0) || \ @@ -229,11 +234,12 @@ typedef enum ((x) == RMU_PERH_ACMP1) || \ ((x) == RMU_PERH_OPAMP) || \ ((x) == RMU_PERH_DAC0) || \ + ((x) == RMU_PERH_ACMP2) || \ ((x) == RMU_PERH_WWDT) || \ ((x) == RMU_PERH_LCD) || \ ((x) == RMU_PERH_IWDT) || \ ((x) == RMU_PERH_RTC) || \ - ((x) == RMU_PERH_TEMP) || \ + ((x) == RMU_PERH_TSENSE) || \ ((x) == RMU_PERH_BKPC) || \ ((x) == RMU_PERH_BKPRAM)) /** @@ -243,10 +249,10 @@ typedef enum /** @addtogroup RMU_Public_Functions * @{ */ -void rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state); -flag_status_t rmu_get_reset_status(rmu_state_t state); -void rmu_clear_reset_status(rmu_state_t state); -void rmu_reset_periperal(rmu_peripheral_t perh); +void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state); +flag_status_t ald_rmu_get_reset_status(rmu_state_t state); +void ald_rmu_clear_reset_status(rmu_state_t state); +void ald_rmu_reset_periperal(rmu_peripheral_t perh); /** * @} */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h similarity index 43% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h rename to bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h index 9d0bce383f27b04dedbe1a93d052241d9c16ec21..0dd6f676b5ecc6f5bd8a9a1b607d235efd749b3e 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtc.h @@ -4,7 +4,7 @@ * @brief Header file of RTC Module driver. * * @version V1.0 - * @date 16 Nov 2017 + * @date 16 Nov 2019 * @author AE Team * @note * @@ -38,365 +38,335 @@ extern "C" { /** * @brief Hours format */ -typedef enum -{ - RTC_HOUR_FORMAT_24 = 0x0, /**< 24-hours format */ - RTC_HOUR_FORMAT_12 = 0x1, /**< 12-hours format */ +typedef enum { + RTC_HOUR_FORMAT_24 = 0x0, /**< 24-hours format */ + RTC_HOUR_FORMAT_12 = 0x1, /**< 12-hours format */ } rtc_hour_format_t; /** * @brief Output mode */ -typedef enum -{ - RTC_OUTPUT_DISABLE = 0x0, /**< Disable output */ - RTC_OUTPUT_ALARM_A = 0x1, /**< Output alarm_a signal */ - RTC_OUTPUT_ALARM_B = 0x2, /**< Output alarm_b signal */ - RTC_OUTPUT_WAKEUP = 0x3, /**< Output wakeup signal */ +typedef enum { + RTC_OUTPUT_DISABLE = 0x0, /**< Disable output */ + RTC_OUTPUT_ALARM_A = 0x1, /**< Output alarm_a signal */ + RTC_OUTPUT_ALARM_B = 0x2, /**< Output alarm_b signal */ + RTC_OUTPUT_WAKEUP = 0x3, /**< Output wakeup signal */ } rtc_output_select_t; /** * @brief Output polarity */ -typedef enum -{ - RTC_OUTPUT_POLARITY_HIGH = 0x0, /**< Polarity is high */ - RTC_OUTPUT_POLARITY_LOW = 0x0, /**< Polarity is low */ +typedef enum { + RTC_OUTPUT_POLARITY_HIGH = 0x0, /**< Polarity is high */ + RTC_OUTPUT_POLARITY_LOW = 0x1, /**< Polarity is low */ } rtc_output_polarity_t; /** * @brief Initialization structure */ -typedef struct -{ - rtc_hour_format_t hour_format; /**< Hours format */ - uint32_t asynch_pre_div; /**< Asynchronous predivider value */ - uint32_t synch_pre_div; /**< Synchronous predivider value */ - rtc_output_select_t output; /**< Output signal type */ - rtc_output_polarity_t output_polarity; /**< Output polarity */ +typedef struct { + rtc_hour_format_t hour_format; /**< Hours format */ + uint32_t asynch_pre_div; /**< Asynchronous predivider value */ + uint32_t synch_pre_div; /**< Synchronous predivider value */ + rtc_output_select_t output; /**< Output signal type */ + rtc_output_polarity_t output_polarity; /**< Output polarity */ } rtc_init_t; /** * @brief Source select */ -typedef enum -{ - RTC_SOURCE_LOSC = 0x0, /**< LOSC */ - RTC_SOURCE_LRC = 0x1, /**< LRC */ - RTC_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */ - RTC_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */ +typedef enum { + RTC_SOURCE_LOSC = 0x0, /**< LOSC */ + RTC_SOURCE_LRC = 0x1, /**< LRC */ + RTC_SOURCE_HRC_DIV_1M = 0x2, /**< HRC divide to 1MHz */ + RTC_SOURCE_HOSC_DIV_1M = 0x3, /**< HOSC divide to 1MHz */ } rtc_source_sel_t; /** * @brief Time structure */ -typedef struct -{ - uint8_t hour; /**< Hours */ - uint8_t minute; /**< Minutes */ - uint8_t second; /**< Seconds */ - uint16_t sub_sec; /**< Sub-seconds */ +typedef struct { + uint8_t hour; /**< Hours */ + uint8_t minute; /**< Minutes */ + uint8_t second; /**< Seconds */ + uint16_t sub_sec; /**< Sub-seconds */ } rtc_time_t; /** * @brief Date structure */ -typedef struct -{ - uint8_t week; /**< Weeks */ - uint8_t day; /**< days */ - uint8_t month; /**< months */ - uint8_t year; /**< years */ +typedef struct { + uint8_t week; /**< Weeks */ + uint8_t day; /**< days */ + uint8_t month; /**< months */ + uint8_t year; /**< years */ } rtc_date_t; /** * @brief Data format */ -typedef enum -{ - RTC_FORMAT_DEC = 0, - RTC_FORMAT_BCD = 1, +typedef enum { + RTC_FORMAT_DEC = 0, /**< Decimal */ + RTC_FORMAT_BCD = 1, /**< BSD */ } rtc_format_t; /** * @brief Index of alarm */ -typedef enum -{ - RTC_ALARM_A = 0x0, /**< Alarm-A */ - RTC_ALARM_B = 0x1, /**< Alarm-B */ +typedef enum { + RTC_ALARM_A = 0x0, /**< Alarm-A */ + RTC_ALARM_B = 0x1, /**< Alarm-B */ } rtc_alarm_idx_t; /** * @brief Alarm mask */ -typedef enum -{ - RTC_ALARM_MASK_NONE = 0x0, /**< Mask is disable */ - RTC_ALARM_MASK_WEEK_DAY = (1U << 30), /**< Mask week or day */ - RTC_ALARM_MASK_HOUR = (1U << 23), /**< Mask hour */ - RTC_ALARM_MASK_MINUTE = (1U << 15), /**< Mask minute */ - RTC_ALARM_MASK_SECOND = (1U << 7), /**< Mask second */ - RTC_ALARM_MASK_ALL = 0x40808080, /**< Mask all */ +typedef enum { + RTC_ALARM_MASK_NONE = 0x0, /**< Mask is disable */ + RTC_ALARM_MASK_WEEK_DAY = (1U << 30), /**< Mask week or day */ + RTC_ALARM_MASK_HOUR = (1U << 23), /**< Mask hour */ + RTC_ALARM_MASK_MINUTE = (1U << 15), /**< Mask minute */ + RTC_ALARM_MASK_SECOND = (1U << 7), /**< Mask second */ + RTC_ALARM_MASK_ALL = 0x40808080, /**< Mask all */ } rtc_alarm_mask_t; /** * @brief Alarm sub-second mask */ -typedef enum -{ - RTC_ALARM_SS_MASK_NONE = 0xF, /**< Mask is disable */ - RTC_ALARM_SS_MASK_14_1 = 0x1, /**< Mask bit(1-14) */ - RTC_ALARM_SS_MASK_14_2 = 0x2, /**< Mask bit(2-14) */ - RTC_ALARM_SS_MASK_14_3 = 0x3, /**< Mask bit(3-14) */ - RTC_ALARM_SS_MASK_14_4 = 0x4, /**< Mask bit(4-14) */ - RTC_ALARM_SS_MASK_14_5 = 0x5, /**< Mask bit(5-14) */ - RTC_ALARM_SS_MASK_14_6 = 0x6, /**< Mask bit(6-14) */ - RTC_ALARM_SS_MASK_14_7 = 0x7, /**< Mask bit(7-14) */ - RTC_ALARM_SS_MASK_14_8 = 0x8, /**< Mask bit(8-14) */ - RTC_ALARM_SS_MASK_14_9 = 0x9, /**< Mask bit(9-14) */ - RTC_ALARM_SS_MASK_14_10 = 0xA, /**< Mask bit(10-14) */ - RTC_ALARM_SS_MASK_14_11 = 0xB, /**< Mask bit(11-14) */ - RTC_ALARM_SS_MASK_14_12 = 0xC, /**< Mask bit(12-14) */ - RTC_ALARM_SS_MASK_14_13 = 0xD, /**< Mask bit(13-14) */ - RTC_ALARM_SS_MASK_14 = 0xE, /**< Mask bit14 */ - RTC_ALARM_SS_MASK_ALL = 0x0, /**< Mask bit(0-14) */ +typedef enum { + RTC_ALARM_SS_MASK_NONE = 0xF, /**< Mask is disable */ + RTC_ALARM_SS_MASK_14_1 = 0x1, /**< Mask bit(1-14) */ + RTC_ALARM_SS_MASK_14_2 = 0x2, /**< Mask bit(2-14) */ + RTC_ALARM_SS_MASK_14_3 = 0x3, /**< Mask bit(3-14) */ + RTC_ALARM_SS_MASK_14_4 = 0x4, /**< Mask bit(4-14) */ + RTC_ALARM_SS_MASK_14_5 = 0x5, /**< Mask bit(5-14) */ + RTC_ALARM_SS_MASK_14_6 = 0x6, /**< Mask bit(6-14) */ + RTC_ALARM_SS_MASK_14_7 = 0x7, /**< Mask bit(7-14) */ + RTC_ALARM_SS_MASK_14_8 = 0x8, /**< Mask bit(8-14) */ + RTC_ALARM_SS_MASK_14_9 = 0x9, /**< Mask bit(9-14) */ + RTC_ALARM_SS_MASK_14_10 = 0xA, /**< Mask bit(10-14) */ + RTC_ALARM_SS_MASK_14_11 = 0xB, /**< Mask bit(11-14) */ + RTC_ALARM_SS_MASK_14_12 = 0xC, /**< Mask bit(12-14) */ + RTC_ALARM_SS_MASK_14_13 = 0xD, /**< Mask bit(13-14) */ + RTC_ALARM_SS_MASK_14 = 0xE, /**< Mask bit14 */ + RTC_ALARM_SS_MASK_ALL = 0x0, /**< Mask bit(0-14) */ } rtc_sub_second_mask_t; /** * @brief Alarm select week or day */ -typedef enum -{ - RTC_SELECT_DAY = 0x0, /**< Alarm select day */ - RTC_SELECT_WEEK = 0x1, /**< Alarm select week */ +typedef enum { + RTC_SELECT_DAY = 0x0, /**< Alarm select day */ + RTC_SELECT_WEEK = 0x1, /**< Alarm select week */ } rtc_week_day_sel_t; /** * @brief Alarm structure */ -typedef struct -{ - rtc_alarm_idx_t idx; /**< Index of alarm */ - rtc_time_t time; /**< Time structure */ - uint32_t mask; /**< Alarm mask */ - rtc_sub_second_mask_t ss_mask; /**< Alarm sub-second mask */ - rtc_week_day_sel_t sel; /**< Select week or day */ - - union - { - uint8_t week; /**< Alarm select week */ - uint8_t day; /**< Alarm select day */ - }; +typedef struct { + rtc_alarm_idx_t idx; /**< Index of alarm */ + rtc_time_t time; /**< Time structure */ + uint32_t mask; /**< Alarm mask */ + rtc_sub_second_mask_t ss_mask; /**< Alarm sub-second mask */ + rtc_week_day_sel_t sel; /**< Select week or day */ + + union { + uint8_t week; /**< Alarm select week */ + uint8_t day; /**< Alarm select day */ + }; } rtc_alarm_t; /** * @brief Time stamp signel select */ -typedef enum -{ - RTC_TS_SIGNAL_SEL_TAMPER0 = 0, /**< Select tamper0 */ - RTC_TS_SIGNAL_SEL_TAMPER1 = 1, /**< Select tamper1 */ +typedef enum { + RTC_TS_SIGNAL_SEL_TAMPER0 = 0, /**< Select tamper0 */ + RTC_TS_SIGNAL_SEL_TAMPER1 = 1, /**< Select tamper1 */ } rtc_ts_signal_sel_t; /** * @brief Time stamp trigger style */ -typedef enum -{ - RTC_TS_RISING_EDGE = 0, /**< Rising edge */ - RTC_TS_FALLING_EDGE = 1, /**< Falling edge */ +typedef enum { + RTC_TS_RISING_EDGE = 0, /**< Rising edge */ + RTC_TS_FALLING_EDGE = 1, /**< Falling edge */ } rtc_ts_trigger_style_t; /** * @brief Index of tamper */ -typedef enum -{ - RTC_TAMPER_0 = 0, /**< Tamper0 */ - RTC_TAMPER_1 = 1, /**< Tamper1 */ +typedef enum { + RTC_TAMPER_0 = 0, /**< Tamper0 */ + RTC_TAMPER_1 = 1, /**< Tamper1 */ } rtc_tamper_idx_t; /** * @brief Tamper trigger type */ -typedef enum -{ - RTC_TAMPER_TRIGGER_LOW = 0, /**< High trigger */ - RTC_TAMPER_TRIGGER_HIGH = 1, /**< Low trigger */ +typedef enum { + RTC_TAMPER_TRIGGER_LOW = 0, /**< High trigger */ + RTC_TAMPER_TRIGGER_HIGH = 1, /**< Low trigger */ } rtc_tamper_trigger_t; /** * @brief Tamper sampling frequency */ -typedef enum -{ - RTC_TAMPER_SAMPLING_FREQ_32768 = 0, /**< RTCCLK / 32768 */ - RTC_TAMPER_SAMPLING_FREQ_16384 = 1, /**< RTCCLK / 16384 */ - RTC_TAMPER_SAMPLING_FREQ_8192 = 2, /**< RTCCLK / 8192 */ - RTC_TAMPER_SAMPLING_FREQ_4096 = 3, /**< RTCCLK / 4096 */ - RTC_TAMPER_SAMPLING_FREQ_2048 = 4, /**< RTCCLK / 2048 */ - RTC_TAMPER_SAMPLING_FREQ_1024 = 5, /**< RTCCLK / 1024 */ - RTC_TAMPER_SAMPLING_FREQ_512 = 6, /**< RTCCLK / 512 */ - RTC_TAMPER_SAMPLING_FREQ_256 = 7, /**< RTCCLK / 256 */ +typedef enum { + RTC_TAMPER_SAMPLING_FREQ_32768 = 0, /**< RTCCLK / 32768 */ + RTC_TAMPER_SAMPLING_FREQ_16384 = 1, /**< RTCCLK / 16384 */ + RTC_TAMPER_SAMPLING_FREQ_8192 = 2, /**< RTCCLK / 8192 */ + RTC_TAMPER_SAMPLING_FREQ_4096 = 3, /**< RTCCLK / 4096 */ + RTC_TAMPER_SAMPLING_FREQ_2048 = 4, /**< RTCCLK / 2048 */ + RTC_TAMPER_SAMPLING_FREQ_1024 = 5, /**< RTCCLK / 1024 */ + RTC_TAMPER_SAMPLING_FREQ_512 = 6, /**< RTCCLK / 512 */ + RTC_TAMPER_SAMPLING_FREQ_256 = 7, /**< RTCCLK / 256 */ } rtc_tamper_sampling_freq_t; /** * @brief Tamper filter time */ -typedef enum -{ - RTC_TAMPER_DURATION_1 = 0, /**< Duration 1 sampling */ - RTC_TAMPER_DURATION_2 = 1, /**< Duration 2 sampling */ - RTC_TAMPER_DURATION_4 = 2, /**< Duration 4 sampling */ - RTC_TAMPER_DURATION_8 = 3, /**< Duration 8 sampling */ +typedef enum { + RTC_TAMPER_DURATION_1 = 0, /**< Duration 1 sampling */ + RTC_TAMPER_DURATION_2 = 1, /**< Duration 2 sampling */ + RTC_TAMPER_DURATION_4 = 2, /**< Duration 4 sampling */ + RTC_TAMPER_DURATION_8 = 3, /**< Duration 8 sampling */ } rtc_tamper_duration_t; /** * @brief Tamper structure */ -typedef struct -{ - rtc_tamper_idx_t idx; /**< Index of tamper */ - rtc_tamper_trigger_t trig; /**< Trigger type */ - rtc_tamper_sampling_freq_t freq; /**< Sampling frequency */ - rtc_tamper_duration_t dur; /**< Filter time */ - type_func_t ts; /**< Enable/Disable trigger time stamp event */ +typedef struct { + rtc_tamper_idx_t idx; /**< Index of tamper */ + rtc_tamper_trigger_t trig; /**< Trigger type */ + rtc_tamper_sampling_freq_t freq; /**< Sampling frequency */ + rtc_tamper_duration_t dur; /**< Filter time */ + type_func_t ts; /**< Enable/Disable trigger time stamp event */ } rtc_tamper_t; /** * @brief Wake-up clock */ -typedef enum -{ - RTC_WAKEUP_CLOCK_DIV_16 = 0, /**< RTCCLK / 16 */ - RTC_WAKEUP_CLOCK_DIV_8 = 1, /**< RTCCLK / 8 */ - RTC_WAKEUP_CLOCK_DIV_4 = 2, /**< RTCCLK / 4 */ - RTC_WAKEUP_CLOCK_DIV_2 = 3, /**< RTCCLK / 2 */ - RTC_WAKEUP_CLOCK_1HZ = 4, /**< 1Hz */ - RTC_WAKEUP_CLOCK_1HZ_PULS = 6, /**< 1Hz and WUT + 65536 */ +typedef enum { + RTC_WAKEUP_CLOCK_DIV_16 = 0, /**< RTCCLK / 16 */ + RTC_WAKEUP_CLOCK_DIV_8 = 1, /**< RTCCLK / 8 */ + RTC_WAKEUP_CLOCK_DIV_4 = 2, /**< RTCCLK / 4 */ + RTC_WAKEUP_CLOCK_DIV_2 = 3, /**< RTCCLK / 2 */ + RTC_WAKEUP_CLOCK_1HZ = 4, /**< 1Hz */ + RTC_WAKEUP_CLOCK_1HZ_PULS = 6, /**< 1Hz and WUT + 65536 */ } rtc_wakeup_clock_t; /** * @brief RTC clock output type */ -typedef enum -{ - RTC_CLOCK_OUTPUT_32768 = 0, /**< 32768Hz */ - RTC_CLOCK_OUTPUT_1024 = 1, /**< 1024Hz */ - RTC_CLOCK_OUTPUT_32 = 2, /**< 32Hz */ - RTC_CLOCK_OUTPUT_1 = 3, /**< 1Hz */ - RTC_CLOCK_OUTPUT_CAL_1 = 4, /**< 1Hz after calibration */ - RTC_CLOCK_OUTPUT_EXA_1 = 5, /**< Exact 1Hz */ +typedef enum { + RTC_CLOCK_OUTPUT_32768 = 0, /**< 32768Hz */ + RTC_CLOCK_OUTPUT_1024 = 1, /**< 1024Hz */ + RTC_CLOCK_OUTPUT_32 = 2, /**< 32Hz */ + RTC_CLOCK_OUTPUT_1 = 3, /**< 1Hz */ + RTC_CLOCK_OUTPUT_CAL_1 = 4, /**< 1Hz after calibration */ + RTC_CLOCK_OUTPUT_EXA_1 = 5, /**< Exact 1Hz */ } rtc_clock_output_t; /** * @ Calibration frequency */ -typedef enum -{ - RTC_CALI_FREQ_10_SEC = 0, /**< Calibrate every 10 seconds */ - RTC_CALI_FREQ_20_SEC = 1, /**< Calibrate every 20 seconds */ - RTC_CALI_FREQ_1_MIN = 2, /**< Calibrate every 1 minute */ - RTC_CALI_FREQ_2_MIN = 3, /**< Calibrate every 2 minutes */ - RTC_CALI_FREQ_5_MIN = 4, /**< Calibrate every 5 minutes */ - RTC_CALI_FREQ_10_MIN = 5, /**< Calibrate every 10 minutes */ - RTC_CALI_FREQ_20_MIN = 6, /**< Calibrate every 20 minutes */ - RTC_CALI_FREQ_1_SEC = 7, /**< Calibrate every 1 second */ +typedef enum { + RTC_CALI_FREQ_10_SEC = 0, /**< Calibrate every 10 seconds */ + RTC_CALI_FREQ_20_SEC = 1, /**< Calibrate every 20 seconds */ + RTC_CALI_FREQ_1_MIN = 2, /**< Calibrate every 1 minute */ + RTC_CALI_FREQ_2_MIN = 3, /**< Calibrate every 2 minutes */ + RTC_CALI_FREQ_5_MIN = 4, /**< Calibrate every 5 minutes */ + RTC_CALI_FREQ_10_MIN = 5, /**< Calibrate every 10 minutes */ + RTC_CALI_FREQ_20_MIN = 6, /**< Calibrate every 20 minutes */ + RTC_CALI_FREQ_1_SEC = 7, /**< Calibrate every 1 second */ } rtc_cali_freq_t; /** * @brief Temperature compensate type */ -typedef enum -{ - RTC_CALI_TC_NONE = 0, /**< Temperature compensate disable */ - RTC_CALI_TC_AUTO_BY_HW = 1, /**< Temperature compensate by hardware */ - RTC_CALI_TC_AUTO_BY_SF = 2, /**< Temperature compensate by software */ - RTC_CALI_TC_AUTO_BY_HW_SF = 3, /**< Temperature compensate by hardware, trigger by software */ +typedef enum { + RTC_CALI_TC_NONE = 0, /**< Temperature compensate disable */ + RTC_CALI_TC_AUTO_BY_HW = 1, /**< Temperature compensate by hardware */ + RTC_CALI_TC_AUTO_BY_SF = 2, /**< Temperature compensate by software */ + RTC_CALI_TC_AUTO_BY_HW_SF = 3, /**< Temperature compensate by hardware, trigger by software */ } rtc_cali_tc_t; /** * @ Calculate frequency */ -typedef enum -{ - RTC_CALI_CALC_FREQ_10_SEC = 0, /**< Calculate every 10 seconds */ - RTC_CALI_CALC_FREQ_20_SEC = 1, /**< Calculate every 20 seconds */ - RTC_CALI_CALC_FREQ_1_MIN = 2, /**< Calculate every 1 minute */ - RTC_CALI_CALC_FREQ_2_MIN = 3, /**< Calculate every 2 minutes */ - RTC_CALI_CALC_FREQ_5_MIN = 4, /**< Calculate every 5 minutes */ - RTC_CALI_CALC_FREQ_10_MIN = 5, /**< Calculate every 10 minutes */ - RTC_CALI_CALC_FREQ_20_MIN = 6, /**< Calculate every 20 minutes */ - RTC_CALI_CALC_FREQ_1_HOUR = 7, /**< Calculate every 1 hour */ +typedef enum { + RTC_CALI_CALC_FREQ_10_SEC = 0, /**< Calculate every 10 seconds */ + RTC_CALI_CALC_FREQ_20_SEC = 1, /**< Calculate every 20 seconds */ + RTC_CALI_CALC_FREQ_1_MIN = 2, /**< Calculate every 1 minute */ + RTC_CALI_CALC_FREQ_2_MIN = 3, /**< Calculate every 2 minutes */ + RTC_CALI_CALC_FREQ_5_MIN = 4, /**< Calculate every 5 minutes */ + RTC_CALI_CALC_FREQ_10_MIN = 5, /**< Calculate every 10 minutes */ + RTC_CALI_CALC_FREQ_20_MIN = 6, /**< Calculate every 20 minutes */ + RTC_CALI_CALC_FREQ_1_HOUR = 7, /**< Calculate every 1 hour */ } rtc_cali_calc_freq_t; /** * @brief Calibration algorithm */ -typedef enum -{ - RTC_CALI_CALC_4 = 0, /**< 4-polynomial */ - RTC_CALI_CALC_2 = 1, /**< 2-parabola */ +typedef enum { + RTC_CALI_CALC_4 = 0, /**< 4-polynomial */ + RTC_CALI_CALC_2 = 1, /**< 2-parabola */ } rtc_cali_calc_t; /** * @brief Calibration structure */ -typedef struct -{ - rtc_cali_freq_t cali_freq; /**< calibrate frequency */ - rtc_cali_tc_t tc; /**< Temperature compensate type */ - rtc_cali_calc_freq_t calc_freq; /**< Calculate frequency */ - rtc_cali_calc_t calc; /**< algorithm */ - type_func_t acc; /**< Enable/Disable decimal accumulate */ +typedef struct { + rtc_cali_freq_t cali_freq; /**< calibrate frequency */ + rtc_cali_tc_t tc; /**< Temperature compensate type */ + rtc_cali_calc_freq_t calc_freq; /**< Calculate frequency */ + rtc_cali_calc_t calc; /**< algorithm */ + type_func_t acc; /**< Enable/Disable decimal accumulate */ } rtc_cali_t; /** * @brief Interrupt type */ -typedef enum -{ - RTC_IT_SEC = (1U << 0), /**< Second */ - RTC_IT_MIN = (1U << 1), /**< Minute */ - RTC_IT_HR = (1U << 2), /**< Hour */ - RTC_IT_DAY = (1U << 3), /**< Day */ - RTC_IT_MON = (1U << 4), /**< Month */ - RTC_IT_YR = (1U << 5), /**< Year */ - RTC_IT_ALMA = (1U << 8), /**< Alarm-A */ - RTC_IT_ALMB = (1U << 9), /**< Alarm-B */ - RTC_IT_TS = (1U << 10), /**< Time stamp */ - RTC_IT_TSOV = (1U << 11), /**< Time stamp overflow */ - RTC_IT_TP0 = (1U << 12), /**< Tamper-0 */ - RTC_IT_TP1 = (1U << 13), /**< Tamper-1 */ - RTC_IT_RSC = (1U << 16), /**< Synchronous complete */ - RTC_IT_SFC = (1U << 17), /**< Shift complete */ - RTC_IT_WU = (1U << 18), /**< Wake-up */ - RTC_IT_TCC = (1U << 24), /**< Temperature compensate complete */ - RTC_IT_TCE = (1U << 25), /**< Temperature compensate error */ +typedef enum { + RTC_IT_SEC = (1U << 0), /**< Second */ + RTC_IT_MIN = (1U << 1), /**< Minute */ + RTC_IT_HR = (1U << 2), /**< Hour */ + RTC_IT_DAY = (1U << 3), /**< Day */ + RTC_IT_MON = (1U << 4), /**< Month */ + RTC_IT_YR = (1U << 5), /**< Year */ + RTC_IT_ALMA = (1U << 8), /**< Alarm-A */ + RTC_IT_ALMB = (1U << 9), /**< Alarm-B */ + RTC_IT_TS = (1U << 10), /**< Time stamp */ + RTC_IT_TSOV = (1U << 11), /**< Time stamp overflow */ + RTC_IT_TP0 = (1U << 12), /**< Tamper-0 */ + RTC_IT_TP1 = (1U << 13), /**< Tamper-1 */ + RTC_IT_RSC = (1U << 16), /**< Synchronous complete */ + RTC_IT_SFC = (1U << 17), /**< Shift complete */ + RTC_IT_WU = (1U << 18), /**< Wake-up */ + RTC_IT_TCC = (1U << 24), /**< Temperature compensate complete */ + RTC_IT_TCE = (1U << 25), /**< Temperature compensate error */ } rtc_it_t; /** * @brief Interrupt flag */ -typedef enum -{ - RTC_IF_SEC = (1U << 0), /**< Second */ - RTC_IF_MIN = (1U << 1), /**< Minute */ - RTC_IF_HR = (1U << 2), /**< Hour */ - RTC_IF_DAY = (1U << 3), /**< Day */ - RTC_IF_MON = (1U << 4), /**< Month */ - RTC_IF_YR = (1U << 5), /**< Year */ - RTC_IF_ALMA = (1U << 8), /**< Alarm-A */ - RTC_IF_ALMB = (1U << 9), /**< Alarm-B */ - RTC_IF_TS = (1U << 10), /**< Time stamp */ - RTC_IF_TSOV = (1U << 11), /**< Time stamp overflow */ - RTC_IF_TP0 = (1U << 12), /**< Tamper-0 */ - RTC_IF_TP1 = (1U << 13), /**< Tamper-1 */ - RTC_IF_RSC = (1U << 16), /**< Synchronous complete */ - RTC_IF_SFC = (1U << 17), /**< Shift complete */ - RTC_IF_WU = (1U << 18), /**< Wake-up */ - RTC_IF_TCC = (1U << 24), /**< Temperature compensate complete */ - RTC_IF_TCE = (1U << 25), /**< Temperature compensate error */ +typedef enum { + RTC_IF_SEC = (1U << 0), /**< Second */ + RTC_IF_MIN = (1U << 1), /**< Minute */ + RTC_IF_HR = (1U << 2), /**< Hour */ + RTC_IF_DAY = (1U << 3), /**< Day */ + RTC_IF_MON = (1U << 4), /**< Month */ + RTC_IF_YR = (1U << 5), /**< Year */ + RTC_IF_ALMA = (1U << 8), /**< Alarm-A */ + RTC_IF_ALMB = (1U << 9), /**< Alarm-B */ + RTC_IF_TS = (1U << 10), /**< Time stamp */ + RTC_IF_TSOV = (1U << 11), /**< Time stamp overflow */ + RTC_IF_TP0 = (1U << 12), /**< Tamper-0 */ + RTC_IF_TP1 = (1U << 13), /**< Tamper-1 */ + RTC_IF_RSC = (1U << 16), /**< Synchronous complete */ + RTC_IF_SFC = (1U << 17), /**< Shift complete */ + RTC_IF_WU = (1U << 18), /**< Wake-up */ + RTC_IF_TCC = (1U << 24), /**< Temperature compensate complete */ + RTC_IF_TCE = (1U << 25), /**< Temperature compensate error */ } rtc_flag_t; /** * @} @@ -405,43 +375,43 @@ typedef enum /** @defgroup RTC_Public_Macro RTC Public Macros * @{ */ -#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55)) -#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0)) -#define RTC_BY_PASS_ENABLE() \ -do { \ - RTC_UNLOCK(); \ - SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ - RTC_LOCK(); \ +#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55)) +#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0)) +#define RTC_BY_PASS_ENABLE() \ +do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ + RTC_LOCK(); \ } while (0) -#define RTC_BY_PASS_DISABLE() \ -do { \ - RTC_UNLOCK(); \ - CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ - RTC_LOCK(); \ +#define RTC_BY_PASS_DISABLE() \ +do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ + RTC_LOCK(); \ } while (0) -#define RTC_SUMMER_TIME_ENABLE() \ -do { \ - RTC_UNLOCK(); \ - SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ - RTC_LOCK(); \ +#define RTC_SUMMER_TIME_ENABLE() \ +do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ + RTC_LOCK(); \ } while (0) -#define RTC_SUMMER_TIME_DISABLE() \ -do { \ - RTC_UNLOCK(); \ - CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ - RTC_LOCK(); \ +#define RTC_SUMMER_TIME_DISABLE() \ +do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ + RTC_LOCK(); \ } while (0) -#define RTC_WINTER_TIME_ENABLE() \ -do { \ - RTC_UNLOCK(); \ - SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ - RTC_LOCK(); \ +#define RTC_WINTER_TIME_ENABLE() \ +do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ + RTC_LOCK(); \ } while (0) -#define RTC_WINTER_TIME_DISABLE() \ -do { \ - RTC_UNLOCK(); \ - CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ - RTC_LOCK(); \ +#define RTC_WINTER_TIME_DISABLE() \ +do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ + RTC_LOCK(); \ } while (0) /** * @} @@ -450,35 +420,35 @@ do { \ /** @defgroup CAN_Private_Macros CAN Private Macros * @{ */ -#define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AA)) -#define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0)) -#define ALARM_MASK_ALL 0x40808080 -#define RTC_TIMEOUT_VALUE 100 +#define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AA)) +#define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0)) +#define ALARM_MASK_ALL 0x40808080 +#define RTC_TIMEOUT_VALUE 100 -#define IS_SHIFT_SUB_SS(x) ((x) < (1U << 15)) -#define IS_RTC_HOUR_FORMAT(x) (((x) == RTC_HOUR_FORMAT_24) || \ +#define IS_SHIFT_SUB_SS(x) ((x) < (1U << 15)) +#define IS_RTC_HOUR_FORMAT(x) (((x) == RTC_HOUR_FORMAT_24) || \ ((x) == RTC_HOUR_FORMAT_12)) -#define IS_RTC_OUTPUT_SEL(x) (((x) == RTC_OUTPUT_DISABLE) || \ +#define IS_RTC_OUTPUT_SEL(x) (((x) == RTC_OUTPUT_DISABLE) || \ ((x) == RTC_OUTPUT_ALARM_A) || \ ((x) == RTC_OUTPUT_ALARM_B) || \ ((x) == RTC_OUTPUT_WAKEUP)) -#define IS_RTC_OUTPUT_POLARITY(x) (((x) == RTC_OUTPUT_POLARITY_HIGH) || \ +#define IS_RTC_OUTPUT_POLARITY(x) (((x) == RTC_OUTPUT_POLARITY_HIGH) || \ ((x) == RTC_OUTPUT_POLARITY_LOW)) -#define IS_RTC_SOURCE_SEL(x) (((x) == RTC_SOURCE_LOSC) || \ +#define IS_RTC_SOURCE_SEL(x) (((x) == RTC_SOURCE_LOSC) || \ ((x) == RTC_SOURCE_LRC) || \ ((x) == RTC_SOURCE_HRC_DIV_1M ) || \ ((x) == RTC_SOURCE_HOSC_DIV_1M)) -#define IS_RTC_ALARM(x) (((x) == RTC_ALARM_A) || \ +#define IS_RTC_ALARM(x) (((x) == RTC_ALARM_A) || \ ((x) == RTC_ALARM_B)) -#define IS_RTC_ALARM_SEL(x) (((x) == RTC_SELECT_DAY) || \ +#define IS_RTC_ALARM_SEL(x) (((x) == RTC_SELECT_DAY) || \ ((x) == RTC_SELECT_WEEK)) -#define IS_RTC_ALARM_MASK(x) (((x) == RTC_ALARM_MASK_NONE) || \ +#define IS_RTC_ALARM_MASK(x) (((x) == RTC_ALARM_MASK_NONE) || \ ((x) == RTC_ALARM_MASK_WEEK_DAY) || \ ((x) == RTC_ALARM_MASK_HOUR) || \ ((x) == RTC_ALARM_MASK_MINUTE) || \ ((x) == RTC_ALARM_MASK_SECOND) || \ ((x) == RTC_ALARM_MASK_ALL)) -#define IS_RTC_ALARM_SS_MASK(x) (((x) == RTC_ALARM_SS_MASK_NONE) || \ +#define IS_RTC_ALARM_SS_MASK(x) (((x) == RTC_ALARM_SS_MASK_NONE) || \ ((x) == RTC_ALARM_SS_MASK_14_1) || \ ((x) == RTC_ALARM_SS_MASK_14_2) || \ ((x) == RTC_ALARM_SS_MASK_14_3) || \ @@ -494,17 +464,17 @@ do { \ ((x) == RTC_ALARM_SS_MASK_14_13) || \ ((x) == RTC_ALARM_SS_MASK_14) || \ ((x) == RTC_ALARM_SS_MASK_ALL)) -#define IS_RTC_TS_SIGNAL(x) (((x) == RTC_TS_SIGNAL_SEL_TAMPER0) || \ +#define IS_RTC_TS_SIGNAL(x) (((x) == RTC_TS_SIGNAL_SEL_TAMPER0) || \ ((x) == RTC_TS_SIGNAL_SEL_TAMPER1)) -#define IS_RTC_TS_STYLE(x) (((x) == RTC_TS_RISING_EDGE) || \ +#define IS_RTC_TS_STYLE(x) (((x) == RTC_TS_RISING_EDGE) || \ ((x) == RTC_TS_FALLING_EDGE)) -#define IS_RTC_FORMAT(x) (((x) == RTC_FORMAT_DEC) || \ +#define IS_RTC_FORMAT(x) (((x) == RTC_FORMAT_DEC) || \ ((x) == RTC_FORMAT_BCD)) -#define IS_RTC_TAMPER(x) (((x) == RTC_TAMPER_0) || \ +#define IS_RTC_TAMPER(x) (((x) == RTC_TAMPER_0) || \ ((x) == RTC_TAMPER_1)) -#define IS_RTC_TAMPER_TRIGGER(x) (((x) == RTC_TAMPER_TRIGGER_LOW) || \ +#define IS_RTC_TAMPER_TRIGGER(x) (((x) == RTC_TAMPER_TRIGGER_LOW) || \ ((x) == RTC_TAMPER_TRIGGER_HIGH)) -#define IS_RTC_TAMPER_SAMPLING_FREQ(x) (((x) == RTC_TAMPER_SAMPLING_FREQ_32768) || \ +#define IS_RTC_TAMPER_SAMPLING_FREQ(x) (((x) == RTC_TAMPER_SAMPLING_FREQ_32768) || \ ((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \ ((x) == RTC_TAMPER_SAMPLING_FREQ_8192) || \ ((x) == RTC_TAMPER_SAMPLING_FREQ_4096) || \ @@ -512,23 +482,23 @@ do { \ ((x) == RTC_TAMPER_SAMPLING_FREQ_1024) || \ ((x) == RTC_TAMPER_SAMPLING_FREQ_512) || \ ((x) == RTC_TAMPER_SAMPLING_FREQ_256)) -#define IS_RTC_TAMPER_DURATION(x) (((x) == RTC_TAMPER_DURATION_1) || \ +#define IS_RTC_TAMPER_DURATION(x) (((x) == RTC_TAMPER_DURATION_1) || \ ((x) == RTC_TAMPER_DURATION_2) || \ ((x) == RTC_TAMPER_DURATION_4) || \ ((x) == RTC_TAMPER_DURATION_8)) -#define IS_RTC_WAKEUP_CLOCK(x) (((x) == RTC_WAKEUP_CLOCK_DIV_16) || \ +#define IS_RTC_WAKEUP_CLOCK(x) (((x) == RTC_WAKEUP_CLOCK_DIV_16) || \ ((x) == RTC_WAKEUP_CLOCK_DIV_8) || \ ((x) == RTC_WAKEUP_CLOCK_DIV_4) || \ ((x) == RTC_WAKEUP_CLOCK_DIV_2) || \ ((x) == RTC_WAKEUP_CLOCK_1HZ) || \ ((x) == RTC_WAKEUP_CLOCK_1HZ_PULS)) -#define IS_RTC_CLOCK_OUTPUT(x) (((x) == RTC_CLOCK_OUTPUT_32768) || \ +#define IS_RTC_CLOCK_OUTPUT(x) (((x) == RTC_CLOCK_OUTPUT_32768) || \ ((x) == RTC_CLOCK_OUTPUT_1024) || \ ((x) == RTC_CLOCK_OUTPUT_32) || \ ((x) == RTC_CLOCK_OUTPUT_1) || \ ((x) == RTC_CLOCK_OUTPUT_CAL_1) || \ ((x) == RTC_CLOCK_OUTPUT_EXA_1)) -#define IS_RTC_CALI_FREQ(x) (((x) == RTC_CALI_FREQ_10_SEC) || \ +#define IS_RTC_CALI_FREQ(x) (((x) == RTC_CALI_FREQ_10_SEC) || \ ((x) == RTC_CALI_FREQ_20_SEC) || \ ((x) == RTC_CALI_FREQ_1_MIN) || \ ((x) == RTC_CALI_FREQ_2_MIN) || \ @@ -536,11 +506,11 @@ do { \ ((x) == RTC_CALI_FREQ_10_MIN) || \ ((x) == RTC_CALI_FREQ_20_MIN) || \ ((x) == RTC_CALI_FREQ_1_SEC)) -#define IS_RTC_CALI_TC(x) (((x) == RTC_CALI_TC_NONE) || \ +#define IS_RTC_CALI_TC(x) (((x) == RTC_CALI_TC_NONE) || \ ((x) == RTC_CALI_TC_AUTO_BY_HW) || \ ((x) == RTC_CALI_TC_AUTO_BY_SF) || \ ((x) == RTC_CALI_TC_AUTO_BY_HW_SF)) -#define IS_RTC_CALC_FREQ(x) (((x) == RTC_CALI_CALC_FREQ_10_SEC) || \ +#define IS_RTC_CALC_FREQ(x) (((x) == RTC_CALI_CALC_FREQ_10_SEC) || \ ((x) == RTC_CALI_CALC_FREQ_20_SEC) || \ ((x) == RTC_CALI_CALC_FREQ_1_MIN) || \ ((x) == RTC_CALI_CALC_FREQ_2_MIN) || \ @@ -548,9 +518,9 @@ do { \ ((x) == RTC_CALI_CALC_FREQ_10_MIN) || \ ((x) == RTC_CALI_CALC_FREQ_20_MIN) || \ ((x) == RTC_CALI_CALC_FREQ_1_HOUR)) -#define IS_RTC_CALI_CALC(x) (((x) == RTC_CALI_CALC_4) || \ +#define IS_RTC_CALI_CALC(x) (((x) == RTC_CALI_CALC_4) || \ ((x) == RTC_CALI_CALC_2)) -#define IS_RTC_IT(x) (((x) == RTC_IT_SEC) || \ +#define IS_RTC_IT(x) (((x) == RTC_IT_SEC) || \ ((x) == RTC_IT_MIN) || \ ((x) == RTC_IT_HR) || \ ((x) == RTC_IT_DAY) || \ @@ -567,7 +537,7 @@ do { \ ((x) == RTC_IT_WU) || \ ((x) == RTC_IT_TCC) || \ ((x) == RTC_IT_TCE)) -#define IS_RTC_IF(x) (((x) == RTC_IF_SEC) || \ +#define IS_RTC_IF(x) (((x) == RTC_IF_SEC) || \ ((x) == RTC_IF_MIN) || \ ((x) == RTC_IF_HR) || \ ((x) == RTC_IF_DAY) || \ @@ -584,12 +554,12 @@ do { \ ((x) == RTC_IF_WU) || \ ((x) == RTC_IF_TCC) || \ ((x) == RTC_IF_TCE)) -#define IS_RTC_SECOND(x) ((x) < 60) -#define IS_RTC_MINUTE(x) ((x) < 60) -#define IS_RTC_HOUR(x) ((x) < 24) -#define IS_RTC_DAY(x) (((x) > 0) && ((x) < 32)) -#define IS_RTC_MONTH(x) (((x) > 0) && ((x) < 13)) -#define IS_RTC_YEAR(x) ((x) < 100) +#define IS_RTC_SECOND(x) ((x) < 60) +#define IS_RTC_MINUTE(x) ((x) < 60) +#define IS_RTC_HOUR(x) ((x) < 24) +#define IS_RTC_DAY(x) (((x) > 0) && ((x) < 32)) +#define IS_RTC_MONTH(x) (((x) > 0) && ((x) < 13)) +#define IS_RTC_YEAR(x) ((x) < 100) /** * @} */ @@ -602,9 +572,9 @@ do { \ * @{ */ /* Initialization functions */ -void rtc_reset(void); -void rtc_init(rtc_init_t *init); -void rtc_source_selcet(rtc_source_sel_t sel); +void ald_rtc_reset(void); +void ald_rtc_init(rtc_init_t *init); +void ald_rtc_source_select(rtc_source_sel_t sel); /** * @} */ @@ -612,11 +582,11 @@ void rtc_source_selcet(rtc_source_sel_t sel); * @{ */ /* Time and date operation functions */ -ald_status_t rtc_set_time(rtc_time_t *time, rtc_format_t format); -ald_status_t rtc_set_date(rtc_date_t *date, rtc_format_t format); -void rtc_get_time(rtc_time_t *time, rtc_format_t format); -void rtc_get_date(rtc_date_t *date, rtc_format_t format); -int32_t rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format); +ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format); +ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format); +void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format); +void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format); +int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format); /** * @} */ @@ -624,8 +594,8 @@ int32_t rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t forma * @{ */ /* Alarm functions */ -void rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format); -void rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format); +void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format); +void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format); /** * @} */ @@ -633,9 +603,9 @@ void rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format); * @{ */ /* Time stamp functions */ -void rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style); -void rtc_cancel_time_stamp(void); -void rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format); +void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style); +void ald_rtc_cancel_time_stamp(void); +void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format); /** * @} */ @@ -643,8 +613,8 @@ void rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t f * @{ */ /* Tamper functions */ -void rtc_set_tamper(rtc_tamper_t *tamper); -void rtc_cancel_tamper(rtc_tamper_idx_t idx); +void ald_rtc_set_tamper(rtc_tamper_t *tamper); +void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx); /** * @} */ @@ -652,9 +622,9 @@ void rtc_cancel_tamper(rtc_tamper_idx_t idx); * @{ */ /* Wakeup functions */ -void rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value); -void rtc_cancel_wakeup(void); -uint16_t rtc_get_wakeup_timer_value(void); +void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value); +void ald_rtc_cancel_wakeup(void); +uint16_t ald_rtc_get_wakeup_timer_value(void); /** * @} */ @@ -662,8 +632,8 @@ uint16_t rtc_get_wakeup_timer_value(void); * @{ */ /* Clock output functions */ -ald_status_t rtc_set_clock_output(rtc_clock_output_t clock); -void rtc_cancel_clock_output(void); +ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock); +void ald_rtc_cancel_clock_output(void); /** * @} */ @@ -671,16 +641,16 @@ void rtc_cancel_clock_output(void); * @{ */ /* Control functions */ -void rtc_interrupt_config(rtc_it_t it, type_func_t state); -void rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state); -ald_status_t rtc_set_shift(type_func_t add_1s, uint16_t sub_ss); -void rtc_set_cali(rtc_cali_t *config); -void rtc_cancel_cali(void); -ald_status_t rtc_get_cali_status(void); -void rtc_write_temp(uint16_t temp); -it_status_t rtc_get_it_status(rtc_it_t it); -flag_status_t rtc_get_flag_status(rtc_flag_t flag); -void rtc_clear_flag_status(rtc_flag_t flag); +void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state); +void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state); +ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss); +void ald_rtc_set_cali(rtc_cali_t *config); +void ald_rtc_cancel_cali(void); +ald_status_t ald_rtc_get_cali_status(void); +void ald_rtc_write_temp(uint16_t temp); +it_status_t ald_rtc_get_it_status(rtc_it_t it); +flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag); +void ald_rtc_clear_flag_status(rtc_flag_t flag); /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h new file mode 100644 index 0000000000000000000000000000000000000000..1756f25f36e9f6759d1ae97798160d41302bd304 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_rtchw.h @@ -0,0 +1,145 @@ +/** + ****************************************************************************** + * @file ald_rtchw.h + * @brief Header file of RTCHW Module driver. + * + * @version V1.0 + * @date 16 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************* + */ + +#ifndef __ALD_RTCHW_H__ +#define __ALD_RTCHW_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_rtc.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup RTCHW + * @{ + */ + +/** @defgroup RTCHW_Public_Types RTCHW Public Types + * @{ + */ +/** + * @brief Hardware calibration algorithm + */ +typedef enum { + RTC_CALI_MODE_NORMAL = 0, /**< Normal mode */ + RTC_CALI_MODE_SLEEP = 1, /**< Low power mode */ +} rtc_hw_cali_mode_t; + +/** + * @brief the parameters table of rtc calibration + */ +typedef struct { + uint32_t MODE_CALI; /**< Calibration Mode */ + uint32_t RTC_CALCR; /**< CALCR */ + uint32_t RTC_TEMPBDR; /**< TEMPBDR */ + uint32_t TEMP_TBDR; /**< TBDR */ + uint32_t RTC_LTAXR; /**< LTAXR */ + uint32_t RTC_HTAXR; /**< HTAXR */ + uint32_t RTC_LTCAR; /**< LTCAR */ + uint32_t RTC_LTCBR; /**< LTCBR */ + uint32_t RTC_LTCCR; /**< LTCCR */ + uint32_t RTC_LTCDR; /**< LTCDR */ + uint32_t RTC_HTCAR; /**< HTCAR */ + uint32_t RTC_HTCBR; /**< HTCBR */ + uint32_t RTC_HTCCR; /**< HTCCR */ + uint32_t RTC_HTCDR; /**< HTCDR */ + uint32_t TEMP_LTGR; /**< LTGR */ + uint32_t TEMP_HTGR; /**< HTGR */ + uint32_t TEMP_CR; /**< CR */ + uint32_t rsv0; /**< Reserved */ + uint32_t RTC_LTCER; /**< LTCER */ + uint32_t RTC_HTCER; /**< HTCER */ + uint32_t TEMP_PEAK; /**< PEAK */ + uint32_t FREQ_PEAK; /**< PEAK */ + uint32_t TEMP_CALI; /**< CALI */ + uint32_t TEMP_CALI_AFTER; /**< AFTER */ + uint32_t TEMP_TCALBDR; /**< TCALBDR */ + uint32_t TEMP_TCALBDR_MINUS; /**< TCALBDR_MINUS */ + uint32_t rsv1[4]; /**< Reserved */ + uint32_t SUM; /**< SUM */ + uint32_t SUM_MINUS; /**< SUM_MINUS */ +} RTCINFO_TypeDef; + +/** + * @brief Hardware calibration structure + */ +typedef struct { + int16_t offset_rtc_bdr; /**< offset:0x00 */ + int16_t offset_temp_bdr; /**< offset:0x02 */ + int16_t offset_ltaxr; /**< offset:0x04 */ + int16_t offset_htaxr; /**< offset:0x06 */ + int16_t offset_ltcar; /**< offset:0x08 */ + int16_t offset_ltcbr; /**< offset:0x0A */ + int16_t offset_ltccr; /**< offset:0x0C */ + int16_t offset_ltcdr; /**< offset:0x0E */ + int16_t offset_htcar; /**< offset:0x10 */ + int16_t offset_htcbr; /**< offset:0x12 */ + int16_t offset_htccr; /**< offset:0x14 */ + int16_t offset_htcdr; /**< offset:0x16 */ + int16_t offset_ltgr; /**< offset:0x18 */ + int16_t offset_htgr; /**< offset:0x1A */ + int16_t offset_ltcer; /**< offset:0x1C */ + int16_t offset_htcer; /**< offset:0x1E */ + int16_t offset_temp_peak; /**< offset:0x20 */ + int16_t offset_freq_peak; /**< offset:0x22 */ + int16_t offset_tcalbdr; /**< offset:0x24 */ + int16_t crc; /**< offset:0x26 */ + int16_t rsv[8]; +} rtc_hw_cali_offset_t; +/** + * @} + */ +/** @defgroup RTCHW_Private_Macros RTCHW Private Macros + * @{ + */ +#ifndef RTC_LOCK +#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0)) +#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55)) +#endif + +#ifndef TSENSE_LOCK +#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0)) +#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669)) +#endif + +#define RTCINFO ((RTCINFO_TypeDef *)0x81000) +/** + * @} + */ + +/** @addtogroup RTCHW_Public_Functions + * @{ + */ +/* Calibration functions */ +void ald_rtc_hw_auto_cali(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..c3084576fff08cb06eb4fb8c0396f07051d3ab08 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_spi.h @@ -0,0 +1,428 @@ +/** + ********************************************************************************* + * + * @file ald_spi.c + * @brief Header file of SPI module driver. + * + * @version V1.0 + * @date 13 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_SPI_H__ +#define __ALD_SPI_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Public_Types SPI Public Types + * @{ + */ + +/** + * @brief clock phase + */ +typedef enum { + SPI_CPHA_FIRST = 0, /**< Transiting data in the first edge */ + SPI_CPHA_SECOND = 1, /**< Transiting data in the seconde edge */ +} spi_cpha_t; + +/** + * @brief clock polarity + */ +typedef enum { + SPI_CPOL_LOW = 0, /**< Polarity hold low when spi-bus is idle */ + SPI_CPOL_HIGH = 1, /**< Polarity hold high when spi-bus is idle */ +} spi_cpol_t; + +/** + * @brief master selection + */ +typedef enum { + SPI_MODE_SLAVER = 0, /**< Slave mode */ + SPI_MODE_MASTER = 1, /**< Master mode */ +} spi_mode_t; + +/** + * @brief baud rate control + */ +typedef enum { + SPI_BAUD_2 = 0, /**< fpclk/2 */ + SPI_BAUD_4 = 1, /**< fpclk/4 */ + SPI_BAUD_8 = 2, /**< fpclk/8 */ + SPI_BAUD_16 = 3, /**< fpclk/16 */ + SPI_BAUD_32 = 4, /**< fpclk/32 */ + SPI_BAUD_64 = 5, /**< fpclk/64 */ + SPI_BAUD_128 = 6, /**< fpclk/128 */ + SPI_BAUD_256 = 7, /**< fpclk/256 */ +} spi_baud_t; + +/** + * @brief frame format + */ +typedef enum { + SPI_FIRSTBIT_MSB = 0, /**< MSB transmitted first */ + SPI_FIRSTBIT_LSB = 1, /**< LSB transmitted first */ +} spi_firstbit_t; + +/** + * @brief data frame format + */ +typedef enum { + SPI_DATA_SIZE_8 = 0, /**< 8-bit data frame format is selected for transmission/reception */ + SPI_DATA_SIZE_16 = 1, /**< 16-bit data frame format is selected for transmission/reception */ +} spi_datasize_t; + +/** + * @brief SPI error status + */ +typedef enum { + SPI_ERROR_NONE = 0, /**< none */ + SPI_ERROR_MODF = 1, /**< mode fault */ + SPI_ERROR_CRC = 2, /**< crc error */ + SPI_ERROR_FRE = 4, /**< frame error */ + SPI_ERROR_RXOV = 8, /**< receive over error */ + SPI_ERROR_TXOV = 0x10, /**< dma error */ + SPI_ERROR_FLAG = 0x20, /**< interrupt flag error */ +} spi_error_t; + +/** + * @brief interrupt control + */ +typedef enum { + SPI_IT_TXE = (1U << 0), /**< Transmit fifo empty interrupt */ + SPI_IT_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt */ + SPI_IT_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt */ + SPI_IT_TXTH = (1U << 4), /**< Transmit fifo under threshold interrupt */ + SPI_IT_RXF = (1U << 9), /**< Receive fifo full interrupt */ + SPI_IT_RXOV = (1U << 10), /**< Receive fifo overflow interrupt */ + SPI_IT_RXUD = (1U << 11), /**< Receive fifo underflow interrupt */ + SPI_IT_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt */ + SPI_IT_CRCERR = (1U << 16), /**< Crc error interrupt */ + SPI_IT_MODF = (1U << 17), /**< Mode error interrupt */ + SPI_IT_FRE = (1U << 18), /**< Frame error interrupt */ +} spi_it_t; + +/** + * @brief interrupt flag + */ +typedef enum { + SPI_IF_TXE = (1U << 0), /**< Transmit fifo empty interrupt flag */ + SPI_IF_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt flag */ + SPI_IF_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt flag */ + SPI_IF_TXTH = (1U << 4), /**< Transmit fifo under threshold interrupt flag */ + SPI_IF_RXF = (1U << 9), /**< Receive fifo full interrupt flag */ + SPI_IF_RXOV = (1U << 10), /**< Receive fifo overflow interrupt flag */ + SPI_IF_RXUD = (1U << 11), /**< Receive fifo underflow interrupt flag */ + SPI_IF_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt flag */ + SPI_IF_CRCERR = (1U << 16), /**< Crc error interrupt flag */ + SPI_IF_MODF = (1U << 17), /**< Mode error interrupt flag */ + SPI_IF_FRE = (1U << 18), /**< Frame error interrupt flag */ +} spi_flag_t; + +/** + * @brief SPI state structures definition + */ +typedef enum { + SPI_STATE_RESET = 0x00, /**< Peripheral is not initialized */ + SPI_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + SPI_STATE_BUSY = 0x02, /**< an internal process is ongoing */ + SPI_STATE_BUSY_TX = 0x11, /**< transmit is ongoing */ + SPI_STATE_BUSY_RX = 0x21, /**< receive is ongoing */ + SPI_STATE_BUSY_TX_RX = 0x31, /**< transmit and receive are ongoing */ + SPI_STATE_TIMEOUT = 0x03, /**< Timeout state */ + SPI_STATE_ERROR = 0x04, /**< Error */ +} spi_state_t; + + +/** + * @brief SPI direction definition + */ +typedef enum { + SPI_DIRECTION_2LINES = 0, /**< 2 lines */ + SPI_DIRECTION_2LINES_RXONLY = 1, /**< 2 lines only rx */ + SPI_DIRECTION_1LINE = 2, /**< 1 line */ + SPI_DIRECTION_1LINE_RX = 3, /**< 1 line only rx */ +} spi_direction_t; + +/** + * @brief SPI dma request definition + */ +typedef enum { + SPI_DMA_REQ_TX = 0, /**< TX dma request */ + SPI_DMA_REQ_RX = 1, /**< RX dma request */ +} spi_dma_req_t; + +/** + * @brief SPI crc length definition + */ +typedef enum { + SPI_FRAME_MOTOROLA = 0, /**< SPI motorola mode */ + SPI_FRAME_TI = 1 /**< SPI TI mode */ +} spi_frame_t; + +/** + * @brief SPI status definition + */ +typedef enum { + SPI_STATUS_TXE = (1U << 0), /**< Transmit fifo empty status */ + SPI_STATUS_TXF = (1U << 1), /**< Transmit fifo full status */ + SPI_STATUS_TXOV = (1U << 2), /**< Transmit fifo overflow status */ + SPI_STATUS_TXUD = (1U << 3), /**< Transmit fifo underflow status */ + SPI_STATUS_TXTH = (1U << 4), /**< Transmit fifo under threshold status */ + SPI_STATUS_RXE = (1U << 8), /**< Receive fifo empty status */ + SPI_STATUS_RXF = (1U << 9), /**< Receive fifo full status */ + SPI_STATUS_RXOV = (1U << 10), /**< Receive fifo overflow status */ + SPI_STATUS_RXUD = (1U << 11), /**< Receive fifo underflow status */ + SPI_STATUS_RXTH = (1U << 12), /**< Receive fifo under threshold status */ + SPI_STATUS_BUSY = (1U << 15), /**< BUSY status */ +} spi_status_t; + +/** + * @brief SPI TXE/RXNE status definition + */ +typedef enum { + SPI_SR_TXE = 0, /**< SR.TXE set */ + SPI_SR_RXNE = 1, /**< SR.RXTH set */ + SPI_SR_TXE_RXNE = 2, /**< SR.TXE and SR.RXNE set */ +} spi_sr_status_t; + + +/** + * @brief SPI init structure definition + */ +typedef struct { + spi_mode_t mode; /**< SPI mode */ + spi_direction_t dir; /**< SPI direction */ + spi_datasize_t data_size; /**< SPI data size */ + spi_baud_t baud; /**< SPI baudrate prescaler */ + spi_cpha_t phase; /**< SPI clock phase */ + spi_cpol_t polarity; /**< SPI clock polarity */ + spi_firstbit_t first_bit; /**< SPI first bit */ + type_func_t ss_en; /**< SPI ssm enable or disable */ + type_func_t crc_calc; /**< SPI crc calculation */ + spi_frame_t frame; /**< SPI frame format */ + uint16_t crc_poly; /**< SPI crc polynomial */ +} spi_init_t; + +/** + * @brief SPI handle structure definition + */ +typedef struct spi_handle_s { + SPI_I2S_TypeDef *perh; /**< SPI registers base address */ + spi_init_t init; /**< SPI communication parameters */ + uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */ + uint16_t tx_size; /**< SPI Tx transfer size */ + uint16_t tx_count; /**< SPI Tx transfer counter */ + uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */ + uint16_t rx_size; /**< SPI Rx Transfer size */ + uint16_t rx_count; /**< SPI Rx Transfer Counter */ +#ifdef ALD_DMA + dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */ +#endif + lock_state_t lock; /**< Locking object */ + spi_state_t state; /**< SPI communication state */ + uint32_t err_code; /**< SPI error code */ + + void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */ + void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */ + void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */ +} spi_handle_t; +/** + * @} + */ + +/** @defgroup SPI_Public_Macros SPI Public Macros + * @{ + */ +#define SPI_RESET_HANDLE_STATE(x) ((x)->state = SPI_STATE_RESET) +#define SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS)) +#define SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS)) +#define SPI_CRC_RESET(x) \ +do { \ + CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ + SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ +} while (0) +#define SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) +#define SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) +#define SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) +#define SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) +#define SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) +#define SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) +#define SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) +#define SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) +#define SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) +#define SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) +/** + * @} + */ + +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ +#define IS_SPI(x) (((x) == SPI0) || \ + ((x) == SPI1) || \ + ((x) == SPI2)) +#define IS_SPI_CPHA(x) (((x) == SPI_CPHA_FIRST) || \ + ((x) == SPI_CPHA_SECOND)) +#define IS_SPI_CPOL(x) (((x) == SPI_CPOL_LOW) || \ + ((x) == SPI_CPOL_HIGH)) +#define IS_SPI_MODE(x) (((x) == SPI_MODE_SLAVER) || \ + ((x) == SPI_MODE_MASTER)) +#define IS_SPI_FIRBIT(x) (((x) == SPI_FIRSTBIT_MSB) || \ + ((x) == SPI_FIRSTBIT_LSB)) +#define IS_SPI_BAUD(x) (((x) == SPI_BAUD_2) || \ + ((x) == SPI_BAUD_4) || \ + ((x) == SPI_BAUD_8) || \ + ((x) == SPI_BAUD_16) || \ + ((x) == SPI_BAUD_32) || \ + ((x) == SPI_BAUD_64) || \ + ((x) == SPI_BAUD_128) || \ + ((x) == SPI_BAUD_256)) +#define IS_SPI_DATASIZE(x) (((x) == SPI_DATA_SIZE_8) || \ + ((x) == SPI_DATA_SIZE_16)) +#define IS_SPI_BIDOE(x) (((x) == SPI_BID_RX) || \ + ((x) == SPI_BID_TX)) +#define IS_SPI_BIDMODE(x) (((x) == SPI_BIDMODE_DUAL) || \ + ((x) == SPI_BIDMODE_SOLE)) +#define IS_SPI_DIRECTION(x) (((x) == SPI_DIRECTION_2LINES) || \ + ((x) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((x) == SPI_DIRECTION_1LINE) || \ + ((x) == SPI_DIRECTION_1LINE_RX)) +#define IS_SPI_DMA_REQ(x) (((x) == SPI_DMA_REQ_TX) || \ + ((x) == SPI_DMA_REQ_RX)) +#define IS_SPI_STATUS(x) (((x) == SPI_STATUS_TXE) || \ + ((x) == SPI_STATUS_TXF) || \ + ((x) == SPI_STATUS_TXOV) || \ + ((x) == SPI_STATUS_TXUD) || \ + ((x) == SPI_STATUS_TXTH) || \ + ((x) == SPI_STATUS_RXE) || \ + ((x) == SPI_STATUS_RXF) || \ + ((x) == SPI_STATUS_RXOV) || \ + ((x) == SPI_STATUS_RXUD) || \ + ((x) == SPI_STATUS_RXTH) || \ + ((x) == SPI_STATUS_BUSY)) +#define IS_SPI_IT(x) (((x) == SPI_IT_TXE) || \ + ((x) == SPI_IT_TXOV) || \ + ((x) == SPI_IT_TXUD) || \ + ((x) == SPI_IT_TXTH) || \ + ((x) == SPI_IT_RXF) || \ + ((x) == SPI_IT_RXOV) || \ + ((x) == SPI_IT_RXUD) || \ + ((x) == SPI_IT_RXTH) || \ + ((x) == SPI_IT_CRCERR) || \ + ((x) == SPI_IT_MODF) || \ + ((x) == SPI_IT_FRE)) +#define IS_SPI_IF(x) (((x) == SPI_IF_TXE) || \ + ((x) == SPI_IF_TXOV) || \ + ((x) == SPI_IF_TXUD) || \ + ((x) == SPI_IF_TXTH) || \ + ((x) == SPI_IF_RXF) || \ + ((x) == SPI_IF_RXOV) || \ + ((x) == SPI_IF_RXUD) || \ + ((x) == SPI_IF_RXTH) || \ + ((x) == SPI_IF_CRCERR) || \ + ((x) == SPI_IF_MODF) || \ + ((x) == SPI_IF_FRE)) +#define IS_SPI_FRAME(x) (((x) == SPI_FRAME_MOTOROLA) || \ + ((x) == SPI_FRAME_TI) ) +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions + * @{ + */ + +/** @addtogroup SPI_Public_Functions_Group1 + * @{ + */ + +ald_status_t ald_spi_init(spi_handle_t *hperh); +void ald_spi_reset(spi_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions_Group2 + * @{ + */ +int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data); +int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data); +uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh, int *status); +ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size); +#ifdef ALD_DMA +ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); +ald_status_t ald_spi_dma_pause(spi_handle_t *hperh); +ald_status_t ald_spi_dma_resume(spi_handle_t *hperh); +ald_status_t ald_spi_dma_stop(spi_handle_t *hperh); +#endif +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions_Group3 + * @{ + */ +void ald_spi_irq_handler(spi_handle_t *hperh); +void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state); +void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed); +void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state); +it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it); +flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status); +flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag); +void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag); +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions_Group4 + * @{ + */ +spi_state_t ald_spi_get_state(spi_handle_t *hperh); +uint32_t ald_spi_get_error(spi_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_sram.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_sram.h new file mode 100644 index 0000000000000000000000000000000000000000..2743b835354791d0963916935d14122fdb220533 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_sram.h @@ -0,0 +1,126 @@ +/** + ********************************************************************************* + * + * @file ald_sram.h + * @brief Header file of EBI_SRAM driver + * + * @version V1.0 + * @date 07 Dec 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_SRAM_H__ +#define __ALD_SRAM_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ald_ebi.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup SRAM + * @{ + */ + +/** @defgroup SRAM_Public_Types SRAM Public Types + * @{ + */ + +/** + * @brief ALD SRAM State structures definition + */ +typedef enum { + ALD_SRAM_STATE_RESET = 0x00U, /**< SRAM not yet initialized or disabled */ + ALD_SRAM_STATE_READY = 0x01U, /**< SRAM initialized and ready for use */ + ALD_SRAM_STATE_BUSY = 0x02U, /**< SRAM internal process is ongoing */ + ALD_SRAM_STATE_ERROR = 0x03U, /**< SRAM error state */ + ALD_SRAM_STATE_PROTECTED = 0x04U /**< SRAM peripheral NORSRAM device write protected */ +} ald_sram_state_t; + +/** + * @brief SRAM handle Structure definition + */ +typedef struct { + EBI_NOR_SRAM_TypeDef *instance; /**< Register base address */ + EBI_NOR_SRAM_EXTENDED_TypeDef *ext; /**< Extended mode register base address */ + ald_ebi_nor_sram_init_t init; /**< SRAM device control configuration parameters */ + lock_state_t lock; /**< SRAM locking object */ + __IO ald_sram_state_t state; /**< SRAM device access state */ +#ifdef ALD_DMA + dma_handle_t hdma; /**< SRAM DMA Handle parameters */ + void(*cplt_cbk)(void *arg); /**< DMA transmit completely callback function */ +#endif +} sram_handle_t; +/** + * @} + */ + +/** @addtogroup SRAM_Public_Functions + * @{ + */ +/** @addtogroup SRAM_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +ald_status_t ald_sram_init(sram_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing); +ald_status_t ald_sram_deinit(sram_handle_t *hperh); +/** + * @} + */ +/** @addtogroup SRAM_Public_Functions_Group2 + * @{ + */ +/* I/O operation functions */ +ald_status_t ald_sram_read_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size); +ald_status_t ald_sram_write_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size); +ald_status_t ald_sram_read_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size); +ald_status_t ald_sram_write_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size); +ald_status_t ald_sram_read_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size); +ald_status_t ald_sram_write_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size); +#ifdef ALD_DMA +ald_status_t ald_sram_read_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch); +ald_status_t ald_sram_write_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch); +#endif +/** + * @} + */ +/** @addtogroup SRAM_Public_Functions_Group3 + * @{ + */ +/* Control functions */ +ald_status_t ald_sram_write_enable(sram_handle_t *hperh); +ald_status_t ald_sram_write_disable(sram_handle_t *hperh); +/** + * @} + */ +/** @addtogroup SRAM_Public_Functions_Group4 + * @{ + */ +/* State functions */ +ald_sram_state_t ald_sram_get_state(sram_handle_t *hperh); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif /* __ALD_SRAM_H__ */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h new file mode 100644 index 0000000000000000000000000000000000000000..29890a9ae43df895ca3639232cb67723e656f640 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_syscfg.h @@ -0,0 +1,95 @@ +/** + ********************************************************************************* + * + * @file ald_syscfg.h + * @brief SYSCFG module driver. + * + * @version V1.0 + * @date 04 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_SYSCFG_H__ +#define __ALD_SYSCFG_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup SYSCFG SYSCFG + * @brief SYSCFG module driver + * @{ + */ + +/** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros + * @{ + */ +#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0) +#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996) +#define GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK) + +#define BOOT_FROM_BOOT_ROM() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) + +#define BOOT_FROM_BOOT_FLASH() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) + +#define BOOT_FROM_FLASH() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +/** + * @} + */ + + +/** @defgroup SYSCFG_Public_Functions SYSCFG Public Functions + * @{ + */ +__STATIC_INLINE__ void ald_vtor_config(uint32_t offset, type_func_t status) +{ + SCB->VTOR = status ? (offset & ~0x3F) : 0; + return; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h similarity index 32% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h rename to bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h index 6eaf44da44a485e87c788d546aff00cc54f77efe..650a33dcbeb14d78a1626d16c81050ab07c9e4b7 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_timer.h @@ -3,10 +3,10 @@ * * @file ald_timer.h * @brief TIMER module driver. - * This is the common part of the TIMER initialization + * This is the common part of the TIMER initialization * * @version V1.0 - * @date 06 Nov 2017 + * @date 06 Nov 2019 * @author AE Team * @note * @@ -19,7 +19,7 @@ #define __ALD_TIMER_H__ #ifdef __cplusplus -extern "C" { + extern "C" { #endif #include "utils.h" @@ -40,528 +40,489 @@ extern "C" { /** * @brief TIMER counter mode */ -typedef enum -{ - TIMER_CNT_MODE_UP = 0, /**< Counter mode up */ - TIMER_CNT_MODE_DOWN = 1, /**< Counter mode down */ - TIMER_CNT_MODE_CENTER1 = 2, /**< Counter mode center1 */ - TIMER_CNT_MODE_CENTER2 = 3, /**< Counter mode center2 */ - TIMER_CNT_MODE_CENTER3 = 4, /**< Counter mode center3 */ +typedef enum { + TIMER_CNT_MODE_UP = 0, /**< Counter mode up */ + TIMER_CNT_MODE_DOWN = 1, /**< Counter mode down */ + TIMER_CNT_MODE_CENTER1 = 2, /**< Counter mode center1 */ + TIMER_CNT_MODE_CENTER2 = 3, /**< Counter mode center2 */ + TIMER_CNT_MODE_CENTER3 = 4, /**< Counter mode center3 */ } timer_cnt_mode_t; /** * @brief TIMER clock division */ -typedef enum -{ - TIMER_CLOCK_DIV1 = 0, /**< No prescaler is used */ - TIMER_CLOCK_DIV2 = 1, /** Clock is divided by 2 */ - TIMER_CLOCK_DIV4 = 2, /** Clock is divided by 4 */ +typedef enum { + TIMER_CLOCK_DIV1 = 0, /**< No prescaler is used */ + TIMER_CLOCK_DIV2 = 1, /** Clock is divided by 2 */ + TIMER_CLOCK_DIV4 = 2, /** Clock is divided by 4 */ } timer_clock_division_t; /** * @brief TIMER output compare and PWM modes */ -typedef enum -{ - TIMER_OC_MODE_TIMERING = 0, /**< Output compare mode is timering */ - TIMER_OC_MODE_ACTIVE = 1, /**< Output compare mode is active */ - TIMER_OC_MODE_INACTIVE = 2, /**< Output compare mode is inactive */ - TIMER_OC_MODE_TOGGLE = 3, /**< Output compare mode is toggle */ - TIMER_OC_MODE_FORCE_INACTIVE = 4, /**< Output compare mode is force inactive */ - TIMER_OC_MODE_FORCE_ACTIVE = 5, /**< Output compare mode is force active */ - TIMER_OC_MODE_PWM1 = 6, /**< Output compare mode is pwm1 */ - TIMER_OC_MODE_PWM2 = 7, /**< Output compare mode is pwm2 */ +typedef enum { + TIMER_OC_MODE_TIMERING = 0, /**< Output compare mode is timering */ + TIMER_OC_MODE_ACTIVE = 1, /**< Output compare mode is active */ + TIMER_OC_MODE_INACTIVE = 2, /**< Output compare mode is inactive */ + TIMER_OC_MODE_TOGGLE = 3, /**< Output compare mode is toggle */ + TIMER_OC_MODE_FORCE_INACTIVE = 4, /**< Output compare mode is force inactive */ + TIMER_OC_MODE_FORCE_ACTIVE = 5, /**< Output compare mode is force active */ + TIMER_OC_MODE_PWM1 = 6, /**< Output compare mode is pwm1 */ + TIMER_OC_MODE_PWM2 = 7, /**< Output compare mode is pwm2 */ } timer_oc_mode_t; /** * @brief TIMER output compare polarity */ -typedef enum -{ - TIMER_OC_POLARITY_HIGH = 0, /**< Output compare polarity is high */ - TIMER_OC_POLARITY_LOW = 1, /**< Output compare polarity is low */ +typedef enum { + TIMER_OC_POLARITY_HIGH = 0, /**< Output compare polarity is high */ + TIMER_OC_POLARITY_LOW = 1, /**< Output compare polarity is low */ } timer_oc_polarity_t; /** * @brief TIMER complementary output compare polarity */ -typedef enum -{ - TIMER_OCN_POLARITY_HIGH = 0, /**< Complementary output compare polarity is high */ - TIMER_OCN_POLARITY_LOW = 1, /**< Complementary output compare polarity is low */ +typedef enum { + TIMER_OCN_POLARITY_HIGH = 0, /**< Complementary output compare polarity is high */ + TIMER_OCN_POLARITY_LOW = 1, /**< Complementary output compare polarity is low */ } timer_ocn_polarity_t; /** * @brief TIMER output compare idle state */ -typedef enum -{ - TIMER_OC_IDLE_RESET = 0, /**< Output compare idle state is reset */ - TIMER_OC_IDLE_SET = 1, /**< Output compare idle state is set */ +typedef enum { + TIMER_OC_IDLE_RESET = 0, /**< Output compare idle state is reset */ + TIMER_OC_IDLE_SET = 1, /**< Output compare idle state is set */ } timer_oc_idle_t; /** * @brief TIMER complementary output compare idle state */ -typedef enum -{ - TIMER_OCN_IDLE_RESET = 0, /**< Complementary output compare idle state is reset */ - TIMER_OCN_IDLE_SET = 1, /**< Complementary output compare idle state is set */ +typedef enum { + TIMER_OCN_IDLE_RESET = 0, /**< Complementary output compare idle state is reset */ + TIMER_OCN_IDLE_SET = 1, /**< Complementary output compare idle state is set */ } timer_ocn_idle_t; /** * @brief TIMER channel */ -typedef enum -{ - TIMER_CHANNEL_1 = 0, /**< Channel 1 */ - TIMER_CHANNEL_2 = 1, /**< Channel 2 */ - TIMER_CHANNEL_3 = 2, /**< Channel 3 */ - TIMER_CHANNEL_4 = 4, /**< Channel 4 */ - TIMER_CHANNEL_ALL = 0xF, /**< All channel */ +typedef enum { + TIMER_CHANNEL_1 = 0, /**< Channel 1 */ + TIMER_CHANNEL_2 = 1, /**< Channel 2 */ + TIMER_CHANNEL_3 = 2, /**< Channel 3 */ + TIMER_CHANNEL_4 = 4, /**< Channel 4 */ + TIMER_CHANNEL_ALL = 0xF, /**< All channel */ } timer_channel_t; /** * @brief TIMER one pulse mode */ -typedef enum -{ - TIMER_OP_MODE_REPEAT = 0, /**< Repetitive */ - TIMER_OP_MODE_SINGLE = 1, /**< single */ +typedef enum { + TIMER_OP_MODE_REPEAT = 0, /**< Repetitive */ + TIMER_OP_MODE_SINGLE = 1, /**< single */ } timer_op_mode_t; /** * @brief TIMER one pulse output channel */ -typedef enum -{ - TIMER_OP_OUTPUT_CHANNEL_1 = 0, /**< One pulse output channal 1 */ - TIMER_OP_OUTPUT_CHANNEL_2 = 1, /**< One pulse output channal 2 */ +typedef enum { + TIMER_OP_OUTPUT_CHANNEL_1 = 0, /**< One pulse output channal 1 */ + TIMER_OP_OUTPUT_CHANNEL_2 = 1, /**< One pulse output channal 2 */ } timer_op_output_channel_t; /** * @brief TIMER time base configuration structure definition */ -typedef struct -{ - uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */ - timer_cnt_mode_t mode; /**< Specifies the counter mode. */ - uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */ - timer_clock_division_t clk_div; /**< Specifies the clock division.*/ - uint32_t re_cnt; /**< Specifies the repetition counter value. */ +typedef struct { + uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */ + timer_cnt_mode_t mode; /**< Specifies the counter mode. */ + uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */ + timer_clock_division_t clk_div; /**< Specifies the clock division.*/ + uint32_t re_cnt; /**< Specifies the repetition counter value. */ } timer_base_init_t; /** * @brief TIMER output compare configuration structure definition */ -typedef struct -{ - timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */ - uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */ - timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */ - timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity. */ - type_func_t oc_fast_en; /**< Specifies the Fast mode state. */ - timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ - timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ +typedef struct { + timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */ + uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */ + timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */ + timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity. */ + type_func_t oc_fast_en; /**< Specifies the Fast mode state. */ + timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ + timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ } timer_oc_init_t; /** * @brief State structures definition */ -typedef enum -{ - TIMER_STATE_RESET = 0x00, /**< Peripheral not yet initialized or disabled */ - TIMER_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ - TIMER_STATE_BUSY = 0x02, /**< An internal process is ongoing */ - TIMER_STATE_TIMEREOUT = 0x03, /**< Timeout state */ - TIMER_STATE_ERROR = 0x04, /**< Reception process is ongoing */ +typedef enum { + TIMER_STATE_RESET = 0x00, /**< Peripheral not yet initialized or disabled */ + TIMER_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + TIMER_STATE_BUSY = 0x02, /**< An internal process is ongoing */ + TIMER_STATE_TIMEREOUT = 0x03, /**< Timeout state */ + TIMER_STATE_ERROR = 0x04, /**< Reception process is ongoing */ } timer_state_t; /** * @brief Active channel structures definition */ -typedef enum -{ - TIMER_ACTIVE_CHANNEL_1 = 0x01, /**< The active channel is 1 */ - TIMER_ACTIVE_CHANNEL_2 = 0x02, /**< The active channel is 2 */ - TIMER_ACTIVE_CHANNEL_3 = 0x04, /**< The active channel is 3 */ - TIMER_ACTIVE_CHANNEL_4 = 0x08, /**< The active channel is 4 */ - TIMER_ACTIVE_CHANNEL_CLEARED = 0x00, /**< All active channels cleared */ +typedef enum { + TIMER_ACTIVE_CHANNEL_1 = 0x01, /**< The active channel is 1 */ + TIMER_ACTIVE_CHANNEL_2 = 0x02, /**< The active channel is 2 */ + TIMER_ACTIVE_CHANNEL_3 = 0x04, /**< The active channel is 3 */ + TIMER_ACTIVE_CHANNEL_4 = 0x08, /**< The active channel is 4 */ + TIMER_ACTIVE_CHANNEL_CLEARED = 0x00, /**< All active channels cleared */ } timer_active_channel_t; /** * @brief TIMER time base handle structure definition */ -typedef struct timer_handle_s -{ - TIMER_TypeDef *perh; /**< Register base address */ - timer_base_init_t init; /**< TIMER Time Base required parameters */ - timer_active_channel_t ch; /**< Active channel */ - lock_state_t lock; /**< Locking object */ - timer_state_t state; /**< TIMER operation state */ - - void (*period_elapse_cbk)(struct timer_handle_s *arg); /**< Period elapse callback */ - void (*delay_elapse_cbk)(struct timer_handle_s *arg); /**< Delay_elapse callback */ - void (*capture_cbk)(struct timer_handle_s *arg); /**< Capture callback */ - void (*pwm_pulse_finish_cbk)(struct timer_handle_s *arg); /**< PWM_pulse_finish callback */ - void (*trigger_cbk)(struct timer_handle_s *arg); /**< Trigger callback */ - void (*break_cbk)(struct timer_handle_s *arg); /**< Break callback */ - void (*com_cbk)(struct timer_handle_s *arg); /**< commutation callback */ - void (*error_cbk)(struct timer_handle_s *arg); /**< Error callback */ +typedef struct timer_handle_s { + TIMER_TypeDef *perh; /**< Register base address */ + timer_base_init_t init; /**< TIMER Time Base required parameters */ + timer_active_channel_t ch; /**< Active channel */ + lock_state_t lock; /**< Locking object */ + timer_state_t state; /**< TIMER operation state */ + + void (*period_elapse_cbk)(struct timer_handle_s *arg); /**< Period elapse callback */ + void (*delay_elapse_cbk)(struct timer_handle_s *arg); /**< Delay_elapse callback */ + void (*capture_cbk)(struct timer_handle_s *arg); /**< Capture callback */ + void (*pwm_pulse_finish_cbk)(struct timer_handle_s *arg); /**< PWM_pulse_finish callback */ + void (*trigger_cbk)(struct timer_handle_s *arg); /**< Trigger callback */ + void (*break_cbk)(struct timer_handle_s *arg); /**< Break callback */ + void (*com_cbk)(struct timer_handle_s *arg); /**< commutation callback */ + void (*error_cbk)(struct timer_handle_s *arg); /**< Error callback */ } timer_handle_t; /** * @brief TIMER encoder mode */ -typedef enum -{ - TIMER_ENC_MODE_TI1 = 1, /**< encoder mode 1 */ - TIMER_ENC_MODE_TI2 = 2, /**< encoder mode 2 */ - TIMER_ENC_MODE_TI12 = 3, /**< encoder mode 3 */ +typedef enum { + TIMER_ENC_MODE_TI1 = 1, /**< encoder mode 1 */ + TIMER_ENC_MODE_TI2 = 2, /**< encoder mode 2 */ + TIMER_ENC_MODE_TI12 = 3, /**< encoder mode 3 */ } timer_encoder_mode_t; /** * @brief TIMER input capture polarity */ -typedef enum -{ - TIMER_IC_POLARITY_RISE = 0, /**< Input capture polarity rising */ - TIMER_IC_POLARITY_FALL = 1, /**< Input capture polarity falling */ - TIMER_IC_POLARITY_BOTH = 3, /**< Input capture polarity rising and falling */ +typedef enum { + TIMER_IC_POLARITY_RISE = 0, /**< Input capture polarity rising */ + TIMER_IC_POLARITY_FALL = 1, /**< Input capture polarity falling */ } timer_ic_polarity_t; /** *@brief TIMER input capture selection */ -typedef enum -{ - TIMER_IC_SEL_DIRECT = 1, /**< IC1 -- TI1 */ - TIMER_IC_SEL_INDIRECT = 2, /**< IC1 -- TI2 */ - TIMER_IC_SEL_TRC = 3, /**< IC1 -- TRC */ +typedef enum { + TIMER_IC_SEL_DIRECT = 1, /**< IC1 -- TI1 */ + TIMER_IC_SEL_INDIRECT = 2, /**< IC1 -- TI2 */ + TIMER_IC_SEL_TRC = 3, /**< IC1 -- TRC */ } timer_ic_select_t; /** * @brief TIMER input capture prescaler */ -typedef enum -{ - TIMER_IC_PSC_DIV1 = 0, /**< Capture performed once every 1 events */ - TIMER_IC_PSC_DIV2 = 1, /**< Capture performed once every 2 events */ - TIMER_IC_PSC_DIV4 = 2, /**< Capture performed once every 4 events */ - TIMER_IC_PSC_DIV8 = 3, /**< Capture performed once every 4 events */ +typedef enum { + TIMER_IC_PSC_DIV1 = 0, /**< Capture performed once every 1 events */ + TIMER_IC_PSC_DIV2 = 1, /**< Capture performed once every 2 events */ + TIMER_IC_PSC_DIV4 = 2, /**< Capture performed once every 4 events */ + TIMER_IC_PSC_DIV8 = 3, /**< Capture performed once every 4 events */ } timer_ic_prescaler_t; /** * @brief TIMER encoder configuration structure definition */ -typedef struct -{ - timer_encoder_mode_t mode; /**< Specifies the encoder mode */ - timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t ic1_sel; /**< Specifies the input */ - timer_ic_prescaler_t ic1_psc; /**< Specifies the Input Capture Prescaler */ - uint32_t ic1_filter; /**< Specifies the input capture filter */ - timer_ic_polarity_t ic2_polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t ic2_sel; /**< Specifies the input */ - timer_ic_prescaler_t ic2_psc; /**< Specifies the Input Capture Prescaler */ - uint32_t ic2_filter; /**< Specifies the input capture filter */ +typedef struct { + timer_encoder_mode_t mode; /**< Specifies the encoder mode */ + timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t ic1_sel; /**< Specifies the input */ + timer_ic_prescaler_t ic1_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic1_filter; /**< Specifies the input capture filter */ + timer_ic_polarity_t ic2_polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t ic2_sel; /**< Specifies the input */ + timer_ic_prescaler_t ic2_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic2_filter; /**< Specifies the input capture filter */ } timer_encoder_init_t; /** * @brief TIMER input capture configuration structure definition */ -typedef struct -{ - timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t sel; /**< Specifies the input */ - timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ - uint32_t filter; /**< Specifies the input capture filter */ +typedef struct { + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t sel; /**< Specifies the input */ + timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ + uint32_t filter; /**< Specifies the input capture filter */ } timer_ic_init_t; /** * @brief TIMER one pulse mode configuration structure definition */ -typedef struct -{ - timer_oc_mode_t mode; /**< Specifies the TIMER mode */ - uint16_t pulse; /**< Specifies the pulse value */ - timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity */ - timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity */ - timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ - timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ - timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ - timer_ic_select_t sel; /**< Specifies the input */ - uint32_t filter; /**< Specifies the input capture filter */ +typedef struct { + timer_oc_mode_t mode; /**< Specifies the TIMER mode */ + uint16_t pulse; /**< Specifies the pulse value */ + timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity */ + timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity */ + timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t sel; /**< Specifies the input */ + uint32_t filter; /**< Specifies the input capture filter */ } timer_one_pulse_init_t; /** @brief TIMER clear input source */ -typedef enum -{ - TIMER_INPUT_NONE = 0, /**< Clear input none */ - TIMER_INPUT_ETR = 1, /**< Clear input etr */ +typedef enum { + TIMER_INPUT_NONE = 0, /**< Clear input none */ + TIMER_INPUT_ETR = 1, /**< Clear input etr */ } timer_clear_input_source_t; /** @brief TIMER clear input polarity */ -typedef enum -{ - TIMER_POLARITY_NO_INV = 0, /**< Polarity for ETRx pin */ - TIMER_POLARITY_INV = 1, /**< Polarity for ETRx pin */ +typedef enum { + TIMER_POLARITY_NO_INV = 0, /**< Polarity for ETRx pin */ + TIMER_POLARITY_INV = 1, /**< Polarity for ETRx pin */ } timer_clear_input_polarity_t; /** @brief TIMER clear input polarity */ -typedef enum -{ - TIMER_ETR_PSC_DIV1 = 0, /**< No prescaler is used */ - TIMER_ETR_PSC_DIV2 = 1, /**< ETR input source is divided by 2 */ - TIMER_ETR_PSC_DIV4 = 2, /**< ETR input source is divided by 4 */ - TIMER_ETR_PSC_DIV8 = 3, /**< ETR input source is divided by 8 */ +typedef enum { + TIMER_ETR_PSC_DIV1 = 0, /**< No prescaler is used */ + TIMER_ETR_PSC_DIV2 = 1, /**< ETR input source is divided by 2 */ + TIMER_ETR_PSC_DIV4 = 2, /**< ETR input source is divided by 4 */ + TIMER_ETR_PSC_DIV8 = 3, /**< ETR input source is divided by 8 */ } timer_etr_psc_t; -/** +/** @brief TIMER CHnREF Clear Select + */ +typedef enum { + TIMER_CHNREF_CLR_CMP_IN = 0, /**< Comparator CMP_IN */ + TIMER_CHNREF_CLR_ETF = 1, /**< External Trigger Signal ETF */ +}timer_chnref_clr_sel_t;/** * @brief TIMER clear input configuration handle structure definition */ -typedef struct -{ - type_func_t state; /**< TIMER clear Input state */ - timer_clear_input_source_t source; /**< TIMER clear Input sources */ - timer_clear_input_polarity_t polarity; /**< TIMER Clear Input polarity */ - timer_etr_psc_t psc; /**< TIMER Clear Input prescaler */ - uint32_t filter; /**< TIMER Clear Input filter */ +typedef struct { + type_func_t state; /**< TIMER clear Input state */ + timer_clear_input_source_t source; /**< TIMER clear Input sources */ + timer_clear_input_polarity_t polarity; /**< TIMER Clear Input polarity */ + timer_etr_psc_t psc; /**< TIMER Clear Input prescaler */ + timer_chnref_clr_sel_t clrsel; /**state = TIMER_STATE_RESET) +#define TIMER_RESET_HANDLE_STATE(hperh) ((hperh)->state = TIMER_STATE_RESET) /** * @brief Enable the TIMER peripheral. */ -#define TIMER_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK)) +#define TIMER_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK)) /** * @brief Enable the TIMER main output. */ -#define TIMER_MOE_ENABLE(hperh) (SET_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK)) +#define TIMER_MOE_ENABLE(hperh) (SET_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK)) /** * @brief Disable the TIMER peripheral. */ #define TIMER_DISABLE(hperh) \ do { \ - if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ - && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ - CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \ + if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \ } while (0) /** @@ -603,47 +564,47 @@ do { \ * @note The Main Output Enable of a timer instance is disabled only if * all the CCx and CCxN channels have been disabled */ -#define TIMER_MOE_DISABLE(hperh) \ +#define TIMER_MOE_DISABLE(hperh) \ do { \ - if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ - && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ - CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \ + if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \ } while (0) /** * @brief Sets the TIMER autoreload register value on runtime without calling * another time any Init function. */ -#define TIMER_SET_AUTORELOAD(handle, AUTORELOAD) \ -do { \ - (handle)->perh->AR = (AUTORELOAD); \ - (handle)->init.period = (AUTORELOAD); \ +#define TIMER_SET_AUTORELOAD(handle, AUTORELOAD) \ +do { \ + (handle)->perh->AR = (AUTORELOAD); \ + (handle)->init.period = (AUTORELOAD); \ } while (0) /** * @brief Gets the TIMER autoreload register value on runtime */ -#define TIMER_GET_AUTORELOAD(handle) ((handle)->perh->AR) +#define TIMER_GET_AUTORELOAD(handle) ((handle)->perh->AR) /** * @brief Gets the TIMER count register value on runtime */ -#define TIMER_GET_CNT(handle) ((handle)->perh->COUNT) +#define TIMER_GET_CNT(handle) ((handle)->perh->COUNT) /** * @brief Gets the TIMER count direction value on runtime */ -#define TIMER_GET_DIR(handle) (READ_BITS((handle)->perh->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS)) +#define TIMER_GET_DIR(handle) (READ_BITS((handle)->perh->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS)) /** * @brief CCx DMA request sent when CCx event occurs */ -#define TIMER_CCx_DMA_REQ_CCx(handle) (CLEAR_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) +#define TIMER_CCx_DMA_REQ_CCx(handle) (CLEAR_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) /** * @brief CCx DMA request sent when update event occurs */ -#define TIMER_CCx_DMA_REQ_UPDATE(handle) (SET_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) +#define TIMER_CCx_DMA_REQ_UPDATE(handle) (SET_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) /** * @brief Enable channel @@ -654,7 +615,7 @@ do { \ * TIMER_CHANNEL_3 * TIMER_CHANNEL_4 */ -#define TIMER_CCx_ENABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ +#define TIMER_CCx_ENABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ (SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2)))))) /** @@ -666,7 +627,7 @@ do { \ * TIMER_CHANNEL_3 * TIMER_CHANNEL_4 */ -#define TIMER_CCx_DISABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ +#define TIMER_CCx_DISABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ (CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2)))) /** @@ -677,7 +638,7 @@ do { \ * TIMER_CHANNEL_2 * TIMER_CHANNEL_3 */ -#define TIMER_CCxN_ENABLE(handle, ch) ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2))) +#define TIMER_CCxN_ENABLE(handle, ch) ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2))) /** * @brief Disable complementary channel @@ -687,7 +648,7 @@ do { \ * TIMER_CHANNEL_2 * TIMER_CHANNEL_3 */ -#define TIMER_CCxN_DISABLE(handle, ch) ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2))) +#define TIMER_CCxN_DISABLE(handle, ch) ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2))) /** * @} */ @@ -695,78 +656,200 @@ do { \ /** @defgroup TIMER_Private_Macros TIMER Private Macros * @{ */ -#define IS_TIMER_INSTANCE(x) (((x) == TIMER0) || \ - ((x) == TIMER1) || \ - ((x) == TIMER2) || \ - ((x) == TIMER3) || \ - ((x) == TIMER4) || \ - ((x) == TIMER5) || \ - ((x) == TIMER6) || \ - ((x) == TIMER7)) -#define IS_ADTIMER_INSTANCE(x) ((x) == TIMER0) -#define IS_TIMER_XOR_INSTANCE(x) (((x) == TIMER0) || ((x) == TIMER6)) -#define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == TIMER0) || \ - ((x) == TIMER2) || \ - ((x) == TIMER3)) -#define IS_TIMER_CC2_INSTANCE(x) (((x) == TIMER0) || \ - ((x) == TIMER2) || \ - ((x) == TIMER3) || \ - ((x) == TIMER6)) -#define IS_TIMER_CC4_INSTANCE(x) (((x) == TIMER0) || \ - ((x) == TIMER6)) -#define IS_TIMER_BREAK_INSTANCE(x) (((x) == TIMER0) || \ - ((x) == TIMER2) || \ - ((x) == TIMER3)) -#define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == TIMER0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == TIMER2) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == TIMER3) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == TIMER6) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2)))) -#define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == TIMER0) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4))) || \ - (((x) == TIMER2) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == TIMER3) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2))) || \ - (((x) == TIMER6) && \ - (((y) == TIMER_CHANNEL_1) || \ - ((y) == TIMER_CHANNEL_2) || \ - ((y) == TIMER_CHANNEL_3) || \ - ((y) == TIMER_CHANNEL_4)))) -#define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == TIMER0) || \ - ((x) == TIMER2) || \ - ((x) == TIMER3)) && \ + +#if defined(ES32F36xx) +#define IS_TIMER_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == AD16C4T1) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1) || \ + ((x) == BS16T0) || \ + ((x) == BS16T1) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C4T1)) +#define IS_ADTIMER_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == AD16C4T1)) +#define IS_TIMER_XOR_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == AD16C4T1) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T0) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1)) +#define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == AD16C4T1) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T0) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1)) +#define IS_TIMER_CC2_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == AD16C4T1) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1)) +#define IS_TIMER_CC4_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == AD16C4T1) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1)) +#define IS_TIMER_BREAK_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == AD16C4T1)) +#define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == AD16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP32C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP32C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == AD16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2)))) +#define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == AD16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == AD16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP32C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP32C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4)))) +#define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == AD16C4T0) || \ + ((x) == AD16C4T1)) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) +#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == AD16C4T1)) +#define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) + +#endif + +#if defined(ES32F39xx) || defined(ES32F336x) +#define IS_TIMER_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1) || \ + ((x) == BS16T0) || \ + ((x) == BS16T1) || \ + ((x) == GP16C4T2) || \ + ((x) == GP16C4T3)) +#define IS_TIMER_XOR_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T2) || \ + ((x) == GP16C4T3) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1)) +#define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP32C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T2) || \ + ((x) == GP16C4T3) || \ + ((x) == GP32C4T1)) +#define IS_TIMER_CC2_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1) || \ + ((x) == GP16C4T2) || \ + ((x) == GP16C4T2) || \ + ((x) == GP16C4T3)) +#define IS_TIMER_CC4_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T2) || \ + ((x) == GP16C4T3) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1)) +#define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == GP16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP32C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP32C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T3) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T2) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2)))) +#define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == GP16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP32C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP32C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T2) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4)))) + +#define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == NULL) || \ + ((x) == NULL)) && \ (((y) == TIMER_CHANNEL_1) || \ ((y) == TIMER_CHANNEL_2) || \ ((y) == TIMER_CHANNEL_3) || \ ((y) == TIMER_CHANNEL_4))) -#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == TIMER0) || \ - ((x) == TIMER2) || \ - ((x) == TIMER3)) -#define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) -#define IS_TIMER_COUNTER_MODE(x) (((x) == TIMER_CNT_MODE_UP) || \ + +#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == NULL) || \ + ((x) == NULL)) + +#define IS_TIMER_BREAK_INSTANCE(x) (((x) == NULL) || \ + ((x) == NULL)) + +#define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) + +#endif + +#define IS_TIMER_COUNTER_MODE(x) (((x) == TIMER_CNT_MODE_UP) || \ ((x) == TIMER_CNT_MODE_DOWN) || \ ((x) == TIMER_CNT_MODE_CENTER1) || \ ((x) == TIMER_CNT_MODE_CENTER2) || \ ((x) == TIMER_CNT_MODE_CENTER3)) -#define IS_TIMER_CLOCK_DIVISION(x) (((x) == TIMER_CLOCK_DIV1) || \ +#define IS_TIMER_CLOCK_DIVISION(x) (((x) == TIMER_CLOCK_DIV1) || \ ((x) == TIMER_CLOCK_DIV2) || \ ((x) == TIMER_CLOCK_DIV4)) -#define IS_TIMER_PWM_MODE(x) (((x) == TIMER_OC_MODE_PWM1) || \ +#define IS_TIMER_PWM_MODE(x) (((x) == TIMER_OC_MODE_PWM1) || \ ((x) == TIMER_OC_MODE_PWM2)) -#define IS_TIMER_OC_MODE(x) (((x) == TIMER_OC_MODE_TIMERING) || \ +#define IS_TIMER_OC_MODE(x) (((x) == TIMER_OC_MODE_TIMERING) || \ ((x) == TIMER_OC_MODE_ACTIVE) || \ ((x) == TIMER_OC_MODE_INACTIVE) || \ ((x) == TIMER_OC_MODE_TOGGLE) || \ @@ -774,48 +857,49 @@ do { \ ((x) == TIMER_OC_MODE_FORCE_INACTIVE) || \ ((x) == TIMER_OC_MODE_PWM1) || \ ((x) == TIMER_OC_MODE_PWM2)) -#define IS_TIMER_OC_POLARITY(x) (((x) == TIMER_OC_POLARITY_HIGH) || \ +#define IS_TIMER_OC_POLARITY(x) (((x) == TIMER_OC_POLARITY_HIGH) || \ ((x) == TIMER_OC_POLARITY_LOW)) -#define IS_TIMER_OCN_POLARITY(x) (((x) == TIMER_OCN_POLARITY_HIGH) || \ +#define IS_TIMER_OCN_POLARITY(x) (((x) == TIMER_OCN_POLARITY_HIGH) || \ ((x) == TIMER_OCN_POLARITY_LOW)) -#define IS_TIMER_OCIDLE_STATE(x) (((x) == TIMER_OC_IDLE_RESET) || \ +#define IS_TIMER_OCIDLE_STATE(x) (((x) == TIMER_OC_IDLE_RESET) || \ ((x) == TIMER_OC_IDLE_SET)) -#define IS_TIMER_OCNIDLE_STATE(x) (((x) == TIMER_OCN_IDLE_RESET) || \ +#define IS_TIMER_OCNIDLE_STATE(x) (((x) == TIMER_OCN_IDLE_RESET) || \ ((x) == TIMER_OCN_IDLE_SET)) -#define IS_TIMER_CHANNELS(x) (((x) == TIMER_CHANNEL_1) || \ +#define IS_TIMER_CHANNELS(x) (((x) == TIMER_CHANNEL_1) || \ ((x) == TIMER_CHANNEL_2) || \ ((x) == TIMER_CHANNEL_3) || \ ((x) == TIMER_CHANNEL_4) || \ ((x) == TIMER_CHANNEL_ALL)) -#define IS_TIMER_OP_MODE(x) (((x) == TIMER_OP_MODE_REPEAT) || \ +#define IS_TIMER_OP_MODE(x) (((x) == TIMER_OP_MODE_REPEAT) || \ ((x) == TIMER_OP_MODE_SINGLE)) -#define IS_TIMER_OP_OUTPUT_CH(x) (((x) == TIMER_OP_OUTPUT_CHANNEL_1) || \ +#define IS_TIMER_OP_OUTPUT_CH(x) (((x) == TIMER_OP_OUTPUT_CHANNEL_1) || \ ((x) == TIMER_OP_OUTPUT_CHANNEL_2)) -#define IS_TIMER_ENCODER_MODE(x) (((x) == TIMER_ENC_MODE_TI1) || \ +#define IS_TIMER_ENCODER_MODE(x) (((x) == TIMER_ENC_MODE_TI1) || \ ((x) == TIMER_ENC_MODE_TI2) || \ ((x) == TIMER_ENC_MODE_TI12)) -#define IS_TIMER_IC_POLARITY(x) (((x) == TIMER_IC_POLARITY_RISE) || \ - ((x) == TIMER_IC_POLARITY_FALL) || \ - ((x) == TIMER_IC_POLARITY_BOTH)) -#define IS_TIMER_IC_SELECT(x) (((x) == TIMER_IC_SEL_DIRECT) || \ +#define IS_TIMER_IC_POLARITY(x) (((x) == TIMER_IC_POLARITY_RISE) || \ + ((x) == TIMER_IC_POLARITY_FALL)) +#define IS_TIMER_IC_SELECT(x) (((x) == TIMER_IC_SEL_DIRECT) || \ ((x) == TIMER_IC_SEL_INDIRECT) || \ ((x) == TIMER_IC_SEL_TRC)) -#define IS_TIMER_IC_PSC(x) (((x) == TIMER_IC_PSC_DIV1) || \ +#define IS_TIMER_IC_PSC(x) (((x) == TIMER_IC_PSC_DIV1) || \ ((x) == TIMER_IC_PSC_DIV2) || \ ((x) == TIMER_IC_PSC_DIV4) || \ ((x) == TIMER_IC_PSC_DIV8)) -#define IS_TIMER_IC_FILTER(x) ((x) <= 0xF) -#define IS_TIMER_DEAD_TIMERE(x) ((x) <= 0xFF) -#define IS_TIMER_CLEAR_INPUT_SOURCE(x) (((x) == TIMER_INPUT_NONE) || \ +#define IS_TIMER_IC_FILTER(x) ((x) <= 0xF) +#define IS_TIMER_DEAD_TIMERE(x) ((x) <= 0xFF) +#define IS_TIMER_CLEAR_INPUT_SOURCE(x) (((x) == TIMER_INPUT_NONE) || \ ((x) == TIMER_INPUT_ETR)) -#define IS_TIMER_CLEAR_INPUT_POLARITY(x) (((x) == TIMER_POLARITY_NO_INV) || \ +#define IS_TIMER_CLEAR_INPUT_POLARITY(x) (((x) == TIMER_POLARITY_NO_INV) || \ ((x) == TIMER_POLARITY_INV)) -#define IS_TIMER_ETR_PSC(x) (((x) == TIMER_ETR_PSC_DIV1) || \ +#define IS_TIMER_ETR_PSC(x) (((x) == TIMER_ETR_PSC_DIV1) || \ ((x) == TIMER_ETR_PSC_DIV2) || \ ((x) == TIMER_ETR_PSC_DIV4) || \ ((x) == TIMER_ETR_PSC_DIV8)) -#define IS_TIMER_CLOCK_SOURCE(x) (((x) == TIMER_SRC_ETRMODE2) || \ - ((x) == TIMER_SRC_INTER) || \ +#define IS_TIMER_CHNREF_CLEAR(X) (((X) == TIMER_CHNREF_CLR_CMP_IN) || \ + ((X) == TIMER_CHNREF_CLR_ETF)) +#define IS_TIMER_CLOCK_SOURCE(x) (((x) == TIMER_SRC_ETRMODE2) || \ + ((x) == TIMER_SRC_INTER) || \ ((x) == TIMER_SRC_ITR0) || \ ((x) == TIMER_SRC_ITR1) || \ ((x) == TIMER_SRC_ITR2) || \ @@ -824,12 +908,12 @@ do { \ ((x) == TIMER_SRC_TI1) || \ ((x) == TIMER_SRC_TI2) || \ ((x) == TIMER_SRC_ETRMODE1)) -#define IS_TIMER_CLOCK_POLARITY(x) (((x) == TIMER_CLK_POLARITY_INV) || \ +#define IS_TIMER_CLOCK_POLARITY(x) (((x) == TIMER_CLK_POLARITY_INV) || \ ((x) == TIMER_CLK_POLARITY_NO_INV) || \ - ((x) == TIMER_CLK_POLARITY_RISE) || \ - ((x) == TIMER_CLK_POLARITY_FALL) || \ + ((x) == TIMER_CLK_POLARITY_RISE) || \ + ((x) == TIMER_CLK_POLARITY_FALL) || \ ((x) == TIMER_CLK_POLARITY_BOTH)) -#define IS_TIMER_SLAVE_MODE(x) (((x) == TIMER_MODE_DISABLE) || \ +#define IS_TIMER_SLAVE_MODE(x) (((x) == TIMER_MODE_DISABLE) || \ ((x) == TIMER_MODE_ENC1) || \ ((x) == TIMER_MODE_ENC2) || \ ((x) == TIMER_MODE_ENC3) || \ @@ -837,7 +921,7 @@ do { \ ((x) == TIMER_MODE_GATED) || \ ((x) == TIMER_MODE_TRIG) || \ ((x) == TIMER_MODE_EXTERNAL1)) -#define IS_TIMER_EVENT_SOURCE(x) (((x) == TIMER_SRC_UPDATE) || \ +#define IS_TIMER_EVENT_SOURCE(x) (((x) == TIMER_SRC_UPDATE) || \ ((x) == TIMER_SRC_CC1) || \ ((x) == TIMER_SRC_CC2) || \ ((x) == TIMER_SRC_CC3) || \ @@ -845,7 +929,7 @@ do { \ ((x) == TIMER_SRC_COM) || \ ((x) == TIMER_SRC_TRIG) || \ ((x) == TIMER_SRC_BREAK)) -#define IS_TIMER_TS(x) (((x) == TIMER_TS_ITR0) || \ +#define IS_TIMER_TS(x) (((x) == TIMER_TS_ITR0) || \ ((x) == TIMER_TS_ITR1) || \ ((x) == TIMER_TS_ITR2) || \ ((x) == TIMER_TS_ITR3) || \ @@ -853,13 +937,13 @@ do { \ ((x) == TIMER_TS_TI1FP1) || \ ((x) == TIMER_TS_TI2FP2) || \ ((x) == TIMER_TS_ETRF)) -#define IS_TIMER_CLOCK_LEVEL(x) (((x) == TIMER_LOCK_LEVEL_OFF) || \ +#define IS_TIMER_CLOCK_LEVEL(x) (((x) == TIMER_LOCK_LEVEL_OFF) || \ ((x) == TIMER_LOCK_LEVEL_1) || \ ((x) == TIMER_LOCK_LEVEL_2) || \ ((x) == TIMER_LOCK_LEVEL_3)) -#define IS_TIMER_BREAK_POLARITY(x) (((x) == TIMER_BREAK_POLARITY_LOW) || \ +#define IS_TIMER_BREAK_POLARITY(x) (((x) == TIMER_BREAK_POLARITY_LOW) || \ ((x) == TIMER_BREAK_POLARITY_HIGH)) -#define IS_TIMER_MASTER_MODE_SEL(x) (((x) == TIMER_TRGO_RESET) || \ +#define IS_TIMER_MASTER_MODE_SEL(x) (((x) == TIMER_TRGO_RESET) || \ ((x) == TIMER_TRGO_ENABLE) || \ ((x) == TIMER_TRGO_UPDATE) || \ ((x) == TIMER_TRGO_OC1) || \ @@ -867,7 +951,7 @@ do { \ ((x) == TIMER_TRGO_OC2REF) || \ ((x) == TIMER_TRGO_OC3REF) || \ ((x) == TIMER_TRGO_OC4REF)) -#define IS_TIMER_IT(x) (((x) == TIMER_IT_UPDATE) || \ +#define IS_TIMER_IT(x) (((x) == TIMER_IT_UPDATE) || \ ((x) == TIMER_IT_CC1) || \ ((x) == TIMER_IT_CC2) || \ ((x) == TIMER_IT_CC3) || \ @@ -875,14 +959,14 @@ do { \ ((x) == TIMER_IT_COM) || \ ((x) == TIMER_IT_TRIGGER) || \ ((x) == TIMER_IT_BREAK)) -#define IS_TIMER_DMA_REQ(x) (((x) == TIMER_DMA_UPDATE) || \ +#define IS_TIMER_DMA_REQ(x) (((x) == TIMER_DMA_UPDATE) || \ ((x) == TIMER_DMA_CC1) || \ ((x) == TIMER_DMA_CC2) || \ ((x) == TIMER_DMA_CC3) || \ ((x) == TIMER_DMA_CC4) || \ ((x) == TIMER_DMA_COM) || \ ((x) == TIMER_DMA_TRIGGER)) -#define IS_TIMER_FLAG(x) (((x) == TIMER_FLAG_UPDATE) || \ +#define IS_TIMER_FLAG(x) (((x) == TIMER_FLAG_UPDATE) || \ ((x) == TIMER_FLAG_CC1) || \ ((x) == TIMER_FLAG_CC2) || \ ((x) == TIMER_FLAG_CC3) || \ @@ -905,16 +989,16 @@ do { \ * @{ */ /* Time Base functions */ -ald_status_t timer_base_init(timer_handle_t *hperh); -void timer_base_reset(timer_handle_t *hperh); -void timer_base_start(timer_handle_t *hperh); -void timer_base_stop(timer_handle_t *hperh); -void timer_base_start_by_it(timer_handle_t *hperh); -void timer_base_stop_by_it(timer_handle_t *hperh); +ald_status_t ald_timer_base_init(timer_handle_t *hperh); +void ald_timer_base_reset(timer_handle_t *hperh); +void ald_timer_base_start(timer_handle_t *hperh); +void ald_timer_base_stop(timer_handle_t *hperh); +void ald_timer_base_start_by_it(timer_handle_t *hperh); +void ald_timer_base_stop_by_it(timer_handle_t *hperh); #ifdef ALD_DMA -ald_status_t timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - uint16_t *buf, uint32_t len, uint8_t dma_ch); -void timer_base_stop_by_dma(timer_handle_t *hperh); +ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_base_stop_by_dma(timer_handle_t *hperh); #endif /** * @} @@ -924,15 +1008,15 @@ void timer_base_stop_by_dma(timer_handle_t *hperh); * @{ */ /* Timer Output Compare functions */ -ald_status_t timer_oc_init(timer_handle_t *hperh); -void timer_oc_start(timer_handle_t *hperh, timer_channel_t ch); -void timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch); -void timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +ald_status_t ald_timer_oc_init(timer_handle_t *hperh); +void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA -ald_status_t timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); -void timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** * @} @@ -942,18 +1026,18 @@ void timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); * @{ */ /* Timer PWM functions */ -ald_status_t timer_pwm_init(timer_handle_t *hperh); -void timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch); -void timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch); -void timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); -void timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq); -void timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty); -void timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch); +ald_status_t ald_timer_pwm_init(timer_handle_t *hperh); +void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq); +void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty); +void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA -ald_status_t timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); -void timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** * @} @@ -963,15 +1047,15 @@ void timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); * @{ */ /* Timer Input Capture functions */ -ald_status_t timer_ic_init(timer_handle_t *hperh); -void timer_ic_start(timer_handle_t *hperh, timer_channel_t ch); -void timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch); -void timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +ald_status_t ald_timer_ic_init(timer_handle_t *hperh); +void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA -ald_status_t timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); -void timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** * @} @@ -981,11 +1065,11 @@ void timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); * @{ */ /* Timer One Pulse functions */ -ald_status_t timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode); -void timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch); -void timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch); -void timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch); -void timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch); +ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode); +void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch); +void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch); +void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch); +void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch); /** * @} */ @@ -994,16 +1078,16 @@ void timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t * @{ */ /* Timer encoder functions */ -ald_status_t timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config); -void timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch); -void timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch); -void timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config); +void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA -ald_status_t timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, - dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, - uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2); -void timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, + uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2); +void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** * @} @@ -1013,15 +1097,15 @@ void timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); * @{ */ /* Timer hall sensor functions */ -ald_status_t timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config); -void timer_hall_sensor_start(timer_handle_t *hperh); -void timer_hall_sensor_stop(timer_handle_t *hperh); -void timer_hall_sensor_start_by_it(timer_handle_t *hperh); -void timer_hall_sensor_stop_by_it(timer_handle_t *hperh); +ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config); +void ald_timer_hall_sensor_start(timer_handle_t *hperh); +void ald_timer_hall_sensor_stop(timer_handle_t *hperh); +void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh); +void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh); #ifdef ALD_DMA -ald_status_t timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - uint16_t *buf, uint32_t len, uint8_t dma_ch); -void timer_hall_sensor_stop_by_dma(timer_handle_t *hperh); +ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh); #endif /** * @} @@ -1031,14 +1115,14 @@ void timer_hall_sensor_stop_by_dma(timer_handle_t *hperh); * @{ */ /* Timer complementary output compare functions */ -void timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch); -void timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch); -void timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA -ald_status_t timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); -void timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** * @} @@ -1048,14 +1132,14 @@ void timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); * @{ */ /* Timer complementary PWM functions */ -void timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch); -void timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch); -void timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); #ifdef ALD_DMA -ald_status_t timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, - timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); -void timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); +ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); #endif /** * @} @@ -1065,10 +1149,10 @@ void timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); * @{ */ /* Timer complementary one pulse functions */ -void timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch); -void timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch); -void timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch); -void timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); /** * @} */ @@ -1077,29 +1161,29 @@ void timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); * @{ */ /* Control functions */ -ald_status_t timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch); -ald_status_t timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch); -ald_status_t timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, - timer_channel_t ch_out, timer_channel_t ch_in); -ald_status_t timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch); -ald_status_t timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config); -ald_status_t timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select); -ald_status_t timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config); -ald_status_t timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config); -ald_status_t timer_generate_event(timer_handle_t *hperh, timer_event_source_t event); -uint32_t timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch); -void timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch); -void timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config); -void timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi); -void timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi); -void timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config); -void timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config); -void timer_irq_handle(timer_handle_t *hperh); -void timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state); -void timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state); -it_status_t timer_get_it_status(timer_handle_t *hperh, timer_it_t it); -flag_status_t timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag); -void timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag); +ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t* config, timer_channel_t ch); +ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t* config, timer_channel_t ch); +ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, + timer_channel_t ch_out, timer_channel_t ch_in); +ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch); +ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config); +ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select); +ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config); +ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config); +ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_t event); +uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch); +void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config); +void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi); +void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi); +void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config); +void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config); +void ald_timer_irq_handler(timer_handle_t *hperh); +void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state); +void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state); +it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it); +flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag); +void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag); /** * @} */ @@ -1108,7 +1192,7 @@ void timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag); * @{ */ /* State functions */ -timer_state_t timer_get_state(timer_handle_t *hperh); +timer_state_t ald_timer_get_state(timer_handle_t *hperh); /** * @} */ diff --git a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h similarity index 40% rename from bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h rename to bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h index 072f892184e98c63b3fce50002da56babe0edbbb..a1d395f487103600c56ac0a13a72a2aa31488397 100644 --- a/bsp/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_trng.h @@ -5,7 +5,7 @@ * @brief Header file of TRNG module driver. * * @version V1.0 - * @date 04 Dec 2017 + * @date 26 Jun 2019 * @author AE Team * @note * @@ -32,84 +32,103 @@ extern "C" { * @{ */ -/** @defgroup TRNG_Public_Macros TRNG Public Macros - * @{ - */ -#define TRNG_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK)) -#define TRNG_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK)) -#define TRNG_ADJM_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK)) -#define TRNG_ADJM_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK)) -/** - * @} - */ - /** @defgroup TRNG_Public_Types TRNG Public Types * @{ */ /** * @brief Data width */ -typedef enum -{ - TRNG_DSEL_1B = 0x0, /**< 1-bit */ - TRNG_DSEL_8B = 0x1, /**< 8-bit */ - TRNG_DSEL_16B = 0x2, /**< 16-bit */ - TRNG_DSEL_32B = 0x3, /**< 32-bit */ +typedef enum { + TRNG_DSEL_1B = 0x0, /**< 1-bit */ + TRNG_DSEL_8B = 0x1, /**< 8-bits */ + TRNG_DSEL_16B = 0x2, /**< 16-bits */ + TRNG_DSEL_32B = 0x3, /**< 32-bits */ } trng_data_width_t; /** * @brief seed type */ -typedef enum -{ - TRNG_SEED_TYPE_0 = 0x0, /**< Using 0 as seed */ - TRNG_SEED_TYPE_1 = 0x1, /**< Using 1 as seed */ - TRNG_SEED_TYPE_LAST = 0x2, /**< Using last seed */ - TRNG_SEED_TYPE_SEED = 0x3, /**< Using value of register */ +typedef enum { + TRNG_SEED_TYPE_0 = 0x0, /**< Using 0 as seed */ + TRNG_SEED_TYPE_1 = 0x1, /**< Using 1 as seed */ + TRNG_SEED_TYPE_LAST = 0x2, /**< Using last seed */ + TRNG_SEED_TYPE_SEED = 0x3, /**< Using value of register */ } trng_seed_type_t; /** * @brief TRNG init structure definition */ -typedef struct -{ - trng_data_width_t data_width; /**< The width of data */ - trng_seed_type_t seed_type; /**< The seed type */ - uint32_t seed; /**< The value of seed */ - uint16_t t_start; /**< T(start) = T(hclk) * (t_start + 1), T(start) > 1ms */ - uint8_t adjc; /**< Adjust parameter */ - uint8_t posten; +typedef struct { + trng_data_width_t data_width; /**< The width of data */ + trng_seed_type_t seed_type; /**< The seed type */ + uint32_t seed; /**< The value of seed */ + uint16_t t_start; /**< T(start) = T(hclk) * (t_start + 1), T(start) > 1ms */ + uint8_t adjc; /**< Adjust parameter */ + type_func_t posten; /**< Data back handle function */ } trng_init_t; +/** + * @brief TRNG state structures definition + */ +typedef enum { + TRNG_STATE_RESET = 0x0, /**< Peripheral is not initialized */ + TRNG_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */ + TRNG_STATE_BUSY = 0x2, /**< An internal process is ongoing */ + TRNG_STATE_ERROR = 0x4, /**< Error */ +} trng_state_t; + /** * @brief State type */ -typedef enum -{ - TRNG_STATUS_START = (1U << 0), /**< Start state */ - TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */ - TRNG_STATUS_SERR = (1U << 2), /**< Error state */ +typedef enum { + TRNG_STATUS_START = (1U << 0), /**< Start state */ + TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */ + TRNG_STATUS_SERR = (1U << 2), /**< Error state */ } trng_status_t; /** * @brief Interrupt type */ -typedef enum -{ - TRNG_IT_START = (1U << 0), /**< Start */ - TRNG_IT_DAVLD = (1U << 1), /**< Data valid */ - TRNG_IT_SERR = (1U << 2), /**< Error */ +typedef enum { + TRNG_IT_START = (1U << 0), /**< Start */ + TRNG_IT_DAVLD = (1U << 1), /**< Data valid */ + TRNG_IT_SERR = (1U << 2), /**< Error */ } trng_it_t; /** * @brief Interrupt flag type */ -typedef enum -{ - TRNG_IF_START = (1U << 0), /**< Start */ - TRNG_IF_DAVLD = (1U << 1), /**< Data valid */ - TRNG_IF_SERR = (1U << 2), /**< Error */ +typedef enum { + TRNG_IF_START = (1U << 0), /**< Start */ + TRNG_IF_DAVLD = (1U << 1), /**< Data valid */ + TRNG_IF_SERR = (1U << 2), /**< Error */ } trng_flag_t; + +/** + * @brief TRNG Handle Structure definition + */ +typedef struct trng_handle_s { + TRNG_TypeDef *perh; /**< Register base address */ + trng_init_t init; /**< TRNG required parameters */ + uint32_t data; /**< result data */ + lock_state_t lock; /**< Locking object */ + trng_state_t state; /**< TRNG operation state */ + + void (*trng_cplt_cbk)(struct trng_handle_s *arg); /**< Trng completed callback */ + void (*err_cplt_cbk)(struct trng_handle_s *arg); /**< Trng error callback */ + void (*init_cplt_cbk)(struct trng_handle_s *arg); /**< Trng init completed callback */ +} trng_handle_t; +/** + * @} + */ + +/** @defgroup TRNG_Public_Macros TRNG Public Macros + * @{ + */ +#define TRNG_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK)) +#define TRNG_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK)) +#define TRNG_ADJM_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK)) +#define TRNG_ADJM_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK)) /** * @} */ @@ -118,24 +137,24 @@ typedef enum * @defgroup TRNG_Private_Macros TRNG Private Macros * @{ */ -#define IS_TRNG_DATA_WIDTH(x) (((x) == TRNG_DSEL_1B) || \ +#define IS_TRNG_DATA_WIDTH(x) (((x) == TRNG_DSEL_1B) || \ ((x) == TRNG_DSEL_8B) || \ ((x) == TRNG_DSEL_16B) || \ ((x) == TRNG_DSEL_32B)) -#define IS_TRNG_SEED_TYPE(x) (((x) == TRNG_SEED_TYPE_0) || \ +#define IS_TRNG_SEED_TYPE(x) (((x) == TRNG_SEED_TYPE_0) || \ ((x) == TRNG_SEED_TYPE_1) || \ ((x) == TRNG_SEED_TYPE_LAST) || \ ((x) == TRNG_SEED_TYPE_SEED)) -#define IS_TRNG_STATUS(x) (((x) == TRNG_STATUS_START) || \ +#define IS_TRNG_STATUS(x) (((x) == TRNG_STATUS_START) || \ ((x) == TRNG_STATUS_DAVLD) || \ ((x) == TRNG_STATUS_SERR)) -#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \ +#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \ ((x) == TRNG_IT_DAVLD) || \ ((x) == TRNG_IT_SERR)) -#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \ +#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \ ((x) == TRNG_IF_DAVLD) || \ ((x) == TRNG_IF_SERR)) -#define IS_TRNG_ADJC(x) ((x) < 4) +#define IS_TRNG_ADJC(x) ((x) < 4) /** * @} */ @@ -147,7 +166,7 @@ typedef enum * @{ */ /* Initialization functions */ -extern void trng_init(trng_init_t *init); +extern ald_status_t ald_trng_init(trng_handle_t *hperh); /** * @} */ @@ -155,23 +174,22 @@ extern void trng_init(trng_init_t *init); * @{ */ /* Control functions */ -extern uint32_t trng_get_result(void); -extern void trng_interrupt_config(trng_it_t it, type_func_t state); -extern flag_status_t trng_get_status(trng_status_t status); -extern it_status_t trng_get_it_status(trng_it_t it); -extern flag_status_t trng_get_flag_status(trng_flag_t flag); -extern void trng_clear_flag_status(trng_flag_t flag); +extern uint32_t ald_trng_get_result(trng_handle_t *hperh); +extern void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state); +extern flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status); +extern it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it); +extern flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag); +extern void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag); +extern void ald_trng_irq_handler(trng_handle_t *hperh); /** * @} */ /** * @} */ - /** * @} */ - /** * @} */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h new file mode 100644 index 0000000000000000000000000000000000000000..775098e1c505edeb73c9d363f66a157b5f3f0528 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_tsense.h @@ -0,0 +1,199 @@ +/** + ********************************************************************************* + * + * @file ald_tsense.h + * @brief Header file of TSENSE module driver. + * + * @version V1.0 + * @date 26 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_TSENSE_H__ +#define __ALD_TSENSE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup TSENSE + * @{ + */ + +/** @defgroup TSENSE_Public_Macros TSENSE Public Macros + * @{ + */ +#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0)) +#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669)) +#define TSENSE_ENABLE() \ +do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_DISABLE() \ +do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_REQ_ENABLE() \ +do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_REQ_DISABLE() \ +do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_CTN_ENABLE() \ +do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_CTN_DISABLE() \ +do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_RESET() \ +do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_RST_MSK); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_LTGR_WR(data) \ +do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->LTGR, (data)); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_HTGR_WR(data) \ +do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->HTGR, (data)); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_TBDR_WR(data) \ +do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->TBDR, (data)); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_TCALBDR_WR(data) \ +do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->TCALBDR, (data)); \ + TSENSE_LOCK(); \ +} while (0) +/** + * @} + */ + +/** @defgroup TSENSE_Public_Types TSENSE Public Types + * @{ + */ +/** + * @brief Temperature update time + */ +typedef enum { + TSENSE_UPDATE_CYCLE_3 = 0x3, /**< 3 Cycles */ + TSENSE_UPDATE_CYCLE_4 = 0x4, /**< 4 Cycles */ + TSENSE_UPDATE_CYCLE_5 = 0x5, /**< 5 Cycles */ + TSENSE_UPDATE_CYCLE_6 = 0x6, /**< 6 Cycles */ + TSENSE_UPDATE_CYCLE_7 = 0x7, /**< 7 Cycles */ +} tsense_update_cycle_t; + +/** + * @brief Temperature output mode + */ +typedef enum { + TSENSE_OUTPUT_MODE_200 = 0x0, /**< 200 cycles update one temperature */ + TSENSE_OUTPUT_MODE_400 = 0x1, /**< 400 cycles update one temperature */ + TSENSE_OUTPUT_MODE_800 = 0x2, /**< 800 cycles update one temperature */ + TSENSE_OUTPUT_MODE_1600 = 0x3, /**< 1600 cycles update one temperature */ + TSENSE_OUTPUT_MODE_3200 = 0x4, /**< 3200 cycles update one temperature */ +} tsense_output_mode_t; + +/** + * @brief Source select + */ +typedef enum { + TSENSE_SOURCE_LOSC = 0x0, /**< LOSC */ + TSENSE_SOURCE_LRC = 0x1, /**< LRC */ +} tsense_source_sel_t; + + +/** + * @brief Define callback function type + */ +typedef void (*tsense_cbk)(uint16_t value, ald_status_t status); +/** + * @} + */ + +/** + * @defgroup TSENSE_Private_Macros TSENSE Private Macros + * @{ + */ +#define IS_TSENSE_SOURCE_SEL(x) (((x) == TSENSE_SOURCE_LOSC) || \ + ((x) == TSENSE_SOURCE_LRC)) +/** + * @} + */ + +/** @addtogroup TSENSE_Public_Functions + * @{ + */ +/** @addtogroup TSENSE_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +extern void ald_tsense_init(void); +extern void ald_tsense_source_select(tsense_source_sel_t sel); +/** + * @} + */ +/** @addtogroup TSENSE_Public_Functions_Group2 + * @{ + */ +/* Control functions */ +extern ald_status_t ald_tsense_get_value(uint16_t *tsense); +extern void ald_tsense_get_value_by_it(tsense_cbk cbk); +extern void ald_tsense_irq_handler(void); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_TSENSE_H__ */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..636a126d60a11cc3991c13f6cc4ca9bb08bdaeef --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_uart.h @@ -0,0 +1,547 @@ +/** + ********************************************************************************* + * + * @file ald_uart.h + * @brief Header file of UART module library. + * + * @version V1.0 + * @date 21 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __ALD_UART_H__ +#define __ALD_UART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/** + * @defgroup UART_Public_Macros UART Public Macros + * @{ + */ +#define UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK)) +#define UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK)) +#define UART_TX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK)) +#define UART_TX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK)) +#define UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RTOEN_MSK)) +#define UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RTOEN_MSK)) +#define UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK)) +#define UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK)) +#define UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK)) +#define UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK)) +#define UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK)) +#define UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK)) +#define UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK)) +#define UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK)) +#define UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK)) +#define UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK)) +#define UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK)) +#define UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK)) +#define UART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FCON, UART_FCON_TFRST_MSK)) +#define UART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FCON, UART_FCON_RFRST_MSK)) +#define UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_LBEN_MSK)) +#define UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_LBEN_MSK)) +#define UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK)) +#define UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK)) +#define UART_AUTOBR_REPT(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABRREPT_MSK)) +#define UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR)) +#define UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS)) +#define UART_ENABLE_SCARD_CLK(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK)) +#define UART_DISABLE_SCARD_CLK(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK)) +#define UART_ENABLE_SCARD_NACK(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK)) +#define UART_DISABLE_SCARD_NACK(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK)) +#define UART_SCARD_ENABLE(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK)) +#define UART_SCARD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK)) +/** + * @} + */ + +/** @defgroup UART_Public_Types UART Public Types + * @{ + */ +/** + * @brief UART word length + */ +typedef enum { + UART_WORD_LENGTH_8B = 0x0, /**< 8-bits */ + UART_WORD_LENGTH_7B = 0x1, /**< 7-bits */ + UART_WORD_LENGTH_6B = 0x2, /**< 6-bits */ + UART_WORD_LENGTH_5B = 0x3, /**< 5-bits */ +} uart_word_length_t; + +/** + * @brief UART stop bits + */ +typedef enum { + UART_STOP_BITS_1 = 0x0, /**< 1-bits */ + UART_STOP_BITS_2 = 0x1, /**< 2-bits */ + UART_STOP_BITS_0_5 = 0x0, /**< 0.5-bits, using smartcard mode */ + UART_STOP_BITS_1_5 = 0x1, /**< 1.5-bits, using smartcard mode */ +} uart_stop_bits_t; + +/** + * @brief UART parity + */ +typedef enum { + UART_PARITY_NONE = 0x0, /**< Not parity */ + UART_PARITY_ODD = 0x1, /**< Odd parity */ + UART_PARITY_EVEN = 0x3, /**< Even parity */ +} uart_parity_t; + +/** + * @brief UART mode + */ +typedef enum { + UART_MODE_UART = 0x0, /**< UART */ + UART_MODE_LIN = 0x1, /**< LIN */ + UART_MODE_IrDA = 0x2, /**< IrDA */ + UART_MODE_RS485 = 0x3, /**< RS485 */ + UART_MODE_HDSEL = 0x4, /**< Single-wire half-duplex */ + UART_MODE_SCARD = 0x5, /**< Smart card */ +} uart_mode_t; + +/** + * @brief UART hardware flow control + */ +typedef enum { + UART_HW_FLOW_CTL_DISABLE = 0x0, /**< Auto-flow-control disable */ + UART_HW_FLOW_CTL_ENABLE = 0x1, /**< Auto-flow-control enable */ +} uart_hw_flow_ctl_t; + +/** + * @brief ALD UART state + */ +typedef enum { + UART_STATE_RESET = 0x00, /**< Peripheral is not initialized */ + UART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */ + UART_STATE_BUSY = 0x02, /**< an internal process is ongoing */ + UART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */ + UART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */ + UART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */ + UART_STATE_TIMEOUT = 0x03, /**< Timeout state */ + UART_STATE_ERROR = 0x04, /**< Error */ +} uart_state_t; + +/** + * @brief UART error codes + */ +typedef enum { + UART_ERROR_NONE = ((uint32_t)0x00), /**< No error */ + UART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */ + UART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */ + UART_ERROR_FE = ((uint32_t)0x04), /**< frame error */ + UART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */ + UART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */ +} uart_error_t; + +/** + * @brief UART init structure definition + */ +typedef struct { + uint32_t baud; /**< Specifies the uart communication baud rate */ + uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ + uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ + uart_parity_t parity; /**< Specifies the parity mode */ + uart_mode_t mode; /**< Specifies uart mode */ + uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ +} uart_init_t; + +/** + * @brief UART handle structure definition + */ +typedef struct uart_handle_s { + UART_TypeDef *perh; /**< UART registers base address */ + uart_init_t init; /**< UART communication parameters */ + uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */ + uint16_t tx_size; /**< UART Tx Transfer size */ + uint16_t tx_count; /**< UART Tx Transfer Counter */ + uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */ + uint16_t rx_size; /**< UART Rx Transfer size */ + uint16_t rx_count; /**< UART Rx Transfer Counter */ +#ifdef ALD_DMA + dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */ + dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */ +#endif + lock_state_t lock; /**< Locking object */ + uart_state_t state; /**< UART communication state */ + uart_error_t err_code; /**< UART Error code */ + + void (*tx_cplt_cbk)(struct uart_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct uart_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct uart_handle_s *arg); /**< error callback */ +} uart_handle_t; + +/** + * @brief UART RS485 configure structure definition + */ +typedef struct { + type_func_t normal; /**< Normal mode */ + type_func_t dir; /**< Auto-direction mode */ + type_func_t invert; /**< Address detection invert */ + uint8_t addr; /**< Address for compare */ +} uart_rs485_config_t; + +/** + * @brief Smart_card clock division + */ +typedef enum { + SCARD_CLOCK_DIV1 = 0x0, /**< No prescaler is used */ + SCARD_CLOCK_DIV2 = 0x1, /** Clock is divided by 2 */ + SCARD_CLOCK_DIV4 = 0x2, /** Clock is divided by 4 */ + SCARD_CLOCK_DIV6 = 0x3, /** Clock is divided by 6 */ +} scard_clk_div_t; + +/** + * @brief Smart_card Rx/Tx handle retry time + */ +typedef enum { + SCARD_RETRY_CNT0 = 0x0, /**< retry time 0 */ + SCARD_RETRY_CNT1 = 0x1, /**< retry time 1 */ + SCARD_RETRY_CNT2 = 0x2, /**< retry time 2 */ + SCARD_RETRY_CNT3 = 0x3, /**< retry time 3 */ + SCARD_RETRY_CNT4 = 0x4, /**< retry time 4 */ + SCARD_RETRY_CNT5 = 0x5, /**< retry time 5 */ + SCARD_RETRY_CNT6 = 0x6, /**< retry time 6 */ + SCARD_RETRY_CNT7 = 0x7 /**< retry time 7 */ +} scard_retry_t; + +/** + * @brief UART Smart card configure structure definition + */ +typedef struct { + uint8_t block_len; /**< Specifies the data block length.*/ + uint8_t pt; /**< Specifies the protect time*/ + scard_retry_t retry; /**< Specifies retry time.*/ + scard_clk_div_t clk_div; /**< Specifies the clock division.*/ + type_func_t clk_out; /**< Specifies the clock out */ +} uart_scard_config_t; + +/** + * @brief LIN detection break length + */ +typedef enum { + LIN_BREAK_LEN_10B = 0x0, /**< 10-bit break */ + LIN_BREAK_LEN_11B = 0x1, /**< 11-bit break */ +} uart_lin_break_len_t; + +/** + * @brief UART TXFIFO size + */ +typedef enum { + UART_TXFIFO_EMPTY = 0x0, /**< Empty */ + UART_TXFIFO_2BYTE = 0x1, /**< 2-Bytes */ + UART_TXFIFO_4BYTE = 0x2, /**< 4-Bytes */ + UART_TXFIFO_8BYTE = 0x3, /**< 8-Bytes */ +} uart_txfifo_t; + +/** + * @brief UART RXFIFO size + */ +typedef enum { + UART_RXFIFO_1BYTE = 0x0, /**< 1-Byte */ + UART_RXFIFO_4BYTE = 0x1, /**< 4-Bytes */ + UART_RXFIFO_8BYTE = 0x2, /**< 8-Bytes */ + UART_RXFIFO_14BYTE = 0x3, /**< 14-Bytes */ +} uart_rxfifo_t; + +/** + * @brief UART auto-baud mode + */ +typedef enum { + UART_ABRMOD_1_TO_0 = 0x0, /**< Detect bit0:1, bit1:0 */ + UART_ABRMOD_1 = 0x1, /**< Detect bit0:1 */ + UART_ABRMOD_0_TO_1 = 0x2, /**< Detect bit0:0, bit1:1 */ +} uart_auto_baud_mode_t; + +/** + * @brief UART DMA Requests + */ +typedef enum { + UART_DMA_REQ_TX = 0x0, /**< TX dma */ + UART_DMA_REQ_RX = 0x1, /**< RX dma */ +} uart_dma_req_t; + +/** + * @brief UART status types + */ +typedef enum { + UART_STATUS_PERR = (1U << 0), /**< Parity error */ + UART_STATUS_FERR = (1U << 1), /**< Framing error */ + UART_STATUS_BKERR = (1U << 2), /**< Break error */ + UART_STATUS_CTSSTA = (1U << 3), /**< Clear to send status */ + UART_STATUS_RSBUSY = (1U << 8), /**< Receive shif register busy */ + UART_STATUS_RFTH = (1U << 9), /**< Receive FIFO trigger threshold */ + UART_STATUS_RFEMPTY = (1U << 10), /**< Receive FIFO empty */ + UART_STATUS_RFFULL = (1U << 11), /**< Receive FIFO full */ + UART_STATUS_RFOERR = (1U << 12), /**< Reveive FIFO overrun error */ + UART_STATUS_RFUERR = (1U << 13), /**< Receive FIFO underrun error */ + UART_STATUS_TSBUSY = (1U << 14), /**< Transmit shit register busy */ + UART_STATUS_TFTH = (1U << 15), /**< Transmit FIFO trigger threshold */ + UART_STATUS_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */ + UART_STATUS_TFFULL = (1U << 17), /**< Transmit FIFO full */ + UART_STATUS_TFOERR = (1U << 18), /**< Transmit FIFO overrun error */ +} uart_status_t; + +/** + * @brief UART interrupt types + */ +typedef enum { + UART_IT_RXBERR = (1U << 0), /**< Receiver byte error */ + UART_IT_ABEND = (1U << 1), /**< Auto-Baud rate detection end */ + UART_IT_ABTO = (1U << 2), /**< Auto-Baud rate detection timeout */ + UART_IT_DCTS = (1U << 3), /**< Delta CTS status */ + UART_IT_RXTO = (1U << 4), /**< Receiver timeout */ + UART_IT_ADDRM = (1U << 5), /**< Addredd match */ + UART_IT_LINBK = (1U << 6), /**< Lin break detection */ + UART_IT_EOB = (1U << 7), /**< End of block */ + UART_IT_NOISE = (1U << 8), /**< Start bit noise detection */ + UART_IT_RFTH = (1U << 9), /**< Receive FIFO trigger threshold */ + UART_IT_RFFULL = (1U << 11), /**< Receive FIFO full */ + UART_IT_RFOERR = (1U << 12), /**< Receive FIFO overrun */ + UART_IT_RFUERR = (1U << 13), /**< Reveive FIFO underrun */ + UART_IT_TSEMPTY = (1U << 14), /**< Transmit shift register empty */ + UART_IT_TFTH = (1U << 15), /**< Transmit FIFO trigger threshold */ + UART_IT_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */ + UART_IT_TFOVER = (1U << 18), /**< Transmit FIFO overrun */ +} uart_it_t; + +/** + * @brief UART flags types + */ +typedef enum { + UART_IF_RXBERR = (1U << 0), /**< Receiver byte error */ + UART_IF_ABEND = (1U << 1), /**< Auto-Baud rate detection end */ + UART_IF_ABTO = (1U << 2), /**< Auto-Baud rate detection timeout */ + UART_IF_DCTS = (1U << 3), /**< Delta CTS status */ + UART_IF_RXTO = (1U << 4), /**< Receiver timeout */ + UART_IF_ADDRM = (1U << 5), /**< Addredd match */ + UART_IF_LINBK = (1U << 6), /**< Lin break detection */ + UART_IF_EOB = (1U << 7), /**< End of block */ + UART_IF_NOISE = (1U << 8), /**< Start bit noise detection */ + UART_IF_RFTH = (1U << 9), /**< Receive FIFO trigger threshold */ + UART_IF_RFFULL = (1U << 11), /**< Receive FIFO full */ + UART_IF_RFOERR = (1U << 12), /**< Receive FIFO overrun */ + UART_IF_RFUERR = (1U << 13), /**< Reveive FIFO underrun */ + UART_IF_TBC = (1U << 14), /**< Transmit shift register empty */ + UART_IF_TFTH = (1U << 15), /**< Transmit FIFO trigger threshold */ + UART_IF_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */ + UART_IF_TFOVER = (1U << 18), /**< Transmit FIFO overrun */ +} uart_flag_t; +/** + * @} + */ + +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +#define IS_UART_SCARD(x)(((x) == UART4) || \ + ((x) == UART5)) +#define IS_UART_ALL(x) (((x) == UART0) || \ + ((x) == UART1) || \ + ((x) == UART2) || \ + ((x) == UART3) || \ + ((x) == UART4) || \ + ((x) == UART5)) +#define IS_UART_WORD_LENGTH(x) (((x) == UART_WORD_LENGTH_5B) || \ + ((x) == UART_WORD_LENGTH_6B) || \ + ((x) == UART_WORD_LENGTH_7B) || \ + ((x) == UART_WORD_LENGTH_8B)) +#define IS_UART_STOPBITS(x) (((x) == UART_STOP_BITS_1) || \ + ((x) == UART_STOP_BITS_2) || \ + ((x) == UART_STOP_BITS_0_5) || \ + ((x) == UART_STOP_BITS_1_5)) +#define IS_UART_PARITY(x) (((x) == UART_PARITY_NONE) || \ + ((x) == UART_PARITY_ODD) || \ + ((x) == UART_PARITY_EVEN)) +#define IS_UART_MODE(x) (((x) == UART_MODE_UART) || \ + ((x) == UART_MODE_LIN) || \ + ((x) == UART_MODE_IrDA) || \ + ((x) == UART_MODE_HDSEL) || \ + ((x) == UART_MODE_SCARD) || \ + ((x) == UART_MODE_RS485)) +#define IS_UART_HARDWARE_FLOW_CONTROL(x) \ + (((x) == UART_HW_FLOW_CTL_DISABLE) || \ + ((x) == UART_HW_FLOW_CTL_ENABLE)) +#define IS_UART_LIN_BREAK_LEN(x) (((x) == LIN_BREAK_LEN_10B) || \ + ((x) == LIN_BREAK_LEN_11B)) +#define IS_UART_TXFIFO_TYPE(x) (((x) == UART_TXFIFO_EMPTY) || \ + ((x) == UART_TXFIFO_2BYTE) || \ + ((x) == UART_TXFIFO_4BYTE) || \ + ((x) == UART_TXFIFO_8BYTE)) +#define IS_UART_RXFIFO_TYPE(x) (((x) == UART_RXFIFO_1BYTE) || \ + ((x) == UART_RXFIFO_4BYTE) || \ + ((x) == UART_RXFIFO_8BYTE) || \ + ((x) == UART_RXFIFO_14BYTE)) +#define IS_UART_AUTO_BAUD_MODE(x) (((x) == UART_ABRMOD_1_TO_0) || \ + ((x) == UART_ABRMOD_1) || \ + ((x) == UART_ABRMOD_0_TO_1)) +#define IS_UART_DMA_REQ(x) (((x) == UART_DMA_REQ_TX) || \ + ((x) == UART_DMA_REQ_RX)) +#define IS_UART_STATUS(x) (((x) == UART_STATUS_PERR) || \ + ((x) == UART_STATUS_FERR) || \ + ((x) == UART_STATUS_BKERR) || \ + ((x) == UART_STATUS_CTSSTA) || \ + ((x) == UART_STATUS_RSBUSY) || \ + ((x) == UART_STATUS_RFEMPTY) || \ + ((x) == UART_STATUS_RFFULL) || \ + ((x) == UART_STATUS_RFOERR) || \ + ((x) == UART_STATUS_RFUERR) || \ + ((x) == UART_STATUS_TSBUSY) || \ + ((x) == UART_STATUS_RFTH) || \ + ((x) == UART_STATUS_TFTH) || \ + ((x) == UART_STATUS_TFEMPTY) || \ + ((x) == UART_STATUS_TFFULL) || \ + ((x) == UART_STATUS_TFOERR)) +#define IS_UART_IT(x) (((x) == UART_IT_RXBERR) || \ + ((x) == UART_IT_ABEND) || \ + ((x) == UART_IT_ABTO) || \ + ((x) == UART_IT_DCTS) || \ + ((x) == UART_IT_RXTO) || \ + ((x) == UART_IT_ADDRM) || \ + ((x) == UART_IT_LINBK) || \ + ((x) == UART_IT_EOB) || \ + ((x) == UART_IT_NOISE) || \ + ((x) == UART_IT_RFTH) || \ + ((x) == UART_IT_RFFULL) || \ + ((x) == UART_IT_RFOERR) || \ + ((x) == UART_IT_RFUERR) || \ + ((x) == UART_IT_TSEMPTY) || \ + ((x) == UART_IT_TFTH) || \ + ((x) == UART_IT_TFEMPTY) || \ + ((x) == UART_IT_TFOVER)) +#define IS_UART_IF(x) (((x) == UART_IF_RXBERR) || \ + ((x) == UART_IF_ABEND) || \ + ((x) == UART_IF_ABTO) || \ + ((x) == UART_IF_DCTS) || \ + ((x) == UART_IF_RXTO) || \ + ((x) == UART_IF_ADDRM) || \ + ((x) == UART_IF_LINBK) || \ + ((x) == UART_IF_EOB) || \ + ((x) == UART_IF_NOISE) || \ + ((x) == UART_IF_RFTH) || \ + ((x) == UART_IF_RFFULL) || \ + ((x) == UART_IF_RFOERR) || \ + ((x) == UART_IF_RFUERR) || \ + ((x) == UART_IF_TBC) || \ + ((x) == UART_IF_TFTH) || \ + ((x) == UART_IF_TFEMPTY) || \ + ((x) == UART_IF_TFOVER)) +#define IS_UART_SCARD_CLK(x) (((x) == SCARD_CLOCK_DIV1) || \ + ((x) == SCARD_CLOCK_DIV2) || \ + ((x) == SCARD_CLOCK_DIV4) || \ + ((x) == SCARD_CLOCK_DIV6)) +#define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21)) +#define IS_UART_DATA(x) ((x) <= 0x1FF) + +#define UART_STATE_TX_MASK (1U << 4) +#define UART_STATE_RX_MASK (1U << 5) +/** + * @} + */ + +/** @addtogroup UART_Public_Functions + * @{ + */ + +/** @addtogroup UART_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void ald_uart_init(uart_handle_t *hperh); +void ald_uart_reset(uart_handle_t *hperh); +void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config); +void ald_uart_scard_config(uart_handle_t *hperh, uart_scard_config_t *config); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_send_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_recv_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_uart_recv_frame_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t t_out); +#ifdef ALD_DMA +ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_uart_dma_pause(uart_handle_t *hperh); +ald_status_t ald_uart_dma_resume(uart_handle_t *hperh); +ald_status_t ald_uart_dma_stop(uart_handle_t *hperh); +#endif +void ald_uart_irq_handler(uart_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group3 + * @{ + */ +/* Peripheral Control functions */ +void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state); +void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state); +void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config, uint8_t level); +void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level); +void uart_lin_break_detect_irq(uart_handle_t *hperh, type_func_t status); +void ald_uart_lin_send_break(uart_handle_t *hperh); +void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len); +void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode); +ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout); +it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it); +flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status); +flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag); +flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag); +void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group4 + * @{ + */ +/* Peripheral State and Errors functions */ +uart_state_t ald_uart_get_state(uart_handle_t *hperh); +uint32_t ald_uart_get_error(uart_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_UART_H__ */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h new file mode 100644 index 0000000000000000000000000000000000000000..436eba700e104dfc7b79ab153ca5eb5b785b73ff --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_usb.h @@ -0,0 +1,602 @@ +/** + ********************************************************************************* + * + * @file ald_usb.h + * @brief Header file of USB module driver. + * + * @version V1.0 + * @date 25 Dec 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_USB_H__ +#define __ALD_USB_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "utils.h" +#include "ald_rmu.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup USB + * @{ + */ + +/** @defgroup USB_Public_Macros USB Public Macros + * @{ + */ + +#define USB_POWER_ISOUP 0x00000080 +#define USB_POWER_SOFTCONN 0x00000040 +#define USB_POWER_HS_EN 0x00000020 +#define USB_POWER_HS_M 0x00000010 +#define USB_POWER_RESET 0x00000008 +#define USB_POWER_RESUME 0x00000004 +#define USB_POWER_SUSPEND 0x00000002 +#define USB_POWER_PWRDNPHY 0x00000001 + +#define USB_DEVCTL_DEV 0x00000080 +#define USB_DEVCTL_FSDEV 0x00000040 +#define USB_DEVCTL_LSDEV 0x00000020 +#define USB_DEVCTL_VBUS_M 0x00000018 +#define USB_DEVCTL_VBUS_NONE 0x00000000 +#define USB_DEVCTL_VBUS_SEND 0x00000008 +#define USB_DEVCTL_VBUS_AVALID 0x00000010 +#define USB_DEVCTL_VBUS_VALID 0x00000018 +#define USB_DEVCTL_HOST 0x00000004 +#define USB_DEVCTL_HOSTREQ 0x00000002 +#define USB_DEVCTL_SESSION 0x00000001 + +#define USB_RXCSRH1_AUTOCL 0x00000080 +#define USB_RXCSRH1_AUTORQ 0x00000040 +#define USB_RXCSRH1_ISO 0x00000040 +#define USB_RXCSRH1_DMAEN 0x00000020 +#define USB_RXCSRH1_DISNYET 0x00000010 +#define USB_RXCSRH1_PIDERR 0x00000010 +#define USB_RXCSRH1_DMAMOD 0x00000008 +#define USB_RXCSRH1_DTWE 0x00000004 +#define USB_RXCSRH1_DT 0x00000002 +#define USB_RXCSRH1_INCOMPRX 0x00000001 + +#define USB_CSRH0_DISPING 0x00000008 +#define USB_CSRH0_DTWE 0x00000004 +#define USB_CSRH0_DT 0x00000002 +#define USB_CSRH0_FLUSH 0x00000001 + +#define USB_TXCSRH1_AUTOSET 0x00000080 +#define USB_TXCSRH1_ISO 0x00000040 +#define USB_TXCSRH1_MODE 0x00000020 +#define USB_TXCSRH1_DMAEN 0x00000010 +#define USB_TXCSRH1_FDT 0x00000008 +#define USB_TXCSRH1_DMAMOD 0x00000004 +#define USB_TXCSRH1_DTWE 0x00000002 +#define USB_TXCSRH1_DT 0x00000001 + +#define USB_TXCSRL1_NAKTO 0x00000080 +#define USB_TXCSRL1_CLRDT 0x00000040 +#define USB_TXCSRL1_STALLED 0x00000020 +#define USB_TXCSRL1_STALL 0x00000010 +#define USB_TXCSRL1_SETUP 0x00000010 +#define USB_TXCSRL1_FLUSH 0x00000008 +#define USB_TXCSRL1_ERROR 0x00000004 +#define USB_TXCSRL1_UNDRN 0x00000004 +#define USB_TXCSRL1_FIFONE 0x00000002 +#define USB_TXCSRL1_TXRDY 0x00000001 + +#define USB_RXCSRL1_CLRDT 0x00000080 +#define USB_RXCSRL1_STALLED 0x00000040 +#define USB_RXCSRL1_STALL 0x00000020 +#define USB_RXCSRL1_REQPKT 0x00000020 +#define USB_RXCSRL1_FLUSH 0x00000010 +#define USB_RXCSRL1_DATAERR 0x00000008 +#define USB_RXCSRL1_NAKTO 0x00000008 +#define USB_RXCSRL1_OVER 0x00000004 +#define USB_RXCSRL1_ERROR 0x00000004 +#define USB_RXCSRL1_FULL 0x00000002 +#define USB_RXCSRL1_RXRDY 0x00000001 + +#define USB_CSRL0_NAKTO 0x00000080 +#define USB_CSRL0_SETENDC 0x00000080 +#define USB_CSRL0_STATUS 0x00000040 +#define USB_CSRL0_RXRDYC 0x00000040 +#define USB_CSRL0_REQPKT 0x00000020 +#define USB_CSRL0_STALL 0x00000020 +#define USB_CSRL0_SETEND 0x00000010 +#define USB_CSRL0_ERROR 0x00000010 +#define USB_CSRL0_DATAEND 0x00000008 +#define USB_CSRL0_SETUP 0x00000008 +#define USB_CSRL0_STALLED 0x00000004 +#define USB_CSRL0_TXRDY 0x00000002 +#define USB_CSRL0_RXRDY 0x00000001 + +#define USB_TYPE0_SPEED_M 0x000000C0 +#define USB_TYPE0_SPEED_HIGH 0x00000040 +#define USB_TYPE0_SPEED_FULL 0x00000080 +#define USB_TYPE0_SPEED_LOW 0x000000C0 + +#define USB_TXTYPE1_SPEED_M 0x000000C0 +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 +#define USB_TXTYPE1_SPEED_HIGH 0x00000040 +#define USB_TXTYPE1_SPEED_FULL 0x00000080 +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 +#define USB_TXTYPE1_PROTO_M 0x00000030 +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 +#define USB_TXTYPE1_PROTO_BULK 0x00000020 +#define USB_TXTYPE1_PROTO_INT 0x00000030 +#define USB_TXTYPE1_TEP_M 0x0000000F +#define USB_TXTYPE1_TEP_S 0 + +#define USB_LPMATTR_ENDPT_M 0x0000F000 +#define USB_LPMATTR_RMTWAK 0x00000100 +#define USB_LPMATTR_HIRD_M 0x000000F0 +#define USB_LPMATTR_LS_M 0x0000000F +#define USB_LPMATTR_LS_L1 0x00000001 +#define USB_LPMATTR_ENDPT_S 12 +#define USB_LPMATTR_HIRD_S 4 + +#define USB_LPMCNTRL_LPMRES 0x00000002 +#define USB_LPMCNTRL_LPMXMT 0x00000001 +#define USB_LPMCNTRL_ENABLE 0x00000006 +#define USB_LPMCNTRL_DISABLE 0x00000000 + +#define USB_INTCTRL_ALL 0x000003FF +#define USB_INTCTRL_STATUS 0x000000FF +#define USB_INTCTRL_VBUS_ERR 0x00000080 +#define USB_INTCTRL_SESSION 0x00000040 +#define USB_INTCTRL_SESSION_END 0x00000040 +#define USB_INTCTRL_DISCONNECT 0x00000020 +#define USB_INTCTRL_CONNECT 0x00000010 +#define USB_INTCTRL_SOF 0x00000008 +#define USB_INTCTRL_BABBLE 0x00000004 +#define USB_INTCTRL_RESET 0x00000004 +#define USB_INTCTRL_RESUME 0x00000002 +#define USB_INTCTRL_SUSPEND 0x00000001 +#define USB_INTCTRL_MODE_DETECT 0x00000200 +#define USB_INTCTRL_POWER_FAULT 0x00000100 + +#define USB_INTEP_ALL 0xFFFFFFFF +#define USB_INTEP_HOST_IN 0xFFFE0000 +#define USB_INTEP_HOST_IN_15 0x80000000 +#define USB_INTEP_HOST_IN_14 0x40000000 +#define USB_INTEP_HOST_IN_13 0x20000000 +#define USB_INTEP_HOST_IN_12 0x10000000 +#define USB_INTEP_HOST_IN_11 0x08000000 +#define USB_INTEP_HOST_IN_10 0x04000000 +#define USB_INTEP_HOST_IN_9 0x02000000 +#define USB_INTEP_HOST_IN_8 0x01000000 +#define USB_INTEP_HOST_IN_7 0x00800000 +#define USB_INTEP_HOST_IN_6 0x00400000 +#define USB_INTEP_HOST_IN_5 0x00200000 +#define USB_INTEP_HOST_IN_4 0x00100000 +#define USB_INTEP_HOST_IN_3 0x00080000 +#define USB_INTEP_HOST_IN_2 0x00040000 +#define USB_INTEP_HOST_IN_1 0x00020000 + +#define USB_INTEP_DEV_OUT 0xFFFE0000 +#define USB_INTEP_DEV_OUT_15 0x80000000 +#define USB_INTEP_DEV_OUT_14 0x40000000 +#define USB_INTEP_DEV_OUT_13 0x20000000 +#define USB_INTEP_DEV_OUT_12 0x10000000 +#define USB_INTEP_DEV_OUT_11 0x08000000 +#define USB_INTEP_DEV_OUT_10 0x04000000 +#define USB_INTEP_DEV_OUT_9 0x02000000 +#define USB_INTEP_DEV_OUT_8 0x01000000 +#define USB_INTEP_DEV_OUT_7 0x00800000 +#define USB_INTEP_DEV_OUT_6 0x00400000 +#define USB_INTEP_DEV_OUT_5 0x00200000 +#define USB_INTEP_DEV_OUT_4 0x00100000 +#define USB_INTEP_DEV_OUT_3 0x00080000 +#define USB_INTEP_DEV_OUT_2 0x00040000 +#define USB_INTEP_DEV_OUT_1 0x00020000 + +#define USB_INTEP_HOST_OUT 0x0000FFFE +#define USB_INTEP_HOST_OUT_15 0x00008000 +#define USB_INTEP_HOST_OUT_14 0x00004000 +#define USB_INTEP_HOST_OUT_13 0x00002000 +#define USB_INTEP_HOST_OUT_12 0x00001000 +#define USB_INTEP_HOST_OUT_11 0x00000800 +#define USB_INTEP_HOST_OUT_10 0x00000400 +#define USB_INTEP_HOST_OUT_9 0x00000200 +#define USB_INTEP_HOST_OUT_8 0x00000100 +#define USB_INTEP_HOST_OUT_7 0x00000080 +#define USB_INTEP_HOST_OUT_6 0x00000040 +#define USB_INTEP_HOST_OUT_5 0x00000020 +#define USB_INTEP_HOST_OUT_4 0x00000010 +#define USB_INTEP_HOST_OUT_3 0x00000008 +#define USB_INTEP_HOST_OUT_2 0x00000004 +#define USB_INTEP_HOST_OUT_1 0x00000002 + +#define USB_INTEP_DEV_IN 0x0000FFFE +#define USB_INTEP_DEV_IN_15 0x00008000 +#define USB_INTEP_DEV_IN_14 0x00004000 +#define USB_INTEP_DEV_IN_13 0x00002000 +#define USB_INTEP_DEV_IN_12 0x00001000 +#define USB_INTEP_DEV_IN_11 0x00000800 +#define USB_INTEP_DEV_IN_10 0x00000400 +#define USB_INTEP_DEV_IN_9 0x00000200 +#define USB_INTEP_DEV_IN_8 0x00000100 +#define USB_INTEP_DEV_IN_7 0x00000080 +#define USB_INTEP_DEV_IN_6 0x00000040 +#define USB_INTEP_DEV_IN_5 0x00000020 +#define USB_INTEP_DEV_IN_4 0x00000010 +#define USB_INTEP_DEV_IN_3 0x00000008 +#define USB_INTEP_DEV_IN_2 0x00000004 +#define USB_INTEP_DEV_IN_1 0x00000002 + +#define USB_INTEP_0 0x00000001 + +#define USB_UNDEF_SPEED 0x80000000 +#define USB_HIGH_SPEED 0x00000002 +#define USB_FULL_SPEED 0x00000001 +#define USB_LOW_SPEED 0x00000000 + +#define USB_HOST_IN_STATUS 0x114F0000 +#define USB_HOST_IN_PID_ERROR 0x10000000 +#define USB_HOST_IN_NOT_COMP 0x01000000 +#define USB_HOST_IN_STALL 0x00400000 +#define USB_HOST_IN_DATA_ERROR 0x00080000 + +#define USB_HOST_IN_NAK_TO 0x00080000 + +#define USB_HOST_IN_ERROR 0x00040000 + +#define USB_HOST_IN_FIFO_FULL 0x00020000 +#define USB_HOST_IN_PKTRDY 0x00010000 +#define USB_HOST_OUT_STATUS 0x000000A7 +#define USB_HOST_OUT_NAK_TO 0x00000080 + +#define USB_HOST_OUT_NOT_COMP 0x00000080 + +#define USB_HOST_OUT_STALL 0x00000020 +#define USB_HOST_OUT_ERROR 0x00000004 + +#define USB_HOST_OUT_FIFO_NE 0x00000002 +#define USB_HOST_OUT_PKTPEND 0x00000001 +#define USB_HOST_EP0_NAK_TO 0x00000080 + +#define USB_HOST_EP0_STATUS 0x00000040 +#define USB_HOST_EP0_ERROR 0x00000010 + +#define USB_HOST_EP0_RX_STALL 0x00000004 +#define USB_HOST_EP0_RXPKTRDY 0x00000001 +#define USB_DEV_RX_PID_ERROR 0x01000000 + +#define USB_DEV_RX_SENT_STALL 0x00400000 +#define USB_DEV_RX_DATA_ERROR 0x00080000 +#define USB_DEV_RX_OVERRUN 0x00040000 + +#define USB_DEV_RX_FIFO_FULL 0x00020000 +#define USB_DEV_RX_PKT_RDY 0x00010000 +#define USB_DEV_TX_NOT_COMP 0x00000080 + +#define USB_DEV_TX_SENT_STALL 0x00000020 +#define USB_DEV_TX_UNDERRUN 0x00000004 +#define USB_DEV_TX_FIFO_NE 0x00000002 +#define USB_DEV_TX_TXPKTRDY 0x00000001 +#define USB_DEV_EP0_SETUP_END 0x00000010 + +#define USB_DEV_EP0_SENT_STALL 0x00000004 +#define USB_DEV_EP0_IN_PKTPEND 0x00000002 +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 + +#define USB_EP_AUTO_SET 0x00000001 +#define USB_EP_AUTO_REQUEST 0x00000002 +#define USB_EP_AUTO_CLEAR 0x00000004 +#define USB_EP_DMA_MODE_0 0x00000008 +#define USB_EP_DMA_MODE_1 0x00000010 +#define USB_EP_DIS_NYET 0x00000020 + + +#define USB_EP_MODE_ISOC 0x00000000 +#define USB_EP_MODE_BULK 0x00000100 +#define USB_EP_MODE_INT 0x00000200 +#define USB_EP_MODE_CTRL 0x00000300 +#define USB_EP_MODE_MASK 0x00000300 +#define USB_EP_SPEED_LOW 0x00000000 +#define USB_EP_SPEED_FULL 0x00001000 +#define USB_EP_SPEED_HIGH 0x00004000 +#define USB_EP_HOST_IN 0x00000000 +#define USB_EP_HOST_OUT 0x00002000 +#define USB_EP_DEV_IN 0x00002000 +#define USB_EP_DEV_OUT 0x00000000 + +#define USB_HOST_PWRFLT_LOW 0x00000010 +#define USB_HOST_PWRFLT_HIGH 0x00000030 +#define USB_HOST_PWRFLT_EP_NONE 0x00000000 +#define USB_HOST_PWRFLT_EP_TRI 0x00000140 +#define USB_HOST_PWRFLT_EP_LOW 0x00000240 +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 +#define USB_HOST_PWREN_MAN_LOW 0x00000000 +#define USB_HOST_PWREN_MAN_HIGH 0x00000001 +#define USB_HOST_PWREN_AUTOLOW 0x00000002 +#define USB_HOST_PWREN_AUTOHIGH 0x00000003 +#define USB_HOST_PWREN_FILTER 0x00010000 + +#define USB_HOST_LPM_RMTWAKE 0x00000100 +#define USB_HOST_LPM_L1 0x00000001 +#define USB_DEV_LPM_NAK 0x00000010 +#define USB_DEV_LPM_NONE 0x00000000 +#define USB_DEV_LPM_EN 0x0000000c +#define USB_DEV_LPM_EXTONLY 0x00000004 +#define USB_DEV_LPM_LS_RMTWAKE 0x00000100 +#define USB_DEV_LPM_LS_L1 0x00000001 +#define USB_INTLPM_ERROR 0x00000020 +#define USB_INTLPM_RESUME 0x00000010 +#define USB_INTLPM_INCOMPLETE 0x00000008 +#define USB_INTLPM_ACK 0x00000004 +#define USB_INTLPM_NYET 0x00000002 +#define USB_INTLPM_STALL 0x00000001 + +#define MAX_NAK_LIMIT 31 +#define DISABLE_NAK_LIMIT 0 + +#define MAX_PACKET_SIZE_EP0 64 +#define USB_EP_0 0 +#define USB_EP_1 1 +#define USB_EP_2 2 +#define USB_EP_3 3 +#define USB_EP_4 4 +#define USB_EP_5 5 +#define NUM_USB_EP 6 +#define IndexToUSBEP(x) ((x)) +#define USBEPToIndex(x) ((x)) + +#define USB_FIFO_SZ_8 0x00000000 +#define USB_FIFO_SZ_16 0x00000001 +#define USB_FIFO_SZ_32 0x00000002 +#define USB_FIFO_SZ_64 0x00000003 +#define USB_FIFO_SZ_128 0x00000004 +#define USB_FIFO_SZ_256 0x00000005 +#define USB_FIFO_SZ_512 0x00000006 +#define USB_FIFO_SZ_1024 0x00000007 +#define USB_FIFO_SZ_2048 0x00000008 +#define USBFIFOSizeToBytes(x) (8 << (x)) + +#define USB_TRANS_OUT 0x00000102 +#define USB_TRANS_IN 0x00000102 +#define USB_TRANS_IN_LAST 0x0000010a +#define USB_TRANS_SETUP 0x0000110a +#define USB_TRANS_STATUS 0x00000142 + +#define USB_DUAL_MODE_HOST 0x00000001 +#define USB_DUAL_MODE_DEVICE 0x00000081 +#define USB_DUAL_MODE_NONE 0x00000080 +#define USB_OTG_MODE_ASIDE_HOST 0x0000001d +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 +#define USB_OTG_MODE_ASIDE_SESS 0x00000009 +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 +#define USB_OTG_MODE_ASIDE_DEV 0x00000019 +#define USB_OTG_MODE_BSIDE_HOST 0x0000009d +#define USB_OTG_MODE_BSIDE_DEV 0x00000099 +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 +#define USB_OTG_MODE_NONE 0x00000080 + +#define USB_DMA_INT_CH8 0x00000080 +#define USB_DMA_INT_CH7 0x00000040 +#define USB_DMA_INT_CH6 0x00000020 +#define USB_DMA_INT_CH5 0x00000010 +#define USB_DMA_INT_CH4 0x00000008 +#define USB_DMA_INT_CH3 0x00000004 +#define USB_DMA_INT_CH2 0x00000002 +#define USB_DMA_INT_CH1 0x00000001 +#define USB_DMA_EP_CFG_TX 0x00000001 +#define USB_DMA_EP_CFG_RX_DEV 0x00000002 +#define USB_DMA_EP_CFG_RX_HOST 0x00000004 +#define USB_DMA_EP_TX_MSK 0x94 +#define USB_DMA_EP_RX_DEV_MSK 0xA8 +#define USB_DMA_EP_RX_HOST_MSK 0xE8 +#define USB_DMA_STATUS_ERROR 0x00000100 + +#define USB_MODE_HOST_VBUS 0x00000004 +#define USB_MODE_HOST 0x00000002 +#define USB_MODE_DEV_VBUS 0x00000005 +#define USB_MODE_DEV 0x00000003 +#define USB_MODE_OTG 0x00000000 + +#define USB_RX_EPSTATUS_SHIFT 16 +#define USB_INTEP_RX_SHIFT 16 + +#define USB_DMA_CFG_START 0x00000001 +#define USB_DMA_CFG_START_NO 0x00000000 +#define USB_DMA_CFG_DIR_WR 0x00000000 +#define USB_DMA_CFG_DIR_RD 0x00000002 +#define USB_DMA_CFG_MODE_0 0x00000000 +#define USB_DMA_CFG_MODE_1 0x00000004 +#define USB_DMA_CFG_IE_DIS 0x00000000 +#define USB_DMA_CFG_IE_EN 0x00000008 +#define USB_DMA_CFG_EP_1 0x00000010 +#define USB_DMA_CFG_EP_2 0x00000020 +#define USB_DMA_CFG_EP_3 0x00000030 +#define USB_DMA_CFG_EP_4 0x00000040 +#define USB_DMA_CFG_EP_5 0x00000050 +#define USB_DMA_CFG_BURST_NONE 0x00000000 +#define USB_DMA_CFG_BURST_4 0x00000200 +#define USB_DMA_CFG_BURST_8 0x00000400 +#define USB_DMA_CFG_BURST_16 0x00000600 +#define USB_DMA_CFG_MODE_MSK 0x00000004 +#define USB_DMA_CFG_EP_POS 0x00000004 +#define USB_DMA_CFG_EP_MSK 0x000000F0 +#define USB_DMA_CH_ERR_MSK 0x100 +/** + * @} + */ + +/** @addtogroup USB_Public_Functions + * @{ + */ + +/** @addtogroup USB_Public_Functions_Group1 + * @{ + */ +/* Base functions */ +extern uint32_t ald_usb_frame_number_get(void); +extern void ald_usb_otg_session_request(bool start); +extern uint32_t ald_usb_mode_get(void); +extern void ald_usb_high_speed_enable(bool enable); +extern uint32_t ald_usb_device_speed_get(void); +extern uint32_t ald_usb_num_ep_get( void); +extern void ald_usb_control_reset(void); +extern void ald_usb_clock_output(void); +extern int ald_usb_eye_diagram_start(uint8_t *buf, uint16_t len); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group2 + * @{ + */ +/* Device functions */ +extern uint8_t ald_usb_dev_get_addr(void); +extern void ald_usb_dev_set_addr(uint8_t addr); +extern void ald_usb_dev_connect(void); +extern void ald_usb_dev_disconnect(void); +extern void ald_usb_dev_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t flags); +extern void ald_usb_dev_ep_get_config(uint32_t ep_idx, uint32_t *p_max, uint32_t *flags); +extern void ald_usb_dev_ep_data_ack(uint32_t ep_idx, bool last); +extern void ald_usb_dev_ep_stall(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_dev_ep_stall_clear(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_dev_ep_status_clear(uint32_t ep_idx, uint32_t flags); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group3 + * @{ + */ +/* Host functions */ +extern uint32_t ald_usb_host_addr_get(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_host_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags); +extern void ald_usb_host_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags); +extern void ald_usb_host_ep_data_ack(uint32_t ep_idx); +extern void ald_usb_host_ep_data_toggle(uint32_t ep_idx, bool toggle, uint32_t flags); +extern void ald_usb_host_ep_status_clear(uint32_t ep_idx, uint32_t flags); +extern uint32_t ald_usb_host_hub_addr_get(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_host_hub_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags); +extern void ald_usb_host_pwr_disable(void); +extern void ald_usb_host_pwr_enable(void); +extern void ald_usb_host_pwr_config(uint32_t flags); +extern void ald_usb_host_pwr_fault_disable(void); +extern void ald_usb_host_pwr_fault_enable(void); +extern void ald_usb_host_request_in(uint32_t ep_idx); +extern void ald_usb_host_request_in_clear(uint32_t ep_idx); +extern void ald_usb_host_request_status(void); +extern void ald_usb_host_reset(bool start); +extern void ald_usb_host_resume(bool start); +extern void ald_usb_host_suspend(void); +extern uint32_t ald_usb_host_speed_get(void); +extern void ald_usb_host_ep_speed_set(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_host_ep_ping(uint32_t ep_idx, bool enable); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group4 + * @{ + */ +/* Endpoint functions */ +extern uint32_t ald_usb_ep_data_avail(uint32_t ep_idx); +extern int32_t ald_usb_ep_data_get(uint32_t ep_idx, uint8_t *data, uint32_t *size); +extern int32_t ald_usb_ep_data_put(uint32_t ep_idx, uint8_t *data, uint32_t size); +extern int32_t ald_usb_ep_data_send(uint32_t ep_idx, uint32_t tx_type); +extern void ald_usb_ep_data_toggle_clear(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_ep_req_packet_count(uint32_t ep_idx, uint32_t count); +extern uint32_t ald_usb_ep_status(uint32_t ep_idx); +extern void ald_usb_ep_dma_config(uint32_t ep_idx, uint32_t flag, type_func_t en); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group5 + * @{ + */ +/* FIFO functions */ +extern uint32_t ald_usb_fifo_addr_get(uint32_t ep_idx); +extern void ald_usb_fifo_config_get(uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags); +extern void ald_usb_fifo_config_set(uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags); +extern void ald_usb_fifo_flush(uint32_t ep_idx, uint32_t flags); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group6 + * @{ + */ +/* Interrupt functions */ +extern void ald_usb_int_disable(uint32_t flags); +extern void ald_usb_int_enable(uint32_t flags); +extern uint32_t ald_usb_int_status_get(void); +extern void ald_usb_int_disable_ep(uint32_t flags); +extern void ald_usb_int_enable_ep(uint32_t flags); +extern uint32_t ald_usb_int_status_ep_get(void); +extern void ald_usb_int_register(void); +extern void ald_usb_int_unregister(void); +extern uint32_t ald_usb_int_num_get(void); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group7 + * @{ + */ +/* DMA functions */ +extern void ald_usb_dma_channel_config(uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl); +extern void ald_usb_dma_mult_recv_start(uint32_t ep_idx); +extern void ald_usb_dma_channel_start(uint8_t ch); +extern void ald_usb_dma_channel_stop(uint8_t ch); +extern uint32_t ald_usb_dma_get_interrupt_flag(void); +extern uint32_t ald_usb_dma_get_channel_error(uint8_t ch); +extern void ald_usb_dma_clear_channel_error(uint8_t ch); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group8 + * @{ + */ +/* LPM functions */ +extern void ald_usb_host_lpm_send(uint32_t addr, uint32_t ep_idx); +extern void ald_usb_host_lpm_config(uint32_t resume_time, uint32_t config); +extern uint32_t ald_usb_lpm_remote_wake_is_enable(void); +extern void ald_usb_host_lpm_resume(void); +extern void ald_usb_dev_lpm_remote_wake(void); +extern void ald_usb_dev_lpm_config(uint32_t config); +extern void ald_usb_dev_lpm_enable(void); +extern void ald_usb_dev_lpm_disable(void); +extern uint32_t ald_usb_lpm_link_status_get(void); +extern uint32_t ald_usb_lpm_ep_get(void); +extern uint32_t ald_usb_lpm_int_status_get(void); +extern void ald_usb_lpm_int_disable(uint32_t ints); +extern void ald_usb_lpm_int_enable(uint32_t ints); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h new file mode 100644 index 0000000000000000000000000000000000000000..f0bef5603aae5f090418153613f4e87706931721 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_wdt.h @@ -0,0 +1,116 @@ +/** + ********************************************************************************* + * + * @file ald_wdt.h + * @brief Header file of WDT module driver. + * + * @version V1.0 + * @date 18 Dec 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#ifndef __ALD_WDT_H__ +#define __ALD_WDT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup WDT + * @{ + */ + +/** @defgroup WDT_Public_Types WDT Public Types + * @{ + */ + +/** + * @brief Wwdt no dog window + */ +typedef enum { + WWDT_WIN_25 = 0x0, /**< No dog window size: 25% */ + WWDT_WIN_50 = 0x1, /**< No dog window size: 50% */ + WWDT_WIN_75 = 0x2, /**< No dog window size: 75% */ + WWDT_WIN_00 = 0x3, /**< No dog window size: 0% */ +} wwdt_win_t; + +/** + * @} + */ + +/** + * @defgroup WDT_Private_Macros WDT Private Macros + * @{ + */ +#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551);} +#define WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFF);} +#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551);} +#define IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFF);} + +/** + * @} + */ + +/** + * @addtogroup WDT_Private_Macros WDT Private Macros + * @{ + */ +#define IS_WWDT_WIN_TYPE(x) ((x == WWDT_WIN_25) || \ + (x == WWDT_WIN_50) || \ + (x == WWDT_WIN_75) || \ + (x == WWDT_WIN_00)) +#define IS_FUNC_STATE(x) (((x) == DISABLE) || \ + ((x) == ENABLE)) +/** + * @} + */ + +/** @addtogroup WWDT_Public_Functions + * @{ + */ +void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt); +void ald_wwdt_start(void); +uint32_t ald_wwdt_get_value(void); +it_status_t ald_wwdt_get_flag_status(void); +void ald_wwdt_clear_flag_status(void); +void ald_wwdt_feed_dog(void); +/** + * @} + */ + +/** @addtogroup IWDT_Public_Functions + * @{ + */ +void ald_iwdt_init(uint32_t load, type_func_t interrupt); +void ald_iwdt_start(void); +uint32_t ald_iwdt_get_value(void); +it_status_t ald_iwdt_get_flag_status(void); +void ald_iwdt_clear_flag_status(void); +void ald_iwdt_feed_dog(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_WDT_H__ */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h new file mode 100644 index 0000000000000000000000000000000000000000..f09c9b06cf606aae1b67c48ec2faadf85435cae5 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/type.h @@ -0,0 +1,122 @@ +/** + ********************************************************************************* + * + * @file type.h + * @brief define type + * + * @version V1.0 + * @date 17 Apr 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __TYPE_H__ +#define __TYPE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#if defined (__CC_ARM) +#define __INLINE__ __inline +#define __STATIC_INLINE__ static __inline +#else +#define __INLINE__ inline +#define __STATIC_INLINE__ static inline +#endif + +#define __isr__ + +typedef enum { + RESET = 0x0, + SET = 0x1, +} flag_status_t, it_status_t; + +typedef enum { + BIT_RESET = 0x0, + BIT_SET = 0x1, +} bit_status_t; + +typedef enum { + DISABLE = 0x0, + ENABLE = 0x1, +} type_func_t; +#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) + +typedef enum { + FALSE = 0x0, + TRUE = 0x1, +} type_bool_t; + +typedef enum { + UNLOCK = 0x0, + LOCK = 0x1, +} lock_state_t; +#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) + + +#define BIT(x) ((1U << (x))) +#define BITS(s, e) ((0xffffffff << (s)) & (0xffffffff >> (31 - (e)))) +#define SET_BIT(reg, bit) ((reg) |= (bit)) +#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit)) +#define READ_BIT(reg, bit) ((reg) & (bit)) +#define READ_BITS(reg, msk, s) (((reg) & (msk)) >> (s)) +#define CLEAR_REG(reg) ((reg) = (0x0)) +#define WRITE_REG(reg, val) ((reg) = (val)) +#define READ_REG(reg) ((reg)) +#define MODIFY_REG(reg, clearmask, setmask) \ + WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask))) +#define UNUSED(x) ((void)(x)) + +#ifdef USE_ASSERT +#define assert_param(x) \ +do { \ + if (!(x)) { \ + __disable_irq(); \ + while (1) \ + ; \ + } \ +} while (0) +#else +#define assert_param(x) +#endif + + +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /* PER base address */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /* RAM base address */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /* Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /* SRAM Address Space bit-band area */ + +__STATIC_INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val) +{ + uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; +} + +__STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val) +{ + uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; +} + +#if defined ( __GNUC__ ) + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __TYPE_H__ */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h new file mode 100644 index 0000000000000000000000000000000000000000..39398b771f7290cbffeeb0a62b821ac2c6341a17 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/utils.h @@ -0,0 +1,187 @@ +/** + ********************************************************************************* + * + * @file utils.h + * @brief This file contains the Utilities functions/types for the driver. + * + * @version V1.0 + * @date 07 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#ifndef __UTILS_H__ +#define __UTILS_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include +#include "ald_conf.h" +#include "type.h" +#ifdef ES32F36xx +#include "es32f36xx.h" +#elif ES32F39xx +#include "es32f39xx.h" +#elif ES32F336x +#include "es32f336x.h" +#endif + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup UTILS + * @{ + */ + +/** @defgroup ALD_Public_Types Public Types + * @{ + */ +/** + * @brief SysTick interval + */ +extern uint32_t __systick_interval; + +/** + * @brief ALD Status structures definition + */ +typedef enum { + OK = 0x0, /**< OK */ + ERROR = 0x1, /**< ERROR */ + BUSY = 0x2, /**< BUSY */ + TIMEOUT = 0x3 /**< TIMEOUT */ +} ald_status_t; + +/** + * @brief NVIC Preemption Priority Group + */ +typedef enum { + NVIC_PRIORITY_GROUP_0 = 0x7, /**< 0-bits for pre-emption priority 4-bits for subpriority */ + NVIC_PRIORITY_GROUP_1 = 0x6, /**< 1-bits for pre-emption priority 3-bits for subpriority */ + NVIC_PRIORITY_GROUP_2 = 0x5, /**< 2-bits for pre-emption priority 2-bits for subpriority */ + NVIC_PRIORITY_GROUP_3 = 0x4, /**< 3-bits for pre-emption priority 1-bits for subpriority */ + NVIC_PRIORITY_GROUP_4 = 0x3, /**< 4-bits for pre-emption priority 0-bits for subpriority */ +} nvic_priority_group_t; + +/** + * @brief SysTick interval definition + */ +typedef enum { + SYSTICK_INTERVAL_1MS = 1000, /**< Interval is 1ms */ + SYSTICK_INTERVAL_10MS = 100, /**< Interval is 10ms */ + SYSTICK_INTERVAL_100MS = 10, /**< Interval is 100ms */ + SYSTICK_INTERVAL_1000MS = 1, /**< Interval is 1s */ +} systick_interval_t; +/** + * @} + */ + +/** @defgroup ALD_Public_Macros Public Macros + * @{ + */ +#define ALD_MAX_DELAY 0xFFFFFFFF + +#define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET) +#define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET) +#define RESET_HANDLE_STATE(x) ((x)->state = 0) +#define DWT_CR *(uint32_t *)0xE0001000 +#define DWT_CYCCNT *(volatile uint32_t *)0xE0001004 +#define DEM_CR *(uint32_t *)0xE000EDFC +#define DEM_CR_TRCENA (1U << 24) +#define DWT_CR_CYCCNTEA (1U << 0) +#define __LOCK(x) \ +do { \ + if ((x)->lock == LOCK) { \ + return BUSY; \ + } \ + else { \ + (x)->lock = LOCK; \ + } \ +} while (0) +#define __UNLOCK(x) \ +do { \ + (x)->lock = UNLOCK; \ +} while (0) +#define ALD_PANIC() \ +do { \ + while (1) \ + ; \ +} while (0) +/** + * @} + */ + +/** @defgroup ALD_Private_Macros Private Macros + * @{ + */ +#define IS_PREEMPT_PRIO(x) ((x) < 16) +#define IS_SUB_PRIO(x) ((x) < 16) +#define IS_SYSTICK_INTERVAL(x) (((x) == SYSTICK_INTERVAL_1MS) || \ + ((x) == SYSTICK_INTERVAL_10MS) || \ + ((x) == SYSTICK_INTERVAL_100MS) || \ + ((x) == SYSTICK_INTERVAL_1000MS)) +/** + * @} + */ + +/** @addtogroup ALD_Public_Functions + * @{ + */ + +/** @addtogroup ALD_Public_Functions_Group1 + * @{ + */ + +/* Initialization functions */ +void ald_cmu_init(void); +void ald_tick_init(uint32_t prio); +void ald_systick_interval_select(systick_interval_t value); + +/** + * @} + */ + +/** @addtogroup ALD_Public_Functions_Group2 + * @{ + */ +/* Peripheral Control functions */ +void ald_inc_tick(void); +void ald_systick_irq_cbk(void); +void ald_delay_ms(__IO uint32_t delay); +uint32_t ald_get_tick(void); +void ald_suspend_tick(void); +void ald_resume_tick(void); +uint32_t ald_get_ald_version(void); +ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout); +void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status); +uint32_t ald_mcu_get_cpu_id(void); +void ald_mcu_timestamp_init(void); +uint32_t ald_mcu_get_timestamp(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __UTILS_H__ */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_acmp.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_acmp.c new file mode 100644 index 0000000000000000000000000000000000000000..75c53bda134c79f7d6d9d7f8d577bb3ee9a072b2 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_acmp.c @@ -0,0 +1,320 @@ +/** + ********************************************************************************* + * + * @file ald_acmp.c + * @brief ACMP module driver. + * + * @version V1.0 + * @date 26 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_acmp.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup ACMP ACMP + * @brief ACMP module driver + * @{ + */ +#ifdef ALD_ACMP + +/** @defgroup ACMP_Public_Functions ACMP Public Functions + * @{ + */ + +/** @defgroup ACMP_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Initializes the ACMP mode according to the specified parameters in + * the acmp_init_t and create the associated handle. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_acmp_init(acmp_handle_t *hperh) +{ + uint32_t tmp = 0; + + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_MODE_TYPE(hperh->init.mode)); + assert_param(IS_ACMP_WARM_UP_TIME_TYPE(hperh->init.warm_time)); + assert_param(IS_ACMP_HYSTSEL_TYPE(hperh->init.hystsel)); + assert_param(IS_ACMP_POS_INPUT_TYPE(hperh->init.p_port)); + assert_param(IS_ACMP_NEG_INPUT_TYPE(hperh->init.n_port)); + assert_param(IS_ACMP_INACTVAL_TYPE(hperh->init.inactval)); + assert_param(IS_FUNC_STATE(hperh->init.out_inv)); + assert_param(IS_ACMP_EDGE_TYPE(hperh->init.edge)); + assert_param(hperh->init.vdd_level < 64); + + __LOCK(hperh); + tmp = ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) | + (hperh->init.inactval << ACMP_CON_INACTV_POS) | (hperh->init.hystsel << ACMP_CON_HYSTSEL_POSS)); + + hperh->perh->CON = tmp; + + tmp |= ((hperh->init.p_port << ACMP_INPUTSEL_PSEL_POSS) | (hperh->init.n_port << ACMP_INPUTSEL_NSEL_POSS) | + (hperh->init.vdd_level << ACMP_INPUTSEL_VDDLVL_POSS)); + hperh->perh->INPUTSEL = tmp; + + if (hperh->init.out_inv) + SET_BIT(hperh->perh->CON, ACMP_CON_OUTINV_MSK); + else + CLEAR_BIT(hperh->perh->CON, ACMP_CON_OUTINV_MSK); + + switch (hperh->init.edge) { + case ACMP_EDGE_NONE: + CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + case ACMP_EDGE_FALL: + SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + case ACMP_EDGE_RISE: + CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + case ACMP_EDGE_ALL: + SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + default: + break; + } + + SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK); + + tmp = 0; + while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0) { + if (tmp++ >= 600000) { + __UNLOCK(hperh); + return ERROR; + } + } + + __UNLOCK(hperh); + return OK; +} +/** + * @} + */ + +/** @defgroup ACMP_Public_Functions_Group2 Interrupt operation functions + * @brief ACMP Interrupt operation functions + * @{ + */ + +/** + * @brief Enables or disables the specified ACMP interrupts. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param it: Specifies the ACMP interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref acmp_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + hperh->perh->IES = it; + else + hperh->perh->IEC = it; + + return; +} + +/** + * @brief Checks whether the specified ACMP interrupt has set or not. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param it: Specifies the ACMP interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref acmp_it_t. + * @retval it_status_t + * - SET + * - RESET + */ +it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_IT_TYPE(it)); + + if (hperh->perh->IEV & it) + return SET; + + return RESET; +} + +/** + * @brief Checks whether the specified ACMP interrupt has occurred or not. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param flag: Specifies the ACMP interrupt source to check. + * This parameter can be one of the @ref acmp_flag_t. + * @retval flag_status_t + * - SET + * - RESET + */ +flag_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_FLAG_TYPE(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** + * @brief Get the status of interrupt flag and interupt source. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP. + * @param flag: Specifies the ACMP interrupt flag. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_acmp_get_mask_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_FLAG_TYPE(flag)); + + if (hperh->perh->IFM & flag) + return SET; + + return RESET; +} + +/** @brief Clear the specified ACMP it flags. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param flag: specifies the it flag. + * This parameter can be one of the @ref acmp_flag_t. + * @retval None + */ +void ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_FLAG_TYPE(flag)); + + hperh->perh->IFC = flag; + return; +} +/** + * @} + */ +/** @defgroup ACMP_Public_Functions_Group3 Output value functions + * @brief ACMP Output value functions + * @{ + */ +/** + * @brief This function handles ACMP interrupt request. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @retval None + */ +void ald_acmp_irq_handler(acmp_handle_t *hperh) +{ + if ((ald_acmp_get_mask_flag_status(hperh, ACMP_FLAG_WARMUP)) == SET) { + ald_acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP); + + if (hperh->acmp_warmup_cplt_cbk) + hperh->acmp_warmup_cplt_cbk(hperh); + } + + if ((ald_acmp_get_mask_flag_status(hperh, ACMP_FLAG_EDGE)) == SET) { + ald_acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE); + + if (hperh->acmp_edge_cplt_cbk) + hperh->acmp_edge_cplt_cbk(hperh); + } + + return; +} + +/** + * @brief This function config acmp output. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param state: ENABLE/DISABLE. + * @retval None + */ +void ald_acmp_out_config(acmp_handle_t *hperh, type_func_t state) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + SET_BIT(hperh->perh->PORT, ACMP_PORT_PEN_MSK); + else + CLEAR_BIT(hperh->perh->PORT, ACMP_PORT_PEN_MSK); + + return; +} + +/** + * @brief This function output acmp result. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @retval output value. + */ +uint8_t ald_acmp_out_result(acmp_handle_t *hperh) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + + return (READ_BIT(hperh->perh->STAT, ACMP_STAT_OUT_MSK) >> ACMP_STAT_OUT_POS); +} + +/** @brief Check whether the specified ACMP flag is set or not. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param status: specifies the status to check. + * This parameter can be one of the @ref acmp_status_t. + * @retval flag_status_t + * - SET + * - RESET + */ +flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_STATUS_TYPE(status)); + + if (hperh->perh->STAT & status) + return SET; + + return RESET; +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_ACMP */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..f98ad7199b12f71e83c6de7f9acbe4a3b3d09676 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_adc.c @@ -0,0 +1,1254 @@ +/** + ****************************************************************************** + * @file ald_adc.c + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) + * peripheral: + * + Initialization functions + * ++ Initialization and Configuration of ADC + * + Operation functions + * ++ Start, stop, get result of conversions of normal + * group, using 3 possible modes: polling, interruption or DMA. + * + Control functions + * ++ Channels configuration on normal group + * ++ Channels configuration on insert group + * ++ Analog Watchdog configuration + * + State functions + * ++ ADC state machine management + * ++ Interrupts and flags management + * + * @version V1.0 + * @date 28 Jun 2019 + * @author AE Team. + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + + +#include "ald_cmu.h" +#include "ald_adc.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC module driver + * @{ + */ + +#ifdef ALD_ADC + +/** @addtogroup ADC_Private_Functions + * @{ + */ +#ifdef ALD_DMA +static void adc_dma_normal_conv_cplt(void *arg); +static void adc_dma_error(void *arg); +#endif +/** + * @} + */ + + +/** @defgroup ADC_Public_Functions ADC Public Functions + * @{ + */ + +/** @defgroup ADC_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Initializes the ADC peripheral and normal group according to + * parameters specified in structure "adc_handle_t". + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_init(adc_handle_t *hperh) +{ + ald_status_t tmp_status = OK; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_DATA_ALIGN_TYPE(hperh->init.data_align)); + assert_param(IS_ADC_SCAN_MODE_TYPE(hperh->init.scan_mode)); + assert_param(IS_ADC_CLK_DIV_TYPE(hperh->init.clk_div)); + assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.neg_ref)); + assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.pos_ref)); + assert_param(IS_ADC_CONV_RES_TYPE(hperh->init.conv_res)); + assert_param(IS_ADC_NCH_LEN_TYPE(hperh->init.nch_len)); + assert_param(IS_ADC_DISC_NBR_TYPE(hperh->init.disc_nbr)); + assert_param(IS_FUNC_STATE(hperh->init.cont_mode)); + assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_sel)); + + if (hperh->state == ADC_STATE_RESET ) { + hperh->error_code = ADC_ERROR_NONE; + hperh->lock = UNLOCK; + } + + ADC_DISABLE(hperh); + ald_adc_reset(hperh); + hperh->state = ADC_STATE_BUSY_INTERNAL; + MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.data_align << ADC_CON1_ALIGN_POS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.cont_mode << ADC_CON1_CM_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.conv_res << ADC_CON0_RSEL_POSS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan_mode << ADC_CON0_SCANEN_POS); + + /* Enable discontinuous mode only if continuous mode is enabled */ + if (hperh->init.disc_mode == ADC_NCH_DISC_EN) { + hperh->init.scan_mode = ENABLE; + SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nbr << ADC_CON0_ETRGN_POSS); + } + else { + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + } + + if ((hperh->init.scan_mode == ENABLE) || (hperh->init.disc_mode == ADC_NCH_DISC_EN)) + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.nch_len << ADC_CHSL_NSL_POSS); + + MODIFY_REG(hperh->perh->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS); + /* if the ADC CLK less than 1MHZ,PWRMOD should be Enable*/ + MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.clk_div << ADC_CCR_CKDIV_POSS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.neg_ref << ADC_CCR_VRNSEL_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.pos_ref << ADC_CCR_VRPSEL_POSS); + MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS); + + if (tmp_status == OK) { + hperh->error_code = ADC_ERROR_NONE; + hperh->state |= ADC_STATE_READY; + hperh->state &= ~(ADC_STATE_ERROR | ADC_STATE_NM_BUSY + | ADC_STATE_IST_BUSY | ADC_STATE_BUSY_INTERNAL); + } + + ald_adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE); + return tmp_status; +} + +/** + * @brief Deinitialize the ADC peripheral registers to their default reset + * values. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_reset(adc_handle_t *hperh) +{ + if (hperh == NULL) + return ERROR; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + ADC_DISABLE(hperh); + + ald_adc_clear_flag_status(hperh, ADC_FLAG_AWD); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_OVR); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); + + WRITE_REG(hperh->perh->CON0, 0x0); + WRITE_REG(hperh->perh->CON1, 0x0); + WRITE_REG(hperh->perh->CCR, 0x0); + WRITE_REG(hperh->perh->WDTH, 0xFFF); + WRITE_REG(hperh->perh->WDTL, 0x0); + WRITE_REG(hperh->perh->ICHOFF1, 0x0); + WRITE_REG(hperh->perh->ICHOFF2, 0x0); + WRITE_REG(hperh->perh->ICHOFF3, 0x0); + WRITE_REG(hperh->perh->ICHOFF4, 0x0); + WRITE_REG(hperh->perh->ICHS, 0x0); + WRITE_REG(hperh->perh->NCHS1, 0x0); + WRITE_REG(hperh->perh->NCHS2, 0x0); + WRITE_REG(hperh->perh->NCHS3, 0x0); + WRITE_REG(hperh->perh->NCHS4, 0x0); + WRITE_REG(hperh->perh->SMPT1, 0x0); + WRITE_REG(hperh->perh->SMPT2, 0x0); + WRITE_REG(hperh->perh->CHSL, 0x0); + + hperh->state = ADC_STATE_RESET; + hperh->error_code = ADC_ERROR_NONE; + return OK; +} +/** + * @} + */ + +/** @defgroup ADC_Public_Functions_Group2 IO operation functions + * @brief Input and Output operation functions + * @{ + */ + +/** + * @brief Enables ADC, starts conversion of normal group. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_start(adc_handle_t *hperh) +{ + if (hperh == NULL) + return ERROR; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + __LOCK(hperh); + ADC_ENABLE(hperh); + hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); + hperh->state |= ADC_STATE_NM_BUSY; + __UNLOCK(hperh); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); + + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + return OK; +} + +/** + * @brief Stop ADC conversion of normal group (and insert channels in + * case of auto_injection mode), disable ADC peripheral. + * @note: ADC peripheral disable is forcing stop of potential + * conversion on insert group. If insert group is under use, it + * should be preliminarily stopped using ald_adc_insert_stop function. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_stop(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + __LOCK(hperh); + + ADC_DISABLE(hperh); + hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_NM_EOC); + hperh->state |= ADC_STATE_READY; + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Wait for normal group conversion to be completed. + * @note This function cannot be used in a particular setup: ADC configured in DMA mode. + * In this case, DMA resets the flag EOC and polling cannot be performed on each conversion. + * @note When use this function,you should be pay attention to the hperh->init.reocs_mode, + * if it is ADC_REOCS_MODE_ALL, it means the function will wait all normal rank conversion finished. + * if it is ADC_REOCS_MODE_ONE, it means the funcion will wait every normal rank conversion finished. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param timeout: Timeout value in millisecond. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart = 0; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + tickstart = ald_get_tick(); + while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK))) { + if (timeout != ALD_MAX_DELAY ) { + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + hperh->state |= ADC_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); + + hperh->state |= ADC_STATE_NM_EOC; + + if ((hperh->init.cont_mode == DISABLE) && (hperh->init.scan_mode == DISABLE)) { + hperh->state &= ~ADC_STATE_NM_BUSY; + + if ((hperh->state & ADC_STATE_IST_BUSY) == 0) + hperh->state |= ADC_STATE_READY; + } + return OK; +} + +/** + * @brief Poll for conversion event. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param event_type: the ADC event type. + * This parameter can be one of the following values: + * ADC_awd_event: ADC Analog watchdog event. + * @param timeout: Timeout value in millisecond. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout) +{ + uint32_t tickstart = 0; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_EVENT_TYPE(event_type)); + + tickstart = ald_get_tick(); + + while (ald_adc_get_flag_status(hperh, (adc_flag_t)event_type) == RESET) { + if (timeout != ALD_MAX_DELAY ) { + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + hperh->state |= ADC_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + + hperh->state |= ADC_STATE_AWD; + return OK; +} + +/** + * @brief Enables ADC, starts conversion of normal group with interruption. + * Interruptions enabled in this function: + * - REOC (end of conversion of normal group) + * Each of these interruptions has its dedicated callback function. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + __LOCK(hperh); + ADC_ENABLE(hperh); + hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); + hperh->state |= ADC_STATE_NM_BUSY; + hperh->error_code = ADC_ERROR_NONE; + + if (READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)) { + hperh->state &= ~(ADC_STATE_IST_EOC); + hperh->state |= ADC_STATE_IST_BUSY; + } + + __UNLOCK(hperh); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); + ald_adc_interrupt_config(hperh, ADC_IT_NCH, ENABLE); + + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + return OK; +} + +/** + * @brief Stop ADC conversion of normal group (and insert group in + * case of auto_injection mode), disable interrution of + * end-of-conversion, disable ADC peripheral. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + __LOCK(hperh); + ADC_DISABLE(hperh); + ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE); + hperh->state |= ADC_STATE_READY; + hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); + + __UNLOCK(hperh); + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Enables ADC, starts conversion of normal group and transfers result + * through DMA. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param buf: The destination Buffer address. + * @param size: The length of data to be transferred from ADC peripheral to memory. + * @param channel: The DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) +{ + if ((hperh == NULL) || (buf == NULL) || (size == 0) || (channel > 5)) + return ERROR; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + __LOCK(hperh); + ADC_ENABLE(hperh); + hperh->state &= ~(ADC_STATE_READY | ADC_STATE_NM_EOC); + hperh->state |= ADC_STATE_NM_BUSY; + + if (READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)) { + hperh->state &= ~(ADC_STATE_IST_EOC); + hperh->state |= ADC_STATE_IST_BUSY; + } + + if ((hperh->state & ADC_STATE_IST_BUSY) != 0) { + hperh->state &= ~(ADC_STATE_ERROR); + hperh->error_code &= ~(ADC_ERROR_OVR | ADC_ERROR_DMA); + } + else { + hperh->state &= ~(ADC_STATE_ERROR); + hperh->error_code = ADC_ERROR_NONE; + } + __UNLOCK(hperh); + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; + + hperh->hdma.cplt_cbk = adc_dma_normal_conv_cplt; + hperh->hdma.cplt_arg = hperh; + hperh->hdma.err_cbk = adc_dma_error; + hperh->hdma.err_arg = hperh; + + ald_dma_config_struct(&hperh->hdma.config); + hperh->hdma.config.src = (void *)&hperh->perh->NCHDR; + hperh->hdma.config.dst = (void *)buf; + hperh->hdma.config.size = size; + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.msel = DMA_MSEL_ADC0; + hperh->hdma.config.msigsel = DMA_MSIGSEL_ADC; + hperh->hdma.config.burst = ENABLE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&hperh->hdma); + + MODIFY_REG(hperh->perh->CON1, ADC_CON1_DMA_MSK, 1 << ADC_CON1_DMA_POS); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + return OK; +} + +/** + * @brief Stop ADC conversion of normal group (and insert group in + * case of auto_insert mode), disable ADC DMA transfer, disable + * ADC peripheral. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t adc_stop_dma(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + __LOCK(hperh); + + ADC_DISABLE(hperh); + ald_pis_destroy(&hperh->hpis); + hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); + hperh->state |= ADC_STATE_READY; + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief DMA transfer complete callback. + * @param arg: argument of the call back. + * @retval None + */ +static void adc_dma_timer_trigger_cplt(void *arg) +{ + adc_timer_config_t *hperh = (adc_timer_config_t *)arg; + + ADC_DISABLE(&hperh->lh_adc); + ald_timer_base_stop(&hperh->lh_timer); + + __UNLOCK(hperh); + if (hperh->lh_adc.adc_reg_cplt_cbk != NULL) + hperh->lh_adc.adc_reg_cplt_cbk(&hperh->lh_adc); + +} + + +/** + * @brief Config Timer trigger adc function + * @param config: Pointer to a adc_timer_config_t structure that + * contains the configuration information for the specified function. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) +{ + __LOCK(config); + + config->lh_pis.perh = PIS; + config->lh_pis.init.producer_clk = PIS_CLK_PCLK1; + config->lh_pis.init.producer_edge = PIS_EDGE_NONE; + config->lh_pis.init.consumer_clk = PIS_CLK_PCLK2; + + #if defined(ES32F36xx) + if (config->p_timer == AD16C4T0) + config->lh_pis.init.producer_src = PIS_TIMER0_UPDATA; + else if (config->p_timer == AD16C4T1) + config->lh_pis.init.producer_src = PIS_TIMER1_UPDATA; + else if (config->p_timer == GP32C4T0) + config->lh_pis.init.producer_src = PIS_TIMER2_UPDATA; + else if (config->p_timer == GP32C4T1) + config->lh_pis.init.producer_src = PIS_TIMER3_UPDATA; + else + return ERROR; + #elif defined(ES32F39xx) || defined(ES32F336x) + if (config->p_timer == GP16C4T0) + config->lh_pis.init.producer_src = PIS_TIMER0_UPDATA; + else if (config->p_timer == GP16C4T1) + config->lh_pis.init.producer_src = PIS_TIMER1_UPDATA; + else if (config->p_timer == GP32C4T0) + config->lh_pis.init.producer_src = PIS_TIMER2_UPDATA; + else if (config->p_timer == GP32C4T1) + config->lh_pis.init.producer_src = PIS_TIMER3_UPDATA; + else + return ERROR; + #endif + + if (config->p_adc == ADC0) + config->lh_pis.init.consumer_trig = PIS_CH6_ADC0_REGULAT; + else + return ERROR; + + ald_pis_create(&config->lh_pis); + + /* Initialize TIMER0 */ + config->lh_timer.perh = config->p_timer; + config->lh_timer.init.prescaler = 0; + config->lh_timer.init.mode = TIMER_CNT_MODE_UP; + config->lh_timer.init.period = ((ald_cmu_get_pclk1_clock() / 1000000) * config->time); + config->lh_timer.init.clk_div = TIMER_CLOCK_DIV1; + config->lh_timer.init.re_cnt = 0; + ald_timer_base_init(&config->lh_timer); + + config->lh_adc.perh = config->p_adc; + config->lh_adc.init.data_align = ADC_DATAALIGN_RIGHT; + config->lh_adc.init.scan_mode = DISABLE; + config->lh_adc.init.cont_mode = DISABLE; + config->lh_adc.init.nch_len = ADC_NCH_LEN_1; + config->lh_adc.init.disc_mode = ADC_ALL_DISABLE; + config->lh_adc.init.disc_nbr = ADC_DISC_NBR_1; + config->lh_adc.init.conv_res = ADC_CONV_RES_12; + config->lh_adc.init.clk_div = ADC_CKDIV_16; + config->lh_adc.init.nche_sel = ADC_NCHESEL_MODE_ONE; + config->lh_adc.init.neg_ref = config->n_ref; + config->lh_adc.init.pos_ref = config->p_ref; + config->lh_adc.adc_reg_cplt_cbk = config->adc_cplt_cbk; + config->lh_adc.adc_inj_cplt_cbk = NULL; + config->lh_adc.adc_out_of_win_cbk = NULL; + config->lh_adc.adc_error_cbk = NULL; + config->lh_adc.adc_ovr_cbk = NULL; + ald_adc_init(&config->lh_adc); + + MODIFY_REG(config->lh_adc.perh->CON1, ADC_CON1_DMA_MSK, 1 << ADC_CON1_DMA_POS); + + config->lh_adc.perh->CON1 |= 0x10000000; + config->lnm_config.channel = config->adc_ch; + config->lnm_config.rank = ADC_NCH_RANK_1; + config->lnm_config.samp_time = ADC_SAMPLETIME_1; + ald_adc_normal_channel_config(&config->lh_adc, &config->lnm_config); + + config->lh_dma.cplt_cbk = adc_dma_timer_trigger_cplt; + config->lh_dma.cplt_arg = config; + config->lh_dma.err_cbk = adc_dma_error; + config->lh_dma.err_arg = &config->lh_adc; + + ald_dma_config_struct(&config->lh_dma.config); + config->lh_dma.perh = DMA0; + config->lh_dma.config.src = (void *)&config->lh_adc.perh->NCHDR; + config->lh_dma.config.dst = (void *)config->buf; + config->lh_dma.config.size = config->size; + config->lh_dma.config.data_width = DMA_DATA_SIZE_HALFWORD; + config->lh_dma.config.src_inc = DMA_DATA_INC_NONE; + config->lh_dma.config.dst_inc = DMA_DATA_INC_HALFWORD; + config->lh_dma.config.msel = config->p_adc == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1; + config->lh_dma.config.msigsel = DMA_MSIGSEL_ADC; + config->lh_dma.config.burst = ENABLE; + config->lh_dma.config.channel = config->dma_ch; + ald_dma_config_basic(&config->lh_dma); + + ADC_ENABLE(&config->lh_adc); + ald_timer_base_start(&config->lh_timer); + + return OK; +} +#endif + +/** + * @brief Get ADC normal group conversion result. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval ADC group normal conversion data + */ +uint32_t ald_adc_normal_get_value(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + hperh->state &= ~ADC_STATE_NM_EOC; + return hperh->perh->NCHDR; +} + +/** + * @brief Enables ADC, starts conversion of insert group. + * Interruptions enabled in this function: None. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_insert_start(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + __LOCK(hperh); + ADC_ENABLE(hperh); + hperh->state &= ~(ADC_STATE_READY | ADC_STATE_IST_EOC); + hperh->state |= ADC_STATE_IST_BUSY; + + if ((hperh->state & ADC_STATE_NM_BUSY) == 0) + hperh->error_code = ADC_ERROR_NONE; + + __UNLOCK(hperh); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); + + if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); + + return OK; +} + +/** + * @brief Stop conversion of insert channels. Disable ADC peripheral if + * no normal conversion is on going. + * @note If ADC must be disabled and if conversion is on going on + * normal group, function ald_adc_normal_stop must be used to stop both + * insert and normal groups, and disable the ADC. + * @note If insert group mode auto-injection is enabled, + * function ald_adc_normal_stop must be used. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_insert_stop(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + __LOCK(hperh); + + if (((hperh->state & ADC_STATE_NM_BUSY) == 0) + && (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))) { + ADC_DISABLE(hperh); + hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY | ADC_STATE_IST_EOC); + hperh->state |= ADC_STATE_READY; + } + else { + hperh->state |= ADC_STATE_ERROR; + __UNLOCK(hperh); + return ERROR; + } + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Wait for insert group conversion to be completed. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param timeout: Timeout value in millisecond. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + tickstart = ald_get_tick(); + + while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_ICHE_MSK))) { + if (timeout != ALD_MAX_DELAY) { + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + hperh->state |= ADC_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + } + + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); + + hperh->state |= ADC_STATE_IST_EOC; + + hperh->state &= ~(ADC_STATE_IST_BUSY); + if ((hperh->state & ADC_STATE_NM_BUSY) == 0) + hperh->state |= ADC_STATE_READY; + + hperh->state &= ~(ADC_STATE_TIMEOUT); + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Enables ADC, starts conversion of insert group with interruption. + * - JEOC (end of conversion of insert group) + * Each of these interruptions has its dedicated callback function. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t.. + */ +ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + __LOCK(hperh); + ADC_ENABLE(hperh); + hperh->state &= ~(ADC_STATE_READY | ADC_STATE_IST_EOC); + hperh->state |= ADC_STATE_IST_BUSY; + + if ((hperh->state & ADC_STATE_NM_BUSY) == 0) + hperh->error_code = ADC_ERROR_NONE; + + __UNLOCK(hperh); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, ENABLE); + + if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); + + return OK; +} + +/** + * @brief Stop conversion of insert channels, disable interruption of + * end-of-conversion. Disable ADC peripheral if no normal conversion + * is on going. + * @note If ADC must be disabled and if conversion is on going on + * normal group, function ald_adc_normal_stop must be used to stop both + * insert and normal groups, and disable the ADC. + * @note If insert group mode auto-injection is enabled, + * function ald_adc_normal_stop must be used. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval None + */ +ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + __LOCK(hperh); + + if (((hperh->state & ADC_STATE_NM_BUSY) == 0) + && (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))) { + ADC_DISABLE(hperh); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); + hperh->state &= ~(ADC_STATE_NM_BUSY | ADC_STATE_IST_BUSY); + hperh->state |= ADC_STATE_READY; + } + else { + ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); + hperh->state |= ADC_STATE_ERROR; + __UNLOCK(hperh); + return ERROR; + } + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Get ADC insert group conversion result. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param ih_rank: the converted ADC insert rank. + * This parameter can be one of the following values: + * @arg ADC_INJ_RANK_1: insert Channel1 selected + * @arg ADC_INJ_RANK_2: insert Channel2 selected + * @arg ADC_INJ_RANK_3: insert Channel3 selected + * @arg ADC_INJ_RANK_4: insert Channel4 selected + * @retval ADC group insert conversion data + */ +uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_rank_t ih_rank) +{ + uint32_t tmp; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_ICH_RANK_TYPE(ih_rank)); + + switch (ih_rank) { + case ADC_ICH_RANK_1: + tmp = hperh->perh->ICHDR1; + break; + case ADC_ICH_RANK_2: + tmp = hperh->perh->ICHDR2; + break; + case ADC_ICH_RANK_3: + tmp = hperh->perh->ICHDR3; + break; + case ADC_ICH_RANK_4: + tmp = hperh->perh->ICHDR4; + break; + default: + break; + } + + return tmp; +} + +/** + * @brief Handles ADC interrupt request + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval None + */ +void ald_adc_irq_handler(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + if (ald_adc_get_it_status(hperh, ADC_IT_NCH) && ald_adc_get_flag_status(hperh, ADC_FLAG_NCH)) { + if ((hperh->state & ADC_STATE_ERROR) == 0) + hperh->state |= ADC_STATE_NM_EOC; + + if (hperh->init.cont_mode == DISABLE) { + ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE); + hperh->state &= ~(ADC_STATE_NM_BUSY); + + if ((hperh->state & ADC_STATE_IST_BUSY) == 0) + hperh->state |= ADC_STATE_READY; + } + + if (hperh->adc_reg_cplt_cbk != NULL) + hperh->adc_reg_cplt_cbk(hperh); + + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_NCH); + } + + if (ald_adc_get_it_status(hperh, ADC_IT_ICH) && ald_adc_get_flag_status(hperh, ADC_FLAG_ICH)) { + if ((hperh->state & ADC_STATE_ERROR) == 0) + hperh->state |= ADC_STATE_IST_EOC; + + if ((!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) && (hperh->init.cont_mode == DISABLE)) { + ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); + hperh->state &= ~(ADC_STATE_IST_BUSY); + + if ((hperh->state & ADC_STATE_NM_BUSY) == 0) + hperh->state |= ADC_STATE_READY; + } + if (hperh->adc_inj_cplt_cbk != NULL) + hperh->adc_inj_cplt_cbk(hperh); + + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICHS); + ald_adc_clear_flag_status(hperh, ADC_FLAG_ICH); + } + + if (ald_adc_get_it_status(hperh, ADC_IT_AWD) && ald_adc_get_flag_status(hperh, ADC_FLAG_AWD)) { + hperh->state |= ADC_STATE_AWD; + + if (hperh->adc_out_of_win_cbk != NULL) + hperh->adc_out_of_win_cbk(hperh); + + ald_adc_clear_flag_status(hperh, ADC_FLAG_AWD); + } + + if (ald_adc_get_it_status(hperh, ADC_IT_OVR) && ald_adc_get_flag_status(hperh, ADC_FLAG_OVR)) { + ald_adc_clear_flag_status(hperh, ADC_FLAG_OVR); + hperh->error_code |= ADC_ERROR_OVR; + hperh->state |= ADC_STATE_ERROR; + + if (hperh->adc_ovr_cbk != NULL) + hperh->adc_ovr_cbk(hperh); + } +} + +/** + * @} + */ + +/** @defgroup ADC_Public_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ + +/** + * @brief Configures the the selected channel to be linked to the normal + * group. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param config: Structure of ADC channel for normal group. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); + assert_param(IS_ADC_NCH_RANK_TYPE(config->rank)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp_time)); + + __LOCK(hperh); + + if (config->rank <= ADC_NCH_RANK_4 ) { + hperh->perh->NCHS1 &= ~(0x1f << ((config->rank - 1) << 3)); + hperh->perh->NCHS1 |= (config->channel << ((config->rank - 1) << 3)); + } + else if (config->rank <= ADC_NCH_RANK_8) { + hperh->perh->NCHS2 &= ~(0x1f << ((config->rank - 5) << 3)); + hperh->perh->NCHS2 |= (config->channel << ((config->rank - 5) << 3)); + } + else if (config->rank <= ADC_NCH_RANK_12) { + hperh->perh->NCHS3 &= ~(0x1f << ((config->rank - 9) << 3)); + hperh->perh->NCHS3 |= (config->channel << ((config->rank - 9) << 3)); + } + else { + hperh->perh->NCHS4 &= ~(0x1f << ((config->rank - 13) << 3)); + hperh->perh->NCHS4 |= (config->channel << ((config->rank - 13) << 3)); + } + + if (config->channel < 8) { + hperh->perh->SMPT1 &= ~(0x0f << (config->channel << 2)); + hperh->perh->SMPT1 |= config->samp_time << (config->channel << 2); + } + else if (config->channel < 16) { + hperh->perh->SMPT2 &= ~(0x0f << ((config->channel - 8) << 2)); + hperh->perh->SMPT2 |= config->samp_time << ((config->channel - 8) << 2); + } + else { + hperh->perh->SMPT3 &= ~(0x0f << ((config->channel - 16) << 2)); + hperh->perh->SMPT3 |= config->samp_time << ((config->channel - 16) << 2); + } + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Configures the the selected channel to be linked to the insert + * group. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param config: Structure of ADC channel for insert group. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config) +{ + uint8_t tmp1, tmp2; + ald_status_t tmp_status = OK; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); + assert_param(IS_ADC_ICH_RANK_TYPE(config->rank)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp_time)); + assert_param(IS_ADC_IST_OFFSET_TYPE(config->offset)); + assert_param(IS_ADC_NBR_OF_IST_TYPE(config->ich_len)); + + __LOCK(hperh); + + if (hperh->init.scan_mode == DISABLE) { + switch (config->rank) { + case ADC_ICH_RANK_1: + MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS1_MSK, config->channel << ADC_ICHS_IS1_POSS); + break; + case ADC_ICH_RANK_2: + MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS2_MSK, config->channel << ADC_ICHS_IS2_POSS); + break; + case ADC_ICH_RANK_3: + MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS3_MSK, config->channel << ADC_ICHS_IS3_POSS); + break; + case ADC_ICH_RANK_4: + MODIFY_REG(hperh->perh->ICHS, ADC_ICHS_IS4_MSK, config->channel << ADC_ICHS_IS4_POSS); + break; + default: + hperh->state |= ADC_STATE_ERROR; + hperh->error_code |= ADC_ERROR_INTERNAL; + tmp_status = ERROR; + break; + } + } + else { + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->ich_len << ADC_CHSL_ISL_POSS); + tmp1 = config->rank ; + tmp2 = config->ich_len; + + if (tmp1 <= tmp2) { + hperh->perh->ICHS &= ~(0x1f << ((tmp1 - 1) << 3)); + hperh->perh->ICHS |= config->channel + << ((tmp1 - 1) << 3); + } + else { + hperh->perh->ICHS &= ~(0x1f << ((tmp1 - 1) << 3)); + hperh->perh->ICHS |= config->channel + << ((tmp1 - 1) << 3); + } + } + + if (config->auto_inj == ENABLE) + SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); + + if (hperh->init.disc_mode == ADC_ICH_DISC_EN) { + if (config->auto_inj == DISABLE) { + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->ich_len << ADC_CHSL_ISL_POSS); + SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + } + else { + hperh->state |= ADC_STATE_ERROR; + hperh->error_code |= ADC_ERROR_INTERNAL; + tmp_status = ERROR; + } + } + + if (config->channel < 8) { + hperh->perh->SMPT1 &= ~(0x03 << (config->channel << 2)); + hperh->perh->SMPT1 |= config->samp_time << (config->channel << 2); + } + else if (config->channel < 16) { + hperh->perh->SMPT2 &= ~(0x03 << ((config->channel - 8) << 2)); + hperh->perh->SMPT2 |= config->samp_time << ((config->channel - 8) << 2); + } + else { + hperh->perh->SMPT3 &= ~(0x03 << ((config->channel - 16) << 2)); + hperh->perh->SMPT3 |= config->samp_time << ((config->channel - 16) << 2); + } + + switch (config->rank) { + case ADC_ICH_RANK_1: + hperh->perh->ICHOFF1 = config->offset; + break; + case ADC_ICH_RANK_2: + hperh->perh->ICHOFF2 = config->offset; + break; + case ADC_ICH_RANK_3: + hperh->perh->ICHOFF3 = config->offset; + break; + case ADC_ICH_RANK_4: + hperh->perh->ICHOFF4 = config->offset; + break; + default: + break; + } + + __UNLOCK(hperh); + return tmp_status; +} + +/** + * @brief Configures the analog watchdog. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param config: Structure of ADC analog watchdog configuration + * @retval ALD status + */ +ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config) +{ + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_ANALOG_WTD_MODE_TYPE(config->watchdog_mode)); + assert_param(IS_FUNC_STATE(config->it_mode)); + assert_param(IS_HTR_TYPE(config->high_threshold)); + assert_param(IS_LTR_TYPE(config->low_threshold)); + + __LOCK(hperh); + + if ((config->watchdog_mode == ADC_ANAWTD_SING_NM) + || (config->watchdog_mode == ADC_ANAWTD_SING_IST) + || (config->watchdog_mode == ADC_ANAWTD_SING_NMIST)) + assert_param(IS_ADC_CHANNELS_TYPE(config->channel)); + + if (config->it_mode == DISABLE) + ald_adc_interrupt_config(hperh, ADC_IT_AWD, DISABLE); + else + ald_adc_interrupt_config(hperh, ADC_IT_AWD, ENABLE); + + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHWDTEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHWDEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK); + hperh->perh->CON0 |= config->watchdog_mode; + + if (READ_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK)) + MODIFY_REG(hperh->perh->CON0, ADC_CON0_AWDCH_MSK, config->channel << ADC_CON0_AWDCH_POSS); + + WRITE_REG(hperh->perh->WDTL, config->low_threshold); + WRITE_REG(hperh->perh->WDTH, config->high_threshold); + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param hperh: Pointer to a adc_handle_t structure. + * @param it: Specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref adc_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->CON0, it); + else + CLEAR_BIT(hperh->perh->CON0, it); + + return; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param hperh: Pointer to a adc_handle_t structure. + * @param it: Specifies the ADC interrupt source to check. + * This parameter can be one of the @ref adc_it_t. + * @retval Status + * - SET + * - RESET + */ +it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_IT_TYPE(it)); + + if (READ_BIT(hperh->perh->CON0, it)) + return SET; + + return RESET; +} + +/** @brief Check whether the specified ADC flag is set or not. + * @param hperh: Pointer to a adc_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref adc_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_FLAGS_TYPE(flag)); + + if (READ_BIT(hperh->perh->STAT, flag)) + return SET; + + return RESET; +} + +/** @brief Clear the specified ADC pending flags. + * @param hperh: Pointer to a adc_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref adc_flag_t. + * @retval None + */ +void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_FLAGS_TYPE(flag)); + + WRITE_REG(hperh->perh->CLR, flag); + return; +} +/** + * @} + */ + +/** @defgroup ADC_Public_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ + +/** + * @brief return the ADC state + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval state + */ +uint32_t ald_adc_get_state(adc_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the ADC error code + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval ADC Error Code + */ +uint32_t ald_adc_get_error(adc_handle_t *hperh) +{ + return hperh->error_code; +} + +/** + *@} + */ + +/** + *@} + */ + +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +#ifdef ALD_DMA +/** + * @brief DMA transfer complete callback. + * @param arg: argument of the call back. + * @retval None + */ +static void adc_dma_normal_conv_cplt(void *arg) +{ + adc_handle_t *hperh = (adc_handle_t *)arg; + + if (hperh->adc_reg_cplt_cbk != NULL) + hperh->adc_reg_cplt_cbk(hperh); + +} + +/** + * @brief DMA error callback + * @param arg: argument of the call back. + * @retval None + */ +static void adc_dma_error(void *arg) +{ + adc_handle_t *hperh = (adc_handle_t *)arg; + hperh->state |= ADC_STATE_ERROR; + hperh->error_code |= ADC_ERROR_DMA; + + if (hperh->adc_error_cbk != NULL) + hperh->adc_error_cbk(hperh); +} +#endif +/** + *@} + */ + +#endif /* ALD_ADC */ + +/** + *@} + */ + +/** + *@} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c new file mode 100644 index 0000000000000000000000000000000000000000..f050818ee4bd4dc9c555ecf72cd975fd53b8c6dc --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_bkpc.c @@ -0,0 +1,162 @@ +/** + ********************************************************************************* + * + * @file ald_bkpc.c + * @brief BKPC module driver. + * + * @version V1.0 + * @date 15 Dec 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_bkpc.h" +#include "ald_rtc.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup BKPC BKPC + * @brief BKPC module driver + * @{ + */ +#ifdef ALD_BKPC + +/** @defgroup BKPC_Public_Functions BKPC Public Functions + * @{ + */ + +/** @addtogroup BKPC_Public_Functions_Group1 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) ald_bkpc_ldo_config() API can configure LDO in backup field. + (+) ald_bkpc_bor_config() API can configure BOR in backup field. + + @endverbatim + * @{ + */ + +/** + * @brief Configure standby wakeup in backup field + * @param port: Wakeup port + * @param level: HIGH/LOW. + * @retval None + */ +void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level) +{ + assert_param(IS_BKPC_WAKEUP_PORT(port)); + assert_param(IS_BKPC_WAKEUP_LEVEL(level)); + + BKPC_UNLOCK(); + SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK); + MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS); + MODIFY_REG(BKPC->CR, BKPC_CR_WKPOL_MSK, level << BKPC_CR_WKPOL_POS); + BKPC_LOCK(); + + return; +} + +/** + * @brief Configure rtc clock in backup field + * @param clock: Clock + * @retval None + */ +void ald_bkpc_rtc_clock_config(bkpc_preh_clk_t clock) +{ + assert_param(IS_BKPC_PREH_CLOCK(clock)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, clock << BKPC_PCCR_RTCCS_POSS); + BKPC_LOCK(); + + return; +} + +/** + * @brief Configure tsense clock in backup field + * @param clock: Clock + * @retval None + */ +void ald_bkpc_tsense_clock_config(bkpc_preh_clk_t clock) +{ + assert_param(IS_BKPC_PREH_CLOCK(clock)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, clock << BKPC_PCCR_TSENSECS_POSS); + BKPC_LOCK(); + + return; +} +/** + * @} + */ + +/** @addtogroup BKPC_Public_Functions_Group2 IO operation functions + * @brief IO operation functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) ald_bkpc_write_ram() API can write data in backup ram. + (+) ald_bkpc_read_ram() API can read data from backup ram. + + @endverbatim + * @{ + */ + +/** + * @brief Write data into backup ram. + * @param idx: Index of backup word. + * @param value: Value which will be written to backup ram. + * @retval None + */ +void ald_bkpc_write_ram(uint8_t idx, uint32_t value) +{ + assert_param(IS_BKPC_RAM_IDX(idx)); + + RTC_UNLOCK(); + WRITE_REG(RTC->BKPR[idx], value); + RTC_LOCK(); + + return; +} + +/** + * @brief Read data from backup ram. + * @param idx: Index of backup word. + * @retval The data. + */ +uint32_t ald_bkpc_read_ram(uint8_t idx) +{ + assert_param(IS_BKPC_RAM_IDX(idx)); + + return READ_REG(RTC->BKPR[idx]); +} +/** + * @} + */ + +/** + * @} + */ +#endif /* ALD_BKPC */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c new file mode 100644 index 0000000000000000000000000000000000000000..e656bbdd7cbe955547940787825ebaa82e15e0fb --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_calc.c @@ -0,0 +1,121 @@ +/** + ********************************************************************************* + * + * @file ald_calc.c + * @brief CALC module driver. + * + * @version V1.0 + * @date 26 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_calc.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup CALC CALC + * @brief CALC module driver + * @{ + */ +#ifdef ALD_CALC + +/** @defgroup CALC_Public_Functions CALC Public Functions + * @brief Accelerating calculate functions + * + * @verbatim + ============================================================================== + ##### Accelerating calculate functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Square root operation. + (+) Division. + (+) Get DZ flag. + + @endverbatim + * @{ + */ + +/** + * @brief Square root operation. + * @param data: The data; + * @retval The value of square root. + */ +uint32_t ald_calc_sqrt(uint32_t data) +{ + WRITE_REG(CALC->RDCND, data); + while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK)); + + return READ_REG(CALC->SQRTRES); +} + +/** + * @brief Calculating division. + * @param dividend: The value of the dividend. + * @param divisor: The value of the divisor. + * @param remainder: The value of the remainder. + * @retval The result of division. + */ +uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder) +{ + CLEAR_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); + SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); + WRITE_REG(CALC->DIVDR, dividend); + WRITE_REG(CALC->DIVSR, divisor); + + while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK)); + + *remainder = READ_REG(CALC->DIVRR); + return READ_REG(CALC->DIVQR); +} + +/** + * @brief Calculating division. + * @param dividend: The value of the dividend. + * @param divisor: The value of the divisor. + * @param remainder: The value of the remainder. + * @retval The result of division. + */ +int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder) +{ + SET_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK); + SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK); + WRITE_REG(CALC->DIVDR, dividend); + WRITE_REG(CALC->DIVSR, divisor); + + while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK)); + + *remainder = READ_REG(CALC->DIVRR); + return READ_REG(CALC->DIVQR); +} + +/** + * @brief Get the flag of divisor is zero. + * @retval The status, SET/RESET. + */ +flag_status_t ald_calc_get_dz_status(void) +{ + if (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_DZ_MSK)) + return SET; + + return RESET; +} + +/** + * @} + */ +#endif /* ALD_CALC */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c new file mode 100644 index 0000000000000000000000000000000000000000..123d3719d565d5f502624879d673037c675ec27a --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_can.c @@ -0,0 +1,1048 @@ +/** + ****************************************************************************** + * @file ald_can.c + * @brief CAN module driver. + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * @version V1.0 + * @date 25 Apr 2019 + * @author AE Team + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the CAN controller interface clock. + (#) CAN pins configuration + (++) Enable the clock for the CAN GPIOs; + (++) Connect and configure the involved CAN pins using the + following function ald_gpio_init(); + (#) Initialise and configure the CAN using ald_can_init() function. + (#) Transmit the CAN frame using ald_can_send()/ald_can_send_by_it() function. + (#) Receive a CAN frame using ald_can_recv()/ald_can_recv_by_it function. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the CAN peripheral transmission and wait the end of this operation + using ald_can_send(), at this stage user can specify the value of timeout + according to his end application. + (+) Start the CAN peripheral reception and wait the end of this operation + using ald_can_recv(), at this stage user can specify the value of timeout + according to his end application + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the CAN peripheral transmission using ald_can_send_by_it() + (+) Start the CAN peripheral reception using ald_can_recv_by_it() + (+) Use ald_can_irq_handler() called under the used CAN Interrupt subroutine + (+) At CAN end of transmission pherh->tx_cplt_cbk() function is executed and user can + add his own code by customization of function pointer pherh->tx_cplt_cbk() + (+) In case of CAN Error, pherh->rx_cplt_cbk() function is executed and user can + add his own code by customization of function pointer pherh->rx_cplt_cbk() + + *** CAN ALD driver macros list *** + ============================================= + [..] + Below the list of most used macros in CAN driver. + + (+) CAN_RESET_HANDLE_STATE(): Reset CAN handle state. + (+) CAN_RX_MSG_PENDING(): Return the number of pending received messages. + (+) CAN_DBG_FREEZE(): Enable or disables the DBG Freeze for CAN. + + [..] + (@) You can refer to the CAN driver header file for used the macros + + @endverbatim + ****************************************************************************** + */ + +#include "ald_can.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup CAN CAN + * @brief CAN module driver + * @{ + */ +#ifdef ALD_CAN + +/** @addtogroup CAN_Private_Functions CAN Private Functions + * @{ + */ +static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num); +static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err); +static ald_status_t __can_recv_by_it(can_handle_t *hperh, uint8_t num); +/** + * @} + */ + +/** @defgroup CAN_Public_Functions CAN Public Functions + * @{ + */ + +/** @defgroup CAN_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + * @verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the CAN. + (+) Configures the CAN reception filter. + (+) Reset the CAN. + + @endverbatim + * @{ + */ + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_init_t. + * @param hperh: pointer to a can_handle_t structure that contains + * the configuration information for the specified CAN. + * @retval Status, see ald_status_t. + */ +ald_status_t ald_can_init(can_handle_t *hperh) +{ + uint32_t tickstart = 0; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_FUNC_STATE(hperh->init.ttcm)); + assert_param(IS_FUNC_STATE(hperh->init.abom)); + assert_param(IS_FUNC_STATE(hperh->init.awk)); + assert_param(IS_FUNC_STATE(hperh->init.abom)); + assert_param(IS_FUNC_STATE(hperh->init.rfom)); + assert_param(IS_FUNC_STATE(hperh->init.txmp)); + assert_param(IS_CAN_MODE(hperh->init.mode)); + assert_param(IS_CAN_SJW(hperh->init.sjw)); + assert_param(IS_CAN_BS1(hperh->init.seg1)); + assert_param(IS_CAN_BS2(hperh->init.seg2)); + assert_param(IS_CAN_PRESCALER(hperh->init.psc)); + + if (hperh->state == CAN_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = CAN_STATE_BUSY; + tickstart = ald_get_tick(); + + CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); + SET_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); + + while (!READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) { + if ((ald_get_tick() - tickstart) > CAN_TIMEOUT_VALUE) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + + return TIMEOUT; + } + } + + MODIFY_REG(hperh->perh->CON, CAN_CON_TTCEN_MSK, hperh->init.ttcm << CAN_CON_TTCEN_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_ABOFFEN_MSK, hperh->init.abom << CAN_CON_ABOFFEN_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_AWKEN_MSK, hperh->init.awk << CAN_CON_AWKEN_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_ARTXDIS_MSK, hperh->init.artx << CAN_CON_ARTXDIS_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_RXFOPM_MSK, hperh->init.rfom << CAN_CON_RXFOPM_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_TXMP_MSK, hperh->init.txmp << CAN_CON_TXMP_POS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_LOOP_MSK, (hperh->init.mode & 0x1) << CAN_BTIME_LOOP_POS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SILENT_MSK, ((hperh->init.mode >> 1) & 0x1) << CAN_BTIME_SILENT_POS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_RESJW_MSK, hperh->init.sjw << CAN_BTIME_RESJW_POSS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SEG1_MSK, hperh->init.seg1 << CAN_BTIME_SEG1_POSS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SEG2_MSK, hperh->init.seg2 << CAN_BTIME_SEG2_POSS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_BPSC_MSK, (hperh->init.psc - 1) << CAN_BTIME_BPSC_POSS); + + CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); + tickstart = ald_get_tick(); + + while (READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) { + if ((ald_get_tick() - tickstart) > CAN_TIMEOUT_VALUE) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + + return TIMEOUT; + } + } + + hperh->err = CAN_ERROR_NONE; + hperh->state = CAN_STATE_READY; + + return OK; +} + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the can_filter_t. + * @param hperh: pointer to a can_handle_t structure. + * @param config: pointer to a can_filter_t structure that + * contains the filter configuration information. + * @retval Status, see ald_status_t. + */ +ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config) +{ + uint32_t pos; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_FILTER_NUMBER(config->number)); + assert_param(IS_CAN_FILTER_MODE(config->mode)); + assert_param(IS_CAN_FILTER_SCALE(config->scale)); + assert_param(IS_CAN_FILTER_FIFO(config->fifo)); + assert_param(IS_FUNC_STATE(config->active)); + assert_param(IS_CAN_BANKNUMBER(config->bank_number)); + + pos = 1 << config->number; + + SET_BIT(hperh->perh->FLTCON, CAN_FLTCON_FLTINI_MSK); + CLEAR_BIT(hperh->perh->FLTGO, pos); + + if (config->scale == CAN_FILTER_SCALE_16) { + CLEAR_BIT(hperh->perh->FLTWS, pos); + hperh->perh->Filter[config->number].FLT1 = + ((0xFFFF & config->mask_id_low) << 16) | + (0xFFFF & config->id_low); + + hperh->perh->Filter[config->number].FLT2 = + ((0xFFFF & config->mask_id_high) << 16) | + (0xFFFF & config->id_high); + } + + if (config->scale == CAN_FILTER_SCALE_32) { + SET_BIT(hperh->perh->FLTWS, pos); + hperh->perh->Filter[config->number].FLT1 = + ((0xFFFF & config->id_high) << 16) | + (0xFFFF & config->id_low); + hperh->perh->Filter[config->number].FLT2 = + ((0xFFFF & config->mask_id_high) << 16) | + (0xFFFF & config->mask_id_low); + } + + MODIFY_REG(hperh->perh->FLTM, pos, config->mode << config->number); + MODIFY_REG(hperh->perh->FLTAS, pos, config->fifo << config->number); + MODIFY_REG(hperh->perh->FLTGO, pos, config->active << config->number); + CLEAR_BIT(hperh->perh->FLTCON, CAN_FLTCON_FLTINI_MSK); + + return OK; +} + +/** + * @brief Reset the CAN peripheral. + * @param hperh: pointer to a can_handle_t structure. + * @retval None + */ +void ald_can_reset(can_handle_t *hperh) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + + hperh->state = CAN_STATE_RESET; + __UNLOCK(hperh); + + return; +} + +/** + * @} + */ + +/** @defgroup CAN_Public_Functions_Group2 IO operation functions + * @brief I/O operation functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Send a CAN frame message. + (+) Send a CAN frame message using interrupt. + (+) Receive a CAN frame message. + (+) Receive a CAN frame message using interrupt. + + *@endverbatim + * @{ + */ + +/** + * @brief Send a CAN frame message. + * @param hperh: pointer to a can_handle_t structure. + * @param msg: message which will be sent. + * @param timeout: specify Timeout value + * @retval Status, see ald_status_t. + */ +ald_status_t ald_can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout) +{ + uint32_t tick; + can_tx_mailbox_t idx; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_IDTYPE(msg->type)); + assert_param(IS_CAN_RTR(msg->rtr)); + assert_param(IS_CAN_DATA_LEN(msg->len)); + + __LOCK(hperh); + SET_BIT(hperh->state, CAN_STATE_TX_MASK); + + if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) + idx = CAN_TX_MAILBOX_0; + else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) + idx = CAN_TX_MAILBOX_1; + else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) + idx = CAN_TX_MAILBOX_2; + else + idx = CAN_TX_MAILBOX_NONE; + + if (idx == CAN_TX_MAILBOX_NONE) { + hperh->state = CAN_STATE_ERROR; + __UNLOCK(hperh); + return ERROR; + } + + CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_IDE_MSK, msg->type << CAN_TXID0_IDE_POS); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_RTR_MSK, msg->rtr << CAN_TXID0_RTR_POS); + + if (msg->type == CAN_ID_STD) { + assert_param(IS_CAN_STDID(msg->std)); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, msg->std << CAN_TXID0_STDID_POSS); + CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK); + } + else { + assert_param(IS_CAN_EXTID(msg->ext)); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, ((msg->ext >> 18) & 0x7FF) << CAN_TXID0_STDID_POSS); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK, (msg->ext & 0x3FFFF) << CAN_TXID0_EXID_POSS); + } + MODIFY_REG(hperh->perh->TxMailBox[idx].TXFCON, CAN_TXFCON0_DLEN_MSK, (msg->len & 0xF) << CAN_TXFCON0_DLEN_POSS); + WRITE_REG(hperh->perh->TxMailBox[idx].TXDL, msg->data[0] | (msg->data[1] << 8) | (msg->data[2] << 16) | (msg->data[3] << 24)); + WRITE_REG(hperh->perh->TxMailBox[idx].TXDH, msg->data[4] | (msg->data[5] << 8) | (msg->data[6] << 16) | (msg->data[7] << 24)); + SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); + tick = ald_get_tick(); + + while (!(ald_can_get_tx_status(hperh, idx))) { + if ((timeout == 0) || ((ald_get_tick() - tick) > timeout)) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + + CLEAR_BIT(hperh->state, CAN_STATE_TX_MASK); + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Send a CAN frame message using interrupt. + * @param hperh: pointer to a can_handle_t structure. + * @param msg: message which will be sent. + * @retval Status, see ald_status_t. + */ +ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg) +{ + uint8_t idx = CAN_TX_MAILBOX_NONE; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_IDTYPE(msg->type)); + assert_param(IS_CAN_RTR(msg->rtr)); + assert_param(IS_CAN_DATA_LEN(msg->len)); + + if ((hperh->state != CAN_STATE_READY) && (hperh->state != CAN_STATE_BUSY_RX)) + return BUSY; + + if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) + idx = CAN_TX_MAILBOX_0; + else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) + idx = CAN_TX_MAILBOX_1; + else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) + idx = CAN_TX_MAILBOX_2; + else + idx = CAN_TX_MAILBOX_NONE; + + if (idx == CAN_TX_MAILBOX_NONE) + return BUSY; + + CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_IDE_MSK, msg->type << CAN_TXID0_IDE_POS); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_RTR_MSK, msg->rtr << CAN_TXID0_RTR_POS); + + if (msg->type == CAN_ID_STD) { + assert_param(IS_CAN_STDID(msg->std)); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, msg->std << CAN_TXID0_STDID_POSS); + CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK); + } + else { + assert_param(IS_CAN_EXTID(msg->ext)); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, ((msg->ext >> 18) & 0x7FF) << CAN_TXID0_STDID_POSS); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK, (msg->ext & 0x3FFFF) << CAN_TXID0_EXID_POSS); + } + + MODIFY_REG(hperh->perh->TxMailBox[idx].TXFCON, CAN_TXFCON0_DLEN_MSK, (msg->len & 0xF) << CAN_TXFCON0_DLEN_POSS); + WRITE_REG(hperh->perh->TxMailBox[idx].TXDL, msg->data[0] | (msg->data[1] << 8) | (msg->data[2] << 16) | (msg->data[3] << 24)); + WRITE_REG(hperh->perh->TxMailBox[idx].TXDH, msg->data[4] | (msg->data[5] << 8) | (msg->data[6] << 16) | (msg->data[7] << 24)); + + SET_BIT(hperh->state, CAN_STATE_TX_MASK); + + ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_TXM, ENABLE); + + SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); + return OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hperh: pointer to a can_handle_t structure. + * @param num: Receive fifo number, CAN_RX_FIFO0 or CAN_RX_FIFO1 + * @param msg: Storing message. + * @param timeout: Specify timeout value + * @retval Status, see ald_status_t. + */ +ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout) +{ + uint32_t tick, stid, exid; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_FIFO(num)); + + __LOCK(hperh); + SET_BIT(hperh->state, CAN_STATE_RX_MASK); + tick = ald_get_tick(); + + while (CAN_RX_MSG_PENDING(hperh, num) == 0) { + if ((timeout == 0) || ((ald_get_tick() - tick) > timeout)) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + + stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS); + exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS); + msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS); + + if (msg->type == CAN_ID_STD) + msg->std = stid; + else + msg->ext = (stid << 18) | exid; + + msg->rtr = (can_remote_req_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_RTR_MSK, CAN_RXF0ID_RTR_POS); + msg->len = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_DLEN_MSK, CAN_RXF0INF_DLEN_POSS); + msg->fmi = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_FLTIDX_MSK, CAN_RXF0INF_FLTIDX_POSS); + msg->data[0] = hperh->perh->RxFIFO[num].RXFDL & 0xFF; + msg->data[1] = (hperh->perh->RxFIFO[num].RXFDL >> 8) & 0xFF; + msg->data[2] = (hperh->perh->RxFIFO[num].RXFDL >> 16) & 0xFF; + msg->data[3] = (hperh->perh->RxFIFO[num].RXFDL >> 24) & 0xFF; + msg->data[4] = hperh->perh->RxFIFO[num].RXFDH & 0xFF; + msg->data[5] = (hperh->perh->RxFIFO[num].RXFDH >> 8) & 0xFF; + msg->data[6] = (hperh->perh->RxFIFO[num].RXFDH >> 16) & 0xFF; + msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF; + + can_rx_fifo_release(hperh, num); + CLEAR_BIT(hperh->state, CAN_STATE_RX_MASK); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receives a correct CAN frame using interrupt. + * @param hperh: pointer to a can_handle_t structure. + * @param num: Specify the FIFO number + * @param msg: Storing message. + * @retval Status, see ald_status_t. + */ +ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_FIFO(num)); + + if ((hperh->state != CAN_STATE_READY) && (hperh->state != CAN_STATE_BUSY_TX)) + return BUSY; + + SET_BIT(hperh->state, CAN_STATE_RX_MASK); + hperh->rx_msg = msg; + + ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); + + if (num == CAN_RX_FIFO0) + ald_can_interrupt_config(hperh, CAN_IT_FP0, ENABLE); + else + ald_can_interrupt_config(hperh, CAN_IT_FP1, ENABLE); + + return OK; +} +/** + * @} + */ + +/** @defgroup CAN_Public_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure CAN sleep. + (+) Configure CAN wakeup. + (+) CAN cancel send message. + (+) Handle CAN interrupt. + (+) Get CAN transmit status. + (+) Configure CAN interrupt ENABLE/DISABLE. + (+) Get CAN interrupt source status. + (+) Get CAN interrupt flag status. + (+) Clear CAN interrupt flag. + + * @endverbatim + * @{ + */ + +/** + * @brief Enters the Sleep(low power) mode. + * @param hperh: pointer to a can_handle_t. + * @retval Status, see ald_status_t. + */ +ald_status_t ald_can_sleep(can_handle_t *hperh) +{ + uint32_t tick; + + assert_param(IS_CAN_ALL(hperh->perh)); + + __LOCK(hperh); + hperh->state = CAN_STATE_BUSY; + + CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); + SET_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); + tick = ald_get_tick(); + + while ((!(READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK))) || READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) { + if ((ald_get_tick() - tick) > CAN_TIMEOUT_VALUE) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + + hperh->state = CAN_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral + * is in the normal mode. + * @param hperh: pointer to a can_handle_t structure. + * @retval Status, see ald_status_t. + */ +ald_status_t ald_can_wake_up(can_handle_t *hperh) +{ + uint32_t tick; + + assert_param(IS_CAN_ALL(hperh->perh)); + + __LOCK(hperh); + hperh->state = CAN_STATE_BUSY; + + CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); + tick = ald_get_tick(); + + while (READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK)) { + if ((ald_get_tick() - tick) > CAN_TIMEOUT_VALUE) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + + hperh->state = CAN_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Handles CAN interrupt request + * @param hperh: pointer to a can_handle_t structure. + * @retval None + */ +void ald_can_irq_handler(can_handle_t* hperh) +{ + if (ald_can_get_it_status(hperh, CAN_IT_TXM)) { + if ((ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_0)) + || (ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_1)) + || (ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_2))) + __can_send_by_it(hperh, 0); + if (hperh->perh->TXSTAT & CAN_TXSTAT_M0TXERR_MSK) { + SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M0REQC_MSK); + __can_send_by_it(hperh, 1); + } + if (hperh->perh->TXSTAT & CAN_TXSTAT_M1TXERR_MSK) { + SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M1REQC_MSK); + __can_send_by_it(hperh, 1); + } + if (hperh->perh->TXSTAT & CAN_TXSTAT_M2TXERR_MSK) { + SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M2REQC_MSK); + __can_send_by_it(hperh, 1); + } + } + + if ((ald_can_get_it_status(hperh, CAN_IT_FP0)) + && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO0) != 0)) + __can_recv_by_it(hperh, CAN_RX_FIFO0); + + if ((ald_can_get_it_status(hperh, CAN_IT_FP1)) + && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO1) != 0)) + __can_recv_by_it(hperh, CAN_RX_FIFO1); + + if ((ald_can_get_flag_status(hperh, CAN_FLAG_WARN)) + && (ald_can_get_it_status(hperh, CAN_IT_WARN)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) + hperh->err |= CAN_ERROR_EWG; + + if ((ald_can_get_flag_status(hperh, CAN_FLAG_PERR)) + && (ald_can_get_it_status(hperh, CAN_IT_PERR)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) + hperh->err |= CAN_ERROR_EPV; + + if ((ald_can_get_flag_status(hperh, CAN_FLAG_BOF)) + && (ald_can_get_it_status(hperh, CAN_IT_BOF)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) + hperh->err |= CAN_ERROR_BOF; + + if (READ_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK) + && (ald_can_get_it_status(hperh, CAN_IT_PRERR)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) { + + switch (READ_BITS(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK, CAN_ERRSTAT_PRERRF_POSS)) { + case(1): + hperh->err |= CAN_ERROR_STF; + break; + case(2): + hperh->err |= CAN_ERROR_FOR; + break; + case(3): + hperh->err |= CAN_ERROR_ACK; + break; + case(4): + hperh->err |= CAN_ERROR_BR; + break; + case(5): + hperh->err |= CAN_ERROR_BD; + break; + case(6): + hperh->err |= CAN_ERROR_CRC; + break; + default: + break; + } + + CLEAR_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK); + + if (READ_BIT(hperh->perh->IE, CAN_IE_TXMEIE_MSK)) + ald_can_interrupt_config(hperh, CAN_IT_TXM, DISABLE); + + if (READ_BIT(hperh->perh->IE, CAN_IE_F0PIE_MSK)) + ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE); + + if (READ_BIT(hperh->perh->IE, CAN_IE_F1PIE_MSK)) + ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE); + } + + if ((ald_can_get_flag_status(hperh, CAN_FLAG_ERR)) && (hperh->err == CAN_ERROR_NONE)) + hperh->err = CAN_ERROR_UNK; + + if (hperh->err != CAN_ERROR_NONE) { + SET_BIT(hperh->perh->IFC, CAN_IFC_ERRIFC_MSK); + hperh->state = CAN_STATE_READY; + + if (hperh->error_cbk != NULL) + hperh->error_cbk(hperh); + } +} + +/** + * @brief Check the transmission status of a CAN Frame. + * @param hperh: pointer to a can_handle_t structure. + * @param box: the index of the mailbox that is used for transmission. + * @retval The new status of transmission(TRUE or FALSE). + */ +type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_TX_MAILBOX(box)); + + switch (box) { + case CAN_TX_MAILBOX_0: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0REQC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0TXC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) + return FALSE; + + return TRUE; + + case CAN_TX_MAILBOX_1: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1REQC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1TXC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) + return FALSE; + + return TRUE; + + case CAN_TX_MAILBOX_2: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2REQC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2TXC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) + return FALSE; + + return TRUE; + + default: + break; + } + + return FALSE; +} + +/** + * @brief Cancel transmission. + * @param hperh: pointer to a can_handle_t structure. + * @param box: the index of the mailbox that is used for transmission. + * @retval None + */ +void ald_can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_TX_MAILBOX(box)); + + switch (box) { + case CAN_TX_MAILBOX_0: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0STPREQ_MSK); + break; + case CAN_TX_MAILBOX_1: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1STPREQ_MSK); + break; + case CAN_TX_MAILBOX_2: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2STPREQ_MSK); + break; + default: + break; + } + + return; +} + +/** + * @brief Enable/disable the specified CAN interrupts. + * @param hperh: Pointer to a can_handle_t structure. + * @param it: Specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref can_it_t. + * @param state: New state of the specified CAN interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->IE, it); + else + CLEAR_BIT(hperh->perh->IE, it); + + return; +} + +/** + * @brief Get the status of CAN interrupt source. + * @param hperh: Pointer to a can_handle_t structure. + * @param it: Specifies the CAN interrupt source. + * This parameter can be one of the @ref can_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_IT(it)); + + if (READ_BIT(hperh->perh->IE, it)) + return SET; + + return RESET; +} + +/** + * @brief Get the status of CAN interrupt flag. + * @param hperh: Pointer to a can_handle_t structure. + * @param flag: Specifies the CAN interrupt flag. + * This parameter can be one of the @ref can_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag) +{ + uint32_t idx = (flag >> 20) & 0x7; + uint32_t _flag = flag & 0xFF8FFFFF; + + assert_param(IS_CAN_GET_FLAG(flag)); + + switch (idx) { + case 0: + if (READ_BIT(hperh->perh->STAT, _flag)) + return SET; + + break; + case 1: + if (READ_BIT(hperh->perh->TXSTAT, _flag)) + return SET; + + break; + case 2: + if (READ_BIT(hperh->perh->RXF0, _flag)) + return SET; + + break; + case 3: + if (READ_BIT(hperh->perh->RXF1, _flag)) + return SET; + + break; + case 4: + if (READ_BIT(hperh->perh->ERRSTAT, _flag)) + return SET; + + break; + default: + break; + } + + return RESET; +} + +/** @brief Clear the specified CAN pending flag. + * @param hperh: pointer to a can_handle_t structure. + * @param flag: specifies the flag to check. + * @retval None. + */ +void ald_can_clear_flag_status(can_handle_t *hperh, can_flag_t flag) +{ + uint32_t idx = (flag >> 20) & 0x7; + uint32_t _flag = flag & 0xFF8FFFFF; + + assert_param(IS_CAN_CLEAR_FLAG(flag)); + + switch (idx) { + case 0: + WRITE_REG(hperh->perh->IFC, _flag); + break; + case 1: + WRITE_REG(hperh->perh->TXSTATC, _flag); + break; + case 2: + WRITE_REG(hperh->perh->RXF0C, _flag); + break; + case 3: + WRITE_REG(hperh->perh->RXF1C, _flag); + break; + default: + break; + } + + return; +} +/** + * @} + */ + +/** @defgroup CAN_Public_Functions_Group4 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * + * @verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to: + (+) Check the CAN state. + (+) Check CAN Errors detected during interrupt process + + * @endverbatim + * @{ + */ +/** + * @brief return the CAN state + * @param hperh: pointer to a can_handle_t structure. + * @retval Status, see can_state_t. + */ +can_state_t ald_can_get_state(can_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the CAN error code + * @param hperh: pointer to a can_handle_t structure. + * @retval CAN Error Code + */ +can_error_t ald_can_get_error(can_handle_t *hperh) +{ + return hperh->err; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Functions CAN Private Functions + * @{ + */ + +/** + * @brief Release rx FIFO + * @param hperh: pointer to a can_handle_t structure. + * @param num: Receive fifo number, CAN_RX_FIFO0 or CAN_RX_FIFO1 + * @retval None + */ +static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num) +{ + if (num == CAN_RX_FIFO0) + SET_BIT(hperh->perh->RXF0, CAN_RXF0_FREE_MSK); + else + SET_BIT(hperh->perh->RXF1, CAN_RXF1_FREE_MSK); +} + + +/** + * @brief transmits a CAN frame message using interrupt. + * @param hperh: pointer to a can_handle_t structure. + * @param err: Error code, 0 - success, 1 - error. + * @retval Status, see ald_status_t. + */ +static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err) +{ + ald_can_interrupt_config(hperh, CAN_IT_TXM, DISABLE); + + if (hperh->state == CAN_STATE_BUSY_TX) { + ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); + } + + CLEAR_BIT(hperh->state, CAN_STATE_TX_MASK); + + if ((err == 0) && (hperh->tx_cplt_cbk)) + hperh->tx_cplt_cbk(hperh); + + if ((err) && (hperh->error_cbk != NULL)) { + hperh->err = CAN_ERROR_UNK; + hperh->error_cbk(hperh); + } + + return OK; +} + +/** + * @brief Receives a correct CAN frame using interrupt. + * @param hperh: Pointer to a can_handle_t structure. + * @param num: Specify the FIFO number + * @retval Status, see ald_status_t. + */ +static ald_status_t __can_recv_by_it(can_handle_t *hperh, uint8_t num) +{ + uint32_t stid, exid; + + stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS); + exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS); + hperh->rx_msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS); + + if (hperh->rx_msg->type == CAN_ID_STD) + hperh->rx_msg->std = stid; + else + hperh->rx_msg->ext = (stid << 18) | exid; + + hperh->rx_msg->rtr = (can_remote_req_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_RTR_MSK, CAN_RXF0ID_RTR_POS); + hperh->rx_msg->len = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_DLEN_MSK, CAN_RXF0INF_DLEN_POSS); + hperh->rx_msg->fmi = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_FLTIDX_MSK, CAN_RXF0INF_FLTIDX_POSS); + hperh->rx_msg->data[0] = hperh->perh->RxFIFO[num].RXFDL & 0xFF; + hperh->rx_msg->data[1] = (hperh->perh->RxFIFO[num].RXFDL >> 8) & 0xFF; + hperh->rx_msg->data[2] = (hperh->perh->RxFIFO[num].RXFDL >> 16) & 0xFF; + hperh->rx_msg->data[3] = (hperh->perh->RxFIFO[num].RXFDL >> 24) & 0xFF; + hperh->rx_msg->data[4] = hperh->perh->RxFIFO[num].RXFDH & 0xFF; + hperh->rx_msg->data[5] = (hperh->perh->RxFIFO[num].RXFDH >> 8) & 0xFF; + hperh->rx_msg->data[6] = (hperh->perh->RxFIFO[num].RXFDH >> 16) & 0xFF; + hperh->rx_msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF; + + if (num == CAN_RX_FIFO0) { + can_rx_fifo_release(hperh, CAN_RX_FIFO0); + ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE); + } + else { + can_rx_fifo_release(hperh, CAN_RX_FIFO1); + ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE); + } + + if (hperh->state == CAN_STATE_BUSY_RX) { + ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); + } + + CLEAR_BIT(hperh->state, CAN_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + + return OK; +} +/** + * @} + */ + +#endif /* ALD_CAN */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c new file mode 100644 index 0000000000000000000000000000000000000000..0ae8b42619cb32674cbd79832855449e0126ec6b --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_cmu.c @@ -0,0 +1,1128 @@ +/** + ********************************************************************************* + * + * @file ald_cmu.c + * @brief CMU module driver. + * + * @version V1.0 + * @date 22 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + *** System clock configure *** + ================================= + [..] + (+) If you don't change system clock, you can using ald_cmu_clock_config_default() API. + It will select HRC as system clock. The system clock is 24MHz. + (+) If you want to change system clock, you can using ald_cmu_clock_config() API. + You can select one of the following as system clock: + @ref CMU_CLOCK_HRC 2MHz or 24MHz + @ref CMU_CLOCK_LRC 32768Hz + @ref CMU_CLOCK_LOSC 32768Hz + @ref CMU_CLOCK_PLL1 36MHz/48MHz/72MHz/96MHz + @ref CMU_CLOCK_HOSC 1MHz -- 24MHz + (+) If you select CMU_CLOCK_PLL1 as system clock, it must config the PLL1 + using ald_cmu_pll1_config() API. The input of clock must be 4MHz. + (+) If you get current clock, you can using ald_cmu_get_clock() API. + + *** BUS division control *** + =================================== + + MCLK sys_clk + -------DIV_SYS-----------+--------------------------System(Core, DMA, Systick ... etc.) + | + | hclk1 + +------DIV_AHB1------------Peripheral(GPIO, CRC, ... etc.) + | + | hclk2 + +------DIV_AHB2------------Peripheral(EBI, QSPI, ... etc.) + | + | pclk1 + +------DIV_APB1------------Peripheral(TIM, UART, ... etc.) + | + | pclk2 + +------DIV_APB2------------Peripheral(ADC, WWDT, ... etc.) + + [..] + (+) Configure the division using ald_cmu_div_config() API. + (+) Get sys_clk using ald_cmu_get_sys_clock() API. + (+) Get hclk1 using ald_cmu_get_hclk1_clock() API. + (+) Get pclk1 using ald_cmu_get_pclk1_clock() API. + (+) Get pclk2 using ald_cmu_get_pclk2_clock() API. + + *** Clock safe configure *** + =================================== + [..] + (+) If you select CMU_CLOCK_HOSC as system clock, you need enable + clock safe using ald_cmu_hosc_safe_config() API. It will change + CMU_CLOCK_HRC as system clock, when the outer crystal stoped. + (+) If you select CMU_CLOCK_LOSC as system clock, you need enable + clock safe using ald_cmu_losc_safe_config() API. It will change + CMU_CLOCK_LRC as system clock, when the outer crystal stoped. + (+) If you select CMU_CLOCK_PLL1 as system clock, you need enable + clock safe using ald_cmu_pll_safe_config() API. It will change + CMU_CLOCK_HRC as system clock, when the pll1 is lose. + (+) The ald_cmu_irq_cbk() will be invoked, when CMU interrupt has + been occurred. You can overwrite this function in application. + + *** Clock output configure *** + =================================== + [..] + (+) Output high-speed clock using ald_cmu_output_high_clock_config() API. + (+) Output low-speed clock using ald_cmu_output_low_clock_config() API. + + *** Peripheral clock configure *** + =================================== + [..] + (+) Configure buzz clock using ald_cmu_buzz_config() API. + (+) Selected lptim0 clock using ald_cmu_lptim0_clock_select() API. + (+) Selected lpuart clock using ald_cmu_lpuart0_clock_select() API. + (+) Selected lcd clock using ald_cmu_lcd_clock_select() API. + (+) Selected qspi clock using ald_cmu_qspi_clock_select() API. + (+) Configure usb clock using ald_cmu_usb_clock_config() API. + (+) Enable/Disable peripheral clock using ald_cmu_perh_clock_config() API. + (+) Selected stop1 clock using ald_cmu_stop1_clock_sel() API. + + *** CMU ALD driver macros list *** + ============================================= + [..] + Below the list of most used macros in CMU driver. + + (+) CMU_HRC_SEL_BY_SW(): HRC clock config by software. + (+) CMU_HRC_SEL_BY_CFGW(): HRC clock config by CFG Word. + (+) CMU_HRC_DIV_1MHZ_ENABLE(): Enable HRC divider to 1MHz. + (+) CMU_HRC_DIV_1MHZ_DISABLE(): Disable HRC divider to 1MHz. + (+) CMU_HOSC_DIV_1MHZ_ENABLE(): Enable HOSC divider to 1MHz. + (+) CMU_HOSC_DIV_1MHZ_DISABLE(): Disable HOSC divider to 1MHz. + (+) CMU_LOSC_ENABLE(): Enable outer low crystal(32768Hz). + (+) CMU_LOSC_DISABLE(): Disable outer low crystal(32768Hz). + (+) CMU_LRC_ENABLE(): Enable LRC(32768Hz). + (+) CMU_LRC_DISABLE(): Disable LRC(32768Hz). + (+) CMU_ULRC_ENABLE(): Enable ULRC(10KHz). + (+) CMU_ULRC_DISABLE(): Disable ULRC(10KHz). + (+) CMU_LP_LRC_ENABLE(): Enable low power LRC(32768Hz). + (+) CMU_LP_LRC_DISABLE(): Disable low power LRC(32768Hz). + (+) CMU_LP_LOSC_ENABLE(): Enable low power LOSC(32768Hz). + (+) CMU_LP_LOSC_DISABLE(): Disable low power LOSC(32768Hz). + (+) CMU_LP_HRC_ENABLE(): Enable low power HRC(2MHz or 24MHz). + (+) CMU_LP_HRC_DISABLE(): Disable low power HRC(2MHz OR 24MHz). + (+) CMU_LP_HOSC_ENABLE(): Enable low power HOSC(1MHz -- 24MHz). + (+) CMU_LP_HOSC_DISABLE(): Disable low power HOSC(1MHz -- 24MHz). + + [..] + (@) You can refer to the CMU driver header file for used the macros + + @endverbatim + ****************************************************************************** + */ + +#include "ald_cmu.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup CMU CMU + * @brief CMU module driver + * @{ + */ + +/** + * @defgroup CMU_Private_Variables CMU Private Variables + * @{ + */ +uint32_t __system_clock = 24000000; +/** + * @} + */ + +/** @defgroup CMU_Private_Functions CMU Private Functions + * @{ + */ + +/** + * @brief Update the current system clock. This function + * will be invoked, when system clock has changed. + * @param clock: The new clock. + * @retval None + */ + +static void cmu_clock_update(uint32_t clock) +{ + __system_clock = clock; + + if (clock > 1000000) + ald_tick_init(TICK_INT_PRIORITY); + + return; +} + +/** + * @brief CMU module interrupt handler + * @retval None + */ +void ald_cmu_irq_handler(void) +{ + /* HOSC stop */ + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); + SYSCFG_LOCK(); + + if ((READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) + || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) + cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); + ald_cmu_irq_cbk(CMU_HOSC_STOP); + } + + /* HOSC start */ + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK); + SYSCFG_LOCK(); + + if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))) + cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 1000000); + ald_cmu_irq_cbk(CMU_HOSC_START); + } + + /* LOSC stop */ + if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); + SYSCFG_LOCK(); + ald_cmu_irq_cbk(CMU_LOSC_STOP); + } + + /* LOSC start */ + if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK); + SYSCFG_LOCK(); + ald_cmu_irq_cbk(CMU_LOSC_START); + } + + /* PLL1 lose */ + if (READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK) && READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); + SYSCFG_LOCK(); + + if (READ_BIT(CMU->PULMCR, CMU_PULMCR_CLKS_MSK) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) + || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) + cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); + ald_cmu_irq_cbk(CMU_PLL1_UNLOCK); + } + + return; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions CMU Public Functions + * @{ + */ + +/** @defgroup CMU_Public_Functions_Group1 System clock configuration + * @brief System clock configuration functions + * + * @verbatim + ============================================================================== + ##### System clock Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure system clock using default parameters. + (+) Configure system clock using specified parameters. + (+) Configure PLL1 using specified parameters. + (+) Get system clock. + + @endverbatim + * @{ + */ + +/** + * @brief Configure system clock using default. + * Select CMU_CLOCK_HRC(24MHz) as system clock and + * enable CMU_CLOCK_LRC(32768Hz). + * @retval The status of ALD. + */ +ald_status_t ald_cmu_clock_config_default(void) +{ + uint32_t cnt = 4000, tmp; + + SYSCFG_UNLOCK(); + + /* Select HRC */ + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) { + SYSCFG_LOCK(); + return ERROR; + } + + WRITE_REG(CMU->CFGR, 0x0); + CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK); /* Select 24Mhz */ + + tmp = READ_REG(CMU->CLKENR); + /* Enable HRC/LRC/LOSC */ + SET_BIT(tmp, CMU_CLKENR_HRCEN_MSK | CMU_CLKENR_LRCEN_MSK | CMU_CLKENR_LOSCEN_MSK); + WRITE_REG(CMU->CLKENR, tmp); + /* Reset LRC */ + for (cnt = 0; cnt < 10000; ++cnt); + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); + + SYSCFG_LOCK(); + return OK; +} + +/** + * @brief Configure system clock using specified parameters + * @param clk: The parameter can be one of the following: + * @arg @ref CMU_CLOCK_HRC 2MHz or 24MHz + * @arg @ref CMU_CLOCK_LRC 32768Hz + * @arg @ref CMU_CLOCK_LOSC 32768Hz + * @arg @ref CMU_CLOCK_PLL1 One of @ref cmu_pll1_output_t + * @arg @ref CMU_CLOCK_HOSC 1MHz -- 24MHz + * @param clock: The clock which will be set. the value depends + * on the parameter of clk. + * @retval The status of ALD. + */ +ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock) +{ + uint32_t cnt = 4000; + + assert_param(IS_CMU_CLOCK(clk)); + SYSCFG_UNLOCK(); + + switch (clk) { + case CMU_CLOCK_HRC: + assert_param(clock == 24000000 || clock == 2000000); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) { + SYSCFG_LOCK(); + return ERROR; + } + + if (clock == 24000000) + CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); + else + SET_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); + + for (cnt = 4000; cnt; --cnt); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCRDY_MSK))) && (--cnt)); + + cmu_clock_update(clock); + break; + + case CMU_CLOCK_LRC: + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC) { + SYSCFG_LOCK(); + return ERROR; + } + + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); + + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt)); + + cmu_clock_update(32768); + break; + + case CMU_CLOCK_LOSC: + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LOSC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC) { + SYSCFG_LOCK(); + return ERROR; + } + + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); + + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCRDY_MSK))) && (--cnt)); + + cmu_clock_update(32768); + break; + + case CMU_CLOCK_PLL1: + MODIFY_REG(CMU->CSR, CMU_CSR_CFT_CMD_MSK, 0xAA << CMU_CSR_CFT_CMD_POSS); + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1) { + SYSCFG_LOCK(); + return ERROR; + } + + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); + + for (cnt = 0; cnt < 5000; ++cnt); + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1ACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); + + if (clock == 96000000) { + ald_cmu_div_config(CMU_HCLK_1, CMU_DIV_2); + ald_cmu_div_config(CMU_HCLK_2, CMU_DIV_2); + ald_cmu_div_config(CMU_PCLK_1, CMU_DIV_2); + ald_cmu_div_config(CMU_PCLK_2, CMU_DIV_4); + for (cnt = 0; cnt < 20000; ++cnt); + } + if (clock == 72000000) { + ald_cmu_div_config(CMU_PCLK_2, CMU_DIV_4); + } + if (clock == 48000000) { + ald_cmu_div_config(CMU_PCLK_2, CMU_DIV_2); + } + + cmu_clock_update(clock); + break; + + case CMU_CLOCK_HOSC: + assert_param(clock <= 24000000); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC) { + SYSCFG_LOCK(); + return ERROR; + } + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1); + + for (cnt = 8000; cnt; --cnt); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); + + cmu_clock_update(clock); + break; + + default: + break; + } + + SYSCFG_LOCK(); + return OK; +} + + + +/** + * @brief Configure PLL1 using specified parameters. + * @param input: The input clock type. + * @param output: The output clock which can be 36MHz/48MHz/72MHz/96MHz. + * When input = CMU_PLL1_INPUT_PLL2; then output must be + * CMU_PLL1_OUTPUT_36M, and then the real clock is (32768x1024)Hz. + * @retval None + */ +void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output) +{ + uint32_t cnt = 4000; + + assert_param(IS_CMU_PLL1_INPUT(input)); + assert_param(IS_CMU_PLL1_OUTPUT(output)); + + SYSCFG_UNLOCK(); + + if (input == CMU_PLL1_INPUT_HRC_6) { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); + } + else if (input == CMU_PLL1_INPUT_PLL2) { + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); + CLEAR_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2RFS_MSK); + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + } + else { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + for (cnt = 0; cnt < 10000; ++cnt); + cnt = 20000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); + } + + MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1RFS_MSK, input << CMU_PLLCFG_PLL1RFS_POSS); + MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1OS_MSK, output << CMU_PLLCFG_PLL1OS_POSS); + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); + + for (cnt = 0; cnt < 4000; ++cnt); + while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL1LCKN_MSK)) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); + + SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 0x3 << CMU_PULMCR_MODE_POSS); + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Gets current system clock. + * @retval The value of system clock. + */ +uint32_t ald_cmu_get_clock(void) +{ + return __system_clock; +} + +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group2 BUS division control + * @brief BUS division control functions + * + * @verbatim + ============================================================================== + ##### BUS division control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure the bus division. + (+) Get ahb1 clock. + (+) Get sys bus clock. + (+) Get apb1 clock. + (+) Get apb2 clock. + + @endverbatim + * @{ + */ + +/** + * @brief Configure the bus division. + * @param bus: The type of bus: + * @arg CMU_HCLK_1 + * @arg CMU_SYS + * @arg CMU_PCLK_1 + * @arg CMU_PCLK_2 + * @param div: The value of divider. + * @retval None + */ +void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div) +{ + assert_param(IS_CMU_BUS(bus)); + assert_param(IS_CMU_DIV(div)); + + SYSCFG_UNLOCK(); + + switch (bus) { + case CMU_HCLK_1: + MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS); + break; + + case CMU_HCLK_2: + MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK2DIV_MSK, div << CMU_CFGR_HCLK2DIV_POSS); + break; + + case CMU_SYS: + MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); + + if ((__system_clock >> div) <= 1000000) { + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + } + else { + ald_tick_init(TICK_INT_PRIORITY); + } + + break; + + case CMU_PCLK_1: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS); + break; + + case CMU_PCLK_2: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, div << CMU_CFGR_PCLK2DIV_POSS); + break; + + default: + break; + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Get AHB1 clock. + * @retval The value of AHB1 clock. + */ +uint32_t ald_cmu_get_hclk1_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, CMU_CFGR_HCLK1DIV_POSS); + + return (__system_clock >> sys_div) >> ahb_div; +} + +/** + * @brief Get SYS clock + * @retval The value of SYS clock + */ +uint32_t ald_cmu_get_sys_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + + return __system_clock >> sys_div; +} + +/** + * @brief Get APB1 clock. + * @retval The value of APB1 clock. + */ +uint32_t ald_cmu_get_pclk1_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t apb1_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, CMU_CFGR_PCLK1DIV_POSS); + + return (__system_clock >> sys_div) >> apb1_div; +} + +/** + * @brief Get APB2 clock. + * @retval The value of APB2 clock. + */ +uint32_t ald_cmu_get_pclk2_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t apb2_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, CMU_CFGR_PCLK2DIV_POSS); + + return (__system_clock >> sys_div) >> apb2_div; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group3 Clock safe configure + * @brief Clock safe configure functions + * + * @verbatim + ============================================================================== + ##### Clock safe configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable outer high crystal safe mode. + (+) Enable/Disable outer low crystal safe mode. + (+) Enable/Disable PLL1 safe mode. + (+) Interrupt callback function. + + @endverbatim + * @{ + */ + +/** + * @brief Enable/Disable outer high crystal safe mode. + * @param clock: the value of outer crystal frequency. + * @param status: The new status. + * @retval None + */ +void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) +{ + assert_param(IS_CMU_HOSC_RANGE(clock)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) { + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); + MODIFY_REG(CMU->HOSMCR, CMU_HOSMCR_FRQS_MSK, clock << CMU_HOSMCR_FRQS_POSS); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); + + ald_mcu_irq_config(CMU_IRQn, 3, 3, ENABLE); + } + else { + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); + + if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) + ald_mcu_irq_config(CMU_IRQn, 3, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Enable/Disable outer low crystal safe mode. + * @param status: The new status. + * @retval None + */ +void ald_cmu_losc_safe_config(type_func_t status) +{ + assert_param(IS_FUNC_STATE(status)); + SYSCFG_UNLOCK(); + + if (status) { + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); + + ald_mcu_irq_config(CMU_IRQn, 3, 3, ENABLE); + } + else { + CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); + CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); + + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) + ald_mcu_irq_config(CMU_IRQn, 3, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Enable/Disable PLL1 safe mode. + * @param status: The new status. + * @retval None + */ +void ald_cmu_pll_safe_config(type_func_t status) +{ + assert_param(IS_FUNC_STATE(status)); + SYSCFG_UNLOCK(); + + if (status) { + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); + MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS); + SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); + + ald_mcu_irq_config(CMU_IRQn, 3, 3, ENABLE); + } + else { + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); + + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0) + ald_mcu_irq_config(CMU_IRQn, 3, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Get clock state. + * @param sr: The state type, see @ref cmu_clock_state_t. + * @retval SET/RESET + */ +flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr) +{ + assert_param(IS_CMU_CLOCK_STATE(sr)); + + if (READ_BIT(CMU->CLKSR, sr)) + return SET; + + return RESET; +} + +/** + * @brief Interrupt callback function. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void ald_cmu_irq_cbk(cmu_security_t se) +{ + return; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group4 Clock output configure + * @brief Clock output configure functions + * + * @verbatim + ============================================================================== + ##### Clock output configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure the high-speed clock output. + (+) Configure the low-speed clock output. + + @endverbatim + * @{ + */ + +/** + * @brief Configure the high-speed clock output. + * @param sel: Select the source: + * @arg CMU_OUTPUT_HIGH_SEL_HOSC + * @arg CMU_OUTPUT_HIGH_SEL_LOSC + * @arg CMU_OUTPUT_HIGH_SEL_HRC + * @arg CMU_OUTPUT_HIGH_SEL_LRC + * @arg CMU_OUTPUT_HIGH_SEL_HOSM + * @arg CMU_OUTPUT_HIGH_SEL_PLL1 + * @arg CMU_OUTPUT_HIGH_SEL_PLL2 + * @arg CMU_OUTPUT_HIGH_SEL_SYSCLK + * @param div: The value of divider: + * @arg CMU_OUTPUT_DIV_1 + * @arg CMU_OUTPUT_DIV_2 + * @arg CMU_OUTPUT_DIV_4 + * @arg CMU_OUTPUT_DIV_8 + * @arg CMU_OUTPUT_DIV_16 + * @arg CMU_OUTPUT_DIV_32 + * @arg CMU_OUTPUT_DIV_64 + * @arg CMU_OUTPUT_DIV_128 + * @param status: The new status. + * @retval None + */ +void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, + cmu_output_high_div_t div, type_func_t status) +{ + assert_param(IS_CMU_OUTPUT_HIGH_SEL(sel)); + assert_param(IS_CMU_OUTPUT_HIGH_DIV(div)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) { + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCOS_MSK, sel << CMU_CLKOCR_HSCOS_POSS); + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCODIV_MSK, div << CMU_CLKOCR_HSCODIV_POSS); + SET_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); + } + else { + CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Configure the low-speed clock output. + * @param sel: Select the source: + * @arg CMU_OUTPUT_LOW_SEL_LOSC + * @arg CMU_OUTPUT_LOW_SEL_LRC + * @arg CMU_OUTPUT_LOW_SEL_LOSM + * @arg CMU_OUTPUT_LOW_SEL_BUZZ + * @arg CMU_OUTPUT_LOW_SEL_ULRC + * @param status: The new status. + * @retval None + */ +void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status) +{ + assert_param(IS_CMU_OUTPUT_LOW_SEL(sel)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) { + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_LSCOS_MSK, sel << CMU_CLKOCR_LSCOS_POSS); + SET_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); + } + else { + CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); + } + + SYSCFG_LOCK(); + return; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group5 Peripheral Clock configure + * @brief Peripheral clock configure functions + * + * @verbatim + ============================================================================== + ##### Peripheral clock configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure buzz clock. + (+) Select lptim0 clock source. + (+) Select lpuart0 clock source. + (+) Select lcd clock source. + (+) Enable/Disable peripheral clock. + + @endverbatim + * @{ + */ + +/** + * @brief Configure buzz clock. + * freq = sysclk / (2^(div + 1) * (dat + 1)) + * @param div: The value of divider. + * @param dat: The value of coefficient. + * @param status: The new status. + * @retval None + */ +void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status) +{ + assert_param(IS_CMU_BUZZ_DIV(div)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) { + MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS); + MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, dat << CMU_BUZZCR_DAT_POSS); + SET_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); + } + else { + CLEAR_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Select lptim0 clock source. + * @param clock: The clock source: + * @arg CMU_LP_PERH_CLOCK_SEL_PCLK2 + * @arg CMU_LP_PERH_CLOCK_SEL_PLL1 + * @arg CMU_LP_PERH_CLOCK_SEL_PLL2 + * @arg CMU_LP_PERH_CLOCK_SEL_HRC + * @arg CMU_LP_PERH_CLOCK_SEL_HOSC + * @arg CMU_LP_PERH_CLOCK_SEL_LRC + * @arg CMU_LP_PERH_CLOCK_SEL_LOSC + * @arg CMU_LP_PERH_CLOCK_SEL_ULRC + * @arg CMU_LP_PERH_CLOCK_SEL_HRC_1M + * @arg CMU_LP_PERH_CLOCK_SEL_HOSC_1M + * @arg CMU_LP_PERH_CLOCK_SEL_LOSM + * @arg CMU_LP_PERH_CLOCK_SEL_HOSM + * @retval None + */ +void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock) +{ + assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); + + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_LPTIM0_MSK, clock << CMU_PERICR_LPTIM0_POSS); + SYSCFG_LOCK(); + + return; +} + +/** + * @brief Select lpuart0 clock source. + * @param clock: The clock source: + * @arg CMU_LP_PERH_CLOCK_SEL_PCLK2 + * @arg CMU_LP_PERH_CLOCK_SEL_PLL1 + * @arg CMU_LP_PERH_CLOCK_SEL_PLL2 + * @arg CMU_LP_PERH_CLOCK_SEL_HRC + * @arg CMU_LP_PERH_CLOCK_SEL_HOSC + * @arg CMU_LP_PERH_CLOCK_SEL_LRC + * @arg CMU_LP_PERH_CLOCK_SEL_LOSC + * @arg CMU_LP_PERH_CLOCK_SEL_ULRC + * @arg CMU_LP_PERH_CLOCK_SEL_HRC_1M + * @arg CMU_LP_PERH_CLOCK_SEL_HOSC_1M + * @arg CMU_LP_PERH_CLOCK_SEL_LOSM + * @arg CMU_LP_PERH_CLOCK_SEL_HOSM + * @retval None + */ +void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock) +{ + assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); + + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_LPUART0_MSK, clock << CMU_PERICR_LPUART0_POSS); + SYSCFG_LOCK(); + + return; +} + +/** + * @brief Select lcd clock source. + * @param clock: The clock source: + * @arg CMU_LCD_SEL_LOSM + * @arg CMU_LCD_SEL_LOSC + * @arg CMU_LCD_SEL_LRC + * @arg CMU_LCD_SEL_ULRC + * @arg CMU_LCD_SEL_HRC_1M + * @arg CMU_LCD_SEL_HOSC_1M + * @retval None + */ +void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock) +{ + assert_param(IS_CMU_LCD_CLOCK_SEL(clock)); + + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_LCD_MSK, clock << CMU_PERICR_LCD_POSS); + SYSCFG_LOCK(); + + return; +} + +/** + * @brief Select QSPI clock source. + * @param clock: The clock source, see @ref cmu_qspi_clock_sel_t. + * @retval None + */ +void ald_cmu_qspi_clock_select(cmu_qspi_clock_sel_t clock) +{ + assert_param(IS_CMU_QSPI_CLOCK_SEL(clock)); + + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_QSPICS_MSK, clock << CMU_PERICR_QSPICS_POSS); + SYSCFG_LOCK(); + + return; +} + +/** + * @brief Configure USB clock source. + * @param clock: The clock source, see @ref cmu_usb_clock_sel_t. + * @param div: The clock division, see @ref cmu_usb_div_t. + * @retval None + */ +void ald_cmu_usb_clock_config(cmu_usb_clock_sel_t clock, cmu_usb_div_t div) +{ + assert_param(IS_CMU_USB_CLOCK_SEL(clock)); + assert_param(IS_CMU_USB_DIV(div)); + + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_USBPHYCS_MSK, clock << CMU_PERICR_USBPHYCS_POSS); + MODIFY_REG(CMU->PERIDIVR, CMU_PERIDIVR_USBPHYDIV_MSK, div << CMU_PERIDIVR_USBPHYDIV_POSS); + SYSCFG_LOCK(); + + return; +} + +/** + * @brief Enable/Disable peripheral clock. + * @param perh: The type of peripheral, you can see @ref cmu_perh_t + * @param status: The new status. + * @retval None + */ +void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status) +{ + uint32_t idx, pos; + + assert_param(IS_CMU_PERH(perh)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (perh == CMU_PERH_ALL) { + if (status) { + WRITE_REG(CMU->AHB1ENR, ~0); + WRITE_REG(CMU->APB1ENR, ~0); + WRITE_REG(CMU->APB2ENR, ~0); + } + else { + WRITE_REG(CMU->AHB1ENR, 0); + WRITE_REG(CMU->APB1ENR, 0); + WRITE_REG(CMU->APB2ENR, 0); + } + + SYSCFG_LOCK(); + return; + } + + idx = (perh >> 27) & 0x3; + pos = perh & ~(0x3 << 27); + + if (status) { + switch (idx) { + case 0: + SET_BIT(CMU->AHB1ENR, pos); + break; + + case 1: + SET_BIT(CMU->APB1ENR, pos); + break; + + case 2: + SET_BIT(CMU->APB2ENR, pos); + break; + + default: + break; + } + } + else { + switch (idx) { + case 0: + CLEAR_BIT(CMU->AHB1ENR, pos); + break; + + case 1: + CLEAR_BIT(CMU->APB1ENR, pos); + break; + + case 2: + CLEAR_BIT(CMU->APB2ENR, pos); + break; + + default: + break; + } + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Select stop1 clock. + * @param clock: See @ref cmu_stop1_clock_t + * @retval None + */ +void ald_cmu_stop1_clock_sel(cmu_stop1_clock_t clock) +{ + assert_param(IS_CMU_STOP1_CLOCK(clock)); + + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->LPENR, CMU_LPENR_STOP1CS_MSK, clock << CMU_LPENR_STOP1CS_POSS); + SYSCFG_LOCK(); + return; +} +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crc.c new file mode 100644 index 0000000000000000000000000000000000000000..ad0199a486f122172f57ffd336d49f0ec284eeb3 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crc.c @@ -0,0 +1,519 @@ +/** + ********************************************************************************* + * + * @file ald_crc.c + * @brief CRC module driver. + * + * @version V1.0 + * @date 18 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_crc.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC module driver + * @{ + */ +#ifdef ALD_CRC + +/** @addtogroup CRC_Private_Functions CRC Private Functions + * @{ + */ +void ald_crc_reset(crc_handle_t *hperh); +#ifdef ALD_DMA +static void crc_dma_calculate_cplt(void *arg); +static void crc_dma_error(void *arg); +#endif +/** + * @} + */ + + +/** @defgroup CRC_Public_Functions CRC Public Functions + * @{ + */ + +/** @defgroup CRC_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Initializes the CRC mode according to the specified parameters in + * the crc_handle_t and create the associated handle. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_init(crc_handle_t *hperh) +{ + uint32_t tmp = 0; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_CRC(hperh->perh)); + assert_param(IS_CRC_MODE(hperh->init.mode)); + assert_param(IS_FUNC_STATE(hperh->init.chs_rev)); + assert_param(IS_FUNC_STATE(hperh->init.data_inv)); + assert_param(IS_FUNC_STATE(hperh->init.data_rev)); + assert_param(IS_FUNC_STATE(hperh->init.chs_inv)); + + ald_crc_reset(hperh); + __LOCK(hperh); + + CRC_ENABLE(hperh); + + tmp = hperh->perh->CR; + + tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATREV_POS) | + (hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) | + (CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) | + (0 << CRC_CR_BYTORD_POS)); + + hperh->perh->CR = tmp; + hperh->perh->SEED = hperh->init.seed; + CRC_RESET(hperh); + + hperh->state = CRC_STATE_READY; + + __UNLOCK(hperh); + return OK; +} + +/** + * @} + */ + +/** @defgroup CRC_Public_Functions_Group2 Calculate functions + * @brief Calculate functions + * @{ + */ + +/** + * @brief Calculate the crc value of data by byte. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate + * @retval result, the result of a amount data + */ +uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); + hperh->state = CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + *((volatile uint8_t *)&(hperh->perh->DATA)) = buf[i]; + + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} + +/** + * @brief Calculate the crc value of data by halfword. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate,width is 2 bytes. + * @retval result, the result of a amount data + */ +uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); + hperh->state = CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + *((volatile uint16_t *)&(hperh->perh->DATA)) = buf[i]; + + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} + +/** + * @brief Calculate the crc value of data by word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate,width is 4 bytes + * @retval result, the result of a amount data + */ +uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); + hperh->state = CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + CRC->DATA = buf[i]; + + for (i = 0; i < 3; i++); + + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} + +/** + * @} + */ + +#ifdef ALD_DMA +/** @defgroup CRC_Public_Functions_Group3 DMA operation functions + * @brief DMA operation functions + * @{ + */ + +/** + * @brief Calculate an amount of data used dma channel + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param res: Pointer to result + * @param size: Amount of data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != CRC_STATE_READY) + return BUSY; + + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); + + hperh->state = CRC_STATE_BUSY; + + hperh->cal_buf = buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; + + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; + + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + hperh->hdma.config.burst = ENABLE; + ald_dma_config_basic(&(hperh->hdma)); + + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); + + return OK; +} + +/** + * @brief Calculate an amount of data used dma channel,data width is half-word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to half_word data buffer + * @param res: Pointer to result + * @param size: Amount of half_word data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != CRC_STATE_READY) + return BUSY; + + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); + + hperh->state = CRC_STATE_BUSY; + + hperh->cal_buf = (uint8_t *)buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; + + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; + + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + hperh->hdma.config.burst = ENABLE; + ald_dma_config_basic(&(hperh->hdma)); + + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); + + return OK; +} + +/** + * @brief Calculate an amount of data used dma channel,data width is word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to word data buffer + * @param res: Pointer to result + * @param size: Amount of word data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != CRC_STATE_READY) + return BUSY; + + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); + + hperh->state = CRC_STATE_BUSY; + + hperh->cal_buf = (uint8_t *)buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; + + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; + + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + hperh->hdma.config.burst = ENABLE; + ald_dma_config_basic(&(hperh->hdma)); + + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); + + return OK; +} + + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_dma_pause(crc_handle_t *hperh) +{ + __LOCK(hperh); + CRC_DMA_DISABLE(hperh); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_dma_resume(crc_handle_t *hperh) +{ + __LOCK(hperh); + CRC_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_dma_stop(crc_handle_t *hperh) +{ + __LOCK(hperh); + CRC_DMA_DISABLE(hperh); + __UNLOCK(hperh); + + hperh->state = CRC_STATE_READY; + return OK; +} + +/** + * @} + */ +#endif + +/** @defgroup CRC_Public_Functions_Group4 Peripheral State and Errors functions + * @brief CRC State and Errors functions + * @{ + */ + +/** + * @brief Returns the CRC state. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval CRC state + */ +crc_state_t ald_crc_get_state(crc_handle_t *hperh) +{ + assert_param(IS_CRC(hperh->perh)); + + return hperh->state; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Functions CRC Private Functions + * @brief CRC Private functions + * @{ + */ + +/** + * @brief Reset the CRC peripheral. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval None + */ +void ald_crc_reset(crc_handle_t *hperh) +{ + hperh->perh->DATA = 0x0; + hperh->perh->CR = 0x2; + hperh->perh->SEED = 0xFFFFFFFF; + + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); + return; +} + +#ifdef ALD_DMA +/** + * @brief DMA CRC calculate process complete callback. + * @param arg: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval None + */ +static void crc_dma_calculate_cplt(void *arg) +{ + crc_handle_t *hperh = (crc_handle_t *)arg; + + *(hperh->cal_res) = CRC->CHECKSUM; + CRC_DMA_DISABLE(hperh); + + hperh->state = CRC_STATE_READY; + + if (hperh->cal_cplt_cbk) + hperh->cal_cplt_cbk(hperh); +} + +/** + * @brief DMA CRC communication error callback. + * @param arg: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval None + */ +static void crc_dma_error(void *arg) +{ + crc_handle_t *hperh = (crc_handle_t *)arg; + + CRC_CLEAR_ERROR_FLAG(hperh); + CRC_DMA_DISABLE(hperh); + + hperh->state = CRC_STATE_READY; + + if (hperh->err_cplt_cbk) + hperh->err_cplt_cbk(hperh); +} +#endif +/** + * @} + */ +#endif /* ALD_CRC */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c new file mode 100644 index 0000000000000000000000000000000000000000..65fd6ce7d4e439a3ce0413d02c747d0008429c7c --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_crypt.c @@ -0,0 +1,1116 @@ +/** + ********************************************************************************* + * + * @file ald_crypt.c + * @brief CRYPT module driver. + * This is the common part of the CRYPT initialization + * + * @version V1.0 + * @date 19 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + + +#include "ald_crypt.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup CRYPT CRYPT + * @brief CRYPT module driver + * @{ + */ +#ifdef ALD_CRYPT + +/** @addtogroup CRYPT_Private_Functions CRYPT Private Functions + * @{ + */ +void crypt_reset(crypt_handle_t *hperh); +#ifdef ALD_DMA +static void crypt_dma_crypt_cplt(void *arg); +static void crypt_dma_error(void *arg); +#endif +/** + * @} + */ + + +/** @defgroup CRYPT_Public_Functions CRYPT Public Functions + * @{ + */ + +/** @defgroup CRYPT_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Initializes the CRYPT mode according to the specified parameters in + * the crypt_init_t and create the associated handle. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_init(crypt_handle_t *hperh) +{ + uint32_t tmp = 0; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_MODE(hperh->init.mode)); + assert_param(IS_CRYPT_KS(hperh->init.key)); + + if ((hperh->init.key == CRYPT_DES_KEYS_1 || hperh->init.key == CRYPT_DES_KEYS_2 || hperh->init.key == CRYPT_DES_KEYS_3) + && (hperh->init.mode == CRYPT_MODE_CTR)) { + return ERROR; + } + + __LOCK(hperh); + crypt_reset(hperh); + + if (hperh->state == CRYPT_STATE_RESET) + __UNLOCK(hperh); + + tmp = hperh->perh->CON; + switch (hperh->init.key) { + case CRYPT_AES_BITS_128: + tmp |= ((CRYPT_CRYSEL_AES << CRYPT_CON_CRYSEL_POS) | \ + (CRYPT_BITS_128 << CRYPT_CON_AESKS_POSS)); + hperh->step = 4; + break; + + case CRYPT_AES_BITS_192: + tmp |= ((CRYPT_CRYSEL_AES << CRYPT_CON_CRYSEL_POS) | \ + (CRYPT_BITS_192 << CRYPT_CON_AESKS_POSS)); + hperh->step = 4; + break; + + case CRYPT_AES_BITS_256: + tmp |= ((CRYPT_CRYSEL_AES << CRYPT_CON_CRYSEL_POS) | \ + (CRYPT_BITS_256 << CRYPT_CON_AESKS_POSS)); + hperh->step = 4; + break; + + case CRYPT_DES_KEYS_1: + SET_BIT(tmp, CRYPT_CON_CRYSEL_MSK); + hperh->step = 2; + break; + + case CRYPT_DES_KEYS_2: + SET_BIT(tmp, CRYPT_CON_CRYSEL_MSK); + tmp |= ((1 << CRYPT_CON_TDES_POS) | (CRYPT_KEYS_2 << CRYPT_CON_DESKS_POS)); + hperh->step = 2; + break; + + case CRYPT_DES_KEYS_3: + SET_BIT(tmp, CRYPT_CON_CRYSEL_MSK); + tmp |= ((1 << CRYPT_CON_TDES_POS) | (CRYPT_KEYS_3 << CRYPT_CON_DESKS_POS)); + hperh->step = 2; + break; + + default: + hperh->state = CRYPT_STATE_ERROR; + __UNLOCK(hperh); + return ERROR; + } + + tmp |= ((1 << CRYPT_CON_FIFOODR_POS) | (hperh->init.mode << CRYPT_CON_MODE_POSS) | \ + (hperh->init.type << CRYPT_CON_TYPE_POSS) | (1 << CRYPT_CON_FIFOEN_POS)); + hperh->perh->CON = tmp; + + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Write the Content of KEY. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param key: Pointer to key data buffer + * @param len: The length of key(32 bits) + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t * key, crypt_key_len_t len) +{ + uint32_t *temp = key; + uint32_t i; + + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; + + if ((hperh == NULL) || (key == NULL)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_KEY_LEN(len)); + + if ((hperh->init.key & 0xF) != len) + return ERROR; + + switch (len) { + case KEY_8_LEN: + hperh->perh->KEY[7] = *temp++; + hperh->perh->KEY[6] = *temp++; + + case KEY_6_LEN: + hperh->perh->KEY[5] = *temp++; + hperh->perh->KEY[4] = *temp++; + + case KEY_4_LEN: + hperh->perh->KEY[3] = *temp++; + hperh->perh->KEY[2] = *temp++; + + case KEY_2_LEN: + hperh->perh->KEY[1] = *temp++; + hperh->perh->KEY[0] = *temp; + break; + + default: + break; + } + + for (i = 0; i < len; i++) + hperh->key[i] = *key++; + + hperh->key_size = len; + + return OK; +} + +/** + * @brief Read the Content of KEY. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param key: Pointer to key data buffer + * @param len: The length of key(32 bits) + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t * key, crypt_key_len_t len) +{ + uint32_t *temp = key; + + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; + + if ((hperh == NULL) || (key == NULL)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_KEY_LEN(len)); + + switch (len) { + case KEY_8_LEN: + *temp++ = hperh->perh->KEY[7]; + *temp++ = hperh->perh->KEY[6]; + + case KEY_6_LEN: + *temp++ = hperh->perh->KEY[5]; + *temp++ = hperh->perh->KEY[4]; + + case KEY_4_LEN: + *temp++ = hperh->perh->KEY[3]; + *temp++ = hperh->perh->KEY[2]; + + case KEY_2_LEN: + *temp++ = hperh->perh->KEY[1]; + *temp = hperh->perh->KEY[0]; + break; + + default: + break; + } + + return OK; +} + +/** + * @brief Write the Content of IV if you use CBC mode + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param iv: Pointer to iv data buffer + * @param len: the length of iv(32 bits) + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t * iv, crypt_ivr_len_t len) +{ + uint32_t *temp = iv; + uint32_t i; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; + + if ((hperh == NULL) || (iv == NULL)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_IV_LEN(len)); + + switch (len) { + case IV_4_LEN: + hperh->perh->IV[3] = *temp++; + hperh->perh->IV[2] = *temp++; + + case IV_2_LEN: + hperh->perh->IV[1] = *temp++; + hperh->perh->IV[0] = *temp; + break; + + default: + break; + } + + for (i = 0; i < len; i++) + hperh->iv[i] = *iv++; + + hperh->iv_size = len; + + CRYPT_IVEN_ENABLE(hperh); + return OK; +} + +/** + * @brief Read the Content of IV. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param iv: Pointer to iv data buffer + * @param len: the length of iv(32 bits) + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv, crypt_ivr_len_t len) +{ + uint32_t *temp = iv; + + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; + + if ((hperh == NULL) || (iv == NULL)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_IV_LEN(len)); + + switch (len) { + case IV_4_LEN: + *temp++ = hperh->perh->IV[3]; + *temp++ = hperh->perh->IV[2]; + + case IV_2_LEN: + *temp++ = hperh->perh->IV[1]; + *temp = hperh->perh->IV[0]; + break; + + default: + break; + } + + return OK; +} + +/** + * @} + */ + +/** @defgroup CRYPT_Public_Functions_Group2 Encrypt or Decrypt functions + * @brief Encrypt or Decrypt functions + * @{ + */ + +/** + * @brief Encrypt an amount of data in blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param plain_text: Pointer to plain data buffer + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of plain data + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 8(des) or 16(ase) + */ +ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t * plain_text, uint8_t * cipher_text, uint32_t size) +{ + uint32_t count = 0; + uint32_t i; + uint32_t *plain_buf = (uint32_t *)plain_text; + uint32_t *cipher_buf = (uint32_t *)cipher_text; + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); + count = size / (4 * hperh->step); + + while (count--) { + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *plain_buf); + plain_buf++; + } + + while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); + + for (i = 0; i < hperh->step; i++) + *cipher_buf++ = CRYPT_READ_FIFO(hperh); + } + + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Decrypt an amount of data in blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param cipher_text: Pointer to cipher data buffer + * @param plain_text: Pointer to plain data buffer + * @param size: Amount of cipher data + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 8(des) or 16(ase) + */ +ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) +{ + uint32_t count = 0; + uint32_t i; + uint32_t *plain_buf = (uint32_t*)plain_text; + uint32_t *cipher_buf = (uint32_t*)cipher_text; + + if (hperh->init.mode == CRYPT_MODE_CTR) { + return ald_crypt_encrypt(hperh, cipher_text, plain_text, size); + } + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_DECRYPT); + count = size / (4 * hperh->step); + + while (count--) { + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *cipher_buf); + cipher_buf++; + } + + while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); + + for (i = 0; i < hperh->step; i++) + *plain_buf++ = CRYPT_READ_FIFO(hperh); + } + + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +void gcm_mul(uint32_t *res, uint32_t *data, uint32_t *iv) +{ + CRYPT->CON = 0; + CRYPT->DATA[0] = data[3]; + CRYPT->DATA[1] = data[2]; + CRYPT->DATA[2] = data[1]; + CRYPT->DATA[3] = data[0]; + CRYPT->IV[0] = iv[3]; + CRYPT->IV[1] = iv[2]; + CRYPT->IV[2] = iv[1]; + CRYPT->IV[3] = iv[0]; + CRYPT->CON |= ((1 << CRYPT_CON_RESCLR_POS) | (3 << CRYPT_CON_MODE_POSS) | \ + (1 << CRYPT_CON_GO_POS)); + + while (READ_BIT(CRYPT->IF, CRYPT_IF_MULTHIF_MSK) == 0); + + res[3] = CRYPT->RES[0]; + res[2] = CRYPT->RES[1]; + res[1] = CRYPT->RES[2]; + res[0] = CRYPT->RES[3]; + + SET_BIT(CRYPT->IFC, CRYPT_IFC_MULTHIFC_MSK); + return; +} + +/** + * @brief verify an amount of data in gcm mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of cipher data + * @param aadata: Pointer to additional authenticated data buffer + * @param alen: Amount of additional authenticated data + * @param tag: Pointer to authentication tag buffer + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag) +{ + uint8_t GCM_HASH_in[0x60] = {0} ; + uint8_t ecb[16] = {0} ; + uint32_t x_temp[4]; + uint64_t u, v; + uint32_t len = 0; + uint32_t j, i, k; + uint32_t *tag_temp, *cipher_text_temp; + + /* calculate u and v */ + u = 128 * ((size % 16) ? (size / 16 + 1) : size / 16) - size * 8; + v = 128 * ((alen % 16) ? (alen / 16 + 1): alen / 16) - alen * 8; + + /* get the input of GHASH algorithm,the input:A||0^v||C||0^u||[len(A)]_64||[len(C)]_64 */ + for (i = 0; i < alen; i++) { + GCM_HASH_in [i] = * (aadata + i); + } + len += alen; + for (i = 0; i < v / 8; i++) { + GCM_HASH_in[i + len] = 0; + } + len += v / 8; + for (i = 0; i < size; i++) { + GCM_HASH_in[i + len] = * (cipher_text + i); + } + len += size; + for (i = 0; i < u / 8; i++) { + GCM_HASH_in[i + len] = 0; + } + len += u / 8; + + for (i = 0; i < 4; i++) { + GCM_HASH_in[i + len] = 0; + } + len += 4; + + for (i = 0; i < 4; i++) { + GCM_HASH_in[i + len] = ((alen * 8) >> (8 * i)) & 0xFF; + } + len += 4; + + for (i = 0; i < 4; i++) { + GCM_HASH_in[i + len] = 0; + } + len += 4; + + for (i = 0; i < 4; i++) { + GCM_HASH_in[i + len] = ((size * 8) >> (8 * i)) & 0xFF; + } + len += 4; + + CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS); + CRYPT->CON |= (CRYPT_MODE_ECB << CRYPT_CON_MODE_POSS); + + ald_crypt_encrypt(hperh, ecb, ecb, 16); + + k = len / 16; + for (i = 0; i < 16; i++) { + tag[i] = 0; + } + + cipher_text_temp = (uint32_t *)GCM_HASH_in; + tag_temp = (uint32_t *)tag; + for (i = 0; i < k; i++) { + for (j = 0; j < 4; j++) { + x_temp[j] = (*cipher_text_temp) ^ tag_temp[j]; + ++cipher_text_temp; + } + + gcm_mul((uint32_t *)tag_temp, x_temp, (uint32_t *)ecb); + } + + /* calculate the authentication tag T, + * T = CIPH_K(J0)^S,J0=IV||0^31||1,CIPH_K is the algorithm of AES in ECB mode + */ + tag_temp = (uint32_t *)tag; + ald_crypt_init(hperh); + CRYPT->CON &= ~(3 << CRYPT_CON_MODE_POSS); + CRYPT->CON |= (CRYPT_MODE_CTR << CRYPT_CON_MODE_POSS); + ald_crypt_write_key(hperh, hperh->key, KEY_4_LEN); + hperh->iv[3] = 1; + ald_crypt_write_ivr(hperh, hperh->iv, IV_4_LEN); + ald_crypt_encrypt(hperh, tag, tag, 16); + + return OK; +} + +/** + * @brief Encrypt an amount of data in non-blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param plain_text: Pointer to plain data buffer + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of plain data + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 8(des) or 16(ase) + */ +ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t * plain_text, uint8_t *cipher_text, uint32_t size) +{ + uint32_t i; + uint32_t *plain_buf = (uint32_t *)plain_text; + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); + hperh->count = hperh->step; + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); + + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *plain_buf); + ++plain_buf; + } + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Decrypt an amount of data in non-blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param plain_text: Pointer to plain data buffer + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of cipher data + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 8(des) or 16(ase) + */ +ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) +{ + uint32_t i; + uint32_t *cipher_buf = (uint32_t*)cipher_text; + + if (hperh->init.mode == CRYPT_MODE_CTR) { + return ald_crypt_decrypt_by_it(hperh, cipher_text, plain_text, size); + } + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_DECRYPT); + hperh->count = hperh->step; + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); + + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *cipher_buf); + cipher_buf ++; + } + + __UNLOCK(hperh); + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Encrypt an amount of data in non-blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param plain_text: Pointer to plain data buffer + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of plain data + * @param channel_m2p: Memory to Crypt module DMA channel + * @param channel_p2m: Crypt module to Memory DMA channel + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 8(des) or 16(ase) + */ +ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t * plain_text, + uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) +{ + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if (plain_text == NULL || cipher_text == NULL || size == 0) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + hperh->count = size; + + if (hperh->hdma_m2p.perh == NULL) + hperh->hdma_m2p.perh = DMA0; + if (hperh->hdma_p2m.perh == NULL) + hperh->hdma_p2m.perh = DMA0; + + hperh->hdma_m2p.cplt_arg = NULL; + hperh->hdma_m2p.cplt_cbk = NULL; + hperh->hdma_m2p.err_arg = NULL; + hperh->hdma_m2p.err_cbk = NULL; + + hperh->hdma_p2m.cplt_arg = (void *)hperh; + hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt; + hperh->hdma_p2m.err_arg = (void *)hperh; + hperh->hdma_p2m.err_cbk = &crypt_dma_error; + + CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); + + ald_dma_config_struct(&hperh->hdma_m2p.config); + hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_m2p.config.src = (void *)hperh->plain_text; + hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; + hperh->hdma_m2p.config.size = size / 4; + hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; + hperh->hdma_m2p.config.burst = ENABLE; + hperh->hdma_m2p.config.channel = channel_m2p; + ald_dma_config_basic(&(hperh->hdma_m2p)); + + ald_dma_config_struct(&hperh->hdma_p2m.config); + hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; + hperh->hdma_p2m.config.dst = (void *)hperh->cipher_text; + hperh->hdma_p2m.config.size = size / 4; + hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD; + hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; + hperh->hdma_p2m.config.burst = ENABLE; + hperh->hdma_p2m.config.channel = channel_p2m; + ald_dma_config_basic(&(hperh->hdma_p2m)); + + CRYPT_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Decrypt an amount of data in non-blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param plain_text: Pointer to plain data buffer + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of cipher data + * @param channel_m2p: Memory to Crypt module DMA channel + * @param channel_p2m: Crypt module to Memory DMA channel + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 8(des) or 16(ase) + */ +ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t * cipher_text, + uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) +{ + if (hperh->init.mode == CRYPT_MODE_CTR) + return ald_crypt_decrypt_by_dma(hperh, cipher_text, plain_text, size, channel_m2p, channel_p2m); + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + if (plain_text == NULL || cipher_text == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + hperh->count = size; + + if (hperh->hdma_m2p.perh == NULL) + hperh->hdma_m2p.perh = DMA0; + if (hperh->hdma_p2m.perh == NULL) + hperh->hdma_p2m.perh = DMA0; + + + hperh->hdma_m2p.cplt_arg = NULL; + hperh->hdma_m2p.cplt_cbk = NULL; + hperh->hdma_m2p.err_arg = NULL; + hperh->hdma_m2p.err_cbk = NULL; + + hperh->hdma_p2m.cplt_arg = (void *)hperh; + hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt; + hperh->hdma_p2m.err_arg = (void *)hperh; + hperh->hdma_p2m.err_cbk = &crypt_dma_error; + + CRYPT_SETDIR(hperh, CRYPT_DECRYPT); + + ald_dma_config_struct(&hperh->hdma_m2p.config); + hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_m2p.config.src = (void *)hperh->cipher_text; + hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; + hperh->hdma_m2p.config.size = size / 4; + hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; + hperh->hdma_m2p.config.burst = ENABLE; + hperh->hdma_m2p.config.channel = channel_m2p; + ald_dma_config_basic(&(hperh->hdma_m2p)); + + ald_dma_config_struct(&hperh->hdma_p2m.config); + hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; + hperh->hdma_p2m.config.dst = (void *)hperh->plain_text; + hperh->hdma_p2m.config.size = size / 4; + hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD; + hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; + hperh->hdma_m2p.config.burst = ENABLE; + hperh->hdma_p2m.config.channel = channel_p2m; + ald_dma_config_basic(&(hperh->hdma_p2m)); + + CRYPT_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return OK; +} + +/** + * @} + */ + +/** @defgroup CRYPT_Public_Functions_Group3 DMA operation functions + * @brief DMA operation functions + * @{ + */ + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh) +{ + __LOCK(hperh); + CRYPT_DMA_DISABLE(hperh); + __UNLOCK(hperh); + + return OK; + +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh) +{ + __LOCK(hperh); + CRYPT_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh) +{ + __LOCK(hperh); + CRYPT_DMA_DISABLE(hperh); + __UNLOCK(hperh); + + hperh->state = CRYPT_STATE_READY; + return OK; +} +#endif + +/** + * @brief This function handles CRYPT interrupt request. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval None + */ +void ald_crypt_irq_handler(crypt_handle_t *hperh) +{ + uint32_t i; + uint32_t *in_buf = (uint32_t *)hperh->cipher_text; + uint32_t *out_buf = (uint32_t *)hperh->plain_text; + + if (READ_BIT(hperh->perh->CON, CRYPT_CON_ENCS_MSK) == (CRYPT_DECRYPT << CRYPT_CON_ENCS_POS)) { + in_buf = (uint32_t *)hperh->cipher_text + hperh->count; + out_buf = (uint32_t *)hperh->plain_text + hperh->count - hperh->step; + } + else { + in_buf = (uint32_t *)hperh->plain_text + hperh->count; + out_buf = (uint32_t *)hperh->cipher_text + hperh->count - hperh->step; + } + + if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET) { + ald_crypt_clear_flag_status(hperh, CRYPT_FLAG_AESIF); + } + + if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DESIF) == SET) { + ald_crypt_clear_flag_status(hperh, CRYPT_FLAG_DESIF); + } + + for (i = 0; i < hperh->step; i++) + *out_buf++ = CRYPT_READ_FIFO(hperh); + + hperh->count = hperh->count + hperh->step; + if (hperh->count > (hperh->size / 4)) { + hperh->count = 0; + hperh->state = CRYPT_STATE_READY; + hperh->crypt_cplt_cbk(hperh); + } + else { + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *in_buf); + ++in_buf; + } + } +} +/** + * @} + */ + +/** @defgroup CRYPT_Public_Functions_Group4 Peripheral Control functions + * @brief CRYPT control functions + * @{ + */ + +/** + * @brief Enables or disables the specified CRYPT interrupts. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param it: Specifies the CRYPT interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg crypt_it_t: CRYPT interrupt + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state) +{ + assert_param(IS_CRYPT(hperh->perh)); + + if (it == CRYPT_IT_IT) { + CLEAR_BIT(CRYPT->CON, CRYPT_CON_IE_MSK); + CRYPT->CON |= (state << CRYPT_CON_IE_POS); + } + + return; +} + +/** @brief Check whether the specified CRYPT flag is set or not. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref crypt_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) +{ + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_FLAG(flag)); + + if (CRYPT->IF & flag) + return SET; + + return RESET; +} + +/** @brief Clear the specified CRYPT pending flags. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param flag: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg CRYPT_FLAG_AESIF: AES encrypt or decrypt Complete flag. + * @arg CRYPT_FLAG_DESIF: AES encrypt or decrypt Complete flag. + * @arg CRYPT_FLAG_DONE: encrypt or decrypt Complete flag. + * @retval None + */ +void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) +{ + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_FLAG(flag)); + + CRYPT->IFC = (uint32_t)flag; + return; +} + +/** + * @brief Checks whether the specified CRYPT interrupt has occurred or not. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param it: Specifies the CRYPT interrupt source to check. + * This parameter can be one of the following values: + * @arg crypt_it_t: CRYPT interrupt + * @retval Status + * - SET + * - RESET + */ +it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it) +{ + assert_param(IS_CRYPT_IT(it)); + + if (READ_BIT(CRYPT->CON, CRYPT_CON_IE_MSK)) + return SET; + + return RESET; +} + + +/** + * @} + */ + +/** @defgroup CRYPT_Public_Functions_Group5 Peripheral State and Errors functions + * @brief State and Errors functions + * @{ + */ + +/** + * @brief Returns the CRYPT state. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval CRYPT state + */ +crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh) +{ + assert_param(IS_CRYPT(hperh->perh)); + + return hperh->state; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CRYPT_Private_Functions CRYPT Private Functions + * @brief CRYPT Private functions + * @{ + */ + +/** + * @brief Reset the CRYPT peripheral. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval None + */ +void crypt_reset(crypt_handle_t *hperh) +{ + hperh->perh->DATA[0] = 0x0; + hperh->perh->DATA[1] = 0x0; + hperh->perh->DATA[2] = 0x0; + hperh->perh->DATA[3] = 0x0; + hperh->perh->KEY[0] = 0x0; + hperh->perh->KEY[1] = 0x0; + hperh->perh->KEY[2] = 0x0; + hperh->perh->KEY[3] = 0x0; + hperh->perh->KEY[4] = 0x0; + hperh->perh->KEY[5] = 0x0; + hperh->perh->KEY[6] = 0x0; + hperh->perh->KEY[7] = 0x0; + hperh->perh->IV[0] = 0x0; + hperh->perh->IV[1] = 0x0; + hperh->perh->IV[2] = 0x0; + hperh->perh->IV[3] = 0x0; + hperh->perh->CON = 0x0; + + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); +} + +#ifdef ALD_DMA +/** + * @brief DMA CRYPT encrypt or decrypt process complete callback. + * @param arg: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval None + */ +static void crypt_dma_crypt_cplt(void *arg) +{ + crypt_handle_t *hperh = (crypt_handle_t *)arg; + + CRYPT_DMA_DISABLE(hperh); + hperh->count = 0; + hperh->plain_text = NULL; + hperh->cipher_text = NULL; + hperh->size = 0; + + hperh->state = CRYPT_STATE_READY; + + if (hperh->crypt_cplt_cbk) + hperh->crypt_cplt_cbk(hperh); +} + +/** + * @brief DMA CRYPT communication error callback. + * @param arg: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval None + */ +static void crypt_dma_error(void *arg) +{ + crypt_handle_t *hperh = (crypt_handle_t *)arg; + CRYPT_DMA_DISABLE(hperh); + + hperh->count = 0; + hperh->plain_text = NULL; + hperh->cipher_text = NULL; + hperh->size = 0; + + hperh->state = CRYPT_STATE_READY; + + if (hperh->err_cplt_cbk) + hperh->err_cplt_cbk(hperh); +} +#endif +/** + * @} + */ + +#endif /* ALD_CRYPT */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dac.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dac.c new file mode 100644 index 0000000000000000000000000000000000000000..ba07048b0715421fd01026d489a8a0cefcdb03f7 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dac.c @@ -0,0 +1,333 @@ +/** + ****************************************************************************** + * @file ald_dac.c + * @brief DAC module driver. + * + * @version V1.0 + * @date 28 Jun 2019 + * @author AE Team. + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_dac.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup DAC DAC + * @brief DAC module driver + * @{ + */ +#ifdef ALD_DAC + +/** @defgroup DAC_Public_Functions DAC Public Functions + * @{ + */ +/** + * @brief Reset the dac mode. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_dac_reset(dac_handle_t *hperh) +{ + assert_param(IS_DAC_TYPE(hperh->perh)); + + hperh->perh->CON = 0; + hperh->perh->CH0CTRL = 0; + hperh->perh->CH1CTRL = 0; + hperh->perh->IES = 0; + hperh->perh->IEC = 0xFF; + hperh->perh->IFC = 0xFF; + hperh->perh->CAL = 0; + + return OK; +} + +/** + * @brief Initializes the DAC peripheral. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_dac_init(dac_handle_t *hperh) +{ + uint32_t tmp; + + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_DAC_CONVERT_TYPE(hperh->init.conv_mode)); + assert_param(IS_DAC_OUTPUT_TYPE(hperh->init.out_mode)); + assert_param(IS_DAC_NEG_REFRESH_TYPE(hperh->init.n_ref)); + assert_param(IS_DAC_POS_REFRESH_TYPE(hperh->init.p_ref)); + assert_param(IS_DAC_REFRESH_TYPE(hperh->init.refresh)); + assert_param(IS_DAC_PRESCALE_TYPE(hperh->init.div)); + assert_param(IS_FUNC_STATE(hperh->init.ch0_reset)); + assert_param(IS_FUNC_STATE(hperh->init.o_ctrl_pis)); + assert_param(IS_FUNC_STATE(hperh->init.sine)); + assert_param(IS_FUNC_STATE(hperh->init.diff)); + + __LOCK(hperh); + ald_dac_reset(hperh); + DAC_CH0_DISABLE(); + DAC_CH1_DISABLE(); + + MODIFY_REG(ADC0->CCR, ADC_CCR_VREFEN_MSK, 1 << ADC_CCR_VREFEN_POS); + + if (hperh->init.p_ref == DAC_POS_REF_VREEFP_BUF || hperh->init.p_ref == DAC_POS_REF_2V) + SET_BIT(ADC0->CCR, (ADC_CCR_IREFEN_MSK | ADC_CCR_VRBUFEN_MSK | ADC_CCR_VCMBUFEN_MSK)); + + MODIFY_REG(ADC0->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS); + + tmp = ((hperh->init.refresh << DAC_CON_RCYCLSEL_POSS) | (hperh->init.div << DAC_CON_PRES_POSS) | + (hperh->init.ch0_reset << DAC_CON_CH0PRESRST_POS) | ( hperh->init.o_ctrl_pis << DAC_CON_OUTENPIS_POS) | + (hperh->init.out_mode << DAC_CON_OUTMD_POSS) | (hperh->init.conv_mode << DAC_CON_CONVMD_POSS) | + (hperh->init.sine << DAC_CON_SINEMD_POS) | (hperh->init.diff << DAC_CON_DIFEN_POS)); + hperh->perh->CON = tmp; + + /* Automatic calibration */ + SET_BIT(hperh->perh->CAL, DAC_CAL_SELF_CALEN_MSK); + for (tmp = 0; tmp < 1000; ++tmp); + CLEAR_BIT(hperh->perh->CAL, DAC_CAL_SELF_CALEN_MSK); + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Configure dac channel. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC module. + * @param config: Pointer to a dac_channel_config_t structure that contains + * the configutation information for dac channel. + * @param ch: Specifies which dac channel to be config. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_dac_channel_config(dac_handle_t *hperh, dac_channel_config_t *config, dac_channel_t ch) +{ + uint32_t tmp; + + if ((hperh == NULL) || (config == NULL)) + return ERROR; + + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->enable)); + assert_param(IS_DAC_TRIGGER_TYPE(config->trigger)); + assert_param(IS_FUNC_STATE(config->refresh_en)); + assert_param(IS_DAC_PISSEL_CH_TYPE(config->pis_ch)); + + __LOCK(hperh); + tmp = ((config->pis_ch << DAC_CH0CTRL_PISSEL_POSS) | (config->trigger << DAC_CH0CTRL_PISEN_POS) | + (config->refresh_en << DAC_CH0CTRL_RCYCLEN_POS) | (config->enable << DAC_CH0CTRL_EN_POS)); + + switch (ch) { + case DAC_CHANNEL_0: + hperh->perh->CH0CTRL = tmp; + break; + + case DAC_CHANNEL_1: + hperh->perh->CH1CTRL = tmp; + break; + + default: + break; + } + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Set dac channel output value. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC module. + * @param ch: Specifies which dac channel to be set. + * @param value: The value be converted,and the valid value is low 12 bit. + * @retval None + */ +void ald_dac_output_set(dac_handle_t *hperh, dac_channel_t ch, uint32_t value) +{ + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_DAC_CHANNEL_TYPE(ch)); + + switch (ch) { + case DAC_CHANNEL_0: + hperh->perh->CH0DATA = value; + break; + + case DAC_CHANNEL_1: + hperh->perh->CH1DATA = value; + break; + + case DAC_CHANNEL_COMB: + hperh->perh->COMBDATA = value; + break; + + default: + break; + } + + return; +} + +/** + * @brief Checks whether the specified DAC flag is set or not. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified dac. + * @param status: Specifies the flag to check. + * @retval The new state. + */ +flag_status_t ald_dac_get_status(dac_handle_t *hperh, dac_status_t status) +{ + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_DAC_STATUS_TYPE(status)); + + return hperh->perh->STAT & status ? SET : RESET; +} + +/** + * @brief Enable or disable the specified interrupt + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC. + * @param it: Specifies the interrupt type to be enabled or disabled + * @arg @ref DAC_IT_CH0 Channel 0 conversion complete interrupt + * @arg @ref DAC_IT_CH1 Channel 1 conversion complete interrupt + * @arg @ref DAC_IT_CH0_UF Channel 0 data underflow interrupt + * @arg @ref DAC_IT_CH1_UF Channel 1 data underflow interrupt + * @param state: New state of the specified interrupt. + * This parameter can be: ENABLE or DISABLE + * @retval Status, see @ref ald_status_t. + */ +void ald_dac_interrupt_config(dac_handle_t *hperh, dac_it_t it, type_func_t state) +{ + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_DAC_INTERRUPT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + hperh->perh->IES |= it; + else + hperh->perh->IEC = it; + + return; +} + +/** + * @brief Get the status of DAC interrupt source. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC. + * @param it: Specifies the DAC interrupt source. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_dac_get_it_status(dac_handle_t *hperh, dac_it_t it) +{ + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_DAC_INTERRUPT_TYPE(it)); + + return hperh->perh->IEV & it ? SET : RESET; +} + +/** + * @brief Checks whether the specified interrupt has occurred or not. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC. + * @param flag: Specifies the interrupt type to check. + * @retval The new state. + */ +flag_status_t ald_dac_get_flag_status(dac_handle_t *hperh, dac_flag_t flag) +{ + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_DAC_FLAG_TYPE(flag)); + + return hperh->perh->RIF & flag ? SET : RESET; +} + +/** + * @brief Get the status of interrupt flag and interupt source. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC. + * @param flag: Specifies the DAC interrupt flag. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_dac_get_mask_flag_status(dac_handle_t *hperh, dac_flag_t flag) +{ + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_DAC_FLAG_TYPE(flag)); + + return hperh->perh->IFM & flag ? SET : RESET; +} + +/** + * @brief Clear interrupt state flag + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC. + * @param flag: Specifies the interrupt type to clear + * @retval None + */ +void ald_dac_clear_flag_status(dac_handle_t *hperh, dac_flag_t flag) +{ + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_DAC_FLAG_TYPE(flag)); + + hperh->perh->IFC = flag; + return; +} + +/** + * @brief This function handles DAC event interrupt request. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +void ald_dac_irq_handler(dac_handle_t *hperh) +{ + if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH0)) { + ald_dac_clear_flag_status(hperh, DAC_FLAG_CH0); + + if (hperh->cbk) + hperh->cbk(hperh, DAC_EVENT_CH0_CPLT); + } + + if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH1)) { + ald_dac_clear_flag_status(hperh, DAC_FLAG_CH1); + + if (hperh->cbk) + hperh->cbk(hperh, DAC_EVENT_CH1_CPLT); + } + + if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH0_UF)) { + ald_dac_clear_flag_status(hperh, DAC_FLAG_CH0_UF); + + if (hperh->cbk) + hperh->cbk(hperh, DAC_EVENT_CH0_UF); + } + + if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH1_UF)) { + ald_dac_clear_flag_status(hperh, DAC_FLAG_CH1_UF); + + if (hperh->cbk) + hperh->cbk(hperh, DAC_EVENT_CH1_UF); + } + + return; +} +/** + *@} + */ +#endif /* ALD_DAC */ +/** + *@} + */ +/** + *@} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..812dd11d65cee28b5b38562d008389a2f37cd410 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_dma.c @@ -0,0 +1,723 @@ +/** + ********************************************************************************* + * + * @file ald_dma.c + * @brief DMA module driver. + * + * @version V1.0 + * @date 09 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA driver can be used as follows: + + (#) System initialization invokes ald_dma_init(), ald_cmu_init() --> ald_dma_init(). + + (#) Declare a dma_handle_t handle structure. + + (#) Configure the dma_handle_t structure, you can configure the + dma_config_t structure with the help of ald_dma_config_struct(). + + (#) Enable the DMA Configure: + (##) Memory -- memory: call ald_dma_config_auto(). + (##) Peripheral -- memory: call ald_dma_config_basic(). + (##) If you want use the dma easily, you can do this: + (+++) Memory -- memory: call ald_dma_config_auto_easy(). + (+++) Peripheral -- memory: call ald_dma_config_basic_easy(). + + (#) Enable the DMA request signal: + (##) Memory -- memory: the DMA request signal is request automatic. + (##) Peripheral -- memory: you need enable peripheral request signal. + + (#) If you enable DMA interrupt, the callback will be invoked: + (##) When DMA transfer is completed, the cplt_cbk() will be invoked. + (##) When DMA bus occurs error, the err_cbk() will be invoked. + + (#) If you don't enable the DMA interrupt, you need do this: + (##) Polling the ald_dma_get_flag_status(), this function's parameter is channel + or DMA_ERR. + (+++) When the function's Parameter is channel, if retval is SET, it means + the DMA transfer is completed. at this moment, you can do something, + and then, you need invoke ald_dma_clear_flag_status() to clear flag. + + (+++) When the function's Parameter is DMA_ERR, if retval is SET, it means + the DMA bus occurs error. at this moment, you can do something, + and then, you need invoke ald_dma_clear_flag_status() to clear flag. + + @endverbatim + */ + +#include +#include "ald_conf.h" +#include "ald_dma.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA module driver + * @{ + */ + +#ifdef ALD_DMA +/** @defgroup DMA_Private_Variables DMA Private Variables + * @{ + */ +dma_descriptor_t dma0_ctrl_base[28] __attribute__ ((aligned(512))); +dma_call_back_t dma0_cbk[12]; +/** + * @} + */ + +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ + +/** + * @brief Configure DMA channel using dma_config_t structure + * @param DMAx: Pointer to DMA peripheral + * @param mode: DMA transfer mode. see @ref dma_cycle_ctrl_t + * @param p: Pointer to dma_cycle_ctrl_t which contains + * DMA channel parameter. see @ref dma_config_t + * @retval None + */ +static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config_t *p) +{ + dma_descriptor_t *descr; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_CYCLECTRL_TYPE(mode)); + assert_param(p->src != NULL); + assert_param(p->dst != NULL); + assert_param(IS_DMA_DATA_SIZE(p->size)); + assert_param(IS_DMA_DATASIZE_TYPE(p->data_width)); + assert_param(IS_DMA_DATAINC_TYPE(p->src_inc)); + assert_param(IS_DMA_DATAINC_TYPE(p->dst_inc)); + assert_param(IS_DMA_ARBITERCONFIG_TYPE(p->R_power)); + assert_param(IS_FUNC_STATE(p->primary)); + assert_param(IS_FUNC_STATE(p->burst)); + assert_param(IS_FUNC_STATE(p->high_prio)); + assert_param(IS_FUNC_STATE(p->iterrupt)); + assert_param(IS_DMA_MSEL_TYPE(p->msel)); + assert_param(IS_DMA_MSIGSEL_TYPE(p->msigsel)); + assert_param(IS_DMA_CHANNEL(p->channel)); + + if (p->primary) + descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + p->channel; + else + descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + p->channel; + + if (p->src_inc == DMA_DATA_INC_NONE) + descr->src = p->src; + else + descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << p->data_width)); + + if (p->dst_inc == DMA_DATA_INC_NONE) + descr->dst = p->dst; + else + descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << p->data_width)); + + descr->ctrl.cycle_ctrl = mode; + descr->ctrl.next_useburst = 0; + descr->ctrl.n_minus_1 = p->size - 1; + descr->ctrl.R_power = p->R_power; + descr->ctrl.src_prot_ctrl = 0, + descr->ctrl.dst_prot_ctrl = 0, + descr->ctrl.src_size = p->data_width; + descr->ctrl.src_inc = p->src_inc; + descr->ctrl.dst_size = p->data_width; + descr->ctrl.dst_inc = p->dst_inc; + + if (p->primary) + WRITE_REG(DMAx->CHPRIALTCLR, (1 << p->channel)); + else + WRITE_REG(DMAx->CHPRIALTSET, (1 << p->channel)); + + if (p->burst) + WRITE_REG(DMAx->CHUSEBURSTSET, (1 << p->channel)); + else + WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << p->channel)); + + if (p->high_prio) + WRITE_REG(DMAx->CHPRSET, (1 << p->channel)); + else + WRITE_REG(DMAx->CHPRCLR, (1 << p->channel)); + + if (p->iterrupt) + SET_BIT(DMAx->IER, (1 << p->channel)); + else + CLEAR_BIT(DMAx->IER, (1 << p->channel)); + + MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSEL_MSK, p->msel << DMA_CH0_SELCON_MSEL_POSS); + MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSIGSEL_MSK, p->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); + return; +} + +/** + * @brief Handle DMA interrupt + * @retval None + */ +void ald_dma_irq_handler(void) +{ + uint32_t i, reg = DMA0->IFLAG; + + for (i = 0; i < DMA_CH_COUNT; ++i) { + if (READ_BIT(reg, (1 << i))) { + if (dma0_cbk[i].cplt_cbk != NULL) + dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg); + + ald_dma_clear_flag_status(DMA0, i); + } + } + + if (READ_BIT(reg, (1U << DMA_ERR))) { + ald_dma_clear_flag_status(DMA0, DMA_ERR); + + for (i = 0; i < DMA_CH_COUNT; ++i) { + if (((DMA0->CHENSET >> i) & 0x1) && (dma0_cbk[i].err_cbk != NULL)) + dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg); + } + } + + return; +} +/** + * @} + */ + +/** @defgroup DMA_Public_Functions DMA Public Functions + * @{ + */ + +/** @defgroup DMA_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * + * @verbatim + =================================================================== + + #### Initialization functions #### + + =================================================================== + [..] + This subsection provides two functions to Initilizate DMA: + (+) ald_dma_reset(): Reset the DMA register. + + (+) ald_dma_init(): Initializate the DMA module. this function is + invoked by ald_cmu_init(). + this function do this: + (++) Initializte private variable dma_ctrl_base and dma_cbk. + (++) Reset DMA register. + (++) Set DMA interrupt priority: preempt_prio=1, sub_priority=1 + (++) Enable DMA interrupt. + (++) Enable DMA bus error interrupt. + (++) Configure CTRLBASE resigter. + (++) Enable DMA module. + + (+) ald_dma_config_struct(): Configure dma_config_t + structure using default parameter. + + @endverbatim + * @{ + */ + +/** + * @brief Reset the DMA register + * @param DMAx: Pointer to DMA peripheral + * @retval None + */ +void ald_dma_reset(DMA_TypeDef *DMAx) +{ + uint32_t i; + + assert_param(IS_DMA(DMAx)); + + WRITE_REG(DMAx->CFG, 0x0); + WRITE_REG(DMAx->CHUSEBURSTCLR, 0xFFF); + WRITE_REG(DMAx->CHREQMASKCLR, 0xFFF); + WRITE_REG(DMAx->CHENCLR, 0xFFF); + WRITE_REG(DMAx->CHPRIALTCLR, 0xFFF); + WRITE_REG(DMAx->CHPRCLR, 0xFFF); + WRITE_REG(DMAx->ERRCLR, 0x1); + WRITE_REG(DMAx->IER, 0x0); + WRITE_REG(DMAx->ICFR, 0x80000FFF); + + for (i = 0; i < DMA_CH_COUNT; ++i) + WRITE_REG(DMAx->CH_SELCON[i], 0x0); + + return; +} + +/** + * @brief DMA module initialization, this function + * is invoked by ald_cmu_init(). + * @param DMAx: Pointer to DMA peripheral + * @retval None + */ +void ald_dma_init(DMA_TypeDef *DMAx) +{ + assert_param(IS_DMA(DMAx)); + + memset(dma0_ctrl_base, 0x0, sizeof(dma0_ctrl_base)); + memset(dma0_cbk, 0x0, sizeof(dma0_cbk)); + + ald_dma_reset(DMAx); + NVIC_SetPriority(DMA_IRQn, 2); + NVIC_EnableIRQ(DMA_IRQn); + SET_BIT(DMAx->IER, DMA_IER_DMAERRIE_MSK); + + WRITE_REG(DMAx->CTRLBASE, (uint32_t)&dma0_ctrl_base); + SET_BIT(DMAx->CFG, DMA_CFG_MASTER_ENABLE_MSK); + + return; +} + +/** + * @brief Configure dma_config_t structure using default parameter. + * User can invoked this function, before configure dma_config_t + * @param p: Pointer to dma_config_t structure, see @ref dma_config_t + * @retval None + */ +void ald_dma_config_struct(dma_config_t *p) +{ + p->data_width = DMA_DATA_SIZE_BYTE; + p->src_inc = DMA_DATA_INC_BYTE; + p->dst_inc = DMA_DATA_INC_BYTE; + p->R_power = DMA_R_POWER_1; + p->primary = ENABLE; + p->burst = DISABLE; + p->high_prio = DISABLE; + p->iterrupt = ENABLE; + + return; +} + +/** + * @} + */ + +/** @defgroup DMA_Public_Functions_Group2 Configure DMA channel functions + * @brief Configure DMA channel functions + * + * @verbatim + =================================================================== + + #### Configure DMA channel functions #### + + =================================================================== + [..] + This subsection provides some functions allowing to configure + DMA channel. Include two type DMA transfer: + (+) Carry data from memory to memory, this mode APIs are: + (++) ald_dma_config_auto(): Configure DMA channel according to + the specified parameter in the dma_handle_t structure. + (++) ald_dma_restart_auto(): Restart DMA transmitted. + (++) ald_dma_config_auto_easy(): Configure DMA channel according + to the specified parameter. If you want use the dma easily, + you can invoke this function. + (+) Carry data from peripheral to memory or from memory to peripheral, + this mode APIs are: + (++) ald_dma_config_basic(): Configure DMA channel according to + the specified parameter in the dma_handle_t structure. + (++) ald_dma_restart_basic(): Restart DMA transmitted. + (++) ald_dma_config_basic_easy(): Configure DMA channel according + to the specified parameter. If you want use the dma easily, + you can invoke this function. + + @endverbatim + * @{ + */ + +/** + * @brief Configure DMA channel according to the specified parameter + * in the dma_handle_t structure. The DMA mode is automatic. + * This mode is used to carry data from memory to memory. + * @param hperh: Pointer to DMA_handle_t structure that contains + * configuration information for specified DMA channel. + * @retval None + */ +void ald_dma_config_auto(dma_handle_t *hperh) +{ + dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; + dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; + dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; + dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; + dma_config_base(hperh->perh, DMA_CYCLE_CTRL_AUTO, &hperh->config); + + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); + + return; +} + +/** + * @brief Restart DMA transmitted. The DMA mode is automatic. + * The other parameters have not changed except 'size' and 'addr'. + * @param hperh: Pointer to DMA_handle_t structure that contains + * configuration information for specified DMA channel. + * @param src: Source data begin pointer + * @param dst: Destination data begin pointer + * @param size: Size. + * @retval None + */ +void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size) +{ + dma_descriptor_t *descr; + + if (hperh->config.primary) + descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel; + else + descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel; + + if (src) { + if (hperh->config.src_inc == DMA_DATA_INC_NONE) + descr->src = src; + else + descr->src = (void *)((uint32_t)src + ((size - 1) << hperh->config.data_width)); + } + + if (dst) { + if (hperh->config.dst_inc == DMA_DATA_INC_NONE) + descr->dst = dst; + else + descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width)); + } + + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); + descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO; + descr->ctrl.n_minus_1 = size - 1; + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); + return; +} + + + +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is automatic. This mode is used to carry data + * from memory to memory. If User want use the dma easily, + * they can invoke this function. + * @param DMAx: Pointer to DMA peripheral + * @param src: Source data begin pointer + * @param dst: Destination data begin pointer + * @param size: The total number of DMA transfers that DMA cycle contains + * @param channel: Channel index which will be used. + * @param cbk: DMA complete callback function + * + * @retval None + */ +void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, + uint16_t size, uint8_t channel, void (*cbk)(void *arg)) +{ + dma_handle_t hperh; + + assert_param(IS_DMA(DMAx)); + + ald_dma_config_struct(&hperh.config); + hperh.config.src = src; + hperh.config.dst = dst; + hperh.config.size = size; + hperh.config.msel = DMA_MSEL_NONE; + hperh.config.msigsel = DMA_MSIGSEL_NONE; + hperh.config.channel = channel; + + hperh.perh = DMAx; + hperh.cplt_cbk = cbk; + hperh.cplt_arg = NULL; + hperh.err_cbk = NULL; + + ald_dma_clear_flag_status(DMAx, channel); + ald_dma_config_auto(&hperh); + + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter + * in the dma_handle_t structure. The DMA mode is basic. + * This mode is used to carry data from peripheral to memory + * or from memory to peripheral. + * @param hperh: Pointer to dma_handle_t structure that contains + * configuration information for specified DMA channel. + * @retval None + */ +void ald_dma_config_basic(dma_handle_t *hperh) +{ + dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; + dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; + dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; + dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; + + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); + dma_config_base(hperh->perh, DMA_CYCLE_CTRL_BASIC, &hperh->config); + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + + return; +} + +/** + * @brief Restart DMA transmitted. The DMA mode is basic. + * The other parameters have not changed except 'size' and 'addr'. + * @param hperh: Pointer to DMA_handle_t structure that contains + * configuration information for specified DMA channel. + * @param src: Source data begin pointer + * @param dst: Destination data begin pointer + * @param size: Size. + * @retval None + */ +void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size) +{ + dma_descriptor_t *descr; + + if (hperh->config.primary) + descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel; + else + descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel; + + if (src) { + if (hperh->config.src_inc == DMA_DATA_INC_NONE) + descr->src = src; + else + descr->src = (void *)((uint32_t)src + ((size - 1) << hperh->config.data_width)); + } + + if (dst) { + if (hperh->config.dst_inc == DMA_DATA_INC_NONE) + descr->dst = dst; + else + descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width)); + } + + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); + descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC; + descr->ctrl.n_minus_1 = size - 1; + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is basic. This mode is used to carry data + * from peripheral to memory or negative direction. If user want + * use the dma easily, they can invoke this function. + * @param DMAx: Pointer to DMA peripheral + * @param src: Source data begin pointer + * @param dst: Destination data begin pointer + * @param size: The total number of DMA transfers that DMA cycle contains + * @param msel: Input source to DMA channel @ref dma_msel_t + * @param msigsel: Input signal to DMA channel @ref dma_msigsel_t + * @param channel: Channel index which will be used + * @param cbk: DMA complete callback function + * + * @retval None + * + */ +void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, + dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) +{ + dma_handle_t hperh; + + assert_param(IS_DMA(DMAx)); + ald_dma_config_struct(&hperh.config); + + if (((uint32_t)src) >= 0x40000000) + hperh.config.src_inc = DMA_DATA_INC_NONE; + + if (((uint32_t)dst) >= 0x40000000) + hperh.config.dst_inc = DMA_DATA_INC_NONE; + + hperh.config.src = src; + hperh.config.dst = dst; + hperh.config.size = size; + hperh.config.msel = msel; + hperh.config.msigsel = msigsel; + hperh.config.channel = channel; + + hperh.perh = DMAx; + hperh.cplt_cbk = cbk; + hperh.cplt_arg = NULL; + hperh.err_cbk = NULL; + + ald_dma_clear_flag_status(DMAx, channel); + ald_dma_config_basic(&hperh); + + return; +} + +/** + * @} + */ + +/** @defgroup DMA_Public_Functions_Group3 DMA Control functions + * @brief DMA control functions + * + * @verbatim + =================================================================== + + #### DMA control functions #### + + =================================================================== + [..] + This subsection provides some functions allowing to control DMA: + (+) ald_dma_channel_config(): Control DMA channel ENABLE/DISABLE. + (+) ald_dma_interrupt_config(): Control DMA channel interrupt ENABLE or + DISABLE. + (+) ald_dma_get_it_status(): Check whether the specified channel + interrupt is SET or RESET. + (+) ald_dma_get_flag_status(): Check whether the specified channel + flag is SET or RESET. + (+) ald_dma_clear_flag_status(): Clear the specified channel + pending flag + + @endverbatim + * @{ + */ + +/** + * @brief Configure channel enable or disable. It will unbind descriptor with + * channel, when channel has been disable. + * @param DMAx: Pointer to DMA peripheral + * @param channel: channel index + * @param state: status of channel: + * @arg ENABLE: Enable the channel + * @arg DISABLE: Disable the channel + * @retval None + */ +void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) +{ + dma_descriptor_t *descr, *alt_descr; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_CHANNEL(channel)); + assert_param(IS_FUNC_STATE(state)); + + descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + alt_descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + + if (state) { + WRITE_REG(DMAx->CHENSET, (1 << channel)); + } + else { + memset(descr, 0x00, sizeof(dma_descriptor_t)); + memset(alt_descr, 0x00, sizeof(dma_descriptor_t)); + WRITE_REG(DMAx->CH_SELCON[channel], 0x0); + WRITE_REG(DMAx->CHENCLR, (1 << channel)); + } + + return; +} + +/** + * @brief Configure the interrupt enable or disable + * @param DMAx: Pointer to DMA peripheral + * @param channel: Channel index or DMA_ERR. + * @arg 0~11: Channel index + * @arg DMA_ERR: DMA bus error + * @param state: status of channel: + * @arg ENABLE: Enable the channel + * @arg DISABLE: Disable the channel + * + * @retval None + */ +void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) +{ + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + SET_BIT(DMAx->IER, (1 << channel)); + else + CLEAR_BIT(DMAx->IER, (1 << channel)); + + return; +} + +/** + * @brief Check whether the specified channel interrupt + * is set or reset + * @param DMAx: Pointer to DMA peripheral + * @param channel: Channel index or DMA_ERR + * @arg 0~11: Channel index + * @arg DMA_ERR: DMA bus error + * @retval Status: + * - SET: Channel interrupt is set + * - RESET: Channel interrupt is reset + */ +it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel) +{ + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + + if (READ_BIT(DMAx->IER, (1 << channel))) + return SET; + + return RESET; +} + +/** + * @brief Check whether the specified channel flag + * is set or reset + * @param DMAx: Pointer to DMA peripheral + * @param channel: Channel index or DMA_ERR + * @arg 0~11: Channel index + * @arg DMA_ERR: DMA bus error + * @retval Status: + * - SET: Channel flag is set + * - RESET: Channel flag is reset + */ +flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel) +{ + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + + if (READ_BIT(DMAx->IFLAG, (1 << channel))) + return SET; + + return RESET; +} + +/** + * @brief Clear the specified channel pending flag + * @param DMAx: Pointer to DMA peripheral + * @param channel: Channel index or DMA_ERR + * @arg 0~11: Channel index + * @arg DMA_ERR: DMA bus error + * @retval None + */ +void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel) +{ + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + + WRITE_REG(DMAx->ICFR, (1 << channel)); + return; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* ALD_DMA */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_ebi.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_ebi.c new file mode 100644 index 0000000000000000000000000000000000000000..5fc69ba3f9d95c79a486e4571a6616116473e0f3 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_ebi.c @@ -0,0 +1,676 @@ +/** + ********************************************************************************* + * + * @file ald_ebi.c + * @brief EBI module driver. + * + * @version V1.0 + * @date 20 Jan 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + ****************************************************************************** + */ + +#include "ald_ebi.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup EBI EBI + * @brief EBI module driver + * @{ + */ +#ifdef ALD_EBI + +/** @defgroup EBI_Public_Functions EBI Public Functions + * @{ + */ + +/** @defgroup EBI_Public_Functions_Group1 NOR-FLASH SRAM initialize functions + * @brief NOR-FLASH SRAM initialize functions + * @{ + */ +/** + * @brief Initialize the EBI_NOR_SRAM device according to the specified + * control parameters in the EBI_NOR_SRAM_InitTypeDef + * @param dev: Pointer to NOR_SRAM device instance + * @param init: Pointer to NOR_SRAM Initialization structure + * @retval None + */ +void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init) +{ + assert_param(IS_EBI_NORSRAM_DEVICE(dev)); + assert_param(IS_EBI_NORSRAM_BANK(init->bank)); + assert_param(IS_EBI_MUX(init->mux)); + assert_param(IS_EBI_MEMORY(init->type)); + assert_param(IS_EBI_NORSRAM_MEMORY_WIDTH(init->width)); + assert_param(IS_EBI_BURSTMODE(init->acc_mode)); + assert_param(IS_EBI_WAIT_POLARITY(init->polarity)); + assert_param(IS_EBI_WRAP_MODE(init->wrap_mode)); + assert_param(IS_EBI_WAIT_SIGNAL_ACTIVE(init->active)); + assert_param(IS_EBI_WRITE_OPERATION(init->write)); + assert_param(IS_EBI_WAITE_SIGNAL(init->signal)); + assert_param(IS_EBI_EXTENDED_MODE(init->ext_mode)); + assert_param(IS_EBI_ASYNWAIT(init->wait)); + assert_param(IS_EBI_WRITE_BURST(init->burst)); + + /* Disable NORSRAM device */ + ald_ebi_nor_sram_disable(dev, init->bank); + + /* Set NORSRAM device control parameters */ + if (init->type == EBI_MEMORY_TYPE_NOR) { + MODIFY_REG(dev->BTCR[init->bank], BCTRLR_CLEAR_MASK, (uint32_t)((uint32_t)EBI_NORSRAM_FLASH_ACCESS_ENABLE + | (uint32_t)init->mux + | (uint32_t)init->type + | (uint32_t)init->width + | (uint32_t)init->acc_mode + | (uint32_t)init->polarity + | (uint32_t)init->wrap_mode + | (uint32_t)init->active + | (uint32_t)init->write + | (uint32_t)init->signal + | (uint32_t)init->ext_mode + | (uint32_t)init->wait + | (uint32_t)init->burst)); + } + else { + MODIFY_REG(dev->BTCR[init->bank], BCTRLR_CLEAR_MASK, (uint32_t)(EBI_NORSRAM_FLASH_ACCESS_DISABLE + | (uint32_t)init->mux + | (uint32_t)init->type + | (uint32_t)init->width + | (uint32_t)init->acc_mode + | (uint32_t)init->polarity + | (uint32_t)init->wrap_mode + | (uint32_t)init->active + | (uint32_t)init->write + | (uint32_t)init->signal + | (uint32_t)init->ext_mode + | (uint32_t)init->wait + | (uint32_t)init->burst)); + } +} + +/** + * @brief Initialize the EBI_NOR_SRAM Timing according to the specified + * parameters in the EBI_NOR_SRAM_TimingTypeDef + * @param dev: Pointer to NOR_SRAM device instance + * @param timing: Pointer to NOR_SRAM Timing structure + * @param bank: NOR_SRAM bank number + * @retval None + */ +void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank) +{ + assert_param(IS_EBI_NORSRAM_DEVICE(dev)); + assert_param(IS_EBI_ADDRESS_SETUP_TIME(timing->addr_setup)); + assert_param(IS_EBI_ADDRESS_HOLD_TIME(timing->addr_hold)); + assert_param(IS_EBI_DATASETUP_TIME(timing->data_setup)); + assert_param(IS_EBI_TURNAROUND_TIME(timing->bus_dur)); + assert_param(IS_EBI_DATA_LATENCY(timing->latency)); + assert_param(IS_EBI_ACCESS_MODE(timing->mode)); + assert_param(IS_EBI_NORSRAM_BANK(bank)); + + /* Set EBI_NORSRAM device timing parameters */ + MODIFY_REG(dev->BTCR[bank + 1U], BTR_CLEAR_MASK, \ + (uint32_t)(timing->addr_setup | \ + ((timing->addr_hold) << EBI_BTRx_ADDHOLD_POSS) | \ + ((timing->data_setup) << EBI_BTRx_DATAHOLD_POSS) | \ + ((timing->bus_dur) << EBI_BTRx_BUSTURN_POSS) | \ + (((timing->div) - 1U) << EBI_BTRx_CLKDIV_POSS) | \ + (((timing->latency) - 1U) << EBI_BTRx_DATALAT_POSS) | \ + (timing->mode))); +} + +/** + * @brief Initialize the EBI_NOR_SRAM Extended mode Timing according to the specified + * parameters in the EBI_NOR_SRAM_TimingTypeDef + * @param dev: Pointer to NOR_SRAM device instance + * @param timing: Pointer to NOR_SRAM Timing structure + * @param bank: NOR_SRAM bank number + * @param mode EBI Extended Mode + * This parameter can be one of the following values: + * @arg EBI_EXTENDED_MODE_DISABLE + * @arg EBI_EXTENDED_MODE_ENABLE + * @retval None + */ +void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode) +{ + assert_param(IS_EBI_EXTENDED_MODE(mode)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + if (mode == EBI_EXTENDED_MODE_ENABLE) { + assert_param(IS_EBI_NORSRAM_EXTENDED_DEVICE(dev)); + assert_param(IS_EBI_ADDRESS_SETUP_TIME(timing->addr_setup)); + assert_param(IS_EBI_ADDRESS_HOLD_TIME(timing->addr_hold)); + assert_param(IS_EBI_DATASETUP_TIME(timing->data_setup)); + assert_param(IS_EBI_TURNAROUND_TIME(timing->bus_dur)); + assert_param(IS_EBI_ACCESS_MODE(timing->mode)); + assert_param(IS_EBI_NORSRAM_BANK(bank)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + MODIFY_REG(dev->BWTR[bank], BWTR_CLEAR_MASK, \ + (uint32_t)(timing->addr_setup | \ + ((timing->addr_hold) << EBI_BWRTRx_ADDHOLD_POSS) | \ + ((timing->data_setup) << EBI_BWRTRx_DATAHOLD_POSS) | \ + timing->mode | \ + ((timing->bus_dur) << EBI_BWRTRx_BUSTURN_POSS))); + } + else { + dev->BWTR[bank] = 0x0FFFFFFFU; + } +} + +/** + * @brief DeInitialize the EBI_NOR_SRAM peripheral + * @param dev: Pointer to NOR_SRAM device instance + * @param e_dev: Pointer to NOR_SRAM extended mode device instance + * @param bank: NOR_SRAM bank number + * @retval ald status + */ +ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank) +{ + assert_param(IS_EBI_NORSRAM_DEVICE(dev)); + assert_param(IS_EBI_NORSRAM_EXTENDED_DEVICE(e_dev)); + assert_param(IS_EBI_NORSRAM_BANK(bank)); + + /* Disable the EBI_NOR/SRAM device */ + ald_ebi_nor_sram_disable(dev, bank); + + /* De-initialize the EBI_NOR/SRAM device */ + if (bank == EBI_NORSRAM_BANK1) + dev->BTCR[bank] = 0x000030DBU; + else + dev->BTCR[bank] = 0x000030D2U; + + dev->BTCR[bank + 1U] = 0x0FFFFFFFU; + e_dev->BWTR[bank] = 0x0FFFFFFFU; + + return OK; +} +/** + * @} + */ + +/** @defgroup EBI_Public_Functions_Group2 NOR-FLASH SRAM control functions + * @brief NOR-FLASH SRAM control functions + * @{ + */ +/** + * @brief Enable the NOR/SRAM device access. + * @param dev: NOR/SRAM Instance + * @param bank: NOR/SRAM Bank + * @retval none + */ +void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NORSRAM_DEVICE(dev)); + assert_param(IS_EBI_NORSRAM_BANK(bank)); + + SET_BIT(dev->BTCR[bank], EBI_BCTRLRx_MEMBKEN_MSK); +} + +/** + * @brief Disable the NORSRAM device access. + * @param dev: EBI_NORSRAM Instance + * @param bank: EBI_NORSRAM Bank + * @retval none + */ +void ald_ebi_nor_sram_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NORSRAM_DEVICE(dev)); + assert_param(IS_EBI_NORSRAM_BANK(bank)); + + CLEAR_BIT(dev->BTCR[bank], EBI_BCTRLRx_MEMBKEN_MSK); +} + +/** + * @brief Enables dynamically NOR-FLASH/SRAM write operation. + * @param dev: Pointer to NOR/SRAM device instance + * @param bank: NOR/SRAM bank number + * @retval void + */ +void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NORSRAM_DEVICE(dev)); + assert_param(IS_EBI_NORSRAM_BANK(bank)); + + /* Enable write operation */ + SET_BIT(dev->BTCR[bank], EBI_WRITE_OPERATION_ENABLE); +} + +/** + * @brief Disables dynamically EBI_NORSRAM write operation. + * @param dev: Pointer to NORSRAM device instance + * @param bank: NORSRAM bank number + * @retval None + */ +void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NORSRAM_DEVICE(dev)); + assert_param(IS_EBI_NORSRAM_BANK(bank)); + + /* Disable write operation */ + CLEAR_BIT(dev->BTCR[bank], EBI_WRITE_OPERATION_ENABLE); +} +/** + * @} + */ + +/** @defgroup EBI_Public_Functions_Group3 NAND-FLASH initialize functions + * @brief NAND-FLASH initialize functions + * @{ + */ +/** + * @brief Initializes the EBI_NAND device according to the specified + * control parameters in the EBI_NAND_HandleTypeDef + * @param dev: Pointer to NAND device instance + * @param init: Pointer to NAND Initialization structure + * @retval None + */ +void ald_ebi_nand_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(init->bank)); + assert_param(IS_EBI_WAIT_FEATURE(init->wait)); + assert_param(IS_EBI_NAND_MEMORY_WIDTH(init->width)); + assert_param(IS_EBI_ECC_STATE(init->ecc)); + assert_param(IS_EBI_ECCPAGE_SIZE(init->size)); + assert_param(IS_EBI_TCLR_TIME(init->cle_time)); + assert_param(IS_EBI_TAR_TIME(init->ale_time)); + + /* Set NAND device control parameters */ + if (init->bank == EBI_NAND_BANK2) { + MODIFY_REG(dev->PCTRLR2, PCTRLR_CLEAR_MASK, ((uint32_t)init->wait | + (uint32_t)EBI_PCTRLR_MEMORY_TYPE_NAND | + (uint32_t)init->width | + (uint32_t)init->ecc | + (uint32_t)init->size | + (uint32_t)((init->cle_time) << EBI_PCTRLRx_CRDLY_POSS) | + (uint32_t)((init->ale_time) << EBI_PCTRLRx_ARDLY_POSS))); + } + else { + MODIFY_REG(dev->PCTRLR3, PCTRLR_CLEAR_MASK, ((uint32_t)init->wait | + (uint32_t)EBI_PCTRLR_MEMORY_TYPE_NAND | + (uint32_t)init->width | + (uint32_t)init->ecc | + (uint32_t)init->size | + (uint32_t)((init->cle_time) << EBI_PCTRLRx_CRDLY_POSS) | + (uint32_t)((init->ale_time) << EBI_PCTRLRx_ARDLY_POSS))); + } +} + +/** + * @brief Initializes the EBI_NAND Common space Timing according to the specified + * parameters in the EBI_NAND_TimingTypeDef + * @param dev: Pointer to NAND device instance + * @param timing: Pointer to NAND timing structure + * @param bank: NAND bank number + * @retval None + */ +void ald_ebi_nand_comm_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_SETUP_TIME(timing->time)); + assert_param(IS_EBI_WAIT_TIME(timing->wait_time)); + assert_param(IS_EBI_HOLD_TIME(timing->hold_time)); + assert_param(IS_EBI_HIZ_TIME(timing->hiz_time)); + assert_param(IS_EBI_NAND_BANK(bank)); + + /* Set EBI_NAND device timing parameters */ + if (bank == EBI_NAND_BANK2) { + MODIFY_REG(dev->PMEMR2, PMEMR_CLEAR_MASK, (timing->time | \ + ((timing->wait_time) << EBI_PMEMRx_MEMWAIT_POSS) | \ + ((timing->hold_time) << EBI_PMEMRx_MEMHOLD_POSS) | \ + ((timing->hiz_time) << EBI_PMEMRx_MEMHIZT_POSS))); + } + else { + MODIFY_REG(dev->PMEMR3, PMEMR_CLEAR_MASK, (timing->time | \ + ((timing->wait_time) << EBI_PMEMRx_MEMWAIT_POSS) | \ + ((timing->hold_time) << EBI_PMEMRx_MEMHOLD_POSS) | \ + ((timing->hiz_time) << EBI_PMEMRx_MEMHIZT_POSS))); + } +} + +/** + * @brief Initializes the EBI_NAND Attribute space Timing according to the specified + * parameters in the EBI_NAND_TimingTypeDef + * @param dev: Pointer to NAND device instance + * @param timing: Pointer to NAND timing structure + * @param bank: NAND bank number + * @retval None + */ +void ald_ebi_nand_attr_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_SETUP_TIME(timing->time)); + assert_param(IS_EBI_WAIT_TIME(timing->wait_time)); + assert_param(IS_EBI_HOLD_TIME(timing->hold_time)); + assert_param(IS_EBI_HIZ_TIME(timing->hiz_time)); + assert_param(IS_EBI_NAND_BANK(bank)); + + /* Set FMC_NAND device timing parameters */ + if (bank == EBI_NAND_BANK2) { + MODIFY_REG(dev->PATTR2, PATTR_CLEAR_MASK, (timing->time | \ + ((timing->wait_time) << EBI_PATTRx_ATTWAIT_POSS) | \ + ((timing->hold_time) << EBI_PATTRx_ATTHOLD_POSS) | \ + ((timing->hiz_time) << EBI_PATTRx_ATTHIZT_POSS))); + } + else { + MODIFY_REG(dev->PATTR3, PATTR_CLEAR_MASK, (timing->time | \ + ((timing->wait_time) << EBI_PATTRx_ATTWAIT_POSS) | \ + ((timing->hold_time) << EBI_PATTRx_ATTHOLD_POSS) | \ + ((timing->hiz_time) << EBI_PATTRx_ATTHIZT_POSS))); + } +} + +/** + * @brief DeInitializes the EBI_NAND device + * @param dev: Pointer to NAND device instance + * @param bank: NAND bank number + * @retval None + */ +void ald_ebi_nand_deinit(EBI_NAND_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + /* Disable the NAND Bank */ + ald_ebi_nand_disable(dev, bank); + + /* De-initialize the NAND Bank */ + if (bank == EBI_NAND_BANK2) { + /* Set the EBI_NAND_BANK2 registers to their reset values */ + WRITE_REG(dev->PCTRLR2, 0x00000018U); + WRITE_REG(dev->STAR2, 0x00000040U); + WRITE_REG(dev->PMEMR2, 0xFCFCFCFCU); + WRITE_REG(dev->PATTR2, 0xFCFCFCFCU); + } + /* EBI_Bank3_NAND */ + else { + /* Set the EBI_NAND_BANK3 registers to their reset values */ + WRITE_REG(dev->PCTRLR3, 0x00000018U); + WRITE_REG(dev->STAR3, 0x00000040U); + WRITE_REG(dev->PMEMR3, 0xFCFCFCFCU); + WRITE_REG(dev->PATTR3, 0xFCFCFCFCU); + } +} +/** + * @} + */ + +/** @defgroup EBI_Public_Functions_Group4 NAND-FLASH control functions + * @brief NAND-FLASH control functions + * @{ + */ +/** + * @brief Enable the NAND device access + * @param dev: EBI_NAND Instance + * @param bank: EBI_NAND Bank + * @retval None + */ +void ald_ebi_nand_enable(EBI_NAND_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + if (bank == EBI_NAND_BANK2) + SET_BIT(dev->PCTRLR2, EBI_PCTRLRx_MEMBKEN_MSK); + else + SET_BIT(dev->PCTRLR3, EBI_PCTRLRx_MEMBKEN_MSK); +} + +/** + * @brief Disable the NAND device access. + * @param dev: EBI_NAND Instance + * @param bank: EBI_NAND Bank + * @retval None + */ +void ald_ebi_nand_disable(EBI_NAND_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + if (bank == EBI_NAND_BANK2) + CLEAR_BIT(dev->PCTRLR2, EBI_PCTRLRx_MEMBKEN_MSK); + else + CLEAR_BIT(dev->PCTRLR3, EBI_PCTRLRx_MEMBKEN_MSK); +} + +/** + * @brief Enable the NAND device interrupt. + * @param dev: EBI_NAND Instance + * @param bank: EBI_NAND Bank + * @param it: EBI_NAND interrupt + * This parameter can be any combination of the following values: + * @arg EBI_IT_RISING_EDGE: Interrupt rising edge. + * @arg EBI_IT_LEVEL: Interrupt level. + * @arg EBI_IT_FALLING_EDGE: Interrupt falling edge. + * @retval None + */ +void ald_ebi_nand_enable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + if (bank == EBI_NAND_BANK2) + SET_BIT(dev->STAR2, it); + else + SET_BIT(dev->STAR3, it); +} + +/** + * @brief Disable the NAND device interrupt. + * @param dev: EBI_NAND Instance + * @param bank: EBI_NAND Bank + * @param it: EBI_NAND interrupt + * This parameter can be any combination of the following values: + * @arg EBI_IT_RISING_EDGE: Interrupt rising edge. + * @arg EBI_IT_LEVEL: Interrupt level. + * @arg EBI_IT_FALLING_EDGE: Interrupt falling edge. + * @retval None + */ +void ald_ebi_nand_disable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + if (bank == EBI_NAND_BANK2) + CLEAR_BIT(dev->STAR2, it); + else + CLEAR_BIT(dev->STAR3, it); +} + +/** + * @brief Enables dynamically EBI_NAND ECC feature. + * @param dev: Pointer to NAND device instance + * @param bank: NAND bank number + * @retval None + */ +void ald_ebi_nand_ecc_enable(EBI_NAND_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + /* Enable ECC feature */ + if (bank == EBI_NAND_BANK2) + SET_BIT(dev->PCTRLR2, EBI_PCTRLRx_ECCEN_MSK); + else + SET_BIT(dev->PCTRLR3, EBI_PCTRLRx_ECCEN_MSK); +} + +/** + * @brief Disables dynamically EBI_NAND ECC feature. + * @param dev: Pointer to NAND device instance + * @param bank: NAND bank number + * @retval None + */ +void ald_ebi_nand_ecc_disable(EBI_NAND_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + /* Disable ECC feature */ + if (bank == EBI_NAND_BANK2) + CLEAR_BIT(dev->PCTRLR2, EBI_PCTRLRx_ECCEN_MSK); + else + CLEAR_BIT(dev->PCTRLR3, EBI_PCTRLRx_ECCEN_MSK); +} + +/** + * @brief Disables dynamically EBI_NAND ECC feature. + * @param dev: Pointer to NAND device instance + * @param val: Pointer to ECC value + * @param bank: NAND bank number + * @param timeout: Timeout wait value + * @retval ALD status + */ +ald_status_t ald_ebi_nand_get_ecc(EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout) +{ + uint32_t tick; + + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + tick = ald_get_tick(); + + /* Wait until FIFO is empty */ + while (ald_ebi_nand_get_flag(dev, bank, EBI_FLAG_FEMPT) == RESET) { + if (timeout != ALD_MAX_DELAY) { + if ((timeout == 0U) || ((ald_get_tick() - tick) > timeout)) + return TIMEOUT; + } + } + + if (bank == EBI_NAND_BANK2) + *val = (uint32_t)dev->ECCRESULT2; + else + *val = (uint32_t)dev->ECCRESULT3; + + return OK; +} + +/** + * @brief Get flag status of the NAND device. + * @param dev: EBI_NAND Instance + * @param bank : EBI_NAND Bank + * @param flag : EBI_NAND flag + * This parameter can be any combination of the following values: + * @arg EBI_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg EBI_FLAG_LEVEL: Interrupt level edge flag. + * @arg EBI_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg EBI_FLAG_FEMPT: FIFO empty flag. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_ebi_nand_get_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + if (bank == EBI_NAND_BANK2) { + if (dev->STAR2 & flag) + return SET; + } else { + if (dev->STAR3 & flag) + return SET; + } + + return RESET; +} + +/** + * @brief Clear flag status of the NAND device. + * @param dev: EBI_NAND Instance + * @param bank: EBI_NAND Bank + * @param flag: EBI_NAND flag + * This parameter can be any combination of the following values: + * @arg EBI_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg EBI_FLAG_LEVEL: Interrupt level edge flag. + * @arg EBI_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg EBI_FLAG_FEMPT: FIFO empty flag. + * @retval None + */ +void ald_ebi_nand_clear_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + /* Enable ECC feature */ + if (bank == EBI_NAND_BANK2) + CLEAR_BIT(dev->STAR2, flag); + else + CLEAR_BIT(dev->STAR3, flag); +} +/** + * @} + */ + +/** @defgroup EBI_Public_Functions_Group5 LCD initialize functions + * @brief LCD initialize functions + * @{ + */ +/** + * @brief Initializes the EBI_LCD device according to the specified + * control parameters in the nor_lcd_handle_t + * @param hlcd: Pointer to LCD device instance + * @retval None + */ +void ald_ebi_lcd_init(ebi_lcd_handle_t *hlcd) +{ + assert_param(IS_EBI_LCD_DEVICE(hlcd->inst)); + assert_param(IS_EBI_BANK_NUMBER(hlcd->init.bank)); + assert_param(IS_EBI_HORIZONTAL_SYNCH(hlcd->init.h_polarity)); + assert_param(IS_EBI_VERTICAL_SYNCH(hlcd->init.v_polarity)); + assert_param(IS_EBI_DATA_ENABLE(hlcd->init.data_polarity)); + assert_param(IS_EBI_LCD_ENABLE(hlcd->init.enable)); + assert_param(IS_EBI_DATA_CLOCK(hlcd->init.clk_polarity)); + assert_param(IS_EBI_LCD_DATASETUP_TIME(hlcd->init.setup)); + assert_param(IS_EBI_HYSNC_PULSE_WIDTH(hlcd->init.h_width)); + assert_param(IS_EBI_VSYNC_PULSE_WIDTH(hlcd->init.v_width)); + assert_param(IS_EBI_FRAME_LINE_NUMBER(hlcd->init.nr_line)); + assert_param(IS_EBI_FRAME_PIXEL_NUMBER(hlcd->init.nr_pixel)); + + MODIFY_REG(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4], LCDCTRL_CLEAR_MASK, + ((uint32_t)hlcd->init.h_polarity | + (uint32_t)hlcd->init.v_polarity | + hlcd->init.data_polarity | + hlcd->init.enable | + hlcd->init.clk_polarity | + hlcd->init.setup << EBI_LCDCTRLx_DATASETUP_POSS | + hlcd->init.h_width << EBI_LCDCTRLx_VSYNCWID_POSS | + hlcd->init.v_width << EBI_LCDCTRLx_HSYNCWID_POSS)); + + WRITE_REG(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4 + 1], + (hlcd->init.nr_line << EBI_LCDSTx_LINECNT_POSS | + hlcd->init.nr_pixel << EBI_LCDSTx_PXLCNT_POSS)); +} + +/** + * @brief Reset the EBI_LCD + * @param hlcd: Pointer to LCD device instance + * @retval None + */ +void ald_ebi_lcd_reset(ebi_lcd_handle_t *hlcd) +{ + assert_param(IS_EBI_LCD_RESET(hlcd->init.reset)); + assert_param(IS_EBI_BANK_NUMBER(hlcd->init.bank)); + + SET_BIT(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4], hlcd->init.reset); +} + +/** + * @} + */ +/** + * @} + */ +#endif +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c new file mode 100644 index 0000000000000000000000000000000000000000..c17ba16b7a578648d7af12a63bc3c28dfe8b5065 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash.c @@ -0,0 +1,229 @@ +/** + ********************************************************************************* + * + * @file ald_flash.c + * @brief FLASH module driver. + * + * @version V1.0 + * @date 17 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + * + ********************************************************************************* + * @verbatim + ============================================================================== + ##### FLASH Peripheral features ##### + ============================================================================== + [..] + Base address is 0x00000000 + + [..] + FLASH have just one programme mode , word programme. + word programme can programme 8 bytes once ; + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provide private functions for ald_flash_ext.c to use + @endverbatim + */ + +#include "ald_flash.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH module driver + * @{ + */ + +#ifdef ALD_FLASH + +#if defined ( __ICCARM__ ) +#define __RAMFUNC __ramfunc +#else +#define __RAMFUNC +#endif + +/** @defgroup Flash_Private_Variables Flash Private Variables + * @{ + */ +/* global variable*/ +static op_cmd_type OP_CMD = OP_FLASH; +/** + * @} + */ + +/** @defgroup Flash_Private_Functions Flash Private Functions + * @brief Flash Private functions + * @{ + */ +/** + * @brief Unlock the flash. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC static ald_status_t flash_unlock(void) +{ + uint16_t i; + uint16_t op_cmd = OP_CMD; + + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + return ERROR; + + FLASH_REG_UNLOCK(); + FLASH_IAP_ENABLE(); + FLASH_REQ(); + + for (i = 0; i < 0xFFFF; i++) { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)) + break; + } + + return i == 0xFFFF ? ERROR : OK; +} + +/** + * @brief Lock the flash. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC static ald_status_t flash_lock(void) +{ + uint16_t i; + uint16_t op_cmd = OP_CMD; + + FLASH_REG_UNLOCK(); + WRITE_REG(MSC->FLASHCR, 0x0); + + for (i = 0; i < 0xFFFF; i++) { + if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))) + break; + } + + return i == 0xFFFF ? ERROR : OK; +} + +/** + * @brief Erase one page. + * @param addr: The erased page's address + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC ald_status_t flash_page_erase(uint32_t addr) +{ + uint32_t i; + uint16_t op_cmd = OP_CMD; + + if (flash_unlock() != OK) + goto end; + + if (op_cmd == OP_FLASH) { + CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); + } + else { + SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); + } + + WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE); + + for (i = 0; i < 0xFFFF; i++) { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + continue; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK)) + goto end; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK)) + goto end; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK)) + break; + } + + if (i == 0xFFFF) + goto end; + + if (flash_lock() == ERROR) + goto end; + + return OK; +end: + flash_lock(); + return ERROR; +} + +/** + * @brief Programme a word. + * @param addr: The word's address, it is must word align. + * @param data: The 8 bytes data be write. + * @param len: The number of data be write. + * @param fifo: Choose if use fifo. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo) +{ + uint16_t i; + uint16_t prog_len; + uint32_t *p_data = data; + uint16_t op_cmd = OP_CMD; + + if (flash_unlock() != OK) + goto end; + + if (op_cmd == OP_FLASH) + CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + else + SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS); + MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS); + + for (prog_len = 0; prog_len < len; prog_len++) { + if (fifo) { + WRITE_REG(MSC->FLASHFIFO, p_data[0]); + WRITE_REG(MSC->FLASHFIFO, p_data[1]); + } + else { + WRITE_REG(MSC->FLASHDL, p_data[0]); + WRITE_REG(MSC->FLASHDH, p_data[1]); + WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP); + } + + p_data += 2; + + for (i = 0; i < 0xFFFF; i++) { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + continue; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK)) + break; + } + } + if (i == 0xFFFF) + goto end; + + if (flash_lock() == ERROR) + goto end; + + return OK; +end: + flash_lock(); + return ERROR; +} +/** + * @} + */ + +#endif + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c new file mode 100644 index 0000000000000000000000000000000000000000..845b02e5fb75cacb03bf7ca9e28361f7530ed3a4 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_flash_ext.c @@ -0,0 +1,330 @@ +/** + ********************************************************************************* + * + * @file ald_flash_ext.c + * @brief FLASH extra module driver. + * + * @version V1.0 + * @date 17 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + * + ********************************************************************************* + * @verbatim + ============================================================================== + ##### FLASH Peripheral features ##### + ============================================================================== + [..] + Base address is 0x00000000 + + [..] + FLASH have just one programme mode , word programme. + word programme can programme 8 bytes once ; + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) programme flash using ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len) + (++) call the function and supply all the three paraments is needs, addr means + the first address to write in this operation, buf is a pointer to the data which + need writing to flash. + + (#) erase flash using ald_flash_erase(uint32_t addr, uint16_t len) + (++) call the function and supply two paraments, addr is the first address to erase, + len is the length to erase + + (#) read flash using ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) + (++) read the flash and save to a buffer, ram_addr is the buffer's first address, + addr is the start reading address in flash, len is the length need read + + @endverbatim + */ + + +#include "ald_flash.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +#ifdef ALD_FLASH + +/** @addtogroup Flash_Private_Variables + * @{ + */ +/* opration buffer*/ +static uint8_t write_buf[FLASH_PAGE_SIZE]; +/** + * @} + */ + +/** @addtogroup Flash_Private_Functions + * @{ + */ + +/** + * @brief Check whether the flash between the given address section + * have been writen, if it have been writen, return TRUE, else + * return FALSE. + * @param begin_addr: The begin address. + * @param end_addr: The end address. + * @retval The check result + * - TRUE + * - FALSE + */ +static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr) +{ + uint8_t* addr_to_read; + uint8_t value; + uint32_t index; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(begin_addr)); + assert_param(IS_FLASH_ADDRESS(end_addr)); + + addr_to_read = (uint8_t *)begin_addr; + index = begin_addr; + value = 0xFF; + + if (begin_addr > end_addr) + return FALSE; + + while (index++ <= end_addr) { + value = *addr_to_read++; + + if (value != 0xFF) + break; + } + + return value == 0xFF ? FALSE : TRUE; +} +/** + * @} + */ + +/** @defgroup Flash_Public_Functions Flash Public Functions + * @verbatim + =============================================================================== + ##### Flash operation functions ##### + =============================================================================== + [..] + This section provides functions allowing to operate flash, such as read and write. + + @endverbatim + * @{ + */ + +/** + * @brief read the specified length bytes from flash, and store to the specified area. + * @param ram_addr: the specified area to store the reading bytes. + * @param addr: the start address. + * @param len: the length to read. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) +{ + uint32_t i; + uint32_t temp; + + assert_param(IS_4BYTES_ALIGN(ram_addr)); + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + + temp = (uint32_t)ram_addr; + + if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0)) + return ERROR; + + for (i = 0; i < len; i++) + ram_addr[i] = ((uint32_t *)addr)[i]; + + return OK; +} + +/** + * @brief Write the give bytes to the given address section. + * @param addr: The start address to write. + * @param buf: The bytes' address. + * @param len: The length to write,and multiple of 2. + * @retval Status, see @ref ald_status_t. + */ + +ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len) +{ + uint32_t index = 0; + uint32_t para = 0; + uint32_t index2 = 0; + uint32_t start_write_addr; + uint32_t end_write_addr; + uint32_t start_word_addr; + uint32_t end_word_addr; + uint16_t len_to_write; + uint32_t len_index; + type_bool_t need_erase_page; + + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + + len_to_write = len; + + __disable_irq(); + while (len_to_write > 0) { + need_erase_page = FALSE; + + for (index = 0; index < FLASH_PAGE_SIZE; index++) + write_buf[index] = 0xFF; + + start_write_addr = addr + (len - len_to_write); + end_write_addr = addr + len - 1; + end_write_addr = FLASH_PAGE_ADDR(start_write_addr) == FLASH_PAGE_ADDR(end_write_addr) + ? end_write_addr : FLASH_PAGEEND_ADDR(start_write_addr); + need_erase_page = page_have_writen(FLASH_WORD_ADDR(start_write_addr), + FLASH_WORDEND_ADDR(end_write_addr)); + + if (need_erase_page) { + if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr), + FLASH_PAGE_SIZE >> 2)) { + __enable_irq(); + return ERROR; + } + + if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr))) { + __enable_irq(); + return ERROR; + } + + para = end_write_addr & (FLASH_PAGE_SIZE - 1); + index = start_write_addr & (FLASH_PAGE_SIZE - 1); + index2 = len - len_to_write; + + while (index <= para) + write_buf[index++] = buf[index2++]; + + index2 = 0; + index = FLASH_PAGE_ADDR(start_write_addr); + para = FLASH_PAGE_ADDR(start_write_addr) + FLASH_PAGE_SIZE; + len_index = FLASH_PAGE_SIZE; + } + else { + para = end_write_addr & (FLASH_PAGE_SIZE - 1); + index = start_write_addr & (FLASH_PAGE_SIZE - 1); + index2 = len - len_to_write; + + while (index <= para) + write_buf[index++] = buf[index2++]; + + start_word_addr = FLASH_WORD_ADDR(start_write_addr); + end_word_addr = FLASH_WORDEND_ADDR(end_write_addr); + index2 = (FLASH_WORD_ADDR(start_word_addr) - FLASH_PAGE_ADDR(start_word_addr)); + index = start_word_addr; + len_index = end_word_addr - start_word_addr + 1; + } + + if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO)) { + __enable_irq(); + return ERROR; + } + + len_to_write = len_to_write - (end_write_addr - start_write_addr + 1); + } + + __enable_irq(); + return OK; +} + +/** + * @brief erase The flash between the given address section. + * @param addr: The start address to erase. + * @param len: The length to erase. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_flash_erase(uint32_t addr, uint16_t len) +{ + int32_t index; + int32_t para; + int32_t start_erase_addr; + int32_t end_erase_addr; + uint16_t len_not_erase; + uint32_t len_index; + type_bool_t page_need_save; + + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + + len_not_erase = len; + + __disable_irq(); + while (len_not_erase > 0) { + page_need_save = FALSE; + + start_erase_addr = addr + len - len_not_erase; + end_erase_addr = addr + len - 1; + end_erase_addr = (FLASH_PAGE_ADDR(start_erase_addr) == FLASH_PAGE_ADDR(end_erase_addr)) + ? end_erase_addr : FLASH_PAGEEND_ADDR(start_erase_addr); + + if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr)) { + if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1))) + page_need_save = TRUE; + } + if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) { + if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr))) + page_need_save = TRUE; + } + + if (page_need_save) { + if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr), + FLASH_PAGE_SIZE >> 2)) { + __enable_irq(); + return ERROR; + } + } + + if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr))) { + __enable_irq(); + return ERROR; + } + + if (page_need_save) { + para = end_erase_addr & (FLASH_PAGE_SIZE - 1); + index = start_erase_addr & (FLASH_PAGE_SIZE - 1); + + while (index <= para) + write_buf[index++] = 0xFF; + + index = FLASH_PAGE_ADDR(start_erase_addr); + len_index = FLASH_PAGE_SIZE; + if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) { + __enable_irq(); + return ERROR; + } + } + len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1); + } + + __enable_irq(); + return OK; +} +/** + * @} + */ + + +#endif + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..58e1481908d1e431fba21efe5c36c2665391668c --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_gpio.c @@ -0,0 +1,635 @@ +/** + ********************************************************************************* + * + * @file ald_gpio.c + * @brief GPIO module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization functions + * + IO operation functions + * + Control functions + * + * @version V1.0 + * @date 07 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + * @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each + port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software + in several modes: + (+) Input mode + (+) Analog mode + (+) Output mode + (+) External interrupt/event lines + + [..] + During and just after reset, the external interrupt lines are not active and + the I/O ports are configured Analog mode. + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + [..] + In Output mode, each IO can be configured on open-drain or push-pull + type and the Output driver can be selected depending on ODRV register. + + [..] + In Input mode, each IO can select filter function. + + [..] + Each IO can select TTL or SMIT type. + + [..] + Each IO have up to eight functions, user can configure the functions depend + on the user's environment. + + [..] + Each IO can be locked. Once locked, uesr can only change the output data. + Only when the CPU reset to unlock the GPIO port. + + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + Each input line can be independently configured to select the type (event or interrupt) and + the corresponding trigger event (rising or falling). Each line can also masked + independently. A pending register maintains the status line of the interrupt requests. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO clock. + + (#) Configure the GPIO pin(s) using ald_gpio_init(). + (++) Configure the IO mode using "mode" member from gpio_init_t structure + (++) Activate Pull-up, Pull-down resistor using "pupd" member from gpio_init_t + structure. + (++) In Output mode, configured on open-drain or push-pull using "odos" + member from gpio_init_t structure. + (++) In Output mode, configured output driver using "odrv" member + from gpio_init_t structure. + (++) In Input mode, configured filter function using "flt" member + from gpio_init_t structure. + (++) Configured type using "type" member from gpio_init_t structure. + (++) Configured functions using "func" member from gpio_init_t structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + + (#) Configure the GPIO pin(s) using ald_gpio_init_default(). + (++) Configure GPIO pin using default param: + init.mode = GPIO_MODE_OUTPUT; + init.odos = GPIO_PUSH_PULL; + init.pupd = GPIO_PUSH_UP; + init.podrv = GPIO_OUT_DRIVE_6; + init.nodrv = GPIO_OUT_DRIVE_6; + init.flt = GPIO_FILTER_DISABLE; + init.type = GPIO_TYPE_TTL; + init.func = GPIO_FUNC_1; + + (#) In case of external interrupt/event mode selection, user need invoke + ald_gpio_exti_init() to configure some param. And then invoke + ald_gpio_exti_interrupt_config() to enable/disable external interrupt/event. + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using NVIC_SetPriority() and enable it using + NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use GPIO_read_pin(). + + (#) To set/reset the level of a pin configured in output mode use + ald_gpio_write_pin()/ald_gpio_toggle_pin(). + + (#) To lock pin configuration until next reset use ald_gpio_lock_pin(). + + (#) Configure external interrupt mode and enable/disable using + ald_gpio_exti_interrupt_config(). + + (#) Get external interrupt flag status using ald_gpio_exti_get_flag_status(). + + (#) Clear pending external interrupt flag status using + ald_gpio_exti_clear_flag_status(). + + @endverbatim + */ + +#include "ald_conf.h" +#include "ald_gpio.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO module driver + * @{ + */ + +#ifdef ALD_GPIO + +/** @defgroup GPIO_Public_Functions GPIO Public Functions + * @{ + */ + +/** @defgroup GPIO_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the GPIOs or external + interrupt to be ready for use. + + @endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified + * parameters in the gpio_init_t. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: The pin which need to initialize. + * @param init: Pointer to a gpio_init_t structure that can contains + * the configuration information for the specified parameters. + * @retval None + */ +void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) +{ + uint32_t i, pos, mask, tmp; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_MODE(init->mode)); + assert_param(IS_GPIO_ODOS(init->odos)); + assert_param(IS_GPIO_PUPD(init->pupd)); + assert_param(IS_GPIO_ODRV(init->podrv)); + assert_param(IS_GPIO_ODRV(init->nodrv)); + assert_param(IS_GPIO_FLT(init->flt)); + assert_param(IS_GPIO_TYPE(init->type)); + assert_param(IS_GPIO_FUNC(init->func)); + + for (i = 0; i < 16; ++i) { + if (((pin >> i) & 0x1) == 0) + continue; + + /* Get position and 2-bits mask */ + pos = i << 1; + mask = 0x3 << pos; + + /* Set PIN mode */ + tmp = READ_REG(GPIOx->MODE); + tmp &= ~mask; + tmp |= (init->mode << pos); + WRITE_REG(GPIOx->MODE, tmp); + + /* Set PIN open-drain or push-pull */ + tmp = READ_REG(GPIOx->ODOS); + tmp &= ~mask; + tmp |= (init->odos << pos); + WRITE_REG(GPIOx->ODOS, tmp); + + /* Set PIN push-up or/and push-down */ + tmp = READ_REG(GPIOx->PUPD); + tmp &= ~mask; + tmp |= (init->pupd << pos); + WRITE_REG(GPIOx->PUPD, tmp); + + /* Set PIN output P-MOS driver */ + tmp = READ_REG(GPIOx->PODRV); + tmp &= ~mask; + tmp |= (init->podrv << pos); + WRITE_REG(GPIOx->PODRV, tmp); + + /* Set PIN output N-MOS driver */ + tmp = READ_REG(GPIOx->NODRV); + tmp &= ~mask; + tmp |= (init->nodrv << pos); + WRITE_REG(GPIOx->NODRV, tmp); + + /* Get position and 1-bit mask */ + pos = i; + mask = 0x1 << pos; + + /* Set PIN filter enable or disable */ + tmp = READ_REG(GPIOx->FLT); + tmp &= ~mask; + tmp |= (init->flt << pos); + WRITE_REG(GPIOx->FLT, tmp); + + /* Set PIN type ttl or smit */ + tmp = READ_REG(GPIOx->TYPE); + tmp &= ~mask; + tmp |= (init->type << pos); + WRITE_REG(GPIOx->TYPE, tmp); + + /* Configure PIN function */ + pos = i < 8 ? (i << 2) : ((i - 8) << 2); + mask = 0xF << pos; + tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1); + tmp &= ~mask; + tmp |= (init->func << pos); + i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp); + } + + return; +} + +/** + * @brief Initialize the GPIOx peripheral using the default parameters. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: The pin which need to initialize. + * @retval None + */ +void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + gpio_init_t init; + + /* Fill GPIO_init_t structure with default parameter */ + init.mode = GPIO_MODE_OUTPUT; + init.odos = GPIO_PUSH_PULL; + init.pupd = GPIO_PUSH_UP; + init.podrv = GPIO_OUT_DRIVE_6; + init.nodrv = GPIO_OUT_DRIVE_6; + init.flt = GPIO_FILTER_DISABLE; + init.type = GPIO_TYPE_CMOS; + init.func = GPIO_FUNC_1; + + ald_gpio_init(GPIOx, pin, &init); + return; +} + +/** + * @brief Sets GPIO function to default(func0). + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @retval None + */ +void ald_gpio_func_default(GPIO_TypeDef *GPIOx) +{ + WRITE_REG(GPIOx->FUNC0, 0x00); + WRITE_REG(GPIOx->FUNC1, 0x00); + + return; +} + +/** + * @brief Initialize the external interrupt according to the specified + * parameters in the exti_init_t. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: The pin which need to initialize. + * @param init: Pointer to a exti_init_t structure that can contains + * the configuration information for the specified parameters. + * @retval None + */ +void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init) +{ + uint8_t i; + uint8_t port; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_FUNC_STATE(init->filter)); + assert_param(IS_EXTI_FLTCKS_TYPE(init->cks)); + + /* Get GPIO port */ + if (GPIOx == GPIOA) + port = 0x0; + else if (GPIOx == GPIOB) + port = 0x1; + else if (GPIOx == GPIOC) + port = 2; + else if (GPIOx == GPIOD) + port = 3; + else if (GPIOx == GPIOE) + port = 4; + else if (GPIOx == GPIOF) + port = 5; + else if (GPIOx == GPIOG) + port = 6; + else if (GPIOx == GPIOH) + port = 7; + else + port = 0; + + /* Get Pin index */ + for (i = 0; i < 16; ++i) { + if (((pin >> i) & 0x1) == 0x1) + break; + } + + /* Select external interrupt line */ + if (i <= 7) { + EXTI->EXTIPSR0 &= ~(0x7 << (i * 4)); + EXTI->EXTIPSR0 |= (port << (i * 4)); + } + else { + i -= 8; + EXTI->EXTIPSR1 &= ~(0x7 << (i * 4)); + EXTI->EXTIPSR1 |= (port << (i * 4)); + } + + /* Configure filter parameter */ + if (init->filter == ENABLE) { + SET_BIT(EXTI->EXTIFLTCR, pin); + MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTCKS_MSK, init->cks << GPIO_EXTIFLTCR_FLTCKS_POSS); + MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS); + } + else { + CLEAR_BIT(EXTI->EXTIFLTCR, pin); + } + + return; +} +/** + * @} + */ + +/** @defgroup GPIO_Public_Functions_Group2 IO operation functions + * @brief GPIO Read and Write + * + @verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the GPIOs. + + @endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: Specifies the pin to read. + * @retval The input pin value + * - BIT_SET + * - BIT_RESET + */ +uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + if (READ_BIT(GPIOx->DIN, pin)) + return BIT_SET; + + else + return BIT_RESET; +} + +/** + * @brief Set or clear the select Pin data. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: The specified pin to be written. + * @param val: The specifies value to be written. + * @retval None + */ +void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + if ((val & (0x01)) == 0x00) + CLEAR_BIT(GPIOx->DOUT, pin); + else + SET_BIT(GPIOx->DOUT, pin); + + return; +} + +/** + * @brief Turn over the select data. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: Specifies the pin to turn over. + * @retval None + */ +void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + WRITE_REG(GPIOx->BIR, pin); + return; +} + +/** + * @brief Turn over the direction. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: Specifies the pin to turn over. + * @retval None + */ +void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + uint32_t i, pos, mask, tmp, value; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + for (i = 0; i < 16; ++i) { + if (((pin >> i) & 0x1) == 0) + continue; + + /* Get position and 2-bits mask */ + pos = i << 1; + mask = 0x3 << pos; + + /* Get the new direction */ + tmp = READ_REG(GPIOx->MODE); + value = (tmp >> pos) & 0x3; + + if ((value == 2) || (value == 3)) + value = 1; + else if (value == 1) { + value = 2; + } + else { + continue; /* do nothing */ + } + + /* Set PIN mode */ + tmp &= ~mask; + tmp |= (value << pos); + WRITE_REG(GPIOx->MODE, tmp); + } + + return; +} + +/** + * @brief Lock the GPIO prot. Once locked, can + * only change the output data. Only when the CPU + * reset to unlock the GPIO port. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: The specified Pin to be written. + * @retval None + */ +void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, UNLOCK_KEY << GPIO_LOCK_KEY_POSS); + WRITE_REG(GPIOx->LOCK, pin); + + return; +} + +/** + * @brief Read the specified input port pin. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @retval The value; + */ +uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + + return READ_REG(GPIOx->DIN); +} + +/** + * @brief Set or clear the select Pin data. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param val: The specifies value to be written. + * @retval None + */ +void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + + WRITE_REG(GPIOx->DOUT, val); + return; +} + + +/** + * @} + */ + +/** @defgroup GPIO_Public_Functions_Group3 Control functions + * @brief EXTI Control functions + * + @verbatim + =============================================================================== + ##### Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to + control external interrupt. + + @endverbatim + * @{ + */ + +/** + * @brief Configure the interrupt according to the specified parameter. + * @param pin: The Pin which need to configure. + * @param style: External interrupt trigger style. + * @param status: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status) +{ + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_TRIGGER_STYLE(style)); + assert_param(IS_FUNC_STATE(status)); + + if (status == ENABLE) { + if (style == EXTI_TRIGGER_RISING_EDGE) { + SET_BIT(EXTI->EXTIRER, pin); + } + else if (style == EXTI_TRIGGER_TRAILING_EDGE) { + SET_BIT(EXTI->EXTIFER, pin); + } + else if (style == EXTI_TRIGGER_BOTH_EDGE) { + SET_BIT(EXTI->EXTIRER, pin); + SET_BIT(EXTI->EXTIFER, pin); + } + else { + ; /* do nothing */ + } + + WRITE_REG(EXTI->EXTICFR, 0xffff); + SET_BIT(EXTI->EXTIEN, pin); + } + else { + if (style == EXTI_TRIGGER_RISING_EDGE) { + CLEAR_BIT(EXTI->EXTIRER, pin); + } + else if (style == EXTI_TRIGGER_TRAILING_EDGE) { + CLEAR_BIT(EXTI->EXTIFER, pin); + } + else if (style == EXTI_TRIGGER_BOTH_EDGE) { + CLEAR_BIT(EXTI->EXTIRER, pin); + CLEAR_BIT(EXTI->EXTIFER, pin); + } + else { + ; /* do nothing */ + } + + CLEAR_BIT(EXTI->EXTIEN, pin); + } + + return; +} + +/** + * @brief Get the Flag about external interrupt. + * @param pin: The pin which belong to external interrupt. + * @retval Flag status + * - SET + * - RESET + */ +flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin) +{ + assert_param(IS_GPIO_PIN(pin)); + + if (READ_BIT(EXTI->EXTIFLAG, pin)) + return SET; + + return RESET; +} + +/** + * @brief Clear the external interrupt flag. + * @param pin: The pin which belong to external interrupt. + * @retval None + */ +void ald_gpio_exti_clear_flag_status(uint16_t pin) +{ + assert_param(IS_GPIO_PIN(pin)); + + WRITE_REG(EXTI->EXTICFR, pin); + return; +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* ALD_GPIO */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..e08fd09c8bc246fe8b2c387d2aef7d8b72ef6141 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2c.c @@ -0,0 +1,2713 @@ +/** + ********************************************************************************* + * + * @file ald_i2c.c + * @brief I2C module driver. + * + * @version V1.0 + * @date 15 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C driver can be used as follows: + + (#) Declare a i2c_handle_t handle structure, for example: + i2c_handle_t hperh; + + (#) Configure the Communication Speed, Addressing mode, Own Address1, + Dual Addressing mode, Own Address2, General call and Nostretch mode in the hperh init structure. + + (#) Initialize the I2C registers by calling the ald_i2c_init(). + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using ald_i2c_master_send() + (+) Receive in master mode an amount of data in blocking mode using ald_i2c_master_recv() + (+) Transmit in slave mode an amount of data in blocking mode using ald_i2c_slave_send() + (+) Receive in slave mode an amount of data in blocking mode using ald_i2c_slave_recv() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using ald_i2c_mem_write() + (+) Read an amount of data in blocking mode from a specific memory address using ald_i2c_mem_read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) The I2C interrupts should have the highest priority in the application in order + to make them uninterruptible. + (+) Transmit in master mode an amount of data in non-blocking mode using ald_i2c_master_send_by_it() + (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_tx_cplt_cbk() + (+) Receive in master mode an amount of data in non-blocking mode using ald_i2c_master_recv_by_it() + (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_rx_cplt_cbk() + (+) Transmit in slave mode an amount of data in non-blocking mode using ald_i2c_slave_send_by_it() + (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_tx_cplt_cbk() + (+) Receive in slave mode an amount of data in non-blocking mode using ald_i2c_slave_recv_by_it() + (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) The I2C interrupts should have the highest priority in the application in order + to make them uninterruptible. + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + ald_i2c_mem_write_by_it() + (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_tx_cplt_cbk() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + ald_i2c_mem_read_by_it() + (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + ald_i2c_master_send_by_dma() + (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_tx_cplt_cbk() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + ald_i2c_master_recv_by_dma() + (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_rx_cplt_cbk() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + ald_i2c_slave_send_by_dma() + (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_tx_cplt_cbk() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + ald_i2c_slave_recv_by_dma() + (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + ald_i2c_mem_write_by_dma() + (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_tx_cplt_cbk() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + ald_i2c_mem_read_by_dma() + (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + + *** I2C ald_status_t driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C ald_status_t driver. + + (+) __I2C_ENABLE: Enable the I2C peripheral + (+) __I2C_DISABLE: Disable the I2C peripheral + (+) I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) I2C_DISABLE_IT: Disable the specified I2C interrupt + (@) You can refer to the I2C ald_status_t driver header file for more useful macros + + *** I2C Workarounds linked to Silicon Limitation *** + ==================================================== + [..] + Below the list of all silicon limitations implemented for library on our product. + (@) See ErrataSheet to know full silicon limitation list of your product. + + (#) Workarounds Implemented inside I2C library + (##) Wrong data read into data register (Polling and Interrupt mode) + (##) Start cannot be generated after a misplaced Stop + (##) Some software events must be managed before the current byte is being transferred: + Workaround: Use DMA in general, except when the Master is receiving a single byte. + For Interupt mode, I2C should have the highest priority in the application. + (##) Mismatch on the "Setup time for a repeated Start condition" timing parameter: + Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if + supported by the slave. + (##) Data valid time (tVD;DAT) violated without the OVR flag being set: + Workaround: If the slave device allows it, use the clock stretching mechanism + by programming no_stretch = I2C_NOSTRETCH_DISABLE in ald_i2c_init. + + @endverbatim + ********************************************************************************* + */ + +#include "ald_i2c.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C module driver + * @{ + */ + +#ifdef ALD_I2C + +/** @addtogroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +#define I2C_TIMEOUT_FLAG (__systick_interval / 20 + 1) +#define I2C_TIMEOUT_ADDR_SLAVE (__systick_interval * 10) +#define I2C_TIMEOUT_BUSY_FLAG (__systick_interval * 10) +#define I2C_MAX_DELAY 0xFFFFFFFF + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions I2C Private Functions + * @{ + */ + +#ifdef ALD_DMA +static void i2c_dma_master_send_cplt(void *argv); +static void i2c_dma_master_recv_cplt(void *argv); +static void i2c_dma_slave_send_cplt(void *argv); +static void i2c_dma_slave_recv_cplt(void *argv); +static void i2c_dma_mem_send_cplt(void *argv); +static void i2c_dma_mem_recv_cplt(void *argv); +static void i2c_dma_error(void *argv); +static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + uint16_t add_size, uint32_t timeout); +#endif +static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout); +static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout); +static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + uint16_t add_size, uint32_t timeout); +static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, + flag_status_t status, uint32_t timeout); +static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, uint32_t flag, uint32_t timeout); +static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout); +static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout); +static ald_status_t i2c_master_send_tc(i2c_handle_t *hperh); +static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh); +static ald_status_t i2c_master_recv_tc(i2c_handle_t *hperh); +static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh); +static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh); +static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh); +static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh); + +/** + * @} + */ + +/** @defgroup I2C_Public_Functions I2C Public functions + * @{ + */ + +/** @defgroup I2C_Public_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialiaze the I2Cx peripheral: + + (+) Call the function ald_i2c_init() to configure the selected device with + the selected configuration: + (++) Communication Speed + (++) Addressing mode + (++) Own Address 1 + (++) Dual Addressing mode + (++) Own Address 2 + (++) General call mode + (++) Nostretch mode + + (+) Call the function ald_i2c_reset() to restore the default configuration + of the selected I2Cx periperal. + +@endverbatim + * @{ + */ + +/** + * @brief I2C Configuration Speed function. + * @param hperh: Pointer to a i2c_handle_t structure that contains. + * the configuration information for the I2C speed. + * @param freqrange: I2C Peripheral bus clock + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_speed_init(i2c_handle_t *hperh, uint32_t freqrange) +{ + float Tsync = 0; + float Tscl = 0; + float Tfre = 0; + uint32_t Tper = 0; + uint32_t presc = 0; + uint32_t tmp = 0; + + if (hperh->init.module == I2C_MODULE_SLAVE) { + hperh->init.clk_speed = 450000; + } + + if (hperh->init.clk_speed <= 100000) { + tmp = freqrange / 4000000; + freqrange = 4000000; + } else { + tmp = freqrange / 8000000; + freqrange = 8000000; + } + + Tscl = 1000.0 / (hperh->init.clk_speed / 1000000.0); + Tfre = 1000.0 / I2C_FREQ_RANGE(freqrange); + + Tsync = (READ_BITS(hperh->perh->CON2, I2C_CON1_DNF_MSK, I2C_CON1_DNF_POSS) + 2) * 2 * Tfre; + + Tper = (uint32_t)((Tscl - Tsync) / Tfre); + + while (Tper > 512) { + Tper = Tper - 512; + presc++; + } + + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_PRESC_MSK, (presc + tmp ) << I2C_TIMINGR_PRESC_POSS); + + if (hperh->init.clk_speed <= I2C_STANDARD_MODE_MAX_CLK) { + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SDADEL_MSK, 2 << I2C_TIMINGR_SDADEL_POSS); + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, 4 << I2C_TIMINGR_SCLDEL_POSS); + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLH_MSK, (((Tper - 2) / 2) - 4) << I2C_TIMINGR_SCLH_POSS); + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLL_MSK, (((Tper - 2) / 2) + 4) << I2C_TIMINGR_SCLL_POSS); + } + else { + if (hperh->init.clk_speed <= I2C_FAST_MODE_MAX_CLK) { + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SDADEL_MSK, 2 << I2C_TIMINGR_SDADEL_POSS); + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, 3 << I2C_TIMINGR_SCLDEL_POSS); + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLH_MSK, (((Tper - 2) / 2) - 6) << I2C_TIMINGR_SCLH_POSS); + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLL_MSK, (((Tper - 2) / 2) + 6) << I2C_TIMINGR_SCLL_POSS); + } + else { + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SDADEL_MSK, 0 << I2C_TIMINGR_SDADEL_POSS); + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, 1 << I2C_TIMINGR_SCLDEL_POSS); + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLH_MSK, (((Tper - 2) / 2) - 3) << I2C_TIMINGR_SCLH_POSS); + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLL_MSK, (((Tper - 2) / 2) + 3) << I2C_TIMINGR_SCLL_POSS); + } + } + + return OK; +} +/** + * @brief Initializes the I2C according to the specified parameters + * in the i2c_init_t and initialize the associated handle. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_init(i2c_handle_t *hperh) +{ + uint32_t freqrange = ald_cmu_get_pclk1_clock(); + + if (hperh == NULL) + return ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_CLOCK_SPEED(hperh->init.clk_speed)); + assert_param(IS_I2C_ADDRESSING_MODE(hperh->init.addr_mode)); + assert_param(IS_I2C_GENERAL_CALL(hperh->init.general_call)); + assert_param(IS_I2C_NO_STRETCH(hperh->init.no_stretch)); + assert_param(IS_I2C_MODULE(hperh->init.module)); + + if (hperh->state == I2C_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = I2C_STATE_BUSY; + + I2C_DISABLE(hperh); + + i2c_speed_init(hperh, freqrange); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NOSTRETCH_MSK, (hperh->init.no_stretch) << I2C_CON1_NOSTRETCH_POS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_GCEN_MSK, (hperh->init.general_call) << I2C_CON1_GCEN_POS); + + if (hperh->init.dual_addr == I2C_DUALADDR_ENABLE) { + CLEAR_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK); + MODIFY_REG(hperh->perh->ADDR1, I2C_ADDR1_OA1_MSK, (hperh->init.own_addr1 & 0x3FF) << I2C_ADDR1_OA1_POSS); + SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK); + + CLEAR_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK); + MODIFY_REG(hperh->perh->ADDR2, I2C_ADDR2_OA2_MSK, (hperh->init.own_addr2 & 0x7F) << I2C_ADDR2_OA2_POSS); + SET_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK); + } else { + if (hperh->init.addr_mode == I2C_ADDR_10BIT) { + CLEAR_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK); + SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1MODE_MSK); + MODIFY_REG(hperh->perh->ADDR1, I2C_ADDR1_OA1_MSK, (hperh->init.own_addr1 & 0x3FF) << I2C_ADDR1_OA1_POSS); + SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK); + } + else { + CLEAR_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK); + MODIFY_REG(hperh->perh->ADDR2, I2C_ADDR2_OA2_MSK, (hperh->init.own_addr2 & 0x7F) << I2C_ADDR2_OA2_POSS); + SET_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK); + } + } + + I2C_ENABLE(hperh); + + hperh->error_code = I2C_ERROR_NONE; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + return OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_reset(i2c_handle_t *hperh) +{ + if (hperh == NULL) + return ERROR; + + I2C_DISABLE(hperh); + + hperh->error_code = I2C_ERROR_NONE; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + __UNLOCK(hperh); + + WRITE_REG(hperh->perh->CON1, 0); + WRITE_REG(hperh->perh->CON2, 0); + WRITE_REG(hperh->perh->ADDR1, 0); + WRITE_REG(hperh->perh->ADDR2, 0); + WRITE_REG(hperh->perh->TIMINGR, 0); + WRITE_REG(hperh->perh->TIMEOUTR, 0); + WRITE_REG(hperh->perh->FCON, 0); + WRITE_REG(hperh->perh->TXDATA, 0); + WRITE_REG(hperh->perh->IDR, I2C_FLAG_MASK); + WRITE_REG(hperh->perh->ICR, I2C_FLAG_MASK); + + I2C_ENABLE(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup I2C_Public_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) ald_i2c_master_send() + (++) ald_i2c_master_recv() + (++) ald_i2c_slave_send() + (++) ald_i2c_slave_recv() + (++) ald_i2c_mem_write() + (++) ald_i2c_mem_read() + + (#) No-Blocking mode functions with Interrupt are : + (++) ald_i2c_master_send_by_it() + (++) ald_i2c_master_recv_by_it() + (++) ald_i2c_slave_send_by_it() + (++) ald_i2c_slave_recv_by_it() + (++) ald_i2c_mem_write_by_it() + (++) ald_i2c_mem_read_by_it() + + (#) No-Blocking mode functions with DMA are : + (++) ald_i2c_master_send_by_dma() + (++) ald_i2c_master_recv_by_dma() + (++) ald_i2c_slave_send_by_dma() + (++) ald_i2c_slave_recv_by_dma() + (++) ald_i2c_mem_write_by_dma() + (++) ald_i2c_mem_read_by_dma() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) hperh->mem_tx_cplt_cbk() + (++) hperh->mem_rx_cplt_cbk() + (++) hperh->master_tx_cplt_cbk() + (++) hperh->master_rx_cplt_cbk() + (++) hperh->slave_tx_cplt_cbk() + (++) hperh->slave_rx_cplt_cbk() + (++) hperh->error_callback() + +@endverbatim + * @{ + */ +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint32_t size, uint32_t timeout) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_write(hperh, dev_addr, timeout); + + if (size <= 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + while (size > 0) { + hperh->perh->TXDATA = (*buf++); + size--; + hperh->xfer_count++; + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) + goto ERROR; + + if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) { + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == OK) { + if (size > 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else { + goto ERROR; + } + } + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == SET) + goto SUCCESS; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == OK) { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + } + else { + goto ERROR; + } + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + +SUCCESS: + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t + */ + ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint32_t size, uint32_t timeout) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_read(hperh, dev_addr, timeout); + + if (size <= 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + while (size > 0) { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) + goto ERROR; + + (*buf++) = hperh->perh->RXDATA; + size--; + hperh->xfer_count++; + + if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) { + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == OK) { + if (size > 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else { + goto ERROR; + } + } + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK)) + goto SUCCESS; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + +SUCCESS: + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint8_t i = 0; + + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + MODIFY_REG(hperh->perh->FCON, I2C_FCON_TXFTH_MSK, 0x03 << I2C_FCON_TXFTH_POSS); + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + + for (i = 0; i < 16; i++) { + hperh->perh->TXDATA = (*buf++); + --size; + hperh->xfer_count++; + + if (size == 0) + break; + } + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_IT_ADDR, timeout) == ERROR) + goto ERROR; + + while (size > 0) { + if (i2c_wait_txe_to_timeout(hperh, timeout) == ERROR) + goto ERROR; + + for (i = 0; i < 8; i++) { + hperh->perh->TXDATA = (*buf++); + --size; + hperh->xfer_count++; + + if (size == 0) + break; + } + } + + goto SUCCESS; + +ERROR: + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + +SUCCESS: + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_count = 0; + hperh->xfer_size = size; + + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_IT_ADDR, timeout) == ERROR) + goto ERROR; + + while (size > 0) { + if (i2c_wait_rxne_to_timeout(hperh, timeout) == ERROR) + goto ERROR; + + SET_BIT(hperh->perh->CON2, I2C_CON2_ACK_UPD_MSK); + (*buf++) = hperh->perh->RXDATA; + --size; + hperh->xfer_count++; + } + + goto SUCCESS; + +ERROR: + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + +SUCCESS: + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG); + + if (size <= 0xff) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + + I2C_CLEAR_IT(hperh , I2C_IT_TXTH); + I2C_CLEAR_IT(hperh , I2C_IT_NACK); + I2C_CLEAR_IT(hperh , I2C_IT_TC); + I2C_CLEAR_IT(hperh , I2C_IT_TCR); + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + I2C_DISABLE_IT(hperh, I2C_FLAG_MASK); + I2C_ENABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK | I2C_IT_TC | I2C_IT_TCR); + + return OK; +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) ; + + if (size <= 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + + I2C_CLEAR_IT(hperh , I2C_IT_RXTH); + I2C_CLEAR_IT(hperh , I2C_IT_TCR); + I2C_CLEAR_IT(hperh , I2C_IT_TC); + + I2C_DISABLE_IT(hperh, I2C_FLAG_MASK); + I2C_ENABLE_IT(hperh, I2C_IT_RXTH | I2C_IT_TCR | I2C_IT_TC); + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + return OK; +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + + I2C_CLEAR_IT(hperh , I2C_IT_TXTH); + I2C_CLEAR_IT(hperh , I2C_IT_ADDR); + I2C_CLEAR_IT(hperh , I2C_IT_NACK); + I2C_CLEAR_IT(hperh , I2C_IT_STOP); + + I2C_DISABLE_IT(hperh, I2C_FLAG_MASK); + I2C_ENABLE_IT(hperh, I2C_IT_ADDR | I2C_IT_NACK | I2C_IT_STOP | I2C_IT_TXTH); + + return OK; +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + + I2C_CLEAR_IT(hperh , I2C_IT_RXTH); + I2C_CLEAR_IT(hperh , I2C_IT_ADDR); + I2C_CLEAR_IT(hperh , I2C_IT_STOP); + + I2C_DISABLE_IT(hperh, I2C_FLAG_MASK); + I2C_ENABLE_IT(hperh, I2C_IT_RXTH | I2C_IT_ADDR | I2C_IT_STOP); + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @note The maximum amount of data to be sent is 0xFF. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent (maximum is 0xFF) + * @param channel: DMA channel as I2C transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint8_t size, uint8_t channel) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + if (size >= 0xFF) + size = 0xFF; + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = i2c_dma_master_send_cplt; + hperh->hdmatx.cplt_arg = hperh; + hperh->hdmatx.err_cbk = i2c_dma_error; + hperh->hdmatx.err_arg = hperh; + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + hperh->hdmatx.config.size = size; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.src = (void *)hperh->p_buff; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG); + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2C receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint8_t size, uint8_t channel) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + if (size >= 0xFF) + size = 0xFF; + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = i2c_dma_master_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2c_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + hperh->hdmarx.config.size = size; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG); + + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + return OK; +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2C Transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (size >= 0xFF) + size = 0xFF; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = i2c_dma_slave_send_cplt; + hperh->hdmatx.cplt_arg = hperh; + hperh->hdmatx.err_cbk = i2c_dma_error; + hperh->hdmatx.err_arg = hperh; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_IT_ADDR, I2C_TIMEOUT_ADDR_SLAVE) == ERROR) { + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + return OK; +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2C receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (size >= 0xFF) + size = 0xFF; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = i2c_dma_slave_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2c_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_IT_ADDR, I2C_TIMEOUT_ADDR_SLAVE) == ERROR) { + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + } + + SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + return OK; +} +#endif + +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t nbyte = 0; + + assert_param(IS_I2C_MEMADD_size(add_size)); + + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_write(hperh, dev_addr, timeout); + + if (add_size == I2C_MEMADD_SIZE_8BIT) { + nbyte = size + 1; + } + else { + nbyte = size + 2; + } + + if (nbyte <= 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) + goto ERROR; + + hperh->xfer_count += 2; + while (size > 0) { + hperh->perh->TXDATA = (*buf++); + --size; + hperh->xfer_count++; + + if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) { + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == OK) { + if (size > 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else { + goto ERROR; + } + } + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) + goto ERROR; + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK)) + goto SUCCESS; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + +SUCCESS: + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t nbyte = 0; + + assert_param(IS_I2C_MEMADD_size(add_size)); + + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->xfer_count = 0; + hperh->xfer_size = size; + + i2c_master_req_write(hperh, dev_addr, timeout); + + nbyte = (add_size == I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + } + + if (size <= 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + while (size > 0) { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) + goto ERROR; + + (*buf++) = hperh->perh->RXDATA; + size--; + hperh->xfer_count++; + + if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) { + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == OK) { + if (size > 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else { + goto ERROR; + } + } + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK)) + goto SUCCESS; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + +SUCCESS: + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint32_t size) +{ + uint32_t nbyte = 0; + + assert_param(IS_I2C_MEMADD_size(add_size)); + + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (add_size == I2C_MEMADD_SIZE_8BIT) { + nbyte = size + 1; + } + else { + nbyte = size + 2; + } + + if (nbyte <= 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + } + + I2C_CLEAR_IT(hperh , I2C_IT_TXTH); + I2C_CLEAR_IT(hperh , I2C_IT_NACK); + I2C_CLEAR_IT(hperh , I2C_IT_TC); + I2C_CLEAR_IT(hperh , I2C_IT_TCR); + + hperh->perh->TXDATA = (*hperh->p_buff++); + hperh->xfer_count++; + + I2C_DISABLE_IT(hperh, I2C_FLAG_MASK); + I2C_ENABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK | I2C_IT_TC | I2C_IT_TCR); + + return OK; +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint32_t size) +{ + uint32_t nbyte = 0; + + assert_param(IS_I2C_MEMADD_size(add_size)); + + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + nbyte = (add_size == I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + } + + if (size <= 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + I2C_CLEAR_IT(hperh , I2C_IT_RXTH); + I2C_CLEAR_IT(hperh , I2C_IT_TC); + I2C_CLEAR_IT(hperh , I2C_IT_TCR); + + I2C_ENABLE_IT(hperh, I2C_IT_RXTH | I2C_IT_TC | I2C_IT_TCR); + + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + return OK; +} + +#ifdef ALD_DMA + +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address(Maxsiz 0xFF) + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint8_t size, uint8_t channel) +{ + uint32_t nbyte = 0; + + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_MEMADD_size(add_size)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = i2c_dma_mem_send_cplt; + hperh->hdmatx.cplt_arg = hperh; + hperh->hdmatx.err_cbk = i2c_dma_error; + hperh->hdmatx.err_arg = hperh; + + nbyte = (add_size == I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.src = (void *)hperh->p_buff; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + } + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + return OK; +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be read + * @param channel: DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint8_t size, uint8_t channel) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_MEMADD_size(add_size)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = i2c_dma_mem_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2c_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + if (add_size == I2C_MEMADD_SIZE_16BIT) { + hperh->hdmatx.config.size = size + 2; + } + else { + hperh->hdmatx.config.size = size + 1; + } + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + hperh->hdmatx.config.size = size; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + if (!I2C_GET_FLAG(hperh, I2C_STAT_TXE)) { + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + } + + if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + __UNLOCK(hperh); + return ERROR; + } + else { + __UNLOCK(hperh); + return TIMEOUT; + } + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + __UNLOCK(hperh); + + return OK; +} + +#endif + +/** + * @} + */ + +/** @defgroup I2C_Public_Functions_Group3 Peripheral state and Errors functions + * @brief Peripheral state and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral state and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval ald_status_t state + */ +i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the I2C error code. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t ald_i2c_get_error(i2c_handle_t *hperh) +{ + return hperh->error_code; +} +/** + * @} + */ + +/** @defgroup I2C_Public_Functions_Group4 IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void ald_i2c_ev_irq_handler(i2c_handle_t *hperh) +{ + uint32_t size = hperh->xfer_size - hperh->xfer_count; + + /**< Transmit FIFO threshold interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TXTH) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_TXTH); + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) { + i2c_master_send_txe(hperh); + } + else if (hperh->mode == I2C_MODE_SLAVE) { + i2c_slave_send_txe(hperh); + } + } + + /**< Receive FIFO threshold interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_RXTH) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_RXTH); + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) { + i2c_master_recv_rxne(hperh); + } + else if (hperh->mode == I2C_MODE_SLAVE) { + i2c_slave_recv_rxne(hperh); + } + } + + /**< Transmit completed interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TC) == SET) { + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) { + if (I2C_MASTER_GET_DIR(hperh) == RESET) { + i2c_master_send_tc(hperh); + } + else { + i2c_master_recv_tc(hperh); + } + } + + ald_i2c_clear_flag_status(hperh, I2C_IT_TC); + } + + /**< Transmit and reload completed interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TCR) == SET) { + if (size > 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + ald_i2c_clear_flag_status(hperh, I2C_IT_TCR); + } + + /**< Transmit FIFO empty interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TXE) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_TXE); + } + + /**< Receive FIFO full interrupt*/ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_RXF) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_RXF); + } + + /**< Address matching interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_ADDR) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_ADDR); + } + + /**< Stop detection interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_STOP) == SET) { + i2c_slave_stopf(hperh); + ald_i2c_clear_flag_status(hperh, I2C_IT_STOP); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hperh: pointer to a i2c_handle_t structure that contains + * the configuration information for I2C module + * @retval NONE + */ +void ald_i2c_er_irq_handler(i2c_handle_t *hperh) +{ + /**< Transmit FIFO overrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TXOV) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_TXOV); + hperh->error_code |= I2C_ERROR_TOV; + } + /**< Transmit FIFO underrun */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TXUD) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_TXUD); + hperh->error_code |= I2C_ERROR_TUD; + } + + /**< Receive FIFO overrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_RXOV) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_RXOV); + hperh->error_code |= I2C_ERROR_ROV; + } + + /**< Receive FIFO underrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_RXUD) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_RXUD); + hperh->error_code |= I2C_ERROR_RUD; + } + + /**< NACK interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_NACK) == SET) { + if (hperh->xfer_count != hperh->xfer_size) + hperh->state |= I2C_ERROR_AF; + + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + + I2C_DISABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK); + ald_i2c_clear_flag_status(hperh, I2C_IT_NACK); + } + + /**< Bus error interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_BERR) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_BERR); + hperh->state |= I2C_ERROR_BERR; + } + + /**< Arbitration loss interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_ARLO) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_ARLO); + hperh->state |= I2C_ERROR_ARLO; + } + + /**< PEC error interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_PECE) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_PECE); + } + + /**< Timeout interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TOUT) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_TOUT); + hperh->state |= I2C_ERROR_TIMEOUT; + } + + /**< SMBus Alert interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_ALERT) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_ALERT); + } + + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); +} + +/** + * @brief Enable/disable the specified I2C interrupts. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param it: Specifies the i2c interrupt sources to be enabled or disabled. + * @param state: New state of the specified I2C interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IER = it; + else + hperh->perh->IDR = it; + + return; +} + +/** + * @brief Get the status of I2C interrupt source. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param it: Specifies the I2C interrupt source. + * This parameter can be one of the @ref i2c_interrupt_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it) +{ + it_status_t status = RESET; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(it)); + + if (hperh->perh->IVS & it) + status = SET; + + return status; +} + +/** + * @brief Get the status of I2C interrupt flag. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param flag: Specifies the I2C interrupt flag. + * This parameter can be one of the @ref i2c_interrupt_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + + +/** + * @brief Get the status of interrupt flag and interupt source. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param flag: Specifies the I2C interrupt flag. + * This parameter can be one of the @ref i2c_interrupt_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_i2c_get_mask_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(flag)); + + if (hperh->perh->IFM & flag) + return SET; + + return RESET; +} + +/** + * @brief Clear the I2C interrupt flag. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param flag: Specifies the I2C interrupt flag. + * @retval None + */ +void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(flag)); + + hperh->perh->ICR = flag; + return; +} + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Handle transmit complete flag for Master Transmit mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_send_tc(i2c_handle_t *hperh) +{ + I2C_DISABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK | I2C_IT_TC | I2C_IT_TCR); + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == RESET) + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + + __UNLOCK(hperh); + hperh->state = I2C_STATE_READY; + + if (hperh->mode == I2C_MODE_MEM) { + if (hperh->mem_tx_cplt_cbk) + hperh->mem_tx_cplt_cbk(hperh); + } + else { + if (hperh->master_tx_cplt_cbk) + hperh->master_tx_cplt_cbk(hperh); + } + + return OK; +} + + +/** + * @brief Handle transmit empty flag for Master Transmit mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh) +{ + if (hperh->xfer_count != hperh->xfer_size) { + hperh->perh->TXDATA = (*hperh->p_buff++); + hperh->xfer_count++; + } + + return OK; +} + +/** + * @brief Handle receive complete for Master Receive mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_recv_tc(i2c_handle_t *hperh) +{ + I2C_DISABLE_IT(hperh, I2C_IT_RXTH | I2C_IT_TCR | I2C_IT_TC); + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == RESET) + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + + __UNLOCK(hperh); + hperh->state = I2C_STATE_READY; + + if (hperh->mode == I2C_MODE_MEM) { + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } + else { + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } + + return OK; +} +/** + * @brief Handle receive not empty for Master Receive mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh) +{ + if (hperh->xfer_size - hperh->xfer_count > 0) { + (*hperh->p_buff++) = hperh->perh->RXDATA; + hperh->xfer_count++; + } + + return OK; +} + +/** + * @brief Handle TXE flag for Slave Transmit mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh) +{ + if (hperh->xfer_size > hperh->xfer_count) { + hperh->perh->TXDATA = (*hperh->p_buff++); + hperh->xfer_count++; + } + + return OK; +} + +/** + * @brief Handle RXNE flag for Slave Receive mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh) +{ + if (hperh->xfer_size > hperh->xfer_count) { + (*hperh->p_buff++) = hperh->perh->RXDATA; + hperh->xfer_count++; + } + + return OK; +} + +/** + * @brief Handle STOPF flag for Slave mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh) +{ + I2C_DISABLE_IT(hperh, I2C_IT_ADDR | I2C_IT_NACK | I2C_IT_RXTH | I2C_IT_TXTH | I2C_IT_STOP); + + hperh->mode = I2C_MODE_NONE; + hperh->error_code = I2C_ERROR_NONE; + __UNLOCK(hperh); + + if (hperh->state == I2C_STATE_BUSY_TX) { + hperh->state = I2C_STATE_READY; + if ((hperh->slave_tx_cplt_cbk) && (hperh->xfer_count != 0)) + hperh->slave_tx_cplt_cbk(hperh); + } + else if (hperh->state == I2C_STATE_BUSY_RX) { + hperh->state = I2C_STATE_READY; + if ((hperh->slave_rx_cplt_cbk) && (hperh->xfer_count != 0)) + hperh->slave_rx_cplt_cbk(hperh); + } + + return OK; +} + + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout) +{ + if (hperh->init.addr_mode == I2C_ADDR_7BIT) { + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + } + else { + SET_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + } + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_SADD_MSK, dev_addr << I2C_CON2_SADD_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + + return OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout) +{ + if (hperh->init.addr_mode == I2C_ADDR_7BIT) { + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + } + else { + SET_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + } + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_SADD_MSK, dev_addr << I2C_CON2_SADD_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + + return OK; +} +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ + +static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout) +{ + i2c_master_req_write(hperh, dev_addr, timeout); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + if (add_size == I2C_MEMADD_SIZE_8BIT) { + hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); + } + else { + hperh->perh->TXDATA = I2C_MEM_ADD_MSB(mem_addr); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) + return ERROR; + + hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); + } + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) + return ERROR; + + return OK; +} +#ifdef ALD_DMA +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout) +{ + uint32_t tim_count = 0; + + if (i2c_master_req_write(hperh, dev_addr, timeout) != OK) { + __UNLOCK(hperh); + return ERROR; + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + if (add_size == I2C_MEMADD_SIZE_8BIT) { + hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); + } + else { + hperh->perh->TXDATA = I2C_MEM_ADD_MSB(mem_addr); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + return ERROR; + } + else { + return TIMEOUT; + } + } + + hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); + } + + while (!I2C_GET_FLAG(hperh, I2C_STAT_TXE)) { + tim_count++; + + if (tim_count > 0xFFFF) + return TIMEOUT; + } + return OK; +} + + +/** +* @brief DMA I2C master transmit process complete callback. +* @param argv: I2C handle +* @retval None +*/ +static void i2c_dma_master_send_cplt(void *argv) +{ + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ERROR) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->master_tx_cplt_cbk) + hperh->master_tx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_slave_send_cplt(void *argv) +{ + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->slave_tx_cplt_cbk) + hperh->slave_tx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C master receive process complete callback + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_master_recv_cplt(void *argv) +{ + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ERROR) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_slave_recv_cplt(void *argv) +{ + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->slave_rx_cplt_cbk) + hperh->slave_rx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C Memory Write process complete callback + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_mem_send_cplt(void *argv) +{ + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ERROR) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->mem_tx_cplt_cbk) + hperh->mem_tx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C Memory Read process complete callback + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_mem_recv_cplt(void *argv) +{ + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == OK) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } +} + +/** +* @brief DMA I2C communication error callback. +* @param argv: I2C handle +* @retval None +*/ +static void i2c_dma_error(void *argv) +{ + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + hperh->error_code |= I2C_ERROR_DMA; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); +} +#endif + +/** + * @brief This function handles I2C Communication timeout. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param flag: specifies the I2C flag to check. + * @param status: The checked flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tickstart = 0; + + tickstart = ald_get_tick(); + if (status == RESET) { + while (I2C_GET_FLAG(hperh, flag) == RESET) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) { + hperh->error_code |= I2C_ERROR_TIMEOUT; + return TIMEOUT; + } + } + } + else { + while (I2C_GET_FLAG(hperh, flag) != RESET) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) { + hperh->error_code |= I2C_ERROR_TIMEOUT; + return TIMEOUT; + } + } + } + + return OK; +} + +/** + * @brief This function handles I2C Communication timeout for Master addressing phase. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param flag: specifies the I2C flag to check. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, uint32_t flag, uint32_t timeout) +{ + uint32_t tickstart = ald_get_tick(); + + while (I2C_GET_IT_FLAG(hperh, flag) == RESET) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) { + hperh->error_code = I2C_ERROR_TIMEOUT; + + return ERROR; + } + } + + return OK; +} + +/** + * @brief This function handles I2C Communication timeout for specific usage of TXE flag. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart = ald_get_tick(); + + while (I2C_GET_FLAG(hperh, I2C_STAT_THTH) == RESET) { + if (I2C_GET_IT_FLAG(hperh, I2C_IT_ARLO)) { + hperh->error_code |= I2C_ERROR_ARLO; + return ERROR; + } + + if (I2C_GET_IT_FLAG(hperh, I2C_IT_NACK) == SET) { + hperh->error_code |= I2C_ERROR_AF; + return ERROR; + } + + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + hperh->error_code |= I2C_ERROR_TIMEOUT; + return ERROR; + } + } + + return OK; +} + +/** + * @brief This function handles I2C Communication timeout for specific usage of RXNE flag. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart = ald_get_tick(); + + while (I2C_GET_FLAG(hperh, I2C_STAT_RXTH) == RESET) { + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + hperh->error_code |= I2C_ERROR_TIMEOUT; + return ERROR; + } + } + + return OK; +} + +/** + * @} + */ + +#endif /* ALD_I2C */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c new file mode 100644 index 0000000000000000000000000000000000000000..beb52f00de84c72f88438e3a4f0cd541ddd59dc2 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_i2s.c @@ -0,0 +1,1356 @@ +/** + ********************************************************************************* + * + * @file ald_I2S.c + * @brief I2S module driver. + * This file provides firmware functions to manage the following + * functionalities of I2S peripheral: + * + Initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + * @version V1.0 + * @date 13 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2S driver can be used as follows: + + (#) Declare a i2s_handle_t structure, for example: + i2s_handle_t hperh; + + (#) Initialize the I2S low level resources: + (##) Enable the I2Sx interface clock + (##) I2S pins configuration + (+++) Enable the clock for the I2S GPIOs + (+++) Configure these I2S pins as push-pull + (##) NVIC configuration if you need to use interrupt process + by implementing the ald_mcu_irq_config() API. + Invoked ald_i2s_irq_handler() function in I2S-IRQ function + (##) DMA Configuration if you need to use DMA process + (+++) Define ALD_DMA in ald_conf.h + (+++) Enable the DMAx clock + + (#) Program the Channel length, Data length, Polarity, Standard, Pcm frame, + external clock and Main clock output, Odd factor and Divide clock in the i2s_init_t structure. + + (#) Initialize the I2S module by invoking the ald_i2s_init() API. + + [..] + Circular mode restriction: + (#) When the I2S DMA Pause/Stop features are used, we must use the following APIs + the ald_i2s_dma_pause()/ ald_i2s_dma_stop(). + + * @endverbatim + */ + +#include "ald_i2s.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup I2S I2S + * @brief I2S module driver + * @{ + */ +#ifdef ALD_I2S + +/** @addtogroup I2S_Private_Functions I2S Private Functions + * @{ + */ + +static ald_status_t i2s_wait_status(i2s_handle_t *hperh, i2s_status_t state, flag_status_t status, uint32_t timeout); +static void __i2s_send_by_it(i2s_handle_t *hperh); +static void __i2s_recv_by_it(i2s_handle_t *hperh); +#ifdef ALD_DMA +static void i2s_dma_send_cplt(void *arg); +static void i2s_dma_recv_cplt(void *arg); +static void i2s_dma_error(void *arg); +#endif +/** + * @} + */ + +/** @defgroup I2S_Public_Functions I2S Public Functions + * @{ + */ + +/** @defgroup I2S_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + * @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + reset the I2Sx peripheral: + + (+) User must configure all related peripherals resources + (CLOCK, GPIO, DMA, NVIC). + + (+) Call the function ald_i2s_init() to configure the selected device with + the selected configuration: + (++) Channel length + (++) Data length + (++) Polarity + (++) Standard + (++) Pcm frame + (++) External clock + (++) Main clock output function + (++) Odd factor + (++) Divide clock + + (+) Call the function ald_i2s_reset() to reset the selected I2Sx periperal. + + @endverbatim + * @{ + */ + +/** + * @brief Reset the I2S peripheral. + * @param hperh: Pointer to a i2s_handle_t structure that contains + * the configuration information for the specified I2S module. + * @retval None + */ +void ald_i2s_reset(i2s_handle_t *hperh) +{ + hperh->perh->I2SCFG = 0x0; + hperh->perh->I2SPR = 0x0; + + I2S_RESET_HANDLE_STATE(hperh); + __UNLOCK(hperh); + + return; +} + +/** + * @brief Initializes the I2S mode according to the specified parameters in + * the i2s_init_t and create the associated handle. + * @param hperh: Pointer to a i2s_handle_t structure that contains + * the configuration information for the specified SPI module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_init(i2s_handle_t *hperh) +{ + uint32_t tmp = 0; + + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_CH_LEN(hperh->init.ch_len)); + assert_param(IS_I2S_DATE_LEN(hperh->init.data_len)); + assert_param(IS_I2S_CPOL(hperh->init.polarity)); + assert_param(IS_I2S_STANDARD(hperh->init.standard)); + assert_param(IS_FUNC_STATE(hperh->init.ext_ck)); + assert_param(IS_FUNC_STATE(hperh->init.mck_en)); + assert_param(IS_I2S_PCMS(hperh->init.pcm_frame)); + assert_param(IS_I2S_ODD(hperh->init.odd)); + assert_param(IS_I2S_DIV(hperh->init.div)); + + if (hperh == NULL) + return ERROR; + + ald_i2s_reset(hperh); + + tmp = hperh->perh->I2SPR; + + tmp |= ((hperh->init.ext_ck << SPI_I2SPR_EXTCKEN_POS) | (hperh->init.odd << SPI_I2SPR_ODD_POS) | + (hperh->init.div << SPI_I2SPR_I2SDIV_POSS)); + + hperh->perh->I2SPR = tmp; + + tmp = hperh->perh->I2SCFG; + + tmp |= ((hperh->init.ch_len << SPI_I2SCFG_CHLEN_POS) | (hperh->init.data_len << SPI_I2SCFG_DATLEN_POSS) | + (hperh->init.polarity << SPI_I2SCFG_CKPOL_POS) | (hperh->init.standard << SPI_I2SCFG_I2SSTD_POSS) | + (1 << SPI_I2SCFG_I2SMOD_POS)); + + hperh->perh->I2SCFG = tmp; + + if (hperh->init.standard == I2S_PCM_STANDARD) + hperh->perh->I2SCFG |= (hperh->init.pcm_frame << SPI_I2SCFG_PCMSYNC_POS); + + hperh->err_code = I2S_ERROR_NONE; + hperh->state = I2S_STATE_READY; + + return OK; +} +/** + * @} + */ + +/** @defgroup I2S_Public_Functions_Group2 IO operation functions + * @brief I2S Transmit and Receive functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the I2S + data transfers. + + [..] The I2S supports master or slave mode: + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The ALD status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the ALD status. + The end of the data processing will be indicated through the + dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The hperh->err_cbk() user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA). + + * @endverbatim + * @{ + */ + +/** + * @brief Master mode transmit an amount of data in blocking mode. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_send(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + + hperh->state = I2S_STATE_BUSY_TX; + hperh->err_code = I2S_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + while (hperh->tx_count > 0) { + if (i2s_wait_status(hperh, I2S_STATUS_TXE, SET, timeout) != OK) { + I2S_DISABLE(hperh); + + hperh->state = I2S_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + hperh->side = READ_BIT(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK); + hperh->perh->DATA = *hperh->tx_buf; + hperh->tx_buf++; + --hperh->tx_count; + } + + if ((i2s_wait_status(hperh, I2S_STATUS_TXE, SET, timeout) != OK) + || (i2s_wait_status(hperh, I2S_STATUS_BUSY, RESET, timeout) != OK)) { + I2S_DISABLE(hperh); + hperh->state = I2S_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + I2S_DISABLE(hperh); + hperh->state = I2S_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Master mode receive an amount of data in blocking mode. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_recv(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = I2S_STATE_BUSY_RX; + hperh->err_code = I2S_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + while (hperh->rx_count > 0) { + *((uint16_t *)&(hperh->perh->DATA)) = 0xffff; + if (i2s_wait_status(hperh, I2S_STATUS_RXE, RESET, timeout) != OK) { + I2S_DISABLE(hperh); + hperh->state = I2S_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + *hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf++; + --hperh->rx_count; + + } + + hperh->state = I2S_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Slave mode transmit an amount of data in blocking mode. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_slave_send(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint32_t timeout) +{ + uint8_t loop; + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + + hperh->state = I2S_STATE_BUSY_TX; + hperh->err_code = I2S_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_SLAVE_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + while (hperh->tx_count > 0) { + if (i2s_wait_status(hperh, I2S_STATUS_TXE, SET, timeout) != OK) { + I2S_DISABLE(hperh); + + hperh->state = I2S_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + hperh->side = READ_BIT(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK); + hperh->perh->DATA = *hperh->tx_buf; + hperh->tx_buf++; + --hperh->tx_count; + } + + if (i2s_wait_status(hperh, I2S_STATUS_TXE, SET, timeout) != OK) { + I2S_DISABLE(hperh); + hperh->state = I2S_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + for (loop = 0; loop < 200; loop++); + I2S_DISABLE(hperh); + hperh->state = I2S_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Slave mode receive an amount of data in blocking mode. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_slave_recv(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = I2S_STATE_BUSY_RX; + hperh->err_code = I2S_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_SLAVE_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + while (hperh->rx_count > 0) { + if (i2s_wait_status(hperh, I2S_STATUS_RXE, RESET, timeout) != OK) { + I2S_DISABLE(hperh); + hperh->state = I2S_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + *hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf++; + --hperh->rx_count; + } + + hperh->state = I2S_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Wraps up master mode transmission in non blocking mode. + * @param hperh: pointer to a i2s_handle_t structure. + * @param buf: Pointer to data transmitted buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16_t size) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = I2S_STATE_BUSY_TX; + hperh->err_code = I2S_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + ald_i2s_interrupt_config(hperh, I2S_IT_TXE, ENABLE); + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Master mode receives an amount of data in non blocking mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16_t size) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = I2S_STATE_BUSY_RX; + hperh->err_code = I2S_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + ald_i2s_interrupt_config(hperh, I2S_IT_RXF, ENABLE); + + __UNLOCK(hperh); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + return OK; +} + +/** + * @brief Wraps up slave mode transmission in non blocking mode. + * @param hperh: pointer to a i2s_handle_t structure. + * @param buf: Pointer to data transmitted buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_slave_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16_t size) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = I2S_STATE_BUSY_TX; + hperh->err_code = I2S_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size - 1; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_SLAVE_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); + + ald_i2s_interrupt_config(hperh, I2S_IT_TXE, ENABLE); + + __UNLOCK(hperh); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + return OK; +} + +/** + * @brief Slave mode receives an amount of data in non blocking mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_slave_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint16_t size) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = I2S_STATE_BUSY_RX; + hperh->err_code = I2S_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_SLAVE_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); + + + __UNLOCK(hperh); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, ENABLE); + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Master mode transmit an amount of data used dma channel + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2S transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = I2S_STATE_BUSY_TX; + hperh->err_code = I2S_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = i2s_dma_send_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = i2s_dma_error; + + /* Configure I2S DMA transmit */ + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.perh = DMA0; + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdma.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdma.config.channel = channel; + hperh->hdma.config.burst = ENABLE; + ald_dma_config_basic(&(hperh->hdma)); + + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, ENABLE); + __UNLOCK(hperh); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + return OK; +} + +/** + * @brief Master mode receive an amount of data used dma channel + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2S transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = I2S_STATE_BUSY_RX; + hperh->err_code = I2S_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = i2s_dma_recv_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = i2s_dma_error; + + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdma.config)); + + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src = (void *)&hperh->perh->DATA; + hperh->hdma.config.dst = (void *)buf; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdma.config.msigsel = DMA_MSIGSEL_SPI_RNR; + hperh->hdma.config.channel = channel; + hperh->hdma.config.burst = ENABLE; + ald_dma_config_basic(&(hperh->hdma)); + + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, ENABLE); + __UNLOCK(hperh); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + return OK; +} + +/** + * @brief Slave mode transmit an amount of data used dma channel + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2S transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_slave_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = I2S_STATE_BUSY_TX; + hperh->err_code = I2S_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_SLAVE_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); + + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = i2s_dma_send_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = i2s_dma_error; + + /* Configure I2S DMA transmit */ + ald_dma_config_struct(&(hperh->hdma.config)); + + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdma.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdma.config.channel = channel; + hperh->hdma.config.burst = ENABLE; + ald_dma_config_basic(&(hperh->hdma)); + + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, ENABLE); + __UNLOCK(hperh); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + return OK; +} + +/** + * @brief Slave mode receive an amount of data used dma channel + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2S transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_slave_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = I2S_STATE_BUSY_RX; + hperh->err_code = I2S_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_SLAVE_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); + + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = i2s_dma_recv_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = i2s_dma_error; + + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdma.config)); + + hperh->hdma.perh = DMA0; + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src = (void *)&hperh->perh->DATA; + hperh->hdma.config.dst = (void *)buf; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdma.config.msigsel = DMA_MSIGSEL_SPI_RNR; + hperh->hdma.config.channel = channel; + hperh->hdma.config.burst = ENABLE; + ald_dma_config_basic(&(hperh->hdma)); + + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, ENABLE); + __UNLOCK(hperh); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + return OK; +} + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval Status + */ +ald_status_t ald_i2s_dma_pause(i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + + __LOCK(hperh); + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE); + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval Status + */ +ald_status_t ald_i2s_dma_resume(i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + + __LOCK(hperh); + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, ENABLE); + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, ENABLE); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval Status + */ +ald_status_t ald_i2s_dma_stop(i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + + __LOCK(hperh); + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE); + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE); + __UNLOCK(hperh); + + hperh->state = I2S_STATE_READY; + return OK; +} +#endif +/** + * @} + */ + +/** @defgroup I2S_Public_Functions_Group3 Control functions + * @brief I2S Control functions + * + * @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the I2S. + (+) Handle interrupt about I2S module. The ald_i2s_irq_handler() function must + be invoked by I2S-IRQ function. + (+) Configure the interrupt DISABLE/ENABLE. + (+) Configure the DMA request. + (+) Get interrupt source status. + (+) Get interrupt flag status. + (+) Clear interrupt flag + + @endverbatim + * @{ + */ + +/** + * @brief This function handles I2S interrupt request. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval None + */ +void ald_i2s_irq_handler(i2s_handle_t *hperh) +{ + if ((ald_i2s_get_it_status(hperh, I2S_IT_RXTH) != RESET) && (ald_i2s_get_it_flag_status(hperh, I2S_IF_RXTH) != RESET)) { + ald_i2s_clear_flag_status(hperh, I2S_IF_RXTH); + if (hperh->state == I2S_STATE_BUSY_RX) + __i2s_recv_by_it(hperh); + } + if ((ald_i2s_get_it_status(hperh, I2S_IT_TXE) != RESET) && (ald_i2s_get_it_flag_status(hperh, I2S_IF_TXE) != RESET)) { + ald_i2s_clear_flag_status(hperh, I2S_IF_TXE); + if (hperh->state == I2S_STATE_BUSY_TX) + __i2s_send_by_it(hperh); + } + + + if (hperh->err_code != I2S_ERROR_NONE) { + ald_i2s_interrupt_config(hperh, I2S_IT_RXF, DISABLE); + ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE); + hperh->state = I2S_STATE_READY; + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + + return; +} + +/** + * @brief Enables or disables the specified I2S interrupts. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param it: Specifies the I2S interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref i2s_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IER |= (uint32_t)it; + else + hperh->perh->IDR |= (uint32_t)it; + + return; +} + +/** + * @brief Enables or disables the dma request. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param req: Specifies the I2S dma request sources to be enabled or disabled. + * This parameter can be one of the @ref i2s_dma_req_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) { + if (req == I2S_DMA_REQ_TX) + SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + else { + if (req == I2S_DMA_REQ_TX) + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + + return; +} + +/** @brief Check whether the specified I2S flag is set or not. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param status: specifies the flag to check. + * This parameter can be one of the @ref i2s_status_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t i2s_get_status(i2s_handle_t *hperh, i2s_status_t status) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_STATUS(status)); + + if (hperh->perh->STAT & status) + return SET; + + return RESET; +} + +/** + * @brief Checks whether the specified I2S interrupt has occurred or not. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param it: Specifies the I2S interrupt source to check. + * This parameter can be one of the @ref i2s_it_t. + * @retval Status + * - SET + * - RESET + */ +it_status_t ald_i2s_get_it_status(i2s_handle_t *hperh, i2s_it_t it) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IT(it)); + + if (hperh->perh->IVS & it) + return SET; + + return RESET; +} + + + +/** @brief Check whether the specified I2S interrupt flag is set or not. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref i2s_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_i2s_get_it_flag_status(i2s_handle_t *hperh, i2s_flag_t flag) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IF(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** @brief Clear the specified I2S interrupt flags. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref i2s_flag_t. + * @retval None + */ +void ald_i2s_clear_flag_status(i2s_handle_t *hperh, i2s_flag_t flag) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IF(flag)); + + + hperh->perh->ICR |= flag; + return; +} + +/** + * @brief This function wait I2S status until timeout. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param flag: specifies the I2S flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2s_wait_status(i2s_handle_t *hperh, i2s_status_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick = ald_get_tick(); + + assert_param(timeout > 0); + + while ((i2s_get_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) { + ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE); + ald_i2s_interrupt_config(hperh, I2S_IT_RXF, DISABLE); + return TIMEOUT; + } + } + + return OK; +} + +/** + * @brief This function wait I2S busy status until timeout. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2s_wait_bsy_flag(i2s_handle_t *hperh, flag_status_t status, uint32_t timeout) +{ + uint32_t tick = ald_get_tick(); + + assert_param(timeout > 0); + + while (READ_BIT(hperh->perh->STAT, SPI_STAT_BUSY_MSK) != status) { + if (((ald_get_tick()) - tick) > timeout) { + ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE); + ald_i2s_interrupt_config(hperh, I2S_IT_RXF, DISABLE); + return TIMEOUT; + } + } + + return OK; +} + +/** + * @} + */ + +/** @defgroup I2S_Public_Functions_Group4 Peripheral State and Errors functions + * @brief I2S State and Errors functions + * + * @verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the I2S. + (+) ald_i2s_get_state() API can check in run-time the state of the I2S peripheral + (+) ald_i2s_get_error() check in run-time Errors occurring during communication + + @endverbatim + * @{ + */ + +/** + * @brief Returns the I2S state. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval Status, see @ref i2s_state_t. + */ +i2s_state_t ald_i2s_get_state(i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + return hperh->state; +} + +/** + * @brief Return the I2S error code + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval I2S Error Code + */ +uint32_t ald_i2s_get_error(i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + return hperh->err_code; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup I2S_Private_Functions I2S Private Functions + * @brief I2S Private functions + * @{ + */ + +/** + * @brief handle program when an tx empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval None. + */ +static void __i2s_send_by_it(i2s_handle_t *hperh) +{ + if (hperh->tx_count == 0) { + ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE); + hperh->state = I2S_STATE_READY; + + if ((i2s_wait_bsy_flag(hperh, RESET, 1000)) != OK) { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return; + } + + hperh->side = READ_BIT(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK); + hperh->perh->DATA = *hperh->tx_buf; + hperh->tx_buf++; + --hperh->tx_count; + + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval None. + */ +static void __i2s_recv_by_it(i2s_handle_t *hperh) +{ + *hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf++; + --hperh->rx_count; + + if (hperh->rx_count == 0) { + ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE); + hperh->state = I2S_STATE_READY; + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return; +} + +#ifdef ALD_DMA +/** + * @brief DMA I2S transmit process complete callback. + * @param arg: Pointer to a void structure. + * @retval None + */ +static void i2s_dma_send_cplt(void *arg) +{ + i2s_handle_t *hperh = (i2s_handle_t *)arg; + + hperh->tx_count = 0; + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE); + hperh->state = I2S_STATE_READY; + + if ((i2s_wait_bsy_flag(hperh, RESET, 1000)) != OK) + hperh->err_code |= I2S_ERROR_FLAG; + + if (hperh->err_code == I2S_ERROR_NONE) { + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA I2S receive process complete callback. + * @param arg: Pointer to a void structure. + * @retval None + */ +static void i2s_dma_recv_cplt(void *arg) +{ + i2s_handle_t *hperh = (i2s_handle_t *)arg; + + hperh->rx_count = 0; + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE); + hperh->state = I2S_STATE_READY; + + if (hperh->err_code == I2S_ERROR_NONE) { + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA I2S communication error callback. + * @param arg: Pointer to a void structure. + * @retval None + */ +static void i2s_dma_error(void *arg) +{ + i2s_handle_t *hperh = (i2s_handle_t *)arg; + + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE); + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE); + SET_BIT(hperh->err_code, I2S_ERROR_DMA); + + hperh->tx_count = 0; + hperh->rx_count = 0; + hperh->state = I2S_STATE_READY; + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; +} + +#endif /* ALD_DMA */ +/** + * @} + */ +#endif /* ALD_I2S */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c new file mode 100644 index 0000000000000000000000000000000000000000..38a2aae19963f612370ff46f50e4aceefd0a54be --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_iap.c @@ -0,0 +1,149 @@ +/** + ********************************************************************************* + * + * @file ald_iap.c + * @brief IAP module driver. + * + * @version V1.0 + * @date 04 Dec 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_iap.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup IAP IAP + * @brief IAP module driver + * @{ + */ +#ifdef ALD_IAP + + +/** @defgroup IAP_Public_Functions IAP Public Functions + * + * @verbatim + ============================================================================== + ##### Erase and Program flash functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Erase flash. + (+) Program flash. + + @endverbatim + * @{ + */ + +/** + * @brief Erases a specified page. + * @param addr: The beginning address of the page to be erased. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t ald_iap_erase_page(uint32_t addr) +{ + uint32_t status; + IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR); + + __disable_irq(); + status = (*iap_pe)(addr); + __enable_irq(); + + return !status; +} + +/** + * @brief Programs a word at a specified address. + * @param addr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param data: Specifies the data to be programmed. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t ald_iap_program_word(uint32_t addr, uint32_t data) +{ + uint32_t status; + IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR); + + if (addr & 0x3) + return 1; + + __disable_irq(); + status = (*iap_wp)(addr, data); + __enable_irq(); + + return !status; +} + +/** + * @brief Programs double words at a specified address. + * @param addr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param data_l: Specifies the LSB data to be programmed. + * @param data_h: Specifies the MSB data to be programmed. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h) +{ + uint32_t status; + IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR); + + if (addr & 0x3) + return 1; + + __disable_irq(); + status = (*iap_dwp)(addr, data_l, data_h); + __enable_irq(); + + return !status; +} + +/** + * @brief Programs datas at a specified address. + * @param addr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param data: Specifies the data to be programmed. + * @param len: Specifies the data length to be programmed. + * Bit0-1 must be zero. + * @param erase: Erase page flag before programming. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase) +{ + uint32_t status; + IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR); + + if ((addr & 0x3) || (len & 0x3)) + return 1; + + __disable_irq(); + status = (*iap_wsp)(addr, data, len, erase); + __enable_irq(); + + return !status; +} +/** + * @} + */ +#endif /* ALD_IAP */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c new file mode 100644 index 0000000000000000000000000000000000000000..1595d520e6033bed22d350933c02ec5e28ec30a3 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nand.c @@ -0,0 +1,1253 @@ +/** + ********************************************************************************* + * + * @file ald_nand.c + * @brief NAND module driver. + * + * @version V1.0 + * @date 18 March 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is used as follows: + (#) NAND flash memory configuration sequence using the function ald_nand_init() + with control and timing parameters for both common and attribute spaces. + (#) Read NAND flash memory maker and device IDs using the function + ald_nand_read_id(). The read information is stored in the nand_id_typedef + structure declared by the function caller. + (#) Access NAND flash memory by read/write operations using the functions + ald_nand_read_page_8b()/nand_read_SpareArea_8b(), + ald_nand_write_page_8b()/ald_nand_write_sparearea_8b(), + ald_nand_read_page_16b()/ald_nand_read_sparearea_16b(), + ald_nand_write_page_16b()/ald_nand_write_sparearea_16b() + to read/write page(s)/spare area(s). + (#) Perform NAND flash Reset chip operation using the function ald_nand_reset(). + (#) Perform NAND flash erase block operation using the function ald_nand_erase_block(). + (#) Read the NAND flash status operation using the function ald_nand_read_status(). + (#) You can also control the NAND device by calling the control APIs ald_nand_ecc_enable()/ + ald_nand_ecc_disable() to respectively enable/disable the ECC code correction + feature or the function ald_nand_get_ecc() to get the ECC correction code. + + @endverbatim + ****************************************************************************** + */ + +#include "ald_nand.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup NAND NAND + * @brief NAND driver modules + * @{ + */ +#ifdef ALD_NAND + +/** @defgroup Nand_Public_Functions NAND Public Functions + * @brief NAND Public functions + * @{ + */ +/** @defgroup Nand_Public_Functions_Group1 Initialization functions + * @brief NAND Initialization functions + * @{ + */ +/** + * @brief Perform NAND memory initialization sequence + * @param hperh: pointer to a nand_handle_t structure + * @param ctiming: pointer to common space timing structure + * @param atiming: pointer to attribute space timing structure + * @retval ald status + */ +ald_status_t ald_nand_init(nand_handle_t *hperh, ald_ebi_nand_timing_t *ctiming, ald_ebi_nand_timing_t *atiming) +{ + if (hperh == NULL) + return ERROR; + if (hperh->state == ALD_NAND_STATE_RESET) + hperh->lock = UNLOCK; + + ald_ebi_nand_init(hperh->instance, &(hperh->init)); + ald_ebi_nand_comm_timing_init(hperh->instance, ctiming, hperh->init.bank); + ald_ebi_nand_attr_timing_init(hperh->instance, atiming, hperh->init.bank); + ald_ebi_nand_enable(hperh->instance, hperh->init.bank); + hperh->state = ALD_NAND_STATE_READY; + + return OK; +} + +/** + * @brief Perform NAND memory De-Initialization sequence + * @param hperh: pointer to a nand_handle_t structure + * @retval ald status + */ +ald_status_t ald_nand_deinit(nand_handle_t *hperh) +{ + ald_ebi_nand_deinit(hperh->instance, hperh->init.bank); + hperh->state = ALD_NAND_STATE_RESET; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief NAND memory reset + * @param hperh: pointer to a nand_handle_t structure + * @retval ald status + */ +ald_status_t ald_nand_reset(nand_handle_t *hperh) +{ + uint32_t deviceaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + hperh->state = ALD_NAND_STATE_BUSY; + + /* Send NAND reset command */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = 0xFF; + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief configure the device: Enter the physical parameters of the device + * @param hperh: pointer to a nand_handle_t structure + * @param pdcfg : pointer to nand_device_cfg_t structure + * @retval ald status + */ +void nand_config_device(nand_handle_t *hperh, nand_device_cfg_t *pdcfg) +{ + hperh->config.page_size = pdcfg->page_size; + hperh->config.spare_size = pdcfg->spare_size; + hperh->config.block_size = pdcfg->block_size; + hperh->config.block_nbr = pdcfg->block_nbr; + hperh->config.plane_size = pdcfg->plane_size; + hperh->config.plane_nbr = pdcfg->plane_nbr; + hperh->config.extra_cmd = pdcfg->extra_cmd; +} +/** + * @} + */ +/** @defgroup Nand_Public_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/** + * @brief Read the NAND memory electronic signature + * @param hperh: pointer to a nand_handle_t structure + * @param id: NAND ID structure + * @retval ald status + */ +ald_status_t ald_nand_read_id(nand_handle_t *hperh, nand_id_t *id) +{ + __IO uint32_t data = 0; + __IO uint32_t data1 = 0; + uint32_t deviceaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + hperh->state = ALD_NAND_STATE_BUSY; + + /* Send Read ID command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_READID; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + + if (hperh->init.width == EBI_NAND_MEM_BUS_WIDTH_8) { + data = *(__IO uint32_t *)deviceaddr; + + id->maker_id = ADDR_1ST_CYCLE(data); + id->device_id = ADDR_2ND_CYCLE(data); + id->third_id = ADDR_3RD_CYCLE(data); + id->fourth_id = ADDR_4TH_CYCLE(data); + } + else { + data = *(__IO uint32_t *)deviceaddr; + data1 = *((__IO uint32_t *)deviceaddr + 4); + + /* Return the data read */ + id->maker_id = ADDR_1ST_CYCLE(data); + id->device_id = ADDR_3RD_CYCLE(data); + id->third_id = ADDR_1ST_CYCLE(data1); + id->fourth_id = ADDR_3RD_CYCLE(data1); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Read page(s) from NAND memory block (8-bits addressing) + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @param buf: pointer to destination read buffer + * @param nr: number of pages to read from block + * @retval ald status + */ +ald_status_t ald_nand_read_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + hperh->state = ALD_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandaddr = ARRAY_ADDRESS(addr, hperh); + + /* Page(s) read loop */ + while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) { + /* update the buffer size */ + size = (hperh->config.page_size) + ((hperh->config.page_size) * num); + + /* Send read page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A; + + /* Cards with page size <= 512 bytes */ + if ((hperh->config.page_size) <= 512U) { + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else { /* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + else { /* (hperh->config.page_size) > 512 */ + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + + /* Check if an extra command is needed for reading pages */ + if (hperh->config.extra_cmd == ENABLE) { + /* Get tick */ + tickstart = ald_get_tick(); + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) + return TIMEOUT; + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00); + } + + /* Get Data into Buffer */ + for (; index < size; index++) { + *(uint8_t *)buf++ = *(uint8_t *)deviceaddr; + } + + num++; + nr--; + nandaddr = (uint32_t)(nandaddr + 1U); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Write page(s) to NAND memory block (8-bits addressing) + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @param buf: pointer to source buffer to write + * @param nr: number of pages to write to block + * @retval ald status + */ +ald_status_t ald_nand_write_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + /* Update the NAND controller state */ + hperh->state = ALD_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandaddr = ARRAY_ADDRESS(addr, hperh); + + /* Page(s) write loop */ + while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) { + /* update the buffer size */ + size = hperh->config.page_size + ((hperh->config.page_size) * num); + + /* Send write page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0; + + /* Cards with page size <= 512 bytes */ + if ((hperh->config.page_size) <= 512U) { + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + else {/* (hperh->config.page_size) > 512 */ + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + + /* Write data to memory */ + for (; index < size; index++) + *(__IO uint8_t *)deviceaddr = *(uint8_t *)buf++; + + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + /* Get tick */ + tickstart = ald_get_tick(); + + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) + return TIMEOUT; + } + + num++; + nr--; + nandaddr = (uint32_t)(nandaddr + 1U); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Read spare area(s) from NAND memory (8-bits addressing) + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @param buf: pointer to source buffer to write + * @param nr: Number of spare area to read + * @retval ald status +*/ +ald_status_t ald_nand_read_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0, columnaddr = 0; + + /* Process Locked */ + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + /* Update the NAND controller state */ + hperh->state = ALD_NAND_STATE_BUSY; + /* NAND raw address calculation */ + nandaddr = ARRAY_ADDRESS(addr, hperh); + /* Column in page address */ + columnaddr = COLUMN_ADDRESS(hperh); + + /* Spare area(s) read loop */ + while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) { + /* update the buffer size */ + size = (hperh->config.spare_size) + ((hperh->config.spare_size) * num); + + /* Cards with page size <= 512 bytes */ + if ((hperh->config.page_size) <= 512U) { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_C; + + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + else {/* (hperh->config.page_size) > 512 */ + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A; + + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + + if (hperh->config.extra_cmd == ENABLE) { + /* Get tick */ + tickstart = ald_get_tick(); + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) + return TIMEOUT; + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00); + } + + /* Get Data into Buffer */ + for (; index < size; index++) + *(uint8_t *)buf++ = *(uint8_t *)deviceaddr; + + num++; + nr--; + nandaddr = (uint32_t)(nandaddr + 1U); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Write spare area(s) to NAND memory (8-bits addressing) + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @param buf: pointer to source buffer to write + * @param nr: number of spare areas to write to block + * @retval ald status + */ +ald_status_t ald_nand_write_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0, columnaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + /* Update the FSMC_NAND controller state */ + hperh->state = ALD_NAND_STATE_BUSY; + /* Page address calculation */ + nandaddr = ARRAY_ADDRESS(addr, hperh); + /* Column in page address */ + columnaddr = COLUMN_ADDRESS(hperh); + + /* Spare area(s) write loop */ + while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) { + /* update the buffer size */ + size = (hperh->config.spare_size) + ((hperh->config.spare_size) * num); + + /* Cards with page size <= 512 bytes */ + if ((hperh->config.page_size) <= 512U) { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0; + + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + else {/* (hperh->config.page_size) > 512 */ + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0; + + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + + /* Write data to memory */ + for (; index < size; index++) + *(__IO uint8_t *)deviceaddr = *(uint8_t *)buf++; + + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + tickstart = ald_get_tick(); + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) + return TIMEOUT; + } + + num++; + nr--; + nandaddr = (uint32_t)(nandaddr + 1U); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Read page(s) from NAND memory block (16-bits addressing) + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @param buf: pointer to destination read buffer + * @param nr: number of pages to read from block + * @retval ald status + */ +ald_status_t ald_nand_read_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + hperh->state = ALD_NAND_STATE_BUSY; + nandaddr = ARRAY_ADDRESS(addr, hperh); + + /* Page(s) read loop */ + while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) { + /* update the buffer size */ + size = (hperh->config.page_size) + ((hperh->config.page_size) * num); + + /* Send read page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A; + + /* Cards with page size <= 512 bytes */ + if ((hperh->config.page_size) <= 512U) { + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + else {/* (hperh->config.page_size) > 512 */ + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + + if (hperh->config.extra_cmd == ENABLE) { + /* Get tick */ + tickstart = ald_get_tick(); + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) + return TIMEOUT; + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00); + } + + /* Get Data into Buffer */ + for (; index < size; index++) + *(uint16_t *)buf++ = *(uint16_t *)deviceaddr; + + num++; + nr--; + nandaddr = (uint32_t)(nandaddr + 1U); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Write page(s) to NAND memory block (16-bits addressing) + * @param hperh: pointer to a nand_handle_t structure + * @param addr : pointer to NAND address structure + * @param buf : pointer to source buffer to write. pbuffer should be 16bits aligned + * @param nr : number of pages to write to block + * @retval ald status + */ +ald_status_t ald_nand_write_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + hperh->state = ALD_NAND_STATE_BUSY; + /* NAND raw address calculation */ + nandaddr = ARRAY_ADDRESS(addr, hperh); + + /* Page(s) write loop */ + while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) { + /* update the buffer size */ + size = (hperh->config.page_size) + ((hperh->config.page_size) * num); + + /* Send write page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0; + + /* Cards with page size <= 512 bytes */ + if ((hperh->config.page_size) <= 512U) { + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else { /* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + else { /* (hperh->config.page_size) > 512 */ + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else { /* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + + /* Write data to memory */ + for (; index < size; index++) + *(__IO uint16_t *)deviceaddr = *(uint16_t *)buf++; + + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + /* Get tick */ + tickstart = ald_get_tick(); + + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) + return TIMEOUT; + } + + num++; + nr--; + nandaddr = (uint32_t)(nandaddr + 1U); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + + + +/** + * @brief Read spare area(s) from NAND memory (16-bits addressing) + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @param buf: pointer to source buffer to write. pbuffer should be 16bits aligned. + * @param nr: Number of spare area to read + * @retval ald status +*/ +ald_status_t ald_nand_read_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0, columnaddr = 0; + + __LOCK(hperh); + + /* Check the NAND controller state */ + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + /* Update the NAND controller state */ + hperh->state = ALD_NAND_STATE_BUSY; + /* NAND raw address calculation */ + nandaddr = ARRAY_ADDRESS(addr, hperh); + /* Column in page address */ + columnaddr = (uint32_t)(COLUMN_ADDRESS(hperh) * 2U); + + /* Spare area(s) read loop */ + while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) { + /* update the buffer size */ + size = (hperh->config.spare_size) + ((hperh->config.spare_size) * num); + + /* Cards with page size <= 512 bytes */ + if ((hperh->config.page_size) <= 512U) { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_C; + + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + else {/* (hperh->config.page_size) > 512 */ + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A; + + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + + if (hperh->config.extra_cmd == ENABLE) { + /* Get tick */ + tickstart = ald_get_tick(); + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) + return TIMEOUT; + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00); + } + + /* Get Data into Buffer */ + for (; index < size; index++) + *(uint16_t *)buf++ = *(uint16_t *)deviceaddr; + + num++; + nr--; + nandaddr = (uint32_t)(nandaddr + 1U); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + + +/** + * @brief Write spare area(s) to NAND memory (16-bits addressing) + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @param buf: pointer to source buffer to write. pbuffer should be 16bits aligned. + * @param nr: number of spare areas to write to block + * @retval ald status + */ +ald_status_t ald_nand_write_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0, columnaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + /* Update the FSMC_NAND controller state */ + hperh->state = ALD_NAND_STATE_BUSY; + /* NAND raw address calculation */ + nandaddr = ARRAY_ADDRESS(addr, hperh); + /* Column in page address */ + columnaddr = (uint32_t)(COLUMN_ADDRESS(hperh) * 2); + + /* Spare area(s) write loop */ + while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) { + /* update the buffer size */ + size = (hperh->config.spare_size) + ((hperh->config.spare_size) * num); + + /* Cards with page size <= 512 bytes */ + if ((hperh->config.page_size) <= 512U) { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0; + + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + else {/* (hperh->config.page_size) > 512 */ + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0; + + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + + /* Write data to memory */ + for (; index < size; index++) + *(__IO uint16_t *)deviceaddr = *(uint16_t *)buf++; + + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + /* Get tick */ + tickstart = ald_get_tick(); + + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) + return TIMEOUT; + } + + num++; + nr--; + nandaddr = (uint32_t)(nandaddr + 1U); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief NAND memory Block erase + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @retval ald status + */ +ald_status_t ald_nand_erase_block(nand_handle_t *hperh, nand_address_t *addr) +{ + uint32_t deviceaddr = 0; + uint32_t tickstart = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + /* Update the NAND controller state */ + hperh->state = ALD_NAND_STATE_BUSY; + + /* Send Erase block command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_ERASE0; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(addr, hperh)); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(addr, hperh)); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(addr, hperh)); + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_ERASE1; + + /* Update the NAND controller state */ + hperh->state = ALD_NAND_STATE_READY; + /* Get tick */ + tickstart = ald_get_tick(); + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) { + __UNLOCK(hperh); + + return TIMEOUT; + } + } + + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup Nand_Public_Functions_Group3 NAND Control functions + * @brief NAND Control functions + * @{ + */ +/** + * @brief This function handles NAND device interrupt request. + * @param hperh: pointer to a nand_handle_t structure + * @retval ald status +*/ +void ald_nand_irq_handler(nand_handle_t *hperh) +{ + /* Check NAND interrupt Rising edge flag */ + if (ald_ebi_nand_get_flag(hperh->instance, hperh->init.bank, EBI_FLAG_RISING_EDGE)) { + ald_nand_irq_cbk(hperh); + ald_ebi_nand_clear_flag(hperh->instance, hperh->init.bank, EBI_FLAG_RISING_EDGE); + } + + /* Check NAND interrupt Level flag */ + if (ald_ebi_nand_get_flag(hperh->instance, hperh->init.bank, EBI_FLAG_LEVEL)) { + ald_nand_irq_cbk(hperh); + ald_ebi_nand_clear_flag(hperh->instance, hperh->init.bank, EBI_FLAG_LEVEL); + } + + if (ald_ebi_nand_get_flag(hperh->instance, hperh->init.bank, EBI_FLAG_FALLING_EDGE)) { + /* NAND interrupt callback*/ + ald_nand_irq_cbk(hperh); + ald_ebi_nand_clear_flag(hperh->instance, hperh->init.bank, EBI_FLAG_FALLING_EDGE); + } + + /* Check NAND interrupt FIFO empty flag */ + if (ald_ebi_nand_get_flag(hperh->instance, hperh->init.bank, EBI_FLAG_FEMPT)) { + ald_nand_irq_cbk(hperh); + ald_ebi_nand_clear_flag(hperh->instance, hperh->init.bank, EBI_FLAG_FEMPT); + } +} + +/** + * @brief NAND interrupt feature callback + * @param hperh: pointer to a nand_handle_t structure + * @retval None + */ +__weak void ald_nand_irq_cbk(nand_handle_t *hperh) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hperh); +} + +/** + * @brief Increment the NAND memory address + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @retval The new status of the increment address operation. It can be: + * - NAND_VALID_ADDRESS: When the new address is valid address + * - NAND_INVALID_ADDRESS: When the new address is invalid address + */ +uint32_t ald_nand_address_inc(nand_handle_t *hperh, nand_address_t *addr) +{ + uint32_t status = NAND_VALID_ADDRESS; + + addr->page++; + + /* Check NAND address is valid */ + if (addr->page == hperh->config.block_size) { + addr->page = 0; + addr->block++; + + if (addr->block == hperh->config.plane_size) { + addr->block = 0; + addr->plane++; + + if (addr->plane == (hperh->config.plane_nbr)) + status = NAND_INVALID_ADDRESS; + } + } + + return status; +} + +/** + * @brief NAND memory read status + * @param hperh: pointer to a nand_handle_t structure + * @retval NAND status + */ +uint32_t ald_nand_read_status(nand_handle_t *hperh) +{ + uint32_t data = 0; + uint32_t addr = 0; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + addr = NAND_DEVICE1; + else + addr = NAND_DEVICE2; + + /* Send Read status operation command */ + *(__IO uint8_t *)((uint32_t)(addr | CMD_AREA)) = NAND_CMD_STATUS; + /* Read status register data */ + data = *(__IO uint8_t *)addr; + + /* Return the status */ + if ((data & NAND_ERROR) == NAND_ERROR) + return NAND_ERROR; + else if ((data & NAND_READY) == NAND_READY) + return NAND_READY; + + return NAND_BUSY; +} + +/** + * @brief return the NAND state + * @param hperh: pointer to a nand_handle_t structure + * @retval ald state + */ +ald_nand_state_t ald_nand_get_state(nand_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Enables dynamically NAND ECC feature. + * @param hperh: pointer to a nand_handle_t structure + * @retval ald status + */ +ald_status_t ald_nand_ecc_enable(nand_handle_t *hperh) +{ + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Update the NAND state */ + hperh->state = ALD_NAND_STATE_BUSY; + /* Enable ECC feature */ + ald_ebi_nand_ecc_enable(hperh->instance, hperh->init.bank); + /* Update the NAND state */ + hperh->state = ALD_NAND_STATE_READY; + + return OK; +} + +/** + * @brief Disables dynamically FSMC_NAND ECC feature. + * @param hperh: pointer to a nand_handle_t structure + * @retval ald status + */ +ald_status_t ald_nand_ecc_disable(nand_handle_t *hperh) +{ + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Update the NAND state */ + hperh->state = ALD_NAND_STATE_BUSY; + /* Disable ECC feature */ + ald_ebi_nand_ecc_disable(hperh->instance, hperh->init.bank); + hperh->state = ALD_NAND_STATE_READY; + + return OK; +} + +/** + * @brief Disables dynamically NAND ECC feature. + * @param hperh: pointer to a nand_handle_t structure + * @param val: pointer to ECC value + * @param timeout: maximum timeout to wait + * @retval ald status + */ +ald_status_t ald_nand_get_ecc(nand_handle_t *hperh, uint32_t *val, uint32_t timeout) +{ + ald_status_t status = OK; + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + hperh->state = ALD_NAND_STATE_BUSY; + status = ald_ebi_nand_get_ecc(hperh->instance, val, hperh->init.bank, timeout); + hperh->state = ALD_NAND_STATE_READY; + + return status; +} +/** + * @} + */ +/** + * @} + */ +#endif +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nor_lcd.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nor_lcd.c new file mode 100644 index 0000000000000000000000000000000000000000..4d52faee86cb735807776ad8b556a352934dc92b --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_nor_lcd.c @@ -0,0 +1,594 @@ +/** + ********************************************************************************* + * + * @file ald_nor_lcd.c + * @brief EBI_NOR_LCD module driver. + * + * @version V1.0 + * @date 25 Dec 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_nor_lcd.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup NOR_LCD NOR_LCD + * @brief NOR_LCD driver modules + * @{ + */ +#ifdef ALD_NOR + +/** @defgroup NOR_LCD_Private_Variables NOR_LCD Private Variables + * @{ + */ +static uint32_t NORMEMDATWIDTH = NOR_MEMORY_8B; +/** + * @} + */ + +/** @defgroup NOR_LCD_Public_Functions NOR_LCD Public Functions + * @brief NOR_LCD public functions + * @{ + */ +/** @defgroup NOR_LCD_Public_Functions_Group1 Initialization functions + * @brief NOR_LCD Initialization functions + * @{ + */ +/** + * @brief Perform the NOR memory Initialization sequence + * @param hperh: pointer to a nor_handle_t structure + * @param timing: pointer to NOR control timing structure + * @param ext_timing: pointer to NOR extended mode timing structure + * @retval ald status + */ +ald_status_t ald_nor_init(nor_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing) +{ + if (hperh == NULL) + return ERROR; + if (hperh->state == ALD_NOR_STATE_RESET) + hperh->lock = UNLOCK; + + /* Initialize NOR control Interface */ + ald_ebi_nor_sram_init(hperh->instance, &(hperh->init)); + /* Initialize NOR timing Interface */ + ald_ebi_nor_sram_timing_init(hperh->instance, timing, hperh->init.bank); + /* Initialize NOR extended mode timing Interface */ + ald_ebi_nor_sram_ext_timing_init(hperh->ext, ext_timing, hperh->init.bank, hperh->init.ext_mode); + /* Enable the NORSRAM device */ + ald_ebi_nor_sram_enable(hperh->instance, hperh->init.bank); + + /* Initialize NOR Memory Data Width*/ + if (hperh->init.width == EBI_NORSRAM_MEM_BUS_WIDTH_8) + NORMEMDATWIDTH = NOR_MEMORY_8B; + else + NORMEMDATWIDTH = NOR_MEMORY_16B; + + hperh->state = ALD_NOR_STATE_READY; + return OK; +} + +/** + * @brief Perform NOR memory De-Initialization sequence + * @param hperh: pointer to a nor_handle_t structure + * @retval ald status + */ +ald_status_t ald_nor_deinit(nor_handle_t *hperh) +{ + ald_ebi_nor_sram_deinit(hperh->instance, hperh->ext, hperh->init.bank); + hperh->state = ALD_NOR_STATE_RESET; + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup NOR_LCD_Public_Functions_Group2 I/O operation functions + * @brief NOR_LCD I/O operation functions + * @{ + */ +/** + * @brief Read NOR flash IDs + * @param hperh: pointer to a nor_handle_t structure + * @param id : pointer to NOR ID structure + * @retval ald status + */ +ald_status_t ald_nor_read_id(nor_handle_t *hperh, nor_id_t *id) +{ + uint32_t devaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + /* Select the NOR device address */ + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else + devaddr = NOR_MEMORY_ADRESS4; + + hperh->state = ALD_NOR_STATE_BUSY; + + /* Send read ID command */ + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); + + /* Read the NOR IDs */ + id->m_code = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, MC_ADDRESS); + id->device_code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE1_ADDR); + id->device_code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE2_ADDR); + id->device_code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE3_ADDR); + + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Returns the NOR memory to Read mode. + * @param hperh: pointer to a nor_handle_t structure + * @retval ald status + */ +ald_status_t ald_nor_return_readmode(nor_handle_t *hperh) +{ + uint32_t devaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + /* Select the NOR device address */ + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else + devaddr = NOR_MEMORY_ADRESS4; + + NOR_WRITE(devaddr, NOR_CMD_DATA_READ_RESET); + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Read data from NOR memory + * @param hperh: pointer to a nor_handle_t structure + * @param addr: pointer to Device address + * @param data: pointer to read data + * @retval ald status + */ +ald_status_t ald_nor_read(nor_handle_t *hperh, uint32_t *addr, uint16_t *data) +{ + uint32_t devaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else + devaddr = NOR_MEMORY_ADRESS4; + + hperh->state = ALD_NOR_STATE_BUSY; + + /* Send read data command */ + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE((uint32_t)addr, NOR_CMD_DATA_READ_RESET); + + *data = *(__IO uint32_t *)(uint32_t)addr; + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Program data to NOR memory + * @param hperh: pointer to a nor_handle_t structure + * @param addr: device address + * @param data: pointer to the data to write + * @retval ald status + */ +ald_status_t ald_nor_program(nor_handle_t *hperh, uint32_t *addr, uint16_t *data) +{ + uint32_t devaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + /* Select the NOR device address */ + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else /* EBI_NORSRAM_BANK4 */ + devaddr = NOR_MEMORY_ADRESS4; + + hperh->state = ALD_NOR_STATE_BUSY; + + /* Send program data command */ + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + + /* Write the data */ + NOR_WRITE(addr, *data); + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Reads a block of data from the EBI NOR memory + * @param hperh: pointer to a nor_handle_t structure + * @param addr: nor memory internal address to read from + * @param data: pointer to the buffer that receives the data read from the + * NOR memory + * @param size : number of Half word to read + * @retval ald status + */ +ald_status_t ald_nor_read_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size) +{ + uint32_t devaddr = 0; + + /* Process Locked */ + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else + devaddr = NOR_MEMORY_ADRESS4; + + hperh->state = ALD_NOR_STATE_BUSY; + + /* Send read data command */ + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(addr, NOR_CMD_DATA_READ_RESET); + + /* Read buffer */ + while (size > 0) { + *data++ = *(__IO uint16_t *)addr; + addr += 2U; + size--; + } + + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Writes a half-word buffer to the EBI NOR memory + * @param hperh: pointer to a nor_handle_t structure + * @param addr: nor memory internal address from which the data + * @param data: pointer to source data buffer + * @param size: number of Half words to write + * @retval ald status + */ +ald_status_t ald_nor_program_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size) +{ + uint16_t * p_currentaddr = (uint16_t *)NULL; + uint16_t * p_endaddr = (uint16_t *)NULL; + uint32_t lastloadedaddr = 0, devaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else + devaddr = NOR_MEMORY_ADRESS4; + + hperh->state = ALD_NOR_STATE_BUSY; + + /* Initialize variables */ + p_currentaddr = (uint16_t*)((uint32_t)(addr)); + p_endaddr = p_currentaddr + (size - 1U); + lastloadedaddr = (uint32_t)(addr); + + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + /* Write Buffer Load Command */ + NOR_WRITE((uint32_t)(p_currentaddr), NOR_CMD_DATA_BUFFER_AND_PROG); + NOR_WRITE((uint32_t)(p_currentaddr), (size - 1U)); + + /* Load Data into NOR Buffer */ + while (p_currentaddr <= p_endaddr) { + lastloadedaddr = (uint32_t)p_currentaddr; + NOR_WRITE(p_currentaddr, *data++); + p_currentaddr++; + } + + NOR_WRITE((uint32_t)(lastloadedaddr), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Erase the specified block of the NOR memory + * @param hperh: pointer to a nor_handle_t structure + * @param blkaddr : block to erase address + * @param addr: device address + * @retval ald status + */ +ald_status_t ald_nor_erase_block(nor_handle_t *hperh, uint32_t blkaddr, uint32_t addr) +{ + uint32_t devaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else + devaddr = NOR_MEMORY_ADRESS4; + + hperh->state = ALD_NOR_STATE_BUSY; + + /* Send block erase command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE((uint32_t)(blkaddr + addr), NOR_CMD_DATA_BLOCK_ERASE); + + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; + +} + +/** + * @brief Erase the entire NOR chip. + * @param hperh: pointer to a nor_handle_t structure + * @retval ald status + */ +ald_status_t ald_nor_erase_chip(nor_handle_t *hperh) +{ + uint32_t devaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + /* Select the NOR device address */ + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else + devaddr = NOR_MEMORY_ADRESS4; + + hperh->state = ALD_NOR_STATE_BUSY; + + /* Send NOR chip erase command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); + + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Read NOR flash CFI IDs + * @param hperh: pointer to a nor_handle_t structure + * @param cfi: pointer to NOR CFI IDs structure + * @retval ald status + */ +ald_status_t ald_nor_read_cfi(nor_handle_t *hperh, nor_cfi_t *cfi) +{ + uint32_t devaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + /* Select the NOR device address */ + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else + devaddr = NOR_MEMORY_ADRESS4; + + hperh->state = ALD_NOR_STATE_BUSY; + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + + cfi->cfi_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI1_ADDRESS); + cfi->cfi_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI2_ADDRESS); + cfi->cfi_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI3_ADDRESS); + cfi->cfi_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI4_ADDRESS); + + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup NOR_LCD_Public_Functions_Group3 Control functions + * @brief NOR_LCD Control functions + * @{ + */ +/** + * @brief Enables dynamically NOR write operation. + * @param hperh: pointer to a nor_handle_t structure + * @retval ald status + */ +ald_status_t ald_nor_write_enable(nor_handle_t *hperh) +{ + __LOCK(hperh); + /* Enable write operation */ + ald_ebi_nor_sram_write_enable(hperh->instance, hperh->init.bank); + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Disables dynamically NOR write operation. + * @param hperh: pointer to a nor_handle_t structure + * @retval ald status + */ +ald_status_t ald_nor_write_disable(nor_handle_t *hperh) +{ + __LOCK(hperh); + hperh->state = ALD_NOR_STATE_BUSY; + /* Disable write operation */ + ald_ebi_nor_sram_write_disable(hperh->instance, hperh->init.bank); + hperh->state = ALD_NOR_STATE_PROTECTED; + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup NOR_LCD_Public_Functions_Group4 State functions + * @brief NOR_LCD State functions + * @{ + */ +/** + * @brief return the NOR controller state + * @param hperh: pointer to a nor_handle_t structure + * @retval nor controller state + */ +ald_nor_state_t ald_nor_get_state(nor_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Returns the NOR operation status. + * @param hperh: pointer to a nor_handle_t structure + * @param addr: device address + * @param timeout: nor progamming timeout + * @retval nor status + */ +nor_status_t ald_nor_get_status(nor_handle_t *hperh, uint32_t addr, uint32_t timeout) +{ + nor_status_t status = ALD_NOR_STATUS_ONGOING; + uint16_t tmp_sr1 = 0, tmp_sr2 = 0; + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = ald_get_tick(); + while ((status != ALD_NOR_STATUS_SUCCESS) && (status != ALD_NOR_STATUS_TIMEOUT)) { + /* Check for the Timeout */ + if (timeout != ALD_MAX_DELAY) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) + status = ALD_NOR_STATUS_TIMEOUT; + } + + /* Read NOR status register (DQ6 and DQ5) */ + tmp_sr1 = *(__IO uint16_t *)addr; + tmp_sr2 = *(__IO uint16_t *)addr; + + /* If DQ6 did not toggle between the two reads then return NOR_Success */ + if ((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6)) + return ALD_NOR_STATUS_SUCCESS; + + if ((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5) + status = ALD_NOR_STATUS_ONGOING; + + tmp_sr1 = *(__IO uint16_t *)addr; + tmp_sr2 = *(__IO uint16_t *)addr; + + /* If DQ6 did not toggle between the two reads then return NOR_Success */ + if ((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6)) + return ALD_NOR_STATUS_SUCCESS; + else if ((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + return ALD_NOR_STATUS_ERROR; + } + + return status; +} +/** + * @} + */ +/** + * @} + */ +#endif +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c new file mode 100644 index 0000000000000000000000000000000000000000..5ffac6ae2bdf6d61039411b4766993995bbb093c --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pis.c @@ -0,0 +1,310 @@ +/** + ********************************************************************************* + * + * @file ald_pis.c + * @brief PIS module driver. + * + * @version V1.0 + * @date 27 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_pis.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup PIS PIS + * @brief PIS module driver + * @{ + */ +#ifdef ALD_PIS + +/** @defgroup PIS_Public_Functions PIS Public Functions + * @{ + */ + +/** @defgroup PIS_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Create the PIS mode according to the specified parameters in + * the pis_handle_t and create the associated handle. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_create(pis_handle_t *hperh) +{ + pis_divide_t temp; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_PIS_SRC(hperh->init.producer_src)); + assert_param(IS_PIS_TRIG(hperh->init.consumer_trig)); + assert_param(IS_PIS_CLOCK(hperh->init.producer_clk)); + assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk)); + assert_param(IS_PIS_EDGE(hperh->init.producer_edge)); + assert_param(IS_PIS_SIGNAL_MODE(hperh->init.producer_signal)); + + __LOCK(hperh); + hperh->perh = PIS; + + /* get location of consumer in channel and position of con0/con1 + * accord to comsumer_trig information */ + temp.HalfWord = (hperh->init.consumer_trig); + hperh->consumer_ch = (pis_ch_t)(temp.ch); + hperh->consumer_con = (pis_con_t)(temp.con); + hperh->consumer_pos = (1 << temp.shift); + + if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) { + __UNLOCK(hperh); + return BUSY; + } + + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS); + + if (hperh->init.producer_clk == hperh->init.consumer_clk) { + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_DIRECT << PIS_CH0_CON_SYNCSEL_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, (hperh->init.consumer_clk) << PIS_CH0_CON_PULCK_POSS); + } + else { + if (hperh->init.producer_signal == PIS_OUT_LEVEL) { + if (hperh->init.consumer_clk == PIS_CLK_PCLK1) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_APB1 << PIS_CH0_CON_SYNCSEL_POSS); + if (hperh->init.consumer_clk == PIS_CLK_PCLK2) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_APB2 << PIS_CH0_CON_SYNCSEL_POSS); + if (hperh->init.consumer_clk == PIS_CLK_SYS) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS); + } + + if (hperh->init.producer_signal == PIS_OUT_PULSE) { + if (hperh->init.consumer_clk == PIS_CLK_PCLK1) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_APB1 << PIS_CH0_CON_SYNCSEL_POSS); + if (hperh->init.consumer_clk == PIS_CLK_PCLK2) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_APB2 << PIS_CH0_CON_SYNCSEL_POSS); + if (hperh->init.consumer_clk == PIS_CLK_SYS) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS); + } + } + + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS); + hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch]; + + /* enable consumer bit, switch pin of consumer */ + if (hperh->init.input_chan == PIS_CHAN_INPUT) { + switch (hperh->consumer_con) { + case PIS_CON_0: + PIS->TAR_CON0 |= hperh->consumer_pos; + break; + case PIS_CON_1: + PIS->TAR_CON1 |= hperh->consumer_pos; + break; + default: + break; + } + } + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Destroy the PIS mode according to the specified parameters in + * the pis_init_t and create the associated handle. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_destroy(pis_handle_t *hperh) +{ + assert_param(IS_PIS(hperh->perh)); + + if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch]) + return ERROR; + + __LOCK(hperh); + + CLEAR_BIT(PIS->CH_OER, (1 << hperh->consumer_ch)); + WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0); + + switch (hperh->consumer_con) { + case PIS_CON_0: + PIS->TAR_CON0 &= ~(hperh->consumer_pos); + break; + case PIS_CON_1: + PIS->TAR_CON1 &= ~(hperh->consumer_pos); + break; + default: + break; + } + + hperh->state = PIS_STATE_RESET; + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup PIS_Public_Functions_Group2 Operation functions + * @brief PIS output enable or disable functions + * @{ + */ + +/** + * @brief Start the PIS output function. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @param ch: The PIS channel enable output + * This parameter can be one of the following values: + * @arg PIS_OUT_CH_0 + * @arg PIS_OUT_CH_1 + * @arg PIS_OUT_CH_2 + * @arg PIS_OUT_CH_3 + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch) +{ + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_OUPUT_CH(ch)); + __LOCK(hperh); + SET_BIT(PIS->CH_OER, (1 << ch)); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Stop the PIS output function. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @param ch: The PIS channel disable output + * This parameter can be one of the following values: + * @arg PIS_OUT_CH_0 + * @arg PIS_OUT_CH_1 + * @arg PIS_OUT_CH_2 + * @arg PIS_OUT_CH_3 + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch) +{ + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_OUPUT_CH(ch)); + __LOCK(hperh); + CLEAR_BIT(PIS->CH_OER, (1 << ch)); + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup PIS_Public_Functions_Group3 Peripheral State and Errors functions + * @brief PIS State and Errors functions + * @{ + */ + +/** + * @brief Returns the PIS state. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @retval ALD state + */ +pis_state_t ald_pis_get_state(pis_handle_t *hperh) +{ + assert_param(IS_PIS(hperh->perh)); + return hperh->state; +} + +/** + * @} + */ + +/** @defgroup PIS_Public_Functions_Group4 modulate output functions + * @brief PIS modulate output signal functions + * @{ + */ + +/** + * @brief Config the PIS modulate signal function + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @param config: Pointer to a pis_modulate_config_t structure that + * contains the selected target (UART0,UART1,UART2,UART3 or + * LPUART0) how to modulate the target output signal. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config) +{ + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_MODU_TARGET(config->target)); + assert_param(IS_PIS_MODU_LEVEL(config->level)); + assert_param(IS_PIS_MODU_SRC(config->src)); + assert_param(IS_PIS_MODU_CHANNEL(config->channel)); + __LOCK(hperh); + + switch (config->target) { + case PIS_UART0_TX: + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMLVLS_MSK, config->level << PIS_UART0_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMSS_MSK, config->src << PIS_UART0_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXSIGS_MSK, config->channel << PIS_UART0_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART1_TX: + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMLVLS_MSK, config->level << PIS_UART1_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMSS_MSK, config->src << PIS_UART1_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXSIGS_MSK, config->channel << PIS_UART1_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART2_TX: + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMLVLS_MSK, config->level << PIS_UART2_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMSS_MSK, config->src << PIS_UART2_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXSIGS_MSK, config->channel << PIS_UART2_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART3_TX: + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMLVLS_MSK, config->level << PIS_UART3_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMSS_MSK, config->src << PIS_UART3_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXSIGS_MSK, config->channel << PIS_UART3_TXMCR_TXSIGS_POSS); + break; + + case PIS_LPUART0_TX: + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXMLVLS_MSK, config->level << PIS_LPUART0_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXMSS_MSK, config->src << PIS_LPUART0_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXSIGS_MSK, config->channel << PIS_LPUART0_TXMCR_TXSIGS_POSS); + break; + + default: + break; + } + + __UNLOCK(hperh); + return OK; +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_PIS */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c new file mode 100644 index 0000000000000000000000000000000000000000..500bd1acc5a49508af599fd78fa97134daed0732 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_pmu.c @@ -0,0 +1,283 @@ +/** + ********************************************************************************* + * + * @file ald_pmu.c + * @brief PMU module driver. + * + * @version V1.0 + * @date 04 Dec 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_pmu.h" +#include "ald_bkpc.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup PMU PMU + * @brief PMU module driver + * @{ + */ +#ifdef ALD_PMU + + +/** @defgroup PMU_Private_Functions PMU Private Functions + * @{ + */ + +/** + * @brief PMU module interrupt handler + * @retval None + */ +void ald_lvd_irq_handler(void) +{ + SYSCFG_UNLOCK(); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + SYSCFG_LOCK(); + + return; +} +/** + * @} + */ + +/** @defgroup PMU_Public_Functions PMU Public Functions + * @{ + */ + +/** @addtogroup PMU_Public_Functions_Group1 Low Power Mode + * @brief Low power mode select functions + * + * @verbatim + ============================================================================== + ##### Low power mode select functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Enter stop1 mode. + (+) Enter stop2 mode. + (+) Enter standby mode. + (+) Get wakeup status. + (+) Clear wakeup status. + + @endverbatim + * @{ + */ + +/** + * @brief Enter stop1 mode + * @retval None + */ +void ald_pmu_stop1_enter(void) +{ + SYSCFG_UNLOCK(); + SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); + MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STOP1 << PMU_CR0_LPM_POSS); + SYSCFG_LOCK(); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + + return; +} + +/** + * @brief Enter stop2 mode + * @retval None + */ +void ald_pmu_stop2_enter(void) +{ + SYSCFG_UNLOCK(); + SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); + MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STOP2 << PMU_CR0_LPM_POSS); + SYSCFG_LOCK(); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + + return; +} + +/** + * @brief Enter standby mode + * @param port: The port whick wake up the standby mode. + * @param level: Wakeup level. + * @retval None + */ +void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level) +{ + ald_bkpc_standby_wakeup_config(port, level); + + SYSCFG_UNLOCK(); + SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); + MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STANDBY << PMU_CR0_LPM_POSS); + SYSCFG_LOCK(); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + + return; +} + +/** + * @brief Configures low power mode. The system clock must + * be less than 2MHz. Such as: LOSC or LRC. + * @param vol: LDO output voltage select in low power mode. + * @param state: New state, ENABLE/DISABLE; + * @retval None + */ +void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state) +{ + assert_param(IS_FUNC_STATE(state)); + SYSCFG_UNLOCK(); + + if (state) { + assert_param(IS_PMU_LDO_LPMODE_OUTPUT(vol)); + + MODIFY_REG(PMU->CR0, PMU_CR0_LPVS_MSK, vol << PMU_CR0_LPVS_POSS); + SET_BIT(PMU->CR0, PMU_CR0_LPRUN_MSK); + } + else { + CLEAR_BIT(PMU->CR0, PMU_CR0_LPRUN_MSK); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Get wakup status. + * @param sr: Status bit. + * @retval Status. + */ +flag_status_t ald_pmu_get_status(pmu_status_t sr) +{ + assert_param(IS_PMU_STATUS(sr)); + + if (READ_BIT(PMU->SR, sr)) + return SET; + + return RESET; +} + +/** + * @brief Clear wakup status. + * @param sr: Status bit. + * @retval None + */ +void ald_pmu_clear_status(pmu_status_t sr) +{ + assert_param(IS_PMU_STATUS(sr)); + SYSCFG_UNLOCK(); + + if (sr == PMU_SR_WUF) + SET_BIT(PMU->CR0, PMU_CR0_CWUF_MSK); + else if (sr == PMU_SR_STANDBYF) + SET_BIT(PMU->CR0, PMU_CR0_CSTANDBYF_MSK); + else + ;/* do nothing */ + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Configure peripheral power + * @param perh: The peripheral + * @param state: ENABLE/DISABLE + * @retval None + */ +void ald_pmu_perh_power_config(pmu_perh_power_t perh, type_func_t state) +{ + assert_param(IS_PMU_PERH_POWER(perh)); + assert_param(IS_FUNC_STATE(state)); + + SYSCFG_UNLOCK(); + + if (state) + SET_BIT(PMU->PWRCR, perh); + else + CLEAR_BIT(PMU->PWRCR, perh); + + SYSCFG_LOCK(); + return; +} +/** + * @} + */ + +/** @addtogroup PMU_Public_Functions_Group2 LVD Configure + * @brief LVD configure functions + * + * @verbatim + ============================================================================== + ##### LVD configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure lvd parameters. + + @endverbatim + * @{ + */ + +/** + * @brief Configure lvd using specified parameters. + * @param sel: LVD threshold voltage. + * @param mode: LVD trigger mode. + * @param state: New state, ENABLE/DISABLE; + * @retval None + */ +void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state) +{ + assert_param(IS_FUNC_STATE(state)); + SYSCFG_UNLOCK(); + + if (state) { + assert_param(IS_PMU_LVD_VOL_SEL(sel)); + assert_param(IS_PMU_LVD_TRIGGER_MODE(mode)); + + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS); + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); + } + else { + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); + } + + SYSCFG_LOCK(); + return; +} +/** + * @} + */ + + +/** + * @} + */ +#endif /* ALD_PMU */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c new file mode 100644 index 0000000000000000000000000000000000000000..d8bd0c9430e727349e1151ab731a25cdc8453b3c --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_qspi.c @@ -0,0 +1,1110 @@ +/** + ********************************************************************************* + * + * @file ald_qspi.c + * @brief QSPI module driver. + * + * @version V1.0 + * @date 09 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ +#include "ald_qspi.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup QSPI QSPI + * @brief QSPI module driver + * @{ + */ + +#ifdef ALD_QSPI + +/** @defgroup QSPI_Private_Functions QSPI Private Functions + * @brief QSPI Private functions + * @{ + */ + +/** + * @brief Wait for a flag state until timeout. + * @param hperh: QSPI handle + * @param timeout: Duration of the time out + * @param tickstart: tick start value + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t qspi_wait_for_idle(qspi_handle_t *hperh, uint32_t tickstart, uint32_t timeout) +{ + /* Wait until flag is in expected state */ + while (READ_BIT(hperh->perh->CR, QSPI_CR_IDLES_MSK) != QSPI_CR_IDLES) { + /* Check for the Timeout */ + if (timeout != ALD_MAX_DELAY) { + if ((timeout == 0U) || ((ald_get_tick() - tickstart) > timeout)) { + return ERROR; + } + } + } + return OK; +} + +/** + * @brief Get indirect read status. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param status: Indirect status. + * @retval Status, see @ref ald_status_t. + */ +static flag_status_t qspi_indrd_get_status(qspi_handle_t *hperh, qspi_indrd_flag_t status) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_INDIRECT_READ_STATUS(status)); + + if (hperh->perh->IRTR & status) + return SET; + + return RESET; +} + +/** + * @} + */ + +/** @defgroup QSPI_Public_Functions QSPI Public Functions + * @brief QSPI Public Functions + * @{ + */ +/** @defgroup QSPI_Public_Functions_Group1 Basic execution functions + * @brief QSPI basic execution functions + * @{ + */ +/** + * @brief Initializes the QSPI basic parameters. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @retval None. + */ +void ald_qspi_init(qspi_handle_t *hperh) +{ + assert_param(IS_QSPI_CLOCK_PRESCALER(hperh->init.clkdiv)); + assert_param(IS_QSPI_CLOCK_PHASE(hperh->init.chpa)); + assert_param(IS_QSPI_CLOCK_POLARITY(hperh->init.cpol)); + + MODIFY_REG(hperh->perh->CR, QSPI_CR_BAUD_MSK | QSPI_CR_CPOL_MSK | QSPI_CR_CPHA_MSK | \ + QSPI_CR_PSL_MSK | QSPI_CR_SWPP_MSK , (hperh->init.clkdiv << QSPI_CR_BAUD_POSS) | \ + (hperh->init.cpol << QSPI_CR_CPOL_POS) | \ + (hperh->init.chpa << QSPI_CR_CPHA_POS) | \ + (hperh->init.chipsel << QSPI_CR_PSL_POSS) | \ + (hperh->init.wrppin << QSPI_CR_SWPP_POS)); + + return; +} + +/** + * @brief DAC read. + * @param addr: address. + * @retval value + */ +uint32_t ald_qspi_dac_rd(uint32_t addr) +{ + return ((*(volatile uint32_t *)(addr))); +} + +/** + * @brief DAC write . + * @param addr: address. + * @param dat: data. + * @retval None + */ +void ald_qspi_dac_wr(uint32_t addr, uint32_t dat) +{ + (*(volatile uint32_t *)(addr)) = dat; +} + +/** + * @brief Configure Read Operations. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param rdcfg: Pointer to configuration structure for QSPI read operations. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_read_config(qspi_handle_t * hperh, const qspi_read_cfg_t * rdcfg) +{ + ald_status_t status = ERROR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_RD_OPCODE(rdcfg->rdcde)); + assert_param(IS_QSPI_DCYLES(rdcfg->dcyles)); + assert_param(IS_QSPI_XFER_TYPE(rdcfg->datxfer)); + assert_param(IS_QSPI_XFER_TYPE(rdcfg->addxfer)); + assert_param(IS_QSPI_XFER_TYPE(rdcfg->instxfer)); + + status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE); + + if (status != OK) + return status; + + MODIFY_REG(hperh->perh->DRIR, QSPI_DRIR_RINST_MSK | QSPI_DRIR_MBEN_MSK | \ + QSPI_DRIR_DCYC_MSK | QSPI_DRIR_ADMODE_MSK | \ + QSPI_DRIR_DMODE_MSK | QSPI_DRIR_IMODE_MSK | \ + QSPI_DRIR_DDRM_MSK, \ + (rdcfg->rdcde | (rdcfg->dcyles << 24) | \ + (rdcfg->addxfer << 12) | (rdcfg->instxfer << 8) | \ + (rdcfg->ddrbit << QSPI_DRIR_DDRM_POS) | (rdcfg->modebit << QSPI_DRIR_MBEN_POS)) | \ + (rdcfg->datxfer << QSPI_DRIR_DMODE_POSS)); + + if (rdcfg->modebit) + MODIFY_REG(hperh->perh->MBR, QSPI_MBR_MODEB_MSK, rdcfg->mbitval); + + return status; +} + +/** + * @brief Configure Write Operations. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param wrcfg: Pointer to configuration structure for QSPI write operations. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_write_config(qspi_handle_t * hperh, const qspi_write_cfg_t * wrcfg) +{ + ald_status_t status = ERROR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_WR_OPCODE(wrcfg->wrcde)); + assert_param(IS_QSPI_DCYLES(wrcfg->dcyles)); + assert_param(IS_QSPI_XFER_TYPE(wrcfg->datxfer)); + assert_param(IS_QSPI_XFER_TYPE(wrcfg->addxfer)); + + status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE); + + if (status != OK) + return status; + + MODIFY_REG(hperh->perh->DWIR, QSPI_DWIR_WINST_MSK | QSPI_DWIR_DCYC_MSK | \ + QSPI_DWIR_ADMODE_MSK | QSPI_DWIR_DMODE_MSK, + wrcfg->wrcde | \ + (wrcfg->addxfer << 12) | \ + (wrcfg->datxfer << 16) | \ + (wrcfg->dcyles << 24)); + if (wrcfg->autowel) + CLEAR_BIT(hperh->perh->DWIR, QSPI_DWIR_WELD_MSK); + else + SET_BIT(hperh->perh->DWIR, QSPI_DWIR_WELD_MSK); + + return status; +} + +/** + * @brief QSPI Device Delay Configuration. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param dlycfg: Device delay configuration structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_device_delay_config(qspi_handle_t * hperh, qspi_dly_cfg_t *dlycfg) +{ + ald_status_t status = ERROR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_DEVICE_DELAY_CCSOT(dlycfg->ccsot)); + assert_param(IS_QSPI_DEVICE_DELAY_CSEOT(dlycfg->cseot)); + assert_param(IS_QSPI_DEVICE_DELAY_CSDADS(dlycfg->csdads)); + assert_param(IS_QSPI_DEVICE_DELAY_CSDA(dlycfg->csda)); + + status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE); + + if (status != OK) + return status; + + MODIFY_REG(hperh->perh->DDLR, QSPI_DDLR_CSSOT_MSK | QSPI_DDLR_CSEOT_MSK | QSPI_DDLR_CSDADS_MSK | QSPI_DDLR_CSDA_MSK, \ + dlycfg->ccsot | (dlycfg->cseot << 8) | (dlycfg->csdads << 16) | (dlycfg->csda << 24)); + return status; +} + +/** + * @brief QSPI Read Data Capture Configuration. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param dtcptcfg: Data capture configuration structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_read_data_capture_config(qspi_handle_t * hperh, qspi_data_capture_cfg_t *dtcptcfg) +{ + ald_status_t status = ERROR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_READ_DATA_CAPTURE_DELAY_READ(dtcptcfg->dlydcl)); + assert_param(IS_QSPI_READ_DATA_SAMPLE_EDGE(dtcptcfg->smpledge)); + assert_param(IS_QSPI_READ_DATA_DELAY_TRANSMIT(dtcptcfg->dlytd)); + + status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE); + + if (status != OK) + return status; + + MODIFY_REG(hperh->perh->RDCR, QSPI_RDCR_BYLPC_MSK | QSPI_RDCR_DLYR_MSK | QSPI_RDCR_SMES_MSK | QSPI_RDCR_DLYT_MSK, \ + dtcptcfg->bypsalcc | (dtcptcfg->dlydcl << 1) | (dtcptcfg->smpledge << 5) | (dtcptcfg->dlytd << 16)); + return status; +} + +/** + * @brief QSPI Flash memory Configuration. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param devcfg: flash parameter configuration structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_device_size_config(qspi_handle_t *hperh, qspi_device_size_t * devcfg) +{ + ald_status_t status = ERROR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_ADDR_SIZE(devcfg->addr)); + assert_param(IS_QSPI_PAGE_SIZE(devcfg->page)); + assert_param(IS_QSPI_BLOCK_SIZE(devcfg->blk)); + assert_param(IS_QSPI_NSS_SIZE(devcfg->cs0)); + assert_param(IS_QSPI_NSS_SIZE(devcfg->cs1)); + assert_param(IS_QSPI_NSS_SIZE(devcfg->cs2)); + assert_param(IS_QSPI_NSS_SIZE(devcfg->cs3)); + + status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE); + + if (status != OK) + return status; + + MODIFY_REG(hperh->perh->DSCR, QSPI_DSCR_ADSIZE_MSK | QSPI_DSCR_PASIZE_MSK | QSPI_DSCR_BKSIZE_MSK | QSPI_DSCR_CS0SIZE_MSK | \ + QSPI_DSCR_CS1SIZE_MSK | QSPI_DSCR_CS2SIZE_MSK | QSPI_DSCR_CS3SIZE_MSK, \ + (devcfg->addr << QSPI_DSCR_ADSIZE_POSS) | \ + (devcfg->page << QSPI_DSCR_PASIZE_POSS) | \ + (devcfg->blk << QSPI_DSCR_BKSIZE_POSS) | \ + (devcfg->cs0 << QSPI_DSCR_CS0SIZE_POSS) | \ + (devcfg->cs1 << QSPI_DSCR_CS1SIZE_POSS) | \ + (devcfg->cs2 << QSPI_DSCR_CS2SIZE_POSS) | \ + (devcfg->cs3 << QSPI_DSCR_CS3SIZE_POSS)); + return OK; +} + +/** + * @brief Initializes the QSPI direct access according to the specified parameters + * in the associated handle. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param dcfg : structure that contains the indirect read command configuration information. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t qspi_dac_config(qspi_handle_t * hperh, qspi_dac_cfg_t * dcfg) +{ + ald_status_t status = ERROR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_WR_OPCODE(dcfg->wrinit.wrcde)); + assert_param(IS_QSPI_DCYLES(dcfg->wrinit.dcyles)); + assert_param(IS_QSPI_XFER_TYPE(dcfg->wrinit.datxfer)); + assert_param(IS_QSPI_XFER_TYPE(dcfg->wrinit.addxfer)); + assert_param(IS_QSPI_XFER_TYPE(dcfg->wrinit.instxfer)); + + status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE); + + if (status != OK) + return status; + + QSPI_DISABLE(hperh); + ald_qspi_init(hperh); + + if (ald_qspi_write_config(hperh, &dcfg->wrinit) != OK) + return ERROR; + if (ald_qspi_read_config(hperh, &dcfg->rdinit) != OK) + return ERROR; + + MODIFY_REG(hperh->perh->DWIR, QSPI_DWIR_WINST_MSK | QSPI_DWIR_DCYC_MSK | \ + QSPI_DWIR_ADMODE_MSK | QSPI_DWIR_DMODE_MSK | \ + QSPI_DWIR_WELD_MSK, dcfg->wrinit.wrcde | dcfg->wrinit.autowel | \ + (dcfg->wrinit.addxfer << 12) | \ + (dcfg->wrinit.datxfer << 16) | \ + (dcfg->wrinit.dcyles << 24)); + MODIFY_REG(hperh->perh->DRIR, QSPI_DRIR_RINST_MSK, dcfg->wrinit.instxfer); + + if (dcfg->addrremap) + MODIFY_REG(hperh->perh->RAR, QSPI_RAR_READDR_MSK, dcfg->remapaddr); + + MODIFY_REG(hperh->perh->CR, QSPI_CR_DTRM_MSK | QSPI_CR_ADEN_MSK | QSPI_CR_XIPIM_MSK | \ + QSPI_CR_XIPNX_MSK | QSPI_CR_AREN_MSK | QSPI_CR_DMAEN_MSK, \ + dcfg->dtrprtcol | dcfg->ahbdecoder); + QSPI_ENABLE(hperh); + return OK; +} + +/** + * @} + */ + +/** @defgroup QSPI_Public_Functions_Group2 Indirect and stig access execution functions + * @brief QSPI indirect and stig access execution functions + * @{ + */ +/** + * @brief Initializes the QSPI indirect access according to the specified parameters + * in the associated handle. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param indcfg: Pointer to indirect access initialization structure qspi_indac_config_t. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_indac_config(qspi_handle_t * hperh, qspi_indac_cfg_t *indcfg) +{ + ald_status_t status = ERROR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_SRAM_PARTITION(indcfg->srampt)); + assert_param(IS_QSPI_INDIRECT_TRIGGER_RANGE(indcfg->trgrng)); + assert_param(IS_QSPI_INDIRECT_READ_WATERMARK(indcfg->rdwmark)); + + status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE); + + if (status != OK) + return status; + + QSPI_DISABLE(hperh); + + MODIFY_REG(hperh->perh->SPR, QSPI_SPR_SRAMPS_MSK, indcfg->srampt); + MODIFY_REG(hperh->perh->IATR, QSPI_IATR_INDTAD_MSK, indcfg->trgaddr); + MODIFY_REG(hperh->perh->ITARR, QSPI_ITARR_RNGW_MSK, indcfg->trgrng); + MODIFY_REG(hperh->perh->IWTWR, QSPI_IWTWR_VAULE_MSK, indcfg->wrwmark); + MODIFY_REG(hperh->perh->IRTWR, QSPI_IRTWR_VAULE_MSK, indcfg->rdwmark); + + QSPI_ENABLE(hperh); + + return OK; +} + +/** + * @brief QSPI write data by interrupt. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param saddr: Write start address. + * @param psrc: Pointer to source data buffer. + * @param size : Write bytes number. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_indac_transmit_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size) +{ + uint32_t i = 0; + uint32_t tmp = 0, pgsize = 0; + assert_param(IS_QSPI_ALL(hperh->perh)); + + if ((psrc == NULL) || (size == 0)) + return ERROR; + + hperh->state = QSPI_STATE_BUSY_TX; + hperh->rx_buf = NULL; + hperh->rx_cnt = 0; + hperh->rx_size = 0; + hperh->tx_buf = psrc; + hperh->tx_cnt = 0; + hperh->tx_size = size; + + tmp = READ_REG(hperh->perh->DSCR); + pgsize = (tmp & 0xfff0) >> 4; + + if (size >= pgsize) + tmp = pgsize; + else + tmp = size; + + hperh->tx_cnt += tmp; + + ald_qspi_clear_it_flag(hperh, QSPI_IF_INDCF); + MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, saddr); + MODIFY_REG(hperh->perh->IWTNR, QSPI_IWTNR_NUM_MSK, size); + ald_qspi_interrupt_config(hperh, QSPI_IT_INDTWF, ENABLE); + ald_qspi_interrupt_config(hperh, QSPI_IT_INDCF, ENABLE); + + /* Trigger indirect write */ + SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK); + + for (i = 0; i < (tmp / 4); ++i) + *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(psrc + 4 * i)); + + return OK; +} + +/** + * @brief Transmit data to flash by poll. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param saddr: Write start address. + * @param psrc: Pointer to source data buffer. + * @param size: Write bytes number. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_indac_transmit_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size) +{ + uint32_t i, j = 0, cnt = 0; + uint32_t tmp = 0; + uint32_t idx = 0, txsm = 0; + assert_param(IS_QSPI_ALL(hperh->perh)); + + if ((psrc == NULL) || (size == 0)) + return ERROR; + + MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, saddr); + MODIFY_REG(hperh->perh->IWTNR, QSPI_IWTNR_NUM_MSK, size); + + /* Counter write times totally */ + if (size % 4) + cnt = (size / 4) + 1; + else + cnt = size / 4; + /* Get transmit SRAM partition (unit:4bytes)*/ + tmp = READ_REG(hperh->perh->SPR); + txsm = QSPI_SRAM_SIZE - tmp; + if (cnt <= txsm) { + /* Trigger indirect write */ + SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK); + for (i = 0; i < cnt; ++i) + *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(psrc + 4 *i)); + } else { + SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK); + for (j = 0; j < (cnt / txsm); ++j) { + for (i = 0; i < txsm; ++i) { + *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(psrc + idx + 4 *i)); + } + idx += txsm * 4; + do { + tmp = READ_REG(hperh->perh->SFLR); + tmp = (tmp >> 16) & 0xffff; + } while (tmp != 0); + } + + for (j = 0; j < (cnt % txsm); ++j) + *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(psrc + idx + 4 *j)); + } + /* Wait for indirect read operation completely */ + do { + tmp = READ_REG(hperh->perh->IWTR); + } while ( tmp & 0x4); + + return OK; +} + +/** + * @brief Read data from flash by poll. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param saddr: Read start address. + * @param desbuf: Pointer to data buffer. + * @param size: Read bytes number. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_indac_read_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size) +{ + + uint32_t i, j = 0, cnt = 0; + uint32_t tmp = 0; + uint32_t idx = 0, rxsm = 0; + + assert_param(IS_QSPI_ALL(hperh->perh)); + + if ((desbuf == NULL) || (size == 0)) + return ERROR; + + MODIFY_REG(hperh->perh->IRTSAR, QSPI_IRTSAR_ADDR_MSK, saddr); + MODIFY_REG(hperh->perh->IRTNR, QSPI_IRTNR_NUM_MSK, size); + /* Counter read times totally */ + if (size % 4) + cnt = (size / 4) + 1; + else + cnt = size / 4; + /* Get read SRAM partition (unit: 4bytes)*/ + rxsm = READ_REG(hperh->perh->SPR) + 1; + if (cnt <= rxsm) { + SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK); + do { + tmp = READ_REG(hperh->perh->SFLR); + tmp = tmp & 0x0000ffff; + } while ( tmp != cnt); + for (i = 0; i < cnt; ++i) + *(uint32_t *)(desbuf + 4 *i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS; + } else { + SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK); + for (j = 0; j < (cnt / rxsm); ++j) { + do { + tmp = READ_REG(hperh->perh->SFLR); + tmp = tmp & 0x0000ffff; + } while ( tmp != rxsm); + for (i = 0; i < rxsm; ++i) { + *(uint32_t *)(desbuf + idx + 4 *i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS; + } + idx += rxsm * 4; + } + do { + tmp = READ_REG(hperh->perh->SFLR); + tmp = tmp & 0x0000ffff; + } while ( tmp != (cnt % rxsm)); + + for (j = 0; j < (cnt % rxsm); ++j) { + *(uint32_t *)(desbuf + idx + 4 *i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS; + } + } + /* Wait for indirect read operation completely */ + do { + tmp = READ_REG(hperh->perh->IRTR); + } while ( tmp & 0x04); + + return OK; +} + +/** + * @brief QSPI read data by interrupt. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param saddr: Read start address. + * @param desbuf: Pointer to destination data buffer. + * @param size: Read bytes length. + * @retval Status, see @ref ald_status_t. + */ + +ald_status_t ald_qspi_indac_read_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + + if ((desbuf == NULL) || (size == 0)) + return ERROR; + + hperh->state = QSPI_STATE_BUSY_RX; + hperh->rx_buf = desbuf; + hperh->rx_cnt = 0; + hperh->rx_size = size; + hperh->tx_buf = NULL; + hperh->tx_cnt = 0; + hperh->tx_size = 0; + + ald_qspi_clear_it_flag(hperh, QSPI_IF_INDCF); + MODIFY_REG(hperh->perh->IRTSAR, QSPI_IRTSAR_ADDR_MSK, saddr); + MODIFY_REG(hperh->perh->IRTNR, QSPI_IRTNR_NUM_MSK, size); + ald_qspi_interrupt_config(hperh, QSPI_IT_INDTWF, ENABLE); + ald_qspi_interrupt_config(hperh, QSPI_IT_INDCF, ENABLE); + SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK); + + return OK; +} + +/** + * @brief Execute a STIG command. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param stigcmd: Pointer to a structure that describes the STIG command. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_execute_stig_cmd(qspi_handle_t * hperh, const qspi_stig_cmd_t * stigcmd) +{ + uint32_t i; + ald_status_t status = ERROR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(stigcmd->addr_len <= 4); + assert_param(stigcmd->wr_len <= 8); + assert_param(stigcmd->rd_len <= 8); + assert_param(stigcmd->d_sycle < 32); + + if (stigcmd->wr_len) + assert_param(stigcmd->wr_buf); + if (stigcmd->rd_len) + assert_param(stigcmd->rd_buf); + + /* wait for Flash idle */ + status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE); + + if (status != OK) + return ERROR; + + MODIFY_REG(hperh->perh->FCR, QSPI_FCR_OPCODE_MSK | QSPI_FCR_DUMNUM_MSK , ((stigcmd->code << 24) | (stigcmd->d_sycle << 7))); + + if (stigcmd->wr_len) { + uint32_t buffer[2] = {0, 0}; + uint8_t * dst = (uint8_t *) buffer; + uint8_t * src = stigcmd->wr_buf; + + MODIFY_REG(hperh->perh->FCR, QSPI_FCR_WDNUM_MSK, (stigcmd->wr_len - 1) << QSPI_FCR_WDNUM_POSS); + SET_BIT(hperh->perh->FCR, QSPI_FCR_WREN_MSK); + + for (i = 0; i < stigcmd->wr_len; i++) + dst[i] = src[i]; + + hperh->perh->FCWLR = buffer[0]; + hperh->perh->FCWHR = buffer[1]; + } else { + CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_WDNUM_MSK); + CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_WREN_MSK); + } + + if (stigcmd->addr_len) { + SET_BIT(hperh->perh->FCR, QSPI_FCR_ADDREN_MSK); + + MODIFY_REG(hperh->perh->FCR, QSPI_FCR_ADNUM_MSK, (stigcmd->addr_len - 1) << QSPI_FCR_ADNUM_POSS); + MODIFY_REG(hperh->perh->FCAR, QSPI_FCAR_CMDADR_MSK, stigcmd->addr); + } else { + CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_ADDREN_MSK); + CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_ADNUM_MSK); + CLEAR_BIT(hperh->perh->FCAR, QSPI_FCAR_CMDADR_MSK); + } + + if (stigcmd->mode_bit) { + SET_BIT(hperh->perh->FCR, QSPI_FCR_MODBEN_MSK); + MODIFY_REG(hperh->perh->MBR, QSPI_MBR_MODEB_MSK, stigcmd->val); + } else { + CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_MODBEN_MSK); + CLEAR_BIT(hperh->perh->MBR, QSPI_MBR_MODEB_MSK); + } + + if (stigcmd->rd_len) { + SET_BIT(hperh->perh->FCR, QSPI_FCR_RDEN_MSK); + MODIFY_REG(hperh->perh->FCR, QSPI_FCR_RDNUM_MSK, (stigcmd->rd_len - 1) << QSPI_FCR_RDNUM_POSS); + } else { + CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_RDEN_MSK); + CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_RDNUM_MSK); + } + + /* Start command execution */ + SET_BIT(hperh->perh->FCR, QSPI_FCR_CMDT_MSK); + + while (hperh->perh->FCR & QSPI_FCR_CMDS_MSK); + + /* Read data if any */ + if (stigcmd->rd_len) { + uint32_t buffer[2] = { 0, 0 }; + const uint8_t * src = (const uint8_t *)buffer; + uint8_t * dst = stigcmd->rd_buf; + + buffer[0] = hperh->perh->FCRLR; + buffer[1] = hperh->perh->FCRHR; + + for (i = 0; i < stigcmd->rd_len; i++) { + dst[i] = src[i]; + } + } + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Sends an amount of data with DMA. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param addr: Write start address. + * @param psrc: Pointer to data buffer. + * @param size: Write data bytes. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_indac_transmit_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *psrc, uint16_t size) +{ + uint16_t cnt = 0; + uint32_t *tmp = (uint32_t*)psrc; + /* Get Indirect Read Trigger Address */ + __IO uint32_t *data_reg = (uint32_t *)hperh->perh->IATR; + + assert_param(IS_QSPI_ALL(hperh->perh)); + + if ((psrc == NULL) || (size == 0)) + return ERROR; + + MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, addr); + MODIFY_REG(hperh->perh->IWTNR, QSPI_IWTNR_NUM_MSK, size); + QSPI_DMA_ENABLE(hperh); + if (size % 4) + cnt = (size / 4) + 1; + else + cnt = size / 4; + + __LOCK(hperh); + + hperh->hdma.perh = DMA0; + hperh->hdma.cplt_cbk = NULL; + ald_dma_config_struct(&hperh->hdma.config); + + hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma.config.src = (void *)tmp; + hperh->hdma.config.dst = (void *)data_reg; + hperh->hdma.config.size = cnt; + hperh->hdma.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_QSPI; + hperh->hdma.config.msigsel = DMA_MSIGSEL_QSPI_WRITE; + hperh->hdma.config.channel = 0; + hperh->hdma.config.R_power = DMA_R_POWER_4; + hperh->hdma.config.burst = ENABLE; + ald_dma_config_basic(&hperh->hdma); + + /* Trigger indirect write */ + SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receive an amount of data with DMA. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param addr: Read start address. + * @param pdbuf: Pointer to data buffer. + * @param size: Read data bytes. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_indac_read_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *pdbuf, uint16_t size) +{ + uint16_t cnt = 0; + ald_status_t status = OK; + uint32_t *tmp = (uint32_t *)pdbuf; + /* Get Indirect Read Trigger Address */ + __IO uint32_t *data_reg = (uint32_t *)hperh->perh->IATR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_ALL(hperh->perh)); + + if ((pdbuf == NULL) || (size == 0)) + return ERROR; + + MODIFY_REG(hperh->perh->IRTSAR, QSPI_IRTSAR_ADDR_MSK, addr); + MODIFY_REG(hperh->perh->IRTNR, QSPI_IRTNR_NUM_MSK, size); + + QSPI_DMA_ENABLE(hperh); + + if (size % 4) + cnt = (size / 4) + 1; + else + cnt = size / 4; + + __LOCK(hperh); + + hperh->hdma.perh = DMA0; + hperh->hdma.cplt_cbk = NULL; + ald_dma_config_struct(&hperh->hdma.config); + + hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma.config.src = (void *)data_reg; + hperh->hdma.config.dst = (void *)tmp; + hperh->hdma.config.size = cnt; + hperh->hdma.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.dst_inc = DMA_DATA_INC_WORD; + hperh->hdma.config.msel = DMA_MSEL_QSPI; + hperh->hdma.config.msigsel = DMA_MSIGSEL_QSPI_READ; + hperh->hdma.config.channel = 0; + hperh->hdma.config.R_power = DMA_R_POWER_4; + hperh->hdma.config.burst = ENABLE; + ald_dma_config_basic(&hperh->hdma); + + /* Trigger indirect write */ + SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK); + __UNLOCK(hperh); + + return status; +} +#endif + +/** + * @} + */ + +/** @defgroup QSPI_Public_Functions_Group3 Status functions + * @brief QSPI status functions + * @{ + */ +/** + * @brief Get the status of QSPI interrupt flag. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param flag: Specifies the QSPI interrupt flag. + * This parameter can be one of the @ref qspi_flag_t. + * @retval Status, see @ref flag_status_t. + */ +flag_status_t qspi_get_flag_status(qspi_handle_t *hperh, qspi_flag_t flag) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_IF(flag)); + + if (hperh->perh->IFR & flag) + return SET; + + return RESET; +} + +/** + * @brief Clear the QSPI interrupt flag. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param flag: Specifies the QSPI interrupt flag. + * This parameter can be one of the @ref qspi_flag_t. + * @retval None + */ +void ald_qspi_clear_it_flag(qspi_handle_t *hperh, qspi_flag_t flag) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_IF(flag)); + + hperh->perh->IFR = flag; + + return; +} + +/** + * @brief Read QSPI SRAM fill level. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param srt: QSPI embeded SRAM type,the value can be one of @ref qspi_sram_t. + * @retval sram fill level value. + */ +uint16_t qspi_read_sram_fill_level(qspi_handle_t * hperh, qspi_sram_t srt) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_INDIRECT_SRAM_FILL_TYPE(srt)); + + if (srt == QSPI_SRAM_RD) + return READ_BITS(hperh->perh->SFLR, QSPI_SFLR_INDRSFL_MSK, QSPI_SFLR_INDRSFL_POSS); + + return READ_BITS(hperh->perh->SFLR, QSPI_SFLR_INDWSFL_MSK, QSPI_SFLR_INDWSFL_POSS); +} + +/** + * @brief QSPI Write Protect Configuration. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param wpcfg: Pointer to the QSPI write protect configuration structer. + * @retval None. + */ +void ald_qspi_write_proect_config(qspi_handle_t * hperh, qspi_wr_protect_t * wpcfg) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + + MODIFY_REG(hperh->perh->WPLR, QSPI_WPLR_LBLKNUM_MSK, wpcfg->lowblk); + MODIFY_REG(hperh->perh->WPHR, QSPI_WPHR_HBLKNUM_MSK, wpcfg->upblk); + QSPI_WRITE_PROTECT_ENABLE(hperh); + + return; +} + +/** + * @brief QSPI Write Protect Inversion. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param state: SRAM protect inversion state. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None. + */ +void ald_qspi_write_proect_inverse(qspi_handle_t * hperh, type_func_t state) +{ + assert_param(IS_FUNC_STATE(state)); + assert_param(IS_QSPI_ALL(hperh->perh)); + + if (state) { + QSPI_WRITE_PROTECT_DISABLE(hperh); + SET_BIT(hperh->perh->WPCR, QSPI_WPCR_WPINV_MSK); + QSPI_WRITE_PROTECT_ENABLE(hperh); + } + else { + QSPI_WRITE_PROTECT_DISABLE(hperh); + SET_BIT(hperh->perh->WPCR, QSPI_WPCR_WPINV_MSK); + QSPI_WRITE_PROTECT_ENABLE(hperh); + } + + return; +} + +/** + * @brief QSPI interrupt handler + * @retval None + */ +void ald_qspi_irq_handler(qspi_handle_t *hperh) +{ + uint32_t regs = 0; + uint32_t tmp = 0, i = 0; + + regs = READ_REG(hperh->perh->DSCR); + regs = (regs & 0x0000fff0) >> 4; + + // indirect transmit + if (hperh->state == QSPI_STATE_BUSY_TX) { + + //QSPI indirect transmit(xfer length longer than watermark value) + if (qspi_get_flag_status(hperh, QSPI_IF_INDTWF) == SET) { + ald_qspi_clear_it_flag(hperh, QSPI_IF_INDTWF); + tmp = hperh->tx_size - hperh->tx_cnt; + if (tmp > regs) { + for (i = 0; i < (regs / 4); ++i) { + *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(hperh->tx_buf + hperh->tx_cnt + 4 * i)); + } + hperh->tx_cnt += regs; + } else { + for (i = 0; i < (tmp / 4); ++i) { + *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(hperh->tx_buf + hperh->tx_cnt + 4 * i)); + } + hperh->tx_cnt += tmp; + } + } + //QSPI indirect transmit completely + if (qspi_get_flag_status(hperh, QSPI_IF_INDCF) == SET) { + ald_qspi_clear_it_flag(hperh, QSPI_IF_INDCF); + ald_qspi_interrupt_config(hperh, QSPI_IT_INDTWF, DISABLE); + //transmit completely callback + } + + } + + // indirect receive + if (hperh->state == QSPI_STATE_BUSY_RX) { + if (qspi_get_flag_status(hperh, QSPI_IF_INDTWF) == SET) { + ald_qspi_clear_it_flag(hperh, QSPI_IF_INDTWF); + tmp = READ_REG(hperh->perh->SFLR); + tmp = tmp & 0xffff; + + for (i = 0; i < tmp; ++i) { + *(uint32_t *)(hperh->rx_buf + hperh->rx_cnt + i*4) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS; + } + hperh->rx_cnt += tmp*4; + } + + if (qspi_get_flag_status(hperh, QSPI_IF_INDCF) == SET) { + ald_qspi_clear_it_flag(hperh, QSPI_IF_INDCF); + ald_qspi_interrupt_config(hperh, QSPI_IT_INDTWF, DISABLE); + + tmp = READ_REG(hperh->perh->SFLR); + tmp = tmp & 0xffff; + + for (i = 0; i < tmp; ++i) { + *(uint32_t *)(hperh->rx_buf + hperh->rx_cnt + i*4) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS; + } + } + } +} + +/** + * @brief Enable/disable the specified QSPI interrupts. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param it: Specifies the QSPI interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref qspi_it_t. + * @param state: New state of the specified QSPI interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_qspi_interrupt_config(qspi_handle_t *hperh, qspi_it_t it, type_func_t state) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IMR |= it; + else + hperh->perh->IMR &= ~it; + + return; +} + +/** + * @brief Configure the QSPI legacy . + * @param hperh: Pointer to a qspi_handle_t structure. + * @param config: structure that contains the legacy configuration information. + * @retval None + */ +void ald_qspi_legacy_config(qspi_handle_t* hperh, const qspi_legacy_cfg_t *config) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + + MODIFY_REG(hperh->perh->TXHR, QSPI_TXHR_TXTH_MSK, config->tx_thrd); + MODIFY_REG(hperh->perh->RXHR, QSPI_RXHR_RXTH_MSK, config->rx_thrd); + QSPI_LEGACY_SPI_ENABLE(hperh); + + return; +} + +/** + * @brief Get QSPI indirect write access status. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param status: qspi indirect write status. + * @retval Status, see @ref ald_status_t. + */ +flag_status_t qspi_indwr_get_status(qspi_handle_t *hperh, qspi_indwr_status_t status) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_INDIRECT_WRITE_STATUS(status)); + + if (hperh->perh->IWTR & status) + return SET; + + return RESET; +} + +/** + * @brief Wait indirect wriet a flag state until time out. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param flag: Flag checked,the parameter can be one of @ref qspi_indwr_status_t. + * @param status: Value of the flag expected,the parameter can be one of @ref flag_status_t. + * @param timeout: Duration of the time out. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t qspi_indwr_wait_flag(qspi_handle_t *hperh, qspi_indwr_status_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick; + + if (timeout == 0) + return ERROR; + + tick = ald_get_tick(); + + /* Waiting for flag */ + while ((qspi_indwr_get_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + + return OK; +} + +/** + * @brief QSPI Indirect read operation wait for specified status. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param flag: specifies the qspi flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t qspi_indrd_wait_flag(qspi_handle_t *hperh, qspi_indrd_flag_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick; + + if (timeout == 0) + return ERROR; + + tick = ald_get_tick(); + + /* Waiting for flag */ + while ((qspi_indrd_get_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + return OK; +} + +/** + * @brief Clear the QSPI interrupt flag. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param flag: Specifies the QSPI interrupt flag. + * This parameter can be one of the @ref qspi_flag_t. + * @retval None + */ +void qspi_clear_flag_status(qspi_handle_t *hperh, qspi_flag_t flag) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_IF(flag)); + + hperh->perh->IFR = flag; + return; +} + +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_QSPI */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c new file mode 100644 index 0000000000000000000000000000000000000000..4e7cd0d3bdda07da89e41a6082d87ad23dd13dbb --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rmu.c @@ -0,0 +1,143 @@ +/** + ********************************************************************************* + * + * @file ald_rmu.c + * @brief RMU module driver. + * + * @version V1.0 + * @date 04 Dec 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_rmu.h" +#include "ald_syscfg.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup RMU RMU + * @brief RMU module driver + * @{ + */ +#ifdef ALD_RMU + +/** @defgroup RMU_Public_Functions RMU Public Functions + * @{ + */ + +/** + * @brief Configure BOR parameters. + * @param flt: filter time. + * @param vol: The voltage. + * @param state: The new status: ENABLE/DISABLE. + * @retval None + */ +void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state) +{ + assert_param(IS_FUNC_STATE(state)); + + SYSCFG_UNLOCK(); + + if (state) { + assert_param(IS_RMU_BORFLT(flt)); + assert_param(IS_RMU_BORVOL(vol)); + + MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS); + MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS); + SET_BIT(RMU->CR, RMU_CR_BOREN_MSK); + } + else { + CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Get specified reset status + * @param state: Speicifies the type of the reset, + * @retval The status: SET/RESET. + */ +flag_status_t ald_rmu_get_reset_status(rmu_state_t state) +{ + assert_param(IS_RMU_STATE(state)); + + if (READ_BIT(RMU->RSTSR, state)) + return SET; + + return RESET; +} + +/** + * @brief Clear the specified reset status + * @param state: Specifies the type of the reset, + * @retval None + */ +void ald_rmu_clear_reset_status(rmu_state_t state) +{ + assert_param(IS_RMU_STATE_CLEAR(state)); + + SYSCFG_UNLOCK(); + WRITE_REG(RMU->CRSTSR, state); + SYSCFG_LOCK(); + + return; +} +/** + * @brief Reset peripheral device + * @param perh: The peripheral device, + * @retval None + */ +void ald_rmu_reset_periperal(rmu_peripheral_t perh) +{ + uint32_t idx, pos; + + assert_param(IS_RMU_PERH(perh)); + + idx = (perh >> 27) & 0x7; + pos = perh & ~(0x7 << 27); + SYSCFG_UNLOCK(); + + switch (idx) { + case 0: + WRITE_REG(RMU->AHB1RSTR, pos); + break; + + case 1: + WRITE_REG(RMU->AHB2RSTR, pos); + break; + + case 2: + WRITE_REG(RMU->APB1RSTR, pos); + break; + + case 4: + WRITE_REG(RMU->APB2RSTR, pos); + break; + + default: + break; + } + + SYSCFG_LOCK(); + return; +} + +/** + * @} + */ +#endif /* ALD_RMU */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..d288c6866cd489b7f7ae60f7314f84afec06dfb0 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtc.c @@ -0,0 +1,1193 @@ +/** + ****************************************************************************** + * @file ald_rtc.c + * @brief RTC module driver. + * This file provides firmware functions to manage the following + * functionalities of the RTC peripheral: + * + Initialization functions + * + Time and date functions + * + Alarm functions + * + Time stamp functions + * + Tamper functions + * + Wake-up functions + * + Clock output functions + * + Peripheral Control functions + * @version V1.0 + * @date 25 Apr 2019 + * @author AE Team + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (+) Enable the RTC controller interface clock. + (+) Select the RTC source clock(default LOSC). + (+) Configure the RTC asynchronous prescaler, synchronous prescaler and hour + format using the ald_rtc_init() function. + + *** Time and date operation *** + ================================= + [..] + (+) To configure the time use the ald_rtc_set_time() function. + (+) To configure the date use the ald_rtc_set_date() function. + (+) To read the time use the ald_rtc_get_time() function. + (+) To read the date use the ald_rtc_get_date() function. + + *** Alarm operation *** + =================================== + [..] + (+) To configure the alarm use ald_rtc_set_alarm() function + (+) To read the alarm use ald_rtc_get_alarm() function + (+) To cancel the alarm use ald_rtc_alarm_cmd() function + + *** Time stamp operation *** + =================================== + [..] + (+) To configure the time stamp use ald_rtc_set_time_stamp() function + (+) To read the time stamp use ald_rtc_get_time_stamp() function + (+) To cancel the time stamp use ald_rtc_cancel_time_stamp() function + + *** Tamper operation *** + =================================== + [..] + (+) To configure the tamper use ald_rtc_set_tamper() function + (+) To cancel the tamper use ald_rtc_alarm_cmd() function + + *** Wake-up operation *** + =================================== + [..] + (+) To configure the wake-up parameters use ald_rtc_set_wakeup() function + (+) To read the re-load register value use ald_rtc_get_wakeup_timer_value() function + (+) To cancel the wake-up use ald_rtc_cancel_wakeup() function + + *** Output clock operation *** + =================================== + [..] + (+) To configure the clock output type use ald_rtc_set_clock_output() function + (+) To cancel the clock output use ald_rtc_cancel_clock_output() function + + *** Control functions *** + =================================== + [..] + (+) Configure interrupt enable/disable. + (+) Enable/disable alarm. + (+) Configure rtc shift. + (+) Calibrate time. + (+) Get interrupt source status. + (+) Get interrupt flag status. + (+) Clear interrupt flag. + + ================================================================== + ##### RTC and low power modes ##### + ================================================================== + [..] The MCU can be woken up from a low power mode by an RTC alternate function. + [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), + RTC wake-up, RTC tamper event detection and RTC time stamp event detection. + These RTC alternate functions can wake up the system from the Stop and + Standby low power modes. + [..] The system can also wake up from low power modes without depending + on an external interrupt (Auto-wake-up mode), by using the RTC alarm + or the RTC wake-up events. + [..] The RTC provides a programmable time base for waking up from the Stop or + Standby mode at regular intervals. Wake-up from STOP and STANDBY modes + is possible only when the RTC clock source is LSE or LSI. + + *** RTC driver macros list *** + ============================================= + [..] + Below the list of most used macros in RTC driver. + + (+) RTC_UNLOCK() Disable the protect. + (+) RTC_LOCK() Enable the protect. + (+) RTC_BY_PASS_ENABLE() Enable the by-pass shadow register. + (+) RTC_BY_PASS_DISABLE() Disable the by-pass shadow register. + (+) RTC_SUMMER_TIME_ENABLE() Enable summer time. + (+) RTC_SUMMER_TIME_DISABLE() Disable summer time. + (+) RTC_WINTER_TIME_ENABLE() Enable winter time. + (+) RTC_WINTER_TIME_DISABLE() Disable winter time. + [..] + (@) You can refer to the RTC driver header file for used the macros + + @endverbatim + ****************************************************************************** + */ + +#include "ald_rtc.h" +#include "ald_bkpc.h" +#include "ald_tsense.h" +#include "ald_syscfg.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup RTC RTC + * @brief RTC module driver + * @{ + */ +#ifdef ALD_RTC + +/** @addtogroup RTC_Private_Functions RTC Private Functions + * @{ + */ +/** + * @brief Converts form 2 digit BCD to Binary. + * @param bcd: BCD value to be converted. + * @retval Converted word. + */ +static uint32_t bcd_to_dec(uint32_t bcd) +{ + return ((bcd & 0xF) + ((bcd >> 4) & 0xF) * 10); +} + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param dec: Byte to be converted. + * @retval Converted byte. + */ +static uint32_t dec_to_bcd(uint32_t dec) +{ + return (((dec / 10) << 4) | (dec % 10)); +} + +/** + * @brief Time and Date consistency check. + * @param t_last: Last time. + * @param d_last: Last date. + * @param time: Current time. + * @param date: Current time. + * @retval status: + * 0 - Not consistency + * 1 - Consistency + */ +static int32_t rtc_consistency_check(rtc_time_t *t_last, + rtc_date_t *d_last, rtc_time_t *time, rtc_date_t *date) +{ + if (t_last->second != time->second) + return 0; + if (t_last->minute != time->minute) + return 0; + if (t_last->hour != time->hour) + return 0; + if (d_last->day != date->day) + return 0; + if (d_last->month != date->month) + return 0; + if (d_last->year != date->year) + return 0; + + return 1; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions RTC Public Functions + * @{ + */ + +/** @defgroup RTC_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * + * @verbatim + =============================================================================== + ##### Initialization function ##### + =============================================================================== + [..] This section provides functions allowing to initialize and configure the + RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + RTC registers Write protection. + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + It is split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize power consumption. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register. + + @endverbatim + * @{ + */ + +/** + * @brief Reset RTC register. + * @retval None + */ +void ald_rtc_reset(void) +{ + RTC_UNLOCK(); + + WRITE_REG(RTC->CON, 0x0); + WRITE_REG(RTC->TAMPCON, 0x0); + WRITE_REG(RTC->WUMAT, 0x0); + WRITE_REG(RTC->IER, 0x0); + WRITE_REG(RTC->IFCR, ~0x0); + + RTC_LOCK(); + return; +} + +/** + * @brief Initialize the RTC module. + * @param init: Pointer to rtc_init_t structure which contains + * the configuration parameters. + * @retval None + */ +void ald_rtc_init(rtc_init_t *init) +{ + assert_param(IS_RTC_HOUR_FORMAT(init->hour_format)); + assert_param(IS_RTC_OUTPUT_SEL(init->output)); + assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity)); + + ald_rtc_reset(); + RTC_UNLOCK(); + + MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS); + MODIFY_REG(RTC->CON, RTC_CON_EOS_MSK, init->output << RTC_CON_EOS_POSS); + MODIFY_REG(RTC->CON, RTC_CON_POL_MSK, init->output_polarity << RTC_CON_POL_POS); + MODIFY_REG(RTC->PSR, RTC_PSR_SPRS_MSK, init->synch_pre_div << RTC_PSR_SPRS_POSS); + MODIFY_REG(RTC->PSR, RTC_PSR_APRS_MSK, init->asynch_pre_div << RTC_PSR_APRS_POSS); + SET_BIT(RTC->CON, RTC_CON_GO_MSK); + + RTC_LOCK(); + return; +} + +/** + * @brief Configure the RTC source. + * @param sel: RTC source type. + * @retval None + */ +void ald_rtc_source_select(rtc_source_sel_t sel) +{ + assert_param(IS_RTC_SOURCE_SEL(sel)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, sel << BKPC_PCCR_RTCCS_POSS); + + if (sel == RTC_SOURCE_LOSC) { + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); + } + else if (sel == RTC_SOURCE_LRC) { + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); + } + else { + ; /* do nothing */ + } + + BKPC_LOCK(); + return; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group2 Time and Date functions + * @brief RTC Time and Date functions + * + * @verbatim + =============================================================================== + ##### Time and Date functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the time use the ald_rtc_set_time() function. + (+) To configure the date use the ald_rtc_set_date() function. + (+) To read the time use the ald_rtc_get_time() function. + (+) To read the date use the ald_rtc_get_date() function. + + @endverbatim + * @{ + */ + +/** + * @brief Set specified time. + * @param time: pointer to a rtc_time_t structure. + * @param format: Data format. + * @retval ALD status. + */ +ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format) +{ + uint32_t tmp; + + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) { + assert_param(IS_RTC_SECOND(time->second)); + assert_param(IS_RTC_MINUTE(time->minute)); + assert_param(IS_RTC_HOUR(time->hour)); + + tmp = (dec_to_bcd(time->second)) | + (dec_to_bcd(time->minute) << 8) | + (dec_to_bcd(time->hour) << 16); + } + else { + assert_param(IS_RTC_SECOND(bcd_to_dec(time->second))); + assert_param(IS_RTC_MINUTE(bcd_to_dec(time->minute))); + assert_param(IS_RTC_HOUR(bcd_to_dec(time->hour))); + + tmp = time->second | (time->minute << 8) | (time->hour << 16); + } + + RTC_UNLOCK(); + WRITE_REG(RTC->TIME, tmp); + WRITE_REG(RTC->SSEC, time->sub_sec); + RTC_LOCK(); + + tmp = ald_get_tick(); + + while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) { + if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) + return TIMEOUT; + } + + return OK; +} + +/** + * @brief Set specified date. + * @param date: pointer to a rtc_date_t structure. + * @param format: Data format. + * @retval ALD status. + */ +ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format) +{ + uint32_t tmp; + + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) { + assert_param(IS_RTC_DAY(date->day)); + assert_param(IS_RTC_MONTH(date->month)); + assert_param(IS_RTC_YEAR(date->year)); + + tmp = (dec_to_bcd(date->day)) | + (dec_to_bcd(date->month) << 8) | + (dec_to_bcd(date->year) << 16) | + (dec_to_bcd(date->week) << 24); + } + else { + assert_param(IS_RTC_DAY(bcd_to_dec(date->day))); + assert_param(IS_RTC_MONTH(bcd_to_dec(date->month))); + assert_param(IS_RTC_YEAR(bcd_to_dec(date->year))); + + tmp = date->day | (date->month << 8) | + (date->year << 16) | (date->week << 24); + } + + RTC_UNLOCK(); + WRITE_REG(RTC->DATE, tmp); + RTC_LOCK(); + + tmp = ald_get_tick(); + + while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) { + if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) + return TIMEOUT; + } + + return OK; +} + +/** + * @brief Get current time. + * @param time: pointer to a rtc_time_t structure. + * @param format: Data format. + * @retval None + */ +void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format) +{ + uint32_t tmp; + + assert_param(time != NULL); + assert_param(IS_RTC_FORMAT(format)); + + time->sub_sec = RTC->SSEC & 0xFFFF; + tmp = RTC->TIME; + + if (format == RTC_FORMAT_DEC) { + time->second = bcd_to_dec(tmp & 0x7F); + time->minute = bcd_to_dec((tmp >> 8) & 0x7F); + time->hour = bcd_to_dec((tmp >> 16) & 0x7F); + } + else { + time->second = tmp & 0x7F; + time->minute = (tmp >> 8) & 0x7F; + time->hour = (tmp >> 16) & 0x7F; + } + + return; +} + +/** + * @brief Get current date. + * @param date: pointer to a rtc_date_t structure. + * @param format: Data format. + * @retval None + */ +void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format) +{ + uint32_t tmp = RTC->DATE; + + assert_param(date != NULL); + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) { + date->day = bcd_to_dec(tmp & 0x3F); + date->month = bcd_to_dec((tmp >> 8) & 0x1F); + date->year = bcd_to_dec((tmp >> 16) & 0xFF); + date->week = bcd_to_dec((tmp >> 24) & 0x7); + } + else { + date->day = tmp & 0x3F; + date->month = (tmp >> 8) & 0x1F; + date->year = (tmp >> 16) & 0xFF; + date->week = (tmp >> 24) & 0x7; + } + + return; +} + +/** + * @brief Get time and date consistency. + * @param date: pointer to a rtc_date_t structure. + * @param time: pointer to a rtc_time_t structure. + * @param format: Data format. + * @retval Status: + * 0 - Consistency + * -1 - Not consistency + */ +int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format) +{ + int32_t nr = 3; + rtc_date_t d_last; + rtc_time_t t_last; + + while (nr--) { + ald_rtc_get_time(&t_last, format); + ald_rtc_get_date(&d_last, format); + ald_rtc_get_time(time, format); + ald_rtc_get_date(date, format); + + if (rtc_consistency_check(&t_last, &d_last, time, date)) + return 0; + } + + return -1; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group3 Alarm functions + * @brief RTC alarm functions + * + * @verbatim + =============================================================================== + ##### Alarm functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the alarm use ald_rtc_set_alarm() function + (+) To read the alarm use ald_rtc_get_alarm() function + + @endverbatim + * @{ + */ + +/** + * @brief Set alarm. + * @param alarm: pointer to rtc_alarm_t struct. + * @param format: Data format. + * @retval None + */ +void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format) +{ + unsigned int tmp, ss_tmp; + + assert_param(IS_RTC_ALARM(alarm->idx)); + assert_param(IS_RTC_ALARM_SEL(alarm->sel)); + assert_param(IS_RTC_ALARM_SS_MASK(alarm->ss_mask)); + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) { + assert_param(IS_RTC_SECOND(alarm->time.second)); + assert_param(IS_RTC_MINUTE(alarm->time.minute)); + assert_param(IS_RTC_HOUR(alarm->time.hour)); + + tmp = (dec_to_bcd(alarm->time.second)) | + (dec_to_bcd(alarm->time.minute) << 8) | + (dec_to_bcd(alarm->time.hour) << 16) | + alarm->mask; + + if (alarm->sel == RTC_SELECT_DAY) { + assert_param(IS_RTC_DAY(alarm->day)); + + tmp |= (dec_to_bcd(alarm->day) << 24); + tmp &= 0x7FFFFFFF; /* Reset bit31 */ + } + else { + tmp |= (1 << (alarm->week + 24)); + tmp |= 0x80000000; /* Set bit31 */ + } + } + else { + assert_param(IS_RTC_SECOND(bcd_to_dec(alarm->time.second))); + assert_param(IS_RTC_MINUTE(bcd_to_dec(alarm->time.minute))); + assert_param(IS_RTC_HOUR(bcd_to_dec(alarm->time.hour))); + + tmp = alarm->time.second | + (alarm->time.minute << 8) | + (alarm->time.hour << 16) | + alarm->mask; + + if (alarm->sel == RTC_SELECT_DAY) { + assert_param(IS_RTC_DAY(bcd_to_dec(alarm->day))); + + tmp |= (alarm->day << 24); + tmp &= 0x7FFFFFFF; /* Reset bit31 */ + } + else { + tmp |= (1 << (alarm->week + 24)); + tmp |= 0x80000000; /* Set bit31 */ + } + } + + ss_tmp = (alarm->time.sub_sec & 0x7F) | + (alarm->ss_mask << 24); + + RTC_UNLOCK(); + + if (alarm->idx == RTC_ALARM_A) { + WRITE_REG(RTC->ALMA, tmp); + WRITE_REG(RTC->ALMASSEC, ss_tmp); + SET_BIT(RTC->CON, RTC_CON_ALMAEN_MSK); + } + else { + WRITE_REG(RTC->ALMB, tmp); + WRITE_REG(RTC->ALMBSSEC, ss_tmp); + SET_BIT(RTC->CON, RTC_CON_ALMBEN_MSK); + } + + RTC_LOCK(); + return; +} + +/** + * @brief Get alarm parameters. + * @param alarm: pointer to rtc_alarm_t struct. + * @param format: Data format. + * @retval None + */ +void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) +{ + uint8_t week; + uint32_t tmp, ss_tmp; + + assert_param(alarm != NULL); + assert_param(IS_RTC_FORMAT(format)); + + if (alarm->idx == RTC_ALARM_A) { + tmp = RTC->ALMA; + ss_tmp = RTC->ALMASSEC; + } + else { + tmp = RTC->ALMB; + ss_tmp = RTC->ALMBSSEC; + } + + if ((tmp >> 31) & 0x1) { + alarm->sel = RTC_SELECT_WEEK; + week = ((tmp >> 24) & 0x7F); + + switch (week) { + case 1: + alarm->week = 0; + break; + case 2: + alarm->week = 1; + break; + case 4: + alarm->week = 2; + break; + case 8: + alarm->week = 3; + break; + case 16: + alarm->week = 4; + break; + case 32: + alarm->week = 5; + break; + case 64: + alarm->week = 6; + break; + default: + break; + } + } + else { + alarm->sel = RTC_SELECT_DAY; + + if (format == RTC_FORMAT_DEC) + alarm->day = bcd_to_dec((tmp >> 24) & 0x3F); + else + alarm->day = (tmp >> 24) & 0x3F; + } + + if (format == RTC_FORMAT_DEC) { + alarm->time.second = bcd_to_dec(tmp & 0x7F); + alarm->time.minute = bcd_to_dec((tmp >> 8) & 0x7F); + alarm->time.hour = bcd_to_dec((tmp >> 16) & 0x3F); + } + else { + alarm->time.second = tmp & 0x7F; + alarm->time.minute = (tmp >> 8) & 0x7F; + alarm->time.hour = (tmp >> 16) & 0x3F; + } + + alarm->time.sub_sec = ss_tmp & 0x7FFF; + alarm->ss_mask = (rtc_sub_second_mask_t)((ss_tmp >> 24) & 0xF); + alarm->mask = tmp & ALARM_MASK_ALL; + + return; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group4 Time stamp functions + * @brief RTC time stamp functions + * + * @verbatim + =============================================================================== + ##### Time stamp functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the time stamp use ald_rtc_set_time_stamp() function + (+) To read the time stamp use ald_rtc_get_time_stamp() function + (+) To cancel the time stamp use ald_rtc_cancel_time_stamp() function + + @endverbatim + * @{ + */ + +/** + * @brief Set time stamp. + * @param sel: time stamp signal select: + * @arg RTC_TS_SIGNAL_SEL_TAMPER0 + * @arg RTC_TS_SIGNAL_SEL_TAMPER1 + * @param style: time stamp trigger style: + * @arg RTC_TS_RISING_EDGE + * @arg RTC_TS_FALLING_EDGE + * @retval None + */ +void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style) +{ + assert_param(IS_RTC_TS_SIGNAL(sel)); + assert_param(IS_RTC_TS_STYLE(style)); + + RTC_UNLOCK(); + + CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); + MODIFY_REG(RTC->CON, RTC_CON_TSSEL_MSK, style << RTC_CON_TSSEL_POS); + MODIFY_REG(RTC->CON, RTC_CON_TSPIN_MSK, sel << RTC_CON_TSPIN_POS); + SET_BIT(RTC->CON, RTC_CON_TSEN_MSK); + + RTC_LOCK(); + return; +} + +/** + * @brief Cancel time stamp. + * @retval None + */ +void ald_rtc_cancel_time_stamp(void) +{ + RTC_UNLOCK(); + CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); + RTC_LOCK(); + + return; +} + +/** + * @brief Get time stamp value. + * @param ts_time: pointer to rtc_time_t structure. + * @param ts_date: pointer to rtc_date_t structure. + * @param format: Data format. + * @retval None + */ +void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format) +{ + uint32_t tmp0, tmp1; + + assert_param(ts_time != NULL); + assert_param(ts_date != NULL); + assert_param(IS_RTC_FORMAT(format)); + + ts_time->sub_sec = RTC->TSSSEC & 0xFFFF; + tmp0 = RTC->TSTIME; + tmp1 = RTC->TSDATE; + + if (format == RTC_FORMAT_DEC) { + ts_time->second = bcd_to_dec(tmp0 & 0x7F); + ts_time->minute = bcd_to_dec((tmp0 >> 8) & 0x7F); + ts_time->hour = bcd_to_dec((tmp0 >> 16) & 0x3F); + ts_date->day = bcd_to_dec(tmp1 & 0x3F); + ts_date->month = bcd_to_dec((tmp1 >> 8) & 0x1F); + ts_date->year = bcd_to_dec((tmp1 >> 16) & 0xFF); + ts_date->week = bcd_to_dec((tmp1 >> 24) & 0x7); + } + else { + ts_time->second = tmp0 & 0x7F; + ts_time->minute = (tmp0 >> 8) & 0x7F; + ts_time->hour = (tmp0 >> 16) & 0x3F; + ts_date->day = tmp1 & 0x3F; + ts_date->month = (tmp1 >> 8) & 0x1F; + ts_date->year = (tmp1 >> 16) & 0xFF; + ts_date->week = (tmp1 >> 24) & 0x7; + } + + return; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group5 Tamper functions + * @brief RTC tamper functions + * + * @verbatim + =============================================================================== + ##### Tamper functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the tamper use ald_rtc_set_tamper() function + (+) To cancel the tamper use ald_rtc_alarm_cmd() function + + @endverbatim + * @{ + */ +/** + * @brief Set tamper parameters. + * @param tamper: pointer to rtc_tamper_t structure. + * @retval None + */ +void ald_rtc_set_tamper(rtc_tamper_t *tamper) +{ + assert_param(IS_RTC_TAMPER(tamper->idx)); + assert_param(IS_RTC_TAMPER_TRIGGER(tamper->trig)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(tamper->freq)); + assert_param(IS_RTC_TAMPER_DURATION(tamper->dur)); + assert_param(IS_FUNC_STATE(tamper->ts)); + + RTC_UNLOCK(); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPTS_MSK, tamper->ts << RTC_TAMPCON_TAMPTS_POS); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPCKS_MSK, tamper->freq << RTC_TAMPCON_TAMPCKS_POSS); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPFLT_MSK, tamper->dur << RTC_TAMPCON_TAMPFLT_POSS); + + if (tamper->idx == RTC_TAMPER_0) { + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP1LV_MSK, tamper->trig << RTC_TAMPCON_TAMP1LV_POS); + SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); + } + else { + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP2LV_MSK, tamper->trig << RTC_TAMPCON_TAMP2LV_POS); + SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK); + } + + RTC_LOCK(); + return; +} + +/** + * @brief Cancel tamper. + * @param idx: index of tamper: + * @arg RTC_TAMPER_0 + * @arg RTC_TAMPER_1 + * @retval None + */ +void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx) +{ + assert_param(IS_RTC_TAMPER(idx)); + + RTC_UNLOCK(); + + if (idx == RTC_TAMPER_0) + CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); + else + CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK); + + RTC_LOCK(); + return; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group6 Wake-up functions + * @brief RTC wake-up functions + * + * @verbatim + =============================================================================== + ##### Wake-up functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the wake-up parameters use ald_rtc_set_wakeup() function + (+) To read the re-load register value use ald_rtc_get_wakeup_timer_value() function + (+) To cancel the wake-up use ald_rtc_cancel_wakeup() function + + @endverbatim + * @{ + */ +/** + * @brief Set wake-up parameters. + * @param clock: pointer to rtc_wakeup_clock_t structure. + * @param value: re-load value. + * @retval None + */ +void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value) +{ + assert_param(IS_RTC_WAKEUP_CLOCK(clock)); + + RTC_UNLOCK(); + MODIFY_REG(RTC->CON, RTC_CON_WUCKS_MSK, clock << RTC_CON_WUCKS_POSS); + WRITE_REG(RTC->WUMAT, value & 0xFFFF); + SET_BIT(RTC->CON, RTC_CON_WUTE_MSK); + RTC_LOCK(); + + return; +} + +/** + * @brief Cancel wake-up. + * @retval None + */ +void ald_rtc_cancel_wakeup(void) +{ + RTC_UNLOCK(); + CLEAR_BIT(RTC->CON, RTC_CON_WUTE_MSK); + RTC_LOCK(); + + return; +} + +/** + * @brief Get wake-up re-load register value. + * @retval Value of re-load register. + */ +uint16_t ald_rtc_get_wakeup_timer_value(void) +{ + return RTC->WUMAT & 0xFFFF; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group7 Clock output functions + * @brief RTC clock output functions + * + * @verbatim + =============================================================================== + ##### Clock output functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the clock output type use ald_rtc_set_clock_output() function + (+) To cancel the clock output use ald_rtc_cancel_clock_output() function + + @endverbatim + * @{ + */ +/** + * @brief Set clock output parameters. + * @param clock: pointer to rtc_clock_output_t structure. + * @retval ALD status. + */ +ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock) +{ + uint32_t cnt = 4000; + assert_param(IS_RTC_CLOCK_OUTPUT(clock)); + + SYSCFG_UNLOCK(); + + if (clock == RTC_CLOCK_OUTPUT_EXA_1) { + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2LCKN_MSK)) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL2RDY_MSK))) && (--cnt)); + } + else { + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + } + + SYSCFG_LOCK(); + RTC_UNLOCK(); + MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, clock << RTC_CON_CKOS_POSS); + SET_BIT(RTC->CON, RTC_CON_CKOE_MSK); + RTC_LOCK(); + + return OK; +} + +/** + * @brief Cancel clock output. + * @retval None + */ +void ald_rtc_cancel_clock_output(void) +{ + RTC_UNLOCK(); + CLEAR_BIT(RTC->CON, RTC_CON_CKOE_MSK); + RTC_LOCK(); + + return; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group8 Control functions + * @brief RTC control functions + * + * @verbatim + =============================================================================== + ##### Control functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) Configure interrupt enable/disable. + (+) Enable/disable alarm. + (+) Configure rtc shift. + (+) Calibrate time. + (+) Get interrupt source status. + (+) Get interrupt flag status. + (+) Clear interrupt flag. + + @endverbatim + * @{ + */ +/** + * @brief Enable/disable the specified RTC interrupts. + * @param it: Specifies the RTC interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref rtc_it_t. + * @param state: New state of the specified RTC interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state) +{ + assert_param(IS_RTC_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + RTC_UNLOCK(); + + if (state == ENABLE) + SET_BIT(RTC->IER, it); + else + CLEAR_BIT(RTC->IER, it); + + RTC_LOCK(); + return; +} + +/** + * @brief Enable/Disable alarm. + * @param idx: index of alarm: + * @arg RTC_ALARM_A + * @arg RTC_ALARM_B + * @param state: New status of the specified alarm: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state) +{ + assert_param(IS_RTC_ALARM(idx)); + assert_param(IS_FUNC_STATE(state)); + + RTC_UNLOCK(); + + if (idx == RTC_ALARM_A) + MODIFY_REG(RTC->CON, RTC_CON_ALMAEN_MSK, state << RTC_CON_ALMAEN_POS); + else + MODIFY_REG(RTC->CON, RTC_CON_ALMBEN_MSK, state << RTC_CON_ALMBEN_POS); + + RTC_LOCK(); + return; +} + +/** + * @brief Set shift parameters. + * @param add_1s: Enable/Disable added 1 second. + * @param sub_ss: value of sub-sconde. + * @retval ALD status. + */ +ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss) +{ + uint32_t tick; + + assert_param(IS_FUNC_STATE(add_1s)); + assert_param(IS_SHIFT_SUB_SS(sub_ss)); + + RTC_UNLOCK(); + MODIFY_REG(RTC->SSECTR, RTC_SSECTR_TRIM_MSK, sub_ss << RTC_SSECTR_TRIM_POSS); + MODIFY_REG(RTC->SSECTR, RTC_SSECTR_INC_MSK, add_1s << RTC_SSECTR_INC_POS); + RTC_LOCK(); + + tick = ald_get_tick(); + + while (READ_BIT(RTC->CON, RTC_CON_SSEC_MSK)) { + if ((ald_get_tick() - tick) > RTC_TIMEOUT_VALUE) + return TIMEOUT; + } + + return OK; +} + +/** + * @brief Set calibation + * @param config: pointer to rtc_cali_t structure. + * @retval None + */ +void ald_rtc_set_cali(rtc_cali_t *config) +{ + assert_param(IS_RTC_CALI_FREQ(config->cali_freq)); + assert_param(IS_RTC_CALI_TC(config->tc)); + assert_param(IS_RTC_CALC_FREQ(config->calc_freq)); + assert_param(IS_RTC_CALI_CALC(config->calc)); + assert_param(IS_FUNC_STATE(config->acc)); + + RTC_UNLOCK(); + RTC_CALI_UNLOCK(); + + MODIFY_REG(RTC->CALCON, RTC_CALCON_CALP_MSK, config->cali_freq << RTC_CALCON_CALP_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, config->tc << RTC_CALCON_TCM_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCP_MSK, config->calc_freq << RTC_CALCON_TCP_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_ALG_MSK, config->calc << RTC_CALCON_ALG_POS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_DCMACC_MSK, config->acc << RTC_CALCON_DCMACC_POS); + SET_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); + + RTC_CALI_LOCK(); + RTC_LOCK(); + + return; +} + +/** + * @brief Cancel calibration + * @retval None + */ +void ald_rtc_cancel_cali(void) +{ + RTC_CALI_UNLOCK(); + CLEAR_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); + RTC_CALI_LOCK(); + + return; +} + +/** + * @brief Get calibration status. + * @retval ALD status. + */ +ald_status_t ald_rtc_get_cali_status(void) +{ + if (READ_BIT(RTC->CALCON, RTC_CALCON_ERR_MSK)) + return ERROR; + else + return OK; +} + +/** + * @brief Write temperature value. + * @param temp: the value of temperature. + * @retval None + */ +void ald_rtc_write_temp(uint16_t temp) +{ + RTC_CALI_UNLOCK(); + MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, temp << RTC_TEMPR_VAL_POSS); + RTC_CALI_LOCK(); + + return; +} + +/** + * @brief Get the status of RTC interrupt source. + * @param it: Specifies the RTC interrupt source. + * This parameter can be one of the @ref rtc_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_rtc_get_it_status(rtc_it_t it) +{ + assert_param(IS_RTC_IT(it)); + + if (READ_BIT(RTC->IER, it)) + return SET; + + return RESET; +} + +/** + * @brief Get the status of RTC interrupt flag. + * @param flag: Specifies the RTC interrupt flag. + * This parameter can be one of the @ref rtc_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag) +{ + assert_param(IS_RTC_IF(flag)); + + if (READ_BIT(RTC->IFR, flag)) + return SET; + + return RESET; +} + +/** @brief Clear the specified RTC pending flag. + * @param flag: specifies the flag to check. + * @retval None. + */ +void ald_rtc_clear_flag_status(rtc_flag_t flag) +{ + assert_param(IS_RTC_IF(flag)); + + RTC_UNLOCK(); + WRITE_REG(RTC->IFCR, flag); + RTC_LOCK(); + + return; +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_RTC */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtchw.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtchw.c new file mode 100644 index 0000000000000000000000000000000000000000..c423f657cb9a61d6db4e710b1b789eff9ccb209c --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_rtchw.c @@ -0,0 +1,207 @@ +/** + ****************************************************************************** + * @file ald_rtchw.c + * @brief RTCHW module driver. + * This file provides firmware functions to manage the following + * functionalities of the RTC peripheral: + * + Calibration functions + * @version V1.0 + * @date 25 Apr 2019 + * @author AE Team + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ******************************************************************************** + */ + +#include "ald_rtchw.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup RTCHW RTCHW + * @brief RTCHW module driver + * @{ + */ +#ifdef ALD_RTC + +/** @addtogroup RTCHW_Private_Functions RTCHW Private Functions + * @{ + */ +/** + * @brief delay losc clock + * @param u: clock numbers. + * @retval None. + */ +static void delay_losc_clk(uint16_t u) +{ + uint16_t i, j; + + for (i = 0; i < u; i++) { + for (j = 0; j < 60; j++) { + __ASM volatile ("nop"); + } + } +} + +/** + * @brief Check parameter for calibation + * @param config: pointer to rtc_hw_cali_offset_t structure. + * @param mode: Running mode, see @ref rtc_hw_cali_mode_t. + * @retval Status. + */ +static uint8_t rtc_hw_auto_check(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode) +{ + uint8_t tom = READ_BITS(TSENSE->CR, TSENSE_CR_TOM_MSK, TSENSE_CR_TOM_POSS); + uint8_t shift[8] = {0, 2, 4, 6, 8, 8, 8, 8}; + + if (mode == RTC_CALI_MODE_NORMAL) { + if ((RTC->CALCON & 0x1F3000F) != (RTCINFO->RTC_CALCR & 0x1F3000F)) + return 1; + } + else { + if ((RTC->CALCON & 0x183000F) != (RTCINFO->RTC_CALCR & 0x183000F)) + return 1; + + if (READ_BITS(RTC->CALCON, RTC_CALCON_TCP_MSK, RTC_CALCON_TCP_POSS) != 7) /* when sleep mode */ + return 1; + } + + if ((TSENSE->CR & 0x7702) != (RTCINFO->TEMP_CR & 0x7702)) + return 1; + if (RTC->TEMPBDR != RTCINFO->RTC_TEMPBDR + config->offset_rtc_bdr) + return 1; + if (RTC->LTAXR != RTCINFO->RTC_LTAXR + config->offset_ltaxr) + return 1; + if (RTC->HTAXR != RTCINFO->RTC_HTAXR + config->offset_htaxr) + return 1; + if (RTC->HTAXR != RTCINFO->RTC_HTCAR + config->offset_htcar) + return 1; + if (RTC->HTCBR != RTCINFO->RTC_HTCBR + config->offset_htcbr) + return 1; + if (RTC->HTCCR != RTCINFO->RTC_HTCCR + config->offset_htccr) + return 1; + if (RTC->HTCDR != RTCINFO->RTC_HTCDR + config->offset_htcdr) + return 1; + if (RTC->HTCER != RTCINFO->RTC_HTCER + config->offset_htcer) + return 1; + if (RTC->LTAXR != RTCINFO->RTC_LTCAR + config->offset_ltcar) + return 1; + if (RTC->LTCBR != RTCINFO->RTC_LTCBR + config->offset_ltcbr) + return 1; + if (RTC->LTCCR != RTCINFO->RTC_LTCCR + config->offset_ltccr) + return 1; + if (RTC->LTCDR != RTCINFO->RTC_LTCDR + config->offset_ltcdr) + return 1; + if (RTC->LTCER != RTCINFO->RTC_LTCER + config->offset_ltcer) + return 1; + if (TSENSE->TBDR != (RTCINFO->TEMP_TBDR & 0xFFFF) + config->offset_temp_bdr) + return 1; + if (TSENSE->LTGR != RTCINFO->TEMP_LTGR + config->offset_ltgr) + return 1; + if (TSENSE->HTGR != RTCINFO->TEMP_HTGR + config->offset_htgr) + return 1; + if (TSENSE->TCALBDR != (((RTCINFO->TEMP_TCALBDR & 0x1FFFFFF) >> shift[tom]) & 0x1FFFF) + + config->offset_tcalbdr) + return 1; + + return 0; +} +/** + * @} + */ + +/** @defgroup RTCHW_Public_Functions RTCHW Public Functions + * @{ + */ +/** + * @brief Hardware automatic calibate + * @param config: pointer to rtc_hw_cali_offset_t structure. + * @param mode: Running mode, see @ref rtc_hw_cali_mode_t + * @retval None + */ +void ald_rtc_hw_auto_cali(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode) +{ + uint8_t shift[8] = {0, 2, 4, 6, 8, 8, 8, 8}; + uint8_t tmp; + uint32_t v = 0; + uint16_t temp_calf; + + if (!(rtc_hw_auto_check(config, mode))) + return; + + RTC_UNLOCK(); + RTC_CALI_UNLOCK(); + TSENSE_UNLOCK(); + + temp_calf = (uint16_t)RTC->CALDR; + while ((READ_BITS(RTC->IFR, RTC_IFR_TCCF_MSK, RTC_IFR_TCCF_POS) == 1) && (v < 0x20000)) /* no usr trig */ + v++; + + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, 0 << RTC_CALCON_TCM_POSS); /* disable auto compensation */ + MODIFY_REG(TSENSE->CR, TSENSE_CR_REQEN_MSK, 0 << TSENSE_CR_REQEN_POS); /* disable temp */ + + RTC->CALDR = temp_calf; + delay_losc_clk(3); + + if (mode == RTC_CALI_MODE_NORMAL) { + v = RTC->CALCON & ~0x01F0000F; + RTC->CALCON = v | (RTCINFO->RTC_CALCR & 0x01F0000F); + } + else { + v = RTC->CALCON & ~0x0180000F; + RTC->CALCON = v | (RTCINFO->RTC_CALCR & 0x0180000F); + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCP_MSK, 7 << RTC_CALCON_TCP_POSS); // when sleep mode, caluate once in 1h + } + + RTC->TEMPBDR = RTCINFO->RTC_TEMPBDR + config->offset_rtc_bdr; + RTC->LTAXR = RTCINFO->RTC_LTAXR + config->offset_ltaxr; + RTC->HTAXR = RTCINFO->RTC_HTAXR + config->offset_htaxr; + RTC->LTCAR = RTCINFO->RTC_LTCAR + config->offset_ltcar; + RTC->LTCBR = RTCINFO->RTC_LTCBR + config->offset_ltcbr; + RTC->LTCCR = RTCINFO->RTC_LTCCR + config->offset_ltccr; + RTC->LTCDR = RTCINFO->RTC_LTCDR + config->offset_ltcdr; + RTC->LTCER = RTCINFO->RTC_LTCER + config->offset_ltcer; + RTC->HTCAR = RTCINFO->RTC_HTCAR + config->offset_htcar; + RTC->HTCBR = RTCINFO->RTC_HTCBR + config->offset_htcbr; + RTC->HTCCR = RTCINFO->RTC_HTCCR + config->offset_htccr; + RTC->HTCDR = RTCINFO->RTC_HTCDR + config->offset_htcdr; + RTC->HTCER = RTCINFO->RTC_HTCER + config->offset_htcer; + MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, 5 << RTC_CON_CKOS_POSS); /* output accuracy 1Hz */ + + v = TSENSE->CR & ~0x00007700; + TSENSE->CR = v | (RTCINFO->TEMP_CR & 0x00007700); + TSENSE->HTGR = RTCINFO->TEMP_HTGR + config->offset_htgr; + TSENSE->LTGR = RTCINFO->TEMP_LTGR + config->offset_ltgr; + tmp = READ_BITS(RTCINFO->TEMP_CR, TSENSE_CR_TOM_MSK, TSENSE_CR_TOM_POSS); + TSENSE->TCALBDR = ((RTCINFO->TEMP_TCALBDR & 0x1FFFFFF) >> shift[tmp]) + config->offset_tcalbdr; + TSENSE->TBDR = RTCINFO->TEMP_TBDR + config->offset_temp_bdr; + + delay_losc_clk(3); + tmp = READ_BITS(RTCINFO->TEMP_CR, TSENSE_CR_REQEN_MSK, TSENSE_CR_REQEN_POS); + MODIFY_REG(TSENSE->CR, TSENSE_CR_REQEN_MSK, tmp << TSENSE_CR_REQEN_POS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, 3 << RTC_CALCON_TCM_POSS); /* usr trig */ + + delay_losc_clk(3); + MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, 1 << RTC_TEMPR_VAL_POSS); /* trig immediate*/ + + delay_losc_clk(3); + tmp = READ_BITS(RTCINFO->RTC_CALCR, RTC_CALCON_TCM_MSK, RTC_CALCON_TCM_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, tmp << RTC_CALCON_TCM_POSS); + + RTC_CALI_LOCK(); + RTC_LOCK(); + TSENSE_LOCK(); + return; +} +/** + * @} + */ +#endif /* ALD_RTC */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..a2de0d5261367017359f1facefc0a9bd66b9a8e5 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_spi.c @@ -0,0 +1,1870 @@ +/** + ********************************************************************************* + * + * @file ald_spi.c + * @brief SPI module driver. + * This file provides firmware functions to manage the following + * functionalities of SPI peripheral: + * + Initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + * @version V1.0 + * @date 13 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI driver can be used as follows: + + (#) Declare a spi_handle_t structure, for example: + spi_handle_t hperh; + + (#) Initialize the SPI low level resources: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as push-pull + (##) NVIC configuration if you need to use interrupt process + by implementing the ald_mcu_irq_config() API. + Invoked ald_spi_irq_handler() function in SPI-IRQ function + (##) DMA Configuration if you need to use DMA process + (+++) Define ALD_DMA in ald_conf.h + (+++) Enable the DMAx clock + + (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI module by invoking the ald_spi_init() API. + + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the ald_spi_dma_pause()/ ald_spi_dma_stop(). + + * @endverbatim + */ + +#include "ald_spi.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI module driver + * @{ + */ +#ifdef ALD_SPI + +/** @addtogroup SPI_Private_Functions SPI Private Functions + * @{ + */ + +static ald_status_t spi_wait_status(spi_handle_t *hperh, spi_status_t state, flag_status_t status, uint32_t timeout); +static void __spi_send_by_it(spi_handle_t *hperh); +static void __spi_recv_by_it(spi_handle_t *hperh); +static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status); +#ifdef ALD_DMA +static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout); +static void spi_dma_send_cplt(void *arg); +static void spi_dma_recv_cplt(void *arg); +static void spi_dma_send_recv_cplt(void *arg); +#endif +/** + * @} + */ + +/** @defgroup SPI_Public_Functions SPI Public Functions + * @{ + */ + +/** @defgroup SPI_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + * @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + reset the SPIx peripheral: + + (+) User must configure all related peripherals resources + (CLOCK, GPIO, DMA, NVIC). + + (+) Call the function ald_spi_init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + + (+) Call the function ald_spi_reset() to reset the selected SPIx periperal. + + @endverbatim + * @{ + */ + +/** + * @brief Reset the SPI peripheral. + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +void ald_spi_reset(spi_handle_t *hperh) +{ + hperh->perh->CON1 = 0x0; + hperh->perh->CON2 = 0x0; + hperh->perh->CRCPOLY = 0x00000007; + + SPI_RESET_HANDLE_STATE(hperh); + __UNLOCK(hperh); + + return; +} + +/** + * @brief Initializes the SPI mode according to the specified parameters in + * the SPI_init_t and create the associated handle. + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_init(spi_handle_t *hperh) +{ + uint32_t tmp = 0; + + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_MODE(hperh->init.mode)); + assert_param(IS_SPI_DIRECTION(hperh->init.dir)); + assert_param(IS_SPI_BAUD(hperh->init.baud)); + assert_param(IS_SPI_FIRBIT(hperh->init.first_bit)); + assert_param(IS_FUNC_STATE(hperh->init.ss_en)); + assert_param(IS_FUNC_STATE(hperh->init.crc_calc)); + assert_param(IS_SPI_DATASIZE(hperh->init.data_size)); + assert_param(IS_SPI_CPHA(hperh->init.phase)); + assert_param(IS_SPI_CPOL(hperh->init.polarity)); + assert_param(IS_SPI_FRAME(hperh->init.frame)); + + if (hperh == NULL) + return ERROR; + + ald_spi_reset(hperh); + + tmp = hperh->perh->CON1; + + if (hperh->init.mode == SPI_MODE_MASTER) + tmp |= 1 << SPI_CON1_SSOUT_POS; + + tmp |= ((hperh->init.phase << SPI_CON1_CPHA_POS) | (hperh->init.polarity << SPI_CON1_CPOL_POS) | + (hperh->init.baud << SPI_CON1_BAUD_POSS) | (hperh->init.data_size << SPI_CON1_FLEN_POS) | + (hperh->init.mode << SPI_CON1_MSTREN_POS) | (hperh->init.ss_en << SPI_CON1_SSEN_POS) | + (hperh->init.first_bit << SPI_CON1_LSBFST_POS)); + + hperh->perh->CON1 = tmp; + + MODIFY_REG(hperh->perh->CON2, SPI_CON2_FRF_MSK, hperh->init.frame << SPI_CON2_FRF_POS); + + if (hperh->init.dir == SPI_DIRECTION_2LINES) { + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); + } + else if (hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) { + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + SET_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); + } + else if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) { + SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDOEN_MSK); + } + else { + SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + SET_BIT(hperh->perh->CON1, SPI_CON1_BIDOEN_MSK); + } + + /* configure CRC */ + hperh->perh->CON1 |= (hperh->init.crc_calc << SPI_CON1_CRCEN_POS); + hperh->perh->CRCPOLY = hperh->init.crc_poly; + + hperh->err_code = SPI_ERROR_NONE; + hperh->state = SPI_STATE_READY; + + if (hperh->init.dir == SPI_DIRECTION_2LINES) + SPI_ENABLE(hperh); + + return OK; +} + +/** + * @brief Config the fifo threshold + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @param threshold: The threshold value of fifo. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t spi_fifo_threshold_config(spi_handle_t *hperh, uint8_t threshold) +{ + assert_param(IS_SPI(hperh->perh)); + + MODIFY_REG(hperh->perh->CON2, SPI_CON2_RXFTH_MSK, threshold << SPI_CON2_RXFTH_POSS); + MODIFY_REG(hperh->perh->CON2, SPI_CON2_TXFTH_MSK, threshold << SPI_CON2_TXFTH_POSS); + + return OK; +} +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group2 IO operation functions + * @brief SPI Transmit and Receive functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master or slave mode: + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The ALD status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the ALD status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() and hperh->tx_rx_cplt_cbk() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The hperh->err_cbk() user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + + * @endverbatim + * @{ + */ + +/** + * @brief Transmit one byte fast in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param data: Data to be sent + * @retval status: + * - 0 Success + * - -1 Failed + */ +int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data) +{ + uint16_t cnt = 5000, temp; + + hperh->perh->DATA = data; + while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt)); + + cnt = 5000; + while (((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) && (--cnt)); + temp = hperh->perh->DATA; + UNUSED(temp); + + return cnt == 0 ? -1 : 0; +} + +/** + * @brief Transmit one byte fast in blocking mode(1line). + * @param hperh: Pointer to a spi_handle_t structure. + * @param data: Data to be sent + * @retval status: + * - 0 Success + * - -1 Failed + */ +int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data) +{ + uint16_t cnt = 5000; + + hperh->perh->DATA = data; + while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt)); + + return cnt == 0 ? -1 : 0; +} + +/** + * @brief Receive one byte fast in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param status: Status, success[0]/failed[-1] + * @retval Data. + */ +uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh, int *status) +{ + uint16_t cnt = 5000; + + if (hperh->init.mode == SPI_MODE_MASTER) { + hperh->perh->DATA = 0xFF; + while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt)); + } + + cnt = 5000; + while (((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) && (--cnt)); + *status = cnt == 0 ? - 1 : 0; + + return (uint8_t)hperh->perh->DATA; +} + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + + hperh->state = SPI_STATE_BUSY_TX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + if (hperh->init.dir == SPI_DIRECTION_1LINE) + SPI_1LINE_TX(hperh); + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) + SPI_ENABLE(hperh); + + if ((hperh->init.mode == SPI_MODE_SLAVER) || (hperh->tx_count == 1)) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *((volatile uint8_t *)hperh->perh + 0x0c) = *hperh->tx_buf; + ++hperh->tx_buf; + --hperh->tx_count; + } + else { + hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); + hperh->tx_buf += 2; + --hperh->tx_count; + } + } + + while (hperh->tx_count > 0) { + if (spi_wait_status(hperh, SPI_STATUS_TXE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *((volatile uint8_t *)hperh->perh + 0x0c) = *hperh->tx_buf; + ++hperh->tx_buf; + --hperh->tx_count; + } + else { + hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); + hperh->tx_buf += 2; + --hperh->tx_count; + } + } + + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + + if ((spi_wait_status(hperh, SPI_STATUS_TXE, SET, timeout) != OK) + || (spi_wait_status(hperh, SPI_STATUS_BUSY, RESET, timeout) != OK)) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + uint16_t temp; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) + SPI_1LINE_RX(hperh); + + if ((hperh->init.mode == SPI_MODE_MASTER) && (hperh->init.dir == SPI_DIRECTION_2LINES)) { + __UNLOCK(hperh); + hperh->state = SPI_STATE_READY; + return ald_spi_send_recv(hperh, buf, buf, size, timeout); + } + + if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) + SPI_ENABLE(hperh); + + if (hperh->rx_count > 0) { + if (hperh->init.data_size <= SPI_DATA_SIZE_8) { + *((uint8_t *)&(hperh->perh->DATA)) = 0xB1; + } + else { + *((uint16_t *)&(hperh->perh->DATA)) = 0xB2B1; + } + } + while (hperh->rx_count > 0) { + if (hperh->rx_count > 1) { + if (hperh->init.data_size <= SPI_DATA_SIZE_8) { + *((uint8_t *)&(hperh->perh->DATA)) = 0xB1; + } + else { + *((uint16_t *)&(hperh->perh->DATA)) = 0xB2B1; + } + } + + if (spi_wait_status(hperh, SPI_STATUS_RXE, RESET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if ((hperh->init.crc_calc == ENABLE) && (READ_BIT(hperh->perh->CON1, SPI_CON1_NXTCRC_MSK) == 0)) { + ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, ENABLE); + SET_BIT(hperh->perh->CON1, SPI_CON1_NXTCRC_MSK); + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + --hperh->rx_count; + } + } + + if (spi_wait_status(hperh, SPI_STATUS_RXE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + --hperh->rx_count; + } + + if (hperh->init.crc_calc) { + if (spi_wait_status(hperh, SPI_STATUS_RXTH, RESET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { + hperh->err_code |= SPI_ERROR_CRC; + SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return ERROR; + } + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). + * @param hperh: Pointer to a spi_handle_t structure. + * @param tx_buf: Pointer to data transmitted buffer + * @param rx_buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) +{ + uint16_t temp; + + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (hperh->init.dir != SPI_DIRECTION_2LINES) + return ERROR; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if (hperh->init.mode == SPI_MODE_SLAVER) { + if (spi_wait_status(hperh, SPI_STATUS_TXE, SET, timeout) != OK) { + SPI_DISABLE(hperh); + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size <= SPI_DATA_SIZE_8) { + *((volatile uint8_t *)hperh->perh + 0x0c) = *hperh->tx_buf; + ++hperh->tx_buf; + --hperh->tx_count; + } + else { + hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); + hperh->tx_buf += 2; + --hperh->tx_count; + } + } + + if (hperh->tx_buf == 0) { + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + + if (spi_wait_status(hperh, SPI_STATUS_RXE, RESET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else { + (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; + hperh->rx_buf += 2; + --hperh->rx_count; + } + } + + while (hperh->tx_count > 0) { + if (spi_wait_status(hperh, SPI_STATUS_TXE, SET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *((volatile uint8_t *)hperh->perh + 0x0c) = *hperh->tx_buf; + ++hperh->tx_buf; + --hperh->tx_count; + } + else { + hperh->perh->DATA = (*(uint16_t *)hperh->tx_buf); + hperh->tx_buf += 2; + --hperh->tx_count; + } + + if (spi_wait_status(hperh, SPI_STATUS_RXE, RESET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else { + (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; + + hperh->rx_buf += 2; + --hperh->rx_count; + } + } + + if (hperh->init.mode == SPI_MODE_SLAVER) { + if (spi_wait_status(hperh, SPI_STATUS_RXE, RESET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + --hperh->rx_count; + } + else { + (*(uint16_t *)hperh->rx_buf) = hperh->perh->DATA; + + hperh->rx_buf += 2; + --hperh->rx_count; + } + } + + if (hperh->init.crc_calc) { + SPI_CRCNEXT_ENABLE(hperh); + + if (spi_wait_status(hperh, SPI_STATUS_TXE, SET, timeout) != OK) { + SPI_DISABLE(hperh); + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if (spi_wait_status(hperh, SPI_STATUS_RXE, RESET, timeout) != OK) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if ((spi_wait_status(hperh, SPI_STATUS_BUSY, RESET, timeout) != OK)) { + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + return TIMEOUT; + } + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { + hperh->err_code |= SPI_ERROR_CRC; + SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + + return ERROR; + } + + hperh->state = SPI_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param hperh: pointer to a spi_handle_t structure. + * @param buf: Pointer to data transmitted buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + __UNLOCK(hperh); + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if (hperh->init.dir == SPI_DIRECTION_1LINE) + SPI_1LINE_TX(hperh); + + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) + SPI_ENABLE(hperh); + + ald_spi_interrupt_config(hperh, SPI_IT_TXE, ENABLE); + + return OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + __UNLOCK(hperh); + + if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) + SPI_1LINE_RX(hperh); + + if (hperh->init.crc_calc == ENABLE) { + SPI_CRC_RESET(hperh); + ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, ENABLE); + } + + ald_spi_interrupt_config(hperh, SPI_IT_RXTH, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_MODF, ENABLE); + + if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) + SPI_ENABLE(hperh); + + if (hperh->init.data_size <= SPI_DATA_SIZE_8) { + *((uint8_t *)&(hperh->perh->DATA)) = 0xB1; + } + else { + *((uint16_t *)&(hperh->perh->DATA)) = 0xB2B1; + } + + return OK; +} + +/** + * @brief Transmit and Receives an amount of data in non blocking mode + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @param tx_buf: Pointer to data transmitted buffer + * @param rx_buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + __UNLOCK(hperh); + + if (hperh->init.crc_calc) { + SPI_CRC_RESET(hperh); + ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, ENABLE); + } + + if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) + SPI_ENABLE(hperh); + + ald_spi_interrupt_config(hperh, SPI_IT_RXTH, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_MODF, ENABLE); + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Transmit an amount of data used dma channel + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as SPI transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + if (hperh->init.dir == SPI_DIRECTION_1LINE) + SPI_1LINE_TX(hperh); + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.cplt_cbk = spi_dma_send_cplt; + + /* Configure SPI DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = channel; + hperh->hdmatx.config.burst = ENABLE; + ald_dma_config_basic(&(hperh->hdmatx)); + + __UNLOCK(hperh); + + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) + SPI_ENABLE(hperh); + + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + + return OK; +} + +/** + * @brief Receive an amount of data used dma channel + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as SPI transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + uint16_t tmp_rx = 0xB1B2; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) + SPI_1LINE_RX(hperh); + if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) { + __UNLOCK(hperh); + return ERROR; + } + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.cplt_cbk = spi_dma_recv_cplt; + + /* Configure SPI DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)&tmp_rx; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.channel = 11; + ald_dma_config_basic(&(hperh->hdmatx)); + + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;; + hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&(hperh->hdmarx)); + + __UNLOCK(hperh); + + if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) + SPI_ENABLE(hperh); + + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + + return OK; +} + +/** + * @brief Transmit and Receive an amount of data used dma channel + * @param hperh: Pointer to a spi_handle_t structure. + * @param tx_buf: Pointer to data buffer + * @param rx_buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param tx_channel: DMA channel as SPI transmit + * @param rx_channel: DMA channel as SPI receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY && hperh->state != SPI_STATE_BUSY_RX) + return BUSY; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmatx.cplt_arg = NULL; + hperh->hdmatx.cplt_cbk = NULL; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.cplt_cbk = spi_dma_send_recv_cplt; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + /* Configure SPI DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)tx_buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.channel = tx_channel; + ald_dma_config_basic(&(hperh->hdmatx)); + + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)rx_buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;; + hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; + hperh->hdmarx.config.burst = ENABLE; + hperh->hdmarx.config.channel = rx_channel; + ald_dma_config_basic(&(hperh->hdmarx)); + + __UNLOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + + return OK; +} + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status + */ +ald_status_t ald_spi_dma_pause(spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + + __LOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status + */ +ald_status_t ald_spi_dma_resume(spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + + __LOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status + */ +ald_status_t ald_spi_dma_stop(spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + + __LOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + __UNLOCK(hperh); + + hperh->state = SPI_STATE_READY; + return OK; +} +#endif +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group3 Control functions + * @brief SPI Control functions + * + * @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) Handle interrupt about SPI module. The ald_spi_irq_handler() function must + be invoked by SPI-IRQ function. + (+) Configure the interrupt DISABLE/ENABLE. + (+) Configure the DMA request. + (+) Get interrupt source status. + (+) Get interrupt flag status. + (+) Clear interrupt flag + + @endverbatim + * @{ + */ + +/** + * @brief This function handles SPI interrupt request. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval None + */ +void ald_spi_irq_handler(spi_handle_t *hperh) +{ + if ((hperh->state == SPI_STATE_BUSY_RX) || (hperh->state == SPI_STATE_BUSY_TX)) { + if ((ald_spi_get_it_status(hperh, SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXTH) != RESET)) + __spi_recv_by_it(hperh); + + if ((ald_spi_get_it_status(hperh, SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXE) != RESET)) + __spi_send_by_it(hperh); + } + + else if (hperh->state == SPI_STATE_BUSY_TX_RX) { + if (hperh->init.mode == SPI_MODE_SLAVER) { + if ((ald_spi_get_it_status(hperh, SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXE) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_TXE); + if ((ald_spi_get_it_status(hperh, SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXTH) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_RXNE); + } + else { + if (hperh->rx_size == hperh->tx_count) { + if ((ald_spi_get_it_status(hperh, SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXE) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_TXE); + } + else { + if ((ald_spi_get_it_status(hperh, SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXE) != RESET) + && (ald_spi_get_it_status(hperh, SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXTH) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_TXE_RXNE); + } + } + + } + + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) { + hperh->err_code |= SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + } + if (ald_spi_get_flag_status(hperh, SPI_IF_MODF) != RESET) { + hperh->err_code |= SPI_ERROR_MODF; + ald_spi_clear_flag_status(hperh, SPI_IF_MODF); + } + if (ald_spi_get_flag_status(hperh, SPI_IF_FRE) != RESET) { + hperh->err_code |= SPI_ERROR_FRE; + ald_spi_clear_flag_status(hperh, SPI_IF_FRE); + + } + if (ald_spi_get_flag_status(hperh, SPI_IF_TXOV) != RESET) { + if (hperh->state != SPI_STATE_BUSY_TX) { + hperh->err_code |= SPI_ERROR_TXOV; + ald_spi_clear_flag_status(hperh, SPI_IF_TXOV); + } + } + if (ald_spi_get_flag_status(hperh, SPI_IF_RXOV) != RESET) { + if (hperh->state != SPI_STATE_BUSY_RX) { + hperh->err_code |= SPI_ERROR_RXOV; + ald_spi_clear_flag_status(hperh, SPI_IF_RXOV); + } + } + + return; +} + +/** + * @brief Enables or disables the specified SPI interrupts. + * @param hperh: Pointer to a spi_handle_t structure. + * @param it: Specifies the SPI interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref spi_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IER |= (uint32_t)it; + else + hperh->perh->IDR |= (uint32_t)it; + + return; +} + +/** + * @brief Configure the specified SPI speed. + * @param hperh: Pointer to a spi_handle_t structure. + * @param speed: Specifies the SPI speed. + * This parameter can be one of the @ref spi_baud_t. + * @retval None + */ +void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed) +{ + uint32_t tmp = 0; + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_BAUD(speed)); + + tmp = hperh->perh->CON1; + tmp &= ~(0x7 << SPI_CON1_BAUD_POSS); + tmp |= (speed << SPI_CON1_BAUD_POSS); + hperh->perh->CON1 = tmp; + return; +} + +/** + * @brief Enables or disables the dma request. + * @param hperh: Pointer to a spi_handle_t structure. + * @param req: Specifies the SPI dma request sources to be enabled or disabled. + * This parameter can be one of the @ref spi_dma_req_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) { + if (req == SPI_DMA_REQ_TX) + SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + else { + if (req == SPI_DMA_REQ_TX) + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + + return; +} + +/** @brief Check whether the specified SPI state flag is set or not. + * @param hperh: Pointer to a spi_handle_t structure. + * @param status: specifies the flag to check. + * This parameter can be one of the @ref spi_status_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_STATUS(status)); + + if (hperh->perh->STAT & status) + return SET; + + return RESET; +} + +/** + * @brief This function handles SPI communication timeout. + * @param hperh: Pointer to a spi_handle_t structure. + * @param state: specifies the SPI flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t spi_wait_status(spi_handle_t *hperh, spi_status_t state, flag_status_t status, uint32_t timeout) +{ + uint32_t tick = ald_get_tick(); + + assert_param(timeout > 0); + + while ((spi_get_status(hperh, state)) != status) { + if (((ald_get_tick()) - tick) > timeout) { + ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_MODF, DISABLE); + return TIMEOUT; + } + } + + return OK; +} + +/** + * @brief Checks whether the specified SPI interrupt has occurred or not. + * @param hperh: Pointer to a spi_handle_t structure. + * @param it: Specifies the SPI interrupt source to check. + * This parameter can be one of the @ref spi_it_t. + * @retval Status + * - SET + * - RESET + */ +it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IT(it)); + + if (hperh->perh->IVS & it) + return SET; + + return RESET; +} + +/** @brief Check whether the specified SPI flag is set or not. + * @param hperh: Pointer to a spi_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref spi_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IF(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** @brief Clear the specified SPI pending flags. + * @param hperh: Pointer to a spi_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref spi_flag_t. + * @retval None + */ +void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IF(flag)); + + + hperh->perh->ICR |= flag; + return; +} + +#ifdef ALD_DMA +/** + * @brief This function handles SPI communication timeout in interrupt function. + * @param hperh: Pointer to a spi_handle_t structure. + * @param flag: specifies the SPI flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout) +{ + assert_param(timeout > 0); + + while (((ald_spi_get_flag_status(hperh, flag)) != status) && (--timeout)); + + if (timeout) + return OK; + + ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_MODF, DISABLE); + + return TIMEOUT; +} +#endif + +static ald_status_t spi_wait_bsy_flag(spi_handle_t *hperh, flag_status_t status, uint32_t timeout) +{ + uint32_t tick = ald_get_tick(); + + assert_param(timeout > 0); + + while ((READ_BIT(hperh->perh->STAT, SPI_STAT_BUSY_MSK)) && (--timeout)); + + if (timeout) + return OK; + + ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_MODF, DISABLE); + + return TIMEOUT; +} + +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group4 Peripheral State and Errors functions + * @brief SPI State and Errors functions + * + * @verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) ald_spi_get_state() API can check in run-time the state of the SPI peripheral + (+) ald_spi_get_error() check in run-time Errors occurring during communication + + @endverbatim + * @{ + */ + +/** + * @brief Returns the SPI state. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval ALD state + */ +spi_state_t ald_spi_get_state(spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + return hperh->state; +} + +/** + * @brief Return the SPI error code + * @param hperh: Pointer to a spi_handle_t structure. + * @retval SPI Error Code + */ +uint32_t ald_spi_get_error(spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + return hperh->err_code; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Functions SPI Private Functions + * @brief SPI Private functions + * @{ + */ + +/** + * @brief handle program when an tx empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static void __spi_send_by_it(spi_handle_t *hperh) +{ + if (hperh->tx_count == 0) { + ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE); + hperh->state = SPI_STATE_READY; + + if (hperh->init.dir == SPI_DIRECTION_2LINES) { + ald_spi_clear_flag_status(hperh, SPI_IF_TXOV); + } + + if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != OK) { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return; + } + + ald_spi_clear_flag_status(hperh, SPI_IF_TXE); + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *((volatile uint8_t *)hperh->perh + 0x0c) = *hperh->tx_buf; + ++hperh->tx_buf; + } + else { + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + --hperh->tx_count; + + if (hperh->tx_count == 0) { + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + } + + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static void __spi_recv_by_it(spi_handle_t *hperh) +{ + uint16_t temp; + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + } + + ald_spi_clear_flag_status(hperh, SPI_IF_RXTH); + --hperh->rx_count; + + if (hperh->rx_count == 0) { + ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE); + hperh->state = SPI_STATE_READY; + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { + hperh->err_code |= SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->init.crc_calc) { + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + if (hperh->init.data_size <= SPI_DATA_SIZE_8) { + *((uint8_t *)&(hperh->perh->DATA)) = 0xB1; + } + else { + *((uint16_t *)&(hperh->perh->DATA)) = 0xB2B1; + } + + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode(2 lines) + * @param hperh: Pointer to a spi_handle_t structure. + * @param status: SR.TXE or SR.RXNE set. + * @retval Status, see @ref ald_status_t. + */ +static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status) +{ + if (hperh->rx_count != 0) { + if ((status == SPI_SR_RXNE) || (status == SPI_SR_TXE_RXNE)) { + ald_spi_clear_flag_status(hperh, SPI_IF_RXTH); + while (spi_get_status(hperh, SPI_STATUS_RXTH) != RESET) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + } + --hperh->rx_count; + } + + if ((hperh->rx_count == 0xffff) && (hperh->init.crc_calc == ENABLE)) + hperh->rx_count = 0; + } + } + + if (hperh->tx_count != 0) { + if ((status == SPI_SR_TXE) || (status == SPI_SR_TXE_RXNE)) { + ald_spi_clear_flag_status(hperh, SPI_IF_TXE); + if (hperh->tx_count == 1) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *((volatile uint8_t *)hperh->perh + 0x0c) = *hperh->tx_buf; + ++hperh->tx_buf; + } + else { + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + + --hperh->tx_count; + + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + } + else { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *((volatile uint8_t *)hperh->perh + 0x0c) = *hperh->tx_buf; + ++hperh->tx_buf; + } + else { + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + + if (--hperh->tx_count == 0) { + if (hperh->init.crc_calc) + SPI_CRCNEXT_ENABLE(hperh); + ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE); + } + } + } + } + + if (hperh->rx_count == 0) { + ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_MODF, DISABLE); + hperh->state = SPI_STATE_READY; + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { + hperh->err_code |= SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->tx_rx_cplt_cbk) + hperh->tx_rx_cplt_cbk(hperh); + } + + return; +} + + +#ifdef ALD_DMA +/** + * @brief DMA SPI transmit process complete callback. + * @param arg: Pointer to a spi_handle_t structure. + * @retval None + */ +static void spi_dma_send_cplt(void *arg) +{ + uint16_t delay; + spi_handle_t *hperh = (spi_handle_t *)arg; + + hperh->tx_count = 0; + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + hperh->state = SPI_STATE_READY; + + if (hperh->init.dir == SPI_DIRECTION_2LINES) + ald_spi_clear_flag_status(hperh, SPI_IF_TXOV); + + if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + for (delay = 0; delay < 3000; delay++); + + if (hperh->err_code == SPI_ERROR_NONE) { + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA SPI receive process complete callback. + * @param arg: Pointer to a spi_handle_t structure. + * @retval None + */ +static void spi_dma_recv_cplt(void *arg) +{ + uint32_t tmp; + spi_handle_t *hperh = (spi_handle_t *)arg; + + hperh->rx_count = 0; + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + hperh->state = SPI_STATE_READY; + + if (hperh->init.crc_calc) { + if ((spi_wait_flag_irq(hperh, SPI_IF_RXTH, SET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + tmp = hperh->perh->DATA; + UNUSED(tmp); + + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) { + SET_BIT(hperh->err_code, SPI_ERROR_CRC); + SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + } + } + + if (hperh->err_code == SPI_ERROR_NONE) { + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA SPI transmit and receive process complete callback. + * @param arg: Pointer to a SPI_handle_t structure. + * @retval None + */ +static void spi_dma_send_recv_cplt(void *arg) +{ + uint32_t tmp; + uint16_t delay; + spi_handle_t *hperh = (spi_handle_t *)arg; + + if (hperh->init.crc_calc) { + if ((spi_wait_flag_irq(hperh, SPI_IF_RXTH, SET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + tmp = hperh->perh->DATA; + UNUSED(tmp); + + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) { + SET_BIT(hperh->err_code, SPI_ERROR_CRC); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + } + } + + if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + for (delay = 0; delay < 3000; delay++); + + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + hperh->tx_count = 0; + hperh->rx_count = 0; + hperh->state = SPI_STATE_READY; + + if (hperh->err_code == SPI_ERROR_NONE) { + if (hperh->tx_rx_cplt_cbk) + hperh->tx_rx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +#endif /* ALD_DMA */ +/** + * @} + */ +#endif /* ALD_SPI */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_sram.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_sram.c new file mode 100644 index 0000000000000000000000000000000000000000..31f749167996b374e95e6acb7e095a8e899d6808 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_sram.c @@ -0,0 +1,381 @@ +/** + ********************************************************************************* + * + * @file ald_sram.c + * @brief SRAM module driver. + * + * @version V1.0 + * @date 25 Dec 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ +#include "ald_sram.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup SRAM SRAM + * @brief SRAM module driver + * @{ + */ + +#ifdef ALD_SRAM + +/** @defgroup SRAM_Public_Functions SRAM Public Functions + * @{ + */ +/** @defgroup SRAM_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * @{ + */ +/** + * @brief Performs the SRAM device initialization sequence + * @param hperh: pointer to a sram_handle_t structure + * @param timing: Pointer to SRAM control timing structure + * @param ext_timing: Pointer to SRAM extended mode timing structure + * @retval ald status + */ +ald_status_t ald_sram_init(sram_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing) +{ + if (hperh == NULL) + return ERROR; + + if (hperh->state == ALD_SRAM_STATE_RESET) + hperh->lock = UNLOCK; + + /* Initialize SRAM control Interface */ + ald_ebi_nor_sram_init(hperh->instance, &(hperh->init)); + /* Initialize SRAM timing Interface */ + ald_ebi_nor_sram_timing_init(hperh->instance, timing, hperh->init.bank); + /* Initialize SRAM extended mode timing Interface */ + ald_ebi_nor_sram_ext_timing_init(hperh->ext, ext_timing, hperh->init.bank, hperh->init.ext_mode); + /* Enable the NORSRAM device */ + ald_ebi_nor_sram_enable(hperh->instance, hperh->init.bank); + + return OK; +} + +/** + * @brief Performs the SRAM device De-initialization sequence. + * @param hperh: pointer to a sram_handle_t structure + * @retval ald status + */ +ald_status_t ald_sram_deinit(sram_handle_t *hperh) +{ + ald_ebi_nor_sram_deinit(hperh->instance, hperh->ext, hperh->init.bank); + hperh->state = ALD_SRAM_STATE_RESET; + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup SRAM_Public_Functions_Group2 I/O operation functions + * @brief I/O operation functions + * @{ + */ +/** + * @brief Reads 8-bit buffer from SRAM memory. + * @param hperh: pointer to a sram_handle_t structure + * @param addr: Pointer to read start address + * @param buf: Pointer to destination buffer + * @param size: Size of the buffer to read from memory + * @retval ald status + */ +ald_status_t ald_sram_read_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size) +{ + __IO uint8_t * psramaddr = (uint8_t *)addr; + + __LOCK(hperh); + hperh->state = ALD_SRAM_STATE_BUSY; + + /* Read data from memory */ + for (; size != 0U; size--) + *buf++ = *(__IO uint8_t *)psramaddr++; + + hperh->state = ALD_SRAM_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Writes 8-bit buffer to SRAM memory. + * @param hperh: pointer to a sram_handle_t structure + * @param addr: Pointer to write start address + * @param buf: Pointer to source buffer to write + * @param size: Size of the buffer to write to memory + * @retval ald status + */ +ald_status_t ald_sram_write_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size) +{ + __IO uint8_t * psramaddr = (uint8_t *)addr; + + if (hperh->state == ALD_SRAM_STATE_PROTECTED) + return ERROR; + + __LOCK(hperh); + hperh->state = ALD_SRAM_STATE_BUSY; + + /* Write data to memory */ + for (; size != 0U; size--) + *(__IO uint8_t *)psramaddr++ = *buf++; + + hperh->state = ALD_SRAM_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Reads 16-bit buffer from SRAM memory. + * @param hperh: pointer to a sram_handle_t structure that contains + * the configuration information for SRAM module. + * @param addr: Pointer to read start address + * @param buf: Pointer to destination buffer + * @param size: Size of the buffer to read from memory + * @retval ald status + */ +ald_status_t ald_sram_read_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size) +{ + __IO uint16_t * psramaddr = (uint16_t *)addr; + + __LOCK(hperh); + hperh->state = ALD_SRAM_STATE_BUSY; + + /* Read data from memory */ + for (; size != 0U; size--) + *buf++ = *(__IO uint16_t *)psramaddr++; + + hperh->state = ALD_SRAM_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Writes 16-bit buffer to SRAM memory. + * @param hperh: pointer to a sram_handle_t structure that contains + * the configuration information for SRAM module. + * @param addr: Pointer to write start address + * @param buf: Pointer to source buffer to write + * @param size: Size of the buffer to write to memory + * @retval ald status + */ +ald_status_t ald_sram_write_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size) +{ + __IO uint16_t * psramaddr = (uint16_t *)addr; + + if (hperh->state == ALD_SRAM_STATE_PROTECTED) + return ERROR; + + __LOCK(hperh); + hperh->state = ALD_SRAM_STATE_BUSY; + + /* Write data to memory */ + for (; size != 0U; size--) + *(__IO uint16_t *)psramaddr++ = *buf++; + + hperh->state = ALD_SRAM_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Reads 32-bit buffer from SRAM memory. + * @param hperh: pointer to a sram_handle_t structure + * @param addr: Pointer to read start address + * @param buf: Pointer to destination buffer + * @param size: Size of the buffer to read from memory + * @retval ald status + */ +ald_status_t ald_sram_read_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size) +{ + __LOCK(hperh); + hperh->state = ALD_SRAM_STATE_BUSY; + + /* Read data from memory */ + for (; size != 0U; size--) + *buf++ = *(__IO uint32_t *)addr++; + + hperh->state = ALD_SRAM_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Writes 32-bit buffer to SRAM memory. + * @param hperh: pointer to a sram_handle_t structure that contains + * the configuration information for SRAM module. + * @param addr: Pointer to write start address + * @param buf: Pointer to source buffer to write + * @param size: Size of the buffer to write to memory + * @retval ald status + */ +ald_status_t ald_sram_write_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size) +{ + if (hperh->state == ALD_SRAM_STATE_PROTECTED) + return ERROR; + + __LOCK(hperh); + hperh->state = ALD_SRAM_STATE_BUSY; + + /* Write data to memory */ + for (; size != 0U; size--) + *(__IO uint32_t *)addr++ = *buf++; + + hperh->state = ALD_SRAM_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Reads a halfwords data from the SRAM memory using DMA transfer. + * @param hperh: pointer to a sram_handle_t structure that contains + * the configuration information for SRAM module. + * @param addr: Pointer to read start address + * @param buf: Pointer to destination buffer + * @param size: Size of the buffer to read from memory + * @param ch: Index of DMA channel + * @retval ald status + */ +ald_status_t ald_sram_read_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch) +{ + if (buf == NULL) + return ERROR; + + hperh->hdma.perh = DMA0; + hperh->hdma.cplt_cbk = hperh->cplt_cbk; + ald_dma_config_struct(&hperh->hdma.config); + + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src = (void *)addr; + hperh->hdma.config.dst = (void *)buf; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.msel = DMA_MSEL_NONE; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = ch; + hperh->hdma.config.R_power = DMA_R_POWER_4; + hperh->hdma.config.burst = ENABLE; + + ald_dma_config_auto(&hperh->hdma); + return OK; +} + +/** + * @brief Write a halfwords data to the SRAM memory using DMA transfer. + * @param hperh: pointer to a sram_handle_t structure that contains + * the configuration information for SRAM module. + * @param addr: Pointer to write start address + * @param buf: Pointer to destination buffer + * @param size: Size of the buffer to write from memory + * @param ch: Index of DMA channel + * @retval ald status + */ +ald_status_t ald_sram_write_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch) +{ + if (buf == NULL) + return ERROR; + ; + hperh->hdma.perh = DMA0; + hperh->hdma.cplt_cbk = hperh->cplt_cbk; + ald_dma_config_struct(&hperh->hdma.config); + + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)addr; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.msel = DMA_MSEL_NONE; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = ch; + hperh->hdma.config.R_power = DMA_R_POWER_4; + hperh->hdma.config.burst = ENABLE; + + ald_dma_config_auto(&hperh->hdma); + return OK; +} +#endif +/** + * @} + */ + +/** @defgroup SRAM_Public_Functions_Group3 Control functions + * @brief Control functions + * @{ + */ +/** + * @brief Enables dynamically SRAM write operation. + * @param hperh: pointer to a sram_handle_t structure + * @retval ald status + */ +ald_status_t ald_sram_write_enable(sram_handle_t *hperh) +{ + __LOCK(hperh); + ald_ebi_nor_sram_write_enable(hperh->instance, hperh->init.bank); + hperh->state = ALD_SRAM_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Disables dynamically SRAM write operation. + * @param hperh: pointer to a sram_handle_t structure + * @retval ald status + */ +ald_status_t ald_sram_write_disable(sram_handle_t *hperh) +{ + __LOCK(hperh); + hperh->state = ALD_SRAM_STATE_BUSY; + ald_ebi_nor_sram_write_disable(hperh->instance, hperh->init.bank); + hperh->state = ALD_SRAM_STATE_PROTECTED; + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @addtogroup SRAM_Public_Functions_Group4 State functions + * @brief State functions + * @{ + */ +/** + * @brief Returns the SRAM controller state + * @param hperh: pointer to a SRAM_HandleTypeDef structure + * @retval ald state + */ +ald_sram_state_t ald_sram_get_state(sram_handle_t *hperh) +{ + return hperh->state; +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_SRAM */ + +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..11deb8d11bc69f9b228475be1eb1f8e1da47c1bc --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_timer.c @@ -0,0 +1,3694 @@ +/** + ********************************************************************************* + * + * @file ald_timer.c + * @brief TIMER module driver. + * This is the common part of the TIMER initialization + * + * @version V1.0 + * @date 06 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include +#include "ald_timer.h" +#include "ald_cmu.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup TIMER TIMER + * @brief TIMER module driver + * @{ + */ +#ifdef ALD_TIMER + +/** @defgroup TIMER_Private_Functions TIMER Private Functions + * @{ + */ +static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init); +static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); +static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); +static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); +static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); +static void timer_ccx_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state); +static void timer_ccxn_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state); +static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter); +static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter); +static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter); +static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter); +static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter); +static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter); +static void timer_etr_set_config(TIMER_TypeDef* TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter); +static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config); +#ifdef ALD_DMA +static void timer_dma_oc_cplt(void *arg); +static void timer_dma_capture_cplt(void *arg); +static void timer_dma_period_elapse_cplt(void *arg); +static void timer_dma_error(void *arg); +static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config); +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions TIMER Public Functions + * @{ + */ + +/** @defgroup TIMER_Public_Functions_Group1 TIMER Base functions + * @brief Time Base functions + * + * @verbatim + ============================================================================== + ##### Timer Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER base. + (+) Reset the TIMER base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Time base Unit according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER base handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_base_init(timer_handle_t *hperh) +{ + if (hperh == NULL) + return ERROR; + + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = TIMER_STATE_BUSY; + timer_base_set_config(hperh->perh, &hperh->init); + hperh->state = TIMER_STATE_READY; + + return OK; +} + +/** + * @brief Reset the TIMER base peripheral + * @param hperh: TIMER base handle + * @retval Status, see @ref ald_status_t. + */ +void ald_timer_base_reset(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + hperh->state = TIMER_STATE_BUSY; + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_RESET; + __UNLOCK(hperh); + + return; +} + +/** + * @brief Starts the TIMER Base generation. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_base_start(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + hperh->state = TIMER_STATE_BUSY; + TIMER_ENABLE(hperh); + hperh->state = TIMER_STATE_READY; + + return; +} + +/** + * @brief Stops the TIMER Base generation. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_base_stop(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + hperh->state = TIMER_STATE_BUSY; + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + + return; +} + +/** + * @brief Starts the TIMER Base generation in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_base_start_by_it(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, ENABLE); + TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER Base generation in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_base_stop_by_it(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, DISABLE); + TIMER_DISABLE(hperh); + + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER Base generation in DMA mode. + * @param hperh: TIMER handle + * @param hdma: Pointer to dma_handle_t. + * @param buf: The source Buffer address. + * @param len: The length of buffer to be transferred from memory to TIMER peripheral + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. +*/ +ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ERROR; + } + + hperh->state = TIMER_STATE_BUSY; + + if (hdma->perh == NULL) + hdma->perh = DMA0; + + hdma->cplt_cbk = timer_dma_period_elapse_cplt; + hdma->cplt_arg = (void *)hperh; + hdma->err_cbk = timer_dma_error; + hdma->err_arg = (void *)hperh; + + ald_dma_config_struct(&hdma->config); + hdma->config.src = (void *)buf; + hdma->config.dst = (void *)&hperh->perh->AR; + hdma->config.size = len; + hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; + hdma->config.src_inc = DMA_DATA_INC_HALFWORD; + hdma->config.dst_inc = DMA_DATA_INC_NONE; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_UPDATE; + hdma->config.channel = dma_ch; + + timer_dma_msel(hperh->perh, &hdma->config); + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, ENABLE); + TIMER_ENABLE(hperh); + + return OK; +} + +/** + * @brief Stops the TIMER Base generation in DMA mode. + * @param hperh: TIMER handle + * @retval None +*/ +void ald_timer_base_stop_by_dma(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, DISABLE); + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group2 TIMER Output Compare functions + * @brief Time Output Compare functions + * + * @verbatim + ============================================================================== + ##### Time Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Output Compare. + (+) Start the Time Output Compare. + (+) Stop the Time Output Compare. + (+) Start the Time Output Compare and enable interrupt. + (+) Stop the Time Output Compare and disable interrupt. + (+) Start the Time Output Compare and enable DMA transfer. + (+) Stop the Time Output Compare and disable DMA transfer. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Output Compare according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_oc_init(timer_handle_t *hperh) +{ + return ald_timer_base_init(hperh); +} + +/** + * @brief Starts the TIMER Output Compare signal generation. + * @param hperh: TIMER handle + * @param ch : TIMER Channel to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); + + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Output Compare signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} + +/** + * @brief Starts the TIMER Output Compare signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); + + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Output Compare signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} + + + + + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER Output Compare signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param hdma: Pointer to dma_handle_t. + * @param buf: The source Buffer address. + * @param len: The length of buffer to be transferred from memory to TIMER peripheral + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ERROR; + } + + hperh->state = TIMER_STATE_BUSY; + + if (hdma->perh == NULL) + hdma->perh = DMA0; + + hdma->cplt_cbk = timer_dma_oc_cplt; + hdma->cplt_arg = (void *)hperh; + hdma->err_cbk = timer_dma_error; + hdma->err_arg = (void *)hperh; + + ald_dma_config_struct(&hdma->config); + hdma->config.src = (void *)buf; + hdma->config.size = len; + hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; + hdma->config.src_inc = DMA_DATA_INC_HALFWORD; + hdma->config.dst_inc = DMA_DATA_INC_NONE; + hdma->config.channel = dma_ch; + + + timer_dma_msel(hperh->perh, &hdma->config); + + switch (ch) { + case TIMER_CHANNEL_1: + hdma->config.dst = (void *)&hperh->perh->CCVAL1; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hdma->config.dst = (void *)&hperh->perh->CCVAL2; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hdma->config.dst = (void *)&hperh->perh->CCVAL3; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + case TIMER_CHANNEL_4: + hdma->config.dst = (void *)&hperh->perh->CCVAL4; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); + + TIMER_ENABLE(hperh); + return OK; +} + +/** + * @brief Stops the TIMER Output Compare signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None +*/ +void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + + case TIMER_CHANNEL_4: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group3 TIMER PWM functions + * @brief TIMER PWM functions + * + * @verbatim + ============================================================================== + ##### Time PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER PWM. + (+) Start the Time PWM. + (+) Stop the Time PWM. + (+) Start the Time PWM and enable interrupt. + (+) Stop the Time PWM and disable interrupt. + (+) Start the Time PWM and enable DMA transfer. + (+) Stop the Time PWM and disable DMA transfer. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER PWM Time Base according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_pwm_init(timer_handle_t *hperh) +{ + return ald_timer_base_init(hperh); +} + +/** + * @brief Starts the PWM signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_oc_start(hperh, ch); + return; +} + +/** + * @brief Stops the PWM signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_oc_stop(hperh, ch); + return; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_oc_start_by_it(hperh, ch); + return; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_oc_stop_by_it(hperh, ch); + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER PWM signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param hdma: Pointer to dma_handle_t. + * @param buf: The source Buffer address. + * @param len: The length of buffer to be transferred from memory to TIMER peripheral + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + return ald_timer_oc_start_by_dma(hperh, ch, hdma, buf, len, dma_ch); +} + +/** + * @brief Stops the TIMER PWM signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_oc_stop_by_dma(hperh, ch); + return; +} +#endif +/** + * @brief Set the PWM freq. + * @param hperh: TIMER handle + * @param freq: PWM freq to set + * @retval None + */ +void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq) +{ + uint32_t _arr = ald_cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1; + + WRITE_REG(hperh->perh->AR, _arr); + hperh->init.period = _arr; +} + +/** + * @brief Set the PWM duty. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param duty: PWM duty to set + * @retval None + */ +void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty) +{ + uint32_t tmp = (hperh->init.period + 1) * duty / 100 - 1; + + if (ch == TIMER_CHANNEL_1) + WRITE_REG(hperh->perh->CCVAL1, tmp); + else if (ch == TIMER_CHANNEL_2) + WRITE_REG(hperh->perh->CCVAL2, tmp); + else if (ch == TIMER_CHANNEL_3) + WRITE_REG(hperh->perh->CCVAL3, tmp); + else if (ch == TIMER_CHANNEL_4) + WRITE_REG(hperh->perh->CCVAL4, tmp); + else { + ;/* do nothing */ + } +} + +/** + * @brief Set capture the PWM. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be captured the PWM + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_PWM_INPUT_INSTANCE(hperh->perh, ch)); + + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); + SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2EN_MSK); + + return; +} +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group4 TIMER Input Capture functions + * @brief Time Input Capture functions + * + * @verbatim + ============================================================================== + ##### Time Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Input Capture. + (+) Start the Time Input Capture. + (+) Stop the Time Input Capture. + (+) Start the Time Input Capture and enable interrupt. + (+) Stop the Time Input Capture and disable interrupt. + (+) Start the Time Input Capture and enable DMA transfer. + (+) Stop the Time Input Capture and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Input Capture Time base according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_ic_init(timer_handle_t *hperh) +{ + return ald_timer_base_init(hperh); +} + +/** + * @brief Starts the TIMER Input Capture measurement. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Input Capture measurement. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER Input Capture measurement in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); + break; + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Input Capture measurement in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); + break; + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_DISABLE(hperh); + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER Input Capture measurement in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param hdma: Pointer to dma_handle_t. + * @param buf: The destination Buffer address. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma, uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ERROR; + } + + hperh->state = TIMER_STATE_BUSY; + + if (hdma->perh == NULL) + hdma->perh = DMA0; + + hdma->cplt_cbk = timer_dma_capture_cplt; + hdma->cplt_arg = (void *)hperh; + hdma->err_cbk = timer_dma_error; + hdma->err_arg = (void *)hperh; + + ald_dma_config_struct(&hdma->config); + hdma->config.dst = (void *)buf; + hdma->config.size = len; + hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; + hdma->config.src_inc = DMA_DATA_INC_NONE; + hdma->config.dst_inc = DMA_DATA_INC_HALFWORD; + hdma->config.channel = dma_ch; + + timer_dma_msel(hperh->perh, &hdma->config); + + switch (ch) { + case TIMER_CHANNEL_1: + hdma->config.src = (void *)&hperh->perh->CCVAL1; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hdma->config.src = (void *)&hperh->perh->CCVAL2; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hdma->config.src = (void *)&hperh->perh->CCVAL3; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + case TIMER_CHANNEL_4: + hdma->config.src = (void *)&hperh->perh->CCVAL4; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_ENABLE(hperh); + return OK; +} + +/** + * @brief Stops the TIMER Input Capture measurement in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + case TIMER_CHANNEL_4: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); + break; + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group5 TIMER One Pulse functions + * @brief Time One Pulse functions + * + * @verbatim + ============================================================================== + ##### Time One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER One Pulse. + (+) Start the Time One Pulse. + (+) Stop the Time One Pulse. + (+) Start the Time One Pulse and enable interrupt. + (+) Stop the Time One Pulse and disable interrupt. + (+) Start the Time One Pulse and enable DMA transfer. + (+) Stop the Time One Pulse and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER One Pulse Time Base according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @param mode: Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIMER_OP_MODE_SINGLE: Only one pulse will be generated. + * @arg TIMER_OP_MODE_REPEAT: Repetitive pulses wil be generated. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode) +{ + if (hperh == NULL) + return ERROR; + + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + assert_param(IS_TIMER_OP_MODE(mode)); + + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = TIMER_STATE_BUSY; + timer_base_set_config(hperh->perh, &hperh->init); + MODIFY_REG(hperh->perh->CON1, TIMER_CON1_SPMEN_MSK, mode << TIMER_CON1_SPMEN_POS); + hperh->state = TIMER_STATE_READY; + + return OK; +} + +/** + * @brief Starts the TIMER One Pulse signal generation. + * @param hperh: TIMER One Pulse handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch) +{ + /* Enable the Capture compare and the Input Capture channels + * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) + * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and + * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output + * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together + */ + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER One Pulse signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch) +{ + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); + + TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER One Pulse signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) +{ + /* Enable the Capture compare and the Input Capture channels + * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) + * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and + * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output + * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together + */ + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER One Pulse signal generation in interrupt mode. + * @param hperh : TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) +{ + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); + + TIMER_DISABLE(hperh); + return; +} +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group6 TIMER Encoder functions + * @brief TIMER Encoder functions + * + * @verbatim + ============================================================================== + ##### Time Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Encoder. + (+) Start the Time Encoder. + (+) Stop the Time Encoder. + (+) Start the Time Encoder and enable interrupt. + (+) Stop the Time Encoder and disable interrupt. + (+) Start the Time Encoder and enable DMA transfer. + (+) Stop the Time Encoder and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Encoder Interface and create the associated handle. + * @param hperh: TIMER handle + * @param config: TIMER Encoder Interface configuration structure + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config) +{ + if (hperh == NULL) + return ERROR; + + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_ENCODER_MODE(config->mode)); + assert_param(IS_TIMER_IC_POLARITY(config->ic1_polarity)); + assert_param(IS_TIMER_IC_POLARITY(config->ic2_polarity)); + assert_param(IS_TIMER_IC_SELECT(config->ic1_sel)); + assert_param(IS_TIMER_IC_SELECT(config->ic2_sel)); + assert_param(IS_TIMER_IC_PSC(config->ic1_psc)); + assert_param(IS_TIMER_IC_PSC(config->ic2_psc)); + assert_param(IS_TIMER_IC_FILTER(config->ic1_filter)); + assert_param(IS_TIMER_IC_FILTER(config->ic2_filter)); + + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = TIMER_STATE_BUSY; + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + timer_base_set_config(hperh->perh, &hperh->init); + + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, config->ic1_sel << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, config->ic2_sel << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->ic1_psc << TIMER_CHMR1_IC1PRES_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->ic2_psc << TIMER_CHMR1_IC2PRES_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->ic1_filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I2FLT_MSK, config->ic2_filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, (config->ic1_polarity & 0x1) << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((config->ic1_polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, (config->ic2_polarity & 0x1) << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((config->ic2_polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS); + + hperh->state = TIMER_STATE_READY; + return OK; +} + +/** + * @brief Starts the TIMER Encoder Interface. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + break; + } + + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Encoder Interface. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + break; + } + + TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER Encoder Interface in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + } + + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Encoder Interface in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + } + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER Encoder Interface in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @param hdma1: Pointer to dma_handle_t. + * @param hdma2: Pointer to dma_handle_t. + * @param buf1: The destination Buffer address. Reading data from CCR1. + * @param buf2: The destination Buffer address. Reading data from CCR2. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch1: Channel of DMA. + * @param dma_ch2: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + dma_handle_t *hdma1, dma_handle_t *hdma2, uint16_t *buf1, + uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf1 == 0) || ((uint32_t)buf2 == 0) || (len == 0)) + return ERROR; + } + + if (hdma1->perh == NULL) + hdma1->perh = DMA0; + if (hdma2->perh == NULL) + hdma2->perh = DMA0; + + hperh->state = TIMER_STATE_BUSY; + hdma1->cplt_cbk = timer_dma_capture_cplt; + hdma1->cplt_arg = (void *)hperh; + hdma1->err_cbk = timer_dma_error; + hdma1->err_arg = (void *)hperh; + + ald_dma_config_struct(&hdma1->config); + hdma1->config.size = len; + hdma1->config.data_width = DMA_DATA_SIZE_HALFWORD; + hdma1->config.src_inc = DMA_DATA_INC_NONE; + hdma1->config.dst_inc = DMA_DATA_INC_HALFWORD; + + timer_dma_msel(hperh->perh, &hdma1->config); + + switch (ch) { + case TIMER_CHANNEL_1: + hdma1->config.src = (void *)&hperh->perh->CCVAL1; + hdma1->config.dst = (void *)buf1; + hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hdma1->config.channel = dma_ch1; + ald_dma_config_basic(hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); + break; + + case TIMER_CHANNEL_2: + hdma1->config.src = (void *)&hperh->perh->CCVAL2; + hdma1->config.dst = (void *)buf2; + hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + hdma1->config.channel = dma_ch2; + ald_dma_config_basic(hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + TIMER_ENABLE(hperh); + break; + + default: + hdma2->cplt_cbk = timer_dma_capture_cplt; + hdma2->cplt_arg = (void *)hperh; + hdma2->err_cbk = timer_dma_error; + hdma2->err_arg = (void *)hperh; + memcpy(&hdma2->config, &hdma1->config, sizeof(dma_config_t)); + + hdma1->config.src = (void *)&hperh->perh->CCVAL1; + hdma1->config.dst = (void *)buf1; + hdma1->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hdma1->config.channel = dma_ch1; + ald_dma_config_basic(hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + + hdma2->config.src = (void *)&hperh->perh->CCVAL2; + hdma2->config.dst = (void *)buf2; + hdma2->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + hdma2->config.channel = dma_ch2; + ald_dma_config_basic(hdma2); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + TIMER_ENABLE(hperh); + break; + } + + return OK; +} + +/** + * @brief Stops the TIMER Encoder Interface in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + } + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group7 TIMER Hall Sensor functions + * @brief TIMER Hall Sensor functions + * + * @verbatim + ============================================================================== + ##### Time Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER hall sensor. + (+) Start the hall sensor. + (+) Stop the hall sensor. + (+) Start the hall sensor and enable interrupt. + (+) Stop the hall sensor and disable interrupt. + (+) Start the hall sensor and enable DMA transfer. + (+) Stop the hal sensor and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Encoder Interface and create the associated handle. + * @param hperh: TIMER handle + * @param config: TIMER Encoder Interface configuration structure + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config) +{ + timer_oc_init_t oc; + + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = TIMER_STATE_READY; + timer_base_set_config(hperh->perh, &hperh->init); + timer_ti1_set_config(hperh->perh, config->polarity, TIMER_IC_SEL_TRC, config->filter); + + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); + SET_BIT(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + + oc.oc_mode = TIMER_OC_MODE_PWM2; + oc.pulse = config->delay; + oc.oc_polarity = TIMER_OC_POLARITY_HIGH; + oc.ocn_polarity = TIMER_OCN_POLARITY_HIGH; + oc.oc_fast_en = DISABLE; + oc.oc_idle = TIMER_OC_IDLE_RESET; + oc.ocn_idle = TIMER_OCN_IDLE_RESET; + timer_oc2_set_config(hperh->perh, &oc); + + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_TRGO_OC2REF << TIMER_SMCON_SMODS_POSS); + return OK; +} +/** + * @brief Starts the TIMER hall sensor interface. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_start(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER hall sensor interface. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_stop(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + TIMER_DISABLE(hperh); + + return; +} + +/** + * @brief Starts the TIMER hall sensor interface in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER hall sensor interface in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + TIMER_DISABLE(hperh); + + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER hall sensor interface in DMA mode. + * @param hperh: TIMER handle + * @param hdma: Pointer to dma_handle_t. + * @param buf: The destination Buffer address. Reading data from CCR1. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0) || (len == 0)) + return ERROR; + } + + if (hdma->perh == NULL) + hdma->perh = DMA0; + + hperh->state = TIMER_STATE_BUSY; + hdma->cplt_cbk = timer_dma_capture_cplt; + hdma->cplt_arg = (void *)hperh; + hdma->err_cbk = timer_dma_error; + hdma->err_arg = (void *)hperh; + + ald_dma_config_struct(&hdma->config); + hdma->config.size = len; + hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; + hdma->config.src_inc = DMA_DATA_INC_NONE; + hdma->config.dst_inc = DMA_DATA_INC_HALFWORD; + + timer_dma_msel(hperh->perh, &hdma->config); + + hdma->config.src = (void *)&hperh->perh->CCVAL1; + hdma->config.dst = (void *)buf; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hdma->config.channel = dma_ch; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); + + return OK; +} +/** + * @brief Stops the TIMER hall sensor interface in DMA mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + TIMER_DISABLE(hperh); + + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group8 TIMER complementary output compare functions + * @brief TIMER complementary output compare functions + * + * @verbatim + ============================================================================== + ##### Time complementary output compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary output compare. + (+) Stop the Time complementary output compare. + (+) Start the Time complementary output compare and enable interrupt. + (+) Stop the Time complementary output compare and disable interrupt. + (+) Start the Time complementary output compare and enable DMA transfer. + (+) Stop the Time complementary output compare and disable DMA transfer. + + * @endverbatim + * @{ + */ + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER output compare signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); + + return; +} + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + default: + break; + } + + ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, ENABLE); + timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER output compare signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + default: + break; + } + + if ((!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1NEN_MSK))) + && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2NEN_MSK))) + && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC3NEN_MSK)))) { + ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, DISABLE); + } + + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); + + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @param hdma: Pointer to dma_handle_t. + * @param buf: The destination Buffer address. Reading data from CCRx. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval None + */ +ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ERROR; + } + + hperh->state = TIMER_STATE_BUSY; + + if (hdma->perh == NULL) + hdma->perh = DMA0; + + hdma->cplt_cbk = timer_dma_oc_cplt; + hdma->cplt_arg = (void *)hperh; + hdma->err_cbk = timer_dma_error; + hdma->err_arg = (void *)hperh; + + ald_dma_config_struct(&hdma->config); + hdma->config.src = (void *)buf; + hdma->config.size = len; + hdma->config.data_width = DMA_DATA_SIZE_HALFWORD; + hdma->config.src_inc = DMA_DATA_INC_HALFWORD; + hdma->config.dst_inc = DMA_DATA_INC_NONE; + hdma->config.channel = dma_ch; + hdma->config.msel = DMA_MSEL_TIMER0; + + switch (ch) { + case TIMER_CHANNEL_1: + hdma->config.dst = (void *)&hperh->perh->CCVAL1; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hdma->config.dst = (void *)&hperh->perh->CCVAL2; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hdma->config.dst = (void *)&hperh->perh->CCVAL3; + hdma->config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(hdma); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); + + return OK; +} + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + default: + break; + } + + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); + + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group9 TIMER complementary PWM functions + * @brief TIMER complementary PWM functions + * + * @verbatim + ============================================================================== + ##### Time complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary PWM. + (+) Stop the Time complementary PWM. + (+) Start the Time complementary PWM and enable interrupt. + (+) Stop the Time complementary PWM and disable interrupt. + (+) Start the Time complementary PWM and enable DMA transfer. + (+) Stop the Time complementary PWM and disable DMA transfer. + + * @endverbatim + * @{ + */ + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_start(hperh, ch); +} + +/** + * @brief Stops the TIMER PWM signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_stop(hperh, ch); +} + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_start_by_it(hperh, ch); +} + +/** + * @brief Stops the TIMER PWM signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_stop_by_it(hperh, ch); +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @param hdma: Pointer to dma_handle_t. + * @param buf: The destination Buffer address. Reading data from CCRx. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval None + */ +ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, dma_handle_t *hdma, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + return ald_timer_ocn_start_by_dma(hperh, hdma, ch, buf, len, dma_ch); +} + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_stop_by_dma(hperh, ch); +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group10 TIMER complementary one pulse functions + * @brief TIMER complementary one pulse functions + * + * @verbatim + ============================================================================== + ##### Time complementary one pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary one pulse. + (+) Stop the Time complementary one pulse. + (+) Start the Time complementary one pulse and enable interrupt. + (+) Stop the Time complementary one pulse and disable interrupt. + + * @endverbatim + * @{ + */ + +/** + * @brief Starts the TIMER one pulse signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_start(hperh, ch); +} + +/** + * @brief Stops the TIMER one pulse signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_stop(hperh, ch); +} + +/** + * @brief Starts the TIMER one pulse signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_start_by_it(hperh, ch); +} + +/** + * @brief Stops the TIMER one pulse signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_stop_by_it(hperh, ch); +} +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group11 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead timere. + (+) Configure Master and the Slave synchronization. + (+) Handle TIMER interrupt. + (+) Get TIMER compare register's vale. + (+) Configure TIMER interrupt ENABLE/DISABLE. + (+) Get TIMER interrupt source status. + (+) Get TIMER interrupt flag status. + (+) Clear TIMER interrupt flag. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Output Compare Channels according to the specified + * parameters in the timer_oc_init_t. + * @param hperh: TIMER handle + * @param config: TIMER Output Compare configuration structure + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t* config, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_OC_MODE(config->oc_mode)); + assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + switch (ch) { + case TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, config); + break; + + case TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, config); + break; + + case TIMER_CHANNEL_3: + timer_oc3_set_config(hperh->perh, config); + break; + + case TIMER_CHANNEL_4: + timer_oc4_set_config(hperh->perh, config); + break; + + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Initializes the TIMER Input Capture Channels according to the specified + * parameters in the timer_ic_init_t. + * @param hperh: TIMER handle + * @param config: TIMER Input Capture configuration structure + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t* config, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_SELECT(config->sel)); + assert_param(IS_TIMER_IC_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + switch (ch) { + case TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); + break; + + case TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS); + break; + + case TIMER_CHANNEL_3: + timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS); + break; + + case TIMER_CHANNEL_4: + timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS); + break; + + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Initializes the TIMER One Pulse Channels according to the specified + * parameters in the timer_one_pulse_init_t. + * @param hperh: TIMER handle + * @param config: TIMER One Pulse configuration structure + * @param ch_out: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @param ch_in: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, + timer_channel_t ch_out, timer_channel_t ch_in) +{ + timer_oc_init_t tmp; + + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_OC_MODE(config->mode)); + assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); + assert_param(IS_TIMER_OCN_POLARITY(config->ocn_polarity)); + assert_param(IS_TIMER_OCIDLE_STATE(config->oc_idle)); + assert_param(IS_TIMER_OCNIDLE_STATE(config->ocn_idle)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_SELECT(config->sel)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (ch_out == ch_in) + return ERROR; + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + tmp.oc_mode = config->mode; + tmp.pulse = config->pulse; + tmp.oc_polarity = config->oc_polarity; + tmp.ocn_polarity = config->ocn_polarity; + tmp.oc_idle = config->oc_idle; + tmp.ocn_idle = config->ocn_idle; + + switch (ch_out) { + case TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, &tmp); + break; + case TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, &tmp); + break; + default: + break; + } + + switch (ch_in) { + case TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param hperh: TIMER handle + * @param config: pointer to a TIMER_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIMER peripheral. + * @param ch: specifies the TIMER Channel + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @arg TIMER_CHANNEL_4: TIMER Channel 4 + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->state)); + assert_param(IS_TIMER_CLEAR_INPUT_SOURCE(config->source)); + assert_param(IS_TIMER_CLEAR_INPUT_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_CHNREF_CLEAR(config->clrsel)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (config->source == TIMER_INPUT_NONE) { + timer_etr_set_config(hperh->perh, TIMER_ETR_PSC_DIV1, TIMER_CLK_POLARITY_NO_INV, 0); + } + else { + timer_etr_set_config(hperh->perh, config->psc, + (timer_clock_polarity_t)config->polarity, config->filter); + } + + if (config->clrsel == TIMER_CHNREF_CLR_CMP_IN) { + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_CHCSEL_MASK); + } + else { + SET_BIT(hperh->perh->SMCON, TIMER_SMCON_CHCSEL_MASK); + } + + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS); + break; + + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS); + break; + + case TIMER_CHANNEL_3: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS); + break; + + case TIMER_CHANNEL_4: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS); + break; + + default: + break; + } + + return OK; +} + +/** + * @brief Configures the clock source to be used + * @param hperh: TIMER handle + * @param config: pointer to a timer_clock_config_t structure that + * contains the clock source information for the TIMER peripheral. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_CLOCK_SOURCE(config->source)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + WRITE_REG(hperh->perh->SMCON, 0x0); + + switch (config->source) { + case TIMER_SRC_INTER: + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + break; + + case TIMER_SRC_ETRMODE1: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ETRMODE2: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK); + break; + + case TIMER_SRC_TI1: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_TI2: + timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_TI1ED: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR0: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR1: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR2: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR3: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param hperh: TIMER handle. + * @param ti1_select: Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg 0: The TIMERx_CH1 pin is connected to TI1 input + * @arg 1: The TIMERx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK, ti1_select << TIMER_CON2_I1FSEL_POS); + return OK; +} + +/** + * @brief Configures the TIMER in Slave mode + * @param hperh: TIMER handle. + * @param config: pointer to a timer_slave_config_t structure that + * contains the selected trigger (internal trigger input, filtered + * timerer input or external trigger input) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_SLAVE_MODE(config->mode)); + assert_param(IS_TIMER_TS(config->input)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + timer_slave_set_config(hperh, config); + ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Configures the TIMER in Slave mode in interrupt mode + * @param hperh: TIMER handle. + * @param config: pointer to a timer_slave_config_t structure that + * contains the selected trigger (internal trigger input, filtered + * timerer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_SLAVE_MODE(config->mode)); + assert_param(IS_TIMER_TS(config->input)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + timer_slave_set_config(hperh, config); + ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, ENABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Generate a software event + * @param hperh: TIMER handle + * @param event: specifies the event source. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_t event) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_EVENT_SOURCE(event)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + WRITE_REG(hperh->perh->SGE, event); + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param hperh: TIMER handle. + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1 : TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2 : TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3 : TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected + * @retval Captured value + */ +uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) +{ + uint32_t tmp; + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + switch (ch) { + case TIMER_CHANNEL_1: + tmp = hperh->perh->CCVAL1; + break; + case TIMER_CHANNEL_2: + tmp = hperh->perh->CCVAL2; + break; + case TIMER_CHANNEL_3: + tmp = hperh->perh->CCVAL3; + break; + case TIMER_CHANNEL_4: + tmp = hperh->perh->CCVAL4; + break; + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return tmp; +} + +/** + * @brief Sets TIMER output mode. + * @param hperh: TIMER handle. + * @param mode: TIMER output mode. + * @param ch: TIMER Channels. + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1 : TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2 : TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3 : TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected + * @retval None + */ +void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_OC_MODE(mode)); + assert_param(IS_TIMER_CHANNELS(ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS); + break; + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS); + break; + case TIMER_CHANNEL_3: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS); + break; + case TIMER_CHANNEL_4: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS); + break; + default: + break; + } + + return; +} + +/** + * @brief Configure the channel in commutation event. + * @param hperh: TIMER handel + * @param config: Parameters of the channel. + * @retval None + */ +void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config) +{ + uint32_t cm1, cm2, cce; + + assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->ch[0].en)); + assert_param(IS_FUNC_STATE(config->ch[0].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[0].mode)); + assert_param(IS_FUNC_STATE(config->ch[1].en)); + assert_param(IS_FUNC_STATE(config->ch[1].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[1].mode)); + assert_param(IS_FUNC_STATE(config->ch[2].en)); + assert_param(IS_FUNC_STATE(config->ch[2].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[2].mode)); + + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); + + cm1 = hperh->perh->CHMR1; + cm2 = hperh->perh->CHMR2; + cce = hperh->perh->CCEP; + + MODIFY_REG(cm1, (0x7 << 4), (config->ch[0].mode << 4)); + MODIFY_REG(cm1, (0x7 << 12), (config->ch[1].mode << 12)); + MODIFY_REG(cm2, (0x7 << 4), (config->ch[2].mode << 4)); + MODIFY_REG(cce, (0x1 << 0), (config->ch[0].en << 0)); + MODIFY_REG(cce, (0x1 << 2), (config->ch[0].n_en << 2)); + MODIFY_REG(cce, (0x1 << 4), (config->ch[1].en << 4)); + MODIFY_REG(cce, (0x1 << 6), (config->ch[1].n_en << 6)); + MODIFY_REG(cce, (0x1 << 8), (config->ch[2].en << 8)); + MODIFY_REG(cce, (0x1 << 10), (config->ch[2].n_en << 10)); + + WRITE_REG(hperh->perh->CHMR1, cm1); + WRITE_REG(hperh->perh->CHMR2, cm2); + WRITE_REG(hperh->perh->CCEP, cce); + + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Configure the TIMER commutation event sequence. + * @param hperh: TIMER handel + * @param ts: the internal trigger corresponding to the timerer interfacing + * with the hall sensor. + * This parameter can be one of the following values: + * @arg TIMER_TS_ITR0 + * @arg TIMER_TS_ITR1 + * @arg TIMER_TS_ITR2 + * @arg TIMER_TS_ITR3 + * @param trgi: the commutation event source. + * This parameter can be one of the following values: + * @arg ENABLE: Commutation event source is TRGI + * @arg DISABLE: Commutation event source is set by software using the COMG bit + * @retval None + */ +void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) +{ + assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_TS(ts)); + assert_param(IS_FUNC_STATE(trgi)); + + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ts << TIMER_SMCON_TSSEL_POSS); + SET_BIT(hperh->perh->CON2, TIMER_CON2_CCPCEN_MSK); + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_CCUSEL_MSK, trgi << TIMER_CON2_CCUSEL_POS); + + return; +} + +/** + * @brief Configure the TIMER commutation event sequence with interrupt. + * @param hperh: TIMER handel + * @param ts: the internal trigger corresponding to the timerer interfacing + * with the hall sensor. + * This parameter can be one of the following values: + * @arg TIMER_TS_ITR0 + * @arg TIMER_TS_ITR1 + * @arg TIMER_TS_ITR2 + * @arg TIMER_TS_ITR3 + * @param trgi: the commutation event source. + * This parameter can be one of the following values: + * @arg ENABLE: Commutation event source is TRGI + * @arg DISABLE: Commutation event source is set by software using the COMG bit + * @retval None + */ +void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) +{ + ald_timer_com_event_config(hperh, ts, trgi); + ald_timer_interrupt_config(hperh, TIMER_IT_COM, ENABLE); +} + +/** + * @brief Configure the break, dead timere, lock level state. + * @param hperh: TIMER handle + * @param config: Pointer to the timer_break_dead_timere_t structure. + * @retval None + */ +void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config) +{ + uint32_t tmp; + + assert_param(IS_TIMER_BREAK_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->off_run)); + assert_param(IS_FUNC_STATE(config->off_idle)); + assert_param(IS_TIMER_CLOCK_LEVEL(config->lock_level)); + assert_param(IS_TIMER_DEAD_TIMERE(config->dead_time)); + assert_param(IS_FUNC_STATE(config->break_state)); + assert_param(IS_TIMER_BREAK_POLARITY(config->polarity)); + assert_param(IS_FUNC_STATE(config->auto_out)); + + tmp = READ_REG(hperh->perh->BDCFG); + MODIFY_REG(tmp, TIMER_BDCFG_OFFSSR_MSK, config->off_run << TIMER_BDCFG_OFFSSR_POS); + MODIFY_REG(tmp, TIMER_BDCFG_OFFSSI_MSK, config->off_idle << TIMER_BDCFG_OFFSSI_POS); + MODIFY_REG(tmp, TIMER_BDCFG_LOCKLVL_MSK, config->lock_level << TIMER_BDCFG_LOCKLVL_POSS); + MODIFY_REG(tmp, TIMER_BDCFG_DT_MSK, config->dead_time << TIMER_BDCFG_DT_POSS); + MODIFY_REG(tmp, TIMER_BDCFG_BRKEN_MSK, config->break_state << TIMER_BDCFG_BRKEN_POS); + MODIFY_REG(tmp, TIMER_BDCFG_BRKP_MSK, config->polarity << TIMER_BDCFG_BRKP_POS); + MODIFY_REG(tmp, TIMER_BDCFG_AOEN_MSK, config->auto_out << TIMER_BDCFG_AOEN_POS); + WRITE_REG(hperh->perh->BDCFG, tmp); + + hperh->state = TIMER_STATE_READY; + return; +} + +/** + * @brief Configure the master mode + * @param hperh: TIMER handle + * @param config: Pointer to the timer_master_config_t structure. + * @retval None + */ +void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_MASTER_MODE_SEL(config->sel)); + assert_param(IS_FUNC_STATE(config->master_en)); + + hperh->state = TIMER_STATE_BUSY; + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_TRGOSEL_MSK, config->sel << TIMER_CON2_TRGOSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_MSCFG_MSK, config->master_en << TIMER_SMCON_MSCFG_POS); + hperh->state = TIMER_STATE_READY; + + return; +} + +/** + * @brief This function handles TIMER interrupts requests. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_irq_handler(timer_handle_t *hperh) +{ + uint32_t reg = hperh->perh->IFM; + + /* Capture or compare 1 event */ + if (READ_BIT(reg, TIMER_FLAG_CC1)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC1); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 2 event */ + if (READ_BIT(reg, TIMER_FLAG_CC2)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC2); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 3 event */ + if (READ_BIT(reg, TIMER_FLAG_CC3)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC3); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC3SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 4 event */ + if (READ_BIT(reg, TIMER_FLAG_CC4)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC4); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC4SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + + /* TIMER Update event */ + if (READ_BIT(reg, TIMER_FLAG_UPDATE)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_UPDATE); + + if (hperh->period_elapse_cbk) + hperh->period_elapse_cbk(hperh); + } + + /* TIMER Break input event */ + if (READ_BIT(reg, TIMER_FLAG_BREAK)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_BREAK); + + if (hperh->break_cbk) + hperh->break_cbk(hperh); + } + + /* TIMER Trigger detection event */ + if (READ_BIT(reg, TIMER_FLAG_TRIGGER)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_TRIGGER); + + if (hperh->trigger_cbk) + hperh->trigger_cbk(hperh); + } + + /* TIMER commutation event */ + if (READ_BIT(reg, TIMER_FLAG_COM)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_COM); + + if (hperh->com_cbk) + hperh->com_cbk(hperh); + } + + return; +} + +/** + * @brief Configure DMA request source. + * @param hperh: TIMER handle + * @param req: DMA request source. + * @param state: New state of the specified DMA request. + * @retval None + */ +void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->DMAEN, req); + else + CLEAR_BIT(hperh->perh->DMAEN, req); + + return; +} + +/** + * @brief Enable/disable the specified TIMER interrupts. + * @param hperh: Pointer to a timer_handle_t structure. + * @param it: Specifies the timer interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref timer_it_t. + * @param state: New state of the specified TIMER interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->IER, it); + else + SET_BIT(hperh->perh->IDR, it); + + return; +} + +/** + * @brief Get the status of TIMER interrupt source. + * @param hperh: Pointer to a timer_handle_t structure. + * @param it: Specifies the TIMER interrupt source. + * This parameter can be one of the @ref timer_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IT(it)); + + if (hperh->perh->IVS & it) + return SET; + + return RESET; +} + +/** + * @brief Get the status of TIMER interrupt flag. + * @param hperh: Pointer to a timer_handle_t structure. + * @param flag: Specifies the TIMER interrupt flag. + * This parameter can be one of the @ref timer_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_FLAG(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** + * @brief Clear the TIMER interrupt flag. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the TIMER interrupt flag. + * This parameter can be one of the @ref timer_flag_t. + * @retval None + */ +void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_FLAG(flag)); + + hperh->perh->ICR = flag; + return; +} +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group12 Peripheral State functions + * @brief Peripheral State functions + * + * @verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permit to get in run-timere the status of the peripheral + and the data flow. + + @endverbatim + * @{ + */ + +/** + * @brief Return the TIMER Base state + * @param hperh: TIMER handle + * @retval TIMER peripheral state + */ +timer_state_t ald_timer_get_state(timer_handle_t *hperh) +{ + return hperh->state; +} +/** + * @} + */ +/** + * @} + */ + +/** @addtogroup TIMER_Private_Functions + * @{ + */ + +#ifdef ALD_DMA +/** + * @brief TIMER DMA out compare complete callback. + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_oc_cplt(void *arg) +{ + timer_handle_t *hperh = (timer_handle_t *)arg; + + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + return; +} + +/** + * @brief TIMER DMA Capture complete callback. + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_capture_cplt(void *arg) +{ + timer_handle_t *hperh = (timer_handle_t *)arg; + + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + return; +} + +/** + * @brief TIMER DMA Period Elapse complete callback. + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_period_elapse_cplt(void *arg) +{ + timer_handle_t *hperh = (timer_handle_t *)arg; + + if (hperh->period_elapse_cbk) + hperh->period_elapse_cbk(hperh); + + hperh->state = TIMER_STATE_READY; + return; +} + +/** + * @brief TIMER DMA error callback + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_error(void *arg) +{ + timer_handle_t *hperh = (timer_handle_t *)arg; + + hperh->state = TIMER_STATE_READY; + if (hperh->error_cbk) + hperh->error_cbk(hperh); + + return; +} +#endif + +/** + * @brief Time Base configuration + * @param TIMERx: TIMER periheral + * @param init: TIMER Base configuration structure + * @retval None + */ +static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init) +{ + assert_param(IS_TIMER_COUNTER_MODE(init->mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(init->clk_div)); + + if (init->mode == TIMER_CNT_MODE_UP || init->mode == TIMER_CNT_MODE_DOWN) { + CLEAR_BIT(TIMERx->CON1, TIMER_CON1_CMSEL_MSK); + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DIRSEL_MSK, init->mode << TIMER_CON1_DIRSEL_POS); + } + else { + MODIFY_REG(TIMERx->CON1, TIMER_CON1_CMSEL_MSK, (init->mode - 1) << TIMER_CON1_CMSEL_POSS); + } + + if (IS_TIMER_CLOCK_DIVISION_INSTANCE(TIMERx)) + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DFCKSEL_MSK, init->clk_div << TIMER_CON1_DFCKSEL_POSS); + + WRITE_REG(TIMERx->AR, init->period); + WRITE_REG(TIMERx->PRES, init->prescaler); + + if (IS_TIMER_REPETITION_COUNTER_INSTANCE(TIMERx)) + WRITE_REG(TIMERx->REPAR, init->re_cnt); + + return; +} + +/** + * @brief Time Ouput Compare 1 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH1OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC1POL_POS); + + if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_1)) { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC1NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK); + } + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1_MSK, oc_config->oc_idle << TIMER_CON2_OISS1_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS1N_POS); + } + + WRITE_REG(TIMERx->CCVAL1, oc_config->pulse); +} + +/** + * @brief Time Ouput Compare 2 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH2OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC2POL_POS); + + if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_2)) { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC2NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK); + } + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2_MSK, oc_config->oc_idle << TIMER_CON2_OISS2_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS2N_POS); + } + + WRITE_REG(TIMERx->CCVAL2, oc_config->pulse); +} + +/** + * @brief Time Ouput Compare 3 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH3OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC3POL_POS); + + if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_3)) { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC3NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK); + } + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3_MSK, oc_config->oc_idle << TIMER_CON2_OISS3_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS3N_POS); + } + + WRITE_REG(TIMERx->CCVAL3, oc_config->pulse); +} + +/** + * @brief Time Ouput Compare 4 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH4OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC4POL_POS); + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS4_MSK, oc_config->oc_idle << TIMER_CON2_OISS4_POS); + } + + WRITE_REG(TIMERx->CCVAL4, oc_config->pulse); +} + +/** + * @brief Enables or disables the TIMER Capture Compare Channel x. + * @param TIMERx: Select the TIMER peripheral + * @param ch: specifies the TIMER Channel + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @arg TIMER_CHANNEL_4: TIMER Channel 4 + * @param state: specifies the TIMER Channel CCxE bit new state. + * @retval None + */ +static void timer_ccx_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state) +{ + assert_param(IS_TIMER_CC2_INSTANCE(TIMERx)); + assert_param(IS_TIMER_CHANNELS(ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS); + break; + + case TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS); + break; + + case TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS); + break; + + case TIMER_CHANNEL_4: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS); + break; + + default: + break; + } +} +/** + * @brief Enables or disables the TIMER Capture Compare Channel xN. + * @param TIMERx: Select the TIMER peripheral + * @param ch: specifies the TIMER Channel + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @param state: specifies the TIMER Channel CCxNE bit new state. + * @retval None + */ +static void timer_ccxn_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state) +{ + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK, state << TIMER_CCEP_CC1NEN_POS); + break; + + case TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK, state << TIMER_CCEP_CC2NEN_POS); + break; + + case TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK, state << TIMER_CCEP_CC3NEN_POS); + break; + + default: + break; + } + +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, sel << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); + + return; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); + + return; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, sel << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); + + return; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); + return; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, sel << TIMER_CHMR2_CC3SSEL_POSS); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, filter << TIMER_CHMR2_I3FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, polarity << TIMER_CCEP_CC3POL_POS); + + return; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, sel << TIMER_CHMR2_CC4SSEL_POSS); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, filter << TIMER_CHMR2_I4FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, polarity << TIMER_CCEP_CC4POL_POS); + return; +} + +/** + * @brief Configures the TIMERx External Trigger (ETR). + * @param TIMERx: Select the TIMER peripheral + * @param psc: The external Trigger Prescaler. + * @param polarity: The external Trigger Polarity. + * @param filter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +static void timer_etr_set_config(TIMER_TypeDef* TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter) +{ + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETFLT_MSK, filter << TIMER_SMCON_ETFLT_POSS); + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPSEL_MSK, psc << TIMER_SMCON_ETPSEL_POSS); + CLEAR_BIT(TIMERx->SMCON, TIMER_SMCON_ECM2EN_MSK); + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPOL_MSK, polarity << TIMER_SMCON_ETPOL_POS); + return; +} + +/** + * @brief Time Slave configuration + * @param hperh: pointer to a timer_handle_t structure that contains + * the configuration information for TIMER module. + * @param config: The slave configuration structure + * @retval None + */ +static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config) +{ + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, config->input << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); + + switch (config->input) { + case TIMER_TS_ETRF: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + break; + + case TIMER_TS_TI1F_ED: + CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS); + break; + + case TIMER_TS_TI1FP1: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + break; + + case TIMER_TS_TI2FP2: + timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + break; + + default: + break; + } +} + +#ifdef ALD_DMA + +/** + * @brief Timer DMA msel signal configuration + * @param hperh: pointer to a timer_handle_t structure that contains + * the configuration information for TIMER module. + * @param config: DMA configuration structure + * @retval None + */ +static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config) +{ + #if defined (ES32F36xx) + if (hperh == AD16C4T0) + config->msel = DMA_MSEL_TIMER0; + if (hperh == AD16C4T1) + config->msel = DMA_MSEL_TIMER1; + if (hperh == GP32C4T0) + config->msel = DMA_MSEL_TIMER2; + if (hperh == GP32C4T1) + config->msel = DMA_MSEL_TIMER3; + if (hperh == BS16T0) + config->msel = DMA_MSEL_TIMER4; + if (hperh == BS16T1) + config->msel = DMA_MSEL_TIMER5; + if (hperh == GP32C4T0) + config->msel = DMA_MSEL_TIMER6; + if (hperh == GP32C4T1) + config->msel = DMA_MSEL_TIMER7; + #elif defined(ES32F39xx) || defined(ES32F336x) + if (hperh == GP16C4T0) + config->msel = DMA_MSEL_TIMER0; + if (hperh == GP16C4T1) + config->msel = DMA_MSEL_TIMER1; + if (hperh == GP32C4T0) + config->msel = DMA_MSEL_TIMER2; + if (hperh == GP32C4T1) + config->msel = DMA_MSEL_TIMER3; + if (hperh == BS16T0) + config->msel = DMA_MSEL_TIMER4; + if (hperh == BS16T1) + config->msel = DMA_MSEL_TIMER5; + if (hperh == GP16C4T2) + config->msel = DMA_MSEL_TIMER6; + if (hperh == GP16C4T3) + config->msel = DMA_MSEL_TIMER7; + #endif +} + +#endif + +/** + * @} + */ +#endif /* ALD_TIMER */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c new file mode 100644 index 0000000000000000000000000000000000000000..59b7d7105c3b699593d99dffda51d497ffc6ece0 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_trng.c @@ -0,0 +1,305 @@ +/** + ********************************************************************************* + * + * @file ald_trng.c + * @brief TRNG module driver. + * + * @version V1.0 + * @date 26 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_trng.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup TRNG TRNG + * @brief TRNG module driver + * @{ + */ +#ifdef ALD_TRNG + +/** @addtogroup CRYPT_Private_Functions CRYPT Private Functions + * @{ + */ +void trng_reset(trng_handle_t *hperh); +/** + * @} + */ + +/** @defgroup TRNG_Public_Functions TRNG Public Functions + * @{ + */ + +/** @addtogroup TRNG_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * + * @verbatim + ============================================================================== + ##### Initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to initialize the TRNG: + (+) This parameters can be configured: + (++) Word Width + (++) Seed Type + (++) Seed + (++) Start Time + (++) Adjust parameter + + @endverbatim + * @{ + */ + + +/** + * @brief Initializes the TRNG according to the specified + * parameters in the trng_init_t. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_trng_init(trng_handle_t *hperh) +{ + uint32_t tmp = 0; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_TRNG_DATA_WIDTH(hperh->init.data_width)); + assert_param(IS_TRNG_SEED_TYPE(hperh->init.seed_type)); + assert_param(IS_TRNG_ADJC(hperh->init.adjc)); + + __LOCK(hperh); + trng_reset(hperh); + + if (hperh->state == TRNG_STATE_RESET) + __UNLOCK(hperh); + + tmp = TRNG->CR; + + if (hperh->init.adjc == 0) + tmp = (0 << TRNG_CR_ADJM_POS); + else + tmp = (1 << TRNG_CR_ADJM_POS); + + tmp |= ((1 << TRNG_CR_TRNGSEL_POS) | (hperh->init.data_width << TRNG_CR_DSEL_POSS) | + (hperh->init.seed_type << TRNG_CR_SDSEL_POSS) | (hperh->init.adjc << TRNG_CR_ADJC_POSS) | + (hperh->init.posten << TRNG_CR_POSTEN_MSK)); + + TRNG->CR = tmp; + + WRITE_REG(TRNG->SEED, hperh->init.seed); + MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (hperh->init.t_start) << TRNG_CFGR_TSTART_POSS); + + hperh->state = TRNG_STATE_READY; + __UNLOCK(hperh); + return OK; +} +/** + * @} + */ + +/** @addtogroup TRNG_Public_Functions_Group2 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) ald_trng_get_result() API can Get the result. + (+) ald_trng_interrupt_config() API can be helpful to configure TRNG interrupt source. + (+) ald_trng_get_it_status() API can get the status of interrupt source. + (+) ald_trng_get_status() API can get the status of SR register. + (+) ald_trng_get_flag_status() API can get the status of interrupt flag. + (+) ald_trng_clear_flag_status() API can clear interrupt flag. + + @endverbatim + * @{ + */ + +/** + * @brief Get the result. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @retval The resultl + */ +uint32_t ald_trng_get_result(trng_handle_t *hperh) +{ + hperh->state = TRNG_STATE_READY; + hperh->data = hperh->perh->DR; + return (uint32_t)hperh->perh->DR; +} + +/** + * @brief Enable/disable the specified interrupts. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @param it: Specifies the interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref trng_it_t. + * @param state: New state of the specified interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state) +{ + assert_param(IS_TRNG_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + SET_BIT(hperh->perh->IER, it); + else + CLEAR_BIT(hperh->perh->IER, it); + + return; +} + +/** + * @brief Get the status of SR register. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @param status: Specifies the TRNG status type. + * This parameter can be one of the @ref trng_status_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status) +{ + assert_param(IS_TRNG_STATUS(status)); + + if (READ_BIT(hperh->perh->SR, status)) + return SET; + + return RESET; +} + +/** + * @brief Get the status of interrupt source. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @param it: Specifies the interrupt source. + * This parameter can be one of the @ref trng_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it) +{ + assert_param(IS_TRNG_IT(it)); + + if (READ_BIT(hperh->perh->IER, it)) + return SET; + + return RESET; +} + +/** + * @brief Get the status of interrupt flag. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @param flag: Specifies the interrupt flag. + * This parameter can be one of the @ref trng_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag) +{ + assert_param(IS_TRNG_FLAG(flag)); + + if (READ_BIT(hperh->perh->IFR, flag)) + return SET; + + return RESET; +} + +/** + * @brief Clear the interrupt flag. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @param flag: Specifies the interrupt flag. + * This parameter can be one of the @ref trng_flag_t. + * @retval None + */ +void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag) +{ + assert_param(IS_TRNG_FLAG(flag)); + WRITE_REG(hperh->perh->IFCR, flag); + + return; +} + +/** + * @brief Reset the TRNG peripheral. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @retval None + */ +void trng_reset(trng_handle_t *hperh) +{ + TRNG->CR = 0; + TRNG->SEED = 0; + TRNG->CFGR = 0x1FF0707; + TRNG->IER = 0; + TRNG->IFCR = 0xFFFFFFFF; + + hperh->state = TRNG_STATE_READY; + __UNLOCK(hperh); + return; +} + +/** + * @brief This function handles TRNG interrupt request. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @retval None + */ +void ald_trng_irq_handler(trng_handle_t *hperh) +{ + if (ald_trng_get_flag_status(hperh, TRNG_IF_SERR) == SET) { + hperh->state = TRNG_STATE_ERROR; + ald_trng_clear_flag_status(hperh, TRNG_IF_SERR); + if (hperh->err_cplt_cbk) + hperh->err_cplt_cbk(hperh); + return; + } + + if (ald_trng_get_flag_status(hperh, TRNG_IF_DAVLD) == SET) { + hperh->data = hperh->perh->DR; + hperh->state = TRNG_STATE_READY; + ald_trng_clear_flag_status(hperh, TRNG_IF_DAVLD); + if (hperh->trng_cplt_cbk) + hperh->trng_cplt_cbk(hperh); + } + + if (ald_trng_get_flag_status(hperh, TRNG_IF_START) == SET) { + hperh->state = TRNG_STATE_BUSY; + ald_trng_clear_flag_status(hperh, TRNG_IF_START); + if (hperh->init_cplt_cbk) + hperh->init_cplt_cbk(hperh); + } +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_TRNG */ +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c new file mode 100644 index 0000000000000000000000000000000000000000..1ffae7bf0e732c9b47757c3ad5ae77b7037626b6 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_tsense.c @@ -0,0 +1,244 @@ +/** + ********************************************************************************* + * + * @file ald_tsense.c + * @brief TSENSE module driver. + * + * @version V1.0 + * @date 26 Jun 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_tsense.h" +#include "ald_bkpc.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup TSENSE TSENSE + * @brief TSENSE module driver + * @{ + */ +#ifdef ALD_TSENSE + + +/** @defgroup TSENSE_Private_Variables TSENSE Private Variables + * @{ + */ +tsense_cbk __tsense_cbk; +/** + * @} + */ + +/** @defgroup TSENSE_Public_Functions TSENSE Public Functions + * @{ + */ + +/** @addtogroup TSENSE_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * + * @verbatim + ============================================================================== + ##### Initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to initialize the TSENSE: + (+) This parameters can be configured: + (++) Update Cycle + (++) Output Mode + (++) Perscaler + (+) Select TSENSE source clock(default LOSC) + + @endverbatim + * @{ + */ + +/** + * @brief Initializes the TSENSE according to the specified + * @retval None + */ +void ald_tsense_init(void) +{ + uint16_t tempt, temptinv; + uint32_t tscic, tscicinv; + + TSENSE_UNLOCK(); + TSENSE->CR = 0; + + SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); + SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); + MODIFY_REG(TSENSE->CR, TSENSE_CR_TSU_MSK, 0x4 << TSENSE_CR_TSU_POSS); + MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, 0x3 << TSENSE_CR_TOM_POSS); + MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, 0x1 << TSENSE_PSR_PRS_POSS); + + TSENSE->HTGR = 0x1FD0C; + TSENSE->LTGR = 0x21BC1; + tempt = *(volatile uint16_t *)0x80348; + temptinv = *(volatile uint16_t *)0x8034A; + tscic = *(volatile uint32_t *)0x80350; + tscicinv = *(volatile uint32_t *)0x80358; + + if ((tempt == (uint16_t)(~temptinv)) && (tscic == (~tscicinv))) { + TSENSE->TBDR = tempt; + TSENSE->TCALBDR = (tscic & 0x1FFFFFF) >> 6; + } + else { + TSENSE->TBDR = 0x1E00; + TSENSE->TCALBDR = 0x1FE70; + } + + TSENSE_LOCK(); + return; +} + +/** + * @brief Configure the TSENSE source. + * @param sel: TSENSE source type. + * @retval None + */ +void ald_tsense_source_select(tsense_source_sel_t sel) +{ + assert_param(IS_TSENSE_SOURCE_SEL(sel)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, sel << BKPC_PCCR_TSENSECS_POSS); + + if (sel == TSENSE_SOURCE_LOSC) { + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); + } + else if (sel == TSENSE_SOURCE_LRC) { + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); + } + else { + ; /* do nothing */ + } + + BKPC_LOCK(); + return; +} +/** + * @} + */ + +/** @addtogroup TSENSE_Public_Functions_Group2 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) ald_tsense_get_value() API can get the current temperature. + (+) ald_tsense_get_value_by_it() API can get the current temperature by interrupt. + (+) ald_tsense_irq_handler() API can handle the interrupt request. + + @endverbatim + * @{ + */ + +/** + * @brief Get the current temperature + * @param tsense: The value of current temperature. + * @retval ALD status: + * @arg @ref OK The value is valid + * @arg @ref ERROR The value is invalid + */ +ald_status_t ald_tsense_get_value(uint16_t *tsense) +{ + uint32_t tmp = 0; + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + + while ((!(READ_BIT(TSENSE->IF, TSENSE_IF_TSENSE_MSK))) && (tmp++ < 1000000)); + + if (tmp >= 1000000) + return TIMEOUT; + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + TSENSE_LOCK(); + + if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) + return ERROR; + + *tsense = READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS); + + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + + return OK; +} + +/** + * @brief Get the current temperature by interrupt + * @param cbk: The callback function + * @retval None + */ +void ald_tsense_get_value_by_it(tsense_cbk cbk) +{ + __tsense_cbk = cbk; + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + SET_BIT(TSENSE->IE, TSENSE_IE_TSENSE_MSK); + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + + return; +} + +/** + * @brief This function handles TSENSE interrupt request. + * @retval None + */ +void ald_tsense_irq_handler(void) +{ + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + TSENSE_LOCK(); + + if (__tsense_cbk == NULL) + return; + + if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) { + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + __tsense_cbk(0, ERROR); + + return; + } + + __tsense_cbk(READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS), OK); + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + + return; +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_TSENSE */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..2e5fc5cdd04bf9d82acb06b3e0fa06a236998321 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_uart.c @@ -0,0 +1,1411 @@ +/** + ********************************************************************************* + * + * @file ald_uart.c + * @brief UART module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + * + Initialization and Configuration functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + * @version V1.0 + * @date 21 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The UART driver can be used as follows: + + (#) Declare a uart_handle_t handle structure. + + (#) Initialize the UART low level resources: + (##) Enable the UARTx interface clock. + (##) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure the UART pins (TX as alternate function pull-up, RX as alternate function Input). + (##) NVIC configuration if you need to use interrupt process (ald_uart_send_by_it() + and ald_uart_recv_by_it() APIs): + (+++) Configure the uart interrupt priority. + (+++) Enable the NVIC UART IRQ handle. + (##) DMA Configuration if you need to use DMA process (ald_uart_send_by_dma() + and ald_uart_recv_by_dma() APIs): + (+++) Select the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) in the hperh Init structure. + + (#) Initialize the UART registers by calling the ald_uart_init() API. + + [..] + Three operation modes are available within this driver: + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using ald_uart_send() + (+) Receive an amount of data in blocking mode using ald_uart_recv() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using ald_uart_send_by_it() + (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->tx_cplt_cbk() + (+) Receive an amount of data in non blocking mode using ald_uart_recv_by_it() + (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_cbk() function is executed and user can + add his own code by customization of function pointer hperh->error_cbk() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using ald_uart_send_by_dma() + (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->tx_cplt_cbk() + (+) Receive an amount of data in non blocking mode (DMA) using ald_uart_recv_by_dma() + (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_cbk() function is executed and user can + add his own code by customization of function pointer hperh->error_cbk() + (+) Pause the DMA Transfer using ald_uart_dma_pause() + (+) Resume the DMA Transfer using ald_uart_dma_resume() + (+) Stop the DMA Transfer using ald_uart_dma_stop() + + @endverbatim + ****************************************************************************** + */ + +#include "ald_uart.h" +#include "ald_cmu.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup UART UART + * @brief UART module driver + * @{ + */ +#ifdef ALD_UART + +/** @defgroup UART_Private_Functions UART Private Functions + * @brief UART Private functions + * @{ + */ +#ifdef ALD_DMA +/** + * @brief DMA uart transmit process complete callback. + * @param arg: Pointer to a uart_handle_t structure. + * @retval None + */ +static void uart_dma_send_cplt(void *arg) +{ + uart_handle_t *hperh = (uart_handle_t *)arg; + hperh->tx_count = hperh->tx_size; + + ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE); + hperh->tx_count = 0; + ald_uart_interrupt_config(hperh, UART_IT_TSEMPTY, ENABLE); + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + + return; +} + +/** + * @brief DMA uart receive process complete callback. + * @param arg: Pointer to a uart_handle_t structure. + * @retval None + */ +static void uart_dma_recv_cplt(void *arg) +{ + uart_handle_t *hperh = (uart_handle_t *)arg; + hperh->tx_count = hperh->tx_size; + + ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE); + hperh->rx_count = 0; + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + + return; +} + +/** + * @brief DMA uart communication error callback. + * @param arg: Pointer to a uart_handle_t structure. + * @retval None + */ +static void uart_dma_error(void *arg) +{ + uart_handle_t *hperh = (uart_handle_t *)arg; + + hperh->rx_count = 0; + hperh->tx_count = 0; + hperh->state = UART_STATE_READY; + hperh->err_code |= UART_ERROR_DMA; + ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE); + ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE); + + if (hperh->error_cbk) + hperh->error_cbk(hperh); + + return; +} +#endif + +/** + * @brief This function handles uart Communication Timeout. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: specifies the uart flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick; + + if (timeout == 0) + return ERROR; + + tick = ald_get_tick(); + + /* Waiting for flag */ + while ((ald_uart_get_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + + return OK; +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __uart_send_by_it(uart_handle_t *hperh) +{ + if ((hperh->state & UART_STATE_TX_MASK) == 0x0) + return BUSY; + + hperh->perh->TXBUF = (uint8_t)(*hperh->tx_buf++ & 0x00FF); + hperh->tx_count++; + + if (hperh->tx_count >= hperh->tx_size) { + ald_uart_interrupt_config(hperh, UART_IT_TFTH, DISABLE); + ald_uart_interrupt_config(hperh, UART_IT_TSEMPTY, ENABLE); + } + + return OK; +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param hperh: pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __uart_end_send_by_it(uart_handle_t *hperh) +{ + ald_uart_interrupt_config(hperh, UART_IT_TSEMPTY, DISABLE); + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __uart_recv_by_it(uart_handle_t *hperh) +{ + if ((hperh->state & UART_STATE_RX_MASK) == 0x0) + return BUSY; + + *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + hperh->rx_count++; + + if (hperh->rx_count >= hperh->rx_size) { + ald_uart_interrupt_config(hperh, UART_IT_RFTH, DISABLE); + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return OK; +} + + +/** + * @} + */ + +/** @defgroup UART_Public_Functions UART Public Functions + * @{ + */ + +/** @defgroup UART_Public_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * + * @verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the UARTx + and configure UARTx param. + (+) For the UARTx only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity + (++) Hardware flow control + (+) For RS485 mode, user also need configure some parameters by + ald_uart_rs485_config(): + (++) Enable/disable normal point mode + (++) Enable/disable auto-direction + (++) Enable/disable address detection invert + (++) Enable/disable address for compare + + @endverbatim + * @{ + */ + +/** + * @brief Reset UART peripheral + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified uart module. + * @retval None + */ +void ald_uart_reset(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + + WRITE_REG(hperh->perh->BRR, 0x0); + WRITE_REG(hperh->perh->LCON, 0x0); + WRITE_REG(hperh->perh->MCON, 0x0); + WRITE_REG(hperh->perh->RS485, 0x0); + WRITE_REG(hperh->perh->SCARD, 0x0); + WRITE_REG(hperh->perh->LIN, 0x0); + WRITE_REG(hperh->perh->RTOR, 0x0); + WRITE_REG(hperh->perh->FCON, 0x0); + WRITE_REG(hperh->perh->IDR, 0xFFF); + hperh->err_code = UART_ERROR_NONE; + hperh->state = UART_STATE_RESET; + + __UNLOCK(hperh); + return; +} + +/** + * @brief Initializes the UARTx according to the specified + * parameters in the uart_handle_t. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +void ald_uart_init(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_BAUDRATE(hperh->init.baud)); + assert_param(IS_UART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_UART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_UART_PARITY(hperh->init.parity)); + assert_param(IS_UART_MODE(hperh->init.mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); + + ald_uart_reset(hperh); + + MODIFY_REG(hperh->perh->LCON, UART_LCON_DLS_MSK, hperh->init.word_length << UART_LCON_DLS_POSS); + MODIFY_REG(hperh->perh->LCON, UART_LCON_STOP_MSK, hperh->init.stop_bits << UART_LCON_STOP_POS); + + if ((hperh->init.parity) != UART_PARITY_NONE) { + SET_BIT(hperh->perh->LCON, UART_LCON_PE_MSK); + + if ((hperh->init.parity) == UART_PARITY_ODD) + CLEAR_BIT(hperh->perh->LCON, UART_LCON_PS_MSK); + + if ((hperh->init.parity) == UART_PARITY_EVEN) + SET_BIT(hperh->perh->LCON, UART_LCON_PS_MSK); + } + + MODIFY_REG(hperh->perh->MCON, UART_MCON_AFCEN_MSK, hperh->init.fctl << UART_MCON_AFCEN_POS); + + hperh->perh->BRR = (ald_cmu_get_pclk1_clock() + (hperh->init.baud >> 1)) / hperh->init.baud; + + if (hperh->init.mode == UART_MODE_LIN) + SET_BIT(hperh->perh->LIN, UART_LIN_LINEN_MSK); + else if (hperh->init.mode == UART_MODE_IrDA) + SET_BIT(hperh->perh->MCON, UART_MCON_IREN_MSK); + else if (hperh->init.mode == UART_MODE_RS485) + SET_BIT(hperh->perh->RS485, UART_RS485_AADEN_MSK); + else if (hperh->init.mode == UART_MODE_HDSEL) + SET_BIT(hperh->perh->MCON, UART_MCON_HDEN_MSK); + else if (hperh->init.mode == UART_MODE_SCARD) + SET_BIT(hperh->perh->SCARD, UART_SCARD_SCEN_MSK); + else + ; /* do nothing */ + + SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK); + SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK); + CLEAR_BIT(hperh->perh->FCON, UART_FCON_TXTH_MSK); + CLEAR_BIT(hperh->perh->FCON, UART_FCON_RXTH_MSK); + SET_BIT(hperh->perh->LCON, UART_LCON_RXEN_MSK); + SET_BIT(hperh->perh->LCON, UART_LCON_TXEN_MSK); + + hperh->state = UART_STATE_READY; + hperh->err_code = UART_ERROR_NONE; + return; +} + +/** + * @brief Configure the RS485 mode according to the specified + * parameters in the uart_rs485_config_t. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @param config: Specifies the RS485 parameters. + * @retval None + */ +void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_FUNC_STATE(config->normal)); + assert_param(IS_FUNC_STATE(config->dir)); + assert_param(IS_FUNC_STATE(config->invert)); + + MODIFY_REG(hperh->perh->RS485, UART_RS485_AADNEN_MSK, config->normal << UART_RS485_AADNEN_POS); + MODIFY_REG(hperh->perh->RS485, UART_RS485_AADACEN_MSK, config->dir << UART_RS485_AADACEN_POS); + MODIFY_REG(hperh->perh->RS485, UART_RS485_AADINV_MSK, config->invert << UART_RS485_AADINV_POS); + MODIFY_REG(hperh->perh->RS485, UART_RS485_ADDR_MSK, config->addr << UART_RS485_ADDR_POSS); + + return; +} + +/** + * @brief Configure the smart card mode according to the specified + * parameters in the uart_scard_config_t. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @param config: Specifies the scard parameters. + * @retval None + */ +void ald_uart_scard_config(uart_handle_t *hperh, uart_scard_config_t *config) +{ + assert_param(IS_UART_SCARD(hperh->perh)); + assert_param(IS_UART_SCARD_CLK(config->clk_div)); + + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_BLEN_MSK, config->block_len << UART_SCARD_BLEN_POSS); + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_GT_MSK, config->pt << UART_SCARD_GT_POSS); + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_SCCNT_MSK, config->retry << UART_SCARD_SCCNT_POSS); + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_PSC_MSK, config->clk_div << UART_SCARD_PSC_POSS); + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_SCLKEN_MSK, config->clk_out << UART_SCARD_SCLKEN_POS); + + return; +} + + + +/** + * @} + */ + +/** @defgroup UART_Public_Functions_Group2 IO operation functions + * @brief UART Transmit and Receive functions + * @verbatim + ============================================================================== + # IO operation functions # + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the UART data transfers. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The Status of all data processing is returned by the same function + after finishing transfer. + (++) Non blocking mode: The communication is performed using Interrupts + or DMA, these APIs return the Status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks + will be executed respectively at the end of the transmit or receive process. + The hperh->error_cbk() user callback will be executed when + a communication error is detected. + + (#) Blocking mode APIs are: + (++) ald_uart_send() + (++) ald_uart_recv() + + (#) Non Blocking mode APIs with Interrupt are: + (++) ald_uart_send_by_it() + (++) ald_uart_recv_by_it() + (++) ald_uart_irq_handler() + + (#) Non Blocking mode functions with DMA are: + (++) ald_uart_send_by_dma() + (++) ald_uart_recv_by_dma() + (++) ald_uart_dma_pause() + (++) ald_uart_dma_resume() + (++) ald_uart_dma_stop() + + (#) A set of transfer complete callbacks are provided in non blocking mode: + (++) hperh->tx_cplt_cbk() + (++) hperh->rx_cplt_cbk() + (++) hperh->error_cbk() + + @endverbatim + * @{ + */ + +/** + * @brief Sends an amount of data in blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); + + hperh->tx_size = size; + hperh->tx_count = 0; + SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK); + + while (size-- > 0) { + if (uart_wait_flag(hperh, UART_STATUS_TFTH, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + hperh->perh->TXBUF = (*buf++ & 0xFF); + hperh->tx_count++; + } + + if (uart_wait_flag(hperh, UART_STATUS_TFEMPTY, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receives an amount of data in blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + + hperh->rx_size = size; + hperh->rx_count = 0; + SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK); + + while (size-- > 0) { + if (uart_wait_flag(hperh, UART_STATUS_RFTH, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + *buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + hperh->rx_count++; + } + + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + __UNLOCK(hperh); + + return OK; + +} + +/** + * @brief Sends an amount of data in blocking mode. + Don't care about device lock. This is for RTOS. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_send_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; + + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); + + hperh->tx_size = size; + hperh->tx_count = 0; + SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK); + + while (size-- > 0) { + if (uart_wait_flag(hperh, UART_STATUS_TFTH, SET, timeout) != OK) { + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + hperh->perh->TXBUF = (*buf++ & 0xFF); + hperh->tx_count++; + } + + if (uart_wait_flag(hperh, UART_STATUS_TFEMPTY, SET, timeout) != OK) { + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + return OK; +} + +/** + * @brief Receives an amount of data in blocking mode. + Don't care about device lock. This is for RTOS. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; + + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + + hperh->rx_size = size; + hperh->rx_count = 0; + SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK); + + while (size-- > 0) { + if (uart_wait_flag(hperh, UART_STATUS_RFTH, SET, timeout) != OK) { + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + *buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + hperh->rx_count++; + } + + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + return OK; + +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = 0; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); + + __UNLOCK(hperh); + SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK); + SET_BIT(hperh->perh->ICR, UART_ICR_TFTH_MSK); + ald_uart_interrupt_config(hperh, UART_IT_TFTH, ENABLE); + + return OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = 0; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + + __UNLOCK(hperh); + SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK); + SET_BIT(hperh->perh->ICR, UART_ICR_RFTH_MSK); + ald_uart_interrupt_config(hperh, UART_IT_RFTH, ENABLE); + return OK; +} + + +/** + * @brief Receives an frame of data in non blocking mode + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Max length of frame. + * @param t_out: Timeout duration. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv_frame_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t t_out) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL ) || (t_out == 0) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = 0; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + + __UNLOCK(hperh); + SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK); + SET_BIT(hperh->perh->ICR, UART_ICR_RFTH_MSK); + SET_BIT(hperh->perh->RTOR, UART_RTOR_RTOEN_MSK); + MODIFY_REG(hperh->perh->RTOR, UART_RTOR_RTO_MSK, t_out << UART_RTOR_RTO_POSS); + ald_uart_interrupt_config(hperh, UART_IT_RFTH, ENABLE); + ald_uart_interrupt_config(hperh, UART_IT_RXTO, ENABLE); + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as UART transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = 0; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + /* Set the dma parameters */ + hperh->hdmatx.cplt_cbk = uart_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = uart_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXBUF; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + if ((hperh->perh == UART4) || (hperh->perh == UART5)) { + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_UART45_TXEMPTY; + } else { + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_UART_TXEMPTY; + } + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.channel = channel; + + if (hperh->init.mode == UART_MODE_RS485) { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + if (hperh->perh == UART0) + hperh->hdmatx.config.msel = DMA_MSEL_UART0; + else if (hperh->perh == UART1) + hperh->hdmatx.config.msel = DMA_MSEL_UART1; + else if (hperh->perh == UART2) + hperh->hdmatx.config.msel = DMA_MSEL_UART2; + else if (hperh->perh == UART3) + hperh->hdmatx.config.msel = DMA_MSEL_UART3; + else if (hperh->perh == UART4) + hperh->hdmatx.config.msel = DMA_MSEL_UART4; + else if (hperh->perh == UART5) + hperh->hdmatx.config.msel = DMA_MSEL_UART5; + else + ; /* do nothing */ + + ald_dma_config_basic(&hperh->hdmatx); + + __UNLOCK(hperh); + SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK); + ald_uart_clear_flag_status(hperh, UART_IF_TBC); + ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, ENABLE); + + + return OK; +} + +/** + * @brief Receives an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param channel: DMA channel as UART receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + /* Set the dma parameters */ + hperh->hdmarx.cplt_cbk = uart_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = uart_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->RXBUF; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + if ((hperh->perh == UART4) || (hperh->perh == UART5)) { + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART45_RNR; + } else { + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART_RNR; + } + + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmarx.config.channel = channel; + + if (hperh->init.mode == UART_MODE_RS485) { + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + if (hperh->perh == UART0) + hperh->hdmarx.config.msel = DMA_MSEL_UART0; + else if (hperh->perh == UART1) + hperh->hdmarx.config.msel = DMA_MSEL_UART1; + else if (hperh->perh == UART2) + hperh->hdmarx.config.msel = DMA_MSEL_UART2; + else if (hperh->perh == UART3) + hperh->hdmarx.config.msel = DMA_MSEL_UART3; + else if (hperh->perh == UART4) + hperh->hdmatx.config.msel = DMA_MSEL_UART4; + else if (hperh->perh == UART5) + hperh->hdmatx.config.msel = DMA_MSEL_UART5; + else + ; + + __UNLOCK(hperh); + ald_dma_config_basic(&hperh->hdmarx); + SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK); + ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, ENABLE); + + return OK; +} + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_dma_pause(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE); + ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE); + return OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_dma_resume(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, ENABLE); + ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, ENABLE); + return OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_dma_stop(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE); + ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE); + hperh->state = UART_STATE_READY; + return OK; +} +#endif + +/** + * @brief This function handles UART interrupt request. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval None + */ +void ald_uart_irq_handler(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + /* Handle parity error */ + if (((ald_uart_get_status(hperh, UART_STATUS_PERR)) != RESET) && \ + (ald_uart_get_state(hperh)) == UART_STATE_RX_MASK) + hperh->err_code |= UART_ERROR_PE; + + /* Handle frame error */ + if (((ald_uart_get_status(hperh, UART_STATUS_FERR)) != RESET) && \ + (ald_uart_get_state(hperh)) == UART_STATE_RX_MASK) + hperh->err_code |= UART_ERROR_FE; + + /* Handle rx overflow error */ + if (((ald_uart_get_status(hperh, UART_STATUS_RFOERR)) != RESET) && \ + (ald_uart_get_state(hperh)) == UART_STATE_RX_MASK) + hperh->err_code |= UART_ERROR_ORE; + + /* Handle tx overflow error */ + if (((ald_uart_get_status(hperh, UART_STATUS_TFOERR)) != RESET) && \ + (ald_uart_get_state(hperh)) == UART_STATE_TX_MASK) + hperh->err_code |= UART_ERROR_ORE; + + /* Receive */ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RFTH)) != RESET) { + ald_uart_clear_flag_status(hperh, UART_IF_RFTH); + __uart_recv_by_it(hperh); + } + + /* Transmit */ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TFTH)) != RESET) { + ald_uart_clear_flag_status(hperh, UART_IF_TFTH); + __uart_send_by_it(hperh); + } + + /* End Transmit */ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TBC)) != RESET) { + ald_uart_clear_flag_status(hperh, UART_IF_TBC); + __uart_end_send_by_it(hperh); + } + + /* Receive frame timeout*/ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RXTO)) != RESET) { + ald_uart_clear_flag_status(hperh, UART_IF_RXTO); + + ald_uart_interrupt_config(hperh, UART_IT_RXTO, DISABLE); + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + /* Handle error state */ + if (hperh->err_code != UART_ERROR_NONE) { + hperh->state = UART_STATE_READY; + + if (hperh->error_cbk) + hperh->error_cbk(hperh); + } +} +/** + * @} + */ + +/** @defgroup UART_Public_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART: + (+) ald_uart_interrupt_config() API can be helpful to configure UART interrupt source. + (+) ald_uart_dma_req_config() API can be helpful to configure UART DMA request. + (+) ald_uart_tx_fifo_config() API can be helpful to configure UART TX FIFO paramters. + (+) ald_uart_rx_fifo_config() API can be helpful to configure UART RX FIFO paramters. + (+) ald_uart_lin_send_break() API can send a frame of break in LIN mode. + (+) ald_uart_lin_detect_break_len_config() API can be helpful to configure the length of break frame. + (+) ald_uart_auto_baud_config() API can be helpful to configure detection data mode. + (+) ald_uart_get_it_status() API can get the status of interrupt source. + (+) ald_uart_get_status() API can get the status of UART_SR register. + (+) ald_uart_get_flag_status() API can get the status of UART flag. + (+) ald_uart_get_mask_flag_status() API can get status os flag and interrupt source. + (+) ald_uart_clear_flag_status() API can clear UART flag. + + @endverbatim + * @{ + */ + +/** + * @brief Enable/disable the specified UART interrupts. + * @param hperh: Pointer to a uart_handle_t structure. + * @param it: Specifies the UART interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref uart_it_t. + * @param state: New state of the specified UART interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IER = it; + else + hperh->perh->IDR = it; + + return; +} + +/** + * @brief Configure UART DMA request. + * @param hperh: Pointer to a uart_handle_t structure. + * @param req: The type of DMA request. + * @param state: New state of the specified DMA request. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (req == UART_DMA_REQ_TX) { + if (state == ENABLE) + SET_BIT(hperh->perh->MCON, UART_MCON_TXDMAEN_MSK); + else + CLEAR_BIT(hperh->perh->MCON, UART_MCON_TXDMAEN_MSK); + } + else { + if (state == ENABLE) + SET_BIT(hperh->perh->MCON, UART_MCON_RXDMAEN_MSK); + else + CLEAR_BIT(hperh->perh->MCON, UART_MCON_RXDMAEN_MSK); + } + + return; +} + +/** + * @brief Configure transmit fifo parameters. + * @param hperh: Pointer to a uart_handle_t structure. + * @param config: Transmit fifo trigger level. + * @param level: Transmit fifo level. + * @retval None + */ +void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config, uint8_t level) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_TXFIFO_TYPE(config)); + + SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK); + MODIFY_REG(hperh->perh->FCON, UART_FCON_TXTH_MSK, config << UART_FCON_TXTH_POSS); + MODIFY_REG(hperh->perh->FCON, UART_FCON_TXFL_MSK, config << UART_FCON_TXFL_POSS); + + return; +} + +/** + * @brief Configure receive fifo parameters. + * @param hperh: Pointer to a uart_handle_t structure. + * @param config: Receive fifo trigger level. + * @param level: Receive fifo level. + * @retval None + */ +void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_RXFIFO_TYPE(config)); + + SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK); + MODIFY_REG(hperh->perh->FCON, UART_FCON_RXTH_MSK, config << UART_FCON_RXTH_POSS); + MODIFY_REG(hperh->perh->FCON, UART_FCON_RXFL_MSK, level << UART_FCON_RXFL_POSS); + + return; +} + +/** + * @brief Enable/Disable break signal detect interrup. + * @param hperh: Pointer to a uart_handle_t structure. + * @param status: The new status. + * @retval None + */ +void uart_lin_break_detect_irq(uart_handle_t *hperh, type_func_t status) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if (status == ENABLE) { + SET_BIT(hperh->perh->IER, UART_IER_LINBK_MSK); + } + else { + CLEAR_BIT(hperh->perh->IER, UART_IER_LINBK_MSK); + } + + return; +} + +/** + * @brief request to send a frame of break. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval None + */ +void ald_uart_lin_send_break(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + SET_BIT(hperh->perh->LIN, UART_LIN_LINBKREQ_MSK); + + hperh->perh->TXBUF = (0x55); + + return; +} + +/** + * @brief Configure the length of break frame to be detect. + * @param hperh: Pointer to a uart_handle_t structure. + * @param len: Length of break frame. + * @arg LIN_BREAK_LEN_10B + * @arg LIN_BREAK_LEN_11B + * @retval None + */ +void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_LIN_BREAK_LEN(len)); + + MODIFY_REG(hperh->perh->LIN, UART_LIN_LINBDL_MSK, len << UART_LIN_LINBDL_POS); + + return; +} + +/** + * @brief Configure the mode of auto-baud-rate detect. + * @param hperh: Pointer to a uart_handle_t structure. + * @param mode: The mode of auto-baud-rate detect. + * @arg UART_ABRMOD_1_TO_0 + * @arg UART_ABRMOD_1 + * @arg UART_ABRMOD_0_TO_1 + * @retval None + */ +void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_AUTO_BAUD_MODE(mode)); + + MODIFY_REG(hperh->perh->MCON, UART_MCON_ABRMOD_MSK, mode << UART_MCON_ABRMOD_POSS); + + return; +} + +/** + * @brief Send address in RS485 mode. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @param addr: the address of RS485 device. + * @param timeout: Timeout duration + * @retval The ALD status. + */ +ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + + SET_BIT(hperh->state, UART_STATE_TX_MASK); + + if (uart_wait_flag(hperh, UART_STATUS_TFEMPTY, SET, timeout) != OK) { + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + WRITE_REG(hperh->perh->TXBUF, (addr | 0x100)); + + if (uart_wait_flag(hperh, UART_STATUS_TFEMPTY, SET, timeout) != OK) { + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + + return OK; +} + +/** + * @brief Get the status of UART interrupt source. + * @param hperh: Pointer to a uart_handle_t structure. + * @param it: Specifies the UART interrupt source. + * This parameter can be one of the @ref uart_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it) +{ + it_status_t status = RESET; + + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IT(it)); + + if (hperh->perh->IVS & it) + status = SET; + + return status; +} + +/** + * @brief Get the status of UART_SR register. + * @param hperh: Pointer to a uart_handle_t structure. + * @param status: Specifies the UART status type. + * This parameter can be one of the @ref uart_status_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_STATUS(status)); + + if (hperh->perh->STAT & status) + return SET; + + return RESET; +} + + +/** + * @brief Get the status of UART interrupt flag. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the UART interrupt flag. + * This parameter can be one of the @ref uart_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** + * @brief Get the status of interrupt flag and interupt source. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the UART interrupt flag. + * This parameter can be one of the @ref uart_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); + + if (hperh->perh->IFM & flag) + return SET; + + return RESET; +} + +/** + * @brief Clear the UART interrupt flag. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the UART interrupt flag. + * This parameter can be one of the @ref uart_flag_t. + * @retval None + */ +void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); + + hperh->perh->ICR = flag; + return; +} +/** + * @} + */ + +/** @defgroup UART_Public_Functions_Group4 Peripheral State and Errors functions + * @brief UART State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + UART communication process, return Peripheral Errors occurred during communication + process + (+) ald_uart_get_state() API can be helpful to check in run-time the state of the UART peripheral. + (+) ald_uart_get_error() check in run-time errors that could be occurred during communication. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the UART state. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval ALD state + */ +uart_state_t ald_uart_get_state(uart_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the UART error code + * @param hperh: Pointer to a uart_handle_t structure. + * @retval UART Error Code + */ +uint32_t ald_uart_get_error(uart_handle_t *hperh) +{ + return hperh->err_code; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* ALD_UART */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c new file mode 100644 index 0000000000000000000000000000000000000000..4749587ddbac7d89726ac2edc011ffe4317fd66d --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_usb.c @@ -0,0 +1,1387 @@ +/** + ********************************************************************************* + * + * @file ald_usb.c + * @brief USB module driver. + * + * @version V1.0 + * @date 25 Dec 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "ald_usb.h" +#include "ald_syscfg.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup USB USB + * @brief USB module driver + * @{ + */ +#ifdef ALD_USB +/** + * @defgroup USB_Public_Functions USB Public Function + * @{ + */ +/** @defgroup USB_Public_Functions_Group1 Base functions + * @brief Base functions + * @{ + */ + +/** + * @brief Gets the number of current frame. + * @retval Number of the frame. + */ +uint32_t ald_usb_frame_number_get(void) +{ + return USB0->FRAME; +} + +/** + * @brief Request the session. + * @param start: true/false. + * @retval None + */ +void ald_usb_otg_session_request(bool start) +{ + if (start) + USB0->DEVCTL |= USB_DEVCTL_SESSION; + else + USB0->DEVCTL &= ~(USB_DEVCTL_SESSION); +} + +/** + * @brief Gets the mode. + * @retval Mode + */ +uint32_t ald_usb_mode_get(void) +{ + return USB0->DEVCTL & (USB_DEVCTL_DEV | USB_DEVCTL_HOST + | USB_DEVCTL_SESSION | USB_DEVCTL_VBUS_M); +} + +/** + * @brief Enable/Disable the high mode. + * @param enable: ENABLE/DISABLE. + * @retval None + */ +void ald_usb_high_speed_enable(bool enable) +{ + if (enable) + USB0->POWER |= USB_POWER_HS_EN; + else + USB0->POWER &= ~(USB_POWER_HS_EN); +} + +/** + * @brief Gets the speed of the device. + * @retval Type of the speed. + */ +uint32_t ald_usb_device_speed_get(void) +{ + if (USB0->POWER & USB_POWER_HS_EN) + return USB_HIGH_SPEED; + + return USB_FULL_SPEED; +} + +/** + * @brief Gets the number of the endpoint. + * @retval Number of the endpoint. + */ +uint32_t ald_usb_num_ep_get( void) +{ + return NUM_USB_EP; +} + +/** + * @brief Reset USB Control. + * @retval None + */ +void ald_usb_control_reset(void) +{ + ald_rmu_reset_periperal(RMU_PERH_USB); +} + +/** + * @brief Output USB clock via PA15, 60MHz/256=234.375KHz. + * @retval None + */ +void ald_usb_clock_output(void) +{ + SYSCFG_UNLOCK(); + SYSCFG->TESTKEY = 0x5A962814; + SYSCFG->TESTKEY = 0xE7CB69A5; + SYSCFG->USBTEST = 0x43; + + return; +} + +/** + * @brief Starts eye diagram for high-speed host. + * @param buf: Buffer for eye diagram. + * @param len: Length of the buffer. + * @retval Status, 0 means success, other values means failure. + */ +int ald_usb_eye_diagram_start(uint8_t *buf, uint16_t len) +{ + if (len < 53) + return -1; + + ald_usb_ep_data_put(0, buf, 53); + USB0->TEST = 0x08 | 0x90; + ald_delay_ms(20); + USB0->CSR0L = USB_CSRL0_TXRDY; + + return 0; +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group2 Device functions + * @brief Device functions + * @{ + */ + +/** + * @brief Gets the address. + * @retval Address. + */ +uint8_t ald_usb_dev_get_addr(void) +{ + return USB0->FADDR; +} + +/** + * @brief Sets the address. + * @param addr: The address which will be set. + * @retval None + */ +void ald_usb_dev_set_addr(uint8_t addr) +{ + USB0->FADDR = addr; +} + +/** + * @brief Enable connection. + * @retval None + */ +void ald_usb_dev_connect(void) +{ + USB0->POWER |= USB_POWER_SOFTCONN; +} + +/** + * @brief Disable connection. + * @retval None + */ +void ald_usb_dev_disconnect(void) +{ + USB0->POWER &= ~(USB_POWER_SOFTCONN); +} + +/** + * @brief Configure the endpoint in device mode. + * @param ep_idx: Index of the endpoint + * @param p_max: Size of the maximum package. + * @param flags: Flags of the endpoint. + * @retval None + */ +void ald_usb_dev_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t flags) +{ + uint32_t tmp = 0; + + if (flags & USB_EP_DEV_IN) { + USB0->CSR[ep_idx - 1].TXxMAXP = p_max; + if (flags & USB_EP_AUTO_SET) + tmp |= USB_TXCSRH1_AUTOSET; + if ((flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + tmp |= USB_TXCSRH1_ISO; + + USB0->CSR[ep_idx - 1].TXxCSRH = (uint8_t)tmp; + USB0->CSR[ep_idx - 1].TXxCSRL = USB_TXCSRL1_CLRDT; + } + else { + USB0->CSR[ep_idx - 1].RXxMAXP = p_max; + if (flags & USB_EP_AUTO_CLEAR) + tmp = USB_RXCSRH1_AUTOCL; + if (flags & USB_EP_DIS_NYET) + tmp |= USB_RXCSRH1_DISNYET; + + if ((flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + tmp |= USB_RXCSRH1_ISO; + + USB0->CSR[ep_idx - 1].RXxCSRH = (uint8_t)tmp; + USB0->CSR[ep_idx - 1].RXxCSRL = USB_RXCSRL1_CLRDT; + } +} + +/** + * @brief Gets the parameters of the endpoint. + * @param ep_idx: Index of the endpoint + * @param p_max: Size of the maximum package. + * @param flags: Flags of the endpoint. + * @retval None + */ +void ald_usb_dev_ep_get_config(uint32_t ep_idx, uint32_t *p_max, uint32_t *flags) +{ + uint32_t tmp; + + if (*flags & USB_EP_DEV_IN) { + *flags = USB_EP_DEV_IN; + *p_max = (uint32_t)USB0->CSR[ep_idx - 1].TXxMAXP; + tmp = (uint32_t)USB0->CSR[ep_idx - 1].TXxCSRH; + + if (tmp & USB_TXCSRH1_AUTOSET) + *flags |= USB_EP_AUTO_SET; + if (tmp & USB_TXCSRH1_ISO) + *flags |= USB_EP_MODE_ISOC; + else + *flags |= USB_EP_MODE_BULK; + } + else { + *flags = USB_EP_DEV_OUT; + *p_max = (uint32_t)USB0->CSR[ep_idx - 1].RXxMAXP; + tmp = (uint32_t)USB0->CSR[ep_idx - 1].RXxCSRH; + + if (tmp & USB_RXCSRH1_AUTOCL) + *flags |= USB_EP_AUTO_CLEAR; + if (tmp & USB_RXCSRH1_ISO) + *flags |= USB_EP_MODE_ISOC; + else + *flags |= USB_EP_MODE_BULK; + } +} + +/** + * @brief Acknowledge the data from the host. + * @param ep_idx: Index of the endpoint + * @param last: true/false + * @retval None + */ +void ald_usb_dev_ep_data_ack(uint32_t ep_idx, bool last) +{ + if (ep_idx == USB_EP_0) + USB0->CSR0L = USB_CSRL0_RXRDYC | (last ? USB_CSRL0_DATAEND : 0); + else + USB0->CSR[ep_idx - 1].RXxCSRL &= ~(USB_RXCSRL1_RXRDY); +} + +/** + * @brief Stall the endpoint. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_dev_ep_stall(uint32_t ep_idx, uint32_t flags) +{ + if (ep_idx == USB_EP_0) + USB0->CSR0L |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC); + else if (flags == USB_EP_DEV_IN) + USB0->CSR[ep_idx - 1].TXxCSRL |= USB_TXCSRL1_STALL; + else + USB0->CSR[ep_idx - 1].RXxCSRL |= USB_RXCSRL1_STALL; +} + +/** + * @brief Cancel the stall status. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_dev_ep_stall_clear(uint32_t ep_idx, uint32_t flags) +{ + if (ep_idx == USB_EP_0) + USB0->CSR0L &= ~USB_CSRL0_STALLED; + else if (flags == USB_EP_DEV_IN) { + USB0->CSR[ep_idx - 1].TXxCSRL &= ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); + USB0->CSR[ep_idx - 1].TXxCSRL |= USB_TXCSRL1_CLRDT; + } + else { + USB0->CSR[ep_idx - 1].RXxCSRL &= ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + USB0->CSR[ep_idx - 1].RXxCSRL |= USB_RXCSRL1_CLRDT; + } +} + +/** + * @brief Clear the status of the endpoint. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_dev_ep_status_clear(uint32_t ep_idx, uint32_t flags) +{ + if (ep_idx == USB_EP_0) { + if (flags & USB_DEV_EP0_OUT_PKTRDY) + USB0->CSR0L |= USB_CSRL0_RXRDYC; + if (flags & USB_DEV_EP0_SETUP_END) + USB0->CSR0L |= USB_CSRL0_SETENDC; + if (flags & USB_DEV_EP0_SENT_STALL) + USB0->CSR0L &= ~(USB_DEV_EP0_SENT_STALL); + } + else { + USB0->CSR[ep_idx - 1].TXxCSRL &= ~(flags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN)); + USB0->CSR[ep_idx - 1].RXxCSRL &= ~((flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR + | USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT); + } +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group3 Host functions + * @brief Host functions + * @{ + */ +/** + * @brief Gets the device's address. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval Address + */ +uint32_t ald_usb_host_addr_get(uint32_t ep_idx, uint32_t flags) +{ + if (flags & USB_EP_HOST_OUT) + return USB0->ADDR[ep_idx].TXxFUNCADDR; + else + return USB0->ADDR[ep_idx].RXxFUNCADDR; +} + +/** + * @brief Sets the device's address. + * @param ep_idx: Index of the endpoint. + * @param addr: The device's address. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags) +{ + if (flags & USB_EP_HOST_OUT) + USB0->ADDR[ep_idx].TXxFUNCADDR = addr; + else + USB0->ADDR[ep_idx].RXxFUNCADDR = addr; +} + +/** + * @brief Configure the endpoint in host mode. + * @param ep_idx: Index of the endpoint. + * @param p_max: Size of the maximum package. + * @param nak_val: Value of the nack. + * @param t_ep: Target endpoint. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags) +{ + uint32_t tmp; + + if (ep_idx == USB_EP_0) { + USB0->NACK = nak_val; + + if (flags & USB_EP_SPEED_HIGH) + USB0->TYPE0 = USB_TYPE0_SPEED_HIGH; + else if (flags & USB_EP_SPEED_FULL) + USB0->TYPE0 = USB_TYPE0_SPEED_FULL; + else + USB0->TYPE0 = USB_TYPE0_SPEED_LOW; + } + else { + tmp = t_ep; + + if (flags & USB_EP_SPEED_HIGH) + tmp |= USB_TXTYPE1_SPEED_HIGH; + else if (flags & USB_EP_SPEED_FULL) + tmp |= USB_TXTYPE1_SPEED_FULL; + else + tmp |= USB_TXTYPE1_SPEED_LOW; + + switch (flags & USB_EP_MODE_MASK) { + case USB_EP_MODE_BULK: + tmp |= USB_TXTYPE1_PROTO_BULK; + break; + + case USB_EP_MODE_ISOC: + tmp |= USB_TXTYPE1_PROTO_ISOC; + break; + + case USB_EP_MODE_INT: + tmp |= USB_TXTYPE1_PROTO_INT; + break; + + case USB_EP_MODE_CTRL: + tmp |= USB_TXTYPE1_PROTO_CTRL; + break; + } + + if (flags & USB_EP_HOST_OUT) { + USB0->CSR[ep_idx - 1].TXxTYPE = tmp; + USB0->CSR[ep_idx - 1].TXxINTERVAL = nak_val; + USB0->CSR[ep_idx - 1].TXxMAXP = p_max; + + tmp = 0; + if (flags & USB_EP_AUTO_SET) + tmp |= USB_TXCSRH1_AUTOSET; + USB0->CSR[ep_idx - 1].TXxCSRH = (uint8_t)tmp; + } + else { + USB0->CSR[ep_idx - 1].RXxTYPE = tmp; + USB0->CSR[ep_idx - 1].RXxINTERVAL = nak_val; + USB0->CSR[ep_idx - 1].RXxMAXP = p_max; + + tmp = 0; + if (flags & USB_EP_AUTO_CLEAR) + tmp |= USB_RXCSRH1_AUTOCL; + if (flags & USB_EP_AUTO_REQUEST) + tmp |= USB_RXCSRH1_AUTORQ; + + USB0->CSR[ep_idx - 1].RXxCSRH = (uint8_t)tmp; + } + } +} + +/** + * @brief Acknowledge the data in host mode. + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_ep_data_ack(uint32_t ep_idx) +{ + if (ep_idx == USB_EP_0) + USB0->CSR0L &= ~(USB_CSRL0_RXRDY); + else + USB0->CSR[ep_idx - 1].RXxCSRL &= ~(USB_RXCSRL1_RXRDY); +} + +/** + * @brief Toggle the data in host mode. + * @param ep_idx: Index of the endpoint. + * @param toggle: true/false. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_ep_data_toggle(uint32_t ep_idx, bool toggle, uint32_t flags) +{ + uint32_t tmp = 0; + + if (toggle) { + if (ep_idx == USB_EP_0) + tmp = USB_CSRH0_DT; + else if (flags == USB_EP_HOST_IN) + tmp = USB_RXCSRH1_DT; + else + tmp = USB_TXCSRH1_DT; + } + + if (ep_idx == USB_EP_0) { + USB0->CSR0H = ((USB0->CSR0H & ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) | + (tmp | USB_CSRH0_DTWE)); + } + else if (flags == USB_EP_HOST_IN) { + USB0->CSR[ep_idx - 1].RXxCSRH = ((USB0->CSR[ep_idx - 1].RXxCSRH & + ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) | + (tmp | USB_RXCSRH1_DTWE)); + } + else { + USB0->CSR[ep_idx - 1].TXxCSRH = ((USB0->CSR[ep_idx - 1].TXxCSRH & + ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) | + (tmp | USB_TXCSRH1_DTWE)); + } +} + +/** + * @brief Clear the status of endpoint in host mode. + * @param ep_idx: Index of the endpoint. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_ep_status_clear(uint32_t ep_idx, uint32_t flags) +{ + if (ep_idx == USB_EP_0) { + USB0->CSR0L &= ~flags; + } + else { + USB0->CSR[ep_idx - 1].TXxCSRL &= ~flags; + USB0->CSR[ep_idx - 1].RXxCSRL &= ~flags; + } +} + +/** + * @brief Gets the HUB's address. + * @param ep_idx: Index of the endpoint. + * @param flags: Flags. + * @retval Address + */ +uint32_t ald_usb_host_hub_addr_get(uint32_t ep_idx, uint32_t flags) +{ + if (flags & USB_EP_HOST_OUT) + return USB0->ADDR[ep_idx].TXxHUBADDR; + else + return USB0->ADDR[ep_idx].RXxHUBADDR; +} + +/** + * @brief Sets the HUB's address. + * @param ep_idx: Index of the endpoint. + * @param addr: HUB's address which will be set. + * @param flags: Flags. + * @retval Address + */ +void ald_usb_host_hub_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags) +{ + if (flags & USB_EP_HOST_OUT) + USB0->ADDR[ep_idx].TXxHUBADDR = addr; + else + USB0->ADDR[ep_idx].RXxHUBADDR = addr; + + if (ep_idx == USB_EP_0) { + if (flags & USB_EP_SPEED_FULL) + USB0->TYPE0 |= USB_TYPE0_SPEED_FULL; + else if (flags & USB_EP_SPEED_HIGH) + USB0->TYPE0 |= USB_TYPE0_SPEED_HIGH; + else + USB0->TYPE0 |= USB_TYPE0_SPEED_LOW; + } +} + +/** + * @brief Disable power. + * @retval None + */ +void ald_usb_host_pwr_disable(void) +{ + return; +} + +/** + * @brief Enable power. + * @retval None + */ +void ald_usb_host_pwr_enable(void) +{ + return; +} + +/** + * @brief Configure power in host mode. + * @param flags: Flags + * @retval None + */ +void ald_usb_host_pwr_config(uint32_t flags) +{ + return; +} + +/** + * @brief Disable the fault parameters of the power. + * @retval None + */ +void ald_usb_host_pwr_fault_disable(void) +{ + return; +} + +/** + * @brief Enable the fault parameters of the power. + * @retval None + */ +void ald_usb_host_pwr_fault_enable(void) +{ + return; +} + +/** + * @brief Request data IN(from device to host) + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_request_in(uint32_t ep_idx) +{ + if (ep_idx == USB_EP_0) + USB0->CSR0L = USB_RXCSRL1_REQPKT; + else + USB0->CSR[ep_idx - 1].RXxCSRL = USB_RXCSRL1_REQPKT; +} + +/** + * @brief Clear the status of request IN. + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_request_in_clear(uint32_t ep_idx) +{ + if (ep_idx == USB_EP_0) + USB0->CSR0L &= ~(USB_RXCSRL1_REQPKT); + else + USB0->CSR[ep_idx - 1].RXxCSRL &= ~(USB_RXCSRL1_REQPKT); +} + +/** + * @brief Request data IN at endpoint 0. + * @retval None + */ +void ald_usb_host_request_status(void) +{ + USB0->CSR0L = USB_CSRL0_REQPKT | USB_CSRL0_STATUS; +} + +/** + * @brief Reset the USB's bus. + * @param start: true/false. + * @retval None + */ +void ald_usb_host_reset(bool start) +{ + if (start) + USB0->POWER |= USB_POWER_RESET; + else + USB0->POWER &= ~(USB_POWER_RESET); +} + +/** + * @brief Resume the devices. + * @param start: true/false. + * @retval None + */ +void ald_usb_host_resume(bool start) +{ + if (start) + USB0->POWER |= USB_POWER_RESUME; + else + USB0->POWER &= ~(USB_POWER_RESUME); +} + +/** + * @brief Suspend the devices. + * @retval None + */ +void ald_usb_host_suspend(void) +{ + USB0->POWER |= USB_POWER_SUSPEND; +} + +/** + * @brief Gets the device's speed. + * @retval Type of the speed. + */ +uint32_t ald_usb_host_speed_get(void) +{ + if (USB0->POWER & USB_POWER_HS_M) + return USB_HIGH_SPEED; + + if (USB0->DEVCTL & USB_DEVCTL_FSDEV) + return USB_FULL_SPEED; + + if (USB0->DEVCTL & USB_DEVCTL_LSDEV) + return USB_LOW_SPEED; + + return USB_UNDEF_SPEED; +} + +/** + * @brief Sets the endpoint speed. + * @param ep_idx: Index of the endpoint. + * @param flags: Type of the speed. + * @retval None + */ +void ald_usb_host_ep_speed_set(uint32_t ep_idx, uint32_t flags) +{ + uint32_t tmp; + + if (flags & USB_EP_SPEED_HIGH) + tmp = USB_TYPE0_SPEED_HIGH; + else if (flags & USB_EP_SPEED_FULL) + tmp = USB_TYPE0_SPEED_FULL; + else + tmp = USB_TYPE0_SPEED_LOW; + + if (ep_idx == USB_EP_0) + USB0->TYPE0 |= tmp; + else if (flags & USB_EP_HOST_OUT) + USB0->CSR[ep_idx - 1].TXxTYPE |= tmp; + else + USB0->CSR[ep_idx - 1].RXxTYPE |= tmp; +} + +/** + * @brief Ping the endpoint. + * @param ep_idx: Index of the endpoint. + * @param enable: ENABLE/DISABLE. + * @retval None + */ +void ald_usb_host_ep_ping(uint32_t ep_idx, bool enable) +{ + if (enable) + USB0->CSR0H &= ~(USB_CSRH0_DISPING); + else + USB0->CSR0H |= USB_CSRH0_DISPING; +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group4 Endpoint functions + * @brief Endpoint functions + * @{ + */ +/** + * @brief Gets the size of the available data. + * @param ep_idx: Index of the endpoint + * @retval Size in bytes. + */ +uint32_t ald_usb_ep_data_avail(uint32_t ep_idx) +{ + if (ep_idx == USB_EP_0) { + if ((USB0->CSR0L & USB_CSRL0_RXRDY) == 0) + return 0; + + return USB0->COUNT0; + } + else { + if ((USB0->CSR[ep_idx - 1].RXxCSRL & USB_CSRL0_RXRDY) == 0) + return 0; + + return USB0->CSR[ep_idx - 1].RXxCOUNT; + } +} + +/** + * @brief Gets the data from FIFO. + * @param ep_idx: Index of the endpoint + * @param data: Pointer to the buffer. + * @param size: Size of the data. + * @retval Status. + */ +int32_t ald_usb_ep_data_get(uint32_t ep_idx, uint8_t *data, uint32_t *size) +{ + uint32_t i; + + if (ep_idx == USB_EP_0) { + if ((USB0->CSR0L & USB_CSRL0_RXRDY) == 0) { + *size = 0; + return -1; + } + i = USB0->COUNT0; + } + else { + if ((USB0->CSR[ep_idx - 1].RXxCSRL & USB_CSRL0_RXRDY) == 0) { + *size = 0; + return -1; + } + i = USB0->CSR[ep_idx - 1].RXxCOUNT; + } + + i = (i < *size) ? i : *size; + *size = i; + + for (; i > 0; i--) + *data++ = USB0->FIFO[ep_idx].Byte[0]; + + return 0; +} + +/** + * @brief Puts data to the FIFO. + * @param ep_idx: Index of the endpoint + * @param data: Pointer to the data. + * @param size: Size of the data. + * @retval Status. + */ +int32_t ald_usb_ep_data_put(uint32_t ep_idx, uint8_t *data, uint32_t size) +{ + if (ep_idx == USB_EP_0) { + if (USB0->CSR0L & USB_CSRL0_TXRDY) + return -1; + } + else { + if (USB0->CSR[ep_idx - 1].TXxCSRL & USB_TXCSRL1_TXRDY) + return -1; + } + + for (; size > 0; size--) + USB0->FIFO[ep_idx].Byte[0] = *data++; + + return 0; +} + +/** + * @brief Send data. + * @param ep_idx: Index of the endpoint + * @param tx_type: Type. + * @retval Status. + */ +int32_t ald_usb_ep_data_send(uint32_t ep_idx, uint32_t tx_type) +{ + uint32_t tmp; + + if (ep_idx == USB_EP_0) { + if (USB0->CSR0L & USB_CSRL0_TXRDY) + return -1; + + tmp = tx_type & 0xff; + USB0->CSR0L = tmp; + } + else { + if (USB0->CSR[ep_idx - 1].TXxCSRL & USB_TXCSRL1_TXRDY) + return -1; + + tmp = (tx_type >> 8) & 0xff; + USB0->CSR[ep_idx - 1].TXxCSRL = tmp; + } + + return 0; +} + +/** + * @brief Clear the status of the toggle. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_ep_data_toggle_clear(uint32_t ep_idx, uint32_t flags) +{ + if (flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + USB0->CSR[ep_idx - 1].TXxCSRL |= USB_TXCSRL1_CLRDT; + else + USB0->CSR[ep_idx - 1].RXxCSRL |= USB_RXCSRL1_CLRDT; +} + +/** + * @brief Sets the size of request data IN + * @param ep_idx: Index of the endpoint + * @param count: Size of request data IN. + * @retval None + */ +void ald_usb_ep_req_packet_count(uint32_t ep_idx, uint32_t count) +{ + USB0->EP_RQPKTCOUNT[ep_idx - 1] = count; +} + +/** + * @brief Gets the status of the endpoint. + * @param ep_idx: Index of the endpoint + * @retval Status. + */ +uint32_t ald_usb_ep_status(uint32_t ep_idx) +{ + uint32_t status; + + if (ep_idx == USB_EP_0) { + status = USB0->CSR0L; + status |= (USB0->CSR0H) << USB_RX_EPSTATUS_SHIFT; + } + else { + status = USB0->CSR[ep_idx - 1].TXxCSRL; + status |= USB0->CSR[ep_idx - 1].TXxCSRH << 8; + status |= USB0->CSR[ep_idx - 1].RXxCSRL << 16; + status |= USB0->CSR[ep_idx - 1].RXxCSRH << 24; + } + + return status; +} + +/** + * @brief Configure the endpoint in DMA mode. + * @param ep_idx: Index of the endpoint + * @param flag: Flags. + * @param en: ENABLE/DISABLE. + * @retval None + */ +void ald_usb_ep_dma_config(uint32_t ep_idx, uint32_t flag, type_func_t en) +{ + if (ep_idx == USB_EP_0) + return; + + if (en) { + switch (flag) { + case USB_DMA_EP_CFG_TX: + USB0->CSR[ep_idx - 1].TXxCSRH |= USB_DMA_EP_TX_MSK; + break; + case USB_DMA_EP_CFG_RX_DEV: + USB0->CSR[ep_idx - 1].RXxCSRH |= USB_DMA_EP_RX_DEV_MSK; + break; + case USB_DMA_EP_CFG_RX_HOST: + USB0->CSR[ep_idx - 1].RXxCSRH |= USB_DMA_EP_RX_HOST_MSK; + break; + default: + break; + } + } + else { + switch (flag) { + case USB_DMA_EP_CFG_TX: + USB0->CSR[ep_idx - 1].TXxCSRH &= ~(USB_DMA_EP_TX_MSK); + break; + case USB_DMA_EP_CFG_RX_DEV: + USB0->CSR[ep_idx - 1].RXxCSRH &= ~(USB_DMA_EP_RX_DEV_MSK); + break; + case USB_DMA_EP_CFG_RX_HOST: + USB0->CSR[ep_idx - 1].RXxCSRH &= ~(USB_DMA_EP_RX_HOST_MSK); + break; + default: + break; + } + } + + return; +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group5 FIFO functions + * @brief FIFO functions + * @{ + */ +/** + * @brief Gets the address of the FIFO. + * @param ep_idx: Index of the endpoint + * @retval Address + */ +uint32_t ald_usb_fifo_addr_get(uint32_t ep_idx) +{ + return (uint32_t)&USB0->FIFO[ep_idx].Word; +} + +/** + * @brief Gets the parameters of the FIFO. + * @param ep_idx: Index of the endpoint + * @param addr: Address. + * @param size: Size of FIFO. + * @param flags: Flags. + * @retval None + */ +void ald_usb_fifo_config_get(uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags) +{ + uint32_t tmp = USB0->INDEX; + + USB0->INDEX = ep_idx; + + if (flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) { + *addr = (USB0->TXFIFOADD << 3); + *size = (USB0->TXFIFOSIZE & 0xF); + } + else { + *addr = (USB0->RXFIFOADD << 3); + *size = (USB0->RXFIFOSIZE & 0xF); + } + + USB0->INDEX = tmp; + return; +} + +/** + * @brief Sets the parameters of the FIFO. + * @param ep_idx: Index of the endpoint + * @param addr: Address. + * @param size: Size of FIFO. + * @param flags: Flags. + * @retval None + */ +void ald_usb_fifo_config_set(uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags) +{ + uint32_t tmp = USB0->INDEX; + + USB0->INDEX = ep_idx; + + if (flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) { + USB0->TXFIFOADD = (addr >> 3); + USB0->TXFIFOSIZE = (size & 0xF); + } + else { + USB0->RXFIFOADD = (addr >> 3); + USB0->RXFIFOSIZE = (size & 0xF); + } + + USB0->INDEX = tmp; + return; +} + +/** + * @brief Flush the FIFO + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_fifo_flush(uint32_t ep_idx, uint32_t flags) +{ + if (ep_idx == USB_EP_0) { + if ((USB0->CSR0L & (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0) + USB0->CSR0H |= USB_CSRH0_FLUSH; + } + else { + if (flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) { + if (USB0->CSR[ep_idx - 1].TXxCSRL & USB_TXCSRL1_TXRDY) + USB0->CSR[ep_idx - 1].TXxCSRL |= USB_TXCSRL1_FLUSH; + } + else { + if (USB0->CSR[ep_idx - 1].RXxCSRL & USB_RXCSRL1_RXRDY) + USB0->CSR[ep_idx - 1].RXxCSRL |= USB_RXCSRL1_FLUSH; + } + } +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group6 Interrupt functions + * @brief Interrupt functions + * @{ + */ +/** + * @brief Disable interrupt. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_disable(uint32_t flags) +{ + if (flags & USB_INTCTRL_STATUS) + USB0->USBIE &= ~(flags & USB_INTCTRL_STATUS); +} + +/** + * @brief Enable interrupt. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_enable(uint32_t flags) +{ + if (flags & USB_INTCTRL_STATUS) + USB0->USBIE |= flags ; +} + +/** + * @brief Gets the status of the interrupt. + * @retval Status. + */ +uint32_t ald_usb_int_status_get(void) +{ + return USB0->USBIS; +} + +/** + * @brief Disable interrupt of the endpoint. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_disable_ep(uint32_t flags) +{ + USB0->TXIE &= ~(flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); + USB0->RXIE &= ~((flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> USB_INTEP_RX_SHIFT); +} + +/** + * @brief Enable interrupt of the endpoint. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_enable_ep(uint32_t flags) +{ + + USB0->TXIE |= flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0); + USB0->RXIE |= ((flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> USB_INTEP_RX_SHIFT); +} + +/** + * @brief Gets the ststus of the endpoint interrupt. + * @retval Status. + */ +uint32_t ald_usb_int_status_ep_get(void) +{ + uint32_t status; + + status = USB0->TXIS; + status |= (USB0->RXIS << USB_INTEP_RX_SHIFT); + + return status; +} + +/** + * @brief Register USB's interrupt. + * @retval None + */ +void ald_usb_int_register(void) +{ + ald_mcu_irq_config(USB_INT_IRQn, 2, 2, ENABLE); + +} + +/** + * @brief Unregister USB's interrupt. + * @retval None + */ +void ald_usb_int_unregister(void) +{ + ald_mcu_irq_config(USB_INT_IRQn, 2, 2, DISABLE); +} + +/** + * @brief Get USB's interrupt number. + * @retval None + */ +uint32_t ald_usb_int_num_get(void) +{ + return USB_INT_IRQn; +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group7 DMA functions + * @brief DMA functions + * @{ + */ +/** + * @brief Configure DMA's channel. + * @param ch: Channel. + * @param addr: Address. + * @param count: Size of the data to be moved. + * @param ctrl: Parameters of the DMA's controler + * @retval None + */ +void ald_usb_dma_channel_config(uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl) +{ + USB0->DMA_CH[ch].DMA_ADDR = addr; + USB0->DMA_CH[ch].DMA_COUNT = count; + USB0->DMA_CH[ch].DMA_CNTL = ctrl; + return; +} + +/** + * @brief Start multiple receive. + * @param ep_idx: Index of the endpoint + * @retval None + */ +void ald_usb_dma_mult_recv_start(uint32_t ep_idx) +{ + USB0->CSR[ep_idx - 1].RXxCSRH &= ~(USB_RXCSRH1_DMAMOD); + return; +} + + +/** + * @brief Start DMA's machine. + * @param ch: Channel. + * @retval None + */ +void ald_usb_dma_channel_start(uint8_t ch) +{ + USB0->DMA_CH[ch].DMA_CNTL |= 0x1; + return; +} + +/** + * @brief Stop DMA's machine. + * @param ch: Channel. + * @retval None + */ +void ald_usb_dma_channel_stop(uint8_t ch) +{ + USB0->DMA_CH[ch].DMA_CNTL &= ~0x1; + return; +} + +/** + * @brief Gets flags of the interrupt. + * @retval Flags of the interrupt. + */ +uint32_t ald_usb_dma_get_interrupt_flag(void) +{ + return USB0->DMA_INTR; +} + +/** + * @brief Gets the status of the error. + * @param ch: Channel. + * @retval Status. + */ +uint32_t ald_usb_dma_get_channel_error(uint8_t ch) +{ + if (USB0->DMA_CH[ch].DMA_CNTL & USB_DMA_CH_ERR_MSK) + return 1; + + return 0; +} + +/** + * @brief Clear the status of the error. + * @param ch: Channel. + * @retval None + */ +void ald_usb_dma_clear_channel_error(uint8_t ch) +{ + USB0->DMA_CH[ch].DMA_CNTL &= ~(USB_DMA_CH_ERR_MSK); +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group8 LPM functions + * @brief LPM functions + * @{ + */ +/** + * @brief Transmit a LPM transaction in host mode. + * @param addr: Address. + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_lpm_send(uint32_t addr, uint32_t ep_idx) +{ + uint32_t tmp; + + USB0->LPM_FADDR = addr; + + tmp = USB0->LPM_ATTR & ~(USB_LPMATTR_ENDPT_M); + tmp |= ep_idx << USB_LPMATTR_ENDPT_S; + + USB0->LPM_ATTR = tmp; + USB0->LPM_CNTRL |= USB_LPMCNTRL_LPMXMT; +} + +/** + * @brief Configure the LPM parameters in host mode. + * @param resume_time: Resume time. + * @param config: Parameters + * @retval None + */ +void ald_usb_host_lpm_config(uint32_t resume_time, uint32_t config) +{ + uint32_t tmp; + + tmp = USB0->LPM_ATTR; + tmp &= ~(USB_LPMATTR_HIRD_M); + tmp |= ((((resume_time - 50) / 75) & 0xF) << USB_LPMATTR_HIRD_S); + tmp |= config; + USB0->LPM_ATTR = tmp; +} + +/** + * @brief Gets status of remote wakeup. + * @retval Status. + */ +uint32_t ald_usb_lpm_remote_wake_is_enable(void) +{ + if (USB0->LPM_ATTR & USB_LPMATTR_RMTWAK) + return 1; + + return 0; +} + +/** + * @brief Initiate a RESUME from the L1 state in host mode. + * @retval None + */ +void ald_usb_host_lpm_resume(void) +{ + USB0->LPM_CNTRL |= USB_LPMCNTRL_LPMRES; +} + +/** + * @brief Enable remote wakeup in device mode. + * @retval None + */ +void ald_usb_dev_lpm_remote_wake(void) +{ + USB0->LPM_CNTRL |= USB_LPMCNTRL_LPMRES; +} + +/** + * @brief Enable remote wakeup in device mode. + * @retval None + */ +void ald_usb_dev_lpm_config(uint32_t config) +{ + USB0->LPM_CNTRL = config; +} + +/** + * @brief Enable LPM in device mode. + * @retval None + */ +void ald_usb_dev_lpm_enable(void) +{ + USB0->LPM_CNTRL |= (USB_LPMCNTRL_LPMXMT | USB_LPMCNTRL_ENABLE); +} + +/** + * @brief Disable LPM in device mode. + * @retval None + */ +void ald_usb_dev_lpm_disable(void) +{ + USB0->LPM_CNTRL &= ~(USB_LPMCNTRL_LPMXMT); +} + +/** + * @brief Gets the link status + * @retval Status + */ +uint32_t ald_usb_lpm_link_status_get(void) +{ + return (USB0->LPM_ATTR & USB_LPMATTR_LS_M); +} + +/** + * @brief Gets the index of the endpoint. + * @retval Index of the endpoint. + */ +uint32_t ald_usb_lpm_ep_get(void) +{ + uint32_t tmp; + + tmp = USB0->LPM_ATTR; + tmp &= USB_LPMATTR_ENDPT_M; + tmp = tmp >> USB_LPMATTR_ENDPT_S; + + return tmp; +} + +/** + * @brief Gets the status of the interrupt. + * @retval Status. + */ +uint32_t ald_usb_lpm_int_status_get(void) +{ + return USB0->LPM_INTR; +} + +/** + * @brief Disable the LPM interrupt. + * @retval None + */ +void ald_usb_lpm_int_disable(uint32_t ints) +{ + USB0->LPM_INTREN &= ~ints; +} + +/** + * @brief Enable the LPM interrupt. + * @retval None + */ +void ald_usb_lpm_int_enable(uint32_t ints) +{ + USB0->LPM_INTREN |= ints; +} +/** + * @} + */ + +/** + * @} + */ +#endif +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_wdt.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..1e69e95d8f614f5f2acefc170978c60c24e77022 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/ald_wdt.c @@ -0,0 +1,214 @@ +/** + ********************************************************************************* + * + * @file ald_wdt.c + * @brief WDT module driver. + * + * @version V1.0 + * @date 18 Dec 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ +#include "ald_conf.h" +#include "ald_wdt.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup WDT WDT + * @brief WDT module driver + * @{ + */ +#ifdef ALD_WDT + + +/** @defgroup WWDT_Public_Functions WWDT Public Functions + * @brief Init and configure WWDT function + * @{ + */ +/** + * @brief Initializes the WWDT according to the specified parameters. + * @param load: Specifies the free-running downcounter value. + * @param win: specifics the no dog windows, + * the parameter can be one of the following values: + * @arg @ref WWDT_WIN_25 No dog window size: 25% + * @arg @ref WWDT_WIN_50 No dog window size: 50% + * @arg @ref WWDT_WIN_75 No dog window size: 75% + * @arg @ref WWDT_WIN_00 No dog window size: 0% + * @param interrupt: Enable or disable interrupt. + * @retval None + */ +void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt) +{ + assert_param(IS_WWDT_WIN_TYPE(win)); + assert_param(IS_FUNC_STATE(interrupt)); + + WWDT_UNLOCK(); + WRITE_REG(WWDT->LOAD, load); + MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, win << WWDT_CON_WWDTWIN_POSS); + SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK); + SET_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK); + MODIFY_REG(WWDT->CON, WWDT_CON_IE_MSK, interrupt << WWDT_CON_IE_POS); + WWDT_LOCK(); + + return; +} + +/** + * @brief Start the WWDT + * @retval None + */ +void ald_wwdt_start(void) +{ + WWDT_UNLOCK(); + SET_BIT(WWDT->CON, WWDT_CON_EN_MSK); + WWDT_LOCK(); + + return; +} + +/** + * @brief Get the free-running downcounter value + * @retval Value + */ +uint32_t ald_wwdt_get_value(void) +{ + return WWDT->VALUE; +} + +/** + * @brief Get interrupt state + * @retval Value + */ +it_status_t ald_wwdt_get_flag_status(void) +{ + if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK)) + return SET; + + return RESET; +} + +/** + * @brief Clear interrupt state + * @retval None + */ +void ald_wwdt_clear_flag_status(void) +{ + WRITE_REG(WWDT->INTCLR, 1); + return; +} + +/** + * @brief Refreshes the WWDT + * @retval None + */ +void ald_wwdt_feed_dog(void) +{ + WWDT_UNLOCK(); + WRITE_REG(WWDT->INTCLR, 0x1); + WWDT_LOCK(); + + return; +} +/** + * @} + */ + +/** @defgroup IWDT_Public_Functions IWDT Public Functions + * @brief Init and configure IWDT function + * @{ + */ +/** + * @brief Initializes the IWDG according to the specified parameters. + * @param load: Specifies the free-running downcounter value. + * @param interrupt: Enable or disable interrupt. + * @retval None + */ +void ald_iwdt_init(uint32_t load, type_func_t interrupt) +{ + assert_param(IS_FUNC_STATE(interrupt)); + + IWDT_UNLOCK(); + WRITE_REG(IWDT->LOAD, load); + SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK); + SET_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK); + MODIFY_REG(IWDT->CON, IWDT_CON_IE_MSK, interrupt << IWDT_CON_IE_POS); + IWDT_LOCK(); + + return; +} + +/** + * @brief Start the IWDT + * @retval None + */ +void ald_iwdt_start(void) +{ + IWDT_UNLOCK(); + SET_BIT(IWDT->CON, IWDT_CON_EN_MSK); + IWDT_LOCK(); + + return; +} + +/** + * @brief Get the free-running downcounter value + * @retval Value + */ +uint32_t ald_iwdt_get_value(void) +{ + return IWDT->VALUE; +} + +/** + * @brief Get interrupt state + * @retval Value + */ +it_status_t ald_iwdt_get_flag_status(void) +{ + if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK)) + return SET; + + return RESET; +} + +/** + * @brief Clear interrupt state + * @retval None + */ +void ald_iwdt_clear_flag_status(void) +{ + WRITE_REG(IWDT->INTCLR, 1); + return; +} + +/** + * @brief Refreshes the WWDT + * @retval None + */ +void ald_iwdt_feed_dog(void) +{ + IWDT_UNLOCK(); + WRITE_REG(IWDT->INTCLR, 1); + IWDT_LOCK(); + + return; +} +/** + * @} + */ + +#endif /* ALD_WDT */ +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c new file mode 100644 index 0000000000000000000000000000000000000000..0de76adf1ebd2af9b9540e0808ffc41e16e895ec --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/utils.c @@ -0,0 +1,428 @@ +/** + ********************************************************************************* + * + * @file utils.c + * @brief This file contains the Utilities functions/types for the driver. + * + * @version V1.0 + * @date 07 Nov 2019 + * @author AE Team + * @note + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + ********************************************************************************* + */ + +#include "utils.h" +#include "ald_dma.h" +#include "ald_cmu.h" + + +/** @defgroup ES32FXXX_ALD EASTSOFT ES32F3xx ALD + * @brief Shanghai Eastsoft Microelectronics Cortex-M Chip Abstraction Layer Driver(ALD) + * @{ + */ + +/** @defgroup UTILS Utils + * @brief Utils module driver + * @{ + */ + +/** @defgroup ALD_Private_Constants Private Constants + * @brief ALD Private Constants + * @{ + */ + +/** + * @brief ALD version number + */ +#define __ALD_VERSION_MAIN (0x01) /**< [31:24] main version */ +#define __ALD_VERSION_SUB1 (0x00) /**< [23:16] sub1 version */ +#define __ALD_VERSION_SUB2 (0x00) /**< [15:8] sub2 version */ +#define __ALD_VERSION_RC (0x00) /**< [7:0] release candidate */ +#define __ALD_VERSION ((__ALD_VERSION_MAIN << 24) | \ + (__ALD_VERSION_SUB1 << 16) | \ + (__ALD_VERSION_SUB2 << 8 ) | \ + (__ALD_VERSION_RC)) +/** + * @} + */ + +/** @defgroup ALD_Private_Variables Private Variables + * @{ + */ +/** @brief lib_tick: Increase by one millisecond + */ +static __IO uint32_t lib_tick; +uint32_t __systick_interval = SYSTICK_INTERVAL_1MS; +/** + * @} + */ + + +/** @defgroup ALD_Public_Functions Public Functions + * @{ + */ + +/** @defgroup ALD_Public_Functions_Group1 Initialization Function + * @brief Initialization functions + * + * @verbatim + =============================================================================== + ##### Initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes interface, the NVIC allocation and initial clock + configuration. It initializes the source of time base also when timeout + is needed and the backup domain when enabled. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) Systick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms. + (++) Time base configuration function (ald_tick_init()) is called automatically + at the beginning of the program after reset by ald_cmu_init() or at + any time when clock is configured. + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if ald_delay_ms() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. + (+) Configure the interval of Systick interrupt. + + @endverbatim + * @{ + */ + +/** + * @brief This function Configures time base source, NVIC and DMA. + * @note This function is called at the beginning of program after reset and before + * the clock configuration. + * @note The time base configuration is based on MSI clock when exiting from Reset. + * Once done, time base tick start incrementing. + * In the default implementation, Systick is used as source of time base. + * The tick variable is incremented each 1ms in its ISR. + * @retval None + */ +void ald_cmu_init(void) +{ + NVIC_SetPriorityGrouping(NVIC_PRIORITY_GROUP_2); + ald_cmu_clock_config_default(); + ald_tick_init(TICK_INT_PRIORITY); +#ifdef ALD_DMA + ald_cmu_perh_clock_config(CMU_PERH_DMA, ENABLE); + ald_dma_init(DMA0); +#endif + return; +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if ald_delay_ms() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param prio: Tick interrupt priority. + * @retval None + */ +__weak void ald_tick_init(uint32_t prio) +{ + /* Configure the SysTick IRQ */ + NVIC_SetPriority(SysTick_IRQn, prio); + SysTick_Config(ald_cmu_get_sys_clock() / SYSTICK_INTERVAL_1MS); + + return; +} + +/** + * @brief Selects the interval of systick interrupt. + * @param value: The value of interval: + * @arg @ref SYSTICK_INTERVAL_1MS 1 millisecond + * @arg @ref SYSTICK_INTERVAL_10MS 10 milliseconds + * @arg @ref SYSTICK_INTERVAL_100MS 100 milliseconds + * @arg @ref SYSTICK_INTERVAL_1000MS 1 second + * @retval None + */ +void ald_systick_interval_select(systick_interval_t value) +{ + assert_param(IS_SYSTICK_INTERVAL(value)); + + SysTick_Config(ald_cmu_get_sys_clock() / value); + __systick_interval = value; + + if (TICK_INT_PRIORITY != 15) + NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY); + + return; +} +/** + * @} + */ + +/** @defgroup ALD_Public_Functions_Group2 Control functions + * @brief Control functions + * + * @verbatim + =============================================================================== + ##### Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the ALD version + (+) Waiting for flag + (+) Configure the interrupt + (+) Provide system tick value + (+) Get CPU ID + (+) Initialize core timestamp + (+) Get core timestamp + @endverbatim + * @{ + */ + +/** + * @brief This function invoked by Systick ISR. + * @note This function is declared as __weak to be overwritten in case of + * other implementations in user file. + * @retval None + */ +__weak void ald_systick_irq_cbk(void) +{ + /* do nothing */ + return; +} + +/** + * @brief This function is called to increment a global variable "lib_tick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in Systick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void ald_inc_tick(void) +{ + ++lib_tick; + ald_systick_irq_cbk(); +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t ald_get_tick(void) +{ + return lib_tick; +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where lib_tick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param delay: specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void ald_delay_ms(__IO uint32_t delay) +{ + uint32_t tick, __delay; + + switch (__systick_interval) { + case SYSTICK_INTERVAL_1MS: + __delay = delay; + break; + + case SYSTICK_INTERVAL_10MS: + __delay = delay / 10; + break; + + case SYSTICK_INTERVAL_100MS: + __delay = delay / 100; + break; + + case SYSTICK_INTERVAL_1000MS: + __delay = delay / 1000; + break; + + default: + __delay = delay; + break; + } + + tick = ald_get_tick(); + __delay = __delay == 0 ? 1 : __delay; + + while ((ald_get_tick() - tick) < __delay) + ; +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Once ald_suspend_tick() is called, the the SysTick interrupt + * will be disabled and so Tick increment is suspended. + * @note This function is declared as __weak to be overwritten + * in case of other implementations in user file. + * @retval None + */ +__weak void ald_suspend_tick(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation, SysTick timer is the source of + * time base. It is used to generate interrupts at regular time + * intervals. Once ald_resume_tick() is called, the the SysTick + * interrupt will be enabled and so Tick increment is resumed. + * @note This function is declared as __weak to be overwritten + * in case of other implementations in user file. + * @retval None + */ +__weak void ald_resume_tick(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief This method returns the ALD revision + * @retval version: 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t ald_get_ald_version(void) +{ + return __ALD_VERSION; +} + +/** + * @brief Waiting the specified bit in the register change to SET/RESET. + * @param reg: The register address. + * @param bit: The specified bit. + * @param status: The status for waiting. + * @param timeout: Timeout duration. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout) +{ + uint32_t tick = ald_get_tick(); + + assert_param(timeout > 0); + + if (status == SET) { + while (!(IS_BIT_SET(*reg, bit))) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + } + else { + while ((IS_BIT_SET(*reg, bit))) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + } + + return OK; +} + +/** + * @brief Configure interrupt. + * @param irq: Interrunpt type. + * @param preempt_prio: preempt priority(0-3). + * @param sub_prio: sub-priority(0-3). + * @param status: Status. + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status) +{ + uint32_t pri; + uint8_t sub_bw, pre_bw; + uint8_t sub_mask = 0xF; + + assert_param(IS_FUNC_STATE(status)); + assert_param(IS_PREEMPT_PRIO(preempt_prio)); + assert_param(IS_SUB_PRIO(sub_prio)); + + if (status == ENABLE) { + pre_bw = 7 - (((SCB->AIRCR) >> 8) & 7); + sub_bw = 4 - pre_bw; + sub_mask >>= pre_bw; + + pri = preempt_prio << sub_bw; + pri |= sub_prio & sub_mask; + + NVIC_SetPriority(irq, pri); + NVIC_EnableIRQ(irq); + } + else { + NVIC_DisableIRQ(irq); + } + + return; +} + +/** + * @brief Get the CPU ID. + * @retval CPU ID. + */ +uint32_t ald_mcu_get_cpu_id(void) +{ + return SCB->CPUID; +} + +/** + * @brief Initialize core timestamp. + * @retval None + */ +void ald_mcu_timestamp_init(void) +{ + DEM_CR |= (uint32_t)DEM_CR_TRCENA; + DWT_CYCCNT = 0x0; + DWT_CR |= (uint32_t)DWT_CR_CYCCNTEA; + + return; +} + +/** + * @brief Get core timestamp. + * @retval None + */ +uint32_t ald_mcu_get_timestamp(void) +{ + return (uint32_t)DWT_CYCCNT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/essemi/es32f369x/libraries/SConscript b/bsp/essemi/es32f369x/libraries/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..f52de2055da7737a601fbaafc7ad475c35df5e14 --- /dev/null +++ b/bsp/essemi/es32f369x/libraries/SConscript @@ -0,0 +1,27 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = [] + +src += Glob('ES32F36xx_ALD_StdPeriph_Driver/Source/*.c') + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['CMSIS/Device/EastSoft/ES32F36xx/Startup/iar/startup_es32f36xx.s'] + +path = [cwd + '/CMSIS/Device/EastSoft/ES32F36xx/Include', + cwd + '/CMSIS/Include', + cwd + '/ES32F36xx_ALD_StdPeriph_Driver/Include'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = ['ES32F36xx']) + +Return('group') diff --git a/bsp/essemi/es32f369x/project.uvoptx b/bsp/essemi/es32f369x/project.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..8d3f54f7f57c43802e344af795ef0131a184de07 --- /dev/null +++ b/bsp/essemi/es32f369x/project.uvoptx @@ -0,0 +1,171 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 2 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0es32f36xx -FL080000 -FS00 -FP0($$Device:ES32F3696LT$Flash\es32f36xx.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0es32f36xx.FLM -FS00 -FL080000 -FP0($$Device:ES32F3696LT$Flash\es32f36xx.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + +     diff --git a/bsp/essemi/es32f369x/project.uvprojx b/bsp/essemi/es32f369x/project.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..1dbadb49a8431a90025626e3daa55d0eec6ae94f --- /dev/null +++ b/bsp/essemi/es32f369x/project.uvprojx @@ -0,0 +1,915 @@ + + + 2.1 +
    ### uVision Project, (C) Keil Software
    + + + rt-thread + 0x4 + ARM-ADS + + + ES32F3696LT + Eastsoft + Eastsoft.ES32_DFP.1.0.5 + http://www.essemi.com + IRAM(0x20000000,0x00018000) IROM(0x00000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0es32f36xx -FS00 -FL080000 -FP0($$Device:ES32F3696LT$Flash\es32f36xx.FLM)) + 0 + $$Device:ES32F3696LT$Device\Include\es32f36xx.h + + + + + + + + + + $$Device:ES32F3696LT$SVD\es32f36xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\keil\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + ES32F36xx + + .;..\..\..\include;applications;.;drivers;libraries\CMSIS\Device\EastSoft\ES32F36xx\Include;libraries\CMSIS\Include;libraries\ES32F36xx_ALD_StdPeriph_Driver\Include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\..\src\signal.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + + + drv_uart.c + 1 + drivers\drv_uart.c + + + + + Libraries + + + ald_acmp.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_acmp.c + + + + + ald_adc.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_adc.c + + + + + ald_bkpc.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_bkpc.c + + + + + ald_calc.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_calc.c + + + + + ald_can.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_can.c + + + + + ald_cmu.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_cmu.c + + + + + ald_crc.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crc.c + + + + + ald_crypt.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_crypt.c + + + + + ald_dac.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dac.c + + + + + ald_dma.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_dma.c + + + + + ald_ebi.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_ebi.c + + + + + ald_flash.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash.c + + + + + ald_flash_ext.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_flash_ext.c + + + + + ald_gpio.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_gpio.c + + + + + ald_i2c.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2c.c + + + + + ald_i2s.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_i2s.c + + + + + ald_iap.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_iap.c + + + + + ald_nand.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nand.c + + + + + ald_nor_lcd.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_nor_lcd.c + + + + + ald_pis.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pis.c + + + + + ald_pmu.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_pmu.c + + + + + ald_qspi.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_qspi.c + + + + + ald_rmu.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rmu.c + + + + + ald_rtc.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtc.c + + + + + ald_rtchw.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_rtchw.c + + + + + ald_spi.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_spi.c + + + + + ald_sram.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_sram.c + + + + + ald_timer.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_timer.c + + + + + ald_trng.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_trng.c + + + + + ald_tsense.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_tsense.c + + + + + ald_uart.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_uart.c + + + + + ald_usb.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_usb.c + + + + + ald_wdt.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\ald_wdt.c + + + + + utils.c + 1 + libraries\ES32F36xx_ALD_StdPeriph_Driver\Source\utils.c + + + + + startup_es32f36xx.s + 2 + libraries\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s + + + + + cpu + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m3\cpuport.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m3\context_rvds.S + + + + + DeviceDrivers + + + can.c + 1 + ..\..\..\components\drivers\can\can.c + + + + + i2c_core.c + 1 + ..\..\..\components\drivers\i2c\i2c_core.c + + + + + i2c_dev.c + 1 + ..\..\..\components\drivers\i2c\i2c_dev.c + + + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + + + + + + + +     diff --git a/bsp/essemi/es32f369x/rtconfig.h b/bsp/essemi/es32f369x/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..928add7eb8be57b29ae5a77d91290d0678ab634b --- /dev/null +++ b/bsp/essemi/es32f369x/rtconfig.h @@ -0,0 +1,174 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40002 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_CAN +#define RT_USING_I2C +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_ES32F3696LT + +/* Hardware Drivers Config */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO + +/* UART Drivers */ + +#define BSP_USING_UART0 + +/* SPI Drivers */ + + +/* I2C Drivers */ + + +/* CAN Drivers */ + + +/* Onboard Peripheral Drivers */ + +/* Offboard Peripheral Drivers */ + + +#endif diff --git a/bsp/essemi/es32f369x/rtconfig.py b/bsp/essemi/es32f369x/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..69c567cc5cf81cee11639d9c21225bf9f9d7e531 --- /dev/null +++ b/bsp/essemi/es32f369x/rtconfig.py @@ -0,0 +1,135 @@ +import os +import sys + +# toolchains options +CROSS_TOOL = 'keil' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# device options +ARCH = 'arm' +CPU = 'cortex-m3' + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': # not support gcc yet + PLATFORM = 'gcc' + EXEC_PATH = 'C:/GCC' + +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil' + +elif CROSS_TOOL == 'iar': # not support iar yet + PLATFORM = 'iar' + EXEC_PATH = 'C:/IAR' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --device DARMSTM' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M0' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M0' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + LFLAGS = ' --config "drivers\linker_scripts\link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS += ' --entry __iar_program_start' + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/essemi/es32f369x/template.uvoptx b/bsp/essemi/es32f369x/template.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..8d3f54f7f57c43802e344af795ef0131a184de07 --- /dev/null +++ b/bsp/essemi/es32f369x/template.uvoptx @@ -0,0 +1,171 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 2 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0es32f36xx -FL080000 -FS00 -FP0($$Device:ES32F3696LT$Flash\es32f36xx.FLM) + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0es32f36xx.FLM -FS00 -FL080000 -FP0($$Device:ES32F3696LT$Flash\es32f36xx.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + +     diff --git a/bsp/essemi/es32f369x/template.uvprojx b/bsp/essemi/es32f369x/template.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..ad28753eb352ebb6ff3cd68c09fd83aa7e811511 --- /dev/null +++ b/bsp/essemi/es32f369x/template.uvprojx @@ -0,0 +1,386 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + rt-thread + 0x4 + ARM-ADS + + + ES32F3696LT + Eastsoft + Eastsoft.ES32_DFP.1.0.5 + http://www.essemi.com + IRAM(0x20000000,0x00018000) IROM(0x00000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0es32f36xx -FS00 -FL080000 -FP0($$Device:ES32F3696LT$Flash\es32f36xx.FLM)) + 0 + $$Device:ES32F3696LT$Device\Include\es32f36xx.h + + + + + + + + + + $$Device:ES32F3696LT$SVD\es32f36xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\keil\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + + + + + + + +     diff --git a/bsp/gd32450z-eval/drivers/drv_enet.c b/bsp/gd32450z-eval/drivers/drv_enet.c index 0f8ce72db6762576ea2eef183c933a54057de613..b1bf632f54d061a2ff88c265585b5c27ad83a0cd 100644 --- a/bsp/gd32450z-eval/drivers/drv_enet.c +++ b/bsp/gd32450z-eval/drivers/drv_enet.c @@ -652,7 +652,10 @@ int rt_hw_gd32_eth_init(void) /* init tx buffer free semaphore */ rt_sem_init(&gd32_emac_device0.tx_buf_free, "tx_buf0", EMAC_TXBUFNB, RT_IPC_FLAG_FIFO); eth_device_init(&(gd32_emac_device0.parent), "e0"); - + + /* change device link status */ + eth_device_linkchange(&(gd32_emac_device0.parent), RT_TRUE); + return 0; } INIT_DEVICE_EXPORT(rt_hw_gd32_eth_init); diff --git a/bsp/imxrt/imxrt1052-atk-commander/board/Kconfig b/bsp/imxrt/imxrt1052-atk-commander/board/Kconfig index 859c2a4fdd2f222e84753acf0dcb2d9f945da266..b4beef948d3f1a51f89cf67501b905793b5e3cd8 100644 --- a/bsp/imxrt/imxrt1052-atk-commander/board/Kconfig +++ b/bsp/imxrt/imxrt1052-atk-commander/board/Kconfig @@ -123,6 +123,12 @@ menu "Onboard Peripheral Drivers" config BSP_USING_SDRAM bool "Enable SDRAM" default n + + config BSP_USING_USB_DEVICE + bool "Enable USB Device" + select RT_USING_USB_DEVICE + default n + endmenu endmenu diff --git a/bsp/imxrt/libraries/drivers/SConscript b/bsp/imxrt/libraries/drivers/SConscript index 7320ff84af5af2d8cb66574c8e21e01d7c528796..c806dada257fc04b7a8914f98d9d77b666990b67 100644 --- a/bsp/imxrt/libraries/drivers/SConscript +++ b/bsp/imxrt/libraries/drivers/SConscript @@ -1,8 +1,10 @@ from building import * -cwd = GetCurrentDir() - src = [] +cwd = [] +CPPDEFINES = [] + +cwd = GetCurrentDir() if GetDepend('BSP_USING_GPIO'): src += ['drv_gpio.c'] @@ -43,8 +45,16 @@ if GetDepend('BSP_USING_LCD'): if GetDepend('BSP_USING_ETH'): src += ['drv_eth.c'] +if GetDepend('BSP_USING_USB_DEVICE'): + src += ['drv_usbd.c'] + src += Glob('usb/device/*.c') + +if GetDepend('BSP_USING_USB_DEVICE'): + src += Glob('usb/phy/*.c') + CPPDEFINES += ['ENDIANNESS'] + path = [cwd,cwd + '/config'] -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES) Return('group') diff --git a/bsp/imxrt/libraries/drivers/drv_usbd.c b/bsp/imxrt/libraries/drivers/drv_usbd.c new file mode 100644 index 0000000000000000000000000000000000000000..b034ba7a72a1a0a095352375148c0f5cb10ccdaa --- /dev/null +++ b/bsp/imxrt/libraries/drivers/drv_usbd.c @@ -0,0 +1,338 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-12-04 ZYH first implementation + */ +#include +#include +#include +#include +#include +#include +#include + +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x0CU) +#define BOARD_USB_PHY_TXCAL45DP (0x06U) +#define BOARD_USB_PHY_TXCAL45DM (0x06U) + +static usb_device_handle ehci0_handle; +static struct udcd _fsl_udc_0; + +static usb_status_t usb_device_callback(usb_device_handle handle, uint32_t callbackEvent, void *eventParam); +static usb_status_t usb_device_endpoint_callback(usb_device_handle handle, usb_device_endpoint_callback_message_struct_t *message, void *callbackParam); + +static void USB_DeviceIsrEnable(uint8_t controllerId) +{ + uint8_t irqNumber; +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) + uint8_t usbDeviceEhciIrq[] = USBHS_IRQS; + irqNumber = usbDeviceEhciIrq[controllerId - kUSB_ControllerEhci0]; +#endif + /* Install isr, set priority, and enable IRQ. */ +#if defined(__GIC_PRIO_BITS) + GIC_SetPriority((IRQn_Type)irqNumber, 3); +#else + NVIC_SetPriority((IRQn_Type)irqNumber, 3); +#endif + EnableIRQ((IRQn_Type)irqNumber); +} + +/*! + * @brief Initializes USB specific setting that was not set by the Clocks tool. + */ +static void USB_DeviceClockInit(uint8_t controllerId) +{ +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) + usb_phy_config_struct_t phyConfig = { + BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM, + }; +#endif +#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) + if (controllerId == kUSB_ControllerEhci0) + { + CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U); + CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U); + } + else + { + CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U); + CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U); + } + USB_EhciPhyInit(controllerId, 0, &phyConfig); +#endif +} + +static struct ep_id _ehci0_ep_pool[] = +{ + {0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED }, + {0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x2, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x2, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x3, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x3, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x4, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x4, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x5, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x5, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x6, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x6, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0x7, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, + {0x7, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, + {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED }, +}; + +/*! + * @brief USB Interrupt service routine. + * + * This function serves as the USB interrupt service routine. + * + * @return None. + */ +void USB_OTG1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + USB_DeviceEhciIsrFunction(ehci0_handle); + /* leave interrupt */ + rt_interrupt_leave(); +} + +static rt_err_t _ehci0_ep_set_stall(rt_uint8_t address) +{ + USB_DeviceStallEndpoint(ehci0_handle, address); + return RT_EOK; +} + +static rt_err_t _ehci0_ep_clear_stall(rt_uint8_t address) +{ + USB_DeviceUnstallEndpoint(ehci0_handle, address); + return RT_EOK; +} + +static rt_err_t _ehci0_set_address(rt_uint8_t address) +{ + USB_DeviceSetStatus(ehci0_handle, kUSB_DeviceStatusAddress, &address); + return RT_EOK; +} + +static rt_err_t _ehci0_set_config(rt_uint8_t address) +{ + return RT_EOK; +} + +static rt_err_t _ehci0_ep_enable(uep_t ep) +{ + usb_device_endpoint_init_struct_t ep_init; + usb_device_endpoint_callback_struct_t ep_callback; + rt_uint32_t param = ep->ep_desc->bEndpointAddress; + RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); + ep_init.maxPacketSize = ep->ep_desc->wMaxPacketSize; + ep_init.endpointAddress = ep->ep_desc->bEndpointAddress; + ep_init.transferType = ep->ep_desc->bmAttributes; + ep_init.zlt = 0; + ep_callback.callbackFn = usb_device_endpoint_callback; + ep_callback.callbackParam = (void *)param; + ep_callback.isBusy = 0; + USB_DeviceInitEndpoint(ehci0_handle, &ep_init, &ep_callback); + return RT_EOK; +} +static rt_err_t _ehci0_ep_disable(uep_t ep) +{ + RT_ASSERT(ep != RT_NULL); + RT_ASSERT(ep->ep_desc != RT_NULL); + USB_DeviceDeinitEndpoint(ehci0_handle, ep->ep_desc->bEndpointAddress); + return RT_EOK; +} + +static rt_size_t _ehci0_ep_read(rt_uint8_t address, void *buffer) +{ + rt_size_t size = 0; + + RT_ASSERT(buffer != RT_NULL); + + return size; +} + +static rt_size_t _ehci0_ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t size) +{ + USB_DeviceRecvRequest(ehci0_handle, address, buffer, size); + return size; +} + +static rt_size_t _ehci0_ep_write(rt_uint8_t address, void *buffer, rt_size_t size) +{ + USB_DeviceSendRequest(ehci0_handle, address, buffer, size); + return size; +} + +static rt_err_t _ehci0_ep0_send_status(void) +{ + _ehci0_ep_write(0x00, NULL, 0); + return RT_EOK; +} + +static rt_err_t _ehci0_suspend(void) +{ + return RT_EOK; +} + +static rt_err_t _ehci0_wakeup(void) +{ + return RT_EOK; +} + +const static struct udcd_ops _ehci0_udc_ops = +{ + _ehci0_set_address, + _ehci0_set_config, + _ehci0_ep_set_stall, + _ehci0_ep_clear_stall, + _ehci0_ep_enable, + _ehci0_ep_disable, + _ehci0_ep_read_prepare, + _ehci0_ep_read, + _ehci0_ep_write, + _ehci0_ep0_send_status, + _ehci0_suspend, + _ehci0_wakeup, +}; + +static rt_err_t drv_ehci0_usbd_init(rt_device_t device) +{ + usb_status_t result; + USB_DeviceClockInit(kUSB_ControllerEhci0); + + result = USB_DeviceInit(kUSB_ControllerEhci0, usb_device_callback, &ehci0_handle); + RT_ASSERT(ehci0_handle); + if(result == kStatus_USB_Success) + { + USB_DeviceIsrEnable(kUSB_ControllerEhci0); + USB_DeviceRun(ehci0_handle); + } + else + { + rt_kprintf("USB_DeviceInit ehci0 error\r\n"); + return RT_ERROR; + } + return RT_EOK; +} + +static int rt_usbd_init(void) +{ + rt_memset((void *)&_fsl_udc_0, 0, sizeof(struct udcd)); + _fsl_udc_0.parent.type = RT_Device_Class_USBDevice; + _fsl_udc_0.parent.init = drv_ehci0_usbd_init; + _fsl_udc_0.ops = &_ehci0_udc_ops; + /* Register endpoint infomation */ + _fsl_udc_0.ep_pool = _ehci0_ep_pool; + _fsl_udc_0.ep0.id = &_ehci0_ep_pool[0]; + + _fsl_udc_0.device_is_hs = RT_FALSE; + rt_device_register((rt_device_t)&_fsl_udc_0, "usbd", 0); + rt_usb_device_init(); + + return 0; +} +INIT_DEVICE_EXPORT(rt_usbd_init); + +static usb_status_t usb_device_endpoint_callback(usb_device_handle handle, usb_device_endpoint_callback_message_struct_t *message, void *callbackParam) +{ + rt_uint32_t ep_addr = (rt_uint32_t)callbackParam; + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + udcd_t udcd = RT_NULL; + uint8_t state; + if(deviceHandle->controllerId == kUSB_ControllerEhci0) + udcd = &_fsl_udc_0; + + if(message->isSetup) + { + rt_usbd_ep0_setup_handler(udcd, (struct urequest*)message->buffer); + } + else if(ep_addr == 0x00) + { + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + if(state == kUSB_DeviceStateAddressing) + { + if (kStatus_USB_Success == USB_DeviceSetStatus(handle, kUSB_DeviceStatusAddress, NULL)) + { + state = kUSB_DeviceStateAddress; + USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + } + } + rt_usbd_ep0_out_handler(udcd, message->length); + } + else if(ep_addr == 0x80) + { + USB_DeviceGetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + if(state == kUSB_DeviceStateAddressing) + { + if (kStatus_USB_Success == USB_DeviceSetStatus(handle, kUSB_DeviceStatusAddress, NULL)) + { + state = kUSB_DeviceStateAddress; + USB_DeviceSetStatus(handle, kUSB_DeviceStatusDeviceState, &state); + } + } + rt_usbd_ep0_in_handler(udcd); + } + else if(ep_addr & 0x80) + { + rt_usbd_ep_in_handler(udcd, ep_addr, message->length); + } + else + { + rt_usbd_ep_out_handler(udcd, ep_addr, message->length); + } + return kStatus_USB_Success; +} + +static usb_status_t usb_device_callback(usb_device_handle handle, uint32_t callbackEvent, void *eventParam) +{ + usb_status_t error = kStatus_USB_Error; + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + usb_device_endpoint_init_struct_t ep0_init = + { + 0x40, + 0x00, + USB_EP_ATTR_CONTROL, + 0 + }; + usb_device_endpoint_callback_struct_t ep0_callback = + { + usb_device_endpoint_callback, + 0, + 0 + }; + udcd_t udcd = RT_NULL; + if(deviceHandle->controllerId == kUSB_ControllerEhci0) + udcd = &_fsl_udc_0; + + switch (callbackEvent) + { + case kUSB_DeviceEventBusReset: + ep0_init.endpointAddress = 0x00; + ep0_callback.callbackParam = (void *)0x00; + USB_DeviceInitEndpoint(deviceHandle, &ep0_init, &ep0_callback); + ep0_init.endpointAddress = 0x80; + ep0_callback.callbackParam = (void *)0x80; + USB_DeviceInitEndpoint(deviceHandle, &ep0_init, &ep0_callback); + rt_usbd_reset_handler(udcd); + break; + case kUSB_DeviceEventAttach: + rt_usbd_connect_handler(udcd); + break; + case kUSB_DeviceEventDetach: + rt_usbd_disconnect_handler(udcd); + break; + } + return error; +} + +/********************* end of file ************************/ diff --git a/bsp/imxrt/libraries/drivers/usb/device/usb_device.h b/bsp/imxrt/libraries/drivers/usb/device/usb_device.h new file mode 100644 index 0000000000000000000000000000000000000000..99e8a879f86bfd358256b516f140b19a7656b9a0 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/device/usb_device.h @@ -0,0 +1,644 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_USB_DEVICE_H__ +#define __FSL_USB_DEVICE_H__ + +/*! + * @addtogroup usb_device_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines Get/Set status Types */ +typedef enum _usb_device_status +{ + kUSB_DeviceStatusTestMode = 1U, /*!< Test mode */ + kUSB_DeviceStatusSpeed, /*!< Current speed */ + kUSB_DeviceStatusOtg, /*!< OTG status */ + kUSB_DeviceStatusDevice, /*!< Device status */ + kUSB_DeviceStatusEndpoint, /*!< Endpoint state usb_device_endpoint_status_t */ + kUSB_DeviceStatusDeviceState, /*!< Device state */ + kUSB_DeviceStatusAddress, /*!< Device address */ + kUSB_DeviceStatusSynchFrame, /*!< Current frame */ + kUSB_DeviceStatusBus, /*!< Bus status */ + kUSB_DeviceStatusBusSuspend, /*!< Bus suspend */ + kUSB_DeviceStatusBusSleep, /*!< Bus suspend */ + kUSB_DeviceStatusBusResume, /*!< Bus resume */ + kUSB_DeviceStatusRemoteWakeup, /*!< Remote wakeup state */ + kUSB_DeviceStatusBusSleepResume, /*!< Bus resume */ +} usb_device_status_t; + +/*! @brief Defines USB 2.0 device state */ +typedef enum _usb_device_state +{ + kUSB_DeviceStateConfigured = 0U, /*!< Device state, Configured*/ + kUSB_DeviceStateAddress, /*!< Device state, Address*/ + kUSB_DeviceStateDefault, /*!< Device state, Default*/ + kUSB_DeviceStateAddressing, /*!< Device state, Address setting*/ + kUSB_DeviceStateTestMode, /*!< Device state, Test mode*/ +} usb_device_state_t; + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) +typedef enum _usb_dcd_detection_sequence_status +{ + kUSB_DcdDetectionNotEnabled = 0x0U, + kUSB_DcdDataPinDetectionCompleted = 0x01U, + kUSB_DcdChargingPortDetectionCompleted = 0x02U, + kUSB_DcdChargerTypeDetectionCompleted = 0x03U, +} usb_dcd_detection_sequence_status_t; + +typedef enum _usb_dcd_detection_sequence_results +{ + kUSB_DcdDetectionNoResults = 0x0U, + kUSB_DcdDetectionStandardHost = 0x01U, + kUSB_DcdDetectionChargingPort = 0x02U, + kUSB_DcdDetectionDedicatedCharger = 0x03U, +} usb_dcd_detection_sequence_results_t; +#endif + +/*! @brief Defines endpoint state */ +typedef enum _usb_endpoint_status +{ + kUSB_DeviceEndpointStateIdle = 0U, /*!< Endpoint state, idle*/ + kUSB_DeviceEndpointStateStalled, /*!< Endpoint state, stalled*/ +} usb_device_endpoint_status_t; + +/*! @brief Control endpoint index */ +#define USB_CONTROL_ENDPOINT (0U) +/*! @brief Control endpoint maxPacketSize */ +#define USB_CONTROL_MAX_PACKET_SIZE (64U) + +#if (USB_DEVICE_CONFIG_EHCI && (USB_CONTROL_MAX_PACKET_SIZE != (64U))) +#error For high speed, USB_CONTROL_MAX_PACKET_SIZE must be 64!!! +#endif + +/*! @brief The setup packet size of USB control transfer. */ +#define USB_SETUP_PACKET_SIZE (8U) +/*! @brief USB endpoint mask */ +#define USB_ENDPOINT_NUMBER_MASK (0x0FU) + +/*! @brief Default invalid value or the endpoint callback length of cancelled transfer */ +#define USB_UNINITIALIZED_VAL_32 (0xFFFFFFFFU) + +/*! @brief Available common EVENT types in device callback */ +typedef enum _usb_device_event +{ + kUSB_DeviceEventBusReset = 1U, /*!< USB bus reset signal detected */ + kUSB_DeviceEventSuspend, /*!< USB bus suspend signal detected */ + kUSB_DeviceEventResume, /*!< USB bus resume signal detected. The resume signal is driven by itself or a host */ + kUSB_DeviceEventSleeped, /*!< USB bus LPM suspend signal detected */ + kUSB_DeviceEventLPMResume, /*!< USB bus LPM resume signal detected. The resume signal is driven by itself or a host + */ + kUSB_DeviceEventError, /*!< An error is happened in the bus. */ + kUSB_DeviceEventDetach, /*!< USB device is disconnected from a host. */ + kUSB_DeviceEventAttach, /*!< USB device is connected to a host. */ + kUSB_DeviceEventSetConfiguration, /*!< Set configuration. */ + kUSB_DeviceEventSetInterface, /*!< Set interface. */ + + kUSB_DeviceEventGetDeviceDescriptor, /*!< Get device descriptor. */ + kUSB_DeviceEventGetConfigurationDescriptor, /*!< Get configuration descriptor. */ + kUSB_DeviceEventGetStringDescriptor, /*!< Get string descriptor. */ + kUSB_DeviceEventGetHidDescriptor, /*!< Get HID descriptor. */ + kUSB_DeviceEventGetHidReportDescriptor, /*!< Get HID report descriptor. */ + kUSB_DeviceEventGetHidPhysicalDescriptor, /*!< Get HID physical descriptor. */ + kUSB_DeviceEventGetBOSDescriptor, /*!< Get configuration descriptor. */ + kUSB_DeviceEventGetDeviceQualifierDescriptor, /*!< Get device qualifier descriptor. */ + kUSB_DeviceEventVendorRequest, /*!< Vendor request. */ + kUSB_DeviceEventSetRemoteWakeup, /*!< Enable or disable remote wakeup function. */ + kUSB_DeviceEventGetConfiguration, /*!< Get current configuration index */ + kUSB_DeviceEventGetInterface, /*!< Get current interface alternate setting value */ + kUSB_DeviceEventSetBHNPEnable, +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) + kUSB_DeviceEventDcdTimeOut, /*!< Dcd detect result is timeout */ + kUSB_DeviceEventDcdUnknownType, /*!< Dcd detect result is unknown type */ + kUSB_DeviceEventSDPDetected, /*!< The SDP facility is detected */ + kUSB_DeviceEventChargingPortDetected, /*!< The charging port is detected */ + kUSB_DeviceEventChargingHostDetected, /*!< The CDP facility is detected */ + kUSB_DeviceEventDedicatedChargerDetected, /*!< The DCP facility is detected */ +#endif +} usb_device_event_t; + +/*! @brief Endpoint callback message structure */ +typedef struct _usb_device_endpoint_callback_message_struct +{ + uint8_t *buffer; /*!< Transferred buffer */ + uint32_t length; /*!< Transferred data length */ + uint8_t isSetup; /*!< Is in a setup phase */ +} usb_device_endpoint_callback_message_struct_t; + +/*! + * @brief Endpoint callback function typedef. + * + * This callback function is used to notify the upper layer what the transfer result is. + * This callback pointer is passed when a specified endpoint is initialized by calling API #USB_DeviceInitEndpoint. + * + * @param handle The device handle. It equals to the value returned from #USB_DeviceInit. + * @param message The result of a transfer, which includes transfer buffer, transfer length, and whether is in a + * setup phase. + * phase for control pipe. + * @param callbackParam The parameter for this callback. It is same with + * usb_device_endpoint_callback_struct_t::callbackParam. + * + * @return A USB error code or kStatus_USB_Success. + */ +typedef usb_status_t (*usb_device_endpoint_callback_t)(usb_device_handle handle, + usb_device_endpoint_callback_message_struct_t *message, + void *callbackParam); + +/*! + * @brief Device callback function typedef. + * + * This callback function is used to notify the upper layer that the device status has changed. + * This callback pointer is passed by calling API #USB_DeviceInit. + * + * @param handle The device handle. It equals the value returned from #USB_DeviceInit. + * @param callbackEvent The callback event type. See enumeration #usb_device_event_t. + * @param eventParam The event parameter for this callback. The parameter type is determined by the callback event. + * + * @return A USB error code or kStatus_USB_Success. + */ +typedef usb_status_t (*usb_device_callback_t)(usb_device_handle handle, uint32_t callbackEvent, void *eventParam); + +/*! @brief Endpoint callback structure */ +typedef struct _usb_device_endpoint_callback_struct +{ + usb_device_endpoint_callback_t callbackFn; /*!< Endpoint callback function*/ + void *callbackParam; /*!< Parameter for callback function*/ + uint8_t isBusy; +} usb_device_endpoint_callback_struct_t; + +/*! @brief Endpoint initialization structure */ +typedef struct _usb_device_endpoint_init_struct +{ + uint16_t maxPacketSize; /*!< Endpoint maximum packet size */ + uint8_t endpointAddress; /*!< Endpoint address*/ + uint8_t transferType; /*!< Endpoint transfer type*/ + uint8_t zlt; /*!< ZLT flag*/ +} usb_device_endpoint_init_struct_t; + +/*! @brief Endpoint status structure */ +typedef struct _usb_device_endpoint_status_struct +{ + uint8_t endpointAddress; /*!< Endpoint address */ + uint16_t endpointStatus; /*!< Endpoint status : idle or stalled */ +} usb_device_endpoint_status_struct_t; + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) +/*! @brief USB DCD charge timing specification structure */ +typedef struct _usb_device_dcd_charging_time +{ + uint16_t dcdSeqInitTime; /*!< The dcd sequence init time */ + uint16_t dcdDbncTime; /*!< The debounce time period on DP signal */ + uint16_t dcdDpSrcOnTime; /*!< The time period comparator enabled */ + uint16_t dcdTimeWaitAfterPrD; /*!< The time period between primary and secondary detection */ + uint8_t dcdTimeDMSrcOn; /*!< The amount of time that the modules enable the Vdm_src */ +} usb_device_dcd_charging_time_t; +#endif + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @name USB device APIs + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Initializes the USB device stack. + * + * This function initializes the USB device module specified by the controllerId. + * + * @param[in] controllerId The controller ID of the USB IP. See the enumeration #usb_controller_index_t. + * @param[in] deviceCallback Function pointer of the device callback. + * @param[out] handle It is an out parameter used to return the pointer of the device handle to the caller. + * + * @retval kStatus_USB_Success The device is initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. + * @retval kStatus_USB_Busy Cannot allocate a device handle. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller according to the controller id. + * @retval kStatus_USB_InvalidControllerInterface The controller driver interfaces is invalid. There is an empty + * interface entity. + * @retval kStatus_USB_Error The macro USB_DEVICE_CONFIG_ENDPOINTS is more than the IP's endpoint number. + * Or, the device has been initialized. + * Or, the mutex or message queue is created failed. + */ +extern usb_status_t USB_DeviceInit(uint8_t controllerId, + usb_device_callback_t deviceCallback, + usb_device_handle *handle); + +/*! + * @brief Enables the device functionality. + * + * The function enables the device functionality, so that the device can be recognized by the host when the device + * detects that it has been connected to a host. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +extern usb_status_t USB_DeviceRun(usb_device_handle handle); + +/*! + * @brief Disables the device functionality. + * + * The function disables the device functionality. After this function called, even if the device is detached to the + * host, + * it can't work. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. + */ +extern usb_status_t USB_DeviceStop(usb_device_handle handle); + +/*! + * @brief De-initializes the device controller. + * + * The function de-initializes the device controller specified by the handle. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. + */ +extern usb_status_t USB_DeviceDeinit(usb_device_handle handle); + +/*! + * @brief Sends data through a specified endpoint. + * + * The function is used to send data through a specified endpoint. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to hold the data need to be sent. The function is not reentrant. + * @param[in] length The data length need to be sent. + * + * @retval kStatus_USB_Success The send request is sent successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Busy Cannot allocate DTDS for current transfer in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error The device is doing reset. + * + * @note The return value indicates whether the sending request is successful or not. The transfer done is notified by + * the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue on the application level. + * The subsequent transfer can begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +extern usb_status_t USB_DeviceSendRequest(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Receives data through a specified endpoint. + * + * The function is used to receive data through a specified endpoint. The function is not reentrant. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to save the received data. + * @param[in] length The data length want to be received. + * + * @retval kStatus_USB_Success The receive request is sent successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Busy Cannot allocate DTDS for current transfer in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error The device is doing reset. + * + * @note The return value indicates whether the receiving request is successful or not. The transfer done is notified by + * the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue on the application level. + * The subsequent transfer can begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +extern usb_status_t USB_DeviceRecvRequest(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Cancels the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The transfer is cancelled. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer or the controller handle is invalid. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceCancel(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Initializes a specified endpoint. + * + * The function is used to initialize a specified endpoint. The corresponding endpoint callback is also initialized. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * @param[in] epInit Endpoint initialization structure. See the structure usb_device_endpoint_init_struct_t. + * @param[in] epCallback Endpoint callback structure. See the structure + * usb_device_endpoint_callback_struct_t. + * + * @retval kStatus_USB_Success The endpoint is initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The epInit or epCallback is NULL pointer. Or the endpoint number is + * more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceInitEndpoint(usb_device_handle handle, + usb_device_endpoint_init_struct_t *epInit, + usb_device_endpoint_callback_struct_t *epCallback); + +/*! + * @brief Deinitializes a specified endpoint. + * + * The function is used to deinitializes a specified endpoint. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is de-initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceDeinitEndpoint(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Stalls a specified endpoint. + * + * The function is used to stall a specified endpoint. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is stalled successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceStallEndpoint(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Unstalls a specified endpoint. + * + * The function is used to unstall a specified endpoint. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is unstalled successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceUnstallEndpoint(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Gets the status of the selected item. + * + * The function is used to get the status of the selected item. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] type The selected item. See the structure #usb_device_status_t. + * @param[out] param The parameter type is determined by the selected item. + * + * @retval kStatus_USB_Success Get status successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The parameter is NULL pointer. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error Unsupported type. + */ +extern usb_status_t USB_DeviceGetStatus(usb_device_handle handle, usb_device_status_t type, void *param); + +/*! + * @brief Sets the status of the selected item. + * + * The function is used to set the status of the selected item. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] type The selected item. See the structure #usb_device_status_t. + * @param[in] param The parameter type is determined by the selected item. + * + * @retval kStatus_USB_Success Set status successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error Unsupported type or the parameter is NULL pointer. + */ +extern usb_status_t USB_DeviceSetStatus(usb_device_handle handle, usb_device_status_t type, void *param); + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) +/*! + * @brief Initializes the device dcd module. + * + * The function initializes the device dcd module. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] time_param The time parameter used to config the dcd timing registers. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +extern usb_status_t USB_DeviceDcdInitModule(usb_device_handle handle, void *time_param); + +/*! + * @brief De-initializes the device dcd module. + * + * The function de-initializes the device dcd module specified by the handle. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. + */ +extern usb_status_t USB_DeviceDcdDeinitModule(usb_device_handle handle); +#endif +/*! + * @brief Device task function. + * + * The function is used to handle the controller message. + * This function should not be called in the application directly. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceTaskFunction(void *deviceHandle); + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +/*! + * @brief Device KHCI task function. + * + * The function is used to handle the KHCI controller message. + * In the bare metal environment, this function should be called periodically in the main function. + * In the RTOS environment, this function should be used as a function entry to create a task. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +#define USB_DeviceKhciTaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +/*! + * @brief Device EHCI task function. + * + * The function is used to handle the EHCI controller message. + * In the bare metal environment, this function should be called periodically in the main function. + * In the RTOS environment, this function should be used as a function entry to create a task. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +#define USB_DeviceEhciTaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) +/*! + * @brief Device EHCI DCD ISR function. + * + * The function is the EHCI DCD interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceDcdHSIsrFunction(void *deviceHandle); +#endif +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +/*! + * @brief Device LPC ip3511 controller task function. + * + * The function is used to handle the LPC ip3511 controller message. + * In the bare metal environment, this function should be called periodically in the main function. + * In the RTOS environment, this function should be used as a function entry to create a task. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +#define USB_DeviceLpcIp3511TaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) +#endif + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +/*! + * @brief Device KHCI ISR function. + * + * The function is the KHCI interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceKhciIsrFunction(void *deviceHandle); +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) +/*! + * @brief Device KHCI DCD ISR function. + * + * The function is the KHCI DCD interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceDcdIsrFunction(void *deviceHandle); +#endif +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +/*! + * @brief Device EHCI ISR function. + * + * The function is the EHCI interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceEhciIsrFunction(void *deviceHandle); +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +/*! + * @brief Device LPC USB ISR function. + * + * The function is the LPC USB interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceLpcIp3511IsrFunction(void *deviceHandle); +#endif + +/*! + * @brief Gets the device stack version function. + * + * The function is used to get the device stack version. + * + * @param[out] version The version structure pointer to keep the device stack version. + * + */ +extern void USB_DeviceGetVersion(uint32_t *version); + +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) +/*! + * @brief Update the hardware tick. + * + * The function is used to update the hardware tick. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] tick Current hardware tick(uint is ms). + * + */ +extern usb_status_t USB_DeviceUpdateHwTick(usb_device_handle handle, uint64_t tick); +#endif + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* __USB_DEVICE_H__ */ diff --git a/bsp/imxrt/libraries/drivers/usb/device/usb_device_dci.c b/bsp/imxrt/libraries/drivers/usb/device/usb_device_dci.c new file mode 100644 index 0000000000000000000000000000000000000000..7a9e0d305f2b1c71202e5bd45eae4470407a0f37 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/device/usb_device_dci.c @@ -0,0 +1,1462 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "usb_device.h" +#include "usb_device_dci.h" + +#include "fsl_device_registers.h" + +#if ((defined(USB_DEVICE_CONFIG_NUM)) && (USB_DEVICE_CONFIG_NUM > 0U)) + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +#include "usb_device_khci.h" +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +#include "usb_device_ehci.h" +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +#include "usb_device_lpcip3511.h" +#endif + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) +#include "fsl_cache.h" +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static usb_status_t USB_DeviceAllocateHandle(uint8_t controllerId, usb_device_struct_t **handle); +static usb_status_t USB_DeviceFreeHandle(usb_device_struct_t *handle); +static usb_status_t USB_DeviceGetControllerInterface( + uint8_t controllerId, const usb_device_controller_interface_struct_t **controllerInterface); +static usb_status_t USB_DeviceTransfer(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); +static usb_status_t USB_DeviceControl(usb_device_handle handle, usb_device_control_type_t type, void *param); +static usb_status_t USB_DeviceResetNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +static usb_status_t USB_DeviceSuspendNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); +static usb_status_t USB_DeviceResumeNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); +#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) +static usb_status_t USB_DeviceSleepNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); + +#endif +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ +#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U)) +static usb_status_t USB_DeviceDetachNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); +static usb_status_t USB_DeviceAttachNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message); +#endif +static usb_status_t USB_DeviceNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +USB_GLOBAL static usb_device_struct_t s_UsbDevice[USB_DEVICE_CONFIG_NUM]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Allocate a device handle. + * + * This function allocates a device handle. + * + * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t. + * @param handle It is out parameter, is used to return pointer of the device handle to the caller. + * + * @retval kStatus_USB_Success Get a device handle successfully. + * @retval kStatus_USB_Busy Cannot allocate a device handle. + * @retval kStatus_USB_Error The device has been initialized. + */ +static usb_status_t USB_DeviceAllocateHandle(uint8_t controllerId, usb_device_struct_t **handle) +{ + uint32_t count; + USB_OSA_SR_ALLOC(); + + USB_OSA_ENTER_CRITICAL(); + /* Check the controller is initialized or not. */ + for (count = 0U; count < USB_DEVICE_CONFIG_NUM; count++) + { + if ((NULL != s_UsbDevice[count].controllerHandle) && (controllerId == s_UsbDevice[count].controllerId)) + { + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Error; + } + } + /* Get a free device handle. */ + for (count = 0U; count < USB_DEVICE_CONFIG_NUM; count++) + { + if (NULL == s_UsbDevice[count].controllerHandle) + { + s_UsbDevice[count].controllerId = controllerId; + *handle = &s_UsbDevice[count]; + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; + } + } + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Busy; +} + +/*! + * @brief Free a device handle. + * + * This function frees a device handle. + * + * @param handle The device handle. + * + * @retval kStatus_USB_Success Free device handle successfully. + */ +static usb_status_t USB_DeviceFreeHandle(usb_device_struct_t *handle) +{ + USB_OSA_SR_ALLOC(); + + USB_OSA_ENTER_CRITICAL(); + handle->controllerHandle = NULL; + handle->controllerId = 0U; + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; +} + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +/* KHCI device driver interface */ +static const usb_device_controller_interface_struct_t s_UsbDeviceKhciInterface = { + USB_DeviceKhciInit, USB_DeviceKhciDeinit, USB_DeviceKhciSend, + USB_DeviceKhciRecv, USB_DeviceKhciCancel, USB_DeviceKhciControl +}; +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +/* EHCI device driver interface */ +static const usb_device_controller_interface_struct_t s_UsbDeviceEhciInterface = { + USB_DeviceEhciInit, USB_DeviceEhciDeinit, USB_DeviceEhciSend, + USB_DeviceEhciRecv, USB_DeviceEhciCancel, USB_DeviceEhciControl +}; +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +/* EHCI device driver interface */ +static const usb_device_controller_interface_struct_t s_UsbDeviceLpc3511IpInterface = { + USB_DeviceLpc3511IpInit, USB_DeviceLpc3511IpDeinit, USB_DeviceLpc3511IpSend, + USB_DeviceLpc3511IpRecv, USB_DeviceLpc3511IpCancel, USB_DeviceLpc3511IpControl +}; +#endif + +/*! + * @brief Get the controller interface handle. + * + * This function is used to get the controller interface handle. + * + * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t. + * @param controllerInterface It is out parameter, is used to return pointer of the device controller handle to the + * caller. + * + * @retval kStatus_USB_Success Get a device handle successfully. + * @retval kStatus_USB_ControllerNotFound The controller id is invalided. + */ +static usb_status_t USB_DeviceGetControllerInterface( + uint8_t controllerId, const usb_device_controller_interface_struct_t **controllerInterface) +{ + usb_status_t error = kStatus_USB_ControllerNotFound; + switch (controllerId) + { +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) + /* Get the KHCI controller driver interface */ + case kUSB_ControllerKhci0: + case kUSB_ControllerKhci1: + *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceKhciInterface; + error = kStatus_USB_Success; + break; +#endif +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) + /* Get the EHCI controller driver interface */ + case kUSB_ControllerEhci0: + case kUSB_ControllerEhci1: + error = kStatus_USB_Success; + *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceEhciInterface; + break; +#endif +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) + /* Get the EHCI controller driver interface */ + case kUSB_ControllerLpcIp3511Fs0: + case kUSB_ControllerLpcIp3511Fs1: + case kUSB_ControllerLpcIp3511Hs0: + case kUSB_ControllerLpcIp3511Hs1: + error = kStatus_USB_Success; + *controllerInterface = (const usb_device_controller_interface_struct_t *)&s_UsbDeviceLpc3511IpInterface; + break; +#endif + default: + break; + } + return error; +} + +/*! + * @brief Start a new transfer. + * + * This function is used to start a new transfer. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param endpointAddress Endpoint address. Bit7 is direction, 0U - USB_OUT, 1U - USB_IN. + * @param buffer The memory address to be transferred, or the memory address to hold the data need to be + * sent. + * @param length The length of the data. + * + * @retval kStatus_USB_Success Get a device handle successfully. + * @retval kStatus_USB_InvalidHandle The device handle is invalided. + * @retval kStatus_USB_ControllerNotFound The controller interface is not found. + * @retval kStatus_USB_Error The device is doing reset. + */ +static usb_status_t USB_DeviceTransfer(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + usb_status_t error = kStatus_USB_Error; + uint8_t endpoint = endpointAddress & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + USB_OSA_SR_ALLOC(); + + if (NULL == deviceHandle) + { + return kStatus_USB_InvalidHandle; + } + + if (NULL != deviceHandle->controllerInterface) + { + if (deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy) + { + return kStatus_USB_Busy; + } + USB_OSA_ENTER_CRITICAL(); + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 1U; + USB_OSA_EXIT_CRITICAL(); + if (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) + { +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + if (length) + { + DCACHE_CleanByRange((uint32_t)buffer, length); + } +#endif + /* Call the controller send interface. */ + error = deviceHandle->controllerInterface->deviceSend(deviceHandle->controllerHandle, endpointAddress, + buffer, length); + } + else + { +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + if (length) + { + DCACHE_CleanInvalidateByRange((uint32_t)buffer, length); + } +#endif + /* Call the controller receive interface. */ + error = deviceHandle->controllerInterface->deviceRecv(deviceHandle->controllerHandle, endpointAddress, + buffer, length); + } + if (kStatus_USB_Success != error) + { + USB_OSA_ENTER_CRITICAL(); + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U; + USB_OSA_EXIT_CRITICAL(); + } + } + else + { + error = kStatus_USB_ControllerNotFound; + } + return error; +} + +/*! + * @brief Control the status of the selected item. + * + * This function is used to control the status of the selected item.. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param type The control type, please refer to the enumeration usb_device_control_type_t. + * @param param The param type is determined by the selected item. + * + * @retval kStatus_USB_Success Get a device handle successfully. + * @retval kStatus_USB_InvalidHandle The device handle is invalided. + * @retval kStatus_USB_ControllerNotFound The controller interface is not found. + * @retval kStatus_USB_Error Unsupport type. + * Or, the param is NULL pointer. + */ +static usb_status_t USB_DeviceControl(usb_device_handle handle, usb_device_control_type_t type, void *param) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + usb_status_t error = kStatus_USB_Error; + + if (NULL == deviceHandle) + { + return kStatus_USB_InvalidHandle; + } + + if (NULL != deviceHandle->controllerInterface) + { + /* Call the controller control interface. */ + error = deviceHandle->controllerInterface->deviceControl(deviceHandle->controllerHandle, type, param); + } + else + { + error = kStatus_USB_ControllerNotFound; + } + return error; +} + +/*! + * @brief Handle the reset notification. + * + * This function is used to handle the reset notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @retval kStatus_USB_Success Get a device handle successfully. + */ +static usb_status_t USB_DeviceResetNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_SR_ALLOC(); +#endif + + handle->isResetting = 1U; + +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + /* Clear remote wakeup feature */ + handle->remotewakeup = 0U; +#endif + +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_ENTER_CRITICAL(); + handle->epCallbackDirectly = 1; + USB_OSA_EXIT_CRITICAL(); +#endif + /* Set the controller to default status. */ + USB_DeviceControl(handle, kUSB_DeviceControlSetDefaultStatus, NULL); +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_ENTER_CRITICAL(); + handle->epCallbackDirectly = 0; + USB_OSA_EXIT_CRITICAL(); +#endif + + handle->state = kUSB_DeviceStateDefault; + handle->deviceAddress = 0U; + + for (uint32_t count = 0U; count < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); count++) + { + handle->epCallback[count].callbackFn = (usb_device_endpoint_callback_t)NULL; + handle->epCallback[count].callbackParam = NULL; + handle->epCallback[count].isBusy = 0U; + } + + /* Call device callback to notify the application that the USB bus reset signal detected. */ + handle->deviceCallback(handle, kUSB_DeviceEventBusReset, NULL); + + handle->isResetting = 0U; + return kStatus_USB_Success; +} + +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +/*! + * @brief Handle the suspend notification. + * + * This function is used to handle the suspend notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceSuspendNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the USB bus suspend signal detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventSuspend, NULL); +} + +/*! + * @brief Handle the resume notification. + * + * This function is used to handle the resume notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceResumeNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the USB bus resume signal detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventResume, NULL); +} +#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) +/*! + * @brief Handle the suspend notification. + * + * This function is used to handle the suspend notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceSleepNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the USB bus suspend signal detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventSleeped, NULL); +} +#endif +/*! + * @brief Handle the remotewakeup notification. + * + * This function is used to handle the remotewakeup notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param flag The buffer pointer to store remotewakeup flag. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceGetRemoteWakeUp(usb_device_struct_t *handle, uint8_t **flag) +{ + /* Call device callback to notify the application that the USB bus suspend signal detected. */ + return USB_DeviceControl(handle, kUSB_DeviceControlGetRemoteWakeUp, flag); +} + +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + +#if (defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U)) +usb_status_t USB_DeviceErrorNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the USB bus error signal detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventError, NULL); +} +#endif /* USB_DEVICE_CONFIG_ERROR_HANDLING */ + +#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U)) +/*! + * @brief Handle the detach notification. + * + * This function is used to handle the detach notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDetachNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the device is disconnected from a host. */ + return handle->deviceCallback(handle, kUSB_DeviceEventDetach, NULL); +} + +/*! + * @brief Handle the attach notification. + * + * This function is used to handle the attach notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceAttachNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the device is connected to a host. */ + return handle->deviceCallback(handle, kUSB_DeviceEventAttach, NULL); +} +#endif + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + ((defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) || \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))) +/*! + * @brief Handle the dcd module timeout notification. + * + * This function is used to handle the dcd module timeout notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDcdTimeOutNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the device charger detect timeout happened. */ + return handle->deviceCallback(handle, kUSB_DeviceEventDcdTimeOut, NULL); +} + +/*! + * @brief Handle the dcd module unknown port type notification. + * + * This function is used to handle the dcd module unknown port type notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDcdUnknownPortTypeNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the device charger detect unknown port type happened. */ + return handle->deviceCallback(handle, kUSB_DeviceEventDcdUnknownType, NULL); +} + +/*! + * @brief Handle the SDP facility is detected notification. + * + * This function is used to handle the SDP facility is detectednotification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDcdSDPDetectNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the SDP facility is detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventSDPDetected, NULL); +} + +/*! + * @brief Handle the charging port is detected notification. + * + * This function is used to handle the charging port is detectednotification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDcdChargingPortDetectNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the charing port is detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventChargingPortDetected, NULL); +} + +/*! + * @brief Handle the CDP facility is detected notification. + * + * This function is used to handle the CDP facility is detectednotification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceDcdChargingHostDetectNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the CDP facility is detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventChargingHostDetected, NULL); +} + +/*! + * @brief Handle the DCP facility is detected notification. + * + * This function is used to handle the DCP facility is detectednotification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ + +static usb_status_t USB_DeviceDcdDedicatedChargerDetectNotification(usb_device_struct_t *handle, + usb_device_callback_message_struct_t *message) +{ + /* Call device callback to notify the application that the DCP facility is detected. */ + return handle->deviceCallback(handle, kUSB_DeviceEventDedicatedChargerDetected, NULL); +} +#endif + +/*! + * @brief Handle the attach notification. + * + * This function is used to handle the attach notification. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceNotification(usb_device_struct_t *handle, usb_device_callback_message_struct_t *message) +{ + uint8_t endpoint = message->code & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = (message->code & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + usb_status_t error = kStatus_USB_Error; + + switch (message->code) + { + case kUSB_DeviceNotifyBusReset: + error = USB_DeviceResetNotification(handle, message); + break; +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + case kUSB_DeviceNotifySuspend: + error = USB_DeviceSuspendNotification(handle, message); + break; + case kUSB_DeviceNotifyResume: + error = USB_DeviceResumeNotification(handle, message); + break; +#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) + case kUSB_DeviceNotifyLPMSleep: + error = USB_DeviceSleepNotification(handle, message); + break; +#endif +#endif + +#if (defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U)) + case kUSB_DeviceNotifyError: + error = USB_DeviceErrorNotification(handle, message); + break; +#endif + +#if USB_DEVICE_CONFIG_DETACH_ENABLE + case kUSB_DeviceNotifyDetach: + error = USB_DeviceDetachNotification(handle, message); + break; + case kUSB_DeviceNotifyAttach: + error = USB_DeviceAttachNotification(handle, message); + break; +#endif +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + ((defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) || \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))) + case kUSB_DeviceNotifyDcdTimeOut: + error = USB_DeviceDcdTimeOutNotification(handle, message); + break; + case kUSB_DeviceNotifyDcdUnknownPortType: + error = USB_DeviceDcdUnknownPortTypeNotification(handle, message); + break; + case kUSB_DeviceNotifySDPDetected: + error = USB_DeviceDcdSDPDetectNotification(handle, message); + break; + case kUSB_DeviceNotifyChargingPortDetected: + error = USB_DeviceDcdChargingPortDetectNotification(handle, message); + break; + case kUSB_DeviceNotifyChargingHostDetected: + error = USB_DeviceDcdChargingHostDetectNotification(handle, message); + break; + case kUSB_DeviceNotifyDedicatedChargerDetected: + error = USB_DeviceDcdDedicatedChargerDetectNotification(handle, message); + break; +#endif + + default: + if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS) + { + if (handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn) + { + usb_device_endpoint_callback_message_struct_t endpointCallbackMessage; + endpointCallbackMessage.buffer = message->buffer; + endpointCallbackMessage.length = message->length; + endpointCallbackMessage.isSetup = message->isSetup; + if (message->isSetup) + { + handle->epCallback[0].isBusy = 0U; + handle->epCallback[1].isBusy = 0U; + } + else + { + handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U; + } + /* Call endpoint callback */ + error = handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn( + handle, &endpointCallbackMessage, + handle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam); + } + } + break; + } + return error; +} + +/*! + * @brief Notify the device that the controller status changed. + * + * This function is used to notify the device that the controller status changed. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceNotificationTrigger(void *handle, void *msg) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + usb_device_callback_message_struct_t *message = (usb_device_callback_message_struct_t *)msg; + + if ((NULL == msg) || (NULL == handle)) + { + return kStatus_USB_InvalidHandle; + } + + /* The device callback is invalid or not. */ + if (!deviceHandle->deviceCallback) + { + return kStatus_USB_Error; + } + +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + if (deviceHandle->epCallbackDirectly) + { + if ((message->code & USB_ENDPOINT_NUMBER_MASK) && (!(message->code & 0x70U))) + { + return USB_DeviceNotification(deviceHandle, message); + } + } + + /* Add the message to message queue when the device task is enabled. */ + if (kStatus_USB_OSA_Success != USB_OsaMsgqSend(deviceHandle->notificationQueue, (void *)message)) + { + return kStatus_USB_Busy; + } + return kStatus_USB_Success; +#else + /* Handle the notification by calling USB_DeviceNotification. */ + return USB_DeviceNotification(deviceHandle, message); +#endif +} + +/*! + * @brief Initialize the USB device stack. + * + * This function initializes the USB device module specified by the controllerId. + * + * @param controllerId The controller id of the USB IP. Please refer to the enumeration usb_controller_index_t. + * @param deviceCallback Function pointer of the device callback. + * @param handle It is out parameter, is used to return pointer of the device handle to the caller. + * + * @retval kStatus_USB_Success The device is initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. + * @retval kStatus_USB_Busy Cannot allocate a device handle. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller according to the controller id. + * @retval kStatus_USB_InvalidControllerInterface The controller driver interfaces is invaild, There is an empty + * interface entity. + * @retval kStatus_USB_Error The macro USB_DEVICE_CONFIG_ENDPOINTS is more than IP's endpoint number. + * Or, the device has been initialized. + * Or, the message queue is created failed. + */ +usb_status_t USB_DeviceInit(uint8_t controllerId, usb_device_callback_t deviceCallback, usb_device_handle *handle) +{ + usb_device_struct_t *deviceHandle = NULL; + usb_status_t error; + uint32_t count; + + if (NULL == handle) + { + return kStatus_USB_InvalidHandle; + } + + /* Allocate a device handle by using the controller id. */ + error = USB_DeviceAllocateHandle(controllerId, &deviceHandle); + + if (kStatus_USB_Success != error) + { + return error; + } + + /* Save the device callback */ + deviceHandle->deviceCallback = deviceCallback; + /* Save the controller id */ + deviceHandle->controllerId = controllerId; + /* Clear the device address */ + deviceHandle->deviceAddress = 0U; + /* Clear the device reset state */ + deviceHandle->isResetting = 0U; + + /* Initialize the enpoints */ + for (count = 0U; count < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); count++) + { + deviceHandle->epCallback[count].callbackFn = (usb_device_endpoint_callback_t)NULL; + deviceHandle->epCallback[count].callbackParam = NULL; + deviceHandle->epCallback[count].isBusy = 0U; + } + + /* Get the controller interface according to the controller id */ + error = USB_DeviceGetControllerInterface(controllerId, &deviceHandle->controllerInterface); + if (kStatus_USB_Success != error) + { + USB_DeviceFreeHandle(deviceHandle); + return error; + } + if (NULL == deviceHandle->controllerInterface) + { + USB_DeviceFreeHandle(deviceHandle); + return kStatus_USB_ControllerNotFound; + } + if (((usb_device_controller_init_t)NULL == deviceHandle->controllerInterface->deviceInit) || + ((usb_device_controller_deinit_t)NULL == deviceHandle->controllerInterface->deviceDeinit) || + ((usb_device_controller_send_t)NULL == deviceHandle->controllerInterface->deviceSend) || + ((usb_device_controller_recv_t)NULL == deviceHandle->controllerInterface->deviceRecv) || + ((usb_device_controller_cancel_t)NULL == deviceHandle->controllerInterface->deviceCancel) || + ((usb_device_controller_control_t)NULL == deviceHandle->controllerInterface->deviceControl)) + { + USB_DeviceFreeHandle(deviceHandle); + return kStatus_USB_InvalidControllerInterface; + } + +#if USB_DEVICE_CONFIG_USE_TASK + /* Create a message queue when the device handle is enabled. */ + if (kStatus_USB_OSA_Success != + USB_OsaMsgqCreate(&deviceHandle->notificationQueue, USB_DEVICE_CONFIG_MAX_MESSAGES, + (1U + (sizeof(usb_device_callback_message_struct_t) - 1U) / sizeof(uint32_t)))) + { + USB_DeviceDeinit(deviceHandle); + return kStatus_USB_Error; + } +#endif + + *handle = deviceHandle; + + /* Initialize the controller */ + error = deviceHandle->controllerInterface->deviceInit(controllerId, deviceHandle, &deviceHandle->controllerHandle); + if (kStatus_USB_Success != error) + { + USB_DeviceDeinit(deviceHandle); + *handle = NULL; + return error; + } + /* Set the device to deafult state */ + deviceHandle->state = kUSB_DeviceStateDefault; + + return error; +} + +/*! + * @brief Enable the device functionality. + * + * The function enables the device functionality, so that the device can be recognized by the host when the device + * detects that it has been connected to a host. + * + * @param handle The device handle got from USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +usb_status_t USB_DeviceRun(usb_device_handle handle) +{ + return USB_DeviceControl(handle, kUSB_DeviceControlRun, NULL); +} +/*! + * @brief Disable the device functionality. + * + * The function disables the device functionality, after this function called, even the device is detached to the host, + * and the device can't work. + * + * @param handle The device handle got from USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + */ +usb_status_t USB_DeviceStop(usb_device_handle handle) +{ + return USB_DeviceControl(handle, kUSB_DeviceControlStop, NULL); +} +/*! + * @brief De-initialize the device controller. + * + * The function de-initializes the device controller specified by the handle. + * + * @param handle The device handle got from USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + */ +usb_status_t USB_DeviceDeinit(usb_device_handle handle) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + + if (NULL == deviceHandle) + { + return kStatus_USB_InvalidHandle; + } + /* De-initialize the controller */ + if (NULL != deviceHandle->controllerInterface) + { + deviceHandle->controllerInterface->deviceDeinit(deviceHandle->controllerHandle); + deviceHandle->controllerInterface = (usb_device_controller_interface_struct_t *)NULL; + } + +#if USB_DEVICE_CONFIG_USE_TASK + /* Destroy the message queue. */ + if (NULL != deviceHandle->notificationQueue) + { + USB_OsaMsgqDestroy(deviceHandle->notificationQueue); + deviceHandle->notificationQueue = NULL; + } +#endif + + /* Free the device handle. */ + USB_DeviceFreeHandle(deviceHandle); + return kStatus_USB_Success; +} + +/*! + * @brief Send data through a specified endpoint. + * + * The function is used to send data through a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint index. + * @param buffer The memory address to hold the data need to be sent. + * @param length The data length need to be sent. + * + * @retval kStatus_USB_Success The send request is sent successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Busy Cannot allocate dtds for current tansfer in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error The device is doing reset. + * + * @note The return value just means if the sending request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceSendRequest(usb_device_handle handle, uint8_t endpointAddress, uint8_t *buffer, uint32_t length) +{ + return USB_DeviceTransfer(handle, (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | + (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), + buffer, length); +} + +/*! + * @brief Receive data through a specified endpoint. + * + * The function is used to receive data through a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint index. + * @param buffer The memory address to save the received data. + * @param length The data length want to be received. + * + * @retval kStatus_USB_Success The receive request is sent successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Busy Cannot allocate dtds for current tansfer in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error The device is doing reset. + * + * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceRecvRequest(usb_device_handle handle, uint8_t endpointAddress, uint8_t *buffer, uint32_t length) +{ + return USB_DeviceTransfer(handle, (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | + (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), + buffer, length); +} + +/*! + * @brief Cancel the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. + * + * @retval kStatus_USB_Success The transfer is cancelled. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +usb_status_t USB_DeviceCancel(usb_device_handle handle, uint8_t endpointAddress) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + usb_status_t error = kStatus_USB_Error; + + if (NULL == deviceHandle) + { + return kStatus_USB_InvalidHandle; + } + + if (NULL != deviceHandle->controllerInterface) + { + error = deviceHandle->controllerInterface->deviceCancel(deviceHandle->controllerHandle, endpointAddress); + } + else + { + error = kStatus_USB_ControllerNotFound; + } + return error; +} + +/*! + * @brief Initialize a specified endpoint. + * + * The function is used to initialize a specified endpoint and the corresponding endpoint callback is also initialized. + * + * @param handle The device handle got from USB_DeviceInit. + * @param epInit Endpoint initizlization structure. Please refer to the structure usb_device_endpoint_init_struct_t. + * @param epCallback Endpoint callback structure. Please refer to the structure + * usb_device_endpoint_callback_struct_t. + * + * @retval kStatus_USB_Success The endpoint is initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The epInit or epCallback is NULL pointer. Or the endpoint number is + * more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +usb_status_t USB_DeviceInitEndpoint(usb_device_handle handle, + usb_device_endpoint_init_struct_t *epInit, + usb_device_endpoint_callback_struct_t *epCallback) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + uint8_t endpoint; + uint8_t direction; + + if (!deviceHandle) + { + return kStatus_USB_InvalidHandle; + } + + if ((!epInit) || (!epCallback)) + { + return kStatus_USB_InvalidParameter; + } + + endpoint = epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK; + direction = (epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + + if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS) + { + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn = epCallback->callbackFn; + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam = + epCallback->callbackParam; + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U; + } + else + { + return kStatus_USB_InvalidParameter; + } + return USB_DeviceControl(handle, kUSB_DeviceControlEndpointInit, epInit); +} + +/*! + * @brief De-initizlize a specified endpoint. + * + * The function is used to de-initizlize a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is de-initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +usb_status_t USB_DeviceDeinitEndpoint(usb_device_handle handle, uint8_t endpointAddress) +{ + usb_device_struct_t *deviceHandle = (usb_device_struct_t *)handle; + uint8_t endpoint = endpointAddress & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = (endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + usb_status_t error = kStatus_USB_Error; +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_SR_ALLOC(); +#endif + + if (!deviceHandle) + { + return kStatus_USB_InvalidHandle; + } +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_ENTER_CRITICAL(); + deviceHandle->epCallbackDirectly = 1; + USB_OSA_EXIT_CRITICAL(); +#endif + error = USB_DeviceControl(handle, kUSB_DeviceControlEndpointDeinit, &endpointAddress); +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + USB_OSA_ENTER_CRITICAL(); + deviceHandle->epCallbackDirectly = 0; + USB_OSA_EXIT_CRITICAL(); +#endif + + if (endpoint < USB_DEVICE_CONFIG_ENDPOINTS) + { + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackFn = + (usb_device_endpoint_callback_t)NULL; + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].callbackParam = NULL; + deviceHandle->epCallback[(uint8_t)((uint32_t)endpoint << 1U) | direction].isBusy = 0U; + } + else + { + return kStatus_USB_InvalidParameter; + } + return error; +} + +/*! + * @brief Stall a specified endpoint. + * + * The function is used to stall a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is stalled successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +usb_status_t USB_DeviceStallEndpoint(usb_device_handle handle, uint8_t endpointAddress) +{ + if ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) < USB_DEVICE_CONFIG_ENDPOINTS) + { + return USB_DeviceControl(handle, kUSB_DeviceControlEndpointStall, &endpointAddress); + } + else + { + return kStatus_USB_InvalidParameter; + } +} + +/*! + * @brief Un-stall a specified endpoint. + * + * The function is used to un-stall a specified endpoint. + * + * @param handle The device handle got from USB_DeviceInit. + * @param endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is un-stalled successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +usb_status_t USB_DeviceUnstallEndpoint(usb_device_handle handle, uint8_t endpointAddress) +{ + if ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) < USB_DEVICE_CONFIG_ENDPOINTS) + { + return USB_DeviceControl(handle, kUSB_DeviceControlEndpointUnstall, &endpointAddress); + } + else + { + return kStatus_USB_InvalidParameter; + } +} + +/*! + * @brief Get the status of the selected item. + * + * The function is used to get the status of the selected item. + * + * @param handle The device handle got from USB_DeviceInit. + * @param type The selected item. Please refer to the structure usb_device_status_t. + * @param param The param type is determined by the selected item. + * + * @retval kStatus_USB_Success Get status successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The param is NULL pointer. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error Unsupported type. + */ +usb_status_t USB_DeviceGetStatus(usb_device_handle handle, usb_device_status_t type, void *param) +{ + uint8_t *temp8; + usb_status_t error = kStatus_USB_Error; + + if (NULL == param) + { + return kStatus_USB_InvalidParameter; + } + switch (type) + { + case kUSB_DeviceStatusSpeed: + error = USB_DeviceControl(handle, kUSB_DeviceControlGetSpeed, param); + break; + case kUSB_DeviceStatusOtg: + error = USB_DeviceControl(handle, kUSB_DeviceControlGetOtgStatus, param); + break; + case kUSB_DeviceStatusDeviceState: + temp8 = (uint8_t *)param; + error = kStatus_USB_Success; + *temp8 = ((usb_device_struct_t *)handle)->state; + break; + case kUSB_DeviceStatusAddress: + temp8 = (uint8_t *)param; + error = kStatus_USB_Success; + *temp8 = ((usb_device_struct_t *)handle)->deviceAddress; + break; + case kUSB_DeviceStatusDevice: + error = USB_DeviceControl(handle, kUSB_DeviceControlGetDeviceStatus, param); + break; + case kUSB_DeviceStatusEndpoint: + error = USB_DeviceControl(handle, kUSB_DeviceControlGetEndpointStatus, param); + break; + case kUSB_DeviceStatusSynchFrame: + error = USB_DeviceControl(handle, kUSB_DeviceControlGetSynchFrame, param); + break; +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + case kUSB_DeviceStatusRemoteWakeup: + temp8 = (uint8_t *)param; + error = kStatus_USB_Success; + *temp8 = ((usb_device_struct_t *)handle)->remotewakeup; + break; +#endif + default: + break; + } + return error; +} + +/*! + * @brief Set the status of the selected item. + * + * The function is used to set the status of the selected item. + * + * @param handle The device handle got from USB_DeviceInit. + * @param type The selected item. Please refer to the structure usb_device_status_t. + * @param param The param type is determined by the selected item. + * + * @retval kStatus_USB_Success Set status successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error Unsupported type, or the param is NULL pointer. + */ +usb_status_t USB_DeviceSetStatus(usb_device_handle handle, usb_device_status_t type, void *param) +{ + usb_status_t error = kStatus_USB_Error; + switch (type) + { +#if (defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U) || \ + (defined(USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) && \ + (defined(USB_DEVICE_CONFIG_USB20_TEST_MODE) && (USB_DEVICE_CONFIG_USB20_TEST_MODE > 0U)) + case kUSB_DeviceStatusTestMode: + error = USB_DeviceControl(handle, kUSB_DeviceControlSetTestMode, param); + break; +#endif + case kUSB_DeviceStatusOtg: + error = USB_DeviceControl(handle, kUSB_DeviceControlSetOtgStatus, param); + break; + case kUSB_DeviceStatusDeviceState: + if (NULL != param) + { + error = kStatus_USB_Success; + ((usb_device_struct_t *)handle)->state = (uint8_t)(*(uint8_t *)param); + } + break; + case kUSB_DeviceStatusAddress: + if (kUSB_DeviceStateAddressing != ((usb_device_struct_t *)handle)->state) + { + if (NULL != param) + { + error = kStatus_USB_Success; + ((usb_device_struct_t *)handle)->deviceAddress = (uint8_t)(*(uint8_t *)param); + ((usb_device_struct_t *)handle)->state = kUSB_DeviceStateAddressing; + } + } + else + { + error = USB_DeviceControl(handle, kUSB_DeviceControlSetDeviceAddress, + &((usb_device_struct_t *)handle)->deviceAddress); + } + break; + case kUSB_DeviceStatusBusResume: + error = USB_DeviceControl(handle, kUSB_DeviceControlResume, param); + break; + case kUSB_DeviceStatusBusSleepResume: + error = USB_DeviceControl(handle, kUSB_DeviceControlSleepResume, param); + break; +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + case kUSB_DeviceStatusRemoteWakeup: + if (NULL != param) + { + error = kStatus_USB_Success; + ((usb_device_struct_t *)handle)->remotewakeup = (uint8_t)(*(uint8_t *)param); + } + break; +#endif + case kUSB_DeviceStatusBusSuspend: + error = USB_DeviceControl(handle, kUSB_DeviceControlSuspend, param); + break; + case kUSB_DeviceStatusBusSleep: + error = USB_DeviceControl(handle, kUSB_DeviceControlSleep, param); + break; + default: + break; + } + return error; +} + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + ((defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) || \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))) +/*! + * @brief Initializes the device dcd module. + * + * The function initializes the device dcd module. + * + * @param handle The device handle got from USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +usb_status_t USB_DeviceDcdInitModule(usb_device_handle handle, void *time_param) +{ + return USB_DeviceControl(handle, kUSB_DeviceControlDcdInitModule, time_param); +} + +/*! + * @brief De-initializes the device dcd module. + * + * The function de-intializes the device dcd module. + * + * @param handle The device handle got from USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +usb_status_t USB_DeviceDcdDeinitModule(usb_device_handle handle) +{ + return USB_DeviceControl(handle, kUSB_DeviceControlDcdDeinitModule, NULL); +} +#endif + +#if USB_DEVICE_CONFIG_USE_TASK +/*! + * @brief Device task function. + * + * The function is used to handle controller message. + * This function should not be called in applicartion directly. + * + * @param handle The device handle got from USB_DeviceInit. + */ +void USB_DeviceTaskFunction(void *deviceHandle) +{ + usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle; + static usb_device_callback_message_struct_t message; + + if (deviceHandle) + { + /* Get the message from the queue */ + if (kStatus_USB_OSA_Success == USB_OsaMsgqRecv(handle->notificationQueue, (uint32_t *)&message, 0U)) + { + /* Handle the message */ + USB_DeviceNotification(handle, &message); + } + } +} +#endif + +/*! + * @brief Get dvice stack version function. + * + * The function is used to get dvice stack version. + * + * @param[out] version The version structure pointer to keep the device stack version. + * + */ +void USB_DeviceGetVersion(uint32_t *version) +{ + if (version) + { + *version = + (uint32_t)USB_MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX); + } +} + +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) +/*! + * @brief Update the hardware tick. + * + * The function is used to update the hardware tick. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] tick Current hardware tick. + * + */ +usb_status_t USB_DeviceUpdateHwTick(usb_device_handle handle, uint64_t tick) +{ + usb_device_struct_t *deviceHandle; + usb_status_t status = kStatus_USB_Success; + + if (handle == NULL) + { + return kStatus_USB_InvalidHandle; + } + deviceHandle = (usb_device_struct_t *)handle; + + deviceHandle->hwTick = tick; + + return status; +} +#endif +#endif /* USB_DEVICE_CONFIG_NUM */ diff --git a/bsp/imxrt/libraries/drivers/usb/device/usb_device_dci.h b/bsp/imxrt/libraries/drivers/usb/device/usb_device_dci.h new file mode 100644 index 0000000000000000000000000000000000000000..fd4fdceb0416aec6815e73a1205ae8d330a3fd85 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/device/usb_device_dci.h @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_DEVICE_DCI_H__ +#define __USB_DEVICE_DCI_H__ + +/*! + * @addtogroup usb_device_controller_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Macro to define controller handle */ +#define usb_device_controller_handle usb_device_handle + +/*! @brief Available notify types for device notification */ +typedef enum _usb_device_notification +{ + kUSB_DeviceNotifyBusReset = 0x10U, /*!< Reset signal detected */ + kUSB_DeviceNotifySuspend, /*!< Suspend signal detected */ + kUSB_DeviceNotifyResume, /*!< Resume signal detected */ + kUSB_DeviceNotifyLPMSleep, /*!< LPM signal detected */ + kUSB_DeviceNotifyLPMResume, /*!< Resume signal detected */ + kUSB_DeviceNotifyError, /*!< Errors happened in bus */ + kUSB_DeviceNotifyDetach, /*!< Device disconnected from a host */ + kUSB_DeviceNotifyAttach, /*!< Device connected to a host */ +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) + kUSB_DeviceNotifyDcdTimeOut, /*!< Device charger detection timeout */ + kUSB_DeviceNotifyDcdUnknownPortType, /*!< Device charger detection unknown port type */ + kUSB_DeviceNotifySDPDetected, /*!< The SDP facility is detected */ + kUSB_DeviceNotifyChargingPortDetected, /*!< The charging port is detected */ + kUSB_DeviceNotifyChargingHostDetected, /*!< The CDP facility is detected */ + kUSB_DeviceNotifyDedicatedChargerDetected, /*!< The DCP facility is detected */ +#endif +} usb_device_notification_t; + +/*! @brief Device notification message structure */ +typedef struct _usb_device_callback_message_struct +{ + uint8_t *buffer; /*!< Transferred buffer */ + uint32_t length; /*!< Transferred data length */ + uint8_t code; /*!< Notification code */ + uint8_t isSetup; /*!< Is in a setup phase */ +} usb_device_callback_message_struct_t; + +/*! @brief Control type for controller */ +typedef enum _usb_device_control_type +{ + kUSB_DeviceControlRun = 0U, /*!< Enable the device functionality */ + kUSB_DeviceControlStop, /*!< Disable the device functionality */ + kUSB_DeviceControlEndpointInit, /*!< Initialize a specified endpoint */ + kUSB_DeviceControlEndpointDeinit, /*!< De-initialize a specified endpoint */ + kUSB_DeviceControlEndpointStall, /*!< Stall a specified endpoint */ + kUSB_DeviceControlEndpointUnstall, /*!< Unstall a specified endpoint */ + kUSB_DeviceControlGetDeviceStatus, /*!< Get device status */ + kUSB_DeviceControlGetEndpointStatus, /*!< Get endpoint status */ + kUSB_DeviceControlSetDeviceAddress, /*!< Set device address */ + kUSB_DeviceControlGetSynchFrame, /*!< Get current frame */ + kUSB_DeviceControlResume, /*!< Drive controller to generate a resume signal in USB bus */ + kUSB_DeviceControlSleepResume, /*!< Drive controller to generate a LPM resume signal in USB bus */ + kUSB_DeviceControlSuspend, /*!< Drive controller to enetr into suspend mode */ + kUSB_DeviceControlSleep, /*!< Drive controller to enetr into sleep mode */ + kUSB_DeviceControlSetDefaultStatus, /*!< Set controller to default status */ + kUSB_DeviceControlGetSpeed, /*!< Get current speed */ + kUSB_DeviceControlGetOtgStatus, /*!< Get OTG status */ + kUSB_DeviceControlSetOtgStatus, /*!< Set OTG status */ + kUSB_DeviceControlSetTestMode, /*!< Drive xCHI into test mode */ + kUSB_DeviceControlGetRemoteWakeUp, /*!< Get flag of LPM Remote Wake-up Enabled by USB host. */ +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) + kUSB_DeviceControlDcdInitModule, + kUSB_DeviceControlDcdDeinitModule, +#endif +} usb_device_control_type_t; + +/*! @brief USB device controller initialization function typedef */ +typedef usb_status_t (*usb_device_controller_init_t)(uint8_t controllerId, + usb_device_handle handle, + usb_device_controller_handle *controllerHandle); + +/*! @brief USB device controller de-initialization function typedef */ +typedef usb_status_t (*usb_device_controller_deinit_t)(usb_device_controller_handle controllerHandle); + +/*! @brief USB device controller send data function typedef */ +typedef usb_status_t (*usb_device_controller_send_t)(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! @brief USB device controller receive data function typedef */ +typedef usb_status_t (*usb_device_controller_recv_t)(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! @brief USB device controller cancel transfer function in a specified endpoint typedef */ +typedef usb_status_t (*usb_device_controller_cancel_t)(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress); + +/*! @brief USB device controller control function typedef */ +typedef usb_status_t (*usb_device_controller_control_t)(usb_device_controller_handle controllerHandle, + usb_device_control_type_t command, + void *param); + +/*! @brief USB device controller interface structure */ +typedef struct _usb_device_controller_interface_struct +{ + usb_device_controller_init_t deviceInit; /*!< Controller initialization */ + usb_device_controller_deinit_t deviceDeinit; /*!< Controller de-initialization */ + usb_device_controller_send_t deviceSend; /*!< Controller send data */ + usb_device_controller_recv_t deviceRecv; /*!< Controller receive data */ + usb_device_controller_cancel_t deviceCancel; /*!< Controller cancel transfer */ + usb_device_controller_control_t deviceControl; /*!< Controller control */ +} usb_device_controller_interface_struct_t; + +/*! @brief USB device status structure */ +typedef struct _usb_device_struct +{ +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + volatile uint64_t hwTick; /*!< Current hw tick(ms)*/ +#endif + usb_device_controller_handle controllerHandle; /*!< Controller handle */ + const usb_device_controller_interface_struct_t *controllerInterface; /*!< Controller interface handle */ +#if USB_DEVICE_CONFIG_USE_TASK + usb_osa_msgq_handle notificationQueue; /*!< Message queue */ +#endif + usb_device_callback_t deviceCallback; /*!< Device callback function pointer */ + usb_device_endpoint_callback_struct_t + epCallback[USB_DEVICE_CONFIG_ENDPOINTS << 1U]; /*!< Endpoint callback function structure */ + uint8_t deviceAddress; /*!< Current device address */ + uint8_t controllerId; /*!< Controller ID */ + uint8_t state; /*!< Current device state */ +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + uint8_t remotewakeup; /*!< Remote wakeup is enabled or not */ +#endif + uint8_t isResetting; /*!< Is doing device reset or not */ +#if (defined(USB_DEVICE_CONFIG_USE_TASK) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) + uint8_t epCallbackDirectly; /*!< Whether call ep callback directly when the task is enabled */ +#endif +} usb_device_struct_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! @}*/ + +#endif /* __USB_DEVICE_DCI_H__ */ diff --git a/bsp/imxrt/libraries/drivers/usb/device/usb_device_ehci.c b/bsp/imxrt/libraries/drivers/usb/device/usb_device_ehci.c new file mode 100644 index 0000000000000000000000000000000000000000..dd7780c772e4208c5a36acfa01a501e051e6a895 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/device/usb_device_ehci.c @@ -0,0 +1,1807 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "fsl_device_registers.h" +#include +#include "usb_device.h" +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) + +#include "usb_device_dci.h" + +#include "usb_device_ehci.h" +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +#include "usb_phy.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM > 0U) + +#error The SOC does not suppoort dedicated RAM case. + +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static void USB_DeviceEhciSetDefaultState(usb_device_ehci_state_struct_t *ehciState); +static usb_status_t USB_DeviceEhciEndpointInit(usb_device_ehci_state_struct_t *ehciState, + usb_device_endpoint_init_struct_t *epInit); +static usb_status_t USB_DeviceEhciEndpointDeinit(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); +static usb_status_t USB_DeviceEhciEndpointStall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); +static usb_status_t USB_DeviceEhciEndpointUnstall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); +static void USB_DeviceEhciFillSetupBuffer(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); +static void USB_DeviceEhciCancelControlPipe(usb_device_ehci_state_struct_t *ehciState, + uint8_t endpoint, + uint8_t direction); +static void USB_DeviceEhciInterruptTokenDone(usb_device_ehci_state_struct_t *ehciState); +static void USB_DeviceEhciInterruptPortChange(usb_device_ehci_state_struct_t *ehciState); +static void USB_DeviceEhciInterruptReset(usb_device_ehci_state_struct_t *ehciState); +static void USB_DeviceEhciInterruptSof(usb_device_ehci_state_struct_t *ehciState); +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +static void USB_DeviceEhciInterruptSuspend(usb_device_ehci_state_struct_t *ehciState); +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ +static usb_status_t USB_DeviceEhciTransfer(usb_device_ehci_state_struct_t *ehciState, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +extern usb_status_t USB_DeviceNotificationTrigger(void *handle, void *msg); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Apply for QH buffer, 2048-byte alignment */ +USB_RAM_ADDRESS_ALIGNMENT(2048) +USB_CONTROLLER_DATA static uint8_t qh_buffer[(USB_DEVICE_CONFIG_EHCI - 1) * 2048 + + USB_DEVICE_CONFIG_ENDPOINTS * 2 * sizeof(usb_device_ehci_qh_struct_t)]; + +/* Apply for DTD buffer, 32-byte alignment */ +USB_RAM_ADDRESS_ALIGNMENT(32) +USB_CONTROLLER_DATA static usb_device_ehci_dtd_struct_t +s_UsbDeviceEhciDtd[USB_DEVICE_CONFIG_EHCI][USB_DEVICE_CONFIG_EHCI_MAX_DTD]; + +/* Apply for ehci device state structure */ +static usb_device_ehci_state_struct_t g_UsbDeviceEhciSate[USB_DEVICE_CONFIG_EHCI]; + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +/* Apply for device dcd state structure */ +static usb_device_dcd_state_struct_t s_UsbDeviceDcdHSState[USB_DEVICE_CONFIG_EHCI]; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief EHCI NC get USB NC bass address. + * + * This function is used to get USB NC bass address. + * + * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. + * + * @retval USB NC bass address. + */ +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) +void *USB_EhciNCGetBase(uint8_t controllerId) +{ + void *usbNCBase = NULL; +#if ((defined FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + uint32_t instance; + uint32_t newinstance = 0; + uint32_t usbnc_base_temp[] = USBNC_BASE_ADDRS; + uint32_t usbnc_base[] = USBNC_BASE_ADDRS; + + if (controllerId < kUSB_ControllerEhci0) + { + return NULL; + } + + controllerId = controllerId - kUSB_ControllerEhci0; + + for (instance = 0; instance < (sizeof(usbnc_base_temp) / sizeof(usbnc_base_temp[0])); instance++) + { + if (usbnc_base_temp[instance]) + { + usbnc_base[newinstance++] = usbnc_base_temp[instance]; + } + } + if (controllerId > newinstance) + { + return NULL; + } + + usbNCBase = (void *)usbnc_base[controllerId]; +#endif + return usbNCBase; +} +#endif +#endif + +/*! + * @brief Set device controller state to default state. + * + * The function is used to set device controller state to default state. + * The function will be called when USB_DeviceEhciInit called or the control type kUSB_DeviceControlGetEndpointStatus + * received in USB_DeviceEhciControl. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciSetDefaultState(usb_device_ehci_state_struct_t *ehciState) +{ + usb_device_ehci_dtd_struct_t *p; + + /* Initialize the dtd free queue */ + ehciState->dtdFree = ehciState->dtd; + p = ehciState->dtdFree; + for (uint32_t i = 1U; i < USB_DEVICE_CONFIG_EHCI_MAX_DTD; i++) + { + p->nextDtdPointer = (uint32_t)&ehciState->dtd[i]; + p = (usb_device_ehci_dtd_struct_t *)p->nextDtdPointer; + } + p->nextDtdPointer = 0U; + ehciState->dtdCount = USB_DEVICE_CONFIG_EHCI_MAX_DTD; + + /* Not use interrupt threshold. */ + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_ITC_MASK; + ehciState->registerBase->USBCMD |= USBHS_USBCMD_ITC(0U); + + /* Disable setup lockout, please refer to "Control Endpoint Operation" section in RM. */ + ehciState->registerBase->USBMODE |= USBHS_USBMODE_SLOM_MASK; + + /* Set the endian by using CPU's endian */ +#if (ENDIANNESS == USB_BIG_ENDIAN) + ehciState->registerBase->USBMODE |= USBHS_USBMODE_ES_MASK; +#else + ehciState->registerBase->USBMODE &= ~USBHS_USBMODE_ES_MASK; +#endif + /* Initialize the QHs of endpoint. */ + for (uint32_t i = 0U; i < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); i++) + { + ehciState->qh[i].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + ehciState->qh[i].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.maxPacketSize = + USB_CONTROL_MAX_PACKET_SIZE; + ehciState->dtdHard[i] = NULL; + ehciState->dtdTail[i] = NULL; + ehciState->qh[i].endpointStatusUnion.endpointStatusBitmap.isOpened = 0U; + } + + /* Add QH buffer address to USBHS_EPLISTADDR_REG */ + ehciState->registerBase->EPLISTADDR = (uint32_t)ehciState->qh; + + /* Clear device address */ + ehciState->registerBase->DEVICEADDR = 0U; + +#if defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U) + ehciState->registerBase->OTGSC = ehciState->registerBase->OTGSC & 0x0000FFFF; + ehciState->registerBase->OTGSC |= USBHS_OTGSC_BSVIE_MASK; +#endif /* USB_DEVICE_CONFIG_DETACH_ENABLE */ + + /* Enable reset, sof, token, stall interrupt */ + ehciState->registerBase->USBINTR = + (USBHS_USBINTR_UE_MASK | USBHS_USBINTR_UEE_MASK | USBHS_USBINTR_PCE_MASK | USBHS_USBINTR_URE_MASK +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + | USBHS_USBINTR_SLE_MASK +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + ); + + /* Clear reset flag */ + ehciState->isResetting = 0U; +} + +/*! + * @brief Initialize a specified endpoint. + * + * The function is used to initialize a specified endpoint. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param epInit The endpoint initialization structure pointer. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciEndpointInit(usb_device_ehci_state_struct_t *ehciState, + usb_device_endpoint_init_struct_t *epInit) +{ + uint32_t primeBit = 1U << ((epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK) + + ((epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); + uint16_t maxPacketSize = epInit->maxPacketSize & USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK; + uint8_t endpoint = (epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK); + uint8_t direction = (epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | direction; + uint8_t transferType = epInit->transferType & USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_TYPE_MASK; + + /* Cancel pending transfer of the endpoint */ + USB_DeviceEhciCancel(ehciState, epInit->endpointAddress); + + if ((ehciState->registerBase->EPPRIME & primeBit) || (ehciState->registerBase->EPSR & primeBit)) + { + return kStatus_USB_Busy; + } + + /* Make the endpoint max packet size align with USB Specification 2.0. */ + if (USB_ENDPOINT_ISOCHRONOUS == transferType) + { + if (maxPacketSize > USB_DEVICE_MAX_HS_ISO_MAX_PACKET_SIZE) + { + maxPacketSize = USB_DEVICE_MAX_HS_ISO_MAX_PACKET_SIZE; + } + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.mult = + 1U + ((maxPacketSize & USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK) >> + USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_SHFIT); + } + else + { + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.mult = 0U; + } + + /* Save the max packet size of the endpoint */ + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.maxPacketSize = + maxPacketSize; + /* Set ZLT bit. */ + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.zlt = !epInit->zlt; + + /* Enable the endpoint. */ + if (USB_ENDPOINT_CONTROL == transferType) + { + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.ios = 1U; + ehciState->registerBase->EPCR0 |= + (direction ? + (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXR_MASK | ((uint32_t)transferType << USBHS_EPCR_TXT_SHIFT)) : + (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXR_MASK | ((uint32_t)transferType << USBHS_EPCR_RXT_SHIFT))); + } + else + { + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.ios = 0U; + ehciState->registerBase->EPCR[endpoint - 1U] |= + (direction ? + (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXR_MASK | ((uint32_t)transferType << USBHS_EPCR_TXT_SHIFT)) : + (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXR_MASK | ((uint32_t)transferType << USBHS_EPCR_RXT_SHIFT))); + } + + ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.isOpened = 1U; + return kStatus_USB_Success; +} + +/*! + * @brief De-initialize a specified endpoint. + * + * The function is used to de-initialize a specified endpoint. + * Current transfer of the endpoint will be cancelled and the specified endpoint will be disabled. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciEndpointDeinit(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) +{ + uint32_t primeBit = + 1U << ((ep & USB_ENDPOINT_NUMBER_MASK) + ((ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); + uint8_t endpoint = (ep & USB_ENDPOINT_NUMBER_MASK); + uint8_t direction = + (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | direction; + + ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.isOpened = 0U; + + /* Cancel the transfer of the endpoint */ + USB_DeviceEhciCancel(ehciState, ep); + + if ((ehciState->registerBase->EPPRIME & primeBit) || (ehciState->registerBase->EPSR & primeBit)) + { + return kStatus_USB_Busy; + } + + /* Clear endpoint state */ + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristics = 0U; + /* Disable the endpoint */ + if (!endpoint) + { + ehciState->registerBase->EPCR0 &= + ~(direction ? (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXT_MASK) : (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXT_MASK)); + } + else + { + ehciState->registerBase->EPCR[endpoint - 1U] &= + ~(direction ? (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXT_MASK) : (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXT_MASK)); + } + + return kStatus_USB_Success; +} + +/*! + * @brief Stall a specified endpoint. + * + * The function is used to stall a specified endpoint. + * Current transfer of the endpoint will be cancelled and the specified endpoint will be stalled. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciEndpointStall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) +{ + uint8_t endpoint = ep & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = + (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | direction; + + /* Cancel the transfer of the endpoint */ + USB_DeviceEhciCancel(ehciState, ep); + + /* Set endpoint stall flag. */ + if (ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.ios) + { + if (!endpoint) + { + ehciState->registerBase->EPCR0 |= (USBHS_EPCR_TXS_MASK | USBHS_EPCR_RXS_MASK); + } + else + { + ehciState->registerBase->EPCR[endpoint - 1U] |= (USBHS_EPCR_TXS_MASK | USBHS_EPCR_RXS_MASK); + } + } + else + { + if (!endpoint) + { + ehciState->registerBase->EPCR0 |= (direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); + } + else + { + ehciState->registerBase->EPCR[endpoint - 1U] |= (direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); + } + } + + return kStatus_USB_Success; +} + +/*! + * @brief Un-stall a specified endpoint. + * + * The function is used to un-stall a specified endpoint. + * Current transfer of the endpoint will be cancelled and the specified endpoint will be un-stalled. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciEndpointUnstall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) +{ + uint8_t endpoint = ep & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = + (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + + /* Clear the endpoint stall state */ + if (!endpoint) + { + ehciState->registerBase->EPCR0 &= ~(direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); + } + else + { + ehciState->registerBase->EPCR[endpoint - 1U] &= ~(direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); + ehciState->registerBase->EPCR[endpoint - 1U] |= (direction ? USBHS_EPCR_TXR_MASK : USBHS_EPCR_RXR_MASK); + } + + return kStatus_USB_Success; +} + +/*! + * @brief Get setup packet data. + * + * The function is used to get setup packet data and copy to a backup buffer. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param ep The endpoint number. + * + */ +static void USB_DeviceEhciFillSetupBuffer(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) +{ + uint8_t waitingSafelyAccess = 1U; + uint8_t index = (ep * 2U) | USB_OUT; + + /* Write 1U to clear corresponding bit in EPSETUPSR. */ + ehciState->registerBase->EPSETUPSR = 1U << ep; + + while (waitingSafelyAccess) + { + /* Set the setup tripwire bit. */ + ehciState->registerBase->USBCMD |= USBHS_USBCMD_SUTW_MASK; + + /* Copy setup packet data to backup buffer */ + ehciState->qh[index].setupBufferBack[0] = ehciState->qh[index].setupBuffer[0]; + ehciState->qh[index].setupBufferBack[1] = ehciState->qh[index].setupBuffer[1]; + + /* Read the USBCMD[SUTW] bit. If set, jump out from the while loop; if cleared continue */ + if (ehciState->registerBase->USBCMD & USBHS_USBCMD_SUTW_MASK) + { + waitingSafelyAccess = 0U; + } + } + /* Clear the setup tripwire bit */ + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_SUTW_MASK; + + /* Poll until the EPSETUPSR bit clearred */ + while (ehciState->registerBase->EPSETUPSR & (1U << ep)) + { + } +} + +/*! + * @brief Cancel the transfer of the control pipe. + * + * The function is used to cancel the transfer of the control pipe. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param endpoint The endpoint number. + * @param direction The direction of the endpoint. + * + */ +static void USB_DeviceEhciCancelControlPipe(usb_device_ehci_state_struct_t *ehciState, + uint8_t endpoint, + uint8_t direction) +{ + usb_device_ehci_dtd_struct_t *currentDtd; + uint32_t index = ((uint32_t)endpoint << 1U) + (uint32_t)direction; + usb_device_callback_message_struct_t message; + + message.buffer = NULL; + message.length = 0U; + /* Get the dtd of the control pipe */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + while (currentDtd) + { + /* Pass the transfer buffer address */ + if (NULL == message.buffer) + { + uint32_t bufferAddress = currentDtd->bufferPointerPage[0]; + message.buffer = (uint8_t *)((bufferAddress & USB_DEVICE_ECHI_DTD_PAGE_MASK) | + (currentDtd->reservedUnion.originalBufferInfo.originalBufferOffest)); + } + /* If the dtd is active, set the message length to USB_UNINITIALIZED_VAL_32. Or set the length by using finished + * length. */ + if (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE) + { + message.length = USB_UNINITIALIZED_VAL_32; + } + else + { + message.length += (currentDtd->reservedUnion.originalBufferInfo.originalBufferLength - + currentDtd->dtdTokenUnion.dtdTokenBitmap.totalBytes); + } + + /* Move the dtd head pointer to next. */ + /* If the pointer of the head equals to the tail, set the dtd queue to null. */ + if (ehciState->dtdHard[index] == ehciState->dtdTail[index]) + { + ehciState->dtdHard[index] = NULL; + ehciState->dtdTail[index] = NULL; + ehciState->qh[index].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + } + else + { + ehciState->dtdHard[index] = (usb_device_ehci_dtd_struct_t *)ehciState->dtdHard[index]->nextDtdPointer; + } + + /* When the ioc is set or the dtd queue is empty, the up layer will be notified. */ + if ((currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc) || + (0 == ((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK))) + { + message.code = endpoint | (uint8_t)((uint32_t)direction << 0x07U); + message.isSetup = 0U; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + message.buffer = NULL; + message.length = 0U; + } + + /* Clear the token field of the dtd. */ + currentDtd->dtdTokenUnion.dtdToken = 0U; + /* Add the dtd to the free dtd queue. */ + currentDtd->nextDtdPointer = (uint32_t)ehciState->dtdFree; + ehciState->dtdFree = currentDtd; + ehciState->dtdCount++; + + /* Get the next in-used dtd. */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + } +} + +/*! + * @brief Handle the endpoint token done interrupt. + * + * The function is used to handle the endpoint token done interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptTokenDone(usb_device_ehci_state_struct_t *ehciState) +{ + uint32_t status; + uint32_t primeBit; + usb_device_ehci_dtd_struct_t *currentDtd; + usb_device_callback_message_struct_t message; + uint8_t endpoint; + uint8_t direction; + uint8_t count; + uint8_t index; + + /* Get the EPSETUPSR to check the setup packect received in which one endpoint. */ + status = ehciState->registerBase->EPSETUPSR; + + if (status) + { + for (endpoint = 0U; endpoint < USB_DEVICE_CONFIG_ENDPOINTS; endpoint++) + { + /* Check the endpoint receive the setup packet. */ + if (status & (1U << endpoint)) + { + /* Get last setup packet */ + usb_setup_struct_t *deviceSetup = + (usb_setup_struct_t *)&ehciState->qh[(uint8_t)((uint32_t)endpoint << 1U) + USB_OUT].setupBufferBack; + + /* Check the direction of the data phase. */ + direction = (deviceSetup->bmRequestType & USB_REQUEST_TYPE_DIR_IN) >> USB_REQUEST_TYPE_DIR_SHIFT; + /* Cancel the data phase transfer */ + USB_DeviceEhciCancelControlPipe(ehciState, endpoint, direction); + /* Cancel the status phase transfer */ + USB_DeviceEhciCancelControlPipe(ehciState, endpoint, 1U ^ direction); + message.code = (endpoint) | (USB_OUT << 0x07U); + message.buffer = (uint8_t *)deviceSetup; + message.length = USB_SETUP_PACKET_SIZE; + message.isSetup = 1U; + /* Fill the setup packet to the backup buffer */ + USB_DeviceEhciFillSetupBuffer(ehciState, endpoint); + /* Notify the up layer the EHCI status changed. */ + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } + } + } + /* Read the USBHS_EPCOMPLETE_REG to get the endpoint transfer done status */ + status = ehciState->registerBase->EPCOMPLETE; + /* Clear the endpoint transfer done status */ + ehciState->registerBase->EPCOMPLETE = status; + + if (status) + { + for (count = 0U; count < 32U; count++) + { + /* Check the transfer is done or not in the specified endpoint. */ + if (status & ((uint32_t)(1U << count))) + { + if (count > 15U) + { + endpoint = count - 16U; + direction = USB_IN; + } + else + { + endpoint = count; + direction = USB_OUT; + } + if (endpoint >= USB_DEVICE_CONFIG_ENDPOINTS) + { + continue; + } + index = (endpoint << 1U) + direction; + message.buffer = NULL; + message.length = 0U; + + /* Get the in-used dtd of the specified endpoint. */ + currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + while (currentDtd) + { + uint8_t isTokenDone = 0; + /* Get the in-used dtd of the specified endpoint. */ + currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + + while (currentDtd) + { + /* Don't handle the active dtd. */ + if ((currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE) || + (currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc)) + { + if ((!(currentDtd->dtdTokenUnion.dtdTokenBitmap.status & + USB_DEVICE_ECHI_DTD_STATUS_ACTIVE)) && + (currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc)) + { + isTokenDone = 1U; + } + break; + } + currentDtd = (usb_device_ehci_dtd_struct_t *)(currentDtd->nextDtdPointer & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + } + + if ((0 == isTokenDone) && (currentDtd)) + { + break; + } + + /* Get the in-used dtd of the specified endpoint. */ + currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + while (currentDtd) + { + /* Don't handle the active dtd. */ + if (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE) + { + break; + } + + /* Save the transfer buffer address */ + if (NULL == message.buffer) + { + message.buffer = + (uint8_t *)((currentDtd->bufferPointerPage[0] & USB_DEVICE_ECHI_DTD_PAGE_MASK) | + (currentDtd->reservedUnion.originalBufferInfo.originalBufferOffest)); + } + /* Save the transferred data length */ + message.length += (currentDtd->reservedUnion.originalBufferInfo.originalBufferLength - + currentDtd->dtdTokenUnion.dtdTokenBitmap.totalBytes); + + /* Move the dtd queue head pointer to next */ + if (ehciState->dtdHard[index] == ehciState->dtdTail[index]) + { + ehciState->dtdHard[index] = NULL; + ehciState->dtdTail[index] = NULL; + ehciState->qh[index].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + } + else + { + ehciState->dtdHard[index] = + (usb_device_ehci_dtd_struct_t *)ehciState->dtdHard[index]->nextDtdPointer; + } + + /* When the ioc is set or the dtd queue is empty, the up layer will be notified. */ + if ((currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc) || + (0 == ((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK))) + { + message.code = endpoint | (uint8_t)((uint32_t)direction << 0x07U); + message.isSetup = 0U; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + message.buffer = NULL; + message.length = 0U; + } + /* Clear the token field of the dtd */ + currentDtd->dtdTokenUnion.dtdToken = 0U; + currentDtd->nextDtdPointer = (uint32_t)ehciState->dtdFree; + ehciState->dtdFree = currentDtd; + ehciState->dtdCount++; + /* Get the next in-used dtd */ + currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + + if ((NULL != currentDtd) && + (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE)) + { + primeBit = 1U << (endpoint + 16U * direction); + + /* Try to prime the next dtd. */ + ehciState->registerBase->EPPRIME = primeBit; + + /* Whether the endpoint transmit/receive buffer is ready or not. If not, wait for prime bit + * cleared and prime the next dtd. */ + if (!(ehciState->registerBase->EPSR & primeBit)) + { + /* Wait for the endpoint prime bit cleared by HW */ + while (ehciState->registerBase->EPPRIME & primeBit) + { + } + + /* If the endpoint transmit/receive buffer is not ready */ + if (!(ehciState->registerBase->EPSR & primeBit)) + { + /* Prime next dtd and prime the transfer */ + ehciState->qh[index].nextDtdPointer = (uint32_t)currentDtd; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + ehciState->registerBase->EPPRIME = primeBit; + } + } + } + } + } + } + } + } +} + +/*! + * @brief Handle the port status change interrupt. + * + * The function is used to handle the port status change interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptPortChange(usb_device_ehci_state_struct_t *ehciState) +{ + usb_device_callback_message_struct_t message; + + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + + /* Whether the port is doing reset. */ + if (!(ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_PR_MASK)) + { + /* If not, update the USB speed. */ + if (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_HSP_MASK) + { + ehciState->speed = USB_SPEED_HIGH; + } + else + { + ehciState->speed = USB_SPEED_FULL; + } + + /* If the device reset flag is non-zero, notify the up layer the device reset finished. */ + if (ehciState->isResetting) + { + message.code = kUSB_DeviceNotifyBusReset; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + ehciState->isResetting = 0U; + } + } + +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + if ((ehciState->isSuspending) && (!(ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_SUSP_MASK))) + { + /* Set the resume flag */ + ehciState->isSuspending = 0U; + + message.code = kUSB_DeviceNotifyResume; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ +} + +/*! + * @brief Handle the reset interrupt. + * + * The function is used to handle the reset interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptReset(usb_device_ehci_state_struct_t *ehciState) +{ + uint32_t status = 0U; + + /* Clear the setup flag */ + status = ehciState->registerBase->EPSETUPSR; + ehciState->registerBase->EPSETUPSR = status; + /* Clear the endpoint complete flag */ + status = ehciState->registerBase->EPCOMPLETE; + ehciState->registerBase->EPCOMPLETE = status; + + do + { + /* Flush the pending transfers */ + ehciState->registerBase->EPFLUSH = USBHS_EPFLUSH_FERB_MASK | USBHS_EPFLUSH_FETB_MASK; + } while (ehciState->registerBase->EPPRIME & (USBHS_EPPRIME_PERB_MASK | USBHS_EPPRIME_PETB_MASK)); + + /* Whether is the port reset. If yes, set the isResetting flag. Or, notify the up layer. */ + if (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_PR_MASK) + { + ehciState->isResetting = 1U; + } + else + { + usb_device_callback_message_struct_t message; + message.buffer = (uint8_t *)NULL; + message.code = kUSB_DeviceNotifyBusReset; + message.length = 0U; + message.isSetup = 0U; + + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } +} + +/*! + * @brief Handle the sof interrupt. + * + * The function is used to handle the sof interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptSof(usb_device_ehci_state_struct_t *ehciState) +{ +} + +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +/*! + * @brief Handle the suspend interrupt. + * + * The function is used to handle the suspend interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptSuspend(usb_device_ehci_state_struct_t *ehciState) +{ + /* If the port is in suspend state, notify the up layer */ + if (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_SUSP_MASK) + { +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) +#else + if (ehciState->registerPhyBase->USB1_VBUS_DET_STAT & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) +#endif + { + usb_device_callback_message_struct_t message; + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + message.code = kUSB_DeviceNotifySuspend; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } + } +} +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + +/*! + * @brief Get dtds and link to QH. + * + * The function is used to get dtds and link to QH. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param endpointAddress The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * @param buffer The memory address needed to be transferred. + * @param length Data length. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciTransfer(usb_device_ehci_state_struct_t *ehciState, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + usb_device_ehci_dtd_struct_t *dtd; + usb_device_ehci_dtd_struct_t *dtdHard; + uint32_t index = ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) << 1U) | + ((endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); + uint32_t primeBit = 1U << ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) + + ((endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); + uint8_t epStatus = primeBit; + uint32_t sendLength; + uint32_t currentIndex = 0U; + uint32_t dtdRequestCount = (length + USB_DEVICE_ECHI_DTD_TOTAL_BYTES - 1U) / USB_DEVICE_ECHI_DTD_TOTAL_BYTES; + uint8_t qhIdle = 0U; + uint8_t waitingSafelyAccess = 1U; + USB_OSA_SR_ALLOC(); + + if (!ehciState) + { + return kStatus_USB_InvalidHandle; + } + + if (0U == ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.isOpened) + { + return kStatus_USB_Error; + } + /* Return error when ehci is doing reset */ + if (ehciState->isResetting) + { + return kStatus_USB_Error; + } + + if (!dtdRequestCount) + { + dtdRequestCount = 1U; + } + + USB_OSA_ENTER_CRITICAL(); + /* The free dtd count need to not less than the transfer requests. */ + if (dtdRequestCount > (uint32_t)ehciState->dtdCount) + { + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Busy; + } + + do + { + /* The transfer length need to not more than USB_DEVICE_ECHI_DTD_TOTAL_BYTES for each dtd. */ + if (length > USB_DEVICE_ECHI_DTD_TOTAL_BYTES) + { + sendLength = USB_DEVICE_ECHI_DTD_TOTAL_BYTES; + } + else + { + sendLength = length; + } + length -= sendLength; + + /* Get a free dtd */ + dtd = ehciState->dtdFree; + + ehciState->dtdFree = (usb_device_ehci_dtd_struct_t *)dtd->nextDtdPointer; + ehciState->dtdCount--; + + /* Save the dtd head when current active buffer offset is zero. */ + if (!currentIndex) + { + dtdHard = dtd; + } + + /* Set the dtd field */ + dtd->nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + dtd->dtdTokenUnion.dtdToken = 0U; + dtd->bufferPointerPage[0] = (uint32_t)(buffer + currentIndex); + dtd->bufferPointerPage[1] = + (dtd->bufferPointerPage[0] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK) & USB_DEVICE_ECHI_DTD_PAGE_MASK; + dtd->bufferPointerPage[2] = dtd->bufferPointerPage[1] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK; + dtd->bufferPointerPage[3] = dtd->bufferPointerPage[2] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK; + dtd->bufferPointerPage[4] = dtd->bufferPointerPage[3] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK; + + dtd->dtdTokenUnion.dtdTokenBitmap.totalBytes = sendLength; + + /* Save the data length needed to be transferred. */ + dtd->reservedUnion.originalBufferInfo.originalBufferLength = sendLength; + /* Save the original buffer address */ + dtd->reservedUnion.originalBufferInfo.originalBufferOffest = + dtd->bufferPointerPage[0] & USB_DEVICE_ECHI_DTD_PAGE_OFFSET_MASK; + dtd->reservedUnion.originalBufferInfo.dtdInvalid = 0U; + + /* Set the IOC field in last dtd. */ + if (!length) + { + dtd->dtdTokenUnion.dtdTokenBitmap.ioc = 1U; + } + + /* Set dtd active */ + dtd->dtdTokenUnion.dtdTokenBitmap.status = USB_DEVICE_ECHI_DTD_STATUS_ACTIVE; + + /* Move the buffer offset index */ + currentIndex += sendLength; + + /* Add dtd to the in-used dtd queue */ + if (ehciState->dtdTail[index]) + { + ehciState->dtdTail[index]->nextDtdPointer = (uint32_t)dtd; + ehciState->dtdTail[index] = dtd; + } + else + { + ehciState->dtdHard[index] = dtd; + ehciState->dtdTail[index] = dtd; + qhIdle = 1U; + } + } while (length); + + /* If the QH is not empty */ + if (!qhIdle) + { + /* If the prime bit is set, nothing need to do. */ + if (ehciState->registerBase->EPPRIME & primeBit) + { + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; + } + + /* To safely a dtd */ + while (waitingSafelyAccess) + { + /* set the ATDTW flag to USBHS_USBCMD_REG. */ + ehciState->registerBase->USBCMD |= USBHS_USBCMD_ATDTW_MASK; + /* Read EPSR */ + epStatus = ehciState->registerBase->EPSR; + /* Wait the ATDTW bit set */ + if (ehciState->registerBase->USBCMD & USBHS_USBCMD_ATDTW_MASK) + { + waitingSafelyAccess = 0U; + } + } + /* Clear the ATDTW bit */ + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_ATDTW_MASK; + } + + /* If QH is empty or the endpoint is not primed, need to link current dtd head to the QH. */ + /* When the endpoint is not primed if qhIdle is zero, it means the QH is empty. */ + if ((qhIdle) || (!(epStatus & primeBit))) + { + ehciState->qh[index].nextDtdPointer = (uint32_t)dtdHard; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + ehciState->registerBase->EPPRIME = primeBit; + while (!(ehciState->registerBase->EPSR & primeBit)) + { + if (ehciState->registerBase->EPCOMPLETE & primeBit) + { + break; + } + else + { + ehciState->registerBase->EPPRIME = primeBit; + } + } + } + + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; +} + +/*! + * @brief Initialize the USB device EHCI instance. + * + * This function initializes the USB device EHCI module specified by the controllerId. + * + * @param controllerId The controller id of the USB IP. Please refer to enumeration type usb_controller_index_t. + * @param handle Pointer of the device handle, used to identify the device object is belonged to. + * @param ehciHandle It is out parameter, is used to return pointer of the device EHCI handle to the caller. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciInit(uint8_t controllerId, + usb_device_handle handle, + usb_device_controller_handle *ehciHandle) +{ + usb_device_ehci_state_struct_t *ehciState; + uint32_t ehci_base[] = USBHS_BASE_ADDRS; + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + usb_device_dcd_state_struct_t *dcdHSState; + uint32_t dcd_base[] = USBHSDCD_BASE_ADDRS; + usb_device_callback_message_struct_t message; +#endif + + if ((controllerId < kUSB_ControllerEhci0) || + ((uint32_t)(controllerId - kUSB_ControllerEhci0) >= USB_DEVICE_CONFIG_EHCI) || + ((uint32_t)(controllerId - kUSB_ControllerEhci0) >= (sizeof(ehci_base) / sizeof(uint32_t)))) + { + return kStatus_USB_ControllerNotFound; + } + + ehciState = &g_UsbDeviceEhciSate[controllerId - kUSB_ControllerEhci0]; + + ehciState->dtd = s_UsbDeviceEhciDtd[controllerId - kUSB_ControllerEhci0]; + ehciState->qh = (usb_device_ehci_qh_struct_t *)&qh_buffer[(controllerId - kUSB_ControllerEhci0) * 2048]; + + ehciState->controllerId = controllerId; + + ehciState->registerBase = (USBHS_Type *)ehci_base[controllerId - kUSB_ControllerEhci0]; +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + ehciState->registerPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciState->registerNcBase = (USBNC_Type *)USB_EhciNCGetBase(controllerId); +#endif + +#endif + + /* Get the HW's endpoint count */ + ehciState->endpointCount = + (uint8_t)((ehciState->registerBase->DCCPARAMS & USBHS_DCCPARAMS_DEN_MASK) >> USBHS_DCCPARAMS_DEN_SHIFT); + + if (ehciState->endpointCount < USB_DEVICE_CONFIG_ENDPOINTS) + { + return kStatus_USB_Error; + } + ehciState->deviceHandle = (usb_device_struct_t *)handle; + + /* Clear the controller mode field and set to device mode. */ + ehciState->registerBase->USBMODE &= ~USBHS_USBMODE_CM_MASK; + ehciState->registerBase->USBMODE |= USBHS_USBMODE_CM(0x02U); + + /* Set the EHCI to default status. */ + USB_DeviceEhciSetDefaultState(ehciState); + *ehciHandle = (usb_device_controller_handle)ehciState; +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + dcdHSState = &s_UsbDeviceDcdHSState[controllerId - kUSB_ControllerEhci0]; + + dcdHSState->controllerId = controllerId; + + dcdHSState->dcdRegisterBase = (USBHSDCD_Type *)dcd_base[controllerId - kUSB_ControllerEhci0]; + + dcdHSState->deviceHandle = (usb_device_struct_t *)handle; + + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + if (ehciState->registerBase->OTGSC & USBHS_OTGSC_BSV_MASK) + { + /* Device is connected to a host. */ + message.code = kUSB_DeviceNotifyAttach; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } +#endif + + return kStatus_USB_Success; +} + +/*! + * @brief De-initialize the USB device EHCI instance. + * + * This function de-initializes the USB device EHCI module. + * + * @param ehciHandle Pointer of the device EHCI handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciDeinit(usb_device_controller_handle ehciHandle) +{ + usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)ehciHandle; + + if (!ehciHandle) + { + return kStatus_USB_InvalidHandle; + } + + /* Disable all interrupt. */ + ehciState->registerBase->USBINTR = 0U; + /* Stop the device functionality. */ + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_RS_MASK; + /* Reset the controller. */ + ehciState->registerBase->USBCMD |= USBHS_USBCMD_RST_MASK; + + return kStatus_USB_Success; +} + +/*! + * @brief Send data through a specified endpoint. + * + * This function sends data through a specified endpoint. + * + * @param ehciHandle Pointer of the device EHCI handle. + * @param endpointAddress Endpoint index. + * @param buffer The memory address to hold the data need to be sent. + * @param length The data length need to be sent. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value just means if the sending request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceEhciSend(usb_device_controller_handle ehciHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + /* Add dtd to the QH */ + return USB_DeviceEhciTransfer( + (usb_device_ehci_state_struct_t *)ehciHandle, + (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), + buffer, length); +} + +/*! + * @brief Receive data through a specified endpoint. + * + * This function Receives data through a specified endpoint. + * + * @param ehciHandle Pointer of the device EHCI handle. + * @param endpointAddress Endpoint index. + * @param buffer The memory address to save the received data. + * @param length The data length want to be received. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceEhciRecv(usb_device_controller_handle ehciHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + /* Add dtd to the QH */ + return USB_DeviceEhciTransfer( + (usb_device_ehci_state_struct_t *)ehciHandle, + (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), + buffer, length); +} + +/*! + * @brief Cancel the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param ehciHandle Pointer of the device EHCI handle. + * @param ep Endpoint address, bit7 is the direction of endpoint, 1U - IN, 0U - OUT. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciCancel(usb_device_controller_handle ehciHandle, uint8_t ep) +{ + usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)ehciHandle; + usb_device_callback_message_struct_t message; + usb_device_ehci_dtd_struct_t *currentDtd; + uint32_t primeBit = + 1U << ((ep & USB_ENDPOINT_NUMBER_MASK) + ((ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); + uint8_t index = + ((ep & USB_ENDPOINT_NUMBER_MASK) << 1U) | ((ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x07U); + + USB_OSA_SR_ALLOC(); + + if (!ehciHandle) + { + return kStatus_USB_InvalidHandle; + } + + USB_OSA_ENTER_CRITICAL(); + + message.buffer = NULL; + message.length = USB_UNINITIALIZED_VAL_32; + + /* Get the first dtd */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + + while (currentDtd) + { + currentDtd->reservedUnion.originalBufferInfo.dtdInvalid = 1U; + currentDtd = (usb_device_ehci_dtd_struct_t *)(currentDtd->nextDtdPointer & USB_DEVICE_ECHI_DTD_POINTER_MASK); + } + + /* Get the first dtd */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + while (currentDtd) + { + if (!currentDtd->reservedUnion.originalBufferInfo.dtdInvalid) + { + break; + } + else + { + if (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE) + { + /* Flush the endpoint to stop a transfer. */ + do + { + /* Set the corresponding bit(s) in the EPFLUSH register */ + ehciState->registerBase->EPFLUSH |= primeBit; + + /* Wait until all bits in the EPFLUSH register are cleared. */ + while (ehciState->registerBase->EPFLUSH & primeBit) + { + } + /* + * Read the EPSR register to ensure that for all endpoints + * commanded to be flushed, that the corresponding bits + * are now cleared. + */ + } while (ehciState->registerBase->EPSR & primeBit); + } + + /* Save the original buffer address. */ + if (NULL == message.buffer) + { + message.buffer = (uint8_t *)((currentDtd->bufferPointerPage[0] & USB_DEVICE_ECHI_DTD_PAGE_MASK) | + (currentDtd->reservedUnion.originalBufferInfo.originalBufferOffest)); + } + + /* Remove the dtd from the dtd in-used queue. */ + if (ehciState->dtdHard[index] == ehciState->dtdTail[index]) + { + ehciState->dtdHard[index] = NULL; + ehciState->dtdTail[index] = NULL; + } + else + { + ehciState->dtdHard[index] = (usb_device_ehci_dtd_struct_t *)ehciState->dtdHard[index]->nextDtdPointer; + } + + /* When the ioc is set or the dtd queue is empty, the up layer will be notified. */ + if ((currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc) || + (0 == ((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK))) + { + message.code = ep; + message.isSetup = 0U; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + message.buffer = NULL; + } + /* Clear the token field. */ + currentDtd->dtdTokenUnion.dtdToken = 0U; + /* Save the dtd to the free queue. */ + currentDtd->nextDtdPointer = (uint32_t)ehciState->dtdFree; + ehciState->dtdFree = currentDtd; + ehciState->dtdCount++; + } + /* Get the next dtd. */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + } + if (!currentDtd) + { + /* Set the QH to empty. */ + ehciState->qh[index].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + } + USB_OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; +} + +/*! + * @brief Control the status of the selected item. + * + * The function is used to control the status of the selected item. + * + * @param ehciHandle Pointer of the device EHCI handle. + * @param type The selected item. Please refer to enumeration type usb_device_control_type_t. + * @param param The param type is determined by the selected item. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciControl(usb_device_controller_handle ehciHandle, usb_device_control_type_t type, void *param) +{ + usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)ehciHandle; + usb_status_t error = kStatus_USB_Error; + uint16_t *temp16; + uint8_t *temp8; +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + usb_device_dcd_state_struct_t *dcdHSState; + dcdHSState = + &s_UsbDeviceDcdHSState[ehciState->controllerId - kUSB_ControllerEhci0]; /*The hard code should be replaced*/ + usb_device_dcd_charging_time_t *deviceDcdTimingConfig = (usb_device_dcd_charging_time_t *)param; +#endif +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + usb_device_struct_t *deviceHandle; + uint64_t startTick; +#endif + + if (!ehciHandle) + { + return kStatus_USB_InvalidHandle; + } + +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + deviceHandle = (usb_device_struct_t *)ehciState->deviceHandle; +#endif + + switch (type) + { + case kUSB_DeviceControlRun: + ehciState->registerBase->USBCMD |= USBHS_USBCMD_RS_MASK; + error = kStatus_USB_Success; + break; + case kUSB_DeviceControlStop: + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_RS_MASK; + error = kStatus_USB_Success; + break; + case kUSB_DeviceControlEndpointInit: + if (param) + { + error = USB_DeviceEhciEndpointInit(ehciState, (usb_device_endpoint_init_struct_t *)param); + } + break; + case kUSB_DeviceControlEndpointDeinit: + if (param) + { + temp8 = (uint8_t *)param; + error = USB_DeviceEhciEndpointDeinit(ehciState, *temp8); + } + break; + case kUSB_DeviceControlEndpointStall: + if (param) + { + temp8 = (uint8_t *)param; + error = USB_DeviceEhciEndpointStall(ehciState, *temp8); + } + break; + case kUSB_DeviceControlEndpointUnstall: + if (param) + { + temp8 = (uint8_t *)param; + error = USB_DeviceEhciEndpointUnstall(ehciState, *temp8); + } + break; + case kUSB_DeviceControlGetDeviceStatus: + if (param) + { + temp16 = (uint16_t *)param; + *temp16 = (USB_DEVICE_CONFIG_SELF_POWER << (USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT)) +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + | (deviceHandle->remotewakeup << (USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT)) +#endif + ; + error = kStatus_USB_Success; + } + break; + case kUSB_DeviceControlGetEndpointStatus: + if (param) + { + usb_device_endpoint_status_struct_t *endpointStatus = (usb_device_endpoint_status_struct_t *)param; + uint8_t ep = (endpointStatus->endpointAddress) & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = + ((endpointStatus->endpointAddress) & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + + if (ep < USB_DEVICE_CONFIG_ENDPOINTS) + { + if (ep) + { + endpointStatus->endpointStatus = (ehciState->registerBase->EPCR[ep - 1U] & + (direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK)) ? + kUSB_DeviceEndpointStateStalled : + kUSB_DeviceEndpointStateIdle; + } + else + { + endpointStatus->endpointStatus = + (ehciState->registerBase->EPCR0 & (direction ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK)) ? + kUSB_DeviceEndpointStateStalled : + kUSB_DeviceEndpointStateIdle; + } + error = kStatus_USB_Success; + } + } + break; + case kUSB_DeviceControlSetDeviceAddress: + if (param) + { + temp8 = (uint8_t *)param; + ehciState->registerBase->DEVICEADDR = (((uint32_t)(*temp8)) << USBHS_DEVICEADDR_USBADR_SHIFT); + error = kStatus_USB_Success; + } + break; + case kUSB_DeviceControlGetSynchFrame: + break; +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +#if defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U) + case kUSB_DeviceControlResume: +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciState->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; +#else + ehciState->registerBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; +#endif + ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; + ehciState->registerBase->PORTSC1 |= USBHS_PORTSC1_FPR_MASK; + startTick = deviceHandle->hwTick; + while ((deviceHandle->hwTick - startTick) < 10) + { + __ASM("nop"); + } + ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_FPR_MASK; + error = kStatus_USB_Success; + break; +#endif /* USB_DEVICE_CONFIG_REMOTE_WAKEUP */ + case kUSB_DeviceControlSuspend: + ehciState->registerBase->OTGSC |= 0x007F0000U; + ehciState->registerPhyBase->PWD = 0xFFFFFFFF; + /* ehciState->registerBase->OTGCTL |= ((1U<<10) | (1U<<17) | (1U<<16)); */ + while (ehciState->registerPhyBase->CTRL & (USBPHY_CTRL_UTMI_SUSPENDM_MASK)) + { + __ASM("nop"); + } + /* ehciState->registerPhyBase->CTRL |= ((1U << 21) | (1U << 22) | (1U << 23)); */ + ehciState->registerBase->USBSTS |= USBHS_USBSTS_SRI_MASK; + ehciState->registerBase->PORTSC1 |= USBHS_PORTSC1_PHCD_MASK; +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciState->registerPhyBase->CTRL |= USBPHY_CTRL_ENVBUSCHG_WKUP_MASK | USBPHY_CTRL_ENIDCHG_WKUP_MASK | + USBPHY_CTRL_ENDPDMCHG_WKUP_MASK | USBPHY_CTRL_ENIRQRESUMEDETECT_MASK; + ehciState->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK | + USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK | + USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK; + ehciState->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WIE_MASK; +#else + ehciState->registerBase->USBGENCTRL = USBHS_USBGENCTRL_WU_IE_MASK; +#endif + ehciState->registerPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; + ehciState->isSuspending = 1U; + error = kStatus_USB_Success; + break; +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + case kUSB_DeviceControlSetDefaultStatus: + for (uint8_t count = 0U; count < USB_DEVICE_CONFIG_ENDPOINTS; count++) + { + USB_DeviceEhciEndpointDeinit(ehciState, (count | (USB_IN << 0x07U))); + USB_DeviceEhciEndpointDeinit(ehciState, (count | (USB_OUT << 0x07U))); + } + USB_DeviceEhciSetDefaultState(ehciState); + error = kStatus_USB_Success; + break; + case kUSB_DeviceControlGetSpeed: + if (param) + { + temp8 = (uint8_t *)param; + *temp8 = ehciState->speed; + error = kStatus_USB_Success; + } + break; + case kUSB_DeviceControlGetOtgStatus: + break; + case kUSB_DeviceControlSetOtgStatus: + break; +#if (defined(USB_DEVICE_CONFIG_USB20_TEST_MODE) && (USB_DEVICE_CONFIG_USB20_TEST_MODE > 0U)) + case kUSB_DeviceControlSetTestMode: + if (param) + { + temp8 = (uint8_t *)param; + ehciState->registerBase->PORTSC1 |= ((uint32_t)(*temp8) << 16U); + error = kStatus_USB_Success; + } + break; +#endif +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + case kUSB_DeviceControlDcdInitModule: + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + dcdHSState->dcdRegisterBase->TIMER0 = USBDCD_TIMER0_TSEQ_INIT(deviceDcdTimingConfig->dcdSeqInitTime); + dcdHSState->dcdRegisterBase->TIMER1 = USBDCD_TIMER1_TDCD_DBNC(deviceDcdTimingConfig->dcdDbncTime); + dcdHSState->dcdRegisterBase->TIMER1 |= USBDCD_TIMER1_TVDPSRC_ON(deviceDcdTimingConfig->dcdDpSrcOnTime); + dcdHSState->dcdRegisterBase->TIMER2_BC12 = + USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(deviceDcdTimingConfig->dcdTimeWaitAfterPrD); + dcdHSState->dcdRegisterBase->TIMER2_BC12 |= + USBDCD_TIMER2_BC12_TVDMSRC_ON(deviceDcdTimingConfig->dcdTimeDMSrcOn); + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_IE_MASK; + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_BC12_MASK; + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_START_MASK; + break; + case kUSB_DeviceControlDcdDeinitModule: + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + break; +#endif + + default: + break; + } + + return error; +} + +/*! + * @brief Handle the EHCI device interrupt. + * + * The function is used to handle the EHCI device interrupt. + * + * @param deviceHandle The device handle got from USB_DeviceInit. + * + */ +void USB_DeviceEhciIsrFunction(void *deviceHandle) +{ + usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle; + usb_device_ehci_state_struct_t *ehciState; + uint32_t status; + + if (NULL == deviceHandle) + { + return; + } + + ehciState = (usb_device_ehci_state_struct_t *)(handle->controllerHandle); + +#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + + if (ehciState->registerNcBase->USB_OTGn_CTRL & USBNC_USB_OTGn_CTRL_WIE_MASK) + { + if (ehciState->registerNcBase->USB_OTGn_CTRL & USBNC_USB_OTGn_CTRL_WIR_MASK) + { + ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; + ehciState->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; + } + } + else + { + } + +#else + if (ehciState->registerBase->USBGENCTRL & USBHS_USBGENCTRL_WU_IE_MASK) + { + if (ehciState->registerBase->USBGENCTRL & (1U << 8)) + { + ehciState->registerBase->USBGENCTRL &= ~(1U << 8); + ehciState->registerBase->USBGENCTRL |= USBHS_USBGENCTRL_WU_INT_CLR_MASK; + ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; + ehciState->registerBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; + } + } + else + { + } +#endif + +#endif + +#if defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U) + if (ehciState->registerBase->OTGSC & USBHS_OTGSC_BSVIS_MASK) + { + usb_device_callback_message_struct_t message; + + ehciState->registerBase->OTGSC |= USBHS_OTGSC_BSVIS_MASK; + + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + if (ehciState->registerBase->OTGSC & USBHS_OTGSC_BSV_MASK) + { + /* Device is connected to a host. */ + message.code = kUSB_DeviceNotifyAttach; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } + else + { + /* Device is disconnected from a host. */ + message.code = kUSB_DeviceNotifyDetach; + USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } + } +#endif /* USB_DEVICE_CONFIG_DETACH_ENABLE */ + + status = ehciState->registerBase->USBSTS; + status &= ehciState->registerBase->USBINTR; + + ehciState->registerBase->USBSTS = status; + +#if defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U) + if (status & USBHS_USBSTS_UEI_MASK) + { + /* Error interrupt */ + USB_DeviceEhciInterruptError(ehciState); + } +#endif /* USB_DEVICE_CONFIG_ERROR_HANDLING */ + + if (status & USBHS_USBSTS_URI_MASK) + { + /* Reset interrupt */ + USB_DeviceEhciInterruptReset(ehciState); + } + + if (status & USBHS_USBSTS_UI_MASK) + { + /* Token done interrupt */ + USB_DeviceEhciInterruptTokenDone(ehciState); + } + + if (status & USBHS_USBSTS_PCI_MASK) + { + /* Port status change interrupt */ + USB_DeviceEhciInterruptPortChange(ehciState); + } + +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + if (status & USBHS_USBSTS_SLI_MASK) + { + /* Suspend interrupt */ + USB_DeviceEhciInterruptSuspend(ehciState); + } +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + + if (status & USBHS_USBSTS_SRI_MASK) + { + /* Sof interrupt */ + USB_DeviceEhciInterruptSof(ehciState); + } +} + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +void USB_DeviceDcdHSIsrFunction(void *deviceHandle) +{ + usb_device_struct_t *handle = (usb_device_struct_t *)deviceHandle; + usb_device_ehci_state_struct_t *ehciState; + usb_device_dcd_state_struct_t *dcdHSState; + uint32_t status; + uint32_t chargerType; + usb_device_callback_message_struct_t message; + + if (NULL == deviceHandle) + { + return; + } + + ehciState = (usb_device_ehci_state_struct_t *)(handle->controllerHandle); + + dcdHSState = &s_UsbDeviceDcdHSState[ehciState->controllerId - kUSB_ControllerEhci0]; + + status = dcdHSState->dcdRegisterBase->STATUS; + + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_IACK_MASK; + + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + + if (status & USBDCD_STATUS_ERR_MASK) + { + if (status & USBDCD_STATUS_TO_MASK) + { + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + message.code = kUSB_DeviceNotifyDcdTimeOut; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + else + { + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + message.code = kUSB_DeviceNotifyDcdUnknownPortType; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + } + else + { + switch (status & USBDCD_STATUS_SEQ_STAT_MASK) + { + case USBDCD_STATUS_SEQ_STAT(kUSB_DcdChargingPortDetectionCompleted): + chargerType = status & USBDCD_STATUS_SEQ_RES_MASK; + if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionStandardHost)) + { + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + message.code = kUSB_DeviceNotifySDPDetected; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + else if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionChargingPort)) + { + message.code = kUSB_DeviceNotifyChargingPortDetected; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + break; + case USBDCD_STATUS_SEQ_STAT(kUSB_DcdChargerTypeDetectionCompleted): + chargerType = status & USBDCD_STATUS_SEQ_RES_MASK; + if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionChargingPort)) + { + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + message.code = kUSB_DeviceNotifyChargingHostDetected; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + else if (chargerType == USBDCD_STATUS_SEQ_RES(kUSB_DcdDetectionDedicatedCharger)) + { + dcdHSState->dcdRegisterBase->CONTROL |= USBDCD_CONTROL_SR_MASK; + message.code = kUSB_DeviceNotifyDedicatedChargerDetected; + USB_DeviceNotificationTrigger(dcdHSState->deviceHandle, &message); + } + break; + + default: + break; + } + } +} +#endif + +#endif /* USB_DEVICE_CONFIG_EHCI */ diff --git a/bsp/imxrt/libraries/drivers/usb/device/usb_device_ehci.h b/bsp/imxrt/libraries/drivers/usb/device/usb_device_ehci.h new file mode 100644 index 0000000000000000000000000000000000000000..869e0632639020680dc4f6e762004cc1a4aab755 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/device/usb_device_ehci.h @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_DEVICE_EHCI_H__ +#define __USB_DEVICE_EHCI_H__ + +#include + +/*! + * @addtogroup usb_device_controller_ehci_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief The maximum value of ISO type maximum packet size for HS in USB specification 2.0 */ +#define USB_DEVICE_MAX_HS_ISO_MAX_PACKET_SIZE (1024U) + +/*! @brief The maximum value of interrupt type maximum packet size for HS in USB specification 2.0 */ +#define USB_DEVICE_MAX_HS_INTERUPT_MAX_PACKET_SIZE (1024U) + +/*! @brief The maximum value of bulk type maximum packet size for HS in USB specification 2.0 */ +#define USB_DEVICE_MAX_HS_BULK_MAX_PACKET_SIZE (512U) + +/*! @brief The maximum value of control type maximum packet size for HS in USB specification 2.0 */ +#define USB_DEVICE_MAX_HS_CONTROL_MAX_PACKET_SIZE (64U) + +/*! @brief EHCI state structure */ +typedef struct _usb_device_ehci_state_struct +{ + usb_device_struct_t *deviceHandle; /*!< Device handle used to identify the device object is belonged to */ + USBHS_Type *registerBase; /*!< The base address of the register */ +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + USBPHY_Type *registerPhyBase; /*!< The base address of the PHY register */ +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + USBNC_Type *registerNcBase; /*!< The base address of the USBNC register */ +#endif +#endif + usb_device_ehci_qh_struct_t *qh; /*!< The QH structure base address */ + usb_device_ehci_dtd_struct_t *dtd; /*!< The DTD structure base address */ + usb_device_ehci_dtd_struct_t *dtdFree; /*!< The idle DTD list head */ + usb_device_ehci_dtd_struct_t + *dtdHard[USB_DEVICE_CONFIG_ENDPOINTS * 2]; /*!< The transferring DTD list head for each endpoint */ + usb_device_ehci_dtd_struct_t + *dtdTail[USB_DEVICE_CONFIG_ENDPOINTS * 2]; /*!< The transferring DTD list tail for each endpoint */ + int8_t dtdCount; /*!< The idle DTD node count */ + uint8_t endpointCount; /*!< The endpoint number of EHCI */ + uint8_t isResetting; /*!< Whether a PORT reset is occurring or not */ + uint8_t controllerId; /*!< Controller ID */ + uint8_t speed; /*!< Current speed of EHCI */ + uint8_t isSuspending; /*!< Is suspending of the PORT */ +} usb_device_ehci_state_struct_t; + +#if (defined(USB_DEVICE_CHARGER_DETECT_ENABLE) && (USB_DEVICE_CHARGER_DETECT_ENABLE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +typedef struct _usb_device_dcd_state_struct +{ + usb_device_struct_t *deviceHandle; /*!< Device handle used to identify the device object belongs to */ + USBHSDCD_Type *dcdRegisterBase; /*!< The base address of the dcd module */ + uint8_t controllerId; /*!< Controller ID */ +} usb_device_dcd_state_struct_t; +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name USB device EHCI functions + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Initializes the USB device EHCI instance. + * + * This function initializes the USB device EHCI module specified by the controllerId. + * + * @param[in] controllerId The controller ID of the USB IP. See the enumeration type usb_controller_index_t. + * @param[in] handle Pointer of the device handle used to identify the device object is belonged to. + * @param[out] ehciHandle An out parameter used to return the pointer of the device EHCI handle to the caller. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciInit(uint8_t controllerId, + usb_device_handle handle, + usb_device_controller_handle *ehciHandle); + +/*! + * @brief Deinitializes the USB device EHCI instance. + * + * This function deinitializes the USB device EHCI module. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciDeinit(usb_device_controller_handle ehciHandle); + +/*! + * @brief Sends data through a specified endpoint. + * + * This function sends data through a specified endpoint. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to hold the data need to be sent. + * @param[in] length The data length to be sent. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value means whether the sending request is successful or not. The transfer completion is indicated + * by the + * corresponding callback function. + * Currently, only one transfer request can be supported for a specific endpoint. + * If there is a specific requirement to support multiple transfer requests for a specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer can begin only when the previous transfer is done (a notification is received through the + * endpoint + * callback). + */ +usb_status_t USB_DeviceEhciSend(usb_device_controller_handle ehciHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Receive data through a specified endpoint. + * + * This function Receives data through a specified endpoint. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to save the received data. + * @param[in] length The data length want to be received. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceEhciRecv(usb_device_controller_handle ehciHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Cancels the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * @param[in] ep Endpoint address, bit7 is the direction of endpoint, 1U - IN, 0U - OUT. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciCancel(usb_device_controller_handle ehciHandle, uint8_t ep); + +/*! + * @brief Controls the status of the selected item. + * + * The function is used to control the status of the selected item. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * @param[in] type The selected item. See enumeration type usb_device_control_type_t. + * @param[in,out] param The parameter type is determined by the selected item. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciControl(usb_device_controller_handle ehciHandle, + usb_device_control_type_t type, + void *param); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* __USB_DEVICE_EHCI_H__ */ diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host.h b/bsp/imxrt/libraries/drivers/usb/host/usb_host.h new file mode 100644 index 0000000000000000000000000000000000000000..53be402cd3640a5f3b9ce4bc181004cb00fc08a8 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host.h @@ -0,0 +1,726 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_HOST_H_ +#define _USB_HOST_H_ + +#include +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +struct _usb_host_transfer; /* for cross reference */ + +/*! + * @addtogroup usb_host_drv + * @{ + */ + +/*! @brief USB host class handle type define */ +typedef void *usb_host_class_handle; + +/*! @brief USB host controller handle type define */ +typedef void *usb_host_controller_handle; + +/*! @brief USB host configuration handle type define */ +typedef void *usb_host_configuration_handle; + +/*! @brief USB host interface handle type define */ +typedef void *usb_host_interface_handle; + +/*! @brief USB host pipe handle type define */ +typedef void *usb_host_pipe_handle; + +/*! @brief Event codes for device attach/detach */ +typedef enum _usb_host_event +{ + kUSB_HostEventAttach = 1U, /*!< Device is attached */ + kUSB_HostEventDetach, /*!< Device is detached */ + kUSB_HostEventEnumerationDone, /*!< Device's enumeration is done and the device is supported */ + kUSB_HostEventNotSupported, /*!< Device's enumeration is done and the device is not supported */ +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + kUSB_HostEventNotSuspended, /*!< Suspend failed */ + kUSB_HostEventSuspended, /*!< Suspend successful */ + kUSB_HostEventNotResumed, /*!< Resume failed */ + kUSB_HostEventDetectResume, /*!< Detect resume signal */ + kUSB_HostEventResumed, /*!< Resume successful */ + kUSB_HostEventL1Sleeped, /*!< L1 Sleep successful,state transition was successful (ACK) */ + kUSB_HostEventL1SleepNYET, /*!< Device was unable to enter the L1 state at this time (NYET) */ + kUSB_HostEventL1SleepNotSupport, /*!< Device does not support the L1 state (STALL) */ + kUSB_HostEventL1SleepError, /*!< Device failed to respond or an error occurred */ + kUSB_HostEventL1NotResumed, /*!< Resume failed */ + kUSB_HostEventL1DetectResume, /*!< Detect resume signal */ + kUSB_HostEventL1Resumed, /*!< Resume successful */ +#endif +} usb_host_event_t; + +/*! @brief USB host device information code */ +typedef enum _usb_host_dev_info +{ + kUSB_HostGetDeviceAddress = 1U, /*!< Device's address */ + kUSB_HostGetDeviceHubNumber, /*!< Device's first hub address */ + kUSB_HostGetDevicePortNumber, /*!< Device's first hub port number */ + kUSB_HostGetDeviceSpeed, /*!< Device's speed */ + kUSB_HostGetDeviceHSHubNumber, /*!< Device's first high-speed hub address */ + kUSB_HostGetDeviceHSHubPort, /*!< Device's first high-speed hub number */ + kUSB_HostGetDeviceLevel, /*!< Device's hub level */ + kUSB_HostGetHostHandle, /*!< Device's host handle */ + kUSB_HostGetDeviceControlPipe, /*!< Device's control pipe handle */ + kUSB_HostGetDevicePID, /*!< Device's PID */ + kUSB_HostGetDeviceVID, /*!< Device's VID */ + kUSB_HostGetHubThinkTime, /*!< Device's hub total think time */ + kUSB_HostGetDeviceConfigIndex, /*!< Device's running zero-based config index */ + kUSB_HostGetConfigurationDes, /*!< Device's configuration descriptor pointer */ + kUSB_HostGetConfigurationLength, /*!< Device's configuration descriptor pointer */ +} usb_host_dev_info_t; + +/*! + * @brief Host callback function typedef. + * + * This callback function is used to notify application device attach/detach event. + * This callback pointer is passed when initializing the host. + * + * @param deviceHandle The device handle, which indicates the attached device. + * @param configurationHandle The configuration handle contains the attached device's configuration information. + * @param event_code The callback event code; See the enumeration host_event_t. + * + * @return A USB error code or kStatus_USB_Success. + * @retval kStatus_USB_Success Application handles the attached device successfully. + * @retval kStatus_USB_NotSupported Application don't support the attached device. + * @retval kStatus_USB_Error Application handles the attached device falsely. + */ +typedef usb_status_t (*host_callback_t)(usb_device_handle deviceHandle, + usb_host_configuration_handle configurationHandle, + uint32_t eventCode); + +/*! + * @brief Transfer callback function typedef. + * + * This callback function is used to notify the upper layer the result of the transfer. + * This callback pointer is passed when calling the send/receive APIs. + * + * @param param The parameter pointer, which is passed when calling the send/receive APIs. + * @param data The data buffer pointer. + * @param data_len The result data length. + * @param status A USB error code or kStatus_USB_Success. + */ +typedef void (*transfer_callback_t)(void *param, uint8_t *data, uint32_t dataLen, usb_status_t status); + +/*! + * @brief Host stack inner transfer callback function typedef. + * + * This callback function is used to notify the upper layer the result of a transfer. + * This callback pointer is passed when initializing the structure usb_host_transfer_t. + * + * @param param The parameter pointer, which is passed when calling the send/receive APIs. + * @param transfer The transfer information; See the structure usb_host_transfer_t. + * @param status A USB error code or kStatus_USB_Success. + */ +typedef void (*host_inner_transfer_callback_t)(void *param, struct _usb_host_transfer *transfer, usb_status_t status); + +/*! @brief USB host endpoint information structure */ +typedef struct _usb_host_ep +{ + usb_descriptor_endpoint_t *epDesc; /*!< Endpoint descriptor pointer*/ + uint8_t *epExtension; /*!< Endpoint extended descriptor pointer*/ + uint16_t epExtensionLength; /*!< Extended descriptor length*/ +} usb_host_ep_t; + +/*! @brief USB host interface information structure */ +typedef struct _usb_host_interface +{ + usb_host_ep_t epList[USB_HOST_CONFIG_INTERFACE_MAX_EP]; /*!< Endpoint array*/ + usb_descriptor_interface_t *interfaceDesc; /*!< Interface descriptor pointer*/ + uint8_t *interfaceExtension; /*!< Interface extended descriptor pointer*/ + uint16_t interfaceExtensionLength; /*!< Extended descriptor length*/ + uint8_t interfaceIndex; /*!< The interface index*/ + uint8_t alternateSettingNumber; /*!< The interface alternate setting value*/ + uint8_t epCount; /*!< Interface's endpoint number*/ +} usb_host_interface_t; + +/*! @brief USB host configuration information structure */ +typedef struct _usb_host_configuration +{ + usb_host_interface_t interfaceList[USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE]; /*!< Interface array*/ + usb_descriptor_configuration_t *configurationDesc; /*!< Configuration descriptor pointer*/ + uint8_t *configurationExtension; /*!< Configuration extended descriptor pointer*/ + uint16_t configurationExtensionLength; /*!< Extended descriptor length*/ + uint8_t interfaceCount; /*!< The configuration's interface number*/ +} usb_host_configuration_t; + +/*! @brief USB host pipe common structure */ +typedef struct _usb_host_pipe +{ + struct _usb_host_pipe *next; /*!< Link the idle pipes*/ + usb_device_handle deviceHandle; /*!< This pipe's device's handle*/ + uint16_t currentCount; /*!< For KHCI transfer*/ + uint16_t nakCount; /*!< Maximum NAK count*/ + uint16_t maxPacketSize; /*!< Maximum packet size*/ + uint16_t interval; /*!< FS/LS: frame unit; HS: micro-frame unit*/ + uint8_t open; /*!< 0 - closed, 1 - open*/ + uint8_t nextdata01; /*!< Data toggle*/ + uint8_t endpointAddress; /*!< Endpoint address*/ + uint8_t direction; /*!< Pipe direction*/ + uint8_t pipeType; /*!< Pipe type, for example USB_ENDPOINT_BULK*/ + uint8_t numberPerUframe; /*!< Transaction number per micro-frame*/ +} usb_host_pipe_t; + +/*! @brief USB host transfer structure */ +typedef struct _usb_host_transfer +{ + struct _usb_host_transfer *next; /*!< The next transfer structure*/ + uint8_t *transferBuffer; /*!< Transfer data buffer*/ + uint32_t transferLength; /*!< Transfer data length*/ + uint32_t transferSofar; /*!< Length transferred so far*/ + host_inner_transfer_callback_t callbackFn; /*!< Transfer callback function*/ + void *callbackParam; /*!< Transfer callback parameter*/ + usb_host_pipe_t *transferPipe; /*!< Transfer pipe pointer*/ + usb_setup_struct_t *setupPacket; /*!< Set up packet buffer*/ + uint8_t direction; /*!< Transfer direction; it's values are USB_OUT or USB_IN*/ + uint8_t setupStatus; /*!< Set up the transfer status*/ + union + { + uint32_t unitHead; /*!< xTD head for this transfer*/ + int32_t transferResult; /*!< KHCI transfer result */ + } union1; + + union + { + uint32_t unitTail; /*! 0U)) +/*! + * @brief Send a bus or device suspend request. + * + * This function is used to send a bus or device suspend request. + * + * @param[in] hostHandle The host handle. + * @param[in] deviceHandle The device handle. + * + * @retval kStatus_USB_Success Request successfully. + * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Error There is no idle transfer. + * Or, the deviceHandle is invalid. + * Or, the request is invalid. + */ +extern usb_status_t USB_HostSuspendDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle); + +/*! + * @brief Send a bus or device resume request. + * + * This function is used to send a bus or device resume request. + * + * @param[in] hostHandle The host handle. + * @param[in] deviceHandle The device handle. + * + * @retval kStatus_USB_Success Request successfully. + * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Error There is no idle transfer. + * Or, the deviceHandle is invalid. + * Or, the request is invalid. + */ +extern usb_status_t USB_HostResumeDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle); +#if ((defined(USB_HOST_CONFIG_LPM_L1)) && (USB_HOST_CONFIG_LPM_L1 > 0U)) +/*! + * @brief Send a bus or device suspend request. + * + * This function is used to send a bus or device suspend request. + * + * @param[in] hostHandle The host handle. + * @param[in] deviceHandle The device handle. + *@param[in] sleeptype Bus suspend or single device suspend. + * + * @retval kStatus_USB_Success Request successfully. + * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Error There is no idle transfer. + * Or, the deviceHandle is invalid. + * Or, the request is invalid. + */ +extern usb_status_t USB_HostL1SleepDeviceResquest(usb_host_handle hostHandle, + usb_device_handle deviceHandle, + uint8_t sleeptype); + +/*! + * @brief Send a bus or device resume request. + * + * This function is used to send a bus or device resume request. + * + * @param[in] hostHandle The host handle. + * @param[in] deviceHandle The device handle. + * *@param[in] sleeptype Bus suspend or single device suspend. + * + * @retval kStatus_USB_Success Request successfully. + * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Error There is no idle transfer. + * Or, the deviceHandle is invalid. + * Or, the request is invalid. + */ +extern usb_status_t USB_HostL1ResumeDeviceResquest(usb_host_handle hostHandle, + usb_device_handle deviceHandle, + uint8_t sleepType); +/*! + * @brief Update the lpm param. + * + * The function is used to configuure the lpm token. + * + * @param[in] hostHandle The host handle. + * @param[in] lpmParam HIRD vaule and whether enable remotewakeup. + * + */ +extern usb_status_t USB_HostL1SleepDeviceResquestConfig(usb_host_handle hostHandle, uint8_t *lpmParam); +#endif +/*! + * @brief Update the hardware tick. + * + * The function is used to update the hardware tick. + * + * @param[in] hostHandle The host handle. + * @param[in] tick Current hardware tick(uint is ms). + * + */ +extern usb_status_t USB_HostUpdateHwTick(usb_host_handle hostHandle, uint64_t tick); + +#endif + +/*! @}*/ + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* _USB_HOST_H_ */ diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.c b/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.c new file mode 100644 index 0000000000000000000000000000000000000000..42b16e071ed3a27144f98a7fa2c01e1101a0b166 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.c @@ -0,0 +1,1414 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "usb_host.h" +#include "usb_host_hci.h" +#include "usb_host_devices.h" + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) +#include "usb_host_hub.h" +#endif /* USB_HOST_CONFIG_HUB */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief enumeration transfer callback function. + * + * @param param callback parameter. + * @param transfer the transfer. + * @param status transfer result status. + */ +static void USB_HostEnumerationTransferCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status); + +/*! + * @brief process the new step state. + * + * @param deviceInstance device instance pointer. + * + * @return kStatus_USB_Success or error codes + */ +static usb_status_t USB_HostProcessState(usb_host_device_instance_t *deviceInstance); + +/*! + * @brief process the previous step transfer result. + * + * @param deviceInstance device instance pointer. + * + * @return kStatus_USB_Success or error codes + */ +static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceInstance); + +/*! + * @brief notify the application event, the callback is registered when initializing host. + * + * @param deviceInstance device instance pointer. + * @param eventCode event code. + * + * @return kStatus_USB_Success or error codes + */ +static usb_status_t USB_HostNotifyDevice(usb_host_device_instance_t *deviceInstance, uint32_t eventCode); + +/*! + * @brief allocate one address. + * + * @param hostInstance host instance pointer. + * + * @return address, 0 is invalid. + */ +static uint8_t USB_HostAllocateDeviceAddress(usb_host_instance_t *hostInstance); + +/*! + * @brief release one address. + * + * @param hostInstance host instance pointer. + * @param address releasing address. + */ +static void USB_HostReleaseDeviceAddress(usb_host_instance_t *hostInstance, uint8_t address); + +/*! + * @brief release device resource. + * + * @param hostInstance host instance pointer. + * @param deviceInstance device instance pointer. + */ +static void USB_HostReleaseDeviceResource(usb_host_instance_t *hostInstance, + usb_host_device_instance_t *deviceInstance); + +/*! + * @brief parse device configuration descriptor. + * + * @param deviceHandle device handle. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle deviceHandle); + +/*! + * @brief remove device instance from host device list. + * + * @param hostHandle host instance handle. + * @param deviceHandle device handle. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostRemoveDeviceInstance(usb_host_handle hostHandle, usb_device_handle deviceHandle); + +/*! + * @brief control the bus. + * + * This function control the host bus. + * + * @param[in] hostHandle the host handle. + * @param[in] controlType the control code, please reference to bus_event_t. + * + * @retval kStatus_USB_Success control successfully. + * @retval kStatus_USB_InvalidHandle The hostHandle is a NULL pointer. + */ +static usb_status_t USB_HostControlBus(usb_host_handle hostHandle, uint8_t controlType); + +extern usb_status_t USB_HostStandardSetGetDescriptor(usb_host_device_instance_t *deviceInstance, + usb_host_transfer_t *transfer, + void *param); +extern usb_status_t USB_HostStandardSetAddress(usb_host_device_instance_t *deviceInstance, + usb_host_transfer_t *transfer, + void *param); +extern usb_status_t USB_HostCh9RequestCommon(usb_host_device_instance_t *deviceInstance, + usb_host_transfer_t *transfer, + uint8_t *buffer, + uint32_t bufferLen); + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + +extern usb_status_t USB_HostHubDeviceEvent(usb_host_handle hostHandle, + usb_device_handle deviceHandle, + usb_host_configuration_handle configurationHandle, + uint32_t eventCode); + +extern uint32_t USB_HostHubGetHsHubNumber(usb_host_handle hostHandle, uint8_t parentHubNo); + +extern uint32_t USB_HostHubGetHsHubPort(usb_host_handle hostHandle, uint8_t parentHubNo, uint8_t parentPortNo); + +extern usb_status_t USB_HostHubRemovePort(usb_host_handle hostHandle, uint8_t hubNumber, uint8_t portNumber); + +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +extern usb_host_instance_t g_UsbHostInstance[USB_HOST_CONFIG_MAX_HOST]; + +/*! @brief enumeration step process array */ +static const usb_host_enum_process_entry_t s_EnumEntries[] = \ +{ + /* kStatus_dev_initial */ + { + 0, 0, NULL, + }, + /* kStatus_DEV_GetDes8 */ + { + kStatus_DEV_SetAddress, kStatus_DEV_GetDes8, USB_HostProcessCallback, + }, + /* kStatus_DEV_SetAddress */ + { + kStatus_DEV_GetDes, kStatus_DEV_SetAddress, USB_HostProcessCallback, + }, + /* kStatus_DEV_GetDes */ + { + kStatus_DEV_GetCfg9, kStatus_DEV_GetDes, NULL, + }, + /* kStatus_DEV_GetCfg9 */ + { + kStatus_DEV_GetCfg, kStatus_DEV_GetCfg9, USB_HostProcessCallback, + }, + /* kStatus_DEV_GetCfg */ + { + kStatus_DEV_SetCfg, kStatus_DEV_GetCfg9, USB_HostProcessCallback, + }, + /* kStatus_DEV_SetCfg */ + { + kStatus_DEV_EnumDone, kStatus_DEV_SetCfg, NULL, + }, +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void USB_HostEnumerationTransferCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status) +{ + uint8_t nextStep = 0; + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)param; + + USB_HostFreeTransfer(deviceInstance->hostHandle, transfer); /* free transfer */ + + if (status == kStatus_USB_Success) + { + nextStep = 1; + } + else if (status == kStatus_USB_TransferStall) + { +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) + usb_echo("no response from device\r\n"); +#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ + if (deviceInstance->stallRetries > 0) /* retry same transfer when stall */ + { + deviceInstance->stallRetries--; + } + else /* process next state when all retries stall */ + { + nextStep = 1; + } + } + else if (status == kStatus_USB_TransferCancel) + { + return; + } + else + { + if (deviceInstance->enumRetries > 0) /* next whole retry */ + { + deviceInstance->enumRetries--; + deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; + deviceInstance->configurationValue = 0; + deviceInstance->state = kStatus_DEV_GetDes8; + } + else + { +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) + usb_echo("Device No Response\r\n"); +#endif + return; + } + } + + if (nextStep == 1) + { + deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; + if (s_EnumEntries[deviceInstance->state - 1].process == NULL) + { + deviceInstance->state = s_EnumEntries[deviceInstance->state - 1].successState; /* next state */ + } + else + { + status = s_EnumEntries[deviceInstance->state - 1].process( + deviceInstance); /* process the previous state result */ + if (status == kStatus_USB_Success) /* process success */ + { + deviceInstance->state = s_EnumEntries[deviceInstance->state - 1].successState; + } + else if (status == kStatus_USB_Retry) /* need retry */ + { + deviceInstance->state = s_EnumEntries[deviceInstance->state - 1].retryState; + } + else if (status == kStatus_USB_NotSupported) /* device don't suport by the application */ + { + return; /* unrecoverable fail */ + } + else /* process error, next retry */ + { + if (deviceInstance->enumRetries > 0) /* next whole retry */ + { + deviceInstance->enumRetries--; + deviceInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; + deviceInstance->configurationValue = 0; + deviceInstance->state = kStatus_DEV_GetDes8; + } + else + { +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) + usb_echo("Device No Response\r\n"); +#endif + return; /* unrecoverable fail */ + } + } + } + } + + if (USB_HostProcessState(deviceInstance) != kStatus_USB_Success) /* process the new state */ + { +#ifdef HOST_ECHO + usb_echo("enumation setup error\r\n"); +#endif + return; + } +} + +static usb_status_t USB_HostProcessState(usb_host_device_instance_t *deviceInstance) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_process_descriptor_param_t getDescriptorParam; + usb_host_transfer_t *transfer; + + /* malloc transfer */ + if (deviceInstance->state != kStatus_DEV_EnumDone) + { + if (USB_HostMallocTransfer(deviceInstance->hostHandle, &transfer) != kStatus_USB_Success) + { +#ifdef HOST_ECHO + usb_echo("error to get transfer\r\n"); +#endif + return kStatus_USB_Error; + } + transfer->callbackFn = USB_HostEnumerationTransferCallback; + transfer->callbackParam = deviceInstance; + + /* reset transfer fields */ + transfer->setupPacket->bmRequestType = 0x00; + transfer->setupPacket->wIndex = 0; + transfer->setupPacket->wLength = 0; + transfer->setupPacket->wValue = 0; + } + + switch (deviceInstance->state) + { + case kStatus_DEV_GetDes8: + case kStatus_DEV_GetDes: /* get descriptor state */ + getDescriptorParam.descriptorLength = sizeof(usb_descriptor_device_t); + if (deviceInstance->state == kStatus_DEV_GetDes8) + { + getDescriptorParam.descriptorLength = 8; + } + getDescriptorParam.descriptorBuffer = (uint8_t *)deviceInstance->deviceDescriptor; + getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_DEVICE; + getDescriptorParam.descriptorIndex = 0; + getDescriptorParam.languageId = 0; + + transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN; + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; + status = USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); + break; + case kStatus_DEV_SetAddress: /* set address state */ + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_SET_ADDRESS; + status = USB_HostStandardSetAddress(deviceInstance, transfer, &deviceInstance->allocatedAddress); + break; + + case kStatus_DEV_GetCfg9: /* get 9 bytes configuration state */ + getDescriptorParam.descriptorBuffer = deviceInstance->enumBuffer; + getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_CONFIGURE; + getDescriptorParam.descriptorIndex = deviceInstance->configurationValue; + getDescriptorParam.descriptorLength = 9; + getDescriptorParam.languageId = 0; + + transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN; + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; + status = USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); + break; + + case kStatus_DEV_GetCfg: /* get configuration state */ + getDescriptorParam.descriptorBuffer = deviceInstance->configurationDesc; + getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_CONFIGURE; + getDescriptorParam.descriptorIndex = deviceInstance->configurationValue; + getDescriptorParam.descriptorLength = deviceInstance->configurationLen; + getDescriptorParam.languageId = 0; + + transfer->setupPacket->bmRequestType |= USB_REQUEST_TYPE_DIR_IN; + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; + status = USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); + break; + + case kStatus_DEV_SetCfg: /* set configuration state */ + transfer->setupPacket->wValue = + USB_SHORT_TO_LITTLE_ENDIAN(deviceInstance->configuration.configurationDesc->bConfigurationValue); + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_SET_CONFIGURATION; + status = USB_HostCh9RequestCommon(deviceInstance, transfer, NULL, 0); + break; + + case kStatus_DEV_EnumDone: /* enumeration done state */ + status = USB_HostNotifyDevice(deviceInstance, + kUSB_HostEventEnumerationDone); /* notify device enumeration done */ + if (status == kStatus_USB_Success) + { + deviceInstance->state = kStatus_DEV_AppUsed; + } + break; + + default: + break; + } + + return status; +} + +static usb_status_t USB_HostProcessCallback(usb_host_device_instance_t *deviceInstance) +{ + usb_host_pipe_t *pipe = (usb_host_pipe_t *)deviceInstance->controlPipe; + usb_status_t status = kStatus_USB_Success; + usb_descriptor_configuration_t *configureDesc; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; + + switch (deviceInstance->state) + { + case kStatus_DEV_GetDes8: /* process get 8 bytes descriptor result */ + pipe->maxPacketSize = deviceInstance->deviceDescriptor->bMaxPacketSize0; + hostInstance->controllerTable->controllerIoctl( + hostInstance->controllerHandle, kUSB_HostUpdateControlPacketSize, deviceInstance->controlPipe); + break; + + case kStatus_DEV_SetAddress: /* process set address result */ + deviceInstance->setAddress = deviceInstance->allocatedAddress; + hostInstance->controllerTable->controllerIoctl( + hostInstance->controllerHandle, kUSB_HostUpdateControlEndpointAddress, deviceInstance->controlPipe); + break; + + case kStatus_DEV_GetDes: /* process set address result */ + /* NULL */ + break; + + case kStatus_DEV_GetCfg9: /* process get 9 bytes configuration result */ + configureDesc = (usb_descriptor_configuration_t *)&deviceInstance->enumBuffer[0]; + + deviceInstance->configurationLen = USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(configureDesc->wTotalLength); + if (deviceInstance->configurationDesc != NULL) + { +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(deviceInstance->configurationDesc); +#else + USB_OsaMemoryFree(deviceInstance->configurationDesc); +#endif + deviceInstance->configurationDesc = NULL; + } + /* for KHCI, the start address and the length should be 4 byte align */ + if ((deviceInstance->configurationLen & 0x03) != 0) + { +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + deviceInstance->configurationDesc = + (uint8_t *)SDK_Malloc((deviceInstance->configurationLen & 0xFFFFFFFCu) + 4, USB_CACHE_LINESIZE); +#else + deviceInstance->configurationDesc = + (uint8_t *)USB_OsaMemoryAllocate((deviceInstance->configurationLen & 0xFFFFFFFCu) + 4); +#endif + } + else + { +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + deviceInstance->configurationDesc = + (uint8_t *)SDK_Malloc(deviceInstance->configurationLen, USB_CACHE_LINESIZE); +#else + deviceInstance->configurationDesc = (uint8_t *)USB_OsaMemoryAllocate(deviceInstance->configurationLen); +#endif + } + if (deviceInstance->configurationDesc == NULL) + { + return kStatus_USB_Error; + } + break; + + case kStatus_DEV_GetCfg: /* process get cofiguration result */ + if (((usb_descriptor_configuration_t *)deviceInstance->configurationDesc)->bMaxPower > + USB_HOST_CONFIG_MAX_POWER) + { + return kStatus_USB_Error; + } + deviceInstance->configurationValue++; + if (USB_HostParseDeviceConfigurationDescriptor(deviceInstance) != + kStatus_USB_Success) /* parse configuration descriptor */ + { + return kStatus_USB_Error; + } + + status = USB_HostNotifyDevice(deviceInstance, kUSB_HostEventAttach); + + if (status != kStatus_USB_Success) + { + /* next configuration */ + if (deviceInstance->configurationValue < deviceInstance->deviceDescriptor->bNumConfigurations) + { + return kStatus_USB_Retry; + } + else + { + USB_HostNotifyDevice(deviceInstance, + kUSB_HostEventNotSupported); /* notify application device is not supported */ + return kStatus_USB_NotSupported; + } + } + break; + + case kStatus_DEV_SetCfg: + /* NULL */ + break; + + default: + break; + } + + return status; +} + +static usb_status_t USB_HostNotifyDevice(usb_host_device_instance_t *deviceInstance, uint32_t eventCode) +{ + usb_host_instance_t *hostInstance; + usb_status_t status1 = kStatus_USB_Error; +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + usb_status_t status2 = kStatus_USB_Error; + uint8_t haveHub; + uint8_t haveNoHub; + uint8_t interfaceIndex; +#endif /* USB_HOST_CONFIG_HUB */ + + if (deviceInstance == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + haveHub = 0; + haveNoHub = 0; + for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) + { + if (((usb_descriptor_interface_t *)deviceInstance->configuration.interfaceList[interfaceIndex].interfaceDesc) + ->bInterfaceClass == USB_HOST_HUB_CLASS_CODE) + { + haveHub = 1; + } + else + { + haveNoHub = 1; + } + } + + if ((haveNoHub == 1) && (hostInstance->deviceCallback != NULL)) + { + status1 = hostInstance->deviceCallback(deviceInstance, &deviceInstance->configuration, + eventCode); /* notify application event */ + } + if (haveHub) + { + status2 = USB_HostHubDeviceEvent(hostInstance, deviceInstance, &deviceInstance->configuration, + eventCode); /* notify hub event */ + } + + if ((status1 == kStatus_USB_Success) || (status2 == kStatus_USB_Success)) /* the device is supported */ + { + return kStatus_USB_Success; + } + else if (eventCode == kUSB_HostEventAttach) /* attach event */ + { + status1 = kStatus_USB_NotSupported; + } + else + { + status1 = kStatus_USB_Error; + } +#else + if (hostInstance->deviceCallback != NULL) + { + status1 = hostInstance->deviceCallback(deviceInstance, &deviceInstance->configuration, + eventCode); /* call host callback function */ + } +#endif + return status1; +} + +static uint8_t USB_HostAllocateDeviceAddress(usb_host_instance_t *hostInstance) +{ + uint8_t address = 0; + uint8_t addressIndex; + uint8_t addressBitIndex; + for (addressIndex = 0; addressIndex < 8; ++addressIndex) /* find the idle address postion byte */ + { + if (hostInstance->addressBitMap[addressIndex] != 0xFF) + { + break; + } + } + if (addressIndex < 8) + { + for (addressBitIndex = 0; addressBitIndex < 8; ++addressBitIndex) /* find the idle address position bit */ + { + if (!(hostInstance->addressBitMap[addressIndex] & (0x01u << addressBitIndex))) + { + hostInstance->addressBitMap[addressIndex] |= (0x01u << addressBitIndex); /* set the allocated bit */ + address = addressIndex * 8 + addressBitIndex + 1; /* the address minimum is 1 */ + break; + } + } + } + return address; +} + +static void USB_HostReleaseDeviceAddress(usb_host_instance_t *hostInstance, uint8_t address) +{ + USB_HostLock(); + hostInstance->addressBitMap[(uint32_t)(address - 1) >> 3] &= + (~(0x01u << (((uint32_t)address - 1) & 0x07U))); /* reset the allocated bit */ + USB_HostUnlock(); +} + +static usb_status_t USB_HostRemoveDeviceInstance(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + usb_host_device_instance_t *currentInstance; + usb_host_device_instance_t *prevInstance; + if ((hostHandle == NULL) || (deviceHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* search and remove device instance */ + prevInstance = (usb_host_device_instance_t *)hostInstance->deviceList; + if (prevInstance == deviceHandle) + { + hostInstance->deviceList = prevInstance->next; + return kStatus_USB_Success; + } + else + { + currentInstance = prevInstance->next; + } + + while (currentInstance != NULL) + { + if (currentInstance == deviceHandle) + { + prevInstance->next = currentInstance->next; + return kStatus_USB_Success; + } + prevInstance = currentInstance; + currentInstance = currentInstance->next; + } + + return kStatus_USB_Success; +} + +static void USB_HostReleaseDeviceResource(usb_host_instance_t *hostInstance, usb_host_device_instance_t *deviceInstance) +{ +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + uint8_t level = 0; +#endif + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + if (deviceInstance == hostInstance->suspendedDevice) + { + hostInstance->suspendedDevice = NULL; + } +#endif + /* release device's address */ + if (deviceInstance->setAddress != 0) + { + USB_HostReleaseDeviceAddress(hostInstance, deviceInstance->setAddress); + } + else + { + if (deviceInstance->allocatedAddress != 0) + { + USB_HostReleaseDeviceAddress(hostInstance, deviceInstance->allocatedAddress); + } + } + + /* close control pipe */ + if (deviceInstance->controlPipe != NULL) + { + USB_HostCancelTransfer(hostInstance, deviceInstance->controlPipe, NULL); + if (USB_HostClosePipe(hostInstance, deviceInstance->controlPipe) != kStatus_USB_Success) + { +#ifdef HOST_ECHO + usb_echo("error when close pipe\r\n"); +#endif + } + deviceInstance->controlPipe = NULL; + } + + /* free configuration buffer */ + if (deviceInstance->configurationDesc != NULL) + { +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(deviceInstance->configurationDesc); +#else + USB_OsaMemoryFree(deviceInstance->configurationDesc); +#endif + } + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + level = deviceInstance->level; +#endif +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(deviceInstance->deviceDescriptor); +#else + USB_OsaMemoryFree(deviceInstance->deviceDescriptor); +#endif + /* free device instance buffer */ + USB_OsaMemoryFree(deviceInstance); + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + /* enable controller attach if root hub */ + if (level == 1) + { + USB_HostControlBus(hostInstance, kUSB_HostBusEnableAttach); + } +#else + /* enable controller attach */ + USB_HostControlBus(hostInstance, kUSB_HostBusEnableAttach); +#endif +} + +static usb_status_t USB_HostParseDeviceConfigurationDescriptor(usb_device_handle deviceHandle) +{ + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + uint32_t endPos; + usb_descriptor_union_t *unionDes; + usb_host_interface_t *interfaceParse = NULL; + usb_host_ep_t *epParse; + uint8_t *buffer; + + if (deviceHandle == NULL) + { + return kStatus_USB_InvalidParameter; + } + + buffer = (uint8_t *)&deviceInstance->configuration; + /* clear the previous parse result, note: end_pos means buffer index here*/ + for (endPos = 0; endPos < sizeof(usb_host_configuration_t); endPos++) + { + buffer[endPos] = 0; + } + for (endPos = 0; endPos < USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE; ++endPos) + { + deviceInstance->interfaceStatus[endPos] = 0; + } + + /* parse configuration descriptor */ + unionDes = (usb_descriptor_union_t *)deviceInstance->configurationDesc; + endPos = (uint32_t)(deviceInstance->configurationDesc + deviceInstance->configurationLen); + + if ((unionDes->common.bLength == USB_DESCRIPTOR_LENGTH_CONFIGURE) && + (unionDes->common.bDescriptorType == USB_DESCRIPTOR_TYPE_CONFIGURE)) + { + /* configuration descriptor */ + deviceInstance->configuration.configurationDesc = (usb_descriptor_configuration_t *)unionDes; + deviceInstance->configuration.configurationExtensionLength = 0; + deviceInstance->configuration.configurationExtension = NULL; + deviceInstance->configuration.interfaceCount = 0; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPos) + { + if (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) + { + if (deviceInstance->configuration.configurationExtension == NULL) + { + deviceInstance->configuration.configurationExtension = (uint8_t *)unionDes; + } + if ((unionDes->common.bDescriptorType == 0x00) || + (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + deviceInstance->configuration.configurationExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + + /* interface descriptor */ + deviceInstance->configuration.interfaceCount = 0; + while ((uint32_t)unionDes < endPos) + { + if (unionDes->common.bDescriptorType == USB_DESCRIPTOR_TYPE_INTERFACE) + { + if (unionDes->interface.bAlternateSetting == 0x00) + { + if (deviceInstance->configuration.interfaceCount >= USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE) + { +#ifdef HOST_ECHO + usb_echo( + "Unsupported Device attached\r\n too many interfaces in one configuration, please increase " + "the USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE value\n"); +#endif + return kStatus_USB_Error; + } + interfaceParse = + &deviceInstance->configuration.interfaceList[deviceInstance->configuration.interfaceCount]; + deviceInstance->configuration.interfaceCount++; + interfaceParse->alternateSettingNumber = 0; + interfaceParse->epCount = 0; + interfaceParse->interfaceDesc = &unionDes->interface; + interfaceParse->interfaceExtensionLength = 0; + interfaceParse->interfaceExtension = NULL; + interfaceParse->interfaceIndex = unionDes->interface.bInterfaceNumber; + if (unionDes->common.bLength == 0x00) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPos) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) && + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) + { + if (interfaceParse->interfaceExtension == NULL) + { + interfaceParse->interfaceExtension = (uint8_t *)unionDes; + } + if ((unionDes->common.bDescriptorType == 0x00) || + (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + interfaceParse->interfaceExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + + /* endpoint descriptor */ + if (interfaceParse->interfaceDesc->bNumEndpoints != 0) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) || + (interfaceParse->interfaceDesc->bNumEndpoints > USB_HOST_CONFIG_INTERFACE_MAX_EP)) + { +#ifdef HOST_ECHO + usb_echo("interface descriptor error\n"); +#endif + return kStatus_USB_Error; + } + for (; interfaceParse->epCount < interfaceParse->interfaceDesc->bNumEndpoints; + (interfaceParse->epCount)++) + { + if (((uint32_t)unionDes >= endPos) || + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) + { +#ifdef HOST_ECHO + usb_echo("endpoint descriptor error\n"); +#endif + return kStatus_USB_Error; + } + epParse = (usb_host_ep_t *)&interfaceParse->epList[interfaceParse->epCount]; + epParse->epDesc = (usb_descriptor_endpoint_t *)unionDes; + epParse->epExtensionLength = 0; + epParse->epExtension = NULL; + if (unionDes->common.bLength == 0x00) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPos) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) && + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE)) + { + if (epParse->epExtension == NULL) + { + epParse->epExtension = (uint8_t *)unionDes; + } + if ((unionDes->common.bDescriptorType == 0x00) || + (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + epParse->epExtensionLength += unionDes->common.bLength; + unionDes = + (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + } + } + } + else + { + if (interfaceParse == NULL) + { + return kStatus_USB_Error; /* in normal situation this cannot reach */ + } + interfaceParse->alternateSettingNumber++; + if (interfaceParse->interfaceExtension == NULL) + { + interfaceParse->interfaceExtension = (uint8_t *)unionDes; + } + if (unionDes->common.bLength == 0x00) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + interfaceParse->interfaceExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPos) + { + if (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) + { + if ((unionDes->common.bDescriptorType == 0x00) || + (unionDes->common.bLength == 0x00)) /* the descriptor data is wrong */ + { + return kStatus_USB_Error; + } + interfaceParse->interfaceExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + } + } + else + { + return kStatus_USB_Error; + } + } + } + + for (endPos = 0; endPos < deviceInstance->configuration.interfaceCount; ++endPos) + { + deviceInstance->interfaceStatus[endPos] = kStatus_interface_Attached; + } + + return kStatus_USB_Success; +} + +usb_status_t USB_HostAttachDevice(usb_host_handle hostHandle, + uint8_t speed, + uint8_t hubNumber, + uint8_t portNumber, + uint8_t level, + usb_device_handle *deviceHandle) +{ + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + usb_host_device_instance_t *newInstance; +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + usb_host_device_instance_t *currentInstance; +#endif + uint8_t address; + usb_host_pipe_init_t pipeInit; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + +/* check whether is the device attached? */ +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + currentInstance = (usb_host_device_instance_t *)hostInstance->deviceList; + while (currentInstance != NULL) + { + if ((currentInstance->hubNumber == hubNumber) && (currentInstance->portNumber == portNumber)) + { + *deviceHandle = NULL; +#ifdef HOST_ECHO + usb_echo("device has attached\r\n"); +#endif + return kStatus_USB_Busy; + } + else + { + currentInstance = currentInstance->next; + } + } +#else + if (hostInstance->deviceList != NULL) + { + *deviceHandle = NULL; + usb_echo("device has attached\r\n"); + return kStatus_USB_Busy; + } +#endif + + /* Allocate new device instance */ + newInstance = (usb_host_device_instance_t *)USB_OsaMemoryAllocate(sizeof(usb_host_device_instance_t)); + if (newInstance == NULL) + { +#ifdef HOST_ECHO + usb_echo("allocate dev instance fail\r\n"); +#endif + return kStatus_USB_AllocFail; + } + + /* new instance fields init */ + newInstance->hostHandle = hostHandle; + newInstance->speed = speed; + newInstance->stallRetries = USB_HOST_CONFIG_ENUMERATION_MAX_STALL_RETRIES; + newInstance->enumRetries = USB_HOST_CONFIG_ENUMERATION_MAX_RETRIES; + newInstance->setAddress = 0; + newInstance->deviceAttachState = kStatus_device_Attached; +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + newInstance->deviceDescriptor = + (usb_descriptor_device_t *)SDK_Malloc(sizeof(usb_descriptor_device_t) + 9, USB_CACHE_LINESIZE); +#else + newInstance->deviceDescriptor = + (usb_descriptor_device_t *)USB_OsaMemoryAllocate(sizeof(usb_descriptor_device_t) + 9); +#endif + if (newInstance->deviceDescriptor == NULL) + { +#ifdef HOST_ECHO + usb_echo("allocate newInstance->deviceDescriptor fail\r\n"); +#endif +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(newInstance->deviceDescriptor); +#else + USB_OsaMemoryFree(newInstance->deviceDescriptor); +#endif + USB_OsaMemoryFree(newInstance); + return kStatus_USB_AllocFail; + } + newInstance->enumBuffer = (uint8_t *)((uint8_t *)newInstance->deviceDescriptor + sizeof(usb_descriptor_device_t)); +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + newInstance->hubNumber = hubNumber; + newInstance->portNumber = portNumber; + newInstance->level = level; + + if ((speed != USB_SPEED_HIGH) && (level > 1)) + { + newInstance->hsHubNumber = USB_HostHubGetHsHubNumber(hostHandle, hubNumber); + newInstance->hsHubPort = USB_HostHubGetHsHubPort(hostHandle, hubNumber, portNumber); + } + else + { + newInstance->hsHubNumber = hubNumber; + newInstance->hsHubPort = portNumber; + } +#endif /* USB_HOST_CONFIG_HUB */ + + USB_HostLock(); + /* allocate address && insert to the dev list */ + address = USB_HostAllocateDeviceAddress(hostInstance); + if (address == 0) + { +#ifdef HOST_ECHO + usb_echo("allocate address fail\r\n"); +#endif + USB_HostUnlock(); +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(newInstance->deviceDescriptor); +#else + USB_OsaMemoryFree(newInstance->deviceDescriptor); +#endif + USB_OsaMemoryFree(newInstance); + return kStatus_USB_Error; + } + newInstance->allocatedAddress = address; + + newInstance->next = (usb_host_device_instance_t *)hostInstance->deviceList; + hostInstance->deviceList = newInstance; + newInstance->state = kStatus_DEV_Initial; + USB_HostUnlock(); + + /* open control pipe */ + pipeInit.devInstance = newInstance; + pipeInit.pipeType = USB_ENDPOINT_CONTROL; + pipeInit.direction = 0; + pipeInit.endpointAddress = 0; + pipeInit.interval = 0; + pipeInit.maxPacketSize = 8; + pipeInit.numberPerUframe = 0; + pipeInit.nakCount = USB_HOST_CONFIG_MAX_NAK; + if (USB_HostOpenPipe(hostHandle, &newInstance->controlPipe, &pipeInit) != kStatus_USB_Success) + { + /* don't need release resource, resource is released when detach */ + *deviceHandle = newInstance; +#if ((defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE > 0U)) + SDK_Free(newInstance->deviceDescriptor); +#else + USB_OsaMemoryFree(newInstance->deviceDescriptor); +#endif + USB_OsaMemoryFree(newInstance); + return kStatus_USB_Error; + } + + /* start enumeration */ + newInstance->state = kStatus_DEV_GetDes8; + USB_HostProcessState(newInstance); /* process enumeration state machine */ + + *deviceHandle = newInstance; + return kStatus_USB_Success; +} + +usb_status_t USB_HostDetachDevice(usb_host_handle hostHandle, uint8_t hubNumber, uint8_t portNumber) +{ + usb_host_device_instance_t *deviceInstance; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + USB_HostLock(); +/* search for device instance handle */ +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; + while (deviceInstance != NULL) + { + if ((deviceInstance->hubNumber == hubNumber) && (deviceInstance->portNumber == portNumber)) + { + break; + } + deviceInstance = deviceInstance->next; + } +#else + deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; +#endif + USB_HostUnlock(); + if (deviceInstance != NULL) + { + return USB_HostDetachDeviceInternal(hostHandle, deviceInstance); /* device instance detach */ + } + return kStatus_USB_Success; +} + +usb_status_t USB_HostDetachDeviceInternal(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + if ((hostHandle == NULL) || (deviceHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + deviceInstance->deviceAttachState = kStatus_device_Detached; /* mark the device is detached from host */ + + if (deviceInstance->state >= kStatus_DEV_Initial) /* device instance is valid */ + { + /* detach internally */ + if (deviceInstance->state < kStatus_DEV_AppUsed) /* enumeration is not done */ + { + if (deviceInstance->controlPipe != NULL) + { + USB_HostCancelTransfer(hostInstance, deviceInstance->controlPipe, NULL); + } + + /* remove device instance from host */ + USB_HostRemoveDeviceInstance(hostInstance, deviceInstance); + USB_HostReleaseDeviceResource(hostInstance, deviceInstance); + } + else /* enumeration has be done and notifed application */ + { + USB_HostNotifyDevice(deviceInstance, kUSB_HostEventDetach); /* notify application device detach */ + } + } + + return kStatus_USB_Success; +} + +uint8_t USB_HostGetDeviceAttachState(usb_device_handle deviceHandle) +{ + return deviceHandle ? ((usb_host_device_instance_t *)deviceHandle)->deviceAttachState : 0x0; +} + +usb_status_t USB_HostValidateDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_device_instance_t *searchDev; + + if (deviceHandle == NULL) + { + return kStatus_USB_InvalidParameter; + } + /* search for the device */ + searchDev = (usb_host_device_instance_t *)((usb_host_instance_t *)hostHandle)->deviceList; + while ((searchDev != NULL) && ((usb_device_handle)searchDev != deviceHandle)) + { + searchDev = searchDev->next; + } + + if (searchDev) + { + return kStatus_USB_Success; + } + return kStatus_USB_Error; +} + +static usb_status_t USB_HostControlBus(usb_host_handle hostHandle, uint8_t controlType) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, + &controlType); + + return status; +} + +usb_status_t USB_HostOpenDeviceInterface(usb_device_handle deviceHandle, usb_host_interface_handle interfaceHandle) +{ + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_instance_t *hostInstance = NULL; + uint8_t interfaceIndex; + uint8_t index = 0; + + if ((deviceHandle == NULL) || (interfaceHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; + USB_HostLock(); + /* check host_instance valid? */ + for (; index < USB_HOST_CONFIG_MAX_HOST; ++index) + { + if ((g_UsbHostInstance[index].occupied == 1) && + ((usb_host_instance_t *)(&g_UsbHostInstance[index]) == (hostInstance))) + { + break; + } + } + if (index >= USB_HOST_CONFIG_MAX_HOST) + { + USB_HostUnlock(); + return kStatus_USB_Error; + } + + /* check deviceHandle valid? */ + if (USB_HostValidateDevice(hostInstance, deviceHandle) != kStatus_USB_Success) + { + USB_HostUnlock(); + return kStatus_USB_Error; + } + + /* search interface and set the interface as opened */ + for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) + { + if (&deviceInstance->configuration.interfaceList[interfaceIndex] == interfaceHandle) + { + deviceInstance->interfaceStatus[interfaceIndex] = kStatus_interface_Opened; + break; + } + } + USB_HostUnlock(); + + return kStatus_USB_Success; +} + +usb_status_t USB_HostCloseDeviceInterface(usb_device_handle deviceHandle, usb_host_interface_handle interfaceHandle) +{ + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_instance_t *hostInstance = NULL; + uint8_t interfaceIndex; + uint8_t removeLabel = 1; + uint8_t index = 0; + + if (deviceHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; + USB_HostLock(); + /* check host_instance valid? */ + for (; index < USB_HOST_CONFIG_MAX_HOST; ++index) + { + if ((g_UsbHostInstance[index].occupied == 1) && + ((usb_host_instance_t *)(&g_UsbHostInstance[index]) == (hostInstance))) + { + break; + } + } + if (index >= USB_HOST_CONFIG_MAX_HOST) + { + USB_HostUnlock(); + return kStatus_USB_Error; + } + + /* check deviceHandle valid? */ + if (USB_HostValidateDevice(hostInstance, deviceHandle) != kStatus_USB_Success) + { + USB_HostUnlock(); + return kStatus_USB_Error; + } + + if (interfaceHandle != NULL) + { + /* search interface and set the interface as detached */ + for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) + { + if (&deviceInstance->configuration.interfaceList[interfaceIndex] == interfaceHandle) + { + deviceInstance->interfaceStatus[interfaceIndex] = kStatus_interface_Detached; + break; + } + } + } + + if (deviceInstance->deviceAttachState == kStatus_device_Detached) /* device is removed from host */ + { + removeLabel = 1; + /* check all the interfaces of the device are not opened */ + for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; ++interfaceIndex) + { + if (deviceInstance->interfaceStatus[interfaceIndex] == kStatus_interface_Opened) + { + removeLabel = 0; + break; + } + } + if (removeLabel == 1) + { + /* remove device instance from host */ + USB_HostRemoveDeviceInstance(hostInstance, deviceInstance); + } + USB_HostUnlock(); + + if (removeLabel == 1) + { + USB_HostReleaseDeviceResource((usb_host_instance_t *)deviceInstance->hostHandle, + deviceInstance); /* release device resource */ + } + } + else + { + USB_HostUnlock(); + } + + return kStatus_USB_Success; +} + +usb_status_t USB_HostRemoveDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + uint8_t interfaceIndex = 0; +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + uint8_t level = 0; + uint8_t devHubNo; + uint8_t devPortNo; +#endif + + if ((hostHandle == NULL) || (deviceHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + if (deviceInstance->hostHandle != hostHandle) + { + return kStatus_USB_InvalidParameter; + } + + if (USB_HostValidateDevice(hostInstance, deviceInstance) == kStatus_USB_Success) /* device is valid */ + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + devHubNo = deviceInstance->hubNumber; + devPortNo = deviceInstance->portNumber; + level = deviceInstance->level; +#endif + + deviceInstance->deviceAttachState = kStatus_device_Detached; + if (deviceInstance->state >= kStatus_DEV_Initial) /* device is valid */ + { + if (deviceInstance->state < kStatus_DEV_AppUsed) /* enumeraion is not done or application don't use */ + { + /* detach internally */ + USB_HostDetachDeviceInternal(hostHandle, deviceHandle); + } + else /* application use the device */ + { + for (interfaceIndex = 0; interfaceIndex < deviceInstance->configuration.interfaceCount; + ++interfaceIndex) + { + if (deviceInstance->interfaceStatus[interfaceIndex] == kStatus_interface_Opened) + { +#ifdef HOST_ECHO + usb_echo("error: there is class instance that is not deinited\r\n"); +#endif + break; + } + } + /* remove device instance from host */ + USB_HostRemoveDeviceInstance(hostInstance, deviceInstance); + USB_HostReleaseDeviceResource(hostInstance, deviceInstance); /* release resource */ + } + } + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + if (level == 1) + { + USB_HostControlBus(hostHandle, kUSB_HostBusReset); /* reset controller port */ + USB_HostControlBus(hostHandle, kUSB_HostBusRestart); /* restart controller port */ + } + else + { + USB_HostHubRemovePort(hostHandle, devHubNo, devPortNo); /* reset hub port */ + } +#else + USB_HostControlBus(hostHandle, kUSB_HostBusReset); /* reset controller port */ + USB_HostControlBus(hostHandle, kUSB_HostBusRestart); /* restart controller port */ +#endif /* USB_HOST_CONFIG_HUB */ + } + + return kStatus_USB_Success; +} diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.h b/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.h new file mode 100644 index 0000000000000000000000000000000000000000..422e876a1229f15a87ddb896d15630cd06a0860f --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_devices.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_HOST_DEV_MNG_H_ +#define _USB_HOST_DEV_MNG_H_ + +#include "usb_host.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @addtogroup usb_host_drv + * @{ + */ +/*! @brief States of device instances enumeration */ +typedef enum _usb_host_device_enumeration_status +{ + kStatus_DEV_Notinit = 0, /*!< Device is invalid */ + kStatus_DEV_Initial, /*!< Device has been processed by host driver */ + kStatus_DEV_GetDes8, /*!< Enumeration process: get 8 bytes' device descriptor */ + kStatus_DEV_SetAddress, /*!< Enumeration process: set device address */ + kStatus_DEV_GetDes, /*!< Enumeration process: get device descriptor */ + kStatus_DEV_GetCfg9, /*!< Enumeration process: get 9 bytes' configuration descriptor */ + kStatus_DEV_GetCfg, /*!< Enumeration process: get configuration descriptor */ + kStatus_DEV_SetCfg, /*!< Enumeration process: set configuration */ + kStatus_DEV_EnumDone, /*!< Enumeration is done */ + kStatus_DEV_AppUsed, /*!< This device has been used by application */ +} usb_host_device_enumeration_status_t; + +/*! @brief States of device's interface */ +typedef enum _usb_host_interface_state +{ + kStatus_interface_Attached = 1, /*!< Interface's default status */ + kStatus_interface_Opened, /*!< Interface is used by application */ + kStatus_interface_Detached, /*!< Interface is not used by application */ +} usb_host_interface_state_t; + +/*! @brief States of device */ +typedef enum _usb_host_device_state +{ + kStatus_device_Detached = 0, /*!< Device is used by application */ + kStatus_device_Attached, /*!< Device's default status */ +} usb_host_device_state_t; + +/*! @brief Device instance */ +typedef struct _usb_host_device_instance +{ + struct _usb_host_device_instance *next; /*!< Next device, or NULL */ + usb_host_handle hostHandle; /*!< Host handle */ + usb_host_configuration_t configuration; /*!< Parsed configuration information for the device */ + usb_descriptor_device_t *deviceDescriptor; /*!< Standard device descriptor */ + usb_host_pipe_handle controlPipe; /*!< Device's control pipe */ + uint8_t *configurationDesc; /*!< Configuration descriptor pointer */ + uint16_t configurationLen; /*!< Configuration descriptor length */ + uint16_t configurationValue; /*!< Configuration index */ + uint8_t interfaceStatus[USB_HOST_CONFIG_CONFIGURATION_MAX_INTERFACE]; /*!< Interfaces' status, please reference to + #usb_host_interface_state_t */ + uint8_t *enumBuffer; /*!< Buffer for enumeration */ + uint8_t state; /*!< Device state for enumeration */ + uint8_t enumRetries; /*!< Re-enumeration when error in control transfer */ + uint8_t stallRetries; /*!< Re-transfer when stall */ + uint8_t speed; /*!< Device speed */ + uint8_t allocatedAddress; /*!< Temporary address for the device. When set address request succeeds, setAddress is + a value, 1 - 127 */ + uint8_t setAddress; /*!< The address has been set to the device successfully, 1 - 127 */ + uint8_t deviceAttachState; /*!< See the usb_host_device_state_t */ +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + /* hub related */ + uint8_t hubNumber; /*!< Device's first connected hub address (root hub = 0) */ + uint8_t portNumber; /*!< Device's first connected hub's port no (1 - 8) */ + uint8_t hsHubNumber; /*!< Device's first connected high-speed hub's address (1 - 8) */ + uint8_t hsHubPort; /*!< Device's first connected high-speed hub's port no (1 - 8) */ + uint8_t level; /*!< Device's level (root device = 0) */ +#endif +} usb_host_device_instance_t; + +typedef struct _usb_host_enum_process_entry +{ + uint8_t successState; /*!< When the last step is successful, the next state value */ + uint8_t retryState; /*!< When the last step need retry, the next state value */ + usb_status_t (*process)(usb_host_device_instance_t *deviceInstance); /*!< When the last step transfer is done, the + function is used to process the transfer + data */ +} usb_host_enum_process_entry_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Calls this function when device attach. + * + * @param hostHandle Host instance handle. + * @param speed Device speed. + * @param hubNumber Device hub no. root device's hub no. is 0. + * @param portNumber Device port no. root device's port no. is 0. + * @param level Device level. root device's level is 1. + * @param deviceHandle Return device handle. + * + * @return kStatus_USB_Success or error codes. + */ +extern usb_status_t USB_HostAttachDevice(usb_host_handle hostHandle, + uint8_t speed, + uint8_t hubNumber, + uint8_t portNumber, + uint8_t level, + usb_device_handle *deviceHandle); + +/*! + * @brief Call this function when device detaches. + * + * @param hostHandle Host instance handle. + * @param hubNumber Device hub no. root device's hub no. is 0. + * @param portNumber Device port no. root device's port no. is 0. + * + * @return kStatus_USB_Success or error codes. + */ +extern usb_status_t USB_HostDetachDevice(usb_host_handle hostHandle, uint8_t hubNumber, uint8_t portNumber); + +/*! + * @brief Call this function when device detaches. + * + * @param hostHandle Host instance handle. + * @param deviceHandle Device handle. + * + * @return kStatus_USB_Success or error codes. + */ +extern usb_status_t USB_HostDetachDeviceInternal(usb_host_handle hostHandle, usb_device_handle deviceHandle); + +/*! + * @brief Gets the device attach/detach state. + * + * @param deviceHandle Device handle. + * + * @return 0x01 - attached; 0x00 - detached. + */ +extern uint8_t USB_HostGetDeviceAttachState(usb_device_handle deviceHandle); + +/*! + * @brief Determine whether the device is attached. + * + * @param hostHandle Host instance pointer. + * @param deviceHandle Device handle. + * + * @return kStatus_USB_Success or error codes. + */ +extern usb_status_t USB_HostValidateDevice(usb_host_handle hostHandle, usb_device_handle deviceHandle); + +/*! @}*/ +#endif /* _USB_HOST_DEV_MNG_H_ */ diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.c b/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.c new file mode 100644 index 0000000000000000000000000000000000000000..8a31514b3ab7e42f90f93b5f293fb7fbce72e2b0 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.c @@ -0,0 +1,4747 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI > 0U)) +#include "usb_host.h" +#include "usb_host_hci.h" +#include "usb_host_devices.h" +#include "fsl_device_registers.h" +#include "usb_host_ehci.h" +#include "usb_phy.h" +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) +#include "usb_host.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM > 0U) + +#error The SOC does not suppoort dedicated RAM case. + +#endif + +#define USB_HOST_EHCI_BANDWIDTH_DELAY (3500U) +#define USB_HOST_EHCI_BANDWIDTH_HUB_LS_SETUP (333U) +#define USB_HOST_EHCI_BANDWIDTH_FRAME_TOTOAL_TIME (900U) + +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) +#define USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH (18U) +#define USB_HOST_EHCI_PORTSC_PTC_J_STATE (0x01U) +#define USB_HOST_EHCI_PORTSC_PTC_K_STATE (0x02U) +#define USB_HOST_EHCI_PORTSC_PTC_SE0_NAK (0x03U) +#define USB_HOST_EHCI_PORTSC_PTC_PACKET (0x04U) +#define USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_HS (0x05U) +#define USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_FS (0x06U) +#define USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_LS (0x07U) +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief compute data bandwidth time. + * + * @param speed data speed. + * @param pipeType data type. + * @param direction data direction. + * @param dataLength data length. + * + *@return time value. + */ +static uint32_t USB_HostBandwidthComputeTime(uint8_t speed, uint8_t pipeType, uint8_t direction, uint32_t dataLength); + +/*! + * @brief compute current allocated bandwidth when ehci work as full-speed or low-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param frameIndex frame index. + * @param frameBandwidths return frame bandwidth data. + */ +static void USB_HostBandwidthFslsHostComputeCurrent(usb_host_ehci_instance_t *ehciInstance, + uint16_t frameIndex, + uint16_t *frameBandwidth); + +/*! + * @brief compute current hub's allocated FS/LS bandwidth when ehci work as hi-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param hubNumber hub address. + * @param frameIndex frame index. + * @param frameBandwidths return frame bandwidth data. + */ +static void USB_HostBandwidthHsHostComputeCurrentFsls(usb_host_ehci_instance_t *ehciInstance, + uint32_t hubNumber, + uint16_t frameIndex, + uint8_t frameBandwidths[8]); + +/*! + * @brief compute current allocated HS bandwidth when ehci work as hi-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param frameIndex frame index. + * @param frameBandwidths return frame bandwidth data. + */ +static void USB_HostBandwidthHsHostComputeCurrentHsAll(usb_host_ehci_instance_t *ehciInstance, + uint16_t frameIndex, + uint8_t frameBandwidths[8]); + +/*! + * @brief allocate HS bandwidth when host work as high-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param uframeInterval micro-frame interval. + * @param timeData time for allocating. + * @param uframe_index_out return start uframe index. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostBandwidthHsHostAllocateHsCommon(usb_host_ehci_instance_t *ehciInstance, + uint16_t uframeInterval, + uint16_t timeData, + uint16_t *uframeIndexOut); + +/*! + * @brief allocate HS interrupt bandwidth when host work as high-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostBandwidthHsHostAllocateInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief allocate bandwidth when host work as full-speed or low-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostBandwidthFslsHostAllocate(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief get the 2 power value of uint8_t. + * + * @param value input uint8_t value. + */ +static uint8_t USB_HostEhciGet2PowerValue(uint8_t value); + +/*! + * @brief memory zero. + * + * @param buffer buffer pointer. + * @param length buffer length. + */ +static void USB_HostEhciZeroMem(uint32_t *buffer, uint32_t length); + +/*! + * @brief host ehci delay. + * + * @param ehciIpBase ehci ip base address. + * @param ms millisecond. + */ +static void USB_HostEhciDelay(USBHS_Type *ehciIpBase, uint32_t ms); + +/*! + * @brief host ehci start async schedule. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief host ehci stop async schedule. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciStopAsync(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief host ehci start periodic schedule. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief host ehci stop periodic schedule. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciStopPeriodic(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief initialize the qtd for one transfer. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * @param transfer transfer information. + * + *@return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer); + +/*! + * @brief release the qtd list. + * + * @param ehciInstance ehci instance pointer. + * @param ehciQtdStart qtd list start pointer. + * @param ehciQtdEnd qtd list end pointer. + * + *@return the transfer's length. + */ +static uint32_t USB_HostEhciQtdListRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_qtd_t *ehciQtdStart, + usb_host_ehci_qtd_t *ehciQtdEnd); + +/*! + * @brief de-initialize qh's linking qtd list. + * 1. remove qtd from qh; 2. remove transfer from qh; 3. release qtd; 4. transfer callback. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe. + * + *@return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciQhQtdListDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief de-initialize transfer's linking qtd list. + * 1. stop this qh schedule; 2. remove qtd from qh; 3. remove transfer from qh; 4. release qtd; 5. transfer callback; 6. + *start this qh schedule. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * @param transfer transfer information. + * + *@return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciTransferQtdListDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer); + +/*! + * @brief initialize QH when opening one control, bulk or interrupt pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciQhInit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief de-initialize QH when closing one control, bulk or interrupt pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciQhDeinit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief add qh to one frame entry. + * + * @param ehciInstance ehci instance pointer. + * @param entryPointerValue entry pointer value. + * @param framePos frame index. + * @param uframeInterval micro-frame interval. + */ +static void USB_HostEhciAddQhToFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t entryPointerValue, + uint16_t framePos, + uint16_t uframeInterval); + +/*! + * @brief remove entry from frame list. + * + * @param ehciInstance ehci instance pointer. + * @param entryPointerValue entry pointer value. + * @param framePos frame index. + */ +static void USB_HostEhciRemoveFromFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t entryPointerValue, + uint16_t framePos); + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) +/*! + * @brief add sitd array to the frame list. + * + * @param ehciInstance ehci instance pointer. + * @param entryPointerValue entry pointer value. + * @param startEntryPointer sitd entry pointer. + */ +static void USB_HostEhciLinkSitd(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + void *startEntryPointer); + +/*! + * @brief initialize sitd array for one transfer. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * @param transfer transfer information. + */ +static usb_status_t USB_HostEhciSitdArrayInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer); + +/*! + * @brief release sitd list. + * + * @param ehciInstance ehci instance pointer. + * @param startSitdPointer start sitd pointer. + * @param endSitdPointer end sitd pointer. + * + * @return transfer's result length. + */ +static uint32_t USB_HostEhciSitdArrayRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_sitd_t *startSitdPointer, + usb_host_ehci_sitd_t *endSitdPointer); + +/*! + * @brief de-initialize sitd list. + * 1. remove transfer; 2. remove sitd from frame list and release sitd; 3. transfer callback + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciSitdArrayDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); +#endif /* USB_HOST_CONFIG_EHCI_MAX_SITD */ + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) +/*! + * @brief compute the frame index when inserting itd. + * + * @param ehciInstance ehci instance pointer. + * @param lastLinkUframe last inserted micro-frame. + * @param startUframe start micro-frame. + * @param uframeInterval micro-frame interval. + * + * @return frame index + */ +static uint32_t USB_HostEhciGetItdLinkFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t lastLinkUframe, + uint16_t startUframe, + uint16_t uframeInterval); + +/*! + * @brief initialize itd list for one transfer. + * 1. initialize itd list; 2. insert itd to frame list. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * @param transfer transfer information. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciItdArrayInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer); + +/*! + * @brief release itd list. + * + * @param ehciInstance ehci instance pointer. + * @param startItdPointer start itd pointer. + * @param endItdPointer end itd pointer. + * + * @return transfer's result length. + */ +static uint32_t USB_HostEhciItdArrayRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_itd_t *startItdPointer, + usb_host_ehci_itd_t *endItdPointer); + +/*! + * @brief de-initialize itd list. + * 1. remove transfer; 2. remove itd from frame list and release itd; 3. transfer callback + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciItdArrayDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); +#endif /* USB_HOST_CONFIG_EHCI_MAX_ITD */ + +/*! + * @brief open control or bulk pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciOpenControlBulk(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief close control or bulk pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciCloseControlBulk(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief open interrupt pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciOpenInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief close interrupt pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciCloseInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) +/*! + * @brief open iso pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciOpenIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief close iso pipe. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciCloseIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer); + +/*! + * @brief allocate HS iso bandwidth when host work as high-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostBandwidthHsHostAllocateIso(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer); + +#endif + +/*! + * @brief reset ehci ip. + * + * @param ehciInstance ehci instance pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciResetIP(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief start ehci ip. + * + * @param ehciInstance ehci instance pointer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciStartIP(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief cancel pipe's transfers. + * + * @param ehciInstance ehci instance pointer. + * @param ehciPipePointer ehci pipe pointer. + * @param transfer the canceling transfer. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciCancelPipe(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer); + +/*! + * @brief control ehci bus. + * + * @param ehciInstance ehci instance pointer. + * @param bus_control control code. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstance, uint8_t busControl); + +/*! + * @brief ehci transaction done process function. + * + * @param ehciInstance ehci instance pointer. + */ +void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief ehci port change interrupt process function. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief ehci timer0 interrupt process function. + * cancel control/bulk transfer that time out. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance); + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) +/*! + * @brief ehci timer1 interrupt process function. + * cancel control/bulk transfer that time out. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciTimer1(usb_host_ehci_instance_t *ehciInstance); +#endif + +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) +/*! + * @brief suspend bus. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciSuspendBus(usb_host_ehci_instance_t *ehciInstance); + +/*! + * @brief resume bus. + * + * @param ehciInstance ehci instance pointer. + */ +static void USB_HostEhciResumeBus(usb_host_ehci_instance_t *ehciInstance); + +extern usb_status_t USB_HostStandardSetGetDescriptor(usb_host_device_instance_t *deviceInstance, + usb_host_transfer_t *transfer, + void *param); +#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* EHCI controller driver instances. */ +#if (USB_HOST_CONFIG_EHCI == 1U) +USB_RAM_ADDRESS_ALIGNMENT(4096) +USB_CONTROLLER_DATA static uint8_t s_UsbHostEhciFrameList1[USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 4]; + +#define USB_HOST_EHCI_FRAME_LIST_ARRAY \ + { \ + &s_UsbHostEhciFrameList1[0] \ + } + +USB_RAM_ADDRESS_ALIGNMENT(64) USB_CONTROLLER_DATA static usb_host_ehci_data_t s_UsbHostEhciData1; +#define USB_HOST_EHCI_DATA_ARRAY \ + { \ + &s_UsbHostEhciData1 \ + } +#elif(USB_HOST_CONFIG_EHCI == 2U) +USB_RAM_ADDRESS_ALIGNMENT(4096) +USB_CONTROLLER_DATA static uint8_t s_UsbHostEhciFrameList1[USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 4]; +USB_RAM_ADDRESS_ALIGNMENT(4096) +USB_CONTROLLER_DATA static uint8_t s_UsbHostEhciFrameList2[USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 4]; +#define USB_HOST_EHCI_FRAME_LIST_ARRAY \ + { \ + &s_UsbHostEhciFrameList1[0], &s_UsbHostEhciFrameList2[0] \ + } + +USB_RAM_ADDRESS_ALIGNMENT(64) USB_CONTROLLER_DATA static usb_host_ehci_data_t s_UsbHostEhciData1; +USB_RAM_ADDRESS_ALIGNMENT(64) USB_CONTROLLER_DATA static usb_host_ehci_data_t s_UsbHostEhciData2; +#define USB_HOST_EHCI_DATA_ARRAY \ + { \ + &s_UsbHostEhciData1, &s_UsbHostEhciData2 \ + } +#else +#error "Please increase the instance count." +#endif + +static uint8_t s_SlotMaxBandwidth[8] = {125, 125, 125, 125, 125, 125, 50, 0}; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! +* @brief EHCI NC get USB NC bass address. +* +* This function is used to get USB NC bass address. +* +* @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. +* +* @retval USB NC bass address. +*/ +#if (defined(USB_HOST_CONFIG_LOW_POWER_MODE) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) +void *USB_EhciNCGetBase(uint8_t controllerId) +{ + void *usbNCBase = NULL; +#if ((defined FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + uint32_t instance; + uint32_t newinstance = 0; + uint32_t usbnc_base_temp[] = USBNC_BASE_ADDRS; + uint32_t usbnc_base[] = USBNC_BASE_ADDRS; + + if (controllerId < kUSB_ControllerEhci0) + { + return NULL; + } + + controllerId = controllerId - kUSB_ControllerEhci0; + + for (instance = 0; instance < (sizeof(usbnc_base_temp) / sizeof(usbnc_base_temp[0])); instance++) + { + if (usbnc_base_temp[instance]) + { + usbnc_base[newinstance++] = usbnc_base_temp[instance]; + } + } + if (controllerId > newinstance) + { + return NULL; + } + + usbNCBase = (void *)usbnc_base[controllerId]; +#endif + return usbNCBase; +} +#endif +#endif + +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) + +usb_status_t USB_HostEhciTestSetMode(usb_host_ehci_instance_t *ehciInstance, uint32_t testMode) +{ + uint32_t ehciPortSC; + + ehciPortSC = ehciInstance->ehciIpBase->PORTSC1; + ehciPortSC &= ~((uint32_t)USBHS_PORTSC1_PTC_MASK); /* clear test mode bits */ + ehciPortSC |= (testMode << USBHS_PORTSC1_PTC_SHIFT); /* set test mode bits */ + ehciInstance->ehciIpBase->PORTSC1 = ehciPortSC; + return kStatus_USB_Success; +} + +static void USB_HostEhciTestSuspendResume(usb_host_ehci_instance_t *ehciInstance) +{ + uint8_t timeCount; + timeCount = 15; /* 15s */ + while (timeCount--) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); + } + USB_HostEhciSuspendBus(ehciInstance); + timeCount = 15; /* 15s */ + while (timeCount--) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); + } + + USB_HostEhciResumeBus(ehciInstance); +} + +static void USB_HostEhciTestCallback(void *param, usb_host_transfer_t *transfer, usb_status_t status) +{ + USB_HostFreeTransfer(param, transfer); +} + +static void USB_HostEhciTestSingleStepGetDeviceDesc(usb_host_ehci_instance_t *ehciInstance, + usb_device_handle deviceHandle) +{ + usb_host_process_descriptor_param_t getDescriptorParam; + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_transfer_t *transfer; + uint8_t timeCount; + + /* disable periodic shedule */ + USB_HostEhciStopPeriodic(ehciInstance); + + timeCount = 15; /* 15s */ + while (timeCount--) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); + } + + /* malloc one transfer */ + if (USB_HostMallocTransfer(ehciInstance->hostHandle, &transfer) != kStatus_USB_Success) + { +#ifdef HOST_ECHO + usb_echo("allocate transfer error\r\n"); +#endif + return; + } + + getDescriptorParam.descriptorLength = sizeof(usb_descriptor_device_t); + getDescriptorParam.descriptorLength = 18; + getDescriptorParam.descriptorBuffer = (uint8_t *)&deviceInstance->deviceDescriptor; + getDescriptorParam.descriptorType = USB_DESCRIPTOR_TYPE_DEVICE; + getDescriptorParam.descriptorIndex = 0; + getDescriptorParam.languageId = 0; + transfer->callbackFn = USB_HostEhciTestCallback; + transfer->callbackParam = ehciInstance->hostHandle; + transfer->setupPacket->bmRequestType = USB_REQUEST_TYPE_DIR_IN; + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; + transfer->setupPacket->wIndex = 0; + transfer->setupPacket->wLength = 0; + transfer->setupPacket->wValue = 0; + USB_HostStandardSetGetDescriptor(deviceInstance, transfer, &getDescriptorParam); +} + +static usb_status_t USB_HostEhciSingleStepQtdListInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer, + uint8_t setupPhase) +{ + volatile usb_host_ehci_qh_t *vltQhPointer; + usb_host_ehci_qtd_t *qtdPointer = NULL; + volatile uint32_t *entryPointer; + uint32_t qtdNumber; + uint32_t dataLength; + uint32_t dataAddress; + uint8_t index; + + /* compute the qtd number */ + qtdNumber = 1; + + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + /* get qtd list */ + USB_HostEhciLock(); + if (qtdNumber <= ehciInstance->ehciQtdNumber) + { + ehciInstance->ehciQtdNumber -= qtdNumber; + qtdPointer = NULL; + do + { + if (qtdPointer != NULL) + { + qtdPointer->nextQtdPointer = (uint32_t)ehciInstance->ehciQtdHead; + } + qtdPointer = ehciInstance->ehciQtdHead; + ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)qtdPointer->nextQtdPointer; + qtdPointer->nextQtdPointer = 0; + } while (--qtdNumber); + } + else + { + USB_HostEhciUnlock(); + return kStatus_USB_Error; + } + USB_HostEhciUnlock(); + + /* int qTD */ + if (setupPhase == 1) /* setup transaction qtd init */ + { + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: need set; ioc: 0; C_Page: 0; PID Code: SETUP; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + qtdPointer->transferResults[0] = + ((0x00000000 << EHCI_HOST_QTD_DT_SHIFT) | (8 << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + (EHCI_HOST_PID_SETUP << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + dataAddress = (uint32_t)(transfer->setupPacket); + qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ + /* set buffer pointer no matter data length */ + for (index = 0; index < 4; ++index) + { + qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000); + } + } + else if (setupPhase == 2) /* data transaction qtd */ + { + dataLength = transfer->transferLength; + if (dataLength != 0) + { + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: need set; ioc: 0; C_Page: 0; PID Code: IN/OUT; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (dataLength << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + + dataAddress = (uint32_t)(transfer->transferBuffer); + qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ + /* set buffer pointer no matter data length */ + for (index = 0; index < 4; ++index) + { + qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000); + } + } + } + else if (setupPhase == 3) + { + /* status transaction qtd */ + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: dont care; ioc: 1; C_Page: 0; PID Code: IN/OUT; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | + (EHCI_HOST_QTD_IOC_MASK) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + + qtdPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; + } + qtdPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; + qtdPointer->transferResults[0] |= EHCI_HOST_QTD_IOC_MASK; /* set IOC */ + + /* save qtd to transfer */ + transfer->union1.unitHead = (uint32_t)qtdPointer; + transfer->union2.unitTail = (uint32_t)qtdPointer; + /* link transfer to qh */ + transfer->next = NULL; + if (vltQhPointer->ehciTransferHead == NULL) + { + transfer->next = NULL; + vltQhPointer->ehciTransferHead = vltQhPointer->ehciTransferTail = transfer; + } + else + { + transfer->next = NULL; + vltQhPointer->ehciTransferTail->next = transfer; + vltQhPointer->ehciTransferTail = transfer; + } + + USB_HostEhciLock(); + /* link qtd to qh (link to end) */ + entryPointer = &(vltQhPointer->nextQtdPointer); + dataAddress = *entryPointer; /* dataAddress variable means entry value here */ + while ((dataAddress) && (!(dataAddress & EHCI_HOST_T_INVALID_VALUE))) + { + entryPointer = (volatile uint32_t *)dataAddress; + dataAddress = *entryPointer; + } + *entryPointer = (uint32_t)qtdPointer; + USB_HostEhciUnlock(); + USB_HostEhciStartAsync(ehciInstance); + + return kStatus_USB_Success; +} + +static void USB_HostEhciTestSingleStepGetDeviceDescData(usb_host_ehci_instance_t *ehciInstance, + usb_device_handle deviceHandle) +{ + static uint8_t buffer[USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH]; + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_transfer_t *transfer; + uint8_t timeCount; + + USB_HostEhciStopPeriodic(ehciInstance); + + if (USB_HostMallocTransfer(ehciInstance->hostHandle, &transfer) != kStatus_USB_Success) + { + return; + } + transfer->callbackFn = USB_HostEhciTestCallback; + transfer->callbackParam = ehciInstance->hostHandle; + transfer->setupPacket->bmRequestType = USB_REQUEST_TYPE_DIR_IN; + transfer->setupPacket->bRequest = USB_REQUEST_STANDARD_GET_DESCRIPTOR; + transfer->setupPacket->wLength = USB_SHORT_TO_LITTLE_ENDIAN(USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH); + transfer->setupPacket->wValue = USB_SHORT_TO_LITTLE_ENDIAN((uint16_t)((uint16_t)USB_DESCRIPTOR_TYPE_DEVICE << 8)); + transfer->setupPacket->wIndex = 0; + USB_HostEhciSingleStepQtdListInit(ehciInstance, (usb_host_ehci_pipe_t *)(deviceInstance->controlPipe), transfer, 1); + + timeCount = 15; /* 15s */ + while (timeCount--) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); + } + + if (USB_HostMallocTransfer(ehciInstance->hostHandle, &transfer) != kStatus_USB_Success) + { + return; + } + transfer->callbackFn = USB_HostEhciTestCallback; + transfer->callbackParam = ehciInstance->hostHandle; + transfer->transferBuffer = buffer; + transfer->transferLength = USB_HOST_EHCI_TEST_DESCRIPTOR_LENGTH; + USB_HostEhciSingleStepQtdListInit(ehciInstance, (usb_host_ehci_pipe_t *)(deviceInstance->controlPipe), transfer, 2); + + if (USB_HostMallocTransfer(ehciInstance->hostHandle, &transfer) != kStatus_USB_Success) + { + return; + } + transfer->callbackFn = USB_HostEhciTestCallback; + transfer->callbackParam = ehciInstance->hostHandle; + transfer->transferBuffer = NULL; + transfer->transferLength = 0; + USB_HostEhciSingleStepQtdListInit(ehciInstance, (usb_host_ehci_pipe_t *)(deviceInstance->controlPipe), transfer, 3); + + timeCount = 15; /* 15s */ + while (timeCount--) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1000U); + } + + usb_echo("test_single_step_get_dev_desc_data finished\r\n"); + + return; +} + +void USB_HostEhciTestModeInit(usb_device_handle deviceHandle) +{ + uint32_t productId; + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_ehci_instance_t *ehciInstance = + (usb_host_ehci_instance_t *)(((usb_host_instance_t *)(deviceInstance->hostHandle))->controllerHandle); + + USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetDevicePID, &productId); + + usb_echo("usb host ehci test mode init product id:0x%x\r\n", productId); + + switch (productId) + { + case 0x0101U: + USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_SE0_NAK); + break; + case 0x0102U: + USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_J_STATE); + break; + case 0x0103U: + USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_K_STATE); + break; + case 0x0104U: + USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_PACKET); + break; + case 0x0105U: + usb_echo("set test mode FORCE_ENALBE_HS\r\n"); + USB_HostEhciTestSetMode(ehciInstance, USB_HOST_EHCI_PORTSC_PTC_FORCE_ENABLE_HS); + break; + case 0x0106U: + USB_HostEhciTestSuspendResume(ehciInstance); + break; + case 0x0107U: + usb_echo("start test SINGLE_STEP_GET_DEV_DESC\r\n"); + USB_HostEhciTestSingleStepGetDeviceDesc(ehciInstance, deviceHandle); + break; + case 0x0108U: + usb_echo("start test SINGLE_STEP_GET_DEV_DESC_DATA\r\n"); + USB_HostEhciTestSingleStepGetDeviceDescData(ehciInstance, deviceHandle); + break; + default: + break; + } + + return; +} + +static void USB_HostEhciSuspendBus(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t ehciPortSC; + + USB_HostEhciLock(); + ehciPortSC = ehciInstance->ehciIpBase->PORTSC1; + if (ehciPortSC & USBHS_PORTSC1_PE_MASK) + { + ehciPortSC = ehciInstance->ehciIpBase->PORTSC1; + ehciPortSC &= (uint32_t)(~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (ehciPortSC | USBHS_PORTSC1_SUSP_MASK); + } + USB_HostEhciUnlock(); +} + +static void USB_HostEhciResumeBus(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t ehciPortSC; + + USB_HostEhciLock(); + /* Resume port */ + ehciPortSC = ehciInstance->ehciIpBase->PORTSC1; + if (ehciPortSC & USBHS_PORTSC1_PE_MASK) + { + ehciPortSC &= (uint32_t)(~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (ehciPortSC | USBHS_PORTSC1_FPR_MASK); + } + USB_HostEhciUnlock(); +} +#endif + +static uint32_t USB_HostBandwidthComputeTime(uint8_t speed, uint8_t pipeType, uint8_t direction, uint32_t dataLength) +{ + uint32_t result = (3167 + ((1000 * dataLength) * 7U * 8U / 6U)) / 1000; + + if (pipeType == USB_ENDPOINT_ISOCHRONOUS) /* iso */ + { + if (speed == USB_SPEED_HIGH) + { + result = 38 * 8 * 2083 + 2083 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + else if (speed == USB_SPEED_FULL) + { + if (direction == USB_IN) + { + result = 7268000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + else + { + result = 6265000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + } + else + { + } + } + else /* interrupt */ + { + if (speed == USB_SPEED_HIGH) + { + result = 55 * 8 * 2083 + 2083 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + else if (speed == USB_SPEED_FULL) + { + result = 9107000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + else if (speed == USB_SPEED_LOW) + { + if (direction == USB_IN) + { + result = 64060000 + 2000 * USB_HOST_EHCI_BANDWIDTH_HUB_LS_SETUP + 676670 * result + + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + else + { + result = 6265000 + 83540 * result + USB_HOST_EHCI_BANDWIDTH_DELAY; + } + } + else + { + } + } + + result /= 1000000; + if (result == 0) + { + result = 1; + } + + return result; +} + +static void USB_HostBandwidthFslsHostComputeCurrent(usb_host_ehci_instance_t *ehciInstance, + uint16_t frameIndex, + uint16_t *frameBandwidth) +{ + usb_host_ehci_pipe_t *ehciPipePointer; + + /* clear the bandwidth */ + *frameBandwidth = 0; + + ehciPipePointer = ehciInstance->ehciRunningPipeList; + while (ehciPipePointer != NULL) + { + /* only compute iso and interrupt pipe */ + if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) || + (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT)) + { + /* does pipe allocate bandwidth in frameIndex frame? note: interval is power of 2. */ + if ((frameIndex >= ehciPipePointer->startFrame) && + (!((uint32_t)(frameIndex - ehciPipePointer->startFrame) & + (uint32_t)(ehciPipePointer->pipeCommon.interval - 1)))) + { + *frameBandwidth += ehciPipePointer->dataTime; + } + } + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } +} + +static void USB_HostBandwidthHsHostComputeCurrentFsls(usb_host_ehci_instance_t *ehciInstance, + uint32_t hubNumber, + uint16_t frameIndex, + uint8_t frameBandwidths[8]) +{ + usb_host_ehci_pipe_t *ehciPipePointer; + uint8_t index; + uint32_t deviceInfo; + + for (index = 0; index < 8; ++index) + { + frameBandwidths[index] = 0; + } + + ehciPipePointer = ehciInstance->ehciRunningPipeList; + while (ehciPipePointer != NULL) + { + /* only compute iso and interrupt pipe */ + if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) || + (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT)) + { + /* compute FS/LS bandwidth that blong to same high-speed hub, because FS/LS bandwidth is allocated from + * first parent high-speed hub */ + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, + kUSB_HostGetDeviceHSHubNumber, &deviceInfo); + if (deviceInfo != hubNumber) + { + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + continue; + } + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &deviceInfo); + if (deviceInfo == USB_SPEED_HIGH) + { + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + continue; + } + + /* does pipe allocate bandwidth in frameIndex frame? note: interval is power of 2. */ + if ((frameIndex >= ehciPipePointer->startFrame) && + (!((uint32_t)(frameIndex - ehciPipePointer->startFrame) & + (uint32_t)(ehciPipePointer->pipeCommon.interval - 1)))) + { + if (ehciPipePointer->pipeCommon.pipeType == + USB_ENDPOINT_ISOCHRONOUS) /* iso bandwidth is allocated once */ + { + frameBandwidths[ehciPipePointer->startUframe + 1] += ehciPipePointer->dataTime; + } + else /* iso bandwidth is allocated three times */ + { + frameBandwidths[ehciPipePointer->startUframe + 1] += ehciPipePointer->dataTime; + frameBandwidths[ehciPipePointer->startUframe + 2] += ehciPipePointer->dataTime; + frameBandwidths[ehciPipePointer->startUframe + 3] += ehciPipePointer->dataTime; + } + } + } + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } + + for (index = 0; index < 7; ++index) /* */ + { + if (frameBandwidths[index] > s_SlotMaxBandwidth[index]) + { + frameBandwidths[index + 1] += (frameBandwidths[index] - s_SlotMaxBandwidth[index]); + frameBandwidths[index] = s_SlotMaxBandwidth[index]; + } + } +} + +static void USB_HostBandwidthHsHostComputeCurrentHsAll(usb_host_ehci_instance_t *ehciInstance, + uint16_t frameIndex, + uint8_t frameBandwidths[8]) +{ + usb_host_ehci_pipe_t *ehciPipePointer; + uint8_t index; + uint32_t deviceInfo; + uint16_t frameInterval; + + for (index = 0; index < 8; ++index) + { + frameBandwidths[index] = 0; + } + + ehciPipePointer = ehciInstance->ehciRunningPipeList; + while (ehciPipePointer != NULL) + { + /* only compute iso and interrupt pipe */ + if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) || + (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT)) + { + frameInterval = ehciPipePointer->pipeCommon.interval; + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &deviceInfo); + if (deviceInfo == USB_SPEED_HIGH) /* high-speed data bandwidth */ + { + /* frameInterval means micro-frame here */ + if (frameIndex >= ehciPipePointer->startFrame) + { + if ((frameInterval > 8) && + (frameIndex * 8 - ehciPipePointer->startFrame * 8 >= ehciPipePointer->startUframe)) + { + if (!((uint32_t)(frameIndex * 8 - ehciPipePointer->startFrame * 8 - + ehciPipePointer->startUframe) & + (uint32_t)(frameInterval - 1))) + { + frameBandwidths[ehciPipePointer->startUframe] += ehciPipePointer->dataTime; + } + } + else + { + for (index = ehciPipePointer->startUframe; index < 8; index += frameInterval) + { + frameBandwidths[index] += ehciPipePointer->dataTime; + } + } + } + } + else /* full-speed split bandwidth */ + { + if ((frameIndex >= ehciPipePointer->startFrame) && + (!((uint32_t)(frameIndex - ehciPipePointer->startFrame) & (uint32_t)(frameInterval - 1)))) + { + for (index = 0; index < 8; ++index) + { + if ((uint32_t)(ehciPipePointer->uframeSmask) & + (uint32_t)(0x01 << index)) /* start-split micro-frames */ + { + frameBandwidths[index] += ehciPipePointer->startSplitTime; + } + if ((uint32_t)(ehciPipePointer->uframeCmask) & + (uint32_t)(0x01 << index)) /* complete-split micro-frames */ + { + frameBandwidths[index] += ehciPipePointer->completeSplitTime; + } + } + } + } + } + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } + + for (index = 0; index < 7; ++index) /* */ + { + if (frameBandwidths[index] > s_SlotMaxBandwidth[index]) + { + frameBandwidths[index + 1] += (frameBandwidths[index] - s_SlotMaxBandwidth[index]); + frameBandwidths[index] = s_SlotMaxBandwidth[index]; + } + } +} + +/*! + * @brief allocate HS bandwidth when host work as high-speed host. + * + * @param ehciInstance ehci instance pointer. + * @param uframeInterval micro-frame interval. + * @param timeData time for allocating. + * @param uframeIndexOut return start uframe index. + * + * @return kStatus_USB_Success or error codes. + */ +static usb_status_t USB_HostBandwidthHsHostAllocateHsCommon(usb_host_ehci_instance_t *ehciInstance, + uint16_t uframeInterval, + uint16_t timeData, + uint16_t *uframeIndexOut) +{ + uint16_t uframeIntervalIndex; + uint16_t uframeIndex; + uint16_t frameIndex; + uint8_t frameTimes[8]; + + frameIndex = 0; + USB_HostBandwidthHsHostComputeCurrentHsAll( + ehciInstance, frameIndex, frameTimes); /* compute the allocated bandwidths in the frameIndex frame */ + for (uframeIntervalIndex = 0; (uframeIntervalIndex < uframeInterval); ++uframeIntervalIndex) /* start micro-frame */ + { + /* for all the micro-frame in interval uframeInterval */ + for (uframeIndex = uframeIntervalIndex; uframeIndex < (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 8); + uframeIndex += uframeInterval) + { + if (frameIndex != (uframeIndex >> 3)) + { + frameIndex = (uframeIndex >> 3); + USB_HostBandwidthHsHostComputeCurrentHsAll( + ehciInstance, frameIndex, + frameTimes); /* compute the allocated bandwidths in the new frameIndex frame */ + } + if (frameTimes[uframeIndex & 0x0007] + timeData > + s_SlotMaxBandwidth[(uframeIndex & 0x0007)]) /* micro-frame has enough idle bandwidth? */ + { + break; /* fail */ + } + } + if (uframeIndex >= (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE * 8)) /* success? */ + { + break; + } + } + + if (uframeIntervalIndex < uframeInterval) + { + *uframeIndexOut = (uframeIntervalIndex); + return kStatus_USB_Success; + } + else + { + return kStatus_USB_Error; + } +} + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + +static usb_status_t USB_HostBandwidthHsHostAllocateIso(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_status_t status; + uint32_t deviceInfo; + uint32_t hubNumber; + uint16_t uframeIntervalIndex = 0; + uint16_t frameIntervalIndex = 0; + uint16_t frameIndex; + uint16_t timeCompleteSplit; + uint16_t timeStartSplit; + uint32_t timeData; + uint8_t SsCsNumber = 0; + uint16_t frameInterval; + uint8_t frameTimes[8]; + uint8_t allocateOk = 1; + uint8_t index; + + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &deviceInfo); + + timeData = USB_HostBandwidthComputeTime( + deviceInfo, USB_ENDPOINT_ISOCHRONOUS, ehciPipePointer->pipeCommon.direction, + ehciPipePointer->pipeCommon.maxPacketSize * ehciPipePointer->pipeCommon.numberPerUframe); + /* pipe is high-speed */ + if (deviceInfo == USB_SPEED_HIGH) + { + uframeIntervalIndex = 0; + status = USB_HostBandwidthHsHostAllocateHsCommon(ehciInstance, ehciPipePointer->uframeInterval, timeData, + &uframeIntervalIndex); + if (status == kStatus_USB_Success) + { + ehciPipePointer->startFrame = (uframeIntervalIndex / 8); + ehciPipePointer->startUframe = (uframeIntervalIndex & 0x0007); + ehciPipePointer->dataTime = timeData; + + return kStatus_USB_Success; + } + } + else /* pipe is full-speed or low-speed */ + { + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetHubThinkTime, + &deviceInfo); /* deviceInfo variable means hub think time */ + timeData += (deviceInfo * 7 / (6 * 12)); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubNumber, + &hubNumber); + frameInterval = ehciPipePointer->pipeCommon.interval; + + /* compute start-split and complete-split bandwidth */ + if (ehciPipePointer->pipeCommon.direction == USB_OUT) + { + timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_OUT, + ehciPipePointer->pipeCommon.maxPacketSize); + timeCompleteSplit = 0; + } + else + { + timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_IN, 1); + timeCompleteSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_ISOCHRONOUS, USB_IN, + ehciPipePointer->pipeCommon.maxPacketSize); + } + /* note: bandwidth must put in one frame */ + for (uframeIntervalIndex = 0; uframeIntervalIndex <= 5; ++uframeIntervalIndex) /* uframe interval */ + { + for (frameIntervalIndex = 0; frameIntervalIndex < frameInterval; ++frameIntervalIndex) /* frame interval */ + { + allocateOk = 1; + for (frameIndex = frameIntervalIndex; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; + frameIndex += frameInterval) /* check all the frames */ + { + /* compute start-split and complete-split number */ + SsCsNumber = (ehciPipePointer->pipeCommon.maxPacketSize + 187) / + 188; /* ss number for iso out; cs number for iso in */ + if (ehciPipePointer->pipeCommon.direction == USB_OUT) /* ISO OUT */ + { + if (uframeIntervalIndex + SsCsNumber > 8) + { + allocateOk = 0; + } + } + else + { + if (uframeIntervalIndex + 2 + SsCsNumber > + 8) /* ISO IN: there are two micro-frame interval between start-split and complete-split */ + { + allocateOk = 0; + } + } + if (allocateOk) + { + /* allocate start-split and complete-split bandwidth */ + USB_HostBandwidthHsHostComputeCurrentHsAll(ehciInstance, frameIndex, frameTimes); + if (ehciPipePointer->pipeCommon.direction == USB_OUT) /* ISO OUT */ + { + index = uframeIntervalIndex; + for (; index < (uframeIntervalIndex + SsCsNumber); ++index) + { + if (frameTimes[index] + timeStartSplit > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + break; + } + } + } + else /* ISO IN */ + { + index = uframeIntervalIndex; + if (frameTimes[index] + timeStartSplit > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + } + if (allocateOk) + { + index = + uframeIntervalIndex + + 2; /* there are two micro-frames interval between start-split and complete-split */ + for (; index < (uframeIntervalIndex + 2 + SsCsNumber); ++index) + { + if (frameTimes[index] + timeCompleteSplit > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + break; + } + } + } + } + } + + /* allocate data bandwidth */ + if (allocateOk) + { + USB_HostBandwidthHsHostComputeCurrentFsls(ehciInstance, hubNumber, frameIndex, frameTimes); + index = uframeIntervalIndex + 1; /* timeData bandwidth start position */ + /* iso must occupy all the uframe bandwidth */ + { + deviceInfo = timeData; /* note: deviceInfo variable means bandwidth here */ + while ((index < 8) && (deviceInfo > s_SlotMaxBandwidth[index])) + { + if (frameTimes[index] > 0) + { + allocateOk = 0; + break; + } + else + { + deviceInfo -= s_SlotMaxBandwidth[index]; + } + ++index; + } + } + } + if (allocateOk) + { + /* data bandwidth can be put in the frame? */ + index = uframeIntervalIndex + 1; /* timeData bandwidth start position */ + frameTimes[index] += timeData; + for (; index < 7; ++index) + { + if (frameTimes[index] > s_SlotMaxBandwidth[index]) + { + frameTimes[index + 1] += (frameTimes[index] - s_SlotMaxBandwidth[index]); + frameTimes[index] = s_SlotMaxBandwidth[index]; + } + else + { + break; + } + } + if (frameTimes[index] > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + } + } + + if (allocateOk) + { + break; + } + } + if (allocateOk) + { + break; + } + } + if (allocateOk) + { + break; + } + } + + if (allocateOk) + { + ehciPipePointer->startFrame = frameIntervalIndex; + ehciPipePointer->startUframe = uframeIntervalIndex; + ehciPipePointer->dataTime = timeData; + ehciPipePointer->startSplitTime = timeStartSplit; + ehciPipePointer->completeSplitTime = timeCompleteSplit; + if (ehciPipePointer->pipeCommon.direction == USB_OUT) + { + index = uframeIntervalIndex; + for (; index < (uframeIntervalIndex + SsCsNumber); ++index) + { + ehciPipePointer->uframeSmask = (uint32_t)ehciPipePointer->uframeSmask | (uint32_t)(0x01 << index); + } + } + else + { + index = uframeIntervalIndex; + ehciPipePointer->uframeSmask = (uint32_t)ehciPipePointer->uframeSmask | (uint32_t)(0x01 << index); + index = uframeIntervalIndex + 2; + for (; index < (uframeIntervalIndex + 2 + SsCsNumber); ++index) + { + ehciPipePointer->uframeCmask = (uint32_t)ehciPipePointer->uframeCmask | (uint32_t)(0x01 << index); + } + } + + return kStatus_USB_Success; + } + } + + return kStatus_USB_Error; +} + +#endif + +static usb_status_t USB_HostBandwidthHsHostAllocateInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_status_t status; + uint32_t deviceInfo; + uint32_t hubNumber; + uint16_t uframeIntervalIndex = 0; + uint16_t frameIntervalIndex = 0; + uint16_t frameIndex; + uint16_t timeCompleteSplit; + uint16_t timeStartSplit; + uint32_t timeData; + uint8_t SsCsNumber; + uint16_t frameInterval; + uint8_t frameTimes[8]; + uint8_t allocateOk = 1; + uint8_t index; + + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &deviceInfo); + + timeData = USB_HostBandwidthComputeTime( + deviceInfo, USB_ENDPOINT_INTERRUPT, ehciPipePointer->pipeCommon.direction, + ehciPipePointer->pipeCommon.maxPacketSize * ehciPipePointer->pipeCommon.numberPerUframe); + /* pipe is high-speed */ + if (deviceInfo == USB_SPEED_HIGH) + { + uframeIntervalIndex = 0; + status = USB_HostBandwidthHsHostAllocateHsCommon(ehciInstance, ehciPipePointer->uframeInterval, timeData, + &uframeIntervalIndex); + if (status == kStatus_USB_Success) + { + ehciPipePointer->startFrame = (uframeIntervalIndex / 8); + ehciPipePointer->startUframe = (uframeIntervalIndex & 0x0007); + /* for HS interrupt start transaction position */ + if (ehciPipePointer->uframeInterval >= 8) + { + ehciPipePointer->uframeSmask = (0x01 << ehciPipePointer->startUframe); + } + else + { + ehciPipePointer->uframeSmask = 0x00u; + for (index = ehciPipePointer->startUframe; index < 8; index += ehciPipePointer->uframeInterval) + { + ehciPipePointer->uframeSmask |= (0x01U << index); + } + } + ehciPipePointer->dataTime = timeData; + + return kStatus_USB_Success; + } + } + else /* pipe is full-speed or low-speed */ + { + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetHubThinkTime, + &deviceInfo); + timeData += (deviceInfo * 7 / (6 * 12)); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubNumber, + &hubNumber); + frameInterval = ehciPipePointer->pipeCommon.interval; + SsCsNumber = 3; /* complete split number */ + + /* compute start-split and complete-split bandwidth */ + if (ehciPipePointer->pipeCommon.direction == USB_OUT) + { + timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT, + ehciPipePointer->pipeCommon.maxPacketSize) + + USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT, 1); + timeCompleteSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_OUT, 0); + } + else + { + timeStartSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN, 1); + timeCompleteSplit = USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN, + ehciPipePointer->pipeCommon.maxPacketSize) + + USB_HostBandwidthComputeTime(USB_SPEED_HIGH, USB_ENDPOINT_INTERRUPT, USB_IN, 0); + } + /* note: bandwidth must put in one frame */ + for (uframeIntervalIndex = 0; uframeIntervalIndex <= 4; ++uframeIntervalIndex) /* uframe interval */ + { + for (frameIntervalIndex = 0; frameIntervalIndex < frameInterval; ++frameIntervalIndex) /* frame interval */ + { + allocateOk = 1; + for (frameIndex = frameIntervalIndex; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; + frameIndex += frameInterval) /* check all the frames */ + { + /* allocate data bandwidth */ + USB_HostBandwidthHsHostComputeCurrentFsls(ehciInstance, hubNumber, frameIndex, frameTimes); + index = uframeIntervalIndex + 1; + for (; index <= (uframeIntervalIndex + 3); ++index) /* data bandwidth number is 3. + uframeIntervalIndex don't exceed 4, so + index cannot exceed 7 */ + { + if (frameTimes[index] + timeData > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + break; + } + } + + if (allocateOk) + { + USB_HostBandwidthHsHostComputeCurrentHsAll(ehciInstance, frameIndex, frameTimes); + /* allocate start_split bandwidth */ + if (frameTimes[uframeIntervalIndex] + timeStartSplit > s_SlotMaxBandwidth[uframeIntervalIndex]) + { + allocateOk = 0; + } + if (allocateOk) + { + /* allocate complete_split bandwidth */ + index = uframeIntervalIndex + 2; + /* complete-split number is normal 3. When uframeIntervalIndex is 4, complete-split number + * is 2. */ + for (; (index <= (uframeIntervalIndex + 1 + SsCsNumber)) && (index < 8); ++index) + { + if (frameTimes[index] + timeCompleteSplit > s_SlotMaxBandwidth[index]) + { + allocateOk = 0; + break; + } + } + } + } + + if (!allocateOk) + { + break; /* allocate fail */ + } + } + if (allocateOk) + { + break; + } + } + if (allocateOk) + { + break; + } + } + + if (allocateOk) + { + ehciPipePointer->startFrame = frameIntervalIndex; + ehciPipePointer->startUframe = uframeIntervalIndex; + ehciPipePointer->uframeSmask = (0x01 << ehciPipePointer->startUframe); + ehciPipePointer->uframeCmask = 0; + index = uframeIntervalIndex + 2; + for (; (index <= (uframeIntervalIndex + 1 + SsCsNumber)) && (index < 8); ++index) + { + ehciPipePointer->uframeCmask = (uint32_t)ehciPipePointer->uframeCmask | (uint32_t)(0x01 << index); + } + ehciPipePointer->dataTime = timeData; + ehciPipePointer->startSplitTime = timeStartSplit; + ehciPipePointer->completeSplitTime = timeCompleteSplit; + + return kStatus_USB_Success; + } + } + + return kStatus_USB_BandwidthFail; +} + +static usb_status_t USB_HostBandwidthFslsHostAllocate(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + uint32_t FslsTime = 0; + uint32_t speed = 0; + uint16_t uframeIntervalIndex; + uint16_t frameIndex; + uint16_t frameInterval; + uint16_t frameTime; + + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetHubThinkTime, + &FslsTime); + FslsTime += (FslsTime * 7 / (6 * 12)); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, &speed); + FslsTime = FslsTime + USB_HostBandwidthComputeTime(speed, ehciPipePointer->pipeCommon.pipeType, + ehciPipePointer->pipeCommon.direction, + ehciPipePointer->pipeCommon.maxPacketSize); + + frameInterval = ehciPipePointer->pipeCommon.interval; + for (uframeIntervalIndex = 0; uframeIntervalIndex < ehciPipePointer->uframeInterval; + ++uframeIntervalIndex) /* uframeIntervalIndex can exceed 8 */ + { + for (frameIndex = (uframeIntervalIndex >> 3); frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; + frameIndex += frameInterval) + { + USB_HostBandwidthFslsHostComputeCurrent(ehciInstance, frameIndex, &frameTime); + if (frameTime + FslsTime > USB_HOST_EHCI_BANDWIDTH_FRAME_TOTOAL_TIME) + { + break; + } + } + if (frameIndex >= USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE) + { + break; + } + } + if (uframeIntervalIndex < ehciPipePointer->uframeInterval) + { + ehciPipePointer->startFrame = (uframeIntervalIndex >> 3); + ehciPipePointer->startUframe = (uframeIntervalIndex & 0x0007); + ehciPipePointer->uframeSmask = 0; /* useless */ + ehciPipePointer->uframeCmask = 0; + ehciPipePointer->dataTime = FslsTime; + + return kStatus_USB_Success; + } + + return kStatus_USB_BandwidthFail; +} + +static uint8_t USB_HostEhciGet2PowerValue(uint8_t value) +{ + if ((value == 0) || (value == 1)) + { + return value; + } + if (value & 0xf0) + { + if (value & 0x80) + { + return 128; + } + else if (value & 0x40) + { + return 64; + } + else if (value & 0x20) + { + return 32; + } + else + { + return 16; + } + } + else + { + if (value & 0x08) + { + return 8; + } + else if (value & 0x04) + { + return 4; + } + else if (value & 0x02) + { + return 2; + } + else + { + return 1; + } + } +} + +static void USB_HostEhciZeroMem(uint32_t *buffer, uint32_t length) +{ + /* note: the zero unit is uint32_t */ + while (length--) + { + *buffer = 0; + buffer++; + } +} + +static void USB_HostEhciDelay(USBHS_Type *ehciIpBase, uint32_t ms) +{ + /* note: the max delay time cannot exceed half of max value (0x4000) */ + int32_t sofStart; + int32_t SofEnd; + uint32_t distance; + + sofStart = (int32_t)(ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + + do + { + SofEnd = (int32_t)(ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + distance = (uint32_t)(SofEnd - sofStart + EHCI_MAX_UFRAME_VALUE + 1); + } while ((distance & EHCI_MAX_UFRAME_VALUE) < (ms * 8)); /* compute the distance between sofStart and SofEnd */ +} + +static void USB_HostEhciStartAsync(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t stateSync; + + if (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK)) + { + /* the status must be same when change USBCMD->ASE */ + do + { + stateSync = ((ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK) | + (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_ASE_MASK)); + } while ((stateSync == USBHS_USBSTS_AS_MASK) || (stateSync == USBHS_USBCMD_ASE_MASK)); + + ehciInstance->ehciIpBase->ASYNCLISTADDR = (uint32_t)(ehciInstance->shedFirstQh); + ehciInstance->ehciIpBase->USBCMD |= USBHS_USBCMD_ASE_MASK; + while (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK)) + { + } + } +} + +static void USB_HostEhciStopAsync(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t stateSync; + + /* the status must be same when change USBCMD->ASE */ + do + { + stateSync = ((ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK) | + (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_ASE_MASK)); + } while ((stateSync == USBHS_USBSTS_AS_MASK) || (stateSync == USBHS_USBCMD_ASE_MASK)); + + ehciInstance->ehciIpBase->USBCMD &= (uint32_t)(~(uint32_t)USBHS_USBCMD_ASE_MASK); /* disable async schedule */ + while (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK) + { + } +} + +static void USB_HostEhciStartPeriodic(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t stateSync; + + if (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK)) + { + /* the status must be same when change USBCMD->PSE */ + do + { + stateSync = ((ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK) | + (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_PSE_MASK)); + } while ((stateSync == USBHS_USBSTS_PS_MASK) || (stateSync == USBHS_USBCMD_PSE_MASK)); + ehciInstance->ehciIpBase->PERIODICLISTBASE = (uint32_t)(ehciInstance->ehciFrameList); + if (!(ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_PSE_MASK)) + { + ehciInstance->ehciIpBase->USBCMD |= USBHS_USBCMD_PSE_MASK; /* start periodic schedule */ + } + while (!(ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK)) + { + } + } + return; +} + +static void USB_HostEhciStopPeriodic(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t stateSync; + + /* the status must be same when change USBCMD->PSE */ + do + { + stateSync = ((ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK) | + (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_PSE_MASK)); + } while ((stateSync == USBHS_USBSTS_PS_MASK) || (stateSync == USBHS_USBCMD_PSE_MASK)); + + ehciInstance->ehciIpBase->USBCMD &= (~USBHS_USBCMD_PSE_MASK); /* stop periodic schedule */ + while (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_PS_MASK) + { + } +} + +static usb_status_t USB_HostEhciQhQtdListInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer) +{ + volatile usb_host_ehci_qh_t *vltQhPointer; + usb_host_ehci_qtd_t *qtdPointer = NULL; + usb_host_ehci_qtd_t *BaseQtdPointer = NULL; + volatile uint32_t *entryPointer; + uint32_t qtdNumber; + uint32_t dataLength; + uint32_t dataAddress; + uint32_t endAddress; + uint8_t index; + + /* compute the qtd number */ + if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL) + { + /* assume setup data don't exceed one qtd data size, one qtd can transfer least 16k data */ + if (transfer->transferLength == 0) + { + qtdNumber = 2; + } + else + { + qtdNumber = 3; + } + } + else + { + qtdNumber = + (((transfer->transferLength) & 0xFFFFC000U) >> 14) + (((transfer->transferLength) & 0x00003FFF) ? 1 : 0); + } + + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + /* get qtd list */ + USB_HostEhciLock(); + if (qtdNumber <= ehciInstance->ehciQtdNumber) + { + ehciInstance->ehciQtdNumber -= qtdNumber; + BaseQtdPointer = ehciInstance->ehciQtdHead; + qtdPointer = NULL; + do + { + if (qtdPointer != NULL) + { + qtdPointer->nextQtdPointer = (uint32_t)ehciInstance->ehciQtdHead; + } + qtdPointer = ehciInstance->ehciQtdHead; + ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)qtdPointer->nextQtdPointer; + qtdPointer->nextQtdPointer = 0; + } while (--qtdNumber); + if (ehciInstance->ehciQtdNumber == 0) + { + ehciInstance->ehciQtdTail = NULL; + } + } + else + { + USB_HostEhciUnlock(); + return kStatus_USB_Error; + } + USB_HostEhciUnlock(); + + /* int qTD list */ + if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL) + { + /* setup transaction qtd */ + qtdPointer = BaseQtdPointer; + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: need set; ioc: 0; C_Page: 0; PID Code: SETUP; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + qtdPointer->transferResults[0] = + ((0x00000000 << EHCI_HOST_QTD_DT_SHIFT) | (8 << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + (EHCI_HOST_PID_SETUP << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + dataAddress = ((uint32_t)transfer->setupPacket); + qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ + /* set buffer pointer no matter data length */ + for (index = 0; index < 4; ++index) + { + qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000U); + } + + /* data transaction qtd */ + dataLength = transfer->transferLength; + if (dataLength != 0) + { + qtdPointer = (usb_host_ehci_qtd_t *)(qtdPointer->nextQtdPointer); + + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: need set; ioc: 0; C_Page: 0; PID Code: IN/OUT; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + if (transfer->direction == USB_OUT) + { + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (dataLength << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + (EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + else + { + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (dataLength << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + + dataAddress = (uint32_t)transfer->transferBuffer; + qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ + /* set buffer pointer no matter data length */ + for (index = 0; index < 4; ++index) + { + qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000U); + } + } + + /* status transaction qtd */ + qtdPointer = (usb_host_ehci_qtd_t *)(qtdPointer->nextQtdPointer); + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: dont care; ioc: 1; C_Page: 0; PID Code: IN/OUT; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + if ((dataLength == 0) || (transfer->direction == USB_OUT)) + { + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | + (EHCI_HOST_QTD_IOC_MASK) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + else + { + qtdPointer->transferResults[0] = + ((0x00000001U << EHCI_HOST_QTD_DT_SHIFT) | (EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | + (EHCI_HOST_QTD_IOC_MASK) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + qtdPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; + } + else + { + dataLength = transfer->transferLength; + dataAddress = (uint32_t)transfer->transferBuffer; + qtdPointer = BaseQtdPointer; + while (1) + { + endAddress = dataAddress + (16 * 1024); + if (endAddress > (uint32_t)(transfer->transferBuffer + transfer->transferLength)) + { + endAddress = (uint32_t)(transfer->transferBuffer + transfer->transferLength); + } + + qtdPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + /* dt: set; ioc: 0; C_Page: 0; PID Code: IN/OUT; Status: Active */ + qtdPointer->transferResults[0] = qtdPointer->transferResults[1] = 0; + if (transfer->direction == USB_OUT) + { + qtdPointer->transferResults[0] = + (((endAddress - dataAddress) << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + ((uint32_t)ehciPipePointer->pipeCommon.nextdata01 << EHCI_HOST_QTD_DT_SHIFT) | + (EHCI_HOST_QTD_CERR_MAX_VALUE << EHCI_HOST_QTD_CERR_SHIFT) | + (EHCI_HOST_PID_OUT << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + else + { + qtdPointer->transferResults[0] = + (((endAddress - dataAddress) << EHCI_HOST_QTD_TOTAL_BYTES_SHIFT) | + ((uint32_t)ehciPipePointer->pipeCommon.nextdata01 << EHCI_HOST_QTD_DT_SHIFT) | + (EHCI_HOST_QTD_CERR_MAX_VALUE << EHCI_HOST_QTD_CERR_SHIFT) | + (EHCI_HOST_PID_IN << EHCI_HOST_QTD_PID_CODE_SHIFT) | (EHCI_HOST_QTD_STATUS_ACTIVE_MASK)); + } + qtdPointer->transferResults[1] = dataAddress; /* current offset is set too */ + /* set buffer pointer no matter data length */ + for (index = 0; index < 4; ++index) + { + qtdPointer->bufferPointers[index] = ((dataAddress + (index + 1) * 4 * 1024) & 0xFFFFF000U); + } + dataAddress = endAddress; /* for next qtd */ + + if (qtdPointer->nextQtdPointer == 0) + { + break; + } + qtdPointer = (usb_host_ehci_qtd_t *)(qtdPointer->nextQtdPointer); + } + + qtdPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; + qtdPointer->transferResults[0] |= EHCI_HOST_QTD_IOC_MASK; /* last one set IOC */ + } + + /* save qtd to transfer */ + transfer->union1.unitHead = (uint32_t)BaseQtdPointer; + transfer->union2.unitTail = (uint32_t)qtdPointer; + /* link transfer to qh */ + transfer->next = NULL; + if (vltQhPointer->ehciTransferHead == NULL) + { + transfer->next = NULL; + vltQhPointer->ehciTransferHead = vltQhPointer->ehciTransferTail = transfer; + } + else + { + transfer->next = NULL; + vltQhPointer->ehciTransferTail->next = transfer; + vltQhPointer->ehciTransferTail = transfer; + } + + USB_HostEhciLock(); + /* link qtd to qh (link to end) */ + entryPointer = &(vltQhPointer->nextQtdPointer); + dataAddress = *entryPointer; /* dataAddress variable means entry value here */ + while ((dataAddress) && (!(dataAddress & EHCI_HOST_T_INVALID_VALUE))) + { + entryPointer = (volatile uint32_t *)dataAddress; + dataAddress = *entryPointer; + } + *entryPointer = (uint32_t)BaseQtdPointer; + USB_HostEhciUnlock(); + USB_HostEhciStartAsync(ehciInstance); + + return kStatus_USB_Success; +} + +static uint32_t USB_HostEhciQtdListRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_qtd_t *ehciQtdStart, + usb_host_ehci_qtd_t *ehciQtdEnd) +{ + uint32_t length = 0; + usb_host_ehci_qtd_t *qtdPointer; + + ehciQtdEnd->nextQtdPointer = 0; + + /* compute remaining length */ + qtdPointer = ehciQtdStart; + while (qtdPointer != ehciQtdEnd) + { + length += + ((qtdPointer->transferResults[0] & EHCI_HOST_QTD_TOTAL_BYTES_MASK) >> EHCI_HOST_QTD_TOTAL_BYTES_SHIFT); + qtdPointer = (usb_host_ehci_qtd_t *)qtdPointer->nextQtdPointer; + } + qtdPointer = ehciQtdEnd; + length += ((qtdPointer->transferResults[0] & EHCI_HOST_QTD_TOTAL_BYTES_MASK) >> EHCI_HOST_QTD_TOTAL_BYTES_SHIFT); + + /* put releasing qtd to idle qtd list */ + USB_HostEhciLock(); + if (ehciInstance->ehciQtdNumber == 0) + { + ehciInstance->ehciQtdHead = ehciQtdStart; + ehciInstance->ehciQtdTail = ehciQtdEnd; + } + else + { + ehciInstance->ehciQtdTail->nextQtdPointer = (uint32_t)ehciQtdStart; + ehciInstance->ehciQtdTail = ehciQtdEnd; + } + + while (ehciQtdStart != ehciQtdEnd) + { + ehciInstance->ehciQtdNumber++; + ehciQtdStart = (usb_host_ehci_qtd_t *)ehciQtdStart->nextQtdPointer; + } + ehciInstance->ehciQtdNumber++; + USB_HostEhciUnlock(); + + return length; +} + +static usb_status_t USB_HostEhciQhQtdListDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + volatile usb_host_ehci_qh_t *vltQhPointer; + usb_host_transfer_t *transfer; + usb_host_transfer_t *nextTransfer; + uint8_t needStop = 0; + + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + + USB_HostEhciLock(); /* this API is called from APP, the host task may occupy to access the same resource */ + /* remove qtd from qh */ + if ((!((uint32_t)vltQhPointer->nextQtdPointer & EHCI_HOST_T_INVALID_VALUE)) || + (!((uint32_t)vltQhPointer->currentQtdPointer & EHCI_HOST_T_INVALID_VALUE))) + { + /* need stop async schedule */ + if ((!(vltQhPointer->horizontalLinkPointer & EHCI_HOST_T_INVALID_VALUE)) && + (ehciPipePointer->pipeCommon.pipeType != USB_ENDPOINT_INTERRUPT)) + { + needStop = 1; + } + if (needStop) + { + USB_HostEhciStopAsync(ehciInstance); + } + vltQhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid current qtd */ + vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */ + vltQhPointer->transferOverlayResults[0] &= (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + if (needStop) + { + USB_HostEhciStartAsync(ehciInstance); + } + } + + /* remove transfer from the QH transfer list */ + transfer = vltQhPointer->ehciTransferHead; + vltQhPointer->ehciTransferHead = vltQhPointer->ehciTransferTail = NULL; + USB_HostEhciUnlock(); + + /* release qtd and transfer callback*/ + while (transfer != NULL) + { + nextTransfer = transfer->next; /* the transfer is released when call back */ + transfer->transferSofar = + USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), + (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); + transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ? + 0 : + (transfer->transferLength - transfer->transferSofar); + transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel); + transfer = nextTransfer; + } + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciTransferQtdListDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer) +{ + volatile usb_host_ehci_qh_t *vltQhPointer; + usb_host_transfer_t *preSearchTransfer; + uint32_t qhNextQtdValue; + uint32_t qtdPointerEntry; + uint32_t *searchQtdEntryPointer; + + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + + USB_HostEhciLock(); /* this API is called from APP, the host task may occupy to access the same resource */ + /* remove qtd from qh */ + qhNextQtdValue = (uint32_t)vltQhPointer->currentQtdPointer; + qtdPointerEntry = *((uint32_t *)qhNextQtdValue + 2); /* note: qtdPointerEntry means qtd status */ + if ((qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE) || (!(qtdPointerEntry & EHCI_HOST_QTD_STATUS_ACTIVE_MASK))) + { + qhNextQtdValue = (uint32_t)vltQhPointer->nextQtdPointer; + } + if (!(qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE)) /* there is pending qtd in the qh */ + { + /* this qh don't schedule temporarily */ + if (ehciPipePointer->pipeCommon.pipeType != USB_ENDPOINT_INTERRUPT) + { + USB_HostEhciStopAsync(ehciInstance); + } + vltQhPointer->currentQtdPointer |= EHCI_HOST_T_INVALID_VALUE; /* invalid current qtd */ + vltQhPointer->nextQtdPointer |= EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */ + if (ehciPipePointer->pipeCommon.pipeType != USB_ENDPOINT_INTERRUPT) + { + USB_HostEhciStartAsync(ehciInstance); + } + + /* remove qtd from qh one by one */ + qtdPointerEntry = transfer->union1.unitHead; + while (1) + { + /* search qh's qtd list for qtdPointerEntry */ + searchQtdEntryPointer = &qhNextQtdValue; + while (!((*searchQtdEntryPointer) & EHCI_HOST_T_INVALID_VALUE)) + { + if ((*searchQtdEntryPointer) == qtdPointerEntry) + { + *searchQtdEntryPointer = *((uint32_t *)qtdPointerEntry); /* remove the qtd from qh */ + break; + } + else + { + searchQtdEntryPointer = (uint32_t *)(*searchQtdEntryPointer); + } + } + if (qtdPointerEntry == transfer->union2.unitTail) + { + break; + } + qtdPointerEntry = *((uint32_t *)qtdPointerEntry); + } + } + + /* remove transfer from the QH transfer list */ + preSearchTransfer = vltQhPointer->ehciTransferHead; + if (preSearchTransfer == transfer) + { + vltQhPointer->ehciTransferHead = preSearchTransfer->next; + } + else + { + while (preSearchTransfer != NULL) + { + if (preSearchTransfer->next == transfer) + { + preSearchTransfer->next = transfer->next; + break; + } + else + { + preSearchTransfer = preSearchTransfer->next; + } + } + } + USB_HostEhciUnlock(); + + /* release qtd and callback */ + transfer->transferSofar = + USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), + (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); + transfer->transferSofar = + (transfer->transferLength < transfer->transferSofar) ? 0 : (transfer->transferLength - transfer->transferSofar); + transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel); + + /* start this qh schedule */ + vltQhPointer->transferOverlayResults[0] &= (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + if ((qhNextQtdValue != 0) && (!(qhNextQtdValue & EHCI_HOST_T_INVALID_VALUE))) + { + vltQhPointer->nextQtdPointer = qhNextQtdValue; + } + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciQhInit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_qh_t *qhPointer = NULL; + uint32_t address, speed, portNumber, hubNumber; + uint32_t controlBits1 = 0; + uint32_t controlBits2 = 0; + /* get qh */ + USB_HostEhciLock(); + if (ehciInstance->ehciQhList != NULL) + { + qhPointer = (usb_host_ehci_qh_t *)ehciInstance->ehciQhList; + ehciInstance->ehciQhList = + (usb_host_ehci_qh_t *)(ehciInstance->ehciQhList->horizontalLinkPointer & EHCI_HOST_POINTER_ADDRESS_MASK); + } + USB_HostEhciUnlock(); + if (qhPointer == NULL) + { +#ifdef HOST_EHCO + usb_echo("get qh error\r\n"); +#endif + return kStatus_USB_Error; + } + ehciPipePointer->ehciQh = (void *)qhPointer; + + /* initialize qh */ + USB_HostEhciZeroMem((uint32_t *)qhPointer, sizeof(usb_host_ehci_qh_t) / 4); + qhPointer->horizontalLinkPointer = EHCI_HOST_T_INVALID_VALUE; + qhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; + qhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + qhPointer->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + qhPointer->ehciPipePointer = ehciPipePointer; + qhPointer->timeOutLabel = 0; + qhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, &speed); + /* initialize staticEndpointStates[0] */ + if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT) + { + /* Software should set the RL field to zero if the queue head is an interrupt endpoint. */ + controlBits1 |= ((0U << EHCI_HOST_QH_RL_SHIFT) & EHCI_HOST_QH_RL_MASK); + } + else + { + if (ehciPipePointer->pipeCommon.nakCount >= 16) + { + controlBits1 |= ((15U << EHCI_HOST_QH_RL_SHIFT) & EHCI_HOST_QH_RL_MASK); + } + else + { + controlBits1 |= + (((uint32_t)ehciPipePointer->pipeCommon.nakCount << EHCI_HOST_QH_RL_SHIFT) & EHCI_HOST_QH_RL_MASK); + } + } + if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL) + { + if (speed != USB_SPEED_HIGH) + { + controlBits1 |= (1 << EHCI_HOST_QH_C_SHIFT); + } + controlBits1 |= (1 << EHCI_HOST_QH_DTC_SHIFT); + } + controlBits1 |= ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT); + controlBits1 |= (speed << EHCI_HOST_QH_EPS_SHIFT); + controlBits1 |= ((uint32_t)ehciPipePointer->pipeCommon.endpointAddress << EHCI_HOST_QH_ENDPT_SHIFT); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress, + &address); + controlBits1 |= (address << EHCI_HOST_QH_DEVICE_ADDRESS_SHIFT); + qhPointer->staticEndpointStates[0] = controlBits1; + if (speed == USB_SPEED_HIGH) + { + controlBits2 |= ((uint32_t)ehciPipePointer->pipeCommon.numberPerUframe << EHCI_HOST_QH_MULT_SHIFT); + } + else + { + controlBits2 |= (0x00000001U << EHCI_HOST_QH_MULT_SHIFT); + } + /*initialize staticEndpointStates[1] */ + if (speed != USB_SPEED_HIGH) + { + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubNumber, + &hubNumber); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHSHubPort, + &portNumber); + } + else + { + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHubNumber, + &hubNumber); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDevicePortNumber, + &portNumber); + } + controlBits2 |= (portNumber << EHCI_HOST_QH_PORT_NUMBER_SHIFT); + controlBits2 |= (hubNumber << EHCI_HOST_QH_HUB_ADDR_SHIFT); + controlBits2 |= ((uint32_t)ehciPipePointer->uframeCmask << EHCI_HOST_QH_UFRAME_CMASK_SHIFT); + controlBits2 |= ((uint32_t)ehciPipePointer->uframeSmask << EHCI_HOST_QH_UFRAME_SMASK_SHIFT); + qhPointer->staticEndpointStates[1] = controlBits2; + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciQhDeinit(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_qh_t *qhPointer; + + qhPointer = (usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + /* de-initialize qtd from qh */ + USB_HostEhciQhQtdListDeinit(ehciInstance, ehciPipePointer); + + /* release QH */ + USB_HostEhciLock(); + qhPointer->horizontalLinkPointer = (uint32_t)ehciInstance->ehciQhList; + ehciInstance->ehciQhList = qhPointer; + USB_HostEhciUnlock(); + + return kStatus_USB_Success; +} + +static void USB_HostEhciAddQhToFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t entryPointerValue, + uint16_t framePos, + uint16_t uframeInterval) +{ + volatile uint32_t *frameEntryPointer; + uint32_t frameEntryValue; + + /* search for the inserting point by interval */ + frameEntryPointer = (volatile uint32_t *)(&((uint32_t *)ehciInstance->ehciFrameList)[framePos]); + while (frameEntryPointer) + { + frameEntryValue = *frameEntryPointer; + if (frameEntryValue & EHCI_HOST_T_INVALID_VALUE) + { + /* insert into the end */ + *((uint32_t *)entryPointerValue) = EHCI_HOST_T_INVALID_VALUE; + *frameEntryPointer = (entryPointerValue | EHCI_HOST_POINTER_TYPE_QH); + break; + } + + if ((frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK) == entryPointerValue) + { + return; /* has inserted */ + } + if (((frameEntryValue & EHCI_HOST_POINTER_TYPE_MASK) == EHCI_HOST_POINTER_TYPE_QH) && + (((usb_host_ehci_qh_t *)(frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK)) + ->ehciPipePointer->uframeInterval <= uframeInterval)) + { + /* insert into this point */ + *((uint32_t *)entryPointerValue) = frameEntryValue; + *frameEntryPointer = (entryPointerValue | EHCI_HOST_POINTER_TYPE_QH); + return; + } + else + { + frameEntryPointer = (volatile uint32_t *)(frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK); + } + } +} + +static void USB_HostEhciRemoveFromFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t entryPointerValue, + uint16_t framePos) +{ + volatile uint32_t *frameEntryPointer; + uint32_t frameEntryValue; + + /* search for the qh/itd/sitd entry */ + frameEntryPointer = (volatile uint32_t *)(&((uint32_t *)ehciInstance->ehciFrameList)[framePos]); + + while (frameEntryPointer) + { + frameEntryValue = *frameEntryPointer; + if (frameEntryValue & EHCI_HOST_T_INVALID_VALUE) + { + return; + } + + if ((frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK) == entryPointerValue) + { + /* remove the entry */ + *frameEntryPointer = *((uint32_t *)entryPointerValue); + break; + } + else + { + frameEntryPointer = (volatile uint32_t *)(frameEntryValue & EHCI_HOST_POINTER_ADDRESS_MASK); + } + } +} + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) +static void USB_HostEhciLinkSitd(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + void *startEntryPointer) +{ + usb_host_ehci_iso_t *isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + usb_host_ehci_sitd_t *sitdPointer; + uint32_t distance; + uint32_t frameInterval; + int32_t shouldLinkFrame; + int32_t currentFrame; + + frameInterval = (ehciPipePointer->uframeInterval >> 3); + + if (isoPointer->lastLinkFrame == 0xFFFF) /* first link */ + { + currentFrame = ((ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE) >> 3); + currentFrame = ((uint32_t)(currentFrame + USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER) & + (EHCI_MAX_UFRAME_VALUE >> 3)); /* add USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER */ + /* frame should align with interval */ + currentFrame -= ehciPipePointer->startFrame; + currentFrame = + ((uint32_t)(currentFrame + frameInterval - 1) & (~(frameInterval - 1))); /* frameInterval is power of 2 */ + currentFrame += ehciPipePointer->startFrame; + } + else + { + shouldLinkFrame = isoPointer->lastLinkFrame + frameInterval; /* continuous next should link frame */ + if (shouldLinkFrame > (int32_t)(EHCI_MAX_UFRAME_VALUE >> 3)) + { + shouldLinkFrame = shouldLinkFrame - ((EHCI_MAX_UFRAME_VALUE >> 3) + 1); + } + currentFrame = ((ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE) >> 3); + distance = ((shouldLinkFrame - currentFrame + (EHCI_MAX_UFRAME_VALUE >> 3) + 1) & + (EHCI_MAX_UFRAME_VALUE >> 3)); /* get the distance from shouldLinkFrame to currentFrame */ + /* shouldLinkFrame has add frameInterval, think about the align with interval, so here add (frameInterval * + * 2) */ + if ((distance <= (USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER + frameInterval * 2)) && (distance > 0)) + { + currentFrame = shouldLinkFrame; + } + else /* re-link */ + { + currentFrame = + ((uint32_t)(currentFrame + USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER) & (EHCI_MAX_UFRAME_VALUE >> 3)); + if (currentFrame > (int32_t)(EHCI_MAX_UFRAME_VALUE >> 3)) + { + currentFrame = currentFrame - ((EHCI_MAX_UFRAME_VALUE >> 3) + 1); + } + /* frame should align with interval */ + currentFrame -= ehciPipePointer->startFrame; + currentFrame = ((uint32_t)(currentFrame + frameInterval - 1) & (~(frameInterval - 1))); + currentFrame += ehciPipePointer->startFrame; + } + } + if (currentFrame >= (int32_t)USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE) /* frame turn around */ + { + shouldLinkFrame = + (currentFrame - USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE); /* shouldLinkFrame means inserted frame position */ + } + else + { + shouldLinkFrame = currentFrame; /* shouldLinkFrame means inserted frame position */ + } + + sitdPointer = (usb_host_ehci_sitd_t *)startEntryPointer; + while (sitdPointer) + { + sitdPointer->frameEntryIndex = shouldLinkFrame; + /* add to frame list head */ + sitdPointer->nextLinkPointer = ((uint32_t *)ehciInstance->ehciFrameList)[shouldLinkFrame]; + ((uint32_t *)ehciInstance->ehciFrameList)[shouldLinkFrame] = + ((uint32_t)sitdPointer | EHCI_HOST_POINTER_TYPE_SITD); + if (sitdPointer->nextSitdIndex == 0xFF) /* 0xFF is invalid value */ + { + break; + } + sitdPointer = &(ehciInstance->ehciSitdIndexBase[sitdPointer->nextSitdIndex]); /* next sitd */ + + shouldLinkFrame += frameInterval; + currentFrame += frameInterval; + if (shouldLinkFrame >= (int32_t)USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE) + { + shouldLinkFrame = (shouldLinkFrame - USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE); + } + } + + if (currentFrame > (int32_t)(EHCI_MAX_UFRAME_VALUE >> 3)) + { + currentFrame = currentFrame - ((EHCI_MAX_UFRAME_VALUE >> 3) + 1); + } + isoPointer->lastLinkFrame = currentFrame; /* save the last link frame value */ +} + +static usb_status_t USB_HostEhciSitdArrayInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer) +{ + usb_host_ehci_iso_t *isoPointer; + uint32_t sitdNumber = 0; + usb_host_ehci_sitd_t *sitdPointer; + uint32_t dataLength = 0; + uint32_t sitdLength = 0; + uint32_t dataBufferValue; + uint32_t hubNumber; + uint32_t portNumber; + uint32_t address; + uint32_t tmp; + uint8_t index; + + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress, + &address); + + sitdNumber = ((transfer->transferLength - 1 + (ehciPipePointer->pipeCommon.maxPacketSize)) / + (ehciPipePointer->pipeCommon.maxPacketSize)); + /* get sitd array */ + tmp = ehciPipePointer - ehciInstance->ehciPipeIndexBase; /* pipe index */ + /* USB_HostEhciLock(); */ + if (ehciInstance->ehciSitdNumber >= sitdNumber) + { + sitdPointer = ehciInstance->ehciSitdList; + transfer->union1.unitHead = (uint32_t)sitdPointer; + for (index = 1; index < sitdNumber; ++index) + { + sitdPointer->nextSitdIndex = + (((usb_host_ehci_sitd_t *)sitdPointer->nextLinkPointer) - ehciInstance->ehciSitdIndexBase); + sitdPointer = (usb_host_ehci_sitd_t *)sitdPointer->nextLinkPointer; + } + sitdPointer->nextSitdIndex = 0xFF; + ehciInstance->ehciSitdList = (usb_host_ehci_sitd_t *)sitdPointer->nextLinkPointer; + ehciInstance->ehciSitdNumber -= sitdNumber; + } + else + { + /* USB_HostEhciUnlock(); */ + return kStatus_USB_Error; + } + /* USB_HostEhciUnlock(); */ + transfer->union2.unitTail = (uint32_t)sitdPointer; + /* initialize sitd array */ + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceHubNumber, + &hubNumber); + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDevicePortNumber, + &portNumber); + sitdPointer = (usb_host_ehci_sitd_t *)transfer->union1.unitHead; + dataLength = transfer->transferLength; + while (sitdNumber--) + { + USB_HostEhciZeroMem((uint32_t *)sitdPointer, 7); + sitdLength = dataLength; + if (sitdLength > ehciPipePointer->pipeCommon.maxPacketSize) + { + sitdLength = ehciPipePointer->pipeCommon.maxPacketSize; + } + dataBufferValue = (uint32_t)(transfer->transferBuffer + (transfer->transferLength - dataLength)); + dataLength -= sitdLength; /* update left data length */ + sitdPointer->transferResults[1] = dataBufferValue; + sitdPointer->transferResults[2] = ((dataBufferValue + 4 * 1024) & 0xFFFFF000U); + sitdPointer->endpointStates[0] = + (((uint32_t)ehciPipePointer->pipeCommon.direction << EHCI_HOST_SITD_DIRECTION_SHIFT) | + (portNumber << EHCI_HOST_SITD_PORT_NUMBER_SHIFT) | (hubNumber << EHCI_HOST_SITD_HUB_ADDR_SHIFT) | + ((uint32_t)ehciPipePointer->pipeCommon.endpointAddress << EHCI_HOST_SITD_ENDPT_SHIFT) | + (address << EHCI_HOST_SITD_DEVICE_ADDRESS_SHIFT)); + sitdPointer->transferResults[0] = + ((sitdLength << EHCI_HOST_SITD_TOTAL_BYTES_SHIFT) | (EHCI_HOST_SITD_STATUS_ACTIVE_MASK)); + + if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) + { + sitdPointer->endpointStates[1] = (((uint32_t)ehciPipePointer->uframeCmask << EHCI_HOST_SITD_CMASK_SHIFT) | + ((uint32_t)ehciPipePointer->uframeSmask << EHCI_HOST_SITD_SMASK_SHIFT)); + + tmp = (sitdLength + 187) / 188; + if (tmp > 1) + { + sitdPointer->transferResults[2] |= (0x01 << EHCI_HOST_SITD_TP_SHIFT); /* for iso split */ + } + else + { + sitdPointer->transferResults[2] |= (0x00 << EHCI_HOST_SITD_TP_SHIFT); /* for iso split */ + } + sitdPointer->transferResults[2] |= (tmp << EHCI_HOST_SITD_TCOUNT_SHIFT); /* for iso split */ + } + + sitdPointer->backPointer = EHCI_HOST_T_INVALID_VALUE; + + sitdPointer = (ehciInstance->ehciSitdIndexBase + sitdPointer->nextSitdIndex); + } + sitdPointer = (usb_host_ehci_sitd_t *)transfer->union2.unitTail; + sitdPointer->transferResults[0] |= (1U << EHCI_HOST_SITD_IOC_SHIFT); /* last set IOC */ + + /* link transfer to usb_host_ehci_iso_t transfer list */ + isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + USB_HostEhciLock(); + if (isoPointer->ehciTransferHead == NULL) + { + transfer->next = NULL; + isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = transfer; + } + else + { + transfer->next = NULL; + isoPointer->ehciTransferTail->next = transfer; + isoPointer->ehciTransferTail = transfer; + } + USB_HostEhciUnlock(); + + /* link itd to frame list (note: initialize frameEntryIndex)*/ + USB_HostEhciLinkSitd(ehciInstance, ehciPipePointer, (void *)transfer->union1.unitHead); + + return kStatus_USB_Success; +} + +static uint32_t USB_HostEhciSitdArrayRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_sitd_t *startSitdPointer, + usb_host_ehci_sitd_t *endSitdPointer) +{ + usb_host_ehci_sitd_t *sitdPointer = startSitdPointer; + uint32_t leftLength = 0; + /* remove itd from frame list */ + while (1) + { + /* record the transfer's result length */ + leftLength += + ((sitdPointer->transferResults[0] & EHCI_HOST_SITD_TOTAL_BYTES_MASK) >> EHCI_HOST_SITD_TOTAL_BYTES_SHIFT); + USB_HostEhciRemoveFromFrame(ehciInstance, (uint32_t)sitdPointer, + sitdPointer->frameEntryIndex); /* remove from the inserted frame list */ + + /* release itd */ + /* USB_HostEhciLock(); */ + sitdPointer->nextLinkPointer = (uint32_t)ehciInstance->ehciSitdList; + ehciInstance->ehciSitdList = sitdPointer; + ehciInstance->ehciSitdNumber++; + /* USB_HostEhciUnlock(); */ + + if (sitdPointer == endSitdPointer) + { + break; + } + + sitdPointer = &(ehciInstance->ehciSitdIndexBase[sitdPointer->nextSitdIndex]); + } + + return leftLength; +} + +static usb_status_t USB_HostEhciSitdArrayDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_iso_t *isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + usb_host_transfer_t *transfer; + usb_host_transfer_t *nextTransfer; + + /* firstly remove the transfer (because host task may occupy to access the resource) */ + USB_HostEhciLock(); + transfer = isoPointer->ehciTransferHead; + isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = NULL; + USB_HostEhciUnlock(); + + while (transfer != NULL) + { + nextTransfer = transfer->next; + /* remove sitd from frame list and release itd */ + transfer->transferSofar = + transfer->transferLength - USB_HostEhciSitdArrayRelease(ehciInstance, + (usb_host_ehci_sitd_t *)transfer->union1.unitHead, + (usb_host_ehci_sitd_t *)transfer->union2.unitTail); + /* transfer callback */ + transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel); + /* next transfer */ + transfer = nextTransfer; + } + + return kStatus_USB_Success; +} +#endif /* USB_HOST_CONFIG_EHCI_MAX_SITD */ + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) +static uint32_t USB_HostEhciGetItdLinkFrame(usb_host_ehci_instance_t *ehciInstance, + uint32_t lastLinkUframe, + uint16_t startUframe, + uint16_t uframeInterval) +{ + int32_t shouldLinkUframe; + int32_t currentUframe; + int32_t distance; + + if (lastLinkUframe != 0xFFFF) + { + shouldLinkUframe = lastLinkUframe + uframeInterval; + if (shouldLinkUframe > (int32_t)EHCI_MAX_UFRAME_VALUE) + { + shouldLinkUframe = shouldLinkUframe - (EHCI_MAX_UFRAME_VALUE + 1); + } + currentUframe = (ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + distance = ((shouldLinkUframe - currentUframe + EHCI_MAX_UFRAME_VALUE + 1) & + EHCI_MAX_UFRAME_VALUE); /* get the distance */ + /* shouldLinkUframe has add uframeInterval, think about the align with interval, so here add (uframeInterval + * * 2) */ + if ((distance <= (int32_t)(USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER + (uframeInterval * 2))) && (distance > 2)) + { + currentUframe = shouldLinkUframe; + } + else /* re-link */ + { + currentUframe = + ((uint32_t)(currentUframe + USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER) & EHCI_MAX_UFRAME_VALUE); + if (currentUframe > (int32_t)EHCI_MAX_UFRAME_VALUE) + { + currentUframe = currentUframe - (EHCI_MAX_UFRAME_VALUE + 1); + } + /* uframe should align with interval */ + currentUframe -= startUframe; + currentUframe = ((uint32_t)(currentUframe + uframeInterval - 1) & + (~((uint32_t)uframeInterval - 1))); /* uframeInterval is power of 2 */ + currentUframe += startUframe; + } + } + else + { + currentUframe = (ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + currentUframe = ((uint32_t)(currentUframe + USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER) & EHCI_MAX_UFRAME_VALUE); + /* uframe should align with interval */ + currentUframe -= startUframe; + currentUframe = ((uint32_t)(currentUframe + uframeInterval - 1) & + (~((uint32_t)uframeInterval - 1))); /* uframeInterval is power of 2 */ + currentUframe += startUframe; + } + + return currentUframe; +} + +static usb_status_t USB_HostEhciItdArrayInit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer) +{ + usb_host_ehci_iso_t *isoPointer; + usb_host_ehci_itd_t *itdPointer = NULL; + usb_host_ehci_itd_t *tmpItdPointer; + uint32_t dataLength; /* the remaining data for sending */ + uint32_t transactionLength; /* the initializing transaction descriptor data length */ + uint32_t itdBufferValue; + uint32_t itdBufferBaseValue; /* for calculating PG value */ + uint32_t address; + uint32_t lastShouldLinkUframe; + uint32_t linkUframe; + uint32_t minDataPerItd = ehciPipePointer->pipeCommon.numberPerUframe * ehciPipePointer->pipeCommon.maxPacketSize; + uint8_t maxItdNumber; + uint8_t index = 0; + + isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress, + &address); + + /* max needed itd number, the actual needed number may be less because micro-frame interval may be less than 8 */ + maxItdNumber = ((transfer->transferLength - 1 + minDataPerItd) / minDataPerItd); + if (ehciPipePointer->uframeInterval < 8) + { + maxItdNumber = ((maxItdNumber * ehciPipePointer->uframeInterval + 7) / 8) + 1; + } + if (maxItdNumber > ehciInstance->ehciItdNumber) + { + return kStatus_USB_Error; + } + + /* link transfer to usb_host_ehci_iso_t transfer list */ + transfer->next = NULL; + /* USB_HostEhciLock(); */ + if (isoPointer->ehciTransferHead == NULL) + { + isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = transfer; + } + else + { + isoPointer->ehciTransferTail->next = transfer; + isoPointer->ehciTransferTail = transfer; + } + /* USB_HostEhciUnlock(); */ + + dataLength = transfer->transferLength; + transfer->union1.unitHead = (uint32_t)NULL; + /* get the link micro-frame */ + lastShouldLinkUframe = USB_HostEhciGetItdLinkFrame( + ehciInstance, isoPointer->lastLinkFrame, + (uint16_t)((ehciPipePointer->startFrame << 3) + ehciPipePointer->startUframe), ehciPipePointer->uframeInterval); + if (lastShouldLinkUframe > EHCI_MAX_UFRAME_VALUE) + { + linkUframe = lastShouldLinkUframe - (EHCI_MAX_UFRAME_VALUE + 1); + } + else + { + linkUframe = lastShouldLinkUframe; + } + while (dataLength) + { + /* get one idle itd */ + tmpItdPointer = ehciInstance->ehciItdList; + ehciInstance->ehciItdList = (usb_host_ehci_itd_t *)tmpItdPointer->nextLinkPointer; + ehciInstance->ehciItdNumber -= 1; + if (tmpItdPointer == NULL) + { + return kStatus_USB_Error; /* this should not reach */ + } + tmpItdPointer->nextItdPointer = NULL; + + /* use the itd */ + if (transfer->union1.unitHead == (uint32_t)NULL) /* first itd */ + { + transfer->union1.unitHead = (uint32_t)tmpItdPointer; + } + else /* link itd list */ + { + itdPointer->nextItdPointer = tmpItdPointer; + } + itdPointer = tmpItdPointer; + + /* itd has been set to all zero when releasing */ + itdBufferBaseValue = itdBufferValue = + (uint32_t)(transfer->transferBuffer + (transfer->transferLength - dataLength)); + for (index = 0; index < 7; ++index) + { + itdPointer->bufferPointers[index] = ((itdBufferBaseValue + (index * 4 * 1024)) & 0xFFFFF000U); + } + /* initialize iTD common fields */ + itdPointer->bufferPointers[0] |= + (((uint32_t)ehciPipePointer->pipeCommon.endpointAddress << EHCI_HOST_ITD_ENDPT_SHIFT) | + (address << EHCI_HOST_ITD_DEVICE_ADDRESS_SHIFT)); + itdPointer->bufferPointers[1] |= + (((uint32_t)ehciPipePointer->pipeCommon.direction << EHCI_HOST_ITD_DIRECTION_SHIFT) | + ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_ITD_MAX_PACKET_SIZE_SHIFT)); + itdPointer->bufferPointers[2] |= (ehciPipePointer->pipeCommon.numberPerUframe); + /* initialize transaction descriptors */ + for (index = (linkUframe & 0x0007); index < 8; index += ehciPipePointer->uframeInterval) + { + transactionLength = ((dataLength > minDataPerItd) ? minDataPerItd : dataLength); + /* initialize the uframeIndex's transaction descriptor in itd */ + itdPointer->transactions[index] = + ((EHCI_HOST_ITD_STATUS_ACTIVE_MASK) | (transactionLength << EHCI_HOST_ITD_TRANSACTION_LEN_SHIFT) | + ((((itdBufferValue & 0xFFFFF000U) - (itdBufferBaseValue & 0xFFFFF000U)) >> + EHCI_HOST_ITD_BUFFER_POINTER_SHIFT) + << EHCI_HOST_ITD_PG_SHIFT) | + (itdBufferValue & EHCI_HOST_ITD_TRANSACTION_OFFSET_MASK)); + dataLength -= transactionLength; + itdBufferValue += transactionLength; + if (dataLength <= 0) + { + break; + } + } + } + + transfer->union2.unitTail = (uint32_t)itdPointer; + itdPointer->transactions[index] |= (1 << EHCI_HOST_ITD_IOC_SHIFT); /* last set IOC */ + + /* link itd to frame list (note: initialize frameEntryIndex)*/ + while (itdPointer) + { + itdPointer->frameEntryIndex = linkUframe; + /* add to frame head */ + itdPointer->nextLinkPointer = ((uint32_t *)ehciInstance->ehciFrameList)[linkUframe >> 3]; + *(uint32_t *)((uint32_t *)ehciInstance->ehciFrameList)[linkUframe >> 3] = + ((uint32_t)itdPointer | EHCI_HOST_POINTER_TYPE_ITD); + itdPointer = itdPointer->nextItdPointer; + if (itdPointer == NULL) + { + break; + } + + linkUframe += ehciPipePointer->uframeInterval; + lastShouldLinkUframe += ehciPipePointer->uframeInterval; + if (linkUframe >= (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE << 3)) + { + linkUframe = (linkUframe - (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE << 3)); + } + } + + if (lastShouldLinkUframe > EHCI_MAX_UFRAME_VALUE) + { + lastShouldLinkUframe = lastShouldLinkUframe - (EHCI_MAX_UFRAME_VALUE + 1); + } + isoPointer->lastLinkFrame = lastShouldLinkUframe; + + return kStatus_USB_Success; +} + +static uint32_t USB_HostEhciItdArrayRelease(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_itd_t *startItdPointer, + usb_host_ehci_itd_t *endItdPointer) +{ + usb_host_ehci_itd_t *itdPointer = startItdPointer; + uint8_t index; + uint32_t doneLength = 0; + + /* remove itd from frame list */ + while (1) + { + /* record the transfer's result length */ + for (index = 0; index < 8; ++index) + { + doneLength += ((itdPointer->transactions[index] & EHCI_HOST_ITD_TRANSACTION_LEN_MASK) >> + EHCI_HOST_ITD_TRANSACTION_LEN_SHIFT); + } + + USB_HostEhciRemoveFromFrame(ehciInstance, (uint32_t)itdPointer, + itdPointer->frameEntryIndex); /* remove from the inserted frame list */ + + /* release itd */ + /* USB_HostEhciLock(); */ + USB_HostEhciZeroMem((uint32_t *)itdPointer, sizeof(usb_host_ehci_itd_t) >> 2); + itdPointer->nextLinkPointer = (uint32_t)ehciInstance->ehciItdList; + ehciInstance->ehciItdList = itdPointer; + ehciInstance->ehciItdNumber++; + /* USB_HostEhciUnlock(); */ + + if (itdPointer == endItdPointer) + { + break; + } + itdPointer = itdPointer->nextItdPointer; + } + + return doneLength; +} + +static usb_status_t USB_HostEhciItdArrayDeinit(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_iso_t *isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + usb_host_transfer_t *transfer; + usb_host_transfer_t *nextTransfer; + uint32_t doneLength = 0; + + /* firstly remove the transfer (because host task may occupy to access the resource) */ + USB_HostEhciLock(); + transfer = isoPointer->ehciTransferHead; + isoPointer->ehciTransferHead = isoPointer->ehciTransferTail = NULL; + USB_HostEhciUnlock(); + + while (transfer != NULL) + { + nextTransfer = transfer->next; + doneLength = 0; + /* remove itd from frame list and release itd */ + doneLength = USB_HostEhciItdArrayRelease(ehciInstance, (usb_host_ehci_itd_t *)transfer->union1.unitHead, + (usb_host_ehci_itd_t *)transfer->union2.unitTail); + + /* transfer callback */ + if (ehciPipePointer->pipeCommon.direction == USB_OUT) + { + doneLength = transfer->transferLength; + } + transfer->transferSofar = doneLength; + transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferCancel); + + /* next transfer */ + transfer = nextTransfer; + } + + return kStatus_USB_Success; +} +#endif /* USB_HOST_CONFIG_EHCI_MAX_ITD */ + +static usb_status_t USB_HostEhciOpenControlBulk(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_qh_t *qhPointer; + + if (USB_HostEhciQhInit(ehciInstance, ehciPipePointer) != kStatus_USB_Success) /* initialize control/bulk qh */ + { + return kStatus_USB_Error; + } + + qhPointer = (usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + + /* add qh to async */ + qhPointer->horizontalLinkPointer = ehciInstance->shedFirstQh->horizontalLinkPointer; + ehciInstance->shedFirstQh->horizontalLinkPointer = ((uint32_t)qhPointer | EHCI_HOST_POINTER_TYPE_QH); + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciCloseControlBulk(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + volatile usb_host_ehci_qh_t *vltPrevQhPointer; + uint32_t horizontalLinkValue; + + /* remove qh from async schedule */ + if ((ehciInstance->shedFirstQh->horizontalLinkPointer & EHCI_HOST_POINTER_ADDRESS_MASK) == + (uint32_t)ehciPipePointer->ehciQh) /* the removing qh is the first qh in the async list */ + { + USB_HostEhciStopAsync(ehciInstance); + ehciInstance->shedFirstQh->horizontalLinkPointer = + ((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer; + USB_HostEhciStartAsync(ehciInstance); + } + else + { + /* search for the removing qh from the async list */ + vltPrevQhPointer = ehciInstance->shedFirstQh; + while (vltPrevQhPointer != NULL) + { + horizontalLinkValue = vltPrevQhPointer->horizontalLinkPointer; + if ((horizontalLinkValue & EHCI_HOST_T_INVALID_VALUE) || + ((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)ehciPipePointer->ehciQh) || + ((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)ehciInstance->shedFirstQh)) + { + break; + } + + vltPrevQhPointer = (volatile usb_host_ehci_qh_t *)(horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK); + } + + /* remove the qh from async list */ + if ((vltPrevQhPointer != NULL) && (!(horizontalLinkValue & EHCI_HOST_T_INVALID_VALUE)) && + ((horizontalLinkValue & EHCI_HOST_POINTER_ADDRESS_MASK) == (uint32_t)ehciPipePointer->ehciQh)) + { + USB_HostEhciStopAsync(ehciInstance); + vltPrevQhPointer->horizontalLinkPointer = + ((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer; + USB_HostEhciStartAsync(ehciInstance); + } + } + ((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer = + EHCI_HOST_T_INVALID_VALUE; /* invalid next qh link */ + return USB_HostEhciQhDeinit(ehciInstance, ehciPipePointer); /* de-initialize qh and release qh */ +} + +static usb_status_t USB_HostEhciOpenInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_status_t status = kStatus_USB_Success; + uint32_t frameIndex; + + /* allocate bandwidth */ + if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) + { + status = USB_HostBandwidthHsHostAllocateInterrupt(ehciInstance, ehciPipePointer); /* host works as high-speed */ + } + else + { + status = USB_HostBandwidthFslsHostAllocate(ehciInstance, + ehciPipePointer); /* host works as full-speed or low-speed */ + } + + if (status != kStatus_USB_Success) + { + return status; + } + if (USB_HostEhciQhInit(ehciInstance, ehciPipePointer) != kStatus_USB_Success) + { + return kStatus_USB_Error; + } + + /* insert QH to frame list */ + for (frameIndex = ehciPipePointer->startFrame; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; + frameIndex += (ehciPipePointer->uframeInterval / 8)) + { + USB_HostEhciAddQhToFrame(ehciInstance, (uint32_t)ehciPipePointer->ehciQh, frameIndex, + ehciPipePointer->uframeInterval); + } + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciCloseInterrupt(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer) +{ + uint32_t frameIndex; + + /* remove from frame list */ + for (frameIndex = ehciPipePointer->startFrame; frameIndex < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; + frameIndex += (ehciPipePointer->uframeInterval / 8)) + { + USB_HostEhciRemoveFromFrame(ehciInstance, (uint32_t)ehciPipePointer->ehciQh, frameIndex); + } + ((usb_host_ehci_qh_t *)ehciPipePointer->ehciQh)->horizontalLinkPointer |= + EHCI_HOST_T_INVALID_VALUE; /* invalid next qh link */ + + return USB_HostEhciQhDeinit(ehciInstance, ehciPipePointer); /* de-initilaze qh and release qh */ +} + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + +static usb_status_t USB_HostEhciOpenIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_iso_t *isoPointer; + usb_status_t status = kStatus_USB_Success; + + if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) + { + status = USB_HostBandwidthHsHostAllocateIso( + ehciInstance, ehciPipePointer); /* allocate iso bandwidth when host works as high-speed */ + } + else + { + status = USB_HostBandwidthFslsHostAllocate( + ehciInstance, ehciPipePointer); /* allocate iso bandwidth when host works as full-speed or low-speed */ + } + + if (status != kStatus_USB_Success) + { + return status; + } + + /* get usb_host_ehci_iso_t */ + if (ehciInstance->ehciIsoList == NULL) + { + return kStatus_USB_Error; + } + USB_HostEhciLock(); + isoPointer = ehciInstance->ehciIsoList; + ehciInstance->ehciIsoList = ehciInstance->ehciIsoList->next; + USB_HostEhciUnlock(); + isoPointer->lastLinkFrame = 0xFFFF; + ehciPipePointer->ehciQh = isoPointer; + + return status; +} + +static usb_status_t USB_HostEhciCloseIso(usb_host_ehci_instance_t *ehciInstance, usb_host_ehci_pipe_t *ehciPipePointer) +{ + usb_host_ehci_iso_t *isoPointer; + uint32_t speed; + + isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + + if (isoPointer->ehciTransferHead != NULL) + { + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &speed); + if (speed == USB_SPEED_HIGH) + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + USB_HostEhciItdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize itd list and free them */ +#endif + } + else + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + USB_HostEhciSitdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize sitd list and free them */ +#endif + } + } + + /* release usb_host_ehci_iso_t */ + USB_HostEhciLock(); + isoPointer->next = ehciInstance->ehciIsoList; + ehciInstance->ehciIsoList = isoPointer; + USB_HostEhciUnlock(); + return kStatus_USB_Success; +} + +#endif + +static usb_status_t USB_HostEhciResetIP(usb_host_ehci_instance_t *ehciInstance) +{ + /* reset controller */ + ehciInstance->ehciIpBase->USBCMD = USBHS_USBCMD_RST_MASK; + while (ehciInstance->ehciIpBase->USBCMD & USBHS_USBCMD_RST_MASK) + { + } +/* set host mode */ +#if (ENDIANNESS == USB_LITTLE_ENDIAN) + ehciInstance->ehciIpBase->USBMODE |= 0x03; +#else + ehciInstance->ehciIpBase->USBMODE |= (0x03 | (0x01 << USBHS_USBMODE_ES_SHIFT)); +#endif + /* check frame list size */ + if (!(ehciInstance->ehciIpBase->HCCPARAMS & USBHS_HCCPARAMS_PFL_MASK)) + { +#if ((USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE < 8) || (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE > 1024)) + return kStatus_USB_Error; +#endif +#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE & (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE - 1)) + return kStatus_USB_Error; /* frame size must be 1024/512/256/128/64/32/16/8 */ +#endif + } + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciStartIP(usb_host_ehci_instance_t *ehciInstance) +{ + uint32_t tmp = 0; + + if (ehciInstance->ehciIpBase->HCSPARAMS & USBHS_HCSPARAMS_PPC_MASK) /* Ports have power port switches */ + { + /* only has one port */ + tmp = ehciInstance->ehciIpBase->PORTSC1; + tmp &= (~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (tmp | USBHS_PORTSC1_PP_MASK); /* turn on port power */ + } + + /* set frame list size */ + if (ehciInstance->ehciIpBase->HCCPARAMS & USBHS_HCCPARAMS_PFL_MASK) + { +#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE <= 64) + ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_FS2_MASK); +#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 64) + ehciInstance->ehciIpBase->USBCMD |= (0x00 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 32) + ehciInstance->ehciIpBase->USBCMD |= (0x01 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 16) + ehciInstance->ehciIpBase->USBCMD |= (0x02 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 8) + ehciInstance->ehciIpBase->USBCMD |= (0x03 << USBHS_USBCMD_FS_SHIFT); +#endif +#else +#if (USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 1024) + ehciInstance->ehciIpBase->USBCMD |= (0x00 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 512) + ehciInstance->ehciIpBase->USBCMD |= (0x01 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 256) + ehciInstance->ehciIpBase->USBCMD |= (0x02 << USBHS_USBCMD_FS_SHIFT); +#elif(USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE == 128) + ehciInstance->ehciIpBase->USBCMD |= (0x03 << USBHS_USBCMD_FS_SHIFT); +#endif +#endif + } + + /* start the controller */ + ehciInstance->ehciIpBase->USBCMD = USBHS_USBCMD_RS_MASK; + + /* set timer0 */ + ehciInstance->ehciIpBase->GPTIMER0LD = (300 * 1000 - 1); /* 100ms */ + + /* enable interrupt (USB interrupt enable + USB error interrupt enable + port change detect enable + system error + * enable + interrupt on async advance enable) + general purpos Timer 0 Interrupt enable */ + ehciInstance->ehciIpBase->USBINTR |= (0x1000037); + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciCancelPipe(usb_host_ehci_instance_t *ehciInstance, + usb_host_ehci_pipe_t *ehciPipePointer, + usb_host_transfer_t *transfer) +{ + usb_host_ehci_qh_t *qhPointer; +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + usb_host_ehci_iso_t *isoPointer; + uint32_t speed; +#endif + uint8_t cancelPipe = 0; + + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_BULK: + case USB_ENDPOINT_CONTROL: + case USB_ENDPOINT_INTERRUPT: + qhPointer = (usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + if (qhPointer->ehciTransferHead == NULL) /* there is no transfer to cancel */ + { + return kStatus_USB_Success; + } + if (transfer != NULL) + { + if ((qhPointer->ehciTransferHead == transfer) && + (qhPointer->ehciTransferHead == qhPointer->ehciTransferTail)) /* only has this one transfer */ + { + cancelPipe = 1; + } + else + { + cancelPipe = 0; + } + } + else + { + cancelPipe = 1; + } + if (cancelPipe == 1) /* cancel all pipe */ + { + USB_HostEhciQhQtdListDeinit(ehciInstance, ehciPipePointer); /* release all the qtd */ + } + else /* cancel one transfer */ + { + USB_HostEhciTransferQtdListDeinit(ehciInstance, ehciPipePointer, transfer); + } + break; + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + case USB_ENDPOINT_ISOCHRONOUS: + isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; + if (isoPointer->ehciTransferHead == NULL) /* there is no transfer to cancel */ + { + return kStatus_USB_Success; + } + /* cancel all pipe, don't implement canceling transfer for iso */ + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &speed); + if (speed == USB_SPEED_HIGH) + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + USB_HostEhciItdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize itd */ +#endif + } + else + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + USB_HostEhciSitdArrayDeinit(ehciInstance, ehciPipePointer); /* de-initialize sitd */ +#endif + } + break; +#endif + + default: + break; + } + + return kStatus_USB_Success; +} + +static usb_status_t USB_HostEhciControlBus(usb_host_ehci_instance_t *ehciInstance, uint8_t busControl) +{ + usb_status_t status = kStatus_USB_Success; + uint32_t portScRegister; + + switch (busControl) + { + case kUSB_HostBusReset: + /* reset port */ + portScRegister = ehciInstance->ehciIpBase->PORTSC1; + portScRegister &= (~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (portScRegister | USBHS_PORTSC1_PR_MASK); + while (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PR_MASK) + { + } + break; + + case kUSB_HostBusRestart: + ehciInstance->deviceAttached = kEHCIDeviceDetached; + ehciInstance->ehciIpBase->USBINTR |= (USBHS_USBINTR_PCE_MASK); /* enable ehci port change interrupt */ + break; + + case kUSB_HostBusEnableAttach: /* enable device attach */ + if (ehciInstance->deviceAttached == kEHCIDeviceDetached) + { + ehciInstance->ehciIpBase->USBINTR |= (USBHS_USBINTR_PCE_MASK); /* enable ehci port change interrupt */ + } + break; + + case kUSB_HostBusDisableAttach: /* disable device attach */ + ehciInstance->ehciIpBase->USBINTR &= (~USBHS_USBINTR_PCE_MASK); /* disable ehci port change interrupt */ + break; +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + case kUSB_HostBusSuspend: + if (ehciInstance->ehciIpBase->PORTSC1 && USBHS_PORTSC1_CCS_MASK) + { + /* set timer1 */ + ehciInstance->ehciIpBase->GPTIMER1LD = (1 * 1000); /* 1ms */ + ehciInstance->ehciIpBase->GPTIMER1CTL |= + (USBHS_GPTIMER0CTL_RUN_MASK | USBHS_GPTIMER0CTL_MODE_MASK | USBHS_GPTIMER0CTL_RST_MASK); + + USB_HostEhciStopAsync(ehciInstance); + USB_HostEhciStopPeriodic(ehciInstance); + while (ehciInstance->ehciIpBase->USBSTS & (USBHS_USBSTS_PS_MASK | USBHS_USBSTS_AS_MASK)) + { + __ASM("nop"); + } + ehciInstance->ehciIpBase->PORTSC1 &= ~USBHS_PORTSC1_WKCN_MASK; + ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_WKDS_MASK; + ehciInstance->ehciIpBase->PORTSC1 |= (USBHS_PORTSC1_SUSP_MASK); /* Suspend the device */ + + ehciInstance->matchTick = 0U; + ehciInstance->ehciIpBase->USBINTR |= (USBHS_USBINTR_TIE1_MASK); + ehciInstance->busSuspendStatus = kBus_EhciStartSuspend; + } + else + { + status = kStatus_USB_Error; + } + break; + case kUSB_HostBusResume: + ehciInstance->ehciIpBase->PORTSC1 &= ~(USBHS_PORTSC1_SUSP_MASK); /* Clear Suspend bit */ + ehciInstance->ehciIpBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; + if (ehciInstance->deviceAttached != kEHCIDeviceDetached) + { + ehciInstance->busSuspendStatus = kBus_EhciStartResume; +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciInstance->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; +#else + ehciInstance->ehciIpBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; +#endif + ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_RS_MASK); + ehciInstance->ehciIpBase->PORTSC1 |= (USBHS_PORTSC1_FPR_MASK); /* Resume the device */ + } + else + { + status = kStatus_USB_Error; + } + break; +#endif + default: + status = kStatus_USB_Error; + break; + } + return status; +} + +void USB_HostEhciTransactionDone(usb_host_ehci_instance_t *ehciInstance) +{ + /* process async QH */ + usb_host_ehci_pipe_t *ehciPipePointer; + usb_host_ehci_pipe_t *ehciClearPipePointer = NULL; + volatile usb_host_ehci_qh_t *vltQhPointer; + volatile usb_host_ehci_qtd_t *vltQtdPointer; + usb_host_transfer_t *transfer; + usb_host_transfer_t *nextTransfer; + uint32_t qtdStatus = 0; +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + volatile usb_host_ehci_itd_t *vltItdPointer; + uint8_t index = 0; +#endif +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + volatile usb_host_ehci_sitd_t *vltSitdPointer; +#endif +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + usb_host_ehci_iso_t *isoPointer; + uint32_t dataLength; + uint32_t speed; +#endif + + ehciPipePointer = ehciInstance->ehciRunningPipeList; /* check all the running pipes */ + while (ehciPipePointer != NULL) + { + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_BULK: + case USB_ENDPOINT_INTERRUPT: + case USB_ENDPOINT_CONTROL: + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; /* pipe's qh */ + transfer = vltQhPointer->ehciTransferHead; /* qh's transfer */ + while (transfer != NULL) + { + nextTransfer = transfer->next; + /* normal case */ + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)transfer->union2.unitTail; + if ((vltQtdPointer->transferResults[0] & (EHCI_HOST_QTD_IOC_MASK)) && + (!(vltQtdPointer->transferResults[0] & + EHCI_HOST_QTD_STATUS_ACTIVE_MASK))) /* transfer is done */ + { + qtdStatus = (vltQtdPointer->transferResults[0] & EHCI_HOST_QTD_STATUS_ERROR_MASK); + transfer->transferSofar = + USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), + (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); + transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ? + 0 : + (transfer->transferLength - transfer->transferSofar); + + vltQhPointer->ehciTransferHead = transfer->next; + vltQhPointer->timeOutLabel = 0; + vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; + if (qtdStatus) /* has errors */ + { + if (!(vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QTD_STATUS_ACTIVE_MASK)) + { + vltQhPointer->transferOverlayResults[0] &= + (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + } + if (qtdStatus & EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK) + { + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_TransferFailed); /* transfer fail */ + } + else + { + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_TransferStall); /* transfer stall */ + } + } + else + { + if ((ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_CONTROL) && + (transfer->setupPacket->bRequest == USB_REQUEST_STANDARD_CLEAR_FEATURE) && + (transfer->setupPacket->bmRequestType == USB_REQUEST_TYPE_RECIPIENT_ENDPOINT) && + ((USB_SHORT_FROM_LITTLE_ENDIAN(transfer->setupPacket->wValue) & 0x00FFu) == + USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT)) + { + ehciClearPipePointer = ehciInstance->ehciRunningPipeList; + while (ehciClearPipePointer != NULL) + { + /* only compute bulk and interrupt pipe */ + if (((ehciClearPipePointer->pipeCommon.endpointAddress | + (ehciClearPipePointer->pipeCommon.direction + << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT)) == + (uint8_t)(USB_SHORT_FROM_LITTLE_ENDIAN(transfer->setupPacket->wIndex))) && + (ehciClearPipePointer->pipeCommon.deviceHandle == + ehciPipePointer->pipeCommon.deviceHandle)) + { + break; + } + ehciClearPipePointer = + (usb_host_ehci_pipe_t *)ehciClearPipePointer->pipeCommon.next; + } + + if ((ehciClearPipePointer != NULL) && + ((ehciClearPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT) || + (ehciClearPipePointer->pipeCommon.pipeType == USB_ENDPOINT_BULK))) + { + ((volatile usb_host_ehci_qh_t *)(ehciClearPipePointer->ehciQh)) + ->transferOverlayResults[0] &= (~EHCI_HOST_QTD_DT_MASK); + } + } + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_Success); /* transfer success */ + } + } + else if ((!(vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QTD_STATUS_ACTIVE_MASK)) && + (vltQhPointer->transferOverlayResults[0] & + EHCI_HOST_QH_STATUS_ERROR_MASK)) /* there is error and transfer is done */ + { + qtdStatus = (vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QH_STATUS_ERROR_MASK); + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)(vltQhPointer->currentQtdPointer); + + if (((uint32_t)vltQtdPointer & EHCI_HOST_T_INVALID_VALUE) || + (vltQtdPointer == NULL)) /* the error status is unreasonable */ + { + vltQhPointer->transferOverlayResults[0] &= + (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + } + else + { + /* remove qtd from qh */ + while ((vltQtdPointer != NULL) && (!(vltQtdPointer->transferResults[0] & + EHCI_HOST_QTD_IOC_MASK))) /* find the IOC qtd */ + { + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQtdPointer->nextQtdPointer; + } + + vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + vltQhPointer->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; + vltQhPointer->transferOverlayResults[0] &= + (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + if (vltQtdPointer != NULL) + { + vltQhPointer->nextQtdPointer = vltQtdPointer->nextQtdPointer; + } + + transfer->transferSofar = USB_HostEhciQtdListRelease( + ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), + (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); + transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ? + 0 : + (transfer->transferLength - transfer->transferSofar); + vltQhPointer->ehciTransferHead = transfer->next; + vltQhPointer->timeOutLabel = 0; + vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; + if (qtdStatus & EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK) + { + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_TransferFailed); /* transfer fail */ + } + else + { + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_TransferStall); /* transfer stall */ + } + } + } + else + { + break; + } + transfer = nextTransfer; + } + break; +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + case USB_ENDPOINT_ISOCHRONOUS: + qtdStatus = 0; /* qtdStatus means break here, because there is only one break in while for misra */ + isoPointer = (usb_host_ehci_iso_t *)ehciPipePointer->ehciQh; /* pipe's usb_host_ehci_iso_t */ + transfer = isoPointer->ehciTransferHead; /* usb_host_ehci_iso_t's transfer */ + while (transfer != NULL) + { + nextTransfer = transfer->next; + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, + kUSB_HostGetDeviceSpeed, &speed); + if (speed == USB_SPEED_HIGH) + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + vltItdPointer = + (volatile usb_host_ehci_itd_t *)(transfer->union2.unitTail); /* transfer's last itd */ + for (index = 0; index < 8; ++index) + { + if (vltItdPointer->transactions[index] & EHCI_HOST_ITD_STATUS_ACTIVE_MASK) + { + break; + } + } + if (index == 8) /* transfer is done */ + { + /* remove itd from frame list and release itd */ + dataLength = USB_HostEhciItdArrayRelease(ehciInstance, + (usb_host_ehci_itd_t *)transfer->union1.unitHead, + (usb_host_ehci_itd_t *)transfer->union2.unitTail); + transfer->transferSofar = dataLength; + isoPointer->ehciTransferHead = transfer->next; + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_Success); /* transfer callback success */ + /* TODO: iso callback error */ + } + else + { + qtdStatus = 1; /* break */ + } +#endif + } + else + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + vltSitdPointer = + (volatile usb_host_ehci_sitd_t *)(transfer->union2.unitTail); /* transfer's last sitd */ + if (!(vltSitdPointer->transferResults[0] & + EHCI_HOST_SITD_STATUS_ACTIVE_MASK)) /* transfer is done */ + { + /* remove sitd from frame list and release itd */ + dataLength = USB_HostEhciSitdArrayRelease( + ehciInstance, (usb_host_ehci_sitd_t *)transfer->union1.unitHead, + (usb_host_ehci_sitd_t *)transfer->union2.unitTail); + transfer->transferSofar = dataLength; + isoPointer->ehciTransferHead = transfer->next; + transfer->callbackFn(transfer->callbackParam, transfer, + kStatus_USB_Success); /* transfer callback success */ + /* TODO: iso callback error */ + } + else + { + qtdStatus = 1; /* break */ + } +#endif + } + if (qtdStatus == 1) + { + break; + } + transfer = nextTransfer; + } + break; +#endif + + default: + break; + } + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } +} + +static void USB_HostEhciPortChange(usb_host_ehci_instance_t *ehciInstance) +{ + /* note: only has one port */ + uint32_t portScRegister = ehciInstance->ehciIpBase->PORTSC1; + int32_t sofStart = 0; + int32_t sofCount = 0; + uint32_t index; + + if (portScRegister & USBHS_PORTSC1_CSC_MASK) /* connection status change */ + { + sofStart = (int32_t)(ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + + /* process CSC bit */ + while (1) + { + portScRegister = ehciInstance->ehciIpBase->PORTSC1; + if (portScRegister & USBHS_PORTSC1_CSC_MASK) + { + /* clear csc bit */ + portScRegister = ehciInstance->ehciIpBase->PORTSC1; + portScRegister &= (~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (portScRegister | USBHS_PORTSC1_CSC_MASK); + } + sofCount = (int32_t)(ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE); + if (((sofCount - sofStart + EHCI_MAX_UFRAME_VALUE + 1) & EHCI_MAX_UFRAME_VALUE) > + (1 * 8)) /* delay 1ms to clear CSC */ + { + break; + } + } + } + + /* process CCS bit */ + portScRegister = ehciInstance->ehciIpBase->PORTSC1; + if (portScRegister & USBHS_PORTSC1_CCS_MASK) /* process attach */ + { + if ((ehciInstance->deviceAttached == kEHCIDevicePhyAttached) || + (ehciInstance->deviceAttached == kEHCIDeviceAttached)) + { + return; + } +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + ehciInstance->busSuspendStatus = kBus_EhciIdle; + ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); +#endif + for (index = 0; index < USB_HOST_EHCI_PORT_CONNECT_DEBOUNCE_DELAY; ++index) + { + USB_HostEhciDelay(ehciInstance->ehciIpBase, 1); + if (!(ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK)) + { + break; + } + } + if (index < USB_HOST_EHCI_PORT_CONNECT_DEBOUNCE_DELAY) /* CCS is cleared */ + { + ehciInstance->deviceAttached = kEHCIDeviceDetached; + return; + } + /* reset port */ + portScRegister = ehciInstance->ehciIpBase->PORTSC1; + portScRegister &= (~EHCI_PORTSC1_W1_BITS); + ehciInstance->ehciIpBase->PORTSC1 = (portScRegister | USBHS_PORTSC1_PR_MASK); + while (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PR_MASK) + { + } + ehciInstance->firstDeviceSpeed = + ((ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_PSPD_MASK) >> USBHS_PORTSC1_PSPD_SHIFT); + /* enable ehci phy disconnection */ + if (ehciInstance->firstDeviceSpeed == USB_SPEED_HIGH) + { + USB_EhcihostPhyDisconnectDetectCmd(ehciInstance->controllerId, 1); + } + + /* wait for reset */ + USB_HostEhciDelay(ehciInstance->ehciIpBase, USB_HOST_EHCI_PORT_RESET_DELAY); + /* process attach */ + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_DEVICE_ATTACH); + /* gpt timer start */ + ehciInstance->ehciIpBase->GPTIMER0CTL |= + (USBHS_GPTIMER0CTL_RUN_MASK | USBHS_GPTIMER0CTL_MODE_MASK | USBHS_GPTIMER0CTL_RST_MASK); + ehciInstance->deviceAttached = kEHCIDevicePhyAttached; + } + else + { + if ((ehciInstance->deviceAttached == kEHCIDevicePhyAttached) || + (ehciInstance->deviceAttached == kEHCIDeviceAttached)) + { +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + ehciInstance->busSuspendStatus = kBus_EhciIdle; + ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); +#endif + /* disable ehci phy disconnection */ + USB_EhcihostPhyDisconnectDetectCmd(ehciInstance->controllerId, 0); + /* disable async and periodic */ + USB_HostEhciStopAsync(ehciInstance); + USB_HostEhciStopPeriodic(ehciInstance); + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_DEVICE_DETACH); + } + } +} + +static void USB_HostEhciTimer0(usb_host_ehci_instance_t *ehciInstance) +{ + volatile usb_host_ehci_qh_t *vltQhPointer; + volatile usb_host_ehci_qtd_t *vltQtdPointer; + usb_host_transfer_t *transfer; + uint32_t backValue; + volatile uint32_t *totalBytesAddress = NULL; + usb_host_ehci_pipe_t *ehciPipePointer = ehciInstance->ehciRunningPipeList; + uint8_t timeoutLabel; + + while (ehciPipePointer != NULL) + { + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_BULK: + case USB_ENDPOINT_CONTROL: + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; /* pipe's qh */ + transfer = vltQhPointer->ehciTransferHead; /* qh's transfer */ + if ((transfer != NULL)) /* there is transfering data */ + { + timeoutLabel = 0; + if (ehciInstance->deviceAttached != kEHCIDeviceAttached) + { + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)transfer->union2.unitTail; + + vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */ + vltQhPointer->transferOverlayResults[0] &= + (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + timeoutLabel = 1; + } + else + { + if (vltQhPointer->transferOverlayResults[0] & EHCI_HOST_QTD_STATUS_ACTIVE_MASK) + { + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQhPointer->currentQtdPointer; + totalBytesAddress = &(vltQhPointer->transferOverlayResults[0]); + } + else + { + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)transfer->union2.unitTail; + totalBytesAddress = ((uint32_t *)vltQtdPointer + 2); + } + + backValue = + (((*totalBytesAddress) & EHCI_HOST_QTD_TOTAL_BYTES_MASK) >> + EHCI_HOST_QTD_TOTAL_BYTES_SHIFT); /* backValue is used for total bytes to transfer */ + if (vltQhPointer->timeOutLabel != backValue) /* use total bytes to reflect the time out */ + { + vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; + vltQhPointer->timeOutLabel = backValue; + } + else + { + /* time out when the total bytes don't change for the duration + * USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE + */ + (vltQhPointer->timeOutValue)--; + if (vltQhPointer->timeOutValue == 0) + { + /* stop the qh schedule */ + USB_HostEhciStopAsync(ehciInstance); + if (backValue != (((*totalBytesAddress) & EHCI_HOST_QTD_TOTAL_BYTES_MASK) >> + EHCI_HOST_QTD_TOTAL_BYTES_SHIFT)) + { + USB_HostEhciStartAsync(ehciInstance); + } + else + { + vltQhPointer->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; /* invalid next qtd */ + vltQhPointer->transferOverlayResults[0] &= + (~EHCI_HOST_QTD_STATUS_MASK); /* clear error status */ + USB_HostEhciStartAsync(ehciInstance); + timeoutLabel = 1; + } + } + } + } + + if (timeoutLabel == 1) + { + /* remove qtd from qh */ + while ((vltQtdPointer != NULL) && + (!(vltQtdPointer->transferResults[0] & EHCI_HOST_QTD_IOC_MASK)) && + (vltQtdPointer != (usb_host_ehci_qtd_t *)vltQhPointer->ehciTransferTail)) + { + vltQtdPointer = (volatile usb_host_ehci_qtd_t *)vltQtdPointer->nextQtdPointer; + } + if ((vltQtdPointer != NULL) && (!(vltQtdPointer->nextQtdPointer & EHCI_HOST_T_INVALID_VALUE))) + { + vltQhPointer->nextQtdPointer = + vltQtdPointer->nextQtdPointer; /* start qh if there are other qtd that don't belong to + the transfer */ + } + transfer->transferSofar = + USB_HostEhciQtdListRelease(ehciInstance, (usb_host_ehci_qtd_t *)(transfer->union1.unitHead), + (usb_host_ehci_qtd_t *)(transfer->union2.unitTail)); + transfer->transferSofar = (transfer->transferLength < transfer->transferSofar) ? + 0 : + (transfer->transferLength - transfer->transferSofar); + + vltQhPointer->ehciTransferHead = transfer->next; + vltQhPointer->timeOutValue = USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE; + transfer->callbackFn(transfer->callbackParam, transfer, kStatus_USB_TransferFailed); + } + } + break; + default: + break; + } + ehciPipePointer = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } +} + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) +static void USB_HostEhciTimer1(usb_host_ehci_instance_t *ehciInstance) +{ + if (ehciInstance->deviceAttached != kEHCIDeviceDetached) + { + if (kBus_EhciStartSuspend == ehciInstance->busSuspendStatus) + { + usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; + + if (0 == ehciInstance->matchTick) + { + ehciInstance->matchTick = hostPointer->hwTick; + } + else + { + if ((hostPointer->hwTick - ehciInstance->matchTick) >= 5) + { + ehciInstance->ehciIpBase->USBCMD &= ~USBHS_USBCMD_RS_MASK; + ehciInstance->ehciIpBase->USBSTS |= USBHS_USBSTS_SRI_MASK; +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) +#if 0 + ehciInstance->registerPhyBase->CTRL |= USBPHY_CTRL_ENVBUSCHG_WKUP_MASK + | USBPHY_CTRL_ENIDCHG_WKUP_MASK + | USBPHY_CTRL_ENDPDMCHG_WKUP_MASK + | USBPHY_CTRL_ENIRQRESUMEDETECT_MASK + ; +#endif +#endif + ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_PHCD_MASK; + + ehciInstance->registerPhyBase->PWD = 0xFFFFFFFFU; + + while (ehciInstance->registerPhyBase->CTRL & (USBPHY_CTRL_UTMI_SUSPENDM_MASK)) + { + __ASM("nop"); + } + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciInstance->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK | + USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK | + USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK; + ehciInstance->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WIE_MASK; +#else + ehciInstance->ehciIpBase->USBGENCTRL = USBHS_USBGENCTRL_WU_IE_MASK; +#endif + ehciInstance->registerPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; + hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, + kUSB_HostEventSuspended); /* call host callback function */ + ehciInstance->busSuspendStatus = kBus_EhciSuspended; + } + } + } + else if (kBus_EhciStartResume == ehciInstance->busSuspendStatus) + { + usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; + if (!(ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_FPR_MASK)) + { + ehciInstance->ehciIpBase->PORTSC1 &= ~USBHS_PORTSC1_WKDS_MASK; + if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK) + { + USB_HostEhciStartAsync(ehciInstance); + USB_HostEhciStartPeriodic(ehciInstance); + } + hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, + kUSB_HostEventResumed); /* call host callback function */ + hostPointer->suspendedDevice = NULL; + ehciInstance->busSuspendStatus = kBus_EhciIdle; + ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); + } + } + else + { + } + } + else + { + ehciInstance->busSuspendStatus = kBus_EhciIdle; + ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); + } +} +#endif + +usb_status_t USB_HostEhciCreate(uint8_t controllerId, + usb_host_handle upperLayerHandle, + usb_host_controller_handle *controllerHandle) +{ + uint32_t index = 0; + usb_osa_status_t osaStatus; + usb_host_ehci_instance_t *ehciInstance; + uint32_t usbhsBaseAddrs[] = USBHS_BASE_ADDRS; + usb_host_ehci_data_t *usbHostEhciData[] = USB_HOST_EHCI_DATA_ARRAY; + uint8_t *usbHostEhciFrameList[] = USB_HOST_EHCI_FRAME_LIST_ARRAY; + uint32_t *framePointer; + + if ((uint32_t)(controllerId - kUSB_ControllerEhci0) >= (sizeof(usbhsBaseAddrs) / sizeof(usbhsBaseAddrs[0]))) + { + return kStatus_USB_ControllerNotFound; + } + + *controllerHandle = NULL; + ehciInstance = (usb_host_ehci_instance_t *)USB_OsaMemoryAllocate( + sizeof(usb_host_ehci_instance_t)); /* malloc host ehci instance */ + if (ehciInstance == NULL) + { + return kStatus_USB_AllocFail; + } + ehciInstance->controllerId = controllerId; + ehciInstance->hostHandle = upperLayerHandle; + ehciInstance->deviceAttached = kEHCIDeviceDetached; + ehciInstance->ehciIpBase = (USBHS_Type *) + usbhsBaseAddrs[controllerId - kUSB_ControllerEhci0]; /* operate ehci ip through the base address */ +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + ehciInstance->busSuspendStatus = kBus_EhciIdle; + +#if (defined(USB_HOST_CONFIG_LOW_POWER_MODE) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + ehciInstance->registerPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciInstance->registerNcBase = (USBNC_Type *)USB_EhciNCGetBase(controllerId); +#endif + +#endif + +#endif + + if (USB_HostEhciResetIP(ehciInstance) != kStatus_USB_Success) /* reset ehci ip */ + { + USB_OsaMemoryFree(ehciInstance); + return kStatus_USB_Error; + } + + /* initialize ehci frame list */ + ehciInstance->ehciFrameList = usbHostEhciFrameList[ehciInstance->controllerId - kUSB_ControllerEhci0]; + + /* initialize ehci units */ + ehciInstance->ehciUnitBase = (uint32_t *)(usbHostEhciData[ehciInstance->controllerId - kUSB_ControllerEhci0]); + /* initialize qh/qtd/itd/sitd/iso list */ + ehciInstance->ehciQhList = (usb_host_ehci_qh_t *)((uint32_t)(ehciInstance->ehciUnitBase)); + ehciInstance->ehciQtdHead = (usb_host_ehci_qtd_t *)((uint32_t)ehciInstance->ehciQhList + + (sizeof(usb_host_ehci_qh_t) * USB_HOST_CONFIG_EHCI_MAX_QH)); + ehciInstance->ehciItdList = (usb_host_ehci_itd_t *)((uint32_t)ehciInstance->ehciQtdHead + + (sizeof(usb_host_ehci_qtd_t) * USB_HOST_CONFIG_EHCI_MAX_QTD)); + ehciInstance->ehciSitdList = ehciInstance->ehciSitdIndexBase = + (usb_host_ehci_sitd_t *)((uint32_t)ehciInstance->ehciItdList + + (sizeof(usb_host_ehci_itd_t) * USB_HOST_CONFIG_EHCI_MAX_ITD)); + ehciInstance->ehciIsoList = (usb_host_ehci_iso_t *)((uint32_t)ehciInstance->ehciSitdList + + (sizeof(usb_host_ehci_sitd_t) * USB_HOST_CONFIG_EHCI_MAX_SITD)); + ehciInstance->ehciPipeIndexBase = + (usb_host_ehci_pipe_t *)((uint32_t)ehciInstance->ehciIsoList + + (sizeof(usb_host_ehci_iso_t) * USB_HOST_EHCI_ISO_NUMBER)); + for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_QH; ++index) + { + ehciInstance->ehciQhList[index - 1].horizontalLinkPointer = (uint32_t)(&ehciInstance->ehciQhList[index]); + } + ehciInstance->ehciQhList[USB_HOST_CONFIG_EHCI_MAX_QH - 1].horizontalLinkPointer = (uint32_t)NULL; + for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_QTD; ++index) + { + ehciInstance->ehciQtdHead[index - 1].nextQtdPointer = (uint32_t)(&ehciInstance->ehciQtdHead[index]); + } + ehciInstance->ehciQtdNumber = USB_HOST_CONFIG_EHCI_MAX_QTD; + ehciInstance->ehciQtdHead[USB_HOST_CONFIG_EHCI_MAX_QTD - 1].nextQtdPointer = (uint32_t)NULL; + ehciInstance->ehciQtdTail = &ehciInstance->ehciQtdHead[USB_HOST_CONFIG_EHCI_MAX_QTD - 1]; + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_ITD; ++index) + { + ehciInstance->ehciItdList[index - 1].nextLinkPointer = (uint32_t)(&ehciInstance->ehciItdList[index]); + } + ehciInstance->ehciItdNumber = USB_HOST_CONFIG_EHCI_MAX_ITD; + ehciInstance->ehciItdList[USB_HOST_CONFIG_EHCI_MAX_ITD - 1].nextLinkPointer = (uint32_t)NULL; +#endif /* USB_HOST_CONFIG_EHCI_MAX_ITD */ + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + for (index = 1; index < USB_HOST_CONFIG_EHCI_MAX_SITD; ++index) + { + ehciInstance->ehciSitdList[index - 1].nextLinkPointer = (uint32_t)(&ehciInstance->ehciSitdList[index]); + } + ehciInstance->ehciSitdNumber = USB_HOST_CONFIG_EHCI_MAX_SITD; + ehciInstance->ehciSitdList[USB_HOST_CONFIG_EHCI_MAX_SITD - 1].nextLinkPointer = (uint32_t)NULL; +#endif /* USB_HOST_CONFIG_EHCI_MAX_SITD */ + +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + for (index = 1; index < USB_HOST_EHCI_ISO_NUMBER; ++index) + { + ehciInstance->ehciIsoList[index - 1].next = &ehciInstance->ehciIsoList[index]; + } + ehciInstance->ehciIsoList[USB_HOST_EHCI_ISO_NUMBER - 1].next = NULL; +#endif + + /* initialize pipes */ + ehciInstance->ehciPipeList = ehciInstance->ehciPipeIndexBase; + for (index = 1; index < USB_HOST_CONFIG_MAX_PIPES; ++index) + { + ehciInstance->ehciPipeList[index - 1].pipeCommon.next = (usb_host_pipe_t *)&ehciInstance->ehciPipeList[index]; + } + /* initialize mutext */ + osaStatus = USB_OsaMutexCreate(&ehciInstance->ehciMutex); + if (osaStatus != kStatus_USB_OSA_Success) + { +#ifdef HOST_ECHO + usb_echo("ehci mutex init fail\r\n"); +#endif + USB_OsaMemoryFree(ehciInstance); + return kStatus_USB_Error; + } + /* initialize task event */ + osaStatus = USB_OsaEventCreate(&ehciInstance->taskEventHandle, 1); + if (osaStatus != kStatus_USB_OSA_Success) + { +#ifdef HOST_ECHO + usb_echo("ehci event init fail\r\n"); +#endif + USB_OsaMutexDestroy(ehciInstance->ehciMutex); + USB_OsaMemoryFree(ehciInstance); + return kStatus_USB_Error; + } + + /* initialize first qh */ + ehciInstance->shedFirstQh = ehciInstance->ehciQhList; + ehciInstance->ehciQhList = + (usb_host_ehci_qh_t *)(ehciInstance->ehciQhList->horizontalLinkPointer & EHCI_HOST_POINTER_ADDRESS_MASK); + ehciInstance->shedFirstQh->staticEndpointStates[0] |= (1 << EHCI_HOST_QH_H_SHIFT); /* first qh */ + ehciInstance->shedFirstQh->horizontalLinkPointer = EHCI_HOST_T_INVALID_VALUE; + ehciInstance->shedFirstQh->currentQtdPointer = EHCI_HOST_T_INVALID_VALUE; + ehciInstance->shedFirstQh->nextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + ehciInstance->shedFirstQh->alternateNextQtdPointer = EHCI_HOST_T_INVALID_VALUE; + ehciInstance->shedFirstQh->horizontalLinkPointer = + (uint32_t)((uint32_t)(ehciInstance->shedFirstQh) | EHCI_HOST_POINTER_TYPE_QH); + + /* initialize periodic list */ + framePointer = (uint32_t *)ehciInstance->ehciFrameList; + for (index = 0; index < USB_HOST_CONFIG_EHCI_FRAME_LIST_SIZE; ++index) + { + framePointer[index] = EHCI_HOST_T_INVALID_VALUE; + } + + USB_HostEhciStartIP(ehciInstance); /* start ehci ip */ + + *controllerHandle = ehciInstance; + + return kStatus_USB_Success; +} + +usb_status_t USB_HostEhciDestory(usb_host_controller_handle controllerHandle) +{ + usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; + + /* disable all interrupts */ + ehciInstance->ehciIpBase->USBINTR = 0; + /* stop the controller */ + ehciInstance->ehciIpBase->USBCMD = 0; + /* free memory */ + USB_OsaMutexDestroy(ehciInstance->ehciMutex); + USB_OsaEventDestroy(ehciInstance->taskEventHandle); + USB_OsaMemoryFree(ehciInstance); + + return kStatus_USB_Success; +} + +usb_status_t USB_HostEhciOpenPipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle *pipeHandle, + usb_host_pipe_init_t *pipeInit) +{ + usb_host_ehci_pipe_t *ehciPipePointer = NULL; + usb_status_t status; + uint32_t speed; + usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; + + /* get one pipe */ + USB_HostEhciLock(); + if (ehciInstance->ehciPipeList != NULL) + { + ehciPipePointer = ehciInstance->ehciPipeList; + ehciInstance->ehciPipeList = (usb_host_ehci_pipe_t *)ehciPipePointer->pipeCommon.next; + } + USB_HostEhciUnlock(); + if (ehciPipePointer == NULL) + { +#ifdef HOST_ECHO + usb_echo("ehci open pipe failed\r\n"); +#endif + return kStatus_USB_Busy; + } + + /* initialize pipe informations */ + USB_HostEhciZeroMem((uint32_t *)ehciPipePointer, sizeof(usb_host_ehci_pipe_t) / 4); + ehciPipePointer->pipeCommon.deviceHandle = pipeInit->devInstance; + ehciPipePointer->pipeCommon.endpointAddress = pipeInit->endpointAddress; + ehciPipePointer->pipeCommon.direction = pipeInit->direction; + ehciPipePointer->pipeCommon.interval = pipeInit->interval; + ehciPipePointer->pipeCommon.maxPacketSize = pipeInit->maxPacketSize; + ehciPipePointer->pipeCommon.pipeType = pipeInit->pipeType; + ehciPipePointer->pipeCommon.numberPerUframe = pipeInit->numberPerUframe; + if (ehciPipePointer->pipeCommon.numberPerUframe == 0) + { + ehciPipePointer->pipeCommon.numberPerUframe = 1; + } + ehciPipePointer->pipeCommon.nakCount = pipeInit->nakCount; + ehciPipePointer->pipeCommon.nextdata01 = 0; + ehciPipePointer->ehciQh = NULL; + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, &speed); + if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_ISOCHRONOUS) + { + ehciPipePointer->pipeCommon.interval = + (1 << (ehciPipePointer->pipeCommon.interval - 1)); /* iso interval is the power of 2 */ + } + else if (ehciPipePointer->pipeCommon.pipeType == USB_ENDPOINT_INTERRUPT) + { + if (speed == USB_SPEED_HIGH) + { + ehciPipePointer->pipeCommon.interval = + (1 << (ehciPipePointer->pipeCommon.interval - 1)); /* HS interrupt interval is the power of 2 */ + } + else + { + ehciPipePointer->pipeCommon.interval = USB_HostEhciGet2PowerValue( + ehciPipePointer->pipeCommon + .interval); /* FS/LS interrupt interval should be the power of 2, it is used for ehci bandwidth */ + } + } + else + { + } + + /* save the micro-frame interval, it is convenient for the interval process */ + if (speed == USB_SPEED_HIGH) + { + ehciPipePointer->uframeInterval = ehciPipePointer->pipeCommon.interval; + } + else + { + ehciPipePointer->uframeInterval = 8 * ehciPipePointer->pipeCommon.interval; + } + + /* open pipe */ + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_CONTROL: + case USB_ENDPOINT_BULK: + status = USB_HostEhciOpenControlBulk(ehciInstance, ehciPipePointer); + break; + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + case USB_ENDPOINT_ISOCHRONOUS: + status = USB_HostEhciOpenIso(ehciInstance, ehciPipePointer); + break; +#endif + + case USB_ENDPOINT_INTERRUPT: + status = USB_HostEhciOpenInterrupt(ehciInstance, ehciPipePointer); + break; + + default: + status = kStatus_USB_Error; + break; + } + + if (status != kStatus_USB_Success) + { + /* release pipe */ + USB_HostEhciLock(); + ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)ehciInstance->ehciPipeList; + ehciInstance->ehciPipeList = ehciPipePointer; + USB_HostEhciUnlock(); + return status; + } + + /* add pipe to run pipe list */ + USB_HostEhciLock(); + ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)ehciInstance->ehciRunningPipeList; + ehciInstance->ehciRunningPipeList = ehciPipePointer; + USB_HostEhciUnlock(); + + *pipeHandle = ehciPipePointer; + return status; +} + +usb_status_t USB_HostEhciClosePipe(usb_host_controller_handle controllerHandle, usb_host_pipe_handle pipeHandle) +{ + usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; + usb_host_ehci_pipe_t *ehciPipePointer = (usb_host_ehci_pipe_t *)pipeHandle; + usb_host_pipe_t *prevPointer = NULL; + + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_BULK: + case USB_ENDPOINT_CONTROL: + USB_HostEhciCloseControlBulk(ehciInstance, ehciPipePointer); + break; + + case USB_ENDPOINT_INTERRUPT: + USB_HostEhciCloseInterrupt(ehciInstance, ehciPipePointer); + break; + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + case USB_ENDPOINT_ISOCHRONOUS: + USB_HostEhciCloseIso(ehciInstance, ehciPipePointer); + break; +#endif + + default: + break; + } + + /* delete pipe from run pipe list */ + USB_HostEhciLock(); + prevPointer = (usb_host_pipe_t *)ehciInstance->ehciRunningPipeList; + if (prevPointer == (usb_host_pipe_t *)ehciPipePointer) + { + ehciInstance->ehciRunningPipeList = (usb_host_ehci_pipe_t *)(prevPointer->next); + } + else + { + while (prevPointer != NULL) + { + if (prevPointer->next == (usb_host_pipe_t *)ehciPipePointer) + { + prevPointer->next = ehciPipePointer->pipeCommon.next; + break; + } + else + { + prevPointer = prevPointer->next; + } + } + } + USB_HostEhciUnlock(); + + /* release pipe */ + USB_HostEhciLock(); + ehciPipePointer->pipeCommon.next = (usb_host_pipe_t *)ehciInstance->ehciPipeList; + ehciInstance->ehciPipeList = ehciPipePointer; + USB_HostEhciUnlock(); + + return kStatus_USB_Success; +} + +usb_status_t USB_HostEhciWritePipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer) +{ + usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; + usb_host_ehci_pipe_t *ehciPipePointer = (usb_host_ehci_pipe_t *)pipeHandle; + usb_status_t status = kStatus_USB_Success; +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + uint32_t speed; +#endif + + switch (ehciPipePointer->pipeCommon.pipeType) + { + case USB_ENDPOINT_BULK: + case USB_ENDPOINT_CONTROL: + case USB_ENDPOINT_INTERRUPT: + status = USB_HostEhciQhQtdListInit(ehciInstance, ehciPipePointer, + transfer); /* initialize qtd for control/bulk transfer */ + break; + +#if (((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) || \ + ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD))) + case USB_ENDPOINT_ISOCHRONOUS: + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceSpeed, + &speed); + if (speed == USB_SPEED_HIGH) + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_ITD) && (USB_HOST_CONFIG_EHCI_MAX_ITD)) + status = USB_HostEhciItdArrayInit(ehciInstance, ehciPipePointer, + transfer); /* initialize itd for iso transfer */ +#endif + } + else + { +#if ((defined USB_HOST_CONFIG_EHCI_MAX_SITD) && (USB_HOST_CONFIG_EHCI_MAX_SITD)) + status = USB_HostEhciSitdArrayInit(ehciInstance, ehciPipePointer, + transfer); /* initialize sitd for iso transfer */ +#endif + } + break; +#endif + + default: + break; + } + return status; +} + +usb_status_t USB_HostEhciReadpipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer) +{ + return USB_HostEhciWritePipe(controllerHandle, pipeHandle, transfer); /* same as write */ +} + +usb_status_t USB_HostEhciIoctl(usb_host_controller_handle controllerHandle, uint32_t ioctlEvent, void *ioctlParam) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_ehci_instance_t *ehciInstance = (usb_host_ehci_instance_t *)controllerHandle; + usb_host_cancel_param_t *param; + usb_host_ehci_pipe_t *ehciPipePointer; + volatile usb_host_ehci_qh_t *vltQhPointer; + uint32_t deviceAddress; + + if (controllerHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + switch (ioctlEvent) + { + case kUSB_HostCancelTransfer: /* cancel pipe or one transfer */ + param = (usb_host_cancel_param_t *)ioctlParam; + status = USB_HostEhciCancelPipe(ehciInstance, (usb_host_ehci_pipe_t *)param->pipeHandle, param->transfer); + break; + + case kUSB_HostBusControl: /* bus control */ + status = USB_HostEhciControlBus(ehciInstance, *((uint8_t *)ioctlParam)); + break; + + case kUSB_HostGetFrameNumber: /* get frame number */ + *((uint32_t *)ioctlParam) = ((ehciInstance->ehciIpBase->FRINDEX & EHCI_MAX_UFRAME_VALUE) >> 3); + break; + + case kUSB_HostUpdateControlEndpointAddress: + ehciPipePointer = (usb_host_ehci_pipe_t *)ioctlParam; + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + /* update address */ + USB_HostHelperGetPeripheralInformation(ehciPipePointer->pipeCommon.deviceHandle, kUSB_HostGetDeviceAddress, + &deviceAddress); + vltQhPointer->staticEndpointStates[0] |= deviceAddress; + break; + + case kUSB_HostUpdateControlPacketSize: + ehciPipePointer = (usb_host_ehci_pipe_t *)ioctlParam; + vltQhPointer = (volatile usb_host_ehci_qh_t *)ehciPipePointer->ehciQh; + USB_HostEhciLock(); + if (ehciInstance->ehciIpBase->USBSTS & USBHS_USBSTS_AS_MASK) + { + USB_HostEhciStopAsync(ehciInstance); + /* update max packet size */ + vltQhPointer->staticEndpointStates[0] = + (((vltQhPointer->staticEndpointStates[0]) & (~EHCI_HOST_QH_MAX_PACKET_LENGTH_MASK)) | + ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT)); + USB_HostEhciStartAsync(ehciInstance); + } + else + { + /* update max packet size */ + vltQhPointer->staticEndpointStates[0] = + (((vltQhPointer->staticEndpointStates[0]) & (~EHCI_HOST_QH_MAX_PACKET_LENGTH_MASK)) | + ((uint32_t)ehciPipePointer->pipeCommon.maxPacketSize << EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT)); + } + USB_HostEhciUnlock(); + break; + + default: + break; + } + return status; +} + +void USB_HostEhciTaskFunction(void *hostHandle) +{ + usb_host_ehci_instance_t *ehciInstance; + uint32_t bitSet; + usb_device_handle deviceHandle; + + if (hostHandle == NULL) + { + return; + } + ehciInstance = (usb_host_ehci_instance_t *)((usb_host_instance_t *)hostHandle)->controllerHandle; + + if (USB_OsaEventWait(ehciInstance->taskEventHandle, 0xFF, 0, 0, &bitSet) == + kStatus_USB_OSA_Success) /* wait all event */ + { + if (bitSet & EHCI_TASK_EVENT_PORT_CHANGE) /* port change */ + { + USB_HostEhciPortChange(ehciInstance); + } + + if (bitSet & EHCI_TASK_EVENT_TIMER0) /* timer0 */ + { + USB_HostEhciTimer0(ehciInstance); + } + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + if (bitSet & EHCI_TASK_EVENT_TIMER1) /* timer1 */ + { + USB_HostEhciTimer1(ehciInstance); + } +#endif + + if (ehciInstance->deviceAttached == kEHCIDeviceAttached) + { + if (bitSet & EHCI_TASK_EVENT_TRANSACTION_DONE) /* transaction done */ + { + USB_HostEhciTransactionDone(ehciInstance); + } + + if (bitSet & EHCI_TASK_EVENT_DEVICE_DETACH) /* device detach */ + { + ehciInstance->ehciIpBase->USBINTR &= + (~USBHS_USBINTR_PCE_MASK); /* disable attach, enable when the detach process is done */ + ehciInstance->deviceAttached = kEHCIDeviceDetached; + USB_HostDetachDevice(ehciInstance->hostHandle, 0, 0); + } + } + else if (ehciInstance->deviceAttached != kEHCIDeviceAttached) + { + if (bitSet & EHCI_TASK_EVENT_DEVICE_ATTACH) /* device is attached */ + { + USB_HostEhciStartAsync(ehciInstance); + USB_HostEhciStartPeriodic(ehciInstance); + + if (USB_HostAttachDevice(ehciInstance->hostHandle, ehciInstance->firstDeviceSpeed, 0, 0, 1, + &deviceHandle) == kStatus_USB_Success) + { + ehciInstance->deviceAttached = kEHCIDeviceAttached; + } + } + } + else + { + } + } +} + +void USB_HostEhciIsrFunction(void *hostHandle) +{ + usb_host_ehci_instance_t *ehciInstance; + static uint32_t interruptStatus = 0; + + if (hostHandle == NULL) + { + return; + } + + ehciInstance = (usb_host_ehci_instance_t *)((usb_host_instance_t *)hostHandle)->controllerHandle; + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + if (ehciInstance->registerNcBase->USB_OTGn_CTRL & USBNC_USB_OTGn_CTRL_WIE_MASK) + { + usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; + ehciInstance->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; + hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, + kUSB_HostEventDetectResume); /* call host callback function */ + + while (!(ehciInstance->registerNcBase->USB_OTGn_PHY_CTRL_0 & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)) + { + } + + if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK) + { + USB_HostEhciStartAsync(ehciInstance); + USB_HostEhciStartPeriodic(ehciInstance); + } + ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_RS_MASK); + if ((kBus_EhciSuspended == ehciInstance->busSuspendStatus)) + { + /* ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_FPR_MASK; */ + ehciInstance->busSuspendStatus = kBus_EhciStartResume; + } + else + { + } + } + else + { + } +#else + if (ehciInstance->ehciIpBase->USBGENCTRL & USBHS_USBGENCTRL_WU_IE_MASK) + { + usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; + + hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, + kUSB_HostEventDetectResume); /* call host callback function */ + + while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) + { + } + ehciInstance->ehciIpBase->USBGENCTRL |= USBHS_USBGENCTRL_WU_INT_CLR_MASK; + ehciInstance->ehciIpBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; + if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK) + { + USB_HostEhciStartAsync(ehciInstance); + USB_HostEhciStartPeriodic(ehciInstance); + } + ehciInstance->ehciIpBase->USBCMD |= (USBHS_USBCMD_RS_MASK); + if ((kBus_EhciSuspended == ehciInstance->busSuspendStatus)) + { + ehciInstance->busSuspendStatus = kBus_EhciStartResume; + /*ehciInstance->ehciIpBase->PORTSC1 |= USBHS_PORTSC1_FPR_MASK; */ + } + else + { + } + } + else + { + } +#endif /* FSL_FEATURE_SOC_USBNC_COUNT */ + +#endif /* USB_HOST_CONFIG_LOW_POWER_MODE */ + + interruptStatus = ehciInstance->ehciIpBase->USBSTS; + interruptStatus &= ehciInstance->ehciIpBase->USBINTR; + while (interruptStatus) /* there are usb interrupts */ + { + ehciInstance->ehciIpBase->USBSTS = interruptStatus; /* clear interrupt */ + + if (interruptStatus & USBHS_USBSTS_SRI_MASK) /* SOF interrupt */ + { + } + + if (interruptStatus & USBHS_USBSTS_SEI_MASK) /* system error interrupt */ + { + } + + if ((interruptStatus & USBHS_USBSTS_UI_MASK) || + (interruptStatus & USBHS_USBSTS_UEI_MASK)) /* USB interrupt or USB error interrupt */ + { + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TRANSACTION_DONE); + } + + if (interruptStatus & USBHS_USBSTS_PCI_MASK) /* port change detect interrupt */ + { +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + usb_host_instance_t *hostPointer = (usb_host_instance_t *)ehciInstance->hostHandle; + if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_FPR_MASK) + { + if (kBus_EhciStartSuspend == ehciInstance->busSuspendStatus) + { + if (ehciInstance->ehciIpBase->PORTSC1 & USBHS_PORTSC1_CCS_MASK) + { + USB_HostEhciStartAsync(ehciInstance); + USB_HostEhciStartPeriodic(ehciInstance); + } + hostPointer->deviceCallback(hostPointer->suspendedDevice, NULL, + kUSB_HostEventNotSuspended); /* call host callback function */ + hostPointer->suspendedDevice = NULL; + ehciInstance->busSuspendStatus = kBus_EhciIdle; + ehciInstance->ehciIpBase->USBINTR &= ~(USBHS_USBINTR_TIE1_MASK); + } + else + { + } + } +#endif + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_PORT_CHANGE); + } + + if (interruptStatus & USBHS_USBSTS_TI0_MASK) /* timer 0 interrupt */ + { + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TIMER0); + } + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + if (interruptStatus & USBHS_USBSTS_TI1_MASK) /* timer 1 interrupt */ + { + USB_OsaEventSet(ehciInstance->taskEventHandle, EHCI_TASK_EVENT_TIMER1); + } +#endif + + interruptStatus = ehciInstance->ehciIpBase->USBSTS; + interruptStatus &= ehciInstance->ehciIpBase->USBINTR; + } +} + +#endif /* USB_HOST_CONFIG_EHCI */ diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.h b/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.h new file mode 100644 index 0000000000000000000000000000000000000000..162d6576cd9aa864ed75d143a07d5685366a8dd3 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_ehci.h @@ -0,0 +1,499 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_HOST_CONTROLLER_EHCI_H_ +#define _USB_HOST_CONTROLLER_EHCI_H_ + +/******************************************************************************* + * KHCI private public structures, enumerations, macros, functions + ******************************************************************************/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* EHCI host macros */ +#define EHCI_HOST_T_INVALID_VALUE (1U) +#define EHCI_HOST_POINTER_TYPE_ITD (0x00U) +#define EHCI_HOST_POINTER_TYPE_QH (0x00000002U) +#define EHCI_HOST_POINTER_TYPE_SITD (0x00000004U) +#define EHCI_HOST_POINTER_TYPE_FSTN (0x00000006U) +#define EHCI_HOST_POINTER_TYPE_MASK (0x00000006U) +#define EHCI_HOST_POINTER_ADDRESS_MASK (0xFFFFFFE0U) +#define EHCI_HOST_PID_OUT (0U) +#define EHCI_HOST_PID_IN (1U) +#define EHCI_HOST_PID_SETUP (2U) + +#define EHCI_HOST_QH_RL_SHIFT (28U) +#define EHCI_HOST_QH_RL_MASK (0xF0000000U) +#define EHCI_HOST_QH_C_SHIFT (27U) +#define EHCI_HOST_QH_MAX_PACKET_LENGTH_SHIFT (16U) +#define EHCI_HOST_QH_MAX_PACKET_LENGTH_MASK (0x07FF0000U) +#define EHCI_HOST_QH_H_SHIFT (15U) +#define EHCI_HOST_QH_DTC_SHIFT (14U) +#define EHCI_HOST_QH_EPS_SHIFT (12U) +#define EHCI_HOST_QH_ENDPT_SHIFT (8U) +#define EHCI_HOST_QH_I_SHIFT (7U) +#define EHCI_HOST_QH_DEVICE_ADDRESS_SHIFT (0U) +#define EHCI_HOST_QH_MULT_SHIFT (30U) +#define EHCI_HOST_QH_PORT_NUMBER_SHIFT (23U) +#define EHCI_HOST_QH_HUB_ADDR_SHIFT (16U) +#define EHCI_HOST_QH_UFRAME_CMASK_SHIFT (8U) +#define EHCI_HOST_QH_UFRAME_SMASK_SHIFT (0U) +#define EHCI_HOST_QH_STATUS_ERROR_MASK (0x0000007EU) +#define EHCI_HOST_QH_STATUS_NOSTALL_ERROR_MASK (0x0000003EU) + +#define EHCI_HOST_QTD_DT_SHIFT (31U) +#define EHCI_HOST_QTD_DT_MASK (0x80000000U) +#define EHCI_HOST_QTD_TOTAL_BYTES_SHIFT (16U) +#define EHCI_HOST_QTD_TOTAL_BYTES_MASK (0x7FFF0000U) +#define EHCI_HOST_QTD_IOC_MASK (0x00008000U) +#define EHCI_HOST_QTD_C_PAGE_SHIFT (12U) +#define EHCI_HOST_QTD_CERR_SHIFT (10U) +#define EHCI_HOST_QTD_CERR_MAX_VALUE (0x00000003U) +#define EHCI_HOST_QTD_PID_CODE_SHIFT (8U) +#define EHCI_HOST_QTD_STATUS_SHIFT (0U) +#define EHCI_HOST_QTD_CURRENT_OFFSET_MASK (0x00000FFFU) +#define EHCI_HOST_QTD_BUFFER_POINTER_SHIFT (12U) +#define EHCI_HOST_QTD_STATUS_ACTIVE_MASK (0x00000080U) +#define EHCI_HOST_QTD_STATUS_MASK (0x000000ffU) +#define EHCI_HOST_QTD_STATUS_ERROR_MASK (0x0000007EU) +#define EHCI_HOST_QTD_STATUS_STALL_ERROR_MASK (0x00000040U) + +#define EHCI_HOST_ITD_STATUS_ACTIVE_MASK (0x80000000U) +#define EHCI_HOST_ITD_TRANSACTION_LEN_SHIFT (16U) +#define EHCI_HOST_ITD_TRANSACTION_LEN_MASK (0x0FFF0000U) +#define EHCI_HOST_ITD_IOC_SHIFT (15U) +#define EHCI_HOST_ITD_PG_SHIFT (12U) +#define EHCI_HOST_ITD_TRANSACTION_OFFSET_SHIFT (0U) +#define EHCI_HOST_ITD_TRANSACTION_OFFSET_MASK (0x00000FFFU) +#define EHCI_HOST_ITD_BUFFER_POINTER_SHIFT (12U) +#define EHCI_HOST_ITD_ENDPT_SHIFT (8U) +#define EHCI_HOST_ITD_DEVICE_ADDRESS_SHIFT (0U) +#define EHCI_HOST_ITD_MAX_PACKET_SIZE_SHIFT (0U) +#define EHCI_HOST_ITD_MULT_SHIFT (0U) +#define EHCI_HOST_ITD_DIRECTION_SHIFT (11U) + +#define EHCI_HOST_SITD_STATUS_ACTIVE_MASK (0x00000080U) +#define EHCI_HOST_SITD_DIRECTION_SHIFT (31U) +#define EHCI_HOST_SITD_PORT_NUMBER_SHIFT (24U) +#define EHCI_HOST_SITD_HUB_ADDR_SHIFT (16U) +#define EHCI_HOST_SITD_ENDPT_SHIFT (8U) +#define EHCI_HOST_SITD_DEVICE_ADDRESS_SHIFT (0U) +#define EHCI_HOST_SITD_CMASK_SHIFT (8U) +#define EHCI_HOST_SITD_SMASK_SHIFT (0U) +#define EHCI_HOST_SITD_TOTAL_BYTES_SHIFT (16U) +#define EHCI_HOST_SITD_TOTAL_BYTES_MASK (0x03FF0000U) +#define EHCI_HOST_SITD_TP_SHIFT (3U) +#define EHCI_HOST_SITD_TCOUNT_SHIFT (0U) +#define EHCI_HOST_SITD_IOC_SHIFT (31U) + +/* register related MACROs */ +#define EHCI_PORTSC1_W1_BITS (0x0000002AU) +#define EHCI_MAX_UFRAME_VALUE (0x00003FFFU) + +/* task event */ +#define EHCI_TASK_EVENT_DEVICE_ATTACH (0x01U) +#define EHCI_TASK_EVENT_TRANSACTION_DONE (0x02U) +#define EHCI_TASK_EVENT_DEVICE_DETACH (0x04U) +#define EHCI_TASK_EVENT_PORT_CHANGE (0x08U) +#define EHCI_TASK_EVENT_TIMER0 (0x10U) +#define EHCI_TASK_EVENT_TIMER1 (0x20U) + +#define USB_HostEhciLock() USB_OsaMutexLock(ehciInstance->ehciMutex) +#define USB_HostEhciUnlock() USB_OsaMutexUnlock(ehciInstance->ehciMutex) + +/******************************************************************************* + * KHCI driver public structures, enumerations, macros, functions + ******************************************************************************/ + +/*! + * @addtogroup usb_host_controller_ehci + * @{ + */ + +/*! @brief The maximum supported ISO pipe number */ +#define USB_HOST_EHCI_ISO_NUMBER USB_HOST_CONFIG_EHCI_MAX_ITD +/*! @brief Check the port connect state delay if the state is unstable */ +#define USB_HOST_EHCI_PORT_CONNECT_DEBOUNCE_DELAY (101U) +/*! @brief Delay for port reset */ +#define USB_HOST_EHCI_PORT_RESET_DELAY (11U) +/*! @brief The SITD inserts a frame interval for putting more SITD continuously. + * There is an interval when an application sends two FS/LS ISO transfers. + * When the interval is less than the macro, the two transfers are continuous in the frame list. Otherwise, the two + * transfers + * are not continuous. + * For example: + * - Use case 1: when inserting the SITD first, the inserted frame = the current frame value + this MACRO value. + * - Use case 2: when inserting SITD is not first, choose between the last inserted frame value and the + * current frame value according to the following criteria: + * If the interval is less than the MACRO value, the new SITD is continuous with the last SITD. + * If not, the new SITD inserting frame = the current frame value + this MACRO value. + */ +#define USB_HOST_EHCI_ISO_BOUNCE_FRAME_NUMBER (2U) +/*! @brief The ITD inserts a micro-frame interval for putting more ITD continuously. + * There is an interval when an application sends two HS ISO transfers. + * When the interval is less than the macro, the two transfers are continuous in the frame list. Otherwise, the two + * transfers + * are not continuous. + * For example: + * - Use case 1: when inserting ITD first, the inserted micro-frame = the current micro-frame value + this MACRO value. + * - Use case 2: when inserting ITD is not first, choose between the last inserted micro-frame value and the + * current micro-frame value according to the following criteria: + * If the interval is less than this MACRO value, the new ITD is continuous with the last ITD. + * If not, the new ITD inserting micro-frame = the current micro-frame value + this MACRO value. + */ +#define USB_HOST_EHCI_ISO_BOUNCE_UFRAME_NUMBER (16U) +/*! @brief Control or bulk transaction timeout value (unit: 100 ms) */ +#define USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE (20U) + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) +typedef enum _bus_ehci_suspend_request_state +{ + kBus_EhciIdle = 0U, + kBus_EhciStartSuspend, + kBus_EhciSuspended, + kBus_EhciStartResume, +} bus_ehci_suspend_request_state_t; +#endif + +/*! @brief EHCI state for device attachment/detachment. */ +typedef enum _host_ehci_device_state_ +{ + kEHCIDevicePhyAttached = 1, /*!< Device is physically attached */ + kEHCIDeviceAttached, /*!< Device is attached and initialized */ + kEHCIDeviceDetached, /*!< Device is detached and de-initialized */ +} host_ehci_device_state_t; + +/*! @brief EHCI pipe structure */ +typedef struct _usb_host_ehci_pipe +{ + usb_host_pipe_t pipeCommon; /*!< Common pipe information */ + void *ehciQh; /*!< Control/bulk/interrupt: QH; ISO: usb_host_ehci_iso_t*/ + + /* bandwidth */ + uint16_t uframeInterval; /*!< Micro-frame interval value */ + uint16_t startFrame; /*!< + Bandwidth start frame: its value is from 0 to frame_list. + */ + uint16_t dataTime; /*!< + Bandwidth time value: + - When the host works as HS: it's the data bandwidth value. + - When the host works as FS/LS: + - For FS/LS device, it's the data bandwidth value when transferring the data by FS/LS. + - For HS device, it's the data bandwidth value when transferring the data by HS. + */ + uint16_t startSplitTime; /*!< + Start splitting the bandwidth time value: + - When the host works as HS, it is the start split bandwidth value. + */ + uint16_t completeSplitTime; /*!< + Complete splitting the bandwidth time value: + - When host works as HS, it is the complete split bandwidth value. + */ + uint8_t startUframe; /*!< + Bandwidth start micro-frame: its value is from 0 to 7. + */ + uint8_t uframeSmask; /*!< + Start micro-frame. + - When host works as an HS: + - For FS/LS device, it's the interrupt or ISO transfer start-split mask. + - For HS device, it's the interrupt transfer start micro-frame mask. + - When host works as FS/LS, it's the interrupt and ISO start micro-frame mask + */ + uint8_t uframeCmask; /*!< + Complete micro-frame + - When host works as HS: + - For FS/LS device, it's the interrupt or ISO transfer complete-split mask. + */ +} usb_host_ehci_pipe_t; + +/*! @brief EHCI QH structure. See the USB EHCI specification */ +typedef struct _usb_host_ehci_qh +{ + uint32_t horizontalLinkPointer; /*!< QH specification filed, queue head a horizontal link pointer */ + uint32_t + staticEndpointStates[2]; /*!< QH specification filed, static endpoint state and configuration information */ + uint32_t currentQtdPointer; /*!< QH specification filed, current qTD pointer */ + uint32_t nextQtdPointer; /*!< QH specification filed, next qTD pointer */ + uint32_t alternateNextQtdPointer; /*!< QH specification filed, alternate next qTD pointer */ + uint32_t + transferOverlayResults[6]; /*!< QH specification filed, transfer overlay configuration and transfer results */ + + /* reserved space */ + usb_host_ehci_pipe_t *ehciPipePointer; /*!< EHCI pipe pointer */ + usb_host_transfer_t *ehciTransferHead; /*!< Transfer list head on this QH */ + usb_host_transfer_t *ehciTransferTail; /*!< Transfer list tail on this QH */ + uint16_t timeOutValue; /*!< Its maximum value is USB_HOST_EHCI_CONTROL_BULK_TIME_OUT_VALUE. When the value is + zero, the transfer times out. */ + uint16_t timeOutLabel; /*!< It's used to judge the transfer timeout. The EHCI driver maintain the value */ +} usb_host_ehci_qh_t; + +/*! @brief EHCI QTD structure. See the USB EHCI specification. */ +typedef struct _usb_host_ehci_qtd +{ + uint32_t nextQtdPointer; /*!< QTD specification filed, the next QTD pointer */ + uint32_t alternateNextQtdPointer; /*!< QTD specification filed, alternate next QTD pointer */ + uint32_t transferResults[2]; /*!< QTD specification filed, transfer results fields */ + uint32_t bufferPointers[4]; /*!< QTD specification filed, transfer buffer fields */ +} usb_host_ehci_qtd_t; + +/*! @brief EHCI ITD structure. See the USB EHCI specification. */ +typedef struct _usb_host_ehci_itd +{ + uint32_t nextLinkPointer; /*!< ITD specification filed, the next linker pointer */ + uint32_t transactions[8]; /*!< ITD specification filed, transactions information */ + uint32_t bufferPointers[7]; /*!< ITD specification filed, transfer buffer fields */ + + /* add space */ + struct _usb_host_ehci_itd *nextItdPointer; /*!< Next ITD pointer */ + uint32_t frameEntryIndex; /*!< The ITD inserted frame value */ + uint32_t reserved[6]; /*!< Reserved fields for 32 bytes align */ +} usb_host_ehci_itd_t; + +/*! @brief EHCI SITD structure. See the USB EHCI specification. */ +typedef struct _usb_host_ehci_sitd +{ + uint32_t nextLinkPointer; /*!< SITD specification filed, the next linker pointer */ + uint32_t endpointStates[2]; /*!< SITD specification filed, endpoint configuration information */ + uint32_t transferResults[3]; /*!< SITD specification filed, transfer result fields */ + uint32_t backPointer; /*!< SITD specification filed, back pointer */ + + /* reserved space */ + uint16_t frameEntryIndex; /*!< The SITD inserted frame value */ + uint8_t nextSitdIndex; /*!< The next SITD index; Get the next SITD pointer through adding base address with the + index. 0xFF means invalid. */ + uint8_t reserved; /*!< Reserved fields for 32 bytes align */ +} usb_host_ehci_sitd_t; + +/*! @brief EHCI ISO structure; An ISO pipe has an instance of this structure to keep the ISO pipe-specific information. + */ +typedef struct _usb_host_ehci_iso +{ + struct _usb_host_ehci_iso *next; /*!< Next instance pointer */ + usb_host_pipe_t *ehciPipePointer; /*!< This ISO's EHCI pipe pointer */ + usb_host_transfer_t *ehciTransferHead; /*!< Transfer list head on this ISO pipe */ + usb_host_transfer_t *ehciTransferTail; /*!< Transfer list head on this ISO pipe */ + + uint16_t lastLinkFrame; /*!< It means that the inserted frame for ISO ITD/SITD. 0xFFFF is invalid. For ITD, it is a + micro-frame value. For SITD, it is a frame value */ +} usb_host_ehci_iso_t; + +/*! @brief EHCI instance structure */ +typedef struct _usb_host_ehci_instance +{ + usb_host_handle hostHandle; /*!< Related host handle*/ + uint32_t *ehciUnitBase; /*!< Keep the QH/QTD/ITD/SITD buffer pointer for release*/ + uint8_t *ehciFrameList; /*!< The frame list of the current ehci instance*/ + usb_host_ehci_qh_t *ehciQhList; /*!< Idle QH list pointer */ + usb_host_ehci_qtd_t *ehciQtdHead; /*!< Idle QTD list pointer head */ + usb_host_ehci_qtd_t *ehciQtdTail; /*!< Idle QTD list pointer tail (recently used qTD will be used)*/ + usb_host_ehci_itd_t *ehciItdList; /*!< Idle ITD list pointer*/ + usb_host_ehci_sitd_t *ehciSitdIndexBase; /*!< SITD buffer's start pointer*/ + usb_host_ehci_sitd_t *ehciSitdList; /*!< Idle SITD list pointer*/ + usb_host_ehci_iso_t *ehciIsoList; /*!< Idle ISO list pointer*/ + USBHS_Type *ehciIpBase; /*!< EHCI IP base address*/ + usb_host_ehci_qh_t *shedFirstQh; /*!< First async QH*/ + usb_host_ehci_pipe_t *ehciPipeIndexBase; /*!< Pipe buffer's start pointer*/ + usb_host_ehci_pipe_t *ehciPipeList; /*!< Idle pipe list pointer*/ + usb_host_ehci_pipe_t *ehciRunningPipeList; /*!< Running pipe list pointer*/ + usb_osa_mutex_handle ehciMutex; /*!< EHCI mutex*/ + usb_osa_event_handle taskEventHandle; /*!< EHCI task event*/ +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + uint64_t matchTick; + USBPHY_Type *registerPhyBase; /*!< The base address of the PHY register */ +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + USBNC_Type *registerNcBase; /*!< The base address of the USBNC register */ +#endif + +#endif + uint8_t controllerId; /*!< EHCI controller ID*/ + uint8_t deviceAttached; /*!< Device attach/detach state, see #host_ehci_device_state_t */ + uint8_t firstDeviceSpeed; /*!< The first device's speed, the controller's work speed*/ + uint8_t ehciItdNumber; /*!< Idle ITD number*/ + uint8_t ehciSitdNumber; /*!< Idle SITD number*/ + uint8_t ehciQtdNumber; /*!< Idle QTD number*/ +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + bus_ehci_suspend_request_state_t busSuspendStatus; /*!< Bus Suspend Status*/ +#endif +} usb_host_ehci_instance_t; + +/*! @brief EHCI data structure */ +typedef struct _usb_host_ehci_data +{ +#if ((defined(USB_HOST_CONFIG_EHCI_MAX_QH)) && (USB_HOST_CONFIG_EHCI_MAX_QH > 0U)) + usb_host_ehci_qh_t ehciQh[USB_HOST_CONFIG_EHCI_MAX_QH]; /*!< Idle QH list array*/ +#endif +#if ((defined(USB_HOST_CONFIG_EHCI_MAX_QTD)) && (USB_HOST_CONFIG_EHCI_MAX_QTD > 0U)) + usb_host_ehci_qtd_t ehciQtd[USB_HOST_CONFIG_EHCI_MAX_QTD]; /*!< Idle QTD list array*/ +#endif +#if ((defined(USB_HOST_CONFIG_EHCI_MAX_ITD)) && (USB_HOST_CONFIG_EHCI_MAX_ITD > 0U)) + usb_host_ehci_itd_t ehciItd[USB_HOST_CONFIG_EHCI_MAX_ITD]; /*!< Idle ITD list array*/ +#endif +#if ((defined(USB_HOST_CONFIG_EHCI_MAX_SITD)) && (USB_HOST_CONFIG_EHCI_MAX_SITD > 0U)) + usb_host_ehci_sitd_t ehciSitd[USB_HOST_CONFIG_EHCI_MAX_SITD]; /*!< Idle SITD list array*/ +#endif +#if ((defined(USB_HOST_EHCI_ISO_NUMBER)) && (USB_HOST_EHCI_ISO_NUMBER > 0U)) + usb_host_ehci_iso_t ehciIso[USB_HOST_EHCI_ISO_NUMBER]; /*!< Idle ISO list array*/ +#endif +#if ((defined(USB_HOST_CONFIG_MAX_PIPES)) && (USB_HOST_CONFIG_MAX_PIPES > 0U)) + usb_host_ehci_pipe_t ehciPipe[USB_HOST_CONFIG_MAX_PIPES]; /*!< Idle pipe list array*/ +#endif +} usb_host_ehci_data_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif +/*! + * @name USB host EHCI APIs + * @{ + */ + +/*! + * @brief Creates the USB host EHCI instance. + * + * This function initializes the USB host EHCI controller driver. + * + * @param[in] controllerId The controller ID of the USB IP. Please refer to the enumeration usb_controller_index_t. + * @param[in] upperLayerHandle The host level handle. + * @param[out] controllerHandle return the controller instance handle. + * + * @retval kStatus_USB_Success The host is initialized successfully. + * @retval kStatus_USB_AllocFail Allocating memory failed. + * @retval kStatus_USB_Error Host mutex create fail, KHCI/EHCI mutex or KHCI/EHCI event create fail. + * Or, KHCI/EHCI IP initialize fail. + */ +extern usb_status_t USB_HostEhciCreate(uint8_t controllerId, + usb_host_handle upperLayerHandle, + usb_host_controller_handle *controllerHandle); + +/*! + * @brief Destroys the USB host EHCI instance. + * + * This function de-initializes The USB host EHCI controller driver. + * + * @param[in] controllerHandle The controller handle. + * + * @retval kStatus_USB_Success The host is initialized successfully. + */ +extern usb_status_t USB_HostEhciDestory(usb_host_controller_handle controllerHandle); + +/*! + * @brief Opens the USB host pipe. + * + * This function opens a pipe according to the pipe_init_ptr parameter. + * + * @param[in] controllerHandle The controller handle. + * @param[out] pipeHandle The pipe handle pointer, it is used to return the pipe handle. + * @param[in] pipeInit It is used to initialize the pipe. + * + * @retval kStatus_USB_Success The host is initialized successfully. + * @retval kStatus_USB_Error There is no idle pipe. + * Or, there is no idle QH for EHCI. + * Or, bandwidth allocate fail for EHCI. + */ +extern usb_status_t USB_HostEhciOpenPipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle *pipeHandle, + usb_host_pipe_init_t *pipeInit); + +/*! + * @brief Closes the USB host pipe. + * + * This function closes a pipe and releases related resources. + * + * @param[in] controllerHandle The controller handle. + * @param[in] pipeHandle The closing pipe handle. + * + * @retval kStatus_USB_Success The host is initialized successfully. + */ +extern usb_status_t USB_HostEhciClosePipe(usb_host_controller_handle controllerHandle, usb_host_pipe_handle pipeHandle); + +/*! + * @brief Sends data to the pipe. + * + * This function requests to send the transfer to the specified pipe. + * + * @param[in] controllerHandle The controller handle. + * @param[in] pipeHandle The sending pipe handle. + * @param[in] transfer The transfer information. + * + * @retval kStatus_USB_Success Sent successfully. + * @retval kStatus_USB_LackSwapBuffer There is no swap buffer for KHCI. + * @retval kStatus_USB_Error There is no idle QTD/ITD/SITD for EHCI. + */ +extern usb_status_t USB_HostEhciWritePipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer); + +/*! + * @brief Receives data from the pipe. + * + * This function requests to receive the transfer from the specified pipe. + * + * @param[in] controllerHandle The controller handle. + * @param[in] pipeHandle The receiving pipe handle. + * @param[in] transfer The transfer information. + + * @retval kStatus_USB_Success Send successfully. + * @retval kStatus_USB_LackSwapBuffer There is no swap buffer for KHCI. + * @retval kStatus_USB_Error There is no idle QTD/ITD/SITD for EHCI. + */ +extern usb_status_t USB_HostEhciReadpipe(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer); + +/*! + * @brief Controls the EHCI. + * + * This function controls the EHCI. + * + * @param[in] controllerHandle The controller handle. + * @param[in] ioctlEvent See enumeration host_bus_control_t. + * @param[in] ioctlParam The control parameter. + * + * @retval kStatus_USB_Success Cancel successfully. + * @retval kStatus_USB_InvalidHandle The controllerHandle is a NULL pointer. + */ +extern usb_status_t USB_HostEhciIoctl(usb_host_controller_handle controllerHandle, + uint32_t ioctlEvent, + void *ioctlParam); + +/*! @}*/ + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* _USB_HOST_CONTROLLER_EHCI_H_ */ diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.c b/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.c new file mode 100644 index 0000000000000000000000000000000000000000..927bf8bd9c398b7973c779b07709916ad2af8004 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.c @@ -0,0 +1,1052 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "fsl_common.h" +#include "usb_host.h" +#include "usb_host_hci.h" +#include "usb_host_devices.h" +#include "fsl_device_registers.h" +#if ((defined USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#include "fsl_cache.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + +extern uint32_t USB_HostHubGetTotalThinkTime(usb_host_handle hostHandle, uint8_t parentHubNo); + +extern usb_status_t USB_HostHubSuspendDevice(usb_host_handle hostHandle); + +extern usb_status_t USB_HostHubResumeDevice(usb_host_handle hostHandle); +#endif + +/*! + * @brief get the idle host instance. + * + * @return host instance pointer. + */ +static usb_host_instance_t *USB_HostGetInstance(void); + +/*! + * @brief release host instance. + * + * @param hostInstance host instance pointer. + */ +static void USB_HostReleaseInstance(usb_host_instance_t *hostInstance); + +/*! + * @brief get the khci/ehci interface. + * + * @param controllerId controller id. + * @param controllerTable return controller interface structure. + */ +static void USB_HostGetControllerInterface(uint8_t controllerId, + const usb_host_controller_interface_t **controllerTable); + +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) +#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) +extern void USB_HostEhciTestModeInit(usb_device_handle devHandle); +#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ +#if ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS)) +extern void USB_HostIp3516HsTestModeInit(usb_device_handle devHandle); +#endif /* USB_HOST_CONFIG_COMPLIANCE_TEST */ +#endif /* USB_HOST_CONFIG_EHCI */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief USB host instance resource */ +usb_host_instance_t g_UsbHostInstance[USB_HOST_CONFIG_MAX_HOST]; + +#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) +#include "usb_host_ehci.h" +static const usb_host_controller_interface_t s_EhciInterface = \ +{ + USB_HostEhciCreate, USB_HostEhciDestory, USB_HostEhciOpenPipe, USB_HostEhciClosePipe, + USB_HostEhciWritePipe, USB_HostEhciReadpipe, USB_HostEhciIoctl, +}; +#endif /* USB_HOST_CONFIG_EHCI */ + +#if ((defined USB_HOST_CONFIG_KHCI) && (USB_HOST_CONFIG_KHCI)) +#include "usb_host_khci.h" +static const usb_host_controller_interface_t s_KhciInterface = \ +{ + USB_HostKhciCreate, USB_HostKhciDestory, USB_HostKhciOpenPipe, USB_HostKhciClosePipe, + USB_HostKhciWritePipe, USB_HostKhciReadpipe, USB_HostKciIoctl, +}; +#endif /* USB_HOST_CONFIG_KHCI */ + +#if ((defined USB_HOST_CONFIG_OHCI) && (USB_HOST_CONFIG_OHCI > 0U)) +#include "usb_host_ohci.h" +static const usb_host_controller_interface_t s_OhciInterface = \ +{ + USB_HostOhciCreate, USB_HostOhciDestory, USB_HostOhciOpenPipe, USB_HostOhciClosePipe, + USB_HostOhciWritePipe, USB_HostOhciReadPipe, USB_HostOhciIoctl, +}; +#endif /* USB_HOST_CONFIG_OHCI */ + +#if ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS > 0U)) +#include "usb_host_ip3516hs.h" +static const usb_host_controller_interface_t s_Ip3516HsInterface = \ +{ + USB_HostIp3516HsCreate, USB_HostIp3516HsDestory, USB_HostIp3516HsOpenPipe, USB_HostIp3516HsClosePipe, + USB_HostIp3516HsWritePipe, USB_HostIp3516HsReadPipe, USB_HostIp3516HsIoctl, +}; +#endif /* USB_HOST_CONFIG_IP3516HS */ + +USB_DMA_NONINIT_DATA_ALIGN(USB_DATA_ALIGN_SIZE) static uint8_t s_Setupbuffer[USB_HOST_CONFIG_MAX_HOST][USB_HOST_CONFIG_MAX_TRANSFERS][USB_DATA_ALIGN_SIZE_MULTIPLE(8)]; +/******************************************************************************* +* Code +******************************************************************************/ + +#if ((defined USB_HOST_CONFIG_COMPLIANCE_TEST) && (USB_HOST_CONFIG_COMPLIANCE_TEST)) +/*FUNCTION*---------------------------------------------------------------- +* +* Function Name : usb_test_mode_init +* Returned Value : None +* Comments : +* This function is called by common class to initialize the class driver. It +* is called in response to a select interface call by application +* +*END*--------------------------------------------------------------------*/ +usb_status_t USB_HostTestModeInit(usb_device_handle deviceHandle) +{ +#if (((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) || \ + ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS))) + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)deviceInstance->hostHandle; +#endif + uint32_t productId; + uint32_t vendorId; + + usb_echo("usb host test init\r\n"); + USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetDevicePID, &productId); + USB_HostHelperGetPeripheralInformation(deviceHandle, kUSB_HostGetDeviceVID, &vendorId); + usb_echo(" vendor id :0x%x product id:0x%x \r\n", vendorId, productId); + + if ((productId != 0x0200U) && (productId != 0x0101) && (productId != 0x0102) && (productId != 0x0103) && + (productId != 0x0104) && (productId != 0x0105) && (productId != 0x0106) && (productId != 0x0107) && + (productId != 0x0108)) + { + usb_echo("Unsupported Device\r\n"); + } + + if (productId == 0x0200U) + { + usb_echo("PET test device attached\r\n"); + } + else + { +#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) + if (hostInstance->controllerTable == &s_EhciInterface) + { + USB_HostEhciTestModeInit(deviceHandle); + } +#elif((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS)) + if (hostInstance->controllerTable == &s_Ip3516HsInterface) + { + USB_HostIp3516HsTestModeInit(deviceHandle); + } +#endif + } + + return kStatus_USB_Success; +} +#endif + +static usb_host_instance_t *USB_HostGetInstance(void) +{ + uint8_t i = 0; + uint32_t index = 0; + USB_OSA_SR_ALLOC(); + USB_OSA_ENTER_CRITICAL(); + for (; i < USB_HOST_CONFIG_MAX_HOST; i++) + { + if (g_UsbHostInstance[i].occupied != 1) + { + uint8_t *buffer = (uint8_t *)&g_UsbHostInstance[i]; + for (uint32_t j = 0U; j < sizeof(usb_host_instance_t); j++) + { + buffer[j] = 0x00U; + } + g_UsbHostInstance[i].occupied = 1; + USB_OSA_EXIT_CRITICAL(); + for (index = 0; index < USB_HOST_CONFIG_MAX_TRANSFERS; ++index) + { + g_UsbHostInstance[i].transferList[index].setupPacket = + (usb_setup_struct_t *)&(s_Setupbuffer[i][index][0]); + } + return &g_UsbHostInstance[i]; + } + } + USB_OSA_EXIT_CRITICAL(); + return NULL; +} + +static void USB_HostReleaseInstance(usb_host_instance_t *hostInstance) +{ + USB_OSA_SR_ALLOC(); + USB_OSA_ENTER_CRITICAL(); + hostInstance->occupied = 0; + USB_OSA_EXIT_CRITICAL(); +} + +static void USB_HostGetControllerInterface(uint8_t controllerId, + const usb_host_controller_interface_t **controllerTable) +{ +#if ((defined USB_HOST_CONFIG_KHCI) && (USB_HOST_CONFIG_KHCI)) + if (controllerId == kUSB_ControllerKhci0) + { + *controllerTable = &s_KhciInterface; + } +#endif /* USB_HOST_CONFIG_KHCI */ + +#if ((defined USB_HOST_CONFIG_EHCI) && (USB_HOST_CONFIG_EHCI)) + if ((controllerId == kUSB_ControllerEhci0) || (controllerId == kUSB_ControllerEhci1)) + { + *controllerTable = &s_EhciInterface; + } +#endif /* USB_HOST_CONFIG_EHCI */ + +#if ((defined USB_HOST_CONFIG_OHCI) && (USB_HOST_CONFIG_OHCI > 0U)) + if (controllerId == kUSB_ControllerOhci0) + { + *controllerTable = &s_OhciInterface; + } +#endif /* USB_HOST_CONFIG_OHCI */ + +#if ((defined USB_HOST_CONFIG_IP3516HS) && (USB_HOST_CONFIG_IP3516HS > 0U)) + if (controllerId == kUSB_ControllerIp3516Hs0) + { + *controllerTable = &s_Ip3516HsInterface; + } +#endif /* USB_HOST_CONFIG_IP3516HS */ +} + +usb_status_t USB_HostInit(uint8_t controllerId, usb_host_handle *hostHandle, host_callback_t callbackFn) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = NULL; + usb_host_transfer_t *transferPrev = NULL; + uint8_t i = 0; + + hostInstance = USB_HostGetInstance(); /* get one host instance */ + if (hostInstance == NULL) + { + return kStatus_USB_InvalidHandle; + } + + /* get khci/ehci API table */ + USB_HostGetControllerInterface(controllerId, &hostInstance->controllerTable); + if (hostInstance->controllerTable == NULL) + { + USB_HostReleaseInstance(hostInstance); + return kStatus_USB_ControllerNotFound; + } + + /* judge the controller interface one time at here */ + if ((hostInstance->controllerTable->controllerCreate == NULL) || + (hostInstance->controllerTable->controllerDestory == NULL) || + (hostInstance->controllerTable->controllerOpenPipe == NULL) || + (hostInstance->controllerTable->controllerClosePipe == NULL) || + (hostInstance->controllerTable->controllerWritePipe == NULL) || + (hostInstance->controllerTable->controllerReadPipe == NULL) || + (hostInstance->controllerTable->controllerIoctl == NULL)) + { + return kStatus_USB_Error; + } + + /* HOST instance init*/ + hostInstance->controllerId = controllerId; + hostInstance->deviceCallback = callbackFn; + hostInstance->deviceList = NULL; + if (kStatus_USB_OSA_Success != USB_OsaMutexCreate(&hostInstance->hostMutex)) + { + USB_HostReleaseInstance(hostInstance); +#ifdef HOST_ECHO + usb_echo("host init: create host mutex fail\r\n"); +#endif + return kStatus_USB_Error; + } + + /* initialize transfer list */ + + hostInstance->transferHead = &hostInstance->transferList[0]; + transferPrev = hostInstance->transferHead; + for (i = 1; i < USB_HOST_CONFIG_MAX_TRANSFERS; ++i) + { + transferPrev->next = &hostInstance->transferList[i]; + transferPrev = transferPrev->next; + } + + /* controller create */ + status = + hostInstance->controllerTable->controllerCreate(controllerId, hostInstance, &(hostInstance->controllerHandle)); + if ((status != kStatus_USB_Success) || (hostInstance->controllerHandle == NULL)) + { + USB_OsaMutexDestroy(hostInstance->hostMutex); + USB_HostReleaseInstance(hostInstance); +#ifdef HOST_ECHO + usb_echo("host init: controller init fail\r\n"); +#endif + return kStatus_USB_Error; + } + + *hostHandle = hostInstance; + return kStatus_USB_Success; +} + +usb_status_t USB_HostDeinit(usb_host_handle hostHandle) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + usb_host_device_instance_t *deviceInstance = NULL; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + /* device list detach */ + deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; + while (deviceInstance != NULL) + { + deviceInstance = (usb_host_device_instance_t *)hostInstance->deviceList; + USB_HostDetachDeviceInternal(hostHandle, deviceInstance); + } + + /* controller instance destory */ + status = hostInstance->controllerTable->controllerDestory(hostInstance->controllerHandle); + hostInstance->controllerHandle = NULL; + if (status != kStatus_USB_Success) + { +#ifdef HOST_ECHO + usb_echo("host controller destory fail\r\n"); +#endif + } + + /* resource release */ + if (hostInstance->hostMutex) + { + USB_OsaMutexDestroy(hostInstance->hostMutex); + hostInstance->hostMutex = NULL; + } + USB_HostReleaseInstance(hostInstance); + + return status; +} + +usb_status_t USB_HostOpenPipe(usb_host_handle hostHandle, + usb_host_pipe_handle *pipeHandle, + usb_host_pipe_init_t *pipeInit) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (pipeInit == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* call controller open pipe interface */ + status = hostInstance->controllerTable->controllerOpenPipe(hostInstance->controllerHandle, pipeHandle, pipeInit); + + return status; +} + +usb_status_t USB_HostClosePipe(usb_host_handle hostHandle, usb_host_pipe_handle pipeHandle) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (pipeHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* call controller close pipe interface */ + status = hostInstance->controllerTable->controllerClosePipe(hostInstance->controllerHandle, pipeHandle); + + return status; +} + +usb_status_t USB_HostSend(usb_host_handle hostHandle, usb_host_pipe_handle pipeHandle, usb_host_transfer_t *transfer) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (pipeHandle == NULL) || (transfer == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* initialize transfer */ + transfer->transferSofar = 0; + transfer->direction = USB_OUT; + + USB_HostLock(); /* This api can be called by host task and app task */ +/* keep this code: in normal situation application will guarantee the device is attached when call send/receive function + */ +#if 0 + if ((USB_HostValidateDevice(pipe_ptr->deviceHandle) != kStatus_USB_Success) || (!(USB_HostGetDeviceAttachState(pipe_ptr->deviceHandle)))) + { + USB_HostUnlock(); + return status; + } +#endif +/* call controller write pipe interface */ +#if ((defined USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + if (transfer->transferLength > 0) + { + DCACHE_CleanByRange((uint32_t)transfer->transferBuffer, transfer->transferLength); + } +#endif + status = hostInstance->controllerTable->controllerWritePipe(hostInstance->controllerHandle, pipeHandle, transfer); + + USB_HostUnlock(); + return status; +} + +usb_status_t USB_HostSendSetup(usb_host_handle hostHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (pipeHandle == NULL) || (transfer == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* initialize transfer */ + transfer->transferSofar = 0; + transfer->next = NULL; + transfer->setupStatus = 0; + if ((transfer->setupPacket->bmRequestType & USB_REQUEST_TYPE_DIR_MASK) == USB_REQUEST_TYPE_DIR_IN) + { + transfer->direction = USB_IN; + } + else + { + transfer->direction = USB_OUT; + } + + USB_HostLock(); /* This API can be called by host task and application task */ +/* keep this code: in normal situation application will guarantee the device is attached when call send/receive function + */ +#if 0 + if ((USB_HostValidateDevice(pipe_ptr->deviceHandle) != kStatus_USB_Success) || (!(USB_HostGetDeviceAttachState(pipe_ptr->deviceHandle)))) + { + USB_HostUnlock(); + return status; + } +#endif +/* call controller write pipe interface */ +#if ((defined USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + DCACHE_CleanByRange((uint32_t)&transfer->setupPacket->bmRequestType, sizeof(usb_setup_struct_t)); + if (transfer->transferLength > 0) + { + DCACHE_CleanInvalidateByRange((uint32_t)transfer->transferBuffer, transfer->transferLength); + } +#endif + status = hostInstance->controllerTable->controllerWritePipe(hostInstance->controllerHandle, pipeHandle, transfer); + + USB_HostUnlock(); + return status; +} + +usb_status_t USB_HostRecv(usb_host_handle hostHandle, usb_host_pipe_handle pipeHandle, usb_host_transfer_t *transfer) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (pipeHandle == NULL) || (transfer == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* initialize transfer */ + transfer->transferSofar = 0; + transfer->direction = USB_IN; + + USB_HostLock(); /* This API can be called by host task and application task */ +/* keep this code: in normal situation application will guarantee the device is attached when call send/receive function + */ +#if 0 + if ((USB_HostValidateDevice(pipe_ptr->deviceHandle) != kStatus_USB_Success) || (!(USB_HostGetDeviceAttachState(pipe_ptr->deviceHandle)))) + { + USB_HostUnlock(); + return status; + } +#endif + +#if ((defined USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + if (transfer->transferLength > 0) + { + DCACHE_CleanInvalidateByRange((uint32_t)transfer->transferBuffer, transfer->transferLength); + } +#endif + status = hostInstance->controllerTable->controllerReadPipe(hostInstance->controllerHandle, pipeHandle, transfer); + + USB_HostUnlock(); + return status; +} + +usb_status_t USB_HostCancelTransfer(usb_host_handle hostHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer) +{ + usb_status_t status = kStatus_USB_Success; + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + usb_host_cancel_param_t cancelParam; + + if ((hostHandle == NULL) || (pipeHandle == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* initialize cancel parameter */ + cancelParam.pipeHandle = pipeHandle; + cancelParam.transfer = transfer; + + /* USB_HostLock(); This api can be called by host task and app task */ + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostCancelTransfer, + &cancelParam); + /* USB_HostUnlock(); */ + + return status; +} + +usb_status_t USB_HostMallocTransfer(usb_host_handle hostHandle, usb_host_transfer_t **transfer) +{ + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if ((hostHandle == NULL) || (transfer == NULL)) + { + return kStatus_USB_InvalidHandle; + } + + /* get one from the transfer_head */ + USB_HostLock(); + if (hostInstance->transferHead != NULL) + { + *transfer = hostInstance->transferHead; + hostInstance->transferHead = hostInstance->transferHead->next; + USB_HostUnlock(); + return kStatus_USB_Success; + } + else + { + *transfer = NULL; + USB_HostUnlock(); + return kStatus_USB_Error; + } +} + +usb_status_t USB_HostFreeTransfer(usb_host_handle hostHandle, usb_host_transfer_t *transfer) +{ + usb_host_instance_t *hostInstance = (usb_host_instance_t *)hostHandle; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + if (transfer == NULL) + { + return kStatus_USB_Success; + } + + /* release one to the transfer_head */ + USB_HostLock(); + transfer->next = hostInstance->transferHead; + hostInstance->transferHead = transfer; + USB_HostUnlock(); + return kStatus_USB_Success; +} + +usb_status_t USB_HostHelperGetPeripheralInformation(usb_device_handle deviceHandle, + uint32_t infoCode, + uint32_t *infoValue) +{ + usb_host_device_instance_t *deviceInstance = (usb_host_device_instance_t *)deviceHandle; + if ((deviceHandle == NULL) || (infoValue == NULL)) + { + return kStatus_USB_InvalidParameter; + } + + switch (infoCode) + { + case kUSB_HostGetDeviceAddress: /* device address */ + *infoValue = (uint32_t)deviceInstance->setAddress; + break; + + case kUSB_HostGetDeviceControlPipe: /* device control pipe */ + *infoValue = (uint32_t)deviceInstance->controlPipe; + break; + + case kUSB_HostGetHostHandle: /* device host handle */ + *infoValue = (uint32_t)deviceInstance->hostHandle; + break; + +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + case kUSB_HostGetDeviceHubNumber: /* device hub address */ + *infoValue = (uint32_t)deviceInstance->hubNumber; + break; + + case kUSB_HostGetDevicePortNumber: /* device port no */ + *infoValue = (uint32_t)deviceInstance->portNumber; + break; + + case kUSB_HostGetDeviceLevel: /* device level */ + *infoValue = (uint32_t)deviceInstance->level; + break; + + case kUSB_HostGetDeviceHSHubNumber: /* device high-speed hub address */ + *infoValue = (uint32_t)deviceInstance->hsHubNumber; + break; + + case kUSB_HostGetDeviceHSHubPort: /* device high-speed hub port no */ + *infoValue = (uint32_t)deviceInstance->hsHubPort; + break; + + case kUSB_HostGetHubThinkTime: /* device hub think time */ + *infoValue = USB_HostHubGetTotalThinkTime(deviceInstance->hostHandle, deviceInstance->hubNumber); + break; +#else + case kUSB_HostGetDeviceHubNumber: /* device hub address */ + case kUSB_HostGetDevicePortNumber: /* device port no */ + case kUSB_HostGetDeviceHSHubNumber: /* device high-speed hub address */ + case kUSB_HostGetDeviceHSHubPort: /* device high-speed hub port no */ + case kUSB_HostGetHubThinkTime: /* device hub think time */ + *infoValue = 0; + break; + case kUSB_HostGetDeviceLevel: /* device level */ + *infoValue = 1; + break; +#endif /* USB_HOST_CONFIG_HUB */ + + case kUSB_HostGetDeviceSpeed: /* device speed */ + *infoValue = (uint32_t)deviceInstance->speed; + break; + + case kUSB_HostGetDevicePID: /* device pid */ + *infoValue = (uint32_t)USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(deviceInstance->deviceDescriptor->idProduct); + break; + + case kUSB_HostGetDeviceVID: /* device vid */ + *infoValue = (uint32_t)USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(deviceInstance->deviceDescriptor->idVendor); + break; + + case kUSB_HostGetDeviceConfigIndex: /* device config index */ + *infoValue = (uint32_t)deviceInstance->configurationValue - 1U; + break; + + case kUSB_HostGetConfigurationDes: /* configuration descriptor pointer */ + *infoValue = (uint32_t)deviceInstance->configurationDesc; + break; + + case kUSB_HostGetConfigurationLength: /* configuration descriptor length */ + *infoValue = (uint32_t)deviceInstance->configurationLen; + break; + + default: + return kStatus_USB_Error; + } + + return kStatus_USB_Success; +} + +usb_status_t USB_HostHelperParseAlternateSetting(usb_host_interface_handle interfaceHandle, + uint8_t alternateSetting, + usb_host_interface_t *interface) +{ + uint32_t endPosition; + usb_descriptor_union_t *unionDes; + usb_host_ep_t *epParse; + + if (interfaceHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + + if (alternateSetting == 0) + { + return kStatus_USB_InvalidParameter; + } + + /* parse configuration descriptor */ + unionDes = (usb_descriptor_union_t *)((usb_host_interface_t *)interfaceHandle) + ->interfaceDesc; /* interface extend descriptor start */ + endPosition = + (uint32_t)unionDes + + ((usb_host_interface_t *)interfaceHandle)->interfaceExtensionLength; /* interface extend descriptor end */ + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + + /* search for the alternate setting interface descritpor */ + while ((uint32_t)unionDes < endPosition) + { + if (unionDes->interface.bDescriptorType == USB_DESCRIPTOR_TYPE_INTERFACE) + { + if (unionDes->interface.bAlternateSetting == alternateSetting) + { + break; + } + else + { + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + } + else + { + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + } + if ((uint32_t)unionDes >= endPosition) + { + return kStatus_USB_Error; + } + + /* initialize interface handle structure instance */ + interface->interfaceDesc = &unionDes->interface; + interface->alternateSettingNumber = 0; + interface->epCount = 0; + interface->interfaceExtension = NULL; + interface->interfaceExtensionLength = 0; + interface->interfaceIndex = unionDes->interface.bInterfaceNumber; + + /* search for endpoint descriptor start position */ + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPosition) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE) && + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) + { + if (interface->interfaceExtension == NULL) + { + interface->interfaceExtension = (uint8_t *)unionDes; + } + interface->interfaceExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + + /* parse endpoint descriptor */ + if (interface->interfaceDesc->bNumEndpoints != 0) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) || + (interface->interfaceDesc->bNumEndpoints > USB_HOST_CONFIG_INTERFACE_MAX_EP)) + { +#ifdef HOST_ECHO + usb_echo("interface descriptor error\n"); +#endif + return kStatus_USB_Error; + } + for (; interface->epCount < interface->interfaceDesc->bNumEndpoints; (interface->epCount)++) + { + if (((uint32_t)unionDes >= endPosition) || + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT)) + { +#ifdef HOST_ECHO + usb_echo("endpoint descriptor error\n"); +#endif + return kStatus_USB_Error; + } + epParse = (usb_host_ep_t *)&interface->epList[interface->epCount]; + epParse->epDesc = (usb_descriptor_endpoint_t *)unionDes; + epParse->epExtensionLength = 0; + epParse->epExtension = NULL; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + while ((uint32_t)unionDes < endPosition) + { + if ((unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_ENDPOINT) && + (unionDes->common.bDescriptorType != USB_DESCRIPTOR_TYPE_INTERFACE)) + { + if (epParse->epExtension == NULL) + { + epParse->epExtension = (uint8_t *)unionDes; + } + epParse->epExtensionLength += unionDes->common.bLength; + unionDes = (usb_descriptor_union_t *)((uint32_t)unionDes + unionDes->common.bLength); + } + else + { + break; + } + } + } + } + + return kStatus_USB_Success; +} + +void USB_HostGetVersion(uint32_t *version) +{ + if (version) + { + *version = + (uint32_t)USB_MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX); + } +} + +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) +/* Send BUS or specific device suepend request */ +usb_status_t USB_HostSuspendDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_instance_t *hostInstance; + usb_host_device_instance_t *deviceInstance; + usb_status_t status = kStatus_USB_Error; + usb_host_bus_control_t type = kUSB_HostBusSuspend; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + hostInstance->suspendedDevice = (void *)deviceHandle; + + if (NULL == deviceHandle) + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + status = USB_HostHubSuspendDevice(hostInstance); +#else + status = + hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type); +#endif + } + else + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + deviceInstance = (usb_host_device_instance_t *)deviceHandle; + if (0 == deviceInstance->hubNumber) + { +#endif + if (hostInstance->deviceList == deviceHandle) + { + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, + kUSB_HostBusControl, &type); + } +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + } + else + { + if (kStatus_USB_Success == USB_HostValidateDevice(hostInstance, deviceHandle)) + { + status = USB_HostHubSuspendDevice(hostInstance); + } + } +#endif + } + if (kStatus_USB_Error == status) + { + hostInstance->suspendedDevice = NULL; + } + return status; +} + +/* Send BUS or specific device resume request */ +usb_status_t USB_HostResumeDeviceResquest(usb_host_handle hostHandle, usb_device_handle deviceHandle) +{ + usb_host_instance_t *hostInstance; + usb_host_device_instance_t *deviceInstance; + usb_status_t status = kStatus_USB_Error; + usb_host_bus_control_t type = kUSB_HostBusResume; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + if (hostInstance->suspendedDevice != deviceHandle) + { + return kStatus_USB_InvalidParameter; + } + hostInstance->suspendedDevice = (void *)deviceHandle; + + if (NULL == deviceHandle) + { + status = + hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type); + } + else + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + deviceInstance = (usb_host_device_instance_t *)deviceHandle; + if (0 == deviceInstance->hubNumber) + { +#endif + if (hostInstance->deviceList == deviceHandle) + { + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, + kUSB_HostBusControl, &type); + } +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) + } + else + { + if (kStatus_USB_Success == USB_HostValidateDevice(hostInstance, deviceHandle)) + { + status = USB_HostHubResumeDevice(hostInstance); + } + } +#endif + } + + return status; +} +#if ((defined(USB_HOST_CONFIG_LPM_L1)) && (USB_HOST_CONFIG_LPM_L1 > 0U)) +/* Send BUS or specific device suepend request */ +usb_status_t USB_HostL1SleepDeviceResquest(usb_host_handle hostHandle, + usb_device_handle deviceHandle, + uint8_t sleepType) +{ + usb_host_instance_t *hostInstance; + usb_status_t status = kStatus_USB_Error; + usb_host_bus_control_t type = kUSB_HostBusL1Sleep; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + hostInstance->suspendedDevice = (void *)deviceHandle; + + if (1U == sleepType) + { + /*#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB))*/ + /*To do, implete hub L1 suspend device*/ + /*#else*/ + status = + hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type); + /*#endif*/ + } + else + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) +/*To do, if device hub number is 0, need suspend the bus ,else suspend the corresponding device*/ +#endif + if (hostInstance->deviceList == deviceHandle) + { + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, + &type); + } + } + if (kStatus_USB_Error == status) + { + hostInstance->suspendedDevice = NULL; + } + return status; +} +/* Send BUS or specific device suepend request */ +usb_status_t USB_HostL1SleepDeviceResquestConfig(usb_host_handle hostHandle, uint8_t *lpmParam) +{ + usb_host_instance_t *hostInstance; + usb_status_t status = kStatus_USB_Error; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + status = + hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostL1Config, lpmParam); + + return status; +} + +/* Send BUS or specific device resume request */ +usb_status_t USB_HostL1ResumeDeviceResquest(usb_host_handle hostHandle, + usb_device_handle deviceHandle, + uint8_t sleepType) +{ + usb_host_instance_t *hostInstance; + + usb_status_t status = kStatus_USB_Error; + usb_host_bus_control_t type = kUSB_HostBusL1Resume; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + if (1U == sleepType) + { + status = + hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, &type); + } + else + { +#if ((defined USB_HOST_CONFIG_HUB) && (USB_HOST_CONFIG_HUB)) +/*To do, if device hub number is 0, need suspend the bus ,else suspend the corresponding device*/ + +#endif + if (hostInstance->deviceList == deviceHandle) + { + status = hostInstance->controllerTable->controllerIoctl(hostInstance->controllerHandle, kUSB_HostBusControl, + &type); + } + } + + return status; +} +#endif +/* Update HW tick(unit is ms) */ +usb_status_t USB_HostUpdateHwTick(usb_host_handle hostHandle, uint64_t tick) +{ + usb_host_instance_t *hostInstance; + usb_status_t status = kStatus_USB_Success; + + if (hostHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + hostInstance = (usb_host_instance_t *)hostHandle; + + hostInstance->hwTick = tick; + + return status; +} +#endif diff --git a/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.h b/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.h new file mode 100644 index 0000000000000000000000000000000000000000..26b6d4a9c56f7c650999acc1924bbb3dca01e252 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/host/usb_host_hci.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_HOST_HCI_H_ +#define _USB_HOST_HCI_H_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief USB host lock */ +#define USB_HostLock() USB_OsaMutexLock(hostInstance->hostMutex) +/*! @brief USB host unlock */ +#define USB_HostUnlock() USB_OsaMutexUnlock(hostInstance->hostMutex) + +/*! + * @addtogroup usb_host_controller_driver + * @{ + */ + +/*! @brief USB host controller control code */ +typedef enum _usb_host_controller_control +{ + kUSB_HostCancelTransfer = 1U, /*!< Cancel transfer code */ + kUSB_HostBusControl, /*!< Bus control code */ + kUSB_HostGetFrameNumber, /*!< Get frame number code */ + kUSB_HostUpdateControlEndpointAddress, /*!< Update control endpoint address */ + kUSB_HostUpdateControlPacketSize, /*!< Update control endpoint maximum packet size */ + kUSB_HostPortAttachDisable, /*!< Disable the port attach event */ + kUSB_HostPortAttachEnable, /*!< Enable the port attach event */ + kUSB_HostL1Config, /*!< L1 suspend Bus control code */ +} usb_host_controller_control_t; + +/*! @brief USB host controller bus control code */ +typedef enum _usb_host_bus_control +{ + kUSB_HostBusReset = 1U, /*!< Reset bus */ + kUSB_HostBusRestart, /*!< Restart bus */ + kUSB_HostBusEnableAttach, /*!< Enable attach */ + kUSB_HostBusDisableAttach, /*!< Disable attach */ + kUSB_HostBusSuspend, /*!< Suspend BUS */ + kUSB_HostBusResume, /*!< Resume BUS */ + kUSB_HostBusL1SuspendInit, /*!< L1 Suspend BUS */ + kUSB_HostBusL1Sleep, /*!< L1 Suspend BUS */ + kUSB_HostBusL1Resume, /*!< L1 Resume BUS */ +} usb_host_bus_control_t; + +/*! @brief USB host controller interface structure */ +typedef struct _usb_host_controller_interface +{ + usb_status_t (*controllerCreate)( + uint8_t controllerId, + usb_host_handle upperLayerHandle, + usb_host_controller_handle *controllerHandle); /*!< Create a controller instance function prototype*/ + usb_status_t (*controllerDestory)( + usb_host_controller_handle controllerHandle); /*!< Destroy a controller instance function prototype*/ + usb_status_t (*controllerOpenPipe)(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle *pipeHandle, + usb_host_pipe_init_t *pipeInit); /*!< Open a controller pipe function prototype*/ + usb_status_t (*controllerClosePipe)( + usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle); /*!< Close a controller pipe function prototype*/ + usb_status_t (*controllerWritePipe)(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer); /*!< Write data to a pipe function prototype*/ + usb_status_t (*controllerReadPipe)(usb_host_controller_handle controllerHandle, + usb_host_pipe_handle pipeHandle, + usb_host_transfer_t *transfer); /*!< Read data from a pipe function prototype*/ + usb_status_t (*controllerIoctl)(usb_host_controller_handle controllerHandle, + uint32_t ioctlEvent, + void *ioctlParam); /*!< Control a controller function prototype*/ +} usb_host_controller_interface_t; + +/*! @}*/ + +/*! + * @addtogroup usb_host_drv + * @{ + */ + +/*! @brief USB host instance structure */ +typedef struct _usb_host_instance +{ + void *controllerHandle; /*!< The low level controller handle*/ + host_callback_t deviceCallback; /*!< Device attach/detach callback*/ + usb_osa_mutex_handle hostMutex; /*!< Host layer mutex*/ + usb_host_transfer_t transferList[USB_HOST_CONFIG_MAX_TRANSFERS]; /*!< Transfer resource*/ + usb_host_transfer_t *transferHead; /*!< Idle transfer head*/ + const usb_host_controller_interface_t *controllerTable; /*!< KHCI/EHCI interface*/ + void *deviceList; /*!< Device list*/ +#if ((defined(USB_HOST_CONFIG_LOW_POWER_MODE)) && (USB_HOST_CONFIG_LOW_POWER_MODE > 0U)) + void *suspendedDevice; /*!< Suspended device handle*/ + volatile uint64_t hwTick; /*!< Current hw tick(ms)*/ + uint8_t sleepType; /*!< L1 LPM device handle*/ +#endif + uint8_t addressBitMap[16]; /*!< Used for address allocation. The first bit is the address 1, second bit is the + address 2*/ + uint8_t occupied; /*!< 0 - the instance is not occupied; 1 - the instance is occupied*/ + uint8_t controllerId; /*!< The controller ID*/ +} usb_host_instance_t; + +/*! @}*/ + +#endif /* _USB_HOST_HCI_H_ */ diff --git a/bsp/imxrt/libraries/drivers/usb/include/usb.h b/bsp/imxrt/libraries/drivers/usb/include/usb.h new file mode 100644 index 0000000000000000000000000000000000000000..256896b472c96ed5aa4ffa4d72f75f0bff5ec080 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/include/usb.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_H__ +#define __USB_H__ + +#include +#include +#include +#include "usb_misc.h" +#include "usb_spec.h" + +/*! + * @addtogroup usb_drv + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Defines USB stack major version */ +#define USB_STACK_VERSION_MAJOR (1U) +/*! @brief Defines USB stack minor version */ +#define USB_STACK_VERSION_MINOR (6U) +/*! @brief Defines USB stack bugfix version */ +#define USB_STACK_VERSION_BUGFIX (3U) + +/*! @brief USB stack version definition */ +#define USB_MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @brief USB error code */ +typedef enum _usb_status +{ + kStatus_USB_Success = 0x00U, /*!< Success */ + kStatus_USB_Error, /*!< Failed */ + + kStatus_USB_Busy, /*!< Busy */ + kStatus_USB_InvalidHandle, /*!< Invalid handle */ + kStatus_USB_InvalidParameter, /*!< Invalid parameter */ + kStatus_USB_InvalidRequest, /*!< Invalid request */ + kStatus_USB_ControllerNotFound, /*!< Controller cannot be found */ + kStatus_USB_InvalidControllerInterface, /*!< Invalid controller interface */ + + kStatus_USB_NotSupported, /*!< Configuration is not supported */ + kStatus_USB_Retry, /*!< Enumeration get configuration retry */ + kStatus_USB_TransferStall, /*!< Transfer stalled */ + kStatus_USB_TransferFailed, /*!< Transfer failed */ + kStatus_USB_AllocFail, /*!< Allocation failed */ + kStatus_USB_LackSwapBuffer, /*!< Insufficient swap buffer for KHCI */ + kStatus_USB_TransferCancel, /*!< The transfer cancelled */ + kStatus_USB_BandwidthFail, /*!< Allocate bandwidth failed */ + kStatus_USB_MSDStatusFail, /*!< For MSD, the CSW status means fail */ + kStatus_USB_EHCIAttached, + kStatus_USB_EHCIDetached, +} usb_status_t; + +/*! @brief USB host handle type define */ +typedef void *usb_host_handle; + +/*! @brief USB device handle type define. For device stack it is the whole device handle; for host stack it is the + * attached device instance handle*/ +typedef void *usb_device_handle; + +/*! @brief USB OTG handle type define */ +typedef void *usb_otg_handle; + +/*! @brief USB controller ID */ +typedef enum _usb_controller_index +{ + kUSB_ControllerKhci0 = 0U, /*!< KHCI 0U */ + kUSB_ControllerKhci1 = 1U, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs, this is reserved + to be used in the future. */ + kUSB_ControllerEhci0 = 2U, /*!< EHCI 0U */ + kUSB_ControllerEhci1 = 3U, /*!< EHCI 1U, Currently, there are no platforms which have two EHCI IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerLpcIp3511Fs0 = 4U, /*!< LPC USB IP3511 FS controller 0 */ + kUSB_ControllerLpcIp3511Fs1 = + 5U, /*!< LPC USB IP3511 FS controller 1, there are no platforms which have two IP3511 IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerLpcIp3511Hs0 = 6U, /*!< LPC USB IP3511 HS controller 0 */ + kUSB_ControllerLpcIp3511Hs1 = + 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which have two IP3511 IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerOhci0 = 8U, /*!< OHCI 0U */ + kUSB_ControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerIp3516Hs0 = 10U, /*!< IP3516HS 0U */ + kUSB_ControllerIp3516Hs1 = + 11U, /*!< IP3516HS 1U, Currently, there are no platforms which have two IP3516HS IPs, this is reserved + to be used in the future. */ +} usb_controller_index_t; + +/** +* @brief USB stack version fields +*/ +typedef struct _usb_version +{ + uint8_t major; /*!< Major */ + uint8_t minor; /*!< Minor */ + uint8_t bugfix; /*!< Bug fix */ +} usb_version_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! @} */ + +#endif /* __USB_H__ */ diff --git a/bsp/imxrt/libraries/drivers/usb/include/usb_device_config.h b/bsp/imxrt/libraries/drivers/usb/include/usb_device_config.h new file mode 100644 index 0000000000000000000000000000000000000000..551d92edc7e27c12248839ebe7529170da08f9f0 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/include/usb_device_config.h @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _USB_DEVICE_CONFIG_H_ +#define _USB_DEVICE_CONFIG_H_ + +/******************************************************************************* +* Definitions +******************************************************************************/ +/*! + * @addtogroup usb_device_configuration + * @{ + */ + +/*! + * @name Hardware instance define + * @{ + */ + +/*! @brief KHCI instance count */ +#define USB_DEVICE_CONFIG_KHCI (0U) + +/*! @brief EHCI instance count */ +#define USB_DEVICE_CONFIG_EHCI (2U) + +/*! @brief LPC USB IP3511 FS instance count */ +#define USB_DEVICE_CONFIG_LPCIP3511FS (0U) + +/*! @brief LPC USB IP3511 HS instance count */ +#define USB_DEVICE_CONFIG_LPCIP3511HS (0U) + +/*! @brief Device instance count, the sum of KHCI and EHCI instance counts*/ +#define USB_DEVICE_CONFIG_NUM \ + (USB_DEVICE_CONFIG_KHCI + USB_DEVICE_CONFIG_EHCI + USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS) + +/* @} */ + +/*! + * @name class instance define + * @{ + */ + +/*! @brief HID instance count */ +#define USB_DEVICE_CONFIG_HID (0U) + +/*! @brief CDC ACM instance count */ +#define USB_DEVICE_CONFIG_CDC_ACM (1U) + +/*! @brief MSC instance count */ +#define USB_DEVICE_CONFIG_MSC (0U) + +/*! @brief Audio instance count */ +#define USB_DEVICE_CONFIG_AUDIO (0U) + +/*! @brief PHDC instance count */ +#define USB_DEVICE_CONFIG_PHDC (0U) + +/*! @brief Video instance count */ +#define USB_DEVICE_CONFIG_VIDEO (0U) + +/*! @brief CCID instance count */ +#define USB_DEVICE_CONFIG_CCID (0U) + +/*! @brief Printer instance count */ +#define USB_DEVICE_CONFIG_PRINTER (0U) + +/*! @brief DFU instance count */ +#define USB_DEVICE_CONFIG_DFU (0U) + +/* @} */ + +/*! @brief Whether device is self power. 1U supported, 0U not supported */ +#define USB_DEVICE_CONFIG_SELF_POWER (1U) + +/*! @brief How many endpoints are supported in the stack. */ +#define USB_DEVICE_CONFIG_ENDPOINTS (4U) + +/*! @brief Whether the device task is enabled. */ +#define USB_DEVICE_CONFIG_USE_TASK (0U) + +/*! @brief How many the notification message are supported when the device task is enabled. */ +#define USB_DEVICE_CONFIG_MAX_MESSAGES (8U) + +/*! @brief Whether test mode enabled. */ +#define USB_DEVICE_CONFIG_USB20_TEST_MODE (0U) + +/*! @brief Whether device CV test is enabled. */ +#define USB_DEVICE_CONFIG_CV_TEST (0U) + +/*! @brief Whether device compliance test is enabled. If the macro is enabled, + the test mode and CV test macroes will be set.*/ +#define USB_DEVICE_CONFIG_COMPLIANCE_TEST (0U) + +#if ((defined(USB_DEVICE_CONFIG_COMPLIANCE_TEST)) && (USB_DEVICE_CONFIG_COMPLIANCE_TEST > 0U)) + +/*! @brief Undefine the marco USB_DEVICE_CONFIG_USB20_TEST_MODE. */ +#undef USB_DEVICE_CONFIG_USB20_TEST_MODE +/*! @brief Undefine the marco USB_DEVICE_CONFIG_CV_TEST. */ +#undef USB_DEVICE_CONFIG_CV_TEST + +/*! @brief enable the test mode. */ +#define USB_DEVICE_CONFIG_USB20_TEST_MODE (1U) + +/*! @brief enable the CV test */ +#define USB_DEVICE_CONFIG_CV_TEST (1U) + +#endif + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) + +/*! @brief The MAX buffer length for the KHCI DMA workaround.*/ +#define USB_DEVICE_CONFIG_KHCI_DMA_ALIGN_BUFFER_LENGTH (64U) +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +/*! @brief How many the DTD are supported. */ +#define USB_DEVICE_CONFIG_EHCI_MAX_DTD (16U) + +/*! @brief Whether the EHCI ID pin detect feature enabled. */ +#define USB_DEVICE_CONFIG_EHCI_ID_PIN_DETECT (0U) +#endif + +/*! @brief Whether the keep alive feature enabled. */ +#define USB_DEVICE_CONFIG_KEEP_ALIVE_MODE (0U) + +/*! @brief Whether the transfer buffer is cache-enabled or not. */ +#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (1U) + +/*! @brief Whether the low power mode is enabled or not. */ +#define USB_DEVICE_CONFIG_LOW_POWER_MODE (0U) + +#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +/*! @brief Whether device remote wakeup supported. 1U supported, 0U not supported */ +#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U) + +/*! @brief Whether LPM is supported. 1U supported, 0U not supported */ +#define USB_DEVICE_CONFIG_LPM_L1 (0U) +#else +/*! @brief The device remote wakeup is unsupported. */ +#define USB_DEVICE_CONFIG_REMOTE_WAKEUP (0U) +#endif + +/*! @brief Whether the device detached feature is enabled or not. */ +#define USB_DEVICE_CONFIG_DETACH_ENABLE (0U) + +/*! @brief Whether handle the USB bus error. */ +#define USB_DEVICE_CONFIG_ERROR_HANDLING (0U) + +/* @} */ +/*! @brief rt-thread port alloc */ +#include +#define USB_OSA_SR_ALLOC(...) +/*! @brief rt-thread port enter critical */ +#define USB_OSA_ENTER_CRITICAL rt_enter_critical +/*! @brief rt-thread port exit critical */ +#define USB_OSA_EXIT_CRITICAL rt_exit_critical + +#endif /* _USB_DEVICE_CONFIG_H_ */ diff --git a/bsp/imxrt/libraries/drivers/usb/include/usb_ehci.h b/bsp/imxrt/libraries/drivers/usb/include/usb_ehci.h new file mode 100644 index 0000000000000000000000000000000000000000..edc349664347bb525d3a1dee13102d1b77d1a71f --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/include/usb_ehci.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_EHCI_H__ +#define __USB_EHCI_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Device QH */ +#define USB_DEVICE_EHCI_QH_POINTER_MASK (0xFFFFFFC0U) +#define USB_DEVICE_EHCI_QH_MULT_MASK (0xC0000000U) +#define USB_DEVICE_EHCI_QH_ZLT_MASK (0x20000000U) +#define USB_DEVICE_EHCI_QH_MAX_PACKET_SIZE_MASK (0x07FF0000U) +#define USB_DEVICE_EHCI_QH_MAX_PACKET_SIZE (0x00000800U) +#define USB_DEVICE_EHCI_QH_IOS_MASK (0x00008000U) + +/* Device DTD */ +#define USB_DEVICE_ECHI_DTD_POINTER_MASK (0xFFFFFFE0U) +#define USB_DEVICE_ECHI_DTD_TERMINATE_MASK (0x00000001U) +#define USB_DEVICE_ECHI_DTD_PAGE_MASK (0xFFFFF000U) +#define USB_DEVICE_ECHI_DTD_PAGE_OFFSET_MASK (0x00000FFFU) +#define USB_DEVICE_ECHI_DTD_PAGE_BLOCK (0x00001000U) +#define USB_DEVICE_ECHI_DTD_TOTAL_BYTES_MASK (0x7FFF0000U) +#define USB_DEVICE_ECHI_DTD_TOTAL_BYTES (0x00004000U) +#define USB_DEVICE_ECHI_DTD_IOC_MASK (0x00008000U) +#define USB_DEVICE_ECHI_DTD_MULTIO_MASK (0x00000C00U) +#define USB_DEVICE_ECHI_DTD_STATUS_MASK (0x000000FFU) +#define USB_DEVICE_EHCI_DTD_STATUS_ERROR_MASK (0x00000068U) +#define USB_DEVICE_ECHI_DTD_STATUS_ACTIVE (0x00000080U) +#define USB_DEVICE_ECHI_DTD_STATUS_HALTED (0x00000040U) +#define USB_DEVICE_ECHI_DTD_STATUS_DATA_BUFFER_ERROR (0x00000020U) +#define USB_DEVICE_ECHI_DTD_STATUS_TRANSACTION_ERROR (0x00000008U) + +typedef struct _usb_device_ehci_qh_struct +{ + union + { + volatile uint32_t capabilttiesCharacteristics; + struct + { + volatile uint32_t reserved1 : 15; + volatile uint32_t ios : 1; + volatile uint32_t maxPacketSize : 11; + volatile uint32_t reserved2 : 2; + volatile uint32_t zlt : 1; + volatile uint32_t mult : 2; + } capabilttiesCharacteristicsBitmap; + } capabilttiesCharacteristicsUnion; + volatile uint32_t currentDtdPointer; + volatile uint32_t nextDtdPointer; + union + { + volatile uint32_t dtdToken; + struct + { + volatile uint32_t status : 8; + volatile uint32_t reserved1 : 2; + volatile uint32_t multiplierOverride : 2; + volatile uint32_t reserved2 : 3; + volatile uint32_t ioc : 1; + volatile uint32_t totalBytes : 15; + volatile uint32_t reserved3 : 1; + } dtdTokenBitmap; + } dtdTokenUnion; + volatile uint32_t bufferPointerPage[5]; + volatile uint32_t reserved1; + uint32_t setupBuffer[2]; + uint32_t setupBufferBack[2]; + union + { + uint32_t endpointStatus; + struct + { + uint32_t isOpened : 1; + uint32_t : 31; + } endpointStatusBitmap; + } endpointStatusUnion; + uint32_t reserved2; +} usb_device_ehci_qh_struct_t; + +typedef struct _usb_device_ehci_dtd_struct +{ + volatile uint32_t nextDtdPointer; + union + { + volatile uint32_t dtdToken; + struct + { + volatile uint32_t status : 8; + volatile uint32_t reserved1 : 2; + volatile uint32_t multiplierOverride : 2; + volatile uint32_t reserved2 : 3; + volatile uint32_t ioc : 1; + volatile uint32_t totalBytes : 15; + volatile uint32_t reserved3 : 1; + } dtdTokenBitmap; + } dtdTokenUnion; + volatile uint32_t bufferPointerPage[5]; + union + { + volatile uint32_t reserved; + struct + { + uint32_t originalBufferOffest : 12; + uint32_t originalBufferLength : 19; + uint32_t dtdInvalid : 1; + } originalBufferInfo; + } reservedUnion; +} usb_device_ehci_dtd_struct_t; + +#endif /* __USB_EHCI_H__ */ diff --git a/bsp/imxrt/libraries/drivers/usb/include/usb_misc.h b/bsp/imxrt/libraries/drivers/usb/include/usb_misc.h new file mode 100644 index 0000000000000000000000000000000000000000..4e65cfa94b230ef9af7857a029538df0ffb25ce2 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/include/usb_misc.h @@ -0,0 +1,452 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_MISC_H__ +#define __USB_MISC_H__ + +#ifndef ENDIANNESS + +#error ENDIANNESS should be defined, and then rebulid the project. + +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Define USB printf */ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +extern int DbgConsole_Printf(const char *fmt_s, ...); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#if defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE < 1) +#define usb_echo printf +#else +#define usb_echo DbgConsole_Printf +#endif + +#if defined(__ICCARM__) + +#ifndef STRUCT_PACKED +#define STRUCT_PACKED __packed +#endif + +#ifndef STRUCT_UNPACKED +#define STRUCT_UNPACKED +#endif + +#elif defined(__GNUC__) + +#ifndef STRUCT_PACKED +#define STRUCT_PACKED +#endif + +#ifndef STRUCT_UNPACKED +#define STRUCT_UNPACKED __attribute__((__packed__)) +#endif + +#elif defined(__CC_ARM) + +#ifndef STRUCT_PACKED +#define STRUCT_PACKED _Pragma("pack(1U)") +#endif + +#ifndef STRUCT_UNPACKED +#define STRUCT_UNPACKED _Pragma("pack()") +#endif + +#endif + +#define USB_SHORT_GET_LOW(x) (((uint16_t)x) & 0xFFU) +#define USB_SHORT_GET_HIGH(x) ((uint8_t)(((uint16_t)x) >> 8U) & 0xFFU) + +#define USB_LONG_GET_BYTE0(x) ((uint8_t)(((uint32_t)(x))) & 0xFFU) +#define USB_LONG_GET_BYTE1(x) ((uint8_t)(((uint32_t)(x)) >> 8U) & 0xFFU) +#define USB_LONG_GET_BYTE2(x) ((uint8_t)(((uint32_t)(x)) >> 16U) & 0xFFU) +#define USB_LONG_GET_BYTE3(x) ((uint8_t)(((uint32_t)(x)) >> 24U) & 0xFFU) + +#define USB_MEM4_ALIGN_MASK (0x03U) + +/* accessory macro */ +#define USB_MEM4_ALIGN(n) ((n + 3U) & (0xFFFFFFFCu)) +#define USB_MEM32_ALIGN(n) ((n + 31U) & (0xFFFFFFE0u)) +#define USB_MEM64_ALIGN(n) ((n + 63U) & (0xFFFFFFC0u)) + +/* big/little endian */ +#define SWAP2BYTE_CONST(n) ((((n)&0x00FFU) << 8U) | (((n)&0xFF00U) >> 8U)) +#define SWAP4BYTE_CONST(n) \ + ((((n)&0x000000FFU) << 24U) | (((n)&0x0000FF00U) << 8U) | (((n)&0x00FF0000U) >> 8U) | (((n)&0xFF000000U) >> 24U)) + +#define USB_ASSIGN_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \ + *((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \ + *((uint8_t *)&(n) + 2) = *((uint8_t *)&(m) + 2); \ + *((uint8_t *)&(n) + 3) = *((uint8_t *)&(m) + 3); \ + } + +#define USB_ASSIGN_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = *((uint8_t *)&(m)); \ + *((uint8_t *)&(n) + 1) = *((uint8_t *)&(m) + 1); \ + } + +#define USB_ASSIGN_MACRO_VALUE_ADDRESS_LONG_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = (uint8_t)m; \ + *((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \ + *((uint8_t *)&(n) + 2) = (uint8_t)(m >> 16); \ + *((uint8_t *)&(n) + 3) = (uint8_t)(m >> 24); \ + } + +#define USB_ASSIGN_MACRO_VALUE_ADDRESS_SHORT_BY_BYTE(n, m) \ + { \ + *((uint8_t *)&(n)) = (uint8_t)m; \ + *((uint8_t *)&(n) + 1) = (uint8_t)(m >> 8); \ + } + +#if (ENDIANNESS == USB_BIG_ENDIAN) + +#define USB_SHORT_TO_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_TO_LITTLE_ENDIAN(n) SWAP4BYTE_CONST(n) +#define USB_SHORT_FROM_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_FROM_LITTLE_ENDIAN(n) SWAP2BYTE_CONST(n) + +#define USB_SHORT_TO_BIG_ENDIAN(n) (n) +#define USB_LONG_TO_BIG_ENDIAN(n) (n) +#define USB_SHORT_FROM_BIG_ENDIAN(n) (n) +#define USB_LONG_FROM_BIG_ENDIAN(n) (n) + +#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[3] = ((n >> 24U) & 0xFFU); \ + m[2] = ((n >> 16U) & 0xFFU); \ + m[1] = ((n >> 8U) & 0xFFU); \ + m[0] = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint8_t)n[3]) << 24U) | (((uint8_t)n[2]) << 16U) | (((uint8_t)n[1]) << 8U) | \ + (((uint8_t)n[0]) << 0U))) + +#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((n >> 24U) & 0xFFU); \ + m[1] = ((n >> 16U) & 0xFFU); \ + m[2] = ((n >> 8U) & 0xFFU); \ + m[3] = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint8_t)n[0]) << 24U) | (((uint8_t)n[1]) << 16U) | (((uint8_t)n[2]) << 8U) | \ + (((uint8_t)n[3]) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[1] = ((n >> 8U) & 0xFFU); \ + m[0] = (n & 0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[1]) << 8U) | (((uint8_t)n[0]) << 0U))) + +#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((n >> 8U) & 0xFFU); \ + m[1] = (n & 0xFFU); \ + } + +#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[0]) << 8U) | (((uint8_t)n[1]) << 0U))) + +#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 3) = ((n >> 24U) & 0xFFU); \ + *((uint8_t *)&(m) + 2) = ((n >> 16U) & 0xFFU); \ + *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \ + *((uint8_t *)&(m) + 0) = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \ + ((uint32_t)(((*((uint8_t *)&(n) + 3)) << 24U) | ((*((uint8_t *)&(n) + 2)) << 16U) | \ + ((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n))) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \ + *((uint8_t *)&(m)) = ((n)&0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) ((uint32_t)(((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n)))))) + +#else + +#define USB_SHORT_TO_LITTLE_ENDIAN(n) (n) +#define USB_LONG_TO_LITTLE_ENDIAN(n) (n) +#define USB_SHORT_FROM_LITTLE_ENDIAN(n) (n) +#define USB_LONG_FROM_LITTLE_ENDIAN(n) (n) + +#define USB_SHORT_TO_BIG_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_TO_BIG_ENDIAN(n) SWAP4BYTE_CONST(n) +#define USB_SHORT_FROM_BIG_ENDIAN(n) SWAP2BYTE_CONST(n) +#define USB_LONG_FROM_BIG_ENDIAN(n) SWAP4BYTE_CONST(n) + +#define USB_LONG_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[3] = ((n >> 24U) & 0xFFU); \ + m[2] = ((n >> 16U) & 0xFFU); \ + m[1] = ((n >> 8U) & 0xFFU); \ + m[0] = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint8_t)n[3]) << 24U) | (((uint8_t)n[2]) << 16U) | (((uint8_t)n[1]) << 8U) | \ + (((uint8_t)n[0]) << 0U))) + +#define USB_LONG_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((n >> 24U) & 0xFFU); \ + m[1] = ((n >> 16U) & 0xFFU); \ + m[2] = ((n >> 8U) & 0xFFU); \ + m[3] = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_BIG_ENDIAN_ADDRESS(n) \ + ((uint32_t)((((uint8_t)n[0]) << 24U) | (((uint8_t)n[1]) << 16U) | (((uint8_t)n[2]) << 8U) | \ + (((uint8_t)n[3]) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_ADDRESS(n, m) \ + { \ + m[1] = ((n >> 8U) & 0xFFU); \ + m[0] = (n & 0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[1]) << 8U) | (((uint8_t)n[0]) << 0U))) + +#define USB_SHORT_TO_BIG_ENDIAN_ADDRESS(n, m) \ + { \ + m[0] = ((n >> 8U) & 0xFFU); \ + m[1] = (n & 0xFFU); \ + } + +#define USB_SHORT_FROM_BIG_ENDIAN_ADDRESS(n) ((uint32_t)((((uint8_t)n[0]) << 8U) | (((uint8_t)n[1]) << 0U))) + +#define USB_LONG_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 3) = ((n >> 24U) & 0xFFU); \ + *((uint8_t *)&(m) + 2) = ((n >> 16U) & 0xFFU); \ + *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \ + *((uint8_t *)&(m) + 0) = (n & 0xFFU); \ + } + +#define USB_LONG_FROM_LITTLE_ENDIAN_DATA(n) \ + ((uint32_t)(((*((uint8_t *)&(n) + 3)) << 24U) | ((*((uint8_t *)&(n) + 2)) << 16U) | \ + ((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n))) << 0U))) + +#define USB_SHORT_TO_LITTLE_ENDIAN_DATA(n, m) \ + { \ + *((uint8_t *)&(m) + 1) = ((n >> 8U) & 0xFFU); \ + *((uint8_t *)&(m)) = ((n)&0xFFU); \ + } + +#define USB_SHORT_FROM_LITTLE_ENDIAN_DATA(n) ((uint32_t)(((*((uint8_t *)&(n) + 1)) << 8U) | ((*((uint8_t *)&(n)))))) + +#endif + +/* + * The following MACROs (USB_GLOBAL, USB_BDT, USB_RAM_ADDRESS_ALIGNMENT, etc) are only used for USB device stack. + * The USB device global variables are put into the section m_usb_global and m_usb_bdt or the section + * .bss.m_usb_global and .bss.m_usb_bdt by using the MACRO USB_GLOBAL and USB_BDT. In this way, the USB device + * global variables can be linked into USB dedicated RAM by USB_STACK_USE_DEDICATED_RAM. + * The MACRO USB_STACK_USE_DEDICATED_RAM is used to decide the USB stack uses dedicated RAM or not. The value of + * the marco can be set as 0, USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL, or USB_STACK_DEDICATED_RAM_TYPE_BDT. + * The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL means USB device global variables, including USB_BDT and + * USB_GLOBAL, are put into the USB dedicated RAM. This feature can only be enabled when the USB dedicated RAM + * is not less than 2K Bytes. + * The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT means USB device global variables, only including USB_BDT, are put + * into the USB dedicated RAM, the USB_GLOBAL will be put into .bss section. This feature is used for some SOCs, + * the USB dedicated RAM size is not more than 512 Bytes. + */ +#define USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL 1 +#define USB_STACK_DEDICATED_RAM_TYPE_BDT 2 + +#if defined(__ICCARM__) + +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __attribute__((weak)) +/* disable misra 19.13 */ +_Pragma("diag_suppress=Pm120") +#define USB_ALIGN_PRAGMA(x) _Pragma(#x) + _Pragma("diag_default=Pm120") + +#define USB_RAM_ADDRESS_ALIGNMENT(n) USB_ALIGN_PRAGMA(data_alignment = n) + _Pragma("diag_suppress=Pm120") +#define USB_LINK_SECTION_PART(str) _Pragma(#str) +#define USB_LINK_SECTION_SUB(sec) USB_LINK_SECTION_PART(location = #sec) +#define USB_LINK_USB_GLOBAL _Pragma("location = \"m_usb_global\"") +#define USB_LINK_USB_BDT _Pragma("location = \"m_usb_bdt\"") +#define USB_LINK_USB_GLOBAL_BSS _Pragma("location = \".bss.m_usb_global\"") +#define USB_LINK_USB_BDT_BSS _Pragma("location = \".bss.m_usb_bdt\"") + _Pragma("diag_default=Pm120") +#define USB_LINK_DMA_NONINIT_DATA _Pragma("location = \"m_usb_dma_noninit_data\"") +#define USB_LINK_NONCACHE_NONINIT_DATA _Pragma("location = \"NonCacheable\"") +#elif defined(__CC_ARM) + +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __weak +#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n))) +#define USB_LINK_SECTION_SUB(sec) __attribute__((section(#sec))) +#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global"))) __attribute__((zero_init)) +#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt"))) __attribute__((zero_init)) +#define USB_LINK_USB_GLOBAL_BSS __attribute__((section(".bss.m_usb_global"))) __attribute__((zero_init)) +#define USB_LINK_USB_BDT_BSS __attribute__((section(".bss.m_usb_bdt"))) __attribute__((zero_init)) +#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data"))) __attribute__((zero_init)) +#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable"))) __attribute__((zero_init)) + +#elif defined(__GNUC__) + +#define USB_WEAK_VAR __attribute__((weak)) +#define USB_WEAK_FUN __attribute__((weak)) +#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n))) +#define USB_LINK_SECTION_SUB(sec) __attribute__((section(#sec))) +#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global, \"aw\", %nobits @"))) +#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt, \"aw\", %nobits @"))) +#define USB_LINK_USB_GLOBAL_BSS __attribute__((section(".bss.m_usb_global, \"aw\", %nobits @"))) +#define USB_LINK_USB_BDT_BSS __attribute__((section(".bss.m_usb_bdt, \"aw\", %nobits @"))) +#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data, \"aw\", %nobits @"))) +#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable, \"aw\", %nobits @"))) + +#else +#error The tool-chain is not supported. +#endif + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + +#if ((defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)) && (defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#elif(defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)) +#define USB_CACHE_LINESIZE MAX(FSL_FEATURE_L2CACHE_LINESIZE_BYTE, 0) +#elif(defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)) +#define USB_CACHE_LINESIZE MAX(0, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#else +#define USB_CACHE_LINESIZE 4 +#endif + +#else +#define USB_CACHE_LINESIZE 4 +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +#define USB_DATA_ALIGN 64 +#else +#define USB_DATA_ALIGN 4 +#endif + +#define USB_DATA_ALIGN_SIZE MAX(USB_CACHE_LINESIZE, USB_DATA_ALIGN) + +#define USB_DATA_ALIGN_SIZE_MULTIPLE(n) ((n + USB_DATA_ALIGN_SIZE - 1) & (~(USB_DATA_ALIGN_SIZE - 1))) + +#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL) + +#define USB_GLOBAL USB_LINK_USB_GLOBAL +#define USB_BDT USB_LINK_USB_BDT + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_SECTION_SUB(m_usb_dma_init_data) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA +#else +#define USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_DATA_INIT_SUB +#define USB_CONTROLLER_DATA USB_LINK_USB_GLOBAL +#endif + +#elif defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM == USB_STACK_DEDICATED_RAM_TYPE_BDT) + +#define USB_BDT USB_LINK_USB_BDT + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_SECTION_SUB(m_usb_dma_init_data) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA +#else +#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS +#define USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_DATA_INIT_SUB +#define USB_CONTROLLER_DATA +#endif + +#else + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) + +#define USB_GLOBAL USB_LINK_DMA_NONINIT_DATA +#define USB_BDT USB_LINK_NONCACHE_NONINIT_DATA +#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA +#define USB_DMA_DATA_INIT_SUB USB_LINK_SECTION_SUB(m_usb_dma_init_data) +#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA + +#else +#define USB_GLOBAL USB_LINK_USB_GLOBAL_BSS +#define USB_BDT USB_LINK_USB_BDT_BSS +#define USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_DATA_INIT_SUB +#define USB_CONTROLLER_DATA +#endif + +#endif + +#define USB_DMA_NONINIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_NONINIT_SUB +#define USB_DMA_INIT_DATA_ALIGN(n) USB_RAM_ADDRESS_ALIGNMENT(n) USB_DMA_DATA_INIT_SUB + +#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \ + (defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE)) +#define USB_DMA_DATA_NONCACHEABLE USB_LINK_NONCACHE_NONINIT_DATA + +#else +#define USB_DMA_DATA_NONCACHEABLE +#endif + +#define USB_GLOBAL_DEDICATED_RAM USB_LINK_USB_GLOBAL + +/* #define USB_RAM_ADDRESS_NONCACHEREG_ALIGNMENT(n, var) AT_NONCACHEABLE_SECTION_ALIGN(var, n) */ +/* #define USB_RAM_ADDRESS_NONCACHEREG(var) AT_NONCACHEABLE_SECTION(var) */ + +#endif /* __USB_MISC_H__ */ diff --git a/bsp/imxrt/libraries/drivers/usb/include/usb_spec.h b/bsp/imxrt/libraries/drivers/usb/include/usb_spec.h new file mode 100644 index 0000000000000000000000000000000000000000..d77b7d3598693a8b6302e101ec2deb689bef3f88 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/include/usb_spec.h @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __USB_SPEC_H__ +#define __USB_SPEC_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* USB speed (the value cannot be changed because EHCI QH use the value directly)*/ +#define USB_SPEED_FULL (0x00U) +#define USB_SPEED_LOW (0x01U) +#define USB_SPEED_HIGH (0x02U) + +/* Set up packet structure */ +typedef struct _usb_setup_struct +{ + uint8_t bmRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} usb_setup_struct_t; + +/* USB standard descriptor endpoint type */ +#define USB_ENDPOINT_CONTROL (0x00U) +#define USB_ENDPOINT_ISOCHRONOUS (0x01U) +#define USB_ENDPOINT_BULK (0x02U) +#define USB_ENDPOINT_INTERRUPT (0x03U) + +/* USB standard descriptor transfer direction (cannot change the value because iTD use the value directly) */ +#define USB_OUT (0U) +#define USB_IN (1U) + +/* USB standard descriptor length */ +#define USB_DESCRIPTOR_LENGTH_DEVICE (0x12U) +#define USB_DESCRIPTOR_LENGTH_CONFIGURE (0x09U) +#define USB_DESCRIPTOR_LENGTH_INTERFACE (0x09U) +#define USB_DESCRIPTOR_LENGTH_ENDPOINT (0x07U) +#define USB_DESCRIPTOR_LENGTH_DEVICE_QUALITIER (0x0AU) +#define USB_DESCRIPTOR_LENGTH_OTG_DESCRIPTOR (5U) +#define USB_DESCRIPTOR_LENGTH_BOS_DESCRIPTOR (5U) + +/* USB Device Capability Type Codes */ +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_WIRELESS (0x01U) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_USB20_EXTENSION (0x02U) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_SUPERSPEED (0x03U) + +/* USB standard descriptor type */ +#define USB_DESCRIPTOR_TYPE_DEVICE (0x01U) +#define USB_DESCRIPTOR_TYPE_CONFIGURE (0x02U) +#define USB_DESCRIPTOR_TYPE_STRING (0x03U) +#define USB_DESCRIPTOR_TYPE_INTERFACE (0x04U) +#define USB_DESCRIPTOR_TYPE_ENDPOINT (0x05U) +#define USB_DESCRIPTOR_TYPE_DEVICE_QUALITIER (0x06U) +#define USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION (0x07U) +#define USB_DESCRIPTOR_TYPE_INTERFAACE_POWER (0x08U) +#define USB_DESCRIPTOR_TYPE_OTG (0x09U) +#define USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION (0x0BU) +#define USB_DESCRIPTOR_TYPE_BOS (0x0F) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY (0x10) + +#define USB_DESCRIPTOR_TYPE_HID (0x21U) +#define USB_DESCRIPTOR_TYPE_HID_REPORT (0x22U) +#define USB_DESCRIPTOR_TYPE_HID_PHYSICAL (0x23U) + +/* USB standard request type */ +#define USB_REQUEST_TYPE_DIR_MASK (0x80U) +#define USB_REQUEST_TYPE_DIR_SHIFT (7U) +#define USB_REQUEST_TYPE_DIR_OUT (0x00U) +#define USB_REQUEST_TYPE_DIR_IN (0x80U) + +#define USB_REQUEST_TYPE_TYPE_MASK (0x60U) +#define USB_REQUEST_TYPE_TYPE_SHIFT (5U) +#define USB_REQUEST_TYPE_TYPE_STANDARD (0U) +#define USB_REQUEST_TYPE_TYPE_CLASS (0x20U) +#define USB_REQUEST_TYPE_TYPE_VENDOR (0x40U) + +#define USB_REQUEST_TYPE_RECIPIENT_MASK (0x1FU) +#define USB_REQUEST_TYPE_RECIPIENT_SHIFT (0U) +#define USB_REQUEST_TYPE_RECIPIENT_DEVICE (0x00U) +#define USB_REQUEST_TYPE_RECIPIENT_INTERFACE (0x01U) +#define USB_REQUEST_TYPE_RECIPIENT_ENDPOINT (0x02U) +#define USB_REQUEST_TYPE_RECIPIENT_OTHER (0x03U) + +/* USB standard request */ +#define USB_REQUEST_STANDARD_GET_STATUS (0x00U) +#define USB_REQUEST_STANDARD_CLEAR_FEATURE (0x01U) +#define USB_REQUEST_STANDARD_SET_FEATURE (0x03U) +#define USB_REQUEST_STANDARD_SET_ADDRESS (0x05U) +#define USB_REQUEST_STANDARD_GET_DESCRIPTOR (0x06U) +#define USB_REQUEST_STANDARD_SET_DESCRIPTOR (0x07U) +#define USB_REQUEST_STANDARD_GET_CONFIGURATION (0x08U) +#define USB_REQUEST_STANDARD_SET_CONFIGURATION (0x09U) +#define USB_REQUEST_STANDARD_GET_INTERFACE (0x0AU) +#define USB_REQUEST_STANDARD_SET_INTERFACE (0x0BU) +#define USB_REQUEST_STANDARD_SYNCH_FRAME (0x0CU) + +/* USB standard request GET Status */ +#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT (0U) +#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT (1U) + +#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_MASK (0x01U) +#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_SHIFT (0U) + +#define USB_REQUEST_STANDARD_GET_STATUS_OTG_STATUS_SELECTOR (0xF000U) + +/* USB standard request CLEAR/SET feature */ +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT (0U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_REMOTE_WAKEUP (1U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_TEST_MODE (2U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_B_HNP_ENABLE (3U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_HNP_SUPPORT (4U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_ALT_HNP_SUPPORT (5U) + +/* USB standard descriptor configure bmAttributes */ +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_MASK (0x80U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_SHIFT (7U) + +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_MASK (0x40U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_SHIFT (6U) + +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_MASK (0x20U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_SHIFT (5U) + +/* USB standard descriptor endpoint bmAttributes */ +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK (0x80U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT (7U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_OUT (0U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN (0x80U) + +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_MASK (0x0FU) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_SHFIT (0U) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_TYPE_MASK (0x03U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_NUMBER_SHFIT (0U) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_MASK (0x0CU) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SHFIT (2U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_NO_SYNC (0x00U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ASYNC (0x04U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ADAPTIVE (0x08U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SYNC (0x0CU) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_MASK (0x30U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_SHFIT (4U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_DATA_ENDPOINT (0x00U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_FEEDBACK_ENDPOINT (0x10U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_IMPLICIT_FEEDBACK_DATA_ENDPOINT (0x20U) + +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK (0x07FFu) +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK (0x1800u) +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_SHFIT (11U) + +/* USB standard descriptor otg bmAttributes */ +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_SRP_MASK (0x01u) +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_HNP_MASK (0x02u) +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_ADP_MASK (0x04u) + +/* USB standard descriptor device capability usb20 extension bmAttributes */ +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_MASK (0x02U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_SHIFT (1U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_MASK (0x04U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_SHIFT (2U) + + +/* Language structure */ +typedef struct _usb_language +{ + uint8_t **string; /* The Strings descriptor array */ + uint32_t *length; /* The strings descriptor length array */ + uint16_t languageId; /* The language id of current language */ +} usb_language_t; + +typedef struct _usb_language_list +{ + uint8_t *languageString; /* The String 0U pointer */ + uint32_t stringLength; /* The String 0U Length */ + usb_language_t *languageList; /* The language list */ + uint8_t count; /* The language count */ +} usb_language_list_t; + +typedef struct _usb_descriptor_common +{ + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* DEVICE Descriptor Type */ + uint8_t bData[1]; /* Data */ +} usb_descriptor_common_t; + +typedef struct _usb_descriptor_device +{ + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* DEVICE Descriptor Type */ + uint8_t bcdUSB[2]; /* UUSB Specification Release Number in Binary-Coded Decimal, e.g. 0x0200U */ + uint8_t bDeviceClass; /* Class code */ + uint8_t bDeviceSubClass; /* Sub-Class code */ + uint8_t bDeviceProtocol; /* Protocol code */ + uint8_t bMaxPacketSize0; /* Maximum packet size for endpoint zero */ + uint8_t idVendor[2]; /* Vendor ID (assigned by the USB-IF) */ + uint8_t idProduct[2]; /* Product ID (assigned by the manufacturer) */ + uint8_t bcdDevice[2]; /* Device release number in binary-coded decimal */ + uint8_t iManufacturer; /* Index of string descriptor describing manufacturer */ + uint8_t iProduct; /* Index of string descriptor describing product */ + uint8_t iSerialNumber; /* Index of string descriptor describing the device serial number */ + uint8_t bNumConfigurations; /* Number of possible configurations */ +} usb_descriptor_device_t; + +typedef struct _usb_descriptor_configuration +{ + uint8_t bLength; /* Descriptor size in bytes = 9U */ + uint8_t bDescriptorType; /* CONFIGURATION type = 2U or 7U */ + uint8_t wTotalLength[2]; /* Length of concatenated descriptors */ + uint8_t bNumInterfaces; /* Number of interfaces, this configuration. */ + uint8_t bConfigurationValue; /* Value to set this configuration. */ + uint8_t iConfiguration; /* Index to configuration string */ + uint8_t bmAttributes; /* Configuration characteristics */ + uint8_t bMaxPower; /* Maximum power from bus, 2 mA units */ +} usb_descriptor_configuration_t; + +typedef struct _usb_descriptor_interface +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} usb_descriptor_interface_t; + +typedef struct _usb_descriptor_endpoint +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSize[2]; + uint8_t bInterval; +} usb_descriptor_endpoint_t; + +typedef struct _usb_descriptor_binary_device_object_store +{ + uint8_t bLength; /* Descriptor size in bytes = 5U */ + uint8_t bDescriptorType; /* BOS Descriptor type = 0FU*/ + uint8_t wTotalLength[2]; /*Length of this descriptor and all of its sub descriptors*/ + uint8_t bNumDeviceCaps; /*The number of separate device capability descriptors in the BOS*/ +} usb_descriptor_bos_t; + +typedef struct _usb_descriptor_usb20_extension +{ + uint8_t bLength; /* Descriptor size in bytes = 7U */ + uint8_t bDescriptorType; /* DEVICE CAPABILITY Descriptor type = 0x10U*/ + uint8_t bDevCapabilityType; /*Length of this descriptor and all of its sub descriptors*/ + uint8_t bmAttributes[4]; /*Bitmap encoding of supported device level features.*/ +} usb_descriptor_usb20_extension_t; + +typedef union _usb_descriptor_union +{ + usb_descriptor_common_t common; /* Common descriptor */ + usb_descriptor_device_t device; /* Device descriptor */ + usb_descriptor_configuration_t configuration; /* Configuration descriptor */ + usb_descriptor_interface_t interface; /* Interface descriptor */ + usb_descriptor_endpoint_t endpoint; /* Endpoint descriptor */ +} usb_descriptor_union_t; + +#endif /* __USB_SPEC_H__ */ diff --git a/bsp/imxrt/libraries/drivers/usb/phy/usb_phy.c b/bsp/imxrt/libraries/drivers/usb/phy/usb_phy.c new file mode 100644 index 0000000000000000000000000000000000000000..70537b97dc61235b531d42e547e01a929f3629d0 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/phy/usb_phy.c @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "fsl_device_registers.h" + +#include + +void *USB_EhciPhyGetBase(uint8_t controllerId) +{ + void *usbPhyBase = NULL; +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + uint32_t instance; + uint32_t newinstance = 0; + uint32_t usbphy_base_temp[] = USBPHY_BASE_ADDRS; + uint32_t usbphy_base[] = USBPHY_BASE_ADDRS; + + if (controllerId < kUSB_ControllerEhci0) + { + return NULL; + } + + controllerId = controllerId - kUSB_ControllerEhci0; + + for (instance = 0; instance < (sizeof(usbphy_base_temp) / sizeof(usbphy_base_temp[0])); instance++) + { + if (usbphy_base_temp[instance]) + { + usbphy_base[newinstance++] = usbphy_base_temp[instance]; + } + } + if (controllerId > newinstance) + { + return NULL; + } + + usbPhyBase = (void *)usbphy_base[controllerId]; +#endif + return usbPhyBase; +} + +/*! + * @brief ehci phy initialization. + * + * This function initialize ehci phy IP. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval kStatus_USB_Success cancel successfully. + * @retval kStatus_USB_Error the freq value is incorrect. + */ +uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return kStatus_USB_Error; + } + +#if ((defined FSL_FEATURE_SOC_ANATOP_COUNT) && (FSL_FEATURE_SOC_ANATOP_COUNT > 0U)) + ANATOP->HW_ANADIG_REG_3P0.RW = + (ANATOP->HW_ANADIG_REG_3P0.RW & + (~(ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x1F) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_ILIMIT_MASK))) | + ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x17) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_LINREG_MASK; + ANATOP->HW_ANADIG_USB2_CHRG_DETECT.SET = + ANATOP_HW_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B_MASK | ANATOP_HW_ANADIG_USB2_CHRG_DETECT_EN_B_MASK; +#endif + +#if (defined USB_ANALOG) + USB_ANALOG->INSTANCE[controllerId - kUSB_ControllerEhci0].CHRG_DETECT_SET = USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(1) | USB_ANALOG_CHRG_DETECT_EN_B(1); +#endif + +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + + usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */ + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */ + /* PWD register provides overall control of the PHY power state */ + usbPhyBase->PWD = 0U; + + /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */ + usbPhyBase->TX = + ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | + (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) | + USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM))); +#endif + + return kStatus_USB_Success; +} + +/*! + * @brief ehci phy initialization for suspend and resume. + * + * This function initialize ehci phy IP for suspend and resume. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval kStatus_USB_Success cancel successfully. + * @retval kStatus_USB_Error the freq value is incorrect. + */ +uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return kStatus_USB_Error; + } + +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ +#endif + +#if ((defined USBPHY_CTRL_AUTORESUME_EN_MASK) && (USBPHY_CTRL_AUTORESUME_EN_MASK > 0U)) + usbPhyBase->CTRL |= USBPHY_CTRL_AUTORESUME_EN_MASK; +#else + usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK; +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK; + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */ + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */ + /* PWD register provides overall control of the PHY power state */ + usbPhyBase->PWD = 0U; +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + /* now the 480MHz USB clock is up, then configure fractional divider after PLL with PFD + * pfd clock = 480MHz*18/N, where N=18~35 + * Please note that USB1PFDCLK has to be less than 180MHz for RUN or HSRUN mode + */ + usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_FRAC(24); /* N=24 */ + usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_CLK_SEL(1); /* div by 4 */ + + usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_DEV_PULLDOWN_MASK; + usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK; + while (!(usbPhyBase->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK)) + { + } +#endif + /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */ + usbPhyBase->TX = + ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | + (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) | + USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM))); +#endif + + return kStatus_USB_Success; +} + +/*! + * @brief ehci phy de-initialization. + * + * This function de-initialize ehci phy IP. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + */ +void USB_EhciPhyDeinit(uint8_t controllerId) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return; + } +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* power down PLL */ + usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* disable USB clock output from USB PHY PLL */ +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* set to 1U to gate clocks */ +#endif +} + +/*! + * @brief ehci phy disconnect detection enable or disable. + * + * This function enable/disable host ehci disconnect detection. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] enable + * 1U - enable; + * 0U - disable; + */ +void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return; + } + + if (enable) + { + usbPhyBase->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; + } + else + { + usbPhyBase->CTRL &= (~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK); + } +#endif +} diff --git a/bsp/imxrt/libraries/drivers/usb/phy/usb_phy.h b/bsp/imxrt/libraries/drivers/usb/phy/usb_phy.h new file mode 100644 index 0000000000000000000000000000000000000000..0409f9c8b90afe8d3585b8c8988055c8545a7912 --- /dev/null +++ b/bsp/imxrt/libraries/drivers/usb/phy/usb_phy.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __USB_PHY_H__ +#define __USB_PHY_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +typedef struct _usb_phy_config_struct +{ + uint8_t D_CAL; /* Decode to trim the nominal 17.78mA current source */ + uint8_t TXCAL45DP; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DP output pin */ + uint8_t TXCAL45DM; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DM output pin */ +} usb_phy_config_struct_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @brief EHCI PHY get USB phy bass address. + * + * This function is used to get USB phy bass address. + * + * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. + * + * @retval USB phy bass address. + */ +extern void *USB_EhciPhyGetBase(uint8_t controllerId); + +/*! + * @brief EHCI PHY initialization. + * + * This function initializes the EHCI PHY IP. + * + * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. + * @param[in] freq The external input clock. + * + * @retval kStatus_USB_Success Cancel successfully. + * @retval kStatus_USB_Error The freq value is incorrect. + */ +extern uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig); + +/*! + * @brief ehci phy initialization for suspend and resume. + * + * This function initialize ehci phy IP for suspend and resume. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval kStatus_USB_Success cancel successfully. + * @retval kStatus_USB_Error the freq value is incorrect. + */ +extern uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig); + +/*! + * @brief EHCI PHY deinitialization. + * + * This function deinitializes the EHCI PHY IP. + * + * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t. + */ +extern void USB_EhciPhyDeinit(uint8_t controllerId); + +/*! + * @brief EHCI PHY disconnect detection enable or disable. + * + * This function enable/disable the host EHCI disconnect detection. + * + * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t. + * @param[in] enable + * 1U - enable; + * 0U - disable; + */ +extern void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable); + +#if defined(__cplusplus) +} +#endif + +#endif /* __USB_PHY_H__ */ diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/project.crun b/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/project.crun deleted file mode 100644 index d71ea555a998cf12241abfbf74dff814f68580e5..0000000000000000000000000000000000000000 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/project.crun +++ /dev/null @@ -1,13 +0,0 @@ - - - 1 - - - * - * - * - 0 - 1 - - - diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/project.dbgdt b/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/project.dbgdt deleted file mode 100644 index 9e08d965925f016fd281403163e79f4fc4663a5a..0000000000000000000000000000000000000000 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/project.dbgdt +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/project.dnx b/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/project.dnx deleted file mode 100644 index e02a226dceffa83443081d9abbc7224a9531bcbe..0000000000000000000000000000000000000000 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/project.dnx +++ /dev/null @@ -1,83 +0,0 @@ - - - - 0 - 1 - 90 - 1 - 1 - 1 - main - 0 - 50 - - - 0 - 1 - - - 0 - 0 - 1 - 0 - 1 - 0 - - - 0 - 0 - 1 - 0 - 1 - - - 1 - - - 1 - 0 - 1 - 0 - 1 - - - 10000000 - 0 - 1 - - - _ 0 - _ 0 - - - 2336342137 - - - D:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\CONFIG\debugger\NXP\MIMXRT1064xxx6A.ddf - - - CMSIS-DAP:0232000005d92a5e00000000000000000000000097969905 - - 0 - 0 - 0 - - - 1 - - - _ 0 - _ "" - _ 0 - - - 0 - - - 0 - - - 0 - 0 - - diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/project.rtthread.cspy.bat b/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/project.rtthread.cspy.bat deleted file mode 100644 index 47542db642fa6203f17e173219c60d10335348f0..0000000000000000000000000000000000000000 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/project.rtthread.cspy.bat +++ /dev/null @@ -1,40 +0,0 @@ -@REM This batch file has been generated by the IAR Embedded Workbench -@REM C-SPY Debugger, as an aid to preparing a command line for running -@REM the cspybat command line utility using the appropriate settings. -@REM -@REM Note that this file is generated every time a new debug session -@REM is initialized, so you may want to move or rename the file before -@REM making changes. -@REM -@REM You can launch cspybat by typing the name of this batch file followed -@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). -@REM -@REM Read about available command line parameters in the C-SPY Debugging -@REM Guide. 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- - - - diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/project_rtthread.jlink b/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/project_rtthread.jlink deleted file mode 100644 index 39b6d054aa31ff6cb3097d398593ba0320c250f6..0000000000000000000000000000000000000000 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/project_rtthread.jlink +++ /dev/null @@ -1,39 +0,0 @@ -[BREAKPOINTS] -ForceImpTypeAny = 0 -ShowInfoWin = 1 -EnableFlashBP = 2 -BPDuringExecution = 0 -[CFI] -CFISize = 0x00 -CFIAddr = 0x00 -[CPU] -MonModeVTableAddr = 0xFFFFFFFF -MonModeDebug = 0 -MaxNumAPs = 0 -LowPowerHandlingMode = 0 -OverrideMemMap = 0 -AllowSimulation = 1 -ScriptFile="" -[FLASH] -CacheExcludeSize = 0x00 -CacheExcludeAddr = 0x00 -MinNumBytesFlashDL = 0 -SkipProgOnCRCMatch = 1 -VerifyDownload = 1 -AllowCaching = 1 -EnableFlashDL = 2 -Override = 0 -Device="ARM7" -[GENERAL] -WorkRAMSize = 0x00 -WorkRAMAddr = 0x00 -RAMUsageLimit = 0x00 -[SWO] -SWOLogFile="" -[MEM] -RdOverrideOrMask = 0x00 -RdOverrideAndMask = 0xFFFFFFFF -RdOverrideAddr = 0xFFFFFFFF -WrOverrideOrMask = 0x00 -WrOverrideAndMask = 0xFFFFFFFF -WrOverrideAddr = 0xFFFFFFFF diff --git a/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/template.wsdt b/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/template.wsdt deleted file mode 100644 index 17763ac6820bd558d7ac4445d317ebd6d2e49fa3..0000000000000000000000000000000000000000 --- a/bsp/imxrt/libraries/templates/imxrt1064xxx/settings/template.wsdt +++ /dev/null @@ -1,302 +0,0 @@ - - - - - - - - 34048 - 34049 - 34050 - 34051 - 34052 - 34053 - 34054 - 34055 - 34056 - 34057 - 34058 - 34059 - - - - - 34000 - 34001 - 0 - - - - - 57600 - 57601 - 57603 - 33024 - 0 - 57607 - 0 - 57635 - 57634 - 57637 - 0 - 57643 - 57644 - 0 - 33090 - 33057 - 57636 - 57640 - 57641 - 33026 - 33065 - 33063 - 33064 - 33053 - 33054 - 0 - 33035 - 33036 - 34399 - 0 - 33038 - 33039 - 0 - - - - - 214 - 27 - 27 - 27 - - - - - 14 - 12 - - - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 000000000000 - - - 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- - - 34049 - 0A0000000A0000006E0000006E000000 - 000000001C0000000003000039000000 - 8192 - 1 - 0 - 32767 - 0 - - - 1 - - - - - 01000000030000000100000000000000000000000100000001000000FFFFFFFF00000000010000000100000000000000280000002800000000000000 - - - - diff --git a/bsp/lpc176x/drivers/sd.c b/bsp/lpc176x/drivers/sd.c index 27f3707da905e0e204ec144a49b86c5c09391d90..61e34ba43a6b2ae2021bf644f268e48b31538c61 100644 --- a/bsp/lpc176x/drivers/sd.c +++ b/bsp/lpc176x/drivers/sd.c @@ -32,7 +32,7 @@ static uint8_t LPC17xx_SD_SendCmd(uint8_t cmd, uint32_t arg); static bool LPC17xx_SD_ReadSector(uint32_t sector, uint8_t *buff, uint32_t count); static bool LPC17xx_SD_ReadDataBlock(uint8_t *buff, uint32_t cnt); static bool LPC17xx_SD_WriteSector(uint32_t sector, const uint8_t *buff, uint32_t count); -static bool LPC17xx_SD_WirteDataBlock(const uint8_t *buff, uint8_t token); +static bool LPC17xx_SD_WriteDataBlock(const uint8_t *buff, uint8_t token); static bool LPC17xx_SD_ReadCfg(SDCFG *cfg); static bool LPC17xx_SD_WaitForReady(void); @@ -155,7 +155,7 @@ static bool LPC17xx_SD_Init(void) Send a Command to Flash card and get a Response cmd: cmd index arg: argument for the cmd - return the received response of the commond + return the received response of the command *****************************************************************************/ static uint8_t LPC17xx_SD_SendCmd(uint8_t cmd, uint32_t arg) { @@ -279,7 +279,7 @@ static bool LPC17xx_SD_WriteSector(uint32_t sector, const uint8_t *buff, uint32_ if (count == 1) /* Single block write */ { if ((LPC17xx_SD_SendCmd(WRITE_BLOCK, sector) == 0) - && LPC17xx_SD_WirteDataBlock(buff, TOKEN_SINGLE_BLOCK)) + && LPC17xx_SD_WriteDataBlock(buff, TOKEN_SINGLE_BLOCK)) count = 0; } else /* Multiple block write */ @@ -289,12 +289,12 @@ static bool LPC17xx_SD_WriteSector(uint32_t sector, const uint8_t *buff, uint32_ { do { - if (!LPC17xx_SD_WirteDataBlock(buff, TOKEN_MULTI_BLOCK)) break; + if (!LPC17xx_SD_WriteDataBlock(buff, TOKEN_MULTI_BLOCK)) break; buff += 512; } while (--count); #if 1 - if (!LPC17xx_SD_WirteDataBlock(0, TOKEN_STOP_TRAN)) /* STOP_TRAN token */ + if (!LPC17xx_SD_WriteDataBlock(0, TOKEN_STOP_TRAN)) /* STOP_TRAN token */ count = 1; #else LPC17xx_SPI_SendByte(TOKEN_STOP_TRAN); @@ -312,7 +312,7 @@ static bool LPC17xx_SD_WriteSector(uint32_t sector, const uint8_t *buff, uint32_ 0xFC -> multi block 0xFD -> Stop *****************************************************************************/ -static bool LPC17xx_SD_WirteDataBlock(const uint8_t *buff, uint8_t token) +static bool LPC17xx_SD_WriteDataBlock(const uint8_t *buff, uint8_t token) { uint8_t resp, i; diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/.config b/bsp/lpc55sxx/lpc55s69_nxp_evk/.config index fe6c720132f37a88bd346157470fbc5aead60b6d..5a5d4619b83c791330744ab8454a7ddbc93a8ffe 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/.config +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/.config @@ -133,7 +133,9 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 CONFIG_RT_USING_HWTIMER=y # CONFIG_RT_USING_CPUTIME is not set CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_ADC=y CONFIG_RT_USING_PWM=y @@ -229,10 +231,12 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -254,7 +258,9 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set # @@ -264,9 +270,23 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTKIT is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set # # security packages @@ -288,6 +308,8 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set # # tools packages @@ -300,6 +322,12 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set # # system packages @@ -317,6 +345,8 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set # CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set # # peripheral libraries and drivers @@ -324,21 +354,31 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_SHT3X is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set # CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_MPU6XXX is not set # CONFIG_PKG_USING_PCF8574 is not set # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set # # miscellaneous packages @@ -349,11 +389,15 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -365,6 +409,12 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set CONFIG_SOC_LPC55S6X_SERIES=y # diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/Kconfig b/bsp/lpc55sxx/lpc55s69_nxp_evk/Kconfig index 39775bd315542b945b182264027ffb49ba3e3220..b6098321391fbe883a944adf5141e7078a77b015 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/Kconfig +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/Kconfig @@ -22,5 +22,5 @@ config SOC_LPC55S6x source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" -source "../libraries/Kconfig" +source "../Libraries/Kconfig" source "board/Kconfig" diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/applications/main.c b/bsp/lpc55sxx/lpc55s69_nxp_evk/applications/main.c index e03a8c6336dcd4075611449ac5e6b23f01183eb7..e0a2e3171fc1637df7bbb04e7fface4647361e4f 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/applications/main.c +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/applications/main.c @@ -1,11 +1,13 @@ /* * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2019-10-24 Magicoe first version + * 2020-01-10 Kevin/Karl Add PS demo * */ @@ -16,8 +18,12 @@ /* GPIO1_4 is Blue LED */ #define LEDB_PIN GET_PINS(1, 4) +extern void protected_storage_demo_thread(void * parameters); + int main(void) { + rt_thread_t t_psa_ps_demo; + #if defined(__CC_ARM) rt_kprintf("using armcc, version: %d\n", __ARMCC_VERSION); #elif defined(__CLANG_ARM) @@ -27,7 +33,15 @@ int main(void) #elif defined(__GNUC__) rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__); #endif - + + t_psa_ps_demo = rt_thread_create("psa_ps_demo", + protected_storage_demo_thread, + RT_NULL, + 512, + ( RT_MAIN_THREAD_PRIORITY - 1), + 50); + if (t_psa_ps_demo != RT_NULL) rt_thread_startup(t_psa_ps_demo); + rt_pin_mode(LEDB_PIN, PIN_MODE_OUTPUT); /* Set GPIO as Output */ while (1) { diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/applications/tfm_ps.c b/bsp/lpc55sxx/lpc55s69_nxp_evk/applications/tfm_ps.c new file mode 100644 index 0000000000000000000000000000000000000000..2c99e474026a72af6dde51a40744ac95b40b3f85 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/applications/tfm_ps.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-10 Kevin/Karl Add PS demo + * + */ + +#include +#include +#include "tfm_ns_lock.h" +#include "psa_protected_storage.h" + +#define TEST_UID_A 2U +#define ASSET_A "THEQUICKBROWNFOXJUMPSOVERALAZYDOG" +#define ASSET_A_SIZE (sizeof( ASSET_A ) - 1) +#define RESETDATA "THISIS" +#define RESETDATA_SIZE (sizeof( RESETDATA ) - 1) +#define READ_LENGTH (ASSET_A_SIZE > RESETDATA_SIZE ? \ + ASSET_A_SIZE : RESETDATA_SIZE) + +void protected_storage_demo_thread(void * parameters) +{ + psa_ps_status_t status; + const psa_ps_uid_t uid = TEST_UID_A; + const psa_ps_create_flags_t flags = PSA_PS_FLAG_NONE; + uint8_t write_data[] = ASSET_A; + const uint32_t data_length = ASSET_A_SIZE; + uint8_t rewrite_data[] = RESETDATA; + const uint32_t reset_data_length = RESETDATA_SIZE; + uint8_t get_data[READ_LENGTH]; + uint32_t counter = 0; + + tfm_ns_lock_init(); + + for ( ; ; ) + { + /* Call TF-M protected storage service and set the asset. */ + status = psa_ps_set(uid, data_length, write_data, flags); + if (status != PSA_PS_SUCCESS) + { + rt_kprintf("[Protected Storage Asset A Set Round %ld] Fail\r\n", counter); + for( ; ; ); + } + + rt_kprintf("[Protected Storage Asset A Set Round %ld] Success\r\n", counter); + + /* Read the asset. */ + status = psa_ps_get(uid, 0, data_length, get_data); + if (status != PSA_PS_SUCCESS) + { + rt_kprintf("[Protected Storage Asset A Get Round %ld] Fail\r\n", counter); + for ( ; ; ); + } + + rt_kprintf("[Protected Storage Asset A Get Round %ld] Success\r\n", counter); + + /* Check the read data. */ + if (memcmp(write_data, get_data, sizeof(write_data) - 1) != 0) + { + rt_kprintf("[Protected Storage Asset A Get Round %ld] Get the wrong data\r\n", counter); + for ( ; ; ); + } + + /* Change the asset. */ + status = psa_ps_set(uid, reset_data_length, rewrite_data, flags); + if (status != PSA_PS_SUCCESS) + { + rt_kprintf("[Protected Storage Asset A Reset Round %ld] Fail\r\n", counter); + } + + rt_kprintf("[Protected Storage Asset A Reset Round %ld] Success\r\n", counter); + + /* Read the asset. */ + status = psa_ps_get(uid, 0, reset_data_length, get_data); + if (status != PSA_PS_SUCCESS) + { + rt_kprintf("[Protected Storage Asset A Get Round %ld] Fail\r\n", counter); + for ( ; ; ); + } + + rt_kprintf("[Protected Storage Asset A Get Round %ld] Success\r\n", counter); + + /* Check the read data. */ + if (memcmp(rewrite_data, get_data, sizeof(rewrite_data) - 1) != 0) + { + rt_kprintf("[Protected Storage Asset A Get Round %ld] Get the wrong data\r\n", counter); + for ( ; ; ); + } + + /* Remove the asset. */ + status = psa_ps_remove(uid); + if (status != PSA_PS_SUCCESS) + { + rt_kprintf("[Protected Storage Asset A Remove Round %ld] Fail\r\n", counter); + for ( ; ; ); + } + + rt_kprintf("[Protected Storage Asset A Remove Round %ld] Success\r\n\n", counter); + + /* Wait for a second. */ + rt_thread_mdelay(1000); + counter++; + } +} + +// end file diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c index 4a7fb3f88573e6a193af1ae259deea711abe1979..22e663b1f44feab59fc5766edc13203eaf6f729f 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -10,6 +11,7 @@ * 2010-05-02 Aozima update CMSIS to 130 * 2017-08-02 XiaoYang porting to LPC54608 bsp * 2019-08-05 Magicoe porting to LPC55S69-EVK bsp + * 2020-01-01 Karl Add RT_USING_TFM support */ #include @@ -56,11 +58,20 @@ void rt_hw_board_init() /* Set the Vector Table base location at 0x10000000 */ SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); #else /* VECT_TAB_FLASH */ + +#ifdef RT_USING_TFM + /* Set the Vector Table base location at 0x00020000 when RTT with TF-M*/ + SCB->VTOR = (0x00020000 & NVIC_VTOR_MASK); +#else /* Set the Vector Table base location at 0x00000000 */ SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK); #endif +#endif +#ifndef RT_USING_TFM + /* This init has finished in secure side of TF-M */ BOARD_BootClockPLL150M(); +#endif //BOARD_BootClockFROHF96M(); /* init systick 1 systick = 1/(100M / 100) 100systick = 1s*/ diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.h b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.h index f2fce5c093f8f96345e8174840e93cbd0526035f..32afed7da3a3886f6462c302ad88e3b15a134244 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.h +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.h @@ -36,10 +36,11 @@ extern int Image$$ARM_LIB_HEAP$$ZI$$Base; #pragma section="HEAP" #define HEAP_BEGIN (__segment_end("HEAP")) #elif defined(__GNUC__) -extern int __bss_end; -#define HEAP_BEGIN ((void *)&__bss_end) +extern int __HeapBase; +extern int __HeapLimit; +#define HEAP_BEGIN ((void *)&__HeapBase) #endif -#define HEAP_END (void*)(0x20000000 + 0x40000) +#define HEAP_END ((void*)&__HeapLimit) void rt_hw_board_init(void); diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf new file mode 100644 index 0000000000000000000000000000000000000000..e0ee619399ec9886b83d181a816a2d367db73c67 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf @@ -0,0 +1,111 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JET98_cm33_core0 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 +** Version: rev. 1.0, 2018-08-22 +** Build: b181008 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** Copyright 2019-2020 Arm Limited. All rights reserved. +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* + * Original code taken from RTT project at: + * https://github.com/RT-Thread/rt-thread + * File: bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_mdk.scf + * Git SHA of the original version: 64945ba882d651a14933eb4e7b3d93d10d6daae1 + */ + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x1000 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x1000 +#endif + +#define m_interrupts_start 0x00020000 +#define m_interrupts_size 0x00000200 + +#define m_text_start 0x00020200 +#define m_text_size 0x00031000 + +#define m_core1_image_start 0x00072000 +#define m_core1_image_size 0x00026000 + +#if (defined(__use_shmem__)) + #define m_data_start 0x20033000 + #define m_data_size 0x00010800 + #define m_rpmsg_sh_mem_start 0x20043800 + #define m_rpmsg_sh_mem_size 0x00000800 +#else + #define m_data_start 0x20033000 + #define m_data_size 0x0000cc00 +#endif + +#define m_usb_sram_start 0x40100000 +#define m_usb_sram_size 0x00004000 + + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + * (+RO) + } + +#if (defined(__use_shmem__)) + RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG + * (rpmsg_sh_mem_section) + } +#endif + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + * (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + + RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { + * (m_usb_bdt) + } + + RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { + * (m_usb_global) + } +} + +LR_CORE1_IMAGE m_core1_image_start { + CORE1_REGION m_core1_image_start m_core1_image_size { + *(M0CODE) + } +} diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/project_ns.uvoptx b/bsp/lpc55sxx/lpc55s69_nxp_evk/project_ns.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..b6a39c92b35e552db63b8007e08ca012561bc352 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/project_ns.uvoptx @@ -0,0 +1,1867 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
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+ 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 2 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x44000 + + + 1 + 0x0 + 0x98000 + + + 1 + 0x40100000 + 0x4000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x98000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x40100000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x44000 + + + 0 + 0x4000000 + 0x8000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + --target=arm-arm-none-eabi + CPU_LPC55S69JBD100_cm33_core0, RT_USING_ARM_LIBC, RT_USING_TFM + + .;..\..\..\include;applications;board;board\MCUX_Config\board;..\Libraries\drivers;..\Libraries\drivers\config;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\Libraries\LPC55S6X\CMSIS\Include;..\Libraries\LPC55S6X\components\codec;..\Libraries\LPC55S6X\LPC55S6X;..\Libraries\LPC55S6X\LPC55S6X\drivers;..\Libraries\LPC55S6X\middleware\sdmmc\inc;..\Libraries\LPC55S6X\middleware\sdmmc\port;.\packages\trusted-firmware-m-v1.0-beta\interface\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x02000000 + + .\board\linker_scripts\LPC55S69_cm33_core0_flash_ns_mdk.scf + + + + + + + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + signal.c + 1 + ..\..\..\src\signal.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Applications + + + main.c + 1 + applications\main.c + + + tfm_ps.c + 1 + .\applications\tfm_ps.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + clock_config.c + 1 + board\MCUX_Config\board\clock_config.c + + + pin_mux.c + 1 + board\MCUX_Config\board\pin_mux.c + + + drv_pin.c + 1 + ..\Libraries\drivers\drv_pin.c + + + drv_led.c + 1 + ..\Libraries\drivers\drv_led.c + + + drv_key.c + 1 + ..\Libraries\drivers\drv_key.c + + + drv_uart.c + 1 + ..\Libraries\drivers\drv_uart.c + + + drv_rtc.c + 1 + ..\Libraries\drivers\drv_rtc.c + + + drv_spi.c + 1 + ..\Libraries\drivers\drv_spi.c + + + drv_sd.c + 1 + ..\Libraries\drivers\drv_sd.c + + + drv_i2c.c + 1 + ..\Libraries\drivers\drv_i2c.c + + + drv_mma8562.c + 1 + ..\Libraries\drivers\drv_mma8562.c + + + drv_adc.c + 1 + ..\Libraries\drivers\drv_adc.c + + + drv_hwtimer.c + 1 + ..\Libraries\drivers\drv_hwtimer.c + + + drv_pwm.c + 1 + ..\Libraries\drivers\drv_pwm.c + + + + + cpu + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + Filesystem + + + dfs.c + 1 + ..\..\..\components\dfs\src\dfs.c + + + dfs_file.c + 1 + ..\..\..\components\dfs\src\dfs_file.c + + + dfs_fs.c + 1 + ..\..\..\components\dfs\src\dfs_fs.c + + + dfs_posix.c + 1 + ..\..\..\components\dfs\src\dfs_posix.c + + + poll.c + 1 + ..\..\..\components\dfs\src\poll.c + + + select.c + 1 + ..\..\..\components\dfs\src\select.c + + + devfs.c + 1 + ..\..\..\components\dfs\filesystems\devfs\devfs.c + + + + + DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + hwtimer.c + 1 + ..\..\..\components\drivers\hwtimer\hwtimer.c + + + i2c_core.c + 1 + ..\..\..\components\drivers\i2c\i2c_core.c + + + i2c_dev.c + 1 + ..\..\..\components\drivers\i2c\i2c_dev.c + + + i2c-bit-ops.c + 1 + ..\..\..\components\drivers\i2c\i2c-bit-ops.c + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + adc.c + 1 + ..\..\..\components\drivers\misc\adc.c + + + rt_drv_pwm.c + 1 + ..\..\..\components\drivers\misc\rt_drv_pwm.c + + + rtc.c + 1 + ..\..\..\components\drivers\rtc\rtc.c + + + block_dev.c + 1 + ..\..\..\components\drivers\sdio\block_dev.c + + + mmcsd_core.c + 1 + ..\..\..\components\drivers\sdio\mmcsd_core.c + + + sd.c + 1 + ..\..\..\components\drivers\sdio\sd.c + + + sdio.c + 1 + ..\..\..\components\drivers\sdio\sdio.c + + + mmc.c + 1 + ..\..\..\components\drivers\sdio\mmc.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + spi_core.c + 1 + ..\..\..\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + ..\..\..\components\drivers\spi\spi_dev.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + msh_file.c + 1 + ..\..\..\components\finsh\msh_file.c + + + finsh_compiler.c + 1 + ..\..\..\components\finsh\finsh_compiler.c + + + finsh_error.c + 1 + ..\..\..\components\finsh\finsh_error.c + + + finsh_heap.c + 1 + ..\..\..\components\finsh\finsh_heap.c + + + finsh_init.c + 1 + ..\..\..\components\finsh\finsh_init.c + + + finsh_node.c + 1 + ..\..\..\components\finsh\finsh_node.c + + + finsh_ops.c + 1 + ..\..\..\components\finsh\finsh_ops.c + + + finsh_parser.c + 1 + ..\..\..\components\finsh\finsh_parser.c + + + finsh_var.c + 1 + ..\..\..\components\finsh\finsh_var.c + + + finsh_vm.c + 1 + ..\..\..\components\finsh\finsh_vm.c + + + finsh_token.c + 1 + ..\..\..\components\finsh\finsh_token.c + + + + + libc + + + libc.c + 1 + ..\..\..\components\libc\compilers\armlibc\libc.c + + + mem_std.c + 1 + ..\..\..\components\libc\compilers\armlibc\mem_std.c + + + stdio.c + 1 + ..\..\..\components\libc\compilers\armlibc\stdio.c + + + stubs.c + 1 + ..\..\..\components\libc\compilers\armlibc\stubs.c + + + time.c + 1 + ..\..\..\components\libc\compilers\common\time.c + + + + + Libraries + + + system_LPC55S69_cm33_core0.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\system_LPC55S69_cm33_core0.c + + + startup_LPC55S69_cm33_core0.s + 2 + ..\Libraries\LPC55S6X\LPC55S6X\arm\startup_LPC55S69_cm33_core0.s + + + fsl_anactrl.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_anactrl.c + + + fsl_casper.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_casper.c + + + fsl_clock.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_clock.c + + + fsl_cmp.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_cmp.c + + + fsl_common.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_common.c + + + fsl_crc.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_crc.c + + + fsl_ctimer.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_ctimer.c + + + fsl_flexcomm.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_flexcomm.c + + + fsl_dma.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_dma.c + + + fsl_gint.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_gint.c + + + fsl_gpio.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_gpio.c + + + fsl_hashcrypt.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_hashcrypt.c + + + fsl_i2c.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2c.c + + + fsl_i2c_dma.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2c_dma.c + + + fsl_i2s.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2s.c + + + fsl_i2s_dma.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2s_dma.c + + + fsl_iap.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_iap.c + + + fsl_inputmux.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_inputmux.c + + + fsl_lpadc.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_lpadc.c + + + fsl_mrt.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_mrt.c + + + fsl_ostimer.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_ostimer.c + + + fsl_pint.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_pint.c + + + fsl_plu.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_plu.c + + + fsl_power.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_power.c + + + fsl_powerquad_basic.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_powerquad_basic.c + + + fsl_prince.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_prince.c + + + fsl_puf.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_puf.c + + + fsl_reset.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_reset.c + + + fsl_rng.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_rng.c + + + fsl_rtc.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_rtc.c + + + fsl_sctimer.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sctimer.c + + + fsl_sdif.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sdif.c + + + fsl_spi.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi.c + + + fsl_spi_dma.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi_dma.c + + + fsl_sysctl.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sysctl.c + + + fsl_usart.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart.c + + + fsl_usart_dma.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart_dma.c + + + fsl_utick.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_utick.c + + + fsl_wwdt.c + 1 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_wwdt.c + + + fsl_sd.c + 1 + ..\Libraries\LPC55S6X\middleware\sdmmc\src\fsl_sd.c + + + fsl_sdmmc_common.c + 1 + ..\Libraries\LPC55S6X\middleware\sdmmc\src\fsl_sdmmc_common.c + + + fsl_sdmmc_event.c + 1 + ..\Libraries\LPC55S6X\middleware\sdmmc\port\sdif\rt_thread\fsl_sdmmc_event.c + + + fsl_sdmmc_host.c + 1 + ..\Libraries\LPC55S6X\middleware\sdmmc\port\sdif\rt_thread\fsl_sdmmc_host.c + + + arm_keil_lib_power_cm33_core0.lib + 4 + ..\Libraries\LPC55S6X\LPC55S6X\arm\keil_lib_power_cm33_core0.lib + + + + + TFM + + + tfm_sst_api.c + 1 + .\packages\trusted-firmware-m-v1.0-beta\interface\src\tfm_sst_api.c + + + tfm_ns_lock_rt-thread.c + 1 + .\packages\trusted-firmware-m-v1.0-beta\interface\src\tfm_ns_lock_rt-thread.c + + + s_veneers.o + 3 + .\packages\trusted-firmware-m-v1.0-beta\cmake_build\install\export\tfm\veneers\s_veneers.o + + + + + + + + + + + + + +     diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/rtconfig.h b/bsp/lpc55sxx/lpc55s69_nxp_evk/rtconfig.h index b46ecc715d41c1a8d22c24728071b1ee3a93bb4c..fcf35369ddd239aeafbea461f1f7b29aec11c847 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/rtconfig.h +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/rtconfig.h @@ -16,7 +16,7 @@ #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_USING_IDLE_HOOK -#define RT_IDEL_HOOK_LIST_SIZE 4 +#define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/rtconfig.py b/bsp/lpc55sxx/lpc55s69_nxp_evk/rtconfig.py index 25d2373c3841759269b533e45dafffafcbde84e9..70c4c80b61bae312eff4c21072c2751939039b5b 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/rtconfig.py +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/rtconfig.py @@ -46,7 +46,7 @@ if PLATFORM == 'gcc': DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' - LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/LPC55S69_cm33_core0_flash.ld' CPATH = '' LPATH = '' diff --git a/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c b/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c index 0b1ee9827d00752f6c11b8795fd1d02334c30c7d..334e22f7014746c25aaeaeed91a69c186d372642 100644 --- a/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c +++ b/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c @@ -36,7 +36,7 @@ #include #define FRAME_PERIOD_US (50) -#define PL041_CHANNLE_NUM (4) +#define PL041_CHANNEL_NUM (4) #define PL041_READ(_a) (*(volatile rt_uint32_t *)(_a)) #define PL041_WRITE(_a, _v) (*(volatile rt_uint32_t *)(_a) = (_v)) @@ -47,7 +47,7 @@ struct pl041_irq_def void *user_data; }; -static struct pl041_irq_def irq_tbl[PL041_CHANNLE_NUM]; +static struct pl041_irq_def irq_tbl[PL041_CHANNEL_NUM]; static void aaci_pl041_delay(rt_uint32_t us) { @@ -169,13 +169,13 @@ rt_uint16_t aaci_ac97_read(rt_uint16_t reg) return v; } -int aaci_pl041_channle_disable(int channle) +int aaci_pl041_channel_disable(int channel) { rt_uint32_t v; void *p_rx, *p_tx; - p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channle * 0x14); - p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channle * 0x14); + p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channel * 0x14); + p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channel * 0x14); v = PL041_READ(p_rx); v &= ~AACI_CR_EN; PL041_WRITE(p_rx, v); @@ -185,13 +185,13 @@ int aaci_pl041_channle_disable(int channle) return 0; } -int aaci_pl041_channle_enable(int channle) +int aaci_pl041_channel_enable(int channel) { rt_uint32_t v; void *p_rx, *p_tx; - p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channle * 0x14); - p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channle * 0x14); + p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channel * 0x14); + p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channel * 0x14); v = PL041_READ(p_rx); v |= AACI_CR_EN; PL041_WRITE(p_rx, v); @@ -201,13 +201,13 @@ int aaci_pl041_channle_enable(int channle) return 0; } -int aaci_pl041_channle_read(int channle, rt_uint16_t *buff, int count) +int aaci_pl041_channel_read(int channel, rt_uint16_t *buff, int count) { void *p_data, *p_status; int i = 0; - p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channle * 0x14); - p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channle * 0x20); + p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channel * 0x14); + p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channel * 0x20); for (i = 0; (!(PL041_READ(p_status) & AACI_SR_RXFE)) && (i < count); i++) { buff[i] = (rt_uint16_t)PL041_READ(p_data); @@ -215,13 +215,13 @@ int aaci_pl041_channle_read(int channle, rt_uint16_t *buff, int count) return i; } -int aaci_pl041_channle_write(int channle, rt_uint16_t *buff, int count) +int aaci_pl041_channel_write(int channel, rt_uint16_t *buff, int count) { void *p_data, *p_status; int i = 0; - p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channle * 0x14); - p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channle * 0x20); + p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channel * 0x14); + p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channel * 0x20); for (i = 0; (!(PL041_READ(p_status) & AACI_SR_TXFF)) && (i < count); i++) { PL041_WRITE(p_data, buff[i]); @@ -229,13 +229,13 @@ int aaci_pl041_channle_write(int channle, rt_uint16_t *buff, int count) return i; } -int aaci_pl041_channle_cfg(int channle, pl041_cfg_t cgf) +int aaci_pl041_channel_cfg(int channel, pl041_cfg_t cgf) { rt_uint32_t v; void *p_rx, *p_tx; - p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channle * 0x14); - p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channle * 0x14); + p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channel * 0x14); + p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channel * 0x14); v = AACI_CR_FEN | AACI_CR_SZ16 | cgf->itype; PL041_WRITE(p_rx, v); v = AACI_CR_FEN | AACI_CR_SZ16 | cgf->otype; @@ -247,86 +247,86 @@ int aaci_pl041_channle_cfg(int channle, pl041_cfg_t cgf) return 0; } -void aaci_pl041_irq_enable(int channle, rt_uint32_t vector) +void aaci_pl041_irq_enable(int channel, rt_uint32_t vector) { rt_uint32_t v; void *p_irq; vector &= vector & 0x7f; - p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channle * 0x14); + p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channel * 0x14); v = PL041_READ(p_irq); v |= vector; PL041_WRITE(p_irq, v); } -void aaci_pl041_irq_disable(int channle, rt_uint32_t vector) +void aaci_pl041_irq_disable(int channel, rt_uint32_t vector) { rt_uint32_t v; void *p_irq; vector &= vector & 0x7f; - p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channle * 0x14); + p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channel * 0x14); v = PL041_READ(p_irq); v &= ~vector; PL041_WRITE(p_irq, v); } -rt_err_t aaci_pl041_irq_register(int channle, pl041_irq_fun_t fun, void *user_data) +rt_err_t aaci_pl041_irq_register(int channel, pl041_irq_fun_t fun, void *user_data) { - if (channle < 0 || channle >= PL041_CHANNLE_NUM) + if (channel < 0 || channel >= PL041_CHANNEL_NUM) { - LOG_E("%s channle:%d err.", __FUNCTION__, channle); + LOG_E("%s channel:%d err.", __FUNCTION__, channel); return -RT_ERROR; } - irq_tbl[channle].fun = fun; - irq_tbl[channle].user_data = user_data; + irq_tbl[channel].fun = fun; + irq_tbl[channel].user_data = user_data; return RT_EOK; } -rt_err_t aaci_pl041_irq_unregister(int channle) +rt_err_t aaci_pl041_irq_unregister(int channel) { - if (channle < 0 || channle >= PL041_CHANNLE_NUM) + if (channel < 0 || channel >= PL041_CHANNEL_NUM) { - LOG_E("%s channle:%d err.", __FUNCTION__, channle); + LOG_E("%s channel:%d err.", __FUNCTION__, channel); return -RT_ERROR; } - irq_tbl[channle].fun = RT_NULL; - irq_tbl[channle].user_data = RT_NULL; + irq_tbl[channel].fun = RT_NULL; + irq_tbl[channel].user_data = RT_NULL; return RT_EOK; } static void aaci_pl041_irq_handle(int irqno, void *param) { - rt_uint32_t mask, channle, m; + rt_uint32_t mask, channel, m; struct pl041_irq_def *_irq = param; void *p_status; mask = PL041_READ(&PL041->allints); PL041_WRITE(&PL041->intclr, mask); - for (channle = 0; (channle < PL041_CHANNLE_NUM) && (mask); channle++) + for (channel = 0; (channel < PL041_CHANNEL_NUM) && (mask); channel++) { mask = mask >> 7; m = mask & 0x7f; if (m & AACI_ISR_ORINTR) { - LOG_W("RX overrun on chan %d", channle); + LOG_W("RX overrun on chan %d", channel); } if (m & AACI_ISR_RXTOINTR) { - LOG_W("RX timeout on chan %d", channle); + LOG_W("RX timeout on chan %d", channel); } if (mask & AACI_ISR_URINTR) { - LOG_W("TX underrun on chan %d", channle); + LOG_W("TX underrun on chan %d", channel); } - p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channle * 0x14); - if (_irq[channle].fun != RT_NULL) + p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channel * 0x14); + if (_irq[channel].fun != RT_NULL) { - _irq[channle].fun(PL041_READ(p_status), _irq[channle].user_data); + _irq[channel].fun(PL041_READ(p_status), _irq[channel].user_data); } } } diff --git a/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.h b/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.h index 5ea146e4360af3fa30a6d93e7ba12903baff4ada..cd972b5bdd4412d45f4c16eb2dc748bd63444a37 100644 --- a/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.h +++ b/bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.h @@ -158,10 +158,10 @@ #define MAINFR_TXB (1 << 1) /* transmit busy */ #define MAINFR_RXB (1 << 0) /* receive busy */ -#define PL041_CHANNLE_LEFT_DAC (0x1 << 3) -#define PL041_CHANNLE_RIGHT_DAC (0x1 << 3) -#define PL041_CHANNLE_LEFT_ADC (0x1 << 3) -#define PL041_CHANNLE_RIGHT_ADC (0x1 << 3) +#define PL041_CHANNEL_LEFT_DAC (0x1 << 3) +#define PL041_CHANNEL_RIGHT_DAC (0x1 << 3) +#define PL041_CHANNEL_LEFT_ADC (0x1 << 3) +#define PL041_CHANNEL_RIGHT_ADC (0x1 << 3) struct reg_pl041 { @@ -225,13 +225,13 @@ typedef void (*pl041_irq_fun_t)(rt_uint32_t status, void * user_data); rt_err_t aaci_pl041_init(void); void aaci_ac97_write(rt_uint16_t reg, rt_uint16_t val); rt_uint16_t aaci_ac97_read(rt_uint16_t reg); -int aaci_pl041_channle_cfg(int channle, pl041_cfg_t cfg); -int aaci_pl041_channle_write(int channle, rt_uint16_t *buff, int count); -int aaci_pl041_channle_read(int channle, rt_uint16_t *buff, int count); -int aaci_pl041_channle_enable(int channle); -int aaci_pl041_channle_disable(int channle); -rt_err_t aaci_pl041_irq_register(int channle, pl041_irq_fun_t fun, void *user_data); -rt_err_t aaci_pl041_irq_unregister(int channle); -void aaci_pl041_irq_disable(int channle, rt_uint32_t vector); -void aaci_pl041_irq_enable(int channle, rt_uint32_t vector); +int aaci_pl041_channel_cfg(int channel, pl041_cfg_t cfg); +int aaci_pl041_channel_write(int channel, rt_uint16_t *buff, int count); +int aaci_pl041_channel_read(int channel, rt_uint16_t *buff, int count); +int aaci_pl041_channel_enable(int channel); +int aaci_pl041_channel_disable(int channel); +rt_err_t aaci_pl041_irq_register(int channel, pl041_irq_fun_t fun, void *user_data); +rt_err_t aaci_pl041_irq_unregister(int channel); +void aaci_pl041_irq_disable(int channel, rt_uint32_t vector); +void aaci_pl041_irq_enable(int channel, rt_uint32_t vector); #endif diff --git a/bsp/qemu-vexpress-a9/drivers/audio/drv_sound.c b/bsp/qemu-vexpress-a9/drivers/audio/drv_sound.c index cee67b0a0b4a052a610b637dd1bb3205482c30ea..a2b46831b800875441df0518e75fc9aa688d1237 100644 --- a/bsp/qemu-vexpress-a9/drivers/audio/drv_sound.c +++ b/bsp/qemu-vexpress-a9/drivers/audio/drv_sound.c @@ -227,13 +227,13 @@ static rt_err_t sound_init(struct rt_audio_device *audio) aaci_pl041_init(); - _cfg.itype = PL041_CHANNLE_LEFT_ADC | PL041_CHANNLE_RIGHT_ADC; - _cfg.otype = PL041_CHANNLE_LEFT_DAC | PL041_CHANNLE_RIGHT_DAC; + _cfg.itype = PL041_CHANNEL_LEFT_ADC | PL041_CHANNEL_RIGHT_ADC; + _cfg.otype = PL041_CHANNEL_LEFT_DAC | PL041_CHANNEL_RIGHT_DAC; _cfg.vol = snd_dev->volume; _cfg.rate = snd_dev->replay_config.samplerate; ac97_reset(); - aaci_pl041_channle_cfg(0, &_cfg); + aaci_pl041_channel_cfg(0, &_cfg); aaci_pl041_irq_register(0, rt_hw_aaci_isr, RT_NULL); return result; @@ -246,7 +246,7 @@ static rt_err_t sound_start(struct rt_audio_device *audio, int stream) if (stream == AUDIO_STREAM_REPLAY) { LOG_D("open sound device"); - aaci_pl041_channle_enable(0); + aaci_pl041_channel_enable(0); aaci_pl041_irq_enable(0, AACI_IE_UR | AACI_IE_TX | AACI_IE_TXC); } @@ -263,7 +263,7 @@ static rt_err_t sound_stop(struct rt_audio_device *audio, int stream) rt_thread_mdelay(100); /* disable irq and channels 0 */ aaci_pl041_irq_disable(0, AACI_IE_UR | AACI_IE_TX | AACI_IE_TXC); - aaci_pl041_channle_disable(0); + aaci_pl041_channel_disable(0); LOG_D("close sound device"); } @@ -295,7 +295,7 @@ static rt_size_t sound_transmit(struct rt_audio_device *audio, const void *write RT_ASSERT(audio != RT_NULL); /* write data to channel_0 fifo */ - aaci_pl041_channle_write(0, (rt_uint16_t *)writeBuf, size >> 1); + aaci_pl041_channel_write(0, (rt_uint16_t *)writeBuf, size >> 1); return size; } diff --git a/bsp/raspi2/.config b/bsp/raspberry-pi/raspi2/.config similarity index 100% rename from bsp/raspi2/.config rename to bsp/raspberry-pi/raspi2/.config diff --git a/bsp/raspi2/Kconfig b/bsp/raspberry-pi/raspi2/Kconfig similarity index 95% rename from bsp/raspi2/Kconfig rename to bsp/raspberry-pi/raspi2/Kconfig index 06cbe1128fdb2402a78c1c1e88206f625eb415a8..f7693c837813f47b0315f2305537b4922259e3c8 100644 --- a/bsp/raspi2/Kconfig +++ b/bsp/raspberry-pi/raspi2/Kconfig @@ -8,7 +8,7 @@ config BSP_DIR config RTT_DIR string option env="RTT_ROOT" - default "../.." + default "../../.." config PKGS_DIR string diff --git a/bsp/raspi2/README.md b/bsp/raspberry-pi/raspi2/README.md similarity index 100% rename from bsp/raspi2/README.md rename to bsp/raspberry-pi/raspi2/README.md diff --git a/bsp/raspi2/SConscript b/bsp/raspberry-pi/raspi2/SConscript similarity index 100% rename from bsp/raspi2/SConscript rename to bsp/raspberry-pi/raspi2/SConscript diff --git a/bsp/raspi2/SConstruct b/bsp/raspberry-pi/raspi2/SConstruct similarity index 100% rename from bsp/raspi2/SConstruct rename to bsp/raspberry-pi/raspi2/SConstruct diff --git a/bsp/raspi2/applications/SConscript b/bsp/raspberry-pi/raspi2/applications/SConscript similarity index 100% rename from bsp/raspi2/applications/SConscript rename to bsp/raspberry-pi/raspi2/applications/SConscript diff --git a/bsp/raspi2/applications/main.c b/bsp/raspberry-pi/raspi2/applications/main.c similarity index 100% rename from bsp/raspi2/applications/main.c rename to bsp/raspberry-pi/raspi2/applications/main.c diff --git a/bsp/raspi2/applications/mnt.c b/bsp/raspberry-pi/raspi2/applications/mnt.c similarity index 100% rename from bsp/raspi2/applications/mnt.c rename to bsp/raspberry-pi/raspi2/applications/mnt.c diff --git a/bsp/raspi2/cpu/SConscript b/bsp/raspberry-pi/raspi2/cpu/SConscript similarity index 100% rename from bsp/raspi2/cpu/SConscript rename to bsp/raspberry-pi/raspi2/cpu/SConscript diff --git a/bsp/raspi2/cpu/armv7.h b/bsp/raspberry-pi/raspi2/cpu/armv7.h similarity index 100% rename from bsp/raspi2/cpu/armv7.h rename to bsp/raspberry-pi/raspi2/cpu/armv7.h diff --git a/bsp/raspi2/cpu/context_gcc.S b/bsp/raspberry-pi/raspi2/cpu/context_gcc.S similarity index 100% rename from bsp/raspi2/cpu/context_gcc.S rename to bsp/raspberry-pi/raspi2/cpu/context_gcc.S diff --git a/bsp/raspi2/cpu/cp15.h b/bsp/raspberry-pi/raspi2/cpu/cp15.h similarity index 100% rename from bsp/raspi2/cpu/cp15.h rename to bsp/raspberry-pi/raspi2/cpu/cp15.h diff --git a/bsp/raspi2/cpu/cp15_gcc.S b/bsp/raspberry-pi/raspi2/cpu/cp15_gcc.S similarity index 100% rename from bsp/raspi2/cpu/cp15_gcc.S rename to bsp/raspberry-pi/raspi2/cpu/cp15_gcc.S diff --git a/bsp/raspi2/cpu/cpu.c b/bsp/raspberry-pi/raspi2/cpu/cpu.c similarity index 100% rename from bsp/raspi2/cpu/cpu.c rename to bsp/raspberry-pi/raspi2/cpu/cpu.c diff --git a/bsp/raspi2/cpu/interrupt.c b/bsp/raspberry-pi/raspi2/cpu/interrupt.c similarity index 100% rename from bsp/raspi2/cpu/interrupt.c rename to bsp/raspberry-pi/raspi2/cpu/interrupt.c diff --git a/bsp/raspi2/cpu/mmu.c b/bsp/raspberry-pi/raspi2/cpu/mmu.c similarity index 100% rename from bsp/raspi2/cpu/mmu.c rename to bsp/raspberry-pi/raspi2/cpu/mmu.c diff --git a/bsp/raspi2/cpu/stack.c b/bsp/raspberry-pi/raspi2/cpu/stack.c similarity index 100% rename from bsp/raspi2/cpu/stack.c rename to bsp/raspberry-pi/raspi2/cpu/stack.c diff --git a/bsp/raspi2/cpu/start_gcc.S b/bsp/raspberry-pi/raspi2/cpu/start_gcc.S similarity index 100% rename from bsp/raspi2/cpu/start_gcc.S rename to bsp/raspberry-pi/raspi2/cpu/start_gcc.S diff --git a/bsp/raspi2/cpu/trap.c b/bsp/raspberry-pi/raspi2/cpu/trap.c similarity index 100% rename from bsp/raspi2/cpu/trap.c rename to bsp/raspberry-pi/raspi2/cpu/trap.c diff --git a/bsp/raspi2/cpu/vector_gcc.S b/bsp/raspberry-pi/raspi2/cpu/vector_gcc.S similarity index 100% rename from bsp/raspi2/cpu/vector_gcc.S rename to bsp/raspberry-pi/raspi2/cpu/vector_gcc.S diff --git a/bsp/raspi2/driver/Kconfig b/bsp/raspberry-pi/raspi2/driver/Kconfig similarity index 100% rename from bsp/raspi2/driver/Kconfig rename to bsp/raspberry-pi/raspi2/driver/Kconfig diff --git a/bsp/raspi2/driver/SConscript b/bsp/raspberry-pi/raspi2/driver/SConscript similarity index 100% rename from bsp/raspi2/driver/SConscript rename to bsp/raspberry-pi/raspi2/driver/SConscript diff --git a/bsp/raspi2/driver/bcm283x.h b/bsp/raspberry-pi/raspi2/driver/bcm283x.h similarity index 100% rename from bsp/raspi2/driver/bcm283x.h rename to bsp/raspberry-pi/raspi2/driver/bcm283x.h diff --git a/bsp/raspi2/driver/board.c b/bsp/raspberry-pi/raspi2/driver/board.c similarity index 100% rename from bsp/raspi2/driver/board.c rename to bsp/raspberry-pi/raspi2/driver/board.c diff --git a/bsp/raspi2/driver/board.h b/bsp/raspberry-pi/raspi2/driver/board.h similarity index 100% rename from bsp/raspi2/driver/board.h rename to bsp/raspberry-pi/raspi2/driver/board.h diff --git a/bsp/raspi2/driver/drv_uart.c b/bsp/raspberry-pi/raspi2/driver/drv_uart.c similarity index 100% rename from bsp/raspi2/driver/drv_uart.c rename to bsp/raspberry-pi/raspi2/driver/drv_uart.c diff --git a/bsp/raspi2/driver/drv_uart.h b/bsp/raspberry-pi/raspi2/driver/drv_uart.h similarity index 100% rename from bsp/raspi2/driver/drv_uart.h rename to bsp/raspberry-pi/raspi2/driver/drv_uart.h diff --git a/bsp/raspi2/figures/raspi2.png b/bsp/raspberry-pi/raspi2/figures/raspi2.png similarity index 100% rename from bsp/raspi2/figures/raspi2.png rename to bsp/raspberry-pi/raspi2/figures/raspi2.png diff --git a/bsp/raspi2/figures/raspi_uart.png b/bsp/raspberry-pi/raspi2/figures/raspi_uart.png similarity index 100% rename from bsp/raspi2/figures/raspi_uart.png rename to bsp/raspberry-pi/raspi2/figures/raspi_uart.png diff --git a/bsp/raspi2/link.lds b/bsp/raspberry-pi/raspi2/link.lds similarity index 100% rename from bsp/raspi2/link.lds rename to bsp/raspberry-pi/raspi2/link.lds diff --git a/bsp/raspi2/rtconfig.h b/bsp/raspberry-pi/raspi2/rtconfig.h similarity index 100% rename from bsp/raspi2/rtconfig.h rename to bsp/raspberry-pi/raspi2/rtconfig.h diff --git a/bsp/raspi2/rtconfig.py b/bsp/raspberry-pi/raspi2/rtconfig.py similarity index 94% rename from bsp/raspi2/rtconfig.py rename to bsp/raspberry-pi/raspi2/rtconfig.py index 37475595a2e644c286296edf571e0bf6bf01cb8b..8c827e82210881bfaef2c9210f163615d7c0581b 100644 --- a/bsp/raspi2/rtconfig.py +++ b/bsp/raspberry-pi/raspi2/rtconfig.py @@ -8,13 +8,13 @@ CROSS_TOOL ='gcc' if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = r'../..' + RTT_ROOT = r'../../..' if os.getenv('RTT_CC'): CROSS_TOOL = os.getenv('RTT_CC') PLATFORM = 'gcc' -EXEC_PATH = r'/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin' +EXEC_PATH = r'/opt/gcc-arm-none-eabi-5_4-2016q3/bin' if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') diff --git a/bsp/raspberry-pi/raspi3-32/.config b/bsp/raspberry-pi/raspi3-32/.config new file mode 100644 index 0000000000000000000000000000000000000000..78d7e6fbafa2a76ad1b194e9aa72db27b3a37ad5 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/.config @@ -0,0 +1,427 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMP=y +CONFIG_RT_CPUS_NR=4 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +CONFIG_RT_USING_MEMTRACE=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +CONFIG_RT_USING_DEVICE_OPS=y +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40002 +CONFIG_ARCH_ARM=y +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_ARM_CORTEX_A=y +CONFIG_ARCH_ARM_CORTEX_A7=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +CONFIG_RT_USING_HWTIMER=y +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_USING_I2C_BITOPS is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=512 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=1024 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +CONFIG_RT_USING_WDT=y +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_LCD_DRIVERS is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +CONFIG_BCM2836_SOC=y + +# +# Hardware Drivers Config +# + +# +# BCM Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +# CONFIG_RT_USING_UART0 is not set +CONFIG_RT_USING_UART1=y +CONFIG_BSP_USING_PIN=y +CONFIG_BSP_USING_SYSTIMER=y +CONFIG_RT_USING_SYSTIMER1=y +CONFIG_RT_USING_SYSTIMER3=y +CONFIG_BSP_USING_I2C=y +CONFIG_BSP_USING_I2C0=y +CONFIG_BSP_USING_I2C1=y +CONFIG_BSP_USING_SPI=y +CONFIG_BSP_USING_SPI0_BUS=y +CONFIG_BSP_USING_SPI0_DEVICE0=y +CONFIG_BSP_USING_SPI0_DEVICE1=y +CONFIG_BSP_USING_WDT=y +CONFIG_BSP_USING_RTC=y +# CONFIG_BSP_USING_ALARM is not set +CONFIG_BSP_USING_SDIO=y +CONFIG_BSP_USING_SDIO0=y +CONFIG_BSP_USING_HDMI=y diff --git a/bsp/raspberry-pi/raspi3-32/Kconfig b/bsp/raspberry-pi/raspi3-32/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..f7693c837813f47b0315f2305537b4922259e3c8 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/Kconfig @@ -0,0 +1,28 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config BCM2836_SOC + bool + select ARCH_ARM_CORTEX_A7 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "driver/Kconfig" diff --git a/bsp/raspberry-pi/raspi3-32/README.md b/bsp/raspberry-pi/raspi3-32/README.md new file mode 100644 index 0000000000000000000000000000000000000000..2d1e18655b654df953829f411b9187ed6062b525 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/README.md @@ -0,0 +1,153 @@ +# Raspberry PI 3B(32位)板级支持包说明 + +## 1. 简介 + +树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发，莓派3采用4核Broadcom BCM2837 (ARMv8)芯片、双核VideoCore IV GPU和1GB内存。 + +这份RT-Thread BSP是针对 Raspberry Pi 3B （32位）的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。 + +随着RT-Thread的发展，它越来越多的向一些Cortex-A等AP类处理器提供支持，例如全志的ARM9、Cortex-A处理器，Xilinx的Zynq处理器等。 + +而RT-Thread也是一套高度社区化发展的操作系统，所以在一些方向推进上希望以社区化方式，大家一起来推动的方式向前发展，在这个过程中RT-Thread得到了不同开发者、不同领域的应用，一步步把RT-Thread推向成熟。而在Cortex-A平台上，目前最流行的硬件平台是树莓派，分树莓派[2B](https://www.raspberrypi.org/products/raspberry-pi-2-model-b/)、[3B](https://www.raspberrypi.org/products/raspberry-pi-3-model-b/)以及最新的[4B](https://www.raspberrypi.org/products/raspberry-pi-4-model-b/)等。 + +RT-Thread对树莓派的支持主要从树莓派2B开始，它是一个四核Cortex-A7的平台，以32位单核的模式运行。后续将推动着RT-Thread向树莓派3，四核Cortex-A53 64位模式发展（中间当然也可能出现四核Cortex-A7模式执行的过渡性版本）。 + +![raspi3_f](figures/raspi3_f.jpg) + +![raspi3_b](figures/raspi3_b.jpg) + +当前Raspberry Pi 3B对应的硬件特性： + +| 硬件 | 描述 | +|------- | ------------------------------- | +| CPU | quad-core ARM Cortex A53(ARMv8) | +| 主频 | 1.2 GHz | +| GPU | VideoCore IV | +| GPU频率 | 400MHz | +| Memory | 1GB (0x0000000 - 0x40000000) | +| | 其中0x3f000000 - 0x40000000为peripheral | + +硬件引脚分布情况 + +![GPIO-Pinout-Diagram-2](figures/GPIO-Pinout-Diagram-2.png) + +## 2. 编译说明 + +Windows环境下推荐使用[env工具][1]进行编译。 + +Linux下推荐使用gcc工具 gcc-arm-none-eabi-5_4-2016q3，如果还没有编译工具，下载后，解开文件。 + +``` +tar vxf gcc-arm-none-eabi-5_4-2016q3-20160926-linux.tar.bz2 +``` + +Linux环境下需要修改编译器目录设置，修改`bsp/raspi3-32/rtconfig.py`中的 + +``` +EXEC_PATH = r'/opt/gcc-arm-none-eabi-5_4-2016q3/bin' +``` + +为编译工具的实际所在目录，这里注意要加上后缀 `/bin` + +进入到`rt-thread/bsp/raspi3-32`目录中，运行以下命令： + +``` +scons +``` + +来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、kernel7.img文件。 +kernel7.img即是要cp到raspberry SD卡中根目录的文件 + +### 2.1 eclipse 编码环境 ### +第一步： 安装 eclipse cdt +第二步： 打开 eclipse cdt 设置workspace ,推荐设置于xxx\xxx\rt-thread\bsp +第三步： Import 工程 General-> Existing Peojects into Workspace 然后 Browse.. 你的raspi3目录，点击Finish + +btw:编译依旧使用scons,目前不支持qemu debug,后期如果有大佬实现ARM JTAG调试 + +## 3. 执行 + +### 3.1 下载[raspbian镜像][3]，生成可以运行的raspbian SD卡 + +Windows下，去[etcher.io][4]下载etcher,这是个可以烧写img的工具 + +解开下载的镜像文件, linux下使用如下的命令 + +``` +unzip 2018-06-27-raspbian-stretch-lite.zip +``` + +准备一张空SD卡，linux环境下，插入电脑并执行 + +``` +sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync +``` + +**注意: /dev/xxx 要换成真实环境中的SD卡所在设置，千万不要弄错。** + +Windows环境下，执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。 + +最后把kernel7.img放入SD boot分区，覆盖原来的文件。 + +### 3.2 准备好串口线 + +目前版本是使用raspi3的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示： + + + +![raspberrypi-console](figures/raspberrypi-console.png) + +串口参数： 115200 8N1 ，硬件和软件流控为关。 + +按上面的方法做好SD卡后，插入树莓派3B，通电可以在串口上看到如下所示的输出信息： + +```text +heap: 0x0005d784 - 0x0045d784 + + \ | / +- RT - Thread Operating System + / | \ 4.0.2 build Jan 9 2020 + 2006 - 2019 Copyright by rt-thread team +[I/I2C] I2C bus [i2c0] registered +[I/I2C] I2C bus [i2c1] registered +[I/SDIO] SD card capacity 15558144 KB. +found part[0], begin: 1048576, size: 63.0MB +found part[1], begin: 67108864, size: 14.793GB +file system initialization done! +boot cpu:3 +msh />cpu = 0x00000003 +cpu 3 startup. +start OK: CPU 3 +boot cpu:2 +cpu = 0x00000002 +cpu 2 startup. +start OK: CPU 2 +boot cpu:1 +cpu = 0x00000001 +cpu 1 startup. +start OK: CPU 1 +Hello RT-Thread! + +msh /> +``` + +## 4. 支持情况 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | UART0| +| GPIO | 支持 | | +| IIC | 支持 | | +| SPI | 支持 | | +| CPU Timer | 支持 | | +| SD卡驱动 | 支持 | | + +## 5. 联系人信息 + +维护人：[bernard][5] + +[1]: https://www.rt-thread.org/page/download.html +[2]: https://launchpad.net/gcc-arm-embedded/4.8/4.8-2014-q1-update/+download/gcc-arm-none-eabi-4_8-2014q1-20140314-linux.tar.bz2 +[3]: https://downloads.raspberrypi.org/raspbian_lite_latest +[4]: https://etcher.io +[5]: https://github.com/BernardXiong diff --git a/bsp/raspberry-pi/raspi3-32/SConscript b/bsp/raspberry-pi/raspi3-32/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..c7ef7659ecea92b1dd9b71a97736a8552ee02551 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/raspberry-pi/raspi3-32/SConstruct b/bsp/raspberry-pi/raspi3-32/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..e94a364d9dd1df4b57b23e774836d1fd871c0a7d --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/SConstruct @@ -0,0 +1,28 @@ +import os +import sys +import rtconfig + +from rtconfig import RTT_ROOT + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/raspberry-pi/raspi3-32/applications/SConscript b/bsp/raspberry-pi/raspi3-32/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..533df8ac31d12aaf4a835cde3a1554d8d65d955a --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/raspberry-pi/raspi3-32/applications/main.c b/bsp/raspberry-pi/raspi3-32/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..cda0e0d711059681785a4a64040dd198ab17cf59 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/applications/main.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-5-30 bernard the first version + */ + +#include + +int main(int argc, char** argv) +{ + rt_kprintf("Hello RT-Thread!\n"); + + return 0; +} diff --git a/bsp/raspberry-pi/raspi3-32/applications/mnt.c b/bsp/raspberry-pi/raspi3-32/applications/mnt.c new file mode 100644 index 0000000000000000000000000000000000000000..88b714022c07228d858be971a801d0bb8fb63f0b --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/applications/mnt.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-5-30 bernard the first version + */ + +#include + +#ifdef BSP_USING_SDIO0 +#include + +int mnt_init(void) +{ + rt_thread_delay(RT_TICK_PER_SECOND); + + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("file system initialization done!\n"); + } + + return 0; +} +INIT_ENV_EXPORT(mnt_init); +#endif + diff --git a/bsp/raspberry-pi/raspi3-32/applications/test_device.c b/bsp/raspberry-pi/raspi3-32/applications/test_device.c new file mode 100644 index 0000000000000000000000000000000000000000..7efb1cfb6418e2f92cea07de3213977fd25a2f30 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/applications/test_device.c @@ -0,0 +1,462 @@ +/* + * File : test_driver.h + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#include +#include +#include +#include +#include +#include "raspi.h" + +#ifdef BSP_USING_HDMI +#include "drv_fb.h" +#endif + +void test_hdmi() +{ + rt_kprintf("Hello Test hdmi!\n"); +#ifdef BSP_USING_HDMI + print_fb_info(); +#ifdef BSP_USING_HDMI_DISPLAY + rt_kprintf("hdmi is tested!\n"); +#else + rt_console_set_device("hdmi"); + rt_kprintf("hdmi is testing!\n"); +#endif + rt_kprintf("search hdmi device"); + rt_device_t hdmi = rt_device_find("hdmi"); + if (hdmi == RT_NULL) + { + rt_kprintf("cannot find hdmi device"); + } + int color = COLOR_YELLOW; + rt_kprintf("begin test hdmi deivice"); + rt_graphix_ops(hdmi) -> set_pixel((char *)&color, 5, 5); + + rt_graphix_ops(hdmi) -> get_pixel((char *)&color, 5, 5); + rt_kprintf("color is %x\n",color); + rt_graphix_ops(hdmi) -> draw_hline((char *)&color, 10, 100, 10); + color = COLOR_GREEN; + rt_graphix_ops(hdmi) -> draw_vline((char *)&color, 10, 10, 100); + int colors[100]; + int i=0; + for (; i < 20; i++) colors[i] = COLOR_RED; + rt_graphix_ops(hdmi) -> blit_line((char *)colors, 20, 20, 20); + +#endif +} + +#ifdef RT_USING_SMP +#define _CPUS_NR RT_CPUS_NR +#else +#define _CPUS_NR 1 +#endif + +#ifdef RT_USING_SMP +static rt_uint8_t rt_thread_stack[_CPUS_NR][128]; +static struct rt_thread smp[_CPUS_NR]; +void smp_test_entry() +{ + rt_kprintf("cpu %d is running.\n",rt_hw_cpu_id()); +} +#endif + +void test_cpusmp(void) +{ + rt_kprintf("Hello Test SMP!\n"); +#ifdef RT_USING_SMP + int i; + char test_name[RT_NAME_MAX]; + for (i = 0; i < _CPUS_NR; i++) + { + rt_sprintf(test_name, "smp%d", i); + rt_thread_init(&smp[i], + test_name, + smp_test_entry, + RT_NULL, + &rt_thread_stack[i][0], + sizeof(rt_thread_stack[i]), + RT_THREAD_PRIORITY_MAX - 2, + 32); + rt_thread_control(&smp[i], RT_THREAD_CTRL_BIND_CPU, (void*)i); + /* startup */ + rt_thread_startup(&smp[i]); + rt_thread_delay(RT_TICK_PER_SECOND); + } +#endif +} + +#ifdef BSP_USING_PIN +#define TEST_PIN_OUT 33 +#define TEST_PIN_IN 37 + +void gpio_rising_test() +{ + rt_kprintf("gpio rising irq function ok!\n"); +} +#endif + +void test_gpio(void) +{ +#ifdef BSP_USING_PIN + rt_uint32_t ret; + rt_kprintf("Hello Test GPIO!\n"); + + rt_pin_mode(TEST_PIN_OUT, PIN_MODE_OUTPUT); + rt_pin_write(TEST_PIN_OUT, PIN_HIGH); + rt_pin_mode(TEST_PIN_IN, PIN_MODE_INPUT); + + ret = rt_pin_read(TEST_PIN_IN); + rt_kprintf("common high input test read result: %d\n",ret); + + rt_pin_write(TEST_PIN_OUT, PIN_LOW); + ret = rt_pin_read(TEST_PIN_IN); + rt_kprintf("common low input test read result: %d\n",ret); + + rt_pin_mode(TEST_PIN_IN, PIN_MODE_INPUT_PULLDOWN); + rt_pin_attach_irq(TEST_PIN_IN, PIN_IRQ_MODE_RISING, gpio_rising_test, RT_NULL); + rt_pin_irq_enable(TEST_PIN_IN, PIN_IRQ_ENABLE); + rt_pin_write(TEST_PIN_OUT, PIN_HIGH); + + rt_pin_irq_enable(TEST_PIN_IN, PIN_IRQ_DISABLE); +#endif +} + +#ifdef BSP_USING_I2C1 +#define DS3231_I2C_BUS_NAME "i2c1" +#define DS3231_ADDR 0x68 +struct rt_i2c_bus_device *i2c_bus = RT_NULL; +static rt_err_t read_regs(struct rt_i2c_bus_device *bus, rt_uint8_t len, rt_uint8_t *buf) +{ + struct rt_i2c_msg msgs; + msgs.addr = DS3231_ADDR; + msgs.flags = RT_I2C_RD; + msgs.buf = buf; + msgs.len = len; + + if (rt_i2c_transfer(bus, &msgs, 1) == 1) + return RT_EOK; + else + return -RT_ERROR; +} +#endif + +void test_i2c(void) +{ +#ifdef BSP_USING_I2C1 + rt_kprintf("Hello Test I2C!\n"); + char name[RT_NAME_MAX]; + rt_uint8_t buf[]={0x00,0x00,0x43,0x15,0x05,0x01,0x03,0x19}; + + rt_strncpy(name, DS3231_I2C_BUS_NAME, RT_NAME_MAX); + i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(name); + if (i2c_bus == RT_NULL) + rt_kprintf("can't find %s device!\n", name); + else + { + read_regs(i2c_bus, 7, buf); + buf[0] = buf[0]&0x7F; //sec + buf[1] = buf[1]&0x7F; //min + buf[2] = buf[2]&0x3F; //hour + buf[3] = buf[3]&0x07; //week + buf[4] = buf[4]&0x3F; //day + buf[5] = buf[5]&0x1F; //mouth + //year/month/day + rt_kprintf("20%02x-%02x-%02x ",buf[6],buf[5],buf[4]); + //hour:minute/second + rt_kprintf("%02x:%02x:%02x \n",buf[2],buf[1],buf[0]); + } +#endif +} + +#define W25Q_SPI_DEVICE_NAME "spi0.0" +void test_spi(void) +{ +#ifdef BSP_USING_SPI + rt_kprintf("Hello Test SPI!\n"); + struct rt_spi_device *spi0_dev0; + struct rt_spi_device *spi0_dev1; + + char name0[RT_NAME_MAX]; + char name1[RT_NAME_MAX]; + + rt_uint8_t w25x_read_id = 0x90; + rt_uint8_t id[5] = {0}; + + rt_strncpy(name0, "spi0.0", RT_NAME_MAX); + rt_strncpy(name1, "spi0.1", RT_NAME_MAX); + + spi0_dev0 = (struct rt_spi_device *)rt_device_find(name0); + spi0_dev1 = (struct rt_spi_device *)rt_device_find(name1); + + + if (!spi0_dev0 || !spi0_dev1) + { + rt_kprintf("spi sample run failed! can't find %s device!\n", name0); + } + else + { + struct rt_spi_message msg1, msg2; + + msg1.send_buf = &w25x_read_id; + msg1.recv_buf = RT_NULL; + msg1.length = 1; + msg1.cs_take = 1; + msg1.cs_release = 0; + msg1.next = &msg2; + + msg2.send_buf = RT_NULL; + msg2.recv_buf = id; + msg2.length = 5; + msg2.cs_take = 0; + msg2.cs_release = 1; + msg2.next = RT_NULL; + + rt_spi_transfer_message(spi0_dev0, &msg1); + rt_kprintf("use rt_spi_transfer_message() read w25q ID is:%x%x\n", id[3], id[4]); + + } +#endif +} + +#ifdef BSP_USING_SYSTIMER +#define TIMER "timer1" + +static rt_err_t timer_timeout_cb(rt_device_t dev, rt_size_t size) +{ + rt_kprintf("enter hardware timer isr\n"); + return 0; +} +#endif +rt_err_t test_hwtimer(void) +{ +#ifdef BSP_USING_SYSTIMER + rt_kprintf("Hello Test HW Timer!\n"); + rt_err_t err; + rt_hwtimerval_t val; + rt_device_t dev = RT_NULL; + rt_tick_t tick; + rt_hwtimer_mode_t mode; + int t = 5; + + if ((dev = rt_device_find(TIMER)) == RT_NULL) + { + rt_kprintf("No Device: %s\n", TIMER); + return -1; + } + + if (rt_device_open(dev, RT_DEVICE_OFLAG_RDWR) != RT_EOK) + { + rt_kprintf("Open %s Fail\n", TIMER); + return -1; + } + + mode = HWTIMER_MODE_PERIOD; + err = rt_device_control(dev, HWTIMER_CTRL_MODE_SET, &mode); + + tick = rt_tick_get(); + rt_kprintf("Start Timer> Tick: %d\n", tick); + + val.sec = t; + val.usec = 0; + rt_kprintf("SetTime: Sec %d, Usec %d\n", val.sec, val.usec); + if (rt_device_write(dev, 0, &val, sizeof(val)) != sizeof(val)) + { + rt_kprintf("SetTime Fail\n"); + goto EXIT; + } + rt_kprintf("Sleep %d sec\n", t); + rt_thread_delay(t*RT_TICK_PER_SECOND); + + err = rt_device_control(dev, HWTIMER_CTRL_STOP, RT_NULL); + rt_kprintf("Timer Stoped\n"); + + rt_device_read(dev, 0, &val, sizeof(val)); + rt_kprintf("Read: Sec = %d, Usec = %d\n", val.sec, val.usec); + + rt_device_set_rx_indicate(dev, timer_timeout_cb); + + mode = HWTIMER_MODE_PERIOD; + err = rt_device_control(dev, HWTIMER_CTRL_MODE_SET, &mode); + + val.sec = t; + val.usec = 0; + rt_kprintf("SetTime: Sec %d, Usec %d\n", val.sec, val.usec); + if (rt_device_write(dev, 0, &val, sizeof(val)) != sizeof(val)) + { + rt_kprintf("SetTime Fail\n"); + goto EXIT; + } + + rt_thread_delay((t *5 + 1)*RT_TICK_PER_SECOND); + +EXIT: + err = rt_device_close(dev); + rt_kprintf("Close %s\n", TIMER); + + return err; +#endif +} + +#ifdef RT_USING_WDT +#define WDT_DEVICE_NAME "wdg" /* 鐪嬮棬鐙楄澶囧悕绉� */ +static rt_device_t wdg_dev; /* 鐪嬮棬鐙楄澶囧彞鏌� */ +static void idle_hook(void) +{ + /* 鍦ㄧ┖闂茬嚎绋嬬殑鍥炶皟鍑芥暟閲屽杺鐙� */ + rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, NULL); + //rt_kprintf("feed the dog!\n "); +} + +rt_err_t test_wdt(void) +{ + rt_kprintf("Hello Test WDT!\n"); + rt_err_t ret = RT_EOK; + rt_uint32_t timeout = 1; /* 婧㈠嚭鏃堕棿锛屽崟浣嶏細绉� */ + char device_name[RT_NAME_MAX]; + rt_strncpy(device_name, WDT_DEVICE_NAME, RT_NAME_MAX); + /* 鏍规嵁璁惧鍚嶇О鏌ユ壘鐪嬮棬鐙楄澶囷紝鑾峰彇璁惧鍙ユ焺 */ + wdg_dev = rt_device_find(device_name); + if (!wdg_dev) + { + rt_kprintf("find %s failed!\n", device_name); + return RT_ERROR; + } + /* 鍒濆鍖栬澶� */ + ret = rt_device_init(wdg_dev); + if (ret != RT_EOK) + { + rt_kprintf("initialize %s failed!\n", device_name); + return RT_ERROR; + } + /* 璁剧疆鐪嬮棬鐙楁孩鍑烘椂闂� */ + ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_SET_TIMEOUT, &timeout); + if (ret != RT_EOK) + { + rt_kprintf("set %s timeout failed!\n", device_name); + return RT_ERROR; + } + /* 鍚姩鐪嬮棬鐙� */ + ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_START, RT_NULL); + if (ret != RT_EOK) + { + rt_kprintf("start %s failed!\n", device_name); + return -RT_ERROR; + } + /* 璁剧疆绌洪棽绾跨▼鍥炶皟鍑芥暟 */ + rt_thread_idle_sethook(idle_hook); + + return ret; + +} +#else +rt_err_t test_wdt(void) +{ + return RT_EOK; +} +#endif + +int test_rtc(void) +{ +#ifdef BSP_USING_RTC + rt_kprintf("Hello Test RTC!\n"); + uint8_t i; + time_t now; + + rt_err_t ret = RT_EOK; + + rt_kprintf("[RTC Test]RTC Test Start...\n"); + rt_thread_delay(RT_TICK_PER_SECOND); + rt_kprintf("[RTC Test]Set RTC 2017-04-01 12:30:46\n\n"); + rt_thread_delay(RT_TICK_PER_SECOND); + + ret = set_date(2017, 4, 1); + if (ret != RT_EOK) + { + rt_kprintf("[RTC Test]Set RTC Date failed\n"); + return RT_ERROR; + } + + rt_thread_delay(RT_TICK_PER_SECOND); + + ret = set_time(12, 30, 46); + if (ret != RT_EOK) + { + rt_kprintf("[RTC Test]Set RTC Time failed\n"); + return RT_ERROR; + } + + rt_thread_delay(RT_TICK_PER_SECOND); + + for (i = 0; i < 10; i++) + { + rt_kprintf("[RTC Test]Read RTC Date and Time: "); + now = time(RT_NULL); + rt_kprintf("%s", ctime(&now)); + + rt_thread_delay(RT_TICK_PER_SECOND); + } + + rt_kprintf("\n"); +#endif + return RT_EOK; +} + +void test_device(int argc, char**argv) +{ + if (0 == strcmp(argv[1],"smp")) + { + test_cpusmp(); + return; + } + if (0 == strcmp(argv[1],"gpio")) + { + test_gpio(); + return; + } + + if (0 == strcmp(argv[1],"i2c")) + { + test_i2c(); + return; + } + + if (0 == strcmp(argv[1],"spi")) + { + test_spi(); + return; + } + + if (0 == strcmp(argv[1],"hwtimer")) + { + test_hwtimer(); + return; + } + + if (0 == strcmp(argv[1],"wdt")) + { + test_wdt(); + return; + } + + if (0 == strcmp(argv[1],"rtc")) + { + test_rtc(); + return; + } + if (0 == strcmp(argv[1],"hdmi")) + { + test_hdmi(); + return; + } + rt_kprintf("param err, please entry test_device \n"); +} +MSH_CMD_EXPORT(test_device, sample: test_device ); diff --git a/bsp/raspberry-pi/raspi3-32/cpu/SConscript b/bsp/raspberry-pi/raspi3-32/cpu/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..eb4ee7a5850f0d1e2e90484aa547997c266be8eb --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/cpu/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/raspberry-pi/raspi3-32/cpu/armv7.h b/bsp/raspberry-pi/raspi3-32/cpu/armv7.h new file mode 100644 index 0000000000000000000000000000000000000000..859b0371b70c415645b8e9bafd76751284c54231 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/cpu/armv7.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + */ + +#ifndef __ARMV7_H__ +#define __ARMV7_H__ + +/* the exception stack without VFP registers */ +struct rt_hw_exp_stack +{ + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; +}; + +struct rt_hw_stack +{ + unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long lr; + unsigned long pc; +}; + +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define MONITORMODE 0x16 +#define ABORTMODE 0x17 +#define HYPMODE 0x1b +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#define T_Bit (1<<5) +#define F_Bit (1<<6) +#define I_Bit (1<<7) +#define A_Bit (1<<8) +#define E_Bit (1<<9) +#define J_Bit (1<<24) + +#endif diff --git a/bsp/raspberry-pi/raspi3-32/cpu/context_gcc.S b/bsp/raspberry-pi/raspi3-32/cpu/context_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..cb95558f7a892756b6f0e725fdf672fc7db957b5 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/cpu/context_gcc.S @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + * 2019-07-28 zdzn add smp support + */ + +#include "../rtconfig.h" +.section .text, "ax" + +#ifdef RT_USING_SMP +#define rt_hw_interrupt_disable rt_hw_local_irq_disable +#define rt_hw_interrupt_enable rt_hw_local_irq_enable +#endif + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mrs r0, cpsr + cpsid i + bx lr + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + msr cpsr, r0 + bx lr + +/* + * void rt_hw_context_switch_to(rt_uint32 to, struct rt_thread *to_thread); + * r0 --> to (thread stack) + * r1 --> to_thread + */ +.globl rt_hw_context_switch_to +rt_hw_context_switch_to: + ldr sp, [r0] @ get new task stack pointer + +#ifdef RT_USING_SMP + mov r0, r1 + bl rt_cpus_lock_status_restore +#endif /*RT_USING_SMP*/ + b rt_hw_context_switch_exit + +.section .bss.share.isr +_guest_switch_lvl: + .word 0 + +.globl vmm_virq_update + +.section .text.isr, "ax" +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to, struct rt_thread *to_thread); + * r0 --> from (from_thread stack) + * r1 --> to (to_thread stack) + * r2 --> to_thread + */ +.globl rt_hw_context_switch +rt_hw_context_switch: + stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) + stmfd sp!, {r0-r12, lr} @ push lr & register file + + mrs r4, cpsr + tst lr, #0x01 + orrne r4, r4, #0x20 @ it's thumb code + + stmfd sp!, {r4} @ push cpsr + +#ifdef RT_USING_LWP + stmfd sp, {r13, r14}^ @ push usr_sp usr_lr + sub sp, #8 +#endif +#ifdef RT_USING_FPU + /* fpu context */ + vmrs r6, fpexc + tst r6, #(1<<30) + beq 1f + vstmdb sp!, {d0-d15} + vstmdb sp!, {d16-d31} + vmrs r5, fpscr + stmfd sp!, {r5} +1: + stmfd sp!, {r6} +#endif + + str sp, [r0] @ store sp in preempted tasks TCB + ldr sp, [r1] @ get new task stack pointer + +#ifdef RT_USING_SMP + mov r0, r2 + bl rt_cpus_lock_status_restore +#endif /*RT_USING_SMP*/ + b rt_hw_context_switch_exit + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); + */ +.equ Mode_USR, 0x10 +.equ Mode_FIQ, 0x11 +.equ Mode_IRQ, 0x12 +.equ Mode_SVC, 0x13 +.equ Mode_ABT, 0x17 +.equ Mode_UND, 0x1B +.equ Mode_SYS, 0x1F + +.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled +.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled + +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread +.globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: +#ifdef RT_USING_SMP + /* r0 :svc_mod context + * r1 :addr of from_thread's sp + * r2 :addr of to_thread's sp + * r3 :to_thread's tcb + */ + + str r0, [r1] + + ldr sp, [r2] + mov r0, r3 + bl rt_cpus_lock_status_restore + + b rt_hw_context_switch_exit + +#else /*RT_USING_SMP*/ + ldr r2, =rt_thread_switch_interrupt_flag + ldr r3, [r2] + cmp r3, #1 + beq _reswitch + ldr ip, =rt_interrupt_from_thread @ set rt_interrupt_from_thread + mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 + str r0, [ip] + str r3, [r2] +_reswitch: + ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread + str r1, [r2] + bx lr +#endif /*RT_USING_SMP*/ + +.global rt_hw_context_switch_exit +rt_hw_context_switch_exit: + +#ifdef RT_USING_SMP +#ifdef RT_USING_SIGNALS + mov r0, sp + cps #Mode_IRQ + bl rt_signal_check + cps #Mode_SVC + mov sp, r0 +#endif +#endif +#ifdef RT_USING_FPU +/* fpu context */ + ldmfd sp!, {r6} + vmsr fpexc, r6 + tst r6, #(1<<30) + beq 1f + ldmfd sp!, {r5} + vmsr fpscr, r5 + vldmia sp!, {d16-d31} + vldmia sp!, {d0-d15} + +#endif + +#ifdef RT_USING_LWP + ldmfd sp, {r13, r14}^ /* usr_sp, usr_lr */ + add sp, #8 +#endif + ldmfd sp!, {r4} + msr spsr_cxsf, r4 /* original mode */ + ldmfd sp!, {r0-r12,lr,pc}^ /* irq return */ + diff --git a/bsp/raspberry-pi/raspi3-32/cpu/cp15.h b/bsp/raspberry-pi/raspi3-32/cpu/cp15.h new file mode 100644 index 0000000000000000000000000000000000000000..14b85b7e6466c5781322483c367f9d0ac13798db --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/cpu/cp15.h @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + */ +#include "raspi.h" +#ifndef __CP15_H__ +#define __CP15_H__ + +#ifndef __STATIC_FORCEINLINE +#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif + +#define __WFI() __asm__ volatile ("wfi":::"memory") + +#define __WFE() __asm__ volatile ("wfe":::"memory") + +#define __SEV() __asm__ volatile ("sev") + +__STATIC_FORCEINLINE void __ISB(void) +{ + __asm__ volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __asm__ volatile ("dsb 0xF":::"memory"); +} + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ + +__STATIC_FORCEINLINE void __DMB(void) +{ + __asm__ volatile ("dmb 0xF":::"memory"); +} + + +#ifdef RT_USING_SMP +static inline void send_ipi_msg(int cpu, int ipi_vector) +{ + IPI_MAILBOX_SET(cpu) = 1 << ipi_vector; +} + +static inline void setup_bootstrap_addr(int cpu, int addr) +{ + CORE_MAILBOX3_SET(cpu) = addr; +} + +static inline void enable_cpu_ipi_intr(int cpu) +{ + COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK; +} + +static inline void enable_cpu_timer_intr(int cpu) +{ + CORETIMER_INTCTL(cpu) = 0x8; +} + +static inline void enable_cntv(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 1; + asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL +} + +static inline void disable_cntv(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 0; + asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL +} + +static inline void mask_cntv(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 2; + asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL +} + +static inline void unmask_cntv(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 1; + asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL +} + +static inline rt_uint64_t read_cntvct(void) +{ + rt_uint32_t val,val1; + asm volatile ("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1)); + return (val); +} + +static inline rt_uint64_t read_cntvoff(void) +{ + + rt_uint64_t val; + asm volatile ("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val)); + return (val); +} + +static inline rt_uint32_t read_cntv_tval(void) +{ + rt_uint32_t val; + asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val)); + return val; +} + + +static inline void write_cntv_tval(rt_uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val)); + return; +} + +static inline rt_uint32_t read_cntfrq(void) +{ + rt_uint32_t val; + asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val)); + return val; +} + + +static inline rt_uint32_t read_cntctrl(void) +{ + rt_uint32_t val; + asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val)); + return val; +} + +static inline uint32_t write_cntctrl(uint32_t val) +{ + + asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val)); + return val; +} +#endif + +unsigned long rt_cpu_get_smp_id(void); + +void rt_cpu_mmu_disable(void); +void rt_cpu_mmu_enable(void); +void rt_cpu_tlb_set(volatile unsigned long*); + +void rt_cpu_dcache_clean_flush(void); +void rt_cpu_icache_flush(void); + +void rt_cpu_vector_set_base(unsigned int addr); +void rt_hw_mmu_init(void); +void rt_hw_vector_init(void); + +void set_timer_counter(unsigned int counter); +void set_timer_control(unsigned int control); +#endif diff --git a/bsp/raspberry-pi/raspi3-32/cpu/cp15_gcc.S b/bsp/raspberry-pi/raspi3-32/cpu/cp15_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..db2e6143ae7258ab7357d3909be42f47de2dd9c9 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/cpu/cp15_gcc.S @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.globl rt_cpu_get_smp_id +rt_cpu_get_smp_id: + mrc p15, #0, r0, c0, c0, #5 + bx lr + +.globl rt_cpu_vector_set_base +rt_cpu_vector_set_base: + /* clear SCTRL.V to customize the vector address */ + mrc p15, #0, r1, c1, c0, #0 + bic r1, #(1 << 13) + mcr p15, #0, r1, c1, c0, #0 + /* set up the vector address */ + mcr p15, #0, r0, c12, c0, #0 + dsb + bx lr + +.globl rt_hw_cpu_dcache_enable +rt_hw_cpu_dcache_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x00000004 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +.globl rt_hw_cpu_icache_enable +rt_hw_cpu_icache_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x00001000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +_FLD_MAX_WAY: + .word 0x3ff +_FLD_MAX_IDX: + .word 0x7ff + +.globl set_timer_counter +set_timer_counter: + mcr p15, #0, r0, c14, c3, #0 @ write virtual timer timerval register + bx lr +.globl set_timer_control +set_timer_control: + mcr p15, #0, r0, c14, c3, #1 @ write virtual timer control register + bx lr + +.globl rt_cpu_dcache_clean_flush +rt_cpu_dcache_clean_flush: + push {r4-r11} + dmb + mrc p15, #1, r0, c0, c0, #1 @ read clid register + ands r3, r0, #0x7000000 @ get level of coherency + mov r3, r3, lsr #23 + beq finished + mov r10, #0 +loop1: + add r2, r10, r10, lsr #1 + mov r1, r0, lsr r2 + and r1, r1, #7 + cmp r1, #2 + blt skip + mcr p15, #2, r10, c0, c0, #0 + isb + mrc p15, #1, r1, c0, c0, #0 + and r2, r1, #7 + add r2, r2, #4 + ldr r4, _FLD_MAX_WAY + ands r4, r4, r1, lsr #3 + clz r5, r4 + ldr r7, _FLD_MAX_IDX + ands r7, r7, r1, lsr #13 +loop2: + mov r9, r4 +loop3: + orr r11, r10, r9, lsl r5 + orr r11, r11, r7, lsl r2 + mcr p15, #0, r11, c7, c14, #2 + subs r9, r9, #1 + bge loop3 + subs r7, r7, #1 + bge loop2 +skip: + add r10, r10, #2 + cmp r3, r10 + bgt loop1 + +finished: + dsb + isb + pop {r4-r11} + bx lr + +.globl rt_cpu_icache_flush +rt_cpu_icache_flush: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate + dsb + isb + bx lr + +.globl rt_hw_cpu_dcache_disable +rt_hw_cpu_dcache_disable: + push {r4-r11, lr} + bl rt_cpu_dcache_clean_flush + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x00000004 + mcr p15, #0, r0, c1, c0, #0 + pop {r4-r11, lr} + bx lr + +.globl rt_hw_cpu_icache_disable +rt_hw_cpu_icache_disable: + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x00001000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +.globl rt_cpu_mmu_disable +rt_cpu_mmu_disable: + mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #1 + mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit + dsb + bx lr + +.globl rt_cpu_mmu_enable +rt_cpu_mmu_enable: + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x001 + mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit + dsb + bx lr + +.globl rt_cpu_tlb_set +rt_cpu_tlb_set: + mcr p15, #0, r0, c2, c0, #0 + dmb + bx lr diff --git a/bsp/raspberry-pi/raspi3-32/cpu/cpu.c b/bsp/raspberry-pi/raspi3-32/cpu/cpu.c new file mode 100644 index 0000000000000000000000000000000000000000..4d02ca35e184139c60a67578ed20f04e4a9e8dff --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/cpu/cpu.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + * 2019-07-28 zdzn add smp support + */ + +#include +#include +#include +#include "cp15.h" + +int rt_hw_cpu_id(void) +{ + int cpu_id; + __asm__ volatile ( + "mrc p15, 0, %0, c0, c0, 5" + :"=r"(cpu_id) + ); + cpu_id &= 0xf; + return cpu_id; +}; + + +#ifdef RT_USING_SMP +void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock) +{ + lock->slock = 0; +} + +void rt_hw_spin_lock(rt_hw_spinlock_t *lock) +{ + unsigned long tmp; + unsigned long newval; + rt_hw_spinlock_t lockval; + __asm__ __volatile__( + "pld [%0]" + ::"r"(&lock->slock) + ); + + __asm__ __volatile__( + "1: ldrex %0, [%3]\n" + " add %1, %0, %4\n" + " strex %2, %1, [%3]\n" + " teq %2, #0\n" + " bne 1b" + : "=&r" (lockval), "=&r" (newval), "=&r" (tmp) + : "r" (&lock->slock), "I" (1 << 16) + : "cc"); + + while (lockval.tickets.next != lockval.tickets.owner) + { + __WFE(); + lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner); + } + + __DMB(); +} + +void rt_hw_spin_unlock(rt_hw_spinlock_t *lock) +{ + __DMB(); + lock->tickets.owner++; + __DSB(); + __SEV(); +} +#endif /*RT_USING_SMP*/ + +/** + * @addtogroup ARM CPU + */ +/*@{*/ + +/** shutdown CPU */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +/*@}*/ diff --git a/bsp/raspberry-pi/raspi3-32/cpu/interrupt.c b/bsp/raspberry-pi/raspi3-32/cpu/interrupt.c new file mode 100644 index 0000000000000000000000000000000000000000..c9e7c17f8f495f1801116023b0361eff28bbe5fd --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/cpu/interrupt.c @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/5/3 Bernard first version + * 2019-07-28 zdzn add smp support + * 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues, + * write addr to mailbox3 to startup smp, and we use mailbox0 for ipi + */ + +#include +#include + +#include "cp15.h" +#include + +#define MAX_HANDLERS 72 + +#ifdef RT_USING_SMP +#define rt_interrupt_nest rt_cpu_self()->irq_nest +#else +extern volatile rt_uint8_t rt_interrupt_nest; +#endif + +const unsigned int VECTOR_BASE = 0x00; +extern void rt_cpu_vector_set_base(unsigned int addr); +extern int system_vectors; + +void rt_hw_vector_init(void) +{ + rt_cpu_vector_set_base((unsigned int)&system_vectors); +} + +/* exception and interrupt handler table */ +struct rt_irq_desc isr_table[MAX_HANDLERS]; + +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +extern int system_vectors; + +static void default_isr_handler(int vector, void *param) +{ +#ifdef RT_USING_SMP + rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector); +#else + rt_kprintf("unhandled irq: %d\n",vector); +#endif +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_uint32_t index; + + /* mask all of interrupts */ + IRQ_DISABLE_BASIC = 0x000000ff; + IRQ_DISABLE1 = 0xffffffff; + IRQ_DISABLE2 = 0xffffffff; + for (index = 0; index < MAX_HANDLERS; index ++) + { + isr_table[index].handler = default_isr_handler; + isr_table[index].param = NULL; +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX); + isr_table[index].counter = 0; +#endif + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + + if (vector < 32) + { + IRQ_DISABLE1 = (1 << vector); + } + else if (vector < 64) + { + vector = vector % 32; + IRQ_DISABLE2 = (1 << vector); + } + else + { + vector = vector - 64; + IRQ_DISABLE_BASIC = (1 << vector); + } +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + if (vector < 32) + { + IRQ_ENABLE1 = (1 << vector); + } + else if (vector < 64) + { + vector = vector % 32; + IRQ_ENABLE2 = (1 << vector); + } + else + { + vector = vector - 64; + IRQ_ENABLE_BASIC = (1 << vector); + } +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector < MAX_HANDLERS) + { + old_handler = isr_table[vector].handler; + + if (handler != RT_NULL) + { +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + } + + return old_handler; +} + +#ifdef RT_USING_SMP +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) +{ + __DSB(); + if (cpu_mask & 0x1) + { + send_ipi_msg(0, ipi_vector); + } + if (cpu_mask & 0x2) + { + send_ipi_msg(1, ipi_vector); + } + if (cpu_mask & 0x4) + { + send_ipi_msg(2, ipi_vector); + } + if (cpu_mask & 0x8) + { + send_ipi_msg(3, ipi_vector); + } + __DSB(); +} +#endif + +#ifdef RT_USING_SMP +void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler) +{ + /* note: ipi_vector maybe different with irq_vector */ + rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); +} +#endif diff --git a/bsp/raspberry-pi/raspi3-32/cpu/interrupt.h b/bsp/raspberry-pi/raspi3-32/cpu/interrupt.h new file mode 100644 index 0000000000000000000000000000000000000000..9aae0f556a0338f5b8afe5d2e2e1275da1012ac3 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/cpu/interrupt.h @@ -0,0 +1,18 @@ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include +#include + +#define INT_IRQ 0x00 +#define INT_FIQ 0x01 + +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); + +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +#endif diff --git a/bsp/raspberry-pi/raspi3-32/cpu/mmu.c b/bsp/raspberry-pi/raspi3-32/cpu/mmu.c new file mode 100644 index 0000000000000000000000000000000000000000..b3541d2ad431ebdd09399989f14f2ca48e06c450 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/cpu/mmu.c @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-01-10 bernard porting to AM1808 + * 2019-07-28 zdzn add smp support + */ + +#include "mmu.h" + +/* dump 2nd level page table */ +void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + for (i = 0; i < 256; i++) + { + rt_uint32_t pte2 = ptb[i]; + if ((pte2 & 0x3) == 0) + { + if (fcnt == 0) + rt_kprintf(" "); + rt_kprintf("%04x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf(" %04x: %x: ", i, pte2); + if ((pte2 & 0x3) == 0x1) + { + rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, + (pte2 >> 15) & 0x1, + ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); + } + else + { + rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1, + ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); + } + } +} + +void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + rt_kprintf("page table@%p\n", ptb); + for (i = 0; i < 1024*4; i++) + { + rt_uint32_t pte1 = ptb[i]; + if ((pte1 & 0x3) == 0) + { + rt_kprintf("%03x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf("%03x: %08x: ", i, pte1); + if ((pte1 & 0x3) == 0x3) + { + rt_kprintf("LPAE\n"); + } + else if ((pte1 & 0x3) == 0x1) + { + rt_kprintf("pte,ns:%d,domain:%d\n", + (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); + /* + *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) + * - 0x80000000 + 0xC0000000)); + */ + } + else if (pte1 & (1 << 18)) + { + rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); + } + else + { + rt_kprintf("section,ns:%d,ap:%x," + "xn:%d,texcb:%02x,domain:%d\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + (((pte1 & (0x7 << 12)) >> 10) | + ((pte1 & 0x0c) >> 2)) & 0x1f, + (pte1 >> 5) & 0xf); + } + } +} + +/* level1 page table, each entry for 1MB memory. */ +volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); +void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, + rt_uint32_t vaddrEnd, + rt_uint32_t paddrStart, + rt_uint32_t attr) +{ + volatile rt_uint32_t *pTT; + volatile int i, nSec; + pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20); + nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); + for (i = 0; i <= nSec; i++) + { + *pTT = attr | (((paddrStart >> 20) + i) << 20); + pTT++; + } +} + +unsigned long rt_hw_set_domain_register(unsigned long domain_val) +{ + unsigned long old_domain; + + asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); + asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); + + return old_domain; +} + +void rt_hw_init_mmu_table() +{ + /* set page table */ + /* 4G 1:1 memory */ + rt_hw_mmu_setmtt(0x00000000, 0x3effffff, 0x00000000, NORMAL_MEM); + /* IO memory region */ + rt_hw_mmu_setmtt(0x3f000000, 0x40010000, 0x3f000000, DEVICE_MEM); +} + +void rt_hw_change_mmu_table(rt_uint32_t vaddrStart, + rt_uint32_t size, + rt_uint32_t paddrStart, rt_uint32_t attr) +{ + rt_hw_mmu_setmtt(vaddrStart, vaddrStart+size-1, paddrStart, attr); +#ifndef RT_USING_SMP + rt_cpu_dcache_clean_flush(); + rt_cpu_icache_flush(); +#endif +} + + +void rt_hw_mmu_init(void) +{ + rt_cpu_dcache_clean_flush(); + rt_cpu_icache_flush(); + rt_hw_cpu_dcache_disable(); + rt_hw_cpu_icache_disable(); + rt_cpu_mmu_disable(); + + /*rt_hw_cpu_dump_page_table(MMUTable);*/ + rt_hw_set_domain_register(0x55555555); + + rt_cpu_tlb_set(MMUTable); + + rt_cpu_mmu_enable(); + + rt_hw_cpu_icache_enable(); + rt_hw_cpu_dcache_enable(); +} + diff --git a/bsp/raspberry-pi/raspi3-32/cpu/mmu.h b/bsp/raspberry-pi/raspi3-32/cpu/mmu.h new file mode 100644 index 0000000000000000000000000000000000000000..6b0c25e9907bda284f7f605a0f3586d2312b094a --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/cpu/mmu.h @@ -0,0 +1,51 @@ +#ifndef MMU_H__ +#define MMU_H__ +#include +#include +#include +#include "cp15.h" + +#define DESC_SEC (0x2) +#define CB (3 << 2) //cache_on, write_back +#define CNB (2 << 2) //cache_on, write_through +#define NCB (1 << 2) //cache_off,WR_BUF on +#define NCNB (0 << 2) //cache_off,WR_BUF off +#define AP_RW (3 << 10) //supervisor=RW, user=RW +#define AP_RO (2 << 10) //supervisor=RW, user=RO +#define XN (1 << 4) // eXecute Never +#define SHARED (1 << 16) /* shareable */ +#define SHAREDEVICE (1 << 2) /* shared device */ +#define STRONGORDER (0 << 2) /* strong ordered */ +#define MEMWBWA ((1 << 12) | (3 << 2)) /* write back, write allocate */ + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0 << 5) +#define DOMAIN1 (0x1 << 5) + +#define DOMAIN0_ATTR (DOMAIN_CHK << 0) +#define DOMAIN1_ATTR (DOMAIN_FAULT << 2) + +/* Read/Write, cache, write back */ +#define RW_CB (AP_RW | DOMAIN0 | CB | DESC_SEC) +/* Read/Write, cache, write through */ +#define RW_CNB (AP_RW | DOMAIN0 | CNB | DESC_SEC) +/* Read/Write without cache and write buffer */ +#define RW_NCNB (AP_RW | DOMAIN0 | NCNB | DESC_SEC) +/* Read/Write without cache and write buffer, no execute */ +#define RW_NCNBXN (AP_RW | DOMAIN0 | NCNB | DESC_SEC | XN) +/* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW | DOMAIN1 | NCNB | DESC_SEC) + +/* device mapping type */ +#define DEVICE_MEM (SHARED | SHAREDEVICE | RW_NCNBXN) +/* normal memory mapping type */ +#define NORMAL_MEM (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC) +#define STRONG_ORDER_MEM (SHARED | AP_RO | XN | DESC_SEC) +#define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000) + +void rt_hw_change_mmu_table(rt_uint32_t vaddrStart, + rt_uint32_t size, + rt_uint32_t paddrStart, rt_uint32_t attr); +#endif diff --git a/bsp/raspberry-pi/raspi3-32/cpu/stack.c b/bsp/raspberry-pi/raspi3-32/cpu/stack.c new file mode 100644 index 0000000000000000000000000000000000000000..c2c60fbf49de71ee23ca7e58d3ff18b907176e83 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/cpu/stack.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-23 Bernard the first version + * 2011-10-05 Bernard add thumb mode + */ +#include +#include +#include + +/** + * @addtogroup AM33xx + */ +/*@{*/ + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + + stack_addr += sizeof(rt_uint32_t); + stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); + stk = (rt_uint32_t *)stack_addr; + *(--stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0xdeadbeef; /* r12 */ + *(--stk) = 0xdeadbeef; /* r11 */ + *(--stk) = 0xdeadbeef; /* r10 */ + *(--stk) = 0xdeadbeef; /* r9 */ + *(--stk) = 0xdeadbeef; /* r8 */ + *(--stk) = 0xdeadbeef; /* r7 */ + *(--stk) = 0xdeadbeef; /* r6 */ + *(--stk) = 0xdeadbeef; /* r5 */ + *(--stk) = 0xdeadbeef; /* r4 */ + *(--stk) = 0xdeadbeef; /* r3 */ + *(--stk) = 0xdeadbeef; /* r2 */ + *(--stk) = 0xdeadbeef; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ + +#ifdef RT_USING_LWP + *(--stk) = 0; /* user lr */ + *(--stk) = 0; /* user sp*/ +#endif +#ifdef RT_USING_FPU + *(--stk) = 0; /* not use fpu*/ +#endif + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/bsp/raspberry-pi/raspi3-32/cpu/start_gcc.S b/bsp/raspberry-pi/raspi3-32/cpu/start_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..ec74213f0738dcdab62aaad3d6715c00aeb6382e --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/cpu/start_gcc.S @@ -0,0 +1,459 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + * 2019-07-28 zdzn add smp support + */ + +#include "../rtconfig.h" +.equ Mode_USR, 0x10 +.equ Mode_FIQ, 0x11 +.equ Mode_IRQ, 0x12 +.equ Mode_SVC, 0x13 +.equ Mode_ABT, 0x17 +.equ Mode_UND, 0x1B +.equ Mode_SYS, 0x1F + +.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled +.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled + +#ifdef RT_USING_FPU +.equ UND_Stack_Size, 0x00000400 +#else +.equ UND_Stack_Size, 0x00000000 +#endif +.equ SVC_Stack_Size, 0x00000400 +.equ ABT_Stack_Size, 0x00000000 +.equ RT_FIQ_STACK_PGSZ, 0x00000000 +.equ RT_IRQ_STACK_PGSZ, 0x00000800 +.equ USR_Stack_Size, 0x00000400 + +#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ) + +.section .data.share.isr +/* stack */ + +#ifdef RT_USING_SMP +.globl stack_start0 +.globl stack_top0 +.globl stack_start1 +.globl stack_top1 +.globl stack_start2 +.globl stack_top2 +.globl stack_start3 +.globl stack_top3 +stack_start0: +.rept ISR_Stack_Size +.byte 0 +.endr +stack_top0: + +stack_start1: +.rept ISR_Stack_Size +.byte 0 +.endr +stack_top1: + +stack_start2: +.rept ISR_Stack_Size +.byte 0 +.endr +stack_top2: + +stack_start3: +.rept ISR_Stack_Size +.byte 0 +.endr +stack_top3: + +.globl boot_indicate +boot_indicate: +.rept 16 +.byte 0 +.endr + +#else +.globl stack_start +.globl stack_top +stack_start: +.rept ISR_Stack_Size +.byte 0 +.endr +stack_top: +#endif + + +.text +/* reset entry */ +.globl _reset +_reset: + + /* Disable IRQ & FIQ */ + cpsid if + + /* Check for HYP mode */ + mrs r0, cpsr_all + and r0, r0, #0x1F + mov r8, #0x1A + cmp r0, r8 + beq overHyped + b continue + +overHyped: /* Get out of HYP mode */ + ldr r1, =continue + msr ELR_hyp, r1 + mrs r1, cpsr_all + and r1, r1, #0x1f ;@ CPSR_MODE_MASK + orr r1, r1, #0x13 ;@ CPSR_MODE_SUPERVISOR + msr SPSR_hyp, r1 + eret + +continue: + + /* disable mmu */ + bl rt_cpu_mmu_disable + /* set the cpu to SVC32 mode and disable interrupt */ + mrs r0, cpsr + bic r0, r0, #0x1f + orr r0, r0, #0x13 + msr cpsr_c, r0 +#ifdef RT_USING_SMP + mrc p15, 0, r0, c0, c0, 5 + ubfx r0, r0, #0, #2 + cmp r0, #0 + beq 1f + /* write boot indicate */ + ldr r5, = boot_indicate + str r0, [r5, r0, lsl #2] + bl secondary_cpu_start + b . +1: +#endif + /* setup stack */ +#ifdef RT_USING_SMP + ldr r0, =stack_top0 +#else + ldr r0, =stack_top +#endif + bl stack_setup + + /* clear .bss */ + mov r0,#0 /* get a zero */ + ldr r1,=__bss_start /* bss start */ + ldr r2,=__bss_end /* bss end */ + +bss_loop: + cmp r1,r2 /* check if data to clear */ + strlo r0,[r1],#4 /* clear 4 bytes */ + blo bss_loop /* loop until done */ + bl rt_hw_init_mmu_table + bl init_mbox_mmu_map + bl rt_hw_mmu_init + + /* start RT-Thread Kernel */ + ldr pc, _rtthread_startup +_rtthread_startup: + .word rtthread_startup + +stack_setup: + + @ Set the startup stack for svc + mov sp, r0 + + @ Enter Undefined Instruction Mode and set its Stack Pointer + msr cpsr_c, #Mode_UND|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #UND_Stack_Size + + @ Enter Abort Mode and set its Stack Pointer + msr cpsr_c, #Mode_ABT|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #ABT_Stack_Size + + @ Enter FIQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #RT_FIQ_STACK_PGSZ + + @ Enter IRQ Mode and set its Stack Pointer + msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit + mov sp, r0 + sub r0, r0, #RT_IRQ_STACK_PGSZ + + /* come back to SVC mode */ + msr cpsr_c, #Mode_SVC|I_Bit|F_Bit + bx lr + +.text + +/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ +.section .text.isr, "ax" + .align 5 +.globl vector_fiq +vector_fiq: + stmfd sp!,{r0-r7,lr} + bl rt_hw_trap_fiq + ldmfd sp!,{r0-r7,lr} + subs pc, lr, #4 + +.globl rt_interrupt_enter +.globl rt_interrupt_leave +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread + +.globl rt_current_thread +.globl vmm_thread +.globl vmm_virq_check + + .align 5 +.globl vector_irq +vector_irq: +#ifdef RT_USING_SMP + clrex + + stmfd sp!, {r0, r1} + cps #Mode_SVC + mov r0, sp /* svc_sp */ + mov r1, lr /* svc_lr */ + + cps #Mode_IRQ + sub lr, lr, #4 + stmfd r0!, {r1, lr} /* svc_lr, svc_pc */ + stmfd r0!, {r2 - r12} + ldmfd sp!, {r1, r2} /* original r0, r1 */ + stmfd r0!, {r1 - r2} + mrs r1, spsr /* original mode */ + stmfd r0!, {r1} + +#ifdef RT_USING_LWP + stmfd r0, {r13, r14}^ /* usr_sp, usr_lr */ + sub r0, #8 +#endif +#ifdef RT_USING_FPU + /* fpu context */ + vmrs r6, fpexc + tst r6, #(1<<30) + beq 1f + vstmdb r0!, {d0-d15} + vstmdb r0!, {d16-d31} + vmrs r5, fpscr + stmfd r0!, {r5} +1: + stmfd r0!, {r6} +#endif + mov r8, r0 + + bl rt_interrupt_enter + bl rt_hw_trap_irq + bl rt_interrupt_leave + + cps #Mode_SVC + mov sp, r8 + mov r0, r8 + + bl rt_scheduler_do_irq_switch + + b rt_hw_context_switch_exit + +#else + stmfd sp!, {r0-r12,lr} + + bl rt_interrupt_enter + bl rt_hw_trap_irq + bl rt_interrupt_leave + + @ if rt_thread_switch_interrupt_flag set, jump to + @ rt_hw_context_switch_interrupt_do and don't return + ldr r0, =rt_thread_switch_interrupt_flag + ldr r1, [r0] + cmp r1, #1 + beq rt_hw_context_switch_interrupt_do + + ldmfd sp!, {r0-r12,lr} + subs pc, lr, #4 + +rt_hw_context_switch_interrupt_do: + mov r1, #0 @ clear flag + str r1, [r0] + + mov r1, sp @ r1 point to {r0-r3} in stack + add sp, sp, #4*4 + ldmfd sp!, {r4-r12,lr}@ reload saved registers + mrs r0, spsr @ get cpsr of interrupt thread + sub r2, lr, #4 @ save old task's pc to r2 + + @ Switch to SVC mode with no interrupt. If the usr mode guest is + @ interrupted, this will just switch to the stack of kernel space. + @ save the registers in kernel space won't trigger data abort. + msr cpsr_c, #I_Bit|F_Bit|Mode_SVC + + stmfd sp!, {r2} @ push old task's pc + stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 + ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread + stmfd sp!, {r1-r4} @ push old task's r0-r3 + stmfd sp!, {r0} @ push old task's cpsr + +#ifdef RT_USING_LWP + stmfd sp, {r13, r14}^ @push usr_sp, usr_lr + sub sp, #8 +#endif +#ifdef RT_USING_FPU + /* fpu context */ + vmrs r6, fpexc + tst r6, #(1<<30) + beq 1f + vstmdb sp!, {d0-d15} + vstmdb sp!, {d16-d31} + vmrs r5, fpscr + stmfd sp!, {r5} +1: + stmfd sp!, {r6} +#endif + + ldr r4, =rt_interrupt_from_thread + ldr r5, [r4] + str sp, [r5] @ store sp in preempted tasks's TCB + + ldr r6, =rt_interrupt_to_thread + ldr r6, [r6] + ldr sp, [r6] @ get new task's stack pointer + +#ifdef RT_USING_FPU +/* fpu context */ + ldmfd sp!, {r6} + vmsr fpexc, r6 + tst r6, #(1<<30) + beq 1f + ldmfd sp!, {r5} + vmsr fpscr, r5 + vldmia sp!, {d16-d31} + vldmia sp!, {d0-d15} +1: +#endif + +#ifdef RT_USING_LWP + ldmfd sp, {r13, r14}^ @pop usr_sp, usr_lr + add sp, #8 +#endif + + ldmfd sp!, {r4} @ pop new task's cpsr to spsr + msr spsr_cxsf, r4 + + ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr + +#endif + +.macro push_svc_reg + sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ + stmia sp, {r0 - r12} @/* Calling r0-r12 */ + mov r0, sp + mrs r6, spsr @/* Save CPSR */ + str lr, [r0, #15*4] @/* Push PC */ + str r6, [r0, #16*4] @/* Push CPSR */ + cps #Mode_SVC + str sp, [r0, #13*4] @/* Save calling SP */ + str lr, [r0, #14*4] @/* Save calling PC */ +.endm + + .align 5 + .globl vector_swi +vector_swi: + push_svc_reg + bl rt_hw_trap_swi + b . + + .align 5 + .globl vector_undef +vector_undef: + push_svc_reg + cps #Mode_UND + bl rt_hw_trap_undef +#ifdef RT_USING_FPU + ldr lr, [sp, #15*4] + ldmia sp, {r0 - r12} + add sp, sp, #17 * 4 + movs pc, lr +#endif + b . + + .align 5 + .globl vector_pabt +vector_pabt: + push_svc_reg + bl rt_hw_trap_pabt + b . + + .align 5 + .globl vector_dabt +vector_dabt: + push_svc_reg + bl rt_hw_trap_dabt + b . + + .align 5 + .globl vector_resv +vector_resv: + push_svc_reg + bl rt_hw_trap_resv + b . + +#ifdef RT_USING_SMP + +.global secondary_cpu_start +secondary_cpu_start: + /* set vector base */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, #(1<<13) + mcr p15, 0, r0, c1, c0, 0 + + /* setup stack */ + mrc p15, 0, r0, c0, c0, 5 + ubfx r0, r0, #0, #2 + ldr r1, =stack_top0 + ldr r2, =ISR_Stack_Size + mul r3, r2, r0 + add r0, r1, r3 + bl stack_setup + /* initialize the mmu table and enable mmu */ + bl rt_hw_mmu_init + b secondary_cpu_c_start + +#endif + +;@ void arm_smp_enable(void); +.globl arm_smp_enable +arm_smp_enable: + mrc p15, 0, r0, c1, c0, 1 ;@ set SMP bit in ACTLR + orr r0, r0, #0x40 + mcr p15, 0, r0, c1, c0, 1 + bx lr +/* + mrrc p15, 1, r0, r1, c15 + orr r0, r0, #0x40 + mcrr p15, 1, r0, r1, c15 + dsb + isb + bx lr +*/ +.text +;@ void arm_smp_disable(void); +.globl arm_smp_disable + +arm_smp_disable: + mrc p15, 0, r0, c1, c0, 1 ;@ clear SMP bit in ACTLR + bic r0, r0, #0x40 + mcr p15, 0, r0, c1, c0, 1 + bx lr +/* + mrrc p15, 1, r0, r1, c15 + bic r0, r0, #0x40 + mcrr p15, 1, r0, r1, c15 + bx lr +*/ + diff --git a/bsp/raspberry-pi/raspi3-32/cpu/trap.c b/bsp/raspberry-pi/raspi3-32/cpu/trap.c new file mode 100644 index 0000000000000000000000000000000000000000..f83f1836952da85d22a69694e8440f8d4abd6f58 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/cpu/trap.c @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + * 2019-07-28 zdzn add smp support + * 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues, + * write addr to mailbox3 to startup smp, and we use mailbox0 for ipi + */ + +#include +#include +#include + +#include "armv7.h" + +extern struct rt_thread *rt_current_thread; +#ifdef RT_USING_FINSH +extern long list_thread(void); +#endif + + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void rt_hw_show_register(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); +} + + +/** + * When comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("undefined instruction:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * The software interrupt instruction (SWI) is used for entering + * Supervisor mode, usually to request a particular supervisor + * function. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("software interrupt:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during an instruction prefetch. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("prefetch abort:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * An abort indicates that the current memory access cannot be completed, + * which occurs during a data access. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("data abort:"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +/** + * Normally, system will never reach here + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("reserved trap:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +void rt_hw_trap_irq(void) +{ + void *param; + uint32_t irq; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + uint32_t value = 0; + value = IRQ_PEND_BASIC & 0x3ff; +#ifdef RT_USING_SMP + uint32_t mailbox_data; + uint32_t cpu_id = rt_hw_cpu_id(); + uint32_t int_source = CORE_IRQSOURCE(cpu_id); + mailbox_data = IPI_MAILBOX_CLEAR(cpu_id); + if (int_source & 0x0f) + { + if (int_source & 0x08) + { + isr_func = isr_table[IRQ_ARM_TIMER].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[IRQ_ARM_TIMER].counter++; +#endif + if (isr_func) + { + param = isr_table[IRQ_ARM_TIMER].param; + isr_func(IRQ_ARM_TIMER, param); + } + } + } + if (int_source & 0xf0) + { + /*it's a ipi interrupt*/ + if (mailbox_data & 0x1) + { + /* clear mailbox */ + IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data; + isr_func = isr_table[IRQ_ARM_MAILBOX].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[IRQ_ARM_MAILBOX].counter++; +#endif + if (isr_func) + { + param = isr_table[IRQ_ARM_MAILBOX].param; + isr_func(IRQ_ARM_MAILBOX, param); + } + } + else + CORE_MAILBOX3_CLEAR(cpu_id) = mailbox_data; + } +#endif + /* local interrupt*/ + if (value) + { + if (value & (1 << 8)) + { + value = IRQ_PEND1; + irq = __rt_ffs(value) - 1; + } + else if (value & (1 << 9)) + { + value = IRQ_PEND2; + irq = __rt_ffs(value) + 31; + } + else + { + value &= 0x0f; + irq = __rt_ffs(value) + 63; + } + + /* get interrupt service routine */ + isr_func = isr_table[irq].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[irq].counter++; +#endif + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[irq].param; + /* turn to interrupt service routine */ + isr_func(irq, param); + } + } +} + +void rt_hw_trap_fiq(void) +{ + +} diff --git a/bsp/raspberry-pi/raspi3-32/cpu/vector_gcc.S b/bsp/raspberry-pi/raspi3-32/cpu/vector_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..eebfe9c13baeab4f4a739db433850658caf6934c --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/cpu/vector_gcc.S @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-05 Bernard the first version + */ + +.section .vectors, "ax" +.code 32 + +.globl system_vectors +system_vectors: + ldr pc, _vector_reset + ldr pc, _vector_undef + ldr pc, _vector_swi + ldr pc, _vector_pabt + ldr pc, _vector_dabt + ldr pc, _vector_resv + ldr pc, _vector_irq + ldr pc, _vector_fiq + +.globl _reset +.globl vector_undef +.globl vector_swi +.globl vector_pabt +.globl vector_dabt +.globl vector_resv +.globl vector_irq +.globl vector_fiq + +_vector_reset: + .word _reset +_vector_undef: + .word vector_undef +_vector_swi: + .word vector_swi +_vector_pabt: + .word vector_pabt +_vector_dabt: + .word vector_dabt +_vector_resv: + .word vector_resv +_vector_irq: + .word vector_irq +_vector_fiq: + .word vector_fiq + +.balignl 16,0xdeadbeef diff --git a/bsp/raspberry-pi/raspi3-32/driver/Kconfig b/bsp/raspberry-pi/raspi3-32/driver/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..aaa7110f1dc3251a17127c65c3a13974c87164ea --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/Kconfig @@ -0,0 +1,103 @@ +menu "Hardware Drivers Config" + menu "BCM Peripheral Drivers" + menuconfig BSP_USING_UART + bool "Using UART" + select RT_USING_SERIAL + default y + + if BSP_USING_UART + config RT_USING_UART0 + bool "Enabel UART 0" + default y + + config RT_USING_UART1 + bool "Enabel UART 1" + default n + endif + + config BSP_USING_PIN + bool "Using PIN" + select RT_USING_PIN + default y + + menuconfig BSP_USING_SYSTIMER + bool "Enable SYSTIMER" + select RT_USING_HWTIMER + default n + + if BSP_USING_SYSTIMER + config RT_USING_SYSTIMER1 + bool "Enable sys timer1" + default n + config RT_USING_SYSTIMER3 + bool "Enable sys timer3" + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C" + select RT_USING_I2C + default n + + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default n + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI" + select RT_USING_SPI + default n + + if BSP_USING_SPI + config BSP_USING_SPI0_BUS + bool "Enable SPI0 BUS" + default n + config BSP_USING_SPI0_DEVICE0 + bool "Enable SPI0 DEVICE0" + select BSP_USING_SPI0_BUS + default n + config BSP_USING_SPI0_DEVICE1 + bool "Enable SPI0 DEVICE1" + select BSP_USING_SPI0_BUS + default n + endif + + config BSP_USING_WDT + bool "Enable WDT" + select RT_USING_WDT + default n + + menuconfig BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + + if BSP_USING_RTC + config BSP_USING_ALARM + bool "Enable Alarm" + select RT_USING_ALARM + default n + endif + + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + default n + + if BSP_USING_SDIO + config BSP_USING_SDIO0 + bool "Enable SDIO0" + select RT_USING_SDIO + default n + endif + menuconfig BSP_USING_HDMI + bool "Enable HDMI" + select BSP_USING_SPI + default n + endmenu +endmenu diff --git a/bsp/raspberry-pi/raspi3-32/driver/SConscript b/bsp/raspberry-pi/raspi3-32/driver/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..c51b2c42bf9c9b0e3c684d59c24ef7d2500c6971 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/SConscript @@ -0,0 +1,31 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Split(''' +board.c +drv_uart.c +mbox.c +''') +CPPPATH = [cwd] + +if GetDepend('BSP_USING_SYSTIMER'): + src += ['drv_timer.c'] +if GetDepend('BSP_USING_PIN'): + src += ['drv_gpio.c'] +if GetDepend('BSP_USING_I2C'): + src += ['drv_i2c.c'] +if GetDepend('BSP_USING_WDT'): + src += ['drv_wdt.c'] +if GetDepend('BSP_USING_SPI'): + src += ['drv_spi.c'] +if GetDepend('BSP_USING_SDIO'): + src += ['drv_sdio.c'] +if GetDepend('BSP_USING_RTC'): + src += ['drv_rtc.c'] +if GetDepend('BSP_USING_HDMI'): + src += ['drv_fb.c'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/raspberry-pi/raspi3-32/driver/board.c b/bsp/raspberry-pi/raspi3-32/driver/board.c new file mode 100644 index 0000000000000000000000000000000000000000..a1b3d603c82c9010fd8bbaa64890eb5edac57912 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/board.c @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#include +#include + +#include "board.h" +#include "drv_uart.h" +#include "drv_timer.h" + +#include "cp15.h" + +#ifdef RT_USING_SMP +unsigned int cntfrq; +#endif + +void rt_hw_timer_isr(int vector, void *parameter) +{ + rt_tick_increase(); +#ifndef RT_USING_SMP + ARM_TIMER_IRQCLR = 0; +#else + mask_cntv(); + __DSB(); + write_cntv_tval(cntfrq); + __DSB(); + unmask_cntv(); + __DSB(); +#endif +} + +int rt_hw_timer_init() +{ +#ifndef RT_USING_SMP + /* timer_clock = apb_clock/(pre_divider + 1) */ + ARM_TIMER_PREDIV = (250 - 1); + + ARM_TIMER_RELOAD = 0; + ARM_TIMER_LOAD = 0; + ARM_TIMER_IRQCLR = 0; + ARM_TIMER_CTRL = 0; + + ARM_TIMER_RELOAD = 10000; + ARM_TIMER_LOAD = 10000; + + /* 23-bit counter, enable interrupt, enable timer */ + ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7); +#else + __DSB(); + cntfrq = 35000; + write_cntv_tval(cntfrq); + enable_cntv(); + __DSB(); + enable_cpu_timer_intr(rt_hw_cpu_id()); +#endif + + rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(IRQ_ARM_TIMER); + return 0; +} +#ifdef RT_USING_SMP +extern void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler); + +void ipi_handler() +{ + rt_scheduler_ipi_handler(0,RT_NULL); +} +#endif +void vector_copy(void) +{ + rt_memcpy((void*)0x0, (void*)0x8000, 64); +} + +void idle_wfi(void) +{ + asm volatile ("wfi"); +} + +void rt_hw_board_init(void) +{ + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); + vector_copy(); + rt_hw_vector_init(); + /* initialize uart */ + rt_hw_uart_init(); + /* initialize timer for os tick */ + rt_hw_timer_init(); + rt_thread_idle_sethook(idle_wfi); +#ifdef RT_USING_CONSOLE + /* set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif /* RT_USING_CONSOLE */ +#ifdef RT_USING_HEAP + /* initialize memory system */ + rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); +#endif + +#ifdef RT_USING_SMP + /* install IPI handle */ + rt_hw_ipi_handler_install(IRQ_ARM_MAILBOX, ipi_handler); + rt_hw_interrupt_umask(IRQ_ARM_MAILBOX); + enable_cpu_ipi_intr(0); +#endif +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +} + + +void _reset(void); +void secondary_cpu_start(void); + +#ifdef RT_USING_SMP +void rt_hw_secondary_cpu_up(void) +{ + int i; + int retry,val; + rt_cpu_dcache_clean_flush(); + rt_cpu_icache_flush(); + /*TODO maybe, there is some bug */ + for (i = RT_CPUS_NR - 1; i>0; i-- ) + { + rt_kprintf("boot cpu:%d\n", i); + setup_bootstrap_addr(i, (int)_reset); + __SEV(); + __DSB(); + __ISB(); + retry = 10; + rt_thread_delay(RT_TICK_PER_SECOND/1000); + do + { + val = CORE_MAILBOX3_CLEAR(i); + if (val == 0) + { + rt_kprintf("start OK: CPU %d \n",i); + break; + } + rt_thread_delay(RT_TICK_PER_SECOND); + + retry --; + if (retry <= 0) + { + rt_kprintf("can't start for CPU %d \n",i); + break; + } + } while (1); + } + __DSB(); + __SEV(); +} + +void secondary_cpu_c_start(void) +{ + uint32_t id; + id = rt_hw_cpu_id(); + rt_kprintf("cpu = 0x%08x\n",id); + rt_hw_timer_init(); + rt_kprintf("cpu %d startup.\n",id); + rt_hw_vector_init(); + enable_cpu_ipi_intr(id); + rt_hw_spin_lock(&_cpus_lock); + rt_system_scheduler_start(); +} + +void rt_hw_secondary_cpu_idle_exec(void) +{ + __WFE(); +} + +#endif + + diff --git a/bsp/raspberry-pi/raspi3-32/driver/board.h b/bsp/raspberry-pi/raspi3-32/driver/board.h new file mode 100644 index 0000000000000000000000000000000000000000..8736027c0625e947c565e89efcb3139beaa671f4 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/board.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-5-30 Bernard the first version + */ + +#ifndef BOARD_H__ +#define BOARD_H__ + +#include + +#include +#include "raspi.h" + +#define __REG32 HWREG32 +extern unsigned char __bss_start; +extern unsigned char __bss_end; + +#define RT_HW_HEAP_BEGIN (void*)&__bss_end +#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 4 * 1024 * 1024) + +void rt_hw_board_init(void); + +#endif + diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_fb.c b/bsp/raspberry-pi/raspi3-32/driver/drv_fb.c new file mode 100644 index 0000000000000000000000000000000000000000..f15fa12fb4515ccc61c48ec78e3b8a47b7aa36e3 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_fb.c @@ -0,0 +1,509 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-08-29 zdzn first version + */ + +#include +#include +#include "mbox.h" +#include "drv_fb.h" +#include "mmu.h" + +#define CHAR_W 8 +#define CHAR_H 12 + +#define COLOR_DELTA 0.05 +static struct rt_hdmi_fb_device _hdmi; + +// https://github.com/xinu-os/xinu/blob/1789b7a50b5b73c2ea76ebd764c54a034097d04d/device/framebuffer_rpi/font.c +unsigned char FONT[] = { +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, /*'!'*/ +0x00, 0x14, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'"'*/ +0x00, 0x00, 0x14, 0x14, 0x3e, 0x14, 0x3e, 0x14, 0x14, 0x00, 0x00, 0x00, /*'#'*/ +0x00, 0x00, 0x08, 0x3c, 0x0a, 0x1c, 0x28, 0x1e, 0x08, 0x00, 0x00, 0x00, /*'$'*/ +0x00, 0x00, 0x06, 0x26, 0x10, 0x08, 0x04, 0x32, 0x30, 0x00, 0x00, 0x00, /*'%'*/ +0x00, 0x00, 0x1c, 0x02, 0x02, 0x04, 0x2a, 0x12, 0x2c, 0x00, 0x00, 0x00, /*'&'*/ +0x00, 0x18, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'''*/ +0x20, 0x10, 0x10, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10, 0x20, 0x00, /*'('*/ +0x02, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, 0x02, 0x00, /*')'*/ +0x00, 0x00, 0x00, 0x08, 0x2a, 0x1c, 0x2a, 0x08, 0x00, 0x00, 0x00, 0x00, /*'*'*/ +0x00, 0x00, 0x00, 0x08, 0x08, 0x3e, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, /*'+'*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x08, 0x04, 0x00, /*','*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'-'*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, /*'.'*/ +0x20, 0x20, 0x10, 0x10, 0x08, 0x08, 0x04, 0x04, 0x02, 0x02, 0x00, 0x00, /*'/'*/ +0x00, 0x1c, 0x22, 0x32, 0x2a, 0x26, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'0'*/ +0x00, 0x08, 0x0c, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, /*'1'*/ +0x00, 0x1c, 0x22, 0x20, 0x10, 0x08, 0x04, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'2'*/ +0x00, 0x1c, 0x22, 0x20, 0x18, 0x20, 0x20, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'3'*/ +0x00, 0x10, 0x18, 0x18, 0x14, 0x14, 0x3e, 0x10, 0x38, 0x00, 0x00, 0x00, /*'4'*/ +0x00, 0x3e, 0x02, 0x02, 0x1e, 0x20, 0x20, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'5'*/ +0x00, 0x18, 0x04, 0x02, 0x1e, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'6'*/ +0x00, 0x3e, 0x22, 0x20, 0x20, 0x10, 0x10, 0x08, 0x08, 0x00, 0x00, 0x00, /*'7'*/ +0x00, 0x1c, 0x22, 0x22, 0x1c, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'8'*/ +0x00, 0x1c, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x10, 0x0c, 0x00, 0x00, 0x00, /*'9'*/ +0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, /*':'*/ +0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x18, 0x18, 0x08, 0x04, 0x00, /*';'*/ +0x00, 0x00, 0x00, 0x30, 0x0c, 0x03, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, /*'<'*/ +0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, /*'='*/ +0x00, 0x00, 0x00, 0x03, 0x0c, 0x30, 0x0c, 0x03, 0x00, 0x00, 0x00, 0x00, /*'>'*/ +0x00, 0x1c, 0x22, 0x20, 0x10, 0x08, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, /*'?'*/ +0x00, 0x00, 0x1c, 0x22, 0x3a, 0x3a, 0x1a, 0x02, 0x1c, 0x00, 0x00, 0x00, /*'@'*/ +0x00, 0x00, 0x08, 0x14, 0x22, 0x22, 0x3e, 0x22, 0x22, 0x00, 0x00, 0x00, /*'A'*/ +0x00, 0x00, 0x1e, 0x22, 0x22, 0x1e, 0x22, 0x22, 0x1e, 0x00, 0x00, 0x00, /*'B'*/ +0x00, 0x00, 0x1c, 0x22, 0x02, 0x02, 0x02, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'C'*/ +0x00, 0x00, 0x0e, 0x12, 0x22, 0x22, 0x22, 0x12, 0x0e, 0x00, 0x00, 0x00, /*'D'*/ +0x00, 0x00, 0x3e, 0x02, 0x02, 0x1e, 0x02, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'E'*/ +0x00, 0x00, 0x3e, 0x02, 0x02, 0x1e, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, /*'F'*/ +0x00, 0x00, 0x1c, 0x22, 0x02, 0x32, 0x22, 0x22, 0x3c, 0x00, 0x00, 0x00, /*'G'*/ +0x00, 0x00, 0x22, 0x22, 0x22, 0x3e, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'H'*/ +0x00, 0x00, 0x3e, 0x08, 0x08, 0x08, 0x08, 0x08, 0x3e, 0x00, 0x00, 0x00, /*'I'*/ +0x00, 0x00, 0x38, 0x20, 0x20, 0x20, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'J'*/ +0x00, 0x00, 0x22, 0x12, 0x0a, 0x06, 0x0a, 0x12, 0x22, 0x00, 0x00, 0x00, /*'K'*/ +0x00, 0x00, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'L'*/ +0x00, 0x00, 0x22, 0x36, 0x2a, 0x2a, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'M'*/ +0x00, 0x00, 0x22, 0x26, 0x26, 0x2a, 0x32, 0x32, 0x22, 0x00, 0x00, 0x00, /*'N'*/ +0x00, 0x00, 0x1c, 0x22, 0x22, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'O'*/ +0x00, 0x00, 0x1e, 0x22, 0x22, 0x1e, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, /*'P'*/ +0x00, 0x00, 0x1c, 0x22, 0x22, 0x22, 0x22, 0x22, 0x1c, 0x30, 0x00, 0x00, /*'Q'*/ +0x00, 0x00, 0x1e, 0x22, 0x22, 0x1e, 0x0a, 0x12, 0x22, 0x00, 0x00, 0x00, /*'R'*/ +0x00, 0x00, 0x1c, 0x22, 0x02, 0x1c, 0x20, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'S'*/ +0x00, 0x00, 0x3e, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, /*'T'*/ +0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'U'*/ +0x00, 0x00, 0x22, 0x22, 0x22, 0x14, 0x14, 0x08, 0x08, 0x00, 0x00, 0x00, /*'V'*/ +0x00, 0x00, 0x22, 0x22, 0x22, 0x2a, 0x2a, 0x36, 0x22, 0x00, 0x00, 0x00, /*'W'*/ +0x00, 0x00, 0x22, 0x22, 0x14, 0x08, 0x14, 0x22, 0x22, 0x00, 0x00, 0x00, /*'X'*/ +0x00, 0x00, 0x22, 0x22, 0x14, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, /*'Y'*/ +0x00, 0x00, 0x3e, 0x20, 0x10, 0x08, 0x04, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'Z'*/ +0x38, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x38, 0x00, /*'['*/ +0x02, 0x02, 0x04, 0x04, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x00, 0x00, /*'\'*/ +0x0e, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x0e, 0x00, /*']'*/ +0x00, 0x08, 0x14, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'^'*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, /*'_'*/ +0x00, 0x0c, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'`'*/ +0x00, 0x00, 0x00, 0x00, 0x3c, 0x22, 0x22, 0x32, 0x2c, 0x00, 0x00, 0x00, /*'a'*/ +0x00, 0x02, 0x02, 0x02, 0x1e, 0x22, 0x22, 0x22, 0x1e, 0x00, 0x00, 0x00, /*'b'*/ +0x00, 0x00, 0x00, 0x00, 0x3c, 0x02, 0x02, 0x02, 0x3c, 0x00, 0x00, 0x00, /*'c'*/ +0x00, 0x20, 0x20, 0x20, 0x3c, 0x22, 0x22, 0x22, 0x3c, 0x00, 0x00, 0x00, /*'d'*/ +0x00, 0x00, 0x00, 0x00, 0x1c, 0x22, 0x3e, 0x02, 0x1c, 0x00, 0x00, 0x00, /*'e'*/ +0x00, 0x38, 0x04, 0x04, 0x1e, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, /*'f'*/ +0x00, 0x00, 0x00, 0x00, 0x3c, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x20, 0x1c, /*'g'*/ +0x00, 0x02, 0x02, 0x02, 0x1e, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'h'*/ +0x00, 0x08, 0x08, 0x00, 0x0c, 0x08, 0x08, 0x08, 0x1c, 0x00, 0x00, 0x00, /*'i'*/ +0x00, 0x10, 0x10, 0x00, 0x1c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0e, /*'j'*/ +0x00, 0x02, 0x02, 0x02, 0x12, 0x0a, 0x06, 0x0a, 0x12, 0x00, 0x00, 0x00, /*'k'*/ +0x00, 0x0c, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x1c, 0x00, 0x00, 0x00, /*'l'*/ +0x00, 0x00, 0x00, 0x00, 0x16, 0x2a, 0x2a, 0x2a, 0x22, 0x00, 0x00, 0x00, /*'m'*/ +0x00, 0x00, 0x00, 0x00, 0x1a, 0x26, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'n'*/ +0x00, 0x00, 0x00, 0x00, 0x1c, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'o'*/ +0x00, 0x00, 0x00, 0x00, 0x1e, 0x22, 0x22, 0x22, 0x1e, 0x02, 0x02, 0x02, /*'p'*/ +0x00, 0x00, 0x00, 0x00, 0x3c, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x20, 0x20, /*'q'*/ +0x00, 0x00, 0x00, 0x00, 0x1a, 0x06, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, /*'r'*/ +0x00, 0x00, 0x00, 0x00, 0x3c, 0x02, 0x1c, 0x20, 0x1e, 0x00, 0x00, 0x00, /*'s'*/ +0x00, 0x08, 0x08, 0x08, 0x3e, 0x08, 0x08, 0x08, 0x30, 0x00, 0x00, 0x00, /*'t'*/ +0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x32, 0x2c, 0x00, 0x00, 0x00, /*'u'*/ +0x00, 0x00, 0x00, 0x00, 0x36, 0x14, 0x14, 0x08, 0x08, 0x00, 0x00, 0x00, /*'v'*/ +0x00, 0x00, 0x00, 0x00, 0x22, 0x2a, 0x2a, 0x2a, 0x14, 0x00, 0x00, 0x00, /*'w'*/ +0x00, 0x00, 0x00, 0x00, 0x22, 0x14, 0x08, 0x14, 0x22, 0x00, 0x00, 0x00, /*'x'*/ +0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x20, 0x1c, /*'y'*/ +0x00, 0x00, 0x00, 0x00, 0x3e, 0x10, 0x08, 0x04, 0x3e, 0x00, 0x00, 0x00, /*'z'*/ +0x20, 0x10, 0x10, 0x10, 0x10, 0x08, 0x10, 0x10, 0x10, 0x10, 0x20, 0x00, /*'{'*/ +0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, /*'|'*/ +0x02, 0x04, 0x04, 0x04, 0x04, 0x08, 0x04, 0x04, 0x04, 0x04, 0x02, 0x00, /*'}'*/ +0x00, 0x04, 0x2a, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'~'*/ +0x00, 0x00, 0x00, 0x08, 0x08, 0x14, 0x14, 0x22, 0x3e, 0x00, 0x00, 0x00, /*DEL*/ +}; + +void newline(fb_t* fb) +{ + uint8_t* to; + uint8_t* from; + int i; + fb->y++; + fb->x = 0; + + if (fb->y == (fb->height / CHAR_H)) + { + + to = (uint8_t*) fb->addr; + from = to + (CHAR_H * fb->pitch); + + for (i = 0; i < ((fb->height - CHAR_H) * fb->pitch); i++) + { + *to++ = *from++; + } + + uint32_t *addr = (uint32_t*) (fb->addr) + (fb->height - CHAR_H) * fb->width; + + for (i = 0; i < (CHAR_H * fb->width); i++) + { + *addr++ = fb->back; + } + + fb->y--; + } +} + +void clear_line(fb_t *fb, const int line) +{ + int i; + uint32_t* addr; + if (line > fb->height / CHAR_H) + { + fb->y = 0; + } + else + { + fb->y = line; + } + + fb->x = 0; + + addr = (uint32_t*) (fb->addr + (line * CHAR_H * fb->depth * fb->width)); + for (i = 0; i < (CHAR_H * fb->width); i++) + { + *addr++ = fb->back; + } + +} + +void clear(fb_t *fb, const uint32_t color) +{ + + uint32_t *addr = (uint32_t*) fb->addr; + uint32_t i; + for (i = 0; i < (fb->height * fb->width); i++) + { + *addr++ = color; + } + fb->x = 0; + fb->y = 0; + +} + +void fb_draw_char(fb_t *fb, char s) +{ + unsigned char* addr = (unsigned char*) fb->addr; + unsigned char *glyph = (unsigned char*) FONT + (s) * 12; + // calculate the offset on screen + int offs = (fb->y * CHAR_H * fb->pitch) + (fb->x * (CHAR_W + 1) * 4); + // variables + int i, j, line, mask, bytesperline = (CHAR_W + 7) / 8; + // display a character + for (j = 0; j < CHAR_H; j++) + { + // display one row + line = offs; + mask = 1; + for (i = 0; i < CHAR_W; i++) + { + // if bit set, we use white color, otherwise black + *((unsigned int*) (addr + line)) = ((int) *glyph) & mask ? fb->fore : fb->back; + mask <<= 1; + line += 4; + } + // adjust to next line + glyph += bytesperline; + offs += fb->pitch; + } +} + +void fb_print(fb_t *fb, char *s) +{ + + // draw next character if it's not zero + while (*s) + { + // handle carrige return + if (*s == '\r') + { + fb->x = 0; + } + else if (*s == '\n') + { + newline(fb); + } + else if (*s == '\t') + { + fb->x = ((fb->x + 4) >> 2) << 2; + } + else if (*s == '\b') + { + if (fb->x) + { + fb->x--; + fb_draw_char(fb, ' '); + } + } + else + { + fb_draw_char(fb, *s); + fb->x++; + } + // next character + if (fb->x == fb->width / CHAR_W) + { + newline(fb); + } + s++; + } +} + +rt_err_t hdmi_fb_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +rt_err_t hdmi_fb_close(rt_device_t dev) +{ + return RT_EOK; +} + +rt_size_t hdmi_fb_read(rt_device_t dev, rt_off_t pos, void *buf, rt_size_t size) +{ + return 0; +} + +rt_size_t hdmi_fb_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + fb_print(&_hdmi.fb, (char *) buffer); +#ifdef BSP_USING_HDMI_DISPLAY + rt_device_t uart = rt_device_find("uart1"); + int old_flag = uart->open_flag; + uart->open_flag |= RT_DEVICE_FLAG_STREAM; + rt_device_write(uart, 0, buffer, size); + uart->open_flag = old_flag; +#endif + return size; +} + +rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args) +{ + return RT_EOK; +} + +const static struct rt_device_ops hdmi_fb_ops = +{ + RT_NULL, + hdmi_fb_open, + hdmi_fb_close, + hdmi_fb_read, + hdmi_fb_write, + hdmi_fb_control +}; + +static struct rt_device_graphic_info _hdmi_info; + +static void hdmi_draw_rect(const char* pixel, int x1, int y1, int x2, int y2) +{ + int i, j; + int line; + for (j = y1; j <= y2; j++) + { + line = (j * _hdmi.fb.pitch) + (x1 * 4); + for (i = x1; i <= x2; i++) + { + // if bit set, we use white color, otherwise black + *((unsigned int*) (_hdmi_info.framebuffer + line)) = *(unsigned int*) pixel; + line += 4; + } + } + +} + +static void hdmi_set_pixel(const char* pixel, int x, int y) +{ + *(uint32_t*) (_hdmi.fb.addr + (y * _hdmi.fb.pitch + x * 4)) = *(uint32_t *) pixel; +} + +static void hdmi_get_pixel(char* pixel, int x, int y) +{ + uint32_t ret = 0; + ret = (*(uint32_t*) (_hdmi.fb.addr + (y * _hdmi.fb.pitch + x * 4)) & 0x00FFFFFF); + *pixel = ret; +} + +static void hdmi_draw_hline(const char* pixel, int x1, int x2, int y) +{ + hdmi_draw_rect(pixel, x1, y, x2, y); +} + +static void hdmi_draw_vline(const char* pixel, int x, int y1, int y2) +{ + hdmi_draw_rect(pixel, x, y1, x, y2); +} + +static void hdmi_blit_line(const char* pixels, int x, int y, rt_size_t size) +{ + int i = 0; + uint32_t *pixel_base = (uint32_t*) (_hdmi.fb.addr + (y * _hdmi.fb.pitch + x * 4)); + uint32_t *colors = (uint32_t *) pixels; + for (i = 0; i < size; i++) + { + pixel_base[i] = colors[i]; + } +} + +static struct rt_device_graphic_ops hdmi_ops = +{ + hdmi_set_pixel, + hdmi_get_pixel, + hdmi_draw_hline, + hdmi_draw_vline, + hdmi_blit_line +}; + +rt_err_t rt_hdmi_fb_device_init(struct rt_hdmi_fb_device *hdmi_fb, const char *name) +{ + struct rt_device *device; + RT_ASSERT(hdmi_fb != RT_NULL); + + device = &hdmi_fb->parent; + device->user_data = &hdmi_ops; + + /* set device type */ + device->type = RT_Device_Class_Graphic; + /* initialize device interface */ +#ifdef RT_USING_DEVICE_OPS + device->ops = &hdmi_fb_ops; +#else + device->init = RT_NULL; + device->open = hdmi_fb_open; + device->close = hdmi_fb_close; + device->read = hdmi_fb_read; + device->write = hdmi_fb_write; + device->control = hdmi_fb_control; +#endif + + /* register to device manager */ + rt_device_register(device, name, RT_DEVICE_FLAG_RDWR); + + return RT_EOK; +} + +/** + * Show a picture + */ +void print_fb_info() +{ + rt_kprintf("FrameBuffer Info: \n \t width %x\t height %x\t depth %x\t addr %x\t size %x\t \n", fb_info.width, + fb_info.height, fb_info.depth, fb_info.addr, fb_info.size); + rt_kprintf("call mbox:%x,%x,%x,%x,%x\n", mbox[0], mbox[1], mbox[2], mbox[3], mbox[4]); +} + +int hdmi_fb_init() +{ + unsigned int *mbox = (unsigned int*) MBOX_ADDR; + mbox[0] = 35 * 4; + mbox[1] = MBOX_REQUEST; + + mbox[2] = 0x48003; //set phy wh + mbox[3] = 8; + mbox[4] = 8; + mbox[5] = 640; //FrameBufferInfo.width + mbox[6] = 480; //FrameBufferInfo.height + + mbox[7] = 0x48004; //set virt wh + mbox[8] = 8; + mbox[9] = 8; + mbox[10] = 640; //FrameBufferInfo.virtual_width + mbox[11] = 480; //FrameBufferInfo.virtual_height + + mbox[12] = 0x48009; //set virt offset + mbox[13] = 8; + mbox[14] = 8; + mbox[15] = 0; //FrameBufferInfo.x_offset + mbox[16] = 0; //FrameBufferInfo.y.offset + + mbox[17] = 0x48005; //set depth + mbox[18] = 4; + mbox[19] = 4; + mbox[20] = 32; //FrameBufferInfo.depth + + mbox[21] = 0x48006; //set pixel order + mbox[22] = 4; + mbox[23] = 4; + mbox[24] = 1; //RGB, not BGR preferably + + mbox[25] = 0x40001; //get framebuffer, gets alignment on request + mbox[26] = 8; + mbox[27] = 8; + mbox[28] = 4096; //FrameBufferInfo.pointer + mbox[29] = 0; //FrameBufferInfo.size + + mbox[30] = 0x40008; //get pitch + mbox[31] = 4; + mbox[32] = 4; + mbox[33] = 0; //FrameBufferInfo.pitch + + mbox[34] = MBOX_TAG_LAST; + if (mbox_call(MBOX_CH_PROP, MMU_DISABLE) && mbox[20] == 32 && mbox[28] != 0) + { + mbox[28] &= 0x3FFFFFFF; + _hdmi.fb.width = mbox[5]; + _hdmi.fb.height = mbox[6]; + _hdmi.fb.pitch = mbox[33]; + //_hdmi.fb.addr = (void*)((unsigned long)mbox[28]); + _hdmi.fb.addr = (rt_uint32_t) mbox[28]; + _hdmi.fb.size = mbox[29]; + _hdmi.fb.depth = 32; + _hdmi.fb.x = 0; + _hdmi.fb.y = 0; + _hdmi.fb.fore = CONSOLE_WHITE; + _hdmi.fb.back = CONSOLE_BLACK; + rt_hdmi_fb_device_init(&_hdmi, "hdmi"); + rt_hw_change_mmu_table(_hdmi.fb.addr, _hdmi.fb.size, _hdmi.fb.addr, DEVICE_MEM); + fb_info.width = _hdmi.fb.width; + fb_info.height = _hdmi.fb.height; + fb_info.addr = _hdmi.fb.addr; + fb_info.size = _hdmi.fb.size; + fb_info.pitch = _hdmi.fb.pitch; + fb_info.depth = _hdmi.fb.depth; + _hdmi_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888; + _hdmi_info.bits_per_pixel = _hdmi.fb.depth; + _hdmi_info.width = _hdmi.fb.width; + _hdmi_info.height = _hdmi.fb.height; + _hdmi_info.framebuffer = (rt_uint8_t *) _hdmi.fb.addr; + } + return 0; +} + +INIT_DEVICE_EXPORT(hdmi_fb_init); diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_fb.h b/bsp/raspberry-pi/raspi3-32/driver/drv_fb.h new file mode 100644 index 0000000000000000000000000000000000000000..4926fa3ab19bcee6c0afb03accc8342a3c939866 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_fb.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-08-29 zdzn first version + */ +#ifndef __DRV_FB_H__ +#define __DRV_FB_H__ + +#define RGB(r, g, b) ((((r))<<16) | (((g))<<8) | ((b))) + +#define COLOR_BLACK RGB(0, 0, 0) + +#define COLOR_GREEN RGB(0, 255, 0) + +#define COLOR_CYAN RGB(0, 255, 255) + +#define COLOR_RED RGB(255, 0, 0) + +#define COLOR_YELLOW RGB(255, 255, 0) + +#define COLOR_WHITE RGB(255, 255, 255) + +#define CONSOLE_WHITE COLOR_WHITE +#define CONSOLE_BLACK COLOR_BLACK +#define CONSOLE_GREEN COLOR_GREEN +#define CONSOLE_CYAN COLOR_CYAN +#define CONSOLE_RED COLOR_RED +#define CONSOLE_YELLOW COLOR_YELLOW + +typedef struct +{ + rt_uint32_t width; + rt_uint32_t height; + rt_uint32_t vwidth; + rt_uint32_t vheight; + rt_uint32_t pitch; + rt_uint32_t depth; + rt_uint32_t fore; + rt_uint32_t back; + rt_uint32_t x; + rt_uint32_t y; + rt_uint32_t addr; + rt_uint32_t size; +} fb_t; + +struct rt_hdmi_fb_device +{ + struct rt_device parent; + fb_t fb; +}; + +fb_t fb_info; +void print_fb_info(); + +#endif/* __DRV_FB_H__ */ diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..c239c56cf28baae35192044076c27fc72a02dc76 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c @@ -0,0 +1,318 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#include "drv_gpio.h" + +#ifdef BSP_USING_PIN +/* + * gpio_int[0] for BANK0 (pins 0-27) + * gpio_int[1] for BANK1 (pins 28-45) + * gpio_int[2] for BANK2 (pins 46-53) + */ +static struct gpio_irq_def _g_gpio_irq_tbl[GPIO_IRQ_NUM]; + +void gpio_set_pud(rt_uint8_t pin, rt_uint8_t pud) +{ + rt_uint8_t num = pin / 32; + rt_uint8_t shift = pin % 32; + BCM283X_GPIO_GPPUD = pud; + DELAY_MICROS(10); + BCM283X_GPIO_GPPUDCLK(num) = 1 << shift; + DELAY_MICROS(10); + BCM283X_GPIO_GPPUD = BCM283X_GPIO_PUD_OFF; + BCM283X_GPIO_GPPUDCLK(num) = 0 << shift; +} + +static void gpio_ack_irq(int irq, bcm_gpio_pin pin) +{ + rt_uint32_t data; + data = IRQ_PEND2; + data &= (0x0 << (irq - 32)); + IRQ_PEND2 = data; + + data = IRQ_DISABLE2; + data |= (0x1 << (irq - 32)); + IRQ_DISABLE2 = data; +} + +void gpio_irq_disable(rt_uint8_t index, bcm_gpio_pin pin) +{ + int irq = 0; + rt_uint32_t reg_value; + rt_uint8_t irq_type; + irq = IRQ_GPIO0 + index; + + gpio_ack_irq(irq, pin); + + irq_type = _g_gpio_irq_tbl[index].irq_type[pin]; + rt_uint8_t shift = pin % 32; + rt_uint32_t mask = 1 << shift; + + switch (irq_type) + { + case PIN_IRQ_MODE_RISING: + reg_value = BCM283X_GPIO_GPREN(pin /32); + BCM283X_GPIO_GPREN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask); + break; + case PIN_IRQ_MODE_FALLING: + reg_value = BCM283X_GPIO_GPFEN(pin /32); + BCM283X_GPIO_GPFEN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask); + break; + case PIN_IRQ_MODE_RISING_FALLING: + reg_value = BCM283X_GPIO_GPAREN(pin /32); + BCM283X_GPIO_GPAREN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask); + reg_value = BCM283X_GPIO_GPAFEN(pin /32); + BCM283X_GPIO_GPAFEN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask); + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + reg_value = BCM283X_GPIO_GPHEN(pin /32); + BCM283X_GPIO_GPHEN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask); + break; + case PIN_IRQ_MODE_LOW_LEVEL: + reg_value = BCM283X_GPIO_GPLEN(pin /32); + BCM283X_GPIO_GPLEN(pin /32) = (reg_value & ~ mask) | (PIN_LOW & mask); + break; + } +} + +void gpio_irq_enable(rt_uint8_t index, bcm_gpio_pin pin) +{ + rt_uint32_t offset; + rt_uint32_t data; + + offset = pin; + if (index == 0) + offset = IRQ_GPIO0 - 32; + else if (index == 1) + offset = IRQ_GPIO1 - 32; + else + offset = IRQ_GPIO2 - 32; + + data = IRQ_ENABLE2; + data |= 0x1 << offset; + IRQ_ENABLE2 = data; + +} + +static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode) +{ + RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL)); + RT_ASSERT(!(mode & 0x8)); + + switch (mode) + { + case PIN_MODE_OUTPUT: + GPIO_FSEL(pin, BCM283X_GPIO_FSEL_OUTP); + break; + case PIN_MODE_INPUT: + GPIO_FSEL(pin, BCM283X_GPIO_FSEL_INPT); + break; + case PIN_MODE_INPUT_PULLUP: + gpio_set_pud(pin, BCM283X_GPIO_PUD_UP); + GPIO_FSEL(pin, BCM283X_GPIO_FSEL_INPT); + break; + case PIN_MODE_INPUT_PULLDOWN: + gpio_set_pud(pin, BCM283X_GPIO_PUD_DOWN); + GPIO_FSEL(pin, BCM283X_GPIO_FSEL_INPT); + break; + case PIN_MODE_OUTPUT_OD: + gpio_set_pud(pin, BCM283X_GPIO_PUD_OFF); + GPIO_FSEL(pin, BCM283X_GPIO_FSEL_OUTP); + break; + } +} + +static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value) +{ + RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL)); + RT_ASSERT(!(value & 0xE)); + + if (value) + BCM283X_GPIO_GPSET(pin / 32) |= (1 << (pin %32)); + else + BCM283X_GPIO_GPCLR(pin / 32) |= (0 << (pin %32)); + +} + +static int raspi_pin_read(struct rt_device *device, rt_base_t pin) +{ + RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL)); + return (BCM2835_GPIO_GPLEV(pin / 32) & (1 << (pin % 32)))? PIN_HIGH : PIN_LOW; +} + +static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL)); + + rt_uint8_t index; + rt_uint32_t reg_value; + if (pin <= 27) + index = 0; + else if (pin <= 45) + index = 1; + else + index = 2; + _g_gpio_irq_tbl[index].irq_cb[pin] = hdr; + _g_gpio_irq_tbl[index].irq_arg[pin] = args; + _g_gpio_irq_tbl[index].irq_type[pin] = mode; + + rt_uint8_t shift = pin % 32; + rt_uint32_t mask = 1 << shift; + + switch (mode) + { + case PIN_IRQ_MODE_RISING: + reg_value = BCM283X_GPIO_GPREN(pin /32); + BCM283X_GPIO_GPREN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask); + break; + case PIN_IRQ_MODE_FALLING: + reg_value = BCM283X_GPIO_GPFEN(pin /32); + BCM283X_GPIO_GPFEN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask); + break; + case PIN_IRQ_MODE_RISING_FALLING: + reg_value = BCM283X_GPIO_GPAREN(pin /32); + BCM283X_GPIO_GPAREN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask); + reg_value = BCM283X_GPIO_GPAFEN(pin /32); + BCM283X_GPIO_GPAFEN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask); + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + reg_value = BCM283X_GPIO_GPHEN(pin /32); + BCM283X_GPIO_GPHEN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask); + break; + case PIN_IRQ_MODE_LOW_LEVEL: + reg_value = BCM283X_GPIO_GPLEN(pin /32); + BCM283X_GPIO_GPLEN(pin /32) = (reg_value & ~ mask) | (PIN_HIGH & mask); + break; + } + return RT_EOK; +} + +static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL)); + + rt_uint8_t index; + if (pin <= 27) + index = 0; + else if (pin <= 45) + index = 1; + else + index = 2; + + gpio_irq_disable(index, pin); + + _g_gpio_irq_tbl[index].irq_cb[pin] = RT_NULL; + _g_gpio_irq_tbl[index].irq_arg[pin] = RT_NULL; + _g_gpio_irq_tbl[index].irq_type[pin] = RT_NULL; + + return RT_EOK; +} + +rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL)); + + rt_uint8_t index; + if (pin <= 27) + index = 0; + else if (pin <= 45) + index = 1; + else + index = 2; + + if (enabled) + gpio_irq_enable(index, pin); + else + gpio_irq_disable(index, pin); + + return RT_EOK; +} + +static void gpio_irq_handler(int irq, void *param) +{ + struct gpio_irq_def *irq_def = (struct gpio_irq_def *)param; + rt_uint32_t pin; + rt_uint32_t value; + rt_uint32_t tmpvalue; + + if (irq == IRQ_GPIO0) + { + /* 0~27 */ + + value = BCM283X_GPIO_GPEDS(0); + value &= 0x0fffffff; + pin = 0; + BCM283X_GPIO_GPEDS(0) = 0; + } + else if (irq == IRQ_GPIO1) + { + /* 28-45 */ + tmpvalue = BCM283X_GPIO_GPEDS(0); + tmpvalue &= (~0x0fffffff); + + value = BCM283X_GPIO_GPEDS(1); + value &= 0x3fff; + value = (value<<4) | tmpvalue; + pin = 28; + BCM283X_GPIO_GPEDS(0) = 0; + BCM283X_GPIO_GPEDS(1) = 0; + } + else if (irq == IRQ_GPIO2) + { + /* 46-53 */ + value = BCM283X_GPIO_GPEDS(1); + value &= (~0x3fff); + value &= 0xff600000; + pin = 46; + BCM283X_GPIO_GPEDS(1) = 0; + } + + while (value) + { + if ((value & 0x1) && (irq_def->irq_cb[pin] != RT_NULL)) + { + irq_def->irq_cb[pin](irq_def->irq_arg[pin]); + gpio_ack_irq(irq,pin); + } + pin++; + value = value >> 1; + } +} + +static const struct rt_pin_ops ops = +{ + raspi_pin_mode, + raspi_pin_write, + raspi_pin_read, + raspi_pin_attach_irq, + raspi_pin_detach_irq, + raspi_pin_irq_enable, +}; +#endif + +int rt_hw_gpio_init(void) +{ +#ifdef BSP_USING_PIN + rt_device_pin_register("gpio", &ops, RT_NULL); + + /* install ISR */ + rt_hw_interrupt_install(IRQ_GPIO0, gpio_irq_handler, &_g_gpio_irq_tbl[0], "gpio0_irq"); + rt_hw_interrupt_umask(IRQ_GPIO0); + + rt_hw_interrupt_install(IRQ_GPIO1, gpio_irq_handler, &_g_gpio_irq_tbl[1], "gpio1_irq"); + rt_hw_interrupt_umask(IRQ_GPIO1); + + rt_hw_interrupt_install(IRQ_GPIO2, gpio_irq_handler, &_g_gpio_irq_tbl[2], "gpio2_irq"); + rt_hw_interrupt_umask(IRQ_GPIO2); +#endif + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_gpio_init); diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..ce0be096e84969de771ae7806ae1f573677e1237 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include + +#include "interrupt.h" +#include "board.h" + +#define GPIO_IRQ_NUM 3 + +#define IRQ_GPIO0 49 +#define IRQ_GPIO1 50 +#define IRQ_GPIO2 51 +#define IRQ_GPIO3 52 + +struct gpio_irq_def +{ + void *irq_arg[32]; + void (*irq_cb[32])(void *param); + rt_uint8_t irq_type[32]; +}; + +enum gpio_irq_clock +{ + GPIO_IRQ_LOSC_32KHZ = 0, + GPIO_IRQ_HOSC_24MHZ +}; + +int rt_hw_gpio_init(void); + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c b/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..35ab7c36d7367e75e4187adc57a14ef2aa78ad3c --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#include "drv_i2c.h" + +//Maybe redefined +typedef unsigned long rt_ubase_t; +typedef rt_ubase_t rt_size_t; + +rt_uint8_t i2c_read_or_write(volatile rt_uint32_t base, rt_uint8_t* buf, rt_uint32_t len, rt_uint8_t flag) +{ + rt_uint32_t status; + rt_uint32_t remaining = len; + rt_uint32_t i = 0; + rt_uint8_t reason = BCM283X_I2C_REASON_OK; + + /* Clear FIFO */ + BCM283X_BSC_C(base) |= (BSC_C_CLEAR_1 & BSC_C_CLEAR_1); + /* Clear Status */ + BCM283X_BSC_S(base) = BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE; + /* Set Data Length */ + BCM283X_BSC_DLEN(base) = len; + if (flag) + { + /* Start read */ + BCM283X_BSC_C(base) = BSC_C_I2CEN | BSC_C_ST | BSC_C_READ; + /* wait for transfer to complete */ + while (!(BCM283X_BSC_S(base) & BSC_S_DONE)) + { + /* we must empty the FIFO as it is populated and not use any delay */ + while (remaining && (BCM283X_BSC_S(base) & BSC_S_RXD)) + { + /* Read from FIFO, no barrier */ + buf[i] = BCM283X_BSC_FIFO(base); + i++; + remaining--; + } + } + /* transfer has finished - grab any remaining stuff in FIFO */ + while (remaining && (BCM283X_BSC_S(base) & BSC_S_RXD)) + { + /* Read from FIFO, no barrier */ + buf[i] = BCM283X_BSC_FIFO(base); + i++; + remaining--; + } + } + else + { + /* pre populate FIFO with max buffer */ + while (remaining && (i < BSC_FIFO_SIZE)) + { + BCM283X_BSC_FIFO(base) = buf[i]; + i++; + remaining--; + } + + /* Enable device and start transfer */ + BCM283X_BSC_C(base) = BSC_C_I2CEN | BSC_C_ST; + + /* Transfer is over when BCM2835_BSC_S_DONE */ + while (!(BCM283X_BSC_S(base) & BSC_S_DONE)) + { + while (remaining && (BCM283X_BSC_S(base) & BSC_S_TXD)) + { + /* Write to FIFO */ + BCM283X_BSC_FIFO(base) = buf[i]; + i++; + remaining--; + } + } + } + + status = BCM283X_BSC_S(base); + if (status & BSC_S_ERR) + { + reason = BCM283X_I2C_REASON_ERROR_NACK; + } + else if (status & BSC_S_CLKT) + { + reason = BCM283X_I2C_REASON_ERROR_CLKT; + } + else if (remaining) + { + reason = BCM283X_I2C_REASON_ERROR_DATA; + } + BCM283X_BSC_C(base) |= (BSC_S_DONE & BSC_S_DONE); + + return reason; +} + +struct raspi_i2c_hw_config +{ + rt_uint8_t bsc_num; + rt_uint8_t sdl_pin; + rt_uint8_t scl_pin; + rt_uint8_t sdl_mode; + rt_uint8_t scl_mode; +}; + +#if (defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1)) + +static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num); +static rt_size_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num); +static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus, + rt_uint32_t, + rt_uint32_t); + +static rt_uint32_t i2c_byte_wait_us = 0; +static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + rt_size_t i; + rt_uint8_t reason; + RT_ASSERT(bus != RT_NULL); + + volatile rt_uint32_t base = (volatile rt_uint32_t)(bus->parent.user_data); + + if (bus->addr == 0) + base = BCM283X_BSC0_BASE; + else + base = BCM283X_BSC1_BASE; + + BCM283X_BSC_A(base) = msgs->addr; + + for (i = 0; i < num; i++) + { + if (msgs[i].flags & RT_I2C_RD) + reason = i2c_read_or_write(base, msgs->buf, msgs->len, 1); + else + reason = i2c_read_or_write(base, msgs->buf, msgs->len, 0); + } + return (reason == 0)? i : 0; +} + +static rt_size_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + return 0; +} +static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus, + rt_uint32_t cmd, + rt_uint32_t arg) +{ + return RT_EOK; +} + +static const struct rt_i2c_bus_device_ops raspi_i2c_ops = +{ + .master_xfer = raspi_i2c_mst_xfer, + .slave_xfer = raspi_i2c_slv_xfer, + .i2c_bus_control = raspi_i2c_bus_control, +}; + + +static rt_err_t raspi_i2c_configure(struct raspi_i2c_hw_config *cfg) +{ + RT_ASSERT(cfg != RT_NULL); + + volatile rt_uint32_t base = cfg->scl_mode ? BCM283X_BSC1_BASE : BCM283X_BSC0_BASE; + + GPIO_FSEL(cfg->sdl_pin, cfg->sdl_mode); /* SDA */ + GPIO_FSEL(cfg->scl_pin, cfg->scl_mode); /* SCL */ + + /* use 0xFFFE mask to limit a max value and round down any odd number */ + rt_uint32_t divider = (BCM283X_CORE_CLK_HZ / 10000) & 0xFFFE; + BCM283X_BSC_DIV(base) = (rt_uint16_t) divider; + i2c_byte_wait_us = (divider * 1000000 * 9 / BCM283X_CORE_CLK_HZ); + + return RT_EOK; +} +#endif + +#if defined (BSP_USING_I2C0) +#define I2C0_BUS_NAME "i2c0" +static struct raspi_i2c_hw_config hw_device0 = +{ + .bsc_num = 0, + .sdl_pin = RPI_GPIO_P1_27, + .scl_pin = RPI_GPIO_P1_28, + .sdl_mode = BCM283X_GPIO_FSEL_ALT0, + .scl_mode = BCM283X_GPIO_FSEL_ALT0, +}; + +struct rt_i2c_bus_device device0 = +{ + .ops = &raspi_i2c_ops, + .addr = 0, +}; + +#endif + +#if defined (BSP_USING_I2C1) +#define I2C1_BUS_NAME "i2c1" +static struct raspi_i2c_hw_config hw_device1 = +{ + .bsc_num = 1, + .sdl_pin = RPI_GPIO_P1_03, + .scl_pin = RPI_GPIO_P1_05, + .sdl_mode = BCM283X_GPIO_FSEL_ALT0, + .scl_mode = BCM283X_GPIO_FSEL_ALT0, +}; +struct rt_i2c_bus_device device1 = +{ + .ops = &raspi_i2c_ops, + .addr = 1, +}; + +#endif + +int rt_hw_i2c_init(void) +{ +#if defined(BSP_USING_I2C0) + raspi_i2c_configure(&hw_device0); + rt_i2c_bus_device_register(&device0, I2C0_BUS_NAME); +#endif + +#if defined(BSP_USING_I2C1) + raspi_i2c_configure(&hw_device1); + rt_i2c_bus_device_register(&device1, I2C1_BUS_NAME); +#endif + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h b/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..ff9e8ca724721dc8b908669de0f69c7e9c535a23 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + +#include +#include + +#include "board.h" + +struct raspi_master_config_t +{ + rt_uint8_t sdl_pin; + rt_uint8_t scl_pin; + rt_uint8_t sdl_pin_mode; + rt_uint8_t scl_pin_mode; + rt_uint8_t slave_address; + rt_uint32_t bsc_base; + rt_uint16_t clk_div; +}; + +struct raspi_i2c_bus +{ + struct rt_i2c_bus_device device; + struct rt_i2c_msg *msg; + rt_uint32_t msg_cnt; + volatile rt_uint32_t msg_ptr; + volatile rt_uint32_t dptr; + char *device_name; + struct raspi_master_config_t *cfg; +}; + +int rt_hw_i2c_init(void); + +#endif diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..8a33e2be644cadde09eb6c653be66dcab62625d2 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c @@ -0,0 +1,301 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#include "drv_rtc.h" + +#ifdef BSP_USING_RTC + +#define RTC_I2C_BUS_NAME "i2c0" +#define RTC_ADDR 0x68 + +static struct rt_device rtc_device; +static struct rt_i2c_bus_device *i2c_bus = RT_NULL; + +rt_uint8_t buf[]= +{ + 0x00, 0x00, 0x43, 0x15, 0x05, 0x01, 0x03, 0x19 +}; + + +rt_uint8_t i2c_write_read_rs(char* cmds, rt_uint32_t cmds_len, char* buf, rt_uint32_t buf_len) +{ + rt_uint32_t remaining = cmds_len; + rt_uint32_t i = 0; + rt_uint8_t reason = BCM283X_I2C_REASON_OK; + + /* Clear FIFO */ + BCM283X_BSC_C(BCM283X_BSC0_BASE) |= (BSC_C_CLEAR_1 & BSC_C_CLEAR_1); + + /* Clear Status */ + BCM283X_BSC_S(BCM283X_BSC0_BASE) = BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE; + + /* Set Data Length */ + BCM283X_BSC_DLEN(BCM283X_BSC0_BASE) = cmds_len; + + /* pre populate FIFO with max buffer */ + while (remaining && (i < BSC_FIFO_SIZE)) + { + BCM283X_BSC_FIFO(BCM283X_BSC0_BASE) = cmds[i]; + i++; + remaining--; + } + + /* Enable device and start transfer */ + BCM283X_BSC_C(BCM283X_BSC0_BASE) |= BSC_C_I2CEN | BSC_C_ST; + + /* poll for transfer has started (way to do repeated start, from BCM2835 datasheet) */ + while (!(BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_TA)) + { + /* Linux may cause us to miss entire transfer stage */ + if (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_DONE) + break; + } + + remaining = buf_len; + i = 0; + + /* Send a repeated start with read bit set in address */ + BCM283X_BSC_DLEN(BCM283X_BSC0_BASE) = buf_len; + BCM283X_BSC_C(BCM283X_BSC0_BASE) = BSC_C_I2CEN | BSC_C_ST | BSC_C_READ; + + /* Wait for write to complete and first byte back. */ + // DELAYMICROS(i2c_byte_wait_us * (cmds_len + 1)); + + /* wait for transfer to complete */ + while (!(BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_DONE)) + { + /* we must empty the FIFO as it is populated and not use any delay */ + while (remaining && (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_RXD)) + { + /* Read from FIFO, no barrier */ + buf[i] = BCM283X_BSC_FIFO(BCM283X_BSC0_BASE); + i++; + remaining--; + } + } + + /* transfer has finished - grab any remaining stuff in FIFO */ + while (remaining && (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_RXD)) + { + /* Read from FIFO */ + buf[i] = BCM283X_BSC_FIFO(BCM283X_BSC0_BASE); + i++; + remaining--; + } + + /* Received a NACK */ + if (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_ERR) + { + reason = BCM283X_I2C_REASON_ERROR_NACK; + } + + /* Received Clock Stretch Timeout */ + else if (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_CLKT) + { + reason = BCM283X_I2C_REASON_ERROR_CLKT; + } + + /* Not all data is sent */ + else if (remaining) + { + reason = BCM283X_I2C_REASON_ERROR_DATA; + } + + BCM283X_BSC_C(BCM283X_BSC0_BASE) = (BSC_S_DONE &BSC_S_DONE); + + return reason; +} + +rt_uint8_t i2c_write(rt_uint8_t* buf, rt_uint32_t len) +{ + rt_uint32_t remaining = len; + rt_uint32_t i = 0; + rt_uint8_t reason = BCM283X_I2C_REASON_OK; + + /* Clear FIFO */ + BCM283X_BSC_C(BCM283X_BSC0_BASE) |= BSC_C_CLEAR_1 & BSC_C_CLEAR_1; + /* Clear Status */ + BCM283X_BSC_S(BCM283X_BSC0_BASE) = BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE; + /* Set Data Length */ + BCM283X_BSC_DLEN(BCM283X_BSC0_BASE) = len; + /* pre populate FIFO with max buffer */ + while (remaining && (i < BSC_FIFO_SIZE)) + { + BCM283X_BSC_FIFO(BCM283X_BSC0_BASE) = buf[i]; + i++; + remaining--; + } + + /* Enable device and start transfer */ + BCM283X_BSC_C(BCM283X_BSC0_BASE) = BSC_C_I2CEN | BSC_C_ST; + + /* Transfer is over when BCM2835_BSC_S_DONE */ + while (!(BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_DONE)) + { + while (remaining && (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_TXD)) + { + /* Write to FIFO */ + BCM283X_BSC_FIFO(BCM283X_BSC0_BASE) = buf[i]; + i++; + remaining--; + } + } + + /* Received a NACK */ + if (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_ERR) + { + reason = BCM283X_I2C_REASON_ERROR_NACK; + } + + /* Received Clock Stretch Timeout */ + else if (BCM283X_BSC_S(BCM283X_BSC0_BASE) & BSC_S_CLKT) + { + reason = BCM283X_I2C_REASON_ERROR_CLKT; + } + + /* Not all data is sent */ + else if (remaining) + { + reason = BCM283X_I2C_REASON_ERROR_DATA; + } + + BCM283X_BSC_C(BCM283X_BSC0_BASE) = BSC_S_DONE & BSC_S_DONE; + return reason; +} + + +static time_t raspi_get_timestamp(void) +{ + struct tm tm_new = {0}; + buf[0] = 0; + + i2c_write_read_rs((char*)buf, 1, (char*)buf, 7); + + tm_new.tm_year = ((buf[6] / 16) + 0x30) * 10 + (buf[6] % 16) + 0x30; + tm_new.tm_mon = ((buf[5] & 0x1F) / 16 + 0x30) + (buf[5] & 0x1F) % 16+ 0x30; + tm_new.tm_mday = ((buf[4] & 0x3F) / 16 + 0x30) + (buf[4] & 0x3F) % 16+ 0x30; + tm_new.tm_hour = ((buf[2] & 0x3F) / 16 + 0x30) + (buf[2] & 0x3F) % 16+ 0x30; + tm_new.tm_min = ((buf[1] & 0x7F) / 16 + 0x30) + (buf[1] & 0x7F) % 16+ 0x30; + tm_new.tm_sec = ((buf[0] & 0x7F) / 16 + 0x30) + (buf[0] & 0x7F) % 16+ 0x30; + + return mktime(&tm_new); +} + +static int raspi_set_timestamp(time_t timestamp) +{ + struct tm *tblock; + tblock = localtime(×tamp); + buf[0] = 0; + buf[1] = tblock->tm_sec; + buf[2] = tblock->tm_min; + buf[3] = tblock->tm_hour; + buf[4] = tblock->tm_wday; + buf[5] = tblock->tm_mday; + buf[6] = tblock->tm_mon; + buf[7] = tblock->tm_year; + + i2c_write(buf, 8); + + return RT_EOK; +} + +static rt_err_t raspi_rtc_init(rt_device_t dev) +{ + i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(RTC_I2C_BUS_NAME); + raspi_set_timestamp(0); + return RT_EOK; +} + +static rt_err_t raspi_rtc_open(rt_device_t dev, rt_uint16_t oflag) +{ + GPIO_FSEL(BCM_GPIO_PIN_0, BCM283X_GPIO_FSEL_ALT0); /* SDA */ + GPIO_FSEL(BCM_GPIO_PIN_1, BCM283X_GPIO_FSEL_ALT0); /* SCL */ + return RT_EOK; +} + +static rt_err_t raspi_rtc_close(rt_device_t dev) +{ + GPIO_FSEL(BCM_GPIO_PIN_0, BCM283X_GPIO_FSEL_INPT); /* SDA */ + GPIO_FSEL(BCM_GPIO_PIN_1, BCM283X_GPIO_FSEL_INPT); /* SCL */ + return RT_EOK; +} + +static rt_err_t raspi_rtc_control(rt_device_t dev, int cmd, void *args) +{ + + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + *(rt_uint32_t *)args = raspi_get_timestamp(); + break; + case RT_DEVICE_CTRL_RTC_SET_TIME: + raspi_set_timestamp(*(time_t *)args); + break; + default: + return RT_EINVAL; + } + return RT_EOK; +} + +static rt_size_t raspi_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + raspi_rtc_control(dev, RT_DEVICE_CTRL_RTC_GET_TIME, buffer); + return size; +} + +static rt_size_t raspi_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + raspi_rtc_control(dev, RT_DEVICE_CTRL_RTC_SET_TIME, (void *)buffer); + return size; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops raspi_rtc_ops = +{ + .init = raspi_rtc_init, + .open = raspi_rtc_open, + .close = raspi_rtc_close, + .read = raspi_rtc_read, + .write = raspi_rtc_write, + .control = raspi_rtc_control +}; +#endif + +int rt_hw_rtc_init(void) +{ + rt_err_t ret = RT_EOK; + + rtc_device.type = RT_Device_Class_RTC; + rtc_device.rx_indicate = RT_NULL; + rtc_device.tx_complete = RT_NULL; + +#ifdef RT_USING_DEVICE_OPS + rtc_device.ops = &raspi_rtc_ops; +#else + rtc_device.init = raspi_rtc_init; + rtc_device.open = raspi_rtc_open; + rtc_device.close = raspi_rtc_close; + rtc_device.read = raspi_rtc_read; + rtc_device.write = raspi_rtc_write; + rtc_device.control = raspi_rtc_control; +#endif + + rtc_device.user_data = RT_NULL; + + /* register a rtc device */ + ret = rt_device_register(&rtc_device, "rtc", RT_DEVICE_FLAG_RDWR); + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_rtc_init); +#endif /* BSP_USING_RTC */ + diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..d850defa68e57c29b82bd4e55e9672fc83a033b4 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#ifndef __DRV_RTC_H__ +#define __DRV_RTC_H__ + +#include +#include + +#include "board.h" + +int rt_hw_rtc_init(void); + +#endif diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.c b/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.c new file mode 100644 index 0000000000000000000000000000000000000000..c547419ca245de92196e0776627502d28b702b51 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.c @@ -0,0 +1,580 @@ +/* + * File : drv_sdio.c + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#include "drv_sdio.h" + +static rt_uint32_t sdCommandTable[] = { + SD_CMD_INDEX(0), + SD_CMD_RESERVED(1), + SD_CMD_INDEX(2) | SD_RESP_R2, + SD_CMD_INDEX(3) | SD_RESP_R1, + SD_CMD_INDEX(4), + SD_CMD_RESERVED(5), //SD_CMD_INDEX(5) | SD_RESP_R4, + SD_CMD_INDEX(6) | SD_RESP_R1, + SD_CMD_INDEX(7) | SD_RESP_R1b, + SD_CMD_INDEX(8) | SD_RESP_R1, + SD_CMD_INDEX(9) | SD_RESP_R2, + SD_CMD_INDEX(10) | SD_RESP_R2, + SD_CMD_INDEX(11) | SD_RESP_R1, + SD_CMD_INDEX(12) | SD_RESP_R1b | SD_CMD_TYPE_ABORT, + SD_CMD_INDEX(13) | SD_RESP_R1, + SD_CMD_RESERVED(14), + SD_CMD_INDEX(15), + SD_CMD_INDEX(16) | SD_RESP_R1, + SD_CMD_INDEX(17) | SD_RESP_R1 | SD_DATA_READ, + SD_CMD_INDEX(18) | SD_RESP_R1 | SD_DATA_READ | SD_CMD_MULTI_BLOCK | SD_CMD_BLKCNT_EN, + SD_CMD_INDEX(19) | SD_RESP_R1 | SD_DATA_READ, + SD_CMD_INDEX(20) | SD_RESP_R1b, + SD_CMD_RESERVED(21), + SD_CMD_RESERVED(22), + SD_CMD_INDEX(23) | SD_RESP_R1, + SD_CMD_INDEX(24) | SD_RESP_R1 | SD_DATA_WRITE, + SD_CMD_INDEX(25) | SD_RESP_R1 | SD_DATA_WRITE | SD_CMD_MULTI_BLOCK | SD_CMD_BLKCNT_EN, + SD_CMD_INDEX(26) | SD_RESP_R1 | SD_DATA_WRITE, //add + SD_CMD_INDEX(27) | SD_RESP_R1 | SD_DATA_WRITE, + SD_CMD_INDEX(28) | SD_RESP_R1b, + SD_CMD_INDEX(29) | SD_RESP_R1b, + SD_CMD_INDEX(30) | SD_RESP_R1 | SD_DATA_READ, + SD_CMD_RESERVED(31), + SD_CMD_INDEX(32) | SD_RESP_R1, + SD_CMD_INDEX(33) | SD_RESP_R1, + SD_CMD_RESERVED(34), + SD_CMD_INDEX(35) | SD_RESP_R1, //add + SD_CMD_INDEX(36) | SD_RESP_R1, //add + SD_CMD_RESERVED(37), + SD_CMD_INDEX(38) | SD_RESP_R1b, + SD_CMD_INDEX(39) | SD_RESP_R4, //add + SD_CMD_INDEX(40) | SD_RESP_R5, //add + SD_CMD_INDEX(41) | SD_RESP_R3, //add, mov from harbote + SD_CMD_RESERVED(42) | SD_RESP_R1, + SD_CMD_RESERVED(43), + SD_CMD_RESERVED(44), + SD_CMD_RESERVED(45), + SD_CMD_RESERVED(46), + SD_CMD_RESERVED(47), + SD_CMD_RESERVED(48), + SD_CMD_RESERVED(49), + SD_CMD_RESERVED(50), + SD_CMD_INDEX(51) | SD_RESP_R1 | SD_DATA_READ, + SD_CMD_RESERVED(52), + SD_CMD_RESERVED(53), + SD_CMD_RESERVED(54), + SD_CMD_INDEX(55) | SD_RESP_R3, + SD_CMD_INDEX(56) | SD_RESP_R1 | SD_CMD_ISDATA, + SD_CMD_RESERVED(57), + SD_CMD_RESERVED(58), + SD_CMD_RESERVED(59), + SD_CMD_RESERVED(60), + SD_CMD_RESERVED(61), + SD_CMD_RESERVED(62), + SD_CMD_RESERVED(63) +}; + +static inline rt_uint32_t read32(rt_uint32_t addr) +{ + return (*((volatile rt_uint32_t *)(addr))); +} + +static inline void write32(rt_uint32_t addr, rt_uint32_t value) +{ + *((volatile rt_uint32_t *)(addr)) = value; +} + +rt_err_t sd_int(struct sdhci_pdata_t * pdat, unsigned int mask) +{ + unsigned int r; + unsigned int m = mask | INT_ERROR_MASK; + int cnt = 1000000; + while (!(read32(pdat->virt + EMMC_INTERRUPT) & (m | INT_ERROR_MASK)) && cnt--) + DELAY_MICROS(1); + r = read32(pdat->virt + EMMC_INTERRUPT); + if (cnt <= 0 || (r & INT_CMD_TIMEOUT) || (r & INT_DATA_TIMEOUT)) + { + write32(pdat->virt + EMMC_INTERRUPT, r); + rt_kprintf("send cmd/data timeout wait for %x int: %x, status: %x\n",mask, r, read32(pdat->virt + EMMC_STATUS)); + return -RT_ETIMEOUT; + } + else if (r & INT_ERROR_MASK) + { + write32(pdat->virt + EMMC_INTERRUPT, r); + rt_kprintf("send cmd/data error %x -> %x\n",r, read32(pdat->virt + EMMC_INTERRUPT)); + return -RT_ERROR; + } + write32(pdat->virt + EMMC_INTERRUPT, mask); + return RT_EOK; +} + +rt_err_t sd_status(struct sdhci_pdata_t * pdat, unsigned int mask) +{ + int cnt = 500000; + while ((read32(pdat->virt + EMMC_STATUS) & mask) && !(read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK) && cnt--) + DELAY_MICROS(1); + if (cnt <= 0) + { + return -RT_ETIMEOUT; + } + else if (read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK) + return -RT_ERROR; + return RT_EOK; +} + +static rt_err_t raspi_transfer_command(struct sdhci_pdata_t * pdat, struct sdhci_cmd_t * cmd) +{ + + rt_uint32_t cmdidx; + rt_err_t ret = RT_EOK; + ret = sd_status(pdat, SR_CMD_INHIBIT); + if (ret) + { + rt_kprintf("ERROR: EMMC busy %d\n", ret); + return ret; + } + + cmdidx = sdCommandTable[cmd->cmdidx]; + if (cmdidx == 0xFFFFFFFF) + return -RT_EINVAL; + if (cmd->datarw == DATA_READ) + cmdidx |= SD_DATA_READ; + if (cmd->datarw == DATA_WRITE) + cmdidx |= SD_DATA_WRITE; + mmcsd_dbg("transfer cmd %x(%d) %x %x\n", cmdidx, cmd->cmdidx, cmd->cmdarg, read32(pdat->virt + EMMC_INTERRUPT)); + write32(pdat->virt + EMMC_INTERRUPT,read32(pdat->virt + EMMC_INTERRUPT)); + write32(pdat->virt + EMMC_ARG1, cmd->cmdarg); + write32(pdat->virt + EMMC_CMDTM, cmdidx); + if (cmd->cmdidx == SD_APP_OP_COND) + DELAY_MICROS(1000); + else if ((cmd->cmdidx == SD_SEND_IF_COND) || (cmd->cmdidx == APP_CMD)) + DELAY_MICROS(100); + ret = sd_int(pdat, INT_CMD_DONE); + if (ret) + { + return ret; + } + if (cmd->resptype & RESP_MASK) + { + + if (cmd->resptype & RESP_R2) + { + rt_uint32_t resp[4]; + resp[0] = read32(pdat->virt + EMMC_RESP0); + resp[1] = read32(pdat->virt + EMMC_RESP1); + resp[2] = read32(pdat->virt + EMMC_RESP2); + resp[3] = read32(pdat->virt + EMMC_RESP3); + if (cmd->resptype == RESP_R2) + { + cmd->response[0] = resp[3]<<8 |((resp[2]>>24)&0xff); + cmd->response[1] = resp[2]<<8 |((resp[1]>>24)&0xff); + cmd->response[2] = resp[1]<<8 |((resp[0]>>24)&0xff); + cmd->response[3] = resp[0]<<8 ; + } + else + { + cmd->response[0] = resp[0]; + cmd->response[1] = resp[1]; + cmd->response[2] = resp[2]; + cmd->response[3] = resp[3]; + } + } + else + cmd->response[0] = read32(pdat->virt + EMMC_RESP0); + } + mmcsd_dbg("response: %x: %x %x %x %x (%x, %x)\n", cmd->resptype, cmd->response[0], cmd->response[1], cmd->response[2], cmd->response[3], read32(pdat->virt + EMMC_STATUS),read32(pdat->virt + EMMC_INTERRUPT)); + return ret; +} + +static rt_err_t read_bytes(struct sdhci_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize) +{ + int c = 0; + rt_err_t ret; + int d; + while (c < blkcount) + { + if ((ret = sd_int(pdat, INT_READ_RDY))) + { + rt_kprintf("timeout happens when reading block %d\n",c); + return ret; + } + for (d=0; d < blksize / 4; d++) + if (read32(pdat->virt + EMMC_STATUS) & SR_READ_AVAILABLE) + buf[d] = read32(pdat->virt + EMMC_DATA); + c++; + buf += blksize / 4; + } + return RT_EOK; +} + +static rt_err_t write_bytes(struct sdhci_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize) +{ + int c = 0; + rt_err_t ret; + int d; + while (c < blkcount) + { + if ((ret = sd_int(pdat, INT_WRITE_RDY))) + { + return ret; + } + for (d=0; d < blksize / 4; d++) + write32(pdat->virt + EMMC_DATA, buf[d]); + c++; + buf += blksize / 4; + } + if ((ret = sd_int(pdat, INT_DATA_DONE))) + { + return ret; + } + return RT_EOK; +} + +static rt_err_t raspi_transfer_data(struct sdhci_pdata_t * pdat, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat) +{ + rt_uint32_t dlen = (rt_uint32_t)(dat->blkcnt * dat->blksz); + rt_err_t ret = sd_status(pdat, SR_DAT_INHIBIT); + if (ret) + { + rt_kprintf("ERROR: EMMC busy\n"); + return ret; + } + if (dat->blkcnt > 1) + { + struct sdhci_cmd_t newcmd; + newcmd.cmdidx = SET_BLOCK_COUNT; + newcmd.cmdarg = dat->blkcnt; + newcmd.resptype = RESP_R1; + ret = raspi_transfer_command(pdat, &newcmd); + if (ret) return ret; + } + write32(pdat->virt + EMMC_BLKSIZECNT, dlen | 1 << 16); + + if (dat->flag & DATA_DIR_READ) + { + cmd->datarw = DATA_READ; + ret = raspi_transfer_command(pdat, cmd); + if (ret) return ret; + mmcsd_dbg("read_block %d, %d\n", dat->blkcnt, dat->blksz ); + ret = read_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz); + } + else if (dat->flag & DATA_DIR_WRITE) + { + cmd->datarw = DATA_WRITE; + ret = raspi_transfer_command(pdat, cmd); + if (ret) return ret; + mmcsd_dbg("write_block %d, %d", dat->blkcnt, dat->blksz ); + ret = write_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz); + } + return ret; +} + +static rt_err_t sdhci_transfer(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat) +{ + struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv; + + if (!dat) + return raspi_transfer_command(pdat, cmd); + + return raspi_transfer_data(pdat, cmd, dat); +} + +static void mmc_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct sdhci_t *sdhci = (struct sdhci_t *)host->private_data; + struct sdhci_cmd_t cmd; + struct sdhci_cmd_t stop; + struct sdhci_data_t dat; + + rt_memset(&cmd, 0, sizeof(struct sdhci_cmd_t)); + rt_memset(&stop, 0, sizeof(struct sdhci_cmd_t)); + rt_memset(&dat, 0, sizeof(struct sdhci_data_t)); + + cmd.cmdidx = req->cmd->cmd_code; + cmd.cmdarg = req->cmd->arg; + cmd.resptype =resp_type(req->cmd); + if (req->data) + { + dat.buf = (rt_uint8_t *)req->data->buf; + dat.flag = req->data->flags; + dat.blksz = req->data->blksize; + dat.blkcnt = req->data->blks; + + req->cmd->err = sdhci_transfer(sdhci, &cmd, &dat); + } + else + { + req->cmd->err = sdhci_transfer(sdhci, &cmd, RT_NULL); + } + + req->cmd->resp[3] = cmd.response[3]; + req->cmd->resp[2] = cmd.response[2]; + req->cmd->resp[1] = cmd.response[1]; + req->cmd->resp[0] = cmd.response[0]; + + if (req->stop) + { + stop.cmdidx = req->stop->cmd_code; + stop.cmdarg = req->stop->arg; + cmd.resptype =resp_type(req->stop); + req->stop->err = sdhci_transfer(sdhci, &stop, RT_NULL); + } + + mmcsd_req_complete(host); +} + +rt_int32_t mmc_card_status(struct rt_mmcsd_host *host) +{ + return 0; +} + +void mmc_enable_irq(struct rt_mmcsd_host *host, rt_int32_t en) +{ + +} + +static rt_err_t sdhci_detect(struct sdhci_t * sdhci) +{ + return RT_EOK; +} + +static rt_err_t sdhci_setwidth(struct sdhci_t * sdhci, rt_uint32_t width) +{ + rt_uint32_t temp = 0; + struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv; + if (width == MMCSD_BUS_WIDTH_4) + { + temp = read32((pdat->virt + EMMC_CONTROL0)); + temp |= C0_HCTL_HS_EN; + temp |= C0_HCTL_DWITDH; // always use 4 data lines: + write32((pdat->virt + EMMC_CONTROL0), temp); + } + return RT_EOK; +} + +static rt_uint32_t sdhci_getdivider(rt_uint32_t sdHostVer, rt_uint32_t freq) +{ + rt_uint32_t divisor; + rt_uint32_t closest = 41666666 / freq; + rt_uint32_t shiftcount = __rt_fls(closest - 1); + + + if (shiftcount > 0) shiftcount--; + if (shiftcount > 7) shiftcount = 7; + if (sdHostVer > HOST_SPEC_V2) + divisor = closest; + else + divisor = (1 << shiftcount); + + if (divisor <= 2) + { + divisor = 2; + shiftcount = 0; + } + + rt_uint32_t hi = 0; + if (sdHostVer > HOST_SPEC_V2) + hi = (divisor & 0x300) >> 2; + rt_uint32_t lo = (divisor & 0x0ff); + rt_uint32_t cdiv = (lo << 8) + hi; + return cdiv; +} + +static rt_err_t sdhci_setclock(struct sdhci_t * sdhci, rt_uint32_t clock) +{ + rt_uint32_t temp = 0; + rt_uint32_t sdHostVer = 0; + int count = 100000; + struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)(sdhci->priv); + + while ((read32(pdat->virt + EMMC_STATUS) & (SR_CMD_INHIBIT | SR_DAT_INHIBIT)) && (--count)) + DELAY_MICROS(1); + if (count <= 0) + { + rt_kprintf("EMMC: Set clock: timeout waiting for inhibit flags. Status %08x.\n",read32(pdat->virt + EMMC_STATUS)); + return RT_ERROR; + } + + // Switch clock off. + temp = read32((pdat->virt + EMMC_CONTROL1)); + temp &= ~C1_CLK_EN; + write32((pdat->virt + EMMC_CONTROL1),temp); + DELAY_MICROS(10); + // Request the new clock setting and enable the clock + temp = read32(pdat->virt + EMMC_SLOTISR_VER); + sdHostVer = (temp & HOST_SPEC_NUM) >> HOST_SPEC_NUM_SHIFT; + int cdiv = sdhci_getdivider(sdHostVer, clock); + temp = read32((pdat->virt + EMMC_CONTROL1)); + temp = (temp & 0xffff003f) | cdiv; + write32((pdat->virt + EMMC_CONTROL1),temp); + DELAY_MICROS(10); + + // Enable the clock. + temp = read32(pdat->virt + EMMC_CONTROL1); + temp |= C1_CLK_EN; + write32((pdat->virt + EMMC_CONTROL1),temp); + DELAY_MICROS(10); + // Wait for clock to be stable. + count = 10000; + while (!(read32(pdat->virt + EMMC_CONTROL1) & C1_CLK_STABLE) && count--) + DELAY_MICROS(10); + if (count <= 0) + { + rt_kprintf("EMMC: ERROR: failed to get stable clock %d.\n", clock); + return RT_ERROR; + } + mmcsd_dbg("set stable clock %d.\n", clock); + return RT_EOK; +} + +static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + struct sdhci_t * sdhci = (struct sdhci_t *)host->private_data; + sdhci_setclock(sdhci, io_cfg->clock); + sdhci_setwidth(sdhci, io_cfg->bus_width); +} + +static const struct rt_mmcsd_host_ops ops = +{ + mmc_request_send, + mmc_set_iocfg, + RT_NULL, + RT_NULL, +}; + +static void sdmmc_gpio_init() +{ +// int pin; +// bcm283x_gpio_fsel(47,BCM283X_GPIO_FSEL_INPT); +// bcm283x_gpio_set_pud(47, BCM283X_GPIO_PUD_UP); +// bcm283x_peri_set_bits(BCM283X_GPIO_BASE + BCM283X_GPIO_GPHEN1, 1<<15, 1<<15); +// for (pin = 53; pin >= 48; pin--) +// { +// bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_ALT3); +// bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_UP); +// } +} + +static rt_err_t reset_emmc(struct sdhci_pdata_t * pdat){ + rt_uint32_t temp; + int cnt; + write32((pdat->virt + EMMC_CONTROL0),0); + temp = read32((pdat->virt + EMMC_CONTROL1)); + temp |= C1_SRST_HC; + write32((pdat->virt + EMMC_CONTROL1),temp); + cnt = 10000; + do + { + DELAY_MICROS(10); + } + while ((read32((pdat->virt + EMMC_CONTROL1)) & C1_SRST_HC) && cnt--); + + if (cnt <= 0) + { + rt_kprintf("ERROR: failed to reset EMMC\n"); + return RT_ERROR; + } + temp = read32((pdat->virt + EMMC_CONTROL1)); + temp |= C1_CLK_INTLEN | C1_TOUNIT_MAX; + write32((pdat->virt + EMMC_CONTROL1),temp); + DELAY_MICROS(10); + return RT_EOK; +} + +#ifdef RT_MMCSD_DBG +void dump_registers(struct sdhci_pdata_t * pdat){ + rt_kprintf("EMMC registers:"); + int i = EMMC_ARG2; + for (; i <= EMMC_CONTROL2; i += 4) + rt_kprintf("\t%x:%x\n", i, read32(pdat->virt + i)); + rt_kprintf("\t%x:%x\n", 0x50, read32(pdat->virt + 0x50)); + rt_kprintf("\t%x:%x\n", 0x70, read32(pdat->virt + 0x70)); + rt_kprintf("\t%x:%x\n", 0x74, read32(pdat->virt + 0x74)); + rt_kprintf("\t%x:%x\n", 0x80, read32(pdat->virt + 0x80)); + rt_kprintf("\t%x:%x\n", 0x84, read32(pdat->virt + 0x84)); + rt_kprintf("\t%x:%x\n", 0x88, read32(pdat->virt + 0x88)); + rt_kprintf("\t%x:%x\n", 0x8c, read32(pdat->virt + 0x8c)); + rt_kprintf("\t%x:%x\n", 0x90, read32(pdat->virt + 0x90)); + rt_kprintf("\t%x:%x\n", 0xf0, read32(pdat->virt + 0xf0)); + rt_kprintf("\t%x:%x\n", 0xfc, read32(pdat->virt + 0xfc)); +} +#endif + +int raspi_sdmmc_init(void) +{ + rt_uint32_t virt; + struct rt_mmcsd_host * host = RT_NULL; + struct sdhci_pdata_t * pdat = RT_NULL; + struct sdhci_t * sdhci = RT_NULL; + +#ifdef BSP_USING_SDIO0 + host = mmcsd_alloc_host(); + if (!host) + { + rt_kprintf("alloc host failed"); + goto err; + } + + sdhci = rt_malloc(sizeof(struct sdhci_t)); + if (!sdhci) + { + rt_kprintf("alloc sdhci failed"); + goto err; + } + rt_memset(sdhci, 0, sizeof(struct sdhci_t)); + + sdmmc_gpio_init(); + + virt = MMC0_BASE_ADDR; + + pdat = (struct sdhci_pdata_t *)rt_malloc(sizeof(struct sdhci_pdata_t)); + RT_ASSERT(pdat != RT_NULL); + + pdat->virt = (rt_uint32_t)virt; + reset_emmc(pdat); + + sdhci->name = "sd0"; + sdhci->voltages = VDD_33_34; + sdhci->width = MMCSD_BUSWIDTH_4; + sdhci->clock = 200 * 1000 * 1000; + sdhci->removeable = RT_TRUE; + + sdhci->detect = sdhci_detect; + sdhci->setwidth = sdhci_setwidth; + sdhci->setclock = sdhci_setclock; + sdhci->transfer = sdhci_transfer; + sdhci->priv = pdat; + + host->ops = &ops; + host->freq_min = 400000; + host->freq_max = 50000000; + host->valid_ocr = VDD_32_33 | VDD_33_34; + host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4; + host->max_seg_size = 2048; + host->max_dma_segs = 10; + host->max_blk_size = 512; + host->max_blk_count = 4096; + + host->private_data = sdhci; + + write32((pdat->virt + EMMC_IRPT_EN),0xffffffff); + write32((pdat->virt + EMMC_IRPT_MASK),0xffffffff); +#ifdef RT_MMCSD_DBG + dump_registers(pdat); +#endif + mmcsd_change(host); +#endif + return RT_EOK; + +err: + if (host) rt_free(host); + if (sdhci) rt_free(sdhci); + + return -RT_EIO; +} + +INIT_DEVICE_EXPORT(raspi_sdmmc_init); diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.h b/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.h new file mode 100644 index 0000000000000000000000000000000000000000..5c052de90a54df9d96f396f497a73f79c516dfc4 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.h @@ -0,0 +1,253 @@ +/* + * File : drv_sdio.h + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#ifndef __DRV_SDIO_H__ +#define __DRV_SDIO_H__ + +#include +#include +#include + +#include "board.h" + +#define MMC0_BASE_ADDR 0x3F300000 + +/* Struct for Intrrrupt Information */ +#define SDXC_CmdDone BIT(0) +#define SDXC_DataDone BIT(1) +#define SDXC_BlockGap BIT(2) +#define SDXC_WriteRdy BIT(4) +#define SDXC_ReadRdy BIT(5) +#define SDXC_Card BIT(8) +#define SDXC_Retune BIT(12) +#define SDXC_BootAck BIT(13) +#define SDXC_EndBoot BIT(14) +#define SDXC_Err BIT(15) +#define SDXC_CTOErr BIT(16) +#define SDXC_CCRCErr BIT(17) +#define SDXC_CENDErr BIT(18) +#define SDXC_CBADErr BIT(19) +#define SDXC_DTOErr BIT(20) +#define SDXC_DCRCErr BIT(21) +#define SDXC_DENDErr BIT(22) +#define SDXC_ACMDErr BIT(24) + +#define SDXC_BLKCNT_EN BIT(1) +#define SDXC_AUTO_CMD12_EN BIT(2) +#define SDXC_AUTO_CMD23_EN BIT(3) +#define SDXC_DAT_DIR BIT(4) //from card to host +#define SDXC_MULTI_BLOCK BIT(5) +#define SDXC_CMD_RSPNS_136 BIT(16) +#define SDXC_CMD_RSPNS_48 BIT(17) +#define SDXC_CMD_RSPNS_48busy BIT(16)|BIT(17) +#define SDXC_CHECK_CRC_CMD BIT(19) +#define SDXC_CMD_IXCHK_EN BIT(20) +#define SDXC_CMD_ISDATA BIT(21) +#define SDXC_CMD_SUSPEND BIT(22) +#define SDXC_CMD_RESUME BIT(23) +#define SDXC_CMD_ABORT BIT(23)|BIT(22) + +#define SDXC_CMD_INHIBIT BIT(0) +#define SDXC_DAT_INHIBIT BIT(1) +#define SDXC_DAT_ACTIVE BIT(2) +#define SDXC_WRITE_TRANSFER BIT(8) +#define SDXC_READ_TRANSFER BIT(9) + +struct sdhci_cmd_t +{ + rt_uint32_t cmdidx; + rt_uint32_t cmdarg; + rt_uint32_t resptype; + rt_uint32_t datarw; +#define DATA_READ 1 +#define DATA_WRITE 2 + rt_uint32_t response[4]; +}; + +struct sdhci_data_t +{ + rt_uint8_t * buf; + rt_uint32_t flag; + rt_uint32_t blksz; + rt_uint32_t blkcnt; +}; + +struct sdhci_t +{ + char * name; + rt_uint32_t voltages; + rt_uint32_t width; + rt_uint32_t clock; + rt_err_t removeable; + void * sdcard; + + rt_err_t (*detect)(struct sdhci_t * sdhci); + rt_err_t (*setwidth)(struct sdhci_t * sdhci, rt_uint32_t width); + rt_err_t (*setclock)(struct sdhci_t * sdhci, rt_uint32_t clock); + rt_err_t (*transfer)(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat); + void * priv; +}; + +struct sdhci_pdata_t +{ + rt_uint32_t virt; +}; + +// EMMC command flags +#define CMD_TYPE_NORMAL 0x00000000 +#define CMD_TYPE_SUSPEND 0x00400000 +#define CMD_TYPE_RESUME 0x00800000 +#define CMD_TYPE_ABORT 0x00c00000 +#define CMD_IS_DATA 0x00200000 +#define CMD_IXCHK_EN 0x00100000 +#define CMD_CRCCHK_EN 0x00080000 +#define CMD_RSPNS_NO 0x00000000 +#define CMD_RSPNS_136 0x00010000 +#define CMD_RSPNS_48 0x00020000 +#define CMD_RSPNS_48B 0x00030000 +#define TM_MULTI_BLOCK 0x00000020 +#define TM_DAT_DIR_HC 0x00000000 +#define TM_DAT_DIR_CH 0x00000010 +#define TM_AUTO_CMD23 0x00000008 +#define TM_AUTO_CMD12 0x00000004 +#define TM_BLKCNT_EN 0x00000002 +#define TM_MULTI_DATA (CMD_IS_DATA|TM_MULTI_BLOCK|TM_BLKCNT_EN) + +#define RCA_NO 1 +#define RCA_YES 2 + +// INTERRUPT register settings +#define INT_AUTO_ERROR 0x01000000 +#define INT_DATA_END_ERR 0x00400000 +#define INT_DATA_CRC_ERR 0x00200000 +#define INT_DATA_TIMEOUT 0x00100000 +#define INT_INDEX_ERROR 0x00080000 +#define INT_END_ERROR 0x00040000 +#define INT_CRC_ERROR 0x00020000 +#define INT_CMD_TIMEOUT 0x00010000 +#define INT_ERR 0x00008000 +#define INT_ENDBOOT 0x00004000 +#define INT_BOOTACK 0x00002000 +#define INT_RETUNE 0x00001000 +#define INT_CARD 0x00000100 +#define INT_READ_RDY 0x00000020 +#define INT_WRITE_RDY 0x00000010 +#define INT_BLOCK_GAP 0x00000004 +#define INT_DATA_DONE 0x00000002 +#define INT_CMD_DONE 0x00000001 +#define INT_ERROR_MASK (INT_CRC_ERROR|INT_END_ERROR|INT_INDEX_ERROR| \ + INT_DATA_TIMEOUT|INT_DATA_CRC_ERR|INT_DATA_END_ERR| \ + INT_ERR|INT_AUTO_ERROR) +#define INT_ALL_MASK (INT_CMD_DONE|INT_DATA_DONE|INT_READ_RDY|INT_WRITE_RDY|INT_ERROR_MASK) + +#define EMMC_ARG2 (0x00) +#define EMMC_BLKSIZECNT (0x04) +#define EMMC_ARG1 (0x08) +#define EMMC_CMDTM (0x0c) +#define EMMC_RESP0 (0x10) +#define EMMC_RESP1 (0x14) +#define EMMC_RESP2 (0x18) +#define EMMC_RESP3 (0x1c) +#define EMMC_DATA (0x20) +#define EMMC_STATUS (0x24) +#define EMMC_CONTROL0 (0x28) +#define EMMC_CONTROL1 (0x2c) +#define EMMC_INTERRUPT (0x30) +#define EMMC_IRPT_MASK (0x34) +#define EMMC_IRPT_EN (0x38) +#define EMMC_CONTROL2 (0x3c) +#define EMMC_BOOT_TIMEOUT (0x70) +#define EMMC_EXRDFIFO_EN (0x84) +#define EMMC_SPI_INT_SPT (0xf0) +#define EMMC_SLOTISR_VER (0xfc) + +// CONTROL register settings +#define C0_SPI_MODE_EN 0x00100000 +#define C0_HCTL_HS_EN 0x00000004 +#define C0_HCTL_DWITDH 0x00000002 + +#define C1_SRST_DATA 0x04000000 +#define C1_SRST_CMD 0x02000000 +#define C1_SRST_HC 0x01000000 +#define C1_TOUNIT_DIS 0x000f0000 +#define C1_TOUNIT_MAX 0x000e0000 +#define C1_CLK_GENSEL 0x00000020 +#define C1_CLK_EN 0x00000004 +#define C1_CLK_STABLE 0x00000002 +#define C1_CLK_INTLEN 0x00000001 + +#define FREQ_SETUP 400000 // 400 Khz +#define FREQ_NORMAL 25000000 // 25 Mhz + +// SLOTISR_VER values +#define HOST_SPEC_NUM 0x00ff0000 +#define HOST_SPEC_NUM_SHIFT 16 +#define HOST_SPEC_V3 2 +#define HOST_SPEC_V2 1 +#define HOST_SPEC_V1 0 + +// STATUS register settings +#define SR_DAT_LEVEL1 0x1e000000 +#define SR_CMD_LEVEL 0x01000000 +#define SR_DAT_LEVEL0 0x00f00000 +#define SR_DAT3 0x00800000 +#define SR_DAT2 0x00400000 +#define SR_DAT1 0x00200000 +#define SR_DAT0 0x00100000 +#define SR_WRITE_PROT 0x00080000 // From SDHC spec v2, BCM says reserved +#define SR_READ_AVAILABLE 0x00000800 // ???? undocumented +#define SR_WRITE_AVAILABLE 0x00000400 // ???? undocumented +#define SR_READ_TRANSFER 0x00000200 +#define SR_WRITE_TRANSFER 0x00000100 +#define SR_DAT_ACTIVE 0x00000004 +#define SR_DAT_INHIBIT 0x00000002 +#define SR_CMD_INHIBIT 0x00000001 + +#define CONFIG_MMC_USE_DMA +#define DMA_ALIGN (32U) + +#define SD_CMD_INDEX(a) ((a) << 24) +#define SD_CMD_RESERVED(a) 0xffffffff +#define SD_CMD_INDEX(a) ((a) << 24) +#define SD_CMD_TYPE_NORMAL 0x0 +#define SD_CMD_TYPE_SUSPEND (1 << 22) +#define SD_CMD_TYPE_RESUME (2 << 22) +#define SD_CMD_TYPE_ABORT (3 << 22) +#define SD_CMD_TYPE_MASK (3 << 22) +#define SD_CMD_ISDATA (1 << 21) +#define SD_CMD_IXCHK_EN (1 << 20) +#define SD_CMD_CRCCHK_EN (1 << 19) +#define SD_CMD_RSPNS_TYPE_NONE 0 // For no response +#define SD_CMD_RSPNS_TYPE_136 (1 << 16) // For response R2 (with CRC), R3,4 (no CRC) +#define SD_CMD_RSPNS_TYPE_48 (2 << 16) // For responses R1, R5, R6, R7 (with CRC) +#define SD_CMD_RSPNS_TYPE_48B (3 << 16) // For responses R1b, R5b (with CRC) +#define SD_CMD_RSPNS_TYPE_MASK (3 << 16) +#define SD_CMD_MULTI_BLOCK (1 << 5) +#define SD_CMD_DAT_DIR_HC 0 +#define SD_CMD_DAT_DIR_CH (1 << 4) +#define SD_CMD_AUTO_CMD_EN_NONE 0 +#define SD_CMD_AUTO_CMD_EN_CMD12 (1 << 2) +#define SD_CMD_AUTO_CMD_EN_CMD23 (2 << 2) +#define SD_CMD_BLKCNT_EN (1 << 1) +#define SD_CMD_DMA 1 +#define SD_RESP_NONE SD_CMD_RSPNS_TYPE_NONE +#define SD_RESP_R1 (SD_CMD_RSPNS_TYPE_48) // | SD_CMD_CRCCHK_EN) +#define SD_RESP_R1b (SD_CMD_RSPNS_TYPE_48B) // | SD_CMD_CRCCHK_EN) +#define SD_RESP_R2 (SD_CMD_RSPNS_TYPE_136) //| SD_CMD_CRCCHK_EN) +#define SD_RESP_R3 SD_CMD_RSPNS_TYPE_48 +#define SD_RESP_R4 SD_CMD_RSPNS_TYPE_136 +#define SD_RESP_R5 (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN) +#define SD_RESP_R5b (SD_CMD_RSPNS_TYPE_48B | SD_CMD_CRCCHK_EN) +#define SD_RESP_R6 (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN) +#define SD_RESP_R7 (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN) +#define SD_DATA_READ (SD_CMD_ISDATA | SD_CMD_DAT_DIR_CH) +#define SD_DATA_WRITE (SD_CMD_ISDATA | SD_CMD_DAT_DIR_HC) +#endif diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_spi.c b/bsp/raspberry-pi/raspi3-32/driver/drv_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..eab7a08b392cda253df6893fe392a45d0e489fc2 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_spi.c @@ -0,0 +1,286 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ +#include "drv_spi.h" + +#ifdef RT_USING_SPI + +#define RPI_CORE_CLK_HZ 250000000 +#define BSP_SPI_MAX_HZ (30* 1000 *1000) +#define SPITIMEOUT 0x0FFF + +void spi_gpio_write(rt_uint8_t pin, rt_uint8_t val) +{ + if (val) + BCM283X_GPIO_GPSET((pin / 32)) = 1 << (pin % 32); + else + BCM283X_GPIO_GPCLR((pin / 32)) = 1 << (pin % 32); +} + +struct raspi_spi_hw_config +{ + rt_uint8_t spi_num; + raspi_gpio_pin sclk_pin; + raspi_pin_select sclk_mode; + raspi_gpio_pin mosi_pin; + raspi_pin_select mosi_mode; + raspi_gpio_pin miso_pin; + raspi_pin_select miso_mode; +#if defined (BSP_USING_SPI0_DEVICE0) || defined (BSP_USING_SPI1_DEVICE0) + raspi_gpio_pin ce0_pin; + raspi_pin_select ce0_mode; +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) || defined (BSP_USING_SPI1_DEVICE1) + raspi_gpio_pin ce1_pin; + raspi_pin_select ce1_mode; +#endif + +#if defined (BSP_USING_SPI1_DEVICE2) + raspi_gpio_pin ce2_pin; + raspi_pin_select ce2_mode; +#endif +}; + +struct raspi_spi_device +{ + char *device_name; + struct rt_spi_bus *spi_bus; + struct rt_spi_device *spi_device; + raspi_gpio_pin cs_pin; +}; + +static rt_err_t raspi_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) +{ + RT_ASSERT(cfg != RT_NULL); + RT_ASSERT(device != RT_NULL); + rt_uint16_t divider; + + // spi clear fifo + BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= BCM283X_SPI0_CS_CLEAR; + + if (cfg->mode & RT_SPI_CPOL) + BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= BCM283X_SPI0_CS_CPOL; + + if (cfg->mode & RT_SPI_CPHA) + BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= BCM283X_SPI0_CS_CPHA; + + if (cfg->mode & RT_SPI_CS_HIGH) + BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= BCM283X_SPI0_CS_CSPOL; + + //set clk + if (cfg->max_hz > BSP_SPI_MAX_HZ) + cfg->max_hz = BSP_SPI_MAX_HZ; + + divider = (rt_uint16_t) ((rt_uint32_t) RPI_CORE_CLK_HZ / cfg->max_hz); + divider &= 0xFFFE; + + BCM283X_SPI0_CLK(BCM283X_SPI0_BASE) = divider; + + return RT_EOK; +} + +rt_uint8_t correct_order(rt_uint8_t b, rt_uint8_t flag) +{ + if (flag) + return raspi_byte_reverse_table[b]; + else + return b; +} + +static rt_err_t spi_transfernb(rt_uint8_t* tbuf, rt_uint8_t* rbuf, rt_uint32_t len, rt_uint8_t flag) +{ + rt_uint32_t TXCnt=0; + rt_uint32_t RXCnt=0; + + /* Clear TX and RX fifos */ + BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= (BCM283X_SPI0_CS_CLEAR & BCM283X_SPI0_CS_CLEAR); + + /* Set TA = 1 */ + BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= (BCM283X_SPI0_CS_TA & BCM283X_SPI0_CS_TA); + + + /* Use the FIFO's to reduce the interbyte times */ + while ((TXCnt < len) || (RXCnt < len)) + { + /* TX fifo not full, so add some more bytes */ + while (((BCM283X_SPI0_CS(BCM283X_SPI0_BASE) & BCM283X_SPI0_CS_TXD)) && (TXCnt < len)) + { + BCM283X_SPI0_FIFO(BCM283X_SPI0_BASE) = correct_order(tbuf[TXCnt],flag); + TXCnt++; + } + /* Rx fifo not empty, so get the next received bytes */ + while (((BCM283X_SPI0_CS(BCM283X_SPI0_BASE) & BCM283X_SPI0_CS_RXD)) && (RXCnt < len)) + { + rbuf[RXCnt] = correct_order(BCM283X_SPI0_FIFO(BCM283X_SPI0_BASE),flag); + RXCnt++; + } + } + /* Wait for DONE to be set */ + while (!(BCM283X_SPI0_CS(BCM283X_SPI0_BASE) & BCM283X_SPI0_CS_DONE)); + + /* Set TA = 0, and also set the barrier */ + BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= (0 & BCM283X_SPI0_CS_TA); + return RT_EOK; +} + +static rt_uint32_t raspi_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->parent.user_data != RT_NULL); + RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL); + + rt_err_t res; + rt_uint8_t flag; + struct rt_spi_configuration config = device->config; + raspi_gpio_pin cs_pin = (raspi_gpio_pin)device->parent.user_data; + + if (config.mode & RT_SPI_MSB) + flag = 0; + else + flag = 1; + if (message->cs_take); + // (config.mode & RT_SPI_CS_HIGH)? + // spi_gpio_write(cs_pin, 1): + // spi_gpio_write(cs_pin, 0); + + /* deal data */ + res = spi_transfernb((rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, + (rt_int32_t)message->length, flag); + + if (message->cs_release) + (config.mode & RT_SPI_CS_HIGH)? + spi_gpio_write(cs_pin, 0): + spi_gpio_write(cs_pin, 1); + + if (res != RT_EOK) + return RT_ERROR; + + return message->length; +} + +rt_err_t raspi_spi_bus_attach_device(const char *bus_name, struct raspi_spi_device *device) +{ + rt_err_t ret; + RT_ASSERT(device != RT_NULL); + ret = rt_spi_bus_attach_device(device->spi_device, device->device_name, bus_name, (void *)(device->cs_pin)); + return ret; +} + +rt_err_t raspi_spi_hw_init(struct raspi_spi_hw_config *hwcfg) +{ + GPIO_FSEL(hwcfg->sclk_pin, hwcfg->sclk_mode); + GPIO_FSEL(hwcfg->miso_pin, hwcfg->miso_mode); + GPIO_FSEL(hwcfg->mosi_pin, hwcfg->mosi_mode); + +#if defined (BSP_USING_SPI0_DEVICE0) + GPIO_FSEL(hwcfg->ce0_pin, hwcfg->ce0_mode); +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) + GPIO_FSEL(hwcfg->ce1_pin, hwcfg->ce1_mode); +#endif + + BCM283X_SPI0_CS(BCM283X_SPI0_BASE) = 0; + BCM283X_SPI0_CS(BCM283X_SPI0_BASE) = BCM283X_SPI0_CS_CLEAR; + + //enable chip select +#if defined (BSP_USING_SPI0_DEVICE0) + BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= 0; +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) + BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= 0x2; +#endif + +#if defined (BSP_USING_SPI0_DEVICE0) && defined (BSP_USING_SPI0_DEVICE1) + BCM283X_SPI0_CS(BCM283X_SPI0_BASE) |= BCM283X_SPI0_CS_CS; +#endif + return RT_EOK; +} + +static struct rt_spi_ops raspi_spi_ops = +{ + .configure = raspi_spi_configure, + .xfer = raspi_spi_xfer +}; + +#if defined (BSP_USING_SPI0_BUS) +#define SPI0_BUS_NAME "spi0" +#define SPI0_DEVICE0_NAME "spi0.0" +#define SPI0_DEVICE1_NAME "spi0.1" + +struct rt_spi_bus spi0_bus; + +#if defined (BSP_USING_SPI0_DEVICE0) +struct rt_spi_device spi0_device0; +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) +static struct rt_spi_device spi0_device1; +#endif + +struct raspi_spi_hw_config raspi_spi0_hw = +{ + .spi_num = 0, + .sclk_pin = RPI_GPIO_P1_23, + .sclk_mode = BCM283X_GPIO_FSEL_ALT0, + .mosi_pin = RPI_GPIO_P1_19, + .mosi_mode = BCM283X_GPIO_FSEL_ALT0, + .miso_pin = RPI_GPIO_P1_21, + .miso_mode = BCM283X_GPIO_FSEL_ALT0, + +#if defined (BSP_USING_SPI0_DEVICE0) + .ce0_pin = RPI_GPIO_P1_24, + .ce0_mode = BCM283X_GPIO_FSEL_ALT0, +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) + .ce1_pin = RPI_GPIO_P1_26, + .ce1_mode = BCM283X_GPIO_FSEL_ALT0, +#endif +}; +#endif + +int rt_hw_spi_init(void) +{ + +#if defined (BSP_USING_SPI0_BUS) + raspi_spi_hw_init(&raspi_spi0_hw); + rt_spi_bus_register(&spi0_bus, SPI0_BUS_NAME, &raspi_spi_ops); + +#if defined (BSP_USING_SPI0_DEVICE0) + struct raspi_spi_device raspi_spi0_device0 = + { + .device_name = SPI0_DEVICE0_NAME, + .spi_bus = &spi0_bus, + .spi_device = &spi0_device0, + .cs_pin = raspi_spi0_hw.ce0_pin, + }; + raspi_spi_bus_attach_device(SPI0_BUS_NAME, &raspi_spi0_device0); +#endif + +#if defined (BSP_USING_SPI0_DEVICE1) + struct raspi_spi_device raspi_spi0_device1 = + { + .device_name = SPI0_DEVICE1_NAME, + .spi_bus = &spi0_bus, + .spi_device = &spi0_device1, + .cs_pin = raspi_spi0_hw.ce1_pin, + }; + raspi_spi_bus_attach_device(SPI0_BUS_NAME, &raspi_spi0_device1); +#endif +#endif + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_spi_init); + +#endif diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_spi.h b/bsp/raspberry-pi/raspi3-32/driver/drv_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..9e4623b327909f16b2b9128b6e4320708b329a31 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_spi.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include +#include + +//#include +#include "board.h" + +#define SPI0_BASE_ADDR (PER_BASE + BCM283X_SPI0_BASE) + +static rt_uint8_t raspi_byte_reverse_table[] = +{ + 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, + 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, + 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, + 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8, + 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, + 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, + 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, + 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc, + 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2, + 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, + 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, + 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, + 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6, + 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6, + 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, + 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, + 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, + 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1, + 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9, + 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, + 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, + 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, + 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed, + 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd, + 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, + 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, + 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, + 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb, + 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7, + 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, + 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, + 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff +}; + +#define SPI_CORE_CLK 250000000U +#define SPI_CS 0x00 +#define SPI_CS_LEN_LONG (1 << 25) +#define SPI_CS_DMA_LEN (1 << 24) +#define SPI_CS_CSPOL2 (1 << 23) +#define SPI_CS_CSPOL1 (1 << 22) +#define SPI_CS_CSPOL0 (1 << 21) +#define SPI_CS_RXF (1 << 20) +#define SPI_CS_RXR (1 << 19) +#define SPI_CS_TXD (1 << 18) +#define SPI_CS_RXD (1 << 17) +#define SPI_CS_DONE (1 << 16) +#define SPI_CS_LEN (1 << 13) +#define SPI_CS_REN (1 << 12) +#define SPI_CS_ADCS (1 << 11) +#define SPI_CS_INTR (1 << 10) +#define SPI_CS_INTD (1 << 9) +#define SPI_CS_DMAEN (1 << 8) +#define SPI_CS_TA (1 << 7) +#define SPI_CS_CSPOL (1 << 6) +#define SPI_CS_CLEAR_RXFIFO (1 << 5) +#define SPI_CS_CLEAR_TXFIFO (1 << 4) +#define SPI_CS_CPOL (1 << 3) +#define SPI_CS_CPHA (1 << 2) +#define SPI_CS_MASK 0x3 +#define SPI_FIFO 0x04 +#define SPI_CLK 0x08 +#define SPI_CLK_MASK 0xffff +#define SPI_DLEN 0x0c +#define SPI_DLEN_MASK 0xffff +#define SPI_LTOH 0x10 +#define SPI_LTOH_MASK 0xf +#define SPI_DC 0x14 +#define SPI_DC_RPANIC_SHIFT 24 +#define SPI_DC_RPANIC_MASK (0xff << SPI_DC_RPANIC_SHIFT) +#define SPI_DC_RDREQ_SHIFT 16 +#define SPI_DC_RDREQ_MASK (0xff << SPI_DC_RDREQ_SHIFT) +#define SPI_DC_TPANIC_SHIFT 8 +#define SPI_DC_TPANIC_MASK (0xff << SPI_DC_TPANIC_SHIFT) +#define SPI_DC_TDREQ_SHIFT 0 +#define SPI_DC_TDREQ_MASK 0xff + +int rt_hw_spi_init(void); + +#endif diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..36a4fd2bafe2f82e0197916268c2f83716ecbfe1 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#include "drv_timer.h" + +#ifdef BSP_USING_SYSTIMER + +static void raspi_systimer_init(rt_hwtimer_t *hwtimer, rt_uint32_t state) +{ + if (state == 0) + hwtimer->ops->stop(hwtimer); +} + +static rt_err_t raspi_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +{ + rt_err_t result = RT_EOK; + rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data; + int timer_id = timer->timer_id; + + if (mode == HWTIMER_MODE_PERIOD) + timer->cnt = cnt; + else + timer->cnt = 0; + + __sync_synchronize(); + if (timer_id == 1) + { + rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_1); + STIMER_C1 = STIMER_CLO + cnt; + } + else if (timer_id == 3) + { + rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_3); + STIMER_C3 = STIMER_CLO + cnt; + } + else + result = -RT_ERROR; + + __sync_synchronize(); + + return result; +} + +static void raspi_systimer_stop(rt_hwtimer_t *hwtimer) +{ + rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data; + int timer_id = timer->timer_id; + if (timer_id == 1) + rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_1); + else if (timer_id == 3) + rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_3); + +} + +static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +{ + /* The frequency value is an immutable value. */ + if (cmd == HWTIMER_CTRL_FREQ_SET) + { + return RT_EOK; + } + else + { + return -RT_ENOSYS; + } +} + + +void rt_device_systimer_isr(int vector, void *param) +{ + + rt_hwtimer_t *hwtimer = (rt_hwtimer_t *) param; + rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data; + RT_ASSERT(timer != RT_NULL); + + int timer_id = timer->timer_id; + + __sync_synchronize(); + if (timer_id == 1) + { + STIMER_CS = 0x2; + STIMER_C1 = STIMER_CLO + timer->cnt; + } + else if (timer_id == 3) + { + STIMER_CS = 0x8; + STIMER_C3 = STIMER_CLO + timer->cnt; + } + __sync_synchronize(); + + rt_device_hwtimer_isr(hwtimer); +} + +static struct rt_hwtimer_device _hwtimer1; +static struct rt_hwtimer_device _hwtimer3; + +static rt_systimer_t _systimer1; +static rt_systimer_t _systimer3; + +const static struct rt_hwtimer_ops systimer_ops = +{ + raspi_systimer_init, + raspi_systimer_start, + raspi_systimer_stop, + RT_NULL, + raspi_systimer_ctrl +}; + +static const struct rt_hwtimer_info _info = +{ + 1000000, /* the maxinum count frequency can be set */ + 1000000, /* the maxinum count frequency can be set */ + 0xFFFFFFFF, /* the maximum counter value */ + HWTIMER_CNTMODE_UP /* count mode (inc/dec) */ +}; + +#endif + +int rt_hw_systimer_init(void) +{ + +#ifdef BSP_USING_SYSTIMER + +#ifdef RT_USING_SYSTIMER1 + _systimer1.timer_id =1; + _hwtimer1.ops = &systimer_ops; + _hwtimer1.info = &_info; + rt_device_hwtimer_register(&_hwtimer1, "timer1",&_systimer1); + rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_1, rt_device_systimer_isr, &_hwtimer1, "systimer1"); + rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_1); +#endif + +#ifdef RT_USING_SYSTIMER3 + _systimer3.timer_id =3; + _hwtimer3.ops = &systimer_ops; + _hwtimer3.info = &_info; + rt_device_hwtimer_register(&_hwtimer3, "timer3",&_systimer3); + rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_3, rt_device_systimer_isr, &_hwtimer3, "systimer3"); + rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_3); +#endif + +#endif + + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_systimer_init); diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_timer.h b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..c85d4c9d1f7a8c0b0ff386e87c5e2bb60b5cdef9 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ +#ifndef __DRV_TIMER_H__ +#define __DRV_TIMER_H__ + +#include +#include + +#include "board.h" + +typedef struct rt_systimer_device +{ + int timer_id; + rt_uint32_t cnt; +} rt_systimer_t; + +int rt_hw_systimer_init(void); + + +#endif diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_uart.c b/bsp/raspberry-pi/raspi3-32/driver/drv_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..18501b78491460ce9a4fc5669442618c38203418 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_uart.c @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/5/5 Bernard The first version + */ + +#include +#include +#include + +#include "board.h" +#include "drv_uart.h" + +#include + +#define AUX_BASE (0x3F000000 + 0x215000) + +struct hw_uart_device +{ + rt_uint32_t hw_base; + rt_uint32_t irqno; +}; + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + if (uart->hw_base == AUX_BASE) + { + rt_uint32_t value; + + /* GPIO function set */ + value = BCM283X_GPIO_GPFSEL(1); + value &= ~(7 << 12); /* GPIO14 */ + value |= 2 << 12 ; /* ALT5 */ + value &= ~(7 << 15); /* GPIO15 */ + value |= 2 << 15 ; /* ALT5 */ + BCM283X_GPIO_GPFSEL(1) = value; + + BCM283X_GPIO_GPPUD = 0; + BCM283X_GPIO_GPPUDCLK(0) = (1 << 14) | (1 << 15); + BCM283X_GPIO_GPPUDCLK(0) = 0; + + AUX_ENABLES(uart->hw_base) = 1; /* Enable UART1 */ + AUX_MU_IER_REG(uart->hw_base) = 0; /* Disable interrupt */ + AUX_MU_CNTL_REG(uart->hw_base) = 0; /* Disable Transmitter and Receiver */ + AUX_MU_LCR_REG(uart->hw_base) = 3; /* Works in 8-bit mode */ + AUX_MU_MCR_REG(uart->hw_base) = 0; /* Disable RTS */ + AUX_MU_IIR_REG(uart->hw_base) = 0xC6; /* Enable FIFO, Clear FIFO */ + AUX_MU_BAUD_REG(uart->hw_base) = 270; /* 115200 = system clock 250MHz / (8 * (baud + 1)), baud = 270 */ + AUX_MU_CNTL_REG(uart->hw_base) = 3; /* Enable Transmitter and Receiver */ + } + + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + AUX_MU_IER_REG(uart->hw_base) = 0x0; + rt_hw_interrupt_mask(uart->irqno); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + AUX_MU_IER_REG(uart->hw_base) = 0x1; + rt_hw_interrupt_umask(uart->irqno); + break; + } + + return RT_EOK; +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + while (!(AUX_MU_LSR_REG(uart->hw_base) & 0x20)); + AUX_MU_IO_REG(uart->hw_base) = c; + + return 1; +} + +static int uart_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + if ((AUX_MU_LSR_REG(uart->hw_base) & 0x01)) + { + ch = AUX_MU_IO_REG(uart->hw_base) & 0xff; + } + + return ch; +} + +static const struct rt_uart_ops _uart_ops = +{ + uart_configure, + uart_control, + uart_putc, + uart_getc, +}; + +static void rt_hw_uart_isr(int irqno, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device*)param; + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); +} + +#ifdef RT_USING_UART0 +/* UART device driver structure */ +static struct hw_uart_device _uart0_device = +{ + RPI_UART0_BASE, + IRQ_PBA8_UART0, +}; +static struct rt_serial_device _serial0; +#endif + +#ifdef RT_USING_UART1 +/* UART1 device driver structure */ +static struct hw_uart_device _uart1_device = +{ + AUX_BASE, + IRQ_AUX, +}; +static struct rt_serial_device _serial1; +#endif + +int rt_hw_uart_init(void) +{ + struct hw_uart_device *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + +#ifdef RT_USING_UART0 + uart = &_uart0_device; + + _serial0.ops = &_uart_ops; + _serial0.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&_serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart0"); +#endif + +#ifdef RT_USING_UART1 + uart = &_uart1_device; + _serial1.ops = &_uart_ops; + _serial1.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&_serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); + /* enable Rx and Tx of UART */ + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial1, "uart1"); +#endif + + return 0; +} diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_uart.h b/bsp/raspberry-pi/raspi3-32/driver/drv_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..5211c19989e486e5270f2d35e67711abd7d80368 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_uart.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-5-30 Bernard the first version + */ + +#ifndef DRV_UART_H__ +#define DRV_UART_H__ + +/* + * Auxiliary + */ +#define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */ +#define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */ +#define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */ +#define AUX_MU_IER_REG(BASE) HWREG32(BASE + 0x44) /* Mini Uart Interrupt Enable 8bit */ +#define AUX_MU_IIR_REG(BASE) HWREG32(BASE + 0x48) /* Mini Uart Interrupt Identify 8bit */ +#define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */ +#define AUX_MU_MCR_REG(BASE) HWREG32(BASE + 0x50) /* Mini Uart Modem Control 8bit */ +#define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */ +#define AUX_MU_MSR_REG(BASE) HWREG32(BASE + 0x58) /* Mini Uart Modem Status 8bit */ +#define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */ +#define AUX_MU_CNTL_REG(BASE) HWREG32(BASE + 0x60) /* Mini Uart Extra Control 8bit */ +#define AUX_MU_STAT_REG(BASE) HWREG32(BASE + 0x64) /* Mini Uart Extra Status 32bit */ +#define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */ +#define AUX_SPI0_CNTL0_REG(BASE) HWREG32(BASE + 0x80) /* SPI 1 Control register 0 32bit */ +#define AUX_SPI0_CNTL1_REG(BASE) HWREG32(BASE + 0x84) /* SPI 1 Control register 1 8bit */ +#define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */ +#define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */ +#define AUX_SPI0_PEEK_REG(BASE) HWREG32(BASE + 0x94) /* SPI 1 Peek 16bit */ +#define AUX_SPI1_CNTL0_REG(BASE) HWREG32(BASE + 0xC0) /* SPI 2 Control register 0 32bit */ +#define AUX_SPI1_CNTL1_REG(BASE) HWREG32(BASE + 0xC4) /* SPI 2 Control register 1 8bit */ + +int rt_hw_uart_init(void); + +#endif /* DRV_UART_H__ */ + diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c b/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..31b242fab5c2a6cd2cadb2b1bdc99415e554a216 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ +#include "drv_wdt.h" + +#ifdef BSP_USING_WDT + +#define SECS_TO_WDOG_TICKS(x) ((x) << 16) +#define WDOG_TICKS_TO_SECS(x) ((x) >> 16) + +static struct raspi_wdt_driver bcm_wdt; + +void raspi_watchdog_init(rt_uint32_t time_init) +{ + bcm_wdt.timeout = time_init; +} + +void raspi_watchdog_start() +{ + volatile rt_uint32_t cur; + PM_WDOG = PM_PASSWORD | (SECS_TO_WDOG_TICKS(bcm_wdt.timeout) & PM_WDOG_TIME_SET); + cur = PM_RSTC; + PM_RSTC = PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET; +} + +void raspi_watchdog_stop() +{ + PM_RSTC = PM_PASSWORD | PM_RSTC_RESET; +} + +void raspi_watchdog_clr() +{ + bcm_wdt.timeout = 0; +} + +void raspi_watchdog_set_timeout(rt_uint32_t timeout_us) +{ + bcm_wdt.timeout = timeout_us; +} + +rt_uint64_t raspi_watchdog_get_timeout() +{ + return bcm_wdt.timeout; +} + +rt_uint64_t raspi_watchdog_get_timeleft() +{ + rt_uint32_t ret = PM_WDOG; + return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET); +} + +static rt_err_t raspi_wdg_init(rt_watchdog_t *wdt) +{ + /*init for 10S*/ + raspi_watchdog_init(1000000); + raspi_watchdog_start(); + raspi_watchdog_stop(); + return RT_EOK; +} + +static rt_err_t raspi_wdg_control(rt_watchdog_t *wdt, int cmd, void *arg) +{ + rt_uint64_t timeout_us = 0; + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + timeout_us = *((rt_uint32_t *)arg) * 1000000; + if (timeout_us >= 0xFFFFFFFF) + timeout_us = 0xFFFFFFFF; + raspi_watchdog_set_timeout((rt_uint32_t)timeout_us); + break; + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + timeout_us = raspi_watchdog_get_timeout(); + *((rt_uint32_t *)arg) = timeout_us / 1000000; + break; + case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: + timeout_us = raspi_watchdog_get_timeleft(); + *((rt_uint32_t *)arg) = timeout_us / 1000000; + break; + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + raspi_watchdog_clr(); + break; + case RT_DEVICE_CTRL_WDT_START: + raspi_watchdog_start(); + break; + case RT_DEVICE_CTRL_WDT_STOP: + raspi_watchdog_stop(); + break; + default: + return RT_EIO; + } + return RT_EOK; +} + +static const struct rt_watchdog_ops raspi_wdg_pos = +{ + raspi_wdg_init, + raspi_wdg_control, +}; + +static rt_watchdog_t raspi_wdg; + +int rt_hw_wdt_init(void) +{ + raspi_wdg.ops = &raspi_wdg_pos; + rt_hw_watchdog_register(&raspi_wdg, "wdg", 0, RT_NULL); + return RT_EOK; +} + +INIT_DEVICE_EXPORT(rt_hw_wdt_init); +#endif /*BSP_USING_WDT */ diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.h b/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.h new file mode 100644 index 0000000000000000000000000000000000000000..0b59ab79f3dc111b0cb6d4e8a09aef81e78242b3 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#ifndef __DRV_WDT_H__ +#define __DRV_WDT_H__ + +#include +#include + +#include "board.h" + +struct raspi_wdt_driver +{ + rt_uint32_t timeout; +}; + +int rt_hw_wdt_init(void); + +#endif diff --git a/bsp/raspberry-pi/raspi3-32/driver/mbox.c b/bsp/raspberry-pi/raspi3-32/driver/mbox.c new file mode 100644 index 0000000000000000000000000000000000000000..bbd5183aa8c1b8e53a2108dd6ef694c5c528fc03 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/mbox.c @@ -0,0 +1,54 @@ +/* + * File : mbox.c + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-08-29 zdzn first version + */ + +/* mailbox message buffer */ +#include "mbox.h" +#include "mmu.h" + +volatile unsigned int *mbox = (volatile unsigned int *) MBOX_ADDR; +/** + * Make a mailbox call. Returns 0 on failure, non-zero on success + */ +void init_mbox_mmu_map() +{ + rt_hw_change_mmu_table(MBOX_ADDR, 96, MBOX_ADDR, STRONG_ORDER_MEM); +} + +int mbox_call(unsigned char ch, int mmu_enable) +{ + unsigned int r = (((MBOX_ADDR)&~0xF) | (ch&0xF)); + if (mmu_enable) + r = BUS_ADDRESS(r); + /* wait until we can write to the mailbox */ + do + { + asm volatile("nop"); + } while (*MBOX_STATUS & MBOX_FULL); + /* write the address of our message to the mailbox with channel identifier */ + *MBOX_WRITE = r; + /* now wait for the response */ + while (1) + { + /* is there a response? */ + do + { + asm volatile("nop"); + } + while (*MBOX_STATUS & MBOX_EMPTY); + /* is it a response to our message? */ + if (r == *MBOX_READ) + { + /* is it a valid successful response? */ + return mbox[1] == MBOX_RESPONSE; + } + } + return 0; +} diff --git a/bsp/raspberry-pi/raspi3-32/driver/mbox.h b/bsp/raspberry-pi/raspi3-32/driver/mbox.h new file mode 100644 index 0000000000000000000000000000000000000000..5c59fd608c10bf0c250ab338c6e5f1641f7b8dcd --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/mbox.h @@ -0,0 +1,63 @@ +/* + * File : mbox.h + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-08-29 zdzn first version + */ + +#ifndef __MBOX_H__ +#define __MBOX_H__ + +/* a properly aligned buffer */ +extern volatile unsigned int* mbox; + +#define MBOX_REQUEST 0 + +/* channels */ +#define MBOX_CH_POWER 0 +#define MBOX_CH_FB 1 +#define MBOX_CH_VUART 2 +#define MBOX_CH_VCHIQ 3 +#define MBOX_CH_LEDS 4 +#define MBOX_CH_BTNS 5 +#define MBOX_CH_TOUCH 6 +#define MBOX_CH_COUNT 7 +#define MBOX_CH_PROP 8 + +/* tags */ +#define MBOX_TAG_SETPOWER 0x28001 +#define MBOX_TAG_SETCLKRATE 0x38002 +#define MBOX_GET_MAC_ADDRESS 0x10003 +#define MBOX_GET_CLOCK_RATE 0x30002 +#define MBOX_SET_CLOCK_RATE 0x38002 +#define MBOX_TAG_LAST 0 + +#define MMIO_BASE 0x3F000000 +#define VIDEOCORE_MBOX (MMIO_BASE+0x0000B880) +#define MBOX_READ ((volatile unsigned int*)(VIDEOCORE_MBOX+0x0)) +#define MBOX_POLL ((volatile unsigned int*)(VIDEOCORE_MBOX+0x10)) +#define MBOX_SENDER ((volatile unsigned int*)(VIDEOCORE_MBOX+0x14)) +#define MBOX_STATUS ((volatile unsigned int*)(VIDEOCORE_MBOX+0x18)) +#define MBOX_CONFIG ((volatile unsigned int*)(VIDEOCORE_MBOX+0x1C)) +#define MBOX_WRITE ((volatile unsigned int*)(VIDEOCORE_MBOX+0x20)) +#define MBOX_RESPONSE 0x80000000 +#define MBOX_FULL 0x80000000 +#define MBOX_EMPTY 0x40000000 + +#define DEVICE_ID_SD_CARD 0 +#define DEVICE_ID_USB_HCD 3 +#define POWER_STATE_OFF (0 << 0) +#define POWER_STATE_ON (1 << 0) +#define POWER_STATE_WAIT (1 << 1) +#define POWER_STATE_NO_DEVICE (1 << 1) // in response +#define MMU_ENABLE 1 +#define MMU_DISABLE 0 + +#define MBOX_ADDR 0xc00000 + +int mbox_call(unsigned char ch, int mmu_enable); +#endif diff --git a/bsp/raspberry-pi/raspi3-32/driver/raspi.h b/bsp/raspberry-pi/raspi3-32/driver/raspi.h new file mode 100644 index 0000000000000000000000000000000000000000..19daa3541df0f9331cc4d737823f8893d779ff04 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/driver/raspi.h @@ -0,0 +1,432 @@ +/* + * File : rsapi.h + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#ifndef __RASPI_H__ +#define __RASPI_H__ + +/* define for bcm283x*/ +typedef enum +{ + BCM_GPIO_PIN_0 = 0, + BCM_GPIO_PIN_1, + BCM_GPIO_PIN_2, + BCM_GPIO_PIN_3, + BCM_GPIO_PIN_4, + BCM_GPIO_PIN_5, + BCM_GPIO_PIN_6, + BCM_GPIO_PIN_7, + BCM_GPIO_PIN_8, + BCM_GPIO_PIN_9, + BCM_GPIO_PIN_10, + BCM_GPIO_PIN_11, + BCM_GPIO_PIN_12, + BCM_GPIO_PIN_13, + BCM_GPIO_PIN_14, + BCM_GPIO_PIN_15, + BCM_GPIO_PIN_16, + BCM_GPIO_PIN_17, + BCM_GPIO_PIN_18, + BCM_GPIO_PIN_19, + BCM_GPIO_PIN_20, + BCM_GPIO_PIN_21, + BCM_GPIO_PIN_22, + BCM_GPIO_PIN_23, + BCM_GPIO_PIN_24, + BCM_GPIO_PIN_25, + BCM_GPIO_PIN_26, + BCM_GPIO_PIN_27, + BCM_GPIO_PIN_28, + BCM_GPIO_PIN_29, + BCM_GPIO_PIN_30, + BCM_GPIO_PIN_31, + BCM_GPIO_PIN_32, + BCM_GPIO_PIN_33, + BCM_GPIO_PIN_34, + BCM_GPIO_PIN_35, + BCM_GPIO_PIN_36, + BCM_GPIO_PIN_37, + BCM_GPIO_PIN_38, + BCM_GPIO_PIN_39, + BCM_GPIO_PIN_40, + BCM_GPIO_PIN_41, + BCM_GPIO_PIN_42, + BCM_GPIO_PIN_43, + BCM_GPIO_PIN_44, + BCM_GPIO_PIN_45, + BCM_GPIO_PIN_46, + BCM_GPIO_PIN_47, + BCM_GPIO_PIN_48, + BCM_GPIO_PIN_49, + BCM_GPIO_PIN_50, + BCM_GPIO_PIN_51, + BCM_GPIO_PIN_52, + BCM_GPIO_PIN_53, + BCM_GPIO_PIN_NULL, +} bcm_gpio_pin; + +typedef enum +{ + BCM283X_GPIO_FSEL_INPT = 0x00, /*!< Input 0b000 */ + BCM283X_GPIO_FSEL_OUTP = 0x01, /*!< Output 0b001 */ + BCM283X_GPIO_FSEL_ALT0 = 0x04, /*!< Alternate function 0 0b100 */ + BCM283X_GPIO_FSEL_ALT1 = 0x05, /*!< Alternate function 1 0b101 */ + BCM283X_GPIO_FSEL_ALT2 = 0x06, /*!< Alternate function 2 0b110, */ + BCM283X_GPIO_FSEL_ALT3 = 0x07, /*!< Alternate function 3 0b111 */ + BCM283X_GPIO_FSEL_ALT4 = 0x03, /*!< Alternate function 4 0b011 */ + BCM283X_GPIO_FSEL_ALT5 = 0x02, /*!< Alternate function 5 0b010 */ + BCM283X_GPIO_FSEL_MASK = 0x07 /*!< Function select bits mask 0b111 */ +} gpio_function_select; + +typedef enum +{ + BCM283X_GPIO_PUD_OFF = 0x00, /*!< Off ? disable pull-up/down 0b00 */ + BCM283X_GPIO_PUD_DOWN = 0x01, /*!< Enable Pull Down control 0b01 */ + BCM283X_GPIO_PUD_UP = 0x02 /*!< Enable Pull Up control 0b10 */ +} gpio_pud_mode; + +#define BCM283X_CORE_CLK_HZ 250000000 /* 50 MHz */ + +/* Base Address */ +#define PER_BASE (0x3F000000) +#define PER_BASE_40000000 (0x40000000) +//#define BCM283X_PERI_BASE (0x3F000000) +//#define BCM283X_PER_BASE_40000000 (0x40000000) + +/* Base Address Registers Offset */ +#define ST_BASE_OFFSET (0x003000) +#define GPIO_PAD_OFFSET (0x100000) +#define CLOCK_BASE_OFFSET (0x101000) +#define GPIO_BASE_OFFSET (0x200000) +#define SPI0_BASE_OFFSET (0x204000) +#define BSC0_BASE_OFFSET (0x205000) +#define GPIO_PWM_OFFSET (0x20C000) +#define AUX_BASE_OFFSET (0x215000) +#define SPI1_BASE_OFFSET (0x215080) +#define SPI2_BASE_OFFSET (0x2150C0) +#define BSC1_BASE_OFFSET (0x804000) +#define BSC2_BASE_OFFSET (0x805000) + +/* IRQ */ +#define IRQ_SYSTEM_TIMER_0 0 +#define IRQ_SYSTEM_TIMER_1 1 +#define IRQ_SYSTEM_TIMER_2 2 +#define IRQ_SYSTEM_TIMER_3 3 +#define IRQ_USB 9 +#define IRQ_AUX 29 +#define IRQ_PCM 55 +#define IRQ_ARM_TIMER 64 +#define IRQ_ARM_MAILBOX 65 + +/* Interrupt Controler */ +#define IRQ_BASE (PER_BASE + 0xB200) +#define IRQ_PEND_BASIC HWREG32(IRQ_BASE + 0x0000) +#define IRQ_PEND1 HWREG32(IRQ_BASE + 0x0004) +#define IRQ_PEND2 HWREG32(IRQ_BASE + 0x0008) +#define IRQ_FIQ_CONTROL HWREG32(IRQ_BASE + 0x000C) +#define IRQ_ENABLE1 HWREG32(IRQ_BASE + 0x0010) +#define IRQ_ENABLE2 HWREG32(IRQ_BASE + 0x0014) +#define IRQ_ENABLE_BASIC HWREG32(IRQ_BASE + 0x0018) +#define IRQ_DISABLE1 HWREG32(IRQ_BASE + 0x001C) +#define IRQ_DISABLE2 HWREG32(IRQ_BASE + 0x0020) +#define IRQ_DISABLE_BASIC HWREG32(IRQ_BASE + 0x0024) + + +/* Defines for WDT*/ +#define PM_BASE (PER_BASE + GPIO_PAD_OFFSET) +#define PM_RSTC HWREG32(PM_BASE + 0x001C) +#define PM_RSTS HWREG32(PM_BASE + 0x0020) +#define PM_WDOG HWREG32(PM_BASE + 0x0024) + +#define PM_PASSWORD 0x5a000000 +#define PM_WDOG_TIME_SET 0x000fffff +#define PM_RSTC_WRCFG_CLR 0xffffffcf +#define PM_RSTS_HADWRH_SET 0x00000040 +#define PM_RSTC_WRCFG_SET 0x00000030 +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020 +#define PM_RSTC_RESET 0x00000102 +#define PM_RSTS_PARTITION_CLR 0xfffffaaa + +/* Defines for System Timer */ +#define STIMER_BASE (PER_BASE + ST_BASE_OFFSET) +#define STIMER_CS HWREG32(STIMER_BASE + 0x0000) +#define STIMER_CLO HWREG32(STIMER_BASE + 0x0004) +#define STIMER_CHI HWREG32(STIMER_BASE + 0x0008) +#define STIMER_C0 HWREG32(STIMER_BASE + 0x000C) +#define STIMER_C1 HWREG32(STIMER_BASE + 0x0010) +#define STIMER_C2 HWREG32(STIMER_BASE + 0x0014) +#define STIMER_C3 HWREG32(STIMER_BASE + 0x0018) + +#define DELAY_MICROS(micros) \ + do{ \ + rt_uint32_t compare = STIMER_CLO + micros * 25; \ + while (STIMER_CLO < compare); \ + } while (0) \ + +/* Defines for GPIO */ +#define BCM283X_GPIO_BASE (PER_BASE + GPIO_BASE_OFFSET) +#define BCM283X_GPIO_GPFSEL(n) HWREG32(BCM283X_GPIO_BASE + 0x0000 + 0x4 * n) /* GPIO Function Select 32bit R/W */ +#define BCM283X_GPIO_GPSET(n) HWREG32(BCM283X_GPIO_BASE + 0x001C + 0x4 * n) /* GPIO Pin Output Set */ +#define BCM283X_GPIO_GPCLR(n) HWREG32(BCM283X_GPIO_BASE + 0x0028 + 0x4 * n) /* GPIO Pin Output Clear */ +#define BCM2835_GPIO_GPLEV(n) HWREG32(BCM283X_GPIO_BASE + 0x0034 + 0x4 * n) /* GPIO Pin Level */ +#define BCM283X_GPIO_GPEDS(n) HWREG32(BCM283X_GPIO_BASE + 0x0040 + 0x4 * n) /* GPIO Pin Event Detect Status */ +#define BCM283X_GPIO_GPREN(n) HWREG32(BCM283X_GPIO_BASE + 0x004c + 0x4 * n) /* GPIO Pin Rising Edge Detect Enable */ +#define BCM283X_GPIO_GPFEN(n) HWREG32(BCM283X_GPIO_BASE + 0x0058 + 0x4 * n) /* GPIO Pin Falling Edge Detect Enable */ +#define BCM283X_GPIO_GPHEN(n) HWREG32(BCM283X_GPIO_BASE + 0x0064 + 0x4 * n) /* GPIO Pin High Detect Enable */ +#define BCM283X_GPIO_GPLEN(n) HWREG32(BCM283X_GPIO_BASE + 0x0070 + 0x4 * n) /* GPIO Pin Low Detect Enable */ +#define BCM283X_GPIO_GPAREN(n) HWREG32(BCM283X_GPIO_BASE + 0x007C + 0x4 * n) /* GPIO Pin Async. Rising Edge Detect */ +#define BCM283X_GPIO_GPAFEN(n) HWREG32(BCM283X_GPIO_BASE + 0x0088 + 0x4 * n) /* GPIO Pin Async. Falling Edge Detect */ +#define BCM283X_GPIO_GPPUD HWREG32(BCM283X_GPIO_BASE + 0x0094) /* GPIO Pin Pull-up/down Enable */ +#define BCM283X_GPIO_GPPUDCLK(n) HWREG32(BCM283X_GPIO_BASE + 0x0098 + 0x4 * n) /* GPIO Pin Pull-up/down Enable Clock */ + +#define GPIO_FSEL_NUM(pin) (pin/10) +#define GPIO_FSEL_SHIFT(pin) ((pin%10)*3) +#define GPIO_FSEL(pin, mode) \ + do{ \ + __sync_synchronize(); \ + BCM283X_GPIO_GPFSEL(GPIO_FSEL_NUM(pin)) |= ((mode & BCM283X_GPIO_FSEL_MASK) << GPIO_FSEL_SHIFT(pin)); \ + } while (0) \ + +/* Defines for I2C */ +#define BCM283X_BSC0_BASE (PER_BASE + BSC0_BASE_OFFSET) //for i2c0 +#define BCM283X_BSC1_BASE (PER_BASE + BSC1_BASE_OFFSET) //for i2c1 +#define BCM283X_BSC2_BASE (PER_BASE + BSC2_BASE_OFFSET) //for hdmi i2c not use + +#define BCM283X_BSC_C(BASE) HWREG32(BASE + 0x0000) /* BSC Master Control */ +#define BCM283X_BSC_S(BASE) HWREG32(BASE + 0x0004) /* BSC Master Status */ +#define BCM283X_BSC_DLEN(BASE) HWREG32(BASE + 0x0008) /* BSC Master Data Length */ +#define BCM283X_BSC_A(BASE) HWREG32(BASE + 0x000c) /* BSC Master Slave Address */ +#define BCM283X_BSC_FIFO(BASE) HWREG32(BASE + 0x0010) /* BSC Master Data FIFO */ +#define BCM283X_BSC_DIV(BASE) HWREG32(BASE + 0x0014) /* BSC Master Clock Divider */ +#define BCM283X_BSC_DEL(BASE) HWREG32(BASE + 0x0018) /* BSC Master Data Delay */ +#define BCM283X_BSC_CLKT(BASE) HWREG32(BASE + 0x001c) /* BSC Master Clock Stretch Timeout */ + +/* Register masks for C Register */ +#define BSC_C_I2CEN 0x00008000 /* I2C Enable, 0 = disabled, 1 = enabled */ +#define BSC_C_INTR 0x00000400 /* Interrupt on RX */ +#define BSC_C_INTT 0x00000200 /* Interrupt on TX */ +#define BSC_C_INTD 0x00000100 /* Interrupt on DONE */ +#define BSC_C_ST 0x00000080 /* Start transfer, 1 = Start a new transfer */ +#define BSC_C_CLEAR_1 0x00000020 /* Clear FIFO Clear */ +#define BSC_C_CLEAR_2 0x00000010 /* Clear FIFO Clear */ +#define BSC_C_READ 0x00000001 /* Read transfer */ + +/* Register masks for S Register */ +#define BSC_S_CLKT 0x00000200 /* Clock stretch timeout */ +#define BSC_S_ERR 0x00000100 /* ACK error */ +#define BSC_S_RXF 0x00000080 /* RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full */ +#define BSC_S_TXE 0x00000040 /* TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full */ +#define BSC_S_RXD 0x00000020 /* RXD FIFO contains data */ +#define BSC_S_TXD 0x00000010 /* TXD FIFO can accept data */ +#define BSC_S_RXR 0x00000008 /* RXR FIFO needs reading (full) */ +#define BSC_S_TXW 0x00000004 /* TXW FIFO needs writing (full) */ +#define BSC_S_DONE 0x00000002 /* Transfer DONE */ +#define BSC_S_TA 0x00000001 /* Transfer Active */ + +#define BSC_FIFO_SIZE (16) /* BSC FIFO size */ + +/* Defines for SPI */ +#define BCM283X_SPI0_BASE (PER_BASE + SPI0_BASE_OFFSET) +#define BCM283X_SPI1_BASE (PER_BASE + SPI1_BASE_OFFSET) +#define BCM283X_SPI2_BASE (PER_BASE + SPI2_BASE_OFFSET) + +#define BCM283X_SPI0_CS(BASE) HWREG32(BASE + 0x0000) /* SPI Master Control and Status */ +#define BCM283X_SPI0_FIFO(BASE) HWREG32(BASE + 0x0004) /* SPI Master TX and RX FIFOs */ +#define BCM283X_SPI0_CLK(BASE) HWREG32(BASE + 0x0008) /* SPI Master Clock Divider */ +#define BCM283X_SPI0_DLEN(BASE) HWREG32(BASE + 0x000c) /* SPI Master Data Length */ +#define BCM283X_SPI0_LTOH(BASE) HWREG32(BASE + 0x0010) /* SPI LOSSI mode TOH */ +#define BCM283X_SPI0_DC(BASE) HWREG32(BASE + 0x0014) /* SPI DMA DREQ Controls */ + +/* Register masks for SPI0_CS */ +#define BCM283X_SPI0_CS_LEN_LONG 0x02000000 /* Enable Long data word in Lossi mode if DMA_LEN is set */ +#define BCM283X_SPI0_CS_DMA_LEN 0x01000000 /* Enable DMA mode in Lossi mode */ +#define BCM283X_SPI0_CS_CSPOL2 0x00800000 /* Chip Select 2 Polarity */ +#define BCM283X_SPI0_CS_CSPOL1 0x00400000 /* Chip Select 1 Polarity */ +#define BCM283X_SPI0_CS_CSPOL0 0x00200000 /* Chip Select 0 Polarity */ +#define BCM283X_SPI0_CS_RXF 0x00100000 /* RXF - RX FIFO Full */ +#define BCM283X_SPI0_CS_RXR 0x00080000 /* RXR RX FIFO needs Reading (full) */ +#define BCM283X_SPI0_CS_TXD 0x00040000 /* TXD TX FIFO can accept Data */ +#define BCM283X_SPI0_CS_RXD 0x00020000 /* RXD RX FIFO contains Data */ +#define BCM283X_SPI0_CS_DONE 0x00010000 /* Done transfer Done */ +#define BCM283X_SPI0_CS_TE_EN 0x00008000 /* Unused */ +#define BCM283X_SPI0_CS_LMONO 0x00004000 /* Unused */ +#define BCM283X_SPI0_CS_LEN 0x00002000 /* LEN LoSSI enable */ +#define BCM283X_SPI0_CS_REN 0x00001000 /* REN Read Enable */ +#define BCM283X_SPI0_CS_ADCS 0x00000800 /* ADCS Automatically Deassert Chip Select */ +#define BCM283X_SPI0_CS_INTR 0x00000400 /* INTR Interrupt on RXR */ +#define BCM283X_SPI0_CS_INTD 0x00000200 /* INTD Interrupt on Done */ +#define BCM283X_SPI0_CS_DMAEN 0x00000100 /* DMAEN DMA Enable */ +#define BCM283X_SPI0_CS_TA 0x00000080 /* Transfer Active */ +#define BCM283X_SPI0_CS_CSPOL 0x00000040 /* Chip Select Polarity */ +#define BCM283X_SPI0_CS_CLEAR 0x00000030 /* Clear FIFO Clear RX and TX */ +#define BCM283X_SPI0_CS_CLEAR_RX 0x00000020 /* Clear FIFO Clear RX */ +#define BCM283X_SPI0_CS_CLEAR_TX 0x00000010 /* Clear FIFO Clear TX */ +#define BCM283X_SPI0_CS_CPOL 0x00000008 /* Clock Polarity */ +#define BCM283X_SPI0_CS_CPHA 0x00000004 /* Clock Phase */ +#define BCM283X_SPI0_CS_CS 0x00000003 /* Chip Select */ + +/* ARM Timer */ +#define ARM_TIMER_BASE (PER_BASE + 0xB000) +#define ARM_TIMER_LOAD HWREG32(ARM_TIMER_BASE + 0x400) +#define ARM_TIMER_VALUE HWREG32(ARM_TIMER_BASE + 0x404) +#define ARM_TIMER_CTRL HWREG32(ARM_TIMER_BASE + 0x408) +#define ARM_TIMER_IRQCLR HWREG32(ARM_TIMER_BASE + 0x40C) +#define ARM_TIMER_RAWIRQ HWREG32(ARM_TIMER_BASE + 0x410) +#define ARM_TIMER_MASKIRQ HWREG32(ARM_TIMER_BASE + 0x414) +#define ARM_TIMER_RELOAD HWREG32(ARM_TIMER_BASE + 0x418) +#define ARM_TIMER_PREDIV HWREG32(ARM_TIMER_BASE + 0x41C) +#define ARM_TIMER_CNTR HWREG32(ARM_TIMER_BASE + 0x420) + +/* ARM Core Timer */ +#define C0TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x40) /* Core0 timers Interrupt control */ +#define C1TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x44) /* Core1 timers Interrupt control */ +#define C2TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x48) /* Core2 timers Interrupt control */ +#define C3TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x4C) /* Core3 timers Interrupt control */ +#define CORETIMER_INTCTL(n) HWREG32(PER_BASE_40000000 + 0x40 + n*4) /* Coren timers Interrupt control */ + +/* ARM Core Mailbox interrupt */ +#define C0MB_INTCTL HWREG32(PER_BASE_40000000 + 0x50) /* Core0 Mailboxes Interrupt control */ +#define C1MB_INTCTL HWREG32(PER_BASE_40000000 + 0x54) /* Core1 Mailboxes Interrupt control */ +#define C2MB_INTCTL HWREG32(PER_BASE_40000000 + 0x58) /* Core2 Mailboxes Interrupt control */ +#define C3MB_INTCTL HWREG32(PER_BASE_40000000 + 0x5C) /* Core3 Mailboxes Interrupt control */ +#define COREMB_INTCTL(n) HWREG32(PER_BASE_40000000 + 0x50 + 4*n) /* Coren Mailboxes Interrupt control */ + +/* ARM Core IRQ/FIQ status */ +#define C0_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x60) /* Core0 IRQ Source */ +#define C1_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x64) /* Core1 IRQ Source */ +#define C2_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x68) /* Core2 IRQ Source */ +#define C3_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x6C) /* Core3 IRQ Source */ +#define C0_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x70) /* Core0 FIQ Source */ +#define C1_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x74) /* Core1 FIQ Source */ +#define C2_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x78) /* Core2 FIQ Source */ +#define C3_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x7C) /* Core3 FIQ Source */ +#define CORE_IRQSOURCE(n) HWREG32(PER_BASE_40000000 + 0x60+ n*0x4) +#define CORE_FIQSOURCE(n) HWREG32(PER_BASE_40000000 + 0x70+ n*0x4) + +#define CORE_MAILBOX3_SET(n) HWREG32(PER_BASE_40000000 + 0x8C + n*0x10) +#define CORE_MAILBOX3_CLEAR(n) HWREG32(PER_BASE_40000000 + 0xCC + n*0x10) +#define CORE_MAILBOX2_SET(n) HWREG32(PER_BASE_40000000 + 0x88 + n*0x10) +#define CORE_MAILBOX2_CLEAR(n) HWREG32(PER_BASE_40000000 + 0xC8 + n*0x10) +#define CORE_MAILBOX1_SET(n) HWREG32(PER_BASE_40000000 + 0x84 + n*0x10) +#define CORE_MAILBOX1_CLEAR(n) HWREG32(PER_BASE_40000000 + 0xC4 + n*0x10) +#define CORE_MAILBOX0_SET(n) HWREG32(PER_BASE_40000000 + 0x80 + n*0x10) +#define CORE_MAILBOX0_CLEAR(n) HWREG32(PER_BASE_40000000 + 0xC0 + n*0x10) + +/* For SMP IPI use MailBox0 */ +#define IPI_MAILBOX_SET CORE_MAILBOX0_SET +#define IPI_MAILBOX_CLEAR CORE_MAILBOX0_CLEAR +#define IPI_MAILBOX_INT_MASK (0x01) + +enum spi_bit_order +{ + BCM283X_SPI_BIT_ORDER_LSBFIRST = 0, /*!< LSB First */ + BCM283X_SPI_BIT_ORDER_MSBFIRST = 1 /*!< MSB First */ +}; + +enum spi_mode +{ + BCM283X_SPI_MODE0 = 0, /*!< CPOL = 0, CPHA = 0 */ + BCM283X_SPI_MODE1 = 1, /*!< CPOL = 0, CPHA = 1 */ + BCM283X_SPI_MODE2 = 2, /*!< CPOL = 1, CPHA = 0 */ + BCM283X_SPI_MODE3 = 3 /*!< CPOL = 1, CPHA = 1 */ +}; + +enum spi_chip_select +{ + BCM283X_SPI_CS0 = 0, /*!< Chip Select 0 */ + BCM283X_SPI_CS1 = 1, /*!< Chip Select 1 */ + BCM283X_SPI_CS2 = 2, /*!< Chip Select 2 (ie pins CS1 and CS2 are asserted) */ + BCM283X_SPI_CS_NONE = 3 /*!< No CS, control it yourself */ +}; + +enum spi_clock_divider +{ + BCM283X_SPI_CLOCK_DIVIDER_65536 = 0, /*!< 65536 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_32768 = 32768, /*!< 32768 = 7.629394531kHz on Rpi2, 12.20703125kHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_16384 = 16384, /*!< 16384 = 15.25878906kHz on Rpi2, 24.4140625kHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_8192 = 8192, /*!< 8192 = 30.51757813kHz on Rpi2, 48.828125kHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_4096 = 4096, /*!< 4096 = 61.03515625kHz on Rpi2, 97.65625kHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_2048 = 2048, /*!< 2048 = 122.0703125kHz on Rpi2, 195.3125kHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_1024 = 1024, /*!< 1024 = 244.140625kHz on Rpi2, 390.625kHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_512 = 512, /*!< 512 = 488.28125kHz on Rpi2, 781.25kHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_256 = 256, /*!< 256 = 976.5625kHz on Rpi2, 1.5625MHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_128 = 128, /*!< 128 = 1.953125MHz on Rpi2, 3.125MHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_64 = 64, /*!< 64 = 3.90625MHz on Rpi2, 6.250MHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_32 = 32, /*!< 32 = 7.8125MHz on Rpi2, 12.5MHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_16 = 16, /*!< 16 = 15.625MHz on Rpi2, 25MHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_8 = 8, /*!< 8 = 31.25MHz on Rpi2, 50MHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_4 = 4, /*!< 4 = 62.5MHz on Rpi2, 100MHz on RPI3. Dont expect this speed to work reliably. */ + BCM283X_SPI_CLOCK_DIVIDER_2 = 2, /*!< 2 = 125MHz on Rpi2, 200MHz on RPI3, fastest you can get. Dont expect this speed to work reliably.*/ + BCM283X_SPI_CLOCK_DIVIDER_1 = 1 /*!< 1 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3, same as 0/65536 */ +}; + +/*redefine for raspi*/ +typedef gpio_function_select raspi_pin_select; +typedef enum +{ + RPI_GPIO_P1_01 = BCM_GPIO_PIN_NULL, + RPI_GPIO_P1_02 = BCM_GPIO_PIN_NULL, + RPI_GPIO_P1_03 = BCM_GPIO_PIN_2, + RPI_GPIO_P1_04 = BCM_GPIO_PIN_NULL, + RPI_GPIO_P1_05 = BCM_GPIO_PIN_3, + RPI_GPIO_P1_06 = BCM_GPIO_PIN_NULL, + RPI_GPIO_P1_07 = BCM_GPIO_PIN_4, + RPI_GPIO_P1_08 = BCM_GPIO_PIN_14, + RPI_GPIO_P1_09 = BCM_GPIO_PIN_NULL, + RPI_GPIO_P1_10 = BCM_GPIO_PIN_15, + RPI_GPIO_P1_11 = BCM_GPIO_PIN_17, + RPI_GPIO_P1_12 = BCM_GPIO_PIN_18, + RPI_GPIO_P1_13 = BCM_GPIO_PIN_27, + RPI_GPIO_P1_14 = BCM_GPIO_PIN_NULL, + RPI_GPIO_P1_15 = BCM_GPIO_PIN_22, + RPI_GPIO_P1_16 = BCM_GPIO_PIN_23, + RPI_GPIO_P1_17 = BCM_GPIO_PIN_NULL, + RPI_GPIO_P1_18 = BCM_GPIO_PIN_24, + RPI_GPIO_P1_19 = BCM_GPIO_PIN_10, + RPI_GPIO_P1_20 = BCM_GPIO_PIN_NULL, + RPI_GPIO_P1_21 = BCM_GPIO_PIN_9, + RPI_GPIO_P1_22 = BCM_GPIO_PIN_25, + RPI_GPIO_P1_23 = BCM_GPIO_PIN_11, + RPI_GPIO_P1_24 = BCM_GPIO_PIN_8, + RPI_GPIO_P1_25 = BCM_GPIO_PIN_NULL, + RPI_GPIO_P1_26 = BCM_GPIO_PIN_7, + RPI_GPIO_P1_27 = BCM_GPIO_PIN_0, + RPI_GPIO_P1_28 = BCM_GPIO_PIN_1, + RPI_GPIO_P1_29 = BCM_GPIO_PIN_5, + RPI_GPIO_P1_30 = BCM_GPIO_PIN_NULL, + RPI_GPIO_P1_31 = BCM_GPIO_PIN_6, + RPI_GPIO_P1_32 = BCM_GPIO_PIN_12, + RPI_GPIO_P1_33 = BCM_GPIO_PIN_13, + RPI_GPIO_P1_34 = BCM_GPIO_PIN_NULL, + RPI_GPIO_P1_35 = BCM_GPIO_PIN_19, + RPI_GPIO_P1_36 = BCM_GPIO_PIN_16, + RPI_GPIO_P1_37 = BCM_GPIO_PIN_26, + RPI_GPIO_P1_38 = BCM_GPIO_PIN_20, + RPI_GPIO_P1_39 = BCM_GPIO_PIN_NULL, + RPI_GPIO_P1_40 = BCM_GPIO_PIN_21, +} raspi_gpio_pin; + +typedef enum +{ + BCM283X_I2C_CLOCK_DIVIDER_2500 = 2500, /* 2500 = 10us = 100 kHz */ + BCM283X_I2C_CLOCK_DIVIDER_626 = 626, /* 622 = 2.504us = 399.3610 kHz */ + BCM283X_I2C_CLOCK_DIVIDER_150 = 150, /* 150 = 60ns = 1.666 MHz (default at reset) */ + BCM283X_I2C_CLOCK_DIVIDER_148 = 148 /* 148 = 59ns = 1.689 MHz */ +} i2c_clock_divider; + +typedef enum +{ + BCM283X_I2C_REASON_OK = 0x00, /* Success */ + BCM283X_I2C_REASON_ERROR_NACK = 0x01, /* Received a NACK */ + BCM283X_I2C_REASON_ERROR_CLKT = 0x02, /* Received Clock Stretch Timeout */ + BCM283X_I2C_REASON_ERROR_DATA = 0x04 /* Not all data is sent / received */ +} i2c_reason_codes; + +#endif diff --git a/bsp/raspberry-pi/raspi3-32/figures/GPIO-Pinout-Diagram-2.png b/bsp/raspberry-pi/raspi3-32/figures/GPIO-Pinout-Diagram-2.png new file mode 100644 index 0000000000000000000000000000000000000000..24238cc23d89f18fca2bc5daa5e3f62abc4c4390 Binary files /dev/null and b/bsp/raspberry-pi/raspi3-32/figures/GPIO-Pinout-Diagram-2.png differ diff --git a/bsp/raspberry-pi/raspi3-32/figures/raspberrypi-console.png b/bsp/raspberry-pi/raspi3-32/figures/raspberrypi-console.png new file mode 100644 index 0000000000000000000000000000000000000000..a36f6f75e050a965fe547cf190925400ce029f7f Binary files /dev/null and b/bsp/raspberry-pi/raspi3-32/figures/raspberrypi-console.png differ diff --git a/bsp/raspberry-pi/raspi3-32/figures/raspi3_b.jpg b/bsp/raspberry-pi/raspi3-32/figures/raspi3_b.jpg new file mode 100644 index 0000000000000000000000000000000000000000..03db419bd89fb16803c1d3b4fc990ca2d662fdd9 Binary files /dev/null and b/bsp/raspberry-pi/raspi3-32/figures/raspi3_b.jpg differ diff --git a/bsp/raspberry-pi/raspi3-32/figures/raspi3_f.jpg b/bsp/raspberry-pi/raspi3-32/figures/raspi3_f.jpg new file mode 100644 index 0000000000000000000000000000000000000000..dd2f25133280c0fc00ac742b4afde45a2ec7f120 Binary files /dev/null and b/bsp/raspberry-pi/raspi3-32/figures/raspi3_f.jpg differ diff --git a/bsp/raspberry-pi/raspi3-32/link.lds b/bsp/raspberry-pi/raspi3-32/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..75e084594312c9f66304ea5bbb32f49cd7e2ba3d --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/link.lds @@ -0,0 +1,149 @@ +/* + * File : link.lds + * COPYRIGHT (C) 2017, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * 2017-5-30 bernard first version + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +SECTIONS +{ + . = 0x00008000; + . = ALIGN(4); + .text : + { + *(.vectors) + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + *(.eh_frame_entry) + } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + + . = ALIGN(4); + .data : + { + *(.data) + *(.data.*) + + *(.data1) + *(.data1.*) + + . = ALIGN(8); + _gp = ABSOLUTE(.); /* Base of small data */ + + *(.sdata) + *(.sdata.*) + } + + . = ALIGN(4); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + . = ALIGN(4); + .bss : + { + PROVIDE(__bss_start = .); + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + PROVIDE(__bss_end = .); + } + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/raspberry-pi/raspi3-32/rtconfig.h b/bsp/raspberry-pi/raspi3-32/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..b861bf8827bd157c85906f5e5ac49a1520a03cf8 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/rtconfig.h @@ -0,0 +1,391 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +/* RT_USING_ARCH_DATA_TYPE is not set */ +#define RT_USING_SMP +#define RT_CPUS_NR 4 +#define RT_ALIGN_SIZE 4 +/* RT_THREAD_PRIORITY_8 is not set */ +#define RT_THREAD_PRIORITY_32 +/* RT_THREAD_PRIORITY_256 is not set */ +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +/* RT_USING_TIMER_SOFT is not set */ +#define RT_DEBUG +#define RT_DEBUG_COLOR +/* RT_DEBUG_INIT_CONFIG is not set */ +/* RT_DEBUG_THREAD_CONFIG is not set */ +/* RT_DEBUG_SCHEDULER_CONFIG is not set */ +/* RT_DEBUG_IPC_CONFIG is not set */ +/* RT_DEBUG_TIMER_CONFIG is not set */ +/* RT_DEBUG_IRQ_CONFIG is not set */ +/* RT_DEBUG_MEM_CONFIG is not set */ +/* RT_DEBUG_SLAB_CONFIG is not set */ +/* RT_DEBUG_MEMHEAP_CONFIG is not set */ +/* RT_DEBUG_MODULE_CONFIG is not set */ + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* RT_USING_SIGNALS is not set */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +/* RT_USING_NOHEAP is not set */ +#define RT_USING_SMALL_MEM +/* RT_USING_SLAB is not set */ +/* RT_USING_MEMHEAP_AS_HEAP is not set */ +#define RT_USING_MEMTRACE +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS +/* RT_USING_INTERRUPT_INFO is not set */ +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40002 +#define ARCH_ARM +/* RT_USING_CPU_FFS is not set */ +#define ARCH_ARM_CORTEX_A +#define ARCH_ARM_CORTEX_A7 +/* ARCH_CPU_STACK_GROWS_UPWARD is not set */ + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + +/* RT_USING_CPLUSPLUS is not set */ + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +/* FINSH_ECHO_DISABLE_DEFAULT is not set */ +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +/* FINSH_USING_AUTH is not set */ +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +/* RT_USING_DFS_MNTTABLE is not set */ +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +/* RT_DFS_ELM_USE_LFN_0 is not set */ +/* RT_DFS_ELM_USE_LFN_1 is not set */ +/* RT_DFS_ELM_USE_LFN_2 is not set */ +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +/* RT_DFS_ELM_USE_ERASE is not set */ +#define RT_DFS_ELM_REENTRANT +#define RT_USING_DFS_DEVFS +/* RT_USING_DFS_ROMFS is not set */ +/* RT_USING_DFS_RAMFS is not set */ +/* RT_USING_DFS_UFFS is not set */ +/* RT_USING_DFS_JFFS2 is not set */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +/* RT_USING_SYSTEM_WORKQUEUE is not set */ +#define RT_USING_SERIAL +/* RT_SERIAL_USING_DMA is not set */ +#define RT_SERIAL_RB_BUFSZ 64 +/* RT_USING_CAN is not set */ +#define RT_USING_HWTIMER +/* RT_USING_CPUTIME is not set */ +#define RT_USING_I2C +/* RT_USING_I2C_BITOPS is not set */ +#define RT_USING_PIN +/* RT_USING_ADC is not set */ +/* RT_USING_PWM is not set */ +/* RT_USING_MTD_NOR is not set */ +/* RT_USING_MTD_NAND is not set */ +/* RT_USING_PM is not set */ +#define RT_USING_RTC +/* RT_USING_ALARM is not set */ +/* RT_USING_SOFT_RTC is not set */ +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 512 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 1024 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 +/* RT_SDIO_DEBUG is not set */ +#define RT_USING_SPI +/* RT_USING_QSPI is not set */ +/* RT_USING_SPI_MSD is not set */ +/* RT_USING_SFUD is not set */ +/* RT_USING_ENC28J60 is not set */ +/* RT_USING_SPI_WIFI is not set */ +#define RT_USING_WDT +/* RT_USING_AUDIO is not set */ +/* RT_USING_SENSOR is not set */ +/* RT_USING_TOUCH is not set */ +/* RT_USING_HWCRYPTO is not set */ +/* RT_USING_WIFI is not set */ + +/* Using USB */ + +/* RT_USING_USB_HOST is not set */ +/* RT_USING_USB_DEVICE is not set */ + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +/* RT_USING_PTHREADS is not set */ +#define RT_USING_POSIX +/* RT_USING_POSIX_MMAP is not set */ +/* RT_USING_POSIX_TERMIOS is not set */ +/* RT_USING_POSIX_AIO is not set */ +/* RT_USING_MODULE is not set */ + +/* Network */ + +/* Socket abstraction layer */ + +/* RT_USING_SAL is not set */ + +/* Network interface device */ + +/* RT_USING_NETDEV is not set */ + +/* light weight TCP/IP stack */ + +/* RT_USING_LWIP is not set */ + +/* AT commands */ + +/* RT_USING_AT is not set */ + +/* VBUS(Virtual Software BUS) */ + +/* RT_USING_VBUS is not set */ + +/* Utilities */ + +/* RT_USING_RYM is not set */ +/* RT_USING_ULOG is not set */ +/* RT_USING_UTEST is not set */ +/* RT_USING_LWP is not set */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + +/* PKG_USING_PAHOMQTT is not set */ +/* PKG_USING_WEBCLIENT is not set */ +/* PKG_USING_WEBNET is not set */ +/* PKG_USING_MONGOOSE is not set */ +/* PKG_USING_WEBTERMINAL is not set */ +/* PKG_USING_CJSON is not set */ +/* PKG_USING_JSMN is not set */ +/* PKG_USING_LIBMODBUS is not set */ +/* PKG_USING_FREEMODBUS is not set */ +/* PKG_USING_LJSON is not set */ +/* PKG_USING_EZXML is not set */ +/* PKG_USING_NANOPB is not set */ + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* PKG_USING_WLANMARVELL is not set */ + +/* Wiced WiFi */ + +/* PKG_USING_WLAN_WICED is not set */ +/* PKG_USING_RW007 is not set */ +/* PKG_USING_COAP is not set */ +/* PKG_USING_NOPOLL is not set */ +/* PKG_USING_NETUTILS is not set */ +/* PKG_USING_AT_DEVICE is not set */ +/* PKG_USING_ATSRV_SOCKET is not set */ +/* PKG_USING_WIZNET is not set */ + +/* IoT Cloud */ + +/* PKG_USING_ONENET is not set */ +/* PKG_USING_GAGENT_CLOUD is not set */ +/* PKG_USING_ALI_IOTKIT is not set */ +/* PKG_USING_AZURE is not set */ +/* PKG_USING_TENCENT_IOTHUB is not set */ +/* PKG_USING_NIMBLE is not set */ +/* PKG_USING_OTA_DOWNLOADER is not set */ +/* PKG_USING_IPMSG is not set */ +/* PKG_USING_LSSDP is not set */ +/* PKG_USING_AIRKISS_OPEN is not set */ +/* PKG_USING_LIBRWS is not set */ +/* PKG_USING_TCPSERVER is not set */ + +/* security packages */ + +/* PKG_USING_MBEDTLS is not set */ +/* PKG_USING_libsodium is not set */ +/* PKG_USING_TINYCRYPT is not set */ + +/* language packages */ + +/* PKG_USING_LUA is not set */ +/* PKG_USING_JERRYSCRIPT is not set */ +/* PKG_USING_MICROPYTHON is not set */ + +/* multimedia packages */ + +/* PKG_USING_OPENMV is not set */ +/* PKG_USING_MUPDF is not set */ +/* PKG_USING_STEMWIN is not set */ + +/* tools packages */ + +/* PKG_USING_CMBACKTRACE is not set */ +/* PKG_USING_EASYFLASH is not set */ +/* PKG_USING_EASYLOGGER is not set */ +/* PKG_USING_SYSTEMVIEW is not set */ +/* PKG_USING_RDB is not set */ +/* PKG_USING_QRCODE is not set */ +/* PKG_USING_ULOG_EASYFLASH is not set */ +/* PKG_USING_ADBD is not set */ + +/* system packages */ + +/* PKG_USING_GUIENGINE is not set */ +/* PKG_USING_PERSIMMON is not set */ +/* PKG_USING_CAIRO is not set */ +/* PKG_USING_PIXMAN is not set */ +/* PKG_USING_LWEXT4 is not set */ +/* PKG_USING_PARTITION is not set */ +/* PKG_USING_FAL is not set */ +/* PKG_USING_SQLITE is not set */ +/* PKG_USING_RTI is not set */ +/* PKG_USING_LITTLEVGL2RTT is not set */ +/* PKG_USING_CMSIS is not set */ +/* PKG_USING_DFS_YAFFS is not set */ +/* PKG_USING_LITTLEFS is not set */ +/* PKG_USING_THREAD_POOL is not set */ + +/* peripheral libraries and drivers */ + +/* PKG_USING_SENSORS_DRIVERS is not set */ +/* PKG_USING_REALTEK_AMEBA is not set */ +/* PKG_USING_SHT2X is not set */ +/* PKG_USING_STM32_SDIO is not set */ +/* PKG_USING_ICM20608 is not set */ +/* PKG_USING_U8G2 is not set */ +/* PKG_USING_BUTTON is not set */ +/* PKG_USING_PCF8574 is not set */ +/* PKG_USING_SX12XX is not set */ +/* PKG_USING_SIGNAL_LED is not set */ +/* PKG_USING_LEDBLINK is not set */ +/* PKG_USING_WM_LIBRARIES is not set */ +/* PKG_USING_KENDRYTE_SDK is not set */ +/* PKG_USING_INFRARED is not set */ +/* PKG_USING_ROSSERIAL is not set */ +/* PKG_USING_AT24CXX is not set */ +/* PKG_USING_MOTIONDRIVER2RTT is not set */ +/* PKG_USING_AD7746 is not set */ +/* PKG_USING_PCA9685 is not set */ +/* PKG_USING_I2C_TOOLS is not set */ +/* PKG_USING_NRF24L01 is not set */ +/* PKG_USING_TOUCH_DRIVERS is not set */ +/* PKG_USING_LCD_DRIVERS is not set */ + +/* miscellaneous packages */ + +/* PKG_USING_LIBCSV is not set */ +/* PKG_USING_OPTPARSE is not set */ +/* PKG_USING_FASTLZ is not set */ +/* PKG_USING_MINILZO is not set */ +/* PKG_USING_QUICKLZ is not set */ +/* PKG_USING_MULTIBUTTON is not set */ +/* PKG_USING_CANFESTIVAL is not set */ +/* PKG_USING_ZLIB is not set */ +/* PKG_USING_DSTR is not set */ +/* PKG_USING_TINYFRAME is not set */ +/* PKG_USING_KENDRYTE_DEMO is not set */ +/* PKG_USING_DIGITALCTRL is not set */ + +/* samples: kernel and components samples */ + +/* PKG_USING_KERNEL_SAMPLES is not set */ +/* PKG_USING_FILESYSTEM_SAMPLES is not set */ +/* PKG_USING_NETWORK_SAMPLES is not set */ +/* PKG_USING_PERIPHERAL_SAMPLES is not set */ +/* PKG_USING_HELLO is not set */ +/* PKG_USING_VI is not set */ +/* PKG_USING_NNOM is not set */ +/* PKG_USING_LIBANN is not set */ +#define BCM2836_SOC + +/* Hardware Drivers Config */ + +/* BCM Peripheral Drivers */ + +#define BSP_USING_UART +/* RT_USING_UART0 is not set */ +#define RT_USING_UART1 +#define BSP_USING_PIN +#define BSP_USING_SYSTIMER +#define RT_USING_SYSTIMER1 +#define RT_USING_SYSTIMER3 +#define BSP_USING_I2C +#define BSP_USING_I2C0 +#define BSP_USING_I2C1 +#define BSP_USING_SPI +#define BSP_USING_SPI0_BUS +#define BSP_USING_SPI0_DEVICE0 +#define BSP_USING_SPI0_DEVICE1 +#define BSP_USING_WDT +#define BSP_USING_RTC +/* BSP_USING_ALARM is not set */ +#define BSP_USING_SDIO +#define BSP_USING_SDIO0 +#define BSP_USING_HDMI + +#endif diff --git a/bsp/raspberry-pi/raspi3-32/rtconfig.py b/bsp/raspberry-pi/raspi3-32/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..fb37e924821c762d20f9132037b25b6e524224d3 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-32/rtconfig.py @@ -0,0 +1,52 @@ +import os + +# toolchains options +ARCH ='armv8-a' +CPU ='cortex-a53' +CROSS_TOOL ='gcc' + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = r'../../..' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +PLATFORM = 'gcc' +EXEC_PATH = r'/usr/bin' +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mfloat-abi=softfp -march=armv8-a -mtune=cortex-a53 -ftree-vectorize -ffast-math' + CFLAGS = DEVICE + ' -Wall' + AFLAGS = ' -c' + ' -march=armv8-a -x assembler-with-cpp -D__ASSEMBLY__' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET kernel7.img\n' + SIZE + ' $TARGET \n' diff --git a/bsp/synopsys/emsk_em9d/.config b/bsp/raspberry-pi/raspi3-64/.config similarity index 57% rename from bsp/synopsys/emsk_em9d/.config rename to bsp/raspberry-pi/raspi3-64/.config index 8451f5d956f0ddd8378ed9c6bfc370b58b4ec5ed..d51c923bf95bfb54459b95c28d1cff0fd1372371 100644 --- a/bsp/synopsys/emsk_em9d/.config +++ b/bsp/raspberry-pi/raspi3-64/.config @@ -1,12 +1,13 @@ # # Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration +# RT-Thread Project Configuration # # # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -18,8 +19,10 @@ CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 -# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_IDLE_THREAD_STACK_SIZE=2048 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 CONFIG_RT_DEBUG=y CONFIG_RT_DEBUG_COLOR=y # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -47,30 +50,38 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # Memory Management # CONFIG_RT_USING_MEMPOOL=y -# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_MEMHEAP=y # CONFIG_RT_USING_NOHEAP is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +CONFIG_RT_USING_MEMTRACE=y CONFIG_RT_USING_HEAP=y # # Kernel Device Object # CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set +CONFIG_RT_USING_DEVICE_OPS=y # CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40000 +CONFIG_RT_VER_NUM=0x40002 +CONFIG_ARCH_CPU_64BIT=y +CONFIG_ARCH_ARM=y +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_ARM_CORTEX_AARCH64=y +CONFIG_ARCH_ARM_CORTEX_A53=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # # RT-Thread Components # CONFIG_RT_USING_COMPONENTS_INIT=y -# CONFIG_RT_USING_USER_MAIN is not set +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 # # C++ features @@ -93,7 +104,7 @@ CONFIG_FINSH_CMD_SIZE=80 # CONFIG_FINSH_USING_AUTH is not set CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_USING_MSH_DEFAULT=y -# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_USING_MSH_ONLY=y CONFIG_FINSH_ARG_MAX=10 # @@ -111,15 +122,16 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set # CONFIG_RT_USING_DFS_JFFS2 is not set -# CONFIG_RT_USING_DFS_NFS is not set # # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y -CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set @@ -129,17 +141,15 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set - -# -# Using WiFi -# +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set # @@ -153,7 +163,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_POSIX is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set # CONFIG_RT_USING_MODULE is not set # @@ -163,88 +176,22 @@ CONFIG_RT_USING_LIBC=y # # Socket abstraction layer # -CONFIG_RT_USING_SAL=y +# CONFIG_RT_USING_SAL is not set # -# protocol stack implement +# Network interface device # -CONFIG_SAL_USING_LWIP=y -CONFIG_SAL_USING_AT=y -# CONFIG_SAL_USING_POSIX is not set -CONFIG_SAL_SOCKETS_NUM=16 -CONFIG_SAL_PROTO_FAMILIES_NUM=4 +# CONFIG_RT_USING_NETDEV is not set # # light weight TCP/IP stack # -CONFIG_RT_USING_LWIP=y -# CONFIG_RT_USING_LWIP141 is not set -CONFIG_RT_USING_LWIP202=y -# CONFIG_RT_USING_LWIP210 is not set -# CONFIG_RT_USING_LWIP_IPV6 is not set -CONFIG_RT_LWIP_IGMP=y -CONFIG_RT_LWIP_ICMP=y -# CONFIG_RT_LWIP_SNMP is not set -CONFIG_RT_LWIP_DNS=y -CONFIG_RT_LWIP_DHCP=y -CONFIG_IP_SOF_BROADCAST=1 -CONFIG_IP_SOF_BROADCAST_RECV=1 - -# -# Static IPv4 Address -# -CONFIG_RT_LWIP_IPADDR="192.168.1.30" -CONFIG_RT_LWIP_GWADDR="192.168.1.1" -CONFIG_RT_LWIP_MSKADDR="255.255.255.0" -CONFIG_RT_LWIP_UDP=y -CONFIG_RT_LWIP_TCP=y -# CONFIG_RT_LWIP_RAW is not set -# CONFIG_RT_LWIP_PPP is not set -CONFIG_RT_MEMP_NUM_NETCONN=8 -CONFIG_RT_LWIP_PBUF_NUM=16 -CONFIG_RT_LWIP_RAW_PCB_NUM=4 -CONFIG_RT_LWIP_UDP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_SEG_NUM=40 -CONFIG_RT_LWIP_TCP_SND_BUF=8196 -CONFIG_RT_LWIP_TCP_WND=8196 -CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 -CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 -CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 -# CONFIG_LWIP_NO_RX_THREAD is not set -# CONFIG_LWIP_NO_TX_THREAD is not set -CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 -CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 -CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 -# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set -CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 -CONFIG_SO_REUSE=1 -CONFIG_LWIP_SO_RCVTIMEO=1 -CONFIG_LWIP_SO_SNDTIMEO=1 -CONFIG_LWIP_SO_RCVBUF=1 -# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set -CONFIG_LWIP_NETIF_LOOPBACK=0 -# CONFIG_RT_LWIP_STATS is not set -# CONFIG_RT_LWIP_DEBUG is not set - -# -# Modbus master and slave stack -# -# CONFIG_RT_USING_MODBUS is not set +# CONFIG_RT_USING_LWIP is not set # # AT commands # -CONFIG_RT_USING_AT=y -# CONFIG_AT_DEBUG is not set -# CONFIG_AT_USING_SERVER is not set -CONFIG_AT_USING_CLIENT=y -CONFIG_AT_CLIENT_NUM_MAX=1 -CONFIG_AT_USING_SOCKET=y -CONFIG_AT_USING_CLI=y -# CONFIG_AT_PRINT_RAW_CMD is not set -CONFIG_AT_SW_VERSION_NUM=0x10200 -# CONFIG_LWIP_USING_DHCPD is not set +# CONFIG_RT_USING_AT is not set # # VBUS(Virtual Software BUS) @@ -254,7 +201,6 @@ CONFIG_AT_SW_VERSION_NUM=0x10200 # # Utilities # -# CONFIG_RT_USING_LOGTRACE is not set # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set @@ -268,10 +214,13 @@ CONFIG_AT_SW_VERSION_NUM=0x10200 # # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_LJSON is not set # CONFIG_PKG_USING_EZXML is not set # CONFIG_PKG_USING_NANOPB is not set @@ -289,25 +238,14 @@ CONFIG_AT_SW_VERSION_NUM=0x10200 # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set -CONFIG_PKG_USING_AT_DEVICE=y -CONFIG_PKG_AT_DEVICE_PATH="/packages/iot/at_device" -CONFIG_PKG_AT_INIT_BY_THREAD=y -# CONFIG_AT_DEVICE_M26 is not set -# CONFIG_AT_DEVICE_EC20 is not set -CONFIG_AT_DEVICE_ESP8266=y -# CONFIG_AT_DEVICE_NOT_SELECTED is not set -CONFIG_AT_DEVICE_SOCKETS_NUM=5 -CONFIG_AT_DEVICE_NAME="uart0" -CONFIG_AT_DEVICE_RECV_BUFF_LEN=512 -CONFIG_AT_DEVICE_WIFI_SSID="embarc" -CONFIG_AT_DEVICE_WIFI_PASSWORD="qazwsxedc" -CONFIG_PKG_USING_AT_DEVICE_LATEST_VERSION=y -# CONFIG_PKG_USING_AT_DEVICE_V100 is not set -# CONFIG_PKG_USING_AT_DEVICE_V110 is not set -CONFIG_PKG_AT_DEVICE_VER="latest" +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set # # IoT Cloud @@ -316,6 +254,21 @@ CONFIG_PKG_AT_DEVICE_VER="latest" # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set # # security packages @@ -336,6 +289,9 @@ CONFIG_PKG_AT_DEVICE_VER="latest" # # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set # # tools packages @@ -344,6 +300,12 @@ CONFIG_PKG_AT_DEVICE_VER="latest" # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set # # system packages @@ -357,17 +319,42 @@ CONFIG_PKG_AT_DEVICE_VER="latest" # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set # # peripheral libraries and drivers # -# CONFIG_PKG_USING_STM32F4_HAL is not set -# CONFIG_PKG_USING_STM32F4_DRIVERS is not set +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set # CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_LCD_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set # # miscellaneous packages @@ -378,13 +365,15 @@ CONFIG_PKG_AT_DEVICE_VER="latest" # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set # CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_DSTR is not set - -# -# sample package -# +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set # # samples: kernel and components samples @@ -393,11 +382,37 @@ CONFIG_PKG_AT_DEVICE_VER="latest" # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +CONFIG_BCM2836_SOC=y +# CONFIG_BSP_SUPPORT_FPU is not set # -# example package: hello +# Hardware Drivers Config # -# CONFIG_PKG_USING_HELLO is not set -CONFIG_SOC_EMSK=y -CONFIG_EMSK_USING_UART0=y -CONFIG_EMSK_USING_UART1=y + +# +# BCM Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +# CONFIG_RT_USING_UART0 is not set +CONFIG_RT_USING_UART1=y +CONFIG_BSP_USING_PIN=y +# CONFIG_BSP_USING_SYSTIMER is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SDIO is not set + +# +# Board Peripheral Drivers +# +# CONFIG_BSP_USING_HDMI is not set diff --git a/bsp/raspberry-pi/raspi3-64/Kconfig b/bsp/raspberry-pi/raspi3-64/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..e596378e077c6ac90afa5623363dbdebdd95e60c --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/Kconfig @@ -0,0 +1,29 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config BCM2836_SOC + bool + select ARCH_ARM_CORTEX_A53 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select ARCH_CPU_64BIT + default y + +source "driver/Kconfig" diff --git a/bsp/raspberry-pi/raspi3-64/README.md b/bsp/raspberry-pi/raspi3-64/README.md new file mode 100644 index 0000000000000000000000000000000000000000..28e00f96c082b426e771953beeeb2ae2a66df77f --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/README.md @@ -0,0 +1,100 @@ +# Raspberry PI 3-64板级支持包说明 + +## 1. 简介 + +树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发，莓派3有三个发行版本： + +* B : 4核 Broadcom BCM2837 (ARMv8-A) 1.2GHz，双核VideoCore IV GPU，1GB内存，100 Base-T Ethernet +* B+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 1GB LPDDR2 SDRAM， GigaE over USB 2.0 +* A+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 512MB LPDDR2 SDRAM + +这份RT-Thread BSP是针对 Raspberry Pi 3 64位模式的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。 + + +## 2. 编译说明 + +### 2.1 Window上的环境搭建 + +Windows环境下推荐使用[env工具][1]进行编译。 + +首先下载Linux上的gcc工具，版本为gcc-arm-8.3选择aarch64-elf就可以。 + +将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。 + +接着修改`bsp\raspberry-pi\raspi3-64\rtconfig.py` + +修改路径： + +``` +EXEC_PATH = r'E:/env_released_1.1.2/env/tools/gnu_gcc/arm_gcc/gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf/bin' +``` + +然后在`bsp\raspberry-pi\raspi3-64\`下输入scons编译即可。 + +### 2.2 Linux上的环境搭建 + +Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。 + +直接进入`bsp\raspberry-pi\raspi3-64`，输入scons编译即可。 + + +## 3. 执行 + +### 3.1 下载[raspbian镜像][3]，生成可以运行的raspbian SD卡 + +Windows下，去[etcher.io][4]下载etcher,这是个可以烧写img的工具 + +解开下载的镜像文件, linux下使用如下的命令 + +``` +unzip 2018-06-27-raspbian-stretch-lite.zip +``` + +准备一张空SD卡，linux环境下，插入电脑并执行 + +``` +sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync +``` + +**注意: /dev/xxx 要换成真实环境中的SD卡所在设置，千万不要弄错。** + +Windows环境下，执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。 + +最后把kernel8.img放入SD boot分区，删除其它 kernel*.img。 + +### 3.2 准备好串口线 + +目前版本是使用raspi3的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示(图片中的板子是pi2，GPIO引脚是一样的)： + +![raspi2](figures/raspi_uart.png) + +串口参数： 115200 8N1 ，硬件和软件流控为关。 + +按上面的方法做好SD卡后，插入树莓派，通电可以在串口上看到如下所示的输出信息： + +```text + heap: 0x00020b20 - 0x00400000 + + \ | / +- RT - Thread Operating System + / | \ 3.1.0 build Aug 23 2019 + 2006 - 2019 Copyright by rt-thread team +Hello RT-Thread! +msh > +``` + +## 4. 支持情况 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | UART0| + +## 5. 联系人信息 + +维护人：[bernard][5] + +[1]: https://www.rt-thread.org/page/download.html +[2]: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads +[3]: https://downloads.raspberrypi.org/raspbian_lite_latest +[4]: https://etcher.io +[5]: https://github.com/BernardXiong diff --git a/bsp/raspberry-pi/raspi3-64/SConscript b/bsp/raspberry-pi/raspi3-64/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..c7ef7659ecea92b1dd9b71a97736a8552ee02551 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/raspberry-pi/raspi3-64/SConstruct b/bsp/raspberry-pi/raspi3-64/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..93f349aab8045ad3c742e72664514a7c240b2b6e --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/SConstruct @@ -0,0 +1,30 @@ +import os +import sys +import rtconfig + +from rtconfig import RTT_ROOT + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) + +# make a building +DoBuilding(TARGET, objs) + diff --git a/bsp/raspberry-pi/raspi3-64/applications/SConscript b/bsp/raspberry-pi/raspi3-64/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..fdf93d423539b5b0bdafc948a1fb549fbc647e3b --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('test/*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/raspberry-pi/raspi3-64/applications/main.c b/bsp/raspberry-pi/raspi3-64/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..bcccbecc00d1ac1c65b159cddd141f30269ec563 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/applications/main.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-5-30 bernard the first version + */ + +#include + +int main(int argc, char** argv) +{ + rt_kprintf("Hi, this is RT-Thread!!\n"); + + return 0; +} + diff --git a/bsp/raspberry-pi/raspi3-64/applications/mnt.c b/bsp/raspberry-pi/raspi3-64/applications/mnt.c new file mode 100644 index 0000000000000000000000000000000000000000..8ec394eb8cbddabd2ce166016621ac2cd8f7df8f --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/applications/mnt.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-5-30 bernard the first version + */ + +#include + +int mnt_init(void) +{ + return 0; +} diff --git a/bsp/raspberry-pi/raspi3-64/applications/test/gpio.h b/bsp/raspberry-pi/raspi3-64/applications/test/gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..52fa671d0f1e03d2315980cd0c575f00c204f10f --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/applications/test/gpio.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2018 bzt (bztsrc@github) + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +#define MMIO_BASE 0x3F000000 + +#define GPFSEL0 ((volatile unsigned int*)(MMIO_BASE+0x00200000)) +#define GPFSEL1 ((volatile unsigned int*)(MMIO_BASE+0x00200004)) +#define GPFSEL2 ((volatile unsigned int*)(MMIO_BASE+0x00200008)) +#define GPFSEL3 ((volatile unsigned int*)(MMIO_BASE+0x0020000C)) +#define GPFSEL4 ((volatile unsigned int*)(MMIO_BASE+0x00200010)) +#define GPFSEL5 ((volatile unsigned int*)(MMIO_BASE+0x00200014)) +#define GPSET0 ((volatile unsigned int*)(MMIO_BASE+0x0020001C)) +#define GPSET1 ((volatile unsigned int*)(MMIO_BASE+0x00200020)) +#define GPCLR0 ((volatile unsigned int*)(MMIO_BASE+0x00200028)) +#define GPLEV0 ((volatile unsigned int*)(MMIO_BASE+0x00200034)) +#define GPLEV1 ((volatile unsigned int*)(MMIO_BASE+0x00200038)) +#define GPEDS0 ((volatile unsigned int*)(MMIO_BASE+0x00200040)) +#define GPEDS1 ((volatile unsigned int*)(MMIO_BASE+0x00200044)) +#define GPHEN0 ((volatile unsigned int*)(MMIO_BASE+0x00200064)) +#define GPHEN1 ((volatile unsigned int*)(MMIO_BASE+0x00200068)) +#define GPPUD ((volatile unsigned int*)(MMIO_BASE+0x00200094)) +#define GPPUDCLK0 ((volatile unsigned int*)(MMIO_BASE+0x00200098)) +#define GPPUDCLK1 ((volatile unsigned int*)(MMIO_BASE+0x0020009C)) diff --git a/bsp/raspberry-pi/raspi3-64/applications/test/uart.c b/bsp/raspberry-pi/raspi3-64/applications/test/uart.c new file mode 100644 index 0000000000000000000000000000000000000000..b3dd4da7eaeac8067715c21b2fd6d5c134f83b0f --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/applications/test/uart.c @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2018 bzt (bztsrc@github) + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +#include "gpio.h" + +/* Auxilary mini UART registers */ +#define AUX_ENABLE ((volatile unsigned int*)(MMIO_BASE+0x00215004)) +#define AUX_MU_IO ((volatile unsigned int*)(MMIO_BASE+0x00215040)) +#define AUX_MU_IER ((volatile unsigned int*)(MMIO_BASE+0x00215044)) +#define AUX_MU_IIR ((volatile unsigned int*)(MMIO_BASE+0x00215048)) +#define AUX_MU_LCR ((volatile unsigned int*)(MMIO_BASE+0x0021504C)) +#define AUX_MU_MCR ((volatile unsigned int*)(MMIO_BASE+0x00215050)) +#define AUX_MU_LSR ((volatile unsigned int*)(MMIO_BASE+0x00215054)) +#define AUX_MU_MSR ((volatile unsigned int*)(MMIO_BASE+0x00215058)) +#define AUX_MU_SCRATCH ((volatile unsigned int*)(MMIO_BASE+0x0021505C)) +#define AUX_MU_CNTL ((volatile unsigned int*)(MMIO_BASE+0x00215060)) +#define AUX_MU_STAT ((volatile unsigned int*)(MMIO_BASE+0x00215064)) +#define AUX_MU_BAUD ((volatile unsigned int*)(MMIO_BASE+0x00215068)) + +/** + * Set baud rate and characteristics (115200 8N1) and map to GPIO + */ +void uart_init() +{ + register unsigned int r; + + /* initialize UART */ + *AUX_ENABLE |=1; // enable UART1, AUX mini uart + *AUX_MU_CNTL = 0; + *AUX_MU_LCR = 3; // 8 bits + *AUX_MU_MCR = 0; + *AUX_MU_IER = 0; + *AUX_MU_IIR = 0xc6; // disable interrupts + *AUX_MU_BAUD = 270; // 115200 baud + /* map UART1 to GPIO pins */ + r=*GPFSEL1; + r&=~((7<<12)|(7<<15)); // gpio14, gpio15 + r|=(2<<12)|(2<<15); // alt5 + *GPFSEL1 = r; + *GPPUD = 0; // enable pins 14 and 15 + r=150; while(r--) { asm volatile("nop"); } + *GPPUDCLK0 = (1<<14)|(1<<15); + r=150; while(r--) { asm volatile("nop"); } + *GPPUDCLK0 = 0; // flush GPIO setup + *AUX_MU_CNTL = 3; // enable Tx, Rx +} + +/** + * Send a character + */ +void uart_send(unsigned int c) { + /* wait until we can send */ + do{asm volatile("nop");}while(!(*AUX_MU_LSR&0x20)); + /* write the character to the buffer */ + *AUX_MU_IO=c; +} + +/** + * Receive a character + */ +char uart_getc() { + char r; + /* wait until something is in the buffer */ + do{asm volatile("nop");}while(!(*AUX_MU_LSR&0x01)); + /* read it and return */ + r=(char)(*AUX_MU_IO); + /* convert carrige return to newline */ + return r=='\r'?'\n':r; +} + +/** + * Display a string + */ +void uart_puts(char *s) { + while(*s) { + /* convert newline to carrige return + newline */ + if(*s=='\n') + uart_send('\r'); + uart_send(*s++); + } +} diff --git a/bsp/raspberry-pi/raspi3-64/applications/test/uart.h b/bsp/raspberry-pi/raspi3-64/applications/test/uart.h new file mode 100644 index 0000000000000000000000000000000000000000..72f8e3151f0831ac2922d0cb0a3aa16e27ca9947 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/applications/test/uart.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2018 bzt (bztsrc@github) + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +void uart_init(); +void uart_send(unsigned int c); +char uart_getc(); +void uart_puts(char *s); diff --git a/bsp/raspberry-pi/raspi3-64/driver/Kconfig b/bsp/raspberry-pi/raspi3-64/driver/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..e45d0a3ca2632208d6618eaccd9fdc2cedc1a16e --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/Kconfig @@ -0,0 +1,112 @@ + +config BSP_SUPPORT_FPU + bool "Using Float" + default n + +menu "Hardware Drivers Config" + menu "BCM Peripheral Drivers" + menuconfig BSP_USING_UART + bool "Using UART" + select RT_USING_SERIAL + default y + + if BSP_USING_UART + config RT_USING_UART0 + bool "Enabel UART 0" + default y + + config RT_USING_UART1 + bool "Enabel UART 1" + default n + endif + + config BSP_USING_PIN + bool "Using PIN" + select RT_USING_PIN + default y + + menuconfig BSP_USING_SYSTIMER + bool "Enable SYSTIMER" + select RT_USING_SYSTIMER + default n + + if RT_USING_SYSTIMER + config RT_USING_SYSTIMER1 + bool "Enable sys timer1" + default n + config RT_USING_SYSTIMER3 + bool "Enable sys timer3" + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C" + select RT_USING_I2C + default n + + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default n + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI" + select RT_USING_SPI + default n + + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0" + default n + config BSP_USING_SPI1 + bool "Enable SPI1" + default n + endif + + config BSP_USING_WDT + bool "Enable WDT" + select RT_USING_WDT + default n + + menuconfig BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + + if BSP_USING_RTC + config BSP_USING_ALARM + bool "Enable Alarm" + select RT_USING_ALARM + default n + endif + + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + default n + + if BSP_USING_SDIO + config BSP_USING_SDIO0 + bool "Enable SDIO0" + select RT_USING_SDIO + default n + endif + endmenu + + menu "Board Peripheral Drivers" + menuconfig BSP_USING_HDMI + bool "Enable HDMI" + select BSP_USING_SPI + default n + + if BSP_USING_HDMI + config BSP_USING_HDMI_DISPLAY + bool "HDMI DISPLAY" + default n + endif + endmenu +endmenu diff --git a/bsp/raspberry-pi/raspi3-64/driver/SConscript b/bsp/raspberry-pi/raspi3-64/driver/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..2c19b9436dc7194e310f73c00164242108a6067f --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/SConscript @@ -0,0 +1,32 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Split(''' +board.c +bcm283x.c +drv_uart.c +mbox.c +''') +CPPPATH = [cwd] + +if GetDepend('BSP_USING_SYSTIMER'): + src += ['drv_timer.c'] +if GetDepend('BSP_USING_PIN'): + src += ['drv_gpio.c'] +if GetDepend('BSP_USING_I2C'): + src += ['drv_i2c.c'] +if GetDepend('BSP_USING_WDT'): + src += ['drv_wdt.c'] +if GetDepend('BSP_USING_SPI'): + src += ['drv_spi.c'] +if GetDepend('BSP_USING_SDIO'): + src += ['drv_sdio.c'] +if GetDepend('BSP_USING_RTC'): + src += ['drv_rtc.c'] +if GetDepend('BSP_USING_HDMI'): + src += ['drv_fb.c'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/raspberry-pi/raspi3-64/driver/bcm283x.c b/bsp/raspberry-pi/raspi3-64/driver/bcm283x.c new file mode 100644 index 0000000000000000000000000000000000000000..ea92c33a0fb856be1995b5098c41263e38ab8c53 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/bcm283x.c @@ -0,0 +1,575 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#include "bcm283x.h" + +rt_uint32_t bcm283x_peri_read(volatile rt_ubase_t addr) +{ + rt_uint32_t ret; + __sync_synchronize(); + ret = HWREG32(addr); + __sync_synchronize(); + return ret; +} + +rt_uint32_t bcm283x_peri_read_nb(volatile rt_ubase_t addr) +{ + return HWREG32(addr); +} + +void bcm283x_peri_write(volatile rt_ubase_t addr, rt_uint32_t value) +{ + __sync_synchronize(); + HWREG32(addr) = value; + __sync_synchronize(); +} + +void bcm283x_peri_write_nb(volatile rt_ubase_t addr, rt_uint32_t value) +{ + HWREG32(addr) = value; +} + +void bcm283x_peri_set_bits(volatile rt_ubase_t addr, rt_uint32_t value, rt_uint32_t mask) +{ + rt_uint32_t v = bcm283x_peri_read(addr); + v = (v & ~mask) | (value & mask); + bcm283x_peri_write(addr, v); +} + +void bcm283x_gpio_fsel(rt_uint8_t pin, rt_uint8_t mode) +{ + volatile rt_ubase_t addr = (BCM283X_GPIO_BASE + BCM283X_GPIO_GPFSEL0 + (pin / 10) * 4); + rt_uint8_t shift = (pin % 10) * 3; + rt_uint32_t mask = BCM283X_GPIO_FSEL_MASK << shift; + rt_uint32_t value = mode << shift; + + bcm283x_peri_set_bits(addr, value, mask); +} + +void bcm283x_gpio_set(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPSET0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + bcm283x_peri_write(addr, 1 << shift); +} + +void bcm283x_gpio_clr(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPCLR0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + bcm283x_peri_write(addr, 1 << shift); +} + +rt_uint8_t bcm283x_gpio_lev(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM2835_GPIO_GPLEV0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + rt_uint32_t value = bcm283x_peri_read(addr); + return (value & (1 << shift)) ? HIGH : LOW; +} + +rt_uint8_t bcm283x_gpio_eds(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + rt_uint32_t value = bcm283x_peri_read(addr); + return (value & (1 << shift)) ? HIGH : LOW; +} + +/* Write a 1 to clear the bit in EDS */ +void bcm283x_gpio_set_eds(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + rt_uint32_t value = 1 << shift; + bcm283x_peri_write(addr, value); +} + +/* Rising edge detect enable */ +void bcm283x_gpio_ren(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPREN0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + rt_uint32_t value = 1 << shift; + bcm283x_peri_set_bits(addr, value, value); +} + +void bcm283x_gpio_clr_ren(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPREN0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + rt_uint32_t value = 1 << shift; + bcm283x_peri_set_bits(addr, 0, value); +} + +/* Falling edge detect enable */ +void bcm283x_gpio_fen(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPFEN0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + rt_uint32_t value = 1 << shift; + bcm283x_peri_set_bits(addr, value, value); +} +void bcm283x_gpio_clr_fen(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPFEN0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + rt_uint32_t value = 1 << shift; + bcm283x_peri_set_bits(addr, 0, value); +} + +/* High detect enable */ +void bcm283x_gpio_hen(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPHEN0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + rt_uint32_t value = 1 << shift; + bcm283x_peri_set_bits(addr, value, value); +} + +void bcm283x_gpio_clr_hen(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPHEN0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + rt_uint32_t value = 1 << shift; + bcm283x_peri_set_bits(addr, 0, value); +} + +/* Low detect enable */ +void bcm283x_gpio_len(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPLEN0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + rt_uint32_t value = 1 << shift; + bcm283x_peri_set_bits(addr, value, value); +} + +void bcm283x_gpio_clr_len(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPLEN0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + rt_uint32_t value = 1 << shift; + bcm283x_peri_set_bits(addr, 0, value); +} + +/* Async rising edge detect enable */ +void bcm283x_gpio_aren(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPAREN0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + rt_uint32_t value = 1 << shift; + bcm283x_peri_set_bits(addr, value, value); +} +void bcm283x_gpio_clr_aren(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPAREN0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + rt_uint32_t value = 1 << shift; + bcm283x_peri_set_bits(addr, 0, value); +} + +/* Async falling edge detect enable */ +void bcm283x_gpio_afen(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPAFEN0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + rt_uint32_t value = 1 << shift; + bcm283x_peri_set_bits(addr, value, value); +} +void bcm283x_gpio_clr_afen(rt_uint8_t pin) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPAFEN0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + rt_uint32_t value = 1 << shift; + bcm283x_peri_set_bits(addr, 0, value); +} + +/* Set pullup/down */ +void bcm283x_gpio_pud(rt_uint8_t pud) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPPUD; + bcm283x_peri_write(addr, pud); +} + +/* Pullup/down clock +// Clocks the value of pud into the GPIO pin +*/ +void bcm283x_gpio_pudclk(rt_uint8_t pin, rt_uint8_t on) +{ + volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPPUDCLK0 + (pin / 32) * 4; + rt_uint8_t shift = pin % 32; + bcm283x_peri_write(addr, (on? 1 : 0) << shift); +} + +void bcm283x_gpio_set_pud(rt_uint8_t pin, rt_uint8_t pud) +{ + bcm283x_gpio_pud(pud); + bcm283x_clo_delayMicros(10); + + bcm283x_gpio_pudclk(pin, 1); + bcm283x_clo_delayMicros(10); + + bcm283x_gpio_pud(BCM283X_GPIO_PUD_OFF); + bcm283x_gpio_pudclk(pin, 0); +} + + +void bcm283x_gpio_write(rt_uint8_t pin, rt_uint8_t val) +{ + if (val) + bcm283x_gpio_set(pin); + else + bcm283x_gpio_clr(pin); +} + +rt_uint64_t bcm283x_st_read(void) +{ + volatile rt_ubase_t addr; + rt_uint32_t hi, lo; + rt_uint64_t st; + + addr = BCM283X_ST_BASE + BCM283X_ST_CHI; + hi = bcm283x_peri_read(addr); + + addr = BCM283X_ST_BASE + BCM283X_ST_CLO; + lo = bcm283x_peri_read(addr); + + addr = BCM283X_ST_BASE + BCM283X_ST_CHI; + st = bcm283x_peri_read(addr); + + /* Test for overflow */ + if (st == hi) + { + rt_kprintf(">> 1crash???\n"); + st <<= 32; + st += lo; + rt_kprintf(">> 2crash!!!\n"); + } + else + { + st <<= 32; + addr = BCM283X_ST_BASE + BCM283X_ST_CLO; + st += bcm283x_peri_read(addr); + } + return st; +} + +/* microseconds */ +void bcm283x_delayMicroseconds(rt_uint64_t micros) +{ + rt_uint64_t start; + + start = bcm283x_st_read(); + rt_kprintf("bcm283x_st_read result: %d\n", start); + + /* Not allowed to access timer registers (result is not as precise)*/ + if (start==0) + return; + + bcm283x_st_delay(start, micros); +} + +void bcm283x_clo_delayMicros(rt_uint32_t micros) +{ + volatile rt_uint32_t addr; + rt_uint32_t compare; + + addr = BCM283X_ST_BASE + BCM283X_ST_CLO; + compare = bcm283x_peri_read(addr) + micros; + while(bcm283x_peri_read(addr) < compare); +} + +void bcm283x_st_delay(rt_uint64_t offset_micros, rt_uint64_t micros) +{ + rt_uint64_t compare = offset_micros + micros; + while(bcm283x_st_read() < compare); +} + + +/* Read an number of bytes from I2C */ +rt_uint8_t bcm283x_i2c_read(rt_uint32_t base, rt_uint8_t* buf, rt_uint32_t len) +{ + volatile rt_uint32_t dlen = base + BCM283X_BSC_DLEN; + volatile rt_uint32_t fifo = base + BCM283X_BSC_FIFO; + volatile rt_uint32_t status = base + BCM283X_BSC_S; + volatile rt_uint32_t control = base + BCM283X_BSC_C; + + rt_uint32_t remaining = len; + rt_uint32_t i = 0; + rt_uint8_t reason = BCM283X_I2C_REASON_OK; + + /* Clear FIFO */ + bcm283x_peri_set_bits(control, BCM283X_BSC_C_CLEAR_1, BCM283X_BSC_C_CLEAR_1); + /* Clear Status */ + bcm283x_peri_write_nb(status, BCM283X_BSC_S_CLKT | BCM283X_BSC_S_ERR | BCM283X_BSC_S_DONE); + /* Set Data Length */ + bcm283x_peri_write_nb(dlen, len); + /* Start read */ + bcm283x_peri_write_nb(control, BCM283X_BSC_C_I2CEN | BCM283X_BSC_C_ST | BCM283X_BSC_C_READ); + + /* wait for transfer to complete */ + while (!(bcm283x_peri_read_nb(status) & BCM283X_BSC_S_DONE)) + { + /* we must empty the FIFO as it is populated and not use any delay */ + while (remaining && bcm283x_peri_read_nb(status) & BCM283X_BSC_S_RXD) + { + /* Read from FIFO, no barrier */ + buf[i] = bcm283x_peri_read_nb(fifo); + i++; + remaining--; + } + } + + /* transfer has finished - grab any remaining stuff in FIFO */ + while (remaining && (bcm283x_peri_read_nb(status) & BCM283X_BSC_S_RXD)) + { + /* Read from FIFO, no barrier */ + buf[i] = bcm283x_peri_read_nb(fifo); + i++; + remaining--; + } + + /* Received a NACK */ + if (bcm283x_peri_read(status) & BCM283X_BSC_S_ERR) + { + reason = BCM283X_I2C_REASON_ERROR_NACK; + } + + /* Received Clock Stretch Timeout */ + else if (bcm283x_peri_read(status) & BCM283X_BSC_S_CLKT) + { + reason = BCM283X_I2C_REASON_ERROR_CLKT; + } + + /* Not all data is received */ + else if (remaining) + { + reason = BCM283X_I2C_REASON_ERROR_DATA; + } + + bcm283x_peri_set_bits(control, BCM283X_BSC_S_DONE, BCM283X_BSC_S_DONE); + + return reason; +} + +int bcm283x_i2c_begin(int no) +{ + if (0 == no) + { + bcm283x_gpio_fsel(BCM_GPIO_PIN_0, BCM283X_GPIO_FSEL_ALT0); /* SDA */ + bcm283x_gpio_fsel(BCM_GPIO_PIN_1, BCM283X_GPIO_FSEL_ALT0); /* SCL */ + } + else + { + bcm283x_gpio_fsel(BCM_GPIO_PIN_2, BCM283X_GPIO_FSEL_ALT0); /* SDA */ + bcm283x_gpio_fsel(BCM_GPIO_PIN_3, BCM283X_GPIO_FSEL_ALT0); /* SCL */ + } + return 0; +} + +void bcm283x_i2c_end(int no) +{ + if (0 == no) + { + bcm283x_gpio_fsel(BCM_GPIO_PIN_0, BCM283X_GPIO_FSEL_INPT); /* SDA */ + bcm283x_gpio_fsel(BCM_GPIO_PIN_1, BCM283X_GPIO_FSEL_INPT); /* SCL */ + } + else + { + bcm283x_gpio_fsel(BCM_GPIO_PIN_2, BCM283X_GPIO_FSEL_INPT); /* SDA */ + bcm283x_gpio_fsel(BCM_GPIO_PIN_3, BCM283X_GPIO_FSEL_INPT); /* SCL */ + } +} + +void bcm283x_i2c_setSlaveAddress(int no, rt_uint8_t saddr) +{ + volatile rt_uint32_t addr; + if (0 == no) + addr = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_A; + else + addr = PER_BASE + BCM283X_BSC1_BASE + BCM283X_BSC_A; + + bcm283x_peri_write(addr, saddr); +} + +void bcm283x_i2c_setClockDivider(int no, rt_uint16_t divider) +{ + volatile rt_uint32_t addr; + if (0 == no) + addr = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_DIV; + else + addr = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_DIV; + bcm283x_peri_write(addr, divider); +} + +void bcm283x_i2c_set_baudrate(int no, rt_uint32_t baudrate) +{ + rt_uint32_t divider; + divider = (BCM283X_CORE_CLK_HZ / baudrate) & 0xFFFE; + bcm283x_i2c_setClockDivider(no, (rt_uint16_t)divider); +} + +/* Writes an number of bytes to I2C */ +rt_uint8_t bcm283x_i2c_write(rt_uint32_t base, const rt_uint8_t * buf, rt_uint32_t len) +{ + volatile rt_uint32_t dlen = base + BCM283X_BSC_DLEN; + volatile rt_uint32_t fifo = base + BCM283X_BSC_FIFO; + volatile rt_uint32_t status = base + BCM283X_BSC_S; + volatile rt_uint32_t control = base + BCM283X_BSC_C; + + rt_uint32_t remaining = len; + rt_uint32_t i = 0; + rt_uint8_t reason = BCM283X_I2C_REASON_OK; + + /* Clear FIFO */ + bcm283x_peri_set_bits(control, BCM283X_BSC_C_CLEAR_1, BCM283X_BSC_C_CLEAR_1); + /* Clear Status */ + bcm283x_peri_write(status, BCM283X_BSC_S_CLKT | BCM283X_BSC_S_ERR | BCM283X_BSC_S_DONE); + /* Set Data Length */ + bcm283x_peri_write(dlen, len); + /* pre populate FIFO with max buffer */ + while(remaining && (i < BCM283X_BSC_FIFO_SIZE)) + { + bcm283x_peri_write_nb(fifo, buf[i]); + i++; + remaining--; + } + + /* Enable device and start transfer */ + bcm283x_peri_write(control, BCM283X_BSC_C_I2CEN | BCM283X_BSC_C_ST); + + /* Transfer is over when BCM2835_BSC_S_DONE */ + while(!(bcm283x_peri_read(status) & BCM283X_BSC_S_DONE)) + { + while (remaining && (bcm283x_peri_read(status) & BCM283X_BSC_S_TXD)) + { + /* Write to FIFO */ + bcm283x_peri_write(fifo, buf[i]); + i++; + remaining--; + } + } + + /* Received a NACK */ + if (bcm283x_peri_read(status) & BCM283X_BSC_S_ERR) + { + reason = BCM283X_I2C_REASON_ERROR_NACK; + } + + /* Received Clock Stretch Timeout */ + else if (bcm283x_peri_read(status) & BCM283X_BSC_S_CLKT) + { + reason = BCM283X_I2C_REASON_ERROR_CLKT; + } + + /* Not all data is sent */ + else if (remaining) + { + reason = BCM283X_I2C_REASON_ERROR_DATA; + } + + bcm283x_peri_set_bits(control, BCM283X_BSC_S_DONE, BCM283X_BSC_S_DONE); + + return reason; +} + +rt_uint8_t bcm283x_i2c_write_read_rs(char* cmds, rt_uint32_t cmds_len, char* buf, rt_uint32_t buf_len) +{ + volatile rt_uint32_t dlen = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_DLEN; + volatile rt_uint32_t fifo = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_FIFO; + volatile rt_uint32_t status = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_S; + volatile rt_uint32_t control = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_C; + + rt_uint32_t remaining = cmds_len; + rt_uint32_t i = 0; + rt_uint8_t reason = BCM283X_I2C_REASON_OK; + + /* Clear FIFO */ + bcm283x_peri_set_bits(control, BCM283X_BSC_C_CLEAR_1, BCM283X_BSC_C_CLEAR_1); + + /* Clear Status */ + bcm283x_peri_write(status, BCM283X_BSC_S_CLKT | BCM283X_BSC_S_ERR | BCM283X_BSC_S_DONE); + + /* Set Data Length */ + bcm283x_peri_write(dlen, cmds_len); + + /* pre populate FIFO with max buffer */ + while(remaining && (i < BCM283X_BSC_FIFO_SIZE)) + { + bcm283x_peri_write_nb(fifo, cmds[i]); + i++; + remaining--; + } + + /* Enable device and start transfer */ + bcm283x_peri_write(control, BCM283X_BSC_C_I2CEN | BCM283X_BSC_C_ST); + + /* poll for transfer has started (way to do repeated start, from BCM2835 datasheet) */ + while (!(bcm283x_peri_read(status) & BCM283X_BSC_S_TA)) + { + /* Linux may cause us to miss entire transfer stage */ + if (bcm283x_peri_read_nb(status) & BCM283X_BSC_S_DONE) + break; + } + + remaining = buf_len; + i = 0; + + /* Send a repeated start with read bit set in address */ + bcm283x_peri_write(dlen, buf_len); + bcm283x_peri_write(control, BCM283X_BSC_C_I2CEN | BCM283X_BSC_C_ST | BCM283X_BSC_C_READ); + + /* Wait for write to complete and first byte back. */ + bcm283x_clo_delayMicros(100); + + /* wait for transfer to complete */ + while (!(bcm283x_peri_read_nb(status) & BCM283X_BSC_S_DONE)) + { + /* we must empty the FIFO as it is populated and not use any delay */ + while (remaining && bcm283x_peri_read(status) & BCM283X_BSC_S_RXD) + { + /* Read from FIFO, no barrier */ + buf[i] = bcm283x_peri_read_nb(fifo); + i++; + remaining--; + } + } + + /* transfer has finished - grab any remaining stuff in FIFO */ + while (remaining && (bcm283x_peri_read(status) & BCM283X_BSC_S_RXD)) + { + /* Read from FIFO */ + buf[i] = bcm283x_peri_read(fifo); + i++; + remaining--; + } + + /* Received a NACK */ + if (bcm283x_peri_read(status) & BCM283X_BSC_S_ERR) + { + reason = BCM283X_I2C_REASON_ERROR_NACK; + } + + /* Received Clock Stretch Timeout */ + else if (bcm283x_peri_read(status) & BCM283X_BSC_S_CLKT) + { + reason = BCM283X_I2C_REASON_ERROR_CLKT; + } + + /* Not all data is sent */ + else if (remaining) + { + reason = BCM283X_I2C_REASON_ERROR_DATA; + } + + bcm283x_peri_set_bits(control, BCM283X_BSC_S_DONE, BCM283X_BSC_S_DONE); + + return reason; +} diff --git a/bsp/raspberry-pi/raspi3-64/driver/bcm283x.h b/bsp/raspberry-pi/raspi3-64/driver/bcm283x.h new file mode 100644 index 0000000000000000000000000000000000000000..fc9ed1feab06c3451447dff420c3b1f4e7eb4486 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/bcm283x.h @@ -0,0 +1,641 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-15 RT-Thread the first version + * 2019-07-29 zdzn add macro definition + */ + +#ifndef __BCM283X_H__ +#define __BCM283X_H__ + +#include +#include + +#define PER_BASE (0x3F000000) +#define PER_BASE_40000000 (0x40000000) + + +#define HIGH 0x1 +#define LOW 0x0 + +#define BCM283X_CORE_CLK_HZ 250000000 /* 50 MHz */ + +/*! Offsets for the bases of various peripherals within the peripherals block + * Base Address of the System Timer registers + */ +/*! Base Address of the Pads registers */ +#define BCM283X_GPIO_PADS 0x100000 +/*! Base Address of the Clock/timer registers */ +#define BCM283X_CLOCK_BASE 0x101000 +/*! Base Address of the GPIO registers */ +//#define BCM283X_GPIO_BASE 0x200000 +/*! Base Address of the SPI0 registers */ +#define BCM283X_SPI0_BASE 0x204000 +/*! Base Address of the PWM registers */ +#define BCM283X_GPIO_PWM 0x20C000 +/*! Base Address of the AUX registers */ +#define BCM283X_AUX_BASE 0x215000 +/*! Base Address of the AUX_SPI1 registers */ +#define BCM283X_SPI1_BASE 0x215080 +/*! Base Address of the AUX_SPI2 registers */ +#define BCM283X_SPI2_BASE 0x2150C0 + +/*! Base Address of the BSC0 registers */ +#define BCM283X_BSC0_BASE 0x205000 //for i2c0 +/*! Base Address of the BSC1 registers */ +#define BCM283X_BSC1_BASE 0x804000 //for i2c1 +/*! Base Address of the BSC1 registers */ +#define BCM283X_BSC2_BASE 0x805000 //for hdmi i2c not use + +/* + * GPIO + */ +#define GPIO_BASE (PER_BASE + 0x200000) +#define GPIO_GPFSEL0 HWREG32(GPIO_BASE + 0x0000) /* GPIO Function Select 0 32bit R/W */ +#define GPIO_GPFSEL1 HWREG32(GPIO_BASE + 0x0004) /* GPIO Function Select 1 32bit R/W */ +#define GPIO_GPFSEL2 HWREG32(GPIO_BASE + 0x0008) /* GPIO Function Select 2 32bit R/W */ +#define GPIO_GPFSEL4 HWREG32(GPIO_BASE + 0x0010) /* GPIO Function Select 4 32bit R/W */ +#define GPIO_GPFSEL5 HWREG32(GPIO_BASE + 0x0014) /* GPIO Function Select 5 32bit R/W */ +#define GPIO_GPSET0 HWREG32(GPIO_BASE + 0x001C) +#define GPIO_GPSET1 HWREG32(GPIO_BASE + 0x0020) +#define GPIO_GPCLR0 HWREG32(GPIO_BASE + 0x0028) +#define GPIO_GPCLR1 HWREG32(GPIO_BASE + 0x002C) +#define GPIO_GPEDS0 HWREG32(GPIO_BASE + 0x0040) /* GPIO Pin Event Detect Status */ +#define GPIO_GPEDS1 HWREG32(GPIO_BASE + 0x0044) +#define GPIO_GPREN0 HWREG32(GPIO_BASE + 0x004c) /* GPIO Pin Rising Edge Detect Enable */ +#define GPIO_GPREN1 HWREG32(GPIO_BASE + 0x0050) +#define GPIO_GPFEN0 HWREG32(GPIO_BASE + 0x0058) /* GPIO Pin Falling Edge Detect Enable */ +#define GPIO_GPFEN1 HWREG32(GPIO_BASE + 0x005C) +#define GPIO_GPHEN0 HWREG32(GPIO_BASE + 0x0064) /* GPIO Pin High Detect Enable */ +#define GPIO_GPHEN1 HWREG32(GPIO_BASE + 0x0068) +#define GPIO_GPLEN0 HWREG32(GPIO_BASE + 0x0070) /* GPIO Pin Low Detect Enable 0 */ +#define GPIO_GPLEN1 HWREG32(GPIO_BASE + 0x0074) +#define GPIO_GPAREN0 HWREG32(GPIO_BASE + 0x007C) /* GPIO Pin Async. Rising Edge Detect */ +#define GPIO_GPAREN1 HWREG32(GPIO_BASE + 0x0080) +#define GPIO_GPAFEN0 HWREG32(GPIO_BASE + 0x0088) /* GPIO Pin Async. Falling Edge Detect */ +#define GPIO_GPAFEN1 HWREG32(GPIO_BASE + 0x008C) +#define GPIO_GPPUD HWREG32(GPIO_BASE + 0x0094) /* GPIO Pin Pull-up/down Enable */ +#define GPIO_GPPUDCLK0 HWREG32(GPIO_BASE + 0x0098) /* GPIO Pin Pull-up/down Enable Clock 0 */ +#define GPIO_GPPUDCLK1 HWREG32(GPIO_BASE + 0x009C) /* GPIO Pin Pull-up/down Enable Clock 1 */ + +#define BCM283X_GPIO_BASE (PER_BASE + 0x200000) +#define BCM283X_GPIO_GPFSEL0 (0x0000) /* GPIO Function Select 0 32bit R/W */ +#define BCM283X_GPIO_GPFSEL1 (0x0004) /* GPIO Function Select 1 32bit R/W */ +#define BCM283X_GPIO_GPFSEL2 (0x0008) /* GPIO Function Select 2 32bit R/W */ +#define BCM283X_GPIO_GPFSEL4 (0x0010) /* GPIO Function Select 4 32bit R/W */ +#define BCM283X_GPIO_GPFSEL5 (0x0014) /* GPIO Function Select 5 32bit R/W */ +#define BCM283X_GPIO_GPSET0 (0x001C) +#define BCM283X_GPIO_GPSET1 (0x0020) +#define BCM283X_GPIO_GPCLR0 (0x0028) +#define BCM283X_GPIO_GPCLR1 (0x002C) +#define BCM2835_GPIO_GPLEV0 (0x0034) /*!< GPIO Pin Level 0 */ +#define BCM2835_GPIO_GPLEV1 (0x0038) /*!< GPIO Pin Level 1 */ +#define BCM283X_GPIO_GPEDS0 (0x0040) /* GPIO Pin Event Detect Status */ +#define BCM283X_GPIO_GPEDS1 (0x0044) +#define BCM283X_GPIO_GPREN0 (0x004c) /* GPIO Pin Rising Edge Detect Enable */ +#define BCM283X_GPIO_GPREN1 (0x0050) +#define BCM283X_GPIO_GPFEN0 (0x0058) /* GPIO Pin Falling Edge Detect Enable */ +#define BCM283X_GPIO_GPFEN1 (0x005C) +#define BCM283X_GPIO_GPHEN0 (0x0064) /* GPIO Pin High Detect Enable */ +#define BCM283X_GPIO_GPHEN1 (0x0068) +#define BCM283X_GPIO_GPLEN0 (0x0070) /* GPIO Pin Low Detect Enable 0 */ +#define BCM283X_GPIO_GPLEN1 (0x0074) +#define BCM283X_GPIO_GPAREN0 (0x007C) /* GPIO Pin Async. Rising Edge Detect */ +#define BCM283X_GPIO_GPAREN1 (0x0080) +#define BCM283X_GPIO_GPAFEN0 (0x0088) /* GPIO Pin Async. Falling Edge Detect */ +#define BCM283X_GPIO_GPAFEN1 (0x008C) +#define BCM283X_GPIO_GPPUD (0x0094) /* GPIO Pin Pull-up/down Enable */ +#define BCM283X_GPIO_GPPUDCLK0 (0x0098) /* GPIO Pin Pull-up/down Enable Clock 0 */ +#define BCM283X_GPIO_GPPUDCLK1 (0x009C) /* GPIO Pin Pull-up/down Enable Clock 1 */ + +enum gpio_function_select +{ + BCM283X_GPIO_FSEL_INPT = 0x00, /*!< Input 0b000 */ + BCM283X_GPIO_FSEL_OUTP = 0x01, /*!< Output 0b001 */ + BCM283X_GPIO_FSEL_ALT0 = 0x04, /*!< Alternate function 0 0b100 */ + BCM283X_GPIO_FSEL_ALT1 = 0x05, /*!< Alternate function 1 0b101 */ + BCM283X_GPIO_FSEL_ALT2 = 0x06, /*!< Alternate function 2 0b110, */ + BCM283X_GPIO_FSEL_ALT3 = 0x07, /*!< Alternate function 3 0b111 */ + BCM283X_GPIO_FSEL_ALT4 = 0x03, /*!< Alternate function 4 0b011 */ + BCM283X_GPIO_FSEL_ALT5 = 0x02, /*!< Alternate function 5 0b010 */ + BCM283X_GPIO_FSEL_MASK = 0x07 /*!< Function select bits mask 0b111 */ +}; + +enum gpio_pud_mode +{ + BCM283X_GPIO_PUD_OFF = 0x00, /*!< Off ? disable pull-up/down 0b00 */ + BCM283X_GPIO_PUD_DOWN = 0x01, /*!< Enable Pull Down control 0b01 */ + BCM283X_GPIO_PUD_UP = 0x02 /*!< Enable Pull Up control 0b10 */ +}; + +/* Defines for BSC I2C + * GPIO register offsets from BCM283X_BSC*_BASE. + * Offsets into the BSC Peripheral block in bytes per 3.1 BSC Register Map + */ +/* I2C Address Map offset address */ +#define BCM283X_BSC_C 0x0000 /*!< BSC Master Control */ +#define BCM283X_BSC_S 0x0004 /*!< BSC Master Status */ +#define BCM283X_BSC_DLEN 0x0008 /*!< BSC Master Data Length */ +#define BCM283X_BSC_A 0x000c /*!< BSC Master Slave Address */ +#define BCM283X_BSC_FIFO 0x0010 /*!< BSC Master Data FIFO */ +#define BCM283X_BSC_DIV 0x0014 /*!< BSC Master Clock Divider */ +#define BCM283X_BSC_DEL 0x0018 /*!< BSC Master Data Delay */ +#define BCM283X_BSC_CLKT 0x001c /*!< BSC Master Clock Stretch Timeout */ + +/* Register masks for C Register */ +#define BCM283X_BSC_C_I2CEN 0x00008000 /*!< I2C Enable, 0 = disabled, 1 = enabled */ +#define BCM283X_BSC_C_INTR 0x00000400 /*!< Interrupt on RX */ +#define BCM283X_BSC_C_INTT 0x00000200 /*!< Interrupt on TX */ +#define BCM283X_BSC_C_INTD 0x00000100 /*!< Interrupt on DONE */ +#define BCM283X_BSC_C_ST 0x00000080 /*!< Start transfer, 1 = Start a new transfer */ +#define BCM283X_BSC_C_CLEAR_1 0x00000020 /*!< Clear FIFO Clear */ +#define BCM283X_BSC_C_CLEAR_2 0x00000010 /*!< Clear FIFO Clear */ +#define BCM283X_BSC_C_READ 0x00000001 /*!< Read transfer */ + +/* Register masks for S Register */ +#define BCM283X_BSC_S_CLKT 0x00000200 /*!< Clock stretch timeout */ +#define BCM283X_BSC_S_ERR 0x00000100 /*!< ACK error */ +#define BCM283X_BSC_S_RXF 0x00000080 /*!< RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full */ +#define BCM283X_BSC_S_TXE 0x00000040 /*!< TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full */ +#define BCM283X_BSC_S_RXD 0x00000020 /*!< RXD FIFO contains data */ +#define BCM283X_BSC_S_TXD 0x00000010 /*!< TXD FIFO can accept data */ +#define BCM283X_BSC_S_RXR 0x00000008 /*!< RXR FIFO needs reading (full) */ +#define BCM283X_BSC_S_TXW 0x00000004 /*!< TXW FIFO needs writing (full) */ +#define BCM283X_BSC_S_DONE 0x00000002 /*!< Transfer DONE */ +#define BCM283X_BSC_S_TA 0x00000001 /*!< Transfer Active */ + +#define BCM283X_BSC_FIFO_SIZE 16 /*!< BSC FIFO size */ + +enum i2c_clock_divider +{ + BCM283X_I2C_CLOCK_DIVIDER_2500 = 2500, /*!< 2500 = 10us = 100 kHz */ + BCM283X_I2C_CLOCK_DIVIDER_626 = 626, /*!< 622 = 2.504us = 399.3610 kHz */ + BCM283X_I2C_CLOCK_DIVIDER_150 = 150, /*!< 150 = 60ns = 1.666 MHz (default at reset) */ + BCM283X_I2C_CLOCK_DIVIDER_148 = 148 /*!< 148 = 59ns = 1.689 MHz */ +}; + +enum i2c_reason_codes +{ + BCM283X_I2C_REASON_OK = 0x00, /*!< Success */ + BCM283X_I2C_REASON_ERROR_NACK = 0x01, /*!< Received a NACK */ + BCM283X_I2C_REASON_ERROR_CLKT = 0x02, /*!< Received Clock Stretch Timeout */ + BCM283X_I2C_REASON_ERROR_DATA = 0x04 /*!< Not all data is sent / received */ +}; + +/* + * Interrupt Controler + */ +#define IRQ_BASE (PER_BASE + 0xB200) +#define IRQ_PEND_BASIC HWREG32(IRQ_BASE + 0x00) +#define IRQ_PEND1 HWREG32(IRQ_BASE + 0x04) +#define IRQ_PEND2 HWREG32(IRQ_BASE + 0x08) +#define IRQ_FIQ_CONTROL HWREG32(IRQ_BASE + 0x0C) +#define IRQ_ENABLE1 HWREG32(IRQ_BASE + 0x10) +#define IRQ_ENABLE2 HWREG32(IRQ_BASE + 0x14) +#define IRQ_ENABLE_BASIC HWREG32(IRQ_BASE + 0x18) +#define IRQ_DISABLE1 HWREG32(IRQ_BASE + 0x1C) +#define IRQ_DISABLE2 HWREG32(IRQ_BASE + 0x20) +#define IRQ_DISABLE_BASIC HWREG32(IRQ_BASE + 0x24) + +/* + * System Timer + */ +#define STIMER_BASE (PER_BASE + 0x3000) +#define STIMER_CS HWREG32(STIMER_BASE + 0x00) +#define STIMER_CLO HWREG32(STIMER_BASE + 0x04) +#define STIMER_CHI HWREG32(STIMER_BASE + 0x08) +#define STIMER_C0 HWREG32(STIMER_BASE + 0x0C) +#define STIMER_C1 HWREG32(STIMER_BASE + 0x10) +#define STIMER_C2 HWREG32(STIMER_BASE + 0x14) +#define STIMER_C3 HWREG32(STIMER_BASE + 0x18) + +/* Defines for ST */ +#define BCM283X_ST_BASE (PER_BASE + 0x3000) +#define BCM283X_ST_CS 0x0000 /*!< System Timer Control/Status */ +#define BCM283X_ST_CLO 0x0004 /*!< System Timer Counter Lower 32 bits */ +#define BCM283X_ST_CHI 0x0008 /*!< System Timer Counter Upper 32 bits */ +#define BCM283X_ST_C0 0x000C +#define BCM283X_ST_C1 0x0010 +#define BCM283X_ST_C2 0x0014 +#define BCM283X_ST_C3 0x0018 + +/* + * ARM Timer + */ +#define ARM_TIMER_BASE (PER_BASE + 0xB000) +#define ARM_TIMER_LOAD HWREG32(ARM_TIMER_BASE + 0x400) +#define ARM_TIMER_VALUE HWREG32(ARM_TIMER_BASE + 0x404) +#define ARM_TIMER_CTRL HWREG32(ARM_TIMER_BASE + 0x408) +#define ARM_TIMER_IRQCLR HWREG32(ARM_TIMER_BASE + 0x40C) +#define ARM_TIMER_RAWIRQ HWREG32(ARM_TIMER_BASE + 0x410) +#define ARM_TIMER_MASKIRQ HWREG32(ARM_TIMER_BASE + 0x414) +#define ARM_TIMER_RELOAD HWREG32(ARM_TIMER_BASE + 0x418) +#define ARM_TIMER_PREDIV HWREG32(ARM_TIMER_BASE + 0x41C) +#define ARM_TIMER_CNTR HWREG32(ARM_TIMER_BASE + 0x420) + +/* + * Core Timer + */ +#define CTIMER_CTL HWREG32(PER_BASE_40000000 + 0x00) /* Control register */ +#define CTIMER_PRE HWREG32(PER_BASE_40000000 + 0x08) /* Core timer prescaler */ +#define CTIMER_LS32B HWREG32(PER_BASE_40000000 + 0x1C) /* Core timer access LS 32 bits */ +#define CTIMER_MS32B HWREG32(PER_BASE_40000000 + 0x20) /* Core timer access MS 32 bits */ + +/* + * ARM Core Timer + */ +#define C0TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x40) /* Core0 timers Interrupt control */ +#define C1TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x44) /* Core1 timers Interrupt control */ +#define C2TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x48) /* Core2 timers Interrupt control */ +#define C3TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x4C) /* Core3 timers Interrupt control */ +#define CORETIMER_INTCTL(n) HWREG32(PER_BASE_40000000 + 0x40 + n*4) /* Core3 timers Interrupt control */ +/* + * ARM Core Mailbox interrupt + */ +#define C0MB_INTCTL HWREG32(PER_BASE_40000000 + 0x50) /* Core0 Mailboxes Interrupt control */ +#define C1MB_INTCTL HWREG32(PER_BASE_40000000 + 0x54) /* Core1 Mailboxes Interrupt control */ +#define C2MB_INTCTL HWREG32(PER_BASE_40000000 + 0x58) /* Core2 Mailboxes Interrupt control */ +#define C3MB_INTCTL HWREG32(PER_BASE_40000000 + 0x5C) /* Core3 Mailboxes Interrupt control */ +#define COREMB_INTCTL(n) HWREG32(PER_BASE_40000000 + 0x50 + 4*n) /* Core3 Mailboxes Interrupt control */ +/* + * ARM Core IRQ/FIQ status + */ +#define C0_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x60) /* Core0 IRQ Source */ +#define C1_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x64) /* Core1 IRQ Source */ +#define C2_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x68) /* Core2 IRQ Source */ +#define C3_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x6C) /* Core3 IRQ Source */ +#define C0_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x70) /* Core0 FIQ Source */ +#define C1_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x74) /* Core1 FIQ Source */ +#define C2_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x78) /* Core2 FIQ Source */ +#define C3_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x7C) /* Core3 FIQ Source */ +#define CORE_IRQSOURCE(n) HWREG32(PER_BASE_40000000 + 0x60+ n*0x4) +#define CORE_FIQSOURCE(n) HWREG32(PER_BASE_40000000 + 0x70+ n*0x4) + +#define CORE_MAILBOX3_SET(n) HWREG32(PER_BASE_40000000 + 0x8C + n*0x10) +#define CORE_MAILBOX3_CLEAR(n) HWREG32(PER_BASE_40000000 + 0xCC + n*0x10) +#define CORE_MAILBOX2_SET(n) HWREG32(PER_BASE_40000000 + 0x88 + n*0x10) +#define CORE_MAILBOX2_CLEAR(n) HWREG32(PER_BASE_40000000 + 0xC8 + n*0x10) +#define CORE_MAILBOX1_SET(n) HWREG32(PER_BASE_40000000 + 0x84 + n*0x10) +#define CORE_MAILBOX1_CLEAR(n) HWREG32(PER_BASE_40000000 + 0xC4 + n*0x10) +#define CORE_MAILBOX0_SET(n) HWREG32(PER_BASE_40000000 + 0x80 + n*0x10) +#define CORE_MAILBOX0_CLEAR(n) HWREG32(PER_BASE_40000000 + 0xC0 + n*0x10) + +/* for smp ipi using mailbox0 */ +#define IPI_MAILBOX_SET CORE_MAILBOX0_SET + +#define IPI_MAILBOX_CLEAR CORE_MAILBOX0_CLEAR +#define IPI_MAILBOX_INT_MASK (0x01) + +#define IRQ_ARM_TIMER 64 +#define IRQ_ARM_MAILBOX 65 +#define IRQ_ARM_DB0 66 +#define IRQ_ARM_DB1 67 +#define IRQ_ARM_GPU0_HALT 68 +#define IRQ_ARM_GPU1_HALT 69 +#define IRQ_ARM_ILLEGAL_ACC1 70 +#define IRQ_ARM_ILLEGAL_ACC0 71 + +#define IRQ_SYSTIMER_MATCH_1 1 +#define IRQ_SYSTIMER_MATCH_3 3 + +#define IRQ_AUX 29 +#define IRQ_IIC_SPI_SLV 43 +#define IRQ_PWA0 45 +#define IRQ_PWA1 46 +#define IRQ_SMI 48 +#define IRQ_GPIO0 49 +#define IRQ_GPIO1 50 +#define IRQ_GPIO2 51 +#define IRQ_GPIO3 52 +#define IRQ_IIC 53 +#define IRQ_SPI 54 +#define IRQ_PCM 55 +#define IRQ_UART 57 + +/* CLOCK */ +#define BCM283X_PLLA 0 +#define BCM283X_PLLB 1 +#define BCM283X_PLLC 2 +#define BCM283X_PLLD 3 +#define BCM283X_PLLH 4 + +#define BCM283X_PLLA_CORE 5 +#define BCM283X_PLLA_PER 6 +#define BCM283X_PLLB_ARM 7 +#define BCM283X_PLLC_CORE0 8 +#define BCM283X_PLLC_CORE1 9 +#define BCM283X_PLLC_CORE2 10 +#define BCM283X_PLLC_PER 11 +#define BCM283X_PLLD_CORE 12 +#define BCM283X_PLLD_PER 13 +#define BCM283X_PLLH_RCAL 14 +#define BCM283X_PLLH_AUX 15 +#define BCM283X_PLLH_PIX 16 + +#define BCM283X_CLOCK_TIMER 17 +#define BCM283X_CLOCK_OTP 18 +#define BCM283X_CLOCK_UART 19 +#define BCM283X_CLOCK_VPU 20 +#define BCM283X_CLOCK_V3D 21 +#define BCM283X_CLOCK_ISP 22 +#define BCM283X_CLOCK_H264 23 +#define BCM283X_CLOCK_VEC 24 +#define BCM283X_CLOCK_HSM 25 +#define BCM283X_CLOCK_SDRAM 26 +#define BCM283X_CLOCK_TSENS 27 +#define BCM283X_CLOCK_EMMC 28 +#define BCM283X_CLOCK_PERI_IMAGE 29 +#define BCM283X_CLOCK_COUNT 30 + +#define CM_PASSWORD 0x5a000000 + +#define CM_GNRICCTL 0x000 +#define CM_GNRICDIV 0x004 +#define CM_VPUCTL 0x008 +#define CM_VPUDIV 0x00c +#define CM_SYSCTL 0x010 +#define CM_SYSDIV 0x014 +#define CM_PERIACTL 0x018 +#define CM_PERIADIV 0x01c +#define CM_PERIICTL 0x020 +#define CM_PERIIDIV 0x024 +#define CM_H264CTL 0x028 +#define CM_H264DIV 0x02c +#define CM_ISPCTL 0x030 +#define CM_ISPDIV 0x034 +#define CM_V3DCTL 0x038 +#define CM_V3DDIV 0x03c +#define CM_CAM0CTL 0x040 +#define CM_CAM0DIV 0x044 +#define CM_CAM1CTL 0x048 +#define CM_CAM1DIV 0x04c +#define CM_CCP2CTL 0x050 +#define CM_CCP2DIV 0x054 +#define CM_DSI0ECTL 0x058 +#define CM_DSI0EDIV 0x05c +#define CM_DSI0PCTL 0x060 +#define CM_DSI0PDIV 0x064 +#define CM_DPICTL 0x068 +#define CM_DPIDIV 0x06c +#define CM_GP0CTL 0x070 +#define CM_GP0DIV 0x074 +#define CM_GP1CTL 0x078 +#define CM_GP1DIV 0x07c +#define CM_GP2CTL 0x080 +#define CM_GP2DIV 0x084 +#define CM_HSMCTL 0x088 +#define CM_HSMDIV 0x08c +#define CM_OTPCTL 0x090 +#define CM_OTPDIV 0x094 +#define CM_PWMCTL 0x0a0 +#define CM_PWMDIV 0x0a4 +#define CM_SMICTL 0x0b0 +#define CM_SMIDIV 0x0b4 +#define CM_TSENSCTL 0x0e0 +#define CM_TSENSDIV 0x0e4 +#define CM_TIMERCTL 0x0e8 +#define CM_TIMERDIV 0x0ec +#define CM_UARTCTL 0x0f0 +#define CM_UARTDIV 0x0f4 +#define CM_VECCTL 0x0f8 +#define CM_VECDIV 0x0fc +#define CM_PULSECTL 0x190 +#define CM_PULSEDIV 0x194 +#define CM_SDCCTL 0x1a8 +#define CM_SDCDIV 0x1ac +#define CM_ARMCTL 0x1b0 +#define CM_EMMCCTL 0x1c0 +#define CM_EMMCDIV 0x1c4 + +#define BCM283X_AUX_IRQ 0x0000 /*!< xxx */ +#define BCM283X_AUX_ENABLE 0x0004 /*!< */ +#define BCM283X_AUX_ENABLE_UART1 0x01 /*!< */ +#define BCM283X_AUX_ENABLE_SPI0 0x02 /*!< SPI0 (SPI1 in the device) */ +#define BCM283X_AUX_ENABLE_SPI1 0x04 /*!< SPI1 (SPI2 in the device) */ +#define BCM283X_AUX_SPI_CNTL0 0x0000 /*!< */ +#define BCM283X_AUX_SPI_CNTL1 0x0004 /*!< */ +#define BCM283X_AUX_SPI_STAT 0x0008 /*!< */ +#define BCM283X_AUX_SPI_PEEK 0x000C /*!< Read but do not take from FF */ +#define BCM283X_AUX_SPI_IO 0x0020 /*!< Write = TX, read=RX */ +#define BCM283X_AUX_SPI_TXHOLD 0x0030 /*!< Write = TX keep CS, read=RX */ +#define BCM283X_AUX_SPI_CLOCK_MIN 30500 /*!< 30,5kHz */ +#define BCM283X_AUX_SPI_CLOCK_MAX 125000000 /*!< 125Mhz */ +#define BCM283X_AUX_SPI_CNTL0_SPEED 0xFFF00000 /*!< */ +#define BCM283X_AUX_SPI_CNTL0_SPEED_MAX 0xFFF /*!< */ +#define BCM283X_AUX_SPI_CNTL0_SPEED_SHIFT 20 /*!< */ +#define BCM283X_AUX_SPI_CNTL0_CS0_N 0x000C0000 /*!< CS 0 low */ +#define BCM283X_AUX_SPI_CNTL0_CS1_N 0x000A0000 /*!< CS 1 low */ +#define BCM283X_AUX_SPI_CNTL0_CS2_N 0x00060000 /*!< CS 2 low */ +#define BCM283X_AUX_SPI_CNTL0_POSTINPUT 0x00010000 /*!< */ +#define BCM283X_AUX_SPI_CNTL0_VAR_CS 0x00008000 /*!< */ +#define BCM283X_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000 /*!< */ +#define BCM283X_AUX_SPI_CNTL0_DOUTHOLD 0x00003000 /*!< */ +#define BCM283X_AUX_SPI_CNTL0_ENABLE 0x00000800 /*!< */ +#define BCM283X_AUX_SPI_CNTL0_CPHA_IN 0x00000400 /*!< */ +#define BCM283X_AUX_SPI_CNTL0_CLEARFIFO 0x00000200 /*!< */ +#define BCM283X_AUX_SPI_CNTL0_CPHA_OUT 0x00000100 /*!< */ +#define BCM283X_AUX_SPI_CNTL0_CPOL 0x00000080 /*!< */ +#define BCM283X_AUX_SPI_CNTL0_MSBF_OUT 0x00000040 /*!< */ +#define BCM283X_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F /*!< */ +#define BCM283X_AUX_SPI_CNTL1_CSHIGH 0x00000700 /*!< */ +#define BCM283X_AUX_SPI_CNTL1_IDLE 0x00000080 /*!< */ +#define BCM283X_AUX_SPI_CNTL1_TXEMPTY 0x00000040 /*!< */ +#define BCM283X_AUX_SPI_CNTL1_MSBF_IN 0x00000002 /*!< */ +#define BCM283X_AUX_SPI_CNTL1_KEEP_IN 0x00000001 /*!< */ +#define BCM283X_AUX_SPI_STAT_TX_LVL 0xFF000000 /*!< */ +#define BCM283X_AUX_SPI_STAT_RX_LVL 0x00FF0000 /*!< */ +#define BCM283X_AUX_SPI_STAT_TX_FULL 0x00000400 /*!< */ +#define BCM283X_AUX_SPI_STAT_TX_EMPTY 0x00000200 /*!< */ +#define BCM283X_AUX_SPI_STAT_RX_FULL 0x00000100 /*!< */ +#define BCM283X_AUX_SPI_STAT_RX_EMPTY 0x00000080 /*!< */ +#define BCM283X_AUX_SPI_STAT_BUSY 0x00000040 /*!< */ +#define BCM283X_AUX_SPI_STAT_BITCOUNT 0x0000003F /*!< */ + +/* Defines for SPI */ +#define BCM283X_SPI0_CS 0x0000 /*!< SPI Master Control and Status */ +#define BCM283X_SPI0_FIFO 0x0004 /*!< SPI Master TX and RX FIFOs */ +#define BCM283X_SPI0_CLK 0x0008 /*!< SPI Master Clock Divider */ +#define BCM283X_SPI0_DLEN 0x000c /*!< SPI Master Data Length */ +#define BCM283X_SPI0_LTOH 0x0010 /*!< SPI LOSSI mode TOH */ +#define BCM283X_SPI0_DC 0x0014 /*!< SPI DMA DREQ Controls */ + +/* Register masks for SPI0_CS */ +#define BCM283X_SPI0_CS_LEN_LONG 0x02000000 /*!< Enable Long data word in Lossi mode if DMA_LEN is set */ +#define BCM283X_SPI0_CS_DMA_LEN 0x01000000 /*!< Enable DMA mode in Lossi mode */ +#define BCM283X_SPI0_CS_CSPOL2 0x00800000 /*!< Chip Select 2 Polarity */ +#define BCM283X_SPI0_CS_CSPOL1 0x00400000 /*!< Chip Select 1 Polarity */ +#define BCM283X_SPI0_CS_CSPOL0 0x00200000 /*!< Chip Select 0 Polarity */ +#define BCM283X_SPI0_CS_RXF 0x00100000 /*!< RXF - RX FIFO Full */ +#define BCM283X_SPI0_CS_RXR 0x00080000 /*!< RXR RX FIFO needs Reading (full) */ +#define BCM283X_SPI0_CS_TXD 0x00040000 /*!< TXD TX FIFO can accept Data */ +#define BCM283X_SPI0_CS_RXD 0x00020000 /*!< RXD RX FIFO contains Data */ +#define BCM283X_SPI0_CS_DONE 0x00010000 /*!< Done transfer Done */ +#define BCM283X_SPI0_CS_TE_EN 0x00008000 /*!< Unused */ +#define BCM283X_SPI0_CS_LMONO 0x00004000 /*!< Unused */ +#define BCM283X_SPI0_CS_LEN 0x00002000 /*!< LEN LoSSI enable */ +#define BCM283X_SPI0_CS_REN 0x00001000 /*!< REN Read Enable */ +#define BCM283X_SPI0_CS_ADCS 0x00000800 /*!< ADCS Automatically Deassert Chip Select */ +#define BCM283X_SPI0_CS_INTR 0x00000400 /*!< INTR Interrupt on RXR */ +#define BCM283X_SPI0_CS_INTD 0x00000200 /*!< INTD Interrupt on Done */ +#define BCM283X_SPI0_CS_DMAEN 0x00000100 /*!< DMAEN DMA Enable */ +#define BCM283X_SPI0_CS_TA 0x00000080 /*!< Transfer Active */ +#define BCM283X_SPI0_CS_CSPOL 0x00000040 /*!< Chip Select Polarity */ +#define BCM283X_SPI0_CS_CLEAR 0x00000030 /*!< Clear FIFO Clear RX and TX */ +#define BCM283X_SPI0_CS_CLEAR_RX 0x00000020 /*!< Clear FIFO Clear RX */ +#define BCM283X_SPI0_CS_CLEAR_TX 0x00000010 /*!< Clear FIFO Clear TX */ +#define BCM283X_SPI0_CS_CPOL 0x00000008 /*!< Clock Polarity */ +#define BCM283X_SPI0_CS_CPHA 0x00000004 /*!< Clock Phase */ +#define BCM283X_SPI0_CS_CS 0x00000003 /*!< Chip Select */ + +enum spi_bit_order +{ + BCM283X_SPI_BIT_ORDER_LSBFIRST = 0, /*!< LSB First */ + BCM283X_SPI_BIT_ORDER_MSBFIRST = 1 /*!< MSB First */ +}; + +enum spi_mode +{ + BCM283X_SPI_MODE0 = 0, /*!< CPOL = 0, CPHA = 0 */ + BCM283X_SPI_MODE1 = 1, /*!< CPOL = 0, CPHA = 1 */ + BCM283X_SPI_MODE2 = 2, /*!< CPOL = 1, CPHA = 0 */ + BCM283X_SPI_MODE3 = 3 /*!< CPOL = 1, CPHA = 1 */ +}; + +enum spi_chip_select +{ + BCM283X_SPI_CS0 = 0, /*!< Chip Select 0 */ + BCM283X_SPI_CS1 = 1, /*!< Chip Select 1 */ + BCM283X_SPI_CS2 = 2, /*!< Chip Select 2 (ie pins CS1 and CS2 are asserted) */ + BCM283X_SPI_CS_NONE = 3 /*!< No CS, control it yourself */ +}; + +enum spi_clock_divider +{ + BCM283X_SPI_CLOCK_DIVIDER_65536 = 0, /*!< 65536 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_32768 = 32768, /*!< 32768 = 7.629394531kHz on Rpi2, 12.20703125kHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_16384 = 16384, /*!< 16384 = 15.25878906kHz on Rpi2, 24.4140625kHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_8192 = 8192, /*!< 8192 = 30.51757813kHz on Rpi2, 48.828125kHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_4096 = 4096, /*!< 4096 = 61.03515625kHz on Rpi2, 97.65625kHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_2048 = 2048, /*!< 2048 = 122.0703125kHz on Rpi2, 195.3125kHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_1024 = 1024, /*!< 1024 = 244.140625kHz on Rpi2, 390.625kHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_512 = 512, /*!< 512 = 488.28125kHz on Rpi2, 781.25kHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_256 = 256, /*!< 256 = 976.5625kHz on Rpi2, 1.5625MHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_128 = 128, /*!< 128 = 1.953125MHz on Rpi2, 3.125MHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_64 = 64, /*!< 64 = 3.90625MHz on Rpi2, 6.250MHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_32 = 32, /*!< 32 = 7.8125MHz on Rpi2, 12.5MHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_16 = 16, /*!< 16 = 15.625MHz on Rpi2, 25MHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_8 = 8, /*!< 8 = 31.25MHz on Rpi2, 50MHz on RPI3 */ + BCM283X_SPI_CLOCK_DIVIDER_4 = 4, /*!< 4 = 62.5MHz on Rpi2, 100MHz on RPI3. Dont expect this speed to work reliably. */ + BCM283X_SPI_CLOCK_DIVIDER_2 = 2, /*!< 2 = 125MHz on Rpi2, 200MHz on RPI3, fastest you can get. Dont expect this speed to work reliably.*/ + BCM283X_SPI_CLOCK_DIVIDER_1 = 1 /*!< 1 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3, same as 0/65536 */ +}; + +/* BCM IO pin */ +enum bcm_gpio_pin +{ + BCM_GPIO_PIN_0 = 0, + BCM_GPIO_PIN_1, + BCM_GPIO_PIN_2, + BCM_GPIO_PIN_3, + BCM_GPIO_PIN_4, + BCM_GPIO_PIN_5, + BCM_GPIO_PIN_6, + BCM_GPIO_PIN_7, + BCM_GPIO_PIN_8, + BCM_GPIO_PIN_9, + BCM_GPIO_PIN_10, + BCM_GPIO_PIN_11, + BCM_GPIO_PIN_12, + BCM_GPIO_PIN_13, + BCM_GPIO_PIN_14, + BCM_GPIO_PIN_15, + BCM_GPIO_PIN_16, + BCM_GPIO_PIN_17, + BCM_GPIO_PIN_18, + BCM_GPIO_PIN_19, + BCM_GPIO_PIN_20, + BCM_GPIO_PIN_21, + BCM_GPIO_PIN_22, + BCM_GPIO_PIN_23, + BCM_GPIO_PIN_24, + BCM_GPIO_PIN_25, + BCM_GPIO_PIN_26, + BCM_GPIO_PIN_27, + BCM_GPIO_PIN_28, + BCM_GPIO_PIN_29, + BCM_GPIO_PIN_30, + BCM_GPIO_PIN_31, + BCM_GPIO_PIN_32, + BCM_GPIO_PIN_33, + BCM_GPIO_PIN_34, + BCM_GPIO_PIN_35, + BCM_GPIO_PIN_36, + BCM_GPIO_PIN_37, + BCM_GPIO_PIN_38, + BCM_GPIO_PIN_39, + BCM_GPIO_PIN_40, + BCM_GPIO_PIN_41, + BCM_GPIO_PIN_42, + BCM_GPIO_PIN_43, + BCM_GPIO_PIN_44, + BCM_GPIO_PIN_45, + BCM_GPIO_PIN_46, + BCM_GPIO_PIN_47, + BCM_GPIO_PIN_48, + BCM_GPIO_PIN_49, + BCM_GPIO_PIN_50, + BCM_GPIO_PIN_51, + BCM_GPIO_PIN_52, + BCM_GPIO_PIN_53, + BCM_GPIO_PIN_NUM, +}; + +rt_uint32_t bcm283x_peri_read(volatile rt_ubase_t addr); +rt_uint32_t bcm283x_peri_read_nb(volatile rt_ubase_t addr); +void bcm283x_peri_write(volatile rt_ubase_t addr, rt_uint32_t value); +void bcm283x_peri_write_nb(volatile rt_ubase_t addr, rt_uint32_t value); +void bcm283x_peri_set_bits(volatile rt_ubase_t addr, rt_uint32_t value, rt_uint32_t mask); + +void bcm283x_gpio_fsel(rt_uint8_t pin, rt_uint8_t mode); +void bcm283x_gpio_set(rt_uint8_t pin); +void bcm283x_gpio_clr(rt_uint8_t pin); + +rt_uint8_t bcm283x_gpio_lev(rt_uint8_t pin); +rt_uint8_t bcm283x_gpio_eds(rt_uint8_t pin); +void bcm283x_gpio_set_eds(rt_uint8_t pin); +void bcm283x_gpio_ren(rt_uint8_t pin); +void bcm283x_gpio_clr_ren(rt_uint8_t pin); +void bcm283x_gpio_fen(rt_uint8_t pin); +void bcm283x_gpio_clr_fen(rt_uint8_t pin); +void bcm283x_gpio_hen(rt_uint8_t pin); +void bcm283x_gpio_clr_hen(rt_uint8_t pin); +void bcm283x_gpio_len(rt_uint8_t pin); +void bcm283x_gpio_clr_len(rt_uint8_t pin); +void bcm283x_gpio_aren(rt_uint8_t pin); +void bcm283x_gpio_clr_aren(rt_uint8_t pin); +void bcm283x_gpio_afen(rt_uint8_t pin); +void bcm283x_gpio_clr_afen(rt_uint8_t pin); +void bcm283x_gpio_pud(rt_uint8_t pud); +void bcm283x_gpio_pudclk(rt_uint8_t pin, rt_uint8_t on); +void bcm283x_gpio_set_pud(rt_uint8_t pin, rt_uint8_t pud); +void bcm283x_gpio_write(rt_uint8_t pin, rt_uint8_t val); +void bcm283x_st_delay(rt_uint64_t offset_micros, rt_uint64_t micros); +rt_uint64_t bcm283x_st_read(void); +void bcm283x_delayMicroseconds(rt_uint64_t micros); +void bcm283x_clo_delayMicros(rt_uint32_t micros); + +int bcm283x_i2c_begin(int no); +void bcm283x_i2c_end(int no); +void bcm283x_i2c_setSlaveAddress(int no, rt_uint8_t saddr); +void bcm283x_i2c_setClockDivider(int no, rt_uint16_t divider); +void bcm283x_i2c_set_baudrate(int no, rt_uint32_t baudrate); +rt_uint8_t bcm283x_i2c_read(rt_uint32_t base, rt_uint8_t* buf, rt_uint32_t len); +rt_uint8_t bcm283x_i2c_write(rt_uint32_t base, const rt_uint8_t * buf, rt_uint32_t len); +rt_uint8_t bcm283x_i2c_write_read_rs(char* cmds, rt_uint32_t cmds_len, char* buf, rt_uint32_t buf_len); + +#endif + diff --git a/bsp/raspberry-pi/raspi3-64/driver/board.c b/bsp/raspberry-pi/raspi3-64/driver/board.c new file mode 100644 index 0000000000000000000000000000000000000000..3c218d09a7060a64889164d47de0153cc3aa82c9 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/board.c @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#include +#include + +#include "board.h" +#include "drv_uart.h" +#include "drv_timer.h" + +#include "cp15.h" + +#ifdef RT_USING_SMP +extern void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler); + +void ipi_handler(){ + rt_scheduler_ipi_handler(0,RT_NULL); +} +#endif + +void rt_hw_timer_isr(int vector, void *parameter) +{ + ARM_TIMER_IRQCLR = 0; + rt_tick_increase(); +} + +int rt_hw_timer_init() +{ + __DSB(); + rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_umask(IRQ_ARM_TIMER); + /* timer_clock = apb_clock/(pre_divider + 1) */ + ARM_TIMER_PREDIV = (250 - 1); + + ARM_TIMER_RELOAD = 0; + ARM_TIMER_LOAD = 0; + ARM_TIMER_IRQCLR = 0; + ARM_TIMER_CTRL = 0; + + ARM_TIMER_RELOAD = 10000; + ARM_TIMER_LOAD = 10000; + + /* 23-bit counter, enable interrupt, enable timer */ + ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7); + return 0; +} + +void idle_wfi(void) +{ + asm volatile ("wfi"); +} + +#define MMU_LEVEL_MASK 0x1ffUL +#define MMU_MAP_ERROR_VANOTALIGN -1 +#define MMU_MAP_ERROR_PANOTALIGN -2 +#define MMU_MAP_ERROR_NOPAGE -3 +#define MMU_MAP_ERROR_CONFLICT -4 + +unsigned char main_tbl[4096] __attribute__((aligned (4096))); +unsigned char __page_start[4096*100] __attribute__((aligned (4096))); +unsigned long __page_off = 0; +unsigned long get_free_page(void) { + __page_off += 4096; + return (unsigned long)(__page_start + __page_off - 4096); +} + +#define MEM_ATTR_MEM ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2)) +#define MEM_ATTR_IO ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2)) + +static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) { + int level; + unsigned long* cur_lv_tbl = lv0_tbl; + unsigned long page; + unsigned long off; + int level_shift = 39; + + if (va & (0x200000UL - 1)) { + return MMU_MAP_ERROR_VANOTALIGN; + } + if (pa & (0x200000UL - 1)) { + return MMU_MAP_ERROR_PANOTALIGN; + } + for (level = 0; level < 2; level++) { + off = (va >> level_shift); + off &= MMU_LEVEL_MASK; + if ((cur_lv_tbl[off] & 1) == 0) { + page = get_free_page(); + if (!page) { + return MMU_MAP_ERROR_NOPAGE; + } + rt_memset((void *)page, 0, 4096); + cur_lv_tbl[off] = page | 0x3UL; + } + page = cur_lv_tbl[off]; + if (!(page & 0x2)) { + //is block! error! + return MMU_MAP_ERROR_CONFLICT; + } + cur_lv_tbl = (unsigned long*)(page & 0x0000fffffffff000UL); + level_shift -= 9; + } + attr &= 0xfff0000000000ffcUL; + pa |= (attr | 0x1UL); //block + off = (va >> 21); + off &= MMU_LEVEL_MASK; + cur_lv_tbl[off] = pa; + return 0; +} + +int armv8_map_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, int count, unsigned long attr) +{ + int i; + int ret; + + if (va & (0x200000 - 1)) + { + return -1; + } + if (pa & (0x200000 - 1)) + { + return -1; + } + for (i = 0; i < count; i++) + { + ret = map_single_page_2M(lv0_tbl, va, pa, attr); + va += 0x200000; + pa += 0x200000; + if (ret != 0) + { + return ret; + } + } + return 0; +} + +/** + * Initialize the Hardware related stuffs. Called from rtthread_startup() + * after interrupt disabled. + */ +void rt_hw_board_init(void) +{ + /* mmu set */ + unsigned long val64; + unsigned long val32; //val32不是uint32_t,val32只是表示相关的那个寄存器是32位的 + int ret; + + val64 = 0x007f6eUL; + asm volatile("msr MAIR_EL1, %0\n dsb sy\n"::"r"(val64)); + asm volatile("mrs %0, MAIR_EL1\n dsb sy\n":"=r"(val64)); + + //TCR_EL1 + val32 = (16UL << 0) + | (0x0UL << 6) + | (0x0UL << 7) + | (0x3UL << 8) + | (0x3UL << 10) + | (0x2UL << 12) + | (0x0UL << 14) + | (0x0UL << 16) + | (0x0UL << 22) + | (0x1UL << 23) + | (0x2UL << 30) + | (0x1UL << 32) + | (0x0UL << 35) + | (0x0UL << 36) + | (0x0UL << 37) + | (0x0UL << 38); + asm volatile("msr TCR_EL1, %0\n"::"r"(val32)); + asm volatile("mrs %0, TCR_EL1\n":"=r"(val32)); + + asm volatile("msr TTBR0_EL1, %0\n dsb sy\n"::"r"(main_tbl)); + asm volatile("mrs %0, TTBR0_EL1\n dsb sy\n":"=r"(val64)); + + rt_memset(main_tbl, 0, 4096); + + ret = armv8_map_2M((unsigned long *)main_tbl, 0x0, 0x0, 32, MEM_ATTR_MEM); //32*2M = 64M + if (ret) + { + goto skip_mmu; + } + ret = armv8_map_2M((unsigned long *)main_tbl, 0x3f000000, 0x3f000000, 8, MEM_ATTR_IO); //8*2M = 16M + if (ret) + { + goto skip_mmu; + } + + //关闭指令cache + __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val64)); + val64 &= ~0x1000; //disable I + __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\n isb sy\n"::"r"(val64)); + + //清除指令cache + __asm__ volatile("IC IALLUIS\n dsb sy\n isb sy\n"); + //清除tlb + __asm__ volatile("tlbi vmalle1\n dsb sy\n isb sy\n"); + + //SCTLR_EL1, turn on mmu + asm volatile("mrs %0, SCTLR_EL1\n":"=r"(val32)); + val32 |= 0x1005; //enable mmu, I C M + asm volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32)); + +skip_mmu: + + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device + rt_hw_vector_init(); // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors); + + /* initialize uart */ + rt_hw_uart_init(); // driver/drv_uart.c + /* initialize timer for os tick */ + rt_hw_timer_init(); + rt_thread_idle_sethook(idle_wfi); + +#ifdef RT_USING_CONSOLE + /* set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif /* RT_USING_CONSOLE */ + +#ifdef RT_USING_HEAP + /* initialize memory system */ + rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + rt_kprintf("__page_off = %x\n", __page_off); +} + +#ifdef RT_USING_SMP +void _reset(void); +void secondary_cpu_start(void); + +void rt_hw_secondary_cpu_up(void) +{ + int i; + int retry,val; + rt_cpu_dcache_clean_flush(); + rt_cpu_icache_flush(); + /*TODO maybe, there is some bug */ + for(i=RT_CPUS_NR-1; i>0; i-- ) + { + rt_kprintf("boot cpu:%d\n", i); + setup_bootstrap_addr(i, (int)_reset); + __SEV(); + __DSB(); + __ISB(); + retry = 10; + rt_thread_delay(RT_TICK_PER_SECOND/1000); + do + { + val = CORE_MAILBOX3_CLEAR(i); + if (val == 0) + { + rt_kprintf("start OK: CPU %d \n",i); + break; + } + rt_thread_delay(RT_TICK_PER_SECOND); + + retry --; + if (retry <= 0) + { + rt_kprintf("can't start for CPU %d \n",i); + break; + } + }while (1); + } + __DSB(); + __SEV(); +} + +void secondary_cpu_c_start(void) +{ + uint32_t id; + id = rt_hw_cpu_id(); + rt_kprintf("cpu = 0x%08x\n",id); + rt_hw_timer_init(); + rt_kprintf("cpu %d startup.\n",id); + rt_hw_vector_init(); + enable_cpu_ipi_intr(id); + rt_hw_spin_lock(&_cpus_lock); + rt_system_scheduler_start(); +} + +void rt_hw_secondary_cpu_idle_exec(void) +{ + __WFE(); +} + +#endif diff --git a/bsp/raspberry-pi/raspi3-64/driver/board.h b/bsp/raspberry-pi/raspi3-64/driver/board.h new file mode 100644 index 0000000000000000000000000000000000000000..40fbfd9d84711029b9fe07cd494bb13fb06874d4 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/board.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-5-30 Bernard the first version + */ + +#ifndef BOARD_H__ +#define BOARD_H__ + +#include + +#include +#include + +#define __REG32 HWREG32 +extern unsigned char __bss_start; +extern unsigned char __bss_end; + +#define RT_HW_HEAP_BEGIN (void*)&__bss_end +#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 4 * 1024 * 1024) + +void rt_hw_board_init(void); + +#endif + diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c new file mode 100644 index 0000000000000000000000000000000000000000..485f7b587bbf1419d6ea110faae3bbced889c5dc --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c @@ -0,0 +1,523 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-08-29 zdzn first version + */ + +#include +#include +#include "mbox.h" +#include "drv_fb.h" +#include "mmu.h" + +#define CHAR_W 8 +#define CHAR_H 12 + +#define COLOR_DELTA 0.05 +static struct rt_hdmi_fb_device _hdmi; + +// https://github.com/xinu-os/xinu/blob/1789b7a50b5b73c2ea76ebd764c54a034097d04d/device/framebuffer_rpi/font.c +unsigned char FONT[] = { +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*' '*/ +0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, /*'!'*/ +0x00, 0x14, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'"'*/ +0x00, 0x00, 0x14, 0x14, 0x3e, 0x14, 0x3e, 0x14, 0x14, 0x00, 0x00, 0x00, /*'#'*/ +0x00, 0x00, 0x08, 0x3c, 0x0a, 0x1c, 0x28, 0x1e, 0x08, 0x00, 0x00, 0x00, /*'$'*/ +0x00, 0x00, 0x06, 0x26, 0x10, 0x08, 0x04, 0x32, 0x30, 0x00, 0x00, 0x00, /*'%'*/ +0x00, 0x00, 0x1c, 0x02, 0x02, 0x04, 0x2a, 0x12, 0x2c, 0x00, 0x00, 0x00, /*'&'*/ +0x00, 0x18, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'''*/ +0x20, 0x10, 0x10, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10, 0x10, 0x20, 0x00, /*'('*/ +0x02, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, 0x02, 0x00, /*')'*/ +0x00, 0x00, 0x00, 0x08, 0x2a, 0x1c, 0x2a, 0x08, 0x00, 0x00, 0x00, 0x00, /*'*'*/ +0x00, 0x00, 0x00, 0x08, 0x08, 0x3e, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, /*'+'*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x08, 0x04, 0x00, /*','*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'-'*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, /*'.'*/ +0x20, 0x20, 0x10, 0x10, 0x08, 0x08, 0x04, 0x04, 0x02, 0x02, 0x00, 0x00, /*'/'*/ +0x00, 0x1c, 0x22, 0x32, 0x2a, 0x26, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'0'*/ +0x00, 0x08, 0x0c, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, /*'1'*/ +0x00, 0x1c, 0x22, 0x20, 0x10, 0x08, 0x04, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'2'*/ +0x00, 0x1c, 0x22, 0x20, 0x18, 0x20, 0x20, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'3'*/ +0x00, 0x10, 0x18, 0x18, 0x14, 0x14, 0x3e, 0x10, 0x38, 0x00, 0x00, 0x00, /*'4'*/ +0x00, 0x3e, 0x02, 0x02, 0x1e, 0x20, 0x20, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'5'*/ +0x00, 0x18, 0x04, 0x02, 0x1e, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'6'*/ +0x00, 0x3e, 0x22, 0x20, 0x20, 0x10, 0x10, 0x08, 0x08, 0x00, 0x00, 0x00, /*'7'*/ +0x00, 0x1c, 0x22, 0x22, 0x1c, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'8'*/ +0x00, 0x1c, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x10, 0x0c, 0x00, 0x00, 0x00, /*'9'*/ +0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, /*':'*/ +0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x18, 0x18, 0x08, 0x04, 0x00, /*';'*/ +0x00, 0x00, 0x00, 0x30, 0x0c, 0x03, 0x0c, 0x30, 0x00, 0x00, 0x00, 0x00, /*'<'*/ +0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, /*'='*/ +0x00, 0x00, 0x00, 0x03, 0x0c, 0x30, 0x0c, 0x03, 0x00, 0x00, 0x00, 0x00, /*'>'*/ +0x00, 0x1c, 0x22, 0x20, 0x10, 0x08, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, /*'?'*/ +0x00, 0x00, 0x1c, 0x22, 0x3a, 0x3a, 0x1a, 0x02, 0x1c, 0x00, 0x00, 0x00, /*'@'*/ +0x00, 0x00, 0x08, 0x14, 0x22, 0x22, 0x3e, 0x22, 0x22, 0x00, 0x00, 0x00, /*'A'*/ +0x00, 0x00, 0x1e, 0x22, 0x22, 0x1e, 0x22, 0x22, 0x1e, 0x00, 0x00, 0x00, /*'B'*/ +0x00, 0x00, 0x1c, 0x22, 0x02, 0x02, 0x02, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'C'*/ +0x00, 0x00, 0x0e, 0x12, 0x22, 0x22, 0x22, 0x12, 0x0e, 0x00, 0x00, 0x00, /*'D'*/ +0x00, 0x00, 0x3e, 0x02, 0x02, 0x1e, 0x02, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'E'*/ +0x00, 0x00, 0x3e, 0x02, 0x02, 0x1e, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, /*'F'*/ +0x00, 0x00, 0x1c, 0x22, 0x02, 0x32, 0x22, 0x22, 0x3c, 0x00, 0x00, 0x00, /*'G'*/ +0x00, 0x00, 0x22, 0x22, 0x22, 0x3e, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'H'*/ +0x00, 0x00, 0x3e, 0x08, 0x08, 0x08, 0x08, 0x08, 0x3e, 0x00, 0x00, 0x00, /*'I'*/ +0x00, 0x00, 0x38, 0x20, 0x20, 0x20, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'J'*/ +0x00, 0x00, 0x22, 0x12, 0x0a, 0x06, 0x0a, 0x12, 0x22, 0x00, 0x00, 0x00, /*'K'*/ +0x00, 0x00, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'L'*/ +0x00, 0x00, 0x22, 0x36, 0x2a, 0x2a, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'M'*/ +0x00, 0x00, 0x22, 0x26, 0x26, 0x2a, 0x32, 0x32, 0x22, 0x00, 0x00, 0x00, /*'N'*/ +0x00, 0x00, 0x1c, 0x22, 0x22, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'O'*/ +0x00, 0x00, 0x1e, 0x22, 0x22, 0x1e, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, /*'P'*/ +0x00, 0x00, 0x1c, 0x22, 0x22, 0x22, 0x22, 0x22, 0x1c, 0x30, 0x00, 0x00, /*'Q'*/ +0x00, 0x00, 0x1e, 0x22, 0x22, 0x1e, 0x0a, 0x12, 0x22, 0x00, 0x00, 0x00, /*'R'*/ +0x00, 0x00, 0x1c, 0x22, 0x02, 0x1c, 0x20, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'S'*/ +0x00, 0x00, 0x3e, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, /*'T'*/ +0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'U'*/ +0x00, 0x00, 0x22, 0x22, 0x22, 0x14, 0x14, 0x08, 0x08, 0x00, 0x00, 0x00, /*'V'*/ +0x00, 0x00, 0x22, 0x22, 0x22, 0x2a, 0x2a, 0x36, 0x22, 0x00, 0x00, 0x00, /*'W'*/ +0x00, 0x00, 0x22, 0x22, 0x14, 0x08, 0x14, 0x22, 0x22, 0x00, 0x00, 0x00, /*'X'*/ +0x00, 0x00, 0x22, 0x22, 0x14, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, /*'Y'*/ +0x00, 0x00, 0x3e, 0x20, 0x10, 0x08, 0x04, 0x02, 0x3e, 0x00, 0x00, 0x00, /*'Z'*/ +0x38, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x38, 0x00, /*'['*/ +0x02, 0x02, 0x04, 0x04, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x00, 0x00, /*'\'*/ +0x0e, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x0e, 0x00, /*']'*/ +0x00, 0x08, 0x14, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'^'*/ +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, /*'_'*/ +0x00, 0x0c, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'`'*/ +0x00, 0x00, 0x00, 0x00, 0x3c, 0x22, 0x22, 0x32, 0x2c, 0x00, 0x00, 0x00, /*'a'*/ +0x00, 0x02, 0x02, 0x02, 0x1e, 0x22, 0x22, 0x22, 0x1e, 0x00, 0x00, 0x00, /*'b'*/ +0x00, 0x00, 0x00, 0x00, 0x3c, 0x02, 0x02, 0x02, 0x3c, 0x00, 0x00, 0x00, /*'c'*/ +0x00, 0x20, 0x20, 0x20, 0x3c, 0x22, 0x22, 0x22, 0x3c, 0x00, 0x00, 0x00, /*'d'*/ +0x00, 0x00, 0x00, 0x00, 0x1c, 0x22, 0x3e, 0x02, 0x1c, 0x00, 0x00, 0x00, /*'e'*/ +0x00, 0x38, 0x04, 0x04, 0x1e, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, /*'f'*/ +0x00, 0x00, 0x00, 0x00, 0x3c, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x20, 0x1c, /*'g'*/ +0x00, 0x02, 0x02, 0x02, 0x1e, 0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'h'*/ +0x00, 0x08, 0x08, 0x00, 0x0c, 0x08, 0x08, 0x08, 0x1c, 0x00, 0x00, 0x00, /*'i'*/ +0x00, 0x10, 0x10, 0x00, 0x1c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0e, /*'j'*/ +0x00, 0x02, 0x02, 0x02, 0x12, 0x0a, 0x06, 0x0a, 0x12, 0x00, 0x00, 0x00, /*'k'*/ +0x00, 0x0c, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x1c, 0x00, 0x00, 0x00, /*'l'*/ +0x00, 0x00, 0x00, 0x00, 0x16, 0x2a, 0x2a, 0x2a, 0x22, 0x00, 0x00, 0x00, /*'m'*/ +0x00, 0x00, 0x00, 0x00, 0x1a, 0x26, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, /*'n'*/ +0x00, 0x00, 0x00, 0x00, 0x1c, 0x22, 0x22, 0x22, 0x1c, 0x00, 0x00, 0x00, /*'o'*/ +0x00, 0x00, 0x00, 0x00, 0x1e, 0x22, 0x22, 0x22, 0x1e, 0x02, 0x02, 0x02, /*'p'*/ +0x00, 0x00, 0x00, 0x00, 0x3c, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x20, 0x20, /*'q'*/ +0x00, 0x00, 0x00, 0x00, 0x1a, 0x06, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, /*'r'*/ +0x00, 0x00, 0x00, 0x00, 0x3c, 0x02, 0x1c, 0x20, 0x1e, 0x00, 0x00, 0x00, /*'s'*/ +0x00, 0x08, 0x08, 0x08, 0x3e, 0x08, 0x08, 0x08, 0x30, 0x00, 0x00, 0x00, /*'t'*/ +0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x32, 0x2c, 0x00, 0x00, 0x00, /*'u'*/ +0x00, 0x00, 0x00, 0x00, 0x36, 0x14, 0x14, 0x08, 0x08, 0x00, 0x00, 0x00, /*'v'*/ +0x00, 0x00, 0x00, 0x00, 0x22, 0x2a, 0x2a, 0x2a, 0x14, 0x00, 0x00, 0x00, /*'w'*/ +0x00, 0x00, 0x00, 0x00, 0x22, 0x14, 0x08, 0x14, 0x22, 0x00, 0x00, 0x00, /*'x'*/ +0x00, 0x00, 0x00, 0x00, 0x22, 0x22, 0x22, 0x22, 0x3c, 0x20, 0x20, 0x1c, /*'y'*/ +0x00, 0x00, 0x00, 0x00, 0x3e, 0x10, 0x08, 0x04, 0x3e, 0x00, 0x00, 0x00, /*'z'*/ +0x20, 0x10, 0x10, 0x10, 0x10, 0x08, 0x10, 0x10, 0x10, 0x10, 0x20, 0x00, /*'{'*/ +0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, /*'|'*/ +0x02, 0x04, 0x04, 0x04, 0x04, 0x08, 0x04, 0x04, 0x04, 0x04, 0x02, 0x00, /*'}'*/ +0x00, 0x04, 0x2a, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*'~'*/ +0x00, 0x00, 0x00, 0x08, 0x08, 0x14, 0x14, 0x22, 0x3e, 0x00, 0x00, 0x00, /*DEL*/ +}; + +void newline(fb_t* fb) +{ + uint8_t* to; + uint8_t* from; + int i; + fb->y++; + fb->x = 0; + + if (fb->y == (fb->height / CHAR_H)) + { + + to = (uint8_t*) fb->addr; + from = to + (CHAR_H * fb->pitch); + + for (i = 0; i < ((fb->height - CHAR_H) * fb->pitch); i++) + { + *to++ = *from++; + } + + uint32_t *addr = (uint32_t*) (fb->addr) + (fb->height - CHAR_H) * fb->width; + + for (i = 0; i < (CHAR_H * fb->width); i++) + { + *addr++ = fb->back; + } + + fb->y--; + } +} + +void clear_line(fb_t *fb, const int line) +{ + int i; + uint32_t* addr; + if (line > fb->height / CHAR_H) + { + fb->y = 0; + } + else + { + fb->y = line; + } + + fb->x = 0; + + addr = (uint32_t*) (fb->addr + (line * CHAR_H * fb->depth * fb->width)); + for (i = 0; i < (CHAR_H * fb->width); i++) + { + *addr++ = fb->back; + } + +} + +void clear(fb_t *fb, const uint32_t color) +{ + + uint32_t *addr = (uint32_t*) fb->addr; + uint32_t i; + for (i = 0; i < (fb->height * fb->width); i++) + { + *addr++ = color; + } + fb->x = 0; + fb->y = 0; + +} + +void fb_draw_char(fb_t *fb, char s) +{ + unsigned char* addr = (unsigned char*) fb->addr; + unsigned char *glyph = (unsigned char*) FONT + (s) * 12; + // calculate the offset on screen + int offs = (fb->y * CHAR_H * fb->pitch) + (fb->x * (CHAR_W + 1) * 4); + // variables + int i, j, line, mask, bytesperline = (CHAR_W + 7) / 8; + // display a character + for (j = 0; j < CHAR_H; j++) + { + // display one row + line = offs; + mask = 1; + for (i = 0; i < CHAR_W; i++) + { + // if bit set, we use white color, otherwise black + *((unsigned int*) (addr + line)) = ((int) *glyph) & mask ? fb->fore : fb->back; + mask <<= 1; + line += 4; + } + // adjust to next line + glyph += bytesperline; + offs += fb->pitch; + } +} + +void fb_print(fb_t *fb, char *s) +{ + + // draw next character if it's not zero + while (*s) + { + // handle carrige return + if (*s == '\r') + { + fb->x = 0; + } + else if (*s == '\n') + { + newline(fb); + } + else if (*s == '\t') + { + fb->x = ((fb->x + 4) >> 2) << 2; + } + else if (*s == '\b') + { + if (fb->x) + { + fb->x--; + fb_draw_char(fb, ' '); + } + } + else + { + fb_draw_char(fb, *s); + fb->x++; + } + // next character + if (fb->x == fb->width / CHAR_W) + { + newline(fb); + } + s++; + } +} + +rt_err_t hdmi_fb_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +rt_err_t hdmi_fb_close(rt_device_t dev) +{ + return RT_EOK; +} + +rt_size_t hdmi_fb_read(rt_device_t dev, rt_off_t pos, void *buf, rt_size_t size) +{ +#ifdef BSP_USING_USPI + char* buffer = (char *) buf; + if(keyboard_available()) + { + int i = 0; + int j = 0; + while (i != size) + { + int ch = keyboard_getchar(); + if(ch != -1) + buffer[j++] = ch; + i++; + } + return j; + + } +#endif + return 0; +} + +rt_size_t hdmi_fb_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + fb_print(&_hdmi.fb, (char *) buffer); +#ifdef BSP_USING_HDMI_DISPLAY + rt_device_t uart = rt_device_find("uart1"); + int old_flag = uart->open_flag; + uart->open_flag |= RT_DEVICE_FLAG_STREAM; + rt_device_write(uart, 0, buffer, size); + uart->open_flag = old_flag; +#endif + return size; + +} + +rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args) +{ + return RT_EOK; +} + +const static struct rt_device_ops hdmi_fb_ops = { + RT_NULL, + hdmi_fb_open, + hdmi_fb_close, + hdmi_fb_read, + hdmi_fb_write, + hdmi_fb_control +}; + +static struct rt_device_graphic_info _hdmi_info; + +static void hdmi_draw_rect(const char* pixel, int x1, int y1, int x2, int y2) +{ + int i, j; + int line; + for (j = y1; j <= y2; j++) + { + line = (j * _hdmi.fb.pitch) + (x1 * 4); + for (i = x1; i <= x2; i++) + { + // if bit set, we use white color, otherwise black + *((unsigned int*) (_hdmi_info.framebuffer + line)) = *(unsigned int*) pixel; + line += 4; + } + } + +} + +static void hdmi_set_pixel(const char* pixel, int x, int y) +{ + *(uint32_t*) (_hdmi.fb.addr + (y * _hdmi.fb.pitch + x * 4)) = *(uint32_t *) pixel; +} + +static void hdmi_get_pixel(char* pixel, int x, int y) +{ + uint32_t ret = 0; + ret = (*(uint32_t*) (_hdmi.fb.addr + (y * _hdmi.fb.pitch + x * 4)) & 0x00FFFFFF); + *pixel = ret; +} + +static void hdmi_draw_hline(const char* pixel, int x1, int x2, int y) +{ + hdmi_draw_rect(pixel, x1, y, x2, y); +} + +static void hdmi_draw_vline(const char* pixel, int x, int y1, int y2) +{ + hdmi_draw_rect(pixel, x, y1, x, y2); +} + +static void hdmi_blit_line(const char* pixels, int x, int y, rt_size_t size) +{ + int i = 0; + uint32_t *pixel_base = (uint32_t*) (_hdmi.fb.addr + (y * _hdmi.fb.pitch + x * 4)); + uint32_t *colors = (uint32_t *) pixels; + for (i = 0; i < size; i++) + { + pixel_base[i] = colors[i]; + } +} + +static struct rt_device_graphic_ops hdmi_ops = { + hdmi_set_pixel, + hdmi_get_pixel, + hdmi_draw_hline, + hdmi_draw_vline, + hdmi_blit_line +}; + +rt_err_t rt_hdmi_fb_device_init(struct rt_hdmi_fb_device *hdmi_fb, const char *name) +{ + struct rt_device *device; + RT_ASSERT(hdmi_fb != RT_NULL); + + device = &hdmi_fb->parent; + device->user_data = &hdmi_ops; + + /* set device type */ + device->type = RT_Device_Class_Graphic; + /* initialize device interface */ +#ifdef RT_USING_DEVICE_OPS + device->ops = &hdmi_fb_ops; +#else + device->init = RT_NULL; + device->open = hdmi_fb_open; + device->close = hdmi_fb_close; + device->read = hdmi_fb_read; + device->write = hdmi_fb_write; + device->control = hdmi_fb_control; +#endif + + /* register to device manager */ + rt_device_register(device, name, RT_DEVICE_FLAG_RDWR); + + return RT_EOK; +} + +/** + * Show a picture + */ +void print_fb_info() +{ + rt_kprintf("FrameBuffer Info: \n \t width %x\t height %x\t depth %x\t addr %x\t size %x\t \n", fb_info.width, + fb_info.height, fb_info.depth, fb_info.addr, fb_info.size); + rt_kprintf("call mbox:%x,%x,%x,%x,%x\n", mbox[0], mbox[1], mbox[2], mbox[3], mbox[4]); +} + +void hdmi_fb_init() +{ + unsigned int *mbox = (unsigned int*) MBOX_ADDR; + mbox[0] = 35 * 4; + mbox[1] = MBOX_REQUEST; + + mbox[2] = 0x48003; //set phy wh + mbox[3] = 8; + mbox[4] = 8; + mbox[5] = 640; //FrameBufferInfo.width + mbox[6] = 480; //FrameBufferInfo.height + + mbox[7] = 0x48004; //set virt wh + mbox[8] = 8; + mbox[9] = 8; + mbox[10] = 640; //FrameBufferInfo.virtual_width + mbox[11] = 480; //FrameBufferInfo.virtual_height + + mbox[12] = 0x48009; //set virt offset + mbox[13] = 8; + mbox[14] = 8; + mbox[15] = 0; //FrameBufferInfo.x_offset + mbox[16] = 0; //FrameBufferInfo.y.offset + + mbox[17] = 0x48005; //set depth + mbox[18] = 4; + mbox[19] = 4; + mbox[20] = 32; //FrameBufferInfo.depth + + mbox[21] = 0x48006; //set pixel order + mbox[22] = 4; + mbox[23] = 4; + mbox[24] = 1; //RGB, not BGR preferably + + mbox[25] = 0x40001; //get framebuffer, gets alignment on request + mbox[26] = 8; + mbox[27] = 8; + mbox[28] = 4096; //FrameBufferInfo.pointer + mbox[29] = 0; //FrameBufferInfo.size + + mbox[30] = 0x40008; //get pitch + mbox[31] = 4; + mbox[32] = 4; + mbox[33] = 0; //FrameBufferInfo.pitch + + mbox[34] = MBOX_TAG_LAST; + if (mbox_call(MBOX_CH_PROP, MMU_DISABLE) && mbox[20] == 32 && mbox[28] != 0) + { + mbox[28] &= 0x3FFFFFFF; + _hdmi.fb.width = mbox[5]; + _hdmi.fb.height = mbox[6]; + _hdmi.fb.pitch = mbox[33]; + //_hdmi.fb.addr = (void*)((unsigned long)mbox[28]); + _hdmi.fb.addr = (rt_uint32_t) mbox[28]; + _hdmi.fb.size = mbox[29]; + _hdmi.fb.depth = 32; + _hdmi.fb.x = 0; + _hdmi.fb.y = 0; + _hdmi.fb.fore = CONSOLE_WHITE; + _hdmi.fb.back = CONSOLE_BLACK; + rt_hdmi_fb_device_init(&_hdmi, "hdmi"); + rt_hw_change_mmu_table(_hdmi.fb.addr, _hdmi.fb.size, _hdmi.fb.addr, DEVICE_MEM); + fb_info.width = _hdmi.fb.width; + fb_info.height = _hdmi.fb.height; + fb_info.addr = _hdmi.fb.addr; + fb_info.size = _hdmi.fb.size; + fb_info.pitch = _hdmi.fb.pitch; + fb_info.depth = _hdmi.fb.depth; + _hdmi_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888; + _hdmi_info.bits_per_pixel = _hdmi.fb.depth; + _hdmi_info.width = _hdmi.fb.width; + _hdmi_info.height = _hdmi.fb.height; + _hdmi_info.framebuffer = (rt_uint8_t *) _hdmi.fb.addr; + } +} + diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_fb.h b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.h new file mode 100644 index 0000000000000000000000000000000000000000..1b733f8d0fbd63ba24f0dea904701d78b79c38a0 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-08-29 zdzn first version + */ +#ifndef __DRV_FB_H__ +#define __DRV_FB_H__ + +#define RGB(r, g, b) ((((r))<<16) | (((g))<<8) | ((b))) + +#define COLOR_BLACK RGB(0, 0, 0) + +#define COLOR_GREEN RGB(0, 255, 0) + +#define COLOR_CYAN RGB(0, 255, 255) + +#define COLOR_RED RGB(255, 0, 0) + +#define COLOR_YELLOW RGB(255, 255, 0) + +#define COLOR_WHITE RGB(255, 255, 255) + +#define CONSOLE_WHITE COLOR_WHITE +#define CONSOLE_BLACK COLOR_BLACK +#define CONSOLE_GREEN COLOR_GREEN +#define CONSOLE_CYAN COLOR_CYAN +#define CONSOLE_RED COLOR_RED +#define CONSOLE_YELLOW COLOR_YELLOW + +typedef struct +{ + rt_uint32_t width; + rt_uint32_t height; + rt_uint32_t vwidth; + rt_uint32_t vheight; + rt_uint32_t pitch; + rt_uint32_t depth; + rt_uint32_t fore; + rt_uint32_t back; + rt_uint32_t x; + rt_uint32_t y; + rt_uint32_t addr; + rt_uint32_t size; +}fb_t; + +struct rt_hdmi_fb_device +{ + struct rt_device parent; + fb_t fb; +}; + +fb_t fb_info; +void print_fb_info(); +void hdmi_fb_init(); + +#endif/* __DRV_FB_H__ */ diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..ce1883cce7c68961da6b50d51b37c2e51a94bf9a --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c @@ -0,0 +1,473 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ +#include "raspi.h" +#include "drv_gpio.h" + +#ifdef BSP_USING_PIN + +struct rpi_pin_index +{ + rt_uint8_t phy_id; + rt_uint8_t bcm_id; + rt_uint8_t signal_name; + rt_uint8_t magic; +}; + +//raspi phy id and bcm id +static struct rpi_pin_index phypin_index[] = +{ + {0, 0, 0, 0}, + {1, 0, 0, 0}, + {2, 0, 0, 0}, + {3, BCM_GPIO_PIN_2, RPI_SDA1, PIN_MAGIC}, + {4, 0, 0, 0}, + {5, BCM_GPIO_PIN_3, RPI_SCL1, PIN_MAGIC}, + {6, 0, 0, 0}, + {7, BCM_GPIO_PIN_4, RPI_GPIO_GCLK, PIN_MAGIC}, + {8, BCM_GPIO_PIN_14, RPI_TXD0, PIN_MAGIC}, + {9, 0, 0, 0}, + {10, BCM_GPIO_PIN_15, RPI_RXD0, PIN_MAGIC}, + {11, BCM_GPIO_PIN_17, RPI_GPIO_GEN0, PIN_MAGIC}, + {12, BCM_GPIO_PIN_18, RPI_GPIO_GEN1, PIN_MAGIC}, + {13, BCM_GPIO_PIN_27, RPI_GPIO_GEN2, PIN_MAGIC}, + {14, 0, 0, 0}, + {15, BCM_GPIO_PIN_22, RPI_GPIO_GEN3, PIN_MAGIC}, + {16, BCM_GPIO_PIN_23, RPI_GPIO_GEN4, PIN_MAGIC}, + {17, 0, 0, 0}, + {18, BCM_GPIO_PIN_24, RPI_GPIO_GEN5, PIN_MAGIC}, + {19, BCM_GPIO_PIN_10, RPI_SPI_MOSI, PIN_MAGIC}, + {20, 0, 0, 0}, + {21, BCM_GPIO_PIN_9, RPI_SPI_MISO, PIN_MAGIC}, + {22, BCM_GPIO_PIN_25, RPI_GPIO_GEN6, PIN_MAGIC}, + {23, BCM_GPIO_PIN_11, RPI_SPI_SCLK, PIN_MAGIC}, + {24, BCM_GPIO_PIN_8, RPI_SPI_CE0_N, PIN_MAGIC}, + {25, 0, 0, 0}, + {26, BCM_GPIO_PIN_7, RPI_SPI_CE1_N, PIN_MAGIC}, + {27, BCM_GPIO_PIN_0, RPI_SDA0, PIN_MAGIC}, + {28, BCM_GPIO_PIN_1, RPI_SCL0, PIN_MAGIC}, + {29, BCM_GPIO_PIN_5, RPI_CAM_CLK, PIN_MAGIC}, + {30, 0, 0, 0}, + {31, BCM_GPIO_PIN_6, RPI_LAN_RUN, PIN_MAGIC}, + {32, BCM_GPIO_PIN_12, 0, PIN_MAGIC}, + {33, BCM_GPIO_PIN_13, 0, PIN_MAGIC}, + {34, 0, 0, 0}, + {35, BCM_GPIO_PIN_19, 0, PIN_MAGIC}, + {36, BCM_GPIO_PIN_16, RPI_STATUS_LED_N, PIN_MAGIC}, + {37, BCM_GPIO_PIN_26, 0, PIN_MAGIC}, + {38, BCM_GPIO_PIN_20, 0, PIN_MAGIC}, + {39, 0, 0, 0}, + {40, BCM_GPIO_PIN_21, RPI_CAM_GPIO, PIN_MAGIC}, +}; + +/* + * gpio_int[0] for BANK0 (pins 0-27) + * gpio_int[1] for BANK1 (pins 28-45) + * gpio_int[2] for BANK2 (pins 46-53) + */ +static struct gpio_irq_def _g_gpio_irq_tbl[GPIO_IRQ_NUM]; + +int gpio_set_func(enum gpio_code code, enum bcm_gpio_pin pin, rt_uint8_t func) +{ + RT_ASSERT((GPIO_CODE_PHY <= code) && (code < GPIO_CODE_NUM)); + RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53)); + + if (func & 0x8) + { + rt_kprintf("[line]:%d There is a warning with parameter input", __LINE__); + return RT_EINVAL; + } + + switch(func) + { + case 0x00: + bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_OUTP); + break; + case 0x01: + bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_INPT); + break; + case 0x02: + bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_UP); + bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_INPT); + break; + case 0x03: + bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_DOWN); + bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_INPT); + break; + case 0x04: + bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_OFF); + bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_OUTP); + break; + } + + return RT_EOK; +} + +int gpio_set_value(enum gpio_code code, enum bcm_gpio_pin pin, rt_uint8_t value) +{ + + RT_ASSERT((GPIO_CODE_PHY <= code) && (code < GPIO_CODE_NUM)); + RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53)); + + if (value & 0xE) + { + rt_kprintf("[line]:%d There is a warning with parameter input", __LINE__); + return RT_EINVAL; + } + + bcm283x_gpio_write(pin, value); + return RT_EOK; +} + +int gpio_get_value(enum gpio_code code, enum bcm_gpio_pin pin) +{ + rt_uint8_t data; + + RT_ASSERT((GPIO_CODE_PHY <= code) && (code < GPIO_CODE_NUM)); + RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53)); + + data = bcm283x_gpio_lev(pin); + return data; +} + +void gpio_set_irq_callback(enum gpio_code port, enum bcm_gpio_pin pin, void (*irq_cb)(void *), void *irq_arg) +{ + RT_ASSERT((GPIO_CODE_PHY < port) && (port < GPIO_CODE_NUM)); + RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53)); + + rt_uint8_t index; + if (pin <= 27) + { + index = 0; + } + else if (pin <= 45) + { + index = 1; + } + else{ + index = 2; + } + _g_gpio_irq_tbl[index].irq_cb[pin] = irq_cb; + _g_gpio_irq_tbl[index].irq_arg[pin] = irq_arg; +} + +void gpio_set_irq_type(enum gpio_code port, enum bcm_gpio_pin pin, rt_uint8_t irq_type) +{ + + RT_ASSERT((GPIO_CODE_PHY < port) && (port < GPIO_CODE_NUM)); + RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53)); + + rt_uint8_t index; + if (pin <= 27) + { + index = 0; + } + else if (pin <= 45) + { + index = 1; + } + else{ + index = 2; + } + _g_gpio_irq_tbl[index].irq_type[pin] = irq_type; + + switch(irq_type) + { + case 0x00: + bcm283x_gpio_ren(pin); + break; + case 0x01: + bcm283x_gpio_fen(pin); + break; + case 0x02: + bcm283x_gpio_aren(pin); + bcm283x_gpio_afen(pin); + break; + case 0x03: + bcm283x_gpio_hen(pin); + break; + case 0x04: + bcm283x_gpio_len(pin); + break; + } +} + +static void gpio_ack_irq(int irq, enum bcm_gpio_pin pin) +{ + rt_uint32_t data; + data = IRQ_PEND2; + data &= (0x0 << (irq - 32)); + IRQ_PEND2 = data; + + data = IRQ_DISABLE2; + data |= (0x1 << (irq - 32)); + IRQ_DISABLE2 = data; +} + +void gpio_irq_disable(enum gpio_code port, enum bcm_gpio_pin pin) +{ + rt_uint8_t index; + int irq = 0; + RT_ASSERT((GPIO_CODE_PHY < port) && (port < GPIO_CODE_NUM)); + RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53)); + + if (pin <= 27) + { + index = 0; + irq = IRQ_GPIO0; + }else if (pin <= 45){ + index = 1; + irq = IRQ_GPIO1; + }else{ + index = 2; + irq = IRQ_GPIO2; + } + + gpio_ack_irq(irq, pin); + + rt_uint8_t irq_type = _g_gpio_irq_tbl[index].irq_type[pin]; + + switch(irq_type) + { + case 0x00: + bcm283x_gpio_clr_ren(pin); + break; + case 0x01: + bcm283x_gpio_clr_fen(pin); + break; + case 0x02: + bcm283x_gpio_clr_aren(pin); + bcm283x_gpio_clr_afen(pin); + break; + case 0x03: + bcm283x_gpio_clr_hen(pin); + break; + case 0x04: + bcm283x_gpio_clr_len(pin); + break; + } +} + +void gpio_clear_irq_callback(enum gpio_code port, enum bcm_gpio_pin pin) +{ + rt_uint8_t index; + gpio_irq_disable(port, pin); + + if (pin <= 27) + { + index = 0; + } + else if (pin <= 45) + { + index = 1; + } + else + { + index = 2; + } + + _g_gpio_irq_tbl[index].irq_cb[pin] = RT_NULL; + _g_gpio_irq_tbl[index].irq_arg[pin] = RT_NULL; + _g_gpio_irq_tbl[index].irq_type[pin] = RT_NULL; + +} + + +void gpio_irq_enable(enum gpio_code port, enum bcm_gpio_pin pin) +{ + + rt_uint32_t offset; + rt_uint32_t data; + + RT_ASSERT((GPIO_CODE_PHY < port) && (port < GPIO_CODE_NUM)); + RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_53)); + + offset = pin; + if (pin <= 27) + { + offset = IRQ_GPIO0 - 32; + } + else if (pin <= 45) + { + offset = IRQ_GPIO1 - 32; + } + else + { + offset = IRQ_GPIO2 - 32; + } + + data = IRQ_ENABLE2; + data |= 0x1 << offset; + IRQ_ENABLE2 = data; + +} + +//gpio_int[0] for BANK0 (pins 0-27) +//gpio_int[1] for BANK1 (pins 28-45) +//gpio_int[2] for BANK2 (pins 46-53) +static void gpio_irq_handler(int irq, void *param) +{ + struct gpio_irq_def *irq_def = (struct gpio_irq_def *)param; + rt_uint32_t pin; + rt_uint32_t addr; + rt_uint32_t value; + rt_uint32_t tmpvalue; + + if (irq == IRQ_GPIO0) + { + /* 0~27 */ + addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS0; // 0~31 + value = bcm283x_peri_read(addr); + value &= 0x0fffffff; + pin = 0; + } + else if (irq == IRQ_GPIO1) + { + /* 28-45 */ + addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS0; + tmpvalue = bcm283x_peri_read(addr); + tmpvalue &= (~0x0fffffff); + + addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS1; + value = bcm283x_peri_read(addr); + value &= 0x3fff; + value = (value<<4) | tmpvalue; + + pin = 28; + } + else if (irq == IRQ_GPIO2) + { + /* 46-53 */ + addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS1; + value = bcm283x_peri_read(addr); + value &= (~0x3fff); + value &= 0xff600000; + pin = 46; + } + + bcm283x_peri_write(addr,0); + + while (value) + { + if ((value & 0x1) && (irq_def->irq_cb[pin] != RT_NULL)) + { + irq_def->irq_cb[pin](irq_def->irq_arg[pin]); + gpio_ack_irq(irq,pin); + } + pin++; + value = value >> 1; + } +} + +static void pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode) +{ + if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC)) + { + rt_kprintf("pin:%d value wrongful", pin); + return; + } + + gpio_set_func(GPIO_CODE_BCM, phypin_index[pin].bcm_id, mode); +} + +static void pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value) +{ + if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC)) + { + rt_kprintf("pin:%d value wrongful", pin); + return; + } + + gpio_set_value(GPIO_CODE_BCM, phypin_index[pin].bcm_id, value); +} + +static int pin_read(struct rt_device *device, rt_base_t pin) +{ + if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC)) + { + rt_kprintf("pin:%d value wrongful", pin); + return 0; + } + + return gpio_get_value(GPIO_CODE_BCM, phypin_index[pin].bcm_id); +} + +static rt_err_t pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC)) + { + rt_kprintf("pin:%d value wrongful", pin); + return RT_ERROR; + } + + gpio_set_irq_callback(GPIO_CODE_BCM , phypin_index[pin].bcm_id, hdr, args); + gpio_set_irq_type(GPIO_CODE_BCM, phypin_index[pin].bcm_id, mode); + + return RT_EOK; +} + +static rt_err_t pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC)) + { + rt_kprintf("pin:%d value wrongful", pin); + return RT_ERROR; + } + + gpio_clear_irq_callback(GPIO_CODE_BCM, phypin_index[pin].bcm_id); + + return RT_EOK; +} + +rt_err_t pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + if ((pin > PIN_NUM(phypin_index)) || (phypin_index[pin].magic != PIN_MAGIC)) + { + rt_kprintf("pin:%d value wrongful", pin); + return RT_ERROR; + } + + if (enabled) + gpio_irq_enable(GPIO_CODE_BCM, phypin_index[pin].bcm_id); + else + gpio_irq_disable(GPIO_CODE_BCM, phypin_index[pin].bcm_id); + + return RT_EOK; +} + +static const struct rt_pin_ops ops = +{ + pin_mode, + pin_write, + pin_read, + pin_attach_irq, + pin_detach_irq, + pin_irq_enable, +}; +#endif + +int rt_hw_gpio_init(void) +{ +#ifdef BSP_USING_PIN + rt_device_pin_register("gpio", &ops, RT_NULL); +#endif + + /* install ISR */ + rt_hw_interrupt_install(IRQ_GPIO0, gpio_irq_handler, &_g_gpio_irq_tbl[0], "gpio0_irq"); + rt_hw_interrupt_umask(IRQ_GPIO0); + + rt_hw_interrupt_install(IRQ_GPIO1, gpio_irq_handler, &_g_gpio_irq_tbl[1], "gpio1_irq"); + rt_hw_interrupt_umask(IRQ_GPIO1); + + rt_hw_interrupt_install(IRQ_GPIO2, gpio_irq_handler, &_g_gpio_irq_tbl[2], "gpio2_irq"); + rt_hw_interrupt_umask(IRQ_GPIO2); + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_gpio_init); diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..b0a67870abde8f9d9781daaf9c5d80c9fb2d7f98 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include +#include +#include +#include + +#include "interrupt.h" +#include "bcm283x.h" +#include "raspi.h" +#include "board.h" + +#define GPIO_IRQ_NUM 3 + +struct gpio_irq_def +{ + void *irq_arg[32]; + void (*irq_cb[32])(void *param); + rt_uint8_t irq_type[32]; +}; + +enum gpio_irq_clock +{ + GPIO_IRQ_LOSC_32KHZ = 0, + GPIO_IRQ_HOSC_24MHZ +}; + +int rt_hw_gpio_init(void); + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c b/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..5163af60eece89e9c80d3d828ad97cf82d4e6a79 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#include "drv_i2c.h" + +#if defined (BSP_USING_I2C0) +#define I2C1BUS_NAME "i2c0" +#endif /*BSP_USING_I2C0*/ + +#if defined (BSP_USING_I2C1) +#define I2C2BUS_NAME "i2c1" +#endif /*BSP_USING_I2C1*/ + +static int i2c_byte_wait_us = 0; + +#ifdef BSP_USING_I2C0 + +static struct raspi_i2c_bus raspi_i2c0 = +{ + .device_name = I2C1BUS_NAME, +}; + +static struct raspi_master_config_t raspi_i2c0_cfg = +{ + .sdl_pin = BCM_GPIO_PIN_0, + .scl_pin = BCM_GPIO_PIN_1, + .sdl_pin_mode = BCM283X_GPIO_FSEL_ALT0, + .scl_pin_mode = BCM283X_GPIO_FSEL_ALT0, + .slave_address = 8, + .bsc_base = (PER_BASE + BCM283X_BSC0_BASE), + .clk_div = BCM283X_I2C_CLOCK_DIVIDER_148, +}; + +#endif /* RT_USING_HW_I2C1 */ + +#ifdef BSP_USING_I2C1 +static struct raspi_i2c_bus raspi_i2c1 = +{ + .device_name = I2C2BUS_NAME, +}; + +static struct raspi_master_config_t raspi_i2c1_cfg = +{ + .sdl_pin = BCM_GPIO_PIN_2, + .scl_pin = BCM_GPIO_PIN_3, + .sdl_pin_mode = BCM283X_GPIO_FSEL_ALT0, + .scl_pin_mode = BCM283X_GPIO_FSEL_ALT0, + .slave_address = 9, + .bsc_base = (PER_BASE + BCM283X_BSC1_BASE), + .clk_div = BCM283X_I2C_CLOCK_DIVIDER_148, +}; +#endif /* RT_USING_HW_I2C2 */ + +#if (defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1)) + +static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num); +static rt_size_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num); +static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus, + rt_uint32_t, + rt_uint32_t); + +void i2c_master_init(struct raspi_master_config_t *cfg) +{ + volatile rt_uint32_t addr; + rt_uint32_t data; + + bcm283x_gpio_fsel(cfg->sdl_pin, cfg->sdl_pin_mode); /* SDA */ + bcm283x_gpio_fsel(cfg->scl_pin, cfg->scl_pin_mode); /* SCL */ + + addr = cfg->bsc_base + BCM283X_BSC_DIV; + data = bcm283x_peri_read(addr); + i2c_byte_wait_us = ( data * 1000000 / BCM283X_CORE_CLK_HZ) * 9; + + addr = cfg->bsc_base + BCM283X_BSC_DIV; + bcm283x_peri_write(addr, cfg->clk_div); + + //update + i2c_byte_wait_us = (cfg->clk_div * 1000000 * 9 / BCM283X_CORE_CLK_HZ); +} + +static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + volatile rt_uint32_t addr; + struct raspi_i2c_bus *raspi_i2c; + rt_size_t i; + RT_ASSERT(bus != RT_NULL); + raspi_i2c = (struct raspi_i2c_bus *) bus; + raspi_i2c->msg = msgs; + raspi_i2c->msg_ptr = 0; + raspi_i2c->msg_cnt = num; + raspi_i2c->dptr = 0; + + addr = raspi_i2c->cfg->bsc_base + BCM283X_BSC_A; + bcm283x_peri_write(addr, msgs->addr); + + for (i = 0; i < num; i++) + { + if ( raspi_i2c->msg[i].flags & RT_I2C_RD ) + { + bcm283x_i2c_read(raspi_i2c->cfg->bsc_base, raspi_i2c->msg->buf, num); + } + else + { + bcm283x_i2c_write(raspi_i2c->cfg->bsc_base, raspi_i2c->msg->buf, num); + } + } + raspi_i2c->msg = RT_NULL; + raspi_i2c->msg_ptr = 0; + raspi_i2c->msg_cnt = 0; + raspi_i2c->dptr = 0; + return i; +} + +static rt_size_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + return 0; +} +static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus, + rt_uint32_t cmd, + rt_uint32_t arg) +{ + return RT_ERROR; +} + +static const struct rt_i2c_bus_device_ops raspi_i2c_ops = +{ + .master_xfer = raspi_i2c_mst_xfer, + .slave_xfer = raspi_i2c_slv_xfer, + .i2c_bus_control = raspi_i2c_bus_control, +}; + +static rt_err_t raspi_i2c_configure(struct raspi_i2c_bus *bus, struct raspi_master_config_t *cfg) +{ + RT_ASSERT(bus != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + bus->device.ops = &raspi_i2c_ops; + bus->cfg = cfg; + + i2c_master_init(cfg); + return RT_EOK; +} +#endif + +int rt_hw_i2c_init(void) +{ + +#if defined(BSP_USING_I2C0) + raspi_i2c_configure(&raspi_i2c0 , &raspi_i2c0_cfg); + rt_i2c_bus_device_register(&raspi_i2c0.device, raspi_i2c0.device_name); +#endif /* BSP_USING_I2C1 */ + +#if defined(BSP_USING_I2C1) + + raspi_i2c_configure(&raspi_i2c1 , &raspi_i2c1_cfg); + rt_i2c_bus_device_register(&raspi_i2c1.device, raspi_i2c1.device_name); + +#endif /* BSP_USING_I2C2 */ + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h b/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..041d6b00db638790440e2d9c3a71c52452b0002a --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + +#include +#include +#include +#include "bcm283x.h" + +struct raspi_master_config_t +{ + rt_uint8_t sdl_pin; + rt_uint8_t scl_pin; + rt_uint8_t sdl_pin_mode; + rt_uint8_t scl_pin_mode; + rt_uint8_t slave_address; + rt_uint32_t bsc_base; + rt_uint16_t clk_div; +}; + +struct raspi_i2c_bus +{ + struct rt_i2c_bus_device device; + struct rt_i2c_msg *msg; + rt_uint32_t msg_cnt; + volatile rt_uint32_t msg_ptr; + volatile rt_uint32_t dptr; + char *device_name; + struct raspi_master_config_t *cfg; +}; + +int rt_hw_i2c_init(void); + +#endif diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..e38393bbd0f8f09965dda2bc4bc2822e05d02126 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + + +#include "drv_rtc.h" + +#ifdef BSP_USING_RTC + +static struct rt_rtc_device rtc_device; + +rt_uint8_t buf[]= +{ + 0x00, 0x00, 0x43, 0x15, 0x05, 0x01, 0x03, 0x19 +}; + +static time_t raspi_get_timestamp(void) +{ + struct tm tm_new = {0}; + buf[0] = 0; + bcm283x_i2c_write_read_rs((char*)buf, 1, (char*)buf, 7); + + tm_new.tm_year = ((buf[6] / 16) + 0x30) * 10 + (buf[6] % 16) + 0x30; + tm_new.tm_mon = ((buf[5] & 0x1F) / 16 + 0x30) + (buf[5] & 0x1F) % 16+ 0x30; + tm_new.tm_mday = ((buf[4] & 0x3F) / 16 + 0x30) + (buf[4] & 0x3F) % 16+ 0x30; + tm_new.tm_hour = ((buf[2] & 0x3F) / 16 + 0x30) + (buf[2] & 0x3F) % 16+ 0x30; + tm_new.tm_min = ((buf[1] & 0x7F) / 16 + 0x30) + (buf[1] & 0x7F) % 16+ 0x30; + tm_new.tm_sec = ((buf[0] & 0x7F) / 16 + 0x30) + (buf[0] & 0x7F) % 16+ 0x30; + + return mktime(&tm_new); +} + +static int raspi_set_timestamp(time_t timestamp) +{ + struct tm *tblock; + tblock = localtime(×tamp); + buf[0] = 0; + buf[1] = tblock->tm_sec; + buf[2] = tblock->tm_min; + buf[3] = tblock->tm_hour; + buf[4] = tblock->tm_wday; + buf[5] = tblock->tm_mday; + buf[6] = tblock->tm_mon; + buf[7] = tblock->tm_year; + bcm283x_i2c_write((PER_BASE + BCM283X_BSC0_BASE) ,buf, 8); + return RT_EOK; +} + +static rt_err_t raspi_rtc_init(rt_device_t dev) +{ + bcm283x_i2c_setSlaveAddress(0, 0x68); + bcm283x_i2c_set_baudrate(0, 10000); + raspi_set_timestamp(0); + return RT_EOK; +} + +static rt_err_t raspi_rtc_open(rt_device_t dev, rt_uint16_t oflag) +{ + bcm283x_i2c_begin(0); + return RT_EOK; +} + +static rt_err_t raspi_rtc_close(rt_device_t dev) +{ + bcm283x_i2c_end(0); + return RT_EOK; +} + +static rt_err_t raspi_rtc_control(rt_device_t dev, int cmd, void *args) +{ + + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + *(rt_uint32_t *)args = raspi_get_timestamp(); + break; + case RT_DEVICE_CTRL_RTC_SET_TIME: + raspi_set_timestamp(*(time_t *)args); + break; + default: + return RT_EINVAL; + } + return RT_EOK; +} + +static rt_size_t raspi_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + raspi_rtc_control(dev, RT_DEVICE_CTRL_RTC_GET_TIME, buffer); + return size; +} + +static rt_size_t raspi_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + raspi_rtc_control(dev, RT_DEVICE_CTRL_RTC_SET_TIME, (void *)buffer); + return size; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops raspi_rtc_ops = +{ + .init = raspi_rtc_init, + .open = raspi_rtc_open, + .close = raspi_rtc_close, + .read = raspi_rtc_read, + .write = raspi_rtc_write, + .control = raspi_rtc_control +}; +#endif + +int rt_hw_rtc_init(void) +{ + rt_memset(&rtc_device, 0, sizeof(rtc_device)); + + rtc_device.device.type = RT_Device_Class_RTC; + rtc_device.device.rx_indicate = RT_NULL; + rtc_device.device.tx_complete = RT_NULL; + rtc_device.device.ops = &raspi_rtc_ops; + rtc_device.device.user_data = RT_NULL; + + /* register a rtc device */ + rt_device_register(&rtc_device.device, "rtc", RT_DEVICE_FLAG_RDWR); + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_rtc_init); +#endif /* BSP_USING_RTC */ + diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.h b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..82306068ca4c057dc4d07362a8d6f0f454141375 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#ifndef __DRV_RTC_H__ +#define __DRV_RTC_H__ + +#include +#include +#include +#include "bcm283x.h" + +struct rt_rtc_device +{ + struct rt_device device; +}; + +int rt_hw_rtc_init(void); + +#endif diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.c b/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.c new file mode 100644 index 0000000000000000000000000000000000000000..4f3018c0ef6b6fbddf4fbc639e0078aba51e83af --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.c @@ -0,0 +1,532 @@ +/* + * File : drv_sdio.c + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#include +#include +#include +#include + +#include "drv_sdio.h" +#include "interrupt.h" +#include "drv_gpio.h" + +#include "bcm283x.h" +#include +#include "bcm283x.h" + + +#include + +#ifdef RT_USING_SDIO +#define CONFIG_MMC_USE_DMA +#define DMA_ALIGN (32U) + +typedef struct EMMCCommand +{ + const char* name; + unsigned int code; + unsigned char resp; + unsigned char rca; + int delay; +} EMMCCommand; + +static EMMCCommand sdCommandTable[] = +{ + {"GO_IDLE_STATE", 0x00000000 | CMD_RSPNS_NO , RESP_NO , RCA_NO ,0}, + {"ALL_SEND_CID" , 0x02000000 | CMD_RSPNS_136 , RESP_R2I, RCA_NO ,0}, + {"SEND_REL_ADDR", 0x03000000 | CMD_RSPNS_48 , RESP_R6 , RCA_NO ,0}, + {"SET_DSR" , 0x04000000 | CMD_RSPNS_NO , RESP_NO , RCA_NO ,0}, + {"SWITCH_FUNC" , 0x06000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0}, + {"CARD_SELECT" , 0x07000000 | CMD_RSPNS_48B , RESP_R1b, RCA_YES ,0}, + {"SEND_IF_COND" , 0x08000000 | CMD_RSPNS_48 , RESP_R7 , RCA_NO ,100}, + {"SEND_CSD" , 0x09000000 | CMD_RSPNS_136 , RESP_R2S, RCA_YES ,0}, + {"SEND_CID" , 0x0A000000 | CMD_RSPNS_136 , RESP_R2I, RCA_YES ,0}, + {"VOLT_SWITCH" , 0x0B000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0}, + {"STOP_TRANS" , 0x0C000000 | CMD_RSPNS_48B , RESP_R1b, RCA_NO ,0}, + {"SEND_STATUS" , 0x0D000000 | CMD_RSPNS_48 , RESP_R1 , RCA_YES ,0}, + {"GO_INACTIVE" , 0x0F000000 | CMD_RSPNS_NO , RESP_NO , RCA_YES ,0}, + {"SET_BLOCKLEN" , 0x10000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0}, + {"READ_SINGLE" , 0x11000000 | CMD_RSPNS_48 | CMD_IS_DATA | TM_DAT_DIR_CH, RESP_R1 , RCA_NO ,0}, + {"READ_MULTI" , 0x12000000 | CMD_RSPNS_48 | TM_MULTI_DATA | TM_DAT_DIR_CH, RESP_R1 , RCA_NO ,0}, + {"SEND_TUNING" , 0x13000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0}, + {"SPEED_CLASS" , 0x14000000 | CMD_RSPNS_48B , RESP_R1b, RCA_NO ,0}, + {"SET_BLOCKCNT" , 0x17000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0}, + {"WRITE_SINGLE" , 0x18000000 | CMD_RSPNS_48 | CMD_IS_DATA | TM_DAT_DIR_HC, RESP_R1 , RCA_NO ,0}, + {"WRITE_MULTI" , 0x19000000 | CMD_RSPNS_48 | TM_MULTI_DATA | TM_DAT_DIR_HC, RESP_R1 , RCA_NO ,0}, + {"PROGRAM_CSD" , 0x1B000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0}, + {"SET_WRITE_PR" , 0x1C000000 | CMD_RSPNS_48B , RESP_R1b, RCA_NO ,0}, + {"CLR_WRITE_PR" , 0x1D000000 | CMD_RSPNS_48B , RESP_R1b, RCA_NO ,0}, + {"SND_WRITE_PR" , 0x1E000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0}, + {"ERASE_WR_ST" , 0x20000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0}, + {"ERASE_WR_END" , 0x21000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0}, + {"ERASE" , 0x26000000 | CMD_RSPNS_48B , RESP_R1b, RCA_NO ,0}, + {"LOCK_UNLOCK" , 0x2A000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0}, + {"APP_CMD" , 0x37000000 | CMD_RSPNS_NO , RESP_NO , RCA_NO ,100}, + {"APP_CMD" , 0x37000000 | CMD_RSPNS_48 , RESP_R1 , RCA_YES ,0}, + {"GEN_CMD" , 0x38000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0}, + + // APP commands must be prefixed by an APP_CMD. + {"SET_BUS_WIDTH", 0x06000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0}, + {"SD_STATUS" , 0x0D000000 | CMD_RSPNS_48 , RESP_R1 , RCA_YES ,0}, // RCA??? + {"SEND_NUM_WRBL", 0x16000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0}, + {"SEND_NUM_ERS" , 0x17000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0}, + {"SD_SENDOPCOND", 0x29000000 | CMD_RSPNS_48 , RESP_R3 , RCA_NO ,1000}, + {"SET_CLR_DET" , 0x2A000000 | CMD_RSPNS_48 , RESP_R1 , RCA_NO ,0}, + {"SEND_SCR" , 0x33000000 | CMD_RSPNS_48 | CMD_IS_DATA | TM_DAT_DIR_CH , RESP_R1 , RCA_NO ,0}, +}; + +static rt_err_t sdhci_setwidth(struct sdhci_t * sdhci, rt_uint32_t width); +static rt_err_t sdhci_setclock(struct sdhci_t * sdhci, rt_uint32_t clock); +static rt_err_t sdhci_transfer(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat); + +static inline rt_uint32_t read32(rt_uint32_t addr) +{ + return( *((volatile rt_uint32_t *)(addr)) ); +} + +static inline void write32(rt_uint32_t addr, rt_uint32_t value) +{ + *((volatile rt_uint32_t *)(addr)) = value; +} + +static rt_err_t raspi_transfer_command(struct sdhci_pdata_t * pdat, struct sdhci_cmd_t * cmd) +{ + rt_uint32_t cmdidx; + rt_uint32_t status; + rt_err_t ret = RT_EOK; + + if(read32(pdat->virt + EMMC_STATUS) & SR_CMD_INHIBIT) + write32(pdat->virt + EMMC_CMDTM, 0x0); + + EMMCCommand* cmdtab = &sdCommandTable[cmd->cmdidx]; + + cmdidx = cmdtab->code; + + write32(pdat->virt + EMMC_ARG1, cmd->cmdarg); + write32(pdat->virt + EMMC_CMDTM, cmdidx); + + do { + status = read32(pdat->virt + EMMC_STATUS); + } while(!(status & SR_CMD_INHIBIT)); + + if(cmd->resptype & RESP_MASK) + { + cmd->response[0] = read32(pdat->virt + EMMC_RESP0); + if(cmd->resptype & RESP_R2) + { + cmd->response[1] = read32(pdat->virt + EMMC_RESP1); + cmd->response[2] = read32(pdat->virt + EMMC_RESP2); + cmd->response[3] = read32(pdat->virt + EMMC_RESP3); + } + } + + return ret; +} + +static rt_err_t read_bytes(struct sdhci_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize) +{ + rt_uint32_t * tmp = buf; + rt_uint32_t count = blkcount * blksize; + rt_uint32_t status, err; + +// status = read32(pdat->virt + PL180_STATUS); +// err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_RX_OVERRUN); +// while((!err) && (count >= sizeof(rt_uint32_t))) +// { +// if(status & PL180_STAT_RX_FIFO_AVL) +// { +// *(tmp) = read32(pdat->virt + PL180_FIFO); +// tmp++; +// count -= sizeof(rt_uint32_t); +// } +// status = read32(pdat->virt + PL180_STATUS); +// err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_RX_OVERRUN); +// } +// +// err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_DAT_BLK_END | PL180_STAT_RX_OVERRUN); +// while(!err) +// { +// status = read32(pdat->virt + PL180_STATUS); +// err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_DAT_BLK_END | PL180_STAT_RX_OVERRUN); +// } +// +// if(status & PL180_STAT_DAT_TIME_OUT) +// return -RT_ERROR; +// else if (status & PL180_STAT_DAT_CRC_FAIL) +// return -RT_ERROR; +// else if (status & PL180_STAT_RX_OVERRUN) +// return -RT_ERROR; +// write32(pdat->virt + PL180_CLEAR, 0x1DC007FF); +// +// if(count) +// return -RT_ERROR; + + return RT_EOK; +} + +static rt_err_t write_bytes(struct sdhci_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize) +{ + rt_uint32_t * tmp = buf; + rt_uint32_t count = blkcount * blksize; + rt_uint32_t status, err; + int i; + +// status = read32(pdat->virt + PL180_STATUS); +// err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT); +// while(!err && count) +// { +// if(status & PL180_STAT_TX_FIFO_HALF) +// { +// if(count >= 8 * sizeof(rt_uint32_t)) +// { +// for(i = 0; i < 8; i++) +// write32(pdat->virt + PL180_FIFO, *(tmp + i)); +// tmp += 8; +// count -= 8 * sizeof(rt_uint32_t); +// } +// else +// { +// while(count >= sizeof(rt_uint32_t)) +// { +// write32(pdat->virt + PL180_FIFO, *tmp); +// tmp++; +// count -= sizeof(rt_uint32_t); +// } +// } +// } +// status = read32(pdat->virt + PL180_STATUS); +// err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT); +// } +// +// err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_DAT_BLK_END); +// while(!err) +// { +// status = read32(pdat->virt + PL180_STATUS); +// err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_DAT_BLK_END); +// } +// +// if(status & PL180_STAT_DAT_TIME_OUT) +// return -RT_ERROR; +// else if (status & PL180_STAT_DAT_CRC_FAIL) +// return -RT_ERROR; +// write32(pdat->virt + PL180_CLEAR, 0x1DC007FF); +// +// if(count) +// return -RT_ERROR; + return RT_EOK; +} + +static rt_err_t raspi_transfer_data(struct sdhci_pdata_t * pdat, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat) +{ + rt_uint32_t dlen = (rt_uint32_t)(dat->blkcnt * dat->blksz); + rt_uint32_t blksz_bits = dat->blksz - 1; + rt_err_t ret = -RT_ERROR; + + write32(pdat->virt + EMMC_BLKSIZECNT, dlen); + + if(dat->flag & DATA_DIR_READ) + { + write32(pdat->virt + EMMC_STATUS, SR_READ_TRANSFER); + ret = raspi_transfer_command(pdat, cmd); + if (ret < 0) return ret; + ret = read_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz); + } + else if(dat->flag & DATA_DIR_WRITE) + { + ret = raspi_transfer_command(pdat, cmd); + if (ret < 0) return ret; + write32(pdat->virt + EMMC_STATUS, SR_WRITE_TRANSFER); + ret = write_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz); + } + + return ret; +} + +static void mmc_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + struct sdhci_t *sdhci = (struct sdhci_t *)host->private_data; + struct sdhci_cmd_t cmd; + struct sdhci_cmd_t stop; + struct sdhci_data_t dat; + + rt_memset(&cmd, 0, sizeof(struct sdhci_cmd_t)); + rt_memset(&stop, 0, sizeof(struct sdhci_cmd_t)); + rt_memset(&dat, 0, sizeof(struct sdhci_data_t)); + + cmd.cmdidx = req->cmd->cmd_code; + EMMCCommand* cmdtab = &sdCommandTable[cmd.cmdidx]; + cmd.cmdarg = req->cmd->arg; + cmd.resptype = cmdtab->resp; + + if(req->data) + { + dat.buf = (rt_uint8_t *)req->data->buf; + dat.flag = req->data->flags; + dat.blksz = req->data->blksize; + dat.blkcnt = req->data->blks; + + req->cmd->err = sdhci_transfer(sdhci, &cmd, &dat); + } + else + { + req->cmd->err = sdhci_transfer(sdhci, &cmd, RT_NULL); + } + + req->cmd->resp[3] = cmd.response[3]; + req->cmd->resp[2] = cmd.response[2]; + req->cmd->resp[1] = cmd.response[1]; + req->cmd->resp[0] = cmd.response[0]; + + if (req->stop) + { + stop.cmdidx = req->stop->cmd_code; + cmdtab = &sdCommandTable[cmd.cmdidx]; + stop.cmdarg = req->stop->arg; + cmd.resptype = cmdtab->resp; + + req->stop->err = sdhci_transfer(sdhci, &stop, RT_NULL); + } + + mmcsd_req_complete(host); +} + + +static rt_err_t sdhci_transfer(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat) +{ + struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv; + + if(!dat) + return raspi_transfer_command(pdat, cmd); + + return raspi_transfer_data(pdat, cmd, dat); +} + + +//#ifdef CONFIG_MMC_USE_DMA +//#ifdef BSP_USING_SDIO0 +////ALIGN(32) static rt_uint8_t dma_buffer[64 * 1024]; +//static rt_uint8_t dma_buffer[64 * 1024]; +//#endif +//#endif + + +static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + struct sdhci_t * sdhci = (struct sdhci_t *)host->private_data; + sdhci_setclock(sdhci, io_cfg->clock); + sdhci_setwidth(sdhci, io_cfg->bus_width); +} + +rt_int32_t mmc_card_status(struct rt_mmcsd_host *host) +{ + return 0; +} + +void mmc_enable_irq(struct rt_mmcsd_host *host, rt_int32_t en) +{ + +} + +static rt_err_t sdhci_detect(struct sdhci_t * sdhci) +{ + return RT_EOK; +} + +static rt_err_t sdhci_setwidth(struct sdhci_t * sdhci, rt_uint32_t width) +{ + rt_uint32_t temp = 0; + struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv; + temp = read32((pdat->virt + EMMC_CONTROL0)); + temp |= C0_HCTL_HS_EN; + temp |= C0_HCTL_DWITDH; // always use 4 data lines: + write32((pdat->virt + EMMC_CONTROL0), temp); + + return RT_EOK; +} + +static rt_uint32_t sdhci_getdivider( rt_uint32_t sdHostVer, rt_uint32_t freq ) +{ + rt_uint32_t divisor; + rt_uint32_t closest = 41666666 / freq; + rt_uint32_t shiftcount = __rt_fls(closest - 1); + + + if (shiftcount > 0) shiftcount--; + if (shiftcount > 7) shiftcount = 7; + if (sdHostVer > HOST_SPEC_V2) + divisor = closest; + else + divisor = (1 << shiftcount); + + if (divisor <= 2) { + divisor = 2; + shiftcount = 0; + } + + rt_uint32_t hi = 0; + if (sdHostVer > HOST_SPEC_V2) + hi = (divisor & 0x300) >> 2; + rt_uint32_t lo = (divisor & 0x0ff); + rt_uint32_t cdiv = (lo << 8) + hi; + return cdiv; +} + +static rt_err_t sdhci_setclock(struct sdhci_t * sdhci, rt_uint32_t clock) +{ + rt_uint32_t temp = 0; + rt_uint32_t sdHostVer = 0; + int count = 100000; + struct sdhci_pdata_t * pdat = (struct sdhci_pdata_t *)sdhci->priv; + + temp = read32(pdat->virt + EMMC_STATUS); + while((temp & (SR_CMD_INHIBIT | SR_DAT_INHIBIT))&&(--count)) + bcm283x_clo_delayMicros(1); + + if( count <= 0 ) + { + rt_kprintf("EMMC: Set clock: timeout waiting for inhibit flags. Status %08x.\n", temp); + return RT_ERROR; + } + + // Switch clock off. + temp = read32((pdat->virt + EMMC_CONTROL1)); + temp |= ~C1_CLK_EN; + write32((pdat->virt + EMMC_CONTROL1),temp); + + bcm283x_clo_delayMicros(10); + + // Request the new clock setting and enable the clock + temp = read32(pdat->virt + EMMC_SLOTISR_VER); + sdHostVer = (temp & HOST_SPEC_NUM) >> HOST_SPEC_NUM_SHIFT; + + int cdiv = sdhci_getdivider(sdHostVer, clock); + temp = read32((pdat->virt + EMMC_CONTROL1)); + temp = (temp & 0xffff003f) | cdiv; + write32((pdat->virt + EMMC_CONTROL1),temp); + bcm283x_clo_delayMicros(10); + + // Enable the clock. + temp = read32(pdat->virt + EMMC_CONTROL1); + temp |= C1_CLK_EN; + write32((pdat->virt + EMMC_CONTROL1),temp); + bcm283x_clo_delayMicros(10); + + // Wait for clock to be stable. + count = 10000; + temp = read32(pdat->virt + EMMC_CONTROL1); + while( !(temp & C1_CLK_STABLE) && count-- ) + bcm283x_clo_delayMicros(10); + + if( count <= 0 ) + { + rt_kprintf("EMMC: ERROR: failed to get stable clock.\n"); + return RT_ERROR; + } + + return RT_EOK; +} + +static const struct rt_mmcsd_host_ops ops = +{ + mmc_request_send, + mmc_set_iocfg, + RT_NULL, + RT_NULL, +}; + +static void sdmmc_gpio_init() +{ + int pin; + + for (pin = BCM_GPIO_PIN_48; pin <= BCM_GPIO_PIN_53; pin++) + { + bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_UP); + bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_ALT3); + } + bcm283x_gpio_set_pud(pin, BCM283X_GPIO_PUD_UP); + bcm283x_gpio_fsel(pin, BCM283X_GPIO_FSEL_INPT); +} + +int raspi_sdmmc_init(void) +{ + rt_uint32_t virt; + rt_uint32_t id; + struct rt_mmcsd_host * host = RT_NULL; + struct sdhci_pdata_t * pdat = RT_NULL; + struct sdhci_t * sdhci = RT_NULL; + + rt_kprintf("raspi_sdmmc_init start\n"); + +#ifdef BSP_USING_SDIO0 + host = mmcsd_alloc_host(); + if (!host) + { + rt_kprintf("alloc host failed"); + goto err; + } + + sdhci = rt_malloc(sizeof(struct sdhci_t)); + if (!sdhci) + { + rt_kprintf("alloc sdhci failed"); + goto err; + } + rt_memset(sdhci, 0, sizeof(struct sdhci_t)); + + rt_kprintf(">> sdmmc_gpio_init\n"); + sdmmc_gpio_init(); + rt_kprintf("<< sdmmc_gpio_init\n"); + + virt = MMC0_BASE_ADDR; + + pdat = (struct sdhci_pdata_t *)rt_malloc(sizeof(struct sdhci_pdata_t)); + RT_ASSERT(pdat != RT_NULL); + + pdat->virt = (rt_uint32_t)virt; + + sdhci->name = "sd0"; + sdhci->voltages = VDD_33_34; + sdhci->width = MMCSD_BUSWIDTH_4; + sdhci->clock = 26 * 1000 * 1000; + sdhci->removeable = RT_TRUE; + + sdhci->detect = sdhci_detect; + sdhci->setwidth = sdhci_setwidth; + sdhci->setclock = sdhci_setclock; + sdhci->transfer = sdhci_transfer; + sdhci->priv = pdat; + //write32(pdat->virt + PL180_POWER, 0xbf); + + host->ops = &ops; + host->freq_min = 400000; + host->freq_max = 50000000; + host->valid_ocr = VDD_32_33 | VDD_33_34; + host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4; + host->max_seg_size = 2048; + host->max_dma_segs = 10; + host->max_blk_size = 512; + host->max_blk_count = 4096; + + host->private_data = sdhci; + + mmcsd_change(host); + + return RT_EOK; + +err: + if(host) rt_free(host); + if(sdhci) rt_free(sdhci); + + return -RT_EIO; +#endif +} +INIT_APP_EXPORT(raspi_sdmmc_init); +#endif diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.h b/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.h new file mode 100644 index 0000000000000000000000000000000000000000..8ab10aebb68ee23dbe8b6d8eb160a1643370d3c4 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.h @@ -0,0 +1,345 @@ +/* + * File : drv_sdio.h + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#ifndef __DRV_SDIO_H__ +#define __DRV_SDIO_H__ + +#include + +#define MMC0_BASE_ADDR 0x20300000 + +struct raspi_mmc +{ + volatile rt_uint32_t arg2_reg; /* (0x000) */ + volatile rt_uint32_t blksizecnt_reg; /* (0x004) */ + volatile rt_uint32_t arg1_reg; /* (0x008) */ + volatile rt_uint32_t cmdtm_reg; /* (0x00C) */ + volatile rt_uint32_t resp0_reg; /* (0x010) */ + volatile rt_uint32_t resp1_reg; /* (0x014) */ + volatile rt_uint32_t resp2_reg; /* (0x018) */ + volatile rt_uint32_t resp3_reg; /* (0x01C) */ + volatile rt_uint32_t data_reg; /* (0x020) */ + volatile rt_uint32_t status_reg; /* (0x024) */ + volatile rt_uint32_t control0_reg; /* (0x028) */ + volatile rt_uint32_t control1_reg; /* (0x02C) */ + volatile rt_uint32_t interrupt_reg; /* (0x030) */ + volatile rt_uint32_t irpt_mask_reg; /* (0x034) */ + volatile rt_uint32_t irpt_en_reg; /* (0x038) */ + volatile rt_uint32_t control2_reg; /* (0x03C) */ + volatile rt_uint32_t reserved1[4]; /* (0x040) */ + volatile rt_uint32_t force_irpt_reg; /* (0x050) */ + volatile rt_uint32_t reserved2[7]; /* (0x054) */ + volatile rt_uint32_t boot_timeout_reg; /* (0x070) */ + volatile rt_uint32_t deg_sel_reg; /* (0x074) */ + volatile rt_uint32_t reserved3[2]; /* (0x078) */ + volatile rt_uint32_t exrdfifo_cfg_reg; /* (0x080) */ + volatile rt_uint32_t exrdfifo_cn_reg; /* (0x084) */ + volatile rt_uint32_t tune_step_reg; /* (0x088) */ + volatile rt_uint32_t tune_step_std_reg; /* (0x08C) */ + volatile rt_uint32_t tune_step_ddr_reg; /* (0x090) */ + volatile rt_uint32_t reserved4[23]; /* (0x094) */ + volatile rt_uint32_t spi_int_reg; /* (0x0f0) */ + volatile rt_uint32_t reserved5[2]; /* (0x0f4) */ + volatile rt_uint32_t slotisr_ver_reg; /* (0x0fC) */ +}; + +typedef struct raspi_mmc *raspi_mmc_t; + +#define MMC0 ((tina_mmc_t)MMC0_BASE_ADDR) + + +#define BIT(x) (1<<(x)) + +/* Struct for Intrrrupt Information */ +#define SDXC_CmdDone BIT(0) +#define SDXC_DataDone BIT(1) +#define SDXC_BlockGap BIT(2) +#define SDXC_WriteRdy BIT(4) +#define SDXC_ReadRdy BIT(5) +#define SDXC_Card BIT(8) +#define SDXC_Retune BIT(12) +#define SDXC_BootAck BIT(13) +#define SDXC_EndBoot BIT(14) +#define SDXC_Err BIT(15) +#define SDXC_CTOErr BIT(16) +#define SDXC_CCRCErr BIT(17) +#define SDXC_CENDErr BIT(18) +#define SDXC_CBADErr BIT(19) +#define SDXC_DTOErr BIT(20) +#define SDXC_DCRCErr BIT(21) +#define SDXC_DENDErr BIT(22) +#define SDXC_ACMDErr BIT(24) + + +/* + SD CMD reg +REG[0-5] : Cmd ID +REG[6] : Has response +REG[7] : Long response +REG[8] : Check response CRC +REG[9] : Has data +REG[10] : Write +REG[11] : Steam mode +REG[12] : Auto stop +REG[13] : Wait previous over +REG[14] : About cmd +REG[15] : Send initialization +REG[21] : Update clock +REG[31] : Load cmd +*/ + + +#define SDXC_BLKCNT_EN BIT(1) +#define SDXC_AUTO_CMD12_EN BIT(2) +#define SDXC_AUTO_CMD23_EN BIT(3) +#define SDXC_DAT_DIR BIT(4) //from card to host +#define SDXC_MULTI_BLOCK BIT(5) +#define SDXC_CMD_RSPNS_136 BIT(16) +#define SDXC_CMD_RSPNS_48 BIT(17) +#define SDXC_CMD_RSPNS_48busy BIT(16)|BIT(17) +#define SDXC_CHECK_CRC_CMD BIT(19) +#define SDXC_CMD_IXCHK_EN BIT(20) +#define SDXC_CMD_ISDATA BIT(21) +#define SDXC_CMD_SUSPEND BIT(22) +#define SDXC_CMD_RESUME BIT(23) +#define SDXC_CMD_ABORT BIT(23)|BIT(22) + +//#define SDXC_CHECK_CRC_CMD BIT(19) +// +//#define SDXC_RESPONSE_CMD BIT(6) +//#define SDXC_LONG_RESPONSE_CMD BIT(7) +//#define SDXC_CHECK_CRC_CMD BIT(8) +//#define SDXC_HAS_DATA_CMD BIT(9) +//#define SDXC_WRITE_CMD BIT(10) +//#define SDXC_STEAM_CMD BIT(11) +//#define SDXC_AUTO_STOP_CMD BIT(12) +//#define SDXC_WAIT_OVER_CMD BIT(13) +//#define SDXC_ABOUT_CMD BIT(14) +//#define SDXC_SEND_INIT_CMD BIT(15) +//#define SDXC_UPDATE_CLOCK_CMD BIT(21) +//#define SDXC_LOAD_CMD BIT(31) + +/* + SD status reg +REG[0] : FIFO_RX_LEVEL +REG[1] : FIFO_TX_LEVEL +REG[2] : FIFO_EMPTY +REG[3] : FIFO_FULL +REG[4-7] : FSM_STA +REG[8] : CARD_PRESENT +REG[9] : CARD_BUSY +REG[10] : FSM_BUSY +REG[11-16]: RESP_IDX +REG[17-21]: FIFO_LEVEL +REG[31] : DMA_REQ +*/ + +#define SDXC_CMD_INHIBIT BIT(0) +#define SDXC_DAT_INHIBIT BIT(1) +#define SDXC_DAT_ACTIVE BIT(2) +#define SDXC_WRITE_TRANSFER BIT(8) +#define SDXC_READ_TRANSFER BIT(9) + +// +// +//#define SDXC_FIFO_RX_LEVEL BIT(0) +//#define SDXC_FIFO_TX_LEVEL BIT(1) +//#define SDXC_FIFO_EMPTY BIT(2) +//#define SDXC_FIFO_FULL BIT(3) +//#define SDXC_CARD_PRESENT BIT(8) +//#define SDXC_CARD_BUSY BIT(9) +//#define SDXC_FSM_BUSY BIT(10) +//#define SDXC_DMA_REQ BIT(31) + +struct mmc_des_v4p1 +{ + rt_uint32_t : 1, + dic : 1, /* disable interrupt on completion */ + last_des : 1, /* 1-this data buffer is the last buffer */ + first_des : 1, /* 1-data buffer is the first buffer,0-data buffer contained in the next descriptor is 1st buffer */ + des_chain : 1, /* 1-the 2nd address in the descriptor is the next descriptor address */ + end_of_ring : 1, /* 1-last descriptor flag when using dual data buffer in descriptor */ + : 24, + card_err_sum : 1, /* transfer error flag */ + own : 1; /* des owner:1-idma owns it, 0-host owns it */ + +#define SDXC_DES_NUM_SHIFT 12 /* smhc2!! */ +#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT) + rt_uint32_t data_buf1_sz : 16, + data_buf2_sz : 16; + rt_uint32_t buf_addr_ptr1; + rt_uint32_t buf_addr_ptr2; +}; + +struct sdhci_cmd_t +{ + rt_uint32_t cmdidx; + rt_uint32_t cmdarg; + //const char* name; + // rt_uint32_t code; + rt_uint32_t resptype; + // rt_uint8_t rca; + // rt_uint32_t delay; + rt_uint32_t response[4]; +}; + +struct sdhci_data_t +{ + rt_uint8_t * buf; + rt_uint32_t flag; + rt_uint32_t blksz; + rt_uint32_t blkcnt; +}; + +struct sdhci_t +{ + char * name; + rt_uint32_t voltages; + rt_uint32_t width; + rt_uint32_t clock; + rt_err_t removeable; + void * sdcard; + + rt_err_t (*detect)(struct sdhci_t * sdhci); + rt_err_t (*setwidth)(struct sdhci_t * sdhci, rt_uint32_t width); + rt_err_t (*setclock)(struct sdhci_t * sdhci, rt_uint32_t clock); + rt_err_t (*transfer)(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat); + void * priv; +}; + +struct sdhci_pdata_t +{ + rt_uint32_t virt; +}; + +// EMMC command flags +#define CMD_TYPE_NORMAL 0x00000000 +#define CMD_TYPE_SUSPEND 0x00400000 +#define CMD_TYPE_RESUME 0x00800000 +#define CMD_TYPE_ABORT 0x00c00000 +#define CMD_IS_DATA 0x00200000 +#define CMD_IXCHK_EN 0x00100000 +#define CMD_CRCCHK_EN 0x00080000 +#define CMD_RSPNS_NO 0x00000000 +#define CMD_RSPNS_136 0x00010000 +#define CMD_RSPNS_48 0x00020000 +#define CMD_RSPNS_48B 0x00030000 +#define TM_MULTI_BLOCK 0x00000020 +#define TM_DAT_DIR_HC 0x00000000 +#define TM_DAT_DIR_CH 0x00000010 +#define TM_AUTO_CMD23 0x00000008 +#define TM_AUTO_CMD12 0x00000004 +#define TM_BLKCNT_EN 0x00000002 +#define TM_MULTI_DATA (CMD_IS_DATA|TM_MULTI_BLOCK|TM_BLKCNT_EN) + +// Response types. +// Note that on the PI, the index and CRC are dropped, leaving 32 bits in RESP0. +#define RESP_NO 0 // No response +//#define RESP_R1 1 // 48 RESP0 contains card status +#define RESP_R1b 11 // 48 RESP0 contains card status, data line indicates busy +#define RESP_R2I 2 // 136 RESP0..3 contains 128 bit CID shifted down by 8 bits as no CRC +#define RESP_R2S 12 // 136 RESP0..3 contains 128 bit CSD shifted down by 8 bits as no CRC +//#define RESP_R3 3 // 48 RESP0 contains OCR register +//#define RESP_R6 6 // 48 RESP0 contains RCA and status bits 23,22,19,12:0 +//#define RESP_R7 7 // 48 RESP0 contains voltage acceptance and check pattern + +#define RCA_NO 1 +#define RCA_YES 2 + +// INTERRUPT register settings +#define INT_AUTO_ERROR 0x01000000 +#define INT_DATA_END_ERR 0x00400000 +#define INT_DATA_CRC_ERR 0x00200000 +#define INT_DATA_TIMEOUT 0x00100000 +#define INT_INDEX_ERROR 0x00080000 +#define INT_END_ERROR 0x00040000 +#define INT_CRC_ERROR 0x00020000 +#define INT_CMD_TIMEOUT 0x00010000 +#define INT_ERR 0x00008000 +#define INT_ENDBOOT 0x00004000 +#define INT_BOOTACK 0x00002000 +#define INT_RETUNE 0x00001000 +#define INT_CARD 0x00000100 +#define INT_READ_RDY 0x00000020 +#define INT_WRITE_RDY 0x00000010 +#define INT_BLOCK_GAP 0x00000004 +#define INT_DATA_DONE 0x00000002 +#define INT_CMD_DONE 0x00000001 +#define INT_ERROR_MASK (INT_CRC_ERROR|INT_END_ERROR|INT_INDEX_ERROR| \ + INT_DATA_TIMEOUT|INT_DATA_CRC_ERR|INT_DATA_END_ERR| \ + INT_ERR|INT_AUTO_ERROR) +#define INT_ALL_MASK (INT_CMD_DONE|INT_DATA_DONE|INT_READ_RDY|INT_WRITE_RDY|INT_ERROR_MASK) + +#define EMMC_ARG2 (0x00) +#define EMMC_BLKSIZECNT (0x04) +#define EMMC_ARG1 (0x08) +#define EMMC_CMDTM (0x0c) +#define EMMC_RESP0 (0x10) +#define EMMC_RESP1 (0x14) +#define EMMC_RESP2 (0x18) +#define EMMC_RESP3 (0x1c) +#define EMMC_DATA (0x20) +#define EMMC_STATUS (0x24) +#define EMMC_CONTROL0 (0x28) +#define EMMC_CONTROL1 (0x2c) +#define EMMC_INTERRUPT (0x30) +#define EMMC_IRPT_MASK (0x34) +#define EMMC_IRPT_EN (0x38) +#define EMMC_CONTROL2 (0x3c) +#define EMMC_BOOT_TIMEOUT (0x70) +#define EMMC_EXRDFIFO_EN (0x84) +#define EMMC_SPI_INT_SPT (0xf0) +#define EMMC_SLOTISR_VER (0xfc) + +// CONTROL register settings +#define C0_SPI_MODE_EN 0x00100000 +#define C0_HCTL_HS_EN 0x00000004 +#define C0_HCTL_DWITDH 0x00000002 + +#define C1_SRST_DATA 0x04000000 +#define C1_SRST_CMD 0x02000000 +#define C1_SRST_HC 0x01000000 +#define C1_TOUNIT_DIS 0x000f0000 +#define C1_TOUNIT_MAX 0x000e0000 +#define C1_CLK_GENSEL 0x00000020 +#define C1_CLK_EN 0x00000004 +#define C1_CLK_STABLE 0x00000002 +#define C1_CLK_INTLEN 0x00000001 + +#define FREQ_SETUP 400000 // 400 Khz +#define FREQ_NORMAL 25000000 // 25 Mhz + +// SLOTISR_VER values +#define HOST_SPEC_NUM 0x00ff0000 +#define HOST_SPEC_NUM_SHIFT 16 +#define HOST_SPEC_V3 2 +#define HOST_SPEC_V2 1 +#define HOST_SPEC_V1 0 + +// STATUS register settings +#define SR_DAT_LEVEL1 0x1e000000 +#define SR_CMD_LEVEL 0x01000000 +#define SR_DAT_LEVEL0 0x00f00000 +#define SR_DAT3 0x00800000 +#define SR_DAT2 0x00400000 +#define SR_DAT1 0x00200000 +#define SR_DAT0 0x00100000 +#define SR_WRITE_PROT 0x00080000 // From SDHC spec v2, BCM says reserved +#define SR_READ_AVAILABLE 0x00000800 // ???? undocumented +#define SR_WRITE_AVAILABLE 0x00000400 // ???? undocumented +#define SR_READ_TRANSFER 0x00000200 +#define SR_WRITE_TRANSFER 0x00000100 +#define SR_DAT_ACTIVE 0x00000004 +#define SR_DAT_INHIBIT 0x00000002 +#define SR_CMD_INHIBIT 0x00000001 + + +#endif diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_spi.c b/bsp/raspberry-pi/raspi3-64/driver/drv_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..70d2096277677abdba283637234950a7f6ca2ee3 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_spi.c @@ -0,0 +1,452 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#include "drv_spi.h" + +#if !defined(BSP_USING_SPI0) && !defined(BSP_USING_SPI1) +#ifdef RT_USING_SPI +#undef RT_USING_SPI +#endif +#endif + +#ifdef RT_USING_SPI + +struct rpi_pin_index +{ + rt_uint8_t phy_id; + rt_uint8_t bcm_id; + rt_uint8_t signal_name; + rt_uint8_t magic; +}; + +//raspi phy id and bcm id +static struct rpi_pin_index phypin_index[] = +{ + {0, 0, 0, 0}, + {1, 0, 0, 0}, + {2, 0, 0, 0}, + {3, BCM_GPIO_PIN_2, RPI_SDA1, PIN_MAGIC}, + {4, 0, 0, 0}, + {5, BCM_GPIO_PIN_3, RPI_SCL1, PIN_MAGIC}, + {6, 0, 0, 0}, + {7, BCM_GPIO_PIN_4, RPI_GPIO_GCLK, PIN_MAGIC}, + {8, BCM_GPIO_PIN_14, RPI_TXD0, PIN_MAGIC}, + {9, 0, 0, 0}, + {10, BCM_GPIO_PIN_15, RPI_RXD0, PIN_MAGIC}, + {11, BCM_GPIO_PIN_17, RPI_GPIO_GEN0, PIN_MAGIC}, + {12, BCM_GPIO_PIN_18, RPI_GPIO_GEN1, PIN_MAGIC}, + {13, BCM_GPIO_PIN_27, RPI_GPIO_GEN2, PIN_MAGIC}, + {14, 0, 0, 0}, + {15, BCM_GPIO_PIN_22, RPI_GPIO_GEN3, PIN_MAGIC}, + {16, BCM_GPIO_PIN_23, RPI_GPIO_GEN4, PIN_MAGIC}, + {17, 0, 0, 0}, + {18, BCM_GPIO_PIN_24, RPI_GPIO_GEN5, PIN_MAGIC}, + {19, BCM_GPIO_PIN_10, RPI_SPI_MOSI, PIN_MAGIC}, + {20, 0, 0, 0}, + {21, BCM_GPIO_PIN_9, RPI_SPI_MISO, PIN_MAGIC}, + {22, BCM_GPIO_PIN_25, RPI_GPIO_GEN6, PIN_MAGIC}, + {23, BCM_GPIO_PIN_11, RPI_SPI_SCLK, PIN_MAGIC}, + {24, BCM_GPIO_PIN_8, RPI_SPI_CE0_N, PIN_MAGIC}, + {25, 0, 0, 0}, + {26, BCM_GPIO_PIN_7, RPI_SPI_CE1_N, PIN_MAGIC}, + {27, BCM_GPIO_PIN_0, RPI_SDA0, PIN_MAGIC}, + {28, BCM_GPIO_PIN_1, RPI_SCL0, PIN_MAGIC}, + {29, BCM_GPIO_PIN_5, RPI_CAM_CLK, PIN_MAGIC}, + {30, 0, 0, 0}, + {31, BCM_GPIO_PIN_6, RPI_LAN_RUN, PIN_MAGIC}, + {32, BCM_GPIO_PIN_12, 0, PIN_MAGIC}, + {33, BCM_GPIO_PIN_13, 0, PIN_MAGIC}, + {34, 0, 0, 0}, + {35, BCM_GPIO_PIN_19, 0, PIN_MAGIC}, + {36, BCM_GPIO_PIN_16, RPI_STATUS_LED_N, PIN_MAGIC}, + {37, BCM_GPIO_PIN_26, 0, PIN_MAGIC}, + {38, BCM_GPIO_PIN_20, 0, PIN_MAGIC}, + {39, 0, 0, 0}, + {40, BCM_GPIO_PIN_21, RPI_CAM_GPIO, PIN_MAGIC}, +}; + + +static rt_uint8_t bcm2835_spi_bit_order = BCM283X_SPI_BIT_ORDER_MSBFIRST; +static rt_uint8_t bcm2835_byte_reverse_table[] = +{ + 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, + 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, + 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, + 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8, + 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, + 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, + 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, + 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc, + 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2, + 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, + 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, + 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, + 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6, + 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6, + 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, + 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, + 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, + 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1, + 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9, + 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, + 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, + 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, + 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed, + 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd, + 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, + 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, + 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, + 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb, + 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7, + 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, + 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, + 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff +}; + +#define BSP_SPI_MAX_HZ (30* 1000 *1000) +#define SPITIMEOUT 0x0FFF + +struct rt_spi_hw_config +{ + rt_int8_t sclk_pin; + rt_int8_t sclk_mode; + rt_int8_t mosi_pin; + rt_int8_t mosi_mode; + rt_int8_t miso_pin; + rt_int8_t miso_mode; + rt_int8_t cs_pin; + rt_int8_t cs_mode; + rt_uint32_t spi_base; + rt_uint32_t clk_div; +}; + +struct rt_sw_spi_cs +{ + rt_uint32_t pin; +}; + +struct rt_spi +{ + char *device_name; + struct rt_spi_bus *spi_bus; + struct rt_spi_hw_config *hwcfg; + struct rt_spi_configuration *cfg; +}; + +static rt_err_t raspi_hostspi_init(struct rt_spi_configuration *cfg) +{ + + volatile rt_uint32_t addr = (PER_BASE + BCM283X_SPI0_BASE) + BCM283X_SPI0_CS; + //volatile rt_uint32_t fifo = (PER_BASE + BCM283X_SPI0_BASE) + BCM283X_SPI0_FIFO; + + // spi clear fifo + bcm283x_peri_set_bits(addr, BCM283X_SPI0_CS_CLEAR, BCM283X_SPI0_CS_CLEAR); + + // /* Set TA = 1 */ + // bcm2835_peri_set_bits(addr, BCM283X_SPI0_CS_TA, BCM283X_SPI0_CS_TA); + + /* Mask in the CPO and CPHA bits of CS */ + + bcm283x_peri_set_bits(addr, (rt_uint32_t)(cfg->mode << 2), BCM283X_SPI0_CS_CPOL | BCM283X_SPI0_CS_CPHA); + + //chipSelect + bcm283x_peri_set_bits(addr, BCM283X_SPI_CS0, BCM283X_SPI0_CS_CS); + + rt_uint8_t shift = 21 + BCM283X_SPI_CS0; + /* Mask in the appropriate CSPOLn bit */ + bcm283x_peri_set_bits(addr, LOW << shift, 1 << shift); + + + if(cfg->max_hz > BSP_SPI_MAX_HZ) + { + cfg->max_hz = BSP_SPI_MAX_HZ; + } + + volatile rt_uint32_t clk_addr = (PER_BASE + BCM283X_SPI0_BASE) + BCM283X_SPI0_CLK; + bcm283x_peri_write(clk_addr, cfg->max_hz); + + return RT_EOK; +} + +static rt_err_t raspi_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) +{ + RT_ASSERT(cfg != RT_NULL); + RT_ASSERT(device != RT_NULL); + + struct rt_spi *hspi = (struct rt_spi *)&device->bus->parent; + hspi->cfg = cfg; + + raspi_hostspi_init(cfg); + + return RT_EOK; +} + + +rt_uint8_t correct_order(rt_uint8_t b) +{ + if (bcm2835_spi_bit_order == BCM283X_SPI_BIT_ORDER_LSBFIRST) + return bcm2835_byte_reverse_table[b]; + else + return b; +} + +static rt_err_t spi_transfernb(rt_uint8_t* tbuf, rt_uint8_t* rbuf, rt_uint32_t len) +{ + volatile rt_uint32_t paddr = SPI0_BASE_ADDR + BCM283X_SPI0_CS; + volatile rt_uint32_t fifo = SPI0_BASE_ADDR + BCM283X_SPI0_FIFO; + rt_uint32_t TXCnt=0; + rt_uint32_t RXCnt=0; + + /* Clear TX and RX fifos */ + bcm283x_peri_set_bits(paddr, BCM283X_SPI0_CS_CLEAR, BCM283X_SPI0_CS_CLEAR); + + /* Set TA = 1 */ + bcm283x_peri_set_bits(paddr, BCM283X_SPI0_CS_TA, BCM283X_SPI0_CS_TA); + + /* Use the FIFO's to reduce the interbyte times */ + while ((TXCnt < len) || (RXCnt < len)) + { + /* TX fifo not full, so add some more bytes */ + while (((bcm283x_peri_read(paddr) & BCM283X_SPI0_CS_TXD)) && (TXCnt < len)) + { + bcm283x_peri_write_nb(fifo, correct_order(tbuf[TXCnt])); + TXCnt++; + } + /* Rx fifo not empty, so get the next received bytes */ + while (((bcm283x_peri_read(paddr) & BCM283X_SPI0_CS_RXD)) && (RXCnt < len)) + { + rbuf[RXCnt] = correct_order(bcm283x_peri_read_nb(fifo)); + RXCnt++; + } + } + /* Wait for DONE to be set */ + while (!(bcm283x_peri_read_nb(paddr) & BCM283X_SPI0_CS_DONE)); + + /* Set TA = 0, and also set the barrier */ + bcm283x_peri_set_bits(paddr, 0, BCM283X_SPI0_CS_TA); + return RT_EOK; + +} + +static rt_uint32_t raspi_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + rt_err_t res; + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL); + + struct rt_spi *hspi = (struct rt_spi *)&device->bus->parent; + /* only send data */ + if (message->recv_buf == RT_NULL) + { + if (message->cs_take) + { + bcm283x_gpio_write(hspi->hwcfg->cs_pin, 0); + } + res = spi_transfernb((rt_uint8_t *)message->send_buf, RT_NULL,(rt_int32_t)message->length); + if (message->cs_release) + { + bcm283x_gpio_write(hspi->hwcfg->cs_pin, 1); + + } + if (res != RT_EOK) + return RT_ERROR; + } + + /* only receive data */ + if (message->send_buf == RT_NULL) + { + if (message->cs_take) + { + bcm283x_gpio_write(hspi->hwcfg->cs_pin, 0); + } + res = spi_transfernb(RT_NULL,(rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length); + if (message->cs_release) + { + bcm283x_gpio_write(hspi->hwcfg->cs_pin, 1); + } + if (res != RT_EOK) + return RT_ERROR; + } + /* send & receive */ + else + { + if (message->cs_take) + { + bcm283x_gpio_write(hspi->hwcfg->cs_pin, 0); + } + res = spi_transfernb((rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf, + (rt_int32_t)message->length); + if (message->cs_release) + { + bcm283x_gpio_write(hspi->hwcfg->cs_pin, 1); + } + if (res != RT_EOK) + return RT_ERROR; + } + + return message->length; +} + +rt_err_t raspi_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin) +{ + rt_err_t ret; + rt_int16_t gpio_pin; + struct rt_spi_device *spi_device; + struct rt_sw_spi_cs *cs_pin; + + gpio_pin = phypin_index[pin].bcm_id; + + spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + + cs_pin = (struct rt_sw_spi_cs *)rt_malloc(sizeof(struct rt_sw_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + + cs_pin->pin = gpio_pin; + + ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + return ret; +} + +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) +rt_uint16_t spi_clockdivider(rt_uint32_t speed_hz) +{ + rt_uint16_t divider; + + if (speed_hz < (rt_uint32_t) BCM283X_AUX_SPI_CLOCK_MIN) + { + speed_hz = (rt_uint32_t) BCM283X_AUX_SPI_CLOCK_MIN; + } + else if (speed_hz > (rt_uint32_t) BCM283X_AUX_SPI_CLOCK_MAX) + { + speed_hz = (rt_uint32_t) BCM283X_AUX_SPI_CLOCK_MAX; + } + + divider = (rt_uint16_t) DIV_ROUND_UP(BCM283X_CORE_CLK_HZ, 2 * speed_hz) - 1; + + if (divider > (rt_uint16_t) BCM283X_AUX_SPI_CNTL0_SPEED_MAX) + { + return (rt_uint16_t) BCM283X_AUX_SPI_CNTL0_SPEED_MAX; + } + + return divider; +} + +rt_err_t raspi_spi_hw_init(struct rt_spi_hw_config *hwcfg) +{ + volatile rt_uint32_t enable = PER_BASE + BCM283X_AUX_BASE + BCM283X_AUX_ENABLE; + volatile rt_uint32_t cntl0 = PER_BASE + BCM283X_SPI1_BASE + BCM283X_AUX_SPI_CNTL0; + volatile rt_uint32_t cntl1 = PER_BASE + BCM283X_SPI1_BASE + BCM283X_AUX_SPI_CNTL1; + + bcm283x_gpio_fsel(hwcfg->sclk_pin, hwcfg->sclk_mode); + bcm283x_gpio_fsel(hwcfg->miso_pin, hwcfg->miso_mode); + bcm283x_gpio_fsel(hwcfg->mosi_pin, hwcfg->mosi_mode); + bcm283x_gpio_fsel(hwcfg->cs_pin, hwcfg->cs_mode); + + hwcfg->clk_div = spi_clockdivider(1000000); // Default 1MHz SPI + + bcm283x_peri_write(enable, BCM283X_AUX_ENABLE_SPI0); + bcm283x_peri_write(cntl1, 0); + bcm283x_peri_write(cntl0, BCM283X_AUX_SPI_CNTL0_CLEARFIFO); + + return RT_EOK; +} + +const static struct rt_spi_ops raspi_spi_ops = +{ + .configure = raspi_spi_configure, + .xfer = raspi_spi_xfer +}; + +#if defined (BSP_USING_SPI0) +#define SPI0BUS_NAME "spi0.0" + +struct rt_spi spi0; +struct rt_spi_bus raspi_spi0_bus = +{ + .ops = &raspi_spi_ops, + .parent.user_data = &spi0 +}; + +struct rt_spi_hw_config raspi_spi0_hw = +{ + .sclk_pin = BCM_GPIO_PIN_11, + .sclk_mode = BCM283X_GPIO_FSEL_ALT0, + .mosi_pin = BCM_GPIO_PIN_10, + .mosi_mode = BCM283X_GPIO_FSEL_ALT0, + .miso_pin = BCM_GPIO_PIN_9, + .miso_mode = BCM283X_GPIO_FSEL_ALT0, + .cs_pin = BCM_GPIO_PIN_8, + .cs_mode = BCM283X_GPIO_FSEL_ALT0, + .spi_base = (PER_BASE + BCM283X_SPI0_BASE), + .clk_div = 0, +}; + +struct rt_spi spi0 = +{ + .device_name = SPI0BUS_NAME, + .spi_bus = &raspi_spi0_bus, + .hwcfg = &raspi_spi0_hw, +}; + +#endif + +#if defined (BSP_USING_SPI1) +#define SPI1BUS_NAME "spi0.1" + +struct rt_spi spi1; +struct rt_spi_bus raspi_spi1_bus = +{ + .ops = &raspi_spi_ops, + .parent.user_data = &spi1 +}; + +struct rt_spi_hw_config raspi_spi1_hw = +{ + .sclk_pin = BCM_GPIO_PIN_11, + .sclk_mode = BCM283X_GPIO_FSEL_ALT0, + .mosi_pin = BCM_GPIO_PIN_10, + .mosi_mode = BCM283X_GPIO_FSEL_ALT0, + .miso_pin = BCM_GPIO_PIN_9, + .miso_mode = BCM283X_GPIO_FSEL_ALT0, + .cs_pin = BCM_GPIO_PIN_7, + .cs_mode = BCM283X_GPIO_FSEL_ALT0, + .spi_base = (PER_BASE + BCM283X_SPI0_BASE), + .clk_div = 0, +}; + +struct rt_spi spi1 = +{ + .device_name = SPI1BUS_NAME, + .spi_bus = &raspi_spi1_bus, + .hwcfg = &raspi_spi1_hw, +}; +#endif + +int rt_hw_spi_bus_init(void) +{ +#if defined (BSP_USING_SPI0) + raspi_spi_hw_init(spi0.hwcfg); + rt_spi_bus_register(spi0.spi_bus, spi0.device_name, spi0.spi_bus->ops); +#endif + +#if defined (BSP_USING_SPI1) + raspi_spi_hw_init(spi1.hwcfg); + rt_spi_bus_register(spi1.spi_bus, spi1.device_name, spi1.spi_bus->ops); +#endif + + return RT_EOK; +} +INIT_PREV_EXPORT(rt_hw_spi_bus_init); + +#endif diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_spi.h b/bsp/raspberry-pi/raspi3-64/driver/drv_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..c4883758e584ee5ddb2a5bc848a74b67b1a13dbf --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_spi.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include +#include + +#include "bcm283x.h" +#include +#include +#include "raspi.h" + +#define SPI0_BASE_ADDR (PER_BASE + BCM283X_SPI0_BASE) + +#define SPI_CORE_CLK 250000000U +#define SPI_CS 0x00 +#define SPI_CS_LEN_LONG (1 << 25) +#define SPI_CS_DMA_LEN (1 << 24) +#define SPI_CS_CSPOL2 (1 << 23) +#define SPI_CS_CSPOL1 (1 << 22) +#define SPI_CS_CSPOL0 (1 << 21) +#define SPI_CS_RXF (1 << 20) +#define SPI_CS_RXR (1 << 19) +#define SPI_CS_TXD (1 << 18) +#define SPI_CS_RXD (1 << 17) +#define SPI_CS_DONE (1 << 16) +#define SPI_CS_LEN (1 << 13) +#define SPI_CS_REN (1 << 12) +#define SPI_CS_ADCS (1 << 11) +#define SPI_CS_INTR (1 << 10) +#define SPI_CS_INTD (1 << 9) +#define SPI_CS_DMAEN (1 << 8) +#define SPI_CS_TA (1 << 7) +#define SPI_CS_CSPOL (1 << 6) +#define SPI_CS_CLEAR_RXFIFO (1 << 5) +#define SPI_CS_CLEAR_TXFIFO (1 << 4) +#define SPI_CS_CPOL (1 << 3) +#define SPI_CS_CPHA (1 << 2) +#define SPI_CS_MASK 0x3 +#define SPI_FIFO 0x04 +#define SPI_CLK 0x08 +#define SPI_CLK_MASK 0xffff +#define SPI_DLEN 0x0c +#define SPI_DLEN_MASK 0xffff +#define SPI_LTOH 0x10 +#define SPI_LTOH_MASK 0xf +#define SPI_DC 0x14 +#define SPI_DC_RPANIC_SHIFT 24 +#define SPI_DC_RPANIC_MASK (0xff << SPI_DC_RPANIC_SHIFT) +#define SPI_DC_RDREQ_SHIFT 16 +#define SPI_DC_RDREQ_MASK (0xff << SPI_DC_RDREQ_SHIFT) +#define SPI_DC_TPANIC_SHIFT 8 +#define SPI_DC_TPANIC_MASK (0xff << SPI_DC_TPANIC_SHIFT) +#define SPI_DC_TDREQ_SHIFT 0 +#define SPI_DC_TDREQ_MASK 0xff + +int rt_hw_spi_bus_init(void); + +#endif diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..0ead0fdf742221ff2703379c059420530c34442f --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#include +#include +#include "bcm283x.h" +#include "drv_timer.h" +#include +#include "cp15.h" + +static void rt_systimer_init(rt_hwtimer_t *hwtimer, rt_uint32_t state) +{ + if (state == 0) + hwtimer->ops->stop(hwtimer); +} + +static rt_err_t rt_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +{ + rt_err_t result = RT_EOK; + rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data; + int timer_id = timer->timer_id; + if (mode == HWTIMER_MODE_PERIOD) + timer->cnt = cnt; + else + timer->cnt = 0; + __DSB(); + if (timer_id == 1) + { + rt_hw_interrupt_umask(IRQ_SYSTIMER_MATCH_1); + STIMER_C1 = STIMER_CLO + cnt; + } + else if (timer_id == 3) + { + rt_hw_interrupt_umask(IRQ_SYSTIMER_MATCH_3); + STIMER_C3 = STIMER_CLO + cnt; + } + else + result = -RT_ERROR; + __DSB(); + + return result; +} + +static void rt_systimer_stop(rt_hwtimer_t *hwtimer) +{ + rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data; + int timer_id = timer->timer_id; + if (timer_id == 1) + rt_hw_interrupt_mask(IRQ_SYSTIMER_MATCH_1); + else if (timer_id == 3) + rt_hw_interrupt_mask(IRQ_SYSTIMER_MATCH_3); + +} + +static rt_err_t rt_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) +{ + /* The frequency value is an immutable value. */ + if (cmd == HWTIMER_CTRL_FREQ_SET) + { + return RT_EOK; + } + else + { + return -RT_ENOSYS; + } +} + +const static struct rt_hwtimer_ops systimer_ops = +{ + rt_systimer_init, + rt_systimer_start, + rt_systimer_stop, + RT_NULL, + rt_systimer_ctrl +}; + +void rt_device_systimer_isr(int vector, void *param) +{ + rt_hwtimer_t *hwtimer = (rt_hwtimer_t *) param; + rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data; + RT_ASSERT(timer != RT_NULL); + int timer_id = timer->timer_id; + + __DSB(); + if (timer_id == 1) + { + STIMER_CS = 0x2; + STIMER_C1 = STIMER_CLO + timer->cnt; + } + else if (timer_id == 3) + { + STIMER_CS = 0x8; + STIMER_C3 = STIMER_CLO + timer->cnt; + } + + __DSB(); + rt_device_hwtimer_isr(hwtimer); +} + +static struct rt_hwtimer_device _hwtimer1; +static struct rt_hwtimer_device _hwtimer3; +static struct rt_systimer_device _systimer1; +static struct rt_systimer_device _systimer3; + +static const struct rt_hwtimer_info _info = +{ + 1000000, /* the maxinum count frequency can be set */ + 1000000, /* the maxinum count frequency can be set */ + 0xFFFFFFFF, /* the maximum counter value */ + HWTIMER_CNTMODE_UP /* count mode (inc/dec) */ +}; + +int rt_hw_systimer_init(void) +{ +#ifdef RT_USING_SYSTIMER1 + _systimer1.timer_id =1; + _hwtimer1.ops = &systimer_ops; + _hwtimer1.info = &_info; + rt_device_hwtimer_register(&_hwtimer1, "timer1",&_systimer1); + rt_hw_interrupt_install(IRQ_SYSTIMER_MATCH_1, rt_device_systimer_isr, &_hwtimer1, "systimer1"); + rt_hw_interrupt_umask(IRQ_SYSTIMER_MATCH_1); +#endif + +#ifdef RT_USING_SYSTIMER3 + _systimer3.timer_id =3; + _hwtimer3.ops = &systimer_ops; + _hwtimer3.info = &_info; + rt_device_hwtimer_register(&_hwtimer3, "timer3",&_systimer3); + rt_hw_interrupt_install(IRQ_SYSTIMER_MATCH_3, rt_device_systimer_isr, &_hwtimer3, "systimer3"); + +#endif + + return 0; +} diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_timer.h b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..c18e3d893c4d6d7ed3e75c5cb58fe6f8eb8a28e7 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ +#ifndef __DRV_TIMER_H__ +#define __DRV_TIMER_H__ + +#include +#include + +typedef struct rt_systimer_device +{ + int timer_id; + rt_uint32_t cnt; +} rt_systimer_t; + +int rt_hw_systimer_init(void); + +#endif diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..fd8ec66af9536a1027df4aa92ec9b6c7222a93b8 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/5/5 Bernard The first version + */ + +#include +#include +#include + +#include "board.h" +#include "drv_uart.h" + +#include + +#define AUX_BASE (0x3F000000 + 0x215000) + +struct hw_uart_device +{ + rt_ubase_t hw_base; + rt_uint32_t irqno; +}; + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + if (uart->hw_base == AUX_BASE) + { + rt_uint32_t value; + + /* GPIO function set */ + value = GPIO_GPFSEL1; + value &= ~(7<<12); /* GPIO14 */ + value |= 2<<12 ; /* ALT5 */ + value &= ~(7<<15); /* GPIO15 */ + value |= 2<<15 ; /* ALT5 */ + GPIO_GPFSEL1 = value; + + /* PullUD disable */ + GPIO_GPPUD = 0; + GPIO_GPPUDCLK0 = (1 << 14) | (1 << 15); + GPIO_GPPUDCLK0 = 0; + + AUX_ENABLES(uart->hw_base) = 1; /* Enable UART1 */ + AUX_MU_IER_REG(uart->hw_base) = 0; /* Disable interrupt */ + AUX_MU_CNTL_REG(uart->hw_base) = 0; /* Disable Transmitter and Receiver */ + AUX_MU_LCR_REG(uart->hw_base) = 3; /* Works in 8-bit mode */ + AUX_MU_MCR_REG(uart->hw_base) = 0; /* Disable RTS */ + AUX_MU_IIR_REG(uart->hw_base) = 0xC6; /* Enable FIFO, Clear FIFO */ + AUX_MU_BAUD_REG(uart->hw_base) = 270; /* 115200 = system clock 250MHz / (8 * (baud + 1)), baud = 270 */ + AUX_MU_CNTL_REG(uart->hw_base) = 3; /* Enable Transmitter and Receiver */ + } + + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + AUX_MU_IER_REG(uart->hw_base) = 0x0; + rt_hw_interrupt_mask(uart->irqno); + break; + + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + AUX_MU_IER_REG(uart->hw_base) = 0x1; + rt_hw_interrupt_umask(uart->irqno); + break; + } + + return RT_EOK; +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + while (!(AUX_MU_LSR_REG(uart->hw_base) & 0x20)); + AUX_MU_IO_REG(uart->hw_base) = c; + + return 1; +} + +static int uart_getc(struct rt_serial_device *serial) +{ + int ch = -1; + struct hw_uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct hw_uart_device *)serial->parent.user_data; + + if ((AUX_MU_LSR_REG(uart->hw_base) & 0x01)) + { + ch = AUX_MU_IO_REG(uart->hw_base) & 0xff; + } + + return ch; +} + +static const struct rt_uart_ops _uart_ops = +{ + uart_configure, + uart_control, + uart_putc, + uart_getc, +}; + +static void rt_hw_uart_isr(int irqno, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device*)param; + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); +} + +#ifdef RT_USING_UART0 +/* UART device driver structure */ +static struct hw_uart_device _uart0_device = +{ + RPI_UART0_BASE, + IRQ_PBA8_UART0, +}; +static struct rt_serial_device _serial0; +#endif + +#ifdef RT_USING_UART1 +/* UART1 device driver structure */ +static struct hw_uart_device _uart1_device = +{ + AUX_BASE, + IRQ_AUX, +}; +static struct rt_serial_device _serial1; +#endif + +int rt_hw_uart_init(void) +{ + struct hw_uart_device *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + +#ifdef RT_USING_UART0 + uart = &_uart0_device; + + _serial0.ops = &_uart_ops; + _serial0.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&_serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart0"); +#endif + +#ifdef RT_USING_UART1 + uart = &_uart1_device; + _serial1.ops = &_uart_ops; + _serial1.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&_serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); + /* enable Rx and Tx of UART */ + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial1, "uart1"); +#endif + + return 0; +} diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_uart.h b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..894c6098dbfaa9d9d0409b45e57a4c0758542226 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-5-30 Bernard the first version + */ + + +#ifndef DRV_UART_H__ +#define DRV_UART_H__ + +/* + * Auxiliary + */ +#define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */ +#define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */ +#define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */ +#define AUX_MU_IER_REG(BASE) HWREG32(BASE + 0x44) /* Mini Uart Interrupt Enable 8bit */ +#define AUX_MU_IIR_REG(BASE) HWREG32(BASE + 0x48) /* Mini Uart Interrupt Identify 8bit */ +#define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */ +#define AUX_MU_MCR_REG(BASE) HWREG32(BASE + 0x50) /* Mini Uart Modem Control 8bit */ +#define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */ +#define AUX_MU_MSR_REG(BASE) HWREG32(BASE + 0x58) /* Mini Uart Modem Status 8bit */ +#define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */ +#define AUX_MU_CNTL_REG(BASE) HWREG32(BASE + 0x60) /* Mini Uart Extra Control 8bit */ +#define AUX_MU_STAT_REG(BASE) HWREG32(BASE + 0x64) /* Mini Uart Extra Status 32bit */ +#define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */ +#define AUX_SPI0_CNTL0_REG(BASE) HWREG32(BASE + 0x80) /* SPI 1 Control register 0 32bit */ +#define AUX_SPI0_CNTL1_REG(BASE) HWREG32(BASE + 0x84) /* SPI 1 Control register 1 8bit */ +#define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */ +#define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */ +#define AUX_SPI0_PEEK_REG(BASE) HWREG32(BASE + 0x94) /* SPI 1 Peek 16bit */ +#define AUX_SPI1_CNTL0_REG(BASE) HWREG32(BASE + 0xC0) /* SPI 2 Control register 0 32bit */ +#define AUX_SPI1_CNTL1_REG(BASE) HWREG32(BASE + 0xC4) /* SPI 2 Control register 1 8bit */ + +int rt_hw_uart_init(void); + +#endif /* DRV_UART_H__ */ + diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c b/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..a1baee96aabbdb73f1dc6e2ad67ce53916a1817a --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ +#include "drv_wdt.h" + +#ifdef BSP_USING_WDT + +#define PM_RSTC 0x1c +#define PM_RSTS 0x20 +#define PM_WDOG 0x24 + +#define PM_PASSWORD 0x5a000000 + +#define PM_WDOG_TIME_SET 0x000fffff +#define PM_RSTC_WRCFG_CLR 0xffffffcf +#define PM_RSTS_HADWRH_SET 0x00000040 +#define PM_RSTC_WRCFG_SET 0x00000030 +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020 +#define PM_RSTC_RESET 0x00000102 +#define PM_RSTS_PARTITION_CLR 0xfffffaaa + +#define SECS_TO_WDOG_TICKS(x) ((x) << 16) +#define WDOG_TICKS_TO_SECS(x) ((x) >> 16) + +static struct raspi_wdt_driver bcm_wdt = +{ + .base = PER_BASE, +}; + +void raspi_watchdog_init(rt_uint32_t time_init) +{ + bcm_wdt.timeout = time_init; +} + +void raspi_watchdog_start() +{ + volatile rt_uint32_t cur; + bcm283x_peri_write(bcm_wdt.base + PM_WDOG, PM_PASSWORD + | (SECS_TO_WDOG_TICKS(bcm_wdt.timeout) & PM_WDOG_TIME_SET)); + bcm283x_peri_write(bcm_wdt.base + PM_WDOG, PM_PASSWORD + | (SECS_TO_WDOG_TICKS(bcm_wdt.timeout) & PM_WDOG_TIME_SET)); + + cur = bcm283x_peri_read(bcm_wdt.base + PM_RSTC); + + bcm283x_peri_write(bcm_wdt.base + PM_RSTC, PM_PASSWORD + | (cur & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET); + +} + +void raspi_watchdog_stop() +{ + bcm283x_peri_write(bcm_wdt.base + PM_RSTC, PM_PASSWORD | PM_RSTC_RESET); +} + +void raspi_watchdog_clr() +{ + bcm_wdt.timeout = 0; +} + +void raspi_watchdog_set_timeout( rt_uint32_t timeout_us) +{ + bcm_wdt.timeout = timeout_us; +} + +rt_uint64_t raspi_watchdog_get_timeout() +{ + return bcm_wdt.timeout; +} + +rt_uint64_t raspi_watchdog_get_timeleft() +{ + rt_uint32_t ret = bcm283x_peri_read(bcm_wdt.base + PM_WDOG); + return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET); +} + +static rt_err_t raspi_wdg_init(rt_watchdog_t *wdt) +{ + /*init for 10S*/ + raspi_watchdog_init(1000000); + raspi_watchdog_start(); + raspi_watchdog_stop(); + return RT_EOK; +} + +static rt_err_t raspi_wdg_control(rt_watchdog_t *wdt, int cmd, void *arg) +{ + rt_uint64_t timeout_us = 0; + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + timeout_us = *((rt_uint32_t *)arg) * 1000000; + if (timeout_us >= 0xFFFFFFFF) + timeout_us = 0xFFFFFFFF; + raspi_watchdog_set_timeout((rt_uint32_t)timeout_us); + break; + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + timeout_us = raspi_watchdog_get_timeout(); + *((rt_uint32_t *)arg) = timeout_us / 1000000; + break; + case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: + timeout_us = raspi_watchdog_get_timeleft(); + *((rt_uint32_t *)arg) = timeout_us / 1000000; + break; + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + raspi_watchdog_clr(); + break; + case RT_DEVICE_CTRL_WDT_START: + raspi_watchdog_start(); + break; + case RT_DEVICE_CTRL_WDT_STOP: + raspi_watchdog_stop(); + break; + default: + return RT_EIO; + } + return RT_EOK; +} + +static const struct rt_watchdog_ops raspi_wdg_pos = +{ + raspi_wdg_init, + raspi_wdg_control, +}; + +static rt_watchdog_t raspi_wdg; + +int rt_hw_wdt_init(void) +{ + raspi_wdg.ops = &raspi_wdg_pos; + rt_hw_watchdog_register(&raspi_wdg, "wdg", 0, RT_NULL); + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_wdt_init); +#endif /*BSP_USING_WDT */ diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h b/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h new file mode 100644 index 0000000000000000000000000000000000000000..a690becfd1c4d18910ee24adc423c4c2d6aafcaf --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#ifndef __DRV_WDT_H__ +#define __DRV_WDT_H__ + +#include +#include +#include +#include + +#include "bcm283x.h" + +struct raspi_wdt_driver +{ + volatile rt_uint32_t base; + rt_uint32_t timeout; +}; + +int rt_hw_wdt_init(void); + +#endif diff --git a/bsp/raspberry-pi/raspi3-64/driver/mbox.c b/bsp/raspberry-pi/raspi3-64/driver/mbox.c new file mode 100644 index 0000000000000000000000000000000000000000..36ed95b429ddd9ea08f02e0011fc58a3b879f4c8 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/mbox.c @@ -0,0 +1,53 @@ +/* + * File : mbox.c + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-08-29 zdzn first version + */ + +/* mailbox message buffer */ +#include "mbox.h" +#include "mmu.h" +//volatile unsigned int __attribute__((aligned(16))) mbox[36]; +volatile unsigned int *mbox = (volatile unsigned int *) MBOX_ADDR; +/** + * Make a mailbox call. Returns 0 on failure, non-zero on success + */ +void init_mbox_mmu_map(){ + rt_hw_change_mmu_table(MBOX_ADDR, 96, MBOX_ADDR, STRONG_ORDER_MEM); +} + +int mbox_call(unsigned char ch, int mmu_enable) +{ + unsigned int r = (((MBOX_ADDR)&~0xF) | (ch&0xF)); + if(mmu_enable) + r = BUS_ADDRESS(r); + /* wait until we can write to the mailbox */ + do + { + asm volatile("nop"); + } while (*MBOX_STATUS & MBOX_FULL); + /* write the address of our message to the mailbox with channel identifier */ + *MBOX_WRITE = r; + /* now wait for the response */ + // rt_kprintf("mailbox request %x\n",r); + while(1) + { + /* is there a response? */ + do + { + asm volatile("nop"); + } while (*MBOX_STATUS & MBOX_EMPTY); + /* is it a response to our message? */ + if (r == *MBOX_READ){ + /* is it a valid successful response? */ + // rt_kprintf("mbox: %x, %x, %x, %x, %x, %x, %x, %x\n", mbox[0], mbox[1], mbox[2], mbox[3], mbox[4], mbox[5], mbox[6], mbox[7]); + return mbox[1] == MBOX_RESPONSE; + } + } + return 0; +} diff --git a/bsp/raspberry-pi/raspi3-64/driver/mbox.h b/bsp/raspberry-pi/raspi3-64/driver/mbox.h new file mode 100644 index 0000000000000000000000000000000000000000..eb7eb0318cdf99bcd99157244b1c56b3b9e7706c --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/mbox.h @@ -0,0 +1,62 @@ +/* + * File : mbox.h + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-08-29 zdzn first version + */ + +#ifndef __MBOX_H__ +#define __MBOX_H__ + + +/* a properly aligned buffer */ +extern volatile unsigned int* mbox; + +#define MBOX_REQUEST 0 + +/* channels */ +#define MBOX_CH_POWER 0 +#define MBOX_CH_FB 1 +#define MBOX_CH_VUART 2 +#define MBOX_CH_VCHIQ 3 +#define MBOX_CH_LEDS 4 +#define MBOX_CH_BTNS 5 +#define MBOX_CH_TOUCH 6 +#define MBOX_CH_COUNT 7 +#define MBOX_CH_PROP 8 + +/* tags */ +#define MBOX_TAG_SETPOWER 0x28001 +#define MBOX_TAG_SETCLKRATE 0x38002 +#define MBOX_GET_MAC_ADDRESS 0x10003 +#define MBOX_TAG_LAST 0 + +#define MMIO_BASE 0x3F000000 +#define VIDEOCORE_MBOX (MMIO_BASE+0x0000B880) +#define MBOX_READ ((volatile unsigned int*)(VIDEOCORE_MBOX+0x0)) +#define MBOX_POLL ((volatile unsigned int*)(VIDEOCORE_MBOX+0x10)) +#define MBOX_SENDER ((volatile unsigned int*)(VIDEOCORE_MBOX+0x14)) +#define MBOX_STATUS ((volatile unsigned int*)(VIDEOCORE_MBOX+0x18)) +#define MBOX_CONFIG ((volatile unsigned int*)(VIDEOCORE_MBOX+0x1C)) +#define MBOX_WRITE ((volatile unsigned int*)(VIDEOCORE_MBOX+0x20)) +#define MBOX_RESPONSE 0x80000000 +#define MBOX_FULL 0x80000000 +#define MBOX_EMPTY 0x40000000 + +#define DEVICE_ID_SD_CARD 0 +#define DEVICE_ID_USB_HCD 3 +#define POWER_STATE_OFF (0 << 0) +#define POWER_STATE_ON (1 << 0) +#define POWER_STATE_WAIT (1 << 1) +#define POWER_STATE_NO_DEVICE (1 << 1) // in response +#define MMU_ENABLE 1 +#define MMU_DISABLE 0 + +#define MBOX_ADDR 0xc00000 + +int mbox_call(unsigned char ch, int mmu_enable); +#endif diff --git a/bsp/raspberry-pi/raspi3-64/driver/raspi.h b/bsp/raspberry-pi/raspi3-64/driver/raspi.h new file mode 100644 index 0000000000000000000000000000000000000000..0d55df2a1171d88e3f8d47dbd99b6db3a6bd61f8 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/driver/raspi.h @@ -0,0 +1,70 @@ +/* + * File : rsapi.h + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-29 zdzn first version + */ + +#ifndef __RASPI_H__ +#define __RASPI_H__ + +#include "bcm283x.h" + +#define PIN_MAGIC (0x5A) +#define PIN_NUM(_N) (sizeof(_N) / sizeof(_N[0])) + +enum gpio_code +{ + GPIO_CODE_PHY = 0, + GPIO_CODE_BCM, + GPIO_CODE_WIRING, + GPIO_CODE_NUM, +}; + +enum rpi_pin_name +{ + RPI_SDA0 = 0, + RPI_SCL0, + RPI_SDA1, + RPI_SCL1, + RPI_GPIO_GCLK, + RPI_CAM_CLK, + RPI_LAN_RUN, + RPI_SPI_CE1_N, + RPI_SPI_CE0_N, + RPI_SPI_MISO, + RPI_SPI_MOSI, + RPI_SPI_SCLK, + RPI_TXD0, + RPI_RXD0, + RPI_STATUS_LED_N, + RPI_GPIO_GEN0, + RPI_GPIO_GEN1, + RPI_CAM_GPIO, + RPI_GPIO_GEN3, + RPI_GPIO_GEN4, + RPI_GPIO_GEN5, + RPI_GPIO_GEN6, + RPI_GPIO_GEN2, + RPI_GPIO_GEN7, + RPI_GPIO_GEN8, + RPI_GPIO_GEN9, + RPI_GPIO_GEN10, + RPI_PWM0_OUT, + RPI_PWM1_OUT, + RPI_HDMI_HPD_P, + RPI_SD_CARD_DET, + RPI_SD_CLK_R, + RPI_SD_CMD_R, + RPI_SD_DATA0_R, + RPI_SD_DATA1_R, + RPI_SD_DATA2_R, + RPI_SD_DATA3_R, + RPI_GPIO_PIN_NUM, +}; + +#endif diff --git a/bsp/raspberry-pi/raspi3-64/figures/raspi_uart.png b/bsp/raspberry-pi/raspi3-64/figures/raspi_uart.png new file mode 100644 index 0000000000000000000000000000000000000000..c6ae382182e3f218c61338dbf0ed5c3066d9550f Binary files /dev/null and b/bsp/raspberry-pi/raspi3-64/figures/raspi_uart.png differ diff --git a/bsp/raspberry-pi/raspi3-64/link.lds b/bsp/raspberry-pi/raspi3-64/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..604a45c11031603f938ddb96fa8f977a98ba67ab --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/link.lds @@ -0,0 +1,151 @@ +/* + * File : link.lds + * COPYRIGHT (C) 2017, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * 2017-5-30 bernard first version + */ + +/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */ + +SECTIONS +{ + . = 0x80000; + . = ALIGN(4096); + .text : + { + KEEP(*(.text.entrypoint)) /* The entry point */ + *(.vectors) + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(16); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(16); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(16); + + /* section information for initial. */ + . = ALIGN(16); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(16); + + . = ALIGN(16); + _etext = .; + } + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + *(.eh_frame_entry) + } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + + . = ALIGN(16); + .data : + { + *(.data) + *(.data.*) + + *(.data1) + *(.data1.*) + + . = ALIGN(16); + _gp = ABSOLUTE(.); /* Base of small data */ + + *(.sdata) + *(.sdata.*) + } + + . = ALIGN(16); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + . = ALIGN(16); + .bss : + { + PROVIDE(__bss_start = .); + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + PROVIDE(__bss_end = .); + } + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} + +__bss_size = (__bss_end - __bss_start)>>3; diff --git a/bsp/raspberry-pi/raspi3-64/qemu-64.bat b/bsp/raspberry-pi/raspi3-64/qemu-64.bat new file mode 100644 index 0000000000000000000000000000000000000000..c009905e2364fe91ef5446940ec5f7da6c0f9e89 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/qemu-64.bat @@ -0,0 +1 @@ +qemu-system-aarch64 -M raspi3 -kernel kernel8.img -serial null -serial stdio \ No newline at end of file diff --git a/bsp/raspberry-pi/raspi3-64/rtconfig.h b/bsp/raspberry-pi/raspi3-64/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..4a8d8c42bce764e5d9a913cedd2265741ad3ea1f --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/rtconfig.h @@ -0,0 +1,382 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +/* RT_USING_ARCH_DATA_TYPE is not set */ +/* RT_USING_SMP is not set */ +#define RT_ALIGN_SIZE 4 +/* RT_THREAD_PRIORITY_8 is not set */ +#define RT_THREAD_PRIORITY_32 +/* RT_THREAD_PRIORITY_256 is not set */ +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 2048 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 2048 +#define RT_DEBUG +#define RT_DEBUG_COLOR +/* RT_DEBUG_INIT_CONFIG is not set */ +/* RT_DEBUG_THREAD_CONFIG is not set */ +/* RT_DEBUG_SCHEDULER_CONFIG is not set */ +/* RT_DEBUG_IPC_CONFIG is not set */ +/* RT_DEBUG_TIMER_CONFIG is not set */ +/* RT_DEBUG_IRQ_CONFIG is not set */ +/* RT_DEBUG_MEM_CONFIG is not set */ +/* RT_DEBUG_SLAB_CONFIG is not set */ +/* RT_DEBUG_MEMHEAP_CONFIG is not set */ +/* RT_DEBUG_MODULE_CONFIG is not set */ + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* RT_USING_SIGNALS is not set */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +/* RT_USING_NOHEAP is not set */ +#define RT_USING_SMALL_MEM +/* RT_USING_SLAB is not set */ +/* RT_USING_MEMHEAP_AS_HEAP is not set */ +#define RT_USING_MEMTRACE +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS +/* RT_USING_INTERRUPT_INFO is not set */ +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40002 +#define ARCH_CPU_64BIT +#define ARCH_ARM +/* RT_USING_CPU_FFS is not set */ +#define ARCH_ARM_CORTEX_AARCH64 +#define ARCH_ARM_CORTEX_A53 +/* ARCH_CPU_STACK_GROWS_UPWARD is not set */ + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + +/* RT_USING_CPLUSPLUS is not set */ + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +/* FINSH_ECHO_DISABLE_DEFAULT is not set */ +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +/* FINSH_USING_AUTH is not set */ +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +/* RT_USING_DFS_MNTTABLE is not set */ +/* RT_USING_DFS_ELMFAT is not set */ +#define RT_USING_DFS_DEVFS +/* RT_USING_DFS_ROMFS is not set */ +/* RT_USING_DFS_RAMFS is not set */ +/* RT_USING_DFS_UFFS is not set */ +/* RT_USING_DFS_JFFS2 is not set */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +/* RT_USING_SYSTEM_WORKQUEUE is not set */ +#define RT_USING_SERIAL +/* RT_SERIAL_USING_DMA is not set */ +#define RT_SERIAL_RB_BUFSZ 64 +/* RT_USING_CAN is not set */ +/* RT_USING_HWTIMER is not set */ +/* RT_USING_CPUTIME is not set */ +/* RT_USING_I2C is not set */ +#define RT_USING_PIN +/* RT_USING_ADC is not set */ +/* RT_USING_PWM is not set */ +/* RT_USING_MTD_NOR is not set */ +/* RT_USING_MTD_NAND is not set */ +/* RT_USING_PM is not set */ +/* RT_USING_RTC is not set */ +/* RT_USING_SDIO is not set */ +/* RT_USING_SPI is not set */ +/* RT_USING_WDT is not set */ +/* RT_USING_AUDIO is not set */ +/* RT_USING_SENSOR is not set */ +/* RT_USING_TOUCH is not set */ +/* RT_USING_HWCRYPTO is not set */ +/* RT_USING_WIFI is not set */ + +/* Using USB */ + +/* RT_USING_USB_HOST is not set */ +/* RT_USING_USB_DEVICE is not set */ + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +/* RT_USING_PTHREADS is not set */ +#define RT_USING_POSIX +/* RT_USING_POSIX_MMAP is not set */ +/* RT_USING_POSIX_TERMIOS is not set */ +/* RT_USING_POSIX_AIO is not set */ +/* RT_USING_MODULE is not set */ + +/* Network */ + +/* Socket abstraction layer */ + +/* RT_USING_SAL is not set */ + +/* Network interface device */ + +/* RT_USING_NETDEV is not set */ + +/* light weight TCP/IP stack */ + +/* RT_USING_LWIP is not set */ + +/* AT commands */ + +/* RT_USING_AT is not set */ + +/* VBUS(Virtual Software BUS) */ + +/* RT_USING_VBUS is not set */ + +/* Utilities */ + +/* RT_USING_RYM is not set */ +/* RT_USING_ULOG is not set */ +/* RT_USING_UTEST is not set */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + +/* PKG_USING_PAHOMQTT is not set */ +/* PKG_USING_WEBCLIENT is not set */ +/* PKG_USING_WEBNET is not set */ +/* PKG_USING_MONGOOSE is not set */ +/* PKG_USING_WEBTERMINAL is not set */ +/* PKG_USING_CJSON is not set */ +/* PKG_USING_JSMN is not set */ +/* PKG_USING_LIBMODBUS is not set */ +/* PKG_USING_FREEMODBUS is not set */ +/* PKG_USING_LJSON is not set */ +/* PKG_USING_EZXML is not set */ +/* PKG_USING_NANOPB is not set */ + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* PKG_USING_WLANMARVELL is not set */ + +/* Wiced WiFi */ + +/* PKG_USING_WLAN_WICED is not set */ +/* PKG_USING_RW007 is not set */ +/* PKG_USING_COAP is not set */ +/* PKG_USING_NOPOLL is not set */ +/* PKG_USING_NETUTILS is not set */ +/* PKG_USING_PPP_DEVICE is not set */ +/* PKG_USING_AT_DEVICE is not set */ +/* PKG_USING_ATSRV_SOCKET is not set */ +/* PKG_USING_WIZNET is not set */ + +/* IoT Cloud */ + +/* PKG_USING_ONENET is not set */ +/* PKG_USING_GAGENT_CLOUD is not set */ +/* PKG_USING_ALI_IOTKIT is not set */ +/* PKG_USING_AZURE is not set */ +/* PKG_USING_TENCENT_IOTHUB is not set */ +/* PKG_USING_JIOT-C-SDK is not set */ +/* PKG_USING_NIMBLE is not set */ +/* PKG_USING_OTA_DOWNLOADER is not set */ +/* PKG_USING_IPMSG is not set */ +/* PKG_USING_LSSDP is not set */ +/* PKG_USING_AIRKISS_OPEN is not set */ +/* PKG_USING_LIBRWS is not set */ +/* PKG_USING_TCPSERVER is not set */ +/* PKG_USING_PROTOBUF_C is not set */ +/* PKG_USING_ONNX_PARSER is not set */ +/* PKG_USING_ONNX_BACKEND is not set */ +/* PKG_USING_DLT645 is not set */ +/* PKG_USING_QXWZ is not set */ +/* PKG_USING_SMTP_CLIENT is not set */ + +/* security packages */ + +/* PKG_USING_MBEDTLS is not set */ +/* PKG_USING_libsodium is not set */ +/* PKG_USING_TINYCRYPT is not set */ + +/* language packages */ + +/* PKG_USING_LUA is not set */ +/* PKG_USING_JERRYSCRIPT is not set */ +/* PKG_USING_MICROPYTHON is not set */ + +/* multimedia packages */ + +/* PKG_USING_OPENMV is not set */ +/* PKG_USING_MUPDF is not set */ +/* PKG_USING_STEMWIN is not set */ +/* PKG_USING_WAVPLAYER is not set */ +/* PKG_USING_TJPGD is not set */ + +/* tools packages */ + +/* PKG_USING_CMBACKTRACE is not set */ +/* PKG_USING_EASYFLASH is not set */ +/* PKG_USING_EASYLOGGER is not set */ +/* PKG_USING_SYSTEMVIEW is not set */ +/* PKG_USING_RDB is not set */ +/* PKG_USING_QRCODE is not set */ +/* PKG_USING_ULOG_EASYFLASH is not set */ +/* PKG_USING_ADBD is not set */ +/* PKG_USING_COREMARK is not set */ +/* PKG_USING_DHRYSTONE is not set */ + +/* system packages */ + +/* PKG_USING_GUIENGINE is not set */ +/* PKG_USING_CAIRO is not set */ +/* PKG_USING_PIXMAN is not set */ +/* PKG_USING_LWEXT4 is not set */ +/* PKG_USING_PARTITION is not set */ +/* PKG_USING_FAL is not set */ +/* PKG_USING_SQLITE is not set */ +/* PKG_USING_RTI is not set */ +/* PKG_USING_LITTLEVGL2RTT is not set */ +/* PKG_USING_CMSIS is not set */ +/* PKG_USING_DFS_YAFFS is not set */ +/* PKG_USING_LITTLEFS is not set */ +/* PKG_USING_THREAD_POOL is not set */ +/* PKG_USING_ROBOTS is not set */ + +/* peripheral libraries and drivers */ + +/* PKG_USING_SENSORS_DRIVERS is not set */ +/* PKG_USING_REALTEK_AMEBA is not set */ +/* PKG_USING_SHT2X is not set */ +/* PKG_USING_STM32_SDIO is not set */ +/* PKG_USING_ICM20608 is not set */ +/* PKG_USING_U8G2 is not set */ +/* PKG_USING_BUTTON is not set */ +/* PKG_USING_PCF8574 is not set */ +/* PKG_USING_SX12XX is not set */ +/* PKG_USING_SIGNAL_LED is not set */ +/* PKG_USING_LEDBLINK is not set */ +/* PKG_USING_WM_LIBRARIES is not set */ +/* PKG_USING_KENDRYTE_SDK is not set */ +/* PKG_USING_INFRARED is not set */ +/* PKG_USING_ROSSERIAL is not set */ +/* PKG_USING_AGILE_BUTTON is not set */ +/* PKG_USING_AGILE_LED is not set */ +/* PKG_USING_AT24CXX is not set */ +/* PKG_USING_MOTIONDRIVER2RTT is not set */ +/* PKG_USING_AD7746 is not set */ +/* PKG_USING_PCA9685 is not set */ +/* PKG_USING_I2C_TOOLS is not set */ +/* PKG_USING_NRF24L01 is not set */ +/* PKG_USING_TOUCH_DRIVERS is not set */ +/* PKG_USING_LCD_DRIVERS is not set */ +/* PKG_USING_MAX17048 is not set */ +/* PKG_USING_RPLIDAR is not set */ + +/* miscellaneous packages */ + +/* PKG_USING_LIBCSV is not set */ +/* PKG_USING_OPTPARSE is not set */ +/* PKG_USING_FASTLZ is not set */ +/* PKG_USING_MINILZO is not set */ +/* PKG_USING_QUICKLZ is not set */ +/* PKG_USING_MULTIBUTTON is not set */ +/* PKG_USING_FLEXIBLE_BUTTON is not set */ +/* PKG_USING_CANFESTIVAL is not set */ +/* PKG_USING_ZLIB is not set */ +/* PKG_USING_DSTR is not set */ +/* PKG_USING_TINYFRAME is not set */ +/* PKG_USING_KENDRYTE_DEMO is not set */ +/* PKG_USING_DIGITALCTRL is not set */ +/* PKG_USING_UPACKER is not set */ +/* PKG_USING_UPARAM is not set */ + +/* samples: kernel and components samples */ + +/* PKG_USING_KERNEL_SAMPLES is not set */ +/* PKG_USING_FILESYSTEM_SAMPLES is not set */ +/* PKG_USING_NETWORK_SAMPLES is not set */ +/* PKG_USING_PERIPHERAL_SAMPLES is not set */ +/* PKG_USING_HELLO is not set */ +/* PKG_USING_VI is not set */ +/* PKG_USING_NNOM is not set */ +/* PKG_USING_LIBANN is not set */ +/* PKG_USING_ELAPACK is not set */ +/* PKG_USING_ARMv7M_DWT is not set */ +/* PKG_USING_VT100 is not set */ +/* PKG_USING_ULAPACK is not set */ +/* PKG_USING_UKAL is not set */ +#define BCM2836_SOC +/* BSP_SUPPORT_FPU is not set */ + +/* Hardware Drivers Config */ + +/* BCM Peripheral Drivers */ + +#define BSP_USING_UART +/* RT_USING_UART0 is not set */ +#define RT_USING_UART1 +#define BSP_USING_PIN +/* BSP_USING_SYSTIMER is not set */ +/* BSP_USING_I2C is not set */ +/* BSP_USING_SPI is not set */ +/* BSP_USING_WDT is not set */ +/* BSP_USING_RTC is not set */ +/* BSP_USING_SDIO is not set */ + +/* Board Peripheral Drivers */ + +/* BSP_USING_HDMI is not set */ + +#endif diff --git a/bsp/raspberry-pi/raspi3-64/rtconfig.py b/bsp/raspberry-pi/raspi3-64/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..e3766650835dcac3eed2d79db8d1212fed1b1f16 --- /dev/null +++ b/bsp/raspberry-pi/raspi3-64/rtconfig.py @@ -0,0 +1,51 @@ +import os + +# toolchains options +ARCH ='aarch64' +CPU ='cortex-a53' +CROSS_TOOL ='gcc' + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = r'../../..' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +PLATFORM = 'gcc' +EXEC_PATH = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/' + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + # PREFIX = 'arm-none-eabi-' + PREFIX = 'aarch64-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -march=armv8-a -mtune=cortex-a53' + CFLAGS = DEVICE + ' -Wall' + AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET kernel8.img\n' + SIZE + ' $TARGET \n' diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_config_macosx.h.orig b/bsp/simulator/SDL2-2.0.7/include/SDL_config_macosx.h.orig deleted file mode 100644 index f03f1ae3dd1afc12f8d4bb2c90eab3dfd697dacc..0000000000000000000000000000000000000000 --- a/bsp/simulator/SDL2-2.0.7/include/SDL_config_macosx.h.orig +++ /dev/null @@ -1,197 +0,0 @@ -/* - Simple DirectMedia Layer - Copyright (C) 1997-2017 Sam Lantinga - - This software is provided 'as-is', without any express or implied - warranty. In no event will the authors be held liable for any damages - arising from the use of this software. - - Permission is granted to anyone to use this software for any purpose, - including commercial applications, and to alter it and redistribute it - freely, subject to the following restrictions: - - 1. The origin of this software must not be misrepresented; you must not - claim that you wrote the original software. If you use this software - in a product, an acknowledgment in the product documentation would be - appreciated but is not required. - 2. Altered source versions must be plainly marked as such, and must not be - misrepresented as being the original software. - 3. This notice may not be removed or altered from any source distribution. -*/ - -#ifndef SDL_config_macosx_h_ -#define SDL_config_macosx_h_ -#define SDL_config_h_ - -#include "SDL_platform.h" - -/* This gets us MAC_OS_X_VERSION_MIN_REQUIRED... */ -#include - -/* This is a set of defines to configure the SDL features */ - -#ifdef __LP64__ - #define SIZEOF_VOIDP 8 -#else - #define SIZEOF_VOIDP 4 -#endif - -/* Useful headers */ -#define HAVE_ALLOCA_H 1 -#define HAVE_SYS_TYPES_H 1 -#define HAVE_STDIO_H 1 -#define STDC_HEADERS 1 -#define HAVE_STRING_H 1 -#define HAVE_INTTYPES_H 1 -#define HAVE_STDINT_H 1 -#define HAVE_CTYPE_H 1 -#define HAVE_MATH_H 1 -#define HAVE_SIGNAL_H 1 - -/* C library functions */ -#define HAVE_MALLOC 1 -#define HAVE_CALLOC 1 -#define HAVE_REALLOC 1 -#define HAVE_FREE 1 -#define HAVE_ALLOCA 1 -#define HAVE_GETENV 1 -#define HAVE_SETENV 1 -#define HAVE_PUTENV 1 -#define HAVE_UNSETENV 1 -#define HAVE_QSORT 1 -#define HAVE_ABS 1 -#define HAVE_BCOPY 1 -#define HAVE_MEMSET 1 -#define HAVE_MEMCPY 1 -#define HAVE_MEMMOVE 1 -#define HAVE_MEMCMP 1 -#define HAVE_STRLEN 1 -#define HAVE_STRLCPY 1 -#define HAVE_STRLCAT 1 -#define HAVE_STRDUP 1 -#define HAVE_STRCHR 1 -#define HAVE_STRRCHR 1 -#define HAVE_STRSTR 1 -#define HAVE_STRTOL 1 -#define HAVE_STRTOUL 1 -#define HAVE_STRTOLL 1 -#define HAVE_STRTOULL 1 -#define HAVE_STRTOD 1 -#define HAVE_ATOI 1 -#define HAVE_ATOF 1 -#define HAVE_STRCMP 1 -#define HAVE_STRNCMP 1 -#define HAVE_STRCASECMP 1 -#define HAVE_STRNCASECMP 1 -#define HAVE_VSSCANF 1 -#define HAVE_VSNPRINTF 1 -#define HAVE_CEIL 1 -#define HAVE_COPYSIGN 1 -#define HAVE_COS 1 -#define HAVE_COSF 1 -#define HAVE_FABS 1 -#define HAVE_FLOOR 1 -#define HAVE_LOG 1 -#define HAVE_POW 1 -#define HAVE_SCALBN 1 -#define HAVE_SIN 1 -#define HAVE_SINF 1 -#define HAVE_SQRT 1 -#define HAVE_SQRTF 1 -#define HAVE_TAN 1 -#define HAVE_TANF 1 -#define HAVE_SIGACTION 1 -#define HAVE_SETJMP 1 -#define HAVE_NANOSLEEP 1 -#define HAVE_SYSCONF 1 -#define HAVE_SYSCTLBYNAME 1 -#define HAVE_ATAN 1 -#define HAVE_ATAN2 1 -#define HAVE_ACOS 1 -#define HAVE_ASIN 1 - -/* Enable various audio drivers */ -#define SDL_AUDIO_DRIVER_COREAUDIO 1 -#define SDL_AUDIO_DRIVER_DISK 1 -#define SDL_AUDIO_DRIVER_DUMMY 1 - -/* Enable various input drivers */ -#define SDL_JOYSTICK_IOKIT 1 -#define SDL_HAPTIC_IOKIT 1 - -/* Enable various shared object loading systems */ -#define SDL_LOADSO_DLOPEN 1 - -/* Enable various threading systems */ -#define SDL_THREAD_PTHREAD 1 -#define SDL_THREAD_PTHREAD_RECURSIVE_MUTEX 1 - -/* Enable various timer systems */ -#define SDL_TIMER_UNIX 1 - -/* Enable various video drivers */ -#define SDL_VIDEO_DRIVER_COCOA 1 -#define SDL_VIDEO_DRIVER_DUMMY 1 -#undef SDL_VIDEO_DRIVER_X11 -#define SDL_VIDEO_DRIVER_X11_DYNAMIC "/usr/X11R6/lib/libX11.6.dylib" -#define SDL_VIDEO_DRIVER_X11_DYNAMIC_XEXT "/usr/X11R6/lib/libXext.6.dylib" -#define SDL_VIDEO_DRIVER_X11_DYNAMIC_XINERAMA "/usr/X11R6/lib/libXinerama.1.dylib" -#define SDL_VIDEO_DRIVER_X11_DYNAMIC_XINPUT2 "/usr/X11R6/lib/libXi.6.dylib" -#define SDL_VIDEO_DRIVER_X11_DYNAMIC_XRANDR "/usr/X11R6/lib/libXrandr.2.dylib" -#define SDL_VIDEO_DRIVER_X11_DYNAMIC_XSS "/usr/X11R6/lib/libXss.1.dylib" -#define SDL_VIDEO_DRIVER_X11_DYNAMIC_XVIDMODE "/usr/X11R6/lib/libXxf86vm.1.dylib" -#define SDL_VIDEO_DRIVER_X11_XDBE 1 -#define SDL_VIDEO_DRIVER_X11_XINERAMA 1 -#define SDL_VIDEO_DRIVER_X11_XRANDR 1 -#define SDL_VIDEO_DRIVER_X11_XSCRNSAVER 1 -#define SDL_VIDEO_DRIVER_X11_XSHAPE 1 -#define SDL_VIDEO_DRIVER_X11_XVIDMODE 1 -#define SDL_VIDEO_DRIVER_X11_HAS_XKBKEYCODETOKEYSYM 1 - -#ifdef MAC_OS_X_VERSION_10_8 -/* - * No matter the versions targeted, this is the 10.8 or later SDK, so you have - * to use the external Xquartz, which is a more modern Xlib. Previous SDKs - * used an older Xlib. - */ -#define SDL_VIDEO_DRIVER_X11_XINPUT2 1 -#define SDL_VIDEO_DRIVER_X11_SUPPORTS_GENERIC_EVENTS 1 -#define SDL_VIDEO_DRIVER_X11_CONST_PARAM_XEXTADDDISPLAY 1 -#endif - -#ifndef SDL_VIDEO_RENDER_OGL -#define SDL_VIDEO_RENDER_OGL 1 -#endif - -/* Enable OpenGL support */ -#ifndef SDL_VIDEO_OPENGL -#define SDL_VIDEO_OPENGL 1 -#endif -#ifndef SDL_VIDEO_OPENGL_CGL -#define SDL_VIDEO_OPENGL_CGL 1 -#endif -#ifndef SDL_VIDEO_OPENGL_GLX -#define SDL_VIDEO_OPENGL_GLX 1 -#endif - -/* Enable Vulkan support */ -/* Metal/MoltenVK/Vulkan only supported on 64-bit architectures and 10.11+ */ -#if TARGET_CPU_X86_64 -#define SDL_VIDEO_VULKAN 1 -#else -#define SDL_VIDEO_VULKAN 0 -#endif - -/* Enable system power support */ -#define SDL_POWER_MACOSX 1 - -/* enable filesystem support */ -#define SDL_FILESYSTEM_COCOA 1 - -/* Enable assembly routines */ -#define SDL_ASSEMBLY_ROUTINES 1 -#ifdef __ppc__ -#define SDL_ALTIVEC_BLITTERS 1 -#endif - -#endif /* SDL_config_macosx_h_ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/SConscript b/bsp/stm32/libraries/HAL_Drivers/SConscript index 02f68afa25679fe7b1b1104ae021267131654fbd..c7d5825f8f88be754f6e914cf9a09f6d5c328d53 100644 --- a/bsp/stm32/libraries/HAL_Drivers/SConscript +++ b/bsp/stm32/libraries/HAL_Drivers/SConscript @@ -72,10 +72,10 @@ if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F7']): if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']): src += ['drv_flash/drv_flash_l4.c'] - + if GetDepend('RT_USING_HWCRYPTO'): src += ['drv_crypto.c'] - + if GetDepend(['BSP_USING_WDT']): src += ['drv_wdt.c'] @@ -88,6 +88,9 @@ if GetDepend(['BSP_USING_USBD']): if GetDepend(['BSP_USING_PULSE_ENCODER']): src += ['drv_pulse_encoder.c'] +if GetDepend(['BSP_USING_USBH']): + src += ['drv_usbh.c'] + src += ['drv_common.c'] path = [cwd] diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h index 46411c5441ec6a0e5263426e63d8fc42a43a5cbb..17768c9a04b2a9ceb36a67010d2b748b2eb6eb15 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h @@ -157,12 +157,12 @@ extern "C" { #define SPI1_RX_DMA_INSTANCE DMA2_Stream0 #define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3 #define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn -#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) -#define SPI4_DMA_TX_IRQHandler DMA2_Stream0_IRQHandler -#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI4_TX_DMA_INSTANCE DMA2_Stream0 -#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4 -#define SPI4_TX_DMA_IRQ DMA2_Stream0_IRQn +#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) +#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler +#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_RX_DMA_INSTANCE DMA2_Stream0 +#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_4 +#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn #endif /* DMA2 stream1 */ @@ -208,12 +208,12 @@ extern "C" { #define SPI1_TX_DMA_INSTANCE DMA2_Stream3 #define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3 #define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn -#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) -#define SPI4_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler -#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN -#define SPI4_TX_DMA_INSTANCE DMA2_Stream3 -#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5 -#define SPI4_TX_DMA_IRQ DMA2_Stream3_IRQn +#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) +#define SPI4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler +#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN +#define SPI4_RX_DMA_INSTANCE DMA2_Stream3 +#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_5 +#define SPI4_RX_DMA_IRQ DMA2_Stream3_IRQn #endif /* DMA2 stream4 */ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h index 14d4aa2affeb7cb2dcf2d8ff945db8cd03494838..38033034930c1ca4eb76ce3364428813d5e5f8ff 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h @@ -61,6 +61,17 @@ extern "C" { #endif /* PWM5_CONFIG */ #endif /* BSP_USING_PWM5 */ +#ifdef BSP_USING_PWM9 +#ifndef PWM9_CONFIG +#define PWM9_CONFIG \ + { \ + .tim_handle.Instance = TIM9, \ + .name = "pwm9", \ + .channel = 0 \ + } +#endif /* PWM9_CONFIG */ +#endif /* BSP_USING_PWM9 */ + #ifdef BSP_USING_PWM12 #ifndef PWM12_CONFIG #define PWM12_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h index cd116d9e19c6a7c76c3092a7b28ce80da4cd5786..bc08f219b9c806eed836c754f336204191363ac1 100644 --- a/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h @@ -27,6 +27,17 @@ extern "C" { } #endif /* TIM_DEV_INFO_CONFIG */ +#ifdef BSP_USING_TIM3 +#ifndef TIM3_CONFIG +#define TIM3_CONFIG \ + { \ + .tim_handle.Instance = TIM3, \ + .tim_irqn = TIM3_IRQn, \ + .name = "timer3", \ + } +#endif /* TIM3_CONFIG */ +#endif /* BSP_USING_TIM3 */ + #ifdef BSP_USING_TIM11 #ifndef TIM11_CONFIG #define TIM11_CONFIG \ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_common.c b/bsp/stm32/libraries/HAL_Drivers/drv_common.c index 1203757a65f36313fc25c9ba0a7803309544edc7..02e0d82be53abea1f767a46c76e5ac35bb6cdee3 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_common.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_common.c @@ -67,6 +67,7 @@ void HAL_ResumeTick(void) void HAL_Delay(__IO uint32_t Delay) { + rt_thread_mdelay(Delay); } /* re-implement tick interface for STM32 HAL */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_eth.c b/bsp/stm32/libraries/HAL_Drivers/drv_eth.c index 097a1622e5c3f6ca971309c59f7f8eca99f03fc3..4ead17dc23af6e3af88f81cf738f9cf1d919d75f 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_eth.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_eth.c @@ -411,11 +411,11 @@ static void phy_linkchange() if (status & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK)) { - rt_uint32_t SR; + rt_uint32_t SR = 0; phy_speed_new |= PHY_LINK; - SR = HAL_ETH_ReadPHYRegister(&EthHandle, PHY_Status_REG, (uint32_t *)&SR); + HAL_ETH_ReadPHYRegister(&EthHandle, PHY_Status_REG, (uint32_t *)&SR); LOG_D("phy control status reg is 0x%X", SR); if (PHY_Status_SPEED_100M(SR)) diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f7.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f7.c index 3ecb0be5e9ff21a1b841005693d9a3a47da4a879..276c9ba0b945010c44840d55647615926e3fdf41 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f7.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f7.c @@ -7,6 +7,7 @@ * Date Author Notes * 2018-12-5 SummerGift first version * 2019-3-2 jinsheng add Macro judgment + * 2020-1-6 duminmin support single bank mode */ #include "board.h" @@ -22,32 +23,6 @@ //#define DRV_DEBUG #define LOG_TAG "drv.flash" #include -#if defined (FLASH_OPTCR_nDBANK) -#define ADDR_FLASH_SECTOR_0 ((rt_uint32_t)0x08000000) /* Base address of Sector 0, 16 Kbytes */ -#define ADDR_FLASH_SECTOR_1 ((rt_uint32_t)0x08004000) /* Base address of Sector 1, 16 Kbytes */ -#define ADDR_FLASH_SECTOR_2 ((rt_uint32_t)0x08008000) /* Base address of Sector 2, 16 Kbytes */ -#define ADDR_FLASH_SECTOR_3 ((rt_uint32_t)0x0800C000) /* Base address of Sector 3, 16 Kbytes */ -#define ADDR_FLASH_SECTOR_4 ((rt_uint32_t)0x08010000) /* Base address of Sector 4, 64 Kbytes */ -#define ADDR_FLASH_SECTOR_5 ((rt_uint32_t)0x08020000) /* Base address of Sector 5, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_6 ((rt_uint32_t)0x08040000) /* Base address of Sector 6, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_7 ((rt_uint32_t)0x08060000) /* Base address of Sector 7, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_8 ((rt_uint32_t)0x08080000) /* Base address of Sector 8, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_9 ((rt_uint32_t)0x080A0000) /* Base address of Sector 9, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_10 ((rt_uint32_t)0x080C0000) /* Base address of Sector 10, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_11 ((rt_uint32_t)0x080E0000) /* Base address of Sector 11, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_12 ((rt_uint32_t)0x08100000) /* Base address of Sector 12, 16 Kbytes */ -#define ADDR_FLASH_SECTOR_13 ((rt_uint32_t)0x08104000) /* Base address of Sector 13, 16 Kbytes */ -#define ADDR_FLASH_SECTOR_14 ((rt_uint32_t)0x08108000) /* Base address of Sector 14, 16 Kbytes */ -#define ADDR_FLASH_SECTOR_15 ((rt_uint32_t)0x0810C000) /* Base address of Sector 15, 16 Kbytes */ -#define ADDR_FLASH_SECTOR_16 ((rt_uint32_t)0x08110000) /* Base address of Sector 16, 64 Kbytes */ -#define ADDR_FLASH_SECTOR_17 ((rt_uint32_t)0x08120000) /* Base address of Sector 17, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_18 ((rt_uint32_t)0x08140000) /* Base address of Sector 18, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_19 ((rt_uint32_t)0x08160000) /* Base address of Sector 19, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_20 ((rt_uint32_t)0x08180000) /* Base address of Sector 20, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_21 ((rt_uint32_t)0x081A0000) /* Base address of Sector 21, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_22 ((rt_uint32_t)0x081C0000) /* Base address of Sector 22, 128 Kbytes */ -#define ADDR_FLASH_SECTOR_23 ((rt_uint32_t)0x081E0000) /* Base address of Sector 23, 128 Kbytes */ -#else #define ADDR_FLASH_SECTOR_0 ((rt_uint32_t)0x08000000) /* Base address of Sector 0, 32 Kbytes */ #define ADDR_FLASH_SECTOR_1 ((rt_uint32_t)0x08008000) /* Base address of Sector 1, 32 Kbytes */ #define ADDR_FLASH_SECTOR_2 ((rt_uint32_t)0x08010000) /* Base address of Sector 2, 32 Kbytes */ @@ -60,7 +35,6 @@ #define ADDR_FLASH_SECTOR_9 ((rt_uint32_t)0x08140000) /* Base address of Sector 9, 256 Kbytes */ #define ADDR_FLASH_SECTOR_10 ((rt_uint32_t)0x08180000) /* Base address of Sector 10, 256 Kbytes */ #define ADDR_FLASH_SECTOR_11 ((rt_uint32_t)0x081C0000) /* Base address of Sector 11, 256 Kbytes */ -#endif /** * @brief Gets the sector of a given address * @param None @@ -68,116 +42,73 @@ */ static rt_uint32_t GetSector(rt_uint32_t Address) { - rt_uint32_t sector = 0; + uint32_t sector = 0; + #if defined (FLASH_OPTCR_nDBANK) - if ((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0)) - { - sector = FLASH_SECTOR_0; - } - else if ((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1)) - { - sector = FLASH_SECTOR_1; - } -#if (FLASH_SECTOR_TOTAL >= 4) - else if ((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2)) - { - sector = FLASH_SECTOR_2; - } - else if ((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3)) - { - sector = FLASH_SECTOR_3; - } -#elif (FLASH_SECTOR_TOTAL >= 8) - else if ((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4)) - { - sector = FLASH_SECTOR_4; - } - else if ((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5)) - { - sector = FLASH_SECTOR_5; - } - else if ((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6)) - { - sector = FLASH_SECTOR_6; - } - else if ((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7)) - { - sector = FLASH_SECTOR_7; - } -#elif (FLASH_SECTOR_TOTAL >= 24) - else if ((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8)) - { - sector = FLASH_SECTOR_8; - } - else if ((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9)) - { - sector = FLASH_SECTOR_9; - } - else if ((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10)) - { - sector = FLASH_SECTOR_10; - } - else if ((Address < ADDR_FLASH_SECTOR_12) && (Address >= ADDR_FLASH_SECTOR_11)) - { - sector = FLASH_SECTOR_11; - } - else if ((Address < ADDR_FLASH_SECTOR_13) && (Address >= ADDR_FLASH_SECTOR_12)) - { - sector = FLASH_SECTOR_12; - } - else if ((Address < ADDR_FLASH_SECTOR_14) && (Address >= ADDR_FLASH_SECTOR_13)) - { - sector = FLASH_SECTOR_13; - } - else if ((Address < ADDR_FLASH_SECTOR_15) && (Address >= ADDR_FLASH_SECTOR_14)) - { - sector = FLASH_SECTOR_14; - } - else if ((Address < ADDR_FLASH_SECTOR_16) && (Address >= ADDR_FLASH_SECTOR_15)) - { - sector = FLASH_SECTOR_15; - } - else if ((Address < ADDR_FLASH_SECTOR_17) && (Address >= ADDR_FLASH_SECTOR_16)) - { - sector = FLASH_SECTOR_16; - } - else if ((Address < ADDR_FLASH_SECTOR_18) && (Address >= ADDR_FLASH_SECTOR_17)) - { - sector = FLASH_SECTOR_17; - } - else if ((Address < ADDR_FLASH_SECTOR_19) && (Address >= ADDR_FLASH_SECTOR_18)) - { - sector = FLASH_SECTOR_18; - } - else if ((Address < ADDR_FLASH_SECTOR_20) && (Address >= ADDR_FLASH_SECTOR_19)) - { - sector = FLASH_SECTOR_19; - } - else if ((Address < ADDR_FLASH_SECTOR_21) && (Address >= ADDR_FLASH_SECTOR_20)) - { - sector = FLASH_SECTOR_20; - } - else if ((Address < ADDR_FLASH_SECTOR_22) && (Address >= ADDR_FLASH_SECTOR_21)) - { - sector = FLASH_SECTOR_21; + FLASH_OBProgramInitTypeDef OBInit; + uint32_t nbank = 0; + + //get duel bank ability:nDBANK(Bit29) + HAL_FLASHEx_OBGetConfig(&OBInit); + nbank = ((OBInit.USERConfig & 0x20000000U) >> 29); + //1:single bank mode + if (1 == nbank) + { + if ((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0)) + { + sector = FLASH_SECTOR_0; + } + else if ((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1)) + { + sector = FLASH_SECTOR_1; + } + else if ((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2)) + { + sector = FLASH_SECTOR_2; + } + else if ((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3)) + { + sector = FLASH_SECTOR_3; + } + else if ((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4)) + { + sector = FLASH_SECTOR_4; + } + else if ((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5)) + { + sector = FLASH_SECTOR_5; + } + else if ((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6)) + { + sector = FLASH_SECTOR_6; + } + else if ((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7)) + { + sector = FLASH_SECTOR_7; + } + else if ((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8)) + { + sector = FLASH_SECTOR_8; + } + else if ((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9)) + { + sector = FLASH_SECTOR_9; + } + else if ((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10)) + { + sector = FLASH_SECTOR_10; + } + else + { + sector = FLASH_SECTOR_11; + } } - else if ((Address < ADDR_FLASH_SECTOR_23) && (Address >= ADDR_FLASH_SECTOR_22)) - { - sector = FLASH_SECTOR_22; - } -#else - else + else //0:dual bank mode { -#if (FLASH_SECTOR_TOTAL == 4) - sector = FLASH_SECTOR_4; -#elif (FLASH_SECTOR_TOTAL == 8) - sector = FLASH_SECTOR_8; -#elif (FLASH_SECTOR_TOTAL == 24) - sector = FLASH_SECTOR_23; -#endif + LOG_E("rtthread doesn't support duel bank mode yet!"); + RT_ASSERT(0); } -#endif -#else +#else //no dual bank ability if ((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0)) { sector = FLASH_SECTOR_0; @@ -186,7 +117,6 @@ static rt_uint32_t GetSector(rt_uint32_t Address) { sector = FLASH_SECTOR_1; } -#if (FLASH_SECTOR_TOTAL >= 4) else if ((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2)) { sector = FLASH_SECTOR_2; @@ -195,7 +125,6 @@ static rt_uint32_t GetSector(rt_uint32_t Address) { sector = FLASH_SECTOR_3; } -#elif (FLASH_SECTOR_TOTAL >= 8) else if ((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4)) { sector = FLASH_SECTOR_4; @@ -212,7 +141,6 @@ static rt_uint32_t GetSector(rt_uint32_t Address) { sector = FLASH_SECTOR_7; } -#elif (FLASH_SECTOR_TOTAL >= 24) else if ((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8)) { sector = FLASH_SECTOR_8; @@ -225,22 +153,15 @@ static rt_uint32_t GetSector(rt_uint32_t Address) { sector = FLASH_SECTOR_10; } -#else - else + else { -#if (FLASH_SECTOR_TOTAL == 4) - sector = FLASH_SECTOR_4; -#elif (FLASH_SECTOR_TOTAL == 8) - sector = FLASH_SECTOR_8; -#elif (FLASH_SECTOR_TOTAL == 24) sector = FLASH_SECTOR_11; -#endif } -#endif #endif return sector; } + /** * Read data from flash. * @note This operation's units is word. @@ -386,6 +307,13 @@ __exit: } #if defined(PKG_USING_FAL) +#define FLASH_SIZE_GRANULARITY_32K (4 * 32 * 1024) +#define FLASH_SIZE_GRANULARITY_128K (128 * 1024) +#define FLASH_SIZE_GRANULARITY_256K (7 * 256 *1024) + +#define STM32_FLASH_START_ADRESS_32K (STM32_FLASH_START_ADRESS) +#define STM32_FLASH_START_ADRESS_128K (STM32_FLASH_START_ADRESS_32K + FLASH_SIZE_GRANULARITY_32K) +#define STM32_FLASH_START_ADRESS_256K (STM32_FLASH_START_ADRESS_128K + FLASH_SIZE_GRANULARITY_128K) static int fal_flash_read_32k(long offset, rt_uint8_t *buf, size_t size); static int fal_flash_read_128k(long offset, rt_uint8_t *buf, size_t size); diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c b/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c index 3f6de0286f2685b3382102ba09851c366c858696..2ebd013edd8bed60408bf9a6117d2a1a8d511a05 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c @@ -254,6 +254,11 @@ void turn_on_lcd_backlight(void) rt_pin_write(LCD_DISP_GPIO_NUM, PIN_HIGH); rt_pin_write(LCD_BL_GPIO_NUM, PIN_HIGH); +} +#else +void turn_on_lcd_backlight(void) +{ + } #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_pm.c b/bsp/stm32/libraries/HAL_Drivers/drv_pm.c index 84ddf6cd4121b8065e823e394c67fb00b7edcdcf..8f3890474e3d1d0988c2e0c7eb8ea485f96f580d 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_pm.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_pm.c @@ -95,11 +95,13 @@ static void run(struct rt_pm *pm, uint8_t mode) { case PM_RUN_MODE_HIGH_SPEED: case PM_RUN_MODE_NORMAL_SPEED: + HAL_PWREx_DisableLowPowerRunMode(); SystemClock_80M(); /* Configure the main internal regulator output voltage (Range1 by default)*/ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); break; case PM_RUN_MODE_MEDIUM_SPEED: + HAL_PWREx_DisableLowPowerRunMode(); SystemClock_24M(); /* Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE2); diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c b/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c index 2c2af0dcc0da9d7e97058e8740bcbc8c4cec347b..23efb88df6459d093d6f194794192dead887e2ca 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c @@ -205,7 +205,7 @@ static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration tim_clock = HAL_RCC_GetPCLK1Freq() * 2; #endif } - + if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV2) { tim_clock = tim_clock / 2; @@ -323,9 +323,9 @@ static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device) tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; #endif - if (HAL_TIM_Base_Init(tim) != HAL_OK) + if (HAL_TIM_PWM_Init(tim) != HAL_OK) { - LOG_E("%s time base init failed", device->name); + LOG_E("%s pwm init failed", device->name); result = -RT_ERROR; goto __exit; } @@ -338,13 +338,6 @@ static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device) goto __exit; } - if (HAL_TIM_PWM_Init(tim) != HAL_OK) - { - LOG_E("%s pwm init failed", device->name); - result = -RT_ERROR; - goto __exit; - } - master_config.MasterOutputTrigger = TIM_TRGO_RESET; master_config.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; if (HAL_TIMEx_MasterConfigSynchronization(tim, &master_config) != HAL_OK) @@ -358,6 +351,8 @@ static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device) oc_config.Pulse = 0; oc_config.OCPolarity = TIM_OCPOLARITY_HIGH; oc_config.OCFastMode = TIM_OCFAST_DISABLE; + oc_config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + oc_config.OCIdleState = TIM_OCIDLESTATE_RESET; /* config pwm channel */ if (device->channel & 0x01) @@ -551,7 +546,6 @@ static int stm32_pwm_init(void) /* register pwm device */ if (rt_device_pwm_register(&stm32_pwm_obj[i].pwm_device, stm32_pwm_obj[i].name, &drv_ops, &stm32_pwm_obj[i].tim_handle) == RT_EOK) { - LOG_D("%s register success", stm32_pwm_obj[i].name); } else diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c index 993e4cbc1a893fd35d576c7ee479454f0b1dd173..914691d2becc61f5385edc9a8d23accb1809a8f6 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c +++ b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c @@ -8,6 +8,7 @@ * 2018-11-5 SummerGift first version * 2018-12-11 greedyhao Porting for stm32f7xx * 2019-01-03 zylx modify DMA initialization and spixfer function + * 2020-01-15 whj4674672 Porting for stm32h7xx */ #include "board.h" @@ -147,6 +148,8 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) SPI_APB_CLOCK = HAL_RCC_GetPCLK1Freq(); +#elif defined(SOC_SERIES_STM32H7) + SPI_APB_CLOCK = HAL_RCC_GetSysClockFreq(); #else SPI_APB_CLOCK = HAL_RCC_GetPCLK2Freq(); #endif @@ -205,6 +208,20 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur spi_handle->State = HAL_SPI_STATE_RESET; #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0) spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE; +#elif defined(SOC_SERIES_STM32H7) + spi_handle->Init.Mode = SPI_MODE_MASTER; + spi_handle->Init.NSS = SPI_NSS_SOFT; + spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE; + spi_handle->Init.NSSPolarity = SPI_NSS_POLARITY_LOW; + spi_handle->Init.CRCPolynomial = 7; + spi_handle->Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; + spi_handle->Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; + spi_handle->Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; + spi_handle->Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE; + spi_handle->Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; + spi_handle->Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE; + spi_handle->Init.IOSwap = SPI_IO_SWAP_DISABLE; + spi_handle->Init.FifoThreshold = SPI_FIFO_THRESHOLD_08DATA; #endif if (HAL_SPI_Init(spi_handle) != HAL_OK) diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c b/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c new file mode 100644 index 0000000000000000000000000000000000000000..680a93e7228f06bf683aad0e327dcbc8874107fb --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-10-30 ZYH the first version + * 2019-12-19 tyustli port to stm32 series + */ +#include "drv_usbh.h" +#include "board.h" + +static HCD_HandleTypeDef stm32_hhcd_fs; +static struct rt_completion urb_completion; +static volatile rt_bool_t connect_status = RT_FALSE; + +void OTG_FS_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_HCD_IRQHandler(&stm32_hhcd_fs); + rt_interrupt_leave(); +} + +void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) +{ + uhcd_t hcd = (uhcd_t)hhcd->pData; + if (!connect_status) + { + connect_status = RT_TRUE; + RT_DEBUG_LOG(RT_DEBUG_USB, ("usb connected\n")); + rt_usbh_root_hub_connect_handler(hcd, OTG_FS_PORT, RT_FALSE); + } +} + +void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) +{ + uhcd_t hcd = (uhcd_t)hhcd->pData; + if (connect_status) + { + connect_status = RT_FALSE; + RT_DEBUG_LOG(RT_DEBUG_USB, ("usb disconnnect\n")); + rt_usbh_root_hub_disconnect_handler(hcd, OTG_FS_PORT); + } +} + +void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) +{ + rt_completion_done(&urb_completion); +} + +static rt_err_t drv_reset_port(rt_uint8_t port) +{ + RT_DEBUG_LOG(RT_DEBUG_USB, ("reset port\n")); + HAL_HCD_ResetPort(&stm32_hhcd_fs); + return RT_EOK; +} + +static int drv_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts) +{ + int timeout = timeouts; + + while (1) + { + if (!connect_status) + { + return -1; + } + rt_completion_init(&urb_completion); + HAL_HCD_HC_SubmitRequest(&stm32_hhcd_fs, + pipe->pipe_index, + (pipe->ep.bEndpointAddress & 0x80) >> 7, + pipe->ep.bmAttributes, + token, + buffer, + nbytes, + 0); + rt_completion_wait(&urb_completion, timeout); + rt_thread_mdelay(1); + if (HAL_HCD_HC_GetState(&stm32_hhcd_fs, pipe->pipe_index) == HC_NAK) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nak\n")); + if (pipe->ep.bmAttributes == USB_EP_ATTR_INT) + { + rt_thread_delay((pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) > 0 ? (pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) : 1); + } + HAL_HCD_HC_Halt(&stm32_hhcd_fs, pipe->pipe_index); + HAL_HCD_HC_Init(&stm32_hhcd_fs, + pipe->pipe_index, + pipe->ep.bEndpointAddress, + pipe->inst->address, + USB_OTG_SPEED_FULL, + pipe->ep.bmAttributes, + pipe->ep.wMaxPacketSize); + continue; + } + else if (HAL_HCD_HC_GetState(&stm32_hhcd_fs, pipe->pipe_index) == HC_STALL) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("stall\n")); + pipe->status = UPIPE_STATUS_STALL; + if (pipe->callback != RT_NULL) + { + pipe->callback(pipe); + } + return -1; + } + else if (HAL_HCD_HC_GetState(&stm32_hhcd_fs, pipe->pipe_index) == URB_ERROR) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("error\n")); + pipe->status = UPIPE_STATUS_ERROR; + if (pipe->callback != RT_NULL) + { + pipe->callback(pipe); + } + return -1; + } + else if(URB_DONE == HAL_HCD_HC_GetURBState(&stm32_hhcd_fs, pipe->pipe_index)) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("ok\n")); + pipe->status = UPIPE_STATUS_OK; + if (pipe->callback != RT_NULL) + { + pipe->callback(pipe); + } + size_t size = HAL_HCD_HC_GetXferCount(&stm32_hhcd_fs, pipe->pipe_index); + if (pipe->ep.bEndpointAddress & 0x80) + { + return size; + } + else if (pipe->ep.bEndpointAddress & 0x00) + { + return size; + } + return nbytes; + } + + continue; + } +} + +static rt_uint16_t pipe_index = 0; +static rt_uint8_t drv_get_free_pipe_index(void) +{ + rt_uint8_t idx; + for (idx = 1; idx < 16; idx++) + { + if (!(pipe_index & (0x01 << idx))) + { + pipe_index |= (0x01 << idx); + return idx; + } + } + return 0xff; +} + +static void drv_free_pipe_index(rt_uint8_t index) +{ + pipe_index &= ~(0x01 << index); +} + +static rt_err_t drv_open_pipe(upipe_t pipe) +{ + pipe->pipe_index = drv_get_free_pipe_index(); + HAL_HCD_HC_Init(&stm32_hhcd_fs, + pipe->pipe_index, + pipe->ep.bEndpointAddress, + pipe->inst->address, + USB_OTG_SPEED_FULL, + pipe->ep.bmAttributes, + pipe->ep.wMaxPacketSize); + /* Set DATA0 PID token*/ + if (stm32_hhcd_fs.hc[pipe->pipe_index].ep_is_in) + { + stm32_hhcd_fs.hc[pipe->pipe_index].toggle_in = 0; + } + else + { + stm32_hhcd_fs.hc[pipe->pipe_index].toggle_out = 0; + } + return RT_EOK; +} + +static rt_err_t drv_close_pipe(upipe_t pipe) +{ + HAL_HCD_HC_Halt(&stm32_hhcd_fs, pipe->pipe_index); + drv_free_pipe_index(pipe->pipe_index); + return RT_EOK; +} + +static struct uhcd_ops _uhcd_ops = +{ + drv_reset_port, + drv_pipe_xfer, + drv_open_pipe, + drv_close_pipe, +}; + +static rt_err_t stm32_hcd_init(rt_device_t device) +{ + HCD_HandleTypeDef *hhcd = (HCD_HandleTypeDef *)device->user_data; + hhcd->Instance = USB_OTG_FS; + hhcd->Init.Host_channels = 8; + hhcd->Init.speed = HCD_SPEED_FULL; + hhcd->Init.dma_enable = DISABLE; + hhcd->Init.phy_itface = HCD_PHY_EMBEDDED; + hhcd->Init.Sof_enable = DISABLE; + RT_ASSERT(HAL_HCD_Init(hhcd) == HAL_OK); + HAL_HCD_Start(hhcd); +#ifdef USBH_USING_CONTROLLABLE_POWER + rt_pin_mode(USBH_POWER_PIN, PIN_MODE_OUTPUT); + rt_pin_write(USBH_POWER_PIN, PIN_LOW); +#endif + return RT_EOK; +} + +int stm_usbh_register(void) +{ + rt_err_t res = -RT_ERROR; + + uhcd_t uhcd = (uhcd_t)rt_malloc(sizeof(struct uhcd)); + if (uhcd == RT_NULL) + { + rt_kprintf("uhcd malloc failed\r\n"); + return -RT_ERROR; + } + + rt_memset((void *)uhcd, 0, sizeof(struct uhcd)); + + uhcd->parent.type = RT_Device_Class_USBHost; + uhcd->parent.init = stm32_hcd_init; + uhcd->parent.user_data = &stm32_hhcd_fs; + + uhcd->ops = &_uhcd_ops; + uhcd->num_ports = OTG_FS_PORT; + stm32_hhcd_fs.pData = uhcd; + + res = rt_device_register(&uhcd->parent, "usbh", RT_DEVICE_FLAG_DEACTIVATE); + if (res != RT_EOK) + { + rt_kprintf("register usb host failed res = %d\r\n", res); + return -RT_ERROR; + } + + rt_usb_host_init(); + + return RT_EOK; +} +INIT_DEVICE_EXPORT(stm_usbh_register); diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usbh.h b/bsp/stm32/libraries/HAL_Drivers/drv_usbh.h new file mode 100644 index 0000000000000000000000000000000000000000..e08f482f2852310485489486e4b391a7b5e43d4f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drv_usbh.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-12-12 ZYH the first version + * 2019-12-19 tyustli port to stm32 series + */ +#ifndef __DRV_USBH_H__ +#define __DRV_USBH_H__ +#include + +#define OTG_FS_PORT 1 + +int stm_usbh_register(void); + +#endif + +/************* end of file ************/ diff --git a/bsp/stm32/libraries/STM32F1xx_HAL/SConscript b/bsp/stm32/libraries/STM32F1xx_HAL/SConscript index af0704c81e60d0fd16fcc27927aafbb55ab9280e..ff87a4aa25ca7d56b4b2d61be956617b177d9d63 100644 --- a/bsp/stm32/libraries/STM32F1xx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32F1xx_HAL/SConscript @@ -16,7 +16,6 @@ STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cec.c -STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c """) @@ -75,6 +74,10 @@ if GetDepend(['RT_USING_MTD_NOR']): if GetDepend(['RT_USING_MTD_NAND']): src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c'] +if GetDepend(['BSP_USING_EXT_SRAM']): + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c'] + src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c'] + if GetDepend(['BSP_USING_ON_CHIP_FLASH']): src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c'] src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c'] diff --git a/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g431xx.s b/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g431xx.s index be5cc3fc227834088a88a6f1ea907a31fa0e0a78..895acc38c709497d261c3da6b3e1e475bac67913 100644 --- a/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g431xx.s +++ b/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g431xx.s @@ -79,7 +79,7 @@ LoopCopyDataInit: adds r4, r0, r3 cmp r4, r1 bcc CopyDataInit - + /* Zero fill the bss segment. */ ldr r2, =_sbss ldr r4, =_ebss @@ -97,9 +97,9 @@ LoopFillZerobss: /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ - bl __libc_init_array +/* bl __libc_init_array */ /* Call the application's entry point.*/ - bl main + bl entry LoopForever: b LoopForever diff --git a/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g441xx.s b/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g441xx.s index dc621f9ad9093604726da512172572e56a18cf3f..cc8cb00ce9a69b29765e3b0010847c122f1b3aa9 100644 --- a/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g441xx.s +++ b/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g441xx.s @@ -79,7 +79,7 @@ LoopCopyDataInit: adds r4, r0, r3 cmp r4, r1 bcc CopyDataInit - + /* Zero fill the bss segment. */ ldr r2, =_sbss ldr r4, =_ebss @@ -97,9 +97,9 @@ LoopFillZerobss: /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ - bl __libc_init_array +/* bl __libc_init_array */ /* Call the application's entry point.*/ - bl main + bl entry LoopForever: b LoopForever diff --git a/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g471xx.s b/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g471xx.s index 918ebee877854772bfbb42f7bea25a2b28aea68d..3924adbc0ab1abcac87374bb584f46f1c4d3cd9a 100644 --- a/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g471xx.s +++ b/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g471xx.s @@ -79,7 +79,7 @@ LoopCopyDataInit: adds r4, r0, r3 cmp r4, r1 bcc CopyDataInit - + /* Zero fill the bss segment. */ ldr r2, =_sbss ldr r4, =_ebss @@ -97,9 +97,9 @@ LoopFillZerobss: /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ - bl __libc_init_array +/* bl __libc_init_array */ /* Call the application's entry point.*/ - bl main + bl entry LoopForever: b LoopForever diff --git a/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g473xx.s b/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g473xx.s index 3b10aeb6ed24e6a5dad919b87839a564f248275c..86e0db30ec7f8114121cd04761f19c516eed612c 100644 --- a/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g473xx.s +++ b/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g473xx.s @@ -79,7 +79,7 @@ LoopCopyDataInit: adds r4, r0, r3 cmp r4, r1 bcc CopyDataInit - + /* Zero fill the bss segment. */ ldr r2, =_sbss ldr r4, =_ebss @@ -97,9 +97,9 @@ LoopFillZerobss: /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ - bl __libc_init_array +/* bl __libc_init_array */ /* Call the application's entry point.*/ - bl main + bl entry LoopForever: b LoopForever diff --git a/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g474xx.s b/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g474xx.s index 2b39625b656054281b4d51d4e407f8ee3f90c2d3..8a418820c3bf9d595d867300ef3cc700414f9dc9 100644 --- a/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g474xx.s +++ b/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g474xx.s @@ -79,7 +79,7 @@ LoopCopyDataInit: adds r4, r0, r3 cmp r4, r1 bcc CopyDataInit - + /* Zero fill the bss segment. */ ldr r2, =_sbss ldr r4, =_ebss @@ -97,9 +97,9 @@ LoopFillZerobss: /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ - bl __libc_init_array +/* bl __libc_init_array */ /* Call the application's entry point.*/ - bl main + bl entry LoopForever: b LoopForever diff --git a/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g483xx.s b/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g483xx.s index 15e3ca13214017f72fcf159eca02715c9b520790..c6c52988de48f8aabb398f02fa1fd1d34e1221b7 100644 --- a/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g483xx.s +++ b/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g483xx.s @@ -79,7 +79,7 @@ LoopCopyDataInit: adds r4, r0, r3 cmp r4, r1 bcc CopyDataInit - + /* Zero fill the bss segment. */ ldr r2, =_sbss ldr r4, =_ebss @@ -97,9 +97,9 @@ LoopFillZerobss: /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ - bl __libc_init_array +/* bl __libc_init_array */ /* Call the application's entry point.*/ - bl main + bl entry LoopForever: b LoopForever diff --git a/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g484xx.s b/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g484xx.s index be0640457eceb9a4257ea2f388620143d95a8810..42d8b4c3a0554f0a9209eae1844000b42098dbda 100644 --- a/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g484xx.s +++ b/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g484xx.s @@ -78,7 +78,7 @@ LoopCopyDataInit: adds r4, r0, r3 cmp r4, r1 bcc CopyDataInit - + /* Zero fill the bss segment. */ ldr r2, =_sbss ldr r4, =_ebss @@ -96,9 +96,9 @@ LoopFillZerobss: /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ - bl __libc_init_array +/* bl __libc_init_array */ /* Call the application's entry point.*/ - bl main + bl entry LoopForever: b LoopForever diff --git a/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32gbk1cb.s b/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32gbk1cb.s index f302f42735c614c8f7e3dbdf1c4bfea08a13a4ab..ae2df5a669ae8b1b21e3f8aba069bfff687a4482 100644 --- a/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32gbk1cb.s +++ b/bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32gbk1cb.s @@ -93,9 +93,9 @@ LoopFillZerobss: /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ - bl __libc_init_array +/* bl __libc_init_array */ /* Call the application's entry point.*/ - bl main + bl entry LoopForever: b LoopForever diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/.mxproject index b231b540b362ccc8366672afc62ca55a32622d39..1e1060294c9086bf09e2870d4681c9e79064fde0 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/.mxproject @@ -5,10 +5,10 @@ SourcePath=F:/rt-thread/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Sr SourceFiles=stm32f1xx_it.c;stm32f1xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; +LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_sdmmc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sd.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_sdmmc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sd.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; [PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;..\\Src/system_stm32f1xx.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;..\\Src/system_stm32f1xx.c;..\Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;; +SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;..\\Src/system_stm32f1xx.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;..\Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;..\\Src/system_stm32f1xx.c;..\Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;; HeaderPath=..\Drivers\STM32F1xx_HAL_Driver\Inc;..\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F1xx\Include;..\Drivers\CMSIS\Include;..\Inc; CDefines=USE_HAL_DRIVER;STM32F103xE;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/CubeMX_Config.ioc index bee20f092636dd0ae539d53bf449849c646a134a..ab50887fd8619021cd5e66be04a2b2470d9b3730 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/CubeMX_Config.ioc @@ -1,27 +1,80 @@ #MicroXplorer Configuration settings - do not modify +FSMC.AddressSetupTime1=0 +FSMC.BusTurnAroundDuration1=0 +FSMC.DataSetupTime1=3 +FSMC.IPParameters=AddressSetupTime1,DataSetupTime1,BusTurnAroundDuration1,WriteOperation1 +FSMC.WriteOperation1=FSMC_WRITE_OPERATION_ENABLE File.Version=6 KeepUserPlacement=false Mcu.Family=STM32F1 -Mcu.IP0=NVIC -Mcu.IP1=RCC -Mcu.IP2=SYS -Mcu.IP3=TIM3 -Mcu.IP4=USART1 -Mcu.IPNb=5 +Mcu.IP0=FSMC +Mcu.IP1=NVIC +Mcu.IP2=RCC +Mcu.IP3=SDIO +Mcu.IP4=SYS +Mcu.IP5=TIM3 +Mcu.IP6=USART1 +Mcu.IPNb=7 Mcu.Name=STM32F103Z(C-D-E)Tx Mcu.Package=LQFP144 Mcu.Pin0=PC14-OSC32_IN Mcu.Pin1=PC15-OSC32_OUT -Mcu.Pin10=VP_SYS_VS_Systick -Mcu.Pin2=OSC_IN -Mcu.Pin3=OSC_OUT -Mcu.Pin4=PC6 -Mcu.Pin5=PC7 -Mcu.Pin6=PA9 -Mcu.Pin7=PA10 -Mcu.Pin8=PA13 -Mcu.Pin9=PA14 -Mcu.PinsNb=11 +Mcu.Pin10=PF12 +Mcu.Pin11=PF13 +Mcu.Pin12=PF14 +Mcu.Pin13=PF15 +Mcu.Pin14=PG0 +Mcu.Pin15=PG1 +Mcu.Pin16=PE7 +Mcu.Pin17=PE8 +Mcu.Pin18=PE9 +Mcu.Pin19=PE10 +Mcu.Pin2=PF0 +Mcu.Pin20=PE11 +Mcu.Pin21=PE12 +Mcu.Pin22=PE13 +Mcu.Pin23=PE14 +Mcu.Pin24=PE15 +Mcu.Pin25=PD8 +Mcu.Pin26=PD9 +Mcu.Pin27=PD10 +Mcu.Pin28=PD11 +Mcu.Pin29=PD12 +Mcu.Pin3=PF1 +Mcu.Pin30=PD13 +Mcu.Pin31=PD14 +Mcu.Pin32=PD15 +Mcu.Pin33=PG2 +Mcu.Pin34=PG3 +Mcu.Pin35=PG4 +Mcu.Pin36=PG5 +Mcu.Pin37=PC6 +Mcu.Pin38=PC7 +Mcu.Pin39=PC8 +Mcu.Pin4=PF2 +Mcu.Pin40=PC9 +Mcu.Pin41=PA9 +Mcu.Pin42=PA10 +Mcu.Pin43=PA13 +Mcu.Pin44=PA14 +Mcu.Pin45=PC10 +Mcu.Pin46=PC11 +Mcu.Pin47=PC12 +Mcu.Pin48=PD0 +Mcu.Pin49=PD1 +Mcu.Pin5=PF3 +Mcu.Pin50=PD2 +Mcu.Pin51=PD4 +Mcu.Pin52=PD5 +Mcu.Pin53=PG10 +Mcu.Pin54=PE0 +Mcu.Pin55=PE1 +Mcu.Pin56=VP_SYS_VS_Systick +Mcu.Pin6=PF4 +Mcu.Pin7=PF5 +Mcu.Pin8=OSC_IN +Mcu.Pin9=OSC_OUT +Mcu.PinsNb=57 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F103ZETx @@ -50,6 +103,12 @@ PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK PA9.Mode=Asynchronous PA9.Signal=USART1_TX +PC10.Mode=SD_4_bits_Wide_bus +PC10.Signal=SDIO_D2 +PC11.Mode=SD_4_bits_Wide_bus +PC11.Signal=SDIO_D3 +PC12.Mode=SD_4_bits_Wide_bus +PC12.Signal=SDIO_CK PC14-OSC32_IN.Mode=LSE-External-Oscillator PC14-OSC32_IN.Signal=RCC_OSC32_IN PC15-OSC32_OUT.Mode=LSE-External-Oscillator @@ -58,6 +117,10 @@ PC6.Locked=true PC6.Signal=S_TIM3_CH1 PC7.Locked=true PC7.Signal=S_TIM3_CH2 +PC8.Mode=SD_4_bits_Wide_bus +PC8.Signal=SDIO_D0 +PC9.Mode=SD_4_bits_Wide_bus +PC9.Signal=SDIO_D1 PCC.Checker=false PCC.Line=STM32F103 PCC.MCU=STM32F103Z(C-D-E)Tx @@ -66,6 +129,51 @@ PCC.Seq0=0 PCC.Series=STM32F1 PCC.Temperature=25 PCC.Vdd=3.3 +PD0.Signal=FSMC_D2_DA2 +PD1.Signal=FSMC_D3_DA3 +PD10.Signal=FSMC_D15_DA15 +PD11.Signal=FSMC_A16_CLE +PD12.Signal=FSMC_A17_ALE +PD13.Signal=FSMC_A18 +PD14.Signal=FSMC_D0_DA0 +PD15.Signal=FSMC_D1_DA1 +PD2.Mode=SD_4_bits_Wide_bus +PD2.Signal=SDIO_CMD +PD4.Signal=FSMC_NOE +PD5.Signal=FSMC_NWE +PD8.Signal=FSMC_D13_DA13 +PD9.Signal=FSMC_D14_DA14 +PE0.Locked=true +PE0.Signal=FSMC_NBL0 +PE1.Locked=true +PE1.Signal=FSMC_NBL1 +PE10.Signal=FSMC_D7_DA7 +PE11.Signal=FSMC_D8_DA8 +PE12.Signal=FSMC_D9_DA9 +PE13.Signal=FSMC_D10_DA10 +PE14.Signal=FSMC_D11_DA11 +PE15.Signal=FSMC_D12_DA12 +PE7.Signal=FSMC_D4_DA4 +PE8.Signal=FSMC_D5_DA5 +PE9.Signal=FSMC_D6_DA6 +PF0.Signal=FSMC_A0 +PF1.Signal=FSMC_A1 +PF12.Signal=FSMC_A6 +PF13.Signal=FSMC_A7 +PF14.Signal=FSMC_A8 +PF15.Signal=FSMC_A9 +PF2.Signal=FSMC_A2 +PF3.Signal=FSMC_A3 +PF4.Signal=FSMC_A4 +PF5.Signal=FSMC_A5 +PG0.Signal=FSMC_A10 +PG1.Signal=FSMC_A11 +PG10.Mode=NorPsramChipSelect3_1 +PG10.Signal=FSMC_NE3 +PG2.Signal=FSMC_A12 +PG3.Signal=FSMC_A13 +PG4.Signal=FSMC_A14 +PG5.Signal=FSMC_A15 PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=false @@ -93,7 +201,7 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=MDK-ARM V5 ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_TIM8_Init-TIM8-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_FSMC_Init-FSMC-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true RCC.ADCFreqValue=36000000 RCC.AHBFreq_Value=72000000 RCC.APB1CLKDivider=RCC_HCLK_DIV2 @@ -120,6 +228,86 @@ RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.TimSysFreq_Value=72000000 RCC.USBFreq_Value=72000000 RCC.VCOOutput2Freq_Value=8000000 +SDIO.ClockDiv=0 +SDIO.IPParameters=ClockDiv +SH.FSMC_A0.0=FSMC_A0,19b-a1 +SH.FSMC_A0.ConfNb=1 +SH.FSMC_A1.0=FSMC_A1,19b-a1 +SH.FSMC_A1.ConfNb=1 +SH.FSMC_A10.0=FSMC_A10,19b-a1 +SH.FSMC_A10.ConfNb=1 +SH.FSMC_A11.0=FSMC_A11,19b-a1 +SH.FSMC_A11.ConfNb=1 +SH.FSMC_A12.0=FSMC_A12,19b-a1 +SH.FSMC_A12.ConfNb=1 +SH.FSMC_A13.0=FSMC_A13,19b-a1 +SH.FSMC_A13.ConfNb=1 +SH.FSMC_A14.0=FSMC_A14,19b-a1 +SH.FSMC_A14.ConfNb=1 +SH.FSMC_A15.0=FSMC_A15,19b-a1 +SH.FSMC_A15.ConfNb=1 +SH.FSMC_A16_CLE.0=FSMC_A16,19b-a1 +SH.FSMC_A16_CLE.ConfNb=1 +SH.FSMC_A17_ALE.0=FSMC_A17,19b-a1 +SH.FSMC_A17_ALE.ConfNb=1 +SH.FSMC_A18.0=FSMC_A18,19b-a1 +SH.FSMC_A18.ConfNb=1 +SH.FSMC_A2.0=FSMC_A2,19b-a1 +SH.FSMC_A2.ConfNb=1 +SH.FSMC_A3.0=FSMC_A3,19b-a1 +SH.FSMC_A3.ConfNb=1 +SH.FSMC_A4.0=FSMC_A4,19b-a1 +SH.FSMC_A4.ConfNb=1 +SH.FSMC_A5.0=FSMC_A5,19b-a1 +SH.FSMC_A5.ConfNb=1 +SH.FSMC_A6.0=FSMC_A6,19b-a1 +SH.FSMC_A6.ConfNb=1 +SH.FSMC_A7.0=FSMC_A7,19b-a1 +SH.FSMC_A7.ConfNb=1 +SH.FSMC_A8.0=FSMC_A8,19b-a1 +SH.FSMC_A8.ConfNb=1 +SH.FSMC_A9.0=FSMC_A9,19b-a1 +SH.FSMC_A9.ConfNb=1 +SH.FSMC_D0_DA0.0=FSMC_D0,16b-d1 +SH.FSMC_D0_DA0.ConfNb=1 +SH.FSMC_D10_DA10.0=FSMC_D10,16b-d1 +SH.FSMC_D10_DA10.ConfNb=1 +SH.FSMC_D11_DA11.0=FSMC_D11,16b-d1 +SH.FSMC_D11_DA11.ConfNb=1 +SH.FSMC_D12_DA12.0=FSMC_D12,16b-d1 +SH.FSMC_D12_DA12.ConfNb=1 +SH.FSMC_D13_DA13.0=FSMC_D13,16b-d1 +SH.FSMC_D13_DA13.ConfNb=1 +SH.FSMC_D14_DA14.0=FSMC_D14,16b-d1 +SH.FSMC_D14_DA14.ConfNb=1 +SH.FSMC_D15_DA15.0=FSMC_D15,16b-d1 +SH.FSMC_D15_DA15.ConfNb=1 +SH.FSMC_D1_DA1.0=FSMC_D1,16b-d1 +SH.FSMC_D1_DA1.ConfNb=1 +SH.FSMC_D2_DA2.0=FSMC_D2,16b-d1 +SH.FSMC_D2_DA2.ConfNb=1 +SH.FSMC_D3_DA3.0=FSMC_D3,16b-d1 +SH.FSMC_D3_DA3.ConfNb=1 +SH.FSMC_D4_DA4.0=FSMC_D4,16b-d1 +SH.FSMC_D4_DA4.ConfNb=1 +SH.FSMC_D5_DA5.0=FSMC_D5,16b-d1 +SH.FSMC_D5_DA5.ConfNb=1 +SH.FSMC_D6_DA6.0=FSMC_D6,16b-d1 +SH.FSMC_D6_DA6.ConfNb=1 +SH.FSMC_D7_DA7.0=FSMC_D7,16b-d1 +SH.FSMC_D7_DA7.ConfNb=1 +SH.FSMC_D8_DA8.0=FSMC_D8,16b-d1 +SH.FSMC_D8_DA8.ConfNb=1 +SH.FSMC_D9_DA9.0=FSMC_D9,16b-d1 +SH.FSMC_D9_DA9.ConfNb=1 +SH.FSMC_NBL0.0=FSMC_NBL0 +SH.FSMC_NBL0.ConfNb=1 +SH.FSMC_NBL1.0=FSMC_NBL1 +SH.FSMC_NBL1.ConfNb=1 +SH.FSMC_NOE.0=FSMC_NOE,Sram1 +SH.FSMC_NOE.ConfNb=1 +SH.FSMC_NWE.0=FSMC_NWE,Sram1 +SH.FSMC_NWE.ConfNb=1 SH.S_TIM3_CH1.0=TIM3_CH1,Encoder_Interface SH.S_TIM3_CH1.ConfNb=1 SH.S_TIM3_CH2.0=TIM3_CH2,Encoder_Interface diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h b/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h index 259acb159bd86c2042e8fca0c832f6afb9b290b8..b4720e93f0ef1361fabea46a567870a755ae00fe 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h @@ -57,12 +57,12 @@ /*#define HAL_PWR_MODULE_ENABLED */ /*#define HAL_RCC_MODULE_ENABLED */ /*#define HAL_RTC_MODULE_ENABLED */ -/*#define HAL_SD_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED /*#define HAL_MMC_MODULE_ENABLED */ /*#define HAL_SDRAM_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */ /*#define HAL_SPI_MODULE_ENABLED */ -/*#define HAL_SRAM_MODULE_ENABLED */ +#define HAL_SRAM_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED /*#define HAL_USART_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Src/main.c index 85ab28b8c93d50a14afed852c2d4f9bef8e380ea..ad22739b6c53262e725f40e163464fc6ea2029fd 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Src/main.c @@ -42,10 +42,14 @@ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ +SD_HandleTypeDef hsd; + TIM_HandleTypeDef htim3; UART_HandleTypeDef huart1; +SRAM_HandleTypeDef hsram1; + /* USER CODE BEGIN PV */ /* USER CODE END PV */ @@ -54,7 +58,9 @@ UART_HandleTypeDef huart1; void SystemClock_Config(void); static void MX_GPIO_Init(void); static void MX_USART1_UART_Init(void); +static void MX_FSMC_Init(void); static void MX_TIM3_Init(void); +static void MX_SDIO_SD_Init(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ @@ -94,7 +100,9 @@ int main(void) /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_USART1_UART_Init(); + MX_FSMC_Init(); MX_TIM3_Init(); + MX_SDIO_SD_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -147,6 +155,42 @@ void SystemClock_Config(void) } } +/** + * @brief SDIO Initialization Function + * @param None + * @retval None + */ +static void MX_SDIO_SD_Init(void) +{ + + /* USER CODE BEGIN SDIO_Init 0 */ + + /* USER CODE END SDIO_Init 0 */ + + /* USER CODE BEGIN SDIO_Init 1 */ + + /* USER CODE END SDIO_Init 1 */ + hsd.Instance = SDIO; + hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + hsd.Init.BusWide = SDIO_BUS_WIDE_1B; + hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + hsd.Init.ClockDiv = 0; + if (HAL_SD_Init(&hsd) != HAL_OK) + { + Error_Handler(); + } + if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SDIO_Init 2 */ + + /* USER CODE END SDIO_Init 2 */ + +} + /** * @brief TIM3 Initialization Function * @param None @@ -239,10 +283,71 @@ static void MX_GPIO_Init(void) /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); } +/* FSMC initialization function */ +static void MX_FSMC_Init(void) +{ + + /* USER CODE BEGIN FSMC_Init 0 */ + + /* USER CODE END FSMC_Init 0 */ + + FSMC_NORSRAM_TimingTypeDef Timing = {0}; + + /* USER CODE BEGIN FSMC_Init 1 */ + + /* USER CODE END FSMC_Init 1 */ + + /** Perform the SRAM1 memory initialization sequence + */ + hsram1.Instance = FSMC_NORSRAM_DEVICE; + hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; + /* hsram1.Init */ + hsram1.Init.NSBank = FSMC_NORSRAM_BANK3; + hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; + hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; + hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16; + hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; + hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; + hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; + hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; + hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; + hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; + hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE; + hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; + hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; + /* Timing */ + Timing.AddressSetupTime = 0; + Timing.AddressHoldTime = 15; + Timing.DataSetupTime = 3; + Timing.BusTurnAroundDuration = 0; + Timing.CLKDivision = 16; + Timing.DataLatency = 17; + Timing.AccessMode = FSMC_ACCESS_MODE_A; + /* ExtTiming */ + + if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK) + { + Error_Handler( ); + } + + /** Disconnect NADV + */ + + __HAL_AFIO_FSMCNADV_DISCONNECTED(); + + /* USER CODE BEGIN FSMC_Init 2 */ + + /* USER CODE END FSMC_Init 2 */ +} + /* USER CODE BEGIN 4 */ /* USER CODE END 4 */ diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c index ac85b3192ff4e8436d4853c3c4039822b08d704b..26c9270e6b749643b44fed54257dd8aaca8bc387 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c @@ -81,6 +81,87 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } +/** +* @brief SD MSP Initialization +* This function configures the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspInit(SD_HandleTypeDef* hsd) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspInit 0 */ + + /* USER CODE END SDIO_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDIO_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN SDIO_MspInit 1 */ + + /* USER CODE END SDIO_MspInit 1 */ + } + +} + +/** +* @brief SD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) +{ + if(hsd->Instance==SDIO) + { + /* USER CODE BEGIN SDIO_MspDeInit 0 */ + + /* USER CODE END SDIO_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDIO_CLK_DISABLE(); + + /**SDIO GPIO Configuration + PC8 ------> SDIO_D0 + PC9 ------> SDIO_D1 + PC10 ------> SDIO_D2 + PC11 ------> SDIO_D3 + PC12 ------> SDIO_CK + PD2 ------> SDIO_CMD + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* USER CODE BEGIN SDIO_MspDeInit 1 */ + + /* USER CODE END SDIO_MspDeInit 1 */ + } + +} + /** * @brief TIM_Encoder MSP Initialization * This function configures the hardware resources used in this example @@ -214,6 +295,190 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) } +static uint32_t FSMC_Initialized = 0; + +static void HAL_FSMC_MspInit(void){ + /* USER CODE BEGIN FSMC_MspInit 0 */ + + /* USER CODE END FSMC_MspInit 0 */ + GPIO_InitTypeDef GPIO_InitStruct ={0}; + if (FSMC_Initialized) { + return; + } + FSMC_Initialized = 1; + + /* Peripheral clock enable */ + __HAL_RCC_FSMC_CLK_ENABLE(); + + /** FSMC GPIO Configuration + PF0 ------> FSMC_A0 + PF1 ------> FSMC_A1 + PF2 ------> FSMC_A2 + PF3 ------> FSMC_A3 + PF4 ------> FSMC_A4 + PF5 ------> FSMC_A5 + PF12 ------> FSMC_A6 + PF13 ------> FSMC_A7 + PF14 ------> FSMC_A8 + PF15 ------> FSMC_A9 + PG0 ------> FSMC_A10 + PG1 ------> FSMC_A11 + PE7 ------> FSMC_D4 + PE8 ------> FSMC_D5 + PE9 ------> FSMC_D6 + PE10 ------> FSMC_D7 + PE11 ------> FSMC_D8 + PE12 ------> FSMC_D9 + PE13 ------> FSMC_D10 + PE14 ------> FSMC_D11 + PE15 ------> FSMC_D12 + PD8 ------> FSMC_D13 + PD9 ------> FSMC_D14 + PD10 ------> FSMC_D15 + PD11 ------> FSMC_A16 + PD12 ------> FSMC_A17 + PD13 ------> FSMC_A18 + PD14 ------> FSMC_D0 + PD15 ------> FSMC_D1 + PG2 ------> FSMC_A12 + PG3 ------> FSMC_A13 + PG4 ------> FSMC_A14 + PG5 ------> FSMC_A15 + PD0 ------> FSMC_D2 + PD1 ------> FSMC_D3 + PD4 ------> FSMC_NOE + PD5 ------> FSMC_NWE + PG10 ------> FSMC_NE3 + PE0 ------> FSMC_NBL0 + PE1 ------> FSMC_NBL1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13 + |GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 + |GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN FSMC_MspInit 1 */ + + /* USER CODE END FSMC_MspInit 1 */ +} + +void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){ + /* USER CODE BEGIN SRAM_MspInit 0 */ + + /* USER CODE END SRAM_MspInit 0 */ + HAL_FSMC_MspInit(); + /* USER CODE BEGIN SRAM_MspInit 1 */ + + /* USER CODE END SRAM_MspInit 1 */ +} + +static uint32_t FSMC_DeInitialized = 0; + +static void HAL_FSMC_MspDeInit(void){ + /* USER CODE BEGIN FSMC_MspDeInit 0 */ + + /* USER CODE END FSMC_MspDeInit 0 */ + if (FSMC_DeInitialized) { + return; + } + FSMC_DeInitialized = 1; + /* Peripheral clock enable */ + __HAL_RCC_FSMC_CLK_DISABLE(); + + /** FSMC GPIO Configuration + PF0 ------> FSMC_A0 + PF1 ------> FSMC_A1 + PF2 ------> FSMC_A2 + PF3 ------> FSMC_A3 + PF4 ------> FSMC_A4 + PF5 ------> FSMC_A5 + PF12 ------> FSMC_A6 + PF13 ------> FSMC_A7 + PF14 ------> FSMC_A8 + PF15 ------> FSMC_A9 + PG0 ------> FSMC_A10 + PG1 ------> FSMC_A11 + PE7 ------> FSMC_D4 + PE8 ------> FSMC_D5 + PE9 ------> FSMC_D6 + PE10 ------> FSMC_D7 + PE11 ------> FSMC_D8 + PE12 ------> FSMC_D9 + PE13 ------> FSMC_D10 + PE14 ------> FSMC_D11 + PE15 ------> FSMC_D12 + PD8 ------> FSMC_D13 + PD9 ------> FSMC_D14 + PD10 ------> FSMC_D15 + PD11 ------> FSMC_A16 + PD12 ------> FSMC_A17 + PD13 ------> FSMC_A18 + PD14 ------> FSMC_D0 + PD15 ------> FSMC_D1 + PG2 ------> FSMC_A12 + PG3 ------> FSMC_A13 + PG4 ------> FSMC_A14 + PG5 ------> FSMC_A15 + PD0 ------> FSMC_D2 + PD1 ------> FSMC_D3 + PD4 ------> FSMC_NOE + PD5 ------> FSMC_NWE + PG10 ------> FSMC_NE3 + PE0 ------> FSMC_NBL0 + PE1 ------> FSMC_NBL1 + */ + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13 + |GPIO_PIN_14|GPIO_PIN_15); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_10); + + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 + |GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); + + /* USER CODE BEGIN FSMC_MspDeInit 1 */ + + /* USER CODE END FSMC_MspDeInit 1 */ +} + +void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef* hsram){ + /* USER CODE BEGIN SRAM_MspDeInit 0 */ + + /* USER CODE END SRAM_MspDeInit 0 */ + HAL_FSMC_MspDeInit(); + /* USER CODE BEGIN SRAM_MspDeInit 1 */ + + /* USER CODE END SRAM_MspDeInit 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig b/bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig index aca91d47fc43dfe64e39997ef688262557a4855e..80ef1ab3a6cd7f96e68dcc6da94520a2fea3942e 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig @@ -34,6 +34,19 @@ menu "Onboard Peripheral Drivers" select BSP_USING_ADC1 default n + config BSP_USING_EXT_SRAM + bool "Enable external sram" + default n + help + Chip name is IS62WV51216, 1Mbytes static RAMs organized as 512K words by 16bits. + + config BSP_USING_SDCARD + bool "Enable SDCARD (sdio)" + select BSP_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n + endmenu menu "On-chip Peripheral Drivers" @@ -203,6 +216,11 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + default n + menuconfig BSP_USING_PULSE_ENCODER bool "Enable Pulse Encoder" default n diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/SConscript b/bsp/stm32/stm32f103-atk-warshipv3/board/SConscript index 0f7ccb024c64a206ee147a009d3a4b19400578f2..2df6ea752e84133b7f4304787941b2756ad0a9f8 100644 --- a/bsp/stm32/stm32f103-atk-warshipv3/board/SConscript +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/SConscript @@ -12,8 +12,15 @@ board.c CubeMX_Config/Src/stm32f1xx_hal_msp.c ''') +if GetDepend(['BSP_USING_EXT_SRAM']): + src += Glob('ports/drv_sram.c') + +if GetDepend(['BSP_USING_SDCARD']): + src += Glob('ports/sdcard_port.c') + path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] +path += [cwd + '/ports/include'] startup_path_prefix = SDK_LIB diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/drv_sram.c b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/drv_sram.c new file mode 100644 index 0000000000000000000000000000000000000000..c0b077e600919896e94e65b2abeee3a8695f5768 --- /dev/null +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/drv_sram.c @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-05 linyiyang first version + */ + +#include +#include +#include + +#ifdef BSP_USING_EXT_SRAM +#include + +#define DRV_DEBUG +#define LOG_TAG "drv.ext_sram" +#include + +static SRAM_HandleTypeDef hsram1; +#ifdef RT_USING_MEMHEAP_AS_HEAP +static struct rt_memheap system_heap; +#endif + +static int external_sram_init(void) +{ + int result = RT_EOK; + + FSMC_NORSRAM_TimingTypeDef Timing = {0}; + + /** Perform the SRAM1 memory initialization sequence + */ + hsram1.Instance = FSMC_NORSRAM_DEVICE; + hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; + + /* hsram1.Init */ + hsram1.Init.NSBank = FSMC_NORSRAM_BANK3; + hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; + hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; +#if EXTERNAL_SRAM_DATA_WIDTH == 8 + hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_8; +#elif EXTERNAL_SRAM_DATA_WIDTH == 16 + hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16; +#else + hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_32; +#endif + hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE; + hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; + hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; + hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; + hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; + hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; + hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE; + hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; + hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE; + + /* Timing */ + Timing.AddressSetupTime = 0; + Timing.AddressHoldTime = 15; + Timing.DataSetupTime = 3; + Timing.BusTurnAroundDuration = 0; + Timing.CLKDivision = 16; + Timing.DataLatency = 17; + Timing.AccessMode = FSMC_ACCESS_MODE_A; + /* ExtTiming */ + + /* Initialize the SRAM controller */ + if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK) + { + LOG_E("External SRAM init failed!"); + result = -RT_ERROR; + } + else + { + LOG_D("External sram init success, mapped at 0x%X, size is %d bytes, data width is %d", EXTERNAL_SRAM_BANK_ADDR, EXTERNAL_SRAM_SIZE, EXTERNAL_SRAM_DATA_WIDTH); +#ifdef RT_USING_MEMHEAP_AS_HEAP + /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */ + rt_memheap_init(&system_heap, "ext_sram", (void *)EXTERNAL_SRAM_BANK_ADDR, EXTERNAL_SRAM_SIZE); +#endif + } + + /** Disconnect NADV + */ + + __HAL_AFIO_FSMCNADV_DISCONNECTED(); + + return result; +} +INIT_BOARD_EXPORT(external_sram_init); + +#ifdef DRV_DEBUG +#ifdef FINSH_USING_MSH +int external_sram_test(void) +{ + int i = 0; + uint32_t start_time = 0, time_cast = 0; +#if EXTERNAL_SRAM_DATA_WIDTH == 8 + char data_width = 1; + uint8_t data = 0; + uint8_t *ptr = (uint8_t *)EXTERNAL_SRAM_BANK_ADDR; +#elif EXTERNAL_SRAM_DATA_WIDTH == 16 + char data_width = 2; + uint16_t data = 0; + uint16_t *ptr = (uint16_t *)EXTERNAL_SRAM_BANK_ADDR; +#else + char data_width = 4; + uint32_t data = 0; + uint32_t *ptr = (uint32_t *)EXTERNAL_SRAM_BANK_ADDR; +#endif + + /* write data */ + LOG_D("Writing the %ld bytes data, waiting....", EXTERNAL_SRAM_SIZE); + start_time = rt_tick_get(); + for (i = 0; i < EXTERNAL_SRAM_SIZE / data_width; i++) + { +#if EXTERNAL_SRAM_DATA_WIDTH == 8 + ((__IO uint8_t *)ptr)[i] = (uint8_t)0x55; +#elif EXTERNAL_SRAM_DATA_WIDTH == 16 + ((__IO uint16_t *)ptr)[i] = (uint16_t)0x5555; +#else + ((__IO uint32_t *)ptr)[i] = (uint32_t)0x55555555; +#endif + } + time_cast = rt_tick_get() - start_time; + LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND, + time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000)); + + /* read data */ + LOG_D("start Reading and verifying data, waiting...."); + for (i = 0; i < EXTERNAL_SRAM_SIZE / data_width; i++) + { +#if EXTERNAL_SRAM_DATA_WIDTH == 8 + data = ((__IO uint8_t *)ptr)[i]; + if (data != 0x55) + { + LOG_E("External SRAM test failed!"); + break; + } +#elif EXTERNAL_SRAM_DATA_WIDTH == 16 + data = ((__IO uint16_t *)ptr)[i]; + if (data != 0x5555) + { + LOG_E("External SRAM test failed!"); + break; + } +#else + data = ((__IO uint32_t *)ptr)[i]; + if (data != 0x55555555) + { + LOG_E("External SRAM test failed!"); + break; + } +#endif + } + + if (i >= EXTERNAL_SRAM_SIZE / data_width) + { + LOG_D("External SRAM test success!"); + } + + return RT_EOK; +} +MSH_CMD_EXPORT(external_sram_test, sram test); +#endif /* FINSH_USING_MSH */ +#endif /* DRV_DEBUG */ +#endif /* BSP_USING_EXT_SRAM */ diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/include/sram_port.h b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/include/sram_port.h new file mode 100644 index 0000000000000000000000000000000000000000..06ee47cca2317ba6ea18f29b744cd1a61c286b34 --- /dev/null +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/include/sram_port.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-05 linyiyang first version + */ + +#ifndef __SDRAM_PORT_H__ +#define __SDRAM_PORT_H__ + +/* parameters for sdram peripheral */ +/* stm32f1 Bank1:0x68000000 */ +#define EXTERNAL_SRAM_BANK_ADDR ((uint32_t)0x68000000) +/* data width: 8, 16, 32 */ +#define EXTERNAL_SRAM_DATA_WIDTH 16 +/* sram size */ +#define EXTERNAL_SRAM_SIZE ((uint32_t)0x100000) + +#endif diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c new file mode 100644 index 0000000000000000000000000000000000000000..a56e1bc35fbf37e4aaf0a49c6220e8075a1024d5 --- /dev/null +++ b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-17 linyiyang add sdcard port file + */ + +#include + +#ifdef BSP_USING_SDCARD + +#include +#include +#include + +#define DBG_TAG "app.card" +#define DBG_LVL DBG_INFO +#include + +void sd_mount(void *parameter) +{ + while (1) + { + rt_thread_mdelay(500); + if(rt_device_find("sd0") != RT_NULL) + { + if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK) + { + LOG_I("sd card mount to '/'"); + break; + } + else + { + LOG_W("sd card mount to '/' failed!"); + } + } + } +} + +int stm32_sdcard_mount(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, + 1024, RT_THREAD_PRIORITY_MAX - 2, 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd_mount thread err!"); + } + return RT_EOK; +} +INIT_APP_EXPORT(stm32_sdcard_mount); + +#endif /* BSP_USING_SDCARD */ + diff --git a/bsp/stm32/stm32f103-dofly-M3S/.cproject b/bsp/stm32/stm32f103-dofly-M3S/.cproject index 3dceacb108b1ef29915628978e2ba121891a8d26..9d9d0548167db3a856d477a7e2cd54ca3297ff1f 100644 --- a/bsp/stm32/stm32f103-dofly-M3S/.cproject +++ b/bsp/stm32/stm32f103-dofly-M3S/.cproject @@ -107,6 +107,26 @@ + @@ -122,11 +142,37 @@ - + + + + + + - + diff --git a/bsp/stm32/stm32f103-yf-ufun/.cproject b/bsp/stm32/stm32f103-yf-ufun/.cproject index b37a91bc57c310c58e5f923b82e8ccca4d5253cb..ac0a340b5381b384fa315fd61402f6f1e100e53a 100644 --- a/bsp/stm32/stm32f103-yf-ufun/.cproject +++ b/bsp/stm32/stm32f103-yf-ufun/.cproject @@ -106,6 +106,26 @@ + @@ -121,11 +141,36 @@ - + + + + + + - + diff --git a/bsp/stm32/stm32f401-st-nucleo/.cproject b/bsp/stm32/stm32f401-st-nucleo/.cproject index 194d91778d11d19681aac177d5283c78f6c4c47b..840b6ea8a3f39eb6dfba26cd8c1f9dfaf437ff7d 100644 --- a/bsp/stm32/stm32f401-st-nucleo/.cproject +++ b/bsp/stm32/stm32f401-st-nucleo/.cproject @@ -108,6 +108,26 @@ + @@ -123,11 +143,36 @@ - + + + + + + - + diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/.cproject b/bsp/stm32/stm32f405-smdz-breadfruit/.cproject index 1742bda37c2e4eda072158aaf8b7557b92a6cd4b..28875aebba199afb7fdc6d7999a9de3a6d0c2b01 100644 --- a/bsp/stm32/stm32f405-smdz-breadfruit/.cproject +++ b/bsp/stm32/stm32f405-smdz-breadfruit/.cproject @@ -108,6 +108,26 @@ + @@ -123,11 +143,36 @@ - + + + + + + - + diff --git a/bsp/stm32/stm32f407-atk-explorer/.cproject b/bsp/stm32/stm32f407-atk-explorer/.cproject index ca7e2cbe655f83748ea5ed5b0c87cbb4ad7a0e92..29d2070c6ba789a2b13d46e94dc3a8c69fd8d2cb 100644 --- a/bsp/stm32/stm32f407-atk-explorer/.cproject +++ b/bsp/stm32/stm32f407-atk-explorer/.cproject @@ -109,6 +109,26 @@ + @@ -124,11 +144,37 @@ - + + + + + + - + diff --git a/bsp/stm32/stm32f407-atk-explorer/README.md b/bsp/stm32/stm32f407-atk-explorer/README.md index 5e8432e01fb98b1616bc23040f7ab6801e313317..6a10371701bfa2c7f1d36ec09019c9055ccfb154 100644 --- a/bsp/stm32/stm32f407-atk-explorer/README.md +++ b/bsp/stm32/stm32f407-atk-explorer/README.md @@ -57,8 +57,8 @@ | WDT | 支持 | | | FLASH | 支持 | 已适配 [FAL](https://github.com/RT-Thread-packages/fal) | | PWM | 支持 | | -| USB Device | 暂不支持 | 即将支持 | -| USB Host | 暂不支持 | 即将支持 | +| USB Device | 支持 | | +| USB Host | 支持 | | | **扩展模块** | **支持情况** | **备注** | | ATK-ESP8266 模块 | 暂不支持 | 即将支持 | diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/.mxproject index 031ff82f9a4595b1236280bf2bb6af850979c717..d10dfb5d6af6a81a32d8c96ade93677146e6766c 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/.mxproject @@ -1,14 +1,14 @@ [PreviousGenFiles] -HeaderPath=E:/workspace/rt-thread/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc +HeaderPath=E:/rt-thread/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; -SourcePath=E:/workspace/rt-thread/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src +SourcePath=E:/rt-thread/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; +LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; [PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null; +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;..\\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;..\\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;; HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; -CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;STM32F407xx; +CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc index fcc30e407e5b539240e582d5e4bb71f0745cae2b..5952039d02797d2f73ce6efc47cdff21058d8490 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/CubeMX_Config.ioc @@ -19,6 +19,7 @@ Mcu.IP13=TIM13 Mcu.IP14=TIM14 Mcu.IP15=USART1 Mcu.IP16=USART3 +Mcu.IP17=USB_OTG_FS Mcu.IP2=IWDG Mcu.IP3=NVIC Mcu.IP4=RCC @@ -27,7 +28,7 @@ Mcu.IP6=SDIO Mcu.IP7=SPI1 Mcu.IP8=SPI2 Mcu.IP9=SYS -Mcu.IPNb=17 +Mcu.IPNb=18 Mcu.Name=STM32F407Z(E-G)Tx Mcu.Package=LQFP144 Mcu.Pin0=PC14-OSC32_IN @@ -44,45 +45,49 @@ Mcu.Pin18=PC9 Mcu.Pin19=PA9 Mcu.Pin2=PH0-OSC_IN Mcu.Pin20=PA10 -Mcu.Pin21=PA13 -Mcu.Pin22=PA14 -Mcu.Pin23=PC10 -Mcu.Pin24=PC11 -Mcu.Pin25=PC12 -Mcu.Pin26=PD2 -Mcu.Pin27=PG11 -Mcu.Pin28=PG13 -Mcu.Pin29=PG14 +Mcu.Pin21=PA11 +Mcu.Pin22=PA12 +Mcu.Pin23=PA13 +Mcu.Pin24=PA14 +Mcu.Pin25=PC10 +Mcu.Pin26=PC11 +Mcu.Pin27=PC12 +Mcu.Pin28=PD2 +Mcu.Pin29=PG11 Mcu.Pin3=PH1-OSC_OUT -Mcu.Pin30=PB3 -Mcu.Pin31=PB4 -Mcu.Pin32=PB5 -Mcu.Pin33=PB6 -Mcu.Pin34=PB7 -Mcu.Pin35=VP_IWDG_VS_IWDG -Mcu.Pin36=VP_RTC_VS_RTC_Activate -Mcu.Pin37=VP_SYS_VS_Systick -Mcu.Pin38=VP_TIM2_VS_ClockSourceINT -Mcu.Pin39=VP_TIM11_VS_ClockSourceINT +Mcu.Pin30=PG13 +Mcu.Pin31=PG14 +Mcu.Pin32=PB3 +Mcu.Pin33=PB4 +Mcu.Pin34=PB5 +Mcu.Pin35=PB6 +Mcu.Pin36=PB7 +Mcu.Pin37=VP_IWDG_VS_IWDG +Mcu.Pin38=VP_RTC_VS_RTC_Activate +Mcu.Pin39=VP_SYS_VS_Systick Mcu.Pin4=PC1 -Mcu.Pin40=VP_TIM13_VS_ClockSourceINT -Mcu.Pin41=VP_TIM14_VS_ClockSourceINT +Mcu.Pin40=VP_TIM2_VS_ClockSourceINT +Mcu.Pin41=VP_TIM11_VS_ClockSourceINT +Mcu.Pin42=VP_TIM13_VS_ClockSourceINT +Mcu.Pin43=VP_TIM14_VS_ClockSourceINT Mcu.Pin5=PC2 Mcu.Pin6=PC3 Mcu.Pin7=PA1 Mcu.Pin8=PA2 Mcu.Pin9=PA3 -Mcu.PinsNb=42 +Mcu.PinsNb=44 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F407ZGTx -MxCube.Version=5.0.0 -MxDb.Version=DB.5.0.0 +MxCube.Version=5.4.0 +MxDb.Version=DB.5.0.40 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.ForceEnableDMAVector=true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SPI1_IRQn=true\:0\:0\:false\:false\:true\:true\:true @@ -94,6 +99,10 @@ PA1.Mode=RMII PA1.Signal=ETH_REF_CLK PA10.Mode=Asynchronous PA10.Signal=USART1_RX +PA11.Mode=Device_Only +PA11.Signal=USB_OTG_FS_DM +PA12.Mode=Device_Only +PA12.Signal=USB_OTG_FS_DP PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire @@ -174,7 +183,7 @@ PH0-OSC_IN.Signal=RCC_OSC_IN PH1-OSC_OUT.Mode=HSE-External-Oscillator PH1-OSC_OUT.Signal=RCC_OSC_OUT PinOutPanel.RotationAngle=0 -ProjectManager.AskForMigrate=false +ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=false ProjectManager.CompilerOptimize=6 ProjectManager.ComputerToolchain=false @@ -183,7 +192,7 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32F407ZGTx -ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.22.0 +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.24.2 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 @@ -200,7 +209,7 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=MDK-ARM V5 ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI1_Init-SPI1-false-HAL-true,5-MX_ETH_Init-ETH-false-HAL-true,6-MX_USART3_UART_Init-USART3-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_IWDG_Init-IWDG-false-HAL-true,10-MX_TIM14_Init-TIM14-false-HAL-true,11-MX_TIM13_Init-TIM13-false-HAL-true,12-MX_TIM11_Init-TIM11-false-HAL-true,13-MX_SDIO_SD_Init-SDIO-false-HAL-true,14-MX_TIM2_Init-TIM2-false-HAL-true,15-MX_SPI2_Init-SPI2-false-HAL-true,16-MX_TIM4_Init-TIM4-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI1_Init-SPI1-false-HAL-true,5-MX_ETH_Init-ETH-false-HAL-true,6-MX_USART3_UART_Init-USART3-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_IWDG_Init-IWDG-false-HAL-true,10-MX_TIM14_Init-TIM14-false-HAL-true,11-MX_TIM13_Init-TIM13-false-HAL-true,12-MX_TIM11_Init-TIM11-false-HAL-true,13-MX_SDIO_SD_Init-SDIO-false-HAL-true,14-MX_TIM2_Init-TIM2-false-HAL-true,15-MX_SPI2_Init-SPI2-false-HAL-true,16-MX_TIM4_Init-TIM4-false-HAL-true,17-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true RCC.48MHZClocksFreq_Value=48000000 RCC.AHBFreq_Value=168000000 RCC.APB1CLKDivider=RCC_HCLK_DIV4 @@ -217,7 +226,7 @@ RCC.HCLKFreq_Value=168000000 RCC.HSE_VALUE=8000000 RCC.HSI_VALUE=16000000 RCC.I2SClocksFreq_Value=192000000 -RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S RCC.LSI_VALUE=32000 RCC.MCO2PinFreq_Value=168000000 RCC.PLLCLKFreq_Value=168000000 @@ -225,7 +234,6 @@ RCC.PLLM=4 RCC.PLLN=168 RCC.PLLQ=7 RCC.PLLQCLKFreq_Value=48000000 -RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE RCC.RTCFreq_Value=32768 @@ -260,6 +268,8 @@ USART1.IPParameters=VirtualMode USART1.VirtualMode=VM_ASYNC USART3.IPParameters=VirtualMode USART3.VirtualMode=VM_ASYNC +USB_OTG_FS.IPParameters=VirtualMode +USB_OTG_FS.VirtualMode=Device_Only VP_IWDG_VS_IWDG.Mode=IWDG_Activate VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h index 9b15113c2c0f8bc7256c6e15765b931c753c713a..bcc1012811d7f366f04108d433a704567bc6d7ff 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -1,33 +1,20 @@ /** ****************************************************************************** - * @file stm32f4xx_hal_conf.h - * @brief HAL configuration file. + * @file stm32f4xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f4xx_hal_conf.h. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2019 STMicroelectronics

    + *

    © Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

    * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -49,7 +36,7 @@ */ #define HAL_MODULE_ENABLED -#define HAL_ADC_MODULE_ENABLED + #define HAL_ADC_MODULE_ENABLED /* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CRC_MODULE_ENABLED */ @@ -79,9 +66,10 @@ /* #define HAL_USART_MODULE_ENABLED */ /* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */ -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED /* #define HAL_DSI_MODULE_ENABLED */ /* #define HAL_QSPI_MODULE_ENABLED */ /* #define HAL_QSPI_MODULE_ENABLED */ @@ -90,8 +78,8 @@ /* #define HAL_SPDIFRX_MODULE_ENABLED */ /* #define HAL_DFSDM_MODULE_ENABLED */ /* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_EXTI_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED @@ -221,12 +209,12 @@ #define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ /* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ +#define PHY_SR ((uint16_t)0x1FU) /*!< PHY status register Offset */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */ -#define PHY_ISFR ((uint16_t)0x000BU) /*!< PHY Interrupt Source Flag register Offset */ +#define PHY_ISFR ((uint16_t)0x001DU) /*!< PHY Interrupt Source Flag register Offset */ #define PHY_ISFR_INT4 ((uint16_t)0x000BU) /*!< PHY Link down inturrupt */ /* ################## SPI peripheral configuration ########################## */ @@ -279,6 +267,10 @@ #include "stm32f4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + #ifdef HAL_DMA2D_MODULE_ENABLED #include "stm32f4xx_hal_dma2d.h" #endif /* HAL_DMA2D_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_it.h b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_it.h index d87cf45f970614d4b73afb897d61ede8b61a36dc..44c3bafe0f3afaa4596b16a182efdd74838e288d 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_it.h +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Inc/stm32f4xx_it.h @@ -73,6 +73,7 @@ void PendSV_Handler(void); void SysTick_Handler(void); void SPI1_IRQHandler(void); void USART1_IRQHandler(void); +void OTG_FS_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/main.c index ef64d82dc1d7cccc15cd3844af9b9a63ef407936..6d1ddd0123555c3b967990461fd4485486a95a4a 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/main.c @@ -84,6 +84,8 @@ TIM_HandleTypeDef htim14; UART_HandleTypeDef huart1; UART_HandleTypeDef huart3; +PCD_HandleTypeDef hpcd_USB_OTG_FS; + /* USER CODE BEGIN PV */ /* Private variables ---------------------------------------------------------*/ @@ -106,6 +108,7 @@ static void MX_SDIO_SD_Init(void); static void MX_TIM2_Init(void); static void MX_SPI2_Init(void); static void MX_TIM4_Init(void); +static void MX_USB_OTG_FS_PCD_Init(void); /* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/ @@ -125,6 +128,7 @@ int main(void) /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ + /* MCU Configuration--------------------------------------------------------*/ @@ -158,6 +162,7 @@ int main(void) MX_TIM2_Init(); MX_SPI2_Init(); MX_TIM4_Init(); + MX_USB_OTG_FS_PCD_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -185,11 +190,11 @@ void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - /**Configure the main internal regulator output voltage + /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE; @@ -206,7 +211,7 @@ void SystemClock_Config(void) { Error_Handler(); } - /**Initializes the CPU, AHB and APB busses clocks + /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; @@ -244,7 +249,7 @@ static void MX_ADC1_Init(void) /* USER CODE BEGIN ADC1_Init 1 */ /* USER CODE END ADC1_Init 1 */ - /**Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) */ hadc1.Instance = ADC1; hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; @@ -262,7 +267,7 @@ static void MX_ADC1_Init(void) { Error_Handler(); } - /**Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. */ sConfig.Channel = ADC_CHANNEL_5; sConfig.Rank = 1; @@ -289,21 +294,18 @@ static void MX_ETH_Init(void) /* USER CODE END ETH_Init 0 */ - uint8_t MACAddr[6] ; - /* USER CODE BEGIN ETH_Init 1 */ /* USER CODE END ETH_Init 1 */ heth.Instance = ETH; heth.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE; heth.Init.PhyAddress = LAN8742A_PHY_ADDRESS; - MACAddr[0] = 0x00; - MACAddr[1] = 0x80; - MACAddr[2] = 0xE1; - MACAddr[3] = 0x00; - MACAddr[4] = 0x00; - MACAddr[5] = 0x00; - heth.Init.MACAddr = &MACAddr[0]; + heth.Init.MACAddr[0] = 0x00; + heth.Init.MACAddr[1] = 0x80; + heth.Init.MACAddr[2] = 0xE1; + heth.Init.MACAddr[3] = 0x00; + heth.Init.MACAddr[4] = 0x00; + heth.Init.MACAddr[5] = 0x00; heth.Init.RxMode = ETH_RXPOLLING_MODE; heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE; heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII; @@ -365,7 +367,7 @@ static void MX_RTC_Init(void) /* USER CODE BEGIN RTC_Init 1 */ /* USER CODE END RTC_Init 1 */ - /**Initialize RTC Only + /** Initialize RTC Only */ hrtc.Instance = RTC; hrtc.Init.HourFormat = RTC_HOURFORMAT_24; @@ -520,6 +522,7 @@ static void MX_TIM2_Init(void) htim2.Init.CounterMode = TIM_COUNTERMODE_UP; htim2.Init.Period = 0; htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim2) != HAL_OK) { Error_Handler(); @@ -577,6 +580,7 @@ static void MX_TIM4_Init(void) htim4.Init.CounterMode = TIM_COUNTERMODE_UP; htim4.Init.Period = 0; htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; sConfig.EncoderMode = TIM_ENCODERMODE_TI1; sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; @@ -622,6 +626,7 @@ static void MX_TIM11_Init(void) htim11.Init.CounterMode = TIM_COUNTERMODE_UP; htim11.Init.Period = 0; htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim11) != HAL_OK) { Error_Handler(); @@ -652,6 +657,7 @@ static void MX_TIM13_Init(void) htim13.Init.CounterMode = TIM_COUNTERMODE_UP; htim13.Init.Period = 0; htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim13.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim13) != HAL_OK) { Error_Handler(); @@ -682,6 +688,7 @@ static void MX_TIM14_Init(void) htim14.Init.CounterMode = TIM_COUNTERMODE_UP; htim14.Init.Period = 0; htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim14) != HAL_OK) { Error_Handler(); @@ -758,6 +765,41 @@ static void MX_USART3_UART_Init(void) } +/** + * @brief USB_OTG_FS Initialization Function + * @param None + * @retval None + */ +static void MX_USB_OTG_FS_PCD_Init(void) +{ + + /* USER CODE BEGIN USB_OTG_FS_Init 0 */ + + /* USER CODE END USB_OTG_FS_Init 0 */ + + /* USER CODE BEGIN USB_OTG_FS_Init 1 */ + + /* USER CODE END USB_OTG_FS_Init 1 */ + hpcd_USB_OTG_FS.Instance = USB_OTG_FS; + hpcd_USB_OTG_FS.Init.dev_endpoints = 4; + hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; + hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; + hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; + hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; + hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; + hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; + hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; + hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; + if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USB_OTG_FS_Init 2 */ + + /* USER CODE END USB_OTG_FS_Init 2 */ + +} + /** * @brief GPIO Initialization Function * @param None diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index 90a333827e5dbfabe6e53ec1eaebc635bf951d99..c7a8ac1f1d0d134ffdbacfd99e80010c10bef4f3 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -107,7 +107,6 @@ void HAL_MspInit(void) */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; if(hadc->Instance==ADC1) { @@ -139,10 +138,8 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) * @param hadc: ADC handle pointer * @retval None */ - void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) { - if(hadc->Instance==ADC1) { /* USER CODE BEGIN ADC1_MspDeInit 0 */ @@ -171,7 +168,6 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) */ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; if(heth->Instance==ETH) { @@ -229,10 +225,8 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) * @param heth: ETH handle pointer * @retval None */ - void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) { - if(heth->Instance==ETH) { /* USER CODE BEGIN ETH_MspDeInit 0 */ @@ -273,7 +267,6 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) */ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) { - if(hrtc->Instance==RTC) { /* USER CODE BEGIN RTC_MspInit 0 */ @@ -294,10 +287,8 @@ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) * @param hrtc: RTC handle pointer * @retval None */ - void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) { - if(hrtc->Instance==RTC) { /* USER CODE BEGIN RTC_MspDeInit 0 */ @@ -320,7 +311,6 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) */ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; if(hsd->Instance==SDIO) { @@ -368,10 +358,8 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) * @param hsd: SD handle pointer * @retval None */ - void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) { - if(hsd->Instance==SDIO) { /* USER CODE BEGIN SDIO_MspDeInit 0 */ @@ -408,7 +396,6 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; if(hspi->Instance==SPI1) { @@ -480,10 +467,8 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) * @param hspi: SPI handle pointer * @retval None */ - void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) { - if(hspi->Instance==SPI1) { /* USER CODE BEGIN SPI1_MspDeInit 0 */ @@ -537,7 +522,6 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { - if(htim_base->Instance==TIM2) { /* USER CODE BEGIN TIM2_MspInit 0 */ @@ -593,7 +577,6 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) */ void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; if(htim_encoder->Instance==TIM4) { @@ -624,7 +607,6 @@ void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; if(htim->Instance==TIM2) { @@ -655,10 +637,8 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) * @param htim_base: TIM_Base handle pointer * @retval None */ - void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) { - if(htim_base->Instance==TIM2) { /* USER CODE BEGIN TIM2_MspDeInit 0 */ @@ -712,10 +692,8 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) * @param htim_encoder: TIM_Encoder handle pointer * @retval None */ - void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* htim_encoder) { - if(htim_encoder->Instance==TIM4) { /* USER CODE BEGIN TIM4_MspDeInit 0 */ @@ -745,7 +723,6 @@ void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* htim_encoder) */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; if(huart->Instance==USART1) { @@ -807,10 +784,8 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) * @param huart: UART handle pointer * @retval None */ - void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) { - if(huart->Instance==USART1) { /* USER CODE BEGIN USART1_MspDeInit 0 */ @@ -852,6 +827,76 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) } +/** +* @brief PCD MSP Initialization +* This function configures the hardware resources used in this example +* @param hpcd: PCD handle pointer +* @retval None +*/ +void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hpcd->Instance==USB_OTG_FS) + { + /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ + + /* USER CODE END USB_OTG_FS_MspInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USB_OTG_FS GPIO Configuration + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + /* USB_OTG_FS interrupt Init */ + HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(OTG_FS_IRQn); + /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ + + /* USER CODE END USB_OTG_FS_MspInit 1 */ + } + +} + +/** +* @brief PCD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hpcd: PCD handle pointer +* @retval None +*/ +void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) +{ + if(hpcd->Instance==USB_OTG_FS) + { + /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */ + + /* USER CODE END USB_OTG_FS_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); + + /**USB_OTG_FS GPIO Configuration + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); + + /* USB_OTG_FS interrupt DeInit */ + HAL_NVIC_DisableIRQ(OTG_FS_IRQn); + /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */ + + /* USER CODE END USB_OTG_FS_MspDeInit 1 */ + } + +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_it.c b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_it.c index 149f219b9c3335d9fad8abbd09693db0eed9447f..9832ed60e3a023b0f9ef362e597a8ead7d40e210 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_it.c +++ b/bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/Src/stm32f4xx_it.c @@ -73,6 +73,7 @@ /* External variables --------------------------------------------------------*/ extern SPI_HandleTypeDef hspi1; extern UART_HandleTypeDef huart1; +extern PCD_HandleTypeDef hpcd_USB_OTG_FS; /* USER CODE BEGIN EV */ /* USER CODE END EV */ @@ -241,6 +242,20 @@ void USART1_IRQHandler(void) /* USER CODE END USART1_IRQn 1 */ } +/** + * @brief This function handles USB On The Go FS global interrupt. + */ +void OTG_FS_IRQHandler(void) +{ + /* USER CODE BEGIN OTG_FS_IRQn 0 */ + //You can open usb device or usb host, but open both of them is fatal error. + /* USER CODE END OTG_FS_IRQn 0 */ + HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); + /* USER CODE BEGIN OTG_FS_IRQn 1 */ + + /* USER CODE END OTG_FS_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig index 5afd038648281be96ea2718f0913e9e395a5e706..12a10a31dabc8eb497d79f9525e4e27d051a942a 100644 --- a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig +++ b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig @@ -296,6 +296,26 @@ menu "On-chip Peripheral Drivers" select RT_USING_DFS default n + config BSP_USING_USBD + bool "Enable USB Device" + select RT_USING_USB_DEVICE + default n + + menuconfig BSP_USING_USBH + bool "Enable USB Host" + select RT_USING_USB_HOST + default n + if BSP_USING_USBH + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers" + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + menuconfig BSP_USING_PULSE_ENCODER bool "Enable Pulse Encoder" default n diff --git a/bsp/stm32/stm32f411-st-nucleo/.cproject b/bsp/stm32/stm32f411-st-nucleo/.cproject index 541ca5a624f814017b14f8a708266379b0038107..ede41532a62f3135c45f2cec8f094681600fe18d 100644 --- a/bsp/stm32/stm32f411-st-nucleo/.cproject +++ b/bsp/stm32/stm32f411-st-nucleo/.cproject @@ -108,6 +108,26 @@     + @@ -123,11 +143,36 @@ - + + + + + + - + diff --git a/bsp/stm32/stm32f427-robomaster-a/README.md b/bsp/stm32/stm32f427-robomaster-a/README.md index 9b288d504840bc204e2b6bdfb2cad5f67166b7c6..bba5febd737aeea9ab5465da268f7f64a1bf0c06 100644 --- a/bsp/stm32/stm32f427-robomaster-a/README.md +++ b/bsp/stm32/stm32f427-robomaster-a/README.md @@ -22,7 +22,7 @@ RoboMaster开发板套件是一款面向机器人DIY的开源主控套件。开 该开发板常用 **板载资源** 如下： -- MCU：STM32f427IIH6，主频 180MHz，2048KB FLASH ，128KB RAM +- MCU：STM32f427IIH6，主频 180MHz，2048KB FLASH ，256KB RAM(含64KB CCM RAM未使用) - 常用外设 - LED：2个，D10（红色，PE11），D9（绿色，PE14） - 按键：1个，KEY（PB2） diff --git a/bsp/stm32/stm32f427-robomaster-a/board/board.h b/bsp/stm32/stm32f427-robomaster-a/board/board.h index 57c8e4a9548660551802e5368f8cecad4b36d6c6..4c74f95682c36d747826b441ab7380fc4b9f654f 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/board.h +++ b/bsp/stm32/stm32f427-robomaster-a/board/board.h @@ -25,7 +25,7 @@ extern "C" { #define STM32_FLASH_SIZE (2048 * 1024) #define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) -#define STM32_SRAM1_SIZE (128) +#define STM32_SRAM1_SIZE (192) #define STM32_SRAM1_START (0x20000000) #define STM32_SRAM1_END (STM32_SRAM1_START + STM32_SRAM1_SIZE * 1024) diff --git a/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.icf b/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.icf index a481a85ff3aa54889ca66f6ac0ee8c81fb7f8370..03094ef488add4cb9107df6e549a1b3ccc08d800 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.icf +++ b/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.icf @@ -6,8 +6,10 @@ define symbol __ICFEDIT_intvec_start__ = 0x08000000; /*-Memory Regions-*/ define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM1_end__ = 0x2002FFFF; +define symbol __ICFEDIT_region_RAM2_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM2_end__ = 0x1000FFFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x0400; diff --git a/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.lds b/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.lds index 9d870aef5e7f9fbc8c91da7c8c147d6851a38ccc..739d4885559f74748ea92cd17774299a6d042e7e 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.lds @@ -6,7 +6,8 @@ MEMORY { ROM (rx) : ORIGIN = 0x08000000, LENGTH = 2048k /* 2048KB flash */ - RAM (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram */ + RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192K sram */ + RAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 64k /* 64K sram */ } ENTRY(Reset_Handler) _system_stack_size = 0x200; @@ -88,7 +89,7 @@ SECTIONS . = ALIGN(4); /* This is used by the startup in order to initialize the .data secion */ _edata = . ; - } > RAM + } > RAM1 .stack : { @@ -97,7 +98,7 @@ SECTIONS . = . + _system_stack_size; . = ALIGN(4); _estack = .; - } > RAM + } > RAM1 __bss_start = .; .bss : @@ -115,7 +116,7 @@ SECTIONS _ebss = . ; *(.bss.init) - } > RAM + } > RAM1 __bss_end = .; _end = .; diff --git a/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.sct b/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.sct index b4e850d63016f424c62d317b2435b88ab8ebd39e..aca2546c3ab5c347005e67f649775651313670f4 100644 --- a/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32f427-robomaster-a/board/linker_scripts/link.sct @@ -8,8 +8,10 @@ LR_IROM1 0x08000000 0x00200000 { ; load region size_region *(InRoot$$Sections) .ANY (+RO) } - RW_IRAM1 0x20000000 0x00020000 { ; RW data + RW_IRAM1 0x20000000 0x00030000 { ; RW data + .ANY (+RW +ZI) + } + RW_IRAM2 0x10000000 0x00010000 { ; RW data .ANY (+RW +ZI) } } - diff --git a/bsp/stm32/stm32f429-atk-apollo/.cproject b/bsp/stm32/stm32f429-atk-apollo/.cproject index e561b1f4eba1174bf6825d62db5ad0fafd4d6fa0..146667cb3eec4ff0975abe057d2de3fe01abcb34 100644 --- a/bsp/stm32/stm32f429-atk-apollo/.cproject +++ b/bsp/stm32/stm32f429-atk-apollo/.cproject @@ -109,6 +109,26 @@ + @@ -124,11 +144,37 @@ - + + + + + + - + diff --git a/bsp/stm32/stm32f429-atk-apollo/README.md b/bsp/stm32/stm32f429-atk-apollo/README.md index f616cebdbd3169ece698d72bac565aefc0aa7774..6ec5108a3a29f7d34e99e4b4e224fd670f29343e 100644 --- a/bsp/stm32/stm32f429-atk-apollo/README.md +++ b/bsp/stm32/stm32f429-atk-apollo/README.md @@ -47,7 +47,7 @@ | MPU9250九轴传感器 | 支持 | | | SDRAM | 支持 | | | SD卡 | 支持 | | -| CAN | 暂不支持 | | +| CAN | 支持 | 和 USB Host 引脚冲突，如需使用该外设，请使用 CubeMX 重新配置 | | **片上外设** | **支持情况** | **备注** | | GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 | | UART | 支持 | UART1/2/3 | @@ -61,7 +61,7 @@ | SDIO | 支持 | | | PWM | 支持 | | | USB Device | 暂不支持 | 即将支持 | -| USB Host | 暂不支持 | 即将支持 | +| USB Host | 支持 | 和 CAN1 引脚冲突，如需使用该外设，请使用 CubeMX 重新配置 | | **扩展模块** | **支持情况** | **备注** | | ATK-ESP8266 模块 | 暂不支持 | 即将支持 | diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/.mxproject index ce6cbcb32b63d2248aa9fc35282f642198659926..5ccdc033db5f5f4ea41f73e593560bbe69e5bc00 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/.mxproject @@ -1,17 +1,17 @@ [PreviousGenFiles] -HeaderPath=E:/work_relative/RT_THREAD/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc +HeaderPath=F:/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc HeaderFiles=stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; -SourcePath=E:/work_relative/RT_THREAD/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src +SourcePath=F:/rt-thread/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; [PreviousLibFiles] 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stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; [] SourceFiles=;; [PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null; +SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null; HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc; CDefines=USE_HAL_DRIVER;STM32F429xx;USE_HAL_DRIVER;STM32F429xx; diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h index 65a892fc3d187c9db2ed800ef8544ba08fe31b97..953a90cf2fbf25c41da396d77e9a1ef328f3ac42 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -38,7 +38,7 @@ #define HAL_ADC_MODULE_ENABLED /* #define HAL_CRYP_MODULE_ENABLED */ -#define HAL_CAN_MODULE_ENABLED +/* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CRC_MODULE_ENABLED */ /* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_DAC_MODULE_ENABLED */ @@ -68,7 +68,7 @@ /* #define HAL_SMARTCARD_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */ /* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ +#define HAL_HCD_MODULE_ENABLED /* #define HAL_DSI_MODULE_ENABLED */ /* #define HAL_QSPI_MODULE_ENABLED */ /* #define HAL_QSPI_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_it.h b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_it.h index e3b003d9ad5adecaca9cb5ebe7047424088a9c2c..c80fb5271c3afdf37e66f5defa2ac3493442b5f8 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_it.h +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Inc/stm32f4xx_it.h @@ -72,6 +72,7 @@ void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); void USART1_IRQHandler(void); +void OTG_FS_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/STM32F429IG.ioc b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/STM32F429IG.ioc index fad96a6839b1689b7fd115758587c1ebdfd9f1b3..ad57d049ee005c350df376c5d5a4d21b5a5822f6 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/STM32F429IG.ioc +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/STM32F429IG.ioc @@ -5,34 +5,32 @@ ADC1.NbrOfConversionFlag=1 ADC1.Rank-0\#ChannelRegularConversion=1 ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES ADC1.master=1 -CAN1.CalculateTimeQuantum=355.55555555555554 -CAN1.IPParameters=CalculateTimeQuantum ETH.IPParameters=MediaInterface ETH.MediaInterface=ETH_MEDIA_INTERFACE_RMII File.Version=6 KeepUserPlacement=false Mcu.Family=STM32F4 Mcu.IP0=ADC1 -Mcu.IP1=CAN1 -Mcu.IP10=SPI1 -Mcu.IP11=SPI2 -Mcu.IP12=SPI5 -Mcu.IP13=SYS -Mcu.IP14=TIM2 -Mcu.IP15=TIM11 -Mcu.IP16=TIM13 -Mcu.IP17=TIM14 -Mcu.IP18=USART1 -Mcu.IP19=USART2 -Mcu.IP2=ETH -Mcu.IP20=USART3 -Mcu.IP3=FMC -Mcu.IP4=IWDG -Mcu.IP5=NVIC -Mcu.IP6=RCC -Mcu.IP7=RTC -Mcu.IP8=SAI1 -Mcu.IP9=SDIO +Mcu.IP1=ETH +Mcu.IP10=SPI2 +Mcu.IP11=SPI5 +Mcu.IP12=SYS +Mcu.IP13=TIM2 +Mcu.IP14=TIM11 +Mcu.IP15=TIM13 +Mcu.IP16=TIM14 +Mcu.IP17=USART1 +Mcu.IP18=USART2 +Mcu.IP19=USART3 +Mcu.IP2=FMC +Mcu.IP20=USB_OTG_FS +Mcu.IP3=IWDG +Mcu.IP4=NVIC +Mcu.IP5=RCC +Mcu.IP6=RTC +Mcu.IP7=SAI1 +Mcu.IP8=SDIO +Mcu.IP9=SPI1 Mcu.IPNb=21 Mcu.Name=STM32F429I(E-G)Tx Mcu.Package=LQFP176 @@ -138,6 +136,7 @@ NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false @@ -148,11 +147,10 @@ PA1.Mode=RMII PA1.Signal=ETH_REF_CLK PA10.Mode=Asynchronous PA10.Signal=USART1_RX -PA11.Locked=true -PA11.Mode=Master -PA11.Signal=CAN1_RX -PA12.Mode=Master -PA12.Signal=CAN1_TX +PA11.Mode=Host_Only +PA11.Signal=USB_OTG_FS_DM +PA12.Mode=Host_Only +PA12.Signal=USB_OTG_FS_DP PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire @@ -300,7 +298,7 @@ ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=true +ProjectManager.LastFirmware=false ProjectManager.LibraryCopy=0 ProjectManager.MainLocation=Src ProjectManager.NoMain=false @@ -357,8 +355,7 @@ RCC.VCOSAIOutputFreq_ValueR=50000000 RCC.VcooutputI2S=160000000 RCC.VcooutputI2SQ=160000000 SAI1.ErrorAudioFreq-SAI_A_MasterWithClock=-49.13 % -SAI1.FrameLength-SAI_B_SyncSlave=8 -SAI1.IPParameters=Instance-SAI_B_SyncSlave,VirtualMode-SAI_B_SyncSlave,Synchro-SAI_B_SyncSlave,FrameLength-SAI_B_SyncSlave,Instance-SAI_A_MasterWithClock,VirtualMode-SAI_A_MasterWithClock,Synchro-SAI_A_MasterWithClock,MClockEnable-SAI_A_MasterWithClock,RealAudioFreq-SAI_A_MasterWithClock,ErrorAudioFreq-SAI_A_MasterWithClock +SAI1.IPParameters=Instance-SAI_B_SyncSlave,VirtualMode-SAI_B_SyncSlave,Synchro-SAI_B_SyncSlave,Instance-SAI_A_MasterWithClock,VirtualMode-SAI_A_MasterWithClock,Synchro-SAI_A_MasterWithClock,MClockEnable-SAI_A_MasterWithClock,RealAudioFreq-SAI_A_MasterWithClock,ErrorAudioFreq-SAI_A_MasterWithClock SAI1.Instance-SAI_A_MasterWithClock=SAI$Index_Block_A SAI1.Instance-SAI_B_SyncSlave=SAI$Index_Block_B SAI1.MClockEnable-SAI_A_MasterWithClock=SAI_MASTERCLOCK_ENABLE @@ -468,6 +465,9 @@ USART2.IPParameters=VirtualMode USART2.VirtualMode=VM_ASYNC USART3.IPParameters=VirtualMode USART3.VirtualMode=VM_ASYNC +USB_OTG_FS.IPParameters=VirtualMode,phy_itface +USB_OTG_FS.VirtualMode=Host_Only +USB_OTG_FS.phy_itface=HCD_PHY_EMBEDDED VP_IWDG_VS_IWDG.Mode=IWDG_Activate VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/main.c index 342aa48b67b361fc120f9b59409ee2bcc87174fc..e17a48a0503bcfb0220dba69fea9bb81a7e9a548 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/main.c @@ -64,8 +64,6 @@ /* Private variables ---------------------------------------------------------*/ ADC_HandleTypeDef hadc1; -CAN_HandleTypeDef hcan1; - ETH_HandleTypeDef heth; IWDG_HandleTypeDef hiwdg; @@ -90,6 +88,8 @@ UART_HandleTypeDef huart1; UART_HandleTypeDef huart2; UART_HandleTypeDef huart3; +HCD_HandleTypeDef hhcd_USB_OTG_FS; + SDRAM_HandleTypeDef hsdram1; /* USER CODE BEGIN PV */ @@ -114,10 +114,10 @@ static void MX_TIM2_Init(void); static void MX_SPI1_Init(void); static void MX_SPI2_Init(void); static void MX_SPI5_Init(void); -static void MX_CAN1_Init(void); static void MX_SAI1_Init(void); static void MX_USART2_UART_Init(void); static void MX_USART3_UART_Init(void); +static void MX_USB_OTG_FS_HCD_Init(void); /* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/ @@ -171,10 +171,10 @@ int main(void) MX_SPI1_Init(); MX_SPI2_Init(); MX_SPI5_Init(); - MX_CAN1_Init(); MX_SAI1_Init(); MX_USART2_UART_Init(); MX_USART3_UART_Init(); + MX_USB_OTG_FS_HCD_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -309,43 +309,6 @@ static void MX_ADC1_Init(void) } -/** - * @brief CAN1 Initialization Function - * @param None - * @retval None - */ -static void MX_CAN1_Init(void) -{ - - /* USER CODE BEGIN CAN1_Init 0 */ - - /* USER CODE END CAN1_Init 0 */ - - /* USER CODE BEGIN CAN1_Init 1 */ - - /* USER CODE END CAN1_Init 1 */ - hcan1.Instance = CAN1; - hcan1.Init.Prescaler = 16; - hcan1.Init.Mode = CAN_MODE_NORMAL; - hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; - hcan1.Init.TimeSeg1 = CAN_BS1_1TQ; - hcan1.Init.TimeSeg2 = CAN_BS2_1TQ; - hcan1.Init.TimeTriggeredMode = DISABLE; - hcan1.Init.AutoBusOff = DISABLE; - hcan1.Init.AutoWakeUp = DISABLE; - hcan1.Init.AutoRetransmission = DISABLE; - hcan1.Init.ReceiveFifoLocked = DISABLE; - hcan1.Init.TransmitFifoPriority = DISABLE; - if (HAL_CAN_Init(&hcan1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN CAN1_Init 2 */ - - /* USER CODE END CAN1_Init 2 */ - -} - /** * @brief ETH Initialization Function * @param None @@ -500,7 +463,7 @@ static void MX_SAI1_Init(void) hsai_BlockB1.Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; hsai_BlockB1.Init.OutputDrive = SAI_OUTPUTDRIVE_DISABLE; hsai_BlockB1.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_EMPTY; - hsai_BlockB1.FrameInit.FrameLength = 8; + hsai_BlockB1.FrameInit.FrameLength = 24; hsai_BlockB1.FrameInit.ActiveFrameLength = 1; hsai_BlockB1.FrameInit.FSDefinition = SAI_FS_STARTFRAME; hsai_BlockB1.FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; @@ -920,6 +883,37 @@ static void MX_USART3_UART_Init(void) } +/** + * @brief USB_OTG_FS Initialization Function + * @param None + * @retval None + */ +static void MX_USB_OTG_FS_HCD_Init(void) +{ + + /* USER CODE BEGIN USB_OTG_FS_Init 0 */ + + /* USER CODE END USB_OTG_FS_Init 0 */ + + /* USER CODE BEGIN USB_OTG_FS_Init 1 */ + + /* USER CODE END USB_OTG_FS_Init 1 */ + hhcd_USB_OTG_FS.Instance = USB_OTG_FS; + hhcd_USB_OTG_FS.Init.Host_channels = 8; + hhcd_USB_OTG_FS.Init.speed = HCD_SPEED_FULL; + hhcd_USB_OTG_FS.Init.dma_enable = DISABLE; + hhcd_USB_OTG_FS.Init.phy_itface = HCD_PHY_EMBEDDED; + hhcd_USB_OTG_FS.Init.Sof_enable = DISABLE; + if (HAL_HCD_Init(&hhcd_USB_OTG_FS) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USB_OTG_FS_Init 2 */ + + /* USER CODE END USB_OTG_FS_Init 2 */ + +} + /* FMC initialization function */ static void MX_FMC_Init(void) { diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index 20fa0028c0072e730e5f28e4532d97d3d11752a0..ad60e8e19ac355df2ed6007c5fa957587b93d6f1 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -160,71 +160,6 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) } -/** -* @brief CAN MSP Initialization -* This function configures the hardware resources used in this example -* @param hcan: CAN handle pointer -* @retval None -*/ -void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(hcan->Instance==CAN1) - { - /* USER CODE BEGIN CAN1_MspInit 0 */ - - /* USER CODE END CAN1_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_CAN1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**CAN1 GPIO Configuration - PA11 ------> CAN1_RX - PA12 ------> CAN1_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF9_CAN1; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USER CODE BEGIN CAN1_MspInit 1 */ - - /* USER CODE END CAN1_MspInit 1 */ - } - -} - -/** -* @brief CAN MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hcan: CAN handle pointer -* @retval None -*/ -void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) -{ - if(hcan->Instance==CAN1) - { - /* USER CODE BEGIN CAN1_MspDeInit 0 */ - - /* USER CODE END CAN1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_CAN1_CLK_DISABLE(); - - /**CAN1 GPIO Configuration - PA11 ------> CAN1_RX - PA12 ------> CAN1_TX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); - - /* USER CODE BEGIN CAN1_MspDeInit 1 */ - - /* USER CODE END CAN1_MspDeInit 1 */ - } - -} - /** * @brief ETH MSP Initialization * This function configures the hardware resources used in this example @@ -909,6 +844,76 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) } +/** +* @brief HCD MSP Initialization +* This function configures the hardware resources used in this example +* @param hhcd: HCD handle pointer +* @retval None +*/ +void HAL_HCD_MspInit(HCD_HandleTypeDef* hhcd) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hhcd->Instance==USB_OTG_FS) + { + /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ + + /* USER CODE END USB_OTG_FS_MspInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USB_OTG_FS GPIO Configuration + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + /* USB_OTG_FS interrupt Init */ + HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(OTG_FS_IRQn); + /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ + + /* USER CODE END USB_OTG_FS_MspInit 1 */ + } + +} + +/** +* @brief HCD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hhcd: HCD handle pointer +* @retval None +*/ +void HAL_HCD_MspDeInit(HCD_HandleTypeDef* hhcd) +{ + if(hhcd->Instance==USB_OTG_FS) + { + /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */ + + /* USER CODE END USB_OTG_FS_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); + + /**USB_OTG_FS GPIO Configuration + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); + + /* USB_OTG_FS interrupt DeInit */ + HAL_NVIC_DisableIRQ(OTG_FS_IRQn); + /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */ + + /* USER CODE END USB_OTG_FS_MspDeInit 1 */ + } + +} + static uint32_t FMC_Initialized = 0; static void HAL_FMC_MspInit(void){ diff --git a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_it.c b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_it.c index 80653c5ad3a6148acdf6ce95d08f312eab7d334f..ecc64e0079df780edcad78ae4aff59f73d2cbf26 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_it.c +++ b/bsp/stm32/stm32f429-atk-apollo/board/CubeMX_Config/Src/stm32f4xx_it.c @@ -72,6 +72,7 @@ /* External variables --------------------------------------------------------*/ extern UART_HandleTypeDef huart1; +extern HCD_HandleTypeDef hhcd_USB_OTG_FS; /* USER CODE BEGIN EV */ /* USER CODE END EV */ @@ -226,6 +227,20 @@ void USART1_IRQHandler(void) /* USER CODE END USART1_IRQn 1 */ } +/** + * @brief This function handles USB On The Go FS global interrupt. + */ +void OTG_FS_IRQHandler(void) +{ + /* USER CODE BEGIN OTG_FS_IRQn 0 */ + + /* USER CODE END OTG_FS_IRQn 0 */ + HAL_HCD_IRQHandler(&hhcd_USB_OTG_FS); + /* USER CODE BEGIN OTG_FS_IRQn 1 */ + + /* USER CODE END OTG_FS_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig index 4705be7b467e06cfbd3d0b9f4eb5d6cb532ed2e1..1d693397c1513e05af8b591f6a18b7b955b405c9 100644 --- a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig @@ -270,6 +270,21 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n + menuconfig BSP_USING_USBH + bool "Enable USB Host" + select RT_USING_USB_HOST + default n + if BSP_USING_USBH + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers" + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + config BSP_USING_SDIO bool "Enable SDIO" select RT_USING_SDIO diff --git a/bsp/stm32/stm32f429-fire-challenger/.cproject b/bsp/stm32/stm32f429-fire-challenger/.cproject index 5c47f8b9b4994e049130f417e7f6c6fe61e13eba..a0ebec16c0461085cd20f5092c907c375f21e6a5 100644 --- a/bsp/stm32/stm32f429-fire-challenger/.cproject +++ b/bsp/stm32/stm32f429-fire-challenger/.cproject @@ -109,6 +109,26 @@ + @@ -124,11 +144,37 @@ - + + + + + + - + diff --git a/bsp/stm32/stm32f469-st-disco/board/SConscript b/bsp/stm32/stm32f469-st-disco/board/SConscript index 3c07ee8dbce7cee76826163b6fc406d5e66d8ab5..9521cc59078876735e09060d77b84e5f31f53242 100644 --- a/bsp/stm32/stm32f469-st-disco/board/SConscript +++ b/bsp/stm32/stm32f469-st-disco/board/SConscript @@ -26,9 +26,6 @@ if GetDepend(['BSP_USING_TOUCH']): if GetDepend(['BSP_USING_SDCARD']): src += ['ports/drv_sdcard.c'] - -if GetDepend(['BSP_USING_QSPI']): - src += ['ports/drv_qspi_flash.c'] path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] diff --git a/bsp/stm32/stm32f767-atk-apollo/.cproject b/bsp/stm32/stm32f767-atk-apollo/.cproject index 6851f72111b72ab273f4cd124eaa9dd9c7f615e3..5a0a52f7266845a818063677750b28d7e2f4f40f 100644 --- a/bsp/stm32/stm32f767-atk-apollo/.cproject +++ b/bsp/stm32/stm32f767-atk-apollo/.cproject @@ -109,6 +109,26 @@ + @@ -124,11 +144,37 @@ - + + + + + + - + diff --git a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/.mxproject index ac37a7c72b94ed5b21cdd76e7273aa023184a40f..f27f66a8333572f7b5c3d69f7d45cb262359e9fb 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/.mxproject @@ -1,14 +1,14 @@ [PreviousGenFiles] -HeaderPath=E:/work/rtt/rt-thread/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc +HeaderPath=F:/rt-thread/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc HeaderFiles=stm32f7xx_it.h;stm32f7xx_hal_conf.h;main.h; -SourcePath=E:/work/rtt/rt-thread/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src +SourcePath=F:/rt-thread/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src SourceFiles=stm32f7xx_it.c;stm32f7xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_iwdg.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_iwdg.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_iwdg.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_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x.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; [PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32f7xx_it.c;..\Src\stm32f7xx_hal_msp.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_iwdg.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c;..\Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_spi_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;..\Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;..\Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;../\Src/system_stm32f7xx.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_iwdg.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c;..\Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_spi_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;..\Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;..\Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;../\Src/system_stm32f7xx.c;../Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;null; +SourceFiles=..\Src\main.c;..\Src\stm32f7xx_it.c;..\Src\stm32f7xx_hal_msp.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_iwdg.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c;..\Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_spi_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;..\Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;..\Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;../\Src/system_stm32f7xx.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_iwdg.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c;..\Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_spi_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;..\Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;..\Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;../\Src/system_stm32f7xx.c;../Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;null; HeaderPath=..\Drivers\STM32F7xx_HAL_Driver\Inc;..\Drivers\STM32F7xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F7xx\Include;..\Drivers\CMSIS\Include;..\Inc; CDefines=USE_HAL_DRIVER;STM32F767xx;USE_HAL_DRIVER;STM32F767xx; diff --git a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc index b22dcde7c8c65bd2beae8b0bbb8622806db0fa61..506854c422a943004816b4b12169c48f8c4be0b3 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc @@ -28,6 +28,7 @@ Mcu.IP17=TIM14 Mcu.IP18=USART1 Mcu.IP19=USART2 Mcu.IP2=ETH +Mcu.IP20=USB_OTG_FS Mcu.IP3=FMC Mcu.IP4=IWDG Mcu.IP5=LTDC @@ -35,13 +36,15 @@ Mcu.IP6=NVIC Mcu.IP7=QUADSPI Mcu.IP8=RCC Mcu.IP9=RTC -Mcu.IPNb=20 +Mcu.IPNb=21 Mcu.Name=STM32F767I(G-I)Tx Mcu.Package=LQFP176 Mcu.Pin0=PC14/OSC32_IN Mcu.Pin1=PC15/OSC32_OUT Mcu.Pin10=PF5 -Mcu.Pin100=VP_TIM14_VS_ClockSourceINT +Mcu.Pin100=VP_TIM11_VS_ClockSourceINT +Mcu.Pin101=VP_TIM13_VS_ClockSourceINT +Mcu.Pin102=VP_TIM14_VS_ClockSourceINT Mcu.Pin11=PF6 Mcu.Pin12=PF7 Mcu.Pin13=PF8 @@ -111,35 +114,35 @@ Mcu.Pin70=PC9 Mcu.Pin71=PA8 Mcu.Pin72=PA9 Mcu.Pin73=PA10 -Mcu.Pin74=PA13 -Mcu.Pin75=PH14 -Mcu.Pin76=PI2 -Mcu.Pin77=PA14 -Mcu.Pin78=PC10 -Mcu.Pin79=PC11 +Mcu.Pin74=PA11 +Mcu.Pin75=PA12 +Mcu.Pin76=PA13 +Mcu.Pin77=PH14 +Mcu.Pin78=PI2 +Mcu.Pin79=PA14 Mcu.Pin8=PF3 -Mcu.Pin80=PC12 -Mcu.Pin81=PD0 -Mcu.Pin82=PD1 -Mcu.Pin83=PD2 -Mcu.Pin84=PD5 -Mcu.Pin85=PD6 -Mcu.Pin86=PG12 -Mcu.Pin87=PG13 -Mcu.Pin88=PG14 -Mcu.Pin89=PG15 +Mcu.Pin80=PC10 +Mcu.Pin81=PC11 +Mcu.Pin82=PC12 +Mcu.Pin83=PD0 +Mcu.Pin84=PD1 +Mcu.Pin85=PD2 +Mcu.Pin86=PD5 +Mcu.Pin87=PD6 +Mcu.Pin88=PG12 +Mcu.Pin89=PG13 Mcu.Pin9=PF4 -Mcu.Pin90=PB6 -Mcu.Pin91=PB8 -Mcu.Pin92=PB9 -Mcu.Pin93=PI5 -Mcu.Pin94=VP_IWDG_VS_IWDG -Mcu.Pin95=VP_RTC_VS_RTC_Activate -Mcu.Pin96=VP_SYS_VS_Systick -Mcu.Pin97=VP_TIM3_VS_ClockSourceINT -Mcu.Pin98=VP_TIM11_VS_ClockSourceINT -Mcu.Pin99=VP_TIM13_VS_ClockSourceINT -Mcu.PinsNb=101 +Mcu.Pin90=PG14 +Mcu.Pin91=PG15 +Mcu.Pin92=PB6 +Mcu.Pin93=PB8 +Mcu.Pin94=PB9 +Mcu.Pin95=PI5 +Mcu.Pin96=VP_IWDG_VS_IWDG +Mcu.Pin97=VP_RTC_VS_RTC_Activate +Mcu.Pin98=VP_SYS_VS_Systick +Mcu.Pin99=VP_TIM3_VS_ClockSourceINT +Mcu.PinsNb=103 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F767IGTx @@ -150,6 +153,7 @@ NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false @@ -160,6 +164,10 @@ PA1.Signal=ETH_REF_CLK PA10.Locked=true PA10.Mode=Asynchronous PA10.Signal=USART1_RX +PA11.Mode=Host_Only +PA11.Signal=USB_OTG_FS_DM +PA12.Mode=Host_Only +PA12.Signal=USB_OTG_FS_DP PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire @@ -377,7 +385,7 @@ RCC.I2C2Freq_Value=54000000 RCC.I2C3Freq_Value=54000000 RCC.I2C4Freq_Value=54000000 RCC.I2SFreq_Value=96000000 -RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,DFSDMAudioFreq_Value,DFSDMFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFTFreq_Value,LPTIM1Freq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLRFreq_Value,PLLSAIN,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIR,PLLSAIRCLKFreq_Value,PLLSAIRDiv,PLLSAIoutputFreq_Value,PLLSourceVirtual,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC2Freq_Value,SDMMCClockSelection,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value +RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,DFSDMAudioFreq_Value,DFSDMFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFTFreq_Value,LPTIM1Freq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLRFreq_Value,PLLSAIN,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIR,PLLSAIRCLKFreq_Value,PLLSAIRDiv,PLLSAIoutputFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC2Freq_Value,SDMMCClockSelection,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value RCC.LCDTFTFreq_Value=9000000 RCC.LPTIM1Freq_Value=54000000 RCC.LSI_VALUE=32000 @@ -400,7 +408,6 @@ RCC.PLLSAIR=4 RCC.PLLSAIRCLKFreq_Value=72000000 RCC.PLLSAIRDiv=RCC_PLLSAIDIVR_8 RCC.PLLSAIoutputFreq_Value=144000000 -RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE RCC.RNGFreq_Value=48000000 RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE RCC.RTCFreq_Value=32768 @@ -514,6 +521,9 @@ USART1.IPParameters=VirtualMode-Asynchronous USART1.VirtualMode-Asynchronous=VM_ASYNC USART2.IPParameters=VirtualMode-Asynchronous USART2.VirtualMode-Asynchronous=VM_ASYNC +USB_OTG_FS.IPParameters=VirtualMode,phy_itface +USB_OTG_FS.VirtualMode=Host_Only +USB_OTG_FS.phy_itface=HCD_PHY_EMBEDDED VP_IWDG_VS_IWDG.Mode=IWDG_Activate VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled diff --git a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h index 311e5d1c738744806feaaf247d278033822d9cd2..f14364403e4ca216c728dbecd69bfd2559dbd56e 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h +++ b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h @@ -70,7 +70,7 @@ /* #define HAL_SMARTCARD_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */ /* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ +#define HAL_HCD_MODULE_ENABLED /* #define HAL_DFSDM_MODULE_ENABLED */ /* #define HAL_DSI_MODULE_ENABLED */ /* #define HAL_JPEG_MODULE_ENABLED */ diff --git a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc/stm32f7xx_it.h b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc/stm32f7xx_it.h index a398e3c63b0923c32a766c6f7129bb4abecf78eb..7212cae561ad029b9d70aaae05187d03e52433d7 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc/stm32f7xx_it.h +++ b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Inc/stm32f7xx_it.h @@ -71,6 +71,7 @@ void SVC_Handler(void); void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); +void OTG_FS_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/main.c index d3f40d6dc335b3862365a101f2f52b8d53d15dc1..69926873b4f1c10172502d096c44b2fa14dc7559 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/main.c @@ -87,6 +87,8 @@ TIM_HandleTypeDef htim14; UART_HandleTypeDef huart1; UART_HandleTypeDef huart2; +HCD_HandleTypeDef hhcd_USB_OTG_FS; + SDRAM_HandleTypeDef hsdram1; /* USER CODE BEGIN PV */ @@ -112,6 +114,7 @@ static void MX_TIM13_Init(void); static void MX_TIM14_Init(void); static void MX_TIM3_Init(void); static void MX_LTDC_Init(void); +static void MX_USB_OTG_FS_HCD_Init(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ @@ -172,6 +175,7 @@ int main(void) MX_TIM14_Init(); MX_TIM3_Init(); MX_LTDC_Init(); + MX_USB_OTG_FS_HCD_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -883,6 +887,37 @@ static void MX_USART2_UART_Init(void) } +/** + * @brief USB_OTG_FS Initialization Function + * @param None + * @retval None + */ +static void MX_USB_OTG_FS_HCD_Init(void) +{ + + /* USER CODE BEGIN USB_OTG_FS_Init 0 */ + + /* USER CODE END USB_OTG_FS_Init 0 */ + + /* USER CODE BEGIN USB_OTG_FS_Init 1 */ + + /* USER CODE END USB_OTG_FS_Init 1 */ + hhcd_USB_OTG_FS.Instance = USB_OTG_FS; + hhcd_USB_OTG_FS.Init.Host_channels = 8; + hhcd_USB_OTG_FS.Init.speed = HCD_SPEED_FULL; + hhcd_USB_OTG_FS.Init.dma_enable = DISABLE; + hhcd_USB_OTG_FS.Init.phy_itface = HCD_PHY_EMBEDDED; + hhcd_USB_OTG_FS.Init.Sof_enable = DISABLE; + if (HAL_HCD_Init(&hhcd_USB_OTG_FS) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USB_OTG_FS_Init 2 */ + + /* USER CODE END USB_OTG_FS_Init 2 */ + +} + /* FMC initialization function */ static void MX_FMC_Init(void) { diff --git a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c index 5e6b7067a8218ef54c397497910fd7c0ad335f13..3fe29e92c967ef341c68a5c374819e7796290f46 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c +++ b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c @@ -1057,6 +1057,76 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) } +/** +* @brief HCD MSP Initialization +* This function configures the hardware resources used in this example +* @param hhcd: HCD handle pointer +* @retval None +*/ +void HAL_HCD_MspInit(HCD_HandleTypeDef* hhcd) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hhcd->Instance==USB_OTG_FS) + { + /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ + + /* USER CODE END USB_OTG_FS_MspInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USB_OTG_FS GPIO Configuration + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + /* USB_OTG_FS interrupt Init */ + HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(OTG_FS_IRQn); + /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ + + /* USER CODE END USB_OTG_FS_MspInit 1 */ + } + +} + +/** +* @brief HCD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hhcd: HCD handle pointer +* @retval None +*/ +void HAL_HCD_MspDeInit(HCD_HandleTypeDef* hhcd) +{ + if(hhcd->Instance==USB_OTG_FS) + { + /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */ + + /* USER CODE END USB_OTG_FS_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); + + /**USB_OTG_FS GPIO Configuration + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); + + /* USB_OTG_FS interrupt DeInit */ + HAL_NVIC_DisableIRQ(OTG_FS_IRQn); + /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */ + + /* USER CODE END USB_OTG_FS_MspDeInit 1 */ + } + +} + static uint32_t FMC_Initialized = 0; static void HAL_FMC_MspInit(void){ diff --git a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_it.c b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_it.c index fc333c38ebb24eb1110ed6f3039cb57383176d6a..f1e4c9ebf83f02f09a8896a7a1490ca2de7a141c 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_it.c +++ b/bsp/stm32/stm32f767-atk-apollo/board/CubeMX_Config/Src/stm32f7xx_it.c @@ -71,7 +71,7 @@ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ - +extern HCD_HandleTypeDef hhcd_USB_OTG_FS; /* USER CODE BEGIN EV */ /* USER CODE END EV */ @@ -212,6 +212,20 @@ void SysTick_Handler(void) /* please refer to the startup file (startup_stm32f7xx.s). */ /******************************************************************************/ +/** + * @brief This function handles USB On The Go FS global interrupt. + */ +void OTG_FS_IRQHandler(void) +{ + /* USER CODE BEGIN OTG_FS_IRQn 0 */ + + /* USER CODE END OTG_FS_IRQn 0 */ + HAL_HCD_IRQHandler(&hhcd_USB_OTG_FS); + /* USER CODE BEGIN OTG_FS_IRQn 1 */ + + /* USER CODE END OTG_FS_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/bsp/stm32/stm32f767-atk-apollo/board/Kconfig b/bsp/stm32/stm32f767-atk-apollo/board/Kconfig index c344d3a8c412dc5086287a37f398ed09330bdb6e..82efc63223edaa0a00d6b37f8ddaadf25ad9ea12 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32f767-atk-apollo/board/Kconfig @@ -17,7 +17,7 @@ menu "Onboard Peripheral Drivers" config BSP_USING_RS232 bool "Enable RS232 (uart2 pin conflict with Ethernet)" - select BSP_USING_UART + select BSP_USING_UART select BSP_USING_UART2 default n @@ -246,6 +246,21 @@ menu "On-chip Peripheral Drivers" select RT_USING_WDT default n + menuconfig BSP_USING_USBH + bool "Enable USB Host" + select RT_USING_USB_HOST + default n + if BSP_USING_USBH + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers" + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + config BSP_USING_SDIO bool "Enable SDIO" select RT_USING_SDIO @@ -255,7 +270,7 @@ menu "On-chip Peripheral Drivers" config BSP_USING_LTDC bool "Enable LTDC" default n - + source "../libraries/HAL_Drivers/Kconfig" endmenu diff --git a/bsp/stm32/stm32f769-st-disco/board/Kconfig b/bsp/stm32/stm32f769-st-disco/board/Kconfig index 0b6af50dea27f7f200264ad4df8e3b49f4242058..9d3d0067181150051b3d09978a5cbc287bed1358 100644 --- a/bsp/stm32/stm32f769-st-disco/board/Kconfig +++ b/bsp/stm32/stm32f769-st-disco/board/Kconfig @@ -3,6 +3,8 @@ menu "Hardware Drivers Config" config SOC_STM32F769NI bool select SOC_SERIES_STM32F7 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN default y menu "Onboard Peripheral Drivers" diff --git a/bsp/stm32/stm32h743-atk-apollo/README.md b/bsp/stm32/stm32h743-atk-apollo/README.md index cf813451fab8f9a2b4d52a55f49d73cc0bdd1c22..18240887f8cfb7489409a4029f0a2cfe18d03805 100644 --- a/bsp/stm32/stm32h743-atk-apollo/README.md +++ b/bsp/stm32/stm32h743-atk-apollo/README.md @@ -51,7 +51,7 @@ | **片上外设** | **支持情况** | **备注** | | GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 | | UART | 支持 | | -| SPI | 暂不支持 | | +| SPI | 支持 | SPI2 | | I2C | 暂不支持 | | | SDIO | 暂不支持 | | | RTC | 支持 | | diff --git a/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/.mxproject index 00d07ece24622bdb37693186fa291c9ea2bbf191..5c90788c8c6e2a0bedf7e00d04250e9619421936 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/.mxproject +++ b/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/.mxproject @@ -1,14 +1,14 @@ [PreviousGenFiles] -HeaderPath=D:/rt_thread/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Inc +HeaderPath=D:/rt_thread_master/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Inc HeaderFiles=stm32h7xx_it.h;stm32h7xx_hal_conf.h;main.h; -SourcePath=D:/rt_thread/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Src +SourcePath=D:/rt_thread_master/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Src SourceFiles=stm32h7xx_it.c;stm32h7xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_iwdg.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dsi.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h;Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_iwdg.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dsi.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h;Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; +LibFiles=Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_iwdg.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dsi.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h;Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_iwdg.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dsi.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h;Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h;Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h;Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; [PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32h7xx_it.c;..\Src\stm32h7xx_hal_msp.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;../\Src/system_stm32h7xx.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;../\Src/system_stm32h7xx.c;../Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c;null; +SourceFiles=..\Src\main.c;..\Src\stm32h7xx_it.c;..\Src\stm32h7xx_hal_msp.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c;../\Src/system_stm32h7xx.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c;../\Src/system_stm32h7xx.c;../Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c;null; HeaderPath=..\Drivers\STM32H7xx_HAL_Driver\Inc;..\Drivers\STM32H7xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7xx\Include;..\Drivers\CMSIS\Include;..\Inc; CDefines=USE_HAL_DRIVER;STM32H743xx;USE_HAL_DRIVER;STM32H743xx; diff --git a/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc index 900863885034a095b550ae06d4fe92ba732a82eb..aeab71c0cd142c3ba0e0addc412df15f07362cd9 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc +++ b/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/CubeMX_Config.ioc @@ -23,8 +23,9 @@ KeepUserPlacement=false Mcu.Family=STM32H7 Mcu.IP0=CORTEX_M7 Mcu.IP1=DEBUG -Mcu.IP10=SYS -Mcu.IP11=USART1 +Mcu.IP10=SPI2 +Mcu.IP11=SYS +Mcu.IP12=USART1 Mcu.IP2=DMA2D Mcu.IP3=FMC Mcu.IP4=IWDG1 @@ -33,7 +34,7 @@ Mcu.IP6=NVIC Mcu.IP7=QUADSPI Mcu.IP8=RCC Mcu.IP9=RTC -Mcu.IPNb=12 +Mcu.IPNb=13 Mcu.Name=STM32H743IITx Mcu.Package=LQFP176 Mcu.Pin0=PC13 @@ -73,53 +74,56 @@ Mcu.Pin39=PH10 Mcu.Pin4=PI10 Mcu.Pin40=PH11 Mcu.Pin41=PH12 -Mcu.Pin42=PD8 -Mcu.Pin43=PD9 -Mcu.Pin44=PD10 -Mcu.Pin45=PD14 -Mcu.Pin46=PD15 -Mcu.Pin47=PG2 -Mcu.Pin48=PG4 -Mcu.Pin49=PG5 +Mcu.Pin42=PB13 +Mcu.Pin43=PB14 +Mcu.Pin44=PB15 +Mcu.Pin45=PD8 +Mcu.Pin46=PD9 +Mcu.Pin47=PD10 +Mcu.Pin48=PD14 +Mcu.Pin49=PD15 Mcu.Pin5=PF0 -Mcu.Pin50=PG6 -Mcu.Pin51=PG7 -Mcu.Pin52=PG8 -Mcu.Pin53=PA9 -Mcu.Pin54=PA10 -Mcu.Pin55=PA13 (JTMS/SWDIO) -Mcu.Pin56=PH13 -Mcu.Pin57=PH14 -Mcu.Pin58=PH15 -Mcu.Pin59=PI0 +Mcu.Pin50=PG2 +Mcu.Pin51=PG4 +Mcu.Pin52=PG5 +Mcu.Pin53=PG6 +Mcu.Pin54=PG7 +Mcu.Pin55=PG8 +Mcu.Pin56=PA9 +Mcu.Pin57=PA10 +Mcu.Pin58=PA13 (JTMS/SWDIO) +Mcu.Pin59=PH13 Mcu.Pin6=PF1 -Mcu.Pin60=PI1 -Mcu.Pin61=PI2 -Mcu.Pin62=PA14 (JTCK/SWCLK) -Mcu.Pin63=PD0 -Mcu.Pin64=PD1 -Mcu.Pin65=PG11 -Mcu.Pin66=PG15 -Mcu.Pin67=PB6 -Mcu.Pin68=PE0 -Mcu.Pin69=PE1 +Mcu.Pin60=PH14 +Mcu.Pin61=PH15 +Mcu.Pin62=PI0 +Mcu.Pin63=PI1 +Mcu.Pin64=PI2 +Mcu.Pin65=PA14 (JTCK/SWCLK) +Mcu.Pin66=PD0 +Mcu.Pin67=PD1 +Mcu.Pin68=PG11 +Mcu.Pin69=PG15 Mcu.Pin7=PF2 -Mcu.Pin70=PI4 -Mcu.Pin71=PI5 -Mcu.Pin72=PI6 -Mcu.Pin73=PI7 -Mcu.Pin74=VP_DMA2D_VS_DMA2D -Mcu.Pin75=VP_IWDG1_VS_IWDG -Mcu.Pin76=VP_RTC_VS_RTC_Activate -Mcu.Pin77=VP_SYS_VS_Systick +Mcu.Pin70=PB6 +Mcu.Pin71=PE0 +Mcu.Pin72=PE1 +Mcu.Pin73=PI4 +Mcu.Pin74=PI5 +Mcu.Pin75=PI6 +Mcu.Pin76=PI7 +Mcu.Pin77=VP_DMA2D_VS_DMA2D +Mcu.Pin78=VP_IWDG1_VS_IWDG +Mcu.Pin79=VP_RTC_VS_RTC_Activate Mcu.Pin8=PF3 +Mcu.Pin80=VP_SYS_VS_Systick Mcu.Pin9=PF4 -Mcu.PinsNb=78 +Mcu.PinsNb=81 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32H743IITx -MxCube.Version=5.2.1 -MxDb.Version=DB.5.0.21 +MxCube.Version=5.3.0 +MxDb.Version=DB.5.0.30 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false @@ -141,6 +145,21 @@ PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK PA9.Locked=true PA9.Mode=Asynchronous PA9.Signal=USART1_TX +PB13.GPIOParameters=GPIO_Speed +PB13.GPIO_Speed=GPIO_SPEED_FREQ_HIGH +PB13.Locked=true +PB13.Mode=Full_Duplex_Master +PB13.Signal=SPI2_SCK +PB14.GPIOParameters=GPIO_Speed +PB14.GPIO_Speed=GPIO_SPEED_FREQ_HIGH +PB14.Locked=true +PB14.Mode=Full_Duplex_Master +PB14.Signal=SPI2_MISO +PB15.GPIOParameters=GPIO_Speed +PB15.GPIO_Speed=GPIO_SPEED_FREQ_HIGH +PB15.Locked=true +PB15.Mode=Full_Duplex_Master +PB15.Signal=SPI2_MOSI PB2.GPIOParameters=GPIO_Speed PB2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH PB2.Mode=Single Bank 1 @@ -288,10 +307,10 @@ ProjectManager.CompilerOptimize=6 ProjectManager.ComputerToolchain=false ProjectManager.CoupleFile=false ProjectManager.CustomerFirmwarePackage= -ProjectManager.DefaultFWLocation=false +ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32H743IITx -ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.4.0 +ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.5.0 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 @@ -308,7 +327,7 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=MDK-ARM V5 ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_FMC_Init-FMC-false-HAL-true,6-MX_DMA2D_Init-DMA2D-false-HAL-true,7-MX_LTDC_Init-LTDC-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_IWDG1_Init-IWDG1-false-HAL-true,10-MX_QUADSPI_Init-QUADSPI-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_FMC_Init-FMC-false-HAL-true,6-MX_DMA2D_Init-DMA2D-false-HAL-true,7-MX_LTDC_Init-LTDC-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_IWDG1_Init-IWDG1-false-HAL-true,10-MX_QUADSPI_Init-QUADSPI-false-HAL-true,11-MX_SPI2_Init-SPI2-false-HAL-true RCC.ADCFreq_Value=50390625 RCC.AHB12Freq_Value=200000000 RCC.AHB4Freq_Value=200000000 @@ -466,6 +485,12 @@ SH.FMC_SDNRAS.0=FMC_SDNRAS,13b-sda1 SH.FMC_SDNRAS.ConfNb=1 SH.FMC_SDNWE.0=FMC_SDNWE,13b-sda1 SH.FMC_SDNWE.ConfNb=1 +SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4 +SPI2.CalculateBaudRate=100.0 MBits/s +SPI2.Direction=SPI_DIRECTION_2LINES +SPI2.IPParameters=VirtualType,Mode,Direction,BaudRatePrescaler,CalculateBaudRate +SPI2.Mode=SPI_MODE_MASTER +SPI2.VirtualType=VM_MASTER USART1.IPParameters=VirtualMode-Asynchronous USART1.VirtualMode-Asynchronous=VM_ASYNC VP_DMA2D_VS_DMA2D.Mode=DMA2D_Activate diff --git a/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Inc/stm32h7xx_hal_conf.h b/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Inc/stm32h7xx_hal_conf.h index 8f082ec91d1d5e1396ca8efa06b9dde77273060a..39a66f19550846548bc3678804ca0ae89dcffe57 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Inc/stm32h7xx_hal_conf.h +++ b/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Inc/stm32h7xx_hal_conf.h @@ -64,7 +64,7 @@ /* #define HAL_SD_MODULE_ENABLED */ /* #define HAL_MMC_MODULE_ENABLED */ /* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED /* #define HAL_SWPMI_MODULE_ENABLED */ /* #define HAL_TIM_MODULE_ENABLED */ #define HAL_UART_MODULE_ENABLED @@ -78,12 +78,12 @@ /* #define HAL_DSI_MODULE_ENABLED */ /* #define HAL_JPEG_MODULE_ENABLED */ /* #define HAL_MDIOS_MODULE_ENABLED */ -/* #define HAL_EXTI_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED #define HAL_MDMA_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED #define HAL_PWR_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED diff --git a/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Src/main.c index 897ace06d10e13e0b756ac8dcda0bd3439c2b591..a12215c0abdaaa0034f840e709625b5d8adbc128 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Src/main.c +++ b/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Src/main.c @@ -73,6 +73,8 @@ QSPI_HandleTypeDef hqspi; RTC_HandleTypeDef hrtc; +SPI_HandleTypeDef hspi2; + UART_HandleTypeDef huart1; SDRAM_HandleTypeDef hsdram1; @@ -91,6 +93,7 @@ static void MX_LTDC_Init(void); static void MX_RTC_Init(void); static void MX_IWDG1_Init(void); static void MX_QUADSPI_Init(void); +static void MX_SPI2_Init(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ @@ -142,6 +145,7 @@ int main(void) MX_RTC_Init(); MX_IWDG1_Init(); MX_QUADSPI_Init(); + MX_SPI2_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ @@ -221,8 +225,8 @@ void SystemClock_Config(void) Error_Handler(); } PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_LTDC - |RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_QSPI - |RCC_PERIPHCLK_FMC; + |RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_SPI2 + |RCC_PERIPHCLK_QSPI|RCC_PERIPHCLK_FMC; PeriphClkInitStruct.PLL3.PLL3M = 5; PeriphClkInitStruct.PLL3.PLL3N = 160; PeriphClkInitStruct.PLL3.PLL3P = 2; @@ -233,6 +237,7 @@ void SystemClock_Config(void) PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_D1HCLK; PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK; + PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL; PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) @@ -457,6 +462,54 @@ static void MX_RTC_Init(void) } +/** + * @brief SPI2 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI2_Init(void) +{ + + /* USER CODE BEGIN SPI2_Init 0 */ + + /* USER CODE END SPI2_Init 0 */ + + /* USER CODE BEGIN SPI2_Init 1 */ + + /* USER CODE END SPI2_Init 1 */ + /* SPI2 parameter configuration*/ + hspi2.Instance = SPI2; + hspi2.Init.Mode = SPI_MODE_MASTER; + hspi2.Init.Direction = SPI_DIRECTION_2LINES; + hspi2.Init.DataSize = SPI_DATASIZE_4BIT; + hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi2.Init.NSS = SPI_NSS_SOFT; + hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4; + hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi2.Init.TIMode = SPI_TIMODE_DISABLE; + hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi2.Init.CRCPolynomial = 0x0; + hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + hspi2.Init.NSSPolarity = SPI_NSS_POLARITY_LOW; + hspi2.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA; + hspi2.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; + hspi2.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; + hspi2.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; + hspi2.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE; + hspi2.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; + hspi2.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE; + hspi2.Init.IOSwap = SPI_IO_SWAP_DISABLE; + if (HAL_SPI_Init(&hspi2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI2_Init 2 */ + + /* USER CODE END SPI2_Init 2 */ + +} + /** * @brief USART1 Initialization Function * @param None diff --git a/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c b/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c index 435f15593b04aaf11929df89ce83648050f64d69..d33aeaf6ad508b9560c76338773925f4d9d026b8 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c +++ b/bsp/stm32/stm32h743-atk-apollo/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c @@ -418,6 +418,73 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) } +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI2 GPIO Configuration + PB13 ------> SPI2_SCK + PB14 ------> SPI2_MISO + PB15 ------> SPI2_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspDeInit 0 */ + + /* USER CODE END SPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI2_CLK_DISABLE(); + + /**SPI2 GPIO Configuration + PB13 ------> SPI2_SCK + PB14 ------> SPI2_MISO + PB15 ------> SPI2_MOSI + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); + + /* USER CODE BEGIN SPI2_MspDeInit 1 */ + + /* USER CODE END SPI2_MspDeInit 1 */ + } + +} + /** * @brief UART MSP Initialization * This function configures the hardware resources used in this example diff --git a/bsp/stm32/stm32h743-atk-apollo/board/Kconfig b/bsp/stm32/stm32h743-atk-apollo/board/Kconfig index 22e2c7820c43ef11c5ba7acfd4b9d84e5f9fb239..13f950b08b338f0931e433732cc40b61eff87402 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32h743-atk-apollo/board/Kconfig @@ -54,6 +54,16 @@ menu "On-chip Peripheral Drivers" bool default n + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + endif + config BSP_USING_QSPI bool "Enable QSPI BUS" select RT_USING_QSPI diff --git a/bsp/stm32/stm32h743-atk-apollo/board/board.c b/bsp/stm32/stm32h743-atk-apollo/board/board.c index 1180633282f1bb61a59a2d53f907f3241e468555..682c2cb83209d400242da3b27590ac18a208c8cf 100644 --- a/bsp/stm32/stm32h743-atk-apollo/board/board.c +++ b/bsp/stm32/stm32h743-atk-apollo/board/board.c @@ -70,8 +70,8 @@ void SystemClock_Config(void) Error_Handler(); } PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_LTDC - |RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_QSPI - |RCC_PERIPHCLK_FMC; + |RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_SPI2 + |RCC_PERIPHCLK_QSPI|RCC_PERIPHCLK_FMC; PeriphClkInitStruct.PLL3.PLL3M = 5; PeriphClkInitStruct.PLL3.PLL3N = 160; PeriphClkInitStruct.PLL3.PLL3P = 2; @@ -82,6 +82,7 @@ void SystemClock_Config(void) PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_D1HCLK; PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK; + PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL; PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) diff --git a/bsp/stm32/stm32l475-atk-pandora/.cproject b/bsp/stm32/stm32l475-atk-pandora/.cproject index d97eb3fc3e72872dec7be8e5bcdf83aa1729cee8..396b8950936caf628376d28c727ad1d0cb24cbb1 100644 --- a/bsp/stm32/stm32l475-atk-pandora/.cproject +++ b/bsp/stm32/stm32l475-atk-pandora/.cproject @@ -108,6 +108,26 @@ + @@ -123,11 +143,37 @@ - + + + + + + - + diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig b/bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig index a227704de873fe63bbc6420b148c9f82637a07ae..bc515891578a525450af286633bb2097cd9e7564 100644 --- a/bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig @@ -3,6 +3,8 @@ menu "Hardware Drivers Config" config SOC_STM32L4R5ZI bool select SOC_SERIES_STM32L4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN default y menu "Onboard Peripheral Drivers" diff --git a/bsp/synopsys/boards/.config b/bsp/synopsys/boards/.config new file mode 100644 index 0000000000000000000000000000000000000000..6ae650f8cc056c7cffc1840426bc2cf6d413cc5d --- /dev/null +++ b/bsp/synopsys/boards/.config @@ -0,0 +1,397 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +CONFIG_RT_DEBUG_INIT_CONFIG=y +CONFIG_RT_DEBUG_INIT=1 +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40002 +CONFIG_RT_USING_CPU_FFS=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +# CONFIG_RT_USING_USER_MAIN is not set + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=1024 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=4096 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=8 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=1024 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_LIBC_USING_TIME is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +CONFIG_PKG_USING_EMBARC_BSP=y +CONFIG_PKG_EMBARC_BSP_PATH="/packages/system/embARC_bsp" +CONFIG_PKG_USING_EMBARC_BSP_UPSTREAM_VERSION=y +# CONFIG_PKG_USING_EMBARC_BSP_MASTER_VERSION is not set +CONFIG_PKG_EMBARC_BSP_VER="upstream" + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +CONFIG_SOC_EMSK=y +CONFIG_EMSK_USING_UART0=y +CONFIG_EMSK_USING_UART1=y diff --git a/bsp/synopsys/emsk_em9d/Kconfig b/bsp/synopsys/boards/Kconfig similarity index 94% rename from bsp/synopsys/emsk_em9d/Kconfig rename to bsp/synopsys/boards/Kconfig index 1bdec3c71fd860c49ab4be0e38547e3e9b5ec051..cfab67824410f593d7b2ff9f789c8c0210804d66 100644 --- a/bsp/synopsys/emsk_em9d/Kconfig +++ b/bsp/synopsys/boards/Kconfig @@ -23,6 +23,7 @@ config SOC_EMSK select ARCH_ARC_EM select RT_USING_COMPONENTS_INIT # select RT_USING_USER_MAIN + select RT_USING_CPU_FFS default y source "$BSP_DIR/drivers/Kconfig" diff --git a/bsp/synopsys/boards/README.md b/bsp/synopsys/boards/README.md new file mode 100644 index 0000000000000000000000000000000000000000..aee6059cfc47c93118d7917ee4773e719be78162 --- /dev/null +++ b/bsp/synopsys/boards/README.md @@ -0,0 +1,128 @@ +# Synopsys ARC Boards support with embARC_BSP + +## embARC_BSP + +The embARC Board support Package (BSP) is a software distributions aimed at facilitating +the development and evaluation of embedded systems based on ARCv2 processors, which is +designed to provide a minimal board support package for ARC users by defining +consistent and simple software interfaces to the processors and onboard devices. + +The embARC BSP is a new generation embARC software development package. ​ +It is designed to be the inter-layer between hardware and operating system. ​ +BSP could hide the difference of hardware/boards, provide a unified interface to upper-layer. ​ +In the scenarios that no OS is required, embARC BSP can also standalone and work in baremetal. + +embARC_BSP features: + +* Support MetaWare & GNU toolchains​ +* Support all development boards and tcf​ +* Support various build systems and compiling environments, + such as ARC MetaWare & GNU IDE, makefile​ +* Designware and Subsystem drivers, including UART and GPIO, I2C, SPI, etc. ​ +* No middleware, no OS​ +* Easy to port to different platform / OS​ +* One example (UART, GPIO, timer)​ +* Code coverage reach 100% in test. ​ +* MISRA-C compliance​ +* C & C++ support, assembly support + +## Supported Boards + +* [ARC Software Development Platform](https://www.synopsys.com/dw/ipdir.php?ds=arc-software-development-platform) +* [ARC EM Starter Kit](https://www.synopsys.com/dw/ipdir.php?ds=arc_em_starter_kit) +* [ARC EM Software Development Platform](https://www.synopsys.com/dw/ipdir.php?ds=arc-em-software-development-platform) +* [ARC HS Development Kit](https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit) +* [ARC IoT Development Kit](https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_development_kit) + + +## Software Requirement + +### embarc_bsp + +There are two ways to get embarc_bsp: + +#### use RT-Thread ENV tool: + +embARC_BSP has been configured as package module, you can just run the command `pkgs --update` in /bsp/synopsys/boards +folder using ENV tool. + +#### without RT-Thread ENV tool: + +We can get it from github: [embarc_bsp](https://github.com/foss-for-synopsys-dwc-arc-processors) + +The default path for embarc_bsp is /bsp/synopsys/boards/packages/embARC_bsp-upstream, +when you use other path, please set the environment variable `EMBARC_BSP_ROOT`. + +### Toolchain + +Now both GNU and MetaWare Toolchain are supported, set the System environment variable RTT_CC select the toolchain. + +GNU: + + set RTT_CC=gnu + +MetaWare: + + set RTT_CC=mw + +#### GNU + +The ARC GNU Toolchain offers all of the benefits of open source tools, including complete source code and a large install base. The ARC GNU IDE Installer consists of Eclipse IDE with [ARC GNU plugin for Eclipse](https://github.com/foss-for-synopsys-dwc-arc-processors/arc_gnu_eclipse/releases), [ARC GNU prebuilt toolchain](https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases) and [OpenOCD for ARC](https://github.com/foss-for-synopsys-dwc-arc-processors/openocd>) + +Here, the ARC GNU toolchain is installed to `c:\arc_gnu`. If not, please change the path configuration in rtconfig.py. + +When you use GNU Toolchain, you need to install [Zadig](http://zadig.akeo.ie) to replace the default FTDI driver with WinUSB driver. See [How to Use OpenOCD on Windows](https://github.com/foss-for-synopsys-dwc-arc-processors/arc_gnu_eclipse/wiki/How-to-Use-OpenOCD-on-Windows>) for more information. + +#### MetaWare +The [DesignWare ARC MetaWare Development Toolkit](https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware) builds on a long legacy of industry-leading compiler and debugger products for embedded applications. It is a complete solution that contains all the components needed to support the development, debugging, and tuning of embedded applications for the DesignWare® ARC® processors. + +Here, the ARC MetaWare toolchain is installed to `C:\ARC\MetaWare`. If not, please change the path configuration in rtconfig.py. + + + + + +## Build & Debug + +### Build embarc_lib + +please run the following cmds to build embarc_lib + + cd /bsp/synopsys/boards + scons --embarc_build + +### Build + +please run the following cmds to build + + cd /bsp/synopsys/boards + scons + +### Debug + +After compile, please use the following cmds to debug + + scons --gdb #use gdb debugger + scons --mdb #use mdb debugger + + +### How to choose different boards + +There are some parameters we can use in scons, for example: + + scons --BOARD=emsk --BD_VER=23 --CUR_CORE=arcem9d --TOOLCHAIN=mw --OLEVEL=O2 + + * BOARD: choose the board, we can set: `emsk, iotdk, emsdp, hsdk, axs`. + * BD_VER: choose the board version, some boards have different versions, for example, + we can set: `10, 22, 23` for emsk board. + * CUR_CORE: choose the arc cores, some boards have different cores, for example, + we can set: `arcem7d, arcem9d, arcem11d` for emsk board. + * TOOLCHAIN: choose the toolchain to build embarc_lib, we can set: `mw, gnu`. + * OLEVEL: choose the build optimize level, we can set: `O0, O2, Os`. + +For more information, you can run the command `scons -h`. + + +## Maintainer +- [vonhust](https://github.com/vonhust) +- [IRISZZW](https://github.com/IRISZZW) diff --git a/bsp/synopsys/emsk_em9d/SConscript b/bsp/synopsys/boards/SConscript similarity index 82% rename from bsp/synopsys/emsk_em9d/SConscript rename to bsp/synopsys/boards/SConscript index 86b6c891cd7a9301e57286b80c2c2184bf2935f0..2e95f4716ccb4c654d29bbcee314696e848f901c 100644 --- a/bsp/synopsys/emsk_em9d/SConscript +++ b/bsp/synopsys/boards/SConscript @@ -8,7 +8,6 @@ list = os.listdir(cwd) ASFLAGS = ' -I' + cwd -objs = objs + SConscript(os.path.join(cwd, '../embarc/SConscript')) for d in list: path = os.path.join(cwd, d) diff --git a/bsp/synopsys/boards/SConstruct b/bsp/synopsys/boards/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..a66e7ec76a7ce73214095651b4c669d6d8965a72 --- /dev/null +++ b/bsp/synopsys/boards/SConstruct @@ -0,0 +1,325 @@ +import os +import sys + +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] + + +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +if os.getenv('EMBARC_BSP_ROOT'): + EMBARC_BSP_ROOT = os.getenv('EMBARC_BSP_ROOT') +else: + EMBARC_BSP_ROOT = RTT_ROOT + '/bsp/synopsys/boards/packages/embARC_bsp-upstream' + +if not os.path.isdir(EMBARC_BSP_ROOT): + print('Cannot found embarc_bsp root directory, please check EMBARC_BSP_ROOT') + print(EMBARC_BSP_ROOT) + exit(-1) + +SUPPORTED_BOARD_DIR = EMBARC_BSP_ROOT + '/board' +SUPPORTED_BOARD = [d for d in os.listdir(SUPPORTED_BOARD_DIR) if os.path.isdir(os.path.join(SUPPORTED_BOARD_DIR,d))] +print 'supported BOARD = ' + str(SUPPORTED_BOARD) + +AddOption('--BOARD', + dest = 'BOARD', + type='string', + nargs=1, + action = 'store', + default = 'emsk', + help = 'select board') + +AddOption('--BD_VER', + dest = 'BD_VER', + type='string', + nargs=1, + action = 'store', + default = '23', + help = 'select bd_ver') + +AddOption('--CUR_CORE', + dest = 'CUR_CORE', + type='string', + nargs=1, + action = 'store', + default = 'arcem9d', + help = 'select cur_core') + +AddOption('--TOOLCHAIN', + dest = 'TOOLCHAIN', + type='string', + nargs=1, + action = 'store', + default = 'gnu', + help = 'select toolchain') + +AddOption('--OLEVEL', + dest = 'OLEVEL', + type='string', + nargs=1, + action = 'store', + default = 'O2', + help = 'select optimize level') + +AddOption('--mdb', + dest = 'mdb', + action = 'store_true', + default = False, + help = 'use mdb to debug the elf') + +AddOption('--gdb', + dest = 'gdb', + action = 'store_true', + default = False, + help = 'use gdb to debug the elf') + +AddOption('--embarc_build', + dest = 'embarc_build', + action = 'store_true', + default = False, + help = 'to generate embarc_lib') + +AddOption('--embarc_clean', + dest = 'embarc_clean', + action = 'store_true', + default = False, + help = 'to clean embarc_lib') + +if GetOption('BOARD'): + board = GetOption('BOARD') + if board not in SUPPORTED_BOARD: + print 'board %s not supported, available boards:' % board + print SUPPORTED_BOARD + exit(0) + else: + BOARD = board + print 'get BOARD = [%s]' % board + +if BOARD == 'emsdp': + SUPPORTED_BD_VER = ['rev2'] +else: + SUPPORTED_BD_VER_DIR = SUPPORTED_BOARD_DIR + '/' + BOARD + '/configs' + SUPPORTED_BD_VER = [d for d in os.listdir(SUPPORTED_BD_VER_DIR) if os.path.isdir(os.path.join(SUPPORTED_BD_VER_DIR,d))] +print 'supported BD_VER = ' + str(SUPPORTED_BD_VER) + +if GetOption('BD_VER'): + bd_ver = GetOption('BD_VER') + if bd_ver not in SUPPORTED_BD_VER: + print 'bd_ver %s not supported, available bd_ver:' % bd_ver + print SUPPORTED_BD_VER + exit(0) + else: + BD_VER = bd_ver + print 'get BD_VER = [%s]' % BD_VER + +if BOARD == 'emsdp': + SUPPORTED_CORE_DIR = SUPPORTED_BOARD_DIR + '/' + BOARD + '/rev2/configs' + SUPPORTED_CORE = [d for d in os.listdir(SUPPORTED_CORE_DIR) if os.path.isdir(os.path.join(SUPPORTED_CORE_DIR,d))] +else: + SUPPORTED_CORE_DIR = SUPPORTED_BD_VER_DIR + '/' + BD_VER + '/tcf' + SUPPORTED_CORE = [os.path.splitext(d)[0] for d in os.listdir(SUPPORTED_CORE_DIR)] + +print 'supported CUR_CORE = ' + str(SUPPORTED_CORE) + +if GetOption('CUR_CORE'): + cur_core = GetOption('CUR_CORE') + if cur_core not in SUPPORTED_CORE: + print 'cur_core %s not supported, available cur_core:' % cur_core + print SUPPORTED_CORE + exit(0) + else: + CUR_CORE = cur_core + print 'get CUR_CORE = [%s]' % CUR_CORE + +SUPPORTED_TOOLCHAIN = ['mw', 'gnu'] + +print 'supported TOOLCHAIN = ' + str(SUPPORTED_TOOLCHAIN) + +if GetOption('TOOLCHAIN'): + toolchain = GetOption('TOOLCHAIN') + if toolchain not in SUPPORTED_TOOLCHAIN: + print 'toolchain %s not supported, available toolchain:' % toolchain + print SUPPORTED_TOOLCHAIN + exit(0) + else: + TOOLCHAIN = toolchain + print 'get TOOLCHAIN = [%s]' % TOOLCHAIN + +SUPPORTED_OLEVEL = ['O0', 'O2', 'Os'] + +print 'supported OLEVEL = ' + str(SUPPORTED_OLEVEL) + +if GetOption('OLEVEL'): + olevel = GetOption('OLEVEL') + if olevel not in SUPPORTED_OLEVEL: + print 'olevel %s not supported, available olevel:' % toolchain + print SUPPORTED_OLEVEL + exit(0) + else: + OLEVEL = olevel + print 'get OLEVEL = [%s]' % olevel + + + +EMBARC_LIB_PATH = EMBARC_BSP_ROOT + '/obj_%s_%s/%s_%s'%(BOARD, BD_VER, TOOLCHAIN, CUR_CORE) +# print 'EMBARC_LIB_PATH = %s'%EMBARC_LIB_PATH + +TARGET = 'rtthread_snps_embarc.elf' +# print 'TARGET = %s'%TARGET + +# ip_ph_dir = EMBARC_BSP_ROOT + '/device/peripheral' +# ip_ph_path = [os.path.join(ip_ph_dir,d) for d in os.listdir(ip_ph_dir) if os.path.isdir(os.path.join(ip_ph_dir,d))] + +if BOARD == 'emsdp': + board_inc_path = [SUPPORTED_CORE_DIR, SUPPORTED_CORE_DIR + '/%s/include'%CUR_CORE] +else: + board_inc_path = [EMBARC_BSP_ROOT + '/board/%s/configs/%s'%(BOARD, BD_VER)] + +# print 'board_inc_path = %s' % board_inc_path +# print 'ip_dw_path = %s' % ip_dw_path +# print 'ip_ss_path = %s' % ip_ss_path +# print 'ip_ph_path = %s' % ip_ph_path + +EMBARC_CPPPATH = [ EMBARC_BSP_ROOT, + EMBARC_BSP_ROOT + '/include', + EMBARC_BSP_ROOT + '/board', + EMBARC_LIB_PATH + '/embARC_generated', + ] + board_inc_path +#print "EMBARC_CPPPATH: %s"%EMBARC_CPPPATH + +if TOOLCHAIN == 'mw': + EXEC_PATH = 'C:/ARC/MetaWare/arc/bin' + MAKE = 'gmake' + PREFIX = '' + CC = 'ccac' + CXX = 'ccac' + AS = 'ccac' + AR = 'arac' + LINK = 'ccac' + TARGET_EXT = 'elf' + SIZE = 'sizeac' + OBJDUMP = 'elfdumpac' + OBJCPY = 'elf2bin' + DBG = 'mdb' + + OPT_ARG_FILE = ' @' + EMBARC_LIB_PATH + '/embARC_generated/ccac.arg ' + MDB_ARG_FILE = ' @' + EMBARC_LIB_PATH + '/embARC_generated/mdb.arg ' + COMMON_COMPILE_OPT = ' -Hnoccm -Hnosdata -Wincompatible-pointer-types -Hnocopyr -Hpurge -fdata-sections -g -%s '%(OLEVEL) + COMMON_DEFINES = ' -DBOARD_%s -D__MW__ -DEMBARC_TCF_GENERATED ' % BOARD.upper() + + CFLAGS = OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES + ' -Hnocplus ' + CXXFLAGS = OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES + AFLAGS = ' -c' + OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES + ' -Hasmcpp -I%s -I%s/embARC_generated -I%s/include '%(EMBARC_BSP_ROOT, EMBARC_LIB_PATH, EMBARC_BSP_ROOT) + + LINKER_SCRIPT_FILE = RTT_ROOT + '/bsp/synopsys/boards/linker_template_mw.ld' + LINK_SCRIPT = EMBARC_LIB_PATH + '/linker_mw.ldf' + + LFLAGS = ' -Hhostlink ' + OPT_ARG_FILE + ' -Hnocopyr -Hnosdata -Hnocrt -Hldopt=-Coutput=rtthread_snps_embarc.map -Hldopt=-Csections -Hldopt=-Ccrossfunc -Hldopt=-Csize -zstdout %s' % LINK_SCRIPT + +elif TOOLCHAIN == 'gnu': + EXEC_PATH = 'C:/arc_gnu/bin' + MAKE = 'make' + PREFIX = 'arc-elf32-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + DBG = PREFIX + 'gdb' + + OPT_ARG_FILE = ' @' + EMBARC_LIB_PATH + '/embARC_generated/gcc.arg ' + MDB_ARG_FILE = ' @' + EMBARC_LIB_PATH + '/embARC_generated/mdb.arg ' + COMMON_COMPILE_OPT = ' -ffunction-sections -fdata-sections -mno-sdata -g -%s '%(OLEVEL) + COMMON_DEFINES = ' -DBOARD_%s -D__GNU__ -DEMBARC_TCF_GENERATED ' % BOARD.upper() + + CFLAGS = OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES + ' -std=gnu99 ' + CXXFLAGS = OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES + AFLAGS = ' -c ' + OPT_ARG_FILE + COMMON_COMPILE_OPT + COMMON_DEFINES + ' -x assembler-with-cpp -I%s -I%s/embARC_generated -I%s/include '%(EMBARC_BSP_ROOT, EMBARC_LIB_PATH, EMBARC_BSP_ROOT) + + LINKER_SCRIPT_FILE = RTT_ROOT + '/bsp/synopsys/boards/linker_template_gnu.ld' + LINK_SCRIPT = EMBARC_LIB_PATH + '/linker_gnu.ldf' + + LFLAGS = ' --specs=nsim.specs ' + OPT_ARG_FILE + ' -mno-sdata -nostartfiles -Wl,--gc-sections,-Map=rtthread_snps_embarc.map,-cref,-u,system_vectors -T %s ' % LINK_SCRIPT + + OPENOCD_SCRIPT_ROOT = EXEC_PATH + '/../share/openocd/scripts' + OPENOCD_CFG_FILE = OPENOCD_SCRIPT_ROOT + '/board/snps_em_sk_v2.2.cfg' + + OPENOCD_OPTIONS = '-s %s -f %s' % (OPENOCD_SCRIPT_ROOT, OPENOCD_CFG_FILE) + + DBG_HW_FLAGS = ''' -ex "target remote | openocd --pipe %s" -ex "load" ''' % OPENOCD_OPTIONS + +else : + print 'TOOLCHAIN %s is not supported, available toolchain:' % TOOLCHAIN + print SUPPORTED_TOOLCHAIN + exit(-1) + +env = Environment(ENV = os.environ, tools = ['mingw'], + AS = AS, ASFLAGS = AFLAGS, + CC = CC, CCFLAGS = CFLAGS, + AR = AR, ARFLAGS = '-rc', + LINK = LINK, LINKFLAGS = LFLAGS, + LIBS = ['embarc'], LIBPATH = EMBARC_LIB_PATH, + CPPPATH = EMBARC_CPPPATH + ) +env.PrependENVPath('PATH', EXEC_PATH) + +Export('RTT_ROOT') +Export('rtconfig') + +embarc_cd_cmd = ' cd %s '%EMBARC_BSP_ROOT +embarc_make_cmd = ' %s -f options/options.mk BOARD=%s BD_VER=%s CUR_CORE=%s TOOLCHAIN=%s V=1 OLEVEL=%s LINKER_SCRIPT_FILE=%s embarc_lib '%(MAKE,BOARD, BD_VER, CUR_CORE, TOOLCHAIN, OLEVEL, LINKER_SCRIPT_FILE) +embarc_clean_cmd = ' %s -f options/options.mk distclean '%MAKE + +if GetOption('embarc_build'): + print 'os.system: ' + embarc_cd_cmd + ' && ' + embarc_make_cmd + os.system(embarc_cd_cmd + ' && ' + embarc_make_cmd) + exit(0) + +if GetOption('embarc_clean'): + os.system(embarc_cd_cmd + ' && ' + embarc_clean_cmd) + exit(0) + +if GetOption('gdb'): + if os.path.isfile(TARGET): + os.system(DBG + DBG_HW_FLAGS + TARGET) + else: + print TARGET + 'not exist, please build first!!' + exit(0) + +if GetOption('mdb'): + if os.path.isfile(TARGET): + startup_path = EMBARC_BSP_ROOT + '/arc/startup' + if BOARD == 'nsim': + os.system('mdb -source_path=%s -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim -off=binary_stdin -off=binary_stdout \ + -on=load_at_paddr -on=reset_upon_restart -off=flush_pipe -off=cr_for_more -OKN %s '%(startup_path, MDB_ARG_FILE) + rtconfig.TARGET) + else: + os.system('mdb -source_path=%s -nooptions -nogoifmain -toggle=include_local_symbols=1 -hard -digilent '%startup_path + rtconfig.TARGET) + else: + print TARGET + 'not exist, please build first!!' + exit(0) + +# os.system(embarc_cd_cmd + ' && ' + embarc_make_cmd) + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +# if the linker script changed, relink the target +Depends(TARGET, LINK_SCRIPT) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/synopsys/emsk_em9d/applications/SConscript b/bsp/synopsys/boards/applications/SConscript similarity index 100% rename from bsp/synopsys/emsk_em9d/applications/SConscript rename to bsp/synopsys/boards/applications/SConscript diff --git a/bsp/synopsys/emsk_em9d/applications/application.c b/bsp/synopsys/boards/applications/application.c similarity index 100% rename from bsp/synopsys/emsk_em9d/applications/application.c rename to bsp/synopsys/boards/applications/application.c diff --git a/bsp/synopsys/emsk_em9d/applications/startup.c b/bsp/synopsys/boards/applications/startup.c similarity index 81% rename from bsp/synopsys/emsk_em9d/applications/startup.c rename to bsp/synopsys/boards/applications/startup.c index f561436272b46a72aa0b1e9dec80f9e8c6922e22..817bf74c9a449e4cd38ad4824748c1597f701892 100644 --- a/bsp/synopsys/emsk_em9d/applications/startup.c +++ b/bsp/synopsys/boards/applications/startup.c @@ -7,7 +7,12 @@ #include #include -#include +#include + +#ifdef RT_USING_HEAP +#define rt_system_heap_size 1024*64 +static rt_uint32_t rt_system_heap[rt_system_heap_size/4] = {0}; +#endif extern int rt_application_init(void); @@ -33,7 +38,7 @@ void rtthread_startup(void) /* initialize memory system */ #ifdef RT_USING_HEAP - rt_system_heap_init(HEAP_BEGIN, HEAP_END); + rt_system_heap_init((void *)rt_system_heap, (void *)(rt_system_heap+rt_system_heap_size)); #endif /* initialize scheduler system */ @@ -58,7 +63,7 @@ void rtthread_startup(void) return ; } -int board_main(void) +int main(void) { /* disable interrupt first */ rt_hw_interrupt_disable(); diff --git a/bsp/synopsys/emsk_em9d/drivers/Kconfig b/bsp/synopsys/boards/drivers/Kconfig similarity index 100% rename from bsp/synopsys/emsk_em9d/drivers/Kconfig rename to bsp/synopsys/boards/drivers/Kconfig diff --git a/bsp/synopsys/emsk_em9d/drivers/SConscript b/bsp/synopsys/boards/drivers/SConscript similarity index 100% rename from bsp/synopsys/emsk_em9d/drivers/SConscript rename to bsp/synopsys/boards/drivers/SConscript diff --git a/bsp/synopsys/emsk_em9d/drivers/board.c b/bsp/synopsys/boards/drivers/rt_board.c similarity index 40% rename from bsp/synopsys/emsk_em9d/drivers/board.c rename to bsp/synopsys/boards/drivers/rt_board.c index 449360f3a5f72900642c870e666b244e5c545ec4..1e1b7e494bedd2125a3dc1850c215655d05278b0 100644 --- a/bsp/synopsys/emsk_em9d/drivers/board.c +++ b/bsp/synopsys/boards/drivers/rt_board.c @@ -10,57 +10,11 @@ #include #include -#include "board.h" -#include "inc/arc/arc_timer.h" -#include "inc/arc/arc_exception.h" +#include "rt_board.h" +#include "arc/arc_timer.h" +#include "arc/arc_exception.h" -#include "inc/embARC_error.h" -#include "mux.h" -#include "dw_uart_obj.h" - - -static void rt_hw_timer_isr(int vector, void *param) -{ - arc_timer_int_clear(BOARD_OS_TIMER_ID); - rt_tick_increase(); -} - -static void emsk_mux_init(void) -{ - MUX_REG *mux_regs; - - mux_regs = (MUX_REG *)(PERIPHERAL_BASE|REL_REGBASE_PINMUX); - mux_init(mux_regs); - - /** - * + Please refer to corresponding EMSK User Guide for detailed information - * -> Appendix: A Hardware Functional Description - * -> Pmods Configuration summary - * + Set up pin-multiplexer of all PMOD connections - * - PM1 J1: Upper row as UART 0, lower row as SPI Slave - * - PM2 J2: IIC 0 and run/halt signals - * - PM3 J3: GPIO Port A and Port C - * - PM4 J4: IIC 1 and Port D - * - PM5 J5: Upper row as SPI Master, lower row as Port A - * - PM6 J6: Upper row as SPI Master, lower row as Port A - */ - set_pmod_mux(mux_regs, PM1_UR_UART_0 | PM1_LR_SPI_S \ - | PM2_I2C_HRI \ - | PM3_GPIO_AC \ - | PM4_I2C_GPIO_D \ - | PM5_UR_SPI_M1 | PM5_LR_GPIO_A \ - | PM6_UR_SPI_M0 | PM6_LR_GPIO_A ); - - /** - * PM1 upper row as UART - * UM4:RXD, UM3:TXD - * UM2:RTS_N, UM1:CTS_N - */ - set_uart_map(mux_regs, 0xe4); -} - -static struct rt_serial_device _emsk_uart0; //abstracted serial for RTT -static struct rt_serial_device _emsk_uart1; +#include "embARC_error.h" static rt_err_t _configure(struct rt_serial_device *serial, struct serial_configure *cfg) { @@ -158,12 +112,7 @@ static int _getc(struct rt_serial_device *serial) } -static void _emsk_uart0_isr(void *ptr) -{ - rt_hw_serial_isr((struct rt_serial_device*)&_emsk_uart0, RT_SERIAL_EVENT_RX_IND); -} - -static const struct rt_uart_ops _emsk_uart0_ops = +static const struct rt_uart_ops uart_ops = { _configure, _control, @@ -171,18 +120,31 @@ static const struct rt_uart_ops _emsk_uart0_ops = _getc, }; -static void _emsk_uart1_isr(void *ptr) +static struct rt_serial_device uart0; +static struct rt_serial_device uart1; +static struct rt_serial_device uart2; +static struct rt_serial_device uart3; + +static void uart0_isr(void *ptr) { - rt_hw_serial_isr((struct rt_serial_device*)&_emsk_uart1, RT_SERIAL_EVENT_RX_IND); + rt_hw_serial_isr((struct rt_serial_device*)&uart0, RT_SERIAL_EVENT_RX_IND); } -static const struct rt_uart_ops _emsk_uart1_ops = +static void uart1_isr(void *ptr) { - _configure, - _control, - _putc, - _getc, -}; + rt_hw_serial_isr((struct rt_serial_device*)&uart1, RT_SERIAL_EVENT_RX_IND); +} + +static void uart2_isr(void *ptr) +{ + rt_hw_serial_isr((struct rt_serial_device*)&uart2, RT_SERIAL_EVENT_RX_IND); +} + +static void uart3_isr(void *ptr) +{ + rt_hw_serial_isr((struct rt_serial_device*)&uart3, RT_SERIAL_EVENT_RX_IND); +} + int rt_hw_uart_init(void) { @@ -198,86 +160,165 @@ int rt_hw_uart_init(void) config.invert = NRZ_NORMAL; config.bufsz = RT_SERIAL_RB_BUFSZ; - _emsk_uart0.ops = &_emsk_uart0_ops; - _emsk_uart0.config = config; + uart0.ops = &uart_ops; + uart0.config = config; - _emsk_uart1.ops = &_emsk_uart1_ops; - _emsk_uart1.config = config; + uart1.ops = &uart_ops; + uart1.config = config; - /* open UART1 for USB-UART interface */ - uart = uart_get_dev(DW_UART_1_ID); - /* default format: 8bits, no parity, 1 stop bits */ - ret = uart->uart_open(config.baud_rate); + uart2.ops = &uart_ops; + uart2.config = config; - if (ret != E_OPNED && ret != E_OK) { - return RT_ERROR; + uart3.ops = &uart_ops; + uart3.config = config; + + /* uart0 init */ + uart = uart_get_dev(0); + + if (uart != NULL) { + /* default format: 8bits, no parity, 1 stop bits */ + ret = uart->uart_open(config.baud_rate); + + if (ret != E_OPNED && ret != E_OK) { + return RT_ERROR; + } + + /* enable rx int */ + uart->uart_control(UART_CMD_SET_RXINT, (void *)0); + /* use customized int isr */ + uart->uart_control(UART_CMD_SET_RXCB, uart0_isr); + uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL); + + rt_hw_serial_register(&uart0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + (void *)0); + } + + /* uart1 init */ + uart = uart_get_dev(1); + + if (uart != NULL) { + /* default format: 8bits, no parity, 1 stop bits */ + ret = uart->uart_open(config.baud_rate); + + if (ret != E_OPNED && ret != E_OK) { + return RT_ERROR; + } + + /* enable rx int */ + uart->uart_control(UART_CMD_SET_RXINT, (void *)0); + /* use customized int isr */ + uart->uart_control(UART_CMD_SET_RXCB, uart1_isr); + uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL); + + rt_hw_serial_register(&uart1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + (void *)1); } - /* enable rx int */ - uart->uart_control(UART_CMD_SET_RXINT, (void *)1); - /* use customized int isr */ - uart->uart_control(UART_CMD_SET_RXCB, _emsk_uart1_isr); - uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL); + /* uart2 init */ + uart = uart_get_dev(2); + + if (uart != NULL) { + /* default format: 8bits, no parity, 1 stop bits */ + ret = uart->uart_open(config.baud_rate); - rt_hw_serial_register(&_emsk_uart1, "uart1", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - (void *)DW_UART_1_ID); + if (ret != E_OPNED && ret != E_OK) { + return RT_ERROR; + } - /* open UART0 in PMOD A*/ - uart = uart_get_dev(DW_UART_0_ID); - /* default format: 8bits, no parity, 1 stop bits */ - ret = uart->uart_open(config.baud_rate); + /* enable rx int */ + uart->uart_control(UART_CMD_SET_RXINT, (void *)0); + /* use customized int isr */ + uart->uart_control(UART_CMD_SET_RXCB, uart2_isr); + uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL); - if (ret != E_OPNED && ret != E_OK) { - return RT_ERROR; + rt_hw_serial_register(&uart2, "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + (void *)2); } - /* enable rx int */ - uart->uart_control(UART_CMD_SET_RXINT, (void *)1); - /* use customized int isr */ - uart->uart_control(UART_CMD_SET_RXCB, _emsk_uart0_isr); - uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL); + /* uart3 init */ + uart = uart_get_dev(3); - rt_hw_serial_register(&_emsk_uart0, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - (void *)DW_UART_0_ID); + if (uart != NULL) { + /* default format: 8bits, no parity, 1 stop bits */ + ret = uart->uart_open(config.baud_rate); + + if (ret != E_OPNED && ret != E_OK) { + return RT_ERROR; + } + + /* enable rx int */ + uart->uart_control(UART_CMD_SET_RXINT, (void *)0); + /* use customized int isr */ + uart->uart_control(UART_CMD_SET_RXCB, uart3_isr); + uart->uart_control(UART_CMD_SET_RXINT_BUF, NULL); + + rt_hw_serial_register(&uart3, "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + (void *)3); + } return RT_EOK; } +#if defined BOARD_EMSK +#define CONSOLE_UART "uart1" +struct rt_serial_device *console_uart = &uart1; +#elif defined BOARD_IOTDK || defined BOARD_EMSDP || defined BOARD_NSIM +#define CONSOLE_UART "uart0" +struct rt_serial_device *console_uart = &uart0; +#elif defined BOARD_AXS +#define CONSOLE_UART "uart2" +struct rt_serial_device *console_uart = &uart2; +#elif defined BOARD_HSDK +#define CONSOLE_UART "uart3" +struct rt_serial_device *console_uart = &uart3; +#else +#error "no supported board selected!" +#endif + void rt_hw_console_output(const char *str) { while(*str != '\0') { if (*str == '\n') { - _putc(&_emsk_uart1,'\r'); + _putc(console_uart,'\r'); } - _putc(&_emsk_uart1,*str); + _putc(console_uart,*str); str++; } } +void rt_hw_board_init() +{ + rt_hw_uart_init(); + rt_components_board_init(); + rt_console_set_device(CONSOLE_UART); +} + + + +static void rt_hw_timer_isr(int vector, void *param) +{ + timer_int_clear(BOARD_OS_TIMER_ID); + rt_tick_increase(); +} + int rt_hw_timer_init(void) { unsigned int cyc = BOARD_CPU_CLOCK / RT_TICK_PER_SECOND; int_disable(BOARD_OS_TIMER_INTNO); /* disable os timer interrupt */ - arc_timer_stop(BOARD_OS_TIMER_ID); - arc_timer_start(BOARD_OS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cyc); + timer_stop(BOARD_OS_TIMER_ID); + timer_start(BOARD_OS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cyc); - int_handler_install(BOARD_OS_TIMER_INTNO, (INT_HANDLER)rt_hw_timer_isr); + int_handler_install(BOARD_OS_TIMER_INTNO, (INT_HANDLER_T)rt_hw_timer_isr); + int_pri_set(BOARD_OS_TIMER_INTNO, INT_PRI_MIN + 1); /* currently, firq(INT_PRI_MIN) not supported*/ int_enable(BOARD_OS_TIMER_INTNO); return 0; } INIT_BOARD_EXPORT(rt_hw_timer_init); - -void rt_hw_board_init() -{ - emsk_mux_init(); - - rt_hw_uart_init(); - rt_components_board_init(); - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -} diff --git a/bsp/synopsys/emsk_em9d/drivers/board.h b/bsp/synopsys/boards/drivers/rt_board.h similarity index 30% rename from bsp/synopsys/emsk_em9d/drivers/board.h rename to bsp/synopsys/boards/drivers/rt_board.h index aebf88bd422d6eaff2c8c3b3a22a72c81655c7b1..734ffc8aa5e281040bf6c098d31a761dffadcfe0 100644 --- a/bsp/synopsys/emsk_em9d/drivers/board.h +++ b/bsp/synopsys/boards/drivers/rt_board.h @@ -4,22 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef __BOARD_H__ -#define __BOARD_H__ +#ifndef __RT_BOARD_H__ +#define __RT_BOARD_H__ -#include "emsk_hardware.h" - -#define BOARD_OS_TIMER_ID 0 -#define BOARD_OS_TIMER_INTNO 16 -#define BOARD_CPU_CLOCK 25000000 - -#if defined(__GNUC__) -extern int __start_heap; -#define HEAP_BEGIN ((void*)&__start_heap) -#endif - -extern int __end_heap; -#define HEAP_END (void*)(&__end_heap) +#include "board.h" void rt_hw_board_init(); diff --git a/bsp/synopsys/boards/linker_template_gnu.ld b/bsp/synopsys/boards/linker_template_gnu.ld new file mode 100644 index 0000000000000000000000000000000000000000..e253bc635c80fa4cc70ae6d7c523bdf01ddb0e02 --- /dev/null +++ b/bsp/synopsys/boards/linker_template_gnu.ld @@ -0,0 +1,169 @@ +#define __ASSEMBLY__ +#include + +MEMORY +{ +#if (REGION_ICCM_SIZE != 0) + REGION_ICCM : ORIGIN = REGION_ICCM_START, LENGTH = REGION_ICCM_SIZE +#endif +#if (REGION_DCCM_SIZE !=0) + REGION_DCCM : ORIGIN = REGION_DCCM_START, LENGTH = REGION_DCCM_SIZE +#endif +#if (REGION_XCCM_SIZE != 0) + REGION_XCCM : ORIGIN = REGION_XCCM_START, LENGTH = REGION_XCCM_SIZE +#endif +#if (REGION_YCCM_SIZE != 0) + REGION_YCCM : ORIGIN = REGION_YCCM_START, LENGTH = REGION_YCCM_SIZE +#endif +#if (REGION_EXT_ROM_SIZE != 0) + REGION_EXT_ROM : ORIGIN = REGION_EXT_ROM_START, LENGTH = REGION_EXT_ROM_SIZE +#endif +#if (REGION_EXT_RAM_SIZE != 0) + REGION_EXT_RAM : ORIGIN = REGION_EXT_RAM_START, LENGTH = REGION_EXT_RAM_SIZE +#endif +} + +ENTRY(_start) + +SECTIONS +{ + .init : + { + . = . + IMAGE_HEAD_SIZE; + _f_init = .; + KEEP (*(.init_vector .init_vector.*)) + KEEP (*(.init_bootstrap .init_bootstrap.*)) + _e_init = .; + } > REGION_ROM + + .vector : ALIGN(1024) + { + _f_vector = .; + *(.vector .vector.*) + _e_vector = .; + } > REGION_ROM + +#if (REGION_XCCM_SIZE != 0) + .x_ccm (NOLOAD) : ALIGN(8) + { + _f_x_ccm = .; + *(.x_ccm .x_cmm.*) + _e_x_ccm = .; + } > REGION_XCCM +#endif + +#if (REGION_YCCM_SIZE != 0) + .y_ccm (NOLOAD) : ALIGN(8) + { + _f_y_ccm = .; + *(.y_ccm .y_ccm.*) + _e_y_ccm = .; + } > REGION_YCCM +#endif + .text : ALIGN(4) + { + _f_text = .; + *(.text .text.* .gnu.linkonce.t.*) + _e_text = .; + } > REGION_ROM + + .rodata : ALIGN(4) + { + _f_rodata = .; + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __CTOR_LIST__ = .; + LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) + KEEP(*(SORT_BY_NAME(".ctors*"))) + LONG(0) + __CTOR_END__ = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP(*(SORT_BY_NAME(".init_array*"))) + __init_array_end = .; + + . = ALIGN(4); + __DTOR_LIST__ = .; + LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) + KEEP(*(SORT_BY_NAME(".dtors*"))) + LONG(0) + __DTOR_END__ = .; + + *(.rodata .rodata.* .gnu.linkonce.r.*) + _e_rodata = .; + } > REGION_ROM + + .data : ALIGN(4) + { + _f_data = .; + *(.data .data.* .gnu.linkonce.d.*) + _f_sdata = .; + __SDATA_BEGIN__ = .; + *(.sdata .sdata.* .gnu.linkonce.s.*) + PROVIDE (__sbss_start = .); + PROVIDE (___sbss_start = .); + _f_sbss = .; + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + _e_sbss = .; + PROVIDE (__sbss_end = .); + PROVIDE (___sbss_end = .); +#if defined(EMBARC_UNIT_TEST) + . = ALIGN(8); + _f_embarc_unittest = .; + KEEP(*(.embarc_unittest)) + _e_embarc_unittest = .; +#endif + _e_sdata = .; + _e_data = .; + } > REGION_RAM AT > REGION_ROM + + .bss (NOLOAD) : ALIGN(8) + { + _f_bss = .; + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + _e_bss = .; + } > REGION_RAM + + .stack (NOLOAD) : + { + . = ALIGN(4); + _f_stack = .; + . = . + _STACKSIZE; + _e_stack = .; + } > REGION_RAM + + .heap (NOLOAD) : + { + . = ALIGN(4); + __start_heap = . ; + _f_heap = .; + . = . + _HEAPSIZE; + _e_heap = .; + __end_heap = . ; + } > REGION_RAM + + _load_addr_text = LOADADDR(.text); + _load_addr_rodata = LOADADDR(.rodata); + _load_addr_data = LOADADDR(.data); +} diff --git a/bsp/synopsys/boards/linker_template_mw.ld b/bsp/synopsys/boards/linker_template_mw.ld new file mode 100644 index 0000000000000000000000000000000000000000..248dc5ac4caa7c8efbd10ed762c4247e979ce387 --- /dev/null +++ b/bsp/synopsys/boards/linker_template_mw.ld @@ -0,0 +1,154 @@ +#define __ASSEMBLY__ +#include + +MEMORY { +#if (REGION_ICCM_SIZE != 0) + REGION_ICCM : ORIGIN = REGION_ICCM_START, LENGTH = REGION_ICCM_SIZE +#endif +#if (REGION_DCCM_SIZE !=0) + REGION_DCCM : ORIGIN = REGION_DCCM_START, LENGTH = REGION_DCCM_SIZE +#endif +#if (REGION_XCCM_SIZE != 0) + REGION_XCCM : ORIGIN = REGION_XCCM_START, LENGTH = REGION_XCCM_SIZE +#endif +#if (REGION_YCCM_SIZE != 0) + REGION_YCCM : ORIGIN = REGION_YCCM_START, LENGTH = REGION_YCCM_SIZE +#endif +#if (REGION_EXT_ROM_SIZE != 0) + REGION_EXT_ROM : ORIGIN = REGION_EXT_ROM_START, LENGTH = REGION_EXT_ROM_SIZE +#endif +#if (REGION_EXT_RAM_SIZE != 0) + REGION_EXT_RAM : ORIGIN = REGION_EXT_RAM_START, LENGTH = REGION_EXT_RAM_SIZE +#endif +} + +ENTRY(_start) + +SECTIONS { + + GROUP : { + .image_head: { + . = . + IMAGE_HEAD_SIZE; + } + .init_bootstrap:{ + _f_init = .; + *(.init_vector .init_vector.*) + *(.init_bootstrap .init_bootstrap.*) + _e_init = .; + } + .vector ALIGN(1024): { + _f_vector = .; + *(.vector .vector.*) + _e_vector = .; + } + } > REGION_ROM + +#if (REGION_XCCM_SIZE != 0) + GROUP (NOLOAD): { + .x_ccm ALIGN(8): { + _f_x_ccm = .; + *(.x_ccm) + *(.x_ccm.*) + _e_x_ccm = .; + } + } > REGION_XCCM +#endif + +#if (REGION_YCCM_SIZE != 0) + GROUP (NOLOAD): { + .y_ccm ALIGN(8): { + _f_y_ccm = .; + *(.y_ccm) + *(.y_ccm.*) + _e_y_ccm = .; + } + } > REGION_YCCM +#endif + + GROUP : { + + .text ALIGN(4): { + _f_text = .; + *(TYPE text) + *(.text*) + _e_text = .; + } + + .rodata ALIGN(4): { + _f_rodata = .; + + _fctors = .; + *(.ctors*) + _ectors = .; + _fdtors = .; + *(.dtors*) + _edtors = .; + _feh_frame = .; + *(.eh_frame*) + _eeh_frame = .; + + *(TYPE lit) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + *(FSymTab*) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + *(VSymTab*) + __vsymtab_end = .; + + . = ALIGN(4); + __rt_init_start = .; + *(.rti_fn*) + __rt_init_end = .; + . = ALIGN(4); + + _e_rodata = .; + } + + } > REGION_ROM + + + GROUP : { + .data ALIGN(8): { + _f_data = .; + _f_sdata = .; + *(.sdata) + *(.sbss) + _e_sdata = .; + *(TYPE data) + } +#if defined(EMBARC_UNIT_TEST) + .unit_test ALIGN(8): { + _f_embarc_unittest = .; + KEEP(*(".embarc_unittest")) + _e_embarc_unittest = .; + } +#endif + .tls ALIGN(8): { + *(.tls*) + _e_data = .; + } + } > REGION_RAM AT > REGION_ROM + + GROUP (NOLOAD) : { + .bss ALIGN(8): { + _f_bss = .; + *(TYPE bss) + _e_bss = .; + } + .stack ALIGN(4) SIZE(_STACKSIZE): {} + .heap? ALIGN(4) SIZE(_HEAPSIZE): {} + } > REGION_RAM + + _f_stack = ADDR(.stack); + _e_stack = ADDR(.stack) + SIZEOF(.stack); + _f_heap = ADDR(.heap); + _e_heap = ADDR(.heap) + SIZEOF(.heap); + + _load_addr_text = LOADADDR(.text); + _load_addr_rodata = LOADADDR(.rodata); + _load_addr_data = LOADADDR(.data); +} diff --git a/bsp/synopsys/boards/rtconfig.h b/bsp/synopsys/boards/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..6df6176c16213f52070e14c43d72c59c93c187cb --- /dev/null +++ b/bsp/synopsys/boards/rtconfig.h @@ -0,0 +1,157 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 16 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_DEBUG +#define RT_DEBUG_COLOR +#define RT_DEBUG_INIT_CONFIG +#define RT_DEBUG_INIT 1 + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40002 +#define RT_USING_CPU_FFS + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 1024 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 8 +#define RT_USING_SERIAL +#define RT_SERIAL_RB_BUFSZ 1024 + +/* Using USB */ + + +/* POSIX layer and C standard library */ + + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + +#define PKG_USING_EMBARC_BSP +#define PKG_USING_EMBARC_BSP_UPSTREAM_VERSION + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define SOC_EMSK +#define EMSK_USING_UART0 +#define EMSK_USING_UART1 + +#endif diff --git a/bsp/synopsys/emsk_em9d/rtconfig.py b/bsp/synopsys/boards/rtconfig.py similarity index 30% rename from bsp/synopsys/emsk_em9d/rtconfig.py rename to bsp/synopsys/boards/rtconfig.py index 7ba12867fd8f9dd3c1ae5df4e4d13827ac2b477c..0bafd172b5b43a9f9f946499c21129cb7b65f002 100644 --- a/bsp/synopsys/emsk_em9d/rtconfig.py +++ b/bsp/synopsys/boards/rtconfig.py @@ -8,12 +8,15 @@ CROSS_TOOL='gcc' if os.getenv('RTT_CC'): CROSS_TOOL = os.getenv('RTT_CC') -# only support GNU GCC compiler -PLATFORM = 'gcc' -EXEC_PATH = 'C:/arc/gnu/bin' +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = 'C:/arc_gnu/bin' +elif CROSS_TOOL =='mw': + PLATFORM = 'mw' + EXEC_PATH = 'C:/ARC/MetaWare/arc/bin' -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') +# if os.getenv('RTT_EXEC_PATH'): +# EXEC_PATH = os.getenv('RTT_EXEC_PATH') BUILD = 'debug' @@ -30,31 +33,26 @@ if PLATFORM == 'gcc': OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' DBG = PREFIX + 'gdb' - DEVICE = ' -mno-sdata -Wall -mcpu=em4_fpus -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel-shifter -mfpu=fpus_all' - CFLAGS = DEVICE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' - LINK_SCRIPT = 'emsk_em9d.ld' - LFLAGS = DEVICE + ' -mno-sdata -nostartfiles -Wl,--gc-sections,-Map=emsk_em9d.map,-cref,-u,system_vectors -T %s' % LINK_SCRIPT - OPENOCD_SCRIPT_ROOT = 'C:/arc/gnu/share/openocd/scripts' - OPENOCD_CFG_FILE = OPENOCD_SCRIPT_ROOT + '/board/snps_em_sk_v2.2.cfg' + TARGET = 'rtthread_snps_embarc.elf' - OPENOCD_OPTIONS = '-s %s -f %s' % (OPENOCD_SCRIPT_ROOT, OPENOCD_CFG_FILE) - - DBG_HW_FLAGS = ''' -ex "target remote | openocd --pipe %s" -ex "load" ''' % OPENOCD_OPTIONS - - - TARGET = 'rtthread_snps_emsk_em9d.' + TARGET_EXT + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_snps_embarc.bin\n' +\ + SIZE + ' $TARGET \n' - CPATH = '' - LPATH = '' +elif PLATFORM == 'mw': + # toolchains + CC = 'ccac' + CXX = 'ccac' + AS = 'ccac' + AR = 'arac' + LINK = 'ccac' + TARGET_EXT = 'elf' + SIZE = 'sizeac' + OBJDUMP = 'elfdumpac' + OBJCPY = 'elf2bin' + DBG = 'mdb' - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' + TARGET = 'rtthread_snps_embarc.elf' - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\ + POST_ACTION = OBJCPY + ' $TARGET rtthread_snps_embarc.bin\n' +\ SIZE + ' $TARGET \n' - #POST_ACTION = DBG + DBG_HW_FLAGS + TARGET diff --git a/bsp/synopsys/embarc/SConscript b/bsp/synopsys/embarc/SConscript deleted file mode 100644 index 9e086739af643b16f0b06432fa76db062ea0e16b..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/SConscript +++ /dev/null @@ -1,28 +0,0 @@ -from building import * - -cwd = GetCurrentDir() - -embarc_arc_hal_SRCS = Split(""" -arc/arc_cache.c -arc/arc_exc_asm.S -arc/arc_exception.c -arc/arc_timer.c -arc/startup/arc_cxx_support.c -arc/startup/arc_startup.S -device/designware/uart/dw_uart.c -device/designware/gpio/dw_gpio.c -""") - - -ASFLAGS = ' -I' + cwd - -src = embarc_arc_hal_SRCS - -path = [cwd, - cwd + '/arc', - cwd + '/arc/startup' - ] - -group = DefineGroup('embarc', src, depend = [], CPPPATH = path, ASFLAGS = ASFLAGS) - -Return('group') diff --git a/bsp/synopsys/embarc/arc/arc_cache.c b/bsp/synopsys/embarc/arc/arc_cache.c deleted file mode 100644 index 632a3e32919a2329d4e4122e7a0fd287c424f0e2..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/arc/arc_cache.c +++ /dev/null @@ -1,420 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-07-15 - * \author Wayne Ren(Wei.Ren@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup ARC_HAL_MISC_CACHE - * \brief implementation of cache related functions - */ - -#include "inc/arc/arc_cache.h" - -#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) - - -struct cache_config { - uint8_t ver; /* version */ - uint8_t assoc; /* Cache Associativity */ - uint16_t line; /* cache line/block size */ - uint32_t capacity; /* capacity */ -}; - - -static struct cache_config icache_config, dcache_config; - -/** - * \brief invalidate multi instruction cache lines - * - * \param[in] start_addr start address in instruction cache - * \param[in] size the bytes to be invalidated - * \return 0, succeeded, -1, failed - */ -int32_t icache_invalidate_mlines(uint32_t start_addr, uint32_t size) -{ - if (!icache_available()) return -1; - - if ((size == 0) || (size > icache_config.capacity)) { - return -1; - } - - uint32_t end_addr; - uint32_t line_size; - uint32_t status; - - line_size = (uint32_t)(icache_config.line); - end_addr = start_addr + size - 1; - start_addr &= (uint32_t)(~(line_size - 1)); - - status = cpu_lock_save(); - do { - _arc_aux_write(AUX_IC_IVIL, start_addr); - Asm("nop_s"); - Asm("nop_s"); - Asm("nop_s"); - start_addr += line_size; - } while (start_addr <= end_addr); - cpu_unlock_restore(status); - - return 0; -} - -/** - * \brief lock multi lines in instruction cache - * - * \param[in] start_addr start address in instruction cache - * \param[in] size the bytes to be locked - * \return 0, succeeded, -1, failed (cache already locked or other reasons) - */ -int32_t icache_lock_mlines(uint32_t start_addr, uint32_t size) -{ - if (!icache_available()) return -1; - - if ((size == 0) || (size > icache_config.capacity)) { - return -1; - } - - uint32_t end_addr; - uint32_t line_size; - uint32_t status; - int32_t ercd = 0; - - line_size = (uint32_t)(icache_config.line); - end_addr = start_addr + size - 1; - start_addr &= (uint32_t)(~(line_size - 1)); - - status = cpu_lock_save(); - do { - _arc_aux_write(AUX_IC_LIL, start_addr); - if(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) { - start_addr += line_size; - } else { - ercd = -1; /* the operation failed */ - break; - } - } while (start_addr <= end_addr); - cpu_unlock_restore(status); - - return ercd; -} - -/** - * \brief directly write icache internal ram - * - * \param[in] cache_addr, icache internal address(way+index+offset) - * \param[in] tag cache tag to write (tag+lock bit+valid bit) - * \param[in] data cache data to write - * \return 0, succeeded, -1, failed - */ -int32_t icache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data) -{ - if (!icache_available()) return -1; - - if (_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS) { - return -1; - } - _arc_aux_write(AUX_IC_RAM_ADDR, cache_addr); - _arc_aux_write(AUX_IC_TAG, tag ); - _arc_aux_write(AUX_IC_DATA, data); - - return 0; -} - -/** - * \brief directly read icache internal ram - * - * \param[in] cache_addr, icache internal address(way+index+offset) - * \param[out] tag cache tag to read (tag+index+lock bit+valid bit) - * \param[out] data cache data to read - * \return 0, succeeded, -1, failed - */ -int32_t icache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data) -{ - if (!icache_available()) return -1; - - if (_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS) { - return -1; - } - _arc_aux_write(AUX_IC_RAM_ADDR, cache_addr); - *tag = _arc_aux_read(AUX_IC_TAG); - *data = _arc_aux_read(AUX_IC_DATA); - - return 0; -} - -/** - * \brief indirectly read icache internal ram - * - * \param[in] mem_addr, memory address - * \param[out] tag cache tag to read - * \param[out] data cache data to read - * \return 0, succeeded, -1, failed - */ -int32_t icache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data) -{ - if (!icache_available()) return -1; - - if (!(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_INDIRECT_ACCESS)) { - return -1; - } - _arc_aux_write(AUX_IC_RAM_ADDR, mem_addr); - if(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) { - *tag = _arc_aux_read(AUX_IC_TAG); - *data = _arc_aux_read(AUX_IC_DATA); - } else { - return -1; /* the specified memory is not in icache */ - } - return 0; - } - -/** - * \brief invalidate multi data cache lines - * - * \param[in] start_addr start address in data cache - * \param[in] size the bytes to be invalidated - * \return 0, succeeded, -1, failed - */ -int32_t dcache_invalidate_mlines(uint32_t start_addr, uint32_t size) -{ - if (!dcache_available()) return -1; - - uint32_t end_addr; - uint32_t line_size; - uint32_t status; - - if ((size == 0) || (size > dcache_config.capacity)) { - return -1; - } - - line_size = (uint32_t)(dcache_config.line); - end_addr = start_addr + size - 1; - start_addr &= (uint32_t)(~(line_size - 1)); - - status = cpu_lock_save(); - do { - _arc_aux_write(AUX_DC_IVDL, start_addr); - Asm("nop_s"); - Asm("nop_s"); - Asm("nop_s"); - /* wait for flush completion */ - while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); - start_addr += line_size; - } while (start_addr <= end_addr); - cpu_unlock_restore(status); - - return 0; - -} - -/** - * \brief flush multi lines in data cache - * - * \param[in] start_addr start address - * \param[in] size the bytes to be flushed - * \return 0, succeeded, -1, failed - */ -int32_t dcache_flush_mlines(uint32_t start_addr, uint32_t size) -{ - if (!dcache_available()) return -1; - - if ((size == 0) || (size > dcache_config.capacity)) { - return -1; - } - - uint32_t end_addr; - uint32_t line_size; - uint32_t status; - - line_size = (uint32_t)(dcache_config.line); - end_addr = start_addr + size - 1; - start_addr &= (uint32_t)(~(line_size - 1)); - - status = cpu_lock_save(); - do { - _arc_aux_write(AUX_DC_FLDL, start_addr); - Asm("nop_s"); - Asm("nop_s"); - Asm("nop_s"); - /* wait for flush completion */ - while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); - start_addr += line_size; - } while (start_addr <= end_addr); - cpu_unlock_restore(status); - - return 0; -} - -/** - * \brief lock multi lines in data cache - * - * \param[in] start_addr start address in data cache - * \param[in] size the bytes to be locked - * \return 0, succeeded, -1, failed - */ -int32_t dcache_lock_mlines(uint32_t start_addr, uint32_t size) -{ - if (!dcache_available()) return -1; - - if ((size == 0) || (size > dcache_config.capacity)) { - return -1; - } - - uint32_t end_addr; - uint32_t line_size; - uint32_t status; - int32_t ercd = 0; - - line_size = (uint32_t)(dcache_config.line); - end_addr = start_addr + size - 1; - start_addr &= (uint32_t)(~(line_size - 1)); - - status = cpu_lock_save(); - do { - _arc_aux_write(AUX_DC_LDL, start_addr); - Asm("nop_s"); - if(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) { - start_addr += line_size; - } else { - ercd = -1; /* the operation failed */ - break; - } - } while (start_addr <= end_addr); - cpu_unlock_restore(status); - - return ercd; -} - -/** - * \brief directly write dcache internal ram - * - * \param[in] cache_addr, dcache internal address(way+index+offset) - * \param[in] tag cache tag to write - * \param[in] data cache data to write - * \return 0, succeeded, -1, failed - */ -int32_t dcache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data) -{ - if (!dcache_available()) return -1; - - if (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS) { - return -1; - } - _arc_aux_write(AUX_DC_RAM_ADDR, cache_addr); - _arc_aux_write(AUX_DC_TAG, tag); - _arc_aux_write(AUX_DC_DATA, data); - - return 0; -} - -/** - * \brief directly read dcache internal ram - * - * \param[in] cache_addr, dcache internal address(way+index+offset) - * \param[out] tag cache tag to read - * \param[out] data cache data to read - * \return 0, succeeded, -1, failed - */ -int32_t dcache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data) -{ - if (!dcache_available()) return -1; - - if (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS) { - return -1; - } - _arc_aux_write(AUX_DC_RAM_ADDR, cache_addr); - *tag = _arc_aux_read(AUX_DC_TAG); - *data = _arc_aux_read(AUX_DC_DATA); - - return 0; -} - -/** - * \brief indirectly read dcache internal ram - * - * \param[in] mem_addr, memory address(tag+index+offset) - * \param[out] tag cache tag to read - * \param[out] data cache data to read - * \return 0, succeeded, -1, failed - */ -int32_t dcache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data) -{ - if (!dcache_available()) return -1; - - if (!(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_INDIRECT_ACCESS)) { - return -1; - } - _arc_aux_write(AUX_DC_RAM_ADDR, mem_addr); - if(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) { - *tag = _arc_aux_read(AUX_DC_TAG); - *data = _arc_aux_read(AUX_DC_DATA); - } else { - return -1; /* the specified memory is not in dcache */ - } - return 0; - } - -/** - * \brief initialize cache - * 1. invalidate icache and dcache - * 2. Only support ARCv2 cache - */ -void arc_cache_init(void) -{ - uint32_t build_cfg; - - build_cfg = _arc_aux_read(AUX_BCR_D_CACHE); - - dcache_config.ver = build_cfg & 0xff; - - if (dcache_config.ver >= 0x04) { /* ARCv2 */ - dcache_enable(DC_CTRL_DISABLE_FLUSH_LOCKED | - DC_CTRL_INDIRECT_ACCESS | DC_CTRL_INVALID_FLUSH); - dcache_invalidate(); - dcache_config.assoc = 1 << ((build_cfg >> 8) & 0xf); - dcache_config.capacity = 512 << ((build_cfg >> 12) & 0xf); - dcache_config.line = 16 << ((build_cfg >> 16) & 0xf); - } - - build_cfg = _arc_aux_read(AUX_BCR_I_CACHE); - - icache_config.ver = build_cfg & 0xff; - - if (icache_config.ver >= 0x04) { /* ARCv2 */ - icache_config.assoc = 1 << ((build_cfg >> 8) & 0xf); - icache_config.capacity = 512 << ((build_cfg >> 12) & 0xf); - icache_config.line = 8 << ((build_cfg >> 16) & 0xf); - - icache_enable(IC_CTRL_IC_ENABLE); - icache_invalidate(); - } - -} diff --git a/bsp/synopsys/embarc/arc/arc_exc_asm.S b/bsp/synopsys/embarc/arc/arc_exc_asm.S deleted file mode 100644 index 7410db315457d37e577582a543b59fbbe3ff89b4..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/arc/arc_exc_asm.S +++ /dev/null @@ -1,201 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-07-15 - * \author Wayne Ren(Wei.Ren@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup ARC_HAL_EXCEPTION_CPU - * \brief assembly part of exception and interrupt processing - */ - -/** - * \addtogroup ARC_HAL_EXCEPTION_CPU - * @{ - */ - -/* function documentation */ -/** - * \fn void exc_entry_cpu(void) - * \brief default entry of CPU exceptions, such as TLB miss and swap. - * - * \fn void exc_entry_int(void) - * \brief normal interrupt exception entry. - * In default, all interrupt exceptions are installed with normal entry. - * If FIRQ is required, exc_entry_firq should be the entry. - * - * \fn void exc_entry_firq(void) - * \brief firq exception entry - */ -/** }@ */ - -/** @cond EXCEPTION_ASM */ - -#define __ASSEMBLY__ -#include "inc/arc/arc.h" -#include "inc/arc/arc_asm_common.h" - - .file "arc_exc_asm.S" - -/* entry for cpu exception handling */ - .text - .global exc_entry_cpu - .weak exc_entry_cpu - .align 4 -exc_entry_cpu: - - EXCEPTION_PROLOGUE - - mov r3, sp /* as exception handler's para(exc_frame) */ - -/* exc_nest_count +1 */ - ld r0, [exc_nest_count] - add r0, r0, 1 - st r0, [exc_nest_count] - -/* find the exception cause */ - lr r0, [AUX_ECR] - lsr r0, r0, 16 - bmsk r0, r0, 7 - mov r1, exc_int_handler_table - ld.as r2, [r1, r0] - - mov r0, r3 - jl [r2] /* jump to exception handler where interrupts are not allowed! */ - -/* interrupts are not allowed */ -exc_return: - -/* exc_nest_count -1 */ - ld r0, [exc_nest_count] - sub r0, r0, 1 - st r0, [exc_nest_count] - - EXCEPTION_EPILOGUE - rtie - - -/****** entry for normal interrupt exception handling ******/ - .global exc_entry_int - .weak exc_entry_int - .align 4 -exc_entry_int: - clri /* disable interrupt */ - -#if ARC_FEATURE_FIRQ == 1 -#if ARC_FEATURE_RGF_NUM_BANKS > 1 - lr r0, [AUX_IRQ_ACT] /* check whether it is P0 interrupt */ - btst r0, 0 - bnz exc_entry_firq -#else - PUSH r10 - lr r10, [AUX_IRQ_ACT] - btst r10, 0 - POP r10 - bnz exc_entry_firq -#endif -#endif - INTERRUPT_PROLOGUE /* save scratch regs, this will be affected */ - - -/* exc_nest_count +1 */ - ld r0, [exc_nest_count] - add r0, r0, 1 - st r0, [exc_nest_count] - - - lr r0, [AUX_IRQ_CAUSE] - mov r1, exc_int_handler_table - ld.as r2, [r1, r0] /* r2 = _kernel_exc_tbl + irqno *4 */ - -/* for the case of software triggered interrupt */ - lr r3, [AUX_IRQ_HINT] - cmp r3, r0 - bne.d irq_hint_handled - xor r3, r3, r3 - sr r3, [AUX_IRQ_HINT] -irq_hint_handled: - seti /* enable higher priority interrupt */ - - mov r0, sp - jl [r2] /* jump to interrupt handler */ - -/* no interrupts are allowed from here */ -int_return: - clri /* disable interrupt */ - -/* exc_nest_count -1 */ - ld r0, [exc_nest_count] - sub r0, r0, 1 - st r0, [exc_nest_count] - - INTERRUPT_EPILOGUE - rtie - -/****** entry for fast irq exception handling ******/ - .global exc_entry_firq - .weak exc_entry_firq - .align 4 -exc_entry_firq: - clri /* disable interrupt */ - SAVE_FIQ_EXC_REGS - -/* exc_nest_count +1 */ - ld r0, [exc_nest_count] - add r0, r0, 1 - st r0, [exc_nest_count] - - lr r0, [AUX_IRQ_CAUSE] - mov r1, exc_int_handler_table - ld.as r2, [r1, r0] /* r2 = _kernel_exc_tbl + irqno *4 */ - -/* for the case of software triggered interrupt */ - lr r3, [AUX_IRQ_HINT] - cmp r3, r0 - bne.d firq_hint_handled - xor r3, r3, r3 - sr r3, [AUX_IRQ_HINT] -firq_hint_handled: - - jl [r2] /* jump to interrupt handler */ - -/* no interrupts are allowed from here */ -firq_return: - -/* exc_nest_count -1 */ - ld r0, [exc_nest_count] - sub r0, r0, 1 - st r0, [exc_nest_count] - - RESTORE_FIQ_EXC_REGS - rtie - -/** @endcond */ diff --git a/bsp/synopsys/embarc/arc/arc_exception.c b/bsp/synopsys/embarc/arc/arc_exception.c deleted file mode 100644 index a256b0b394a473ce0877fe0851ac220dde8f4948..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/arc/arc_exception.c +++ /dev/null @@ -1,501 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-07-15 - * \author Wayne Ren(Wei.Ren@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup ARC_HAL_EXCEPTION_CPU ARC_HAL_EXCEPTION_INTERRUPT - * \brief C Implementation of exception and interrupt management - */ -#include "inc/arc/arc_exception.h" -#include "inc/arc/arc_cache.h" - -//#define DBG_LESS -//#include "embARC_debug.h" - -/** - * \addtogroup ARC_HAL_EXCEPTION_CPU - * @{ - * \var exc_entry_table - * \brief exception entry table - * - * install exception entry table to ARC_AUX_INT_VECT_BASE in startup. - * According to ARCv2 ISA, vectors are fetched in instruction space and thus - * may be present in ICCM, Instruction Cache, or - * main memory accessed by instruction fetch logic. - * So it is put into a specific section .vector. - * - * Please note that the exc_entry_table maybe cached in ARC. Some functions is - * defined in .s files. - * - */ - -/** - * \ingroup ARC_HAL_EXCEPTION_CPU - * \brief default cpu exception handler - * \param p_excinf pointer to the exception frame - */ -static void exc_handler_default(void *p_excinf) -{ - // uint32_t excpt_cause_reg = 0; - // uint32_t excpt_ret_reg = 0; - // uint32_t exc_no = 0; - - // excpt_cause_reg = _arc_aux_read(AUX_ECR); - // excpt_ret_reg = _arc_aux_read(AUX_ERRET); - // exc_no = (excpt_cause_reg >> 16) & 0xff; - - Asm("kflag 1"); -} - - -/** - * \ingroup ARC_HAL_EXCEPTION_INTERRUPT - * \brief default interrupt handler - * \param[in] p_excinf information for interrupt handler - */ -static void int_handler_default(void *p_excinf) -{ - // uint32_t int_cause_reg = 0; - - // int_cause_reg = _arc_aux_read(AUX_IRQ_CAUSE); - Asm("kflag 1"); -} - -__attribute__ ((aligned(1024), section(".vector"))) -EXC_ENTRY exc_entry_table[NUM_EXC_ALL] = { - [0] = _arc_reset, - [1 ... NUM_EXC_CPU-1] = exc_entry_cpu, - [NUM_EXC_CPU ... NUM_EXC_ALL-1] = exc_entry_int - }; -/** - * \var exc_int_handler_table - * \brief the cpu exception and interrupt exception handler table - * called in exc_entry_default and exc_entry_int - */ -EXC_HANDLER exc_int_handler_table[NUM_EXC_ALL] = { - [0 ... NUM_EXC_CPU-1] = exc_handler_default, - [NUM_EXC_CPU ... NUM_EXC_ALL-1] = int_handler_default -}; - -/** - * \var exc_nest_count - * \brief the counter for exc/int processing, =0 no int/exc - * >1 in int/exc processing - * @} - */ -uint32_t exc_nest_count; - -typedef struct aux_irq_ctrl_field { - /* note: little endian */ - uint32_t save_nr_gpr_pairs: 5; /** Indicates number of general-purpose register pairs saved, from 0 to 8/16 */ - uint32_t res: 4; /** Reserved */ - uint32_t save_blink: 1; /** Indicates whether to save and restore BLINK */ - uint32_t save_lp_regs: 1; /** Indicates whether to save and restore loop registers (LP_COUNT, LP_START, LP_END) */ - uint32_t save_u_to_u: 1; /** Indicates if user context is saved to user stack */ - uint32_t res2: 1; /** Reserved */ - uint32_t save_idx_regs: 1; /** Indicates whether to save and restore code-density registers (EI_BASE, JLI_BASE, LDI_BASE) */ - uint32_t res3: 18; /** Reserved */ -} aux_irq_ctrl_field_t; - -typedef union { - aux_irq_ctrl_field_t bits; - uint32_t value; -} aux_irq_ctrl_t; - -/** - * \ingroup ARC_HAL_EXCEPTION_CPU ARC_HAL_EXCEPTION_INTERRUPT - * \brief intialize the exception and interrupt handling - */ -void exc_int_init(void) -{ - uint32_t i; - uint32_t status; - aux_irq_ctrl_t ictrl; - - ictrl.value = 0; - -#ifndef ARC_FEATURE_RF16 - ictrl.bits.save_nr_gpr_pairs = 6; /* r0 to r11 (r12 saved manually) */ -#else - ictrl.bits.save_nr_gpr_pairs = 3; /* r0 to r3, r10, r11 */ -#endif - ictrl.bits.save_blink = 1; - ictrl.bits.save_lp_regs = 1; /* LP_COUNT, LP_START, LP_END */ - ictrl.bits.save_u_to_u = 0; /* user ctxt saved on kernel stack */ - ictrl.bits.save_idx_regs = 1; /* JLI, LDI, EI */ - - status = arc_lock_save(); - for (i = NUM_EXC_CPU; i < NUM_EXC_ALL; i++) { - /* interrupt level triggered, disabled, priority is the lowest */ - _arc_aux_write(AUX_IRQ_SELECT, i); - _arc_aux_write(AUX_IRQ_ENABLE, 0); - _arc_aux_write(AUX_IRQ_TRIGGER, 0); -#if defined(ARC_FEATURE_SEC_PRESENT) && (SECURESHIELD_VERSION < 2) - _arc_aux_write(AUX_IRQ_PRIORITY, (1 << AUX_IRQ_PRIORITY_BIT_S)|(INT_PRI_MAX - INT_PRI_MIN)); -#else - _arc_aux_write(AUX_IRQ_PRIORITY, INT_PRI_MAX - INT_PRI_MIN); -#endif - } - _arc_aux_write(AUX_IRQ_CTRL, ictrl.value); - - arc_unlock_restore(status); - - /** ipm should be set after cpu unlock restore to avoid reset of the status32 value */ - arc_int_ipm_set((INT_PRI_MAX - INT_PRI_MIN)); -} - -/** - * \ingroup ARC_HAL_EXCEPTION_CPU - * \brief install a CPU exception entry - * \param[in] excno exception number - * \param[in] entry the entry of exception to install - */ -int32_t exc_entry_install(const uint32_t excno, EXC_ENTRY entry) -{ - uint32_t status; - - EXC_ENTRY *table = (EXC_ENTRY *)_arc_aux_read(AUX_INT_VECT_BASE); - - if (excno < NUM_EXC_ALL && entry != NULL - && table[excno] != entry) { - status = cpu_lock_save(); - /* directly write to mem, as arc gets exception handler from mem not from cache */ - /* FIXME, here maybe icache is dirty, need to be invalidated */ - table[excno] = entry; - - if (_arc_aux_read(AUX_BCR_D_CACHE) > 0x2) { - /* dcache is available */ - dcache_flush_line((uint32_t)&table[excno]); - } - - if (_arc_aux_read(AUX_BCR_D_CACHE) > 0x2) { - /* icache is available */ - icache_invalidate_line((uint32_t)&table[excno]); - } - cpu_unlock_restore(status); - return 0; - } - return -1; -} - -/** - * \ingroup ARC_HAL_EXCEPTION_CPU - * \brief get the installed CPU exception entry - * \param[in] excno exception number - * \return the installed CPU exception entry - */ -EXC_ENTRY exc_entry_get(const uint32_t excno) -{ - if (excno < NUM_EXC_ALL) { - return exc_entry_table[excno]; - } - return NULL; -} - -/** - * \ingroup ARC_HAL_EXCEPTION_CPU - * \brief install an exception handler - * \param[in] excno exception number - * \param[in] handler the handler of exception to install - */ -int32_t exc_handler_install(const uint32_t excno, EXC_HANDLER handler) -{ - if (excno < NUM_EXC_ALL && handler != NULL) { - exc_int_handler_table[excno] = handler; - return 0; - } - - return -1; -} - -/** - * \ingroup ARC_HAL_EXCEPTION_CPU - * \brief get the installed exception handler - * \param[in] excno exception number - * \return the installed exception handler or NULL - */ -EXC_HANDLER exc_handler_get(const uint32_t excno) -{ - if (excno < NUM_EXC_ALL) { - return exc_int_handler_table[excno]; - } - - return NULL; -} - - -#ifndef EMBARC_OVERRIDE_ARC_INTERRUPT_MANAGEMENT -/** - * \brief disable the specific interrupt - * - * \param[in] intno interrupt number - */ -int32_t int_disable(const uint32_t intno) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - arc_int_disable(intno); - return 0; - } - - return -1; -} - -/** - * \brief enable the specific int - * - * \param[in] intno interrupt number - */ -int32_t int_enable(const uint32_t intno) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - arc_int_enable(intno); - return 0; - } - - return -1; -} - -/** - * \brief check whether the specific int is enabled - * - * \param[in] intno interrupt number - * \return 0 disabled, 1 enabled, < 0 error - */ -int32_t int_enabled(const uint32_t intno) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - _arc_aux_write(AUX_IRQ_SELECT, intno); - return _arc_aux_read(AUX_IRQ_ENABLE); - } - - return -1; -} - -/** - * \brief get the interrupt priority mask - * - * \returns interrupt priority mask, negative num - */ -int32_t int_ipm_get(void) -{ - return ((int32_t)arc_int_ipm_get() + INT_PRI_MIN); -} - - -/** - * \brief set the interrupt priority mask - * - * \param[in] intpri interrupt priority - */ -int32_t int_ipm_set(int32_t intpri) -{ - if (intpri >= INT_PRI_MIN && intpri <= INT_PRI_MAX) { - intpri = intpri - INT_PRI_MIN; - arc_int_ipm_set(intpri); - return 0; - } - - return -1; -} - - -/** - * \brief get current interrupt priority mask - * - * \param[in] intno interrupt number - * \return <0 interrupt priority, 0 error - */ -int32_t int_pri_get(const uint32_t intno) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - return (int32_t)arc_int_pri_get(intno) + INT_PRI_MIN; - } - - return 0; -} - - -/** - * \brief set interrupt priority - * - * \param[in] intno interrupt number - * \param[in] intpri interrupt priority - * \return <0 error, 0 ok - */ -int32_t int_pri_set(const uint32_t intno, int32_t intpri) -{ - uint32_t status; - - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - status = cpu_lock_save(); - intpri = intpri - INT_PRI_MIN; - arc_int_pri_set(intno,(uint32_t)intpri); - cpu_unlock_restore(status); - return 0; - } - return -1; -} - -/** - * \brief set interrupt secure or not secure - * This function is valid in secureshield v2 - * \param[in] intno interrupt number - * \param[in] secure, 0 for normal, >0 for secure - * \return <0 error, 0 ok - */ -int32_t int_secure_set(const uint32_t intno, uint32_t secure) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - arc_int_secure_set(intno, secure); - return 0; - } - return -1; - -} - - -/** - * \brief probe the pending status of interrupt - * - * \param[in] intno interrupt number - * - * \returns 1 pending, 0 no pending, -1 error - */ -int32_t int_probe(const uint32_t intno) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - return arc_int_probe(intno); - } - return -1; -} - - -/** - * \brief trigger the interrupt in software - * - * \param[in] intno interrupt number - * \return 0 ok, -1 error - */ -int32_t int_sw_trigger(const uint32_t intno) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - arc_int_sw_trigger(intno); - return 0; - } - return -1; -} - -/** - * \brief config the interrupt level triggered or pulse triggered - * - * \param[in] intno interrupt number - * \param[in] level, 0-level trigger, 1-pulse triggered - * \return 0 ok, -1 error - */ -int32_t int_level_config(const uint32_t intno, const uint32_t level) -{ - if (intno >= NUM_EXC_CPU && intno < NUM_EXC_ALL) { - arc_int_level_config(intno, level); - return 0; - } - return -1; -} - - -/** - * \brief lock cpu, disable interrupts - */ -void cpu_lock(void) -{ - arc_lock(); -} - -/** - * \brief unlock cpu, enable interrupts to happen - */ -void cpu_unlock(void) -{ - arc_unlock(); -} - -/** - * \brief lock cpu and return status - * - * \returns cpu status - */ -uint32_t cpu_lock_save(void) -{ - return arc_lock_save(); -} - -/** - * \brief unlock cpu with the specific status - * - * \param[in] status cpu status saved by cpu_lock_save - */ -void cpu_unlock_restore(const uint32_t status) -{ - arc_unlock_restore(status); -} - -/** - * \ingroup ARC_HAL_EXCEPTION_INTERRUPT - * \brief install an interrupt handler - * \param[in] intno interrupt number - * \param[in] handler interrupt handler to install - */ -int32_t int_handler_install(const uint32_t intno, INT_HANDLER handler) -{ - /*!< \todo parameter check ? */ - if (intno >= NUM_EXC_CPU) { - return exc_handler_install(intno, handler); - } - - return -1; -} - -/** - * \ingroup ARC_HAL_EXCEPTION_INTERRUPT - * \brief get the installed an interrupt handler - * \param[in] intno interrupt number - * \return the installed interrupt handler or NULL - */ -INT_HANDLER int_handler_get(const uint32_t intno) -{ - if (intno >= NUM_EXC_CPU) { - return exc_handler_get(intno); - } - - return NULL; -} -#endif /* EMBARC_OVERRIDE_ARC_INTERRUPT_MANAGEMENT */ diff --git a/bsp/synopsys/embarc/arc/arc_timer.c b/bsp/synopsys/embarc/arc/arc_timer.c deleted file mode 100644 index 3d0c4b4f834ebda43b6c20b9c897844e72f3711a..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/arc/arc_timer.c +++ /dev/null @@ -1,211 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-07-15 - * \author Wayne Ren(Wei.Ren@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup ARC_HAL_MISC_TIMER - * \brief implementation of internal timer related functions - * \todo RTC support should be improved if RTC is enabled - */ -#include "inc/arc/arc_timer.h" -#include "inc/arc/arc.h" -#include "inc/arc/arc_builtin.h" - -/** - * \brief check whether the specific timer present - * \param[in] no timer number - * \retval 1 present - * \retval 0 not present - */ -int32_t arc_timer_present(const uint32_t no) -{ - uint32_t bcr = _arc_aux_read(AUX_BCR_TIMERS); - switch (no) { - case TIMER_0: - bcr = (bcr >> 8) & 1; - break; - case TIMER_1: - bcr = (bcr >> 9) & 1; - break; - case TIMER_RTC: - bcr = (bcr >> 10) & 1; - break; - default: - bcr = 0; - /* illegal argument so return false */ - break; - } - - return (int)bcr; -} - -/** - * \brief start the specific timer - * \param[in] no timer number - * \param[in] mode timer mode - * \param[in] val timer limit value (not for RTC) - * \return 0 success, -1 failure - */ -int32_t arc_timer_start(const uint32_t no, const uint32_t mode, const uint32_t val) -{ - if (arc_timer_present(no) == 0) { - return -1; - } - - switch (no) { - case TIMER_0: - _arc_aux_write(AUX_TIMER0_CTRL, 0); - _arc_aux_write(AUX_TIMER0_LIMIT, val); - _arc_aux_write(AUX_TIMER0_CTRL, mode); - _arc_aux_write(AUX_TIMER0_CNT, 0); - break; - case TIMER_1: - _arc_aux_write(AUX_TIMER1_CTRL, 0); - _arc_aux_write(AUX_TIMER1_LIMIT, val); - _arc_aux_write(AUX_TIMER1_CTRL, mode); - _arc_aux_write(AUX_TIMER1_CNT, 0); - break; - case TIMER_RTC: - _arc_aux_write(AUX_RTC_CTRL, mode); - break; - default: - return -1; - } - - return 0; -} - -/** - * \brief stop and clear the specific timer - * - * \param[in] no timer number - * \return 0 success, -1 failure - */ -int32_t arc_timer_stop(const uint32_t no) -{ - if (arc_timer_present(no) == 0) { - return -1; - } - - switch (no) { - case TIMER_0 : - _arc_aux_write(AUX_TIMER0_CTRL, 0); - _arc_aux_write(AUX_TIMER0_LIMIT,0); - _arc_aux_write(AUX_TIMER0_CNT, 0); - break; - case TIMER_1: - _arc_aux_write(AUX_TIMER1_CTRL, 0); - _arc_aux_write(AUX_TIMER1_LIMIT,0); - _arc_aux_write(AUX_TIMER1_CNT, 0); - break; - case TIMER_RTC: - _arc_aux_write(AUX_RTC_CTRL, TIMER_RTC_CLEAR); - break; - default: - return -1; - } - - return 0; -} - -/** - * \brief get timer current tick - * - * \param[in] no timer number - * \param[out] val, timer value - * \return 0 success, -1 failure - */ -int32_t arc_timer_current(const uint32_t no, void *val) -{ - if (arc_timer_present(no) == 0) { - return -1; - } - - switch (no) { - case TIMER_0 : - *((uint32_t *)val) = _arc_aux_read(AUX_TIMER0_CNT); - break; - case TIMER_1 : - *((uint32_t *)val) = _arc_aux_read(AUX_TIMER1_CNT); - break; - case TIMER_RTC: - *((uint64_t *)val) = _arc_aux_read(AUX_RTC_LOW); - break; - default : - return -1; - } - - return 0; -} - -/** - * \brief clear the interrupt pending bit of timer - * - * \param[in] no timer number - * \return 0 success, -1 failure - */ -int32_t arc_timer_int_clear(const uint32_t no) -{ - uint32_t val; - - if (arc_timer_present(no) == 0) { - return -1; - } - - switch (no) { - case TIMER_0 : - val = _arc_aux_read(AUX_TIMER0_CTRL); - val &= ~TIMER_CTRL_IP; - _arc_aux_write(AUX_TIMER0_CTRL, val); - break; - case TIMER_1 : - val = _arc_aux_read(AUX_TIMER1_CTRL); - val &= ~TIMER_CTRL_IP; - _arc_aux_write(AUX_TIMER1_CTRL, val); - break; - default : - return -1; - } - - return 0; -} - -/** - * \brief init internal timer - */ -void arc_timer_init(void) -{ - arc_timer_stop(TIMER_0); - arc_timer_stop(TIMER_1); - arc_timer_stop(TIMER_RTC); -} diff --git a/bsp/synopsys/embarc/arc/startup/arc_cxx_support.c b/bsp/synopsys/embarc/arc/startup/arc_cxx_support.c deleted file mode 100644 index af842fddc651165a9ec8f87c8585e9426dba668f..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/arc/startup/arc_cxx_support.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) 2012-2014 Wind River Systems, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* ------------------------------------------ - * Copyright (c) 2015, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2016-03-02 - * \author Wayne Ren(wei.ren@synopsys.com) ---------------------------------------------- */ -#include "embARC_BSP_config.h" -#if defined(__GNU__) -/* embARC's GNU C++ support takes reference from Zephyr (cpp_xxx.c) */ - -/** - * @file - Constructor module - * @brief - * The ctors section contains a list of function pointers that execute the - * C++ constructors of static global objects. These must be executed before - * the application's main() routine. - * - * NOTE: Not all compilers put those function pointers into the ctors section; - * some put them into the init_array section instead. - */ - -/* What a constructor function pointer looks like */ - -typedef void (*CtorFuncPtr)(void); - -/* Constructor function pointer list is generated by the linker script. */ - -extern CtorFuncPtr __CTOR_LIST__[]; -extern CtorFuncPtr __CTOR_END__[]; - -/** - * - * @brief Invoke all C++ style global object constructors - * - * This routine is invoked before the execution of the - * application's main(). - */ -void __do_global_ctors_aux(void) -{ - unsigned int nCtors; - - nCtors = (unsigned int)__CTOR_LIST__[0]; - - while (nCtors >= 1) { - __CTOR_LIST__[nCtors--](); - } -} - -typedef void (*DtorFuncPtr)(void); - -extern DtorFuncPtr __DTOR_LIST__[]; -extern DtorFuncPtr __DTOR_END__[]; - -/** - * - * @brief Invoke all C++ style global object destructors - * - * This routine is invoked after the execution of the - * application's main(). - */ -void __do_global_dtors_aux(void) -{ - unsigned int nDtors; - unsigned int i; - - nDtors = (unsigned int)__DTOR_LIST__[0]; - i = 0; - - while (i <= nDtors) { - __DTOR_LIST__[i++](); - } -} - -void *__dso_handle = 0; - -/** - * @brief Register destructor for a global object - * - * @param destructor the global object destructor function - * @param objptr global object pointer - * @param dso Dynamic Shared Object handle for shared libraries - * - * Function does nothing at the moment, assuming the global objects - * do not need to be deleted - * - * @return N/A - */ -int __cxa_atexit(void (*destructor)(void *), void *objptr, void *dso) -{ - return 0; -} - -typedef void (*func_ptr)(void); - -extern func_ptr __init_array_start[0]; -extern func_ptr __init_array_end[0]; - -/** - * @brief Execute initialization routines referenced in .init_array section - * - * @return N/A - */ -void __do_init_array_aux(void) -{ - for (func_ptr *func = __init_array_start; - func < __init_array_end; - func++) { - (*func)(); - } -} - -/** - * @brief Stub for pure virtual functions - * - * This routine is needed for linking C++ code that uses pure virtual - * functions. - * - * @return N/A - */ -void __cxa_pure_virtual(void) -{ - while (1) { - ; - } -} -#endif diff --git a/bsp/synopsys/embarc/arc/startup/arc_startup.S b/bsp/synopsys/embarc/arc/startup/arc_startup.S deleted file mode 100644 index 26a6fdb519e44474cad560feff35e0eed921e6b7..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/arc/startup/arc_startup.S +++ /dev/null @@ -1,262 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-07-15 - * \author Wayne Ren(Wei.Ren@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup ARC_HAL_STARTUP - * \brief assembly part of startup process - */ - -/** - * \addtogroup ARC_HAL_STARTUP - * @{ - */ -/** @cond STARTUP_ASM */ - -#define __ASSEMBLY__ -#include "embARC_BSP_config.h" -#include "inc/arc/arc.h" - - .file "arc_startup.S" - -.weak _f_sdata /* start of small data, defined in link script */ -.weak init_hardware_hook /* app hardware init hook */ -.weak init_software_hook /* app software init hook */ - -.extern board_main -.extern exc_entry_table - -/* initial vector table */ - .section .init_vector, "a" - .long _arc_reset - .section .init_bootstrap, "ax" - .global _arc_reset - .global _start - .align 4 -_start: -_arc_reset: -_arc_reset_stage1: - kflag STATUS32_RESET_VALUE - -/* STAGE 1 */ - -/* necessary hardware should be done first to speed up initialization - 1. system clk - 2. mem controller must be initialized before any access to external - mem. - 3. others -*/ -_arc_cache_init_start: - lr r0, [AUX_BCR_D_CACHE] - cmp r0, 2 - /* invalidate dcache */ - jle _arc_icache_init - mov r0, 1 - sr r0, [AUX_DC_IVDC] - sr r0, [AUX_DC_CTRL] -_arc_icache_init: - lr r0, [AUX_BCR_I_CACHE] - cmp r0, 2 - jle _arc_cache_init_end - /* invalidate icache */ - mov r0, 1 - sr r0, [AUX_IC_IVIC] - nop_s - nop_s - nop_s - sr r0, [AUX_IC_CTRL] - -_arc_cache_init_end: - mov r0, init_hardware_hook - cmp r0, 0 - jlne [r0] - -/* STAGE 2: init necessary registers */ - -_arc_reset_stage2: - mov r0, 0 - -/* interrupt related init */ - sr r0, [AUX_IRQ_ACT] - sr r0, [AUX_IRQ_CTRL] - sr r0, [AUX_IRQ_HINT] - -/* use the new vector table to replace the old one */ -#if defined(ARC_FEATURE_SEC_PRESENT) && (SECURESHIELD_VERSION < 2) - sr exc_entry_table, [AUX_INT_VECT_BASE_S] -#else - sr exc_entry_table, [AUX_INT_VECT_BASE] -#endif - -/* init stack */ -#if ARC_FEATURE_RGF_BANKED_REGS >= 16 && ARC_FEATURE_RGF_BANKED_REGS > 1 && ARC_FEATURE_FIRQ == 1 -#if _STACKSIZE < 512 -#error "not enough stack size for irq and firq" -#endif - -/* switch to register bank1 */ - lr r0, [AUX_STATUS32] - bic r0, r0, 0x70000 - or r0, r0, 0x10000 - kflag r0 -/* set sp, gp, fp in bank1 */ - mov sp, _e_stack - mov gp, _f_sdata - mov fp, 0 -/* come back to bank0 */ - lr r0, [AUX_STATUS32] - bic r0, r0, 0x70000 - kflag r0 - mov sp, _e_stack-256 -#else - mov sp, _e_stack /* init stack pointer */ -#endif - mov gp, _f_sdata /* init small-data base register */ - mov fp, 0 /* init fp register */ - -_arc_reset_stage3: -_s3_copy_text: - mov r0, _f_text - mov r1, _load_addr_text - cmp r0, r1 - -/* if load addr == run addr, no need to copy */ - jeq _s3_copy_rodata - mov r3, _e_text -_s3_copy_text_loop: - ld.ab r2, [r1, 4] - st.ab r2, [r0, 4] - cmp r0, r3 - jlt _s3_copy_text_loop -_s3_copy_rodata: - mov r0, _f_rodata - mov r1, _load_addr_rodata - cmp r0, r1 - -/* if load addr == run addr, no need to copy */ - jeq _s3_copy_data - mov r3, _e_rodata -_s3_copy_rodata_loop: - ld.ab r2, [r1, 4] - st.ab r2, [r0, 4] - cmp r0, r3 - jlt _s3_copy_rodata_loop -_s3_copy_data: - mov r0, _f_data - mov r1, _load_addr_data - cmp r0, r1 - jeq _s3_clear_bss - -/* if load addr == run addr, no need to copy */ - mov r3, _e_data -_s3_copy_data_loop: - ld.ab r2, [r1, 4] - st.ab r2, [r0, 4] - cmp r0, r3 - jlt _s3_copy_data_loop -_s3_clear_bss: - mov r0, _f_bss - mov r1, _e_bss - cmp r0, r1 - jge _arc_reset_call_main - mov r2, 0 -_s3_clear_bss_loop: - st.ab r2, [r0, 4] - cmp r0, r1 - jlt _s3_clear_bss_loop - -/* STAGE 3: go to main */ - -_arc_reset_call_main: - -/* \todo add cpp init here */ - mov r0, init_software_hook - cmp r0, 0 - jlne [r0] -/* board level library init */ -/* early init of interrupt and exception */ - jl exc_int_init -/* init cache */ - jl arc_cache_init -#if defined(__MW__) - jl _init -#elif defined(__GNU__) - jl __do_global_ctors_aux - jl __do_init_array_aux -#endif - jl board_main /* board-level main */ -#if defined(__MW__) - jl _fini -#elif defined(__GNU__) - jl __do_global_dtors_aux -#endif - .global _exit_loop - .global _exit_halt - .align 4 -_exit_halt: -_exit_loop: - flag 0x1 - nop - nop - nop - b _exit_loop - -#if defined(__MW__) - .global _init, _fini - .section ".init",text -_init: - .cfa_bf _init - push %blink - .cfa_push {%blink} - - .section ".init$999999", text, 1, 2, check_text_align=0 - pop %blink - .cfa_pop {%blink} - j [%blink] - .cfa_ef - - .section ".fini", text -_fini: - .cfa_bf _fini - push %blink - .cfa_push {%blink} - - .section ".fini$999999", text, 1, 2, check_text_align=0 - pop %blink - .cfa_pop {%blink} - j [%blink] - .cfa_ef -#endif -/** @endcond */ - -/** }@*/ diff --git a/bsp/synopsys/embarc/device/designware/gpio/dw_gpio.c b/bsp/synopsys/embarc/device/designware/gpio/dw_gpio.c deleted file mode 100644 index ce79414fc6ce7b59558ea382a5a125dee19049ab..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/device/designware/gpio/dw_gpio.c +++ /dev/null @@ -1,481 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-07-22 - * \author Wayne Ren(Wei.Ren@synopsys.com) ---------------------------------------------- */ - -/** - * \defgroup DEVICE_DW_GPIO Designware GPIO Driver - * \ingroup DEVICE_DW - * \brief Designware GPIO Driver Implementation - */ - -/** - * \file - * \brief designware gpio driver - * \ingroup DEVICE_DW_GPIO - * \brief Designware GPIO driver - */ -#include "inc/embARC_toolchain.h" -#include "inc/embARC_error.h" -#include "inc/arc/arc_exception.h" - -#include "device/designware/gpio/dw_gpio.h" - -/** check expressions used in DesignWare GPIO driver implementation */ -#define DW_GPIO_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) - -#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK -/** valid check of uart info object */ -#define VALID_CHK_GPIO_INFO_OBJECT(gpioinfo_obj_ptr) { \ - DW_GPIO_CHECK_EXP((gpioinfo_obj_ptr)!=NULL, E_OBJ); \ - DW_GPIO_CHECK_EXP(((gpioinfo_obj_ptr)->gpio_ctrl)!=NULL, E_OBJ); \ - } -#endif - -/** - * \defgroup DEVICE_DW_GPIO_STATIC DesignWare GPIO Driver Static Functions - * \ingroup DEVICE_DW_GPIO - * \brief Static or inline functions, variables for DesignWare GPIO handle gpio operations, - * only used in this file - * @{ - */ -Inline uint32_t dw_gpio_read_ext(DW_GPIO_PORT_PTR port) -{ - return port->regs->EXT_PORTS[port->no]; -} - -Inline uint32_t dw_gpio_read_dir(DW_GPIO_PORT_PTR port) -{ - return port->regs->SWPORTS[port->no].DDR; -} - -Inline uint32_t dw_gpio_read_dr(DW_GPIO_PORT_PTR port) -{ - return port->regs->SWPORTS[port->no].DR; -} - -Inline uint32_t dw_gpio_read_mthd(DW_GPIO_PORT_PTR port) -{ - return port->regs->INTEN; -} - -Inline void dw_gpio_int_enable(DW_GPIO_PORT_PTR port, uint32_t bit_mask) -{ - port->regs->INTEN |= bit_mask; -} - -Inline void dw_gpio_int_disable(DW_GPIO_PORT_PTR port, uint32_t bit_mask) -{ - port->regs->INTEN &= (~bit_mask); -} - -Inline void dw_gpio_int_mask(DW_GPIO_PORT_PTR port, uint32_t bit_mask) -{ - port->regs->INTMASK |= bit_mask; -} - -Inline void dw_gpio_int_unmask(DW_GPIO_PORT_PTR port, uint32_t bit_mask) -{ - port->regs->INTMASK &= (~bit_mask); -} - -Inline uint32_t dw_gpio_int_read_level(DW_GPIO_PORT_PTR port) -{ - return port->regs->INTTYPE_LEVEL; -} - -Inline uint32_t dw_gpio_int_read_polarity(DW_GPIO_PORT_PTR port) -{ - return port->regs->INT_POLARITY; -} - -Inline uint32_t dw_gpio_int_read_debounce(DW_GPIO_PORT_PTR port) -{ - return port->regs->DEBOUNCE; -} - -Inline uint32_t dw_gpio_int_read_status(DW_GPIO_PORT_PTR port) -{ - return port->regs->INTSTATUS; -} - -Inline void dw_gpio_int_clear(DW_GPIO_PORT_PTR port, uint32_t bit_mask) -{ - port->regs->PORTA_EOI = bit_mask; -} - -static void dw_gpio_int_write_level(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t bit_level) -{ - uint32_t reg_val; - - reg_val = port->regs->INTTYPE_LEVEL; - reg_val &= (~bit_mask); - bit_level &= bit_mask; - reg_val |= bit_level; - - port->regs->INTTYPE_LEVEL = reg_val; -} - -static void dw_gpio_int_write_polarity(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t bit_polarity) -{ - uint32_t reg_val; - - reg_val = port->regs->INT_POLARITY; - - reg_val &= (~bit_mask); - bit_polarity &= bit_mask; - reg_val |= bit_polarity; - - port->regs->INT_POLARITY = reg_val; -} - -static void dw_gpio_int_write_debounce(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t bit_debounce) -{ - uint32_t reg_val; - - reg_val = port->regs->DEBOUNCE; - - reg_val &= (~bit_mask); - bit_debounce &= bit_mask; - reg_val |= bit_debounce; - - port->regs->DEBOUNCE = reg_val; -} - -static void dw_gpio_set_int_cfg(DW_GPIO_PORT_PTR port, DEV_GPIO_INT_CFG *int_cfg) -{ - dw_gpio_int_write_level(port, int_cfg->int_bit_mask, int_cfg->int_bit_type); - dw_gpio_int_write_polarity(port, int_cfg->int_bit_mask, int_cfg->int_bit_polarity); - dw_gpio_int_write_debounce(port, int_cfg->int_bit_mask, int_cfg->int_bit_debounce); -} - -static void dw_gpio_get_int_cfg(DW_GPIO_PORT_PTR port, DEV_GPIO_INT_CFG *int_cfg) -{ - int_cfg->int_bit_type = dw_gpio_int_read_level(port) & int_cfg->int_bit_mask; - int_cfg->int_bit_polarity = dw_gpio_int_read_polarity(port) & int_cfg->int_bit_mask; - int_cfg->int_bit_debounce = dw_gpio_int_read_debounce(port) & int_cfg->int_bit_mask; -} - -static void dw_gpio_write_dr(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t val) -{ - uint32_t temp_reg; - - temp_reg = port->regs->SWPORTS[port->no].DR; - temp_reg &= ~bit_mask; - val &= bit_mask; - temp_reg |= val; - - port->regs->SWPORTS[port->no].DR = temp_reg; -} - -static void dw_gpio_write_dir(DW_GPIO_PORT_PTR port, uint32_t bit_mask, uint32_t val) -{ - uint32_t temp_reg; - - temp_reg = port->regs->SWPORTS[port->no].DDR; - temp_reg &= ~bit_mask; - val &= bit_mask; - temp_reg |= val; - - port->regs->SWPORTS[port->no].DDR = temp_reg; -} - -static uint32_t dw_gpio_read_val(DW_GPIO_PORT_PTR port) -{ - uint32_t val; - - val = dw_gpio_read_ext(port) & (~dw_gpio_read_dir(port)); - val |= dw_gpio_read_dr(port) & dw_gpio_read_dir(port); - - return val; -} - -/** @} end of group DEVICE_DW_GPIO_STATIC */ - -/* interface for DEV_GPIO */ -/** Open designware gpio device with specified io direction configuration */ -int32_t dw_gpio_open(DEV_GPIO *gpio_obj, uint32_t dir) -{ - int32_t ercd = E_OK; - DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info); - - /* START ERROR CHECK */ - VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl); - DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ); - - port_info_ptr->opn_cnt ++; - if (port_info_ptr->opn_cnt > 1) { /* opened before */ - if (dir == port_info_ptr->direction) { /* direction is the same */ - return E_OK; - } else { /* open with different direction */ - return E_OPNED; - } - } - - dw_gpio_write_dir(port, port->valid_bit_mask, dir); - - if (port->no == DW_GPIO_PORT_A) { - dw_gpio_int_clear(port, DW_GPIO_MASK_ALL); - dw_gpio_int_disable(port, DW_GPIO_MASK_ALL); - dw_gpio_int_unmask(port, DW_GPIO_MASK_ALL); - /* install gpio interrupt handler */ - int_handler_install(port->intno, port->int_handler); - int_disable(port->intno); - /** Set int type, int polarity and debounce configuration to default settings of device gpio */ - dw_gpio_set_int_cfg(port, (DEV_GPIO_INT_CFG *)(&gpio_int_cfg_default)); - port_info_ptr->method = dw_gpio_read_mthd(port); - } else { - port_info_ptr->method = DEV_GPIO_BITS_MTHD_DEFAULT; - } - - dw_gpio_write_dr(port, port->valid_bit_mask, 0); - - port_info_ptr->direction = dir; - port_info_ptr->extra = NULL; - -error_exit: - return ercd; -} - -/** Close designware gpio device */ -int32_t dw_gpio_close(DEV_GPIO *gpio_obj) -{ - int32_t ercd = E_OK; - DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info); - - /* START ERROR CHECK */ - VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl); - DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ); - - DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_OK); - - port_info_ptr->opn_cnt --; - if (port_info_ptr->opn_cnt == 0) { - dw_gpio_write_dr(port, port->valid_bit_mask, 0); - dw_gpio_write_dir(port, port->valid_bit_mask, 0); - if (port->no == DW_GPIO_PORT_A) { - dw_gpio_int_clear(port, DW_GPIO_MASK_ALL); - dw_gpio_int_disable(port, DW_GPIO_MASK_ALL); - int_disable(port->intno); - } - - port_info_ptr->direction = 0; - port_info_ptr->method = 0; - port_info_ptr->extra = NULL; - } else { - ercd = E_OPNED; - } - -error_exit: - return ercd; -} - -/** Read designware gpio device value */ -int32_t dw_gpio_read(DEV_GPIO *gpio_obj, uint32_t *val, uint32_t mask) -{ - int32_t ercd = E_OK; - DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info); - - /* START ERROR CHECK */ - VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl); - DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ); - DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED); - - DW_GPIO_CHECK_EXP(val!=NULL, E_PAR); - - //*val = dw_gpio_read_ext(port) & mask; - *val = dw_gpio_read_val(port) & mask; - -error_exit: - return ercd; -} - -/** Write designware gpio device value */ -int32_t dw_gpio_write(DEV_GPIO *gpio_obj, uint32_t val, uint32_t mask) -{ - int32_t ercd = E_OK; - DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info); - - /* START ERROR CHECK */ - VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl); - DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ); - DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED); - - dw_gpio_write_dr(port, mask, val); - -error_exit: - return ercd; -} - -/** Control designware gpio device */ -int32_t dw_gpio_control(DEV_GPIO *gpio_obj, uint32_t ctrl_cmd, void *param) -{ - int32_t ercd = E_OK; - DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info); - - /* START ERROR CHECK */ - VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl); - DW_GPIO_CHECK_EXP(port->no <= DW_GPIO_PORT_D, E_OBJ); - DW_GPIO_CHECK_EXP(port_info_ptr->opn_cnt > 0, E_CLSED); - - uint32_t val32; /** to receive unsigned int value */ - - if (ctrl_cmd == GPIO_CMD_SET_BIT_DIR_INPUT) { - val32 = (uint32_t)param; - dw_gpio_write_dir(port, val32, DW_GPIO_INPUT_ALL); - port_info_ptr->direction = dw_gpio_read_dir(port); - } else if (ctrl_cmd == GPIO_CMD_SET_BIT_DIR_OUTPUT) { - val32 = (uint32_t)param; - dw_gpio_write_dir(port, val32, DW_GPIO_OUTPUT_ALL); - port_info_ptr->direction = dw_gpio_read_dir(port); - } else if (ctrl_cmd == GPIO_CMD_GET_BIT_DIR) { - DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - port_info_ptr->direction = dw_gpio_read_dir(port); - *((int32_t *)param) = port_info_ptr->direction; - } else { - DW_GPIO_CHECK_EXP(port->no == DW_GPIO_PORT_A, E_NOSPT); - /* output pin cannot be used as interrupt */ - DEV_GPIO_INT_CFG *gpio_int_cfg; - DEV_GPIO_BIT_ISR *port_bit_isr; - - switch (ctrl_cmd) { - case GPIO_CMD_SET_BIT_INT_CFG: - DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - gpio_int_cfg = (DEV_GPIO_INT_CFG *)param; - dw_gpio_set_int_cfg(port, gpio_int_cfg); - break; - case GPIO_CMD_GET_BIT_INT_CFG: - DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - gpio_int_cfg = (DEV_GPIO_INT_CFG *)param; - /** read configuration, each bit stands for different configuration */ - dw_gpio_get_int_cfg(port, gpio_int_cfg); - break; - case GPIO_CMD_SET_BIT_ISR: - DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - port_bit_isr = (DEV_GPIO_BIT_ISR *)param; - if (port_bit_isr->int_bit_ofs < port->gpio_bit_isr->int_bit_max_cnt) { - port->gpio_bit_isr->int_bit_handler_ptr[port_bit_isr->int_bit_ofs] = port_bit_isr->int_bit_handler; - } else { - ercd = E_PAR; - } - break; - case GPIO_CMD_GET_BIT_ISR: - DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - port_bit_isr = (DEV_GPIO_BIT_ISR *)param; - if (port_bit_isr->int_bit_ofs < port->gpio_bit_isr->int_bit_max_cnt) { - port_bit_isr->int_bit_handler = port->gpio_bit_isr->int_bit_handler_ptr[port_bit_isr->int_bit_ofs]; - } else { - ercd = E_PAR; - } - break; - case GPIO_CMD_ENA_BIT_INT: - val32 = (uint32_t)param; - dw_gpio_int_enable(port, val32); - port_info_ptr->method = dw_gpio_read_mthd(port); - if (port_info_ptr->method) { - int_enable(port->intno); - } - break; - case GPIO_CMD_DIS_BIT_INT: - val32 = (uint32_t)param; - dw_gpio_int_disable(port, val32); - port_info_ptr->method = dw_gpio_read_mthd(port); - if (port_info_ptr->method == 0) { - int_disable(port->intno); - } - break; - case GPIO_CMD_GET_BIT_MTHD: - DW_GPIO_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - port_info_ptr->method = dw_gpio_read_mthd(port); - *((int32_t *)param) = port_info_ptr->method; - break; - default: - ercd = E_NOSPT; - break; - } - } -error_exit: - return ercd; -} - -/** designware gpio interrupt process */ -int32_t dw_gpio_isr_handler(DEV_GPIO *gpio_obj, void *ptr) -{ - int32_t ercd = E_OK; - DEV_GPIO_INFO_PTR port_info_ptr = &(gpio_obj->gpio_info); - - /* START ERROR CHECK */ - VALID_CHK_GPIO_INFO_OBJECT(port_info_ptr); - /* END OF ERROR CHECK */ - - DW_GPIO_PORT_PTR port = (DW_GPIO_PORT_PTR)(port_info_ptr->gpio_ctrl); - DW_GPIO_CHECK_EXP(port->no == DW_GPIO_PORT_A, E_NOSPT); - - uint32_t i, gpio_bit_isr_state; - uint32_t max_int_bit_count = 0; - - /** read interrupt status */ - gpio_bit_isr_state = dw_gpio_int_read_status(port); - - if (port->gpio_bit_isr) { - max_int_bit_count = (port->gpio_bit_isr->int_bit_max_cnt); - } else { - dw_gpio_int_clear(port, gpio_bit_isr_state); - } - - for (i=0; igpio_bit_isr->int_bit_handler_ptr[i]) { - port->gpio_bit_isr->int_bit_handler_ptr[i](gpio_obj); - } - dw_gpio_int_clear(port, (1< - -#include "inc/embARC_toolchain.h" -#include "inc/embARC_error.h" - -#include "inc/arc/arc_exception.h" - -#include "device/designware/iic/dw_iic_hal.h" -#include "device/designware/iic/dw_iic.h" - -/** check expressions used in DesignWare IIC driver implementation */ -#define DW_IIC_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) - -#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK -/** valid check of iic info object */ -#define VALID_CHK_IIC_INFO_OBJECT(iicinfo_obj_ptr) { \ - DW_IIC_CHECK_EXP((iicinfo_obj_ptr)!=NULL, E_OBJ); \ - DW_IIC_CHECK_EXP(((iicinfo_obj_ptr)->iic_ctrl)!=NULL, E_OBJ); \ - } -#endif - -/** - * \name DesignWare IIC Interrupt Callback Routine Select Marcos - * \brief DesignWare IIC interrupt callback routines select macros definitions - * @{ - */ -#define DW_IIC_RDY_SND (1U) /*!< ready to send callback */ -#define DW_IIC_RDY_RCV (2U) /*!< ready to receive callback */ -/** @} */ - -/** - * \defgroup DEVICE_DW_IIC_STATIC DesignWare IIC Driver Static Functions - * \ingroup DEVICE_DW_IIC - * \brief Static or inline functions, variables for DesignWare IIC handle iic operations, - * only used in this file. - * @{ - */ -/** Disable designware iic device */ -Inline void dw_iic_disable(DW_IIC_REG *iic_reg_ptr) -{ - iic_reg_ptr->IC_ENABLE = DW_IIC_DISABLE; -} -/** Enable designware iic device */ -Inline void dw_iic_enable(DW_IIC_REG *iic_reg_ptr) -{ - iic_reg_ptr->IC_ENABLE = DW_IIC_ENABLE; -} - -/** Clear all designware iic interrupt */ -Inline void dw_iic_clear_interrupt_all(DW_IIC_REG *iic_reg_ptr) -{ - (void)iic_reg_ptr->IC_CLR_INTR; -} - -/** test whether iic is ready to write, 1 ready, 0 not ready */ -Inline int32_t dw_iic_putready(DW_IIC_REG *iic_reg_ptr) -{ - return ((iic_reg_ptr->IC_STATUS & IC_STATUS_TFNF) != 0); -} -/** test whether iic is ready to receive, 1 ready, 0 not ready */ -Inline int32_t dw_iic_getready(DW_IIC_REG *iic_reg_ptr) -{ - return ((iic_reg_ptr->IC_STATUS & IC_STATUS_RFNE) != 0); -} -/** Write data into IIC TX FIFO with STOP/RESTART Condition, and R/W bit */ -Inline void dw_iic_putdata(DW_IIC_REG *iic_reg_ptr, uint32_t data) -{ - iic_reg_ptr->IC_DATA_CMD = data; -} - -/** Read Data from IIC RX FIFO */ -Inline uint32_t dw_iic_getdata(DW_IIC_REG *iic_reg_ptr) -{ - return (iic_reg_ptr->IC_DATA_CMD) & 0xff; -} - -/** Enable designware iic bit interrupt with mask */ -Inline void dw_iic_unmask_interrupt(DW_IIC_REG *iic_reg_ptr, uint32_t mask) -{ - iic_reg_ptr->IC_INTR_MASK |= mask; -} - -/** Disable designware iic bit interrupt with mask */ -Inline void dw_iic_mask_interrupt(DW_IIC_REG *iic_reg_ptr, uint32_t mask) -{ - iic_reg_ptr->IC_INTR_MASK &= ~mask; -} - -/** Get TX FIFO Length */ -Inline uint32_t dw_iic_get_txfifo_len(DW_IIC_REG *iic_reg_ptr) -{ - uint32_t txfifolen; - - txfifolen = ((iic_reg_ptr->IC_COMP_PARAM_1 >> 16) & 0xff) + 1; - - return txfifolen; -} - -/** Get RX FIFO Length */ -Inline uint32_t dw_iic_get_rxfifo_len(DW_IIC_REG *iic_reg_ptr) -{ - uint32_t rxfifolen; - - rxfifolen = ((iic_reg_ptr->IC_COMP_PARAM_1 >> 8) & 0xff) + 1; - - return rxfifolen; -} - -/** Set designware iic transfer in 7bit of 10bit addressing mode as a master */ -Inline void dw_iic_set_mstaddr_mode(DW_IIC_REG *iic_reg_ptr, uint32_t mode) -{ -#if DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT - if (mode == IIC_7BIT_ADDRESS) { - iic_reg_ptr->IC_TAR &= ~IC_10BITADDR_MASTER; - } else { - iic_reg_ptr->IC_TAR |= IC_10BITADDR_MASTER; - } -#else - dw_iic_disable(iic_reg_ptr); - if (mode == IIC_7BIT_ADDRESS) { - iic_reg_ptr->IC_CON &= ~MST_10_BIT_ADDR_MODE; - } else { - iic_reg_ptr->IC_CON |= MST_10_BIT_ADDR_MODE; - } - dw_iic_enable(iic_reg_ptr); -#endif -} - -/** Set designware iic transfer in 7bit of 10bit addressing mode as a slave */ -Inline void dw_iic_set_slvaddr_mode(DW_IIC_REG *iic_reg_ptr, uint32_t mode) -{ - dw_iic_disable(iic_reg_ptr); - if (mode == IIC_7BIT_ADDRESS) { - iic_reg_ptr->IC_CON &= ~SLV_10_BIT_ADDR_MODE; - } else { - iic_reg_ptr->IC_CON |= SLV_10_BIT_ADDR_MODE; - } - dw_iic_enable(iic_reg_ptr); -} - -/** Set designware iic transfer target address for addressing any iic slave device as a master */ -Inline void dw_iic_set_taraddr(DW_IIC_REG *iic_reg_ptr, uint32_t address) -{ -#if DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT - iic_reg_ptr->IC_TAR &= ~(IC_TAR_10BIT_ADDR_MASK); - iic_reg_ptr->IC_TAR |= (IC_TAR_10BIT_ADDR_MASK & address); -#else - dw_iic_disable(iic_reg_ptr); - iic_reg_ptr->IC_TAR &= ~(IC_TAR_10BIT_ADDR_MASK); - iic_reg_ptr->IC_TAR |= (IC_TAR_10BIT_ADDR_MASK & address); - dw_iic_enable(iic_reg_ptr); -#endif -} - -/** Set designware iic slave address as a slave */ -Inline void dw_iic_set_slvaddr(DW_IIC_REG *iic_reg_ptr, uint32_t address) -{ - dw_iic_disable(iic_reg_ptr); - iic_reg_ptr->IC_SAR &= ~(IC_SAR_10BIT_ADDR_MASK); - iic_reg_ptr->IC_SAR |= (IC_SAR_10BIT_ADDR_MASK & address); - dw_iic_enable(iic_reg_ptr); -} - -/** Select speed mode, and return proper speed mode configuration */ -Inline uint32_t dw_iic_select_speedmode(uint32_t speedmode) -{ - uint32_t speedcfg; - - if (speedmode == IIC_SPEED_STANDARD) { - speedcfg = IC_CON_SPEED_STANDARD; - } else if (speedmode == IIC_SPEED_FAST) { - speedcfg = IC_CON_SPEED_FAST; - } else if (speedmode == IIC_SPEED_FASTPLUS) { - speedcfg = IC_CON_SPEED_FAST; - } else if (speedmode == IIC_SPEED_HIGH) { - speedcfg = IC_CON_SPEED_HIGH; - } else { - speedcfg = IC_CON_SPEED_HIGH; - } - return speedcfg; -} -/** Set designware iic speed mode */ -Inline void dw_iic_set_speedmode(DW_IIC_REG *iic_reg_ptr, uint32_t speedmode) -{ - uint32_t ic_con_val; - - dw_iic_disable(iic_reg_ptr); - ic_con_val = iic_reg_ptr->IC_CON & (~IC_CON_SPEED_MASK); - ic_con_val |= dw_iic_select_speedmode(speedmode); - iic_reg_ptr->IC_CON = ic_con_val; - dw_iic_enable(iic_reg_ptr); -} - -/** Set designware working mode as master or slave */ -Inline void dw_iic_set_working_mode(DW_IIC_REG *iic_reg_ptr, uint32_t mode) -{ - uint32_t ic_con_val; - dw_iic_disable(iic_reg_ptr); - ic_con_val = iic_reg_ptr->IC_CON & (~IC_CON_MST_SLV_MODE_MASK); - if (mode == DEV_MASTER_MODE) { - ic_con_val |= IC_CON_ENA_MASTER_MODE; - } else { - ic_con_val |= IC_CON_ENA_SLAVE_MODE; - } - dw_iic_enable(iic_reg_ptr); -} - -/** Set IC_CLK frequency by configuration the *CNT registers for different speed modes */ -Inline void dw_iic_set_scl_cnt(DW_IIC_REG *iic_reg_ptr, DW_IIC_SCL_CNT *scl_cnt) -{ - dw_iic_disable(iic_reg_ptr); - iic_reg_ptr->IC_SS_SCL_HCNT = scl_cnt->ss_scl_hcnt; - iic_reg_ptr->IC_SS_SCL_LCNT = scl_cnt->ss_scl_lcnt; - iic_reg_ptr->IC_FS_SCL_HCNT = scl_cnt->fs_scl_hcnt; - iic_reg_ptr->IC_FS_SCL_LCNT = scl_cnt->fs_scl_lcnt; - iic_reg_ptr->IC_HS_SCL_HCNT = scl_cnt->hs_scl_hcnt; - iic_reg_ptr->IC_HS_SCL_LCNT = scl_cnt->hs_scl_lcnt; - dw_iic_enable(iic_reg_ptr); -} - -/** Set spike suppression configuration */ -Inline void dw_iic_set_spike_len(DW_IIC_REG *iic_reg_ptr, DW_IIC_SPKLEN *spklen) -{ - dw_iic_disable(iic_reg_ptr); - iic_reg_ptr->IC_FS_SPKLEN = spklen->fs_spklen; - iic_reg_ptr->IC_HS_SPKLEN = spklen->hs_spklen; - dw_iic_enable(iic_reg_ptr); -} - -Inline void dw_iic_flush_tx(DW_IIC_REG *iic_reg_ptr) -{ - (void)iic_reg_ptr->IC_CLR_INTR; -} - -Inline void dw_iic_flush_rx(DW_IIC_REG *iic_reg_ptr) -{ -} - -static uint32_t dw_iic_get_slv_state(DW_IIC_REG *iic_reg_ptr) -{ - uint32_t status; - uint32_t slv_state = IIC_SLAVE_STATE_FREE; - - status = iic_reg_ptr->IC_RAW_INTR_STAT; - if (status & IC_INTR_STAT_GEN_CALL) { - /* General Call address is received and it is acknowledged */ - slv_state |= IIC_SLAVE_STATE_GC_REQ; - } - if (status & IC_INTR_STAT_RX_FULL) { - /* master is attempting to write data to this slave */ - slv_state |= IIC_SLAVE_STATE_WR_REQ; - } - if (status & IC_INTR_STAT_RD_REQ) { - /* master is attempting to read data from this slave */ - slv_state |= IIC_SLAVE_STATE_RD_REQ; - } - if (status & IC_INTR_STAT_RX_DONE) { - /* master does not acknowledge a transmitted byte, and transmission is done */ - slv_state |= IIC_SLAVE_STATE_RD_DONE; - status = iic_reg_ptr->IC_CLR_RX_DONE; - } - if (status & IC_INTR_STAT_START_DET) { - /* a START or RESTART condition has occurred */ - slv_state |= IIC_SLAVE_STATE_START; - status = iic_reg_ptr->IC_CLR_START_DET; /* Clear it when read */ - } - if (status & IC_INTR_STAT_STOP_DET) { - /* a STOP condition has occurred */ - slv_state |= IIC_SLAVE_STATE_STOP; - status = iic_reg_ptr->IC_CLR_STOP_DET; /* Clear it when read */ - } - if (status & (IC_INTR_STAT_TX_ABRT|IC_INTR_STAT_TX_OVER\ - |IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)) { - /* error case */ - slv_state |= IIC_SLAVE_STATE_ERROR; - status = iic_reg_ptr->IC_CLR_TX_ABRT; /* Clear it when read */ - status = iic_reg_ptr->IC_CLR_TX_OVER; - status = iic_reg_ptr->IC_CLR_RX_OVER; - status = iic_reg_ptr->IC_CLR_RX_UNDER; - } - - return slv_state; -} - -/** Init Designware IIC Device into Master mode */ -static void dw_iic_master_init(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t speed_mode, uint32_t addr_mode, uint32_t tar_addr) -{ - uint32_t ic_con_val = 0; - DW_IIC_REG *iic_reg_ptr = iic_ctrl_ptr->dw_iic_regs; - - dw_iic_disable(iic_reg_ptr); - - /* disable all iic interrupt */ - iic_reg_ptr->IC_INTR_MASK = IC_INT_DISABLE_ALL; - - /* Set to 7bit addressing and update target address */ - iic_reg_ptr->IC_TAR = (tar_addr & IC_TAR_10BIT_ADDR_MASK) | IC_TAR_SPECIAL | IC_TAR_GC_OR_START; - /* master mode, restart enabled */ - ic_con_val = dw_iic_select_speedmode(speed_mode) | IC_CON_ENA_MASTER_MODE | IC_CON_RESTART_EN; - -#if DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT - if (addr_mode == IIC_10BIT_ADDRESS) { - iic_reg_ptr->IC_TAR |= MST_10_BIT_ADDR_MODE; - } -#else - if (addr_mode == IIC_10BIT_ADDRESS) { - ic_con_val |= MST_10_BIT_ADDR_MODE; - } -#endif - /* Set final IC_CON value */ - iic_reg_ptr->IC_CON = ic_con_val; - /* FIFO threshold settings */ - iic_reg_ptr->IC_TX_TL = IIC_TX_THRESHOLD; - iic_reg_ptr->IC_RX_TL = IIC_RX_THRESHOLD; - /* Master code settings */ - iic_reg_ptr->IC_HS_MADDR = iic_ctrl_ptr->iic_master_code; - dw_iic_enable(iic_reg_ptr); - - /* Clock Settings */ - dw_iic_set_scl_cnt(iic_reg_ptr, &(iic_ctrl_ptr->iic_scl_cnt)); - dw_iic_set_spike_len(iic_reg_ptr, &(iic_ctrl_ptr->iic_spklen)); -} - -/** Init Designware IIC Device into Slave mode */ -static void dw_iic_slave_init(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t addr_mode, uint32_t slv_addr) -{ - uint32_t ic_con_val = 0; - DW_IIC_REG *iic_reg_ptr = iic_ctrl_ptr->dw_iic_regs; - - dw_iic_disable(iic_reg_ptr); - - /* disable all iic interrupt */ - iic_reg_ptr->IC_INTR_MASK = IC_INT_DISABLE_ALL; - - /* Set slave device address as a slave */ - iic_reg_ptr->IC_SAR = slv_addr & IC_SAR_10BIT_ADDR_MASK; - /* slave mode, 7 bit slave address */ - ic_con_val = IC_CON_ENA_SLAVE_MODE; - /* If addr mode select to be 10 bit address mode */ - if (addr_mode == IIC_10BIT_ADDRESS) { - ic_con_val |= SLV_10_BIT_ADDR_MODE; - } - - /* Set final IC_CON value */ - iic_reg_ptr->IC_CON = ic_con_val; - /* FIFO threshold settings */ - iic_reg_ptr->IC_TX_TL = IIC_TX_THRESHOLD; - iic_reg_ptr->IC_RX_TL = IIC_RX_THRESHOLD; - - dw_iic_enable(iic_reg_ptr); -} - -/** Check error for IIC master device */ -static int32_t dw_iic_mst_chkerr(DW_IIC_CTRL *iic_ctrl_ptr) -{ - uint32_t status; - int32_t ercd = IIC_ERR_NONE; - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - status = iic_reg_ptr->IC_RAW_INTR_STAT; - if (status & IC_INTR_STAT_TX_ABRT) { - status = iic_reg_ptr->IC_TX_ABRT_SOURCE; - if (status & IIC_MST_ABRT_LOST_BUS) { - ercd = IIC_ERR_LOST_BUS; - } else if (status & IIC_MST_ABRT_ADDR_NOACK) { - ercd = IIC_ERR_ADDR_NOACK; - } else if (status & IIC_MST_ABRT_DATA_NOACK) { - ercd = IIC_ERR_DATA_NOACK; - } else { - ercd = IIC_ERR_UNDEF; - } - status = iic_reg_ptr->IC_CLR_TX_ABRT; - } else { - if (status & IC_INTR_STAT_TX_OVER) { - iic_ctrl_ptr->iic_tx_over ++; - status = iic_reg_ptr->IC_CLR_TX_OVER; - } - if (status & (IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)) { - iic_ctrl_ptr->iic_rx_over ++; - status = iic_reg_ptr->IC_CLR_RX_OVER; - status = iic_reg_ptr->IC_CLR_RX_UNDER; - } - } - return ercd; -} - -/** Check error for IIC slave device */ -static int32_t dw_iic_slv_chkerr(DW_IIC_CTRL *iic_ctrl_ptr) -{ - uint32_t status; - int32_t ercd = IIC_ERR_NONE; - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - status = iic_reg_ptr->IC_RAW_INTR_STAT; - if (status & IC_INTR_STAT_TX_ABRT) { - status = iic_reg_ptr->IC_TX_ABRT_SOURCE; - if (status & IIC_SLV_ABRT_LOST_BUS) { - ercd = IIC_ERR_LOST_BUS; - } else if (status & IC_TX_ABRT_SLVFLUSH_TXFIFO) { - /* Flush tx fifo */ - status = iic_reg_ptr->IC_TX_ABRT_SOURCE; - } else { - ercd = IIC_ERR_UNDEF; - } - status = iic_reg_ptr->IC_CLR_TX_ABRT; - } else { - if (status & IC_INTR_STAT_TX_OVER) { - iic_ctrl_ptr->iic_tx_over ++; - status = iic_reg_ptr->IC_CLR_TX_OVER; - } - if (status & (IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)) { - iic_ctrl_ptr->iic_rx_over ++; - status = iic_reg_ptr->IC_CLR_RX_OVER; - status = iic_reg_ptr->IC_CLR_RX_UNDER; - } - } - return ercd; -} - -/** enable designware iic */ -static void dw_iic_enable_device(DEV_IIC_INFO *iic_info_ptr) -{ - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - if ((iic_info_ptr->status & DEV_ENABLED) == 0) { - dw_iic_enable(iic_reg_ptr); - iic_info_ptr->status |= DEV_ENABLED; - } -} - -/** disable designware iic */ -static void dw_iic_disable_device(DEV_IIC_INFO *iic_info_ptr) -{ - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - uint32_t i; - - for (i=0; iIC_ENABLE_STATUS & IC_ENABLE_STATUS_IC_EN) == 0) { - break; - } - } - iic_info_ptr->status &= ~DEV_ENABLED; -} - -static void dw_iic_reset_device(DEV_IIC_INFO *iic_info_ptr) -{ - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - dw_iic_disable_device(iic_info_ptr); - dw_iic_clear_interrupt_all(iic_reg_ptr); - iic_info_ptr->next_cond = IIC_MODE_STOP; - iic_info_ptr->cur_state = IIC_FREE; - iic_info_ptr->err_state = IIC_ERR_NONE; - iic_ctrl_ptr->iic_tx_over = 0; - iic_ctrl_ptr->iic_rx_over = 0; - dw_iic_enable_device(iic_info_ptr); -} - -/** Disable iic master interrupt for transmit or receive */ -static void dw_iic_mst_dis_cbr(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t cbrtn) -{ - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - switch (cbrtn) { - case DW_IIC_RDY_SND: - dw_iic_mask_interrupt(iic_reg_ptr, IC_INT_MST_TX_ENABLE); - iic_ctrl_ptr->int_status &= ~DW_IIC_TXINT_ENABLE; - break; - case DW_IIC_RDY_RCV: - dw_iic_mask_interrupt(iic_reg_ptr, IC_INT_MST_RX_ENABLE); - iic_ctrl_ptr->int_status &= ~DW_IIC_RXINT_ENABLE; - break; - default: - break; - } -} - -/** Disable iic slave interrupt for transmit or receive */ -static void dw_iic_slv_dis_cbr(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t cbrtn) -{ - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - switch (cbrtn) { - case DW_IIC_RDY_SND: - dw_iic_mask_interrupt(iic_reg_ptr, IC_INT_SLV_TX_ENABLE); - iic_ctrl_ptr->int_status &= ~DW_IIC_TXINT_ENABLE; - break; - case DW_IIC_RDY_RCV: - dw_iic_mask_interrupt(iic_reg_ptr, IC_INT_SLV_RX_ENABLE); - iic_ctrl_ptr->int_status &= ~DW_IIC_RXINT_ENABLE; - break; - default: - break; - } -} - -/** Enable iic master interrupt for transmit or receive */ -static void dw_iic_mst_ena_cbr(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t cbrtn) -{ - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - switch (cbrtn) { - case DW_IIC_RDY_SND: - iic_ctrl_ptr->int_status |= DW_IIC_TXINT_ENABLE; - dw_iic_unmask_interrupt(iic_reg_ptr, IC_INT_MST_TX_ENABLE); - break; - case DW_IIC_RDY_RCV: - iic_ctrl_ptr->int_status |= DW_IIC_RXINT_ENABLE; - dw_iic_unmask_interrupt(iic_reg_ptr, IC_INT_MST_RX_ENABLE); - break; - default: - break; - } -} - -/** Enable iic slave interrupt for transmit or receive */ -static void dw_iic_slv_ena_cbr(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t cbrtn) -{ - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - switch (cbrtn) { - case DW_IIC_RDY_SND: - iic_ctrl_ptr->int_status |= DW_IIC_TXINT_ENABLE; - dw_iic_unmask_interrupt(iic_reg_ptr, IC_INT_SLV_TX_ENABLE); - break; - case DW_IIC_RDY_RCV: - iic_ctrl_ptr->int_status |= DW_IIC_RXINT_ENABLE; - dw_iic_unmask_interrupt(iic_reg_ptr, IC_INT_SLV_RX_ENABLE); - break; - default: - break; - } -} - -/** - * \brief disable designware iic send or receive interrupt - * \param[in] DEV_IIC_INFO *iic_info_ptr - * \param[in] cbrtn control code of callback routine of send or receive - */ -static void dw_iic_dis_cbr(DEV_IIC_INFO *iic_info_ptr, uint32_t cbrtn) -{ - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - - if (iic_info_ptr->mode == DEV_MASTER_MODE) { - dw_iic_mst_dis_cbr(iic_ctrl_ptr, cbrtn); - } else { - dw_iic_slv_dis_cbr(iic_ctrl_ptr, cbrtn); - } - - if (iic_ctrl_ptr->int_status & DW_IIC_GINT_ENABLE) { - if ((iic_ctrl_ptr->int_status & (DW_IIC_RXINT_ENABLE|DW_IIC_TXINT_ENABLE)) == 0) { - int_disable(iic_ctrl_ptr->intno); - iic_ctrl_ptr->int_status &= ~DW_IIC_GINT_ENABLE; - } - } -} - -/** - * \brief enable DesignWare IIC send or receive interrupt - * \param[in] DEV_IIC_INFO *iic_info_ptr - * \param[in] cbrtn control code of callback routine of send or receive - */ -static void dw_iic_ena_cbr(DEV_IIC_INFO *iic_info_ptr, uint32_t cbrtn) -{ - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - - if (iic_info_ptr->mode == DEV_MASTER_MODE) { - dw_iic_mst_ena_cbr(iic_ctrl_ptr, cbrtn); - } else { - dw_iic_slv_ena_cbr(iic_ctrl_ptr, cbrtn); - } - - if ((iic_ctrl_ptr->int_status & DW_IIC_GINT_ENABLE) == 0) { - if (iic_ctrl_ptr->int_status & (DW_IIC_RXINT_ENABLE|DW_IIC_TXINT_ENABLE)) { - iic_ctrl_ptr->int_status |= DW_IIC_GINT_ENABLE; - int_enable(iic_ctrl_ptr->intno); - } - } -} - -/** - * \brief enable designware iic interrupt - * \param iic_info_ptr iic information structure pointer - */ -static void dw_iic_enable_interrupt(DEV_IIC_INFO *iic_info_ptr) -{ - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - - int_handler_install(iic_ctrl_ptr->intno, iic_ctrl_ptr->dw_iic_int_handler); - iic_ctrl_ptr->int_status |= DW_IIC_GINT_ENABLE; - int_enable(iic_ctrl_ptr->intno); /** enable iic interrupt */ -} -/** - * \brief disable designware iic interrupt - * \param iic_info_ptr iic information structure pointer - */ -static void dw_iic_disable_interrupt(DEV_IIC_INFO *iic_info_ptr) -{ - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - - /** disable iic send&receive interrupt after disable iic interrupt */ - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND); - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV); - /* disable iic interrupt */ - int_disable(iic_ctrl_ptr->intno); - iic_ctrl_ptr->int_status &= ~(DW_IIC_GINT_ENABLE|DW_IIC_TXINT_ENABLE|DW_IIC_RXINT_ENABLE); -} - -/** abort current interrupt transmit transfer */ -static void dw_iic_abort_tx(DEV_IIC *iic_obj) -{ - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - - if (iic_ctrl_ptr->int_status & DW_IIC_TXINT_ENABLE) { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND); - iic_info_ptr->status |= DEV_IN_TX_ABRT; - if (iic_info_ptr->iic_cbs.tx_cb != NULL) { - iic_info_ptr->iic_cbs.tx_cb(iic_obj); - } - iic_info_ptr->status &= ~(DEV_IN_TX_ABRT); - } -} - -/** abort current interrupt receive transfer */ -static void dw_iic_abort_rx(DEV_IIC *iic_obj) -{ - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - - if (iic_ctrl_ptr->int_status & DW_IIC_RXINT_ENABLE) { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV); - iic_info_ptr->status |= DEV_IN_RX_ABRT; - if (iic_info_ptr->iic_cbs.rx_cb != NULL) { - iic_info_ptr->iic_cbs.rx_cb(iic_obj); - } - iic_info_ptr->status &= ~(DEV_IN_RX_ABRT); - } -} - -/** Get available transmit fifo count */ -static int32_t dw_iic_get_txavail(DW_IIC_CTRL *iic_ctrl_ptr) -{ - int32_t tx_avail = 0; - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - if (iic_ctrl_ptr->tx_fifo_len <= 1) { - if (dw_iic_putready(iic_reg_ptr) == 1) { - tx_avail = 1; - } else { - tx_avail = 0; - } - } else { - tx_avail = iic_ctrl_ptr->tx_fifo_len - iic_reg_ptr->IC_TXFLR; - } - return tx_avail; -} - -/** Get available receive fifo count */ -static int32_t dw_iic_get_rxavail(DW_IIC_CTRL *iic_ctrl_ptr) -{ - int32_t rx_avail = 0; - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - if (iic_ctrl_ptr->rx_fifo_len <= 1) { - if (dw_iic_getready(iic_reg_ptr) == 1) { - rx_avail = 1; - } else { - rx_avail = 0; - } - } else { - rx_avail = iic_reg_ptr->IC_RXFLR; - } - return rx_avail; -} - -/** - * IIC Master device transmit 1 data, - * next_cond can be \ref IC_DATA_CMD_STOP, - * \ref IC_DATA_CMD_RESTART and ref IC_DATA_CMD_NONE - */ -static int32_t dw_iic_mst_write_data(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t data, uint32_t next_cond) -{ - uint32_t i = 0; - int32_t ercd = IIC_ERR_NONE; - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - while (dw_iic_putready(iic_reg_ptr) == 0) { - if (i++ > iic_ctrl_ptr->retry_cnt) return IIC_ERR_TIMEOUT; - ercd = dw_iic_mst_chkerr(iic_ctrl_ptr); - if (ercd != IIC_ERR_NONE) return ercd; - } - dw_iic_putdata(iic_reg_ptr, data|IC_DATA_CMD_WRITE_REQ|next_cond); - - return ercd; -} - -/** IIC Slave device transmit 1 data */ -static int32_t dw_iic_slv_write_data(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t data) -{ - uint32_t i = 0; - int32_t ercd = IIC_ERR_NONE; - uint32_t slv_state, temp; - uint32_t ready2send = 0; - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - for (i = 0; i < iic_ctrl_ptr->retry_cnt; i++) { - ercd = dw_iic_slv_chkerr(iic_ctrl_ptr); - if (ercd != IIC_ERR_NONE) return ercd; - slv_state = iic_reg_ptr->IC_RAW_INTR_STAT; - if (slv_state & IC_INTR_STAT_RD_REQ) { - if (dw_iic_putready(iic_reg_ptr)) { - temp = iic_reg_ptr->IC_CLR_RD_REQ; - ready2send = 1; - break; - } - } else if (slv_state & IC_INTR_STAT_RX_DONE) { /* Put RX Done before STOP */ - temp = iic_reg_ptr->IC_CLR_RX_DONE; - return IIC_ERR_MSTSTOP; - } else if (slv_state & IC_INTR_STAT_STOP_DET) { - temp = iic_reg_ptr->IC_CLR_STOP_DET; - return IIC_ERR_MSTSTOP; - } - } - if (ready2send) { - dw_iic_putdata(iic_reg_ptr, data|IC_DATA_CMD_WRITE_REQ); - } else { - ercd = IIC_ERR_TIMEOUT; - } - - return ercd; -} - -/** - * IIC Master device receive 1 data, - * next_cond can be \ref IC_DATA_CMD_STOP, - * \ref IC_DATA_CMD_RESTART and ref IC_DATA_CMD_NONE - */ -static int32_t dw_iic_mst_read_data(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t *data, uint32_t next_cond) -{ - uint32_t i = 0; - int32_t ercd = IIC_ERR_NONE; - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - /* Issue a read request */ - while (dw_iic_putready(iic_reg_ptr) == 0) { - if (i++ > iic_ctrl_ptr->retry_cnt) return IIC_ERR_TIMEOUT; - ercd = dw_iic_mst_chkerr(iic_ctrl_ptr); - if (ercd != IIC_ERR_NONE) return ercd; - } - dw_iic_putdata(iic_reg_ptr, next_cond|IC_DATA_CMD_READ_REQ); - /* Wait to read data */ - i = 0; - while (dw_iic_getready(iic_reg_ptr) == 0) { - if (i++ > iic_ctrl_ptr->retry_cnt) return IIC_ERR_TIMEOUT; - ercd = dw_iic_mst_chkerr(iic_ctrl_ptr); - if (ercd != IIC_ERR_NONE) return ercd; - } - *data = dw_iic_getdata(iic_reg_ptr); - return ercd; -} - -/** IIC Slave device receive 1 data */ -static int32_t dw_iic_slv_read_data(DW_IIC_CTRL *iic_ctrl_ptr, uint32_t *data) -{ - uint32_t i = 0; - int32_t ercd = IIC_ERR_NONE; - uint32_t slv_state, temp; - uint32_t ready2read = 0; - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - for (i = 0; i < iic_ctrl_ptr->retry_cnt; i++) { - ercd = dw_iic_slv_chkerr(iic_ctrl_ptr); - if (ercd != IIC_ERR_NONE) return ercd; - slv_state = iic_reg_ptr->IC_RAW_INTR_STAT; - if (slv_state & IC_INTR_STAT_START_DET) { - temp = iic_reg_ptr->IC_CLR_START_DET; - } - if (slv_state & IC_INTR_STAT_RX_FULL) { - if (dw_iic_getready(iic_reg_ptr)) { - ready2read = 1; - break; - } - } else if (slv_state & IC_INTR_STAT_STOP_DET) { - temp = iic_reg_ptr->IC_CLR_STOP_DET; - return IIC_ERR_MSTSTOP; - } - } - if (ready2read) { - *data = dw_iic_getdata(iic_reg_ptr); - } else { - ercd = IIC_ERR_TIMEOUT; - } - - return ercd; -} - -/** IIC Master transmit called in interrupt */ -static void dw_iic_mst_int_write(DEV_IIC *iic_obj) -{ - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl); - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG_PTR)(iic_ctrl_ptr->dw_iic_regs); - uint32_t iic_int_status; /** iic interrupt status */ - uint32_t last_cond, xmit_data, xmit_end = 0; - DEV_BUFFER *buf_ptr; - uint8_t *p_charbuf; - - if (iic_info_ptr->next_cond == IIC_MODE_STOP) { - last_cond = IC_DATA_CMD_STOP; - } else { - last_cond = IC_DATA_CMD_RESTART; - } - iic_int_status = (iic_reg_ptr->IC_INTR_STAT); - buf_ptr = &(iic_info_ptr->tx_buf); - p_charbuf = (uint8_t *)buf_ptr->buf; - if (p_charbuf) { - if (iic_int_status & IC_INTR_STAT_TX_EMPTY) { - xmit_end = 0; - while (dw_iic_putready(iic_reg_ptr)) { - xmit_data = (uint32_t)(p_charbuf[buf_ptr->ofs])|IC_DATA_CMD_WRITE_REQ; - if (buf_ptr->ofs == (buf_ptr->len-1)) { - xmit_end = 1; - xmit_data |= last_cond; - } else { - xmit_data |= IC_DATA_CMD_NONE; - } - buf_ptr->ofs ++; - dw_iic_putdata(iic_reg_ptr, xmit_data); - if (xmit_end) { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND); - iic_info_ptr->cur_state = IIC_FREE; - if (iic_info_ptr->iic_cbs.tx_cb) { - iic_info_ptr->iic_cbs.tx_cb(iic_obj); - } - /* clear the send buffer pointer */ - memset(buf_ptr, 0, sizeof(DEV_BUFFER)); - break; - } - } - } - if (iic_int_status & IC_INTR_STAT_TX_OVER) { - iic_ctrl_ptr->iic_tx_over ++; - } - if (iic_int_status & IC_INTR_STAT_TX_ABRT) { - iic_info_ptr->err_state = dw_iic_mst_chkerr(iic_ctrl_ptr); - if (iic_info_ptr->err_state != IIC_ERR_NONE) { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND); - iic_info_ptr->cur_state = IIC_FREE; - if (iic_info_ptr->iic_cbs.err_cb) { - iic_info_ptr->iic_cbs.err_cb(iic_obj); - } - /* clear the send buffer pointer */ - memset(buf_ptr, 0, sizeof(DEV_BUFFER)); - } - } - } else { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND); - iic_info_ptr->cur_state = IIC_FREE; - } - /* Clear Interrupt */ - iic_int_status = iic_reg_ptr->IC_CLR_INTR; -} - -/** IIC Master receive called in interrupt */ -static void dw_iic_mst_int_read(DEV_IIC *iic_obj) -{ - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl); - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG_PTR)(iic_ctrl_ptr->dw_iic_regs); - uint32_t iic_int_status; /** iic interrupt status */ - uint32_t last_cond, xmit_data; - DEV_BUFFER *buf_ptr; - DW_IIC_BUFFER *dw_iic_rxbuf_ptr; - uint8_t *p_charbuf; - - if (iic_info_ptr->next_cond == IIC_MODE_STOP) { - last_cond = IC_DATA_CMD_STOP; - } else { - last_cond = IC_DATA_CMD_RESTART; - } - iic_int_status = (iic_reg_ptr->IC_INTR_STAT); - buf_ptr = &(iic_info_ptr->rx_buf); - p_charbuf = (uint8_t *)buf_ptr->buf; - if (p_charbuf) { - dw_iic_rxbuf_ptr = &(iic_ctrl_ptr->dw_iic_rxbuf); - if (iic_int_status & IC_INTR_STAT_TX_EMPTY) { - while (dw_iic_putready(iic_reg_ptr)) { - if (dw_iic_rxbuf_ptr->ofs >= dw_iic_rxbuf_ptr->len) { - dw_iic_mask_interrupt(iic_reg_ptr, IC_INTR_STAT_TX_EMPTY); - break; - } - xmit_data = IC_DATA_CMD_READ_REQ; - if (dw_iic_rxbuf_ptr->ofs == (dw_iic_rxbuf_ptr->len-1)) { - xmit_data |= last_cond; - } else { - xmit_data |= IC_DATA_CMD_NONE; - } - dw_iic_rxbuf_ptr->ofs ++; - dw_iic_putdata(iic_reg_ptr, xmit_data); - } - } - if (iic_int_status & IC_INTR_STAT_RX_FULL) { - while (dw_iic_getready(iic_reg_ptr)) { - p_charbuf[buf_ptr->ofs] = dw_iic_getdata(iic_reg_ptr); - buf_ptr->ofs ++; - if (buf_ptr->ofs >= buf_ptr->len) { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV); - iic_info_ptr->cur_state = IIC_FREE; - if (iic_info_ptr->iic_cbs.rx_cb) { - iic_info_ptr->iic_cbs.rx_cb(iic_obj); - } - /* clear the send buffer pointer */ - memset(buf_ptr, 0, sizeof(DEV_BUFFER)); - dw_iic_rxbuf_ptr->ofs = 0; - dw_iic_rxbuf_ptr->len = 0; - break; - } - } - } - if (iic_int_status & (IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)) { - iic_ctrl_ptr->iic_rx_over ++; - } - if (iic_int_status & IC_INTR_STAT_TX_ABRT) { - iic_info_ptr->err_state = dw_iic_mst_chkerr(iic_ctrl_ptr); - if (iic_info_ptr->err_state != IIC_ERR_NONE) { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV); - iic_info_ptr->cur_state = IIC_FREE; - if (iic_info_ptr->iic_cbs.err_cb) { - iic_info_ptr->iic_cbs.err_cb(iic_obj); - } - /* clear the send buffer pointer */ - memset(buf_ptr, 0, sizeof(DEV_BUFFER)); - dw_iic_rxbuf_ptr->ofs = 0; - dw_iic_rxbuf_ptr->len = 0; - } - } - } else { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV); - iic_info_ptr->cur_state = IIC_FREE; - } - /* Clear Interrupt */ - iic_int_status = iic_reg_ptr->IC_CLR_INTR; -} - -/** IIC Slave transmit called in interrupt */ -static void dw_iic_slv_int_process(DEV_IIC *iic_obj) -{ - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl); - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG_PTR)(iic_ctrl_ptr->dw_iic_regs); - uint32_t iic_int_status; /** iic interrupt status */ - - iic_int_status = (iic_reg_ptr->IC_INTR_STAT); - if (iic_int_status & IC_INTR_STAT_RD_REQ) { /* Read request from master */ - if (iic_info_ptr->iic_cbs.tx_cb) { - iic_info_ptr->iic_cbs.tx_cb(iic_obj); - } else { /* When tx callback function is not set disable this tx int for slave */ - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND); - } - } - if (iic_int_status & IC_INTR_STAT_RX_FULL) { /* Write request from master */ - if (iic_info_ptr->iic_cbs.rx_cb) { - iic_info_ptr->iic_cbs.rx_cb(iic_obj); - } else { /* When rx callback function is not set disable this rx int for slave */ - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV); - } - } - if (iic_int_status & IC_INTR_STAT_TX_OVER) { - iic_ctrl_ptr->iic_tx_over ++; - } - if (iic_int_status & (IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)) { - iic_ctrl_ptr->iic_rx_over ++; - } - if (iic_int_status & IC_INTR_STAT_TX_ABRT) { - iic_info_ptr->err_state = dw_iic_slv_chkerr(iic_ctrl_ptr); - if (iic_info_ptr->err_state != IIC_ERR_NONE) { - if (iic_info_ptr->iic_cbs.err_cb) { - iic_info_ptr->iic_cbs.err_cb(iic_obj); - } - } - } - /* Clear Interrupt */ - iic_int_status = iic_reg_ptr->IC_CLR_INTR; -} - -/** @} end of group DEVICE_DW_IIC_STATIC */ - -/** - * \defgroup DEVICE_DW_IIC_IMPLEMENT DesignWare IIC Driver Function API Implement - * \ingroup DEVICE_DW_IIC - * \brief implement device hal iic api with DesignWare IIC - * @{ - */ - -/** - * \brief open a designware iic device - * \param[in] iic_obj iic device object pointer - * \param[in] mode iic working mode (master or slave) - * \param[in] param When mode is \ref DEV_MASTER_MODE, param stands for \ref dev_iic_info::speed_mode "speed mode", - * when mode is \ref DEV_SLAVE_MODE, param stands for \ref dev_iic_info::slv_addr "slave device 7bit address" - * \retval E_OK Open successfully without any issues - * \retval E_OPNED If device was opened before with different parameters, - * then just increase the \ref dev_iic_info::opn_cnt "opn_cnt" and return \ref E_OPNED - * \retval E_OBJ Device object is not valid - * \retval E_SYS Device is opened for different mode before, if you want to open it with different mode, you need to fully close it first. - * \retval E_PAR Parameter is not valid - * \retval E_NOSPT Open settings are not supported - */ -int32_t dw_iic_open (DEV_IIC *iic_obj, uint32_t mode, uint32_t param) -{ - int32_t ercd = E_OK; - uint32_t support_modes; - uint32_t param2check; - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - - /* START ERROR CHECK */ - VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr); - DW_IIC_CHECK_EXP((mode==DEV_MASTER_MODE)||(mode==DEV_SLAVE_MODE), E_PAR); - if (mode == DEV_MASTER_MODE) { - DW_IIC_CHECK_EXP((param>=IIC_SPEED_STANDARD) && (param<=IIC_SPEED_ULTRA), E_PAR); - } - /* END OF ERROR CHECK */ - - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - - /* Check supported modes, master or slave */ - support_modes = iic_ctrl_ptr->support_modes; - DW_IIC_CHECK_EXP( (((support_modes)&DW_IIC_MASTER_SUPPORTED)&&(mode == DEV_MASTER_MODE)) || \ - (((support_modes)&DW_IIC_SLAVE_SUPPORTED)&&(mode == DEV_SLAVE_MODE)), E_NOSPT); - - /** Check opened before use case */ - if (iic_info_ptr->opn_cnt > 0) { - if (mode != iic_info_ptr->mode) { - /* current working mode is different from passing mode */ - return E_SYS; - } - if (mode == DEV_MASTER_MODE) { /* param is speed_mode when as master */ - param2check = iic_info_ptr->speed_mode; - } else { /* param is slv_addr when as slave */ - param2check = iic_info_ptr->slv_addr; - } - iic_info_ptr->opn_cnt ++; - if (param != param2check) { /* open with different speed mode */ - return E_OPNED; - } else { - return E_OK; - } - } - /* auto increase open count */ - iic_info_ptr->opn_cnt ++; - - iic_info_ptr->mode = mode; - if (iic_info_ptr->addr_mode == IIC_7BIT_ADDRESS) { - iic_info_ptr->tar_addr &= IIC_7BIT_ADDRESS_MASK; - iic_info_ptr->slv_addr &= IIC_7BIT_ADDRESS_MASK; - } else { - iic_info_ptr->addr_mode = IIC_10BIT_ADDRESS; - iic_info_ptr->tar_addr &= IIC_10BIT_ADDRESS_MASK; - iic_info_ptr->slv_addr &= IIC_10BIT_ADDRESS_MASK; - } - -/* Do FIFO Length get before init */ -#if DW_IIC_CALC_FIFO_LEN_ENABLE - iic_ctrl_ptr->tx_fifo_len = dw_iic_get_txfifo_len(iic_ctrl_ptr->dw_iic_regs); - iic_ctrl_ptr->rx_fifo_len = dw_iic_get_rxfifo_len(iic_ctrl_ptr->dw_iic_regs); -#endif - - /* Disable device before init it */ - dw_iic_disable_device(iic_info_ptr); - - if (mode == DEV_MASTER_MODE) { - iic_info_ptr->speed_mode = param; - dw_iic_master_init(iic_ctrl_ptr, param, iic_info_ptr->addr_mode, iic_info_ptr->tar_addr); - } else { - iic_info_ptr->slv_addr = param; - dw_iic_slave_init(iic_ctrl_ptr, iic_info_ptr->addr_mode, param); - } - iic_info_ptr->status = DEV_ENABLED; - iic_info_ptr->cur_state = IIC_FREE; - iic_info_ptr->err_state = IIC_ERR_NONE; - iic_info_ptr->next_cond = IIC_MODE_STOP; - iic_info_ptr->extra = NULL; - - iic_ctrl_ptr->iic_tx_over = 0; - iic_ctrl_ptr->iic_rx_over = 0; - iic_ctrl_ptr->int_status = 0; - memset(&(iic_ctrl_ptr->dw_iic_rxbuf), 0, sizeof(DW_IIC_BUFFER)); - iic_ctrl_ptr->dw_iic_rxbuf.buf = &(iic_info_ptr->rx_buf); - /** install iic interrupt into system */ - dw_iic_disable_interrupt(iic_info_ptr); - int_handler_install(iic_ctrl_ptr->intno, iic_ctrl_ptr->dw_iic_int_handler); - memset(&(iic_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(iic_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(iic_info_ptr->iic_cbs), 0, sizeof(DEV_IIC_CBS)); - -error_exit: - return ercd; -} - -/** - * \brief Close a DesignWare IIC device - * \param[in] iic_obj iic device object pointer - * \retval E_OK Close successfully without any issues(including secenary that device is already closed) - * \retval E_OPNED Device is still opened, the device \ref dev_iic_info::opn_cnt "opn_cnt" decreased by 1 - * \retval E_OBJ Device object is not valid - */ -int32_t dw_iic_close (DEV_IIC *iic_obj) -{ - int32_t ercd = E_OK; - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - - /* START ERROR CHECK */ - VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr); - DW_IIC_CHECK_EXP(iic_info_ptr->opn_cnt > 0, E_OK); - /* END OF ERROR CHECK */ - - iic_info_ptr->opn_cnt --; - if (iic_info_ptr->opn_cnt == 0) { - dw_iic_disable_interrupt(iic_info_ptr); - dw_iic_abort_tx(iic_obj); - dw_iic_abort_rx(iic_obj); - memset(&(iic_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(iic_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(iic_info_ptr->iic_cbs), 0, sizeof(DEV_IIC_CBS)); - dw_iic_disable_device(iic_info_ptr); - iic_info_ptr->status = DEV_DISABLED; - iic_info_ptr->next_cond = IIC_MODE_STOP; - iic_info_ptr->extra = NULL; - } else { - ercd = E_OPNED; - } - -error_exit: - return ercd; -} - -/** - * \brief Control iic by ctrl command - * \param[in] iic_obj iic device object pointer - * \param[in] ctrl_cmd \ref DEVICE_HAL_IIC_CTRLCMD "control command", to change or get some thing related to iic - * \param[in,out] param parameters that maybe argument of the command, - * or return values of the command, must not be NULL - * \retval E_OK Control device successfully - * \retval E_CLSED Device is not opened - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid for current control command - * \retval E_SYS Control device failed, due to hardware issues, such as device is disabled - * \retval E_CTX Control device failed, due to different reasons like in transfer state - * \retval E_NOSPT Control command is not supported or not valid - */ -int32_t dw_iic_control (DEV_IIC *iic_obj, uint32_t ctrl_cmd, void *param) -{ - int32_t ercd = E_OK; - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - - /* START ERROR CHECK */ - VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr); - DW_IIC_CHECK_EXP(iic_info_ptr->opn_cnt > 0, E_CLSED); - /* END OF ERROR CHECK */ - - uint32_t val32; /** to receive unsigned int value */ - DEV_BUFFER *devbuf; - - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL *)(iic_info_ptr->iic_ctrl); - DW_IIC_REG *iic_reg_ptr = (DW_IIC_REG *)(iic_ctrl_ptr->dw_iic_regs); - - /* check whether current device is disabled */ - if ((iic_info_ptr->status & DEV_ENABLED) == 0) { - /** When device is disabled, - * only IIC_CMD_ENA_DEV, IIC_CMD_DIS_DEV, IIC_CMD_GET_STATUS, IIC_CMD_RESET - * are available, other commands will return E_SYS - */ - if ((ctrl_cmd != IIC_CMD_ENA_DEV) && \ - (ctrl_cmd != IIC_CMD_DIS_DEV) && \ - (ctrl_cmd != IIC_CMD_GET_STATUS) && \ - (ctrl_cmd != IIC_CMD_RESET) ) { - return E_SYS; - } - } - - switch (ctrl_cmd) { - /* Commmon commands for both master and slave mode */ - case IIC_CMD_GET_STATUS: - DW_IIC_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = iic_info_ptr->status; - break; - case IIC_CMD_ENA_DEV: - dw_iic_enable_device(iic_info_ptr); - break; - case IIC_CMD_DIS_DEV: - dw_iic_disable_device(iic_info_ptr); - break; - case IIC_CMD_RESET: - dw_iic_reset_device(iic_info_ptr); - break; - case IIC_CMD_FLUSH_TX: - dw_iic_flush_tx(iic_reg_ptr); - break; - case IIC_CMD_FLUSH_RX: - dw_iic_flush_rx(iic_reg_ptr); - break; - case IIC_CMD_SET_ADDR_MODE: - val32 = (uint32_t)param; - DW_IIC_CHECK_EXP((val32==IIC_7BIT_ADDRESS) || (val32==IIC_10BIT_ADDRESS), E_PAR); - if (iic_info_ptr->mode == DEV_MASTER_MODE) { - dw_iic_set_mstaddr_mode(iic_reg_ptr, val32); - } else { - dw_iic_set_slvaddr_mode(iic_reg_ptr, val32); - } - iic_info_ptr->addr_mode = val32; - break; - case IIC_CMD_GET_RXAVAIL: - DW_IIC_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = dw_iic_get_rxavail(iic_ctrl_ptr); - break; - case IIC_CMD_GET_TXAVAIL: - DW_IIC_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = dw_iic_get_txavail(iic_ctrl_ptr); - break; - case IIC_CMD_SET_TXCB: - DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - iic_info_ptr->iic_cbs.tx_cb = param; - break; - case IIC_CMD_SET_RXCB: - DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - iic_info_ptr->iic_cbs.rx_cb = param; - break; - case IIC_CMD_SET_ERRCB: - DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - iic_info_ptr->iic_cbs.err_cb = param; - break; - case IIC_CMD_ABORT_TX: - dw_iic_abort_tx(iic_obj); - if ((iic_info_ptr->mode == DEV_MASTER_MODE) \ - && (iic_info_ptr->cur_state == IIC_IN_TX)) { - iic_info_ptr->cur_state = IIC_FREE; - } - break; - case IIC_CMD_ABORT_RX: - dw_iic_abort_rx(iic_obj); - if ((iic_info_ptr->mode == DEV_MASTER_MODE) \ - && (iic_info_ptr->cur_state == IIC_IN_RX)) { - iic_info_ptr->cur_state = IIC_FREE; - } - break; - case IIC_CMD_SET_TXINT: - if (iic_info_ptr->mode == DEV_MASTER_MODE) { - DW_IIC_CHECK_EXP(iic_info_ptr->cur_state != IIC_IN_RX, E_CTX); - } - val32 = (uint32_t)param; - if (val32 == 0) { - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_SND); - iic_info_ptr->cur_state = IIC_FREE; - } else { - iic_info_ptr->cur_state = IIC_IN_TX; - dw_iic_ena_cbr(iic_info_ptr, DW_IIC_RDY_SND); - } - break; - case IIC_CMD_SET_RXINT: - if (iic_info_ptr->mode == DEV_MASTER_MODE) { - DW_IIC_CHECK_EXP(iic_info_ptr->cur_state != IIC_IN_TX, E_CTX); - } - val32 = (uint32_t)param; - if (val32 == 0) { - iic_info_ptr->cur_state = IIC_FREE; - dw_iic_dis_cbr(iic_info_ptr, DW_IIC_RDY_RCV); - } else { - iic_info_ptr->cur_state = IIC_IN_RX; - dw_iic_ena_cbr(iic_info_ptr, DW_IIC_RDY_RCV); - } - break; - case IIC_CMD_SET_TXINT_BUF: - if (iic_info_ptr->mode == DEV_MASTER_MODE) { - DW_IIC_CHECK_EXP(iic_info_ptr->cur_state != IIC_IN_TX, E_CTX); - } - DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - if (param != NULL) { - devbuf = (DEV_BUFFER *)param; - iic_info_ptr->tx_buf = *devbuf; - iic_info_ptr->tx_buf.ofs = 0; - } else { - iic_info_ptr->tx_buf.buf = NULL; - iic_info_ptr->tx_buf.len = 0; - iic_info_ptr->tx_buf.ofs = 0; - } - break; - case IIC_CMD_SET_RXINT_BUF: - if (iic_info_ptr->mode == DEV_MASTER_MODE) { - DW_IIC_CHECK_EXP(iic_info_ptr->cur_state != IIC_IN_RX, E_CTX); - } - DW_IIC_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - if (param != NULL) { - devbuf = (DEV_BUFFER *)param; - iic_info_ptr->rx_buf = *devbuf; - iic_info_ptr->rx_buf.ofs = 0; - iic_ctrl_ptr->dw_iic_rxbuf.ofs = 0; - iic_ctrl_ptr->dw_iic_rxbuf.len = devbuf->len; - } else { - iic_info_ptr->rx_buf.buf = NULL; - iic_info_ptr->rx_buf.len = 0; - iic_info_ptr->rx_buf.ofs = 0; - iic_ctrl_ptr->dw_iic_rxbuf.ofs = 0; - iic_ctrl_ptr->dw_iic_rxbuf.len = 0; - } - break; - - /* Master mode only commands */ - case IIC_CMD_MST_SET_SPEED_MODE: - DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT); - val32 = (uint32_t)param; - DW_IIC_CHECK_EXP((val32>=IIC_SPEED_STANDARD) && (val32<=IIC_SPEED_ULTRA), E_PAR); - dw_iic_set_speedmode(iic_reg_ptr, val32); - iic_info_ptr->speed_mode = val32; - break; - case IIC_CMD_MST_SET_TAR_ADDR: - DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT); - if (iic_info_ptr->addr_mode == IIC_7BIT_ADDRESS) { - val32 = ((uint32_t)param) & IIC_7BIT_ADDRESS_MASK; - } else { - val32 = ((uint32_t)param) & IIC_10BIT_ADDRESS_MASK; - } - if (val32 != iic_info_ptr->tar_addr) { - dw_iic_set_taraddr(iic_reg_ptr, val32); - iic_info_ptr->tar_addr = val32; - } - break; - case IIC_CMD_MST_SET_NEXT_COND: - DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT); - val32 = (uint32_t)param; - DW_IIC_CHECK_EXP((val32==IIC_MODE_STOP) || (val32==IIC_MODE_RESTART), E_PAR); - iic_info_ptr->next_cond = (uint32_t)param; - break; - - /* Slave mode only commands */ - case IIC_CMD_SLV_SET_SLV_ADDR: - DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_SLAVE_MODE, E_NOSPT); - if (iic_info_ptr->addr_mode == IIC_7BIT_ADDRESS) { - val32 = ((uint32_t)param) & IIC_7BIT_ADDRESS_MASK; - } else { - val32 = ((uint32_t)param) & IIC_10BIT_ADDRESS_MASK; - } - dw_iic_set_slvaddr(iic_reg_ptr, val32); - iic_info_ptr->slv_addr = val32; - break; - case IIC_CMD_SLV_GET_SLV_STATE: - DW_IIC_CHECK_EXP(iic_info_ptr->mode == DEV_SLAVE_MODE, E_NOSPT); - DW_IIC_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((uint32_t *)param) = dw_iic_get_slv_state(iic_reg_ptr); - break; - - default: - ercd = E_NOSPT; - break; - } - -error_exit: - return ercd; -} - -/** - * \brief poll transmit data through DesignWare IIC as master or slave - * \param[in] iic_obj iic device object pointer - * \param[in] data data that need to send (data must be uint8_t type) - * \param[in] len data length need to send - * \retval >0 Byte count that was successfully sent for poll method, - * it might can't send that much due to \ref \ref dev_iic_info::err_state "different error state". - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid - * \retval E_CTX Device is still in transfer state - * \retval E_SYS Can't write data to hardware due to hardware issues, such as device is disabled - */ -int32_t dw_iic_write (DEV_IIC *iic_obj, const void *data, uint32_t len) -{ - int32_t ercd = E_OK; - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - - /* START ERROR CHECK */ - VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr); - DW_IIC_CHECK_EXP(iic_info_ptr->opn_cnt > 0, E_CLSED); - DW_IIC_CHECK_EXP(iic_info_ptr->status & DEV_ENABLED, E_SYS); - DW_IIC_CHECK_EXP(data!=NULL, E_PAR); - DW_IIC_CHECK_EXP(len>0, E_PAR); - /* END OF ERROR CHECK */ - - int32_t i = 0; - uint32_t last_cond = 0; /* Last data for transmit, STOP or RESTART */ - int32_t error_state = IIC_ERR_NONE; - const uint8_t *p_charbuf = (const uint8_t *)data; - - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl); - - if (iic_info_ptr->mode == DEV_MASTER_MODE) { /* Master mode transmit data */ - if (iic_info_ptr->next_cond == IIC_MODE_STOP) { - last_cond = IC_DATA_CMD_STOP; - } else { - last_cond = IC_DATA_CMD_RESTART; - } - - /* Try to transmit 0 -> (len-1) data */ - len = len - 1; /* Last data write differently */ - while (i < len) { - error_state = dw_iic_mst_write_data(iic_ctrl_ptr, (uint32_t)(p_charbuf[i]), IC_DATA_CMD_NONE); - if (error_state != IIC_ERR_NONE) { - break; - } - i ++; - } - /* Try to transmit the last data with STOP or RESTART condition */ - if (error_state == IIC_ERR_NONE) { - error_state = dw_iic_mst_write_data(iic_ctrl_ptr, (uint32_t)(p_charbuf[len]), last_cond); - if (error_state == IIC_ERR_NONE) { - i = i + 1; /* Add last data into send count */ - } - } - } else { /* Slave mode transmit data */ - while (i < len) { - error_state = dw_iic_slv_write_data(iic_ctrl_ptr, (uint32_t)(p_charbuf[i])); - if (error_state != IIC_ERR_NONE) { - break; - } - i ++; - } - } - iic_info_ptr->err_state = error_state; - ercd = i; - -error_exit: - return ercd; -} - -/** - * \brief read data through DesignWare IIC - * \param[in] iic_obj iic device object pointer - * \param[out] data data that need to read (data must be uint8_t type) - * \param[in] len data count need to read - * \retval >0 Byte count that was successfully received for poll method, - * it might can't send that much due to \ref \ref dev_iic_info::err_state "different error state". - * \retval E_OBJ Device object is not valid or not exists - * \retval E_CTX Device is still in transfer state - * \retval E_PAR Parameter is not valid - * \retval E_SYS Can't receive data from hardware due to hardware issues, such as device is disabled - */ -int32_t dw_iic_read (DEV_IIC *iic_obj, void *data, uint32_t len) -{ - int32_t ercd = E_OK; - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - - /* START ERROR CHECK */ - VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr); - DW_IIC_CHECK_EXP(iic_info_ptr->opn_cnt > 0, E_CLSED); - DW_IIC_CHECK_EXP(iic_info_ptr->status & DEV_ENABLED, E_SYS); - DW_IIC_CHECK_EXP(data!=NULL, E_PAR); - DW_IIC_CHECK_EXP(len>0, E_PAR); - /* END OF ERROR CHECK */ - - int32_t i = 0; - uint32_t last_cond = 0; /* Last data for receive, STOP or RESTART */ - uint32_t val32 = 0; - int32_t error_state = IIC_ERR_NONE; - uint8_t *p_charbuf = (uint8_t *)data; - - DW_IIC_CTRL *iic_ctrl_ptr = (DW_IIC_CTRL_PTR)(iic_info_ptr->iic_ctrl); - - if (iic_info_ptr->mode == DEV_MASTER_MODE) { /* Master mode receive data */ - if (iic_info_ptr->next_cond == IIC_MODE_STOP) { - last_cond = IC_DATA_CMD_STOP; - } else { - last_cond = IC_DATA_CMD_RESTART; - } - - /* Try to receive 0 -> (len-1) data */ - len = len - 1; /* Last data write differently */ - while (i < len) { - error_state = dw_iic_mst_read_data(iic_ctrl_ptr, &val32, IC_DATA_CMD_NONE); - if (error_state != IIC_ERR_NONE) { - break; - } else { - p_charbuf[i] = (uint8_t)val32; - } - i ++; - } - /* Try to receive the last data with STOP or RESTART condition */ - if (error_state == IIC_ERR_NONE) { - error_state = dw_iic_mst_read_data(iic_ctrl_ptr, &val32, last_cond); - if (error_state == IIC_ERR_NONE) { - p_charbuf[len] = (uint8_t)val32; - i = i + 1; /* Add last data into send count */ - } - } - } else { /* Slave mode receive data */ - while (i < len) { - error_state = dw_iic_slv_read_data(iic_ctrl_ptr, &val32); - if (error_state != IIC_ERR_NONE) { - break; - } else { - p_charbuf[i] = (uint8_t)val32; - } - i ++; - } - } - iic_info_ptr->err_state = error_state; - ercd = i; - -error_exit: - return ercd; -} - -/** - * \brief DesignWare IIC interrupt processing routine - * \param[in] iic_info_ptr DEV_IIC *iic_obj - * \param[in] ptr extra information - */ -void dw_iic_isr(DEV_IIC *iic_obj, void *ptr) -{ - int32_t ercd = E_OK; - DEV_IIC_INFO *iic_info_ptr = &(iic_obj->iic_info); - - /* START ERROR CHECK */ - VALID_CHK_IIC_INFO_OBJECT(iic_info_ptr); - /* END OF ERROR CHECK */ - - if (iic_info_ptr->mode == DEV_MASTER_MODE) { - if (iic_info_ptr->cur_state == IIC_IN_TX) { - dw_iic_mst_int_write(iic_obj); - } else { - dw_iic_mst_int_read(iic_obj); - } - } else { - dw_iic_slv_int_process(iic_obj); - } - -error_exit: - return; -} -/** @} end of group DEVICE_DW_IIC_IMPLEMENT */ diff --git a/bsp/synopsys/embarc/device/designware/iic/dw_iic.h b/bsp/synopsys/embarc/device/designware/iic/dw_iic.h deleted file mode 100644 index 55c551a67e59f4c9d5031e9b680452ce7f4aae1e..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/device/designware/iic/dw_iic.h +++ /dev/null @@ -1,242 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2017.03 - * \date 2014-06-30 - * \author Huaqi Fang(Huaqi.Fang@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \brief designware iic driver header file - * \ingroup DEVICE_DW_IIC - */ - -#ifndef _DW_IIC_H_ -#define _DW_IIC_H_ - -#include "device/device_hal/inc/dev_iic.h" - -#include "inc/arc/arc_exception.h" - - -/** - * If this header file is included, - * will indicate that this designware iic device - * is used - */ -#define DEVICE_USE_DESIGNWARE_IIC - -/** - * \defgroup DEVICE_DW_IIC_INFO DesignWare IIC Related Information - * \ingroup DEVICE_DW_IIC - * \brief Defines some macros of DesignWare IIC need. - * \details macros like, iic number - * @{ - */ -#define DW_IIC_MASTER_SUPPORTED (0x1) /*!< Support Designware IIC Master Mode */ -#define DW_IIC_SLAVE_SUPPORTED (0x2) /*!< Support Designware IIC Slave Mode */ -/*!< Support Designware IIC Both Master and Slave Mode */ -#define DW_IIC_BOTH_SUPPORTED (DW_IIC_MASTER_SUPPORTED|DW_IIC_SLAVE_SUPPORTED) -/** @} */ - -/** - * \defgroup DEVICE_DW_IIC_REGSTRUCT DesignWare IIC Register Structure - * \ingroup DEVICE_DW_IIC - * \brief contains definitions of DesignWare IIC register structure. - * \details detailed description of DesignWare IIC register information - * @{ - */ -/** - * \brief DesignWare IIC register structure - * \details Detailed struct description of DesignWare IIC - * block register information, implementation of dev_iic_info::iic_regs - */ -typedef volatile struct dw_iic_reg { - uint32_t IC_CON; /*!< (0x00) : IIC control */ - uint32_t IC_TAR; /*!< (0x04) : IIC target address */ - uint32_t IC_SAR; /*!< (0x08) : IIC slave address */ - uint32_t IC_HS_MADDR; /*!< (0x0c) : IIC HS Master Mode Code address */ - uint32_t IC_DATA_CMD; /*!< (0x10) : IIC Rx/Tx Data Buffer and Command */ - uint32_t IC_SS_SCL_HCNT; /*!< (0x14) : Standard Speed IIC clock SCL High Count */ - uint32_t IC_SS_SCL_LCNT; /*!< (0x18) : Standard Speed IIC clock SCL Low Count */ - uint32_t IC_FS_SCL_HCNT; /*!< (0x1c) : Fast Speed IIC clock SCL Low Count */ - uint32_t IC_FS_SCL_LCNT; /*!< (0x20) : Fast Speed IIC clock SCL Low Count */ - uint32_t IC_HS_SCL_HCNT; /*!< (0x24) : High Speed IIC clock SCL Low Count */ - uint32_t IC_HS_SCL_LCNT; /*!< (0x28) : High Speed IIC clock SCL Low Count */ - uint32_t IC_INTR_STAT; /*!< (0x2c) : IIC Interrupt Status */ - uint32_t IC_INTR_MASK; /*!< (0x30) : IIC Interrupt Mask */ - uint32_t IC_RAW_INTR_STAT; /*!< (0x34) : IIC Raw Interrupt Status */ - uint32_t IC_RX_TL; /*!< (0x38) : IIC Receive FIFO Threshold */ - uint32_t IC_TX_TL; /*!< (0x3c) : IIC Transmit FIFO Threshold */ - uint32_t IC_CLR_INTR; /*!< (0x40) : Clear combined and Individual Interrupts */ - uint32_t IC_CLR_RX_UNDER; /*!< (0x44) : Clear RX_UNDER Interrupt */ - uint32_t IC_CLR_RX_OVER; /*!< (0x48) : Clear RX_OVER Interrupt */ - uint32_t IC_CLR_TX_OVER; /*!< (0x4c) : Clear TX_OVER Interrupt */ - uint32_t IC_CLR_RD_REQ; /*!< (0x50) : Clear RQ_REQ Interrupt */ - uint32_t IC_CLR_TX_ABRT; /*!< (0x54) : Clear TX_ABRT Interrupt */ - uint32_t IC_CLR_RX_DONE; /*!< (0x58) : Clear RX_DONE Interrupt */ - uint32_t IC_CLR_ACTIVITY; /*!< (0x5c) : Clear ACTIVITY Interrupt */ - uint32_t IC_CLR_STOP_DET; /*!< (0x60) : Clear STOP_DET Interrupt */ - uint32_t IC_CLR_START_DET; /*!< (0x64) : Clear START_DET Interrupt */ - uint32_t IC_CLR_GEN_CALL; /*!< (0x68) : Clear GEN_CALL Interrupt */ - uint32_t IC_ENABLE; /*!< (0x6c) : IIC Enable */ - uint32_t IC_STATUS; /*!< (0x70) : IIC Status */ - uint32_t IC_TXFLR; /*!< (0x74) : Transmit FIFO Level Register */ - uint32_t IC_RXFLR; /*!< (0x78) : Receive FIFO Level Register */ - uint32_t IC_SDA_HOLD; /*!< (0x7c) : SDA Hold Time Length Reg */ - uint32_t IC_TX_ABRT_SOURCE; /*!< (0x80) : IIC Transmit Abort Status Reg */ - uint32_t IC_SLV_DATA_NACK_ONLY; /*!< (0x84) : Generate SLV_DATA_NACK Register */ - uint32_t IC_DMA_CR; /*!< (0x88) : DMA Control Register */ - uint32_t IC_DMA_TDLR; /*!< (0x8c) : DMA Transmit Data Level */ - uint32_t IC_DMA_RDLR; /*!< (0x90) : DMA Receive Data Level */ - uint32_t IC_SDA_SETUP; /*!< (0x94) : SDA Setup Register */ - uint32_t IC_ACK_GENERAL_CALL; /*!< (0x98) : ACK General Call Register */ - uint32_t IC_ENABLE_STATUS; /*!< (0x9c) : Enable Status Register */ - uint32_t IC_FS_SPKLEN; /*!< (0xa0) : ISS and FS spike suppression limit */ - uint32_t IC_HS_SPKLEN; /*!< (0xa4) : HS spike suppression limit */ - uint32_t RESERVED[19]; /*!< (0xa8) : Reserved */ - uint32_t IC_COMP_PARAM_1; /*!< (0xf4) : Component Parameter Register */ - uint32_t IC_COMP_VERSION; /*!< (0xf8) : Component Version ID Reg */ - uint32_t IC_COMP_TYPE; /*!< (0xfc) : Component Type Reg */ -} DW_IIC_REG, *DW_IIC_REG_PTR; -/** @} */ - -/** Spike Suppression Limit Configurations */ -typedef struct dw_iic_spklen { - uint32_t fs_spklen; /*!< value for IC_FS_SPKLEN, Tsp for fast mode is 50ns */ - uint32_t hs_spklen; /*!< value for IC_HS_SPKLEN, Tsp for high-speed mode is 10ns */ -} DW_IIC_SPKLEN, *DW_IIC_SPKLEN_PTR; - -/** IIC Clock SCL High and Low Count Configurations for Different Speed */ -typedef struct dw_iic_scl_cnt { - uint32_t ss_scl_hcnt; /*!< value for IC_SS_SCL_HCNT */ - uint32_t ss_scl_lcnt; /*!< value for IC_SS_SCL_LCNT */ - uint32_t fs_scl_hcnt; /*!< value for IC_FS_SCL_HCNT */ - uint32_t fs_scl_lcnt; /*!< value for IC_FS_SCL_LCNT */ - uint32_t hs_scl_hcnt; /*!< value for IC_HS_SCL_HCNT */ - uint32_t hs_scl_lcnt; /*!< value for IC_HS_SCL_LCNT */ -} DW_IIC_SCL_CNT, *DW_IIC_SCL_CNT_PTR; - -#define DW_IIC_GINT_DISABLED (0) /*!< designware interrupt disabled for control iic irq/fiq */ -#define DW_IIC_GINT_ENABLE (1<<0) /*!< designware interrupt enabled for control iic irq/fiq */ -#define DW_IIC_TXINT_ENABLE (1<<1) /*!< designware interrupt enabled for control transmit process */ -#define DW_IIC_RXINT_ENABLE (1<<2) /*!< designware interrupt enabled for control transmit process */ - -typedef struct dw_iic_buffer { - DEV_BUFFER *buf; - uint32_t ofs; - uint32_t len; -} DW_IIC_BUFFER, *DW_IIC_BUFFER_PTR; - -/** - * \brief DesignWare IIC control structure definition - * \details implement of dev_iic_info::iic_ctrl - */ -typedef struct dw_iic_ctrl { - DW_IIC_REG *dw_iic_regs; /*!< iic device registers */ - /* Variables which should be set during object implementation */ - uint32_t support_modes; /*!< supported iic modes */ - uint32_t tx_fifo_len; /*!< transmit fifo length */ - uint32_t rx_fifo_len; /*!< receive fifo length */ - uint32_t iic_master_code; /*!< value for IC_HS_MADDR */ - uint32_t retry_cnt; /*!< retry count for TX or RX */ - uint32_t intno; /*!< iic interrupt vector number */ - INT_HANDLER dw_iic_int_handler; /*!< iic interrupt handler */ - DW_IIC_SPKLEN iic_spklen; /*!< iic spike suppression length settings */ - DW_IIC_SCL_CNT iic_scl_cnt; /*!< iic scl count settings */ - /* Variables which always change during iic operation */ - uint32_t int_status; /*!< iic interrupt status */ - uint32_t iic_tx_over; /*!< iic tx overflow count */ - uint32_t iic_rx_over; /*!< iic rx overflow count */ - DW_IIC_BUFFER dw_iic_rxbuf; /*!< iic read buffer for receive data */ -} DW_IIC_CTRL, *DW_IIC_CTRL_PTR; - -/*!< One possible value for \ref dw_iic_ctrl::retry_cnt */ -#define DW_IIC_MAX_RETRY_COUNT (100000) - -#if DW_IIC_USE_IC_CLK_MHZ == 100 /*!< 100MHz */ -/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */ -static const DW_IIC_SPKLEN dw_iic_spklen_const = {5, 1}; - -/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */ -#if DW_IIC_USE_HS_BUS_LOADING_100PF -static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0x6, 0x10}; -#else -static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0xc, 0x20}; -#endif - -#elif DW_IIC_USE_IC_CLK_MHZ == 50 /* 50MHz */ -/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */ -static const DW_IIC_SPKLEN dw_iic_spklen_const = {5, 1}; - -/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */ -#if DW_IIC_USE_HS_BUS_LOADING_100PF -static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x00c8, 0x00eb, 0x001e, 0x0041, 0x6, 0x8}; -#else -static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x00c8, 0x00eb, 0x001e, 0x0041, 0x6, 0x10}; -#endif - -#else /* Default 100MHz */ -/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */ -static const DW_IIC_SPKLEN dw_iic_spklen_const = {5, 1}; - -/*!< One possible value for \ref dw_iic_ctrl::iic_spklen */ -#if DW_IIC_USE_HS_BUS_LOADING_100PF -static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0x6, 0x10}; -#else -static const DW_IIC_SCL_CNT dw_iic_sclcnt_const = {0x0190, 0x01d6, 0x003c, 0x0082, 0xc, 0x20}; -#endif - -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup DEVICE_DW_IIC_FUNCDLR DesignWare IIC Function Declaration - * \ingroup DEVICE_DW_IIC - * \brief Contains declarations of designware iic functions. - * \details This are only used in iic object implementation source file - * @{ - */ -extern int32_t dw_iic_open (DEV_IIC *iic_obj, uint32_t mode, uint32_t param); -extern int32_t dw_iic_close (DEV_IIC *iic_obj); -extern int32_t dw_iic_control (DEV_IIC *iic_obj, uint32_t ctrl_cmd, void *param); -extern int32_t dw_iic_write (DEV_IIC *iic_obj, const void *data, uint32_t len); -extern int32_t dw_iic_read (DEV_IIC *iic_obj, void *data, uint32_t len); -extern void dw_iic_isr(DEV_IIC *iic_obj, void *ptr); - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif /* _DW_IIC_H_ */ diff --git a/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal.h b/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal.h deleted file mode 100644 index f7ec0d27a25e4cb833f802f8b47a491c5107acda..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal.h +++ /dev/null @@ -1,186 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2017.03 - * \date 2014-06-30 - * \author Huaqi Fang(Huaqi.Fang@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup DEVICE_DW_IIC - * \brief DesignWare IIC driver hardware description related header file - * \details detailed hardware related definitions of DesignWare IIC driver - */ - -#ifndef _DEVICE_DW_IIC_HAL_H_ -#define _DEVICE_DW_IIC_HAL_H_ - -#include "device/designware/iic/dw_iic_hal_cfg.h" - -/** Enable Designware IIC */ -#define DW_IIC_ENABLE (1) -/** Disable Designware IIC */ -#define DW_IIC_DISABLE (0) - -/** Stop Condition issue after this byte */ -#define IC_DATA_CMD_STOP (1 << 9) -/** Restart Condition issue after this byte */ -#define IC_DATA_CMD_RESTART (1 << 10) -/** No Restart or stop condition after this byte */ -#define IC_DATA_CMD_NONE (0) - -/** Perform a write request */ -#define IC_DATA_CMD_WRITE_REQ (0) -/** Perform a read request */ -#define IC_DATA_CMD_READ_REQ (1 << 8) - -/** Fields of IC_CON register */ -/* DW_APB I2C IP Config Dependencies. */ -#if DW_IIC_ALLOW_RESTART -#define IC_CON_RESTART_EN (1 << 5) -#else -#define IC_CON_RESTART_EN (0x00) -#endif - -/* Master Addressing Mode Config */ -#if DW_IIC_MST_10_BIT_ADDR_SUPPORT -#define MST_10_BIT_ADDR_MODE (1 << 4) -#define IC_10BITADDR_MASTER (1 << 12) -#else -#define MST_10_BIT_ADDR_MODE (0x00) -#define IC_10BITADDR_MASTER (0x00) -#endif - -/* Slave Addressing Mode Config */ -#if DW_IIC_SLV_10_BIT_ADDR_SUPPORT -#define SLV_10_BIT_ADDR_MODE (1 << 3) -#else -#define SLV_10_BIT_ADDR_MODE (0x00) -#endif - -#if DW_IIC_SPECIAL_START_BYTE -#define IC_TAR_SPECIAL (1 << 11) -#define IC_TAR_GC_OR_START (1 << 10) -#else -#define IC_TAR_SPECIAL (0x00) -#define IC_TAR_GC_OR_START (0x00) -#endif - -/** 7bit IIC address mask for target address register */ -#define IC_TAR_7BIT_ADDR_MASK (0x7F) -/** 7bit IIC address mask for slave address register */ -#define IC_SAR_7BIT_ADDR_MASK (0x7F) -/** 10bit IIC address mask for target address register */ -#define IC_TAR_10BIT_ADDR_MASK (0x3FF) -/** 10bit IIC address mask for slave address register */ -#define IC_SAR_10BIT_ADDR_MASK (0x3FF) - -/** Speed modes of IC_CON */ -#define IC_CON_SPEED_MASK (0x6) -#define IC_CON_SPEED_STANDARD (0x2) -#define IC_CON_SPEED_FAST (0x4) -#define IC_CON_SPEED_HIGH (0x6) -/** Working mode of IC_CON */ -#define IC_CON_MST_SLV_MODE_MASK (0x41) -#define IC_CON_ENA_MASTER_MODE (0x41) -#define IC_CON_ENA_SLAVE_MODE (0) - -/* IIC interrupt control */ -#define IC_INT_DISABLE_ALL (0x0) -#define IC_INT_ENABLE_ALL (0x7FF) -/* Interrupt Register Fields */ -#define IC_INTR_STAT_GEN_CALL (1 << 11) -#define IC_INTR_STAT_START_DET (1 << 10) -#define IC_INTR_STAT_STOP_DET (1 << 9) -#define IC_INTR_STAT_ACTIVITY (1 << 8) -#define IC_INTR_STAT_RX_DONE (1 << 7) -#define IC_INTR_STAT_TX_ABRT (1 << 6) -#define IC_INTR_STAT_RD_REQ (1 << 5) -#define IC_INTR_STAT_TX_EMPTY (1 << 4) -#define IC_INTR_STAT_TX_OVER (1 << 3) -#define IC_INTR_STAT_RX_FULL (1 << 2) -#define IC_INTR_STAT_RX_OVER (1 << 1) -#define IC_INTR_STAT_RX_UNDER (1 << 0) - -/* Interrupt enable mask as master */ -#define IC_INT_MST_TX_ENABLE (IC_INTR_STAT_TX_EMPTY|IC_INTR_STAT_TX_OVER|IC_INTR_STAT_TX_ABRT) -#define IC_INT_MST_RX_ENABLE (IC_INTR_STAT_TX_EMPTY|IC_INTR_STAT_RX_FULL|IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER|IC_INTR_STAT_TX_ABRT) - -/* Interrupt enable mask as master */ -#define IC_INT_SLV_COMMON_ENABLE (IC_INTR_STAT_START_DET|IC_INTR_STAT_STOP_DET) -#define IC_INT_SLV_TX_ENABLE (IC_INTR_STAT_RD_REQ|IC_INTR_STAT_TX_ABRT) -#define IC_INT_SLV_RX_ENABLE (IC_INTR_STAT_RX_FULL|IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER) - -/* IC_ENABLE_STATUS Bits */ -#define IC_ENABLE_STATUS_IC_EN (1 << 0) -#define IC_ENABLE_STATUS_SLV_DIS (1 << 1) -#define IC_ENABLE_STATUS_SLV_RX_LOST (1 << 2) - -/* IIC TX & RX threshold settings */ -#define IIC_TX_THRESHOLD (0) -#define IIC_RX_THRESHOLD (0) - -/* DW_APB IIC (DW_IC_STATUS) Status Register Fields. */ -#define IC_STATUS_ACTIVITY (0x01) -#define IC_STATUS_TFNF (0x02) /* (1 << 1) */ -#define IC_STATUS_TFE (0x04) /* (1 << 2) */ -#define IC_STATUS_RFNE (0x08) /* (1 << 3) */ -#define IC_STATUS_RFF (0x10) /* (1 << 4) */ -#define IC_STATUS_MASTER_ACT (0x20) /* (1 << 5) */ -#define IC_STATUS_SLAVE_ACT (0x40) /* (1 << 6) */ - -/* IC_TX_ABRT_SOURCE Register Bit Fields */ -#define IC_TX_ABRT_7B_ADDR_NOACK (1 << 0) -#define IC_TX_ABRT_10ADDR1_NOACK (1 << 1) -#define IC_TX_ABRT_10ADDR2_NOACK (1 << 2) -#define IC_TX_ABRT_TXDATA_NOACK (1 << 3) -#define IC_TX_ABRT_GCALL_NOACK (1 << 4) -#define IC_TX_ABRT_GCALL_READ (1 << 5) -#define IC_TX_ABRT_HS_ACKDET (1 << 6) -#define IC_TX_ABRT_SBYTE_ACKDET (1 << 7) -#define IC_TX_ABRT_HS_NORSTRT (1 << 8) -#define IC_TX_ABRT_SBYTE_NORSTRT (1 << 9) -#define IC_TX_ABRT_10B_RD_NORSTRT (1 << 10) -#define IC_TX_ABRT_MASTER_DIS (1 << 11) -#define IC_TX_ABRT_ARB_LOST (1 << 12) -#define IC_TX_ABRT_SLVFLUSH_TXFIFO (1 << 13) -#define IC_TX_ABRT_SLV_ARBLOST (1 << 14) -#define IC_TX_ABRT_SLVRD_INTX (1 << 15) - -/* Combined bits for iic abort source as master */ -#define IIC_MST_ABRT_ADDR_NOACK (IC_TX_ABRT_7B_ADDR_NOACK|IC_TX_ABRT_10ADDR1_NOACK|IC_TX_ABRT_10ADDR1_NOACK) -#define IIC_MST_ABRT_LOST_BUS (IC_TX_ABRT_ARB_LOST) -#define IIC_MST_ABRT_DATA_NOACK (IC_TX_ABRT_TXDATA_NOACK) - -/* Combined bits for iic abort source as slave */ -#define IIC_SLV_ABRT_LOST_BUS (IC_TX_ABRT_ARB_LOST|IC_TX_ABRT_SLV_ARBLOST) - -/** @} */ - -#endif /* _DEVICE_DW_IIC_HAL_H_ */ diff --git a/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal_cfg.h b/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal_cfg.h deleted file mode 100644 index 1073162176c3961d9f58d6f8669a2694fd06efa0..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/device/designware/iic/dw_iic_hal_cfg.h +++ /dev/null @@ -1,82 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2017.03 - * \date 2014-07-01 - * \author Huaqi Fang(Huaqi.Fang@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup DEVICE_DW_IIC - * \brief DesignWare IIC driver hardware description - * related header file configuration file - * \details configuration file to enable or disable some function of iic - */ - -#ifndef _DEVICE_DW_IIC_HAL_CFG_H_ -#define _DEVICE_DW_IIC_HAL_CFG_H_ - -#ifndef DW_IIC_ALLOW_RESTART -#define DW_IIC_ALLOW_RESTART (1) /*!< allow restart configuration */ -#endif - -#ifdef DW_IIC_SPECIAL_START_BYTE -#define DW_IIC_SPECIAL_START_BYTE (0) /*!< SPECIAL bit enable in IC_TAR */ -#endif - -#ifndef DW_IIC_MST_10_BIT_ADDR_SUPPORT -#define DW_IIC_MST_10_BIT_ADDR_SUPPORT (1) /*!< enable 10-bit address mode */ -#endif - -#ifdef DW_IIC_SLV_10_BIT_ADDR_SUPPORT -#define DW_IIC_SLV_10_BIT_ADDR_SUPPORT (1) /*!< slave 10-bit addressing mode */ -#endif - -#ifndef DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT -#define DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT (0) /*!< Dynamic target address update support */ -#endif - -#ifndef DW_IIC_DISABLE_MAX_T_POLL_CNT -#define DW_IIC_DISABLE_MAX_T_POLL_CNT (1250) /*!< Timeout count, approximate to be 25us in 50MHz CPU @ Standard mode */ -#endif - -#ifndef DW_IIC_CALC_FIFO_LEN_ENABLE -#define DW_IIC_CALC_FIFO_LEN_ENABLE (1) /*!< Default enable calculate fifo length */ -#endif - -#ifndef DW_IIC_USE_IC_CLK_MHZ -#define DW_IIC_USE_IC_CLK_MHZ (50) /*!< Default use 50MHz IC_CLK */ -#endif - -#ifndef DW_IIC_USE_HS_BUS_LOADING_100PF -#define DW_IIC_USE_HS_BUS_LOADING_100PF (1) /*!< Use bus loading 100pf */ -#endif - -#endif /* _DEVICE_DW_IIC_HAL_CFG_H_ */ - diff --git a/bsp/synopsys/embarc/device/designware/spi/dw_spi.c b/bsp/synopsys/embarc/device/designware/spi/dw_spi.c deleted file mode 100644 index bea413b411869cbf91d06d3307f75b087851ca60..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/device/designware/spi/dw_spi.c +++ /dev/null @@ -1,1337 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2017.03 - * \date 2014-06-25 - * \author Huaqi Fang(Huaqi.Fang@synopsys.com) ---------------------------------------------- */ - -/** - * \defgroup DEVICE_DW_SPI Designware SPI Driver - * \ingroup DEVICE_DW - * \brief Designware SPI Driver Implementation - */ - -/** - * \file - * \brief DesignWare SPI driver implementation based on device hal layer definition (\ref dev_spi.h) - * \ingroup DEVICE_DW_SPI - */ -#include - -#include "inc/embARC_toolchain.h" -#include "inc/embARC_error.h" - -#include "inc/arc/arc_exception.h" - -#include "device/designware/spi/dw_spi_hal.h" -#include "device/designware/spi/dw_spi.h" - -/** - * \defgroup DEVICE_DW_SPI_DEFINES DesignWare SPI Driver Macros - * \ingroup DEVICE_DW_SPI - * \brief DesignWare SPI driver macros used in spi driver - * @{ - */ -/** check expressions used in DesignWare SPI driver implementation */ -#define DW_SPI_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) - -/** convert DesignWare frequence to divisor */ -#define DW_SPI_FREQ2DV(perifreq, spifreq) ((perifreq) / (spifreq)) - -#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK -/** valid check of spi info object */ -#define VALID_CHK_SPI_INFO_OBJECT(spiinfo_obj_ptr) { \ - DW_SPI_CHECK_EXP((spiinfo_obj_ptr)!=NULL, E_OBJ); \ - DW_SPI_CHECK_EXP(((spiinfo_obj_ptr)->spi_ctrl)!=NULL, E_OBJ); \ - } -#endif - -/** - * \defgroup DEVICE_DW_SPI_DEF_CBR DesignWare SPI Interrupt Callback Routine Select Marcos - * \ingroup DEVICE_DW_SPI_DEFINES - * \brief DesignWare SPI interrupt callback routines select macros definitions - * @{ - */ -#define DW_SPI_RDY_SND (1U) /*!< ready to send callback */ -#define DW_SPI_RDY_RCV (2U) /*!< ready to receive callback */ -#define DW_SPI_RDY_XFER (3U) /*!< ready to transfer callback */ -/** @} */ - -/** @} */ - -/** - * \defgroup DEVICE_DW_SPI_STATIC DesignWare SPI Driver Static Functions - * \ingroup DEVICE_DW_SPI - * \brief Static or inline functions, variables for DesignWare SPI handle spi operations, - * only used in this file. - * @{ - */ - -/** Disable designware spi device */ -Inline void dw_spi_disable(DW_SPI_REG *spi_reg_ptr) -{ -/** disable spi operations, then program spi control regs is possible */ - spi_reg_ptr->SSIENR = DW_SPI_SSI_DISABLE; -} -/** Enable designware spi device */ -Inline void dw_spi_enable(DW_SPI_REG *spi_reg_ptr) -{ - spi_reg_ptr->SSIENR = DW_SPI_SSI_ENABLE; -} - -/** Clear all designware spi interrupt */ -Inline void dw_spi_clear_interrupt_all(DW_SPI_REG *spi_reg_ptr) -{ - (void)spi_reg_ptr->ICR; -} - -/** test whether spi is busy, busy return 1, else 0 */ -Inline int32_t dw_spi_busy(DW_SPI_REG *spi_reg_ptr) -{ - return ((spi_reg_ptr->SR & DW_SPI_SR_BUSY) != 0); -} -/** test whether spi is ready to send, 1 ready, 0 not ready */ -Inline int32_t dw_spi_putready(DW_SPI_REG *spi_reg_ptr) -{ - return ((spi_reg_ptr->SR & DW_SPI_SR_TFNF) != 0); -} -/** test whether spi is read to receive, 1 ready, 0 not ready */ -Inline int32_t dw_spi_getready(DW_SPI_REG *spi_reg_ptr) -{ - return ((spi_reg_ptr->SR & DW_SPI_SR_RFNE) != 0); -} -/** write data to spi send fifo */ -Inline void dw_spi_putdata(DW_SPI_REG *spi_reg_ptr, int32_t data) -{ - spi_reg_ptr->DATAREG = (uint32_t)data; -} -/** read data from spi receive fifo, return data received */ -Inline int32_t dw_spi_getdata(DW_SPI_REG *spi_reg_ptr) -{ - return (int32_t)spi_reg_ptr->DATAREG; -} -/** - * \brief send data by spi when available, - * mostly used in interrupt method, non-blocked function - * \param[in] spi_reg_ptr spi register structure pointer - * \param[in] data data to be sent - * \retval E_OK send successfully - * \retval E_OBJ not ready to send data - */ -Inline int32_t dw_spi_snd_dat(DW_SPI_REG *spi_reg_ptr, int32_t data) -{ - if (dw_spi_putready(spi_reg_ptr)) { - dw_spi_putdata(spi_reg_ptr, data); - return E_OK; - } - return E_OBJ; -} -/** - * \brief receive one char from spi, - * mostly used in interrupt routine, non-blocked function - * \param[in] spi_reg_ptr spi register structure pointer - * \return data received by the spi - */ -Inline int32_t dw_spi_rcv_dat(DW_SPI_REG *spi_reg_ptr) -{ - return dw_spi_getdata(spi_reg_ptr); -} -/** - * \brief send char by spi in poll method, blocked function - * \param[in] spi_reg_ptr spi register structure pointer - * \param[in] data data to be sent - */ -Inline void dw_spi_psnd_dat(DW_SPI_REG *spi_reg_ptr, int32_t data) -{ - /** wait until spi is ready to send */ - while (!dw_spi_putready(spi_reg_ptr)); /* blocked */ - /** send char */ - dw_spi_putdata(spi_reg_ptr, data); -} -/** - * \brief receive one char from spi in poll method, blocked function - * \param[in] spi_reg_ptr spi register structure pointer - * \return data received by the spi - */ -Inline int32_t dw_spi_prcv_dat(DW_SPI_REG *spi_reg_ptr) -{ - /** wait until spi is ready to receive */ - while (!dw_spi_getready(spi_reg_ptr)); /* blocked */ - /** receive data */ - return dw_spi_getdata(spi_reg_ptr); -} - -/** Reset designware FIFO by disable spi device, then enable device */ -Inline void dw_spi_reset_fifo(DW_SPI_REG *spi_reg_ptr) -{ - dw_spi_disable(spi_reg_ptr); - dw_spi_enable(spi_reg_ptr); -} - -/** Enable designware spi bit interrupt with mask */ -Inline void dw_spi_unmask_interrupt(DW_SPI_REG *spi_reg_ptr, uint32_t mask) -{ - spi_reg_ptr->IMR |= mask; -} - -/** Disable designware spi bit interrupt with mask */ -Inline void dw_spi_mask_interrupt(DW_SPI_REG *spi_reg_ptr, uint32_t mask) -{ - spi_reg_ptr->IMR &= ~mask; -} - -/** Set designware spi device frequency */ -Inline void dw_spi_set_freq(DW_SPI_CTRL *spi_ctrl_ptr, uint32_t freq) -{ - uint32_t sck_divisor; - DW_SPI_REG *spi_reg_ptr = spi_ctrl_ptr->dw_spi_regs; - - dw_spi_disable(spi_reg_ptr); - - sck_divisor = DW_SPI_FREQ2DV(spi_ctrl_ptr->dw_apb_bus_freq, freq); - spi_reg_ptr->BAUDR = sck_divisor; - dw_spi_enable(spi_reg_ptr); -} - -/** Set designware spi device data frame size */ -static int32_t dw_spi_set_dfs(DW_SPI_REG *spi_reg_ptr, uint32_t dfs) -{ - uint32_t ctrl0_reg; - if ((dfs <= 3) || (dfs > 16)) return -1; - - dw_spi_disable(spi_reg_ptr); - ctrl0_reg = spi_reg_ptr->CTRLR0; - ctrl0_reg &= ~(DW_SPI_CTRLR0_DFS_MASK); - spi_reg_ptr->CTRLR0 = ctrl0_reg | (dfs-1); - dw_spi_enable(spi_reg_ptr); - - return 0; -} - -/** Choose proper designware spi clock mode setting value */ -Inline uint32_t dw_spi_select_clockmode(uint32_t clk_mode) -{ - return (clk_mode << DW_SPI_CTRLR0_SC_OFS); -} - -/** Set designware spi clock mode */ -Inline int32_t dw_spi_set_clockmode(DW_SPI_REG *spi_reg_ptr, uint32_t clk_mode) -{ - if (clk_mode > SPI_CPOL_1_CPHA_1) { - return -1; - } - dw_spi_disable(spi_reg_ptr); - spi_reg_ptr->CTRLR0 &= ~(DW_SPI_CTRLR0_SC_MASK); - spi_reg_ptr->CTRLR0 |= dw_spi_select_clockmode(clk_mode); - dw_spi_enable(spi_reg_ptr); - return 0; -} - -/** Select a spi slave with slv_line */ -Inline int32_t dw_spi_select_slave(DW_SPI_REG *spi_reg_ptr, uint32_t slv_line) -{ - /* check if spi busy */ - if (dw_spi_busy(spi_reg_ptr)) return -1; - - spi_reg_ptr->SER = 1<SER = 0; - return 0; -} - -Inline void dw_spi_flush_tx(DW_SPI_REG *spi_reg_ptr) -{ - dw_spi_reset_fifo(spi_reg_ptr); -} - -Inline void dw_spi_flush_rx(DW_SPI_REG *spi_reg_ptr) -{ - dw_spi_reset_fifo(spi_reg_ptr); -} - -/** Get TX FIFO Length. - * calculate spi fifo length using fifo threshold method - * If you attempt to set bits [7:0] of this register to - * a value greater than or equal to the depth of the FIFO, - * this field is not written and retains its current value. - */ -static uint32_t dw_spi_get_txfifo_len(DW_SPI_REG *spi_reg_ptr) -{ - uint32_t fifo_thr_lev_tmp, left, right, i; - - fifo_thr_lev_tmp = spi_reg_ptr->TXFTLR; - - if (fifo_thr_lev_tmp != 0) { - left = fifo_thr_lev_tmp; - } else { - left = DW_SPI_MIN_FIFO_LENGTH; - } - right = DW_SPI_MAX_FIFO_LENGTH + 1; - - for (i = left; i <= right; i++) { - spi_reg_ptr->TXFTLR = i; - if (spi_reg_ptr->TXFTLR != i) { - break; - } - } - spi_reg_ptr->TXFTLR = fifo_thr_lev_tmp; /* restore old fifo threshold */ - - return (i); -} - -/** Get RX FIFO Length */ -static uint32_t dw_spi_get_rxfifo_len(DW_SPI_REG *spi_reg_ptr) -{ - uint32_t fifo_thr_lev_tmp, left, right, i; - - fifo_thr_lev_tmp = spi_reg_ptr->RXFTLR; - - if (fifo_thr_lev_tmp != 0) { - left = fifo_thr_lev_tmp; - } else { - left = DW_SPI_MIN_FIFO_LENGTH; - } - right = DW_SPI_MAX_FIFO_LENGTH + 1; - - for (i = left; i <= right; i++) { - spi_reg_ptr->RXFTLR = i; - if (spi_reg_ptr->RXFTLR != i) { - break; - } - } - spi_reg_ptr->RXFTLR = fifo_thr_lev_tmp; /* restore old fifo threshold */ - - return (i); -} - -/** Init Designware SPI Hardware */ -static void dw_spi_hw_init(DW_SPI_CTRL *spi_ctrl_ptr, uint32_t clk_mode, uint32_t dfs) -{ - uint32_t ctrl0_reg = 0; - DW_SPI_REG *spi_reg_ptr = spi_ctrl_ptr->dw_spi_regs; - - dw_spi_disable(spi_reg_ptr); - - /* Clear interrupts */ - ctrl0_reg = spi_reg_ptr->ICR; - /* Mask all interrupts */ - spi_reg_ptr->IMR = 0; - - ctrl0_reg = DW_SPI_CTRLR0_FRF_MOTOROLA | DW_SPI_TMOD_TRANSMIT_RECEIVE \ - | dw_spi_select_clockmode(clk_mode) | (dfs - 1) | DW_SPI_CTRLR0_SLV_OE_ENABLE; - spi_reg_ptr->CTRLR0 = ctrl0_reg; - spi_reg_ptr->CTRLR1 = 0; - - /* deselect slaves */ - spi_reg_ptr->SER = 0; - - /* Set threshold values for both tx and rx */ - spi_reg_ptr->TXFTLR = 0; - spi_reg_ptr->RXFTLR = 0; - - dw_spi_enable(spi_reg_ptr); -} - -/** enable designware spi */ -static void dw_spi_enable_device(DEV_SPI_INFO *spi_info_ptr) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - - if ((spi_info_ptr->status & DEV_ENABLED) == 0) { - dw_spi_enable(spi_reg_ptr); - spi_info_ptr->status |= DEV_ENABLED; - } -} - -/** disable designware spi */ -static void dw_spi_disable_device(DEV_SPI_INFO *spi_info_ptr) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - - dw_spi_disable(spi_reg_ptr); - spi_info_ptr->status &= ~DEV_ENABLED; -} - - -/** - * \brief disable designware spi send or receive interrupt - * \param[in] DEV_SPI_INFO *spi_info_ptr - * \param[in] cbrtn control code of callback routine of send or receive - */ -static int32_t dw_spi_dis_cbr(DEV_SPI_INFO *spi_info_ptr, uint32_t cbrtn) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - int32_t ercd = E_OK; - - if ((spi_info_ptr->status & DW_SPI_IN_XFER) != 0) { /* only in transfer need do check */ - switch (cbrtn) { - case DW_SPI_RDY_SND: - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_TX, E_CTX); - spi_info_ptr->status &= ~(DW_SPI_IN_TX); - break; - case DW_SPI_RDY_RCV: - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_RX, E_CTX); - spi_info_ptr->status &= ~(DW_SPI_IN_RX); - break; - case DW_SPI_RDY_XFER: - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_XFER, E_CTX); - spi_info_ptr->status &= ~(DW_SPI_IN_XFER); - break; - default: - break; - } - } - - dw_spi_mask_interrupt(spi_ctrl_ptr->dw_spi_regs, DW_SPI_IMR_XFER); - - if (spi_ctrl_ptr->int_status & DW_SPI_GINT_ENABLE) { - int_disable(spi_ctrl_ptr->intno); - spi_ctrl_ptr->int_status &= ~DW_SPI_GINT_ENABLE; - } - -error_exit: - return ercd; -} - -/** - * \brief enable DesignWare SPI send or receive interrupt - * \param[in] DEV_SPI_INFO *spi_info_ptr - * \param[in] cbrtn control code of callback routine of send or receive - */ -static int32_t dw_spi_ena_cbr(DEV_SPI_INFO *spi_info_ptr, uint32_t cbrtn) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - int32_t ercd = E_OK; - - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == 0, E_CTX); - switch (cbrtn) { - case DW_SPI_RDY_SND: - spi_info_ptr->status |= DW_SPI_IN_TX; - break; - case DW_SPI_RDY_RCV: - spi_info_ptr->status |= DW_SPI_IN_RX; - break; - case DW_SPI_RDY_XFER: - spi_info_ptr->status |= DW_SPI_IN_XFER; - break; - default: - break; - } - dw_spi_unmask_interrupt(spi_ctrl_ptr->dw_spi_regs, DW_SPI_IMR_XFER); - - if ((spi_ctrl_ptr->int_status & DW_SPI_GINT_ENABLE) == 0) { - spi_ctrl_ptr->int_status |= DW_SPI_GINT_ENABLE; - int_enable(spi_ctrl_ptr->intno); - } - -error_exit: - return ercd; -} - -/** - * \brief enable designware spi interrupt - * \param spi_info_ptr spi information structure pointer - */ -static void dw_spi_enable_interrupt(DEV_SPI_INFO *spi_info_ptr) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - - int_handler_install(spi_ctrl_ptr->intno, spi_ctrl_ptr->dw_spi_int_handler); - spi_ctrl_ptr->int_status |= DW_SPI_GINT_ENABLE; - int_enable(spi_ctrl_ptr->intno); /** enable spi interrupt */ -} -/** - * \brief disable designware spi interrupt - * \param spi_info_ptr spi information structure pointer - */ -static void dw_spi_disable_interrupt(DEV_SPI_INFO *spi_info_ptr) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - - /** disable spi send&receive interrupt after disable spi interrupt */ - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_SND); - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_RCV); - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_XFER); - /* disable spi interrupt */ - dw_spi_mask_interrupt(spi_ctrl_ptr->dw_spi_regs, DW_SPI_IMR_XFER); - spi_info_ptr->status &= ~DW_SPI_IN_XFER; - int_disable(spi_ctrl_ptr->intno); - spi_ctrl_ptr->int_status &= ~(DW_SPI_GINT_ENABLE); -} - -static void dw_spi_reset_device(DEV_SPI_INFO *spi_info_ptr) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - - dw_spi_disable_device(spi_info_ptr); - dw_spi_disable_interrupt(spi_info_ptr); - dw_spi_clear_interrupt_all(spi_reg_ptr); - dw_spi_enable_device(spi_info_ptr); -} - -/** abort current interrupt transmit transfer */ -static int32_t dw_spi_abort_tx(DEV_SPI *spi_obj) -{ - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - int32_t ercd = E_OK; - - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) != 0, E_OK); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_TX, E_CTX); - - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_SND); - spi_info_ptr->status |= DEV_IN_TX_ABRT; - if (spi_info_ptr->spi_cbs.tx_cb != NULL) { - spi_info_ptr->spi_cbs.tx_cb(spi_obj); - } - spi_info_ptr->status &= ~(DEV_IN_TX_ABRT); - -error_exit: - return ercd; -} - -/** abort current interrupt receive transfer */ -static int32_t dw_spi_abort_rx(DEV_SPI *spi_obj) -{ - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - int32_t ercd = E_OK; - - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) != 0, E_OK); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_RX, E_CTX); - - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_RCV); - spi_info_ptr->status |= DEV_IN_RX_ABRT; - if (spi_info_ptr->spi_cbs.rx_cb != NULL) { - spi_info_ptr->spi_cbs.rx_cb(spi_obj); - } - spi_info_ptr->status &= ~(DEV_IN_RX_ABRT); - -error_exit: - return ercd; -} - -/** abort current interrupt transfer */ -static int32_t dw_spi_abort_xfer(DEV_SPI *spi_obj) -{ - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - int32_t ercd = E_OK; - - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) != 0, E_OK); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_XFER, E_CTX); - - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_XFER); - spi_info_ptr->status |= DEV_IN_XFER_ABRT; - if (spi_info_ptr->spi_cbs.xfer_cb != NULL) { - spi_info_ptr->spi_cbs.xfer_cb(spi_obj); - } - spi_info_ptr->status &= ~(DEV_IN_XFER_ABRT); - -error_exit: - return ercd; -} - -/** Get available transmit fifo count */ -static int32_t dw_spi_get_txavail(DW_SPI_CTRL *spi_ctrl_ptr) -{ - int32_t tx_avail = 0; - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - -#if DW_SPI_CALC_FIFO_LEN_ENABLE - if (spi_ctrl_ptr->tx_fifo_len <= 1) { - if (dw_spi_putready(spi_reg_ptr) == 1) { - tx_avail = 1; - } else { - tx_avail = 0; - } - } else -#endif - { - tx_avail = spi_ctrl_ptr->tx_fifo_len - spi_reg_ptr->TXFLR; - } - return tx_avail; -} - -/** Get available receive fifo count */ -static int32_t dw_spi_get_rxavail(DW_SPI_CTRL *spi_ctrl_ptr) -{ - int32_t rx_avail = 0; - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - -#if DW_SPI_CALC_FIFO_LEN_ENABLE - if (spi_ctrl_ptr->rx_fifo_len <= 1) { - if (dw_spi_getready(spi_reg_ptr) == 1) { - rx_avail = 1; - } else { - rx_avail = 0; - } - } else -#endif - { - rx_avail = spi_reg_ptr->RXFLR; - } - return rx_avail; -} - -static uint32_t dw_spi_tx_max(DW_SPI_CTRL *spi_ctrl_ptr) -{ - uint32_t tx_left, tx_room; - DW_SPI_TRANSFER *xfer = &(spi_ctrl_ptr->dw_xfer); - - tx_left = (xfer->xfer_len - xfer->tx_idx) / xfer->nbytes; - tx_room = dw_spi_get_txavail(spi_ctrl_ptr); - - return (tx_left < tx_room) ? tx_left : tx_room; -} - -static uint32_t dw_spi_rx_max(DW_SPI_CTRL *spi_ctrl_ptr) -{ - uint32_t rx_left, rx_room; - DW_SPI_TRANSFER *xfer = &(spi_ctrl_ptr->dw_xfer); - - rx_left = (xfer->xfer_len - xfer->rx_idx) / xfer->nbytes; - rx_room = dw_spi_get_rxavail(spi_ctrl_ptr); - - return (rx_left < rx_room) ? rx_left : rx_room; -} - -Inline int32_t dw_spi_rx_end(DW_SPI_CTRL *spi_ctrl_ptr) -{ - DW_SPI_TRANSFER *xfer = &(spi_ctrl_ptr->dw_xfer); - - return (xfer->rx_idx >= xfer->xfer_len); -} - -Inline int32_t dw_spi_tx_end(DW_SPI_CTRL *spi_ctrl_ptr) -{ - DW_SPI_TRANSFER *xfer = &(spi_ctrl_ptr->dw_xfer); - - return (xfer->tx_idx >= xfer->xfer_len); -} - -/** 1 for end, 0 for not end */ -Inline int32_t dw_spi_xfer_end(DW_SPI_CTRL *spi_ctrl_ptr) -{ - return (dw_spi_tx_end(spi_ctrl_ptr) && dw_spi_rx_end(spi_ctrl_ptr)); -} - -static int32_t dw_spi_writer(DEV_SPI_INFO *spi_info_ptr) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl); - DW_SPI_TRANSFER *dw_xfer = &(spi_ctrl_ptr->dw_xfer); - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - uint32_t tx_max = dw_spi_tx_max(spi_ctrl_ptr); - int32_t tx_w; - uint32_t tx_cnt = tx_max; - - if (dw_xfer->tx_xfer == NULL) { - return 0; - } - while (tx_max) { - if (dw_xfer->tx_xfer->tx_idx >= dw_xfer->tx_xfer->tot_len) { - dw_xfer->tx_xfer = dw_xfer->tx_xfer->next; - if (dw_xfer->tx_xfer == NULL) { - break; - } - } - if ( (dw_xfer->tx_xfer->tx_idx >= dw_xfer->tx_xfer->tx_ofs) \ - && (dw_xfer->tx_xfer->tx_idx < dw_xfer->tx_xfer->tx_totlen)) { - if (dw_xfer->nbytes == 1) { - tx_w = (int32_t)(*(int8_t *)(dw_xfer->tx_xfer->tx_buf)); - } else { - tx_w = (int32_t)(*(int16_t *)(dw_xfer->tx_xfer->tx_buf)); - } - dw_xfer->tx_xfer->tx_buf += dw_xfer->nbytes; - } else { - tx_w = spi_info_ptr->dummy; - } - dw_spi_putdata(spi_reg_ptr, tx_w); - dw_xfer->tx_xfer->tx_idx += dw_xfer->nbytes; - dw_xfer->tx_idx += dw_xfer->nbytes; - tx_max --; - } - return ((tx_cnt-tx_max) * dw_xfer->nbytes); -} - -static int32_t dw_spi_reader(DEV_SPI_INFO *spi_info_ptr) -{ - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl); - DW_SPI_TRANSFER *dw_xfer = &(spi_ctrl_ptr->dw_xfer); - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - uint32_t rx_max = dw_spi_rx_max(spi_ctrl_ptr); - int32_t rx_w; - uint32_t rx_cnt = rx_max; - - if (dw_xfer->rx_xfer == NULL) { - return 0; - } - while (rx_max) { - if (dw_xfer->rx_xfer->rx_idx >= dw_xfer->rx_xfer->tot_len) { - dw_xfer->rx_xfer = dw_xfer->rx_xfer->next; - if (dw_xfer->rx_xfer == NULL) { - break; - } - } - rx_w = dw_spi_getdata(spi_reg_ptr); - if ( (dw_xfer->rx_xfer->rx_idx >= dw_xfer->rx_xfer->rx_ofs) \ - && (dw_xfer->rx_xfer->rx_idx < dw_xfer->rx_xfer->rx_totlen) ) { - if (dw_xfer->nbytes == 1) { - *(int8_t *)(dw_xfer->rx_xfer->rx_buf) = rx_w; - } else { - *(int16_t *)(dw_xfer->rx_xfer->rx_buf) = rx_w; - } - dw_xfer->rx_xfer->rx_buf += dw_xfer->nbytes; - } - dw_xfer->rx_xfer->rx_idx += dw_xfer->nbytes; - dw_xfer->rx_idx += dw_xfer->nbytes; - rx_max --; - } - return ((rx_cnt-rx_max) * dw_xfer->nbytes); -} - -Inline uint32_t dw_spi_nbytes(uint32_t dfs) -{ - uint32_t nbytes = 1; - - if (dfs > 8) nbytes = 2; - return nbytes; -} - -static void dw_spi_init_transfer(DW_SPI_CTRL *spi_ctrl_ptr, DEV_SPI_TRANSFER *xfer, uint32_t dfs) -{ - DW_SPI_TRANSFER *dw_xfer= &(spi_ctrl_ptr->dw_xfer); - uint32_t tot_len = 0; - - dw_xfer->tx_xfer = xfer; - dw_xfer->rx_xfer = xfer; - dw_xfer->tx_idx = 0; - dw_xfer->rx_idx = 0; - dw_xfer->nbytes = dw_spi_nbytes(dfs); - - /** Calculate all transfer length */ - while (xfer) { - DEV_SPI_XFER_INIT(xfer); - tot_len += xfer->tot_len; - xfer = xfer->next; - } - dw_xfer->xfer_len = tot_len; -} - -/* Check buffer align status, 0 for aligned, -1 for not-aligned */ -static int32_t dw_spi_chk_xfer_aligned(DEV_SPI_TRANSFER *xfer, uint32_t dfs) -{ - uint32_t align_bytes = 1; - if (xfer == NULL) return -1; - - if (dfs > 8) { - align_bytes = 2; - } else { - return 0; - } - - while (xfer) { - /* check tx buffer align status */ - if (xfer->tx_len != 0) { - if (xfer->tx_len % align_bytes) return -1; - if (xfer->tx_ofs % align_bytes) return -1; - if (!CHECK_ALIGN_BYTES(xfer->tx_buf, align_bytes)) return -1; - } - /* check tx buffer align status */ - if (xfer->rx_len != 0) { - if (xfer->rx_len % align_bytes) return -1; - if (xfer->rx_ofs % align_bytes) return -1; - if (!CHECK_ALIGN_BYTES(xfer->rx_buf, align_bytes)) return -1; - } - xfer = xfer->next; - } - return 0; -} - -static uint32_t dw_spi_poll_transfer(DEV_SPI_INFO *spi_info_ptr) -{ - uint32_t len = 0; - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl); - - spi_info_ptr->status |= DEV_IN_XFER; - while (!dw_spi_xfer_end(spi_ctrl_ptr)) { - len += dw_spi_writer(spi_info_ptr); - len += dw_spi_reader(spi_info_ptr); - } - spi_info_ptr->status &= ~DEV_IN_XFER; - - return len>>1; -} - -/** @} */ - -/** - * \brief open a designware spi device - * \param[in] spi_obj spi object pointer - * \param[in] mode spi working mode (master or slave) - * \param[in] param parameter, for master, param is the freq, for slave, param is dfs - * \retval E_OK Open successfully without any issues - * \retval E_OPNED If device was opened before with different parameters, - * then just increase the \ref dev_spi_info::opn_cnt "opn_cnt" and return \ref E_OPNED - * \retval E_OBJ Device object is not valid - * \retval E_SYS Device is opened for different mode before, if you want to open it with different mode, you need to fully close it first. - * \retval E_PAR Parameter is not valid - * \retval E_NOSPT Open settings are not supported - */ -int32_t dw_spi_open (DEV_SPI *spi_obj, uint32_t mode, uint32_t param) -{ - int32_t ercd = E_OK; - uint32_t param2check; - uint32_t clk_mode, dfs_val; - uint32_t support_modes; - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - - /* START ERROR CHECK */ - VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr); - DW_SPI_CHECK_EXP((mode==DEV_MASTER_MODE)||(mode==DEV_SLAVE_MODE), E_PAR); - if (mode == DEV_SLAVE_MODE) { /* clock mode should be in the enum structure */ - DW_SPI_CHECK_EXP((param>=SPI_CPOL_0_CPHA_0) && (param<=SPI_CPOL_1_CPHA_1), E_PAR); - } else { /* frequence should > 0 */ - DW_SPI_CHECK_EXP(param>0, E_PAR); - } - /* END OF ERROR CHECK */ - - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl); - - /* Check supported modes, master or slave */ - support_modes = spi_ctrl_ptr->support_modes; - DW_SPI_CHECK_EXP( (((support_modes)&DW_SPI_MASTER_SUPPORTED)&&(mode == DEV_MASTER_MODE)) || \ - (((support_modes)&DW_SPI_SLAVE_SUPPORTED)&&(mode == DEV_SLAVE_MODE)), E_NOSPT); - - /** Check opened before use case */ - if (spi_info_ptr->opn_cnt > 0) { - if (mode != spi_info_ptr->mode) { - /* current working mode is different from passing mode */ - return E_SYS; - } - if (mode == DEV_MASTER_MODE) { /* param is freq when as master */ - param2check = spi_info_ptr->freq; - } else { /* param is clk_mode when as slave */ - param2check = spi_info_ptr->clk_mode; - } - spi_info_ptr->opn_cnt ++; - if (param != param2check) { /* open with different speed mode */ - return E_OPNED; - } else { - return E_OK; - } - } - /* auto increase open count */ - spi_info_ptr->opn_cnt ++; - - /* Do FIFO Length get before init */ -#if DW_SPI_CALC_FIFO_LEN_ENABLE - spi_ctrl_ptr->tx_fifo_len = dw_spi_get_txfifo_len(spi_ctrl_ptr->dw_spi_regs); - spi_ctrl_ptr->rx_fifo_len = dw_spi_get_rxfifo_len(spi_ctrl_ptr->dw_spi_regs); -#endif - /* hardware init */ - spi_info_ptr->mode = mode; - clk_mode = SPI_CLK_MODE_DEFAULT; - dfs_val = SPI_DFS_DEFAULT; - if (mode == DEV_SLAVE_MODE) { - clk_mode = param; - } - spi_info_ptr->dfs = dfs_val; - spi_info_ptr->clk_mode = clk_mode; - dw_spi_hw_init(spi_ctrl_ptr, clk_mode, dfs_val); - if (mode == DEV_MASTER_MODE) { /* Deselect all slaves, and set frequence */ - dw_spi_deselect_slave(spi_ctrl_ptr->dw_spi_regs, 0); - dw_spi_set_freq(spi_ctrl_ptr, param); - spi_info_ptr->freq = param; - } - - spi_info_ptr->status = DEV_ENABLED; - spi_info_ptr->extra = NULL; - spi_info_ptr->slave = SPI_SLAVE_NOT_SELECTED; - spi_info_ptr->dummy = 0xff; - - spi_ctrl_ptr->int_status = 0; - dw_spi_init_transfer(spi_ctrl_ptr, NULL, dfs_val); - - /** install spi interrupt into system */ - dw_spi_disable_interrupt(spi_info_ptr); - int_handler_install(spi_ctrl_ptr->intno, spi_ctrl_ptr->dw_spi_int_handler); - memset(&(spi_info_ptr->xfer), 0, sizeof(DEV_SPI_TRANSFER)); - memset(&(spi_info_ptr->spi_cbs), 0, sizeof(DEV_SPI_CBS)); - -error_exit: - return ercd; -} - -/** - * \brief close a DesignWare SPI device - * \param[in] spi_obj spi object pointer - * \retval E_OK Close successfully without any issues(including scenario that device is already closed) - * \retval E_OPNED Device is still opened, the device \ref dev_spi_info::opn_cnt "opn_cnt" decreased by 1 - * \retval E_OBJ Device object is not valid - */ -int32_t dw_spi_close (DEV_SPI *spi_obj) -{ - int32_t ercd = E_OK; - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - - /* START ERROR CHECK */ - VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr); - DW_SPI_CHECK_EXP(spi_info_ptr->opn_cnt > 0, E_OK); - /* END OF ERROR CHECK */ - - spi_info_ptr->opn_cnt --; - if (spi_info_ptr->opn_cnt == 0) { - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - - dw_spi_disable_interrupt(spi_info_ptr); - dw_spi_abort_tx(spi_obj); - dw_spi_abort_rx(spi_obj); - memset(&(spi_info_ptr->xfer), 0, sizeof(DEV_SPI_TRANSFER)); - memset(&(spi_info_ptr->spi_cbs), 0, sizeof(DEV_SPI_CBS)); - memset(&(spi_ctrl_ptr->dw_xfer), 0, sizeof(DW_SPI_TRANSFER)); - dw_spi_disable_device(spi_info_ptr); - spi_info_ptr->status = DEV_DISABLED; - spi_info_ptr->extra = NULL; - } else { - ercd = E_OPNED; - } - -error_exit: - return ercd; -} - -/** - * \brief control spi by ctrl command - * \param[in] spi_obj spi object pointer - * \param[in] ctrl_cmd control command code to do specific spi work - * \param[in,out] param parameters used to control spi or return something - * \retval E_OK Control device successfully - * \retval E_CLSED Device is not opened - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid for current control command - * \retval E_SYS Control device failed, due to hardware issues, such as device is disabled - * \retval E_CTX Control device failed, due to different reasons like in transfer state - * \retval E_NOSPT Control command is not supported or not valid - */ -int32_t dw_spi_control (DEV_SPI *spi_obj, uint32_t ctrl_cmd, void *param) -{ - int32_t ercd = E_OK; - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - - /* START ERROR CHECK */ - VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr); - DW_SPI_CHECK_EXP(spi_info_ptr->opn_cnt > 0, E_CLSED); - /* END OF ERROR CHECK */ - - uint32_t val32; /** to receive unsigned int value */ - DEV_BUFFER *devbuf; - - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL *)(spi_info_ptr->spi_ctrl); - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - DEV_SPI_TRANSFER *spi_xfer = &(spi_info_ptr->xfer); - - /* check whether current device is disabled */ - if ((spi_info_ptr->status & DEV_ENABLED) == 0) { - /** When device is disabled, - * only SPI_CMD_ENA_DEV, SPI_CMD_DIS_DEV, SPI_CMD_GET_STATUS, SPI_CMD_RESET - * are available, other commands will return E_SYS - */ - if ((ctrl_cmd != SPI_CMD_ENA_DEV) && \ - (ctrl_cmd != SPI_CMD_DIS_DEV) && \ - (ctrl_cmd != SPI_CMD_GET_STATUS) && \ - (ctrl_cmd != SPI_CMD_RESET) ) { - return E_SYS; - } - } - - switch (ctrl_cmd) { - /* Commmon commands for both master and slave mode */ - case SPI_CMD_GET_STATUS: - DW_SPI_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = spi_info_ptr->status; - break; - case SPI_CMD_SET_CLK_MODE: - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - val32 = (uint32_t)param; - DW_SPI_CHECK_EXP((val32>=SPI_CPOL_0_CPHA_0) && (val32<=SPI_CPOL_1_CPHA_1), E_PAR); - if (dw_spi_set_clockmode(spi_reg_ptr, val32) == 0) { - spi_info_ptr->clk_mode = val32; - } else { - ercd = E_SYS; - } - break; - case SPI_CMD_ENA_DEV: - dw_spi_enable_device(spi_info_ptr); - break; - case SPI_CMD_DIS_DEV: - dw_spi_disable_device(spi_info_ptr); - break; - case SPI_CMD_RESET: - dw_spi_reset_device(spi_info_ptr); - break; - case SPI_CMD_FLUSH_TX: - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - dw_spi_flush_tx(spi_reg_ptr); - break; - case SPI_CMD_FLUSH_RX: - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - dw_spi_flush_rx(spi_reg_ptr); - break; - case SPI_CMD_SET_DFS: - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - val32 = (uint32_t)param; - DW_SPI_CHECK_EXP(val32>0, E_PAR); - if (dw_spi_set_dfs(spi_reg_ptr, val32) == 0) { - spi_info_ptr->dfs = val32; - } else { - ercd = E_SYS; - } - break; - case SPI_CMD_SET_DUMMY_DATA: - val32 = (uint32_t)param; - spi_info_ptr->dummy = val32; - break; - case SPI_CMD_GET_RXAVAIL: /* Notice in bytes unit */ - DW_SPI_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = dw_spi_get_rxavail(spi_ctrl_ptr) * dw_spi_nbytes(spi_info_ptr->dfs); - break; - case SPI_CMD_GET_TXAVAIL: /* Notice in bytes unit */ - DW_SPI_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = dw_spi_get_txavail(spi_ctrl_ptr) * dw_spi_nbytes(spi_info_ptr->dfs); - break; - case SPI_CMD_SET_TXCB: - DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - spi_info_ptr->spi_cbs.tx_cb = param; - break; - case SPI_CMD_SET_RXCB: - DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - spi_info_ptr->spi_cbs.rx_cb = param; - break; - case SPI_CMD_SET_XFERCB: - DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - spi_info_ptr->spi_cbs.xfer_cb = param; - break; - case SPI_CMD_SET_ERRCB: - DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - spi_info_ptr->spi_cbs.err_cb = param; - break; - case SPI_CMD_ABORT_TX: - ercd = dw_spi_abort_tx(spi_obj); - break; - case SPI_CMD_ABORT_RX: - ercd = dw_spi_abort_rx(spi_obj); - break; - case SPI_CMD_ABORT_XFER: - ercd = dw_spi_abort_xfer(spi_obj); - break; - case SPI_CMD_SET_TXINT: - val32 = (uint32_t)param; - if (val32 == 0) { - ercd = dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_SND); - } else { - ercd = dw_spi_ena_cbr(spi_info_ptr, DW_SPI_RDY_SND); - } - break; - case SPI_CMD_SET_RXINT: - val32 = (uint32_t)param; - if (val32 == 0) { - ercd = dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_RCV); - } else { - ercd = dw_spi_ena_cbr(spi_info_ptr, DW_SPI_RDY_RCV); - } - break; - case SPI_CMD_SET_TXINT_BUF: - DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - if (param != NULL) { - devbuf = (DEV_BUFFER *)param; - DEV_SPI_XFER_SET_TXBUF(spi_xfer, devbuf->buf, 0, devbuf->len); - DEV_SPI_XFER_SET_RXBUF(spi_xfer, NULL, devbuf->len, 0); - DEV_SPI_XFER_SET_NEXT(spi_xfer, NULL); - DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned(spi_xfer, spi_info_ptr->dfs) == 0, E_PAR); - dw_spi_init_transfer(spi_ctrl_ptr, spi_xfer, spi_info_ptr->dfs); - } else { - DEV_SPI_XFER_SET_TXBUF(spi_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_RXBUF(spi_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_NEXT(spi_xfer, NULL); - dw_spi_init_transfer(spi_ctrl_ptr, NULL, spi_info_ptr->dfs); - } - break; - case SPI_CMD_SET_RXINT_BUF: - DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - if (param != NULL) { - devbuf = (DEV_BUFFER *)param; - DEV_SPI_XFER_SET_TXBUF(spi_xfer, NULL, devbuf->len, 0); - DEV_SPI_XFER_SET_RXBUF(spi_xfer, devbuf->buf, 0, devbuf->len); - DEV_SPI_XFER_SET_NEXT(spi_xfer, NULL); - /* Check transfer align */ - DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned(spi_xfer, spi_info_ptr->dfs) == 0, E_PAR); - dw_spi_init_transfer(spi_ctrl_ptr, spi_xfer, spi_info_ptr->dfs); - } else { - DEV_SPI_XFER_SET_TXBUF(spi_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_RXBUF(spi_xfer, NULL, 0, 0); - DEV_SPI_XFER_SET_NEXT(spi_xfer, NULL); - dw_spi_init_transfer(spi_ctrl_ptr, NULL, spi_info_ptr->dfs); - } - break; - case SPI_CMD_TRANSFER_POLLING: - DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - if (param != NULL) { - /* Check transfer align */ - DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned((DEV_SPI_TRANSFER *)param, spi_info_ptr->dfs) == 0, E_PAR); - *spi_xfer = *((DEV_SPI_TRANSFER *)param); - dw_spi_init_transfer(spi_ctrl_ptr, spi_xfer, spi_info_ptr->dfs); - /* Transfer data by poll */ - dw_spi_poll_transfer(spi_info_ptr); - } else { - ercd = E_PAR; - } - break; - case SPI_CMD_TRANSFER_INT: - DW_SPI_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - if (param != NULL) { - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - /* Check transfer align */ - DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned((DEV_SPI_TRANSFER *)param, spi_info_ptr->dfs) == 0, E_PAR); - *spi_xfer = *((DEV_SPI_TRANSFER *)param); - dw_spi_init_transfer(spi_ctrl_ptr, spi_xfer, spi_info_ptr->dfs); - /* Transfer data by interrupt */ - ercd = dw_spi_ena_cbr(spi_info_ptr, DW_SPI_RDY_XFER); - } else { - ercd = dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_XFER); - } - break; - - /* Master mode only commands */ - case SPI_CMD_MST_SET_FREQ: - DW_SPI_CHECK_EXP(spi_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - val32 = (uint32_t)param; - DW_SPI_CHECK_EXP(val32>0, E_PAR); - dw_spi_set_freq(spi_ctrl_ptr, val32); - spi_info_ptr->freq = val32; - break; - case SPI_CMD_MST_SEL_DEV: - DW_SPI_CHECK_EXP(spi_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - val32 = (uint32_t)param; - if (dw_spi_select_slave(spi_reg_ptr, val32) == 0) { - spi_info_ptr->slave = val32; - } else { - ercd = E_SYS; - } - break; - case SPI_CMD_MST_DSEL_DEV: - DW_SPI_CHECK_EXP(spi_info_ptr->mode == DEV_MASTER_MODE, E_NOSPT); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - val32 = (uint32_t)param; - if (dw_spi_deselect_slave(spi_reg_ptr, val32) == 0) { - spi_info_ptr->slave = SPI_SLAVE_NOT_SELECTED; - } else { - ercd = E_SYS; - } - break; - - /* Slave mode only commands */ - - - default: - ercd = E_NOSPT; - break; - } - -error_exit: - return ercd; -} - -/** - * \brief send data through DesignWare SPI - * \param[in] spi_obj spi object pointer - * \param[in] data pointer to data need to send by spi - * \param[in] len length of data to be sent - * \retval >0 Byte count that was successfully sent for poll method - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid - * \retval E_CTX Device is still in transfer state - * \retval E_SYS Can't write data to hardware due to hardware issues, such as device is disabled - */ -int32_t dw_spi_write (DEV_SPI *spi_obj, const void *data, uint32_t len) -{ - int32_t ercd = E_OK; - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - - /* START ERROR CHECK */ - VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr); - DW_SPI_CHECK_EXP(spi_info_ptr->opn_cnt > 0, E_CLSED); - DW_SPI_CHECK_EXP(spi_info_ptr->status & DEV_ENABLED, E_SYS); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - DW_SPI_CHECK_EXP(data!=NULL, E_PAR); - DW_SPI_CHECK_EXP(len>0, E_PAR); - /* END OF ERROR CHECK */ - - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl); - DEV_SPI_TRANSFER spi_xfer; - - /* Master and Slave transmit */ - DEV_SPI_XFER_SET_TXBUF(&spi_xfer, data, 0, len); - DEV_SPI_XFER_SET_RXBUF(&spi_xfer, NULL, len, 0); - DEV_SPI_XFER_SET_NEXT(&spi_xfer, NULL); - - /* Check transfer align */ - DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned(&spi_xfer, spi_info_ptr->dfs) == 0, E_PAR); - - dw_spi_init_transfer(spi_ctrl_ptr, &spi_xfer, spi_info_ptr->dfs); - - ercd = dw_spi_poll_transfer(spi_info_ptr); - -error_exit: - return ercd; -} - -/** - * \brief read data through DesignWare SPI - * \param[in] spi_info_ptr spi information structure pointer - * \param[out] data data that need to read (data must be char type) - * \param[in] len data count need to read - * \retval >=0 data have been read - * \retval E_PAR arguments passed was wrong - * \retval E_OBJ spi has something error, nothing can be done - * \retval E_CLSED spi was closed, not available for control - * \retval <0 other error code not defined here - */ -int32_t dw_spi_read (DEV_SPI *spi_obj, void *data, uint32_t len) -{ - int32_t ercd = E_OK; - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - - /* START ERROR CHECK */ - VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr); - DW_SPI_CHECK_EXP(spi_info_ptr->opn_cnt > 0, E_CLSED); - DW_SPI_CHECK_EXP(spi_info_ptr->status & DEV_ENABLED, E_SYS); - DW_SPI_CHECK_EXP((spi_info_ptr->status & DEV_IN_XFER) == 0, E_CTX); - DW_SPI_CHECK_EXP(data!=NULL, E_PAR); - DW_SPI_CHECK_EXP(len>0, E_PAR); - /* END OF ERROR CHECK */ - - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl); - DEV_SPI_TRANSFER spi_xfer; - - /* Master and Slave transmit */ - DEV_SPI_XFER_SET_TXBUF(&spi_xfer, NULL, len, 0); - DEV_SPI_XFER_SET_RXBUF(&spi_xfer, data, 0, len); - DEV_SPI_XFER_SET_NEXT(&spi_xfer, NULL); - - /* Check transfer align */ - DW_SPI_CHECK_EXP(dw_spi_chk_xfer_aligned(&spi_xfer, spi_info_ptr->dfs) == 0, E_PAR); - - dw_spi_init_transfer(spi_ctrl_ptr, &spi_xfer, spi_info_ptr->dfs); - - ercd = dw_spi_poll_transfer(spi_info_ptr); - -error_exit: - return ercd; -} - -/** - * \brief DesignWare SPI interrupt processing routine - * \param[in] spi_info_ptr DEV_SPI_INFO *spi_info_ptr - * \param[in] ptr extra information - */ -void dw_spi_isr(DEV_SPI *spi_obj, void *ptr) -{ - int32_t ercd = E_OK; - DEV_SPI_INFO *spi_info_ptr = &(spi_obj->spi_info); - - /* START ERROR CHECK */ - VALID_CHK_SPI_INFO_OBJECT(spi_info_ptr); - /* END OF ERROR CHECK */ - - DW_SPI_CTRL *spi_ctrl_ptr = (DW_SPI_CTRL_PTR)(spi_info_ptr->spi_ctrl); - DW_SPI_REG *spi_reg_ptr = (DW_SPI_REG *)(spi_ctrl_ptr->dw_spi_regs); - - uint32_t isr_status; - - isr_status = spi_reg_ptr->ISR; - - if (!isr_status) return; - if (spi_ctrl_ptr->dw_xfer.xfer_len == 0) { - dw_spi_disable_interrupt(spi_info_ptr); - } else { - if (isr_status & (DW_SPI_IMR_TXOIM|DW_SPI_IMR_RXOIM|DW_SPI_IMR_RXUIM)) { - dw_spi_clear_interrupt_all(spi_reg_ptr); - dw_spi_disable_interrupt(spi_info_ptr); - if (spi_info_ptr->spi_cbs.err_cb) { - spi_info_ptr->spi_cbs.err_cb(spi_obj); - } - memset(&(spi_ctrl_ptr->dw_xfer), 0, sizeof(DW_SPI_TRANSFER)); - } - dw_spi_reader(spi_info_ptr); - if (isr_status & DW_SPI_IMR_TXEIM) { - dw_spi_writer(spi_info_ptr); - } - if (dw_spi_xfer_end(spi_ctrl_ptr)) { - if ((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_TX) { - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_SND); - if (spi_info_ptr->spi_cbs.tx_cb) { - spi_info_ptr->spi_cbs.tx_cb(spi_obj); - } - } else if ((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_RX) { - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_RCV); - if (spi_info_ptr->spi_cbs.rx_cb) { - spi_info_ptr->spi_cbs.rx_cb(spi_obj); - } - } else if ((spi_info_ptr->status & DW_SPI_IN_XFER) == DW_SPI_IN_XFER) { - dw_spi_dis_cbr(spi_info_ptr, DW_SPI_RDY_XFER); - if (spi_info_ptr->spi_cbs.xfer_cb) { - spi_info_ptr->spi_cbs.xfer_cb(spi_obj); - } - } else { - dw_spi_disable_interrupt(spi_info_ptr); - } - memset(&(spi_ctrl_ptr->dw_xfer), 0, sizeof(DW_SPI_TRANSFER)); - } - } - -error_exit: - return; -} -/** @} */ /* DEVICE_DW_SPI_IMPLEMENT */ - -/** @} */ /* DEVICE_DW_SPI */ diff --git a/bsp/synopsys/embarc/device/designware/spi/dw_spi.h b/bsp/synopsys/embarc/device/designware/spi/dw_spi.h deleted file mode 100644 index ef2faa90e60af39ad8ffd475a15a0f46d420edd2..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/device/designware/spi/dw_spi.h +++ /dev/null @@ -1,190 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2017.03 - * \date 2014-06-25 - * \author Huaqi Fang(Huaqi.Fang@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \brief DesignWare SPI driver header file - * \ingroup DEVICE_DW_SPI - */ - -#ifndef _DEVICE_DW_SPI_H_ -#define _DEVICE_DW_SPI_H_ - -#include "device/device_hal/inc/dev_spi.h" - -/** - * if this header file is included, - * will indicate that this designware spi device - * is used - */ -#define DEVICE_USE_DESIGNWARE_SPI - -#define DW_SPI_IN_FREE (0) /*!< Currently not in spi transfer */ -#define DW_SPI_IN_XFER (DEV_IN_TX|DEV_IN_RX|DEV_IN_XFER) /*!< Currently in spi transfer */ -#define DW_SPI_IN_TX (DEV_IN_TX|DEV_IN_XFER) /*!< Currently in spi tx */ -#define DW_SPI_IN_RX (DEV_IN_RX|DEV_IN_XFER) /*!< Currently in spi rx */ - -#define DW_SPI_GINT_DISABLED (0) /*!< designware interrupt disabled for control iic irq/fiq */ -#define DW_SPI_GINT_ENABLE (1<<0) /*!< designware interrupt enabled for control iic irq/fiq */ - -#define DW_SPI_MASTER_SUPPORTED (0x1) /*!< Support Designware SPI Master Mode */ -#define DW_SPI_SLAVE_SUPPORTED (0x2) /*!< Support Designware SPI Slave Mode */ -/*!< Support Designware SPI Both Master and Slave Mode */ -#define DW_SPI_BOTH_SUPPORTED (DW_SPI_MASTER_SUPPORTED|DW_SPI_SLAVE_SUPPORTED) - -/** - * \defgroup DEVICE_DW_SPI_REGSTRUCT DesignWare SPI Register Structure - * \ingroup DEVICE_DW_SPI - * \brief contains definitions of DesignWare SPI register structure. - * \details detailed description of DesignWare SPI register information - * @{ - */ -/** - * \brief DesignWare SPI register structure - * \details Detailed struct description of DesignWare SPI - * block register information, implementation of dev_spi_info::spi_regs - */ -typedef volatile struct dw_spi_reg -{ - /*!< Control Register */ - /*!< SPI Control Register 0 (0x0) */ - uint32_t CTRLR0; - /*!< SPI Control Register 1 (0x4) */ - uint32_t CTRLR1; - /*!< Enable Register */ - /*!< SPI Enable Register (0x8) */ - uint32_t SSIENR; - /*!< SPI Microwire Control Register (0xC) */ - uint32_t MWCR; - /*!< SPI Slave Enable Register (0x10) */ - uint32_t SER; - /*!< SPI Baud Rate Select Register (0x14) */ - uint32_t BAUDR; - /*!< TX and RX FIFO Control Register */ - /*!< SPI Transmit FIFO Threshold Level Register (0x18) */ - uint32_t TXFTLR; - /*!< SPI Receive FIFO Threshold Level Register (0x1C) */ - uint32_t RXFTLR; - /*!< SPI Transmit FIFO Level Register (0x20) */ - uint32_t TXFLR; - /*!< SPI Receive FIFO Level Register (0x24) */ - uint32_t RXFLR; - /*!< SPI Status Register (0x28) */ - uint32_t SR; - /*!< Interrupt Enable/Disable/Control Registers */ - /*!< SPI Interrupt Mask Register (0x2C) */ - uint32_t IMR; - /*!< SPI Interrupt Status Register (0x30) */ - uint32_t ISR; - /*!< SPI Raw Interrupt Status Register (0x34) */ - uint32_t RISR; - /*!< SPI Transmit FIFO Overflow Interrupt Clear Register (0x38) */ - uint32_t TXOICR; - /*!< SPI Receive FIFO Overflow Interrupt Clear Register (0x3C) */ - uint32_t RXOICR; - /*!< SPI Receive FIFO Underflow Interrupt Clear Register (0x40) */ - uint32_t RXUICR; - /*!< SPI Multi-Master Interrupt Clear Register (0x44) */ - uint32_t MSTICR; - /*!< SPI Interrupt Clear Register (0x48) */ - uint32_t ICR; - /*!< DMA Control Register (0x4C) */ - uint32_t DMACR; - /*!< DMA Transmit Data Level (0x50) */ - uint32_t DMATDLR; - /*!< DMA Receive Data Level (0x54) */ - uint32_t DMARDLR; - /*!< SPI Identification Register (0x58) */ - uint32_t IDR; - /*!< SPI CoreKit ID Register (Value after Reset : 0x3332322A) (0x5C) */ - uint32_t SSI_VER_ID; - /*!< Data Register */ - /*!< SPI DATA Register for both Read and Write (0x60) */ - uint32_t DATAREG; -} DW_SPI_REG, *DW_SPI_REG_PTR; -/** @} */ - -/** Designware SPI Message Transfer */ -typedef struct dw_spi_transfer { - uint32_t xfer_len; - uint32_t tx_idx; - uint32_t rx_idx; - uint32_t nbytes; - DEV_SPI_TRANSFER *tx_xfer; - DEV_SPI_TRANSFER *rx_xfer; -} DW_SPI_TRANSFER, *DW_SPI_TRANSFER_PTR; - -/** - * \brief DesignWare SPI control structure definition - * \details implement of dev_spi_info::dev_spi_info - */ -typedef struct dw_spi_ctrl { - DW_SPI_REG *dw_spi_regs; /*!< spi register */ - /* Variables which should be set during object implementation */ - uint32_t support_modes; /*!< supported spi modes */ - uint32_t intno; /*!< interrupt no */ - uint32_t dw_apb_bus_freq; /*!< spi ip apb bus frequency */ - uint32_t tx_fifo_len; /*!< transmit fifo length */ - uint32_t rx_fifo_len; /*!< receive fifo length */ - INT_HANDLER dw_spi_int_handler; /*!< spi interrupt handler */ - /* Variables which always change during iic operation */ - uint32_t int_status; /*!< iic interrupt status */ - DW_SPI_TRANSFER dw_xfer; /*!< designware spi transfer */ -} DW_SPI_CTRL, *DW_SPI_CTRL_PTR; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup DEVICE_DW_SPI_FUNCDLR DesignWare SPI Function Declaration - * \ingroup DEVICE_DW_SPI - * \brief contains declarations of designware spi functions. - * \details This are only used in \ref dw_spi_obj.c - * @{ - */ -extern int32_t dw_spi_open (DEV_SPI *spi_obj, uint32_t mode, uint32_t param); -extern int32_t dw_spi_close (DEV_SPI *spi_obj); -extern int32_t dw_spi_control (DEV_SPI *spi_obj, uint32_t ctrl_cmd, void *param); -extern int32_t dw_spi_write (DEV_SPI *spi_obj, const void *data, uint32_t len); -extern int32_t dw_spi_read (DEV_SPI *spi_obj, void *data, uint32_t len); -extern void dw_spi_isr(DEV_SPI *spi_obj, void *ptr); -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif /* _DEVICE_DW_SPI_H_ */ diff --git a/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal.h b/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal.h deleted file mode 100644 index b1a233c6996288db0fe9b9ace7741dae0af21415..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal.h +++ /dev/null @@ -1,141 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2017.03 - * \date 2014-06-25 - * \author Huaqi Fang(Huaqi.Fang@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup DEVICE_DW_SPI - * \brief DesignWare SPI driver hardware description related header file - * \details detailed hardware related definitions of DesignWare SPI driver - */ - -#ifndef _DEVICE_DW_SPI_HAL_H_ -#define _DEVICE_DW_SPI_HAL_H_ - -#include "device/designware/spi/dw_spi_hal_cfg.h" - -/* DW APB SPI bit definitions */ - -/** - * \name DesignWare SPI HAL CTRL0 Macros - * \brief DesignWare SPI hal ctrl0 macros, - * include dfs, scph, scppl, tmod, etc - * @{ - */ -#define DW_SPI_CTRLR0_DFS_MASK (0xf) - -#define DW_SPI_CTRLR0_SC_OFS (6) -#define DW_SPI_CTRLR0_SC_MASK (0xC0) -#define DW_SPI_CTRLR0_SCPH_HIGH (0x40) -#define DW_SPI_CTRLR0_SCPH_LOW (0) -#define DW_SPI_CTRLR0_SCPOL_HIGH (0x80) -#define DW_SPI_CTRLR0_SCPOL_LOW (0) - -#define DW_SPI_CTRLR0_TMOD_MASK (0x300) -#define DW_SPI_TMOD_TRANSMIT_RECEIVE (0) -#define DW_SPI_TMOD_TRANSMIT_ONLY (0x100) -#define DW_SPI_TMOD_RECEIVE_ONLY (0x200) -#define DW_SPI_TMOD_EEPROM_READ_ONLY (0x300) - -#define DW_SPI_CTRLR0_FRF_MOTOROLA (0x0) -#define DW_SPI_CTRLR0_FRF_TI (0x10) -#define DW_SPI_CTRLR0_FRF_MICROWIRE (0x20) - -#define DW_SPI_CTRLR0_SLV_OE_DISABLE (1<<10) -#define DW_SPI_CTRLR0_SLV_OE_ENABLE (0) - - -/** @} */ - -/** - * \name DesignWare SPI HAL ISR Flags - * \brief DesignWare SPI hal Interrupt Status Flags - * @{ - */ -#define DW_SPI_TX_OVERFLOW_ERROR (0x2) -#define DW_SPI_RX_UNDERFLOW_ERROR (0x4) -#define DW_SPI_RX_OVERFLOW_ERROR (0x8) - -#define DW_SPI_ISR_RX_FIFO_INT_MASK (0x10) -#define DW_SPI_ISR_TX_FIFO_INT_MASK (0x1) -#define DW_SPI_ISR_TX_OVERFLOW_INT_MASK (0x2) -#define DW_SPI_ISR_RX_UNDERFLOW_INT_MASK (0x4) -#define DW_SPI_ISR_RX_OVERFLOW_INT_MASK (0x8) -/** @} */ - -/** - * \name DesignWare SPI HAL SR Flags - * \brief DesignWare SPI hal Status Flags - * @{ - */ -#define DW_SPI_SR_DCOL (0x40) -#define DW_SPI_SR_TXE (0x20) -#define DW_SPI_SR_RFF (0x10) -#define DW_SPI_SR_RFNE (0x8) -#define DW_SPI_SR_TFE (0x4) -#define DW_SPI_SR_TFNF (0x2) -#define DW_SPI_SR_BUSY (0x1) -/** @} */ - -/** - * \name DesignWare SPI HAL SSI Enable Macros - * \brief DesignWare SPI hal ssi enable macros - * @{ - */ -/* Macros */ -#define DW_SPI_SSI_ENABLE (1) /*!< SSI Enable */ -#define DW_SPI_SSI_DISABLE (0) /*!< SSI Disable */ -/** @} */ - -/** - * \name DesignWare SPI HAL IMR Macros - * \brief DesignWare SPI hal interrupt mask macros - * @{ - */ -#define DW_SPI_IMR_MSTIM (0x20) /*!< Multi-Master Contention Interrupt Mask */ -#define DW_SPI_IMR_RXFIM (0x10) /*!< Receive FIFO Full Interrupt Mask */ -#define DW_SPI_IMR_RXOIM (0x08) /*!< Receive FIFO Overflow Interrupt Mask */ -#define DW_SPI_IMR_RXUIM (0x04) /*!< Receive FIFO Underflow Interrupt Mask */ -#define DW_SPI_IMR_TXOIM (0x02) /*!< Transmit FIFO Overflow Interrupt Mask */ -#define DW_SPI_IMR_TXEIM (0x01) /*!< Transmit FIFO Empty Interrupt Mask */ - -#define DW_SPI_IMR_XFER (DW_SPI_IMR_TXEIM|DW_SPI_IMR_RXFIM|DW_SPI_IMR_TXOIM|DW_SPI_IMR_RXOIM|DW_SPI_IMR_RXUIM) -/** @} */ - -#define DW_SPI_SSI_IDLE (1) -#define DW_SPI_SPI_TRANSMIT (1) -#define DW_SPI_SPI_RECEIVE (2) -#define DW_SPI_SSI_MASTER (1) -#define DW_SPI_SSI_SLAVE (0) - - -#endif /* _DEVICE_DW_SPI_HAL_H_ */ diff --git a/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal_cfg.h b/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal_cfg.h deleted file mode 100644 index d6caf71466ae2e09fd1cb2209fd28e8e7ede9815..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/device/designware/spi/dw_spi_hal_cfg.h +++ /dev/null @@ -1,58 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2017.03 - * \date 2015-09-09 - * \author Huaqi Fang(Huaqi.Fang@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup DEVICE_DW_SPI - * \brief DesignWare SPI driver hardware description - * related header file configuration file - * \details configuration file to enable or disable some function of spi - */ - -#ifndef _DEVICE_DW_SPI_HAL_CFG_H_ -#define _DEVICE_DW_SPI_HAL_CFG_H_ - -#ifndef DW_SPI_CALC_FIFO_LEN_ENABLE -#define DW_SPI_CALC_FIFO_LEN_ENABLE (1) /*!< Defaultly enable calculate fifo length */ -#endif - -#ifndef DW_SPI_MAX_FIFO_LENGTH -#define DW_SPI_MAX_FIFO_LENGTH (256) /*!< Max FIFO depth for designware SPI device */ -#endif - -#ifndef DW_SPI_MIN_FIFO_LENGTH -#define DW_SPI_MIN_FIFO_LENGTH (2) /*!< Min FIFO depth for designware SPI device */ -#endif - -#endif /* _DEVICE_DW_SPI_HAL_CFG_H_ */ - diff --git a/bsp/synopsys/embarc/device/designware/uart/dw_uart.c b/bsp/synopsys/embarc/device/designware/uart/dw_uart.c deleted file mode 100644 index 999ee751e075cc225444e50911fc259aa5fddd83..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/device/designware/uart/dw_uart.c +++ /dev/null @@ -1,956 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-06-20 - * \author Huaqi Fang(Huaqi.Fang@synopsys.com) ---------------------------------------------- */ - -/** - * \defgroup DEVICE_DW_UART Designware UART Driver - * \ingroup DEVICE_DW - * \brief Designware UART Driver Implementation - */ - -/** - * \file - * \ingroup DEVICE_DW_UART - * \brief DesignWare UART driver implementation based on device hal layer definition (\ref dev_uart.h) - */ -#include - -#include "inc/embARC_toolchain.h" -#include "inc/embARC_error.h" - -#include "inc/arc/arc_exception.h" - -#include "device/designware/uart/dw_uart_hal.h" -#include "device/designware/uart/dw_uart.h" - - -/** - * \name DesignWare UART Driver Macros - * \brief DesignWare UART driver macros used in uart driver - * @{ - */ -/** check expressions used in DesignWare UART driver implementation */ -#define DW_UART_CHECK_EXP(EXPR, ERROR_CODE) CHECK_EXP(EXPR, ercd, ERROR_CODE, error_exit) - -#ifndef DISABLE_DEVICE_OBJECT_VALID_CHECK -/** valid check of uart info object */ -#define VALID_CHK_UART_INFO_OBJECT(uartinfo_obj_ptr) { \ - DW_UART_CHECK_EXP((uartinfo_obj_ptr)!=NULL, E_OBJ); \ - DW_UART_CHECK_EXP(((uartinfo_obj_ptr)->uart_ctrl)!=NULL, E_OBJ); \ - } -#endif - -/** convert DesignWare baudrate to divisor */ -#define DW_UART_BAUD2DIV(perifreq, baud) ((perifreq) / ((baud)*16)) - -/** - * \name DesignWare UART Interrupt Callback Routine Select Marcos - * \brief DesignWare UART interrupt callback routines select macros definitions - * @{ - */ -#define DW_UART_RDY_SND (1U) /*!< ready to send callback */ -#define DW_UART_RDY_RCV (2U) /*!< ready to receive callback */ -/** @} */ - -/** @} */ - -/** - * \defgroup DEVICE_DW_UART_STATIC DesignWare UART Driver Static Functions - * \ingroup DEVICE_DW_UART - * \brief Static or inline functions, variables for DesignWare UART handle uart operations, - * only used in this file - * @{ - */ -const uint8_t dw_uart_databits[] = { \ - DW_UART_LCR_WORD_LEN5, DW_UART_LCR_WORD_LEN6, \ - DW_UART_LCR_WORD_LEN7, DW_UART_LCR_WORD_LEN8}; -const uint8_t dw_uart_parity[] = { - DW_UART_LCR_PARITY_NONE, DW_UART_LCR_PARITY_ODD, - DW_UART_LCR_PARITY_EVEN, DW_UART_LCR_PARITY_MASK, - DW_UART_LCR_PARITY_SPACE -}; -const uint8_t dw_uart_stopbits[] = { - DW_UART_LCR_1_STOP_BIT, DW_UART_LCR_1D5_STOP_BIT, - DW_UART_LCR_2_STOP_BIT -}; - -/** test whether uart is ready to send, 1 ready, 0 not ready */ -Inline int32_t dw_uart_putready(DW_UART_REG *uart_reg_ptr) -{ - return ((uart_reg_ptr->USR & DW_UART_USR_TFNF) != 0); -} -/** test whether uart is ready to receive, 1 ready, 0 not ready */ -Inline int32_t dw_uart_getready(DW_UART_REG *uart_reg_ptr) -{ - return ((uart_reg_ptr->USR & DW_UART_USR_RFNE) != 0); -} -/** write char to uart send fifo */ -Inline void dw_uart_putchar(DW_UART_REG *uart_reg_ptr, char chr) -{ - uart_reg_ptr->DATA = chr; -} -/** read data from uart receive fifo, return data received */ -Inline int32_t dw_uart_getchar(DW_UART_REG *uart_reg_ptr) -{ - return (int32_t)uart_reg_ptr->DATA; -} -/** - * \brief send char by uart when available, - * mostly used in interrupt method, non-blocked function - * \param[in] uart_reg_ptr uart register structure pointer - * \param[in] chr char to be sent - * \retval 0 send successfully - * \retval -1 not ready to send data - */ -Inline int32_t dw_uart_snd_chr(DW_UART_REG *uart_reg_ptr, char chr) -{ - if (dw_uart_putready(uart_reg_ptr)) { - dw_uart_putchar(uart_reg_ptr, chr); - return 0; - } - return -1; -} -/** - * \brief receive one char from uart, - * mostly used in interrupt routine, non-blocked function - * \param[in] uart_reg_ptr uart register structure pointer - * \return data received by the uart - */ -Inline int32_t dw_uart_rcv_chr(DW_UART_REG *uart_reg_ptr) -{ - return dw_uart_getchar(uart_reg_ptr); -} -/** - * \brief send char by uart in poll method, blocked function - * \param[in] uart_reg_ptr uart register structure pointer - * \param[in] chr char to be sent - */ -Inline void dw_uart_psnd_chr(DW_UART_REG *uart_reg_ptr, char chr) -{ - /** wait until uart is ready to send */ - while (!dw_uart_putready(uart_reg_ptr)); /* blocked */ - /** send char */ - dw_uart_putchar(uart_reg_ptr, chr); -} -/** - * \brief receive one char from uart in poll method, blocked function - * \param[in] uart_reg_ptr uart register structure pointer - * \return data received by the uart - */ -Inline int32_t dw_uart_prcv_chr(DW_UART_REG *uart_reg_ptr) -{ - /** wait until uart is ready to receive */ - while (!dw_uart_getready(uart_reg_ptr)); /* blocked */ - /** receive data */ - return dw_uart_getchar(uart_reg_ptr); -} - -/** Get TX FIFO Length */ -Inline uint32_t dw_uart_get_txfifo_len(DW_UART_REG *uart_reg_ptr) -{ - uint32_t txfifolen; - uint32_t uart_cpr; - - uart_cpr = uart_reg_ptr->CPR; - if (uart_cpr & DW_UART_CPR_FIFO_STAT) { - txfifolen = ((uart_cpr & DW_UART_CPR_FIFO_MODE) >> DW_UART_CPR_FIFO_MODE_OFS) << 4; - } else { - txfifolen = 0; - } - - return txfifolen; -} - -/** Get RX FIFO Length */ -Inline uint32_t dw_uart_get_rxfifo_len(DW_UART_REG *uart_reg_ptr) -{ - uint32_t rxfifolen; - uint32_t uart_cpr; - - uart_cpr = uart_reg_ptr->CPR; - if (uart_cpr & DW_UART_CPR_FIFO_STAT) { - rxfifolen = ((uart_cpr & DW_UART_CPR_FIFO_MODE) >> DW_UART_CPR_FIFO_MODE_OFS) << 4; - } else { - rxfifolen = 0; - } - - return rxfifolen; -} - -/** - * \brief set designware uart DPS value - * \param uart_reg_ptr uart register structure - * \param dps data bits/parity bit/stop bits parameter - * \retval 0 Set ok - * \retval !0 Set failed - */ -static int32_t dw_uart_set_dps(DW_UART_REG *uart_reg_ptr, UART_DPS_FORMAT *dps) -{ - uint32_t dps_value = 0; - - if (dps == NULL) return -1; - /* data bits check */ - if ((dps->databits < 5) || (dps->databits > 8)) return -1; - /* stop bits check */ - if (dps->stopbits > UART_STPBITS_TWO) return -1; - /* parity bit type check */ - if (dps->parity > UART_PARITY_SPACE) return -1; - - dps_value |= (uint32_t)dw_uart_databits[dps->databits-5]; - dps_value |= (uint32_t)dw_uart_stopbits[dps->stopbits]; - dps_value |= (uint32_t)dw_uart_parity[dps->parity]; - - /* clear dps bits */ - uart_reg_ptr->LCR &= (~DW_UART_LCR_DPS_MASK); - /* set dps bits */ - uart_reg_ptr->LCR |= dps_value; - - return 0; -} - -/** - * \brief set designware uart baudrate - * \param uart_reg_ptr uart register structure - * \param baud_divisor uart baudrate divisor - */ -static void dw_uart_set_baud(DW_UART_REG *uart_reg_ptr, uint32_t baud_divisor) -{ - /* enable uart baudrate update */ - uart_reg_ptr->LCR |= DW_UART_LCR_DLAB; - /** - * setting uart baudrate registers - */ - uart_reg_ptr->DATA = baud_divisor & 0xff; /*!< DLL */ - uart_reg_ptr->IER = (baud_divisor>>8) & 0xff; /*!< DLH */ - /** disable DLAB */ - uart_reg_ptr->LCR &= ~(DW_UART_LCR_DLAB); -} - -/** - * \brief Do uart software reset - * \param uart_reg_ptr uart register structure - */ -Inline void dw_uart_software_reset(DW_UART_REG *uart_reg_ptr) -{ - uart_reg_ptr->SRR = DW_UART_SRR_UR|DW_UART_SRR_RFR|DW_UART_SRR_XFR; - while(uart_reg_ptr->USR & DW_UART_USR_BUSY); /* wait until software reset completed */ -} - -/** - * \brief set designware uart baudrate - * \param uart_reg_ptr uart register structure - * \param hwfc uart hardware flow control type - * \note Need to set corresponding pin functions - */ -static void dw_uart_set_hwfc(DW_UART_REG *uart_reg_ptr, UART_HW_FLOW_CONTROL hwfc) -{ - if (hwfc == UART_FC_NONE) { - uart_reg_ptr->MCR &= ~(DW_UART_MCR_AFCE|DW_UART_MCR_RTS); - } - if ((hwfc == UART_FC_RTS) || (hwfc == UART_FC_BOTH)) { - uart_reg_ptr->MCR |= (DW_UART_MCR_AFCE|DW_UART_MCR_RTS); - } - if ((hwfc == UART_FC_CTS) || (hwfc == UART_FC_BOTH)) { - uart_reg_ptr->MCR |= (DW_UART_MCR_AFCE); - } -} - -Inline void dw_uart_set_break(DW_UART_REG *uart_reg_ptr) -{ - uart_reg_ptr->LCR |= DW_UART_LCR_BREAK; -} - -Inline void dw_uart_clr_break(DW_UART_REG *uart_reg_ptr) -{ - uart_reg_ptr->LCR &= ~DW_UART_LCR_BREAK; -} - -/** - * \brief init designware uart with selected baud - * \param[in] uart_reg_ptr uart register structure pointer - * \param[in] baud_divisor baudrate divisor - */ -static void dw_uart_init(DW_UART_REG *uart_reg_ptr, uint32_t baud_divisor, UART_DPS_FORMAT *dps, UART_HW_FLOW_CONTROL hwfc) -{ - dw_uart_software_reset(uart_reg_ptr); - - dw_uart_set_hwfc(uart_reg_ptr, hwfc); - dw_uart_set_dps(uart_reg_ptr, dps); - dw_uart_set_baud(uart_reg_ptr, baud_divisor); - - uart_reg_ptr->IIR = 0x1; /** enable uart fifo (FCR IIR is the same) */ - uart_reg_ptr->IER = 0x0; /** disable all uart interrupt */ -} - -/** - * \brief set designware uart baudrate - * \param uart_info_ptr uart information structure pointer - */ -static void dw_uart_flush_output(DEV_UART_INFO *uart_info_ptr) -{ - uint32_t i; - char *p_charbuf; - - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - if (uart_info_ptr->tx_buf.buf != NULL) { - p_charbuf = (char *)(uart_info_ptr->tx_buf.buf); - for (i = uart_info_ptr->tx_buf.ofs; i < uart_info_ptr->tx_buf.len; i ++) { - dw_uart_psnd_chr(uart_reg_ptr, p_charbuf[i]); - } - /* clear transmit buffer */ - uart_info_ptr->tx_buf.buf = NULL; - uart_info_ptr->tx_buf.len = 0; - uart_info_ptr->tx_buf.ofs = 0; - } - /* wait until transmit fifo is empty */ - while ((uart_reg_ptr->USR & DW_UART_USR_TFE) == 0); - while (uart_reg_ptr->USR & DW_UART_USR_BUSY); -} - -/** - * \brief disable designware uart send or receive interrupt - * \param[in] DEV_UART_INFO *uart_info_ptr - * \param[in] cbrtn control code of callback routine of send or receive - */ -static void dw_uart_dis_cbr(DEV_UART_INFO *uart_info_ptr, uint32_t cbrtn) -{ - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - switch (cbrtn) { - case DW_UART_RDY_SND: - uart_reg_ptr->IER &= ~DW_UART_IER_XMIT_EMPTY; - uart_ctrl_ptr->int_status &= ~DW_UART_TXINT_ENABLE; - break; - case DW_UART_RDY_RCV: - uart_reg_ptr->IER &= ~DW_UART_IER_DATA_AVAIL; - uart_ctrl_ptr->int_status &= ~DW_UART_RXINT_ENABLE; - break; - default: - break; - } - if (uart_ctrl_ptr->int_status & DW_UART_GINT_ENABLE) { - if ((uart_ctrl_ptr->int_status & (DW_UART_RXINT_ENABLE|DW_UART_TXINT_ENABLE)) == 0) { - int_disable(uart_ctrl_ptr->intno); - uart_ctrl_ptr->int_status &= ~DW_UART_GINT_ENABLE; - } - } -} - -/** - * \brief enable DesignWare UART send or receive interrupt - * \param[in] DEV_UART_INFO *uart_info_ptr - * \param[in] cbrtn control code of callback routine of send or receive - */ -static void dw_uart_ena_cbr(DEV_UART_INFO *uart_info_ptr, uint32_t cbrtn) -{ - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - switch (cbrtn) { - case DW_UART_RDY_SND: - uart_ctrl_ptr->int_status |= DW_UART_TXINT_ENABLE; - uart_reg_ptr->IER |= DW_UART_IER_XMIT_EMPTY; - break; - case DW_UART_RDY_RCV: - uart_ctrl_ptr->int_status |= DW_UART_RXINT_ENABLE; - uart_reg_ptr->IER |= DW_UART_IER_DATA_AVAIL; - break; - default: - break; - } - if ((uart_ctrl_ptr->int_status & DW_UART_GINT_ENABLE) == 0) { - if (uart_ctrl_ptr->int_status & (DW_UART_RXINT_ENABLE|DW_UART_TXINT_ENABLE)) { - uart_ctrl_ptr->int_status |= DW_UART_GINT_ENABLE; - int_enable(uart_ctrl_ptr->intno); - } - } -} - -/** - * \brief enable designware uart interrupt - * \param uart_info_ptr uart information structure pointer - */ -static void dw_uart_enable_interrupt(DEV_UART_INFO *uart_info_ptr) -{ - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - - int_handler_install(uart_ctrl_ptr->intno, uart_ctrl_ptr->dw_uart_int_handler); - uart_ctrl_ptr->int_status |= DW_UART_GINT_ENABLE; - int_enable(uart_ctrl_ptr->intno); /** enable uart interrupt */ -} -/** - * \brief disable designware uart interrupt - * \param uart_info_ptr uart information structure pointer - */ -static void dw_uart_disable_interrupt(DEV_UART_INFO *uart_info_ptr) -{ - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - - /** disable uart send&receive interrupt after disable uart interrupt */ - dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_SND); - dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_RCV); - /* disable uart interrupt */ - int_disable(uart_ctrl_ptr->intno); - uart_ctrl_ptr->int_status &= ~(DW_UART_GINT_ENABLE|DW_UART_TXINT_ENABLE|DW_UART_RXINT_ENABLE); -} - -/** enable designware uart */ -static void dw_uart_enable_device(DEV_UART_INFO *uart_info_ptr) -{ - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - if ((uart_info_ptr->status & DEV_ENABLED) == 0) { - dw_uart_set_baud(uart_reg_ptr, uart_info_ptr->baudrate); - uart_info_ptr->status |= DEV_ENABLED; - } -} - -/** disable designware uart */ -static void dw_uart_disable_device(DEV_UART_INFO *uart_info_ptr) -{ - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - if ((uart_info_ptr->status & DEV_ENABLED) == DEV_ENABLED) { - dw_uart_set_baud(uart_reg_ptr, 0); - uart_info_ptr->status &= ~DEV_ENABLED; - } -} - -/** abort current interrupt transmit transfer */ -static void dw_uart_abort_tx(DEV_UART *uart_obj) -{ - DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info); - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - - if (uart_ctrl_ptr->int_status & DW_UART_TXINT_ENABLE) { - dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_SND); - uart_info_ptr->status |= DEV_IN_TX_ABRT; - if (uart_info_ptr->uart_cbs.tx_cb != NULL) { - uart_info_ptr->uart_cbs.tx_cb(uart_obj); - } - uart_info_ptr->status &= ~(DEV_IN_TX_ABRT); - } -} - -/** abort current interrupt receive transfer */ -static void dw_uart_abort_rx(DEV_UART *uart_obj) -{ - DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info); - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - - if (uart_ctrl_ptr->int_status & DW_UART_RXINT_ENABLE) { - dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_RCV); - uart_info_ptr->status |= DEV_IN_RX_ABRT; - if (uart_info_ptr->uart_cbs.rx_cb != NULL) { - uart_info_ptr->uart_cbs.rx_cb(uart_obj); - } - uart_info_ptr->status &= ~(DEV_IN_RX_ABRT); - } -} - -/** Get available transmit fifo count */ -static int32_t dw_uart_get_txavail(DW_UART_CTRL *uart_ctrl_ptr) -{ - int32_t tx_avail = 0; - DW_UART_REG *uart_reg_ptr = (DW_UART_REG *)(uart_ctrl_ptr->dw_uart_regbase); - - if (uart_ctrl_ptr->tx_fifo_len <= 1) { - if (dw_uart_putready(uart_reg_ptr) == 1) { - tx_avail = 1; - } else { - tx_avail = 0; - } - } else { - tx_avail = uart_ctrl_ptr->tx_fifo_len - uart_reg_ptr->TFL; - } - return tx_avail; -} - -/** Get available receive fifo count */ -static int32_t dw_uart_get_rxavail(DW_UART_CTRL *uart_ctrl_ptr) -{ - int32_t rx_avail = 0; - DW_UART_REG *uart_reg_ptr = (DW_UART_REG *)(uart_ctrl_ptr->dw_uart_regbase); - - if (uart_ctrl_ptr->rx_fifo_len <= 1) { - if (dw_uart_getready(uart_reg_ptr) == 1) { - rx_avail = 1; - } else { - rx_avail = 0; - } - } else { - rx_avail = uart_reg_ptr->RFL; - } - return rx_avail; -} - - -/** @} end of group DEVICE_DW_UART_STATIC */ - -/** - * \brief open a designware uart device - * \param[in] uart_obj uart object structure pointer - * \param[in] baud baudrate to initialized - * \retval E_OK Open successfully without any issues - * \retval E_OPNED If device was opened before with different baudrate, then return E_OPNED - * \retval E_OBJ Device object is not valid - * \retval E_PAR Parameter is not valid - * \retval E_NOSPT Open settings are not supported - */ -int32_t dw_uart_open (DEV_UART *uart_obj, uint32_t baud) -{ - int32_t ercd = E_OK; - DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info); - - /* START ERROR CHECK */ - VALID_CHK_UART_INFO_OBJECT(uart_info_ptr); - DW_UART_CHECK_EXP(baud>0, E_PAR); - /* END OF ERROR CHECK */ - - uart_info_ptr->opn_cnt ++; - if (uart_info_ptr->opn_cnt > 1) { /* opened before */ - if (baud == uart_info_ptr->baudrate) { /* baudrate is the same */ - return E_OK; - } else { /* open with different baudrate */ - return E_OPNED; - } - } - - int32_t baud_divisor = 0; - - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - /* Get FIFO Length */ - uart_ctrl_ptr->tx_fifo_len = dw_uart_get_txfifo_len(uart_reg_ptr); - uart_ctrl_ptr->rx_fifo_len = dw_uart_get_rxfifo_len(uart_reg_ptr); - - /** init uart */ - uart_info_ptr->baudrate = baud; - baud_divisor = DW_UART_BAUD2DIV(uart_ctrl_ptr->dw_apb_bus_freq, baud); - uart_info_ptr->dps_format = dps_format_default; - uart_info_ptr->hwfc = hwfc_default; - dw_uart_init(uart_reg_ptr, baud_divisor, &(uart_info_ptr->dps_format), uart_info_ptr->hwfc); - - uart_info_ptr->status = DEV_ENABLED; - uart_info_ptr->extra = NULL; - - /** - * uart interrupt related init - */ - dw_uart_disable_interrupt(uart_info_ptr); - /** install uart interrupt into system */ - int_handler_install(uart_ctrl_ptr->intno, uart_ctrl_ptr->dw_uart_int_handler); - - memset(&(uart_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(uart_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(uart_info_ptr->uart_cbs), 0, sizeof(DEV_UART_CBS)); - -error_exit: - return ercd; -} - -/** - * \brief close a DesignWare UART device - * \param[in] uart_obj uart object structure pointer - * \retval E_OK Open successfully without any issues - * \retval E_OPNED Device is still opened, the device opn_cnt decreased by 1 - * \retval E_OBJ Device object is not valid - */ -int32_t dw_uart_close (DEV_UART *uart_obj) -{ - int32_t ercd = E_OK; - DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info); - - /* START ERROR CHECK */ - VALID_CHK_UART_INFO_OBJECT(uart_info_ptr); - DW_UART_CHECK_EXP(uart_info_ptr->opn_cnt > 0, E_OK); - /* END OF ERROR CHECK */ - - uart_info_ptr->opn_cnt --; - if (uart_info_ptr->opn_cnt == 0) { - dw_uart_disable_interrupt(uart_info_ptr); - dw_uart_abort_tx(uart_obj); - dw_uart_abort_rx(uart_obj); - dw_uart_flush_output(uart_info_ptr); - memset(&(uart_info_ptr->tx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(uart_info_ptr->rx_buf), 0, sizeof(DEV_BUFFER)); - memset(&(uart_info_ptr->uart_cbs), 0, sizeof(DEV_UART_CBS)); - dw_uart_disable_device(uart_info_ptr); - uart_info_ptr->status = 0; - uart_info_ptr->extra = NULL; - } else { - ercd = E_OPNED; - } - -error_exit: - return ercd; -} - -/** - * \brief control uart by ctrl command - * \param[in] uart_obj uart object structure pointer - * \param[in] ctrl_cmd control command code to do specific uart work - * \param[in,out] param parameters used to control uart or return something - * \retval E_OK Control device successfully - * \retval E_CLSED Device is not opened - * \retval E_DIS Device is disabled - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid for current control command - * \retval E_SYS Control device failed, due to hardware issues - * \retval E_CTX Control device failed, due to different reasons like in transfer state - * \retval E_NOSPT Control command is not supported or not valid - */ -int32_t dw_uart_control (DEV_UART *uart_obj, uint32_t ctrl_cmd, void *param) -{ - int32_t ercd = E_OK; - DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info); - - /* START ERROR CHECK */ - VALID_CHK_UART_INFO_OBJECT(uart_info_ptr); - DW_UART_CHECK_EXP(uart_info_ptr->opn_cnt > 0, E_CLSED); - /* END OF ERROR CHECK */ - - uint32_t val32; /** to receive unsigned int value */ - int32_t baud_divisor = 0; - DEV_BUFFER *devbuf; - UART_DPS_FORMAT *dps_ptr; - UART_HW_FLOW_CONTROL hwfc_local; - - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - /* check whether current device is disabled */ - if ((uart_info_ptr->status & DEV_ENABLED) == 0) { - /** When device is disabled, - * only UART_CMD_ENA_DEV, UART_CMD_DIS_DEV, UART_CMD_GET_STATUS - * are available, other commands will return E_SYS - */ - if ((ctrl_cmd != UART_CMD_ENA_DEV) && \ - (ctrl_cmd != UART_CMD_DIS_DEV) && \ - (ctrl_cmd != UART_CMD_GET_STATUS) ) { - return E_SYS; - } - } - - switch (ctrl_cmd) { - case UART_CMD_SET_BAUD: - val32 = (uint32_t)param; - DW_UART_CHECK_EXP(val32>0, E_PAR); - if (val32 != uart_info_ptr->baudrate) { - baud_divisor = DW_UART_BAUD2DIV(uart_ctrl_ptr->dw_apb_bus_freq, val32); - dw_uart_set_baud(uart_reg_ptr, baud_divisor); - uart_info_ptr->baudrate = val32; - } - break; - case UART_CMD_GET_STATUS: - DW_UART_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = uart_info_ptr->status; - break; - case UART_CMD_ENA_DEV: - dw_uart_enable_device(uart_info_ptr); - break; - case UART_CMD_DIS_DEV: - dw_uart_disable_device(uart_info_ptr); - break; - case UART_CMD_FLUSH_OUTPUT: - dw_uart_flush_output(uart_info_ptr); - break; - case UART_CMD_GET_RXAVAIL: - DW_UART_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = dw_uart_get_rxavail(uart_ctrl_ptr); - break; - case UART_CMD_GET_TXAVAIL: - DW_UART_CHECK_EXP((param!=NULL) && CHECK_ALIGN_4BYTES(param), E_PAR); - *((int32_t *)param) = dw_uart_get_txavail(uart_ctrl_ptr); - break; - case UART_CMD_BREAK_SET: - dw_uart_set_break(uart_reg_ptr); - break; - case UART_CMD_BREAK_CLR: - dw_uart_clr_break(uart_reg_ptr); - break; - case UART_CMD_SET_DPS_FORMAT: - DW_UART_CHECK_EXP(param!=NULL, E_PAR); - dps_ptr = (UART_DPS_FORMAT *)param; - if (dw_uart_set_dps(uart_reg_ptr, dps_ptr) == 0) { - uart_info_ptr->dps_format = *dps_ptr; - } else { - ercd = E_PAR; - } - break; - case UART_CMD_SET_HWFC: - hwfc_local = (UART_HW_FLOW_CONTROL)param; - DW_UART_CHECK_EXP(((hwfc_local>=UART_FC_NONE) && (hwfc_local<=UART_FC_BOTH)), E_PAR); - dw_uart_set_hwfc(uart_reg_ptr, hwfc_local); - uart_info_ptr->hwfc = hwfc_local; - break; - case UART_CMD_SET_TXCB: - DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - uart_info_ptr->uart_cbs.tx_cb = param; - break; - case UART_CMD_SET_RXCB: - DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - uart_info_ptr->uart_cbs.rx_cb = param; - break; - case UART_CMD_SET_ERRCB: - DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - uart_info_ptr->uart_cbs.err_cb = param; - break; - case UART_CMD_ABORT_TX: - dw_uart_abort_tx(uart_obj); - break; - case UART_CMD_ABORT_RX: - dw_uart_abort_rx(uart_obj); - break; - case UART_CMD_SET_TXINT: - val32 = (uint32_t)param; - if (val32 == 0) { - dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_SND); - } else { - dw_uart_ena_cbr(uart_info_ptr, DW_UART_RDY_SND); - } - break; - case UART_CMD_SET_RXINT: - val32 = (uint32_t)param; - if (val32 == 0) { - dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_RCV); - } else { - dw_uart_ena_cbr(uart_info_ptr, DW_UART_RDY_RCV); - } - break; - case UART_CMD_SET_TXINT_BUF: - DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - if (param != NULL) { - devbuf = (DEV_BUFFER *)param; - uart_info_ptr->tx_buf = *devbuf; - uart_info_ptr->tx_buf.ofs = 0; - } else { - uart_info_ptr->tx_buf.buf = NULL; - uart_info_ptr->tx_buf.len = 0; - uart_info_ptr->tx_buf.ofs = 0; - } - break; - case UART_CMD_SET_RXINT_BUF: - DW_UART_CHECK_EXP(CHECK_ALIGN_4BYTES(param), E_PAR); - if (param != NULL) { - devbuf = (DEV_BUFFER *)param; - uart_info_ptr->rx_buf = *devbuf; - uart_info_ptr->rx_buf.ofs = 0; - } else { - uart_info_ptr->rx_buf.buf = NULL; - uart_info_ptr->rx_buf.len = 0; - uart_info_ptr->rx_buf.ofs = 0; - } - break; - default: - ercd = E_NOSPT; - break; - } - -error_exit: - return ercd; -} - -/** - * \brief send data through DesignWare UART - * \param[in] uart_obj uart object structure pointer - * \param[in] data data that need to send (data must be char type) - * \param[in] len data length need to send - * \retval >0 Byte count that was successfully sent for poll method - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid for current control command - * \retval E_SYS Can't write data to hardware due to hardware issues - */ -int32_t dw_uart_write (DEV_UART *uart_obj, const void *data, uint32_t len) -{ - int32_t ercd = E_OK; - DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info); - - /* START ERROR CHECK */ - VALID_CHK_UART_INFO_OBJECT(uart_info_ptr); - DW_UART_CHECK_EXP(uart_info_ptr->opn_cnt > 0, E_CLSED); - DW_UART_CHECK_EXP(uart_info_ptr->status & DEV_ENABLED, E_SYS); - DW_UART_CHECK_EXP(data!=NULL, E_PAR); - DW_UART_CHECK_EXP(len>0, E_PAR); - /* END OF ERROR CHECK */ - - int32_t i = 0; - const char *p_charbuf = (const char *)data; - - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - while (i < len) { - dw_uart_psnd_chr(uart_reg_ptr, p_charbuf[i++]); - } - ercd = i; - -error_exit: - return ercd; -} - -/** - * \brief read data through DesignWare UART - * \param[in] uart_obj uart object structure pointer - * \param[out] data data that need to read (data must be char type) - * \param[in] len data count need to read - * \retval >0 Byte count that was successfully sent for poll method - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid for current control command - * \retval E_SYS Can't receive data from hardware due to hardware issues, such as device is disabled - */ -int32_t dw_uart_read (DEV_UART *uart_obj, void *data, uint32_t len) -{ - int32_t ercd = E_OK; - DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info); - - /* START ERROR CHECK */ - VALID_CHK_UART_INFO_OBJECT(uart_info_ptr); - DW_UART_CHECK_EXP(uart_info_ptr->opn_cnt > 0, E_CLSED); - DW_UART_CHECK_EXP(uart_info_ptr->status & DEV_ENABLED, E_SYS); - DW_UART_CHECK_EXP(data!=NULL, E_PAR); - DW_UART_CHECK_EXP(len>0, E_PAR); - /* END OF ERROR CHECK */ - - int32_t i = 0; - char *p_charbuf = (char *)data; - - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - while (i < len) { - p_charbuf[i++] = dw_uart_prcv_chr(uart_reg_ptr); - } - ercd = i; - -error_exit: - return ercd; -} - -/** - * \brief DesignWare UART interrupt processing routine - * \param[in] uart_obj uart object structure pointer - * \param[in] ptr extra information - */ -void dw_uart_isr (DEV_UART *uart_obj, void *ptr) -{ - int32_t ercd = E_OK; - DEV_UART_INFO *uart_info_ptr = &(uart_obj->uart_info); - - /* START ERROR CHECK */ - VALID_CHK_UART_INFO_OBJECT(uart_info_ptr); - /* END OF ERROR CHECK */ - - uint32_t uart_int_status; /** uart interrupt status */ - volatile uint32_t temp; /** read error status to clear interrupt */ - DEV_BUFFER *buf_ptr; - char *p_charbuf; - - DW_UART_CTRL *uart_ctrl_ptr = (DW_UART_CTRL_PTR)(uart_info_ptr->uart_ctrl); - DW_UART_REG *uart_reg_ptr = (DW_UART_REG_PTR)(uart_ctrl_ptr->dw_uart_regbase); - - /** get uart interrupt status */ - uart_int_status = (uart_reg_ptr->IIR) & DW_UART_IIR_INT_ID_MASK; - - switch (uart_int_status) { - case DW_UART_IIR_MDM_STATUS: - temp = (volatile uint32_t)(uart_reg_ptr->MSR); - break; - case DW_UART_IIR_LINE_STATUS: - if (uart_info_ptr->uart_cbs.err_cb) { - uart_info_ptr->uart_cbs.err_cb(uart_info_ptr); - } - temp = (volatile uint32_t)(uart_reg_ptr->LSR); - break; - case DW_UART_IIR_XMIT_EMPTY: - buf_ptr = &(uart_info_ptr->tx_buf); - p_charbuf = (char *)buf_ptr->buf; - if (p_charbuf != NULL) { - while (dw_uart_putready(uart_reg_ptr)) { - dw_uart_putchar(uart_reg_ptr, p_charbuf[buf_ptr->ofs]); - buf_ptr->ofs ++; - if (buf_ptr->ofs >= buf_ptr->len) { - dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_SND); - if (uart_info_ptr->uart_cbs.tx_cb) { - uart_info_ptr->uart_cbs.tx_cb(uart_obj); - } - /* clear the send buffer pointer */ - memset(buf_ptr, 0, sizeof(DEV_BUFFER)); - break; - } - } - } else { - if (uart_info_ptr->uart_cbs.tx_cb) { - uart_info_ptr->uart_cbs.tx_cb(uart_obj); - } - } - break; - case DW_UART_IIR_RX_TIMEOUT: - temp = dw_uart_getchar(uart_reg_ptr); - break; - case DW_UART_IIR_DATA_AVAIL: - buf_ptr = &(uart_info_ptr->rx_buf); - p_charbuf = (char *)buf_ptr->buf; - if (p_charbuf != NULL) { - while (dw_uart_getready(uart_reg_ptr)) { - p_charbuf[buf_ptr->ofs] = (char)dw_uart_getchar(uart_reg_ptr); - buf_ptr->ofs ++; - if (buf_ptr->ofs >= buf_ptr->len) { - dw_uart_dis_cbr(uart_info_ptr, DW_UART_RDY_RCV); - if (uart_info_ptr->uart_cbs.rx_cb) { - uart_info_ptr->uart_cbs.rx_cb(uart_obj); - } - /* clear the send buffer pointer */ - memset(buf_ptr, 0, sizeof(DEV_BUFFER)); - break; - } - } - } else { - if (uart_info_ptr->uart_cbs.rx_cb) { - uart_info_ptr->uart_cbs.rx_cb(uart_obj); - } - } - break; - default: - temp = (volatile uint32_t)(uart_reg_ptr->USR); - break; - } - -error_exit: - return; -} diff --git a/bsp/synopsys/embarc/device/designware/uart/dw_uart.h b/bsp/synopsys/embarc/device/designware/uart/dw_uart.h deleted file mode 100644 index 366c4fccc22a931b4cc84fb80261e1a4e8e9529d..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/device/designware/uart/dw_uart.h +++ /dev/null @@ -1,141 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-06-20 - * \author Huaqi Fang(Huaqi.Fang@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup DEVICE_DW_UART - * \brief DesignWare UART driver header file - * \details detailed definitions of designware uart driver - */ - -#ifndef _DW_UART_H_ -#define _DW_UART_H_ - -#include "device/device_hal/inc/dev_uart.h" - -#include "inc/arc/arc_exception.h" - -/** - * if this header file is included, - * will indicate that this designware uart device - * is used - */ -#define DEVICE_USE_DESIGNWARE_UART - -/** - * \name DesignWare UART Register Structure - * \brief contains definitions of DesignWare UART register structure. - * @{ - */ -/** - * \brief DesignWare UART register structure - * \details Detailed struct description of DesignWare UART - * block register information, implementation of dev_uart_info::uart_regs - */ -typedef volatile struct dw_uart_reg { - uint32_t DATA; /*!< data in/out and DLL */ - uint32_t IER; /*!< Interrupt enable register and DLH */ - uint32_t IIR; /*!< Interrupt Id register and FCR */ - uint32_t LCR; /*!< Line control Register */ - uint32_t MCR; /*!< Modem control register */ - uint32_t LSR; /*!< Line Status Register */ - uint32_t MSR; /*!< Modem status Register */ - uint32_t SCRATCHPAD; /*!< Uart scratch pad register */ - uint32_t LPDLL; /*!< Low Power Divisor Latch (Low) Reg */ - uint32_t LPDLH; /*!< Low Power Divisor Latch (High) Reg */ - uint32_t RES1[2]; /*!< Reserved */ - uint32_t SHR[16]; /*!< Shadow data register(SRBR and STHR) */ - uint32_t FAR; /*!< FIFO Access register */ - uint32_t TFR; /*!< Transmit FIFO Read */ - uint32_t RFW; /*!< Receive FIFO write */ - uint32_t USR; /*!< UART status register */ - uint32_t TFL; /*!< Transmit FIFO level */ - uint32_t RFL; /*!< Receive FIFO level */ - uint32_t SRR; /*!< Software reset register */ - uint32_t SRTS; /*!< Shadow request to send */ - uint32_t SBCR; /*!< Shadow break control */ - uint32_t SDMAM; /*!< Shadow DMA mode */ - uint32_t SFE; /*!< Shadow FIFO enable */ - uint32_t SRT; /*!< Shadow RCVR Trigger */ - uint32_t STET; /*!< Shadow TX empty register */ - uint32_t HTX; /*!< Halt TX */ - uint32_t DMASA; /*!< DMA Software ACK */ - uint32_t RES2[18]; /*!< Reserved */ - uint32_t CPR; /*!< Camponent parameter register */ - uint32_t UCV; /*!< UART Component Version */ - uint32_t CTR; /*!< Component typw register */ -} DW_UART_REG, *DW_UART_REG_PTR; -/** @} */ - -#define DW_UART_GINT_DISABLED (0) /*!< designware interrupt disabled for control uart irq/fiq */ -#define DW_UART_GINT_ENABLE (1<<0) /*!< designware interrupt enabled for control uart irq/fiq */ -#define DW_UART_TXINT_ENABLE (1<<1) /*!< designware interrupt enabled for control transmit process */ -#define DW_UART_RXINT_ENABLE (1<<2) /*!< designware interrupt enabled for control transmit process */ - -/** - * \brief DesignWare UART control structure definition - * \details implement of dev_uart_info::uart_ctrl - */ -typedef struct dw_uart_ctrl { - uint32_t dw_uart_regbase; /*!< uart ip register base */ - uint32_t dw_apb_bus_freq; /*!< uart ip apb bus frequency */ - uint32_t intno; /*!< uart interrupt vector number */ - INT_HANDLER dw_uart_int_handler; /*!< uart interrupt handler */ - uint32_t tx_fifo_len; /*!< transmit fifo length, set by user in object implementation */ - uint32_t rx_fifo_len; /*!< receive fifo length, set by user in object implementation */ - uint32_t int_status; /*!< interrupt status for designware uart */ -} DW_UART_CTRL, *DW_UART_CTRL_PTR; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name DesignWare UART Function Declaration - * \brief contains declarations of designware uart functions. - * \details This are only used in uart object implementation source file - * @{ - */ -extern int32_t dw_uart_open (DEV_UART *uart_obj, uint32_t baud); -extern int32_t dw_uart_close (DEV_UART *uart_obj); -extern int32_t dw_uart_control (DEV_UART *uart_obj, uint32_t ctrl_cmd, void *param); -extern int32_t dw_uart_write (DEV_UART *uart_obj, const void *data, uint32_t len); -extern int32_t dw_uart_read (DEV_UART *uart_obj, void *data, uint32_t len); -extern void dw_uart_isr(DEV_UART *uart_obj, void *ptr); -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* _DW_UART_H_ */ diff --git a/bsp/synopsys/embarc/device/designware/uart/dw_uart_hal.h b/bsp/synopsys/embarc/device/designware/uart/dw_uart_hal.h deleted file mode 100644 index 367894df997e06b13cf425392bb9d73f10662d5a..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/device/designware/uart/dw_uart_hal.h +++ /dev/null @@ -1,253 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-06-20 - * \author Huaqi Fang(Huaqi.Fang@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup DEVICE_DW_IIC - * \brief DesignWare UART driver hardware description related header file - * \details detailed hardware related definitions of DesignWare UART driver - */ - -#ifndef _DEVICE_DW_UART_HAL_H_ -#define _DEVICE_DW_UART_HAL_H_ - -/* DW APB UART bit definitions */ - -/** - * \name DesignWare UART HAL IER Marcos - * \brief DesignWare UART hal IER related macros - * @{ - */ -/* IER */ -#define DW_UART_IER_DATA_AVAIL (0x01) -#define DW_UART_IER_XMIT_EMPTY (0x02) -#define DW_UART_IER_LINE_STATUS (0x04) -#define DW_UART_IER_MDM_STATUS (0x08) -#define DW_UART_IER_PTIME (0x80) -/** @} */ - -/** - * \name DesignWare UART HAL IIR Marcos - * \brief DesignWare UART hal IIR related macros - * @{ - */ -/* IIR */ -/* IIR READ */ -#define DW_UART_IIR_IP (0x01) -#define DW_UART_IIR_MASK (0x0E) -#define DW_UART_IIR_READ_FIFO_ENABLE (0xC0) - -/* Possible interrupt IIR_MASK values */ -#define DW_UART_IIR_MDM_STATUS (0x00) -#define DW_UART_IIR_XMIT_EMPTY (0x02) -#define DW_UART_IIR_DATA_AVAIL (0x04) -#define DW_UART_IIR_LINE_STATUS (0x06) -#define DW_UART_IIR_RX_TIMEOUT (0x0C) -#define DW_UART_IIR_INT_ID_MASK (0x0f) - -/* IIR WRITE */ -#define DW_UART_IIR_FIFO_ENABLE (0x01) -#define DW_UART_IIR_RCVR_FIFO_RESET (0x02) -#define DW_UART_IIR_XMIT_FIFO_RESET (0x04) -#define DW_UART_IIR_DMA_MODE_SELECT (0x08) -#define DW_UART_IIR_RCV_TRIGGER_MASK (0xC0) - -/* Values for IIR receive trigger */ -#define DW_UART_IIR_TRIGGER_LEVEL_1_CHAR (0x00) -#define DW_UART_IIR_TRIGGER_LEVEL_1_4_FULL (0x40) -#define DW_UART_IIR_TRIGGER_LEVEL_1_2_FULL (0x80) -#define DW_UART_IIR_TRIGGER_LEVEL_2_LESS_FULL (0xC0) -/** @} */ - -/** - * \name DesignWare UART HAL LCR Marcos - * \brief DesignWare UART hal LCR related macros - * @{ - */ -/* LCR */ -#define DW_UART_LCR_WORD_LEN_MASK (0x03) -#define DW_UART_LCR_STOP_BIT_MASK (0x04) -#define DW_UART_LCR_PARITY_MASK (0x38) -#define DW_UART_LCR_DPS_MASK (0x3F) -#define DW_UART_LCR_STICK_PARITY (0x20) -#define DW_UART_LCR_BREAK (0x40) -#define DW_UART_LCR_DLAB (0x80) - -/* Word length values */ -#define DW_UART_LCR_WORD_LEN5 (0x00) -#define DW_UART_LCR_WORD_LEN6 (0x01) -#define DW_UART_LCR_WORD_LEN7 (0x02) -#define DW_UART_LCR_WORD_LEN8 (0x03) - -/* stop bit values */ -#define DW_UART_LCR_1_STOP_BIT (0x00) -#define DW_UART_LCR_1D5_STOP_BIT (0x04) -#define DW_UART_LCR_2_STOP_BIT (0x04) - -/* Parity bit values */ -#define DW_UART_LCR_PARITY_NONE (0x00) -#define DW_UART_LCR_PARITY_ODD (0x08) -#define DW_UART_LCR_PARITY_EVEN (0x18) -#define DW_UART_LCR_PARITY_MARK (0x28) -#define DW_UART_LCR_PARITY_SPACE (0x38) - -/** @} */ - -/** - * \name DesignWare UART HAL MCR Marcos - * \brief DesignWare UART hal MCR related macros - * @{ - */ -/* MCR */ -#define DW_UART_MCR_DTR (0x01) -#define DW_UART_MCR_RTS (0x02) -#define DW_UART_MCR_LOOPBACK (0x10) -#define DW_UART_MCR_AFCE (0x20) -#define DW_UART_MCR_SIRE (0x40) -/** @} */ - -/** - * \name DesignWare UART HAL LSR Marcos - * \brief DesignWare UART hal LSR related macros - * @{ - */ -/* LSR */ -#define DW_UART_LSR_DR (0x01) -#define DW_UART_LSR_OVERRUN (0x02) -#define DW_UART_LSR_PARITYERR (0x04) -#define DW_UART_LSR_FRAMEERR (0x08) -#define DW_UART_LSR_BREAKRCVD (0x10) -#define DW_UART_LSR_TXD_EMPTY (0x20) -#define DW_UART_LSR_TX_STATUS (0x40) -#define DW_UART_LSR_RX_FIFOERR (0x80) -/** @} */ - -/** - * \name DesignWare UART HAL MSR Marcos - * \brief DesignWare UART hal MSR related macros - * @{ - */ -/* MSR */ -#define DW_UART_MSR_DCTS (0x01) -#define DW_UART_MSR_DDSR (0x02) -#define DW_UART_MSR_TERI (0x04) -#define DW_UART_MSR_DDCD (0x08) -#define DW_UART_MSR_CTS (0x10) -#define DW_UART_MSR_DSR (0x20) -#define DW_UART_MSR_RIC (0x40) -#define DW_UART_MSR_DCD (0x80) -/** @} */ - -/** - * \name DesignWare UART HAL FCR Marcos - * \brief DesignWare UART hal FCR related macros - * @{ - */ -/* FCR */ -#define DW_UART_FCR_FEN (0x01) -#define DW_UART_FCR_RFR (0x02) -#define DW_UART_FCR_TFR (0x04) -#define DW_UART_FCR_DMS (0x08) -#define DW_UART_FCR_RTL (0xC0) -/** @} */ - -/** - * \name DesignWare UART HAL USR Marcos - * \brief DesignWare UART hal USR related macros - * @{ - */ -/* USR */ -#define DW_UART_USR_BUSY (0x01) -#define DW_UART_USR_TFNF (0x02) -#define DW_UART_USR_TFE (0x04) -#define DW_UART_USR_RFNE (0x08) -#define DW_UART_USR_RFF (0x10) -/** @} */ - -/** - * \name DesignWare UART HAL SFE Marcos - * \brief DesignWare UART hal SFE related macros - * @{ - */ -/* SFE */ -#define DW_UART_SFE_SHADOW_FIFO_ENABLE (0x01) -/** @} */ - -/** - * \name DesignWare UART HAL SRR Marcos - * \brief DesignWare UART hal SRR related macros - * @{ - */ -/* SRR */ -#define DW_UART_SRR_UR (0x01) -#define DW_UART_SRR_RFR (0x02) -#define DW_UART_SRR_XFR (0x04) -/** @} */ - -/** - * \name DesignWare UART HAL SRT Marcos - * \brief DesignWare UART hal SRT related macros - * @{ - */ -/* SRT */ -#define DW_UART_SRT_TRIGGER_LEVEL_1_CHAR (0x00) -#define DW_UART_SRT_TRIGGER_LEVEL_1_4_FULL (0x01) -#define DW_UART_SRT_TRIGGER_LEVEL_1_2_FULL (0x02) -#define DW_UART_SRT_TRIGGER_LEVEL_2_LESS_FULL (0x03) -/** @} */ - -/** - * \name DesignWare UART HAL STET Marcos - * \brief DesignWare UART hal STET related macros - * @{ - */ -/* STET*/ -#define DW_UART_STET_FIFO_EMPTY (0x00) -#define DW_UART_STET_2_CHARS_IN_FIFO (0x01) -#define DW_UART_STET_1_4_FULL (0x02) -#define DW_UART_STET_1_2_FULL (0x03) -/** @} */ - -/** - * \name DesignWare UART HAL CPR Marcos - * \brief DesignWare UART hal CPR related macros - * @{ - */ -/* CPR*/ -#define DW_UART_CPR_FIFO_STAT (1<<10) -#define DW_UART_CPR_FIFO_MODE_OFS (16) -#define DW_UART_CPR_FIFO_MODE_MASK (0xFF) -#define DW_UART_CPR_FIFO_MODE (0xFF0000) -/** @} */ - -#endif /* _DEVICE_DW_UART_HAL_H_ */ diff --git a/bsp/synopsys/embarc/device/device_hal/inc/dev_common.h b/bsp/synopsys/embarc/device/device_hal/inc/dev_common.h deleted file mode 100644 index 623d54a6116151db2bf949e1ea31876665d1deda..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/device/device_hal/inc/dev_common.h +++ /dev/null @@ -1,173 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-06-16 - * \author Huaqi Fang(Huaqi.Fang@synopsys.com) ---------------------------------------------- */ - -/** - * \defgroup DEVICE_HAL_COMMON Common Device Layer Definitions - * \ingroup DEVICE_HAL_DEF - * \brief common definitions for device layer (\ref dev_common.h) - * - * @{ - * - * \file - * \brief header file to define common definitions for device layer - * \details Here in this file provide definitions that need by other - * devices in device layer - */ - -#ifndef _DEVICE_HAL_COMMON_H_ -#define _DEVICE_HAL_COMMON_H_ - -#include - -/** - * \defgroup DEVICE_HAL_COMMON_DEVSTATE Common Device State - * \ingroup DEVICE_HAL_COMMON - * \brief definitions for device state - * \details here defines macros for device open/close, - * device working good/error, used in - * \ref DEVICE_HAL_UART, \ref DEVICE_HAL_SPI, - * \ref DEVICE_HAL_IIC, \ref DEVICE_HAL_GPIO - * @{ - */ -/* - * macros for device open and close state - */ -#define DEV_CLOSED (0) /*!< Indicate that device was closed */ -#define DEV_OPENED (1) /*!< Indicate that the device was opened */ - -/* - * macros for device good and error state - */ -#define DEV_GOOD (0) /*!< Indicate device is good */ -#define DEV_ERROR (1) /*!< Indicate device error */ -/** @} */ - -/** - * \defgroup DEVICE_HAL_COMMON_DEVMTHD Common Device Working Method - * \ingroup DEVICE_HAL_COMMON - * \brief definitions for device working method(interrupt or poll) - * \details here defines macros for working method, - * interrupt or poll method,used in - * \ref DEVICE_HAL_UART, \ref DEVICE_HAL_SPI, - * \ref DEVICE_HAL_IIC, \ref DEVICE_HAL_GPIO - * @{ - */ -/* - * macros for device working method - */ -#define DEV_POLL_METHOD (0) /*!< Indicate that the device running in poll method */ -#define DEV_INTERRUPT_METHOD (1) /*!< Indicate that the device running in interrupt method */ -/** @} */ - -/** - * \defgroup DEVICE_HAL_COMMON_DEVMODE Common Device Working Mode - * \ingroup DEVICE_HAL_COMMON - * \brief definitions for device working mode(master or slave) - * \details here defines macros for working mode, - * Master or Slave mode,used in - * \ref DEV_HAL_IIC, \ref DEV_HAL_SPI. - * @{ - */ -/* - * macros for device working mode - */ -#define DEV_MASTER_MODE (0) /*!< Indicate that the device working as master */ -#define DEV_SLAVE_MODE (1) /*!< Indicate that the device working as slave */ -/** @} */ - -/** - * \defgroup DEVICE_HAL_COMMON_DEVSTATUS Common Device Status - * \ingroup DEVICE_HAL_COMMON - * \brief definitions for device status, 1 bit for 1 function - * @{ - */ -#define DEV_DISABLED (0) /*!< Bit 0 for device enabled state, disabled */ -#define DEV_ENABLED (1<<0) /*!< Bit 0 for device enabled state, enabled */ -#define DEV_IN_TX (1<<1) /*!< Bit 1 for device in transmit state */ -#define DEV_IN_RX (1<<2) /*!< Bit 2 for device in receive state */ -#define DEV_IN_XFER (1<<3) /*!< Bit 3 for device in transfer state */ -#define DEV_IN_TX_ABRT (1<<4) /*!< Bit 4 for device in transmit abort state */ -#define DEV_IN_RX_ABRT (1<<5) /*!< Bit 5 for device in receive abort state */ -#define DEV_IN_XFER_ABRT (1<<6) /*!< Bit 6 for device in transfer abort state */ -/** @} */ - -/** - * \defgroup DEVICE_HAL_COMMON_DEFCMD Common Device Defining Command - * \ingroup DEVICE_HAL_COMMON - * \brief definitions for defining command code - * \details here defines macros to define command code, - * in system code, use \ref DEV_SET_SYSCMD to define command code. - * in user code, use \ref DEV_SET_USRCMD to define command code. - * So that there will be no conflicts in system and user defined command code. - * this used used in - * \ref DEVICE_HAL_UART, \ref DEVICE_HAL_SPI, - * \ref DEVICE_HAL_IIC, \ref DEVICE_HAL_GPIO, - * and in user code - * @{ - */ -/* - * macros for control command base - */ -#define DEV_SYS_CMDBSE (0x00000000) /*!< default system device control command base(defined by embARC) */ -#define DEV_USR_CMDBSE (0x80000000) /*!< default user device control command base(defined by user) in user implementing */ -#define DEV_SET_SYSCMD(cmd) (DEV_SYS_CMDBSE|(cmd)) /*!< set device system control command */ -#define DEV_SET_USRCMD(cmd) (DEV_USR_CMDBSE|(cmd)) /*!< set device user control command */ - -#define CONV2VOID(param) ((void *)(param)) /*!< convert param into void * type */ -/** @} */ - -/** - * Common Device Buffer Structure - */ -typedef struct dev_buffer { - void *buf; /*!< buffer pointer */ - uint32_t len; /*!< buffer length in bytes */ - uint32_t ofs; /*!< current offset in buffer */ -} DEV_BUFFER; - -/** Init device buffer */ -#define DEV_BUFFER_INIT(devbuf, buffer, size) { \ - (devbuf)->buf = (void *)(buffer); \ - (devbuf)->len = (uint32_t)(size); \ - (devbuf)->ofs = (uint32_t)(0); \ - } - -/** - * Device callback function typedef. - * This is usually used in device callback settings, - * and \ptr should be the device object pointer, - * such as DEV_IIC * */ -typedef void (*DEV_CALLBACK) (void *ptr); - -/** @} */ -#endif /* _DEVICE_HAL_COMMON_H_ */ diff --git a/bsp/synopsys/embarc/device/device_hal/inc/dev_gpio.h b/bsp/synopsys/embarc/device/device_hal/inc/dev_gpio.h deleted file mode 100644 index 290fd313a2ea399c9a8da7b8b5cfbd4823c92169..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/device/device_hal/inc/dev_gpio.h +++ /dev/null @@ -1,424 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-06-17 - * \author Huaqi Fang(Huaqi.Fang@synopsys.com) ---------------------------------------------- */ - -/** - * \defgroup DEVICE_HAL_GPIO GPIO Device HAL Interface - * \ingroup DEVICE_HAL_DEF - * \brief definitions for gpio device hardware layer (\ref dev_gpio.h) - * \details provide interfaces for gpio driver to implement - * Here is a diagram for the gpio interface. - * - * \htmlonly - *
    - *
    - * GPIO Device HAL Interface Diagram - *

    GPIO Device HAL Interface Diagram

    - *
    - *
    - * \endhtmlonly - * - * @{ - * - * \file - * \brief gpio device hardware layer definitions - * \details Provide common definitions for gpio device, - * then the software developer can develop gpio driver - * following these definitions, and the applications - * can directly call this definition to realize functions - * - */ - -#ifndef _DEVICE_HAL_GPIO_H_ -#define _DEVICE_HAL_GPIO_H_ - -#include "device/device_hal/inc/dev_common.h" - -/** - * \defgroup DEVICE_HAL_GPIO_DEFDIR GPIO Port Direction Definition - * \ingroup DEVICE_HAL_GPIO - * \brief Define macros to indicate gpio directions - * @{ - */ -/* - * defines for gpio directions - */ -#define GPIO_DIR_INPUT (0) /*!< gpio works as input */ -#define GPIO_DIR_OUTPUT (1) /*!< gpio works as output */ -/** @} */ - -/** - * \defgroup DEVICE_HAL_GPIO_CTRLCMD GPIO Device Control Commands - * \ingroup DEVICE_HAL_GPIO - * \brief Definitions for gpio control command, used in \ref dev_gpio::gpio_control "GPIO IO Control" - * \details These commands defined here can be used in user code directly. - * - Parameters Usage - * - For passing parameters like integer, just use uint32_t/int32_t to directly pass values - * - For passing parameters for a structure, please use pointer to pass values - * - For getting some data, please use pointer to store the return data - * - Common Return Values - * - \ref E_OK, Control device successfully - * - \ref E_CLSED, Device is not opened - * - \ref E_OBJ, Device object is not valid or not exists - * - \ref E_PAR, Parameter is not valid for current control command - * - \ref E_SYS, Control device failed, due to hardware issues such as device is disabled - * - \ref E_NOSPT, Control command is not supported or not valid - * @{ - */ -/** - * Set the \ref dev_gpio_info::direction "direction" of masked bits of gpio port into \ref GPIO_DIR_INPUT "input" - * - Param type : uint32_t - * - Param usage : 1 in each bit will be masked. - * - Return value explanation : - */ -#define GPIO_CMD_SET_BIT_DIR_INPUT DEV_SET_SYSCMD(0) -/** - * Set the \ref dev_gpio_info::direction "direction" of masked bits of gpio port into \ref GPIO_DIR_OUTPUT "output" - * - Param type : uint32_t - * - Param usage : 1 in each bit will be masked. - * - Return value explanation : - */ -#define GPIO_CMD_SET_BIT_DIR_OUTPUT DEV_SET_SYSCMD(1) -/** - * Get \ref dev_gpio_info::direction "gpio port direction". - * - Param type : uint32_t - * - Param usage : 1 bit for 1 bit of gpio port, 0 for input, 1 for output - * - Return value explanation : - */ -#define GPIO_CMD_GET_BIT_DIR DEV_SET_SYSCMD(2) -/** - * Set gpio interrupt configuration for each bit. - * - Param type : \ref DEV_GPIO_INT_CFG * - * - Param usage : store gpio interrupt configuration for each bit. - * - Return value explanation : - */ -#define GPIO_CMD_SET_BIT_INT_CFG DEV_SET_SYSCMD(3) -/** - * Get gpio interrupt configuration for each bit. - * - Param type : \ref DEV_GPIO_INT_CFG * - * - Param usage : First set int_bit_mask in DEV_GPIO_INT_CFG structure to - * the mask of which bit of GPIO you want to get. And the interrupt configuration - * will be stored in the structure DEV_GPIO_INT_CFG, each bit stand for each bit of port. - * - Return value explanation : - */ -#define GPIO_CMD_GET_BIT_INT_CFG DEV_SET_SYSCMD(4) -/** - * Set gpio service routine for each bit. - * - Param type : \ref DEV_GPIO_BIT_ISR * - * - Param usage : store gpio handler information for each bit, int handler's param will be DEV_GPIO *. - * - Return value explanation : - */ -#define GPIO_CMD_SET_BIT_ISR DEV_SET_SYSCMD(5) -/** - * Get gpio service routine for each bit. - * - Param type : \ref DEV_GPIO_BIT_ISR * - * - Param usage : By passing int_bit_ofs in DEV_GPIO_BIT_ISR, - * it will return interrupt handler for this bit and store it in int_bit_handler. - * - Return value explanation : - */ -#define GPIO_CMD_GET_BIT_ISR DEV_SET_SYSCMD(6) -/** - * Enable gpio interrupt of the masked bits. - * - Param type : uint32_t - * - Param usage : 1 in each bit will be masked. - * - Return value explanation : - */ -#define GPIO_CMD_ENA_BIT_INT DEV_SET_SYSCMD(7) -/** - * Disable gpio interrupt of the masked bits. - * - Param type : uint32_t - * - Param usage : 1 in each bit will be masked. - * - Return value explanation : - */ -#define GPIO_CMD_DIS_BIT_INT DEV_SET_SYSCMD(8) -/** - * Get \ref dev_gpio_info::method "gpio interrupt enable status". - * - Param type : uint32_t * - * - Param usage : 1 bit for 1 bit of gpio port, 0 for poll, 1 for interrupt - * - Return value explanation : - */ -#define GPIO_CMD_GET_BIT_MTHD DEV_SET_SYSCMD(9) -/* @} */ - -/** - * \defgroup DEVICE_HAL_GPIO_INT_CFG_SET GPIO Device Int Configuration Settings - * \ingroup DEVICE_HAL_GPIO - * \brief definition of gpio interrupt type - * @{ - */ - -/* GPIO Mask Defintions */ -/** Mask none bits of the max 32bits */ -#define GPIO_BITS_MASK_NONE (0) -/** Mask all bits of the max 32bits */ -#define GPIO_BITS_MASK_ALL (0XFFFFFFFF) - -/* GPIO Interrupt Type Related Definitions */ - -/** Level sensitive interrupt type for 1 bit */ -#define GPIO_INT_LEVEL_TRIG (0) -/** Edge sensitive interrupt type for 1 bit */ -#define GPIO_INT_EDGE_TRIG (1) -/** Level sensitive interrupt type for all 32 bits */ -#define GPIO_INT_LEVEL_TRIG_ALL (0) -/** Edge sensitive interrupt type for all 32 bits */ -#define GPIO_INT_EDGE_TRIG_ALL (0XFFFFFFFF) - -/* For bit settings */ -/** Set bit interrupt type of gpio into level sensitive */ -#define GPIO_INT_BIT_LEVEL_TRIG(bit_ofs) (GPIO_INT_LEVEL_TRIG<<(bit_ofs)) -/** Set bit interrupt type of gpio into edge sensitive */ -#define GPIO_INT_BIT_EDGE_TRIG(bit_ofs) (GPIO_INT_EDGE_TRIG<<(bit_ofs)) -/* For bits settings */ -/** Set interrupt type of masked bits of gpio into level sensitive */ -#define GPIO_INT_BITS_LEVEL_TRIG(bit_mask) (GPIO_INT_LEVEL_TRIG_ALL&(bit_mask)) -/** Set bit interrupt type of gpio into edge sensitive */ -#define GPIO_INT_BITS_EDGE_TRIG(bit_mask) (GPIO_INT_EDGE_TRIG_ALL&(bit_mask)) - -/* GPIO Interrupt Polarity Related Definitions */ - -/** GPIO Interrupt polarity type enum */ -typedef enum gpio_int_polarity { - /* Polarity for 1 bit */ - GPIO_INT_ACTIVE_LOW = 0, /*!< Active low for level-sensitive interrupt for 1 bit */ - GPIO_INT_FALLING_EDGE = 0, /*!< Falling-edge for edge-sensitive interrupt for 1 bit */ - GPIO_INT_ACTIVE_HIGH = 1, /*!< Active high for level-sensitive interrupt for 1 bit */ - GPIO_INI_RISING_EDGE = 1, /*!< Rising-edge for edge-sensitive interrupt for 1 bit */ - /* Polartiy for all 32 bits */ - GPIO_INT_ACTIVE_LOW_ALL = 0, /*!< Active low for level-sensitive interrupt for all bits */ - GPIO_INT_FALLING_EDGE_ALL = 0, /*!< Falling-edge for edge-sensitive interrupt for all bits */ - GPIO_INT_ACTIVE_HIGH_ALL = 0XFFFFFFFF, /*!< Active high for level-sensitive interrupt for all bits */ - GPIO_INI_RISING_EDGE_ALL = 0XFFFFFFFF /*!< Rising-edge for edge-sensitive interrupt for all bits */ -} GPIO_INT_POLARITY; - -/* For bit settings */ -/** Set bit polarity of gpio into active low */ -#define GPIO_INT_BIT_POL_ACT_LOW(bit_ofs) (GPIO_INT_ACTIVE_LOW<<(bit_ofs)) -/** Set bit polarity of gpio into active high */ -#define GPIO_INT_BIT_POL_ACT_HIGH(bit_ofs) (GPIO_INT_ACTIVE_HIGH<<(bit_ofs)) -/** Set bit polarity of gpio into falling edge */ -#define GPIO_INT_BIT_POL_FALL_EDGE(bit_ofs) (GPIO_INT_FALLING_EDGE<<(bit_ofs)) -/** Set bit polarity of gpio into rising edge */ -#define GPIO_INT_BIT_POL_RISE_EDGE(bit_ofs) (GPIO_INI_RISING_EDGE<<(bit_ofs)) - -/* For bits settings */ -/** Set polarity of masked bits of gpio into active low */ -#define GPIO_INT_BITS_POL_ACT_LOW(bit_mask) (GPIO_INT_ACTIVE_LOW_ALL&(bit_mask)) -/** Set polarity of masked bits of gpio into active high */ -#define GPIO_INT_BITS_POL_ACT_HIGH(bit_mask) (GPIO_INT_ACTIVE_HIGH_ALL&(bit_mask)) -/** Set polarity of masked bits of gpio into falling edge */ -#define GPIO_INT_BITS_POL_FALL_EDGE(bit_mask) (GPIO_INT_FALLING_EDGE_ALL&(bit_mask)) -/** Set polarity of masked bits of gpio into rising edge */ -#define GPIO_INT_BITS_POL_RISE_EDGE(bit_mask) (GPIO_INI_RISING_EDGE_ALL&(bit_mask)) - -/* GPIO Interrupt Debounce Related Definitions */ - -/* For bit settings */ -/** Disable debounce circuitry for 1 bit */ -#define GPIO_INT_NO_DEBOUNCE (0) -/** Enable debounce circuitry for 1 bit */ -#define GPIO_INT_DEBOUNCE (1) - -/* For bits settings */ -/** Disable debounce circuitry for all bits */ -#define GPIO_INT_NO_DEBOUNCE_ALL (0) -/** Enable debounce circuitry for all bits */ -#define GPIO_INT_DEBOUNCE_ALL (0XFFFFFFFF) - -/* For bit settings */ -/** Set bit interrupt debounce of gpio into enabled */ -#define GPIO_INT_BIT_ENA_DEBOUNCE(bit_ofs) (GPIO_INT_DEBOUNCE<<(bit_ofs)) -/** Set bit interrupt debounce of gpio into disabled */ -#define GPIO_INT_BIT_DIS_DEBOUNCE(bit_ofs) (GPIO_INT_NO_DEBOUNCE<<(bit_ofs)) -/* For bits settings */ -/** Set bit interrupt debounce of gpio into enabled */ -#define GPIO_INT_BITS_ENA_DEBOUNCE(bit_mask) (GPIO_INT_DEBOUNCE_ALL&(bit_mask)) -/** Set bit interrupt debounce of gpio into disabled */ -#define GPIO_INT_BITS_DIS_DEBOUNCE(bit_mask) (GPIO_INT_NO_DEBOUNCE_ALL&(bit_mask)) - -/** GPIO interrupt configuration */ -typedef struct dev_gpio_int_cfg { - uint32_t int_bit_mask; /*!< interrupt bit mask for gpio */ - uint32_t int_bit_type; /*!< \ref GPIO_INT_LEVEL_TRIG "level sensitive" or \ref GPIO_INT_EDGE_TRIG "edge sensitive" for each gpio bit */ - uint32_t int_bit_polarity; /*!< active high or low, refer to \ref GPIO_INT_POLARITY for each gpio bit */ - uint32_t int_bit_debounce; /*!< \ref GPIO_INT_DEBOUNCE "enable" or \ref GPIO_INT_NO_DEBOUNCE "disable" debounce logic for each gpio bit */ -} DEV_GPIO_INT_CFG, * DEV_GPIO_INT_CFG_PTR; - -/** Default interrupt configuration for all gpio bits */ -static const DEV_GPIO_INT_CFG gpio_int_cfg_default = \ - {GPIO_BITS_MASK_ALL, GPIO_INT_LEVEL_TRIG_ALL, \ - GPIO_INT_ACTIVE_LOW_ALL, GPIO_INT_NO_DEBOUNCE_ALL}; - -/** GPIO interrupt handler or Interrupt Service Routine(ISR) */ -typedef void (*DEV_GPIO_HANDLER) (void *ptr); - -/** interrupt handler for each port bit */ -typedef struct dev_gpio_bit_isr { - uint32_t int_bit_ofs; /*!< int bit offset */ - DEV_GPIO_HANDLER int_bit_handler; /*!< interrupt handler */ -} DEV_GPIO_BIT_ISR, * DEV_GPIO_BIT_ISR_PTR; -/* @} */ - -/** - * \defgroup DEVICE_HAL_GPIO_DEVSTRUCT GPIO Device Interface Definition - * \ingroup DEVICE_HAL_GPIO - * \brief contains definitions of gpio device structure. - * \details This structure will be used in user implemented code, which was called - * \ref DEVICE_IMPL "Device Driver Implement Layer" for gpio to use in implementation code. - * Application developer should use the GPIO API provided here to access to GPIO devices. - * BSP developer should follow the API definition to implement GPIO device drivers. - * @{ - */ -/** - * \brief gpio information struct definition - * \details informations about gpio open count, working status - * gpio registers and control block, gpio io direction and interrupt/poll for each bit of gpio - * \note Only available for gpio with max 32bits - */ -typedef struct dev_gpio_info { - void *gpio_ctrl; /*!< gpio control related pointer, implemented by bsp developer, and this should be set during gpio object implementation */ - uint32_t opn_cnt; /*!< gpio open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */ - uint32_t direction; /*!< each bit direction of this GPIO, default all \ref GPIO_DIR_INPUT "input" for first open */ - uint32_t method; /*!< int/poll method for each bit of GPIO, 0 for poll, 1 for interrupt, default all \ref DEV_POLL_METHOD "poll" for first open */ - void * extra; /*!< a extra pointer to get hook to applications which should not used by bsp developer, - this should be NULL for first open and you can \ref DEV_GPIO_INFO_SET_EXTRA_OBJECT "set" - or \ref DEV_GPIO_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */ -} DEV_GPIO_INFO, * DEV_GPIO_INFO_PTR; -/** Set extra information pointer of gpio info */ -#define DEV_GPIO_INFO_SET_EXTRA_OBJECT(gpio_info_ptr, extra_info) (gpio_info_ptr)->extra = (void *)(extra_info) -/** Get extra information pointer of gpio info */ -#define DEV_GPIO_INFO_GET_EXTRA_OBJECT(gpio_info_ptr) ((gpio_info_ptr)->extra) - -/** Method of all gpio bits set to poll */ -#define DEV_GPIO_BITS_MTHD_POLL (0) -/** Method of all gpio bits set to interrupt */ -#define DEV_GPIO_BITS_MTHD_INTERRUPT (0xFFFFFFFF) -/** Default method of all gpio bits should be poll for first open */ -#define DEV_GPIO_BITS_MTHD_DEFAULT (DEV_GPIO_BITS_MTHD_POLL) - -/** - * \brief gpio device interface definition - * \details define gpio device interface, like gpio information structure, - * fuctions to open/close/control gpio, write or read data via gpio - * \note all this details are implemented by user in user porting code - */ -typedef struct dev_gpio { - DEV_GPIO_INFO gpio_info; /*!< gpio device information */ - int32_t (*gpio_open) (uint32_t dir); /*!< open gpio device with pre-defined gpio direction */ - int32_t (*gpio_close) (void); /*!< close gpio device */ - int32_t (*gpio_control) (uint32_t ctrl_cmd, void *param); /*!< control gpio device */ - int32_t (*gpio_write) (uint32_t val, uint32_t mask); /*!< write gpio device with val, only write the masked bits */ - int32_t (*gpio_read) (uint32_t *val, uint32_t mask); /*!< read gpio device val, only read the masked bits */ -} DEV_GPIO, * DEV_GPIO_PTR; - -/** - * \fn int32_t (* dev_gpio::gpio_open) (uint32_t dir) - * \details Open a gpio device with pre-defined io direction. - * \param[in] dir gpio direction for each bit - * \retval E_OK Open successfully without any issues - * \retval E_OPNED If device was opened before with different parameters, - * then just increase the \ref dev_gpio_info::opn_cnt "opn_cnt" and return \ref E_OPNED - * \retval E_OBJ Device object is not valid - * \retval E_PAR Parameter is not valid - * \retval E_NOSPT Open settings are not supported - */ - -/** - * \fn int32_t (* dev_gpio::gpio_close) (void) - * \details Close an gpio device, just decrease the \ref dev_gpio_info::opn_cnt "opn_cnt", - * if \ref dev_gpio_info::opn_cnt "opn_cnt" equals 0, then close the device - * \retval E_OK Close successfully without any issues(including scenario that device is already closed) - * \retval E_OPNED Device is still opened, the device \ref dev_gpio_info::opn_cnt "opn_cnt" decreased by 1 - * \retval E_OBJ Device object is not valid - */ - -/** - * \fn int32_t (* dev_gpio::gpio_control) (uint32_t ctrl_cmd, void *param) - * \details Control an gpio device by \ref ctrl_cmd, with passed \ref param. - * you can control gpio device using predefined gpio control commands defined using \ref DEV_SET_SYSCMD - * (which must be implemented by bsp developer), such as \ref GPIO_CMD_SET_BIT_DIR_INPUT - * "change masked gpio direction to input", and \ref DEVICE_HAL_GPIO_CTRLCMD "more". - * And you can also control gpio device using your own specified commands defined using \ref DEV_SET_USRCMD, - * but these specified commands should be defined in your own gpio device driver implementation. - * \param[in] ctrl_cmd \ref DEVICE_HAL_GPIO_CTRLCMD "control command", to change or get some thing related to gpio - * \param[in,out] param parameters that maybe argument of the command, or return values of the command - * \retval E_OK Control device successfully - * \retval E_CLSED Device is not opened - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid for current control command - * \retval E_SYS Control device failed, due to hardware issues - * \retval E_CTX Control device failed, due to different reasons like in transfer state - * \retval E_NOSPT Control command is not supported or not valid, such as interrupt is not supported - */ - -/** - * \fn int32_t (* dev_gpio::gpio_write) (uint32_t val, uint32_t mask) - * \details Write gpio with \ref val, and only change the masked bits of gpio. - * \param[in] val the data that need to write to gpio - * \param[in] mask gpio bit mask - * \retval E_OK Write gpio with specified value successfully - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid - */ - -/** - * \fn int32_t (* dev_gpio::gpio_read) (uint32_t *val, uint32_t mask) - * \details Read the masked gpio value - * \param[out] val pointer to data need to read from gpio - * \param[in] mask gpio bit mask - * \retval E_OK Read gpio data successfully - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid - */ - -/** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief get an \ref dev_gpio "gpio device" by gpio device id. - * For how to use gpio device hal refer to \ref dev_gpio "Functions in gpio device structure" - * \param[in] gpio_id id of gpio, defined by user - * \retval !NULL pointer to an \ref dev_gpio "gpio device structure" - * \retval NULL failed to find the gpio device by \ref gpio_id - * \note need to implemented by user in user code - */ -extern DEV_GPIO_PTR gpio_get_dev(int32_t gpio_id); - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif /* _DEVICE_HAL_GPIO_H_ */ diff --git a/bsp/synopsys/embarc/device/device_hal/inc/dev_iic.h b/bsp/synopsys/embarc/device/device_hal/inc/dev_iic.h deleted file mode 100644 index 14106671ffdac11a2e6c83bae2b46dc1ea3d6304..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/device/device_hal/inc/dev_iic.h +++ /dev/null @@ -1,526 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2017.03 - * \date 2014-06-16 - * \author Huaqi Fang(Huaqi.Fang@synopsys.com) ---------------------------------------------- */ - -/** - * \defgroup DEVICE_HAL_IIC IIC Device HAL Interface - * \ingroup DEVICE_HAL_DEF - * \brief definitions for iic device hardware layer (\ref dev_iic.h) - * \details provide interfaces for iic driver to implement - * Here is a diagram for the iic interface. - * - * \htmlonly - *
    - *
    - * IIC Device HAL Interface Diagram - *

    IIC Device HAL Interface Diagram

    - *
    - *
    - * \endhtmlonly - * - * @{ - * - * \file - * \brief iic device hardware layer definitions - * \details provide common definitions for iic device, - * then software developer can develop iic driver - * following this definitions, and the applications - * can directly call this definition to realize functions - */ - -#ifndef _DEVICE_HAL_IIC_H_ -#define _DEVICE_HAL_IIC_H_ - -#include "device/device_hal/inc/dev_common.h" - -/** - * \defgroup DEVICE_HAL_IIC_CFG IIC Related Configurations - * \ingroup DEVICE_HAL_IIC - * \brief Macros for IIC device related configurations. - * @{ - */ -/** IIC Bus possible speed modes */ -typedef enum iic_speed_mode { - IIC_SPEED_STANDARD = 0, /*!< Bidirectional, Standard-mode (Sm), with a bit rate up to 100 kbit/s */ - IIC_SPEED_FAST = 1, /*!< Bidirectional, Fast-mode (Fm), with a bit rate up to 400 kbit/s */ - IIC_SPEED_FASTPLUS = 2, /*!< Bidirectional, Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s */ - IIC_SPEED_HIGH = 3, /*!< Bidirectional, High-speed mode (Hs-mode), with a bit rate up to 3.4 Mbit/s */ - IIC_SPEED_ULTRA = 4 /*!< Unidirectional(Write only), Ultra Fast-mode (UFm), with a bit rate up to 5 Mbit/s */ -} IIC_SPEED_MODE; - -/** IIC next Condition */ -typedef enum iic_next_condtion { - IIC_MODE_STOP = 0, /*!< Send a STOP condition after write/read operation */ - IIC_MODE_RESTART = 1 /*!< Send a RESTART condition after write/read operation */ -} IIC_NEXT_CONDTION; - -/** IIC Error State */ -typedef enum iic_error_state { - IIC_ERR_NONE = 0, /*!< Currently in iic device free state */ - IIC_ERR_LOST_BUS = 1, /*!< Master or slave lost bus during operation */ - IIC_ERR_ADDR_NOACK = 2, /*!< Slave address is sent but not addressed by any slave devices */ - IIC_ERR_DATA_NOACK = 3, /*!< Data in transfer is not acked when it should be acked */ - IIC_ERR_TIMEOUT = 4, /*!< Transfer timeout, no more data is received or sent */ - IIC_ERR_MSTSTOP = 5, /*!< Slave received a STOP condition from master device */ - IIC_ERR_UNDEF = 6 /*!< Undefined error cases */ -} IIC_ERROR_STATE; - -/** IIC Working State */ -typedef enum iic_working_state { - IIC_FREE = 0, /*!< Currently in iic device free state */ - IIC_IN_TX = 1, /*!< Currently in iic master transmit state */ - IIC_IN_RX = 2 /*!< Currently in iic master receive state */ -} IIC_WORKING_STATE; - -/** IIC Addressing Mode */ -typedef enum iic_address_mode { - IIC_7BIT_ADDRESS = 0, /*!< Use 7bit address mode */ - IIC_10BIT_ADDRESS = 1 /*!< Use 10bit address mode */ -} IIC_ADDRESS_MODE; - -/** IIC Slave State */ -typedef enum iic_slave_state { - IIC_SLAVE_STATE_FREE = 0, /*!< None state, in free */ - IIC_SLAVE_STATE_START = (1<<1), /*!< Start or Restart condition, clear it when read */ - IIC_SLAVE_STATE_STOP = (1<<2), /*!< Stop condition, clear it when read */ - IIC_SLAVE_STATE_RD_REQ = (1<<3), /*!< Read request from master, this will trigger the slave transmit callback */ - IIC_SLAVE_STATE_RD_DONE = (1<<4), /*!< Read request done from master, clear it when read */ - IIC_SLAVE_STATE_WR_REQ = (1<<5), /*!< Write request from master, this will trigger the slave receive callback */ - IIC_SLAVE_STATE_GC_REQ = (1<<6), /*!< General call request from master */ - IIC_SLAVE_STATE_ERROR = (1<<7) /*!< Error, clear it when read */ -} IIC_SLAVE_STATE; - -/** 7bit IIC address mask */ -#define IIC_7BIT_ADDRESS_MASK (0x7F) -/** 10bit IIC address mask */ -#define IIC_10BIT_ADDRESS_MASK (0x3FF) -/** @} */ - -/** - * \defgroup DEVICE_HAL_IIC_CTRLCMD IIC Device Control Commands - * \ingroup DEVICE_HAL_IIC - * \brief Definitions for iic control command, used in \ref dev_iic::iic_control "IIC IO Control" - * \details These commands defined here can be used in user code directly. - * - Parameters Usage - * - For passing parameters like integer, just use uint32_t/int32_t to directly pass values - * - For passing parameters for a structure, please use pointer to pass values - * - For getting some data, please use pointer to store the return data - * - Common Return Values - * - \ref E_OK, Control device successfully - * - \ref E_CLSED, Device is not opened - * - \ref E_OBJ, Device object is not valid or not exists - * - \ref E_PAR, Parameter is not valid for current control command - * - \ref E_SYS, Control device failed, due to hardware issues such as device is disabled - * - \ref E_CTX, Control device failed, due to different reasons like in transfer state - * - \ref E_NOSPT, Control command is not supported or not valid - * @{ - */ - -/** Define IIC control commands for common usage */ -#define DEV_SET_IIC_SYSCMD(cmd) DEV_SET_SYSCMD((cmd)) -/** Define IIC control commands for master usage */ -#define DEV_SET_IIC_MST_SYSCMD(cmd) DEV_SET_SYSCMD(0x00004000|(cmd)) -/** Define IIC control commands for slave usage */ -#define DEV_SET_IIC_SLV_SYSCMD(cmd) DEV_SET_SYSCMD(0x00008000|(cmd)) - -/* ++++ Common commands for IIC Device ++++ */ -/** - * Get \ref dev_iic_info::status "current device status" - * - Param type : uint32_t * - * - Param usage : store result of current status - * - Return value explanation : - */ -#define IIC_CMD_GET_STATUS DEV_SET_IIC_SYSCMD(0) -/** - * Set \ref dev_iic_info::addr_mode "iic addressing mode". - * - Param type : uint32_t - * - Param usage : iic addressing mode, possible values can be found \ref IIC_ADDRESS_MODE "here" - * - Return value explanation : - */ -#define IIC_CMD_SET_ADDR_MODE DEV_SET_IIC_SYSCMD(1) -/** - * Set \ref dev_iic_cbs::tx_cb "iic transmit success callback" function - * when all required bytes are transmitted for interrupt method - * - Param type : \ref DEV_CALLBACK * or NULL - * - Param usage : transmit success callback function for iic - * - Return value explanation : - */ -#define IIC_CMD_SET_TXCB DEV_SET_IIC_SYSCMD(2) -/** - * Set \ref dev_iic_cbs::rx_cb "iic receive success callback" function - * when all required bytes are received for interrupt method - * - Param type : \ref DEV_CALLBACK * or NULL - * - Param usage : receive success callback function for iic - * - Return value explanation : - */ -#define IIC_CMD_SET_RXCB DEV_SET_IIC_SYSCMD(3) -/** - * Set \ref dev_iic_cbs::err_cb "iic transfer error callback" function - * when something error happened for interrupt method - * - Param type : \ref DEV_CALLBACK * or NULL - * - Param usage : transfer error callback function for iic - * - Return value explanation : - */ -#define IIC_CMD_SET_ERRCB DEV_SET_IIC_SYSCMD(4) -/** - * Set buffer for interrupt transmit, and it will set \ref dev_iic_info::tx_buf "tx_buf". - * - IIC master mode use case \n - * For master mode, if you set tx buffer to NULL, when tx interrupt is enabled and entered into tx interrupt, - * it will automatically disable the tx interrupt, so when you want to transfer something, you need to set the - * tx buffer to Non-NULL and enable tx interrupt, when the tx buffer is sent, it will disable the tx interrupt - * and call tx callback function if available. - * - IIC slave mode use case \n - * For slave mode, the tx buffer is not used, only tx callback function is used, and if tx callback is not set, - * then it will automatically disable the tx interrupt, if tx callback is set, it will call the tx callback function - * and you need to write or read in the tx callback function, to avoid meaningless waiting, you can use control command - * \ref IIC_CMD_GET_TXAVAIL to get how many bytes space existing in transmit fifo, and use iic_write to send the available - * bytes. - * - Param type : DEV_BUFFER * or NULL - * - Param usage : buffer structure pointer, if param is NULL, then it will set tx_buf to NULL - * - Return value explanation : - */ -#define IIC_CMD_SET_TXINT_BUF DEV_SET_IIC_SYSCMD(5) -/** - * Set buffer for interrupt receive, and it will set \ref dev_iic_info::rx_buf "rx_buf" - * - IIC master mode use case \n - * Similar to \ref IIC_CMD_SET_TXINT_BUF - * - IIC slave mode use case \n - * Similiar to \ref IIC_CMD_SET_TXINT_BUF - * - Param type : DEV_BUFFER * or NULL - * - Param usage : buffer structure pointer, if param is NULL, then it will set rx_buf to NULL - * - Return value explanation : - */ -#define IIC_CMD_SET_RXINT_BUF DEV_SET_IIC_SYSCMD(6) -/** - * Enable or disable transmit interrupt, - * for master mode, only one of tx and rx interrupt can be enabled, - * if tx interrupt is enabled, then rx interrupt can't be changed. - * - Param type : uint32_t - * - Param usage : enable(none-zero) or disable(zero) flag - * - Return value explanation : - */ -#define IIC_CMD_SET_TXINT DEV_SET_IIC_SYSCMD(7) -/** - * Enable or disable receive interrupt, - * for master mode, only one of tx and rx interrupt can be enabled, - * if rx interrupt is enabled, then tx interrupt can't be changed. - * - Param type : uint32_t - * - Param usage : enable(none-zero) or disable(zero) flag - * - Return value explanation : - */ -#define IIC_CMD_SET_RXINT DEV_SET_IIC_SYSCMD(8) -/** - * Abort current interrupt transmit operation if tx interrupt enabled, - * it will disable transmit interrupt, and set \ref DEV_IN_TX_ABRT - * in \ref dev_iic_info::status "status" variable, - * and call the transmit callback function, when tx callback is finished, - * it will clear \ref DEV_IN_TX_ABRT and return - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define IIC_CMD_ABORT_TX DEV_SET_IIC_SYSCMD(9) -/** - * Abort current interrupt receive operation if rx interrupt enabled, - * it will disable receive interrupt, and set \ref DEV_IN_TX_ABRT - * in \ref dev_iic_info::status "status" variable, - * and call the receive callback function, when rx callback is finished, - * it will clear \ref DEV_IN_TX_ABRT and return - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define IIC_CMD_ABORT_RX DEV_SET_IIC_SYSCMD(10) -/** - * Do a software reset for IIC device, it will stop current transfer, - * and clear error state and bring device to normal state, set next condition to STOP - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define IIC_CMD_RESET DEV_SET_IIC_SYSCMD(11) -/** - * Flush iic device transmit buffer or fifo - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define IIC_CMD_FLUSH_TX DEV_SET_IIC_SYSCMD(12) -/** - * Flush iic device receive buffer or fifo - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define IIC_CMD_FLUSH_RX DEV_SET_IIC_SYSCMD(13) -/** - * Enable iic device - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define IIC_CMD_ENA_DEV DEV_SET_IIC_SYSCMD(14) -/** - * Disable iic device, when device is disabled, - * only \ref IIC_CMD_ENA_DEV, \ref IIC_CMD_DIS_DEV, - * \ref IIC_CMD_GET_STATUS and \ref IIC_CMD_RESET - * commands can be executed, other commands will return \ref E_SYS - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define IIC_CMD_DIS_DEV DEV_SET_IIC_SYSCMD(15) -/** - * Get how many bytes space in iic are available to transmit, - * this can be used in interrupt callback functions, - * cooperate with \ref dev_iic::iic_write "iic_write" API to realize non-blocked write - * - Param type : int32_t * - * - Param usage : store the write available bytes, > 0 for available bytes, 0 for not available - * - Return value explaination : - */ -#define IIC_CMD_GET_TXAVAIL DEV_SET_IIC_SYSCMD(16) -/** - * Get how many bytes in iic are available to receive, - * this can be used in interrupt callback functions, - * cooperate with \ref dev_iic::iic_read "iic_read" API to realize non-blocked read - * - Param type : int32_t * - * - Param usage : store the read available bytes, > 0 for available bytes, 0 for not available - * - Return value explanation : - */ -#define IIC_CMD_GET_RXAVAIL DEV_SET_IIC_SYSCMD(17) - -/* ++++ Master only commands for IIC Device ++++ */ -/** - * Set \ref dev_iic_info::speed_mode "iic speed mode". - * - Param type : uint32_t - * - Param usage : iic speed mode, possible values can be found \ref IIC_SPEED_MODE "here", - * and if passing mode is not supported, it will choose a lower supported speed mode - * - Return value explanation : - */ -#define IIC_CMD_MST_SET_SPEED_MODE DEV_SET_IIC_MST_SYSCMD(0) -/** - * Set next condition for following transmit or receive operation. - * For example, you can change next condition before iic_read or iic_write, - * then in iic_read/iic_write operation, it will send a STOP/RESTART condition - * after the last byte of this operation. For interrupt, this is similar. - * - Param type : uint32_t - * - Param usage : next condition can be \ref IIC_NEXT_CONDTION - * - Return value explanation : - */ -#define IIC_CMD_MST_SET_NEXT_COND DEV_SET_IIC_MST_SYSCMD(1) -/** - * Set target slave device address for selecting slave device - * - Param type : uint32_t - * - Param usage : target slave address value - * - Return value explanation : - */ -#define IIC_CMD_MST_SET_TAR_ADDR DEV_SET_IIC_MST_SYSCMD(2) - - -/* ++++ Slave only commands for IIC Device ++++ */ -/** - * Set slave address when working as slave iic device - * - Param type : uint32_t - * - Param usage : slave address value - * - Return value explanation : - */ -#define IIC_CMD_SLV_SET_SLV_ADDR DEV_SET_IIC_SLV_SYSCMD(0) -/** - * Get \ref iic_slave_state "slave state" when working as slave iic device - * - Param type : uint32_t * - * - Param usage : slave state - * - Return value explanation : - */ -#define IIC_CMD_SLV_GET_SLV_STATE DEV_SET_IIC_SLV_SYSCMD(1) - -/** @} */ - -/** - * \defgroup DEVICE_HAL_IIC_CALLBACK IIC Interrupt callback functions - * \ingroup DEVICE_HAL_IIC - * \brief callback function structure for IIC device - * @{ - */ -typedef struct dev_iic_cbs { - DEV_CALLBACK tx_cb; /*!< iic data transmit success required bytes callback */ - DEV_CALLBACK rx_cb; /*!< iic data receive success required bytes callback */ - DEV_CALLBACK err_cb; /*!< iic error callback */ -} DEV_IIC_CBS, *DEV_IIC_CBS_PTR; -/** @} */ - -/** - * \defgroup DEVICE_HAL_IIC_DEVSTRUCT IIC Device Structure - * \ingroup DEVICE_HAL_IIC - * \brief contains definitions of iic device structure. - * \details this structure will be used in user implemented code, which was called - * Device Driver Implement Layer for iic to realize in user code. - * @{ - */ -/** - * \brief iic information struct definition - * \details informations about iic open state, working state, - * baurate, iic registers, working method, interrupt number - */ -typedef struct dev_iic_info { - void *iic_ctrl; /*!< iic control related pointer, implemented by bsp developer, and this should be set during iic object implementation */ - uint32_t opn_cnt; /*!< iic open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */ - uint32_t status; /*!< current working status, refer to \ref DEVICE_HAL_COMMON_DEVSTATUS, this should be \ref DEV_ENABLED for first open */ - uint32_t mode; /*!< current working mode, which can be \ref DEV_MASTER_MODE "master mode" or \ref DEV_SLAVE_MODE "slave mode" */ - uint32_t speed_mode; /*!< current working \ref IIC_SPEED_MODE "iic speed mode" */ - uint32_t cur_state; /*!< \ref IIC_WORKING_STATE "current working state for iic device", this should be \ref IIC_FREE for first open */ - uint32_t err_state; /*!< \ref IIC_ERROR_STATE "current error state for iic device", this should be \ref IIC_ERR_NONE for first open */ - uint32_t addr_mode; /*!< \ref IIC_ADDRESS_MODE "current addressing mode", this should be \ref IIC_7BIT_ADDRESS for first open */ - uint32_t slv_addr; /*!< slave address when working as slave iic device, this should be 0 for first open */ - uint32_t tar_addr; /*!< target slave device address when addressing that slave device, this should be 0 for first open */ - uint32_t next_cond; /*!< \ref IIC_NEXT_CONDTION "next condition for master transmit or receive", \ - possible values are STOP or RESTART, it should be STOP for first open */ - DEV_BUFFER tx_buf; /*!< transmit buffer via interrupt, this should be all zero for first open */ - DEV_BUFFER rx_buf; /*!< receive buffer via interrupt, this should be all zero for first open */ - DEV_IIC_CBS iic_cbs; /*!< iic callbacks, for both master and slave mode, this should be all NULL for first open */ - void *extra; /*!< a extra pointer to get hook to applications which should not used by bsp developer, - this should be NULL for first open and you can \ref DEV_IIC_INFO_SET_EXTRA_OBJECT "set" - or \ref DEV_IIC_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */ -} DEV_IIC_INFO, * DEV_IIC_INFO_PTR; - -/** Set extra information pointer of iic info */ -#define DEV_IIC_INFO_SET_EXTRA_OBJECT(iic_info_ptr, extra_info) (iic_info_ptr)->extra = (void *)(extra_info) -/** Get extra information pointer of iic info */ -#define DEV_IIC_INFO_GET_EXTRA_OBJECT(iic_info_ptr) ((iic_info_ptr)->extra) - -/** - * \brief iic device interface definition - * \details define iic device interface, like iic information structure, - * fuctions to get iic info, open/close/control iic, send/receive data by iic - * \note all this details are implemented by user in user porting code - */ -typedef struct dev_iic { - DEV_IIC_INFO iic_info; /*!< iic device information */ - int32_t (*iic_open) (uint32_t mode, uint32_t param); /*!< open iic device in master/slave mode, \ - when in master mode, param stands for speed mode, \ - when in slave mode, param stands for slave address */ - int32_t (*iic_close) (void); /*!< close iic device */ - int32_t (*iic_control) (uint32_t ctrl_cmd, void *param);/*!< control iic device */ - int32_t (*iic_write) (const void *data, uint32_t len); /*!< send data by iic device (blocking method) */ - int32_t (*iic_read) (void *data, uint32_t len); /*!< read data from iic device (blocking method) */ -} DEV_IIC, * DEV_IIC_PTR; - -/** - * \fn int32_t (* dev_iic::iic_open) (uint32_t mode, uint32_t param) - * \details open an iic device with selected mode (master or slave) with defined \ref param - * \param[in] mode working mode (\ref DEV_MASTER_MODE "master" or \ref DEV_SLAVE_MODE "slave") - * \param[in] param When mode is \ref DEV_MASTER_MODE, param stands for \ref dev_iic_info::speed_mode "speed mode", - * when mode is \ref DEV_SLAVE_MODE, param stands for \ref dev_iic_info::slv_addr "slave device 7bit address" - * \retval E_OK Open successfully without any issues - * \retval E_OPNED If device was opened before with different parameters, - * then just increase the \ref dev_iic_info::opn_cnt "opn_cnt" and return \ref E_OPNED - * \retval E_OBJ Device object is not valid - * \retval E_SYS Device is opened for different mode before, if you want to open it with different mode, you need to fully close it first. - * \retval E_PAR Parameter is not valid - * \retval E_NOSPT Open settings are not supported - */ - -/** - * \fn int32_t (* dev_iic::iic_close) (void) - * \details close an iic device, just decrease the \ref dev_iic_info::opn_cnt "opn_cnt", - * if \ref dev_iic_info::opn_cnt "opn_cnt" equals 0, then close the device - * \retval E_OK Close successfully without any issues(including scenario that device is already closed) - * \retval E_OPNED Device is still opened, the device \ref dev_iic_info::opn_cnt "opn_cnt" decreased by 1 - * \retval E_OBJ Device object is not valid - */ - -/** - * \fn int32_t (* dev_iic::iic_control) (uint32_t ctrl_cmd, void *param) - * \details control an iic device by \ref ctrl_cmd, with passed \ref param. - * you can control iic device using predefined iic control commands defined using \ref DEV_SET_SYSCMD - * (which must be implemented by bsp developer), such as \ref IIC_CMD_SET_SPEED "set iic speed mode", - * \ref IIC_CMD_FLUSH_TX "flush tx" and \ref DEVICE_HAL_IIC_CTRLCMD "more". - * And you can also control iic device using your own specified commands defined using \ref DEV_SET_USRCMD, - * but these specified commands should be defined in your own iic device driver implementation. - * \param[in] ctrl_cmd \ref DEVICE_HAL_IIC_CTRLCMD "control command", to change or get some thing related to iic - * \param[in,out] param parameters that maybe argument of the command, - * or return values of the command, must not be NULL - * \retval E_OK Control device successfully - * \retval E_CLSED Device is not opened - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid for current control command - * \retval E_SYS Control device failed, due to hardware issues, such as device is disabled - * \retval E_CTX Control device failed, due to different reasons like in transfer state - * \retval E_NOSPT Control command is not supported or not valid - */ - -/** - * \fn int32_t (* dev_iic::iic_write) (const void *data, uint32_t len) - * \details send \ref data through iic with defined \ref len to slave device which slave address is \ref slv_addr. - * \param[in] data pointer to data need to send by iic - * \param[in] len length of data to be sent - * \retval >0 Byte count that was successfully sent for poll method, - * it might can't send that much due to \ref \ref dev_iic_info::err_state "different error state". - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid - * \retval E_CTX Device is still in transfer state - * \retval E_SYS Can't write data to hardware due to hardware issues, such as device is disabled - */ - -/** - * \fn int32_t (* dev_iic::iic_read) (void *data, uint32_t len) - * \details receive \ref data of defined \ref len through iic from slave device which slave address is \ref slv_addr. - * \param[out] data pointer to data need to received by iic - * \param[in] len length of data to be received - * \retval >0 Byte count that was successfully received for poll method, - * it might can't send that much due to \ref \ref dev_iic_info::err_state "different error state". - * \retval E_OBJ Device object is not valid or not exists - * \retval E_CTX Device is still in transfer state - * \retval E_PAR Parameter is not valid - * \retval E_SYS Can't receive data from hardware due to hardware issues, such as device is disabled - */ -/** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief get an \ref dev_iic "iic device" by iic device id. - * For how to use iic device hal refer to \ref DEVICE_HAL_IIC_DEVSTRUCT "Functions in iic device structure" - * \param[in] iic_id id of iic, defined by user - * \retval !NULL pointer to an \ref dev_iic "iic device structure" - * \retval NULL failed to find the iic device by \ref iic_id - * \note need to implemented by user in user code - */ -extern DEV_IIC_PTR iic_get_dev(int32_t iic_id); - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif /* _DEVICE_HAL_IIC_H_ */ diff --git a/bsp/synopsys/embarc/device/device_hal/inc/dev_spi.h b/bsp/synopsys/embarc/device/device_hal/inc/dev_spi.h deleted file mode 100644 index 4469654e5452329436badd2bc0df866c3e4f6735..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/device/device_hal/inc/dev_spi.h +++ /dev/null @@ -1,577 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2017.03 - * \date 2014-06-16 - * \author Huaqi Fang(Huaqi.Fang@synopsys.com) ---------------------------------------------- */ - -/** - * \defgroup DEVICE_HAL_SPI SPI Device HAL Interface - * \ingroup DEVICE_HAL_DEF - * \brief definitions for spi device hardware layer (\ref dev_spi.h) - * \details provide interfaces for spi driver to implement - * Here is a diagram for the spi interface. - * - * \htmlonly - *
    - *
    - * SPI Device HAL Interface Diagram - *

    SPI Device HAL Interface Diagram

    - *
    - *
    - * \endhtmlonly - * - * @{ - * - * \file - * \brief spi device hardware layer definitions - * \details provide common definitions for spi device, - * then software developer can develop spi driver - * following this definitions, and the applications - * can directly call this definition to realize functions - */ - -#ifndef _DEVICE_HAL_SPI_H_ -#define _DEVICE_HAL_SPI_H_ - -#include "device/device_hal/inc/dev_common.h" - - -/** - * \defgroup DEVICE_HAL_SPI_CTRLCMD SPI Device Control Commands - * \ingroup DEVICE_HAL_SPI - * \brief Definitions for spi control command, used in \ref dev_spi::spi_control "SPI IO Control" - * \details These commands defined here can be used in user code directly. - * - Parameters Usage - * - For passing parameters like integer, just use uint32_t/int32_t to directly pass values - * - For passing parameters for a structure, please use pointer to pass values - * - For getting some data, please use pointer to store the return data - * - Common Return Values - * - \ref E_OK, Control device successfully - * - \ref E_CLSED, Device is not opened - * - \ref E_OBJ, Device object is not valid or not exists - * - \ref E_PAR, Parameter is not valid for current control command - * - \ref E_SYS, Control device failed, due to hardware issues such as device is disabled - * - \ref E_CTX, Control device failed, due to different reasons like in transfer state - * - \ref E_NOSPT, Control command is not supported or not valid - * - Usage Comment - * - For SPI poll or interrupt read/write/transfer operations, only 1 operation can be triggered. - * If there is a operation is running, any other operation will return \ref E_CTX - * - If SPI is in transfer, then the following operations may return \ref E_CTX. Like - * \ref SPI_CMD_SET_CLK_MODE, \ref SPI_CMD_SET_TXINT_BUF, \ref SPI_CMD_SET_RXINT_BUF, - * \ref SPI_CMD_SET_TXINT, \ref SPI_CMD_SET_RXINT, \ref SPI_CMD_ABORT_TX, \ref SPI_CMD_ABORT_RX, - * \ref SPI_CMD_FLUSH_TX, \ref SPI_CMD_FLUSH_RX, \ref SPI_CMD_SET_DFS, \ref SPI_CMD_TRANSFER_POLLING, - * \ref SPI_CMD_TRANSFER_INT, \ref SPI_CMD_ABORT_XFER, \ref SPI_CMD_MST_SEL_DEV, \ref SPI_CMD_MST_DSEL_DEV, - * \ref SPI_CMD_MST_SET_FREQ and \ref dev_spi::spi_write "SPI Poll Write" or \ref dev_spi::spi_read "SPI Poll Read". - * @{ - */ - -/** Define SPI control commands for common usage */ -#define DEV_SET_SPI_SYSCMD(cmd) DEV_SET_SYSCMD((cmd)) -/** Define SPI control commands for master usage */ -#define DEV_SET_SPI_MST_SYSCMD(cmd) DEV_SET_SYSCMD(0x00001000|(cmd)) -/** Define SPI control commands for slave usage */ -#define DEV_SET_SPI_SLV_SYSCMD(cmd) DEV_SET_SYSCMD(0x00002000|(cmd)) - - -/* ++++ Common commands for SPI Device ++++ */ -/** - * Get \ref dev_spi_info::status "current device status" - * - Param type : uint32_t * - * - Param usage : store result of current status - * - Return value explanation : - */ -#define SPI_CMD_GET_STATUS DEV_SET_SPI_SYSCMD(0) -/** - * set the \ref dev_spi_info::clk_mode "clock mode" of spi transfer - * - Param type : uint32_t - * - Param usage : spi clock mode to choose clock phase and clock polarity - * - Return value explanation : - */ -#define SPI_CMD_SET_CLK_MODE DEV_SET_SPI_SYSCMD(1) -/** - * set spi \ref dev_spi_info::dfs "data frame size" - * - Param type : uint32_t - * - Param usage : should > 0 - * - Return value explanation : If dfs is not supported, then return \ref E_SYS - */ -#define SPI_CMD_SET_DFS DEV_SET_SPI_SYSCMD(2) -/** - * set the \ref dev_spi_info::dummy "dummy data" during spi transfer - * - Param type : uint32_t - * - Param usage : dummy data to transfer - * - Return value explanation : - */ -#define SPI_CMD_SET_DUMMY_DATA DEV_SET_SPI_SYSCMD(3) -/** - * Set \ref dev_spi_cbs::tx_cb "spi transmit success callback" function - * when all required bytes are transmitted for interrupt method - * - Param type : \ref DEV_CALLBACK * or NULL - * - Param usage : transmit success callback function for spi - * - Return value explanation : - */ -#define SPI_CMD_SET_TXCB DEV_SET_SPI_SYSCMD(4) -/** - * Set \ref dev_spi_cbs::rx_cb "spi receive success callback" function - * when all required bytes are received for interrupt method - * - Param type : \ref DEV_CALLBACK * or NULL - * - Param usage : receive success callback function for spi - * - Return value explanation : - */ -#define SPI_CMD_SET_RXCB DEV_SET_SPI_SYSCMD(5) -/** - * Set \ref dev_spi_cbs::xfer_cb "spi transfer success callback" function - * when all required transfer are done for interrupt method - * - Param type : \ref DEV_CALLBACK * or NULL - * - Param usage : transfer success callback function for spi - * - Return value explanation : - */ -#define SPI_CMD_SET_XFERCB DEV_SET_SPI_SYSCMD(6) -/** - * Set \ref dev_spi_cbs::err_cb "spi transfer error callback" function - * when something error happened for interrupt method - * - Param type : \ref DEV_CALLBACK * or NULL - * - Param usage : transfer error callback function for spi - * - Return value explanation : - */ -#define SPI_CMD_SET_ERRCB DEV_SET_SPI_SYSCMD(7) -/** - * Set buffer in interrupt transmit, and it will set \ref dev_spi_info::xfer "spi tranfer". - * - SPI master and slave mode use case \n - * For both master and slave mode, if you set tx buffer to NULL, when tx interrupt is enabled and entered into tx interrupt, - * it will automatically disable the tx interrupt, so when you want to transfer something, you need to set the - * tx buffer to Non-NULL and enable tx interrupt, when the tx buffer is sent, it will disable the tx interrupt - * and call tx callback function if available. - * - Param type : DEV_BUFFER * or NULL - * - Param usage : buffer structure pointer, if param is NULL, then it will set xfer to empty - * - Return value explanation : - */ -#define SPI_CMD_SET_TXINT_BUF DEV_SET_SPI_SYSCMD(8) -/** - * Set buffer in interrupt receive, and it will set \ref dev_spi_info::xfer "spi tranfer". - * - SPI master mode use case \n - * Similar to \ref SPI_CMD_SET_TXINT_BUF - * - SPI slave mode use case \n - * Similiar to \ref SPI_CMD_SET_TXINT_BUF - * - Param type : DEV_BUFFER * or NULL - * - Param usage : buffer structure pointer, if param is NULL, then it will set xfer to empty - * - Return value explanation : - */ -#define SPI_CMD_SET_RXINT_BUF DEV_SET_SPI_SYSCMD(9) -/** - * Enable or disable transmit interrupt, - * for master mode, only one of tx and rx interrupt can be enabled, - * if tx interrupt is enabled, then rx interrupt can't be enabled. - * - Param type : uint32_t - * - Param usage : enable(none-zero) or disable(zero) flag - * - Return value explanation : - */ -#define SPI_CMD_SET_TXINT DEV_SET_SPI_SYSCMD(10) -/** - * Enable or disable receive interrupt, - * for master mode, only one of tx and rx interrupt can be enabled, - * if rx interrupt is enabled, then tx interrupt can't be enabled. - * - Param type : uint32_t - * - Param usage : enable(none-zero) or disable(zero) flag - * - Return value explanation : - */ -#define SPI_CMD_SET_RXINT DEV_SET_SPI_SYSCMD(11) -/** - * start the transfer by polling - * - Param type : \ref DEV_SPI_TRANSFER * - * - Param usage : - * - Return value explanation : - */ -#define SPI_CMD_TRANSFER_POLLING DEV_SET_SPI_SYSCMD(12) -/** - * start the transfer by interrupt - * - Param type : \ref DEV_SPI_TRANSFER * or NULL - * - Param usage : If NULL, it will disable transfer interrupt, if not NULL, it will enable transfer interrupt - * - Return value explanation : - */ -#define SPI_CMD_TRANSFER_INT DEV_SET_SPI_SYSCMD(13) -/** - * Abort current interrupt transmit operation if tx interrupt enabled, - * it will disable transmit interrupt, and set \ref DEV_IN_TX_ABRT - * in \ref dev_spi_info::status "status" variable, - * and call the transmit callback function, when tx callback is finished, - * it will clear \ref DEV_IN_TX_ABRT and return - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define SPI_CMD_ABORT_TX DEV_SET_SPI_SYSCMD(14) -/** - * Abort current interrupt receive operation if rx interrupt enabled, - * it will disable receive interrupt, and set \ref DEV_IN_TX_ABRT - * in \ref dev_spi_info::status "status" variable, - * and call the receive callback function, when rx callback is finished, - * it will clear \ref DEV_IN_TX_ABRT and return - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define SPI_CMD_ABORT_RX DEV_SET_SPI_SYSCMD(15) -/** - * Abort current interrupt transfer operation if transfer is issued, - * it will disable transfer interrupt, and set \ref DEV_IN_XFER_ABRT - * in \ref dev_spi_info::status "status" variable, - * and call the transfer callback function, when xfer callback is finished, - * it will clear \ref DEV_IN_XFER_ABRT and return - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define SPI_CMD_ABORT_XFER DEV_SET_SPI_SYSCMD(16) -/** - * Do a software reset for SPI device, it will stop current transfer, - * and clear error state and bring device to normal state, set next condition to STOP - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define SPI_CMD_RESET DEV_SET_SPI_SYSCMD(17) -/** - * Flush spi tx fifo, this will clear the data in tx fifo - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define SPI_CMD_FLUSH_TX DEV_SET_SPI_SYSCMD(18) -/** - * Flush spi rx fifo, this will clear the data in rx fifo - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define SPI_CMD_FLUSH_RX DEV_SET_SPI_SYSCMD(19) -/** - * Enable spi device - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define SPI_CMD_ENA_DEV DEV_SET_SPI_SYSCMD(20) -/** - * Disable spi device, when device is disabled, - * only \ref SPI_CMD_ENA_DEV, \ref SPI_CMD_DIS_DEV, - * \ref SPI_CMD_GET_STATUS and \ref SPI_CMD_RESET - * commands can be executed, other commands will return \ref E_SYS - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define SPI_CMD_DIS_DEV DEV_SET_SPI_SYSCMD(21) -/** - * Get how many bytes space in spi are available to transmit, - * this can be used in interrupt callback functions, - * cooperate with \ref dev_spi::spi_write "spi_write" API to realize non-blocked write - * - Param type : int32_t * - * - Param usage : store the write available bytes, > 0 for available bytes, 0 for not available - * - Return value explanation : - */ -#define SPI_CMD_GET_TXAVAIL DEV_SET_SPI_SYSCMD(22) -/** - * Get how many bytes in spi are available to receive, - * this can be used in interrupt callback functions, - * cooperate with \ref dev_spi::spi_read "spi_read" API to realize non-blocked read - * - Param type : int32_t * - * - Param usage : store the read available bytes, > 0 for available bytes, 0 for not available - * - Return value explanation : - */ -#define SPI_CMD_GET_RXAVAIL DEV_SET_SPI_SYSCMD(23) - - -/* ++++ Master only commands for SPI Device ++++ */ -/** - * select spi slave device - * - Param type : uint32_t - * - Param usage : the number of spi slave device to select - * - Return value explanation : return \ref E_SYS when selection can't be done, return \ref E_CTX during transfer - */ -#define SPI_CMD_MST_SEL_DEV DEV_SET_SPI_MST_SYSCMD(0) -/** - * de-select spi slave device - * - Param type : uint32_t - * - Param usage : the number of spi slave device to de-select - * - Return value explanation : return \ref E_SYS when selection can't be done, return \ref E_CTX during transfer - */ -#define SPI_CMD_MST_DSEL_DEV DEV_SET_SPI_MST_SYSCMD(1) - /** - * Set \ref dev_spi_info::freq "spi frequency". - * - Param type : uint32_t - * - Param usage : spi freq - * - Return value explanation : no return - */ -#define SPI_CMD_MST_SET_FREQ DEV_SET_SPI_MST_SYSCMD(2) - - -/* ++++ Slave only commands for SPI Device ++++ */ - -/* \todo add spi slave related CMDs */ - -/** @} */ - -/** - * \defgroup DEVICE_HAL_SPI_CALLBACK SPI Interrupt callback functions - * \ingroup DEVICE_HAL_SPI - * \brief callback function structure for SPI device - * @{ - */ -typedef struct dev_spi_cbs { - DEV_CALLBACK tx_cb; /*!< spi data transmit success required bytes callback */ - DEV_CALLBACK rx_cb; /*!< spi data receive success required bytes callback */ - DEV_CALLBACK err_cb; /*!< spi error callback */ - DEV_CALLBACK xfer_cb; /*!< transfer callback */ -} DEV_SPI_CBS, *DEV_SPI_CBS_PTR; -/** @} */ - -/** SPI Clock Mode */ -typedef enum spi_clk_mode { - SPI_CPOL_0_CPHA_0 = 0, /*!< Inactive state of serial clock is low, serial clock toggles in middle of first data bit */ - SPI_CPOL_0_CPHA_1 = 1, /*!< Inactive state of serial clock is low, serial clock toggles at start of first data bit */ - SPI_CPOL_1_CPHA_0 = 2, /*!< Inactive state of serial clock is high, serial clock toggles in middle of first data bit */ - SPI_CPOL_1_CPHA_1 = 3, /*!< Inactive state of serial clock is high, serial clock toggles at start of first data bit */ - - SPI_CLK_MODE_0 = SPI_CPOL_0_CPHA_0, /*!< Equal to \ref SPI_CPOL_0_CPHA_0 */ - SPI_CLK_MODE_1 = SPI_CPOL_0_CPHA_1, /*!< Equal to \ref SPI_CPOL_0_CPHA_1 */ - SPI_CLK_MODE_2 = SPI_CPOL_1_CPHA_0, /*!< Equal to \ref SPI_CPOL_1_CPHA_0 */ - SPI_CLK_MODE_3 = SPI_CPOL_1_CPHA_1 /*!< Equal to \ref SPI_CPOL_1_CPHA_1 */ -} SPI_CLK_MODE; - -#define SPI_CLK_MODE_DEFAULT SPI_CPOL_0_CPHA_0 /*!< Default SPI device clock mode */ - -/** - * \defgroup DEVICE_HAL_SPI_DEVSTRUCT SPI Device Structure - * \ingroup DEVICE_HAL_SPI - * \brief contains definitions of spi device structure. - * \details this structure will be used in user implemented code, which was called - * Device Driver Implement Layer for spi to realize in user code. - * @{ - */ -typedef struct dev_spi_transfer DEV_SPI_TRANSFER, *DEV_SPI_TRANSFER_PTR; -/** - * \brief spi read and write data structure used by \ref SPI_CMD_TRANSFER - * spi write then read data - * - */ -struct dev_spi_transfer { - DEV_SPI_TRANSFER *next; - /* Calc by software */ - /** tot_len = (tx_totlen>rx_totlen)?tx_totlen:rx_totlen */ - uint32_t tot_len; - /* Set by user */ - uint8_t *tx_buf; - uint32_t tx_ofs; - uint32_t tx_len; - uint8_t *rx_buf; - uint32_t rx_ofs; - uint32_t rx_len; - /* Should auto set to proper value during set buffer value */ - uint32_t tx_idx; - uint32_t tx_totlen; /** tx_totlen = tx_len + tx_ofs */ - uint32_t rx_idx; - uint32_t rx_totlen; /** rx_totlen = rx_len + rx_ofs */ -}; - -/** Set tx buffer of device spi transfer */ -#define DEV_SPI_XFER_SET_TXBUF(xfer, buf, ofs, len) { \ - (xfer)->tx_buf = (uint8_t *)(buf); \ - (xfer)->tx_len = (uint32_t)(len); \ - (xfer)->tx_ofs = (uint32_t)(ofs); \ - (xfer)->tx_idx = 0; \ - (xfer)->tx_totlen = ( (uint32_t)(len) \ - + (uint32_t)(ofs) ) ; \ - } - -/** Set rx buffer of device spi transfer */ -#define DEV_SPI_XFER_SET_RXBUF(xfer, buf, ofs, len) { \ - (xfer)->rx_buf = (uint8_t *)(buf); \ - (xfer)->rx_len = (uint32_t)(len); \ - (xfer)->rx_ofs = (uint32_t)(ofs); \ - (xfer)->rx_idx = 0; \ - (xfer)->rx_totlen = ( (uint32_t)(len) \ - + (uint32_t)(ofs) ) ; \ - } - -/** Calculate total length of current transfer without next transfer */ -#define DEV_SPI_XFER_CALC_TOTLEN(xfer) (xfer)->tot_len = \ - ((xfer)->tx_totlen > (xfer)->rx_totlen) ? (xfer)->tx_totlen : (xfer)->rx_totlen ; - -/** Set next SPI transfer */ -#define DEV_SPI_XFER_SET_NEXT(xfer, next_xfer) (xfer)->next = (next_xfer); - -/** Init spi transfer */ -#define DEV_SPI_XFER_INIT(xfer) { \ - (xfer)->tx_idx = 0; \ - (xfer)->rx_idx = 0; \ - (xfer)->tx_totlen = ((xfer)->tx_len \ - + (xfer)->tx_ofs) ; \ - (xfer)->rx_totlen = ((xfer)->rx_len \ - + (xfer)->rx_ofs) ; \ - DEV_SPI_XFER_CALC_TOTLEN(xfer); \ - } -/** - * \brief spi information struct definition - * \details informations about spi open state, working state, - * frequency, spi registers, working method, interrupt number - */ -typedef struct dev_spi_info { - void *spi_ctrl; /*!< spi control related */ - uint32_t status; /*!< current working status, refer to \ref DEVICE_HAL_COMMON_DEVSTATUS, this should be \ref DEV_ENABLED for first open */ - uint32_t freq; /*!< spi working baudrate */ - uint8_t mode; /*!< spi working mode (master/slave) */ - uint8_t clk_mode; /*!< spi clock phase and polarity, this should be \ref SPI_CLK_MODE_DEFAULT for first open */ - uint8_t opn_cnt; /*!< spi open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */ - uint8_t slave; /*!< current selected slave device no, start from 0, this should be \ref SPI_SLAVE_NOT_SELECTED for first open */ - uint8_t dfs; /*!< data frame size, this should be \ref SPI_DFS_DEFAULT for first open */ - - DEV_SPI_TRANSFER xfer; /*!< spi transfer, this should be set to all zero for first open */ - DEV_SPI_CBS spi_cbs; /*!< spi callbacks, for both master and slave mode, this should be all NULL for first open */ - void *extra; /*!< a extra pointer to get hook to applications which should not used by bsp developer, - this should be NULL for first open and you can \ref DEV_SPI_INFO_SET_EXTRA_OBJECT "set" - or \ref DEV_SPI_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */ - uint32_t dummy; /*!< dummy write data when send and receive, this should be \ref SPI_DUMMY_DEFAULT for first open */ -} DEV_SPI_INFO, * DEV_SPI_INFO_PTR; - -/** Set extra information pointer of spi info */ -#define DEV_SPI_INFO_SET_EXTRA_OBJECT(spi_info_ptr, extra_info) (spi_info_ptr)->extra = (void *)(extra_info) -/** Get extra information pointer of spi info */ -#define DEV_SPI_INFO_GET_EXTRA_OBJECT(spi_info_ptr) ((spi_info_ptr)->extra) - -#define SPI_DFS_DEFAULT 8 /*!< Default spi data frame size */ -#define SPI_SLAVE_NOT_SELECTED (0xFF) /*!< Slave is not selected */ -#define SPI_DUMMY_DEFAULT (0xFF) /*!< default dummy value for first open */ - -/** - * \brief spi device interface definition - * \details define spi device interface, like spi information structure, - * fuctions to get spi info, open/close/control spi, send/receive data by spi - * \note all this details are implemented by user in user porting code - */ -typedef struct dev_spi { - DEV_SPI_INFO spi_info; /*!< spi device information */ - int32_t (*spi_open) (uint32_t mode, uint32_t param); /*!< open spi device in master/slave mode, \ - when in master mode, param stands for frequency, \ - when in slave mode, param stands for clock mode */ - int32_t (*spi_close) (void); /*!< close spi device */ - int32_t (*spi_control) (uint32_t ctrl_cmd, void *param); /*!< control spi device */ - int32_t (*spi_write) (const void *data, uint32_t len); /*!< send data to spi device (blocking method) */ - int32_t (*spi_read) (void *data, uint32_t len); /*!< read data from spi device (blocking method) */ -} DEV_SPI, * DEV_SPI_PTR; - -/** - * \fn int32_t (* dev_spi::spi_open) (uint32_t mode, uint32_t param) - * \details open an spi device with selected mode (master or slave) with defined \ref param - * \param[in] mode working mode (\ref DEV_MASTER_MODE "master" or \ref DEV_SLAVE_MODE "slave") - * \param[in] param When mode is \ref DEV_MASTER_MODE, param stands for \ref dev_spi_info::freq "frequency", - * when mode is \ref DEV_SLAVE_MODE, param stands for \ref dev_spi_info::clk_mode "slave clock mode" - * \retval E_OK Open successfully without any issues - * \retval E_OPNED If device was opened before with different parameters, - * then just increase the \ref dev_spi_info::opn_cnt "opn_cnt" and return \ref E_OPNED - * \retval E_OBJ Device object is not valid - * \retval E_SYS Device is opened for different mode before, if you want to open it with different mode, you need to fully close it first. - * \retval E_PAR Parameter is not valid - * \retval E_NOSPT Open settings are not supported - */ - -/** - * \fn int32_t (* dev_spi::spi_close) (void) - * \details close an spi device, just decrease the \ref dev_spi_info::opn_cnt "opn_cnt", - * if \ref dev_spi_info::opn_cnt "opn_cnt" equals 0, then close the device - * \retval E_OK Close successfully without any issues(including scenario that device is already closed) - * \retval E_OPNED Device is still opened, the device \ref dev_spi_info::opn_cnt "opn_cnt" decreased by 1 - * \retval E_OBJ Device object is not valid - */ - -/** - * \fn int32_t (* dev_spi::spi_control) (uint32_t ctrl_cmd, void *param) - * \details control an spi device by \ref ctrl_cmd, with passed \ref param. - * you can control spi device using predefined spi control commands defined using \ref DEV_SET_SYSCMD - * (which must be implemented by bsp developer), such as \ref SPI_CMD_MST_SET_FREQ "set spi master frequency", - * \ref SPI_CMD_FLUSH_TX "flush tx" and \ref DEVICE_HAL_SPI_CTRLCMD "more". - * And you can also control spi device using your own specified commands defined using \ref DEV_SET_USRCMD, - * but these specified commands should be defined in your own spi device driver implementation. - * \param[in] ctrl_cmd \ref DEVICE_HAL_SPI_CTRLCMD "control command", to change or get some thing related to spi - * \param[in,out] param parameters that maybe argument of the command, - * or return values of the command, must not be NULL - * \retval E_OK Control device successfully - * \retval E_CLSED Device is not opened - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid for current control command - * \retval E_SYS Control device failed, due to hardware issues, such as device is disabled - * \retval E_CTX Control device failed, due to different reasons like in transfer state - * \retval E_NOSPT Control command is not supported or not valid - */ - -/** - * \fn int32_t (* dev_spi::spi_write) (const void *data, uint32_t len) - * \details send \ref data through spi with defined \ref len to slave device . - * \param[in] data pointer to data need to send by spi - * \param[in] len length of data to be sent - * \retval >0 Byte count that was successfully sent for poll method - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid - * \retval E_CTX Device is still in transfer state - * \retval E_SYS Can't write data to hardware due to hardware issues, such as device is disabled - */ - -/** - * \fn int32_t (* dev_spi::spi_read) (void *data, uint32_t len) - * \details receive \ref data of defined \ref len through spi from slave device . - * \param[out] data pointer to data need to received by spi - * \param[in] len length of data to be received - * \retval >0 Byte count that was successfully received for poll method - * \retval E_OBJ Device object is not valid or not exists - * \retval E_CTX Device is still in transfer state - * \retval E_PAR Parameter is not valid - * \retval E_SYS Can't receive data from hardware due to hardware issues, such as device is disabled - */ -/** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief get an \ref dev_spi "spi device" by spi device id. - * For how to use spi device hal refer to \ref dev_spi "Functions in spi device structure" - * \param[in] spi_id id of spi, defined by user - * \retval !NULL pointer to an \ref dev_spi "spi device structure" - * \retval NULL failed to find the spi device by \ref spi_id - * \note need to implemented by user in user code - */ -extern DEV_SPI_PTR spi_get_dev(int32_t spi_id); - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif /* _DEVICE_HAL_SPI_H_ */ diff --git a/bsp/synopsys/embarc/device/device_hal/inc/dev_uart.h b/bsp/synopsys/embarc/device/device_hal/inc/dev_uart.h deleted file mode 100644 index c8e17d64212b9edbeb4c764503ffb5aae340aee9..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/device/device_hal/inc/dev_uart.h +++ /dev/null @@ -1,475 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-06-16 - * \author Huaqi Fang(Huaqi.Fang@synopsys.com) ---------------------------------------------- */ - -/** - * \defgroup DEVICE_HAL_UART UART Device HAL Interface - * \ingroup DEVICE_HAL_DEF - * \brief Definitions for uart device hardware layer (\ref dev_uart.h) - * \details Provide unified APIs for uart driver to implement. - * Here is a diagram for the uart interface. - * - * \htmlonly - *
    - *
    - * UART Device HAL Interface Diagram - *

    UART Device HAL Interface Diagram

    - *
    - *
    - * \endhtmlonly - * - * ### Reference Links - * * [Serial Port](https://en.wikipedia.org/wiki/Serial_port) - * - * @{6 - * - * \file - * \brief uart device hardware layer definitions - * \details Provide common definitions for uart device, - * then software developer can develop uart driver - * following this definitions, and the applications - * can directly call this definition to realize functions - * - */ - -#ifndef _DEVICE_HAL_UART_H_ -#define _DEVICE_HAL_UART_H_ - -#include "device/device_hal/inc/dev_common.h" - -/** - * \defgroup DEVICE_HAL_UART_BAUD UART Device Baudrate Definitions - * \ingroup DEVICE_HAL_UART - * \brief Macros for uart baudrate. - * \details Definitions for baudrate from 4800 to 115200bps. - * @{ - */ -/* - * defines for uart baudrates - */ -#define UART_BAUDRATE_110 (110) /*!< uart baudrate 110bps */ -#define UART_BAUDRATE_300 (300) /*!< uart baudrate 300bps */ -#define UART_BAUDRATE_600 (600) /*!< uart baudrate 600bps */ -#define UART_BAUDRATE_1200 (1200) /*!< uart baudrate 1200bps */ -#define UART_BAUDRATE_2400 (2400) /*!< uart baudrate 2400bps */ -#define UART_BAUDRATE_4800 (4800) /*!< uart baudrate 4800bps */ -#define UART_BAUDRATE_9600 (9600) /*!< uart baudrate 9600bps */ -#define UART_BAUDRATE_14400 (14400) /*!< uart baudrate 14400bps */ -#define UART_BAUDRATE_19200 (19200) /*!< uart baudrate 19200bps */ -#define UART_BAUDRATE_38400 (38400) /*!< uart baudrate 38400bps */ -#define UART_BAUDRATE_57600 (57600) /*!< uart baudrate 57600bps */ -#define UART_BAUDRATE_115200 (115200) /*!< uart baudrate 115200bps */ -#define UART_BAUDRATE_230400 (230400) /*!< uart baudrate 230400bps */ -#define UART_BAUDRATE_460800 (460800) /*!< uart baudrate 460800bps */ -#define UART_BAUDRATE_921600 (921600) /*!< uart baudrate 921600bps */ -/** @} */ - -/** - * \defgroup DEVICE_HAL_UART_FORMAT UART Device Format Definitions - * \ingroup DEVICE_HAL_UART - * \brief Macros for uart format. - * \details Definitions for uart format like databits, parity, stopbits. - * @{ - */ -/** - * UART Device Parity Types Enum - */ -typedef enum { - UART_PARITY_NONE = 0, /*!< no parity bit */ - UART_PARITY_ODD = 1, /*!< odd parity bit */ - UART_PARITY_EVEN = 2, /*!< even parity bit */ - UART_PARITY_MARK = 3, /*!< mark parity bit, always logical 1 */ - UART_PARITY_SPACE = 4 /*!< space parity bit, always logical 0 */ -} UART_PARITY; - -/** - * UART Device Stop Bits Enum - */ -typedef enum { - UART_STPBITS_ONE = 0, /*!< 1 stop bit */ - UART_STPBITS_ONEHALF = 1, /*!< 1.5 stop bits */ - UART_STPBITS_TWO = 2 /*!< 2 stop bits */ -} UART_STOPBITS; - -/** - * UART DPS Format: databits/parity/stopbits - */ -typedef struct uart_dps_format { - uint32_t databits; /*!< data bits */ - UART_PARITY parity; /*!< parity bit type */ - UART_STOPBITS stopbits; /*!< stop bits */ -} UART_DPS_FORMAT; - -#define UART_DATABITS_DEFAULT 8 /*!< default data bits */ - -/** Default UART DPS format */ -static const UART_DPS_FORMAT dps_format_default = {UART_DATABITS_DEFAULT, UART_PARITY_NONE, UART_STPBITS_ONE}; -/** @} */ - -/** - * UART Device Hardware Flow Control Types Enum - */ -typedef enum { - UART_FC_NONE = 0, /*!< Non hardware flow control */ - UART_FC_RTS = 1, /*!< Request To Send */ - UART_FC_CTS = 2, /*!< Clear To Send */ - UART_FC_BOTH = 3 /*!< Both hardware flow control methods */ -} UART_HW_FLOW_CONTROL; -/** Default hardware flow control method */ -static const UART_HW_FLOW_CONTROL hwfc_default = UART_FC_NONE; - -/** - * \defgroup DEVICE_HAL_UART_CTRLCMD UART Device Control Commands - * \ingroup DEVICE_HAL_UART - * \brief Definitions for uart control command, used in \ref dev_uart::uart_control "UART IO Control" - * \details These commands defined here can be used in user code directly. - * - Parameters Usage - * - For passing parameters like integer, just use uint32_t/int32_t to directly pass values - * - For passing parameters for a structure, please use pointer to pass values - * - For getting some data, please use pointer to store the return data - * - Common Return Values - * - \ref E_OK, Control device successfully - * - \ref E_CLSED, Device is not opened - * - \ref E_OBJ, Device object is not valid or not exists - * - \ref E_PAR, Parameter is not valid for current control command - * - \ref E_SYS, Control device failed, due to hardware issues such as device is disabled - * - \ref E_CTX, Control device failed, due to different reasons like in transfer state - * - \ref E_NOSPT, Control command is not supported or not valid - * @{ - */ -/** - * Set \ref dev_uart_info::baudrate "uart baudrate". - * - Param type : uint32_t - * - Param usage : uart baudrate, must above zero. Here is a list of \ref DEVICE_HAL_UART_BAUD "possible baudrates" - * - Return value explanation : - */ -#define UART_CMD_SET_BAUD DEV_SET_SYSCMD(0) -/** - * Get \ref dev_uart_info::status "current device status" - * - Param type : uint32_t * - * - Param usage : store result of current status - * - Return value explanation : - */ -#define UART_CMD_GET_STATUS DEV_SET_SYSCMD(1) -/** - * Enable uart device - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define UART_CMD_ENA_DEV DEV_SET_SYSCMD(2) -/** - * Disable uart device, when device is disabled, - * only \ref UART_CMD_ENA_DEV, \ref UART_CMD_DIS_DEV and - * \ref UART_CMD_GET_STATUS commands can be executed, - * other commands will return \ref E_SYS - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define UART_CMD_DIS_DEV DEV_SET_SYSCMD(3) -/** - * Flush uart device output - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define UART_CMD_FLUSH_OUTPUT DEV_SET_SYSCMD(4) -/** - * Get how many bytes space in uart are available to transmit, - * this can be used in interrupt callback functions, - * cooperate with \ref dev_uart::uart_write "uart_write" API to realize non-blocked write - * - Param type : int32_t * - * - Param usage : store the write available bytes, > 0 for available bytes, 0 for not available - * - Return value explanation : - */ -#define UART_CMD_GET_TXAVAIL DEV_SET_SYSCMD(5) -/** - * Get how many bytes in uart are available to receive, - * this can be used in interrupt callback functions, - * cooperate with \ref dev_uart::uart_read "uart_read" API to realize non-blocked read - * - Param type : int32_t * - * - Param usage : store the read available bytes, > 0 for available bytes, 0 for not available - * - Return value explanation : - */ -#define UART_CMD_GET_RXAVAIL DEV_SET_SYSCMD(6) -/** - * Cause a break condition to be transmitted to the receiving device - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define UART_CMD_BREAK_SET DEV_SET_SYSCMD(7) -/** - * Clear break condition and return to normal - * - Param type : NULL - * - Param usage : param is not required - * - Return value explanation : - */ -#define UART_CMD_BREAK_CLR DEV_SET_SYSCMD(8) -/** - * Change uart \ref dev_uart_info::dps_format "D/P/S(Data/Parity/Stop) format" - * - Param type : \ref UART_DPS_FORMAT * - * - Param usage : uart dps format including databits, parity and stopbits - * - Return value explanation : - */ -#define UART_CMD_SET_DPS_FORMAT DEV_SET_SYSCMD(9) -/** - * Set uart device \ref dev_uart_info::hwfc "hardware flow control" - * - Param type : \ref UART_HW_FLOW_CONTROL - * - Param usage : uart dps format including databits, parity and stopbits - * - Return value explanation : - */ -#define UART_CMD_SET_HWFC DEV_SET_SYSCMD(10) -/** - * Set \ref dev_uart_cbs::tx_cb "uart transmit success callback" function - * when all required bytes are transmitted for interrupt method - * - Param type : \ref DEV_CALLBACK * or NULL - * - Param usage : transmit success callback function for uart - * - Return value explanation : - */ -#define UART_CMD_SET_TXCB DEV_SET_SYSCMD(11) -/** - * Set \ref dev_uart_cbs::rx_cb "uart receive success callback" function - * when all required bytes are received for interrupt method - * - Param type : \ref DEV_CALLBACK * or NULL - * - Param usage : receive success callback function for uart - * - Return value explanation : - */ -#define UART_CMD_SET_RXCB DEV_SET_SYSCMD(12) -/** - * Set \ref dev_uart_cbs::err_cb "uart transfer error callback" function - * when something error happened for interrupt method - * - Param type : \ref DEV_CALLBACK * or NULL - * - Param usage : transfer error callback function for uart - * - Return value explanation : - */ -#define UART_CMD_SET_ERRCB DEV_SET_SYSCMD(13) -/** - * Set transmit buffer via interrupt, and it will set \ref dev_uart_info::tx_buf "tx_buf" - * - Param type : DEV_BUFFER * or NULL - * - Param usage : buffer structure pointer, if param is NULL, then it will set tx_buf to NULL - * - Return value explanation : - */ -#define UART_CMD_SET_TXINT_BUF DEV_SET_SYSCMD(14) -/** - * Set receive buffer via interrupt, and it will set \ref dev_uart_info::rx_buf "rx_buf" - * - Param type : DEV_BUFFER * or NULL - * - Param usage : buffer structure pointer, if param is NULL, then it will set rx_buf to NULL - * - Return value explanation : - */ -#define UART_CMD_SET_RXINT_BUF DEV_SET_SYSCMD(15) -/** - * Enable or disable transmit interrupt - * - Param type : uint32_t - * - Param usage : enable(none-zero) or disable(zero) flag - * - Return value explanation : - */ -#define UART_CMD_SET_TXINT DEV_SET_SYSCMD(16) -/** - * Enable or disable receive interrupt - * - Param type : uint32_t - * - Param usage : enable(none-zero) or disable(zero) flag - * - Return value explanation : - */ -#define UART_CMD_SET_RXINT DEV_SET_SYSCMD(17) -/** - * Abort current interrupt transmit operation if tx interrupt enabled, - * it will disable transmit interrupt, and set \ref DEV_IN_TX_ABRT - * in \ref dev_uart_info::status "status" variable, - * and call the transmit callback function, when tx callback is finished, - * it will clear \ref DEV_IN_TX_ABRT and return - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define UART_CMD_ABORT_TX DEV_SET_SYSCMD(18) -/** - * Abort current interrupt receive operation if rx interrupt enabled, - * it will disable receive interrupt, and set \ref DEV_IN_TX_ABRT - * in \ref dev_uart_info::status "status" variable, - * and call the receive callback function, when rx callback is finished, - * it will clear \ref DEV_IN_TX_ABRT and return - * - Param type : NULL - * - Param usage : - * - Return value explanation : - */ -#define UART_CMD_ABORT_RX DEV_SET_SYSCMD(19) - -/** @} */ - -/** - * \defgroup DEVICE_HAL_UART_CALLBACK UART Interrupt callback functions - * \ingroup DEVICE_HAL_UART - * \brief callback function structure for UART device - * @{ - */ -typedef struct dev_uart_cbs { - DEV_CALLBACK tx_cb; /*!< uart data transmit success required bytes callback */ - DEV_CALLBACK rx_cb; /*!< uart data receive success required bytes callback */ - DEV_CALLBACK err_cb; /*!< uart error callback */ -} DEV_UART_CBS, *DEV_UART_CBS_PTR; -/** @} */ - -/** - * \defgroup DEVICE_HAL_UART_DEVSTRUCT UART Device Interface Definition - * \ingroup DEVICE_HAL_UART - * \brief Contains definitions of uart device interface structure. - * \details This structure will be used in user implemented code, which was called - * \ref DEVICE_IMPL "Device Driver Implement Layer" for uart to use in implementation code. - * Application developer should use the UART API provided here to access to UART devices. - * BSP developer should follow the API definition to implement UART device drivers. - * @{ - */ -/** - * \brief UART information struct definition - * \details informations about uart open count, working status, - * baudrate, uart registers and ctrl structure, uart dps format - */ -typedef struct dev_uart_info { - void *uart_ctrl; /*!< uart control related pointer, implemented by bsp developer, and this should be set during uart object implementation */ - uint32_t opn_cnt; /*!< uart open count, open it will increase 1, close it will decrease 1, 0 for close, >0 for open */ - uint32_t status; /*!< current working status, refer to \ref DEVICE_HAL_COMMON_DEVSTATUS, this should be \ref DEV_ENABLED for first open */ - uint32_t baudrate; /*!< uart baud rate, this should be the value of baud passing by uart_open if first successfully opened */ - UART_DPS_FORMAT dps_format; /*!< D/P/S format settings for uart device, here is \ref dps_format_default "default settings for first open" */ - UART_HW_FLOW_CONTROL hwfc; /*!< UART hardware flow control, here is \ref hwfc_default "default hardware flow control settings for first open" */ - DEV_BUFFER tx_buf; /*!< transmit buffer via interrupt, this should be all zero for first open */ - DEV_BUFFER rx_buf; /*!< receive buffer via interrupt, this should be all zero for first open */ - DEV_UART_CBS uart_cbs; /*!< uart callbacks, callback arguments should be \ref DEV_UART * or NULL, this should be all NULL for first open */ - void *extra; /*!< a extra pointer to get hook to applications which should not used by bsp developer, - this should be NULL for first open and you can \ref DEV_UART_INFO_SET_EXTRA_OBJECT "set" - or \ref DEV_UART_INFO_GET_EXTRA_OBJECT "get" the extra information pointer */ -} DEV_UART_INFO, * DEV_UART_INFO_PTR; - -/** Set extra information pointer of uart info */ -#define DEV_UART_INFO_SET_EXTRA_OBJECT(uart_info_ptr, extra_info) (uart_info_ptr)->extra = (void *)(extra_info) -/** Get extra information pointer of uart info */ -#define DEV_UART_INFO_GET_EXTRA_OBJECT(uart_info_ptr) ((uart_info_ptr)->extra) - -/** - * \brief UART device interface definition - * \details Define uart device interface, like uart information structure, - * provide functions to open/close/control uart, send/receive data by uart - * \note All this details are implemented by user in user porting code - */ -typedef struct dev_uart { - DEV_UART_INFO uart_info; /*!< UART device information */ - int32_t (*uart_open) (uint32_t baud); /*!< Open uart device */ - int32_t (*uart_close) (void); /*!< Close uart device */ - int32_t (*uart_control) (uint32_t ctrl_cmd, void *param); /*!< Control uart device */ - int32_t (*uart_write) (const void *data, uint32_t len); /*!< Send data by uart device(blocked) */ - int32_t (*uart_read) (void *data, uint32_t len); /*!< Read data from uart device(blocked) */ -} DEV_UART, * DEV_UART_PTR; - -/** - * \fn int32_t (* dev_uart::uart_open) (uint32_t baud) - * \details open an uart device with defined baudrate - * \param[in] baud \ref DEVICE_HAL_UART_BAUD "initial baudrate of uart", must > 0 - * \retval E_OK Open successfully without any issues - * \retval E_OPNED If device was opened before with different parameters, - * then just increase the \ref dev_uart_info::opn_cnt "opn_cnt" and return \ref E_OPNED - * \retval E_OBJ Device object is not valid - * \retval E_PAR Parameter is not valid - * \retval E_NOSPT Open settings are not supported - */ - -/** - * \fn int32_t (* dev_uart::uart_close) (void) - * \details close an uart device, just decrease the \ref dev_uart_info::opn_cnt "opn_cnt", - * if \ref dev_uart_info::opn_cnt "opn_cnt" equals 0, then close the device - * \retval E_OK Close successfully without any issues(including scenario that device is already closed) - * \retval E_OPNED Device is still opened, the device \ref dev_uart_info::opn_cnt "opn_cnt" decreased by 1 - * \retval E_OBJ Device object is not valid - */ - -/** - * \fn int32_t (* dev_uart::uart_control) (uint32_t ctrl_cmd, void *param) - * \details control an uart device by \ref ctrl_cmd, with passed \ref param. - * you can control uart device using predefined uart control commands defined using \ref DEV_SET_SYSCMD - * (which must be implemented by bsp developer), such as \ref UART_CMD_SET_BAUD "change baudrate", - * \ref UART_CMD_FLUSH_OUTPUT "flush output" and \ref DEVICE_HAL_UART_CTRLCMD "more". - * And you can also control uart device using your own specified commands defined using \ref DEV_SET_USRCMD, - * but these specified commands should be defined in your own uart device driver implementation. - * \param[in] ctrl_cmd \ref DEVICE_HAL_UART_CTRLCMD "control command", to change or get some thing related to uart - * \param[in,out] param parameters that maybe argument of the command, or return values of the command - * \retval E_OK Control device successfully - * \retval E_CLSED Device is not opened - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid for current control command - * \retval E_SYS Control device failed, due to hardware issues, such as device is disabled - * \retval E_CTX Control device failed, due to different reasons like in transfer state - * \retval E_NOSPT Control command is not supported or not valid - */ - -/** - * \fn int32_t (* dev_uart::uart_write) (const void *data, uint32_t len) - * \details send \ref data through uart with defined \ref len(blocked). - * \param[in] data pointer to data need to send by uart, must not be NULL - * \param[in] len length of data to be sent, must > 0 - * \retval >0 Byte count that was successfully sent for poll method - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid - * \retval E_SYS Can't write data to hardware due to hardware issues, such as device is disabled - */ - -/** - * \fn int32_t (* dev_uart::uart_read) (void *data, uint32_t len) - * \details receive \ref data of defined \ref len through uart(blocked). - * \param[out] data pointer to data need to received by uart, must not be NULL - * \param[in] len length of data to be received, must > 0 - * \retval >0 Byte count that was successfully received for poll method - * \retval E_OBJ Device object is not valid or not exists - * \retval E_PAR Parameter is not valid - * \retval E_SYS Can't receive data from hardware due to hardware issues, such as device is disabled - */ -/** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief get an \ref dev_uart "uart device" by uart device id. - * For how to use uart device hal refer to \ref DEVICE_HAL_UART_DEVSTRUCT "Functions in uart device structure" - * \param[in] uart_id id of uart, defined by user - * \retval !NULL pointer to an \ref dev_uart "uart device structure" - * \retval NULL failed to find the uart device by \ref uart_id - * \note need to implemented by user in user code - */ -extern DEV_UART_PTR uart_get_dev(int32_t uart_id); - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif /* _DEVICE_HAL_UART_H_ */ diff --git a/bsp/synopsys/embarc/inc/arc/arc.h b/bsp/synopsys/embarc/inc/arc/arc.h deleted file mode 100644 index 91c0a3850ef9e474b24b95e2748651947463393e..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/inc/arc/arc.h +++ /dev/null @@ -1,436 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-06-20 - * \author Wayne Ren(Wei.Ren@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup ARC_HAL_CORE_COMM - * \brief header file including common core definitions - */ - - /** - * \addtogroup ARC_HAL_CORE_COMM - * @{ - */ - - -#ifndef _ARC_HAL_CORE_H_ -#define _ARC_HAL_CORE_H_ - -#include "inc/arc/arc_feature_config.h" - -/** - * \name exception number definitions - * @{ - */ - -/* ARC exception number */ -#define EXC_NO_RESET (0) /*!< reset vector, the entry of power up and reset */ -#define EXC_NO_MEM_ERR (1) /*!< external memory bus error */ -#define EXC_NO_INS_ERR (2) /*!< illegal instruction or illegal instruction sequence */ -#define EXC_NO_MAC_CHK (3) /*!< machine check error */ -#define EXC_NO_TLB_MISS_I (4) /*!< instruction TLB missing exception, useless without MMU */ -#define EXC_NO_TLB_MISS_D (5) /*!< data TLB missing exception, useless without MMU */ -#define EXC_NO_PRO_VIO (6) /*!< protection violation */ -#define EXC_NO_PRI_VIO (7) /*!< privilege violation */ -#define EXC_NO_SWI (8) /*!< software interrupt */ -#define EXC_NO_TRAP (9) /*!< trap */ -#define EXC_NO_EXT (10) /*!< extension exception */ -#define EXC_NO_DIV_ZER0 (11) /*!< divide by zero */ -#define EXC_NO_DC_ERR (12) /*!< data cache consistency error */ -#define EXC_NO_MAL_ALIGN (13) /*!< misaligned data access */ -#define EXC_NO_RESERVE0 (14) /*!< reserved */ -#define EXC_NO_RESERVE1 (15) /*!< reserved */ - -/* extension interrupts */ -#define EXC_NO_16 (16) /*!< interrupt vector 16 */ -#define EXC_NO_17 (17) /*!< interrupt vector 17 */ -#define EXC_NO_18 (18) /*!< interrupt vector 18 */ -#define EXC_NO_19 (19) /*!< interrupt vector 19 */ -#define EXC_NO_20 (20) /*!< interrupt vector 20 */ -#define EXC_NO_21 (21) /*!< interrupt vector 21 */ -#define EXC_NO_22 (22) /*!< interrupt vector 22 */ -#define EXC_NO_23 (23) /*!< interrupt vector 23 */ -#define EXC_NO_24 (24) /*!< interrupt vector 24 */ -#define EXC_NO_25 (25) /*!< interrupt vector 25 */ -#define EXC_NO_26 (26) /*!< interrupt vector 26 */ -#define EXC_NO_27 (27) /*!< interrupt vector 27 */ -#define EXC_NO_28 (28) /*!< interrupt vector 28 */ -#define EXC_NO_29 (29) /*!< interrupt vector 29 */ -#define EXC_NO_30 (30) /*!< interrupt vector 30 */ -#define EXC_NO_31 (31) /*!< interrupt vector 31 */ -/* ... ARC supports 255 interrupt vectors at most */ -#define EXC_NO_255 (255) /*!< interrupt vector 255 */ - -/** @} */ - -/** - * \name exception vector offset - * @{ - */ -#define EXC_NO_TO_OFFSET(no) (no << 2) - -/* ARC exception vector offset */ -#define EXC_VECTOR_RESET (0x00) /*!< EXC_NO_RESET offset */ -#define EXC_VECTOR_MEM_ERR (0x04) /*!< EXC_NO_MEM_ERR offset */ -#define EXC_VECTOR_INS_ERR (0x08) /*!< EXC_NO_INS_ERR offset */ -#define EXC_VECTOR_MAC_CHK (0x0c) /*!< EXC_NO_MAC_CHK offset */ -#define EXC_VECTOR_TLB_MISS_I (0x10) /*!< EXC_NO_TLB_MISS_I offset */ -#define EXC_VECTOR_TLB_MISS_D (0x14) /*!< EXC_NO_TLB_MISS_D offset */ -#define EXC_VECTOR_PRO_VIO (0x18) /*!< EXC_NO_PRO_VIO offset */ -#define EXC_VECTOR_PRI_VIO (0x1c) /*!< EXC_NO_PRI_VIO offset */ -#define EXC_VECTOR_SWI (0x20) /*!< EXC_NO_SWI offset */ -#define EXC_VECTOR_TRAP (0x24) /*!< EXC_NO_TRAP offset */ -#define EXC_VECTOR_EXT (0x28) /*!< EXC_NO_EXT offset */ -#define EXC_VECTOR_DIV_ZER0 (0x2c) /*!< EXC_NO_DIV_ZER0 offset */ -#define EXC_VECTOR_DC_ERR (0x30) /*!< EXC_NO_DC_ERR offset */ -#define EXC_VECTOR_MAL_ALIGN (0x34) /*!< EXC_NO_MAL_ALIGN offset */ -#define EXC_VECTOR_RESERVE0 (0x38) /*!< EXC_NO_RESERVE0 offset */ -#define EXC_VECTOR_RESERVE1 (0x3c) /*!< EXC_NO_RESERVE1 offset */ -/** @} */ - -/** - * \name build configuration register - * @{ - */ -#define AUX_BCR_VER (0x60) /*!< build configuration register version */ -#define AUX_BCR_BTA (0x63) /*!< build configuration for BTA LINK */ -#define AUX_BCR_VECBASE (0x68) /*!< build configuration for interrupt vector base */ -#define AUX_BCR_MPU (0x6d) /*!< build configuration for memory protection unit */ -#define AUX_BCR_RF (0x6e) /*!< build configuration for core registers */ -#define AUX_BCR_D_CACHE (0x72) /*!< build configuration for data cache */ -#define AUX_BCR_DCCM (0x74) /*!< build configuration for DCCM */ -#define AUX_BCR_TIMERS (0x75) /*!< build configuration for processor timers */ -#define AUX_BCR_AP (0x76) /*!< build configuration for actionpoints */ -#define AUX_BCR_I_CACHE (0x77) /*!< build configuration for instruction cache */ -#define AUX_BCR_ICCM (0x78) /*!< build configuration for ICCM */ -#define AUX_BCR_DSP (0x7a) /*!< build configuration for DSP */ -#define AUX_BCR_MUL (0x7b) /*!< build configuration for multiply */ -#define AUX_BCR_SWAP (0x7c) /*!< build configuration for swap */ -#define AUX_BCR_NORM (0x7d) /*!< build configuration for normalize */ -#define AUX_BCR_MIXMAX (0x7e) /*!< build configuration for MIN/MAX */ -#define AUX_BCR_BARREL (0x7f) /*!< build configuration for barrel shift */ -#define AUX_BCR_ISA (0xc1) /*!< build configuration for ISA configuration */ -#define AUX_BCR_STACK (0xc5) /*!< build configuration for stack region */ -#define AUX_BCR_ERP (0xc7) /*!< build configuration for error protection */ -#define AUX_BCR_FPU (0xc8) /*!< build configuration for floating-point unit */ -#define AUX_BCR_CPORT (0xc9) /*!< build configuration for code protection */ -#define AUX_BCR_BS (0xcb) /*!< build configuration for bitstream */ -#define AUX_BCR_AGU (0xcc) /*!< build configuration for address generate unit */ -#define AUX_BCR_DMAC (0xcd) /*!< build configuration for DMA */ -#define AUX_BCR_CONNECT_SYSTEM (0xd0) /*!< build configuration for arc connect */ -#define AUX_BCR_CONNECT_SEMA (0xd1) /*!< build configuration for inter-core semaphore */ -#define AUX_BCR_CONNECT_MESSAGE (0xd2) /*!< build configuration for inter-code message */ -#define AUX_BCR_CONNECT_PMU (0xd3) /*!< build configuration for power management unit */ -#define AUX_BCR_CONNECT_GFRC (0xd6) /*!< build configuration for global free running counter */ -#define AUX_BCR_CAL_STORE (0xd9) /*!< build configuration for calibration parameter storage */ -#define AUX_BCR_CONNECT_ICI (0xe0) /*!< build configuration for inter-core interrupt unit */ -#define AUX_BCR_CONNECT_ICD (0xe1) /*!< build configuration for inter-core debug unit */ -#define AUX_BCR_CONNECT_PDM (0xe3) /*!< build configuration for power domain management unit*/ -#define AUX_BCR_RTT (0xf2) /*!< build configuration for real-time trace */ -#define AUX_BCR_IRQ (0xf3) /*!< build configuration for interrupt */ -#define AUX_BCR_PCT (0xf5) /*!< build configuration for performance counters */ -#define AUX_BCR_CC (0xf6) /*!< build configuration for performance counters */ -#define AUX_BCR_PDM_DVFS (0xf7) /*!< build configuration for PDM and DVFS */ - -#define AUX_BCR_SEC_BUILD (0xdb) - -/* from 0xF5 and 0xF6 */ - -#define AUX_BCR_IFQUEUE (0xfe) /*!< build configuration for instruction fetch queue */ -#define AUX_BCR_SMART (0xff) /*!< build configuration for SmaRT debug feature */ -/** @} */ - - -#define AUX_SEC_STAT (0x9) -#define AUX_SEC_STAT_BIT_SSC (0) -#define AUX_SEC_STAT_BIT_NSRT (1) -#define AUX_SEC_STAT_BIT_NSRU (2) -#define AUX_SEC_STAT_BIT_IRM (3) -#define AUX_SEC_STAT_BIT_SUE (4) -#define AUX_SEC_STAT_BIT_NIC (5) - -/** - * \name status register STATUS32 - * @{ - */ -#define AUX_STATUS32 (0xa) -#define AUX_STATUS32_P0 (0xb) - -/* STATUS32 bit-field definition */ -#define AUX_STATUS_BIT_AE (5) /*!< processor is in an exception */ -#define AUX_STATUS_BIT_DE (6) /*!< delayed branch is pending */ -#define AUX_STATUS_BIT_U (7) /*!< user mode */ -#define AUX_STATUS_BIT_L (12) /*!< zero-overhead loop enable */ -#define AUX_STATUS_BIT_IE (31) /*!< interrupt enable */ - -/* masks correspond to STATUS32 bit-field */ -#define AUX_STATUS_MASK_AE (1< Pre Incr - * Eff Addr for load = [reg2 + x] - * - * LD.ab reg1, [reg2, x] => Post Incr - * Eff Addr for load = [reg2] - */ -#if defined(__GNU__) -.macro PUSH reg - st.a \reg, [sp, -4] -.endm - -.macro PUSHAX aux - lr r10, [\aux] - PUSH r10 -.endm - -.macro POP reg - ld.ab \reg, [sp, 4] -.endm - -.macro POPAX aux - POP r10 - sr r10, [\aux] -.endm -#else -.macro PUSH, reg - st.a reg, [sp, -4] -.endm - -.macro PUSHAX, aux - lr r10, [aux] - PUSH r10 -.endm - -.macro POP, reg - ld.ab reg, [sp, 4] -.endm - -.macro POPAX, aux - POP r10 - sr r10, [aux] -.endm -#endif - -/*-------------------------------------------------------------- - * Helpers to save/restore callee-saved regs: - * used by several macros below - *-------------------------------------------------------------*/ -.macro SAVE_CALLEE_REGS - PUSH r13 - PUSH r14 - PUSH r15 -#ifndef ARC_FEATURE_RF16 - PUSH r16 - PUSH r17 - PUSH r18 - PUSH r19 - PUSH r20 - PUSH r21 - PUSH r22 - PUSH r23 - PUSH r24 - PUSH r25 -#endif -.endm - -.macro RESTORE_CALLEE_REGS -#ifndef ARC_FEATURE_RF16 - POP r25 - POP r24 - POP r23 - POP r22 - POP r21 - POP r20 - POP r19 - POP r18 - POP r17 - POP r16 -#endif - POP r15 - POP r14 - POP r13 -.endm - -.macro CLEAR_CALLEE_REGS -#ifndef ARC_FEATURE_RF16 - mov r25, 0 - mov r24, 0 - mov r23, 0 - mov r22, 0 - mov r21, 0 - mov r20, 0 - mov r19, 0 - mov r18, 0 - mov r17, 0 - mov r16, 0 -#endif - mov r15, 0 - mov r14, 0 - mov r13, 0 -.endm - -.macro CLEAR_SCRATCH_REGS - mov r1, 0 - mov r2, 0 - mov r3, 0 - mov r4, 0 - mov r5, 0 - mov r6, 0 - mov r7, 0 - mov r8, 0 - mov r9, 0 - mov r10, 0 - mov r11, 0 - mov r12, 0 - - mov fp, 0 - mov r29, 0 - mov r30, 0 -.endm - - -.macro SAVE_LP_REGS - PUSH r60 - PUSHAX AUX_LP_START - PUSHAX AUX_LP_END -.endm - -.macro RESTORE_LP_REGS - POPAX AUX_LP_END - POPAX AUX_LP_START - POP r10 -/* must not use the LP_COUNT register(r60) as the destination of multi-cycle instruction */ - mov r60, r10 - -.endm - -.macro SAVE_R0_TO_R12 - PUSH r0 - PUSH r1 - PUSH r2 - PUSH r3 -#ifndef ARC_FEATURE_RF16 - PUSH r4 - PUSH r5 - PUSH r6 - PUSH r7 - PUSH r8 - PUSH r9 -#endif - PUSH r10 - PUSH r11 - PUSH r12 -.endm - -.macro RESTORE_R0_TO_R12 - POP r12 - POP r11 - POP r10 -#ifndef ARC_FEATURE_RF16 - POP r9 - POP r8 - POP r7 - POP r6 - POP r5 - POP r4 -#endif - POP r3 - POP r2 - POP r1 - POP r0 -.endm - -.macro SAVE_CODE_DENSITY - PUSHAX AUX_JLI_BASE - PUSHAX AUX_LDI_BASE - PUSHAX AUX_EI_BASE -.endm - -.macro RESTORE_CODE_DENSITY - POPAX AUX_EI_BASE - POPAX AUX_LDI_BASE - POPAX AUX_JLI_BASE -.endm - -/* todo: check the contents of NON_SCRATCH_REGS in debug */ -.macro SAVE_NONSCRATCH_REGS -/* r0-r12 are saved by caller function */ - PUSH gp - PUSH fp - PUSH blink - SAVE_CALLEE_REGS -.endm - -.macro RESTORE_NONSCRATCH_REGS - RESTORE_CALLEE_REGS - POP blink - POP fp - POP gp -.endm - - -.macro SAVE_FIQ_EXC_REGS -#ifndef ARC_FEATURE_RGF_BANKED_REGS - SAVE_R0_TO_R12 - - PUSH gp - PUSH fp - PUSH r30 /* general purpose */ - PUSH blink - -#else -#if ARC_FEATURE_RGF_BANKED_REGS != 4 && ARC_FEATURE_RGF_BANKED_REGS != 8 && \ - ARC_FEATURE_RGF_BANKED_REGS != 16 && ARC_FEATURE_RGF_BANKED_REGS != 32 -#error "unsupported ARC_FEATURE_RGF_BANKED_REGS" -#endif - -#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8 || \ - ARC_FEATURE_RGF_BANKED_REGS == 16 - PUSH r4 - PUSH r5 - PUSH r6 - PUSH r7 - PUSH r8 - PUSH r9 -#endif - -#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8 - PUSH r10 - PUSH r11 -#endif - -#if ARC_FEATURE_RGF_BANKED_REGS == 4 - PUSH r12 -#endif - -#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8 - PUSH gp - PUSH fp - PUSH r30 /* general purpose */ - PUSH blink -#endif - -#endif /* #ifndef ARC_FEATURE_RGF_BANKED_REGS */ - -#ifdef ARC_FEATURE_CODE_DENSITY - SAVE_CODE_DENSITY -#endif - SAVE_LP_REGS -.endm - -.macro RESTORE_FIQ_EXC_REGS - RESTORE_LP_REGS -#ifdef ARC_FEATURE_CODE_DENSITY - RESTORE_CODE_DENSITY -#endif - -#ifndef ARC_FEATURE_RGF_BANKED_REGS - POP blink - POP r30 - POP fp - POP gp - - RESTORE_R0_TO_R12 -#else - -#if ARC_FEATURE_RGF_BANKED_REGS != 4 && ARC_FEATURE_RGF_BANKED_REGS != 8 && \ - ARC_FEATURE_RGF_BANKED_REGS != 16 && ARC_FEATURE_RGF_BANKED_REGS != 32 -#error "unsupported ARC_FEATURE_RGF_BANKED_REGS" -#endif - -#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8 - POP blink - POP r30 - POP fp - POP gp -#endif - -#if ARC_FEATURE_RGF_BANKED_REGS == 4 - POP r12 -#endif - -#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8 - POP r11 - POP r10 -#endif - -#if ARC_FEATURE_RGF_BANKED_REGS == 4 || ARC_FEATURE_BANKED_REGS == 8 || \ - ARC_FEATURE_RGF_BANKED_REGS == 16 - POP r9 - POP r8 - POP r7 - POP r6 - POP r5 - POP r4 -#endif - -#endif /* #ifndef ARC_FEATURE_RGF_BANKED_REGS */ -.endm - -/* normal interrupt prologue, pc, status and r0-r11 are saved by hardware */ -.macro INTERRUPT_PROLOGUE - PUSH r12 - PUSH gp - PUSH fp - PUSH ilink - PUSH r30 - - sub sp, sp, 4 /* skip bta */ -.endm - - -/* normal interrupt epilogue, pc, status and r0-r11 are restored by hardware */ -.macro INTERRUPT_EPILOGUE - add sp, sp, 4 /* skip bta */ - - POP r30 - POP ilink - POP fp - POP gp - POP r12 -.endm - -#if SECURESHIELD_VERSION == 2 -/* exception prologue, create the same frame of interrupt manually */ -.macro EXCEPTION_PROLOGUE - st.as r10, [sp, -6] /* save r10 first, free up a register*/ - - PUSHAX AUX_ERSTATUS - sub sp, sp, 4 /* slot for SEC_STAT */ - PUSHAX AUX_ERRET - - PUSH blink - - PUSH r11 - sub sp, sp, 4 /* r10 is pushed before */ -#ifndef ARC_FEATURE_RF16 - PUSH r9 - PUSH r8 - PUSH r7 - PUSH r6 - PUSH r5 - PUSH r4 -#endif - PUSH r3 - PUSH r2 - PUSH r1 - PUSH r0 - -#ifdef ARC_FEATURE_CODE_DENSITY - SAVE_CODE_DENSITY -#endif - SAVE_LP_REGS - - PUSH r12 - PUSH gp - PUSH fp - PUSH ilink - PUSH r30 - - PUSHAX AUX_ERBTA -.endm - -/* exception epilogue, restore the same frame of interrupt manually */ -.macro EXCEPTION_EPILOGUE - POPAX AUX_ERBTA - - POP r30 - POP ilink - POP fp - POP gp - POP r12 - - RESTORE_LP_REGS - -#ifdef ARC_FEATURE_CODE_DENSITY - RESTORE_CODE_DENSITY -#endif - POP r0 - POP r1 - POP r2 - POP r3 -#ifndef ARC_FEATURE_RF16 - POP r4 - POP r5 - POP r6 - POP r7 - POP r8 - POP r9 -#endif - add sp, sp, 4 /* r10 will be popped finally */ - POP r11 - - POP blink - - - POPAX AUX_ERRET - add sp, sp, 4 /* slot for SEC_STAT */ - POPAX AUX_ERSTATUS - - ld.as r10, [sp, -6] /* restore r10 */ -.endm -#else /* normal version */ -/* exception prologue, create the same frame of interrupt manually */ -.macro EXCEPTION_PROLOGUE -#ifdef ARC_FEATURE_CODE_DENSITY - st.as r10, [sp, -11] /* save r10 first, free up a register*/ -#else - st.as r10, [sp, -8] -#endif - PUSHAX AUX_ERSTATUS - PUSHAX AUX_ERRET - -#ifdef ARC_FEATURE_CODE_DENSITY - SAVE_CODE_DENSITY -#endif - SAVE_LP_REGS - - PUSH blink - - PUSH r11 - sub sp, sp, 4 /* r10 is pushed before */ -#ifndef ARC_FEATURE_RF16 - PUSH r9 - PUSH r8 - PUSH r7 - PUSH r6 - PUSH r5 - PUSH r4 -#endif - PUSH r3 - PUSH r2 - PUSH r1 - PUSH r0 - - PUSH r12 - PUSH gp - PUSH fp - PUSH ilink - PUSH r30 - - PUSHAX AUX_ERBTA -.endm - -/* exception epilogue, restore the same frame of interrupt manually */ -.macro EXCEPTION_EPILOGUE - POPAX AUX_ERBTA - - POP r30 - POP ilink - POP fp - POP gp - POP r12 - - POP r0 - POP r1 - POP r2 - POP r3 -#ifndef ARC_FEATURE_RF16 - POP r4 - POP r5 - POP r6 - POP r7 - POP r8 - POP r9 -#endif - add sp, sp, 4 /* r10 will be popped finally */ - POP r11 - - POP blink - - RESTORE_LP_REGS - -#ifdef ARC_FEATURE_CODE_DENSITY - RESTORE_CODE_DENSITY -#endif - - POPAX AUX_ERRET - POPAX AUX_ERSTATUS - -#ifdef ARC_FEATURE_CODE_DENSITY - ld.as r10, [sp, -11] /* restore r10 */ -#else - ld.as r10, [sp, -8] -#endif -.endm - -#endif /* SECURESHIELD_VERSION == 2 */ - -#endif /* _ARC_HAL_ASM_COMMON_H */ -/** @endcond */ diff --git a/bsp/synopsys/embarc/inc/arc/arc_builtin.h b/bsp/synopsys/embarc/inc/arc/arc_builtin.h deleted file mode 100644 index d9b76124ff0c8602766a4f432a17634c16e30080..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/inc/arc/arc_builtin.h +++ /dev/null @@ -1,301 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-06-12 - * \author Wayne Ren(Wei.Ren@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup ARC_HAL_BUILTIN - * \brief header file of builtin and helper functions - * - * The Metaware toolchain and the GNU toolchain are supported. The details please go to see the file. - */ - -/** - * \addtogroup ARC_HAL_BUILTIN - * @{ - */ - -#ifndef _ARC_HAL_BUILTIN_H_ -#define _ARC_HAL_BUILTIN_H_ - -#include "inc/embARC_toolchain.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__MW__) /* Metaware toolchain */ - -#define _arc_nop _nop /*!< no operation, generate a nop instruction produces a single NOP instruction in the compiled code */ - -#define _arc_brk _brk /*!< generate a brk instruction */ - -#define _arc_clri _clri /*!< generate a clri instruction */ - -#define _arc_seti(c) _seti(c) /*!< generate a seti instruction */ - -#define _arc_core_write(regno, val) _core_write(val, regno) /*!< write core register */ - -#define _arc_core_read(regno) _core_read(regno) /*!< read core register */ - -#define _arc_lr_reg(aux) _lr(aux) /*!< read auxiliary register */ - -#define _arc_sr_reg(aux, val) _sr(val, aux) /*!< write auxiliary register */ - -#define _arc_sleep(a) _sleep(a) /*!< generate a sleep instruction */ - -#define _arc_flag(a) _flag(a) /*!< generate a flag instruction */ - -#define _arc_kflag(a) - -#define _arc_sync _sync /*!< generate a sync instruction */ - -/* - * !< _arc_usually (expr) evaluates expression expr and - * informs the compiler that the value is usually true. - */ -#define _arc_usually(a) _Usually((a)) - -/* - * !< _arc_rarely (expr) evaluates expression expr and - * informs the compiler that the value is rarely true. - */ -#define _arc_rarely(a) _Rarely((a)) - -#if 0 -/** - * \brief Reverses the byte order of the 16-bit operand, - * reversing the endianness of the value. - * Not for ARC HS family - */ -#define _arc_swap16(a) _swap16(a) -/** - * \brief Reverses the byte order of the 32-bit operand, - * reversing the endianness of the value. - * Not for ARC HS family - */ -#define _arc_swap32(a) _swap32(a) -#else -Inline uint32_t _arc_swap32(uint32_t val) { - register uint32_t v; - __asm__ volatile ("swape %0, %1" :"=r"(v): "r"(val)); - return v; -} - -Inline uint16_t _arc_swap16(uint32_t val) { - register uint32_t temp; - register uint32_t v; - __asm__ volatile ("swape %0, %1" :"=r"(temp): "r"(val)); - __asm__ volatile ("lsr16 %0, %1" :"=r"(v): "r"(temp)); - return (unsigned short)v; -} -#endif - -/** - * \brief Each call to _swi() generates one - * software interrupt instruction (SWI) for processors - * to support the SWI instruction. - */ -#define _arc_swi _swi - -/* \todo add more builtin functions of metaware tool */ - -#elif defined (__GNU__) /* GNU toolchain */ - -#define _arc_nop __builtin_arc_nop -#define _arc_brk __builtin_arc_brk -#define _arc_seti(c) __builtin_arc_seti(c) -#define _arc_core_write(regno, val) __builtin_arc_core_write(regno,val) -#define _arc_core_read(regno) __builtin_arc_core_read(regno) -#define _arc_flag(a) __builtin_arc_flag(a) -#define _arc_kflag(a) __builtin_arc_kflag(a) -#define _arc_lr_reg(aux) __builtin_arc_lr(aux) -/* don't uncomment this now */ -//#define _arc_sr_reg(aux, val) __builtin_arc_sr(aux, val) -#define _arc_sleep(a) __builtin_arc_sleep(a) -//#define _arc_sync __builtin_arc_sync - -/** - * \brief _arc_usually (expr) evaluates expression expr and - * informs the compiler that the value is usually true. - */ -#define _arc_usually(a) __builtin_expect((int)(a), 1) - -/** - * \brief _arc_rarely (expr) evaluates expression expr and - * informs the compiler that the value is rarely true. - */ -#define _arc_rarely(a) __builtin_expect((int)(a), 0) - -/** - * \brief Each call to _swi() generates one - * software interrupt instruction (SWI) for processors - * to support the SWI instruction. - */ -#define _arc_swi __builtin_arc_swi - -Inline uint32_t _arc_clri(void) { - register uint32_t v; - __asm__ volatile ("clri %0" :"=r"(v)); - return v; - -} -/* \todo add more builtin functions of gnu tool */ - -Inline uint32_t _arc_swap32(uint32_t val) { - register uint32_t v; - __asm__ volatile ("swape %0, %1" :"=r"(v): "r"(val)); - return v; -} - -Inline uint16_t _arc_swap16(uint32_t val) { - register uint32_t temp; - register uint32_t v; - __asm__ volatile ("swape %0, %1" :"=r"(temp): "r"(val)); - __asm__ volatile ("lsr16 %0, %1" :"=r"(v): "r"(temp)); - return (unsigned short)v; -} - -Inline void _arc_sync(void) { - __asm__ volatile ("sync"); -} - -/** - * \note Following is a workaround for arc gcc - * built-in function __builtin_arc_sr. - * But it is wrong in GCC arc-4.8-R3-rc3 and shouldn't be used. - */ - -/* - * The auxiliary register address is specified as a long immediate operand by caller. - * e.g. - * write_aux_reg(0x69, some_val); - * This generates the tightest code. - */ -#define write_aux_reg(reg_imm, val) \ -({ \ - Asm( \ - " sr %0, [%1] \n" \ - : \ - : "ir"(val), "r"(reg_imm)); \ -}) - -#define _arc_sr_reg(aux, val) write_aux_reg(aux, val) - -#endif - -/* \todo add more helper functions here, such as memory operation */ - -#define _arc_aux_read(aux) _arc_lr_reg(aux) -#define _arc_aux_write(aux, val) _arc_sr_reg(aux, val) - -/** - * \name cache related helper function - * @{ - */ - -/** - * \brief read memory and bypass the cache - * \param[in] ptr memory address - * \return value in the memory - */ -Inline uint32_t _arc_read_uncached_32(void *ptr) -{ - uint32_t __ret; - Asm("ld.di %0, [%1]":"=r"(__ret):"r"(ptr)); - return __ret; -} - -/** - * \brief write memory and bypass the cache - * \param[in] ptr memory address - * \param[in] data vaule to be written - */ -Inline void _arc_write_uncached_32(void *ptr, uint32_t data) -{ - Asm("st.di %0, [%1]":: "r"(data), "r"(ptr)); -} - -/** - * \brief read memory with cache - * \param[in] ptr memory address - * \returns value in the memory - */ -Inline uint32_t _arc_read_cached_32(void *ptr) -{ - uint32_t __ret; - Asm("ld %0, [%1]":"=r"(__ret):"r"(ptr)); - return __ret; -} - -/** - * \brief read memory with cache - * \param[in] ptr memory address - * \param[in] data vaule to be written - * \return description - */ -Inline void _arc_write_cached_32(void *ptr, uint32_t data) -{ - Asm("st %0, [%1]":: "r"(data), "r"(ptr)); -} - -/** - * \brief go to main function with proper arguments - * \param argc argument count - * \param argv argument content array - * \retval return value of main function - */ -Inline int32_t _arc_goto_main(int argc, char **argv) { - int __ret; - __asm__ volatile( - "mov %%r0, %1\n" - "mov %%r1, %2\n" - "push_s %%blink\n" - "jl main\n" - "pop_s %%blink\n" - "mov %0, %%r0" - :"=r"(__ret): "r"(argc), "r"(argv)); - return (int)__ret; -} - -#ifdef __cplusplus -} -#endif - -#if defined(LIB_SECURESHIELD) && defined(LIB_SECURESHIELD_OVERRIDES) && (SECURESHIELD_VERSION == 1) -#define OVERRIDE_ARC_HAL_BUILTIN_H -#include "secureshield_overrides.h" -#endif - -/** @} */ -#endif /* _ARC_HAL_BUILTIN_H_ */ -/** @} */ diff --git a/bsp/synopsys/embarc/inc/arc/arc_cache.h b/bsp/synopsys/embarc/inc/arc/arc_cache.h deleted file mode 100644 index dfbc7df9a5952d73d8460e4a616d934dad7a1a84..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/inc/arc/arc_cache.h +++ /dev/null @@ -1,321 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-07-15 - * \author Wayne Ren(Wei.Ren@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup ARC_HAL_MISC_CACHE - * \brief header file of cache module - */ - -#ifndef _ARC_HAL_CACHE_H_ -#define _ARC_HAL_CACHE_H_ - -#include "inc/embARC_toolchain.h" -#include "inc/arc/arc.h" -#include "inc/arc/arc_builtin.h" -#include "inc/arc/arc_exception.h" - -/** - * \name instruction cache control register related definition - * \todo this definitions will be reviewed. - * @{ - */ -#define IC_CTRL_IC_ENABLE 0x0 /*!< enable instruction cache */ -#define IC_CTRL_IC_DISABLE 0x1 /*!< disable instruction cache */ -#define IC_CTRL_DIRECT_ACCESS 0x0 /*!< direct access mode */ -#define IC_CTRL_INDIRECT_ACCESS 0x20 /*!< indirect access mode */ -#define IC_CTRL_OP_SUCCEEDED 0x8 /*!< instruction cache operation succeeded */ -/** @} */ - -/** - * \name data cache control register related definition - * \todo this definition will be reviewed. - * @{ - */ -#define IC_CTRL_I -#define DC_CTRL_DC_ENABLE 0x0 /*!< enable data cache */ -#define DC_CTRL_DC_DISABLE 0x1 /*!< disable data cache */ -#define DC_CTRL_INVALID_ONLY 0x0 /*!< invalid data cache only */ -#define DC_CTRL_INVALID_FLUSH 0x40 /*!< invalid and flush data cache */ -#define DC_CTRL_ENABLE_FLUSH_LOCKED 0x80 /*!< the locked data cache can be flushed */ -#define DC_CTRL_DISABLE_FLUSH_LOCKED 0x0 /*!< the locked data cache cannot be flushed */ -#define DC_CTRL_FLUSH_STATUS 0x100 /*!< flush status */ -#define DC_CTRL_DIRECT_ACCESS 0x0 /*!< direct access mode */ -#define DC_CTRL_INDIRECT_ACCESS 0x20 /*!< indirect access mode */ -#define DC_CTRL_OP_SUCCEEDED 0x4 /*!< data cache operation succeeded */ -/** @} */ - -/** - * \name instruction cache related inline function - * @{ - */ - -/** - * \brief check whether instruction cache is available, - * 0 for not available, >0 for available - */ -Inline uint8_t icache_available(void) -{ - return (_arc_aux_read(AUX_BCR_I_CACHE) & 0xF); -} - -/** - * \brief enable instruction cache - * \param[in] icache_en_mask operation mask - */ -Inline void icache_enable(uint32_t icache_en_mask) -{ - if (!icache_available()) return; - _arc_aux_write(AUX_IC_CTRL, icache_en_mask); -} - -/** - * \brief disable instruction cache - */ -Inline void icache_disable(void) -{ - if (!icache_available()) return; - _arc_aux_write(AUX_IC_CTRL, IC_CTRL_IC_DISABLE); -} - -/** - * \brief invalidate the entire instruction cache - */ -Inline void icache_invalidate(void) -{ - if (!icache_available()) return; - /* invalidate the entire icache */ - _arc_aux_write(AUX_IC_IVIC, 0); - Asm("nop_s"); - Asm("nop_s"); - Asm("nop_s"); -} - -/** - * \brief invalidate specific cache line - * \param[in] address memory address - */ -Inline void icache_invalidate_line(uint32_t address) -{ - if (!icache_available()) return; - _arc_aux_write(AUX_IC_IVIL, address); - /* the 3 nops are required by ARCv2 ISA */ - Asm("nop_s"); - Asm("nop_s"); - Asm("nop_s"); -} - -/** - * \brief lock specific cache line - * \param[in] address memory address - * \return 0, succeeded, -1, failed - */ -Inline int32_t icache_lock_line(uint32_t address) -{ - if (!icache_available()) return -1; - _arc_aux_write(AUX_IC_LIL, address); - if(_arc_aux_read(AUX_IC_CTRL) & IC_CTRL_OP_SUCCEEDED) { - return 0; - } else { - return -1; - } -} - -/** - * \brief set icache access mode - * \param[in] mode, access mode, 1: indirect access 0:direct access - */ -Inline void icache_access_mode(uint32_t mode) -{ - if (!icache_available()) return; - if (mode) { - _arc_aux_write(AUX_IC_CTRL, _arc_aux_read(AUX_IC_CTRL) | IC_CTRL_INDIRECT_ACCESS); - } else { - _arc_aux_write(AUX_IC_CTRL, _arc_aux_read(AUX_IC_CTRL) & (~IC_CTRL_INDIRECT_ACCESS)); - } -} - - -/** @} */ - -/** - * \name data cache related inline functions - * @{ - */ - -/** - * \brief check whether data cache is available, - * 0 for not available, >0 for available - */ -Inline uint8_t dcache_available(void) -{ - return (_arc_aux_read(AUX_BCR_D_CACHE) & 0xF); -} - -/** - * \brief invalidate the entire data cache - */ -Inline void dcache_invalidate(void) -{ - if (!dcache_available()) return; - uint32_t status; - - status = cpu_lock_save(); - _arc_aux_write(AUX_DC_IVDC, 1); - /* wait for flush completion */ - while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); - cpu_unlock_restore(status); -} - -/** - * \brief invalidate the specific cache line - * \param[in] address memory address - */ -Inline void dcache_invalidate_line(uint32_t address) -{ - if (!dcache_available()) return; - _arc_aux_write(AUX_DC_IVDL, address); - Asm("nop_s"); - Asm("nop_s"); - Asm("nop_s"); -} - -/** - * \brief enable data cache - * \param[in] dcache_en_mask operation mask - */ -Inline void dcache_enable(uint32_t dcache_en_mask) -{ - if (!dcache_available()) return; - _arc_aux_write(AUX_DC_CTRL, dcache_en_mask); -} - -/** - * \brief disable data cache - */ -Inline void dcache_disable(void) -{ - if (!dcache_available()) return; - _arc_aux_write(AUX_DC_CTRL, DC_CTRL_DC_DISABLE); -} - -/** - * \brief flush data cache - */ -Inline void dcache_flush(void) -{ - if (!dcache_available()) return; - uint32_t status; - - status = cpu_lock_save(); - _arc_aux_write(AUX_DC_FLSH, 1); - /* wait for flush completion */ - while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); - cpu_unlock_restore(status); -} - -/** - * \brief flush the specific data cache line - * \param[in] address memory address - */ -Inline void dcache_flush_line(uint32_t address) -{ - if (!dcache_available()) return; - - uint32_t status; - - status = cpu_lock_save(); - _arc_aux_write(AUX_DC_FLDL, address); - while (_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); - cpu_unlock_restore(status); -} - -/** - * \brief lock the specific data cache line - * \param[in] address memory address - * \return 0, succeeded, -1, failed - */ -Inline int dcache_lock_line(uint32_t address) -{ - if (!dcache_available()) return -1; - _arc_aux_write(AUX_DC_LDL, address); - if(_arc_aux_read(AUX_DC_CTRL) & DC_CTRL_OP_SUCCEEDED) { - return 0; - } else { - return -1; - } -} - -/** - * \brief set dcache access mode - * \param[in] mode, access mode, 1: indirect access 0:direct access - */ -Inline void dcache_access_mode(uint32_t mode) -{ - if (!dcache_available()) return; - if (mode) { - _arc_aux_write(AUX_DC_CTRL, _arc_aux_read(AUX_DC_CTRL) | DC_CTRL_INDIRECT_ACCESS); - } else { - _arc_aux_write(AUX_DC_CTRL, _arc_aux_read(AUX_DC_CTRL) & (~DC_CTRL_INDIRECT_ACCESS)); - } -} - -/** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name declarations of cache related functions - * @{ - */ -extern int32_t icache_invalidate_mlines(uint32_t start_addr, uint32_t size); -extern int32_t icache_lock_mlines(uint32_t start_addr, uint32_t size); -extern int32_t icache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data); -extern int32_t icache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data); -extern int32_t icache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data); -extern int32_t dcache_invalidate_mlines(uint32_t start_addr, uint32_t size); -extern int32_t dcache_flush_mlines(uint32_t start_addr, uint32_t size); -extern int32_t dcache_lock_mlines(uint32_t start_addr, uint32_t size); -extern int32_t dcache_direct_write(uint32_t cache_addr, uint32_t tag, uint32_t data); -extern int32_t dcache_direct_read(uint32_t cache_addr, uint32_t *tag, uint32_t *data); -extern int32_t dcache_indirect_read(uint32_t mem_addr, uint32_t *tag, uint32_t *data); -extern void arc_cache_init(void); - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif /* _ARC_HAL_CACHE_H_ */ diff --git a/bsp/synopsys/embarc/inc/arc/arc_em.h b/bsp/synopsys/embarc/inc/arc/arc_em.h deleted file mode 100644 index cfb9636449cd6f2f8d2f08a7da5a5da3a2435cff..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/inc/arc/arc_em.h +++ /dev/null @@ -1,133 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-06-12 - * \author Wayne Ren(Wei.Ren@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup ARC_HAL_CORE_EM - * \brief header file of EM series - */ - -/** - * \addtogroup ARC_HAL_CORE_EM - * @{ - */ - -#ifndef _ARC_HAL_EM_H_ -#define _ARC_HAL_EM_H_ - -#include "inc/arc/arc.h" - -#define AUX_ACC0_LO (0x580) -#define AUX_ACC0_GLO (0x581) -#define AUX_ACC0_HI (0x582) -#define AUX_ACC0_GHI (0x583) -#define AUX_DSP_BFLY0 (0x598) -#define AUX_DSP_FFT_CTRL (0x59e) -#define AUX_DSP_CTRL (0x59f) - -#define AUX_AGU_AUX_AP0 (0x5c0) -#define AUX_AGU_AUX_AP1 (0x5c1) -#define AUX_AGU_AUX_AP2 (0x5c2) -#define AUX_AGU_AUX_AP3 (0x5c3) -#define AUX_AGU_AUX_AP4 (0x5c4) -#define AUX_AGU_AUX_AP5 (0x5c5) -#define AUX_AGU_AUX_AP6 (0x5c6) -#define AUX_AGU_AUX_AP7 (0x5c7) -#define AUX_AGU_AUX_AP8 (0x5c8) -#define AUX_AGU_AUX_AP9 (0x5c9) -#define AUX_AGU_AUX_AP10 (0x5ca) -#define AUX_AGU_AUX_AP11 (0x5cb) -#define AUX_AGU_AUX_AP12 (0x5cc) -#define AUX_AGU_AUX_AP13 (0x5cd) -#define AUX_AGU_AUX_AP14 (0x5ce) -#define AUX_AGU_AUX_AP15 (0x5cf) - -#define AUX_AGU_AXU_OS0 (0x5d0) -#define AUX_AGU_AXU_OS1 (0x5d1) -#define AUX_AGU_AXU_OS2 (0x5d2) -#define AUX_AGU_AXU_OS3 (0x5d3) -#define AUX_AGU_AXU_OS4 (0x5d4) -#define AUX_AGU_AXU_OS5 (0x5d5) -#define AUX_AGU_AXU_OS6 (0x5d6) -#define AUX_AGU_AXU_OS7 (0x5d7) -#define AUX_AGU_AXU_OS8 (0x5d8) -#define AUX_AGU_AXU_OS9 (0x5d9) -#define AUX_AGU_AXU_OS10 (0x5da) -#define AUX_AGU_AXU_OS11 (0x5db) -#define AUX_AGU_AXU_OS12 (0x5dc) -#define AUX_AGU_AXU_OS13 (0x5dd) -#define AUX_AGU_AXU_OS14 (0x5de) -#define AUX_AGU_AXU_OS15 (0x5df) - -#define AUX_AGU_AUX_MOD0 (0x5e0) -#define AUX_AGU_AUX_MOD1 (0x5e1) -#define AUX_AGU_AUX_MOD2 (0x5e2) -#define AUX_AGU_AUX_MOD3 (0x5e3) -#define AUX_AGU_AUX_MOD4 (0x5e4) -#define AUX_AGU_AUX_MOD5 (0x5e5) -#define AUX_AGU_AUX_MOD6 (0x5e6) -#define AUX_AGU_AUX_MOD7 (0x5e7) -#define AUX_AGU_AUX_MOD8 (0x5e8) -#define AUX_AGU_AUX_MOD9 (0x5e9) -#define AUX_AGU_AUX_MOD10 (0x5ea) -#define AUX_AGU_AUX_MOD11 (0x5eb) -#define AUX_AGU_AUX_MOD12 (0x5ec) -#define AUX_AGU_AUX_MOD13 (0x5ed) -#define AUX_AGU_AUX_MOD14 (0x5ee) -#define AUX_AGU_AUX_MOD15 (0x5ef) -#define AUX_AGU_AUX_MOD16 (0x5f0) -#define AUX_AGU_AUX_MOD17 (0x5f1) -#define AUX_AGU_AUX_MOD18 (0x5f2) -#define AUX_AGU_AUX_MOD19 (0x5f3) -#define AUX_AGU_AUX_MOD20 (0x5f4) -#define AUX_AGU_AUX_MOD21 (0x5f5) -#define AUX_AGU_AUX_MOD22 (0x5f6) -#define AUX_AGU_AUX_MOD23 (0x5f7) - -#define AUX_XCCM_BASE (0x5f8) -#define AUX_YCCM_BASE (0x5f9) - - -/** \todo add em series specific definitions here */ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _ARC_HAL_EM_H_ */ - -/** @} */ diff --git a/bsp/synopsys/embarc/inc/arc/arc_exception.h b/bsp/synopsys/embarc/inc/arc/arc_exception.h deleted file mode 100644 index e485b159c399ae1afdd6661a797a44ab1d12e98a..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/inc/arc/arc_exception.h +++ /dev/null @@ -1,461 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-07-15 - * \author Wayne Ren(Wei.Ren@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup ARC_HAL_EXCEPTION_CPU ARC_HAL_EXCEPTION_INTERRUPT - * \brief header file of exception and interrupt management module - */ - -#ifndef _ARC_HAL_EXCEPTION_H_ -#define _ARC_HAL_EXCEPTION_H_ - -#include "inc/embARC_toolchain.h" -#include "inc/arc/arc.h" -#include "inc/arc/arc_builtin.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup ARC_HAL_EXCEPTION_CPU - * @{ - * \todo need a conf.h from application or board to define the - * features of processor, such as number of exception, code - * density and FIQ. - */ -#ifndef NUM_EXC_CPU -#define NUM_EXC_CPU 16 /*!< number of CPU exceptions */ -#endif - -#ifndef NUM_EXC_INT -#define NUM_EXC_INT 9 /*!< number of interrupt exceptions, defined by users*/ -#endif - -#define NUM_EXC_ALL (NUM_EXC_CPU + NUM_EXC_INT) /*!< total number of exceptions */ - - - -#ifdef ARC_FEATURE_SEC_PRESENT -typedef struct int_exc_frame { - uint32_t erbta; - - uint32_t r30; /* r30 is useless, skipped? */ - uint32_t ilink; /* r29 is useless, skipped?*/ - /* r28 is sp, saved other place */ - uint32_t fp; /* r27 */ - uint32_t gp; /* r26 */ - - uint32_t r12; - - uint32_t lp_end, lp_start, lp_count; - -#ifdef ARC_FEATURE_CODE_DENSITY - uint32_t ei, ldi, jli; -#endif - - uint32_t r0, r1, r2, r3; -#ifndef ARC_FEATURE_RF16 - uint32_t r4, r5, r6, r7, r8, r9; -#endif - uint32_t r10, r11; - - uint32_t blink; /* r31 */ - uint32_t ret; - uint32_t sec_stat; - uint32_t status32; -} EMBARC_PACKED INT_EXC_FRAME; -#else -typedef struct int_exc_frame { - uint32_t erbta; - - uint32_t r30; /* r30 is useless, skipped? */ - uint32_t ilink; /* r29 is useless, skipped?*/ - /* r28 is sp, saved other place */ - uint32_t fp; /* r27 */ - uint32_t gp; /* r26 */ - - uint32_t r12; - - uint32_t r0, r1, r2, r3; -#ifndef ARC_FEATURE_RF16 - uint32_t r4, r5, r6, r7, r8, r9; -#endif - uint32_t r10, r11; - - uint32_t blink; /* r31 */ - - uint32_t lp_end, lp_start, lp_count; - -#ifdef ARC_FEATURE_CODE_DENSITY - uint32_t ei, ldi, jli; -#endif - - uint32_t ret; - uint32_t status32; -} EMBARC_PACKED INT_EXC_FRAME; -#endif - -typedef struct callee_frame { -#ifndef ARC_FEATURE_RF16 - uint32_t r25; - uint32_t r24; - uint32_t r23; - uint32_t r22; - uint32_t r21; - uint32_t r20; - uint32_t r19; - uint32_t r18; - uint32_t r17; - uint32_t r16; -#endif - uint32_t r15; - uint32_t r14; - uint32_t r13; -} EMBARC_PACKED CALLEE_FRAME; - -typedef struct processor_frame { - CALLEE_FRAME callee_regs; - INT_EXC_FRAME exc_frame; -} EMBARC_PACKED PROCESSOR_FRAME; - -#define ARC_PROCESSOR_FRAME_SIZE (sizeof(PROCESSOR_FRAME) / sizeof(uint32_t)) -#define ARC_EXC_FRAME_SIZE (sizeof(INT_EXC_FRAME) / sizeof(uint32_t)) -#define ARC_CALLEE_FRAME_SIZE (sizeof(CALLEE_FRAME) / sizeof(uint32_t)) - - -extern uint32_t exc_nest_count; - -/** - * \brief write the exception vector base - * - * \param[in] vec_base the target vector base - */ -Inline void arc_vector_base_write(const void * vec_base) -{ - _arc_aux_write(AUX_INT_VECT_BASE, (uint32_t)vec_base); -} - -/** - * \brief read current exception vector base - * - * \returns exception vector base (uint32_t) - */ -Inline uint32_t arc_vector_base_read(void) -{ - return _arc_aux_read(AUX_INT_VECT_BASE); -} - -/** - * \brief sense whether in exc/interrupt processing - * - * \retval 0 not in exc/interrupt processing - * \retval 1 in exc/interrupt processing - */ -Inline uint32_t exc_sense(void) -{ - return (exc_nest_count > 0U); -} - -/** @}*/ - -/** - * \addtogroup ARC_HAL_EXCEPTION_INTERRUPT - * @{ - */ -#ifndef INT_PRI_MIN -#define INT_PRI_MIN (-2) /*!< the minimum interrupt priority */ -#endif - -#define INT_PRI_MAX (-1) /*!< the maximum interrupt priority */ -/** - * \brief disable the specific interrupt - * - * \param[in] intno interrupt number - */ -Inline void arc_int_disable(const uint32_t intno) -{ - _arc_aux_write(AUX_IRQ_SELECT, intno); - _arc_aux_write(AUX_IRQ_ENABLE, 0); -} - -/** - * \brief enable the specific int - * - * \param[in] intno interrupt number - */ -Inline void arc_int_enable(const uint32_t intno) -{ - _arc_aux_write(AUX_IRQ_SELECT, intno); - _arc_aux_write(AUX_IRQ_ENABLE, 1); -} - -/** - * \brief check whether the specific int is enabled - * - * \param[in] intno interrupt number - * \return 0 disabled, 1 enabled - */ -Inline uint32_t arc_int_enabled(const uint32_t intno) -{ - _arc_aux_write(AUX_IRQ_SELECT, intno); - return _arc_aux_read(AUX_IRQ_ENABLE); -} - -/** - * \brief get the interrupt priority mask - * - * \returns interrupt priority mask, negative num - */ -Inline uint32_t arc_int_ipm_get(void) -{ - return ((_arc_aux_read(AUX_STATUS32) >> 1) & 0x0f); -} - -/** - * \brief set the interrupt priority mask - * - * \param[in] intpri interrupt priority - */ -Inline void arc_int_ipm_set(uint32_t intpri) -{ - volatile uint32_t status; - status = _arc_aux_read(AUX_STATUS32) & ~0x1e; - - status = status | ((intpri << 1) & 0x1e); - /* sr cannot write AUX_STATUS32 */ - Asm("kflag %0"::"ir"(status)); -} - -/** - * \brief get current interrupt priority mask - * - * \param[in] intno interrupt number - */ -Inline uint32_t arc_int_pri_get(const uint32_t intno) -{ - _arc_aux_write(AUX_IRQ_SELECT, intno); - return _arc_aux_read(AUX_IRQ_PRIORITY); -} - -/** - * \brief set interrupt priority - * - * \param[in] intno interrupt number - * \param[in] intpri interrupt priority - */ -Inline void arc_int_pri_set(const uint32_t intno, uint32_t intpri) -{ - _arc_aux_write(AUX_IRQ_SELECT, intno); - _arc_aux_write(AUX_IRQ_PRIORITY, intpri | (_arc_aux_read(AUX_IRQ_PRIORITY) & 0xfffffff0)); -} - -/** - * \brief set interrupt secure or not secure - * - * \param[in] intno interrupt number - * \param[in] secure, 0 for normal, >0 for secure - */ -Inline void arc_int_secure_set(const uint32_t intno, uint32_t secure) -{ - - _arc_aux_write(AUX_IRQ_SELECT, intno); - - if (secure) { - _arc_aux_write(AUX_IRQ_PRIORITY, _arc_aux_read(AUX_IRQ_PRIORITY) | - (1 << AUX_IRQ_PRIORITY_BIT_S)); - } else { - _arc_aux_write(AUX_IRQ_PRIORITY, _arc_aux_read(AUX_IRQ_PRIORITY) & 0xf); - } - -} - -/** - * \brief probe the pending status of interrupt - * - * \param[in] intno interrupt number - * - * \returns 1 pending, 0 no pending - */ -Inline uint32_t arc_int_probe(const uint32_t intno) -{ - _arc_aux_write(AUX_IRQ_SELECT, intno); - return _arc_aux_read(AUX_IRQ_PENDING); -} - -/** - * \brief trigger the interrupt in software - * - * \param[in] intno interrupt number - */ -Inline void arc_int_sw_trigger(const uint32_t intno) -{ - _arc_aux_write(AUX_IRQ_HINT, intno); -} - -/** - * \brief config the interrupt level triggered or pulse triggered - * - * \param[in] intno interrupt number - * \param[in] level, 0-level trigger, 1-pluse triggered - */ -Inline void arc_int_level_config(const uint32_t intno, const uint32_t level) -{ - _arc_aux_write(AUX_IRQ_SELECT, intno); - _arc_aux_write(AUX_IRQ_TRIGGER, level); -} - -/** - * \brief lock cpu, disable interrupts - */ -Inline void arc_lock(void) -{ - Asm("clri"); - Asm("":::"memory"); -} - -/** - * \brief unlock cpu, enable interrupts to happen - */ -Inline void arc_unlock(void) -{ - Asm("":::"memory"); - Asm("seti"); -} - -/** - * \brief lock cpu and staus - * - * \returns cpu status - */ -Inline uint32_t arc_lock_save(void) -{ - return _arc_clri(); -} - -/** - * \brief unlock cpu with the specific status - * - * \param[in] status cpu status saved by cpu_lock_save - */ -Inline void arc_unlock_restore(const uint32_t status) -{ - _arc_seti(status); -} -/** @}*/ - -/** - * \addtogroup ARC_HAL_EXCEPTION_CPU - * @{ - */ -/** - * \typedef EXC_ENTRY - * \brief the data type for exception entry - */ -typedef void (*EXC_ENTRY) (void); -/** - * \typedef EXC_HANDLER - * \brief the data type for exception handler - */ -typedef void (*EXC_HANDLER) (void *exc_frame); -/** @}*/ - - -/** - * \ingroup ARC_HAL_EXCEPTION_INTERRUPT - * \typedef INT_HANDLER - * \brief the data type for interrupt handler - */ -typedef void (*INT_HANDLER) (void *ptr); - -extern EXC_ENTRY exc_entry_table[NUM_EXC_ALL]; -extern EXC_HANDLER exc_int_handler_table[NUM_EXC_ALL]; - -/** \ingroup ARC_HAL_EXCEPTION_CPU - * @{ - */ -/** - * \fn _arc_reset - * \brief the reset entry - */ -extern void _arc_reset(void); -/** - * \fn exc_entry_cpu - * \brief the default CPU exception entry - */ -extern void exc_entry_cpu(void); - -/** - * \fn exc_entry_firq - * \brief the fast interrupt exception entry - */ -extern void exc_entry_firq(void); -/** - * \fn exc_entry_int - * \brief the interrupt exception entry - */ -extern void exc_entry_int(void); -/** @}*/ - -/* excetpion related apis */ -extern void exc_int_init(void); -extern int32_t exc_entry_install(const uint32_t excno, EXC_ENTRY entry); -extern EXC_ENTRY exc_entry_get(const uint32_t excno); -extern int32_t exc_handler_install(const uint32_t excno, EXC_HANDLER handler); -extern EXC_HANDLER exc_handler_get(const uint32_t excno); - -/* interrupt related apis */ -extern int32_t int_disable(const uint32_t intno); -extern int32_t int_enable(const uint32_t intno); -extern int32_t int_enabled(const uint32_t intno); -extern int32_t int_ipm_get(void); -extern int32_t int_ipm_set(int32_t intpri); -extern int32_t int_pri_get(const uint32_t intno); -extern int32_t int_pri_set(const uint32_t intno, int32_t intpri); -extern int32_t int_probe(const uint32_t intno); -extern int32_t int_sw_trigger(const uint32_t intno); -extern int32_t int_level_config(const uint32_t intno, const uint32_t level); -extern void cpu_lock(void); -extern void cpu_unlock(void); -extern uint32_t cpu_lock_save(void); -extern void cpu_unlock_restore(const uint32_t status); -extern int32_t int_handler_install(const uint32_t intno, INT_HANDLER handler); -extern INT_HANDLER int_handler_get(const uint32_t intno); -extern int32_t int_secure_set(const uint32_t intno, uint32_t secure); - -#ifdef __cplusplus -} -#endif - -#endif /* _ARC_HAL_EXCEPTION_H_*/ diff --git a/bsp/synopsys/embarc/inc/arc/arc_feature_config.h b/bsp/synopsys/embarc/inc/arc/arc_feature_config.h deleted file mode 100644 index 87b1913df5336f061788f26e581061e1f665a1cd..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/inc/arc/arc_feature_config.h +++ /dev/null @@ -1,397 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2016-09-08 - * \author Huaqi Fang(Huaqi.Fang@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup ARC_HAL_MISC - * \brief header file for arc feature configuration - */ - -/** - * \addtogroup ARC_HAL_MISC - * @{ - */ - -#ifndef _ARC_FEATURE_CONFIG_H_ -#define _ARC_FEATURE_CONFIG_H_ - -// Enable core_config.h in EMSK OSP -//#ifdef EMBARC_TCF_GENERATED -#include "arc_core_config.h" -//#endif - -/** ARC baseline instruction set version number */ -#if !defined(_ARCVER) -#if defined(core_config_cir_identity_arcver) -#define _ARCVER core_config_cir_identity_arcver -#else -#define _ARCVER 0x42 -#endif -#endif - -/** ARC CPU Clock Frequency in Hz unit */ -#if !defined(ARC_FEATURE_CPU_CLOCK_FREQ) -#if defined(core_config_clock_speed) -#define ARC_FEATURE_CPU_CLOCK_FREQ (core_config_clock_speed*1000000) -#endif -#endif - -/** ARC PC size */ -#if !defined(ARC_FEATURE_PC_SIZE) -#if defined(core_config_pc_size) -#define ARC_FEATURE_PC_SIZE core_config_pc_size -#else -#define ARC_FEATURE_PC_SIZE 32 -#endif -#endif - -/** ARC LPC size */ -#if !defined(ARC_FEATURE_LPC_SIZE) -#if defined(core_config_lpc_size) -#define ARC_FEATURE_LPC_SIZE core_config_lpc_size -#else -#define ARC_FEATURE_LPC_SIZE 32 -#endif -#endif - -/** ARC Addr size */ -#if !defined(ARC_FEATURE_ADDR_SIZE) -#if defined(core_config_addr_size) -#define ARC_FEATURE_ADDR_SIZE core_config_addr_size -#else -#define ARC_FEATURE_ADDR_SIZE 32 -#endif -#endif - -/** ARC Endian/Byte Order */ -#define ARC_FEATURE_LITTLE_ENDIAN 1234 -#define ARC_FEATURE_BIG_ENDIAN 4321 - -#if !defined(ARC_FEATURE_BYTE_ORDER) -#if defined(core_config_bcr_isa_config_b) -#if core_config_bcr_isa_config_b == 0 -#define ARC_FEATURE_BYTE_ORDER ARC_FEATURE_LITTLE_ENDIAN -#else -#define ARC_FEATURE_BYTE_ORDER ARC_FEATURE_BIG_ENDIAN -#endif -#else -#define ARC_FEATURE_BYTE_ORDER ARC_FEATURE_LITTLE_ENDIAN -#endif -#endif - -/** Reduced register option, if enabled, ARC_FEATURE_RF16 will be defined */ -#if !defined(ARC_FEATURE_RF16) -#if defined(core_config_bcr_rf_build_e) && core_config_bcr_rf_build_e == 1 -#define ARC_FEATURE_RF16 -#endif -#endif - -/** Unaligned access option, if enabled, ARC_FEATURE_UNALIGNED will be defined */ -#if !defined(ARC_FEATURE_UNALIGNED) -#if defined(core_config_unaligned) && core_config_unaligned == 1 -#define ARC_FEATURE_UNALIGNED -#endif -#endif - - -/** Code density option, if enabled, ARC_FEATURE_CODE_DENSITY will be defined */ -#if !defined(ARC_FEATURE_CODE_DENSITY) -#if defined(core_config_code_density) && core_config_code_density == 1 -#define ARC_FEATURE_CODE_DENSITY -#endif -#endif - -/** The number of register file banks */ -#if !defined(ARC_FEATURE_RGF_NUM_BANKS) -#if defined(core_config_rgf_num_banks) -#define ARC_FEATURE_RGF_NUM_BANKS core_config_rgf_num_banks -#else -#define ARC_FEATURE_RGF_NUM_BANKS 1 -#endif -#endif - -/** The number of registers replicated per register bank */ -#if !defined(ARC_FEATURE_RGF_BANKED_REGS) -#if defined(core_config_rgf_banked_regs) -#define ARC_FEATURE_RGF_BANKED_REGS core_config_rgf_banked_regs -#endif -#endif - -/** Interrupt unit presence */ -#if !defined(ARC_FEATURE_INTERRUPTS_PRESENT) -#if defined(core_config_interrupts_present) -#define ARC_FEATURE_INTERRUPTS_PRESENT core_config_interrupts_present -#endif -#endif - -/** FIRQ_OPTION configuration option, 1 for enabled, 0 for disabled */ -#if !defined(ARC_FEATURE_FIRQ) -#if defined(core_config_bcr_irq_build_f) -#define ARC_FEATURE_FIRQ core_config_bcr_irq_build_f -#else -#define ARC_FEATURE_FIRQ 0 -#endif -#endif - -/** The number of interrupts */ -#if !defined(NUM_EXC_INT) -#if defined(core_config_interrupts_number) -#define NUM_EXC_INT core_config_interrupts_number -#endif -#endif - -/** The number of external interrupts */ -#if !defined(NUM_EXC_EXT_INT) -#if defined(core_config_interrupts_externals) -#define NUM_EXC_EXT_INT core_config_interrupts_externals -#endif -#endif - -/** The interrupt priority levels */ -#if !defined(INT_PRI_MIN) -#if defined(core_config_interrupts_priorities) -#define INT_PRI_MIN (-core_config_interrupts_priorities) -#endif -#endif - -// ARC TIMER_BUILD -/** Timer0 present or not */ -#if !defined(ARC_FEATURE_TIMER0_PRESENT) -#if defined(core_config_timer0) -#define ARC_FEATURE_TIMER0_PRESENT core_config_timer0 -#define ARC_FEATURE_TIMER0_LEVEL (core_config_timer0_level-core_config_interrupts_priorities) -#define ARC_FEATURE_TIMER0_VECTOR core_config_timer0_vector -#endif -#endif - -/** Timer1 present or not */ -#if !defined(ARC_FEATURE_TIMER1_PRESENT) -#if defined(core_config_timer1) -#define ARC_FEATURE_TIMER1_PRESENT core_config_timer1 -#define ARC_FEATURE_TIMER1_LEVEL (core_config_timer1_level-core_config_interrupts_priorities) -#define ARC_FEATURE_TIMER1_VECTOR core_config_timer1_vector -#endif -#endif - -/** Secure Timer0 present or not */ -#if !defined(ARC_FEATURE_SEC_TIMER0_PRESENT) -#if defined(core_config_sec_timer0) -#define ARC_FEATURE_SEC_TIMER0_PRESENT core_config_sec_timer0 -#define ARC_FEATURE_SEC_TIMER0_LEVEL (core_config_sec_timer0_level-core_config_interrupts_priorities) -#define ARC_FEATURE_SEC_TIMER0_VECTOR 20 -#endif -#endif - -/** Secure Timer1 present or not */ -#if !defined(ARC_FEATURE_SEC_TIMER1_PRESENT) -#if defined(core_config_sec_timer1) -#define ARC_FEATURE_SEC_TIMER1_PRESENT core_config_sec_timer1 -#define ARC_FEATURE_SEC_TIMER1_LEVEL (core_config_sec_timer1_level-core_config_interrupts_priorities) -#define ARC_FEATURE_SEC_TIMER1_VECTOR 21 -#endif -#endif - - -/** 64bit RTC present or not */ -#if !defined(ARC_FEATURE_RTC_PRESENT) -#if defined(core_config_rtc) -#define ARC_FEATURE_RTC_PRESENT core_config_rtc -#endif -#endif - -// Memory related definitions -/** ICCM Presence, base address and size */ -#if !defined(ARC_FEATURE_ICCM_PRESENT) -#if defined(core_config_iccm_present) && core_config_iccm_present == 1 -#define ARC_FEATURE_ICCM_PRESENT 1 -#define ARC_FEATURE_ICCM_BASE core_config_iccm_base -#define ARC_FEATURE_ICCM_SIZE core_config_iccm_size -#endif -#endif - -/** ICCM0 Presence, base address and size */ -#if !defined(ARC_FEATURE_ICCM0_PRESENT) -#if defined(core_config_iccm0_present) && core_config_iccm0_present == 1 -#define ARC_FEATURE_ICCM0_PRESENT 1 -#define ARC_FEATURE_ICCM0_BASE core_config_iccm0_base -#define ARC_FEATURE_ICCM0_SIZE core_config_iccm0_size -#endif -#endif - -/** ICCM1 Presence, base address and size */ -#if !defined(ARC_FEATURE_ICCM1_PRESENT) -#if defined(core_config_iccm1_present) && core_config_iccm1_present == 1 -#define ARC_FEATURE_ICCM1_PRESENT 1 -#define ARC_FEATURE_ICCM1_BASE core_config_iccm1_base -#define ARC_FEATURE_ICCM1_SIZE core_config_iccm1_size -#endif -#endif - -/** DCCM Presence, base address and size */ -#if !defined(ARC_FEATURE_DCCM_PRESENT) -#if defined(core_config_dccm_present) && core_config_dccm_present == 1 -#define ARC_FEATURE_DCCM_PRESENT 1 -#define ARC_FEATURE_DCCM_BASE core_config_dccm_base -#define ARC_FEATURE_DCCM_SIZE core_config_dccm_size -#ifdef core_config_dccm_interleave -#define ARC_FEATURE_DCCM_INTERLEAVE core_config_dccm_interleave -#endif -#endif -#endif - -/** Peripheral memory region(DMP) base address, if dmp configured, this macro will be defined as base address */ -#if !defined(ARC_FEATURE_DMP_PERIPHERAL) -#if defined(core_config_cir_dmp_peripheral) -#define ARC_FEATURE_DMP_PERIPHERAL core_config_cir_dmp_peripheral -#endif -#endif - -/** MPU options */ -#if !defined(ARC_FEATURE_MPU_PRESENT) -#if defined(core_config_mpu_present) && core_config_mpu_present == 1 -#define ARC_FEATURE_MPU_PRESENT 1 -#define ARC_FEATURE_MPU_VERSION core_config_bcr_mpu_build_version -#define ARC_FEATURE_MPU_REGIONS core_config_mpu_regions -#ifdef core_config_bcr_mpu_build_i -#define ARC_FEATURE_MPU_BUILD_I core_config_bcr_mpu_build_i -#endif -#ifdef core_config_bcr_mpu_build_s -#define ARC_FEATURE_MPU_BUILD_S core_config_bcr_mpu_build_s -#endif -#endif -#endif - -/** Secure BCR SEC_BUILD BCR */ -#if !defined(ARC_FEATURE_SEC_PRESENT) -#if defined(core_config_bcr_sec_build) -#define ARC_FEATURE_SEC_PRESENT 1 -#define ARC_FEATURE_SEC_VERSION core_config_bcr_sec_build_version -#define ARC_FEATURE_SEC_BUILD_DSM core_config_bcr_sec_build_dsm -#define ARC_FEATURE_SEC_BUILD_NSM core_config_bcr_sec_build_nsm -#define ARC_FEATURE_SEC_BUILD_I1SM core_config_bcr_sec_build_i1sm -#define ARC_FEATURE_SEC_BUILD_I0SM core_config_bcr_sec_build_i0sm -#define ARC_FEATURE_SEC_BUILD_S core_config_bcr_sec_build_s -#define ARC_FEATURE_SEC_BUILD_EI core_config_bcr_sec_build_ei -#define ARC_FEATURE_SEC_BUILD_ED core_config_bcr_sec_build_ed -#endif -#endif - -#if !defined(ARC_FEATURE_SEC_MODES) -#if defined(core_config_sec_modes) -#define ARC_FEATURE_SEC_MODES core_config_sec_modes -#endif -#endif - -/** Data Cache options */ -#if !defined(ARC_FEATURE_DCACHE_PRESENT) -#if defined(core_config_dcache_present) && core_config_dcache_present == 1 -#define ARC_FEATURE_DCACHE_PRESENT 1 -#define ARC_FEATURE_DCACHE_BUILD core_config_bcr_d_cache_build -#define ARC_FEATURE_DCACHE_BUILD_VERSION core_config_bcr_d_cache_build_version -#define ARC_FEATURE_DCACHE_BUILD_ASSOC core_config_bcr_d_cache_build_assoc -#define ARC_FEATURE_DCACHE_BUILD_CAPACITY core_config_bcr_d_cache_build_capacity -#define ARC_FEATURE_DCACHE_BUILD_BSIZE core_config_bcr_d_cache_build_bsize -#define ARC_FEATURE_DCACHE_BUILD_FL core_config_bcr_d_cache_build_fl -#define ARC_FEATURE_DCACHE_BUILD_U core_config_bcr_d_cache_build_u -#define ARC_FEATURE_DCACHE_SIZE core_config_dcache_size -#define ARC_FEATURE_DCACHE_LINE_SIZE core_config_dcache_line_size -#define ARC_FEATURE_DCACHE_WAYS core_config_dcache_ways -#define ARC_FEATURE_DCACHE_FEATURE core_config_dcache_feature -#endif -#endif - -/** Instruction Cache options */ -#if !defined(ARC_FEATURE_ICACHE_PRESENT) -#if defined(core_config_icache_present) && core_config_icache_present == 1 -#define ARC_FEATURE_ICACHE_PRESENT 1 -#define ARC_FEATURE_ICACHE_BUILD core_config_bcr_i_cache_build -#define ARC_FEATURE_ICACHE_BUILD_VERSION core_config_bcr_i_cache_build_version -#define ARC_FEATURE_ICACHE_BUILD_ASSOC core_config_bcr_i_cache_build_assoc -#define ARC_FEATURE_ICACHE_BUILD_CAPACITY core_config_bcr_i_cache_build_capacity -#define ARC_FEATURE_ICACHE_BUILD_BSIZE core_config_bcr_i_cache_build_bsize -#define ARC_FEATURE_ICACHE_BUILD_FL core_config_bcr_i_cache_build_fl -#define ARC_FEATURE_ICACHE_BUILD_D core_config_bcr_i_cache_build_d -#define ARC_FEATURE_ICACHE_SIZE core_config_icache_size -#define ARC_FEATURE_ICACHE_LINE_SIZE core_config_icache_line_size -#define ARC_FEATURE_ICACHE_WAYS core_config_icache_ways -#define ARC_FEATURE_ICACHE_FEATURE core_config_icache_feature -#endif -#endif - -/** ARC uDMA options */ -#if !defined(ARC_FEATURE_DMAC) -#if defined(core_config_dmac) -#define ARC_FEATURE_DMAC core_config_dmac -#define CORE_DMAC_CHANNELS core_config_dmac_channels -#define CORE_DMAC_REGISTERS core_config_dmac_registers -#if core_config_bcr_dmac_build_int_cfg == 2 && core_config_bcr_dmac_build_int_cfg == 4 -#define DMA_MULTI_IRQ 1 -#else -#define DMA_MULTI_IRQ 0 -#endif -#define ARC_FEATURE_DMAC_PRESENT core_config_dmac -#define ARC_FEATURE_DMAC_VERSION core_config_bcr_dmac_build_version -#define ARC_FEATURE_DMAC_CHANNELS core_config_dmac_channels -#define ARC_FEATURE_DMAC_REGISTERS core_config_dmac_registers -#define ARC_FEATURE_DMAC_INT_CFG core_config_bcr_dmac_build_int_cfg -#define ARC_FEATURE_DMAC_FIFO_DEPTH core_config_dmac_fifo_depth - -#ifdef ARC_FEATURE_SEC_TIMER0_PRESENT -#define DMA_IRQ_NUM_START 22 -#define ARC_FEATURE_DMAC_VECTOR_START 22 -#else -#define DMA_IRQ_NUM_START 20 -#define ARC_FEATURE_DMAC_VECTOR_START 20 -#endif - -#endif -#endif - - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef ARC_FEATURE_UNALIGNED -#define STATUS32_RESET_VALUE (1<<19) -#else -#define STATUS32_RESET_VALUE (0) -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _ARC_FEATURE_CONFIG_H_ */ - -/** @} */ diff --git a/bsp/synopsys/embarc/inc/arc/arc_timer.h b/bsp/synopsys/embarc/inc/arc/arc_timer.h deleted file mode 100644 index b5237f31a9b831a2f9937cc3a5c6176b81c86286..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/inc/arc/arc_timer.h +++ /dev/null @@ -1,99 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-07-15 - * \author Wayne Ren(Wei.Ren@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup ARC_HAL_MISC_TIMER - * \brief header file of ARC internal timer - */ - -/** - * \addtogroup ARC_HAL_MISC_TIMER - * @{ - */ - -#ifndef _ARC_HAL_TIMER_H_ -#define _ARC_HAL_TIMER_H_ -#include "inc/arc/arc.h" -#include "inc/embARC_toolchain.h" - -/** - * \name arc internal timers names - * @{ - */ -#define TIMER_0 0 /*!< macro name for arc internal timer 0 */ -#define TIMER_1 1 /*!< macro name for arc internal timer 1 */ -#define TIMER_RTC 2 /*!< macro name for arc internal RTC */ - -/** @} */ - -/** - * \name bit definition of RTC CTRL reg - * @{ - */ - -#define TIMER_RTC_ENABLE 0x01 /*!< enable RTC */ -#define TIMER_RTC_CLEAR 0x02 /* clears the AUX_RTC_LOW and AUX_RTC_HIGH */ -#define TIMER_RTC_STATUS_A0 0x40000000 /*!< track bit of atomicity of reads of RTC */ -#define TIMER_RTC_STATUS_A1 0x80000000 /*!< track bit of atomicity of reads of RTC */ - -/** @} */ - -/** - * \name bit definition of timer CTRL reg - * @{ - */ -#define TIMER_CTRL_IE (1 << 0) /*!< Interrupt when count reaches limit */ -#define TIMER_CTRL_NH (1 << 1) /*!< Count only when CPU NOT halted */ -#define TIMER_CTRL_W (1 << 2) /*!< watchdog enable */ -#define TIMER_CTRL_IP (1 << 3) /*!< interrupt pending */ - -/** @} */ - -#ifdef __cplusplus -extern "C" { -#endif - -extern int32_t arc_timer_present(const uint32_t no); -extern int32_t arc_timer_start(const uint32_t no, const uint32_t mode, const uint32_t val); -extern int32_t arc_timer_stop(const uint32_t no); -extern int32_t arc_timer_current(const uint32_t no, void* val); -extern int32_t arc_timer_int_clear(const uint32_t no); -extern void arc_timer_init(void); - -#ifdef __cplusplus -} -#endif - -#endif /* _ARC_HAL_TIMER_H_ */ -/** }@*/ diff --git a/bsp/synopsys/embarc/inc/embARC_debug.h b/bsp/synopsys/embarc/inc/embARC_debug.h deleted file mode 100644 index 092374622d1a51cc65f9711a48766bcf72fb047a..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/inc/embARC_debug.h +++ /dev/null @@ -1,94 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2017, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2017.03 - * \date 2014-12-26 - * \author Wayne Ren(Wei.Ren@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup EMBARC_DEBUG - * \brief necessary definitions of debug - */ - -#ifndef _EMBARC_DEBUG_H_ -#define _EMBARC_DEBUG_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef EMBARC_PRINTF - #include "common/xprintf.h" - #define EMBARC_PRINTF xprintf -#endif - -/* - * if you want to use DBG or dbg_printf, - * please define DEBUG or DBG_LESS or DBG_MORE before include embARC_debug.h - * DEBUG: enable debug print - * DBG_LESS: enable less debug msg - * DBG_MORE: enable more debug msg - **/ - -#if defined(DEBUG) -#if defined(DEBUG_HOSTLINK) -#include -#define DBG(fmt, ...) printf(fmt, ##__VA_ARGS__) -#else -#define DBG(fmt, ...) EMBARC_PRINTF(fmt, ##__VA_ARGS__) -#endif -#else -#define DBG(fmt, ...) -#endif - -#define DBG_LESS_INFO 0x01 /* less debug messages */ -#define DBG_MORE_INFO 0x02 /* more debug messages */ - - -#if defined (DBG_LESS) -#define DBG_TYPE (DBG_LESS_INFO) -#elif defined (DBG_MORE) -#define DBG_TYPE ((DBG_LESS_INFO) | (DBG_MORE_INFO)) -#else -#define DBG_TYPE 0 -#endif - -#if DBG_TYPE > 0 -#define dbg_printf(type, fmt, ...) \ - if (((type) & DBG_TYPE)) { EMBARC_PRINTF(fmt, ##__VA_ARGS__); } -#else -#define dbg_printf(type, fmt, ...) -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* DEBUG_H_ */ diff --git a/bsp/synopsys/embarc/inc/embARC_error.h b/bsp/synopsys/embarc/inc/embARC_error.h deleted file mode 100644 index 9bd9c318aabec0faa4663e7d4c95270474845da9..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/inc/embARC_error.h +++ /dev/null @@ -1,156 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-12-25 - * \author Wayne Ren(Wei.Ren@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup EMBARC_ERROR - * \brief header file to define common definitions error management - */ - -/** - * \addtogroup EMBARC_ERROR - * @{ - */ - -#ifndef _EMBARC_ERROR_H_ -#define _EMBARC_ERROR_H_ - -#include -#include "inc/arc/arc_builtin.h" - -#ifdef __cplusplus -extern "C" { -#endif -/** - * \name Main Error Code Definitions - * @{ - */ -#define E_OK (0) /*!< ok */ -#define E_SYS (-5) /*!< system error */ -#define E_NOSPT (-9) /*!< unsupported features */ -#define E_RSFN (-10) /*!< reserved function code */ -#define E_RSATR (-11) /*!< reserved attribute */ -#define E_PAR (-17) /*!< parameter error */ -#define E_ID (-18) /*!< invalid ID number */ -#define E_CTX (-25) /*!< context error */ -#define E_MACV (-26) /*!< memory access violation */ -#define E_OACV (-27) /*!< object access violation */ -#define E_ILUSE (-28) /*!< illegal service call use */ -#define E_NOMEM (-33) /*!< insufficient memory */ -#define E_NOID (-34) /*!< no ID number available */ -#define E_NORES (-35) /*!< no resource available */ -#define E_OBJ (-41) /*!< object state error */ -#define E_NOEXS (-42) /*!< non-existent object */ -#define E_QOVR (-43) /*!< queue overflow */ -#define E_RLWAI (-49) /*!< forced release from waiting */ -#define E_TMOUT (-50) /*!< polling failure or timeout */ -#define E_DLT (-51) /*!< waiting object deleted */ -#define E_CLS (-52) /*!< waiting object state changed */ -#define E_WBLK (-57) /*!< non-blocking accepted */ -#define E_BOVR (-58) /*!< buffer overflow */ -#define E_OPNED (-6) /*!< device is opened */ -#define E_CLSED (-7) /*!< device is closed */ -/** @} end of name */ - -/** - * \name Generate And Decompose Error Code - * @{ - */ -#ifndef ERCD -/** generate error code using main error code and sub error code */ -#define ERCD(mercd, sercd) \ - ((uint32_t)((((uint32_t) sercd) << 8) | (((uint32_t) mercd) & 0xffU))) -#endif /* ERCD */ - -#ifndef MERCD -#ifdef INT8_MAX -/** get main error code from error code */ -#define MERCD(ercd) ((uint32_t)((int8_t)(ercd))) -#else /* INT8_MAX */ -/** get main error code from error code */ -#define MERCD(ercd) ((uint32_t)(((uint32_t) ercd) | ~0xffU)) -#endif /* INT8_MAX */ -#endif /* MERCD */ - -#ifndef SERCD -/** get sub error code from error code */ -#define SERCD(ercd) ((uint32_t)((ercd) >> 8)) -#endif /* SERCD */ -/** @} end of name */ - -/** - * \name Check Error - * @{ - */ -/** - * \brief check an expression to see if it is right, and when error - * set the ercd, and goto exit_label - * \param EXPR the expression that need to be checked (==0 failed) - * \param ERCD MUST pass a variable to here to get the error code - * \param ERROR_CODE error code that pass to ERCD - * \param EXIT_LABEL a label to go when error happens - */ -#define CHECK_EXP(EXPR, ERCD, ERROR_CODE, EXIT_LABEL) { \ - if (_arc_rarely(!(EXPR))) { \ - ERCD = (ERROR_CODE); \ - goto EXIT_LABEL; \ - } \ - } -/** - * \brief check an expression to see if it is right, and when error - * directly goto exit_label - * \param EXPR the expression that need to be checked (==0 failed) - * \param EXIT_LABEL a label to go when error happens - * \retval - */ -#define CHECK_EXP_NOERCD(EXPR, EXIT_LABEL) { \ - if (_arc_rarely(!(EXPR))) { \ - goto EXIT_LABEL; \ - } \ - } -/** check cnt bytes align, 1 for aligned, 0 for not-aligned */ -#define CHECK_ALIGN_BYTES(pointer, cnt) ((((uint32_t)(pointer)) & (cnt-1)) == 0) -/** check 2 bytes align, 1 for aligned, 0 for not-aligned */ -#define CHECK_ALIGN_2BYTES(pointer) ((((uint32_t)(pointer)) & 0x1) == 0) -/** check 4 bytes align, 1 for aligned, 0 for not-aligned */ -#define CHECK_ALIGN_4BYTES(pointer) ((((uint32_t)(pointer)) & 0x3) == 0) -/** check 8 bytes align, 1 for aligned, 0 for not-aligned */ -#define CHECK_ALIGN_8BYTES(pointer) ((((uint32_t)(pointer)) & 0x7) == 0) -/** @} end of name */ - -#ifdef __cplusplus -} -#endif - -#endif /* _EMBARC_ERROR_H_ */ -/** @} end of group EMBARC_ERROR */ diff --git a/bsp/synopsys/embarc/inc/embARC_toolchain.h b/bsp/synopsys/embarc/inc/embARC_toolchain.h deleted file mode 100644 index 37aef66064b0ec25fae7c0748b1135e8f012c8c5..0000000000000000000000000000000000000000 --- a/bsp/synopsys/embarc/inc/embARC_toolchain.h +++ /dev/null @@ -1,121 +0,0 @@ -/* ------------------------------------------ - * Copyright (c) 2016, Synopsys, Inc. All rights reserved. - - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - - * 1) Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - - * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * \version 2016.05 - * \date 2014-12-25 - * \author Wayne Ren(Wei.Ren@synopsys.com) ---------------------------------------------- */ - -/** - * \file - * \ingroup TOOLCHAIN - * \brief toolchain dependent definitions - */ - -#include /* C99 standard lib */ -#include /* C99 standard lib */ -#include /* C99 standard lib */ -#include /* C99 standard lib */ - -#include "embARC_BSP_config.h" - -/** - * \addtogroup TOOLCHAIN - * @{ - */ - -#ifndef _EMBARC_TOOLCHAIN_H_ -#define _EMBARC_TOOLCHAIN_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * macro definitions of compiler extend function - */ -#ifndef __cplusplus /* C++ supports inline */ -#if __STDC_VERSION__ < 199901L /* C99 supports inline */ -#ifndef inline -#define inline __inline__ /* inline function */ -#endif -#endif /* __STDC_VERSION__ < 199901L */ -#endif /* __cplusplus */ - -#ifndef Inline -#define Inline static __inline__ /* inline function */ -#endif - -#ifndef __cplusplus /* C++ supports asm */ -#ifndef asm -#define asm __asm__ /* inline asm */ -#endif -#endif /* __cplusplus */ - -#ifndef Asm -#define Asm __asm__ volatile /* inline asm (no optimization) */ -#endif - -/* compiler attributes */ -#define EMBARC_FORCEINLINE __attribute__((always_inline)) -#define EMBARC_NOINLINE __attribute__((noinline)) -#define EMBARC_PACKED __attribute__((packed)) -#define EMBARC_WEAK __attribute__((weak)) -#define EMBARC_ALIAS(f) __attribute__((weak, alias (#f))) -#define EMBARC_LINKTO(f) __attribute__((alias (#f))) -#define EMBARC_NORETURN __attribute__((noreturn)) -#define EMBARC_NAKED __attribute__((naked)) /* function without return */ -#define EMBARC_ALIGNED(x) __attribute__((aligned(x))) - - -/* array count macro */ -#define EMBARC_ARRAY_COUNT(x) (sizeof(x)/sizeof(x[0])) - -/* convert macro argument to string */ -/* note: this needs one level of indirection, accomplished with the helper macro - * __EMBARC_TO_STRING */ -#define __EMBARC_TO_STRING(x) #x -#define EMBARC_TO_STRING(x) __EMBARC_TO_STRING(x) - -#if defined(__GNU__) -/* GNU tool specific definitions */ - -#elif defined(__MW__) -/* Metaware tool specific definitions */ -/* Metaware toolchain related definitions */ - -#else -#error "unsupported toolchain" -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _EMBARC_TOOLCHAIN_H_ */ -/** }@ */ diff --git a/bsp/synopsys/emsk_em9d/README.md b/bsp/synopsys/emsk_em9d/README.md deleted file mode 100644 index d5cc11fe886e42f3c0142712ba29318a842b7db6..0000000000000000000000000000000000000000 --- a/bsp/synopsys/emsk_em9d/README.md +++ /dev/null @@ -1,77 +0,0 @@ -# Synopsys DesignWare ARC EM Starter Kit - -## Overview - -The DesignWare™ ARC™ EM Starter Kit(EMSK, emsk) is a low-cost, versatile -solution enabling rapid software development and software debugging, and -profiling for the ARC EM Family of processors. The EM Family includes the EM4, -EM6, EM5D, EM7D, EM9D, and EM11D cores. - -![EM Starter Kit](figures/emsk_board.jpg) - -The EMSK consists of a hardware platform and a software package, including -pre-installed FPGA images of different configurations of the ARC EM Processor -with peripherals. - -The development board is based on a Xilinx Spartan-6 LX45 FPGA. It supports -hardware extensions using six 2x6 connectors supporting a total of 48 user I/O -pins (plus power and ground pins) that can be used to connect components such -as sensors, actuators, memories, displays, buttons, switches, and -communication devices. A Digilent Pmod™ compatible extension board containing -a four-channel 12-bit A/D converter with an IIC interface and an AC power -adapter are included in the package. - -## Board Resources - -| Hardware | Description | -| -- | -- | -| SOC | EMSK | -| Core | EM9D | -| Arch | 32-bit ARC EM | -| Frequency | 20/25 Mhz | -| RAM | 128 MB DDR RAM + 256 KB Instruction CCM + 256 KB Data CCM | -|Flash | 16 MB SPI Flash for FPGA configuration with 128 KB reserved for application | - -## Usage - -### FPGA Configuration - -Current, only em9d configuration is supported and tested for RT-Thread. However, -it's can be easily applied to other configurations because all emsk configurations almost share the same memory map and periphreals. - -Please refer [EMSK configuration](https://embarc.org/embarc_osp/doc/build/html/board/emsk.html) for details. - -### Toolchain - -The ARC GNU Toolchain offers all of the benefits of open source tools, including complete source code and a large install base. The ARC GNU IDE Installer consists of Eclipse IDE with [ARC GNU plugin for Eclipse](https://github.com/foss-for-synopsys-dwc-arc-processors/arc_gnu_eclipse/releases), [ARC GNU prebuilt toolchain](https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases) and [OpenOCD for ARC](https://github.com/foss-for-synopsys-dwc-arc-processors/openocd>) - -Here, the ARC GNU toolchain is installed to `c:\arc\gnu`. If not, please change the path configuration in rtconfig.py. - -### Compile - -please run the following cmds to compile - - cd /bsp/synopsys/emsk_em9d - scons - -## Debug - -You need to install [Zadig](http://zadig.akeo.ie) to replace the default FTDI driver with WinUSB driver. See [How to Use OpenOCD on Windows](https://github.com/foss-for-synopsys-dwc-arc-processors/arc_gnu_eclipse/wiki/How-to-Use-OpenOCD-on-Windows>) for more information. - -After compile, please use the following cmds to debug - - scons --gdb - - -## Supported Drivers - -| Driver | Supported | Comment | -| ------ | ---- | :------: | -| UART1 | yes | USB-UART for shell & log | -| UART0 | yes | PMOD A UART for UART modules, e.g. esp8266 | - -## Maintainer -- [vonhust](https://github.com/vonhust) - -## Notes - diff --git a/bsp/synopsys/emsk_em9d/drivers/arc_core_config.h b/bsp/synopsys/emsk_em9d/drivers/arc_core_config.h deleted file mode 100644 index 8340e94091779744f2d4c6fbcca28582b85dd201..0000000000000000000000000000000000000000 --- a/bsp/synopsys/emsk_em9d/drivers/arc_core_config.h +++ /dev/null @@ -1,229 +0,0 @@ -/* This file is automatically generated from tcf file. DO NOT EDIT */ -#ifndef __core_config_h - #define __core_config_h 1 - #define core_config_cir_identity 0x00000042 - #define core_config_cir_identity_chipid 0 - #define core_config_cir_identity_arcnum 0 - #define core_config_cir_identity_arcver 66 - #define core_config_cir_identity_family 4 - #define core_config_cir_identity_corever 2 - #define core_config_cir_aux_dccm 0x80000000 - #define core_config_bcr_bcr_ver 0x00000002 - #define core_config_bcr_bcr_ver_version 2 - #define core_config_bcr_vecbase_ac_build 0x00000010 - #define core_config_bcr_rf_build 0x0000c902 - #define core_config_bcr_rf_build_version 2 - #define core_config_bcr_rf_build_p 1 - #define core_config_bcr_rf_build_e 0 - #define core_config_bcr_rf_build_r 0 - #define core_config_bcr_rf_build_b 1 - #define core_config_bcr_rf_build_d 3 - #define core_config_bcr_dccm_build 0x00010904 - #define core_config_bcr_dccm_build_cycles 0 - #define core_config_bcr_dccm_build_interleave 1 - #define core_config_bcr_dccm_build_size1 0 - #define core_config_bcr_dccm_build_size0 9 - #define core_config_bcr_dccm_build_version 4 - #define core_config_bcr_timer_build 0x00010304 - #define core_config_bcr_timer_build_sp1 0 - #define core_config_bcr_timer_build_sp0 0 - #define core_config_bcr_timer_build_p1 0 - #define core_config_bcr_timer_build_p0 1 - #define core_config_bcr_timer_build_st1 0 - #define core_config_bcr_timer_build_st0 0 - #define core_config_bcr_timer_build_rtc 0 - #define core_config_bcr_timer_build_rtsc_ver 1 - #define core_config_bcr_timer_build_rtsc 0 - #define core_config_bcr_timer_build_t0 1 - #define core_config_bcr_timer_build_t1 1 - #define core_config_bcr_timer_build_version 4 - #define core_config_bcr_ap_build 0x00000405 - #define core_config_bcr_ap_build_version 5 - #define core_config_bcr_ap_build_type 4 - #define core_config_bcr_iccm_build 0x00000a04 - #define core_config_bcr_iccm_build_iccm1_size1 0 - #define core_config_bcr_iccm_build_iccm0_size1 0 - #define core_config_bcr_iccm_build_iccm1_size0 0 - #define core_config_bcr_iccm_build_iccm0_size0 10 - #define core_config_bcr_iccm_build_version 4 - #define core_config_bcr_xy_build 0x00001620 - #define core_config_bcr_xy_build_memsize 1 - #define core_config_bcr_xy_build_interleaved 1 - #define core_config_bcr_xy_build_config 2 - #define core_config_bcr_xy_build_version 32 - #define core_config_bcr_dsp_build 0x00003521 - #define core_config_bcr_dsp_build_wide 0 - #define core_config_bcr_dsp_build_itu_pa 1 - #define core_config_bcr_dsp_build_acc_shift 2 - #define core_config_bcr_dsp_build_comp 1 - #define core_config_bcr_dsp_build_divsqrt 1 - #define core_config_bcr_dsp_build_version 33 - #define core_config_bcr_multiply_build 0x00022a06 - #define core_config_bcr_multiply_build_version16x16 2 - #define core_config_bcr_multiply_build_dsp 2 - #define core_config_bcr_multiply_build_cyc 2 - #define core_config_bcr_multiply_build_type 2 - #define core_config_bcr_multiply_build_version32x32 6 - #define core_config_bcr_swap_build 0x00000003 - #define core_config_bcr_swap_build_version 3 - #define core_config_bcr_norm_build 0x00000003 - #define core_config_bcr_norm_build_version 3 - #define core_config_bcr_minmax_build 0x00000002 - #define core_config_bcr_minmax_build_version 2 - #define core_config_bcr_barrel_build 0x00000303 - #define core_config_bcr_barrel_build_version 3 - #define core_config_bcr_barrel_build_shift_option 3 - #define core_config_bcr_isa_config 0x12447402 - #define core_config_bcr_isa_config_d 1 - #define core_config_bcr_isa_config_c 2 - #define core_config_bcr_isa_config_l 0 - #define core_config_bcr_isa_config_n 1 - #define core_config_bcr_isa_config_a 0 - #define core_config_bcr_isa_config_b 0 - #define core_config_bcr_isa_config_addr_size 4 - #define core_config_bcr_isa_config_lpc_size 7 - #define core_config_bcr_isa_config_pc_size 4 - #define core_config_bcr_isa_config_version 2 - #define core_config_bcr_stack_region_build 0x00000002 - #define core_config_bcr_fpu_build 0x00000f02 - #define core_config_bcr_fpu_build_da 0 - #define core_config_bcr_fpu_build_dd 0 - #define core_config_bcr_fpu_build_dc 0 - #define core_config_bcr_fpu_build_df 0 - #define core_config_bcr_fpu_build_dp 0 - #define core_config_bcr_fpu_build_fd 0 - #define core_config_bcr_fpu_build_fm 0 - #define core_config_bcr_fpu_build_sd 1 - #define core_config_bcr_fpu_build_sc 1 - #define core_config_bcr_fpu_build_sf 1 - #define core_config_bcr_fpu_build_sp 1 - #define core_config_bcr_fpu_build_version 2 - #define core_config_bcr_bs_build 0x00000001 - #define core_config_bcr_bs_build_version 1 - #define core_config_bcr_agu_build 0x01988c01 - #define core_config_bcr_agu_build_accordian 1 - #define core_config_bcr_agu_build_wb_size 4 - #define core_config_bcr_agu_build_num_modifier 24 - #define core_config_bcr_agu_build_num_offset 8 - #define core_config_bcr_agu_build_num_addr 12 - #define core_config_bcr_agu_build_version 1 - #define core_config_bcr_dmac_build 0x000a0101 - #define core_config_bcr_dmac_build_int_cfg 1 - #define core_config_bcr_dmac_build_fifo 1 - #define core_config_bcr_dmac_build_chan_mem 0 - #define core_config_bcr_dmac_build_channels 1 - #define core_config_bcr_dmac_build_version 1 - #define core_config_bcr_core_config 0x00000101 - #define core_config_bcr_core_config_turbo_boost 1 - #define core_config_bcr_core_config_version 1 - #define core_config_bcr_irq_build 0x13101401 - #define core_config_bcr_irq_build_raz 0 - #define core_config_bcr_irq_build_f 1 - #define core_config_bcr_irq_build_p 3 - #define core_config_bcr_irq_build_exts 16 - #define core_config_bcr_irq_build_irqs 20 - #define core_config_bcr_irq_build_version 1 - #define core_config_bcr_pct_build 0x08080102 - #define core_config_bcr_pct_build_version 2 - #define core_config_bcr_pct_build_s 1 - #define core_config_bcr_pct_build_i 0 - #define core_config_bcr_pct_build_c 8 - #define core_config_bcr_cc_build 0x006f0004 - #define core_config_bcr_cc_build_version 4 - #define core_config_bcr_cc_build_cc 111 - #define core_config_bcr_ifqueue_build 0x00000002 - #define core_config_bcr_ifqueue_build_bd 0 - #define core_config_bcr_ifqueue_build_version 2 - #define core_config_bcr_smart_build 0x00002003 - #define core_config_bcr_smart_build_version 3 - #define core_config_bcr_smart_build_stack_size 8 - #define core_config_cir_aux_iccm 0x00000000 - #define core_config_cir_dmp_peripheral 0xf0000000 - #define core_config_cir_xccm_base 0xc0000000 - #define core_config_cir_yccm_base 0xe0000000 - #define core_config_family 4 - #define core_config_core_version 2 - #define core_config_family_name "arcv2em" - #define core_config_rgf_num_banks 2 - #define core_config_rgf_banked_regs 32 - #define core_config_rgf_num_wr_ports 2 - #define core_config_endian "little" - #define core_config_endian_little 1 - #define core_config_endian_big 0 - #define core_config_lpc_size 32 - #define core_config_pc_size 32 - #define core_config_addr_size 32 - #define core_config_unaligned 1 - #define core_config_code_density 1 - #define core_config_div_rem "radix2" - #define core_config_div_rem_radix2 1 - #define core_config_turbo_boost 1 - #define core_config_swap 1 - #define core_config_bitscan 1 - #define core_config_mpy_option "mpyd" - #define core_config_mpy_option_num 8 - #define core_config_shift_assist 1 - #define core_config_barrel_shifter 1 - #define core_config_dsp 1 - #define core_config_dsp2 1 - #define core_config_dsp_complex 1 - #define core_config_dsp_divsqrt "radix2" - #define core_config_dsp_divsqrt_radix2 1 - #define core_config_dsp_itu 1 - #define core_config_dsp_accshift "full" - #define core_config_dsp_accshift_full 1 - #define core_config_agu_large 1 - #define core_config_agu_wb_depth 4 - #define core_config_agu_accord 1 - #define core_config_xy 1 - #define core_config_xy_config "dccm_x_y" - #define core_config_xy_config_dccm_x_y 1 - #define core_config_xy_size 8192 - #define core_config_xy_size_KM "8K" - #define core_config_xy_interleave 1 - #define core_config_xy_x_base 0xc0000000 - #define core_config_xy_y_base 0xe0000000 - #define core_config_bitstream 1 - #define core_config_fpus_div 1 - #define core_config_fpu_mac 1 - #define core_config_fpus_mpy_slow 1 - #define core_config_fpus_div_slow 1 - #define core_config_timer0 1 - #define core_config_timer0_level 1 - #define core_config_timer0_vector 16 - #define core_config_timer1 1 - #define core_config_timer1_level 0 - #define core_config_timer1_vector 17 - #define core_config_action_points 2 - #define core_config_stack_check 1 - #define core_config_smart_stack_entries 8 - #define core_config_ifq_present 1 - #define core_config_ifq_entries 1 - #define core_config_interrupts_present 1 - #define core_config_interrupts_number 20 - #define core_config_interrupts_priorities 4 - #define core_config_interrupts_externals 16 - #define core_config_interrupts 20 - #define core_config_interrupt_priorities 4 - #define core_config_ext_interrupts 16 - #define core_config_interrupts_firq 1 - #define core_config_interrupts_base 0x0 - #define core_config_dccm_present 1 - #define core_config_dccm_size 0x20000 - #define core_config_dccm_base 0x80000000 - #define core_config_dccm_interleave 1 - #define core_config_iccm_present 1 - #define core_config_iccm0_present 1 - #define core_config_iccm_size 0x40000 - #define core_config_iccm0_size 0x40000 - #define core_config_iccm_base 0x00000000 - #define core_config_iccm0_base 0x00000000 - #define core_config_pct_counters 8 - #define core_config_dmac 1 - #define core_config_dmac_channels 2 - #define core_config_dmac_registers 0 - #define core_config_dmac_fifo_depth 2 - #define core_config_dmac_int_config "single_internal" - #define core_config_clock_speed 20 -#endif /* __core_config_h */ - diff --git a/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.c b/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.c deleted file mode 100644 index 8701a0e9c76bfb668981469c08fb77d4dc78d411..0000000000000000000000000000000000000000 --- a/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * Copyright (c) 2018, Synopsys, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "inc/arc/arc.h" -#include "inc/arc/arc_builtin.h" - -#include "dw_gpio_obj.h" - -#include "emsk_hardware.h" -/* - * Uncomment this to enable default - * gpio bit handler output message - * by uart - */ - -#ifdef ARC_FEATURE_DMP_PERIPHERAL -#define PERIPHERAL_BASE ARC_FEATURE_DMP_PERIPHERAL -#else -#define PERIPHERAL_BASE _arc_aux_read(AUX_DMP_PERIPHERAL) -#endif - -#if (USE_DW_GPIO_PORT_A) -static DEV_GPIO port_a; -static DW_GPIO_PORT dw_gpio_port_a; -static DEV_GPIO_HANDLER dw_gpio_bit_handler_a[EMSK_GPIO_A_INT_MAX_COUNT]; -static DW_GPIO_BIT_ISR dw_gpio_bit_isr_a = { - EMSK_GPIO_A_INT_MAX_COUNT, dw_gpio_bit_handler_a -}; - -static int32_t porta_open(uint32_t dir) -{ - return dw_gpio_open(&port_a, dir); -} - -static int32_t porta_close(void) -{ - return dw_gpio_close(&port_a); -} - -static int32_t porta_control(uint32_t ctrl_cmd, void *param) -{ - return dw_gpio_control(&port_a, ctrl_cmd, param); -} - -static int32_t porta_write(uint32_t val, uint32_t mask) -{ - return dw_gpio_write(&port_a, val, mask); -} - -static int32_t porta_read(uint32_t *val, uint32_t mask) -{ - return dw_gpio_read(&port_a, val, mask); -} - -static void porta_isr(void *ptr) -{ - dw_gpio_isr_handler(&port_a, ptr); -} - -static void porta_install(void) -{ - uint32_t i; - DEV_GPIO_PTR port_ptr = &port_a; - DEV_GPIO_INFO_PTR info_ptr = &(port_a.gpio_info); - DW_GPIO_PORT_PTR dw_port_ptr = &(dw_gpio_port_a); - - info_ptr->gpio_ctrl = (void *)dw_port_ptr; - info_ptr->opn_cnt = 0; - info_ptr->method = 0; - info_ptr->direction = 0; - info_ptr->extra = 0; - - dw_port_ptr->no = DW_GPIO_PORT_A; - dw_port_ptr->regs = (DW_GPIO_REG_PTR)(PERIPHERAL_BASE|REL_REGBASE_GPIO0); - dw_port_ptr->valid_bit_mask = EMSK_GPIO_A_VALID_MASK; - dw_port_ptr->intno = INTNO_GPIO; - dw_port_ptr->int_handler = porta_isr; - - for (i=0; igpio_bit_isr = &dw_gpio_bit_isr_a; - - port_ptr->gpio_open = porta_open; - port_ptr->gpio_close = porta_close; - port_ptr->gpio_control = porta_control; - port_ptr->gpio_write = porta_write; - port_ptr->gpio_read = porta_read; -} -#endif - -#if (USE_DW_GPIO_PORT_B) -static DEV_GPIO port_b; -static DW_GPIO_PORT dw_gpio_port_b; - -static int32_t portb_open(uint32_t dir) -{ - return dw_gpio_open(&port_b, dir); -} - -static int32_t portb_close(void) -{ - return dw_gpio_close(&port_b); -} - -static int32_t portb_control(uint32_t ctrl_cmd, void *param) -{ - return dw_gpio_control(&port_b, ctrl_cmd, param); -} - -static int32_t portb_write(uint32_t val, uint32_t mask) -{ - return dw_gpio_write(&port_b, val, mask); -} - -static int32_t portb_read(uint32_t *val, uint32_t mask) -{ - return dw_gpio_read(&port_b, val, mask); -} - -static void portb_isr(void *ptr) -{ - dw_gpio_isr_handler(&port_b, ptr); -} - -static void portb_install(void) -{ - DEV_GPIO_PTR port_ptr = &port_b; - DEV_GPIO_INFO_PTR info_ptr = &(port_b.gpio_info); - DW_GPIO_PORT_PTR dw_port_ptr = &(dw_gpio_port_b); - - info_ptr->gpio_ctrl = (void *)dw_port_ptr; - info_ptr->opn_cnt = 0; - info_ptr->method = 0; - info_ptr->direction = 0; - info_ptr->extra = 0; - - dw_port_ptr->no = DW_GPIO_PORT_B; - dw_port_ptr->regs = (DW_GPIO_REG_PTR)(PERIPHERAL_BASE|REL_REGBASE_GPIO0); - dw_port_ptr->valid_bit_mask = EMSK_GPIO_B_VALID_MASK; - - dw_port_ptr->intno = INTNO_GPIO; - dw_port_ptr->int_handler = portb_isr; - dw_port_ptr->gpio_bit_isr = NULL; - - port_ptr->gpio_open = portb_open; - port_ptr->gpio_close = portb_close; - port_ptr->gpio_control = portb_control; - port_ptr->gpio_write = portb_write; - port_ptr->gpio_read = portb_read; -} -#endif - - -#if (USE_DW_GPIO_PORT_C) -static DEV_GPIO port_c; -static DW_GPIO_PORT dw_gpio_port_c; - -static int32_t portc_open(uint32_t dir) -{ - return dw_gpio_open(&port_c, dir); -} - -static int32_t portc_close(void) -{ - return dw_gpio_close(&port_c); -} - -static int32_t portc_control(uint32_t ctrl_cmd, void *param) -{ - return dw_gpio_control(&port_c, ctrl_cmd, param); -} - -static int32_t portc_write(uint32_t val, uint32_t mask) -{ - return dw_gpio_write(&port_c, val, mask); -} - -static int32_t portc_read(uint32_t *val, uint32_t mask) -{ - return dw_gpio_read(&port_c, val, mask); -} - -static void portc_isr(void *ptr) -{ - dw_gpio_isr_handler(&port_c, ptr); -} - -static void portc_install(void) -{ - DEV_GPIO_PTR port_ptr = &port_c; - DEV_GPIO_INFO_PTR info_ptr = &(port_c.gpio_info); - DW_GPIO_PORT_PTR dw_port_ptr = &(dw_gpio_port_c); - - info_ptr->gpio_ctrl = (void *)dw_port_ptr; - info_ptr->opn_cnt = 0; - info_ptr->method = 0; - info_ptr->direction = 0; - info_ptr->extra = 0; - - dw_port_ptr->no = DW_GPIO_PORT_C; - dw_port_ptr->regs = (DW_GPIO_REG_PTR)(PERIPHERAL_BASE|REL_REGBASE_GPIO0); - dw_port_ptr->valid_bit_mask = EMSK_GPIO_C_VALID_MASK; - - dw_port_ptr->intno = INTNO_GPIO; - dw_port_ptr->int_handler = portc_isr; - dw_port_ptr->gpio_bit_isr = NULL; - - port_ptr->gpio_open = portc_open; - port_ptr->gpio_close = portc_close; - port_ptr->gpio_control = portc_control; - port_ptr->gpio_write = portc_write; - port_ptr->gpio_read = portc_read; -} -#endif - -#if (USE_DW_GPIO_PORT_D) -static DEV_GPIO port_d; -static DW_GPIO_PORT dw_gpio_port_d; - -static int32_t portd_open(uint32_t dir) -{ - return dw_gpio_open(&port_d, dir); -} - -static int32_t portd_close(void) -{ - return dw_gpio_close(&port_d); -} - -static int32_t portd_control(uint32_t ctrl_cmd, void *param) -{ - return dw_gpio_control(&port_d, ctrl_cmd, param); -} - -static int32_t portd_write(uint32_t val, uint32_t mask) -{ - return dw_gpio_write(&port_d, val, mask); -} - -static int32_t portd_read(uint32_t *val, uint32_t mask) -{ - return dw_gpio_read(&port_d, val, mask); -} - -static void portd_isr(void *ptr) -{ - dw_gpio_isr_handler(&port_d, ptr); -} - -static void portd_install(void) -{ - DEV_GPIO_PTR port_ptr = &port_d; - DEV_GPIO_INFO_PTR info_ptr = &(port_d.gpio_info); - DW_GPIO_PORT_PTR dw_port_ptr = &(dw_gpio_port_d); - - info_ptr->gpio_ctrl = (void *)dw_port_ptr; - info_ptr->opn_cnt = 0; - info_ptr->method = 0; - info_ptr->direction = 0; - info_ptr->extra = 0; - - dw_port_ptr->no = DW_GPIO_PORT_D; - dw_port_ptr->regs = (DW_GPIO_REG_PTR)(PERIPHERAL_BASE|REL_REGBASE_GPIO0); - dw_port_ptr->valid_bit_mask = EMSK_GPIO_D_VALID_MASK; - - dw_port_ptr->intno = INTNO_GPIO; - dw_port_ptr->int_handler = portd_isr; - dw_port_ptr->gpio_bit_isr = NULL; - - port_ptr->gpio_open = portd_open; - port_ptr->gpio_close = portd_close; - port_ptr->gpio_control = portd_control; - port_ptr->gpio_write = portd_write; - port_ptr->gpio_read = portd_read; -} -#endif - -DEV_GPIO_PTR gpio_get_dev(int32_t gpio_id) -{ - static uint32_t install_flag = 0; - - /* intall device objects */ - if (install_flag == 0) { - install_flag = 1; - dw_gpio_all_install(); - } - - switch (gpio_id) { -#if (USE_DW_GPIO_PORT_A) - case DW_GPIO_PORT_A: return &port_a; -#endif -#if (USE_DW_GPIO_PORT_B) - case DW_GPIO_PORT_B: return &port_b; -#endif -#if (USE_DW_GPIO_PORT_C) - case DW_GPIO_PORT_C: return &port_c; -#endif -#if (USE_DW_GPIO_PORT_D) - case DW_GPIO_PORT_D: return &port_d; -#endif - default: - break; - } - return NULL; -} - -void dw_gpio_all_install(void) -{ -#if (USE_DW_GPIO_PORT_A) - porta_install(); -#endif -#if (USE_DW_GPIO_PORT_B) - portb_install(); -#endif -#if (USE_DW_GPIO_PORT_C) - portc_install(); -#endif -#if (USE_DW_GPIO_PORT_D) - portd_install(); -#endif -} diff --git a/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.h b/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.h deleted file mode 100644 index d39a09159d33bccf840902d6fd49dda152fcbe04..0000000000000000000000000000000000000000 --- a/bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2018, Synopsys, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _DW_GPIO_OBJ_H_ -#define _DW_GPIO_OBJ_H_ - -#include "device/designware/gpio/dw_gpio.h" - -/** - * \name Designware GPIO Port Bank Control Macros - * @{ - */ -#define USE_DW_GPIO_PORT_A 1 -#define USE_DW_GPIO_PORT_B 1 -#define USE_DW_GPIO_PORT_C 1 -#define USE_DW_GPIO_PORT_D 1 -/** @} end of name */ - -/** - * \name Designware GPIO Port Interrupt Available Number Macros - * @{ - */ -#define EMSK_GPIO_A_INT_MAX_COUNT 32 -#define EMSK_GPIO_B_INT_MAX_COUNT 0 -#define EMSK_GPIO_C_INT_MAX_COUNT 0 -#define EMSK_GPIO_D_INT_MAX_COUNT 0 -/** @} end of name */ - -/** - * \name Designware GPIO Port Available Bits Macros - * @{ - */ -#define EMSK_GPIO_A_VALID_MASK DW_GPIO_MASK_ALL -#define EMSK_GPIO_B_VALID_MASK DW_GPIO_MASK_ALL -#define EMSK_GPIO_C_VALID_MASK DW_GPIO_MASK_ALL -#define EMSK_GPIO_D_VALID_MASK DW_GPIO_MASK_ALL -/** @} end of name */ - -#ifdef __cplusplus -extern "C" { -#endif - -extern void dw_gpio_all_install(void); - -#ifdef __cplusplus -} -#endif - -#endif /* _DW_GPIO_OBJ_H_*/ diff --git a/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.c b/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.c deleted file mode 100644 index 9e3ebd3db90179892278d812bedf3fb04944446e..0000000000000000000000000000000000000000 --- a/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.c +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright (c) 2018, Synopsys, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "inc/arc/arc.h" -#include "inc/arc/arc_builtin.h" -#include "inc/embARC_toolchain.h" -#include "inc/embARC_error.h" - -#include "inc/arc/arc_exception.h" -#include "device/designware/uart/dw_uart.h" -#include "dw_uart_obj.h" - -#include "emsk_hardware.h" - -#define DW_UART_FIFO_LEN 32 - -/** - * \name EMSK DesignWare UART 0 Object Instantiation - * @{ - */ -#if (USE_DW_UART_0) -static void dw_uart_0_isr(void *ptr); -#define DW_UART_0_RELBASE (REL_REGBASE_UART0) /*!< designware uart 0 relative baseaddr */ -#define DW_UART_0_INTNO (INTNO_UART0) /*!< designware uart 0 interrupt number */ - -DEV_UART dw_uart_0; /*!< designware uart object */ -DW_UART_CTRL dw_uart_0_ctrl = { /*!< designware uart 0 ctrl */ - 0, CLK_BUS_APB, DW_UART_0_INTNO, (INT_HANDLER)dw_uart_0_isr, - DW_UART_FIFO_LEN, DW_UART_FIFO_LEN, 0 -}; - -/** designware uart 0 open */ -static int32_t dw_uart_0_open (uint32_t baud) -{ - return dw_uart_open(&dw_uart_0, baud); -} -/** designware uart 0 close */ -static int32_t dw_uart_0_close (void) -{ - return dw_uart_close(&dw_uart_0); -} -/** designware uart 0 control */ -static int32_t dw_uart_0_control (uint32_t ctrl_cmd, void *param) -{ - return dw_uart_control(&dw_uart_0, ctrl_cmd, param); -} -/** designware uart 0 write */ -static int32_t dw_uart_0_write (const void *data, uint32_t len) -{ - return dw_uart_write(&dw_uart_0, data, len); -} -/** designware uart 0 close */ -static int32_t dw_uart_0_read (void *data, uint32_t len) -{ - return dw_uart_read(&dw_uart_0, data, len); -} -/** designware uart 0 interrupt rountine */ -static void dw_uart_0_isr(void *ptr) -{ - dw_uart_isr(&dw_uart_0, ptr); -} -/** install designware uart 0 to system */ -static void dw_uart_0_install(void) -{ - uint32_t uart_abs_base = 0; - DEV_UART *dw_uart_ptr = &dw_uart_0; - DEV_UART_INFO *dw_uart_info_ptr = &(dw_uart_0.uart_info); - DW_UART_CTRL *dw_uart_ctrl_ptr = &dw_uart_0_ctrl; - - /** - * get absolute designware base address - */ - uart_abs_base = (uint32_t)PERIPHERAL_BASE + DW_UART_0_RELBASE; - dw_uart_ctrl_ptr->dw_uart_regbase = uart_abs_base; - - /** uart info init */ - dw_uart_info_ptr->uart_ctrl = (void *)dw_uart_ctrl_ptr; - dw_uart_info_ptr->opn_cnt = 0; - dw_uart_info_ptr->status = 0; - dw_uart_info_ptr->baudrate = UART_BAUDRATE_115200; /* default 115200bps */ - - /** uart dev init */ - dw_uart_ptr->uart_open = dw_uart_0_open; - dw_uart_ptr->uart_close = dw_uart_0_close; - dw_uart_ptr->uart_control = dw_uart_0_control; - dw_uart_ptr->uart_write = dw_uart_0_write; - dw_uart_ptr->uart_read = dw_uart_0_read; - -} -#endif /* USE_DW_UART_0 */ -/** @} end of name */ - -/** - * \name EMSK DesignWare UART 1 Object Instantiation - * @{ - */ -#if (USE_DW_UART_1) -static void dw_uart_1_isr(void *ptr); -#define DW_UART_1_RELBASE (REL_REGBASE_UART1) /*!< designware uart 1 relative baseaddr */ -#define DW_UART_1_INTNO (INTNO_UART1) /*!< designware uart 1 interrupt number */ - -DEV_UART dw_uart_1; /*!< designware uart 1 object */ -DW_UART_CTRL dw_uart_1_ctrl = { /*!< designware uart 1 ctrl */ - 0, CLK_BUS_APB, DW_UART_1_INTNO, (INT_HANDLER)dw_uart_1_isr, - DW_UART_FIFO_LEN, DW_UART_FIFO_LEN, 0 -}; - -/** designware uart 1 open */ -static int32_t dw_uart_1_open (uint32_t baud) -{ - return dw_uart_open(&dw_uart_1, baud); -} -/** designware uart 1 close */ -static int32_t dw_uart_1_close (void) -{ - return dw_uart_close(&dw_uart_1); -} -/** designware uart 1 control */ -static int32_t dw_uart_1_control (uint32_t ctrl_cmd, void *param) -{ - return dw_uart_control(&dw_uart_1, ctrl_cmd, param); -} -/** designware uart 1 write */ -static int32_t dw_uart_1_write (const void *data, uint32_t len) -{ - return dw_uart_write(&dw_uart_1, data, len); -} -/** designware uart 1 close */ -static int32_t dw_uart_1_read (void *data, uint32_t len) -{ - return dw_uart_read(&dw_uart_1, data, len); -} -/** designware uart 1 interrupt routine */ -static void dw_uart_1_isr(void *ptr) -{ - dw_uart_isr(&dw_uart_1, ptr); -} -/** install designware uart 1 to system */ -static void dw_uart_1_install(void) -{ - uint32_t uart_abs_base = 0; - DEV_UART *dw_uart_ptr = &dw_uart_1; - DEV_UART_INFO *dw_uart_info_ptr = &(dw_uart_1.uart_info); - DW_UART_CTRL *dw_uart_ctrl_ptr = &dw_uart_1_ctrl; - - /** - * get absolute designware base address - */ - uart_abs_base = (uint32_t)PERIPHERAL_BASE + DW_UART_1_RELBASE; - dw_uart_ctrl_ptr->dw_uart_regbase = uart_abs_base; - - /** uart info init */ - dw_uart_info_ptr->uart_ctrl = (void *)dw_uart_ctrl_ptr; - dw_uart_info_ptr->opn_cnt = 0; - dw_uart_info_ptr->status = 0; - dw_uart_info_ptr->baudrate = UART_BAUDRATE_115200; /* default 115200bps */ - - /** uart dev init */ - dw_uart_ptr->uart_open = dw_uart_1_open; - dw_uart_ptr->uart_close = dw_uart_1_close; - dw_uart_ptr->uart_control = dw_uart_1_control; - dw_uart_ptr->uart_write = dw_uart_1_write; - dw_uart_ptr->uart_read = dw_uart_1_read; -} -#endif /* USE_DW_UART_1 */ -/** @} end of name */ - -/** get one designware device structure */ -DEV_UART_PTR uart_get_dev(int32_t uart_id) -{ - static uint32_t install_flag = 0; - - /* intall device objects */ - if (install_flag == 0) { - install_flag = 1; - dw_uart_all_install(); - } - - switch (uart_id) { -#if (USE_DW_UART_0) - case DW_UART_0_ID: - return &dw_uart_0; - break; -#endif -#if (USE_DW_UART_1) - case DW_UART_1_ID: - return &dw_uart_1; - break; -#endif - default: - break; - } - return NULL; -} - -/** - * \brief install all uart objects - * \note \b MUST be called during system init - */ -void dw_uart_all_install(void) -{ -#if (USE_DW_UART_0) - dw_uart_0_install(); -#endif -#if (USE_DW_UART_1) - dw_uart_1_install(); -#endif -} diff --git a/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.h b/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.h deleted file mode 100644 index 7a63880fabec5291058112e796e553846701dbc9..0000000000000000000000000000000000000000 --- a/bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2018, Synopsys, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _DW_UART_OBJ_H_ -#define _DW_UART_OBJ_H_ - -#include "device/device_hal/inc/dev_uart.h" - -/** - * \name DesignWare UART Object Number - * @{ - */ -#define DW_UART_NUM (2) /*!< DesignWare UART valid number */ -/** @} end of name */ - -/** - * \name Designware UART Object ID Macros - * @{ - */ -#define DW_UART_0_ID 0 /*!< uart 0 id macro */ -#define DW_UART_1_ID 1 /*!< uart 1 id macro */ -/** @} end of name */ - -/** - * \name Designware UART Object Control Macros - * @{ - */ -#define USE_DW_UART_0 1 /*!< enable use designware uart 0 */ -#define USE_DW_UART_1 1 /*!< enable use designware uart 1 */ -/** @} end of name */ - -/** - * \name Designware UART Ringbuffer Size Control Macros - * @{ - */ -#define MAX_SNDBUF_SIZE 256 /*!< max size of uart send buffer */ -#define MAX_RCVBUF_SIZE 10 /*!< max size of uart recv buffer */ -/** @} end of name */ - -#ifdef __cplusplus -extern "C" { -#endif - -extern void dw_uart_all_install(void); - -#ifdef __cplusplus -} -#endif - -#endif /* _DW_UART_OBJ_H_ */ diff --git a/bsp/synopsys/emsk_em9d/drivers/embARC_BSP_config.h b/bsp/synopsys/emsk_em9d/drivers/embARC_BSP_config.h deleted file mode 100644 index 706aac94c45250a2040cbce23f7f954c3917445c..0000000000000000000000000000000000000000 --- a/bsp/synopsys/emsk_em9d/drivers/embARC_BSP_config.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2018, Synopsys, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _EMBARC_BSP_CONFIG_H_ -#define _EMBARC_BSP_CONFIG_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#define BOARD_EMSK -/**************************************************************************** - * BSP Definitions - ****************************************************************************/ -/** - * Toolchain Definition for MetaWare or GNU - */ -//#define __MW__ -#define __GNU__ - -/** - * Must be set. - * If changed, modify .lcf file for - * .stack ALIGN(4) SIZE(524288): {} - * .heap? ALIGN(4) SIZE(524288): {} - */ -#define _STACKSIZE (4 * 1024) -#define _HEAPSZ (32 * 1024) - - - -#ifdef __cplusplus -} -#endif - -#endif /* _EMBARC_CONFIG_BSP_H_ */ diff --git a/bsp/synopsys/emsk_em9d/drivers/emsk_hardware.h b/bsp/synopsys/emsk_em9d/drivers/emsk_hardware.h deleted file mode 100644 index d60e3143898222fbf9306b9bf93c57f524c69cd5..0000000000000000000000000000000000000000 --- a/bsp/synopsys/emsk_em9d/drivers/emsk_hardware.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2018, Synopsys, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _EMSK_HARDWARE_H_ -#define _EMSK_HARDWARE_H_ - -#include "inc/arc/arc_feature_config.h" - -/** CPU Clock Frequency definition */ -#if defined(BOARD_CPU_FREQ) - /*!< Get cpu clock frequency definition from build system */ - #define CLK_CPU (BOARD_CPU_FREQ) -#elif defined(ARC_FEATURE_CPU_CLOCK_FREQ) - /*!< Get cpu clock frequency definition from tcf file */ - #define CLK_CPU (ARC_FEATURE_CPU_CLOCK_FREQ) -#else - /*!< Default cpu clock frequency */ - #define CLK_CPU (20000000) -#endif - -/** Peripheral Bus Reference Clock definition */ -#ifdef BOARD_DEV_FREQ - /*!< Get peripheral bus reference clock defintion from build system */ - #define CLK_BUS_APB (BOARD_DEV_FREQ) -#else - /*!< Default peripheral bus reference clock defintion */ - #define CLK_BUS_APB (50000000U) -#endif - -#ifdef ARC_FEATURE_DMP_PERIPHERAL -#define PERIPHERAL_BASE ARC_FEATURE_DMP_PERIPHERAL -#else -#define PERIPHERAL_BASE _arc_aux_read(AUX_DMP_PERIPHERAL) -#endif - -/* Device Register Base Address */ -#define REL_REGBASE_PINMUX (0x00000000U) /*!< PINMUX */ -#define REL_REGBASE_SPI_MST_CS_CTRL (0x00000014U) /*!< SPI Master Select Ctrl */ -#define REL_REGBASE_GPIO0 (0x00002000U) /*!< GPIO 0 Onboard */ -#define REL_REGBASE_TIMERS (0x00003000U) /*!< DW TIMER */ -#define REL_REGBASE_I2C0 (0x00004000U) /*!< I2C 0 */ -#define REL_REGBASE_I2C1 (0x00005000U) /*!< I2C 1 */ -#define REL_REGBASE_SPI0 (0x00006000U) /*!< SPI Master */ -#define REL_REGBASE_SPI1 (0x00007000U) /*!< SPI Slave */ -#define REL_REGBASE_UART0 (0x00008000U) /*!< UART0 is connected to PMOD */ -#define REL_REGBASE_UART1 (0x00009000U) /*!< UART1 is USB-UART use UART1 as default */ -#define REL_REGBASE_UART2 (0x0000A000U) /*!< UART2 */ -#define REL_REGBASE_WDT (0x0000B000U) /*!< WDT */ -// #define REL_REGBASE_I2S_MASTER_IN (0x0000C000U) /*!< I2S Master In */ -// #define REL_REGBASE_I2S_MASTER_OUT (0x0000D000U) /*!< I2S Master Out */ -// #define REL_REGBASE_GMAC (0x0000E000U) /*!< GMAC */ - -/* Interrupt Connection */ -#define INTNO_TIMER0 16 /*!< ARC Timer0 */ -#define INTNO_TIMER1 17 /*!< ARC Timer1 */ -#define INTNO_SECURE_TIMER0 20 /*!< Core Secure Timer 0 */ -#define INTNO_DMA_START 22 /*!< Core DMA Controller */ -#define INTNO_DMA_COMPLETE 22 /*!< Core DMA Controller Complete */ -#define INTNO_DMA_ERROR 23 /*!< Core DMA Controller Error */ -#define INTNO_GPIO 24 /*!< GPIO controller */ -#define INTNO_I2C0 25 /*!< I2C_0 controller */ -#define INTNO_I2C1 26 /*!< I2C_1 controller */ -#define INTNO_SPI_MASTER 27 /*!< SPI Master controller */ -#define INTNO_SPI_SLAVE 28 /*!< SPI Slave controller */ -#define INTNO_UART0 29 /*!< UART0 */ -#define INTNO_UART1 30 /*!< UART1 */ -#define INTNO_UART2 31 /*!< UART2 */ -#define INTNO_DW_WDT 32 /*!< WDT */ -#define INTNO_DW_TMR0 33 /*!< DW Timer 0 */ -#define INTNO_DW_TMR1 34 /*!< DW Timer 1 */ -// #define INTNO_I2S_Master_In 33 /*!< I2S Master In */ -// #define INTNO_I2S_Master_Out 34 /*!< I2S Master Out */ -// #define INTNO_GMAC 35 /*!< GMAC */ - -/* SPI Mater Signals Usage */ -#define EMSK_SPI_LINE_0 0 /*!< CS0 -- Pmod 6 pin1 */ -#define EMSK_SPI_LINE_1 1 /*!< CS1 -- Pmod 5 pin1 or Pmod 6 pin 7 */ -#define EMSK_SPI_LINE_2 2 /*!< CS2 -- Pmod 6 pin8 */ -#define EMSK_SPI_LINE_SDCARD 3 /*!< CS3 -- On-board SD card */ -#define EMSK_SPI_LINE_SPISLAVE 4 /*!< CS4 -- Internal SPI slave */ -#define EMSK_SPI_LINE_SFLASH 5 /*!< CS5 -- On-board SPI Flash memory */ - -#endif /* _EMSK_HARDWARE_H_ */ diff --git a/bsp/synopsys/emsk_em9d/drivers/mux.c b/bsp/synopsys/emsk_em9d/drivers/mux.c deleted file mode 100644 index a56cb15212ba53b44a326a21e92fa26f8cd611c5..0000000000000000000000000000000000000000 --- a/bsp/synopsys/emsk_em9d/drivers/mux.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2018, Synopsys, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "mux_hal.h" -#include "mux.h" - -static MUX_REG *mux_ctrl_regs = (MUX_REG *)0; - -/** initialize i2c controller and set slave device address */ -void mux_init(MUX_REG *mux_regs) -{ - // Initialize Mux controller registers by default values - mux_regs[PMOD_MUX_CTRL] = PMOD_MUX_CTRL_DEFAULT; - mux_regs[SPI_MAP_CTRL] = SPI_MAP_CTRL_DEFAULT; - mux_regs[UART_MAP_CTRL] = UART_MAP_CTRL_DEFAULT; - mux_ctrl_regs = mux_regs; -} - -/** Get mux ctrl register pointer, only valid after mux_init */ -MUX_REG *get_mux_regs(void) -{ - return mux_ctrl_regs; -} - -/** set PMOD muxer scheme */ -void set_pmod_mux(MUX_REG *mux_regs, uint32_t val) -{ - mux_regs[PMOD_MUX_CTRL] = val; -} - -/** get PMOD muxer scheme */ -uint32_t get_pmod_mux(MUX_REG *mux_regs) -{ - return (uint32_t) mux_regs[PMOD_MUX_CTRL]; -} - -/** set PMOD muxer scheme */ -void change_pmod_mux(MUX_REG *mux_regs, uint32_t val, uint32_t change_bits) -{ - mux_regs[PMOD_MUX_CTRL] = ((mux_regs[PMOD_MUX_CTRL] & ~change_bits) | val); -} - -/** set SPI connection scheme */ -void set_spi_map(MUX_REG *mux_regs, uint32_t val) -{ - mux_regs[SPI_MAP_CTRL] = val; -} - -/** get SPI connection scheme */ -uint32_t get_spi_map(MUX_REG *mux_regs) -{ - return (uint32_t) mux_regs[SPI_MAP_CTRL]; -} - -/** set UART connection scheme */ -void set_uart_map(MUX_REG *mux_regs, uint32_t val) -{ - mux_regs[UART_MAP_CTRL] = val; -} - -/** get UART connection scheme */ -uint32_t get_uart_map(MUX_REG *mux_regs) -{ - return (uint32_t) mux_regs[UART_MAP_CTRL]; -} diff --git a/bsp/synopsys/emsk_em9d/drivers/mux.h b/bsp/synopsys/emsk_em9d/drivers/mux.h deleted file mode 100644 index 47f796bebe52d86c37845a5eba7beff18b75e017..0000000000000000000000000000000000000000 --- a/bsp/synopsys/emsk_em9d/drivers/mux.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2018, Synopsys, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _MUX_H_ -#define _MUX_H_ - -#include "inc/embARC_toolchain.h" - -#define BIT0 (0) -#define BIT1 (1) -#define BIT2 (2) -#define BIT3 (3) -#define PM1_OFFSET (0) -#define PM2_OFFSET (4) -#define PM3_OFFSET (8) -#define PM4_OFFSET (12) -#define PM5_OFFSET (16) -#define PM6_OFFSET (20) -#define PM7_OFFSET (24) - -#define PM1_MASK (0xf << PM1_OFFSET) -#define PM2_MASK (0xf << PM2_OFFSET) -#define PM3_MASK (0xf << PM3_OFFSET) -#define PM4_MASK (0xf << PM4_OFFSET) -#define PM5_MASK (0xf << PM5_OFFSET) -#define PM6_MASK (0xf << PM6_OFFSET) -#define PM7_MASK (0xf << PM7_OFFSET) - - -#define SPI_MAP_NORMAL (0) -#define SPI_MAP_LOOPBACK (1) - -#define UART_MAP_TYPE4 (0xE4) -#define UART_MAP_TYPE3 (0x6C) - -/** - * \name Default pin muxer settings - * @{ - */ -#define PMOD_MUX_CTRL_DEFAULT (0) /*!< all pins are configured as GPIO inputs */ -#define SPI_MAP_CTRL_DEFAULT (SPI_MAP_NORMAL) /*!< normal SPI mode */ -#define UART_MAP_CTRL_DEFAULT (UART_MAP_TYPE4) /*!< TYPE4 PMOD compatible */ -/** @} end of name */ - -/** - * \name PMOD 1 Multiplexor - * @{ - */ -#define PM1_UR_GPIO_C ((0 << BIT0) << PM1_OFFSET) /*!< Pmod1[4:1] are connected to DW GPIO Port C[11:8] */ -#define PM1_UR_UART_0 ((1 << BIT0) << PM1_OFFSET) /*!< Pmod1[4:1] are connected to DW UART0 signals */ - -#define PM1_LR_GPIO_A ((0 << BIT2) << PM1_OFFSET) /*!< Pmod1[10:7] are connected to DW GPIO Port A[11:8] */ -#define PM1_LR_SPI_S ((1 << BIT2) << PM1_OFFSET) /*!< Pmod1[10:7] are connected to DW SPI Slave signals */ -/** @} end of name */ - - -/** - * \name PMOD 2 Multiplexor - * @{ - */ -#define PM2_GPIO_AC ((0 << BIT0) << PM2_OFFSET) /*!< Pmod2[4:1] are connected to DW GPIO Port C[15:12], - Pmod2[10:7] are connected to DW GPIO Port A[15:12] */ - -#define PM2_I2C_HRI ((1 << BIT0) << PM2_OFFSET) /*!< connect I2C to Pmod2[4:1] and halt/run interface to Pmod2[10:7] */ -/** @} end of name */ - - -/** - * \name PMOD 3 Multiplexor - * @{ - */ -#define PM3_GPIO_AC ((0 << BIT0) << PM3_OFFSET) /*!< Pmod3[4:1] are connected to DW GPIO Port C[19:16], - Pmod3[10:7] are connected to DW GPIO Port A[19:16] */ - -#define PM3_I2C_GPIO_D ((1 << BIT0) << PM3_OFFSET) /*!< Pmod3[4:3] are connected to DW I2C signals, - Pmod3[2:1] are connected to DW GPIO Port D[1:0], - Pmod3[10:7] are connected to DW GPIO Port D[3:2] */ -/** @} end of name */ - - -/** - * \name PMOD 4 Multiplexor - * @{ - */ -#define PM4_GPIO_AC ((0 << BIT0) << PM4_OFFSET) /*!< Pmod4[4:1] are connected to DW GPIO Port C[23:20], - Pmod4[10:7] are connected to DW GPIO Port A[23:20] */ - -#define PM4_I2C_GPIO_D ((1 << BIT0) << PM4_OFFSET) /*!< Pmod4[4:3] are connected to DW I2C signals, - Pmod4[2:1] are connected to DW GPIO Port D[5:4], - Pmod4[10:7] are connected to DW GPIO Port D[7:6] */ -/** @} end of name */ - -/** - * \name PMOD 5 Multiplexor - * @{ - */ -#define PM5_UR_GPIO_C ((0 << BIT0) << PM5_OFFSET) /*!< Pmod5[4:1] are connected to DW GPIO Port C[27:24] */ -#define PM5_UR_SPI_M1 ((1 << BIT0) << PM5_OFFSET) /*!< Pmod5[4:1] are connected to DW SPI Master signals using CS1_N */ - -#define PM5_LR_GPIO_A ((0 << BIT2) << PM5_OFFSET) /*!< Pmod5[10:7] are connected to DW GPIO Port A[27:24] */ -#define PM5_LR_SPI_M2 ((1 << BIT2) << PM5_OFFSET) /*!< Pmod5[10:7] are connected to DW SPI Master signals using CS2_N */ -/** @} end of name */ - - -/** - * \name PMOD 6 Multiplexor - * @{ - */ -#define PM6_UR_GPIO_C ((0 << BIT0) << PM6_OFFSET) /*!< Pmod6[4:1] are connected to DW GPIO Port C[31:28] */ -#define PM6_UR_SPI_M0 ((1 << BIT0) << PM6_OFFSET) /*!< Pmod6[4:1] are connected to DW SPI Master signals using CS0_N */ - -#define PM6_LR_GPIO_A ((0 << BIT2) << PM6_OFFSET) /*!< Pmod6[10:7] are connected to DW GPIO Port A[31:28] */ - -#define PM6_LR_CSS_STAT ((1 << BIT2) << PM6_OFFSET) /*!< Pmod6[8:7] are connected to the DW SPI Master chip select signals CS1_N and CS2_N, - Pmod6[6:5] are connected to the ARC EM halt and sleep status signals */ -/** @} end of name */ - -/** - * \name PMOD 7 Multiplexor - * @{ - */ -#define PM7_GPIO_D ((0 << BIT0) << PM7_OFFSET) /*!< Pmod7[4:1] are connected to DW GPIO Port D[11:8] */ -#define PM7_STAT ((1 << BIT0) << PM7_OFFSET) /*!< Pmod7[4:1] are connected to the ARC EM sleep status signals */ -/** @} end of name */ -typedef volatile uint32_t MUX_REG; - -#ifdef __cplusplus -extern "C" { -#endif - -extern void mux_init(MUX_REG *mux_regs); -extern MUX_REG *get_mux_regs(void); -extern void set_pmod_mux(MUX_REG *mux_regs, uint32_t val); -extern uint32_t get_pmod_mux(MUX_REG *mux_regs); -extern void change_pmod_mux(MUX_REG *mux_regs, uint32_t val, uint32_t change_bits); -extern void set_spi_map(MUX_REG *mux_regs, uint32_t val); -extern uint32_t get_spi_map(MUX_REG *mux_regs); -extern void set_uart_map(MUX_REG *mux_regs, uint32_t val); -extern uint32_t get_uart_map(MUX_REG *mux_regs); - -#ifdef __cplusplus -} -#endif - -#endif /* _MUX_H_ */ diff --git a/bsp/synopsys/emsk_em9d/drivers/mux_hal.h b/bsp/synopsys/emsk_em9d/drivers/mux_hal.h deleted file mode 100644 index 9a5c8c14b95be6f400646c2a209af1d6faa8a791..0000000000000000000000000000000000000000 --- a/bsp/synopsys/emsk_em9d/drivers/mux_hal.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2018, Synopsys, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _MUX_HAL_H_ -#define _MUX_HAL_H_ - -/** - * \name Mux Control Register Index - * @{ - */ -#define PMOD_MUX_CTRL 0 /*!< 32-bits, offset 0x0, - This register controls mapping of the peripheral device signals on Pmod connectors */ - -#define I2C_MAP_CTRL 1 /*!< 32-bits, offset 0x4 */ - -#define SPI_MAP_CTRL 2 /*!< 32-bits, offset 0x8, - SPI_MAP_CTRL[0] selects the mode of operation of the SPI Slave: - - Normal operation, SPI_MAP_CTRL[0]=0: SPI Slave is connected to Pmod1 at connector J1. - - Loop-back mode, SPI_MAP_CTRL[0]=1: SPI Slave is connected to the SPI Master inside the FPGA using CS4. - */ - -#define UART_MAP_CTRL 3 /*!< 32-bits, offset 0x8, - This register controls the mapping of the UART signals on the Pmod1 connector. */ -/** @} end of name */ - - -#endif /* _MUX_HAL_H_ */ diff --git a/bsp/synopsys/emsk_em9d/emsk_em9d.ld b/bsp/synopsys/emsk_em9d/emsk_em9d.ld deleted file mode 100644 index 849ecf63294c7020a54cc1d9ed82214b685cf785..0000000000000000000000000000000000000000 --- a/bsp/synopsys/emsk_em9d/emsk_em9d.ld +++ /dev/null @@ -1,114 +0,0 @@ -MEMORY -{ - ICCM : ORIGIN = 0x00000000, LENGTH = 0x40000 - DCCM : ORIGIN = 0x80000000, LENGTH = 0x20000 - EXT_RAM : ORIGIN = 0x10000000, LENGTH = 0x8000000 -} -ENTRY(_start) -SECTIONS -{ - .init : - { - _f_init = .; - KEEP (*(.init_vector)) - KEEP (*(.init_bootstrap)) - _e_init = .; - } > EXT_RAM - .vector : ALIGN(1024) - { - _f_vector = .; - *(.vector) - _e_vector = .; - } > EXT_RAM - .text : ALIGN(4) - { - _f_text = .; - *(.text .text.* .gnu.linkonce.t.*) - _e_text = .; - } > EXT_RAM - .rodata : ALIGN(4) - { - _f_rodata = .; - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - - __CTOR_LIST__ = .; - LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) - KEEP(*(SORT_BY_NAME(".ctors*"))) - LONG(0) - __CTOR_END__ = .; - . = ALIGN(4); - __init_array_start = .; - KEEP(*(SORT_BY_NAME(".init_array*"))) - __init_array_end = .; - . = ALIGN(4); - __DTOR_LIST__ = .; - LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) - KEEP(*(SORT_BY_NAME(".dtors*"))) - LONG(0) - __DTOR_END__ = .; - *(.rodata .rodata.* .gnu.linkonce.r.*) - _e_rodata = .; - } > EXT_RAM - .data : ALIGN(4) - { - _f_data = .; - *(.data .data.* .gnu.linkonce.d.*) - _f_sdata = .; - __SDATA_BEGIN__ = .; - *(.sdata .sdata.* .gnu.linkonce.s.*) - _e_sdata = .; - _e_data = .; - } > EXT_RAM - .bss (NOLOAD) : ALIGN(8) - { - PROVIDE (__sbss_start = .); - PROVIDE (___sbss_start = .); - _f_bss = .; - _f_sbss = .; - *(.dynsbss) - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - _e_sbss = .; - PROVIDE (__sbss_end = .); - PROVIDE (___sbss_end = .); - *(.dynbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - _e_bss = .; - } > EXT_RAM - .stack (NOLOAD) : - { - . = ALIGN(4); - _f_stack = .; - . = . + 4096; - _e_stack = .; - } > EXT_RAM - .heap (NOLOAD) : - { - . = ALIGN(4); - __start_heap = . ; - _f_heap = .; - . = . + 0x8000; - _e_heap = .; - __end_heap = . ; - } > EXT_RAM - _load_addr_text = LOADADDR(.text); - _load_addr_rodata = LOADADDR(.rodata); - _load_addr_data = LOADADDR(.data); -} diff --git a/bsp/synopsys/emsk_em9d/figures/emsk_board.jpg b/bsp/synopsys/emsk_em9d/figures/emsk_board.jpg deleted file mode 100644 index c96c3d6b6efe2c637ff55cb78767089c310740be..0000000000000000000000000000000000000000 Binary files a/bsp/synopsys/emsk_em9d/figures/emsk_board.jpg and /dev/null differ diff --git a/bsp/synopsys/emsk_em9d/openocd.log b/bsp/synopsys/emsk_em9d/openocd.log deleted file mode 100644 index 4ef893515e7dc5680ca9d8115dfb885d550604dd..0000000000000000000000000000000000000000 --- a/bsp/synopsys/emsk_em9d/openocd.log +++ /dev/null @@ -1,9 +0,0 @@ -Warn : deprecated option: -p/--pipe. Use '-c "gdb_port pipe; log_output openocd.log"' instead. -adapter speed: 5000 kHz -Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED -Info : clock speed 5000 kHz -Info : JTAG tap: arc-em.cpu tap/device found: 0x200044b1 (mfg: 0x258, part: 0x0004, ver: 0x2) -Info : JTAG tap: arc-em.cpu tap/device found: 0x200044b1 (mfg: 0x258, part: 0x0004, ver: 0x2) -target state: halted -Info : accepting 'gdb' connection from pipe -Info : dropped 'gdb' connection diff --git a/bsp/synopsys/emsk_em9d/rtconfig.h b/bsp/synopsys/emsk_em9d/rtconfig.h deleted file mode 100644 index d2fab1109a7fed7a0e57c972e70d4fbd83c374e8..0000000000000000000000000000000000000000 --- a/bsp/synopsys/emsk_em9d/rtconfig.h +++ /dev/null @@ -1,143 +0,0 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ - -// - -// -#define RT_NAME_MAX 6 -// -#define RT_ALIGN_SIZE 4 -// -// 8 -// 32 -// 256 -// -#define RT_THREAD_PRIORITY_MAX 32 -// -#define RT_TICK_PER_SECOND 1000 -// -#define IDLE_THREAD_STACK_SIZE 512 -//
    -#define RT_DEBUG -#define RT_DEBUG_COLOR -// -// #define RT_THREAD_DEBUG -// -#define RT_USING_OVERFLOW_CHECK -//
    - -// -#define RT_USING_HOOK -//
    -// #define RT_USING_TIMER_SOFT -// -#define RT_TIMER_THREAD_PRIO 4 -// -#define RT_TIMER_THREAD_STACK_SIZE 512 -// -#define RT_TIMER_TICK_PER_SECOND 10 -//
    - -//
    -// -#define RT_USING_SEMAPHORE -// -#define RT_USING_MUTEX -// -#define RT_USING_EVENT -// -#define RT_USING_MAILBOX -// -#define RT_USING_MESSAGEQUEUE -//
    - -//
    -// -#define RT_USING_MEMPOOL -// -// #define RT_USING_MEMHEAP -// -#define RT_USING_HEAP -// -// #define RT_USING_MEMHEAP_AS_HEAP -// -#define RT_USING_SMALL_MEM -// -// #define RT_USING_SLAB -//
    - -//
    -#define RT_USING_DEVICE -// -#define RT_USING_DEVICE_IPC -// -#define RT_USING_SERIAL -// -#define RT_UART_RX_BUFFER_SIZE 64 -// -#define RT_USING_INTERRUPT_INFO -//
    - -//
    -#define RT_USING_CONSOLE -// -#define RT_CONSOLEBUF_SIZE 128 -// -#define RT_CONSOLE_DEVICE_NAME "uart1" -//
    - -// -#define RT_USING_COMPONENTS_INIT -//
    -#define RT_USING_FINSH -// -#define FINSH_USING_MSH -// -#define FINSH_USING_MSH_DEFAULT -// -#define FINSH_USING_SYMTAB -// -#define FINSH_USING_DESCRIPTION -// -#define FINSH_THREAD_STACK_SIZE 4096 -//
    - -//
    -// -// -#define RT_USING_PTHREADS -//
    - -//
    -// #define RT_USING_DFS -// -// #define DFS_USING_WORKDIR -// -#define DFS_FILESYSTEMS_MAX 2 -// -#define DFS_FD_MAX 4 -// -#define RT_USING_DFS_ELMFAT -// -// 1 -// 2 -// -#define RT_DFS_ELM_USE_LFN 1 -// -#define RT_DFS_ELM_MAX_LFN 64 -// -// #define RT_USING_DFS_YAFFS2 -// -// #define RT_USING_DFS_UFFS -// -// #define RT_USING_DFS_DEVFS -// -// #define RT_USING_DFS_NFS -// -#define RT_NFS_HOST_EXPORT "192.168.1.5:/" -//
    -//     - - -#endif diff --git a/bsp/w60x/drivers/board.c b/bsp/w60x/drivers/board.c index c104733d5b63e1b4d9ba3c747c0b8ddc3402b114..e4e2ccde47a2208ce2d515dfd7be234b71002dee 100644 --- a/bsp/w60x/drivers/board.c +++ b/bsp/w60x/drivers/board.c @@ -213,6 +213,42 @@ void rt_hw_cpu_reset(void) tls_sys_reset(); } +/** + * The time delay function. + * + * @param microseconds. + */ +#include "wm_regs.h" +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + #ifdef RT_USING_FINSH #include static void reboot(uint8_t argc, char **argv) diff --git a/bsp/w60x/drivers/drv_soft_i2c.c b/bsp/w60x/drivers/drv_soft_i2c.c index a9365eaf0742a1104f08251bca32d69a612b986c..b2e0b5b5083bcb22e44623643288b3bc26dbd8c1 100644 --- a/bsp/w60x/drivers/drv_soft_i2c.c +++ b/bsp/w60x/drivers/drv_soft_i2c.c @@ -138,40 +138,7 @@ static rt_int32_t w60x_get_scl(void *data) return tls_gpio_read((enum tls_io_name)scl); } -/** - * The time delay function. - * - * @param microseconds. - */ -static void w60x_udelay(rt_uint32_t us) -{ - rt_uint32_t ticks; - rt_uint32_t told, tnow, tcnt = 0; - rt_uint32_t reload = SysTick->LOAD; - ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); - told = SysTick->VAL; - while (1) - { - tnow = SysTick->VAL; - if (tnow != told) - { - if (tnow < told) - { - tcnt += told - tnow; - } - else - { - tcnt += reload - tnow + told; - } - told = tnow; - if (tcnt >= ticks) - { - break; - } - } - } -} static const struct rt_i2c_bit_ops w60x_bit_ops_default = { @@ -180,7 +147,7 @@ static const struct rt_i2c_bit_ops w60x_bit_ops_default = .set_scl = w60x_set_scl, .get_sda = w60x_get_sda, .get_scl = w60x_get_scl, - .udelay = w60x_udelay, + .udelay = rt_hw_us_delay, .delay_us = 1, .timeout = 100 }; @@ -201,9 +168,9 @@ static rt_err_t w60x_i2c_bus_unlock(const struct w60x_soft_i2c_config *cfg) while (i++ < 9) { rt_pin_write(cfg->scl, PIN_HIGH); - w60x_udelay(100); + rt_hw_us_delay(100); rt_pin_write(cfg->scl, PIN_LOW); - w60x_udelay(100); + rt_hw_us_delay(100); } } if (PIN_LOW == rt_pin_read(cfg->sda)) diff --git a/bsp/w60x/makeimg.py b/bsp/w60x/makeimg.py index 277ad872d516d27ebe6eed89b5738ad0599a0faa..f3f194cd90cd143a9f0ee05f9841e11da02e741b 100644 --- a/bsp/w60x/makeimg.py +++ b/bsp/w60x/makeimg.py @@ -103,6 +103,11 @@ if __name__=='__main__': # Setting the makeimg_all.exe file path makeimg_all_file=wmlib_path_full + '/Tools/makeimg_all.exe' + if (platform.system() == "Linux"): + wm_gzip_file=wmlib_path_full + '/Tools/wm_gzip.py' + makeimg_file=wmlib_path_full + '/Tools/makeimg' + makeimg_all_file=wmlib_path_full + '/Tools/makeimg_all' + # Get absolute path out_path = os.path.abspath(out_path).replace('\\', '/'); bin_file = os.path.abspath(bin_file).replace('\\', '/'); @@ -149,7 +154,10 @@ if __name__=='__main__': print('make_SEC_param' + make_SEC_param) print('make_FLS_param' + make_FLS_param) - do_makeimg(wm_gzip_file, gzip_param) + if (platform.system() == "Linux"): + do_makeimg("python",wm_gzip_file + " " + gzip_param) + else: + do_makeimg(wm_gzip_file, gzip_param) do_makeimg(makeimg_file, make_img_param) do_makeimg(makeimg_file, make_GZ_param) do_makeimg(makeimg_file, make_SEC_param) @@ -177,7 +185,10 @@ if __name__=='__main__': print('make_SEC_param' + make_SEC_param) print('make_FLS_param' + make_FLS_param) - do_makeimg(wm_gzip_file, gzip_param) + if (platform.system() == "Linux"): + do_makeimg("python",wm_gzip_file + " " + gzip_param) + else: + do_makeimg(wm_gzip_file, gzip_param) do_makeimg(makeimg_file, make_img_param) do_makeimg(makeimg_file, make_GZ_param) do_makeimg(makeimg_file, make_SEC_param) @@ -211,4 +222,4 @@ if __name__=='__main__': if os.path.exists(rm_file): os.remove(rm_file) - print('end') \ No newline at end of file + print('end') diff --git a/components/dfs/filesystems/uffs/uffs_nandif.c b/components/dfs/filesystems/uffs/uffs_nandif.c index 47cb88b6aa79b45e405929f65203747762a78316..2e1a981fbacb97efa9d08309c3f767b46d5b36e3 100644 --- a/components/dfs/filesystems/uffs/uffs_nandif.c +++ b/components/dfs/filesystems/uffs/uffs_nandif.c @@ -135,7 +135,7 @@ const uffs_FlashOps nand_ops = nand_read_page, /* ReadPage() */ NULL, /* ReadPageWithLayout */ nand_write_page, /* WritePage() */ - NULL, /* WirtePageWithLayout */ + NULL, /* WritePageWithLayout */ #if defined(RT_UFFS_USE_CHECK_MARK_FUNCITON) nand_check_block, nand_mark_badblock, @@ -302,7 +302,7 @@ const uffs_FlashOps nand_ops = NULL, /* ReadPage() */ ReadPageWithLayout, /* ReadPageWithLayout */ NULL, /* WritePage() */ - WritePageWithLayout,/* WirtePageWithLayout */ + WritePageWithLayout,/* WritePageWithLayout */ #if defined(RT_UFFS_USE_CHECK_MARK_FUNCITON) nand_check_block, diff --git a/components/drivers/Kconfig b/components/drivers/Kconfig index c567233c847b67257056816456bc29fecc0658f0..3995199ac23892e07e22b5a45c6e1fd56d2a75e7 100755 --- a/components/drivers/Kconfig +++ b/components/drivers/Kconfig @@ -712,6 +712,9 @@ menu "Using USB" config RT_VCOM_TASK_STK_SIZE int "virtual com thread stack size" default 512 + config RT_CDC_RX_BUFSIZE + int "virtual com rx buffer size" + default 128 config RT_VCOM_TX_USE_DMA bool "Enable to use dma for vcom tx" default n diff --git a/components/drivers/audio/audio.c b/components/drivers/audio/audio.c index 28ddf0fe560629f3698220841e307edbc6132ca6..4cec8a4a9ca206520bf0ed870958c568cf8b6a1e 100644 --- a/components/drivers/audio/audio.c +++ b/components/drivers/audio/audio.c @@ -33,7 +33,7 @@ static rt_err_t _audio_send_replay_frame(struct rt_audio_device *audio) rt_err_t result = RT_EOK; rt_uint8_t *data; rt_size_t dst_size, src_size; - rt_uint16_t position, remain_bytes, index = 0; + rt_uint16_t position, remain_bytes = 0, index = 0; struct rt_audio_buf_info *buf_info; RT_ASSERT(audio != RT_NULL); diff --git a/components/drivers/sensors/sensor.c b/components/drivers/sensors/sensor.c index 91b256bd665fbaa6416086279c68e5255ae7a688..18c5830fbffa1ae9e5bca6c4e23cf20a7ed1f43b 100644 --- a/components/drivers/sensors/sensor.c +++ b/components/drivers/sensors/sensor.c @@ -31,7 +31,9 @@ static char *const sensor_name_str[] = "tvoc_", /* TVOC Level */ "noi_", /* Noise Loudness */ "step_", /* Step sensor */ - "forc_" /* Force sensor */ + "forc_", /* Force sensor */ + "dust_", /* Dust sensor */ + "eco2_" /* eCO2 sensor */ }; /* Sensor interrupt correlation function */ diff --git a/components/drivers/sensors/sensor.h b/components/drivers/sensors/sensor.h index 9c6e5ecc55660ec063605037e723ebde68ac10e4..0dae3d66f57c8f7f86aaaf82cf378655a04d320e 100755 --- a/components/drivers/sensors/sensor.h +++ b/components/drivers/sensors/sensor.h @@ -45,6 +45,8 @@ extern "C" { #define RT_SENSOR_CLASS_NOISE (11) /* Noise Loudness */ #define RT_SENSOR_CLASS_STEP (12) /* Step sensor */ #define RT_SENSOR_CLASS_FORCE (13) /* Force sensor */ +#define RT_SENSOR_CLASS_DUST (14) /* Dust sensor */ +#define RT_SENSOR_CLASS_ECO2 (15) /* eCO2 sensor */ /* Sensor vendor types */ @@ -56,6 +58,9 @@ extern "C" { #define RT_SENSOR_VENDOR_GOERTEK (5) /* Goertek */ #define RT_SENSOR_VENDOR_MIRAMEMS (6) /* MiraMEMS */ #define RT_SENSOR_VENDOR_DALLAS (7) /* Dallas */ +#define RT_SENSOR_VENDOR_ASAIR (8) /* Aosong */ +#define RT_SENSOR_VENDOR_SHARP (9) /* Sharp */ +#define RT_SENSOR_VENDOR_SENSIRION (10) /* Sensirion */ /* Sensor unit types */ @@ -190,6 +195,8 @@ struct rt_sensor_data rt_int32_t noise; /* Noise Loudness. unit: HZ */ rt_uint32_t step; /* Step sensor. unit: 1 */ rt_int32_t force; /* Force sensor. unit: mN */ + rt_uint32_t dust; /* Dust sensor. unit: ug/m3 */ + rt_uint32_t eco2; /* eCO2 sensor. unit: ppm */ } data; }; diff --git a/components/drivers/serial/serial.c b/components/drivers/serial/serial.c index 50dd7e188b16ad3058dc014d21931d5b4ba0856f..d1c04dec6f8c4e7bd65f36953acf624ed0035e3d 100644 --- a/components/drivers/serial/serial.c +++ b/components/drivers/serial/serial.c @@ -330,14 +330,16 @@ rt_inline int _serial_int_tx(struct rt_serial_device *serial, const rt_uint8_t * static void _serial_check_buffer_size(void) { static rt_bool_t already_output = RT_FALSE; - + if (already_output == RT_FALSE) { +#if !defined(RT_USING_ULOG) || defined(ULOG_USING_ISR_LOG) LOG_W("Warning: There is no enough buffer for saving data," " please increase the RT_SERIAL_RB_BUFSZ option."); +#endif already_output = RT_TRUE; } -} +} #if defined(RT_USING_POSIX) || defined(RT_SERIAL_USING_DMA) static rt_size_t _serial_fifo_calc_recved_len(struct rt_serial_device *serial) @@ -1286,4 +1288,3 @@ void rt_hw_serial_isr(struct rt_serial_device *serial, int event) #endif /* RT_SERIAL_USING_DMA */ } } - diff --git a/components/drivers/spi/sfud/src/sfud.c b/components/drivers/spi/sfud/src/sfud.c index f666b06806c64d61c76235cc850046989eeadf78..e5b03131ff3ccaef7c92d070d15c6e8228ab18d6 100644 --- a/components/drivers/spi/sfud/src/sfud.c +++ b/components/drivers/spi/sfud/src/sfud.c @@ -897,7 +897,7 @@ static sfud_err set_write_enabled(const sfud_flash *flash, bool enabled) { if (enabled && (register_status & SFUD_STATUS_REGISTER_WEL) == 0) { SFUD_INFO("Error: Can't enable write status."); return SFUD_ERR_WRITE; - } else if (!enabled && (register_status & SFUD_STATUS_REGISTER_WEL) == 1) { + } else if (!enabled && (register_status & SFUD_STATUS_REGISTER_WEL) != 0) { SFUD_INFO("Error: Can't disable write status."); return SFUD_ERR_WRITE; } diff --git a/components/drivers/usb/usbdevice/class/cdc_vcom.c b/components/drivers/usb/usbdevice/class/cdc_vcom.c index b6044b37a7c5298b3e5477c25c1f26a16cc69730..c94a438131c63614561100b74bff7e0991bf8871 100644 --- a/components/drivers/usb/usbdevice/class/cdc_vcom.c +++ b/components/drivers/usb/usbdevice/class/cdc_vcom.c @@ -28,7 +28,11 @@ #define VCOM_TX_TIMEOUT 1000 #endif /*RT_VCOM_TX_TIMEOUT*/ +#ifdef RT_CDC_RX_BUFSIZE +#define CDC_RX_BUFSIZE RT_CDC_RX_BUFSIZE +#else #define CDC_RX_BUFSIZE 128 +#endif #define CDC_MAX_PACKET_SIZE 64 #define VCOM_DEVICE "vcom" diff --git a/components/drivers/usb/usbdevice/class/ecm.c b/components/drivers/usb/usbdevice/class/ecm.c index b98b5007f4ebc36743c60ca10d633319ad5c47c5..cf948adbfc06fd643ae7f88f9ae68a8f62d065a4 100644 --- a/components/drivers/usb/usbdevice/class/ecm.c +++ b/components/drivers/usb/usbdevice/class/ecm.c @@ -419,12 +419,12 @@ rt_err_t rt_ecm_eth_tx(rt_device_t dev, struct pbuf* p) p->tot_len = USB_ETH_MTU; } - result = rt_sem_take(&device->tx_buffer_free, rt_tick_from_millisecond(1000)); + result = rt_sem_take(&ecm_eth_dev->tx_buffer_free, rt_tick_from_millisecond(1000)); if(result != RT_EOK) { LOG_W("wait for buffer free timeout"); /* if cost 1s to wait send done it said that connection is close . drop it */ - rt_sem_release(&device->tx_buffer_free); + rt_sem_release(&ecm_eth_dev->tx_buffer_free); return result; } diff --git a/components/libc/Kconfig b/components/libc/Kconfig index 2d1e9315f19a05d0d4b34250572e280af67a61a4..26e156522bad58d0d070553400a432b022ad9904 100644 --- a/components/libc/Kconfig +++ b/components/libc/Kconfig @@ -34,9 +34,19 @@ if RT_USING_LIBC && RT_USING_DFS default n endif +endif + +if RT_USING_LIBC config RT_USING_MODULE bool "Enable dynamic module with dlopen/dlsym/dlclose feature" default n + + if RT_USING_MODULE + config RT_USING_CUSTOM_DLMODULE + bool "Enable load dynamic module by custom" + default n + endif + endif if RT_USING_LIBC != y diff --git a/components/libc/libdl/dlelf.c b/components/libc/libdl/dlelf.c index 1265ffcb07651be57f0408bd72d4a0b0463bb95f..55ef0d8951112ca61e9f53e76bb3a49a092b5910 100644 --- a/components/libc/libdl/dlelf.c +++ b/components/libc/libdl/dlelf.c @@ -226,6 +226,40 @@ rt_err_t dlmodule_load_shared_object(struct rt_dlmodule* module, void *module_pt length); count ++; } + + /* get priority & stack size params*/ + rt_uint32_t flag = 0; + rt_uint16_t priority; + rt_uint32_t stacksize; + for (i = 0; i < shdr[index].sh_size / sizeof(Elf32_Sym); i++) + { + if (((flag & 0x01) == 0) && + (rt_strcmp((const char *)(strtab + symtab[i].st_name), "dlmodule_thread_priority") == 0)) + { + flag |= 0x01; + priority = *(rt_uint16_t*)(module->mem_space + symtab[i].st_value - module->vstart_addr); + if (priority < RT_THREAD_PRIORITY_MAX) + { + module->priority = priority; + } + } + + if (((flag & 0x02) == 0) && + (rt_strcmp((const char *)(strtab + symtab[i].st_name), "dlmodule_thread_stacksize") == 0)) + { + flag |= 0x02; + stacksize = *(rt_uint32_t*)(module->mem_space + symtab[i].st_value - module->vstart_addr); + if ((stacksize < 2048) || (stacksize > 1024 * 32)) + { + module->stack_size = stacksize; + } + } + + if ((flag & 0x03) == 0x03) + { + break; + } + } } return RT_EOK; diff --git a/components/libc/libdl/dlmodule.c b/components/libc/libdl/dlmodule.c index dbebfc896136fc207f3c353d47e16730c241873c..2829b7df7d7bcace97557902adbe82b8f4f78484 100644 --- a/components/libc/libdl/dlmodule.c +++ b/components/libc/libdl/dlmodule.c @@ -14,7 +14,9 @@ #include "dlmodule.h" #include "dlelf.h" +#if defined(RT_USING_POSIX) #include +#endif #define DBG_TAG "DLMD" #define DBG_LVL DBG_INFO @@ -419,11 +421,14 @@ struct rt_dlmodule *rt_module_self(void) struct rt_dlmodule* dlmodule_load(const char* filename) { - int fd, length = 0; +#if defined(RT_USING_POSIX) + int fd = -1, length = 0; +#endif rt_err_t ret = RT_EOK; rt_uint8_t *module_ptr = RT_NULL; struct rt_dlmodule *module = RT_NULL; +#if defined(RT_USING_POSIX) fd = open(filename, O_RDONLY, 0); if (fd >= 0) { @@ -446,6 +451,9 @@ struct rt_dlmodule* dlmodule_load(const char* filename) { goto __exit; } +#endif + + if (!module_ptr) goto __exit; /* check ELF header */ if (rt_memcmp(elf_module->e_ident, RTMMAG, SELFMAG) != 0 && @@ -512,7 +520,9 @@ struct rt_dlmodule* dlmodule_load(const char* filename) return module; __exit: +#if defined(RT_USING_POSIX) if (fd >= 0) close(fd); +#endif if (module_ptr) rt_free(module_ptr); if (module) dlmodule_destroy(module); @@ -558,6 +568,184 @@ struct rt_dlmodule* dlmodule_exec(const char* pgname, const char* cmd, int cmd_s return module; } +#if defined(RT_USING_CUSTOM_DLMODULE) +struct rt_dlmodule* dlmodule_load_custom(const char* filename, struct rt_dlmodule_ops* ops) +{ +#if defined(RT_USING_POSIX) + int fd = -1, length = 0; +#endif + rt_err_t ret = RT_EOK; + rt_uint8_t *module_ptr = RT_NULL; + struct rt_dlmodule *module = RT_NULL; + + if (ops) + { + RT_ASSERT(ops->load); + RT_ASSERT(ops->unload); + module_ptr = ops->load(filename); + } +#if defined(RT_USING_POSIX) + else + { + fd = open(filename, O_RDONLY, 0); + if (fd >= 0) + { + length = lseek(fd, 0, SEEK_END); + lseek(fd, 0, SEEK_SET); + + if (length == 0) goto __exit; + + module_ptr = (uint8_t*) rt_malloc (length); + if (!module_ptr) goto __exit; + + if (read(fd, module_ptr, length) != length) + goto __exit; + + /* close file and release fd */ + close(fd); + fd = -1; + } + else + { + goto __exit; + } + } +#endif + + if (!module_ptr) goto __exit; + + /* check ELF header */ + if (rt_memcmp(elf_module->e_ident, RTMMAG, SELFMAG) != 0 && + rt_memcmp(elf_module->e_ident, ELFMAG, SELFMAG) != 0) + { + rt_kprintf("Module: magic error\n"); + goto __exit; + } + + /* check ELF class */ + if (elf_module->e_ident[EI_CLASS] != ELFCLASS32) + { + rt_kprintf("Module: ELF class error\n"); + goto __exit; + } + + module = dlmodule_create(); + if (!module) goto __exit; + + /* set the name of module */ + _dlmodule_set_name(module, filename); + + LOG_D("rt_module_load: %.*s", RT_NAME_MAX, module->parent.name); + + if (elf_module->e_type == ET_REL) + { + ret = dlmodule_load_relocated_object(module, module_ptr); + } + else if (elf_module->e_type == ET_DYN) + { + ret = dlmodule_load_shared_object(module, module_ptr); + } + else + { + rt_kprintf("Module: unsupported elf type\n"); + goto __exit; + } + + /* check return value */ + if (ret != RT_EOK) goto __exit; + + /* release module data */ + if (ops) + { + ops->unload(module_ptr); + } + else + { + rt_free(module_ptr); + } + + /* increase module reference count */ + module->nref ++; + + /* deal with cache */ +#ifdef RT_USING_CACHE + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, module->mem_space, module->mem_size); + rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, module->mem_space, module->mem_size); +#endif + + /* set module initialization and cleanup function */ + module->init_func = dlsym(module, "module_init"); + module->cleanup_func = dlsym(module, "module_cleanup"); + module->stat = RT_DLMODULE_STAT_INIT; + /* do module initialization */ + if (module->init_func) + { + module->init_func(module); + } + + return module; + +__exit: +#if defined(RT_USING_POSIX) + if (fd >= 0) close(fd); +#endif + if (module_ptr) + { + if (ops) + { + ops->unload(module_ptr); + } + else + { + rt_free(module_ptr); + } + } + + if (module) dlmodule_destroy(module); + + return RT_NULL; +} + +struct rt_dlmodule* dlmodule_exec_custom(const char* pgname, const char* cmd, int cmd_size, struct rt_dlmodule_ops* ops) +{ + struct rt_dlmodule *module = RT_NULL; + + module = dlmodule_load_custom(pgname, ops); + if (module) + { + if (module->entry_addr) + { + /* exec this module */ + rt_thread_t tid; + + module->cmd_line = rt_strdup(cmd); + + /* check stack size and priority */ + if (module->priority > RT_THREAD_PRIORITY_MAX) module->priority = RT_THREAD_PRIORITY_MAX - 1; + if (module->stack_size < 2048 || module->stack_size > (1024 * 32)) module->stack_size = 2048; + + tid = rt_thread_create(module->parent.name, _dlmodule_thread_entry, (void*)module, + module->stack_size, module->priority, 10); + if (tid) + { + tid->module_id = module; + module->main_thread = tid; + + rt_thread_startup(tid); + } + else + { + /* destory dl module */ + dlmodule_destroy(module); + module = RT_NULL; + } + } + } + + return module; +} +#endif + void dlmodule_exit(int ret_code) { rt_thread_t thread; diff --git a/components/libc/libdl/dlmodule.h b/components/libc/libdl/dlmodule.h index 4a4ead33035e8b7d33d6ce22d9579ac20c4c95ce..b366c7603e5ef26a9b7cea5c829a4c71ea5584fa 100644 --- a/components/libc/libdl/dlmodule.h +++ b/components/libc/libdl/dlmodule.h @@ -59,6 +59,12 @@ struct rt_dlmodule struct rt_module_symtab *symtab; /* module symbol table */ }; +struct rt_dlmodule_ops +{ + rt_uint8_t *(*load)(const char* filename); /* load dlmodule file data */ + rt_err_t (*unload)(rt_uint8_t *param); /* unload dlmodule file data */ +}; + struct rt_dlmodule *dlmodule_create(void); rt_err_t dlmodule_destroy(struct rt_dlmodule* module); @@ -66,6 +72,12 @@ struct rt_dlmodule *dlmodule_self(void); struct rt_dlmodule *dlmodule_load(const char* pgname); struct rt_dlmodule *dlmodule_exec(const char* pgname, const char* cmd, int cmd_size); + +#if defined(RT_USING_CUSTOM_DLMODULE) +struct rt_dlmodule* dlmodule_load_custom(const char* filename, struct rt_dlmodule_ops* ops); +struct rt_dlmodule* dlmodule_exec_custom(const char* pgname, const char* cmd, int cmd_size, struct rt_dlmodule_ops* ops); +#endif + void dlmodule_exit(int ret_code); struct rt_dlmodule *dlmodule_find(const char *name); diff --git a/components/net/at/Kconfig b/components/net/at/Kconfig index 50de0055456df9b74779de2ddb05d7d4860fd01b..37d51c6ce352c9106ff99eaae6e05119c4cc536b 100644 --- a/components/net/at/Kconfig +++ b/components/net/at/Kconfig @@ -75,7 +75,7 @@ if RT_USING_AT default n config AT_CMD_MAX_LEN - int "The maximum lenght of AT Commonds buffer" + int "The maximum lenght of AT Commands buffer" default 128 endif diff --git a/components/net/lwip-1.4.1/src/arch/sys_arch.c b/components/net/lwip-1.4.1/src/arch/sys_arch.c index c31bd59c1d8d9212c7a0f6f49e2b1a60373b4206..2392dde2fa6420374b2c7e808fdf51da1b9b0747 100644 --- a/components/net/lwip-1.4.1/src/arch/sys_arch.c +++ b/components/net/lwip-1.4.1/src/arch/sys_arch.c @@ -27,7 +27,7 @@ * Change Logs: * Date Author Notes * 2012-12-8 Bernard add file header - * export bsd socket symbol for RT-Thread Application Module + * export bsd socket symbol for RT-Thread Application Module * 2017-11-15 Bernard add lock for init_done callback. */ @@ -259,7 +259,7 @@ void sys_sem_signal(sys_sem_t *sem) * * @return If the timeout argument is non-zero, it will return the number of milliseconds * spent waiting for the semaphore to be signaled; If the semaphore isn't signaled - * within the specified time, it will return SYS_ARCH_TIMEOUT; If the thread doesn't + * within the specified time, it will return SYS_ARCH_TIMEOUT; If the thread doesn't * wait for the semaphore, it will return zero */ u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout) @@ -498,14 +498,10 @@ u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout) } ret = rt_mb_recv(*mbox, (rt_ubase_t *)msg, t); - if(ret == -RT_ETIMEOUT) + if(ret != RT_EOK) { return SYS_ARCH_TIMEOUT; } - else - { - LWIP_ASSERT("rt_mb_recv returned with error!", ret == RT_EOK); - } /* get elapse msecond */ tick = rt_tick_get() - tick; @@ -536,7 +532,7 @@ u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg) } else { - if (ret == RT_EOK) + if (ret == RT_EOK) ret = 1; } diff --git a/components/net/lwip-1.4.1/src/core/snmp/msg_out.c b/components/net/lwip-1.4.1/src/core/snmp/msg_out.c index 485f076a5319f23a711835ce0e420af55b320977..d5f0937632683a30e82750de54ff377e70bec985 100644 --- a/components/net/lwip-1.4.1/src/core/snmp/msg_out.c +++ b/components/net/lwip-1.4.1/src/core/snmp/msg_out.c @@ -306,7 +306,7 @@ snmp_authfail_trap(void) * * @param vb_len varbind-list length * @param rhl points to returned header lengths - * @return the required lenght for encoding the response header + * @return the required length for encoding the response header */ static u16_t snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len) @@ -353,7 +353,7 @@ snmp_resp_header_sum(struct snmp_msg_pstat *m_stat, u16_t vb_len) * * @param vb_len varbind-list length * @param thl points to returned header lengths - * @return the required lenght for encoding the trap header + * @return the required length for encoding the trap header */ static u16_t snmp_trap_header_sum(struct snmp_msg_trap *m_trap, u16_t vb_len) diff --git a/components/net/lwip-1.4.1/src/lwipopts.h b/components/net/lwip-1.4.1/src/lwipopts.h index dd59acd5898bde63dd9aca074e905c2d96c802a5..a23a1679701e64f4b3c256c27bfb84304c3c2e48 100644 --- a/components/net/lwip-1.4.1/src/lwipopts.h +++ b/components/net/lwip-1.4.1/src/lwipopts.h @@ -264,8 +264,8 @@ #endif /* - * You can re-define following setting in rtcofnig.h to overwrite the default - * setting in the lwip opts.h + * You can re-define following setting in rtcofnig.h to overwrite the default + * setting in the lwip opts.h */ /* MEMP_NUM_NETBUF: the number of struct netbufs. */ // #define MEMP_NUM_NETBUF 2 @@ -499,6 +499,14 @@ /* no read/write/close for socket */ #define LWIP_POSIX_SOCKETS_IO_NAMES 0 + +/** + * LWIP_NETIF_HOSTNAME==1: Support netif hostname + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 1 +#endif + #define LWIP_NETIF_API 1 /* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. */ diff --git a/components/net/lwip-1.4.1/src/netif/ethernetif.c b/components/net/lwip-1.4.1/src/netif/ethernetif.c index 9d8fa650a4af02cfd9d6290d81f015e062b38494..75f86d75d8eedf50c4a218dd129bcbf4dac5cdf8 100644 --- a/components/net/lwip-1.4.1/src/netif/ethernetif.c +++ b/components/net/lwip-1.4.1/src/netif/ethernetif.c @@ -165,7 +165,7 @@ static int lwip_netdev_set_dhcp(struct netdev *netif, rt_bool_t is_enabled) extern int lwip_ping_recv(int s, int *ttl); extern err_t lwip_ping_send(int s, ip_addr_t *addr, int size); -int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, +int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, uint32_t timeout, struct netdev_ping_resp *ping_resp) { int s, ttl, recv_len, result = 0; @@ -180,7 +180,7 @@ int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, struct addrinfo hint, *res = RT_NULL; struct sockaddr_in *h = RT_NULL; struct in_addr ina; - + RT_ASSERT(netif); RT_ASSERT(host); RT_ASSERT(ping_resp); @@ -199,7 +199,7 @@ int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, return -RT_ERROR; } rt_memcpy(&(ping_resp->ip_addr), &target_addr, sizeof(ip_addr_t)); - + /* new a socket */ if ((s = lwip_socket(AF_INET, SOCK_RAW, IP_PROTO_ICMP)) < 0) { @@ -267,7 +267,7 @@ const struct netdev_ops lwip_netdev_ops = lwip_netdev_set_addr_info, #ifdef RT_LWIP_DNS lwip_netdev_set_dns_server, -#else +#else NULL, #endif /* RT_LWIP_DNS */ @@ -315,7 +315,7 @@ static int netdev_add(struct netif *lwip_netif) rt_strncpy(name, lwip_netif->name, LWIP_NETIF_NAME_LEN); result = netdev_register(netdev, name, (void *)lwip_netif); - + /* Update netdev info after registered */ netdev->flags = lwip_netif->flags; netdev->mtu = lwip_netif->mtu; @@ -325,7 +325,7 @@ static int netdev_add(struct netif *lwip_netif) netdev->ip_addr = lwip_netif->ip_addr; netdev->gw = lwip_netif->gw; netdev->netmask = lwip_netif->netmask; - + #ifdef RT_LWIP_DHCP netdev_low_level_set_dhcp_status(netdev, RT_TRUE); #endif @@ -440,8 +440,13 @@ static err_t eth_netif_device_init(struct netif *netif) rt_err_t eth_device_init_with_flag(struct eth_device *dev, const char *name, rt_uint16_t flags) { struct netif* netif; - +#if LWIP_NETIF_HOSTNAME +#define LWIP_HOSTNAME_LEN 16 + char *hostname = RT_NULL; + netif = (struct netif*) rt_malloc (sizeof(struct netif) + LWIP_HOSTNAME_LEN); +#else netif = (struct netif*) rt_malloc (sizeof(struct netif)); +#endif if (netif == RT_NULL) { rt_kprintf("malloc netif failed\n"); @@ -476,6 +481,13 @@ rt_err_t eth_device_init_with_flag(struct eth_device *dev, const char *name, rt_ netif->output = etharp_output; netif->linkoutput = ethernetif_linkoutput; +#if LWIP_NETIF_HOSTNAME + /* Initialize interface hostname */ + hostname = (char *)netif + sizeof(struct netif); + rt_sprintf(hostname, "rtthread_%02x%02x", name[0], name[1]); + netif->hostname = hostname; +#endif /* LWIP_NETIF_HOSTNAME */ + /* if tcp thread has been started up, we add this netif to the system */ if (rt_thread_find("tcpip") != RT_NULL) { @@ -630,7 +642,7 @@ static void eth_rx_thread_entry(void* parameter) while (1) { if(device->eth_rx == RT_NULL) break; - + p = device->eth_rx(&(device->parent)); if (p != RT_NULL) { diff --git a/components/net/lwip-2.0.2/src/arch/sys_arch.c b/components/net/lwip-2.0.2/src/arch/sys_arch.c index b2abaeab54ba13cce8b02cf8bafc9a9db8f7e0cc..f7ed6eedec6df40e5ae767ca3602f50628a9d7b6 100644 --- a/components/net/lwip-2.0.2/src/arch/sys_arch.c +++ b/components/net/lwip-2.0.2/src/arch/sys_arch.c @@ -27,7 +27,7 @@ * Change Logs: * Date Author Notes * 2012-12-8 Bernard add file header - * export bsd socket symbol for RT-Thread Application Module + * export bsd socket symbol for RT-Thread Application Module * 2017-11-15 Bernard add lock for init_done callback. */ @@ -270,7 +270,7 @@ void sys_sem_signal(sys_sem_t *sem) * * @return If the timeout argument is non-zero, it will return the number of milliseconds * spent waiting for the semaphore to be signaled; If the semaphore isn't signaled - * within the specified time, it will return SYS_ARCH_TIMEOUT; If the thread doesn't + * within the specified time, it will return SYS_ARCH_TIMEOUT; If the thread doesn't * wait for the semaphore, it will return zero */ u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout) @@ -509,12 +509,9 @@ u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout) } ret = rt_mb_recv(*mbox, (rt_ubase_t *)msg, t); - - if(ret == -RT_ETIMEOUT) - return SYS_ARCH_TIMEOUT; - else + if(ret != RT_EOK) { - LWIP_ASSERT("rt_mb_recv returned with error!", ret == RT_EOK); + return SYS_ARCH_TIMEOUT; } /* get elapse msecond */ @@ -545,7 +542,7 @@ u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg) return SYS_ARCH_TIMEOUT; else { - if (ret == RT_EOK) + if (ret == RT_EOK) ret = 1; } diff --git a/components/net/lwip-2.0.2/src/lwipopts.h b/components/net/lwip-2.0.2/src/lwipopts.h index f90ef1a8253ebc20ca4115c7caf10dc6efc9e005..c53863e1abe858b14df28b838a8a8ec3292b2da6 100644 --- a/components/net/lwip-2.0.2/src/lwipopts.h +++ b/components/net/lwip-2.0.2/src/lwipopts.h @@ -531,6 +531,13 @@ #define LWIP_TCP_KEEPALIVE 1 #endif +/** + * LWIP_NETIF_HOSTNAME==1: Support netif hostname + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 1 +#endif + /** * LWIP_NETIF_API==1: Support netif api (in netifapi.c) */ diff --git a/components/net/lwip-2.0.2/src/netif/ethernetif.c b/components/net/lwip-2.0.2/src/netif/ethernetif.c index a7bed3065f02b3395517139c6529235c0e83b9f6..6c5621281c473664b290149bd54e9a4b5b73bbc7 100644 --- a/components/net/lwip-2.0.2/src/netif/ethernetif.c +++ b/components/net/lwip-2.0.2/src/netif/ethernetif.c @@ -173,7 +173,7 @@ static int lwip_netdev_set_dhcp(struct netdev *netif, rt_bool_t is_enabled) extern int lwip_ping_recv(int s, int *ttl); extern err_t lwip_ping_send(int s, ip_addr_t *addr, int size); -int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, +int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, uint32_t timeout, struct netdev_ping_resp *ping_resp) { int s, ttl, recv_len, result = 0; @@ -188,7 +188,7 @@ int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, struct addrinfo hint, *res = RT_NULL; struct sockaddr_in *h = RT_NULL; struct in_addr ina; - + RT_ASSERT(netif); RT_ASSERT(host); RT_ASSERT(ping_resp); @@ -207,7 +207,7 @@ int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, return -RT_ERROR; } rt_memcpy(&(ping_resp->ip_addr), &target_addr, sizeof(ip_addr_t)); - + /* new a socket */ if ((s = lwip_socket(AF_INET, SOCK_RAW, IP_PROTO_ICMP)) < 0) { @@ -275,7 +275,7 @@ const struct netdev_ops lwip_netdev_ops = lwip_netdev_set_addr_info, #ifdef RT_LWIP_DNS lwip_netdev_set_dns_server, -#else +#else NULL, #endif /* RT_LWIP_DNS */ @@ -323,8 +323,8 @@ static int netdev_add(struct netif *lwip_netif) rt_strncpy(name, lwip_netif->name, LWIP_NETIF_NAME_LEN); result = netdev_register(netdev, name, (void *)lwip_netif); - - /* Update netdev info after registered */ + + /* Update netdev info after registered */ netdev->flags = lwip_netif->flags; netdev->mtu = lwip_netif->mtu; netdev->ops = &lwip_netdev_ops; @@ -333,7 +333,7 @@ static int netdev_add(struct netif *lwip_netif) netdev->ip_addr = lwip_netif->ip_addr; netdev->gw = lwip_netif->gw; netdev->netmask = lwip_netif->netmask; - + #ifdef RT_LWIP_DHCP netdev_low_level_set_dhcp_status(netdev, RT_TRUE); #endif @@ -412,7 +412,7 @@ static err_t eth_netif_device_init(struct netif *netif) /* network interface device register */ netdev_add(netif); #endif /* RT_USING_NETDEV */ - + ethif = (struct eth_device*)netif->state; if (ethif != RT_NULL) { @@ -481,8 +481,13 @@ static err_t eth_netif_device_init(struct netif *netif) rt_err_t eth_device_init_with_flag(struct eth_device *dev, const char *name, rt_uint16_t flags) { struct netif* netif; - +#if LWIP_NETIF_HOSTNAME +#define LWIP_HOSTNAME_LEN 16 + char *hostname = RT_NULL; + netif = (struct netif*) rt_malloc (sizeof(struct netif) + LWIP_HOSTNAME_LEN); +#else netif = (struct netif*) rt_malloc (sizeof(struct netif)); +#endif if (netif == RT_NULL) { rt_kprintf("malloc netif failed\n"); @@ -519,7 +524,9 @@ rt_err_t eth_device_init_with_flag(struct eth_device *dev, const char *name, rt_ #if LWIP_NETIF_HOSTNAME /* Initialize interface hostname */ - netif->hostname = "rtthread"; + hostname = (char *)netif + sizeof(struct netif); + rt_sprintf(hostname, "rtthread_%02x%02x", name[0], name[1]); + netif->hostname = hostname; #endif /* LWIP_NETIF_HOSTNAME */ /* if tcp thread has been started up, we add this netif to the system */ @@ -531,7 +538,7 @@ rt_err_t eth_device_init_with_flag(struct eth_device *dev, const char *name, rt_ ipaddr.addr = inet_addr(RT_LWIP_IPADDR); gw.addr = inet_addr(RT_LWIP_GWADDR); netmask.addr = inet_addr(RT_LWIP_MSKADDR); -#else +#else IP4_ADDR(&ipaddr, 0, 0, 0, 0); IP4_ADDR(&gw, 0, 0, 0, 0); IP4_ADDR(&netmask, 0, 0, 0, 0); @@ -683,7 +690,7 @@ static void eth_rx_thread_entry(void* parameter) while (1) { if(device->eth_rx == RT_NULL) break; - + p = device->eth_rx(&(device->parent)); if (p != RT_NULL) { @@ -706,9 +713,9 @@ static void eth_rx_thread_entry(void* parameter) } #endif -/* this function does not need, - * use eth_system_device_init_private() - * call by lwip_system_init(). +/* this function does not need, + * use eth_system_device_init_private() + * call by lwip_system_init(). */ int eth_system_device_init(void) { @@ -855,22 +862,22 @@ void list_if(void) ip6_addr_t *addr; int addr_state; int i; - + addr = (ip6_addr_t *)&netif->ip6_addr[0]; addr_state = netif->ip6_addr_state[0]; - - rt_kprintf("\nipv6 link-local: %s state:%02X %s\n", ip6addr_ntoa(addr), + + rt_kprintf("\nipv6 link-local: %s state:%02X %s\n", ip6addr_ntoa(addr), addr_state, ip6_addr_isvalid(addr_state)?"VALID":"INVALID"); - + for(i=1; iip6_addr[i]; addr_state = netif->ip6_addr_state[i]; - - rt_kprintf("ipv6[%d] address: %s state:%02X %s\n", i, ip6addr_ntoa(addr), + + rt_kprintf("ipv6[%d] address: %s state:%02X %s\n", i, ip6addr_ntoa(addr), addr_state, ip6_addr_isvalid(addr_state)?"VALID":"INVALID"); } - + } rt_kprintf("\r\n"); #endif /* LWIP_IPV6 */ diff --git a/components/net/lwip-2.1.0/src/arch/sys_arch.c b/components/net/lwip-2.1.0/src/arch/sys_arch.c index dc08715ecc2baef274a92be3b4cde92ff8d59169..0633501bb6376e2a42e71f568a5da565cb931fe0 100755 --- a/components/net/lwip-2.1.0/src/arch/sys_arch.c +++ b/components/net/lwip-2.1.0/src/arch/sys_arch.c @@ -27,7 +27,7 @@ * Change Logs: * Date Author Notes * 2012-12-8 Bernard add file header - * export bsd socket symbol for RT-Thread Application Module + * export bsd socket symbol for RT-Thread Application Module * 2017-11-15 Bernard add lock for init_done callback. * 2018-11-02 MurphyZhao port to lwip2.1.0 */ @@ -78,7 +78,7 @@ static err_t netif_device_init(struct netif *netif) /* copy device flags to netif flags */ netif->flags = ethif->flags; netif->mtu = ETHERNET_MTU; - + /* set output */ netif->output = etharp_output; @@ -278,7 +278,7 @@ void sys_sem_signal(sys_sem_t *sem) * * @return If the timeout argument is non-zero, it will return the number of milliseconds * spent waiting for the semaphore to be signaled; If the semaphore isn't signaled - * within the specified time, it will return SYS_ARCH_TIMEOUT; If the thread doesn't + * within the specified time, it will return SYS_ARCH_TIMEOUT; If the thread doesn't * wait for the semaphore, it will return zero */ u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout) @@ -523,12 +523,9 @@ u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout) } ret = rt_mb_recv(*mbox, (rt_ubase_t *)msg, t); - - if(ret == -RT_ETIMEOUT) - return SYS_ARCH_TIMEOUT; - else + if(ret != RT_EOK) { - LWIP_ASSERT("rt_mb_recv returned with error!", ret == RT_EOK); + return SYS_ARCH_TIMEOUT; } /* get elapse msecond */ @@ -559,7 +556,7 @@ u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg) return SYS_ARCH_TIMEOUT; else { - if (ret == RT_EOK) + if (ret == RT_EOK) ret = 1; } diff --git a/components/net/lwip-2.1.0/src/lwipopts.h b/components/net/lwip-2.1.0/src/lwipopts.h index 405e95ce6408efe7b1c6d3c6636f408611c7c8fd..7e02a8a9f9468a08da3ec064b5e98390e1186323 100644 --- a/components/net/lwip-2.1.0/src/lwipopts.h +++ b/components/net/lwip-2.1.0/src/lwipopts.h @@ -538,6 +538,13 @@ #define LWIP_TCP_KEEPALIVE 1 #endif +/** + * LWIP_NETIF_HOSTNAME==1: Support netif hostname + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 1 +#endif + /** * LWIP_NETIF_API==1: Support netif api (in netifapi.c) */ diff --git a/components/net/lwip-2.1.0/src/netif/ethernetif.c b/components/net/lwip-2.1.0/src/netif/ethernetif.c index 66ea1d2376e543dc5d918c59dae422a2807952c7..55ffaa89df494797772e1a0db7a9e5f0f99f6bcb 100755 --- a/components/net/lwip-2.1.0/src/netif/ethernetif.c +++ b/components/net/lwip-2.1.0/src/netif/ethernetif.c @@ -174,7 +174,7 @@ static int lwip_netdev_set_dhcp(struct netdev *netif, rt_bool_t is_enabled) extern int lwip_ping_recv(int s, int *ttl); extern err_t lwip_ping_send(int s, ip_addr_t *addr, int size); -int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, +int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, uint32_t timeout, struct netdev_ping_resp *ping_resp) { int s, ttl, recv_len, result = 0; @@ -189,7 +189,7 @@ int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, struct addrinfo hint, *res = RT_NULL; struct sockaddr_in *h = RT_NULL; struct in_addr ina; - + RT_ASSERT(netif); RT_ASSERT(host); RT_ASSERT(ping_resp); @@ -208,7 +208,7 @@ int lwip_netdev_ping(struct netdev *netif, const char *host, size_t data_len, return -RT_ERROR; } rt_memcpy(&(ping_resp->ip_addr), &target_addr, sizeof(ip_addr_t)); - + /* new a socket */ if ((s = lwip_socket(AF_INET, SOCK_RAW, IP_PROTO_ICMP)) < 0) { @@ -276,7 +276,7 @@ const struct netdev_ops lwip_netdev_ops = lwip_netdev_set_addr_info, #ifdef RT_LWIP_DNS lwip_netdev_set_dns_server, -#else +#else NULL, #endif /* RT_LWIP_DNS */ @@ -315,7 +315,7 @@ static int netdev_add(struct netif *lwip_netif) { return -ERR_IF; } - + #ifdef SAL_USING_LWIP extern int sal_lwip_netdev_set_pf_info(struct netdev *netdev); /* set the lwIP network interface device protocol family information */ @@ -324,7 +324,7 @@ static int netdev_add(struct netif *lwip_netif) rt_strncpy(name, lwip_netif->name, LWIP_NETIF_NAME_LEN); result = netdev_register(netdev, name, (void *)lwip_netif); - + /* Update netdev info after registered */ netdev->flags = lwip_netif->flags; netdev->mtu = lwip_netif->mtu; @@ -367,7 +367,7 @@ static int netdev_flags_sync(struct netif *lwip_netif) { return -ERR_IF; } - + netdev->mtu = lwip_netif->mtu; netdev->flags |= lwip_netif->flags; @@ -430,7 +430,7 @@ static err_t eth_netif_device_init(struct netif *netif) /* copy device flags to netif flags */ netif->flags = (ethif->flags & 0xff); netif->mtu = ETHERNET_MTU; - + /* set output */ netif->output = etharp_output; @@ -487,8 +487,13 @@ static err_t eth_netif_device_init(struct netif *netif) rt_err_t eth_device_init_with_flag(struct eth_device *dev, const char *name, rt_uint16_t flags) { struct netif* netif; - +#if LWIP_NETIF_HOSTNAME +#define LWIP_HOSTNAME_LEN 16 + char *hostname = RT_NULL; + netif = (struct netif*) rt_malloc (sizeof(struct netif) + LWIP_HOSTNAME_LEN); +#else netif = (struct netif*) rt_malloc (sizeof(struct netif)); +#endif if (netif == RT_NULL) { rt_kprintf("malloc netif failed\n"); @@ -518,13 +523,15 @@ rt_err_t eth_device_init_with_flag(struct eth_device *dev, const char *name, rt_ /* set linkoutput */ netif->linkoutput = ethernetif_linkoutput; - + /* get hardware MAC address */ rt_device_control(&(dev->parent), NIOCTL_GADDR, netif->hwaddr); #if LWIP_NETIF_HOSTNAME /* Initialize interface hostname */ - netif->hostname = "rtthread"; + hostname = (char *)netif + sizeof(struct netif); + rt_sprintf(hostname, "rtthread_%02x%02x", name[0], name[1]); + netif->hostname = hostname; #endif /* LWIP_NETIF_HOSTNAME */ /* if tcp thread has been started up, we add this netif to the system */ @@ -536,7 +543,7 @@ rt_err_t eth_device_init_with_flag(struct eth_device *dev, const char *name, rt_ ipaddr.addr = inet_addr(RT_LWIP_IPADDR); gw.addr = inet_addr(RT_LWIP_GWADDR); netmask.addr = inet_addr(RT_LWIP_MSKADDR); -#else +#else IP4_ADDR(&ipaddr, 0, 0, 0, 0); IP4_ADDR(&gw, 0, 0, 0, 0); IP4_ADDR(&netmask, 0, 0, 0, 0); @@ -688,7 +695,7 @@ static void eth_rx_thread_entry(void* parameter) while (1) { if(device->eth_rx == RT_NULL) break; - + p = device->eth_rx(&(device->parent)); if (p != RT_NULL) { @@ -711,9 +718,9 @@ static void eth_rx_thread_entry(void* parameter) } #endif -/* this function does not need, - * use eth_system_device_init_private() - * call by lwip_system_init(). +/* this function does not need, + * use eth_system_device_init_private() + * call by lwip_system_init(). */ int eth_system_device_init(void) { @@ -860,22 +867,22 @@ void list_if(void) ip6_addr_t *addr; int addr_state; int i; - + addr = (ip6_addr_t *)&netif->ip6_addr[0]; addr_state = netif->ip6_addr_state[0]; - - rt_kprintf("\nipv6 link-local: %s state:%02X %s\n", ip6addr_ntoa(addr), + + rt_kprintf("\nipv6 link-local: %s state:%02X %s\n", ip6addr_ntoa(addr), addr_state, ip6_addr_isvalid(addr_state)?"VALID":"INVALID"); - + for(i=1; iip6_addr[i]; addr_state = netif->ip6_addr_state[i]; - - rt_kprintf("ipv6[%d] address: %s state:%02X %s\n", i, ip6addr_ntoa(addr), + + rt_kprintf("ipv6[%d] address: %s state:%02X %s\n", i, ip6addr_ntoa(addr), addr_state, ip6_addr_isvalid(addr_state)?"VALID":"INVALID"); } - + } rt_kprintf("\r\n"); #endif /* LWIP_IPV6 */ diff --git a/components/net/uip/uip/lc-switch.h b/components/net/uip/uip/lc-switch.h index f32885fd1e09bb9c5ed7e4125cda2d10fb311e41..90e22bd09fab5d4d1eb7c7b89a6aec8d2d16f6d7 100644 --- a/components/net/uip/uip/lc-switch.h +++ b/components/net/uip/uip/lc-switch.h @@ -55,7 +55,7 @@ */ #ifndef __LC_SWITCH_H__ -#define __LC_SWTICH_H__ +#define __LC_SWITCH_H__ /* WARNING! lc implementation using switch() does not work if an LC_SET() is done within another switch() statement! */ diff --git a/components/utilities/ulog/ulog.c b/components/utilities/ulog/ulog.c index 8a8d142effebfd256dd40a293eadf6c27e0348fa..76100892982dde363d1e80b7439dc57a1c06d530 100644 --- a/components/utilities/ulog/ulog.c +++ b/components/utilities/ulog/ulog.c @@ -81,12 +81,12 @@ struct rt_ulog /* all backends */ rt_slist_t backend_list; /* the thread log's line buffer */ - char log_buf_th[ULOG_LINE_BUF_SIZE]; + char log_buf_th[ULOG_LINE_BUF_SIZE + 1]; #ifdef ULOG_USING_ISR_LOG /* the ISR log's line buffer */ rt_base_t output_locker_isr_lvl; - char log_buf_isr[ULOG_LINE_BUF_SIZE]; + char log_buf_isr[ULOG_LINE_BUF_SIZE + 1]; #endif /* ULOG_USING_ISR_LOG */ #ifdef ULOG_USING_ASYNC_OUTPUT @@ -396,7 +396,7 @@ void ulog_output_to_all_backend(rt_uint32_t level, const char *tag, rt_bool_t is #if !defined(ULOG_USING_COLOR) || defined(ULOG_USING_SYSLOG) backend->output(backend, level, tag, is_raw, log, size); #else - if (backend->support_color) + if (backend->support_color || is_raw) { backend->output(backend, level, tag, is_raw, log, size); } @@ -728,6 +728,8 @@ void ulog_hexdump(const char *tag, rt_size_t width, rt_uint8_t *buf, rt_size_t s } /* package newline sign */ log_len += ulog_strcpy(log_len, log_buf + log_len, ULOG_NEWLINE_SIGN); + /*add string end sign*/ + log_buf[log_len] = '\0'; /* do log output */ do_output(LOG_LVL_DBG, NULL, RT_TRUE, log_buf, log_len); } diff --git a/documentation/coding_style_cn.md b/documentation/coding_style_cn.md index 0aff3cb543d7bb320fb329ccedc689581b459aa1..26bed9d045963b20f51f9844e92f00daa917a8f9 100644 --- a/documentation/coding_style_cn.md +++ b/documentation/coding_style_cn.md @@ -131,7 +131,7 @@ C语言头文件为了避免多次重复包含，需要定义一个符号。这 } ``` -唯一的例外是 swtich 语句，switch-case 语句采用 case 语句与 swtich 对齐的方式， +唯一的例外是 switch 语句，switch-case 语句采用 case 语句与 switch 对齐的方式， 例如： ```c @@ -173,7 +173,7 @@ case 语句与前面的 switch 语句对齐，后续的语句则采用缩进的 } ``` -建议在括号前留出一个空格(涉及的包括 if、for、while、swtich 语句)，而运算表达式 +建议在括号前留出一个空格(涉及的包括 if、for、while、switch 语句)，而运算表达式 中，运算符与字符串间留一个空格。另外，不要在括号的表达式两侧留空格，例如： ```c diff --git a/include/rtdef.h b/include/rtdef.h index c8184a5a4bf8cdbb8c63ccea1aab5df682101bbc..8b862130825d0693b223ef239ba89b0b153eb1ba 100644 --- a/include/rtdef.h +++ b/include/rtdef.h @@ -431,6 +431,7 @@ struct rt_object_information #define RT_TIMER_CTRL_GET_TIME 0x1 /**< get timer control command */ #define RT_TIMER_CTRL_SET_ONESHOT 0x2 /**< change timer to one shot */ #define RT_TIMER_CTRL_SET_PERIODIC 0x3 /**< change timer to periodic */ +#define RT_TIMER_CTRL_GET_STATE 0x4 /**< get timer run state active or deactive*/ #ifndef RT_TIMER_SKIP_LIST_LEVEL #define RT_TIMER_SKIP_LIST_LEVEL 1 diff --git a/libcpu/aarch64/SConscript b/libcpu/aarch64/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..453afe4b3ec77bfe37a1c02abc6be4fcdd5ebe75 --- /dev/null +++ b/libcpu/aarch64/SConscript @@ -0,0 +1,16 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# cpu porting code files +if rtconfig.CPU != 'common': + group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/aarch64/cortex-a53/SConscript b/libcpu/aarch64/cortex-a53/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..57a5accc5c95f0967fc55ac86f66032d49fb9d2e --- /dev/null +++ b/libcpu/aarch64/cortex-a53/SConscript @@ -0,0 +1,15 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +asm_src = Split(''' +context_gcc.S +vector_gcc.S +entry_point.S +cpu_gcc.S +''') +CPPPATH = [cwd] + +group = DefineGroup('cpu', src + asm_src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/aarch64/cortex-a53/armv8.h b/libcpu/aarch64/cortex-a53/armv8.h new file mode 100644 index 0000000000000000000000000000000000000000..43508905443e73c1c87af39c7e115147559cb505 --- /dev/null +++ b/libcpu/aarch64/cortex-a53/armv8.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + */ + +#ifndef __ARMV8_H__ +#define __ARMV8_H__ + +/* the exception stack without VFP registers */ +struct rt_hw_exp_stack +{ + unsigned long long pc; + unsigned long long spsr; + unsigned long long x30; + unsigned long long xz; + unsigned long long x28; + unsigned long long x29; + unsigned long long x26; + unsigned long long x27; + unsigned long long x24; + unsigned long long x25; + unsigned long long x22; + unsigned long long x23; + unsigned long long x20; + unsigned long long x21; + unsigned long long x18; + unsigned long long x19; + unsigned long long x16; + unsigned long long x17; + unsigned long long x14; + unsigned long long x15; + unsigned long long x12; + unsigned long long x13; + unsigned long long x10; + unsigned long long x11; + unsigned long long x8; + unsigned long long x9; + unsigned long long x6; + unsigned long long x7; + unsigned long long x4; + unsigned long long x5; + unsigned long long x2; + unsigned long long x3; + unsigned long long x0; + unsigned long long x1; +}; + +#define SP_ELx ( ( unsigned long long ) 0x01 ) +#define SP_EL0 ( ( unsigned long long ) 0x00 ) +#define PSTATE_EL1 ( ( unsigned long long ) 0x04 ) +#define PSTATE_EL2 ( ( unsigned long long ) 0x08 ) +#define PSTATE_EL3 ( ( unsigned long long ) 0x0c ) + +rt_ubase_t rt_hw_get_current_el(void); +void rt_hw_set_elx_env(void); +void rt_hw_set_current_vbar(rt_ubase_t addr); + +#endif diff --git a/libcpu/aarch64/cortex-a53/context_gcc.S b/libcpu/aarch64/cortex-a53/context_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..f58ea1b15da31c215539ea52af89c645aa318743 --- /dev/null +++ b/libcpu/aarch64/cortex-a53/context_gcc.S @@ -0,0 +1,312 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-06 ZhaoXiaowei the first version + */ + +.macro SAVE_CONTEXT + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Save the entire context. */ + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X4, X5, [SP, #-0x10]! + STP X6, X7, [SP, #-0x10]! + STP X8, X9, [SP, #-0x10]! + STP X10, X11, [SP, #-0x10]! + STP X12, X13, [SP, #-0x10]! + STP X14, X15, [SP, #-0x10]! + STP X16, X17, [SP, #-0x10]! + STP X18, X19, [SP, #-0x10]! + STP X20, X21, [SP, #-0x10]! + STP X22, X23, [SP, #-0x10]! + STP X24, X25, [SP, #-0x10]! + STP X26, X27, [SP, #-0x10]! + STP X28, X29, [SP, #-0x10]! + STP X30, XZR, [SP, #-0x10]! + + MRS X0, CurrentEL + CMP X0, 0xc + B.EQ 3f + CMP X0, 0x8 + B.EQ 2f + CMP X0, 0x4 + B.EQ 1f + B . +3: + MRS X3, SPSR_EL3 + /* Save the ELR. */ + MRS X2, ELR_EL3 + B 0f +2: + MRS X3, SPSR_EL2 + /* Save the ELR. */ + MRS X2, ELR_EL2 + B 0f +1: + MRS X3, SPSR_EL1 + MRS X2, ELR_EL1 + B 0f +0: + + STP X2, X3, [SP, #-0x10]! + + MOV X0, SP /* Move SP into X0 for saving. */ + + /* Switch to use the ELx stack pointer. */ + MSR SPSEL, #1 + + .endm + +.macro SAVE_CONTEXT_T + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Save the entire context. */ + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X4, X5, [SP, #-0x10]! + STP X6, X7, [SP, #-0x10]! + STP X8, X9, [SP, #-0x10]! + STP X10, X11, [SP, #-0x10]! + STP X12, X13, [SP, #-0x10]! + STP X14, X15, [SP, #-0x10]! + STP X16, X17, [SP, #-0x10]! + STP X18, X19, [SP, #-0x10]! + STP X20, X21, [SP, #-0x10]! + STP X22, X23, [SP, #-0x10]! + STP X24, X25, [SP, #-0x10]! + STP X26, X27, [SP, #-0x10]! + STP X28, X29, [SP, #-0x10]! + STP X30, XZR, [SP, #-0x10]! + + MRS X0, CurrentEL + CMP X0, 0xc + B.EQ 3f + CMP X0, 0x8 + B.EQ 2f + CMP X0, 0x4 + B.EQ 1f + B . +3: + MRS X3, SPSR_EL3 + MOV X2, X30 + B 0f +2: + MRS X3, SPSR_EL2 + MOV X2, X30 + B 0f +1: + MRS X3, SPSR_EL1 + MOV X2, X30 + B 0f +0: + + STP X2, X3, [SP, #-0x10]! + + MOV X0, SP /* Move SP into X0 for saving. */ + + /* Switch to use the ELx stack pointer. */ + MSR SPSEL, #1 + + .endm + +.macro RESTORE_CONTEXT + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Set the SP to point to the stack of the task being restored. */ + MOV SP, X0 + + LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */ + + MRS X0, CurrentEL + CMP X0, 0xc + B.EQ 3f + CMP X0, 0x8 + B.EQ 2f + CMP X0, 0x4 + B.EQ 1f + B . +3: + MSR SPSR_EL3, X3 + MSR ELR_EL3, X2 + B 0f +2: + MSR SPSR_EL2, X3 + MSR ELR_EL2, X2 + B 0f +1: + MSR SPSR_EL1, X3 + MSR ELR_EL1, X2 + B 0f +0: + + LDP X30, XZR, [SP], #0x10 + LDP X28, X29, [SP], #0x10 + LDP X26, X27, [SP], #0x10 + LDP X24, X25, [SP], #0x10 + LDP X22, X23, [SP], #0x10 + LDP X20, X21, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + + /* Switch to use the ELx stack pointer. _RB_ Might not be required. */ + MSR SPSEL, #1 + + ERET + + .endm + +.text +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS X0, DAIF + MSR DAIFSet, #3 + DSB SY + RET + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + DSB SY + MOV X1, #0xC0 + ANDS X0, X0, X1 + B.NE rt_hw_interrupt_enable_exit + MSR DAIFClr, #3 +rt_hw_interrupt_enable_exit: + RET + +/* + * void rt_hw_context_switch_to(rt_ubase_t to); + * r0 --> to + */ +.globl rt_hw_context_switch_to +rt_hw_context_switch_to: + LDR X0, [X0] + RESTORE_CONTEXT + +.text +/* + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to); + * r0 --> from + * r1 --> to + */ +.globl rt_hw_context_switch +rt_hw_context_switch: + + MOV X8,X0 + MOV X9,X1 + + SAVE_CONTEXT_T + + STR X0, [X8] // store sp in preempted tasks TCB + LDR X0, [X9] // get new task stack pointer + + RESTORE_CONTEXT + +/* + * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to); + */ +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread +.globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + ADR X2, rt_thread_switch_interrupt_flag + LDR X3, [X2] + CMP X3, #1 + B.EQ _reswitch + ADR X4, rt_interrupt_from_thread // set rt_interrupt_from_thread + MOV X3, #1 // set rt_thread_switch_interrupt_flag to 1 + STR X0, [X4] + STR X3, [X2] +_reswitch: + ADR X2, rt_interrupt_to_thread // set rt_interrupt_to_thread + STR X1, [X2] + RET + +.text + +// -- Exception handlers ---------------------------------- + + .align 8 +.globl vector_fiq +vector_fiq: + SAVE_CONTEXT + STP X0, X1, [SP, #-0x10]! + BL rt_hw_trap_fiq + LDP X0, X1, [SP], #0x10 + RESTORE_CONTEXT + +.globl rt_interrupt_enter +.globl rt_interrupt_leave +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread + + +// ------------------------------------------------------------------- + + .align 8 +.globl vector_irq +vector_irq: + SAVE_CONTEXT + STP X0, X1, [SP, #-0x10]! + + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + LDP X0, X1, [SP], #0x10 + + // if rt_thread_switch_interrupt_flag set, jump to + // rt_hw_context_switch_interrupt_do and don't return + ADR X1, rt_thread_switch_interrupt_flag + LDR X2, [X1] + CMP X2, #1 + B.NE vector_irq_exit + + MOV X2, #0 // clear flag + STR X2, [X1] + + ADR X3, rt_interrupt_from_thread + LDR X4, [X3] + STR x0, [X4] // store sp in preempted tasks's TCB + + ADR x3, rt_interrupt_to_thread + LDR X4, [X3] + LDR x0, [X4] // get new task's stack pointer + +vector_irq_exit: + RESTORE_CONTEXT + +// ------------------------------------------------- + + .align 8 + .globl vector_error +vector_error: + SAVE_CONTEXT + BL rt_hw_trap_error + B . diff --git a/libcpu/aarch64/cortex-a53/cp15.h b/libcpu/aarch64/cortex-a53/cp15.h new file mode 100644 index 0000000000000000000000000000000000000000..91c37d679f55c1ebd8597f777ca8245f1442e2f0 --- /dev/null +++ b/libcpu/aarch64/cortex-a53/cp15.h @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + */ + +#ifndef __CP15_H__ +#define __CP15_H__ + +#include "bcm283x.h" +#ifndef __STATIC_FORCEINLINE +#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif + +#define __WFI() __asm__ volatile ("wfi":::"memory") + +#define __WFE() __asm__ volatile ("wfe":::"memory") + +#define __SEV() __asm__ volatile ("sev") + +__STATIC_FORCEINLINE void __ISB(void) +{ + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __asm__ volatile ("dsb 0xF":::"memory"); +} + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ + +__STATIC_FORCEINLINE void __DMB(void) +{ + __asm__ volatile ("dmb 0xF":::"memory"); +} + +#ifdef RT_USING_SMP +static inline void send_ipi_msg(int cpu, int ipi_vector) +{ + IPI_MAILBOX_SET(cpu) = 1 << ipi_vector; +} + +static inline void setup_bootstrap_addr(int cpu, int addr) +{ + CORE_MAILBOX3_SET(cpu) = addr; +} + +static inline void enable_cpu_ipi_intr(int cpu) +{ + COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK; +} + +static inline void enable_cpu_timer_intr(int cpu) +{ + CORETIMER_INTCTL(cpu) = 0x8; +} + +static inline void enable_cntv(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 1; + asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL +} + +static inline void disable_cntv(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 0; + asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL +} + +static inline void mask_cntv(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 2; + asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL +} + +static inline void unmask_cntv(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 1; + asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL +} + +static inline rt_uint64_t read_cntvct(void) +{ + rt_uint32_t val,val1; + asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1)); + return (val); +} + +static inline rt_uint64_t read_cntvoff(void) +{ + + rt_uint64_t val; + asm volatile("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val)); + return (val); +} + +static inline rt_uint32_t read_cntv_tval(void) +{ + rt_uint32_t val; + asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val) ); + return val; +} + + +static inline void write_cntv_tval(rt_uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val) ); + return; +} + +static inline rt_uint32_t read_cntfrq(void) +{ + rt_uint32_t val; + asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val) ); + return val; +} + + +static inline rt_uint32_t read_cntctrl(void) +{ + rt_uint32_t val; + asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val) ); + return val; +} + +static inline uint32_t write_cntctrl(uint32_t val) +{ + + asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val) ); + return val; +} +#endif + +unsigned long rt_cpu_get_smp_id(void); + +void rt_cpu_mmu_disable(void); +void rt_cpu_mmu_enable(void); +void rt_cpu_tlb_set(volatile unsigned long*); + +void rt_cpu_dcache_clean_flush(void); +void rt_cpu_icache_flush(void); + +void rt_cpu_vector_set_base(rt_ubase_t addr); +void rt_hw_mmu_init(void); +void rt_hw_vector_init(void); + +void set_timer_counter(unsigned int counter); +void set_timer_control(unsigned int control); +#endif diff --git a/libcpu/aarch64/cortex-a53/cpu.c b/libcpu/aarch64/cortex-a53/cpu.c new file mode 100644 index 0000000000000000000000000000000000000000..962a53a0710765087adee863b094fdefd35e445e --- /dev/null +++ b/libcpu/aarch64/cortex-a53/cpu.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + * 2019-07-28 zdzn add smp support + */ + +#include +#include +#include +#include "cp15.h" + +int rt_hw_cpu_id(void) +{ + int cpu_id; + rt_base_t value; + + __asm__ volatile ( + "mrs %0, mpidr_el1" + :"=r"(value) + ); + cpu_id = value & 0xf; + return cpu_id; +}; + +#ifdef RT_USING_SMP +void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock) +{ + lock->slock = 0; +} + +void rt_hw_spin_lock(rt_hw_spinlock_t *lock) +{ + unsigned long tmp; + unsigned long newval; + rt_hw_spinlock_t lockval; + __asm__ __volatile__( + "pld [%0]" + ::"r"(&lock->slock) + ); + + __asm__ __volatile__( + "1: ldrex %0, [%3]\n" + " add %1, %0, %4\n" + " strex %2, %1, [%3]\n" + " teq %2, #0\n" + " bne 1b" + : "=&r" (lockval), "=&r" (newval), "=&r" (tmp) + : "r" (&lock->slock), "I" (1 << 16) + : "cc"); + + while (lockval.tickets.next != lockval.tickets.owner) { + __WFE(); + lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner); + } + + __DMB(); +} + +void rt_hw_spin_unlock(rt_hw_spinlock_t *lock) +{ + __DMB(); + lock->tickets.owner++; + __DSB(); + __SEV(); +} +#endif /*RT_USING_SMP*/ + +/** + * @addtogroup ARM CPU + */ +/*@{*/ + +/** shutdown CPU */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +/*@}*/ diff --git a/libcpu/aarch64/cortex-a53/cpu_gcc.S b/libcpu/aarch64/cortex-a53/cpu_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..b8c8b8768c596714c29c7733ef18fc66cf1bb9f0 --- /dev/null +++ b/libcpu/aarch64/cortex-a53/cpu_gcc.S @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2018-10-06 ZhaoXiaowei the first version + */ + +.text +.globl rt_hw_get_current_el +rt_hw_get_current_el: + MRS X0, CurrentEL + CMP X0, 0xc + B.EQ 3f + CMP X0, 0x8 + B.EQ 2f + CMP X0, 0x4 + B.EQ 1f + + LDR X0, =0 + B 0f +3: + LDR X0, =3 + B 0f +2: + LDR X0, =2 + B 0f +1: + LDR X0, =1 + B 0f +0: + RET + + +.globl rt_hw_set_current_vbar +rt_hw_set_current_vbar: + MRS X1, CurrentEL + CMP X1, 0xc + B.EQ 3f + CMP X1, 0x8 + B.EQ 2f + CMP X1, 0x4 + B.EQ 1f + B 0f +3: + MSR VBAR_EL3,X0 + B 0f +2: + MSR VBAR_EL2,X0 + B 0f +1: + MSR VBAR_EL1,X0 + B 0f +0: + RET + + +.globl rt_hw_set_elx_env +rt_hw_set_elx_env: + MRS X1, CurrentEL + CMP X1, 0xc + B.EQ 3f + CMP X1, 0x8 + B.EQ 2f + CMP X1, 0x4 + B.EQ 1f + B 0f +3: + MRS X0, SCR_EL3 + ORR X0, X0, #0xF /* SCR_EL3.NS|IRQ|FIQ|EA */ + MSR SCR_EL3, X0 + B 0f +2: + MRS X0, HCR_EL2 + ORR X0, X0, #0x38 + MSR HCR_EL2, X0 + B 0f +1: + B 0f +0: + RET diff --git a/libcpu/aarch64/cortex-a53/entry_point.S b/libcpu/aarch64/cortex-a53/entry_point.S new file mode 100644 index 0000000000000000000000000000000000000000..6d2c69226b64ffc2226308bcd01aee3dbffe176a --- /dev/null +++ b/libcpu/aarch64/cortex-a53/entry_point.S @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2020-01-15 bigmagic the first version + */ + +.section ".text.entrypoint" + +.set EL1_stack, __el1_stack + +.global _start + +// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware +// loads 'kernel8.img' file in. +_start: + // read cpu id, stop slave cores + mrs x1, mpidr_el1 // MPIDR_EL1: Multi-Processor Affinity Register + and x1, x1, #3 + cbz x1, .L__cpu_0 // .L prefix is the local label in ELF + + // cpu id > 0, stop + // cpu id == 0 will also goto here after returned from entry() if possible +.L__current_cpu_idle: + wfe + b .L__current_cpu_idle + +.L__cpu_0: // cpu id == 0 + + // set stack before our code + + /* Define stack pointer for current exception level */ + // ldr x2, =EL1_stack + // mov sp, x2 + + ldr x1, =_start + + // set up EL1 + mrs x0, CurrentEL // CurrentEL Register. bit 2, 3. Others reserved + and x0, x0, #12 // clear reserved bits + + // running at EL3? + cmp x0, #12 // 1100b. So, EL3 + bne .L__not_in_el3 // 11? !EL3 -> 5: + + // should never be executed, just for completeness. (EL3) + mov x2, #0x5b1 + msr scr_el3, x2 // SCR_ELn Secure Configuration Register + mov x2, #0x3c9 + msr spsr_el3, x2 // SPSR_ELn. Saved Program Status Register. 1111001001 + adr x2, .L__not_in_el3 + msr elr_el3, x2 + eret // Exception Return: from EL3, continue from .L__not_in_el3 + + // running at EL2 or EL1 +.L__not_in_el3: + cmp x0, #4 // 0x04 0100 EL1 + beq .L__in_el1 // EL1 -> 5: + + // in EL2 + msr sp_el1, x1 // Set sp of EL1 to _start + + // enable CNTP for EL1 + mrs x0, cnthctl_el2 // Counter-timer Hypervisor Control register + orr x0, x0, #3 + msr cnthctl_el2, x0 + msr cntvoff_el2, xzr + + // enable AArch64 in EL1 + mov x0, #(1 << 31) // AArch64 + orr x0, x0, #(1 << 1) // SWIO hardwired on Pi3 + msr hcr_el2, x0 + mrs x0, hcr_el2 + + // change execution level to EL1 + mov x2, #0x3c4 + msr spsr_el2, x2 // 1111000100 + adr x2, .L__in_el1 + msr elr_el2, x2 + eret // exception return. from EL2. continue from .L__in_el1 + +.L__in_el1: + mov sp, x1 // in EL1. Set sp to _start + + // Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction + mov x1, #0x00300000 // Don't trap any SIMD/FP instructions in both EL0 and EL1 + msr cpacr_el1, x1 + + mrs x1, sctlr_el1 + orr x1, x1, #(1 << 12) + bic x1, x1, #(3 << 3) + bic x1, x1, #(1 << 1) + msr sctlr_el1, x1 + + // clear bss + ldr x1, =__bss_start + ldr w2, =__bss_size + +.L__clean_bss_loop: + cbz w2, .L__jump_to_entry + str xzr, [x1], #8 + sub w2, w2, #1 + cbnz w2, .L__clean_bss_loop + + // jump to C code, should not return +.L__jump_to_entry: + bl entry + // for failsafe, halt this core too + b .L__current_cpu_idle diff --git a/libcpu/aarch64/cortex-a53/interrupt.c b/libcpu/aarch64/cortex-a53/interrupt.c new file mode 100644 index 0000000000000000000000000000000000000000..8ad60c6de2248e9aaff0ff0df594faf75134b938 --- /dev/null +++ b/libcpu/aarch64/cortex-a53/interrupt.c @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/5/3 Bernard first version + * 2019-07-28 zdzn add smp support + * 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues, + * write addr to mailbox3 to startup smp, and we use mailbox0 for ipi + */ + +#include +#include + +#include "cp15.h" +#include "armv8.h" + +#include + +#define MAX_HANDLERS 72 + +#ifdef RT_USING_SMP +#define rt_interrupt_nest rt_cpu_self()->irq_nest +#else +extern volatile rt_uint8_t rt_interrupt_nest; +#endif + +extern int system_vectors; + +/* exception and interrupt handler table */ +struct rt_irq_desc isr_table[MAX_HANDLERS]; + +rt_ubase_t rt_interrupt_from_thread; +rt_ubase_t rt_interrupt_to_thread; +rt_ubase_t rt_thread_switch_interrupt_flag; + +void rt_hw_vector_init(void) +{ + rt_hw_set_current_vbar((rt_ubase_t)&system_vectors); // cpu_gcc.S +} + +static void default_isr_handler(int vector, void *param) +{ +#ifdef RT_USING_SMP + rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector); +#else + rt_kprintf("unhandled irq: %d\n",vector); +#endif +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_uint32_t index; + + /* mask all of interrupts */ + IRQ_DISABLE_BASIC = 0x000000ff; + IRQ_DISABLE1 = 0xffffffff; + IRQ_DISABLE2 = 0xffffffff; + for (index = 0; index < MAX_HANDLERS; index ++) + { + isr_table[index].handler = default_isr_handler; + isr_table[index].param = NULL; +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX); + isr_table[index].counter = 0; +#endif + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + if (vector < 32) + { + IRQ_DISABLE1 = (1 << vector); + } + else if (vector<64) + { + vector = vector % 32; + IRQ_DISABLE2 = (1 << vector); + } + else + { + vector = vector - 64; + IRQ_DISABLE_BASIC = (1 << vector); + } +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + if (vector < 32) + { + IRQ_ENABLE1 = (1 << vector); + } + else if (vector < 64) + { + vector = vector % 32; + IRQ_ENABLE2 = (1 << vector); + } + else + { + vector = vector - 64; + IRQ_ENABLE_BASIC = (1 << vector); + } +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector < MAX_HANDLERS) + { + old_handler = isr_table[vector].handler; + + if (handler != RT_NULL) + { +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + } + + return old_handler; +} + +#ifdef RT_USING_SMP +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) +{ + __DSB(); + if(cpu_mask & 0x1) + { + send_ipi_msg(0, ipi_vector); + } + if(cpu_mask & 0x2) + { + send_ipi_msg(1, ipi_vector); + } + if(cpu_mask & 0x4) + { + send_ipi_msg(2, ipi_vector); + } + if(cpu_mask & 0x8) + { + send_ipi_msg(3, ipi_vector); + } + __DSB(); +} +#endif + +#ifdef RT_USING_SMP +void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler) +{ + /* note: ipi_vector maybe different with irq_vector */ + rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); +} +#endif diff --git a/libcpu/aarch64/cortex-a53/interrupt.h b/libcpu/aarch64/cortex-a53/interrupt.h new file mode 100644 index 0000000000000000000000000000000000000000..0c20f79bcc18000a87f471b2098e639839245f68 --- /dev/null +++ b/libcpu/aarch64/cortex-a53/interrupt.h @@ -0,0 +1,29 @@ + +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include +#include + +#define INT_IRQ 0x00 +#define INT_FIQ 0x01 + +//void rt_hw_vector_init(void); + +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); + +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +#endif diff --git a/libcpu/aarch64/cortex-a53/mmu.c b/libcpu/aarch64/cortex-a53/mmu.c new file mode 100644 index 0000000000000000000000000000000000000000..29934b26a43a08cf5d50a836622889c1ad0da08f --- /dev/null +++ b/libcpu/aarch64/cortex-a53/mmu.c @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-01-10 bernard porting to AM1808 + * 2019-07-28 zdzn add smp support + */ + +#include "mmu.h" + +/* dump 2nd level page table */ +void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + for (i = 0; i < 256; i++) + { + rt_uint32_t pte2 = ptb[i]; + if ((pte2 & 0x3) == 0) + { + if (fcnt == 0) + rt_kprintf(" "); + rt_kprintf("%04x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf(" %04x: %x: ", i, pte2); + if ((pte2 & 0x3) == 0x1) + { + rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, + (pte2 >> 15) & 0x1, + ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); + } + else + { + rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1, + ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); + } + } +} + +void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + rt_kprintf("page table@%p\n", ptb); + for (i = 0; i < 1024*4; i++) + { + rt_uint32_t pte1 = ptb[i]; + if ((pte1 & 0x3) == 0) + { + rt_kprintf("%03x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf("%03x: %08x: ", i, pte1); + if ((pte1 & 0x3) == 0x3) + { + rt_kprintf("LPAE\n"); + } + else if ((pte1 & 0x3) == 0x1) + { + rt_kprintf("pte,ns:%d,domain:%d\n", + (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); + /* + *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) + * - 0x80000000 + 0xC0000000)); + */ + } + else if (pte1 & (1 << 18)) + { + rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); + } + else + { + rt_kprintf("section,ns:%d,ap:%x," + "xn:%d,texcb:%02x,domain:%d\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + (((pte1 & (0x7 << 12)) >> 10) | + ((pte1 & 0x0c) >> 2)) & 0x1f, + (pte1 >> 5) & 0xf); + } + } +} + +/* level1 page table, each entry for 1MB memory. */ +volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); +void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, + rt_uint32_t vaddrEnd, + rt_uint32_t paddrStart, + rt_uint32_t attr) +{ + volatile rt_uint32_t *pTT; + volatile int i, nSec; + pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20); + nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); + for(i = 0; i <= nSec; i++) + { + *pTT = attr | (((paddrStart >> 20) + i) << 20); + pTT++; + } +} + +unsigned long rt_hw_set_domain_register(unsigned long domain_val) +{ +#if 0 + unsigned long old_domain; + + asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); + asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); + + return old_domain; +#else + return 0; +#endif +} + +void rt_hw_init_mmu_table() +{ + /* set page table */ + /* 4G 1:1 memory */ + rt_hw_mmu_setmtt(0x00000000, 0x3effffff, 0x00000000, NORMAL_MEM); + /* IO memory region */ + rt_hw_mmu_setmtt(0x3f000000, 0x40010000, 0x3f000000, DEVICE_MEM); +} + +void rt_hw_change_mmu_table(rt_uint32_t vaddrStart, + rt_uint32_t size, + rt_uint32_t paddrStart, rt_uint32_t attr) +{ + rt_hw_mmu_setmtt(vaddrStart, vaddrStart+size-1, paddrStart, attr); +} + +void rt_hw_mmu_init(void) +{ + rt_cpu_dcache_clean_flush(); + rt_cpu_icache_flush(); + rt_hw_cpu_dcache_disable(); + rt_hw_cpu_icache_disable(); + rt_cpu_mmu_disable(); + + /*rt_hw_cpu_dump_page_table(MMUTable);*/ + rt_hw_set_domain_register(0x55555555); + + rt_cpu_tlb_set(MMUTable); + + rt_cpu_mmu_enable(); + + rt_hw_cpu_icache_enable(); + rt_hw_cpu_dcache_enable(); +} diff --git a/libcpu/aarch64/cortex-a53/mmu.h b/libcpu/aarch64/cortex-a53/mmu.h new file mode 100644 index 0000000000000000000000000000000000000000..5bef6094860092b22bb32b3dd10e508105da7233 --- /dev/null +++ b/libcpu/aarch64/cortex-a53/mmu.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-15 bigmagic the first version + */ +#ifndef MMU_H__ +#define MMU_H__ +#include +#include +#include +#include "cp15.h" + +#define DESC_SEC (0x2) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO +#define XN (1<<4) // eXecute Never +#define SHARED (1<<16) /* shareable */ +#define SHAREDEVICE (1<<2) /* shared device */ +#define STRONGORDER (0<<2) /* strong ordered */ +#define MEMWBWA ((1<<12)|(3<<2)) /* write back, write allocate */ + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +/* Read/Write, cache, write back */ +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) +/* Read/Write, cache, write through */ +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) +/* Read/Write without cache and write buffer */ +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) +/* Read/Write without cache and write buffer, no execute */ +#define RW_NCNBXN (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN) +/* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) + +/* device mapping type */ +#define DEVICE_MEM (SHARED|SHAREDEVICE|RW_NCNBXN) +/* normal memory mapping type */ +#define NORMAL_MEM (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC) +#define STRONG_ORDER_MEM (SHARED|AP_RO|XN|DESC_SEC) +#define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000) + +void rt_hw_change_mmu_table(rt_uint32_t vaddrStart, + rt_uint32_t size, + rt_uint32_t paddrStart, rt_uint32_t attr); +#endif diff --git a/libcpu/aarch64/cortex-a53/stack.c b/libcpu/aarch64/cortex-a53/stack.c new file mode 100644 index 0000000000000000000000000000000000000000..68222c2c67d440913a54c3e243f4898577f41172 --- /dev/null +++ b/libcpu/aarch64/cortex-a53/stack.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-23 Bernard the first version + * 2011-10-05 Bernard add thumb mode + */ +#include +#include + +#include + +#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0) +#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0) +#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0) + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_ubase_t *stk; + rt_ubase_t current_el; + + stk = (rt_ubase_t*)stack_addr; + + *(--stk) = ( rt_ubase_t ) 11; /* X1 */ + *(--stk) = ( rt_ubase_t ) parameter; /* X0 */ + *(--stk) = ( rt_ubase_t ) 33; /* X3 */ + *(--stk) = ( rt_ubase_t ) 22; /* X2 */ + *(--stk) = ( rt_ubase_t ) 55; /* X5 */ + *(--stk) = ( rt_ubase_t ) 44; /* X4 */ + *(--stk) = ( rt_ubase_t ) 77; /* X7 */ + *(--stk) = ( rt_ubase_t ) 66; /* X6 */ + *(--stk) = ( rt_ubase_t ) 99; /* X9 */ + *(--stk) = ( rt_ubase_t ) 88; /* X8 */ + *(--stk) = ( rt_ubase_t ) 11; /* X11 */ + *(--stk) = ( rt_ubase_t ) 10; /* X10 */ + *(--stk) = ( rt_ubase_t ) 13; /* X13 */ + *(--stk) = ( rt_ubase_t ) 12; /* X12 */ + *(--stk) = ( rt_ubase_t ) 15; /* X15 */ + *(--stk) = ( rt_ubase_t ) 14; /* X14 */ + *(--stk) = ( rt_ubase_t ) 17; /* X17 */ + *(--stk) = ( rt_ubase_t ) 16; /* X16 */ + *(--stk) = ( rt_ubase_t ) 19; /* X19 */ + *(--stk) = ( rt_ubase_t ) 18; /* X18 */ + *(--stk) = ( rt_ubase_t ) 21; /* X21 */ + *(--stk) = ( rt_ubase_t ) 20; /* X20 */ + *(--stk) = ( rt_ubase_t ) 23; /* X23 */ + *(--stk) = ( rt_ubase_t ) 22; /* X22 */ + *(--stk) = ( rt_ubase_t ) 25; /* X25 */ + *(--stk) = ( rt_ubase_t ) 24; /* X24 */ + *(--stk) = ( rt_ubase_t ) 27; /* X27 */ + *(--stk) = ( rt_ubase_t ) 26; /* X26 */ + *(--stk) = ( rt_ubase_t ) 29; /* X29 */ + *(--stk) = ( rt_ubase_t ) 28; /* X28 */ + *(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */ + *(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */ + + current_el = rt_hw_get_current_el(); + + if(current_el == 3) + { + *(--stk) = INITIAL_SPSR_EL3; + } + else if(current_el == 2) + { + *(--stk) = INITIAL_SPSR_EL2; + } + else + { + *(--stk) = INITIAL_SPSR_EL1; + } + + *(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} diff --git a/libcpu/aarch64/cortex-a53/startup_gcc.S b/libcpu/aarch64/cortex-a53/startup_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..ea4268148c8f50e924cc0ff6bbccecb68bec2ab7 --- /dev/null +++ b/libcpu/aarch64/cortex-a53/startup_gcc.S @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + + .global Reset_Handler + .section ".start", "ax" +Reset_Handler: + nop diff --git a/libcpu/aarch64/cortex-a53/trap.c b/libcpu/aarch64/cortex-a53/trap.c new file mode 100644 index 0000000000000000000000000000000000000000..13ae6d1b9e58bf25bf78bd6e2cd5346a81a180d3 --- /dev/null +++ b/libcpu/aarch64/cortex-a53/trap.c @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2018-10-06 ZhaoXiaowei the first version + */ + +#include +#include + +#include "interrupt.h" +#include "armv8.h" + +extern struct rt_thread *rt_current_thread; +#ifdef RT_USING_FINSH +extern long list_thread(void); +#endif + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void rt_hw_show_register(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%16.16llx r01:0x%16.16llx r02:0x%16.16llx r03:0x%16.16llx\n", regs->x0, regs->x1, regs->x2, regs->x3); + rt_kprintf("r04:0x%16.16llx r05:0x%16.16llx r06:0x%16.16llx r07:0x%16.16llx\n", regs->x4, regs->x5, regs->x6, regs->x7); + rt_kprintf("r08:0x%16.16llx r09:0x%16.16llx r10:0x%16.16llx r11:0x%16.16llx\n", regs->x8, regs->x9, regs->x10, regs->x11); + rt_kprintf("r12:0x%16.16llx r13:0x%16.16llx r14:0x%16.16llx r15:0x%16.16llx\n", regs->x12, regs->x13, regs->x14, regs->x15); + rt_kprintf("r16:0x%16.16llx r17:0x%16.16llx r18:0x%16.16llx r19:0x%16.16llx\n", regs->x16, regs->x17, regs->x18, regs->x19); + rt_kprintf("r20:0x%16.16llx r21:0x%16.16llx r22:0x%16.16llx r23:0x%16.16llx\n", regs->x20, regs->x21, regs->x22, regs->x23); + rt_kprintf("r24:0x%16.16llx r25:0x%16.16llx r26:0x%16.16llx r27:0x%16.16llx\n", regs->x24, regs->x25, regs->x26, regs->x27); + rt_kprintf("r28:0x%16.16llx r29:0x%16.16llx r30:0x%16.16llx", regs->x28, regs->x29, regs->x30); + rt_kprintf("spsr:0x%16.16llx", regs->spsr); + rt_kprintf("return pc:0x%16.16llx", regs->pc); +} + +/** + * When comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_error(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("error exception:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +#define GIC_ACK_INTID_MASK 0x000003ff + +void rt_hw_trap_irq(void) +{ + void *param; + uint32_t irq; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + uint32_t value = 0; + value = IRQ_PEND_BASIC & 0x3ff; +#ifdef RT_USING_SMP + uint32_t mailbox_data; + uint32_t cpu_id = rt_hw_cpu_id(); + uint32_t int_source = CORE_IRQSOURCE(cpu_id); + mailbox_data = IPI_MAILBOX_CLEAR(cpu_id); + if (int_source & 0x0f) + { + if (int_source & 0x08){ + isr_func = isr_table[IRQ_ARM_TIMER].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[IRQ_ARM_TIMER].counter++; +#endif + if (isr_func) + { + param = isr_table[IRQ_ARM_TIMER].param; + isr_func(IRQ_ARM_TIMER, param); + } + } + } + if (int_source & 0xf0) + { + /*it's a ipi interrupt*/ + if (mailbox_data & 0x1){ + /* clear mailbox */ + IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data; + isr_func = isr_table[IRQ_ARM_MAILBOX].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[IRQ_ARM_MAILBOX].counter++; +#endif + if (isr_func) + { + param = isr_table[IRQ_ARM_MAILBOX].param; + isr_func(IRQ_ARM_MAILBOX, param); + } + } + else + CORE_MAILBOX3_CLEAR(cpu_id) = mailbox_data; + } +#endif + /* local interrupt*/ + if (value) + { + if (value & (1 << 8)) + { + value = IRQ_PEND1; + irq = __rt_ffs(value) - 1; + } + else if (value & (1 << 9)) + { + value = IRQ_PEND2; + irq = __rt_ffs(value) + 31; + } + else + { + value &= 0x0f; + irq = __rt_ffs(value) + 63; + } + + /* get interrupt service routine */ + isr_func = isr_table[irq].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[irq].counter++; +#endif + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[irq].param; + /* turn to interrupt service routine */ + isr_func(irq, param); + } + } +} + +void rt_hw_trap_fiq(void) +{ + void *param; + uint32_t irq; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + uint32_t value = 0; + value = IRQ_PEND_BASIC & 0x3ff; +#ifdef RT_USING_SMP + uint32_t mailbox_data; + uint32_t cpu_id = rt_hw_cpu_id(); + uint32_t int_source = CORE_IRQSOURCE(cpu_id); + mailbox_data = IPI_MAILBOX_CLEAR(cpu_id); + if (int_source & 0x0f) + { + if (int_source & 0x08) + { + isr_func = isr_table[IRQ_ARM_TIMER].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[IRQ_ARM_TIMER].counter++; +#endif + if (isr_func) + { + param = isr_table[IRQ_ARM_TIMER].param; + isr_func(IRQ_ARM_TIMER, param); + } + } + } + if (int_source & 0xf0) + { + /*it's a ipi interrupt*/ + if (mailbox_data & 0x1) + { + /* clear mailbox */ + IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data; + isr_func = isr_table[IRQ_ARM_MAILBOX].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[IRQ_ARM_MAILBOX].counter++; +#endif + if (isr_func) + { + param = isr_table[IRQ_ARM_MAILBOX].param; + isr_func(IRQ_ARM_MAILBOX, param); + } + } + else + CORE_MAILBOX3_CLEAR(cpu_id) = mailbox_data; + } +#endif + /* local interrupt*/ + if (value) + { + if (value & (1 << 8)) + { + value = IRQ_PEND1; + irq = __rt_ffs(value) - 1; + } + else if (value & (1 << 9)) + { + value = IRQ_PEND2; + irq = __rt_ffs(value) + 31; + } + else + { + value &= 0x0f; + irq = __rt_ffs(value) + 63; + } + + /* get interrupt service routine */ + isr_func = isr_table[irq].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[irq].counter++; +#endif + if (irq > 1) + rt_kprintf("interrupt fiq %d\n", irq); + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[irq].param; + /* turn to interrupt service routine */ + isr_func(irq, param); + } + } +} diff --git a/libcpu/aarch64/cortex-a53/vector_gcc.S b/libcpu/aarch64/cortex-a53/vector_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..fc88cce7f864ba7b884eb105abf582fe080ccb5c --- /dev/null +++ b/libcpu/aarch64/cortex-a53/vector_gcc.S @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2018-10-06 ZhaoXiaowei the first version + */ + +.text + +.globl system_vectors +.globl vector_error +.globl vector_irq +.globl vector_fiq + +system_vectors: +.align 11 + .set VBAR, system_vectors + .org VBAR + // Exception from CurrentEL (EL1) with SP_EL0 (SPSEL=1) + .org (VBAR + 0x00 + 0) + B vector_error // Synchronous + .org (VBAR + 0x80 + 0) + B vector_irq // IRQ/vIRQ + .org (VBAR + 0x100 + 0) + B vector_fiq // FIQ/vFIQ + .org (VBAR + 0x180 + 0) + B vector_error // Error/vError + + // Exception from CurrentEL (EL1) with SP_ELn + .org (VBAR + 0x200 + 0) + B vector_error // Synchronous + .org (VBAR + 0x280 + 0) + B vector_irq // IRQ/vIRQ + .org (VBAR + 0x300 + 0) + B vector_fiq // FIQ/vFIQ + .org (VBAR + 0x380 + 0) + B vector_error + + // Exception from lower EL, aarch64 + .org (VBAR + 0x400 + 0) + B vector_error + .org (VBAR + 0x480 + 0) + B vector_error + .org (VBAR + 0x500 + 0) + B vector_error + .org (VBAR + 0x580 + 0) + B vector_error + + // Exception from lower EL, aarch32 + .org (VBAR + 0x600 + 0) + B vector_error + .org (VBAR + 0x680 + 0) + B vector_error + .org (VBAR + 0x700 + 0) + B vector_error + .org (VBAR + 0x780 + 0) + B vector_error + .org (VBAR + 0x800 + 0) + B vector_error diff --git a/libcpu/arc/em/SConscript b/libcpu/arc/em/SConscript index 49c32b689d6b1711aa89a8b7c77193bd4f477579..ff1d8c134d2b7124e2229c555d2d846a92ac5234 100644 --- a/libcpu/arc/em/SConscript +++ b/libcpu/arc/em/SConscript @@ -8,9 +8,7 @@ cwd = GetCurrentDir() src = Glob('*.c') CPPPATH = [cwd] - -if rtconfig.PLATFORM == 'gcc': - src += Glob('*_gcc.S') +src += Glob('*.S') group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) diff --git a/libcpu/arc/em/contex_gcc.S b/libcpu/arc/em/contex_gcc_mw.S similarity index 61% rename from libcpu/arc/em/contex_gcc.S rename to libcpu/arc/em/contex_gcc_mw.S index a8abe089bf60c615d44086ca402d63673a98e7bf..81b291c1c8f2d9419e9a36c19dc5d926c2ebdd8b 100644 --- a/libcpu/arc/em/contex_gcc.S +++ b/libcpu/arc/em/contex_gcc_mw.S @@ -4,20 +4,43 @@ * SPDX-License-Identifier: Apache-2.0 */ #define __ASSEMBLY__ -#include "inc/arc/arc.h" -#include "inc/arc/arc_asm_common.h" +#include "include/arc/arc.h" +#include "include/arc/arc_asm_common.h" -.global rt_interrupt_enter; .type rt_interrupt_enter, %function -.global rt_interrupt_leave; .type rt_interrupt_leave, %function -.global context_switch_reqflg; .type context_switch_reqflg, %object -.global rt_interrupt_from_thread; .type rt_interrupt_from_thread, %object -.global rt_interrupt_to_thread; .type rt_interrupt_to_thread, %object +.global rt_interrupt_enter; +.global rt_interrupt_leave; +.global context_switch_reqflg; +.global rt_interrupt_from_thread; +.global rt_interrupt_to_thread; +.global exc_nest_count; +.global set_hw_stack_check; .text .align 4 dispatcher: st sp, [r0] ld sp, [r1] +#if ARC_FEATURE_STACK_CHECK +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bclr r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif + jl set_hw_stack_check +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bset r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bset r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif +#endif pop r0 j [r0] @@ -29,8 +52,8 @@ dispatch_r: /* * rt_base_t rt_hw_interrupt_disable(); */ -.global rt_hw_interrupt_disable -.type rt_hw_interrupt_disable, %function + .global rt_hw_interrupt_disable + .align 4 rt_hw_interrupt_disable: clri r0 j [blink] @@ -39,15 +62,15 @@ rt_hw_interrupt_disable: /* * void rt_hw_interrupt_enable(rt_base_t level); */ -.global rt_hw_interrupt_enable -.type rt_hw_interrupt_enable, %function + .global rt_hw_interrupt_enable + .align 4 rt_hw_interrupt_enable: seti r0 j [blink] -.global rt_hw_context_switch_interrupt -.type rt_hw_context_switch_interrupt, %function + .global rt_hw_context_switch_interrupt + .align 4 rt_hw_context_switch_interrupt: st r0, [rt_interrupt_from_thread] st r1, [rt_interrupt_to_thread] @@ -61,8 +84,8 @@ rt_hw_context_switch_interrupt: * r0 --> from * r1 --> to */ -.global rt_hw_context_switch -.type rt_hw_context_switch, %function + .global rt_hw_context_switch + .align 4 rt_hw_context_switch: SAVE_NONSCRATCH_REGS mov r2, dispatch_r @@ -74,15 +97,37 @@ rt_hw_context_switch: * void rt_hw_context_switch_to(rt_uint32 to); * r0 --> to */ -.global rt_hw_context_switch_to -.type rt_hw_context_switch_to, %function + .global rt_hw_context_switch_to + .align 4 rt_hw_context_switch_to: ld sp, [r0] +#if ARC_FEATURE_STACK_CHECK + mov r1, r0 +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bclr r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif + jl set_hw_stack_check +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bset r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bset r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif +#endif pop r0 j [r0] -.global start_r -.type start_r, %function + .global start_r + .align 4 start_r: pop blink; pop r1 @@ -92,6 +137,19 @@ start_r: j_s.d [r1] kflag r2 +/* + * int __rt_ffs(int value); + * r0 --> value + */ + .global __rt_ffs + .align 4 +__rt_ffs: + breq r0, 0, __rt_ffs_return + ffs r1, r0 + add r0, r1, 1 +__rt_ffs_return: + j [blink] + /****** exceptions and interrupts handing ******/ /****** entry for exception handling ******/ .global exc_entry_cpu @@ -106,8 +164,7 @@ exc_entry_cpu: ld r0, [exc_nest_count] add r1, r0, 1 st r1, [exc_nest_count] - cmp r0, 0 - bne exc_handler_1 + brne r0, 0, exc_handler_1 /* change to exception stack if interrupt happened in task context */ mov sp, _e_stack exc_handler_1: @@ -127,13 +184,13 @@ ret_exc: mov r1, exc_nest_count ld r0, [r1] sub r0, r0, 1 - cmp r0, 0 - bne.d ret_exc_1 st r0, [r1] + brne r0, 0, ret_exc_1 /* nest exception case */ + lr r1, [AUX_IRQ_ACT] /* nest interrupt case */ + brne r1, 0, ret_exc_1 ld r0, [context_switch_reqflg] - cmp r0, 0 - bne ret_exc_2 + brne r0, 0, ret_exc_2 ret_exc_1: /* return from non-task context, interrupts or exceptions are nested */ EXCEPTION_EPILOGUE rtie @@ -196,10 +253,20 @@ exc_entry_int: st r2, [exc_nest_count] seti /* enable higher priority interrupt */ - cmp r3, 0 - bne irq_handler_1 + brne r3, 0, irq_handler_1 /* change to exception stack if interrupt happened in task context */ mov sp, _e_stack +#if ARC_FEATURE_STACK_CHECK +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bclr r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif +#endif irq_handler_1: PUSH blink @@ -228,13 +295,17 @@ ret_int: mov r1, exc_nest_count ld r0, [r1] sub r0, r0, 1 - cmp r0, 0 - bne.d ret_int_1 st r0, [r1] +/* if there are multi-bits set in IRQ_ACT, it's still in nest interrupt */ + lr r0, [AUX_IRQ_CAUSE] + sr r0, [AUX_IRQ_SELECT] + lr r3, [AUX_IRQ_PRIORITY] + lr r1, [AUX_IRQ_ACT] + bclr r2, r1, r3 + brne r2, 0, ret_int_1 ld r0, [context_switch_reqflg] - cmp r0, 0 - bne ret_int_2 + brne r0, 0, ret_int_2 ret_int_1: /* return from non-task context */ INTERRUPT_EPILOGUE rtie @@ -263,4 +334,31 @@ ret_int_r: /* recover AUX_IRQ_ACT to restore the interrup status */ POPAX AUX_IRQ_ACT INTERRUPT_EPILOGUE - rtie \ No newline at end of file + rtie + +/****** entry for fast irq exception handling ******/ + .global exc_entry_firq + .weak exc_entry_firq + .align 4 +exc_entry_firq: + SAVE_FIQ_EXC_REGS + + lr r0, [AUX_IRQ_CAUSE] + mov r1, exc_int_handler_table +/* r2 = _kernel_exc_tbl + irqno *4 */ + ld.as r2, [r1, r0] + +/* for the case of software triggered interrupt */ + lr r3, [AUX_IRQ_HINT] + cmp r3, r0 + bne.d firq_hint_handled + xor r3, r3, r3 + sr r3, [AUX_IRQ_HINT] +firq_hint_handled: +/* jump to interrupt handler */ + mov r0, sp + jl [r2] + +firq_return: + RESTORE_FIQ_EXC_REGS + rtie diff --git a/libcpu/arc/em/cpuport.c b/libcpu/arc/em/cpuport.c index 88c2e12f9b693b109579121aaf24a7072964df75..34f538881fcc6c93e1cc0d87047d1453bc4a308c 100644 --- a/libcpu/arc/em/cpuport.c +++ b/libcpu/arc/em/cpuport.c @@ -5,11 +5,13 @@ */ #include -#include "inc/arc/arc_exception.h" - -/* enable interrupt and set interrupt priority mask */ -#define ARC_INIT_STATUS (AUX_STATUS_MASK_IE | ((-1 - INT_PRI_MIN) << 1)) +#include "arc/arc_exception.h" +#if ARC_FEATURE_STACK_CHECK +#define ARC_INIT_STATUS ((1 << AUX_STATUS_BIT_SC) | AUX_STATUS_MASK_IE | ((-1 - INT_PRI_MIN) << 1) | STATUS32_RESET_VALUE) +#else +#define ARC_INIT_STATUS (AUX_STATUS_MASK_IE | ((-1 - INT_PRI_MIN) << 1) | STATUS32_RESET_VALUE) +#endif extern void start_r(void); @@ -17,6 +19,7 @@ extern void start_r(void); rt_uint32_t context_switch_reqflg; rt_uint32_t rt_interrupt_from_thread; rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t exc_nest_count; struct init_stack_frame { rt_uint32_t pc; @@ -66,4 +69,19 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)) { exception_handle = exception_handle; -} \ No newline at end of file +} + +void set_hw_stack_check(rt_uint32_t *from, rt_uint32_t *to) +{ + struct rt_thread *rt_thread_to; + if (to != NULL) { + rt_thread_to = rt_container_of(to, struct rt_thread, sp); +#if ARC_FEATURE_SEC_PRESENT + arc_aux_write(AUX_S_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr)); + arc_aux_write(AUX_S_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size); +#else + arc_aux_write(AUX_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr)); + arc_aux_write(AUX_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size); +#endif + } +} diff --git a/libcpu/arm/cortex-a53/cp15.h b/libcpu/arm/cortex-a53/cp15.h new file mode 100644 index 0000000000000000000000000000000000000000..14b85b7e6466c5781322483c367f9d0ac13798db --- /dev/null +++ b/libcpu/arm/cortex-a53/cp15.h @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + */ +#include "raspi.h" +#ifndef __CP15_H__ +#define __CP15_H__ + +#ifndef __STATIC_FORCEINLINE +#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif + +#define __WFI() __asm__ volatile ("wfi":::"memory") + +#define __WFE() __asm__ volatile ("wfe":::"memory") + +#define __SEV() __asm__ volatile ("sev") + +__STATIC_FORCEINLINE void __ISB(void) +{ + __asm__ volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __asm__ volatile ("dsb 0xF":::"memory"); +} + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ + +__STATIC_FORCEINLINE void __DMB(void) +{ + __asm__ volatile ("dmb 0xF":::"memory"); +} + + +#ifdef RT_USING_SMP +static inline void send_ipi_msg(int cpu, int ipi_vector) +{ + IPI_MAILBOX_SET(cpu) = 1 << ipi_vector; +} + +static inline void setup_bootstrap_addr(int cpu, int addr) +{ + CORE_MAILBOX3_SET(cpu) = addr; +} + +static inline void enable_cpu_ipi_intr(int cpu) +{ + COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK; +} + +static inline void enable_cpu_timer_intr(int cpu) +{ + CORETIMER_INTCTL(cpu) = 0x8; +} + +static inline void enable_cntv(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 1; + asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL +} + +static inline void disable_cntv(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 0; + asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL +} + +static inline void mask_cntv(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 2; + asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL +} + +static inline void unmask_cntv(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 1; + asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL +} + +static inline rt_uint64_t read_cntvct(void) +{ + rt_uint32_t val,val1; + asm volatile ("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1)); + return (val); +} + +static inline rt_uint64_t read_cntvoff(void) +{ + + rt_uint64_t val; + asm volatile ("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val)); + return (val); +} + +static inline rt_uint32_t read_cntv_tval(void) +{ + rt_uint32_t val; + asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val)); + return val; +} + + +static inline void write_cntv_tval(rt_uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val)); + return; +} + +static inline rt_uint32_t read_cntfrq(void) +{ + rt_uint32_t val; + asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val)); + return val; +} + + +static inline rt_uint32_t read_cntctrl(void) +{ + rt_uint32_t val; + asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val)); + return val; +} + +static inline uint32_t write_cntctrl(uint32_t val) +{ + + asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val)); + return val; +} +#endif + +unsigned long rt_cpu_get_smp_id(void); + +void rt_cpu_mmu_disable(void); +void rt_cpu_mmu_enable(void); +void rt_cpu_tlb_set(volatile unsigned long*); + +void rt_cpu_dcache_clean_flush(void); +void rt_cpu_icache_flush(void); + +void rt_cpu_vector_set_base(unsigned int addr); +void rt_hw_mmu_init(void); +void rt_hw_vector_init(void); + +void set_timer_counter(unsigned int counter); +void set_timer_control(unsigned int control); +#endif diff --git a/libcpu/arm/cortex-a53/cpu.c b/libcpu/arm/cortex-a53/cpu.c new file mode 100644 index 0000000000000000000000000000000000000000..4d02ca35e184139c60a67578ed20f04e4a9e8dff --- /dev/null +++ b/libcpu/arm/cortex-a53/cpu.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + * 2019-07-28 zdzn add smp support + */ + +#include +#include +#include +#include "cp15.h" + +int rt_hw_cpu_id(void) +{ + int cpu_id; + __asm__ volatile ( + "mrc p15, 0, %0, c0, c0, 5" + :"=r"(cpu_id) + ); + cpu_id &= 0xf; + return cpu_id; +}; + + +#ifdef RT_USING_SMP +void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock) +{ + lock->slock = 0; +} + +void rt_hw_spin_lock(rt_hw_spinlock_t *lock) +{ + unsigned long tmp; + unsigned long newval; + rt_hw_spinlock_t lockval; + __asm__ __volatile__( + "pld [%0]" + ::"r"(&lock->slock) + ); + + __asm__ __volatile__( + "1: ldrex %0, [%3]\n" + " add %1, %0, %4\n" + " strex %2, %1, [%3]\n" + " teq %2, #0\n" + " bne 1b" + : "=&r" (lockval), "=&r" (newval), "=&r" (tmp) + : "r" (&lock->slock), "I" (1 << 16) + : "cc"); + + while (lockval.tickets.next != lockval.tickets.owner) + { + __WFE(); + lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner); + } + + __DMB(); +} + +void rt_hw_spin_unlock(rt_hw_spinlock_t *lock) +{ + __DMB(); + lock->tickets.owner++; + __DSB(); + __SEV(); +} +#endif /*RT_USING_SMP*/ + +/** + * @addtogroup ARM CPU + */ +/*@{*/ + +/** shutdown CPU */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +/*@}*/ diff --git a/libcpu/arm/cortex-a53/interrupt.c b/libcpu/arm/cortex-a53/interrupt.c new file mode 100644 index 0000000000000000000000000000000000000000..c9e7c17f8f495f1801116023b0361eff28bbe5fd --- /dev/null +++ b/libcpu/arm/cortex-a53/interrupt.c @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/5/3 Bernard first version + * 2019-07-28 zdzn add smp support + * 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues, + * write addr to mailbox3 to startup smp, and we use mailbox0 for ipi + */ + +#include +#include + +#include "cp15.h" +#include + +#define MAX_HANDLERS 72 + +#ifdef RT_USING_SMP +#define rt_interrupt_nest rt_cpu_self()->irq_nest +#else +extern volatile rt_uint8_t rt_interrupt_nest; +#endif + +const unsigned int VECTOR_BASE = 0x00; +extern void rt_cpu_vector_set_base(unsigned int addr); +extern int system_vectors; + +void rt_hw_vector_init(void) +{ + rt_cpu_vector_set_base((unsigned int)&system_vectors); +} + +/* exception and interrupt handler table */ +struct rt_irq_desc isr_table[MAX_HANDLERS]; + +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +extern int system_vectors; + +static void default_isr_handler(int vector, void *param) +{ +#ifdef RT_USING_SMP + rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector); +#else + rt_kprintf("unhandled irq: %d\n",vector); +#endif +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_uint32_t index; + + /* mask all of interrupts */ + IRQ_DISABLE_BASIC = 0x000000ff; + IRQ_DISABLE1 = 0xffffffff; + IRQ_DISABLE2 = 0xffffffff; + for (index = 0; index < MAX_HANDLERS; index ++) + { + isr_table[index].handler = default_isr_handler; + isr_table[index].param = NULL; +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX); + isr_table[index].counter = 0; +#endif + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + + if (vector < 32) + { + IRQ_DISABLE1 = (1 << vector); + } + else if (vector < 64) + { + vector = vector % 32; + IRQ_DISABLE2 = (1 << vector); + } + else + { + vector = vector - 64; + IRQ_DISABLE_BASIC = (1 << vector); + } +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + if (vector < 32) + { + IRQ_ENABLE1 = (1 << vector); + } + else if (vector < 64) + { + vector = vector % 32; + IRQ_ENABLE2 = (1 << vector); + } + else + { + vector = vector - 64; + IRQ_ENABLE_BASIC = (1 << vector); + } +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector < MAX_HANDLERS) + { + old_handler = isr_table[vector].handler; + + if (handler != RT_NULL) + { +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + } + + return old_handler; +} + +#ifdef RT_USING_SMP +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) +{ + __DSB(); + if (cpu_mask & 0x1) + { + send_ipi_msg(0, ipi_vector); + } + if (cpu_mask & 0x2) + { + send_ipi_msg(1, ipi_vector); + } + if (cpu_mask & 0x4) + { + send_ipi_msg(2, ipi_vector); + } + if (cpu_mask & 0x8) + { + send_ipi_msg(3, ipi_vector); + } + __DSB(); +} +#endif + +#ifdef RT_USING_SMP +void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler) +{ + /* note: ipi_vector maybe different with irq_vector */ + rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); +} +#endif diff --git a/libcpu/arm/cortex-a53/interrupt.h b/libcpu/arm/cortex-a53/interrupt.h new file mode 100644 index 0000000000000000000000000000000000000000..9aae0f556a0338f5b8afe5d2e2e1275da1012ac3 --- /dev/null +++ b/libcpu/arm/cortex-a53/interrupt.h @@ -0,0 +1,18 @@ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include +#include + +#define INT_IRQ 0x00 +#define INT_FIQ 0x01 + +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); + +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +#endif diff --git a/libcpu/arm/cortex-a53/mmu.c b/libcpu/arm/cortex-a53/mmu.c new file mode 100644 index 0000000000000000000000000000000000000000..b3541d2ad431ebdd09399989f14f2ca48e06c450 --- /dev/null +++ b/libcpu/arm/cortex-a53/mmu.c @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-01-10 bernard porting to AM1808 + * 2019-07-28 zdzn add smp support + */ + +#include "mmu.h" + +/* dump 2nd level page table */ +void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + for (i = 0; i < 256; i++) + { + rt_uint32_t pte2 = ptb[i]; + if ((pte2 & 0x3) == 0) + { + if (fcnt == 0) + rt_kprintf(" "); + rt_kprintf("%04x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf(" %04x: %x: ", i, pte2); + if ((pte2 & 0x3) == 0x1) + { + rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, + (pte2 >> 15) & 0x1, + ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); + } + else + { + rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1, + ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); + } + } +} + +void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + rt_kprintf("page table@%p\n", ptb); + for (i = 0; i < 1024*4; i++) + { + rt_uint32_t pte1 = ptb[i]; + if ((pte1 & 0x3) == 0) + { + rt_kprintf("%03x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf("%03x: %08x: ", i, pte1); + if ((pte1 & 0x3) == 0x3) + { + rt_kprintf("LPAE\n"); + } + else if ((pte1 & 0x3) == 0x1) + { + rt_kprintf("pte,ns:%d,domain:%d\n", + (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); + /* + *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) + * - 0x80000000 + 0xC0000000)); + */ + } + else if (pte1 & (1 << 18)) + { + rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); + } + else + { + rt_kprintf("section,ns:%d,ap:%x," + "xn:%d,texcb:%02x,domain:%d\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + (((pte1 & (0x7 << 12)) >> 10) | + ((pte1 & 0x0c) >> 2)) & 0x1f, + (pte1 >> 5) & 0xf); + } + } +} + +/* level1 page table, each entry for 1MB memory. */ +volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); +void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, + rt_uint32_t vaddrEnd, + rt_uint32_t paddrStart, + rt_uint32_t attr) +{ + volatile rt_uint32_t *pTT; + volatile int i, nSec; + pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20); + nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); + for (i = 0; i <= nSec; i++) + { + *pTT = attr | (((paddrStart >> 20) + i) << 20); + pTT++; + } +} + +unsigned long rt_hw_set_domain_register(unsigned long domain_val) +{ + unsigned long old_domain; + + asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); + asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); + + return old_domain; +} + +void rt_hw_init_mmu_table() +{ + /* set page table */ + /* 4G 1:1 memory */ + rt_hw_mmu_setmtt(0x00000000, 0x3effffff, 0x00000000, NORMAL_MEM); + /* IO memory region */ + rt_hw_mmu_setmtt(0x3f000000, 0x40010000, 0x3f000000, DEVICE_MEM); +} + +void rt_hw_change_mmu_table(rt_uint32_t vaddrStart, + rt_uint32_t size, + rt_uint32_t paddrStart, rt_uint32_t attr) +{ + rt_hw_mmu_setmtt(vaddrStart, vaddrStart+size-1, paddrStart, attr); +#ifndef RT_USING_SMP + rt_cpu_dcache_clean_flush(); + rt_cpu_icache_flush(); +#endif +} + + +void rt_hw_mmu_init(void) +{ + rt_cpu_dcache_clean_flush(); + rt_cpu_icache_flush(); + rt_hw_cpu_dcache_disable(); + rt_hw_cpu_icache_disable(); + rt_cpu_mmu_disable(); + + /*rt_hw_cpu_dump_page_table(MMUTable);*/ + rt_hw_set_domain_register(0x55555555); + + rt_cpu_tlb_set(MMUTable); + + rt_cpu_mmu_enable(); + + rt_hw_cpu_icache_enable(); + rt_hw_cpu_dcache_enable(); +} + diff --git a/libcpu/arm/cortex-m33/context_gcc.S b/libcpu/arm/cortex-m33/context_gcc.S index 3c7dcfa3d7f72088ec9e0a2cee52ce36d60b62c9..18e97c631ed4118e33c6702ed632274b11310f3e 100644 --- a/libcpu/arm/cortex-m33/context_gcc.S +++ b/libcpu/arm/cortex-m33/context_gcc.S @@ -98,7 +98,7 @@ PendSV_Handler: MSR PRIMASK, r2 /* if r1 == 0x00, do msr PRIMASK, r2 */ BX lr /* if r1 == 0x00, do bx lr */ -schedule +schedule: PUSH {r2} /* store interrupt state */ /* clear rt_thread_switch_interrupt_flag to 0 */ diff --git a/libcpu/rx/context_iar.S b/libcpu/rx/context_iar.S index 143ae003156146d343714ea617aa03cebccf24f0..db02ce4d1fcd973c923831ecea238bf9f5717359 100644 --- a/libcpu/rx/context_iar.S +++ b/libcpu/rx/context_iar.S @@ -73,12 +73,12 @@ ___interrupt_27: MOV.L #_rt_interrupt_from_thread, R15 MOV.L [ R15 ], R15 MOV.L R0, [ R15 ] - BRA swtich_to_thread + BRA switch_to_thread need_modify_isp: MVFC ISP, R15 ADD #12, R15 MVTC R15, ISP -swtich_to_thread: +switch_to_thread: SETPSW U MOV.L #_rt_interrupt_to_thread, R15 MOV.L [ R15 ], R15 diff --git a/libcpu/rx/cpuport.c b/libcpu/rx/cpuport.c index e8a75c629e78bb19df682f98b1d02754721b055e..681c0e8e6ec49fbbb619ccee31d89be29d09eb58 100644 --- a/libcpu/rx/cpuport.c +++ b/libcpu/rx/cpuport.c @@ -58,7 +58,7 @@ struct stack_frame }; /** - * Initilial the threah stack. + * Initilial the thread stack. * * @author LXZ (2014/11/8) * @@ -158,7 +158,7 @@ void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) ENTER_INTERRUPT(); } /** - * swithc thread out the interrupt + * switch thread out the interrupt * * @author LXZ (2014/11/8) * diff --git a/src/Kconfig b/src/Kconfig index 22942a017eec66720c9f13880291881ab126395a..63a7a67887285ff1b45b584c505cd45faf655476 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -331,7 +331,7 @@ endmenu config RT_VER_NUM hex - default 0x40002 + default 0x40003 help RT-Thread version number diff --git a/src/components.c b/src/components.c index df3e0f0fb37ad8bf0053c3860316f297ea14c911..e7824b65efe10f8e74416eb45db6a94fd75ef501 100644 --- a/src/components.c +++ b/src/components.c @@ -92,7 +92,7 @@ void rt_components_board_init(void) rt_kprintf(":%d done\n", result); } #else - const init_fn_t *fn_ptr; + volatile const init_fn_t *fn_ptr; for (fn_ptr = &__rt_init_rti_board_start; fn_ptr < &__rt_init_rti_board_end; fn_ptr++) { @@ -118,7 +118,7 @@ void rt_components_init(void) rt_kprintf(":%d done\n", result); } #else - const init_fn_t *fn_ptr; + volatile const init_fn_t *fn_ptr; for (fn_ptr = &__rt_init_rti_board_end; fn_ptr < &__rt_init_rti_end; fn_ptr ++) { @@ -174,11 +174,11 @@ void main_thread_entry(void *parameter) { extern int main(void); extern int $Super$$main(void); - + #ifdef RT_USING_COMPONENTS_INIT /* RT-Thread components initialization */ rt_components_init(); -#endif +#endif #ifdef RT_USING_SMP rt_hw_secondary_cpu_up(); #endif diff --git a/src/kservice.c b/src/kservice.c index 58f04330f1014b5a66b685ba1a50393dadf344f0..0a8786e17add34930b7fe772fa3723daa87068f8 100644 --- a/src/kservice.c +++ b/src/kservice.c @@ -538,7 +538,7 @@ void rt_show_version(void) rt_kprintf("- RT - Thread Operating System\n"); rt_kprintf(" / | \\ %d.%d.%d build %s\n", RT_VERSION, RT_SUBVERSION, RT_REVISION, __DATE__); - rt_kprintf(" 2006 - 2019 Copyright by rt-thread team\n"); + rt_kprintf(" 2006 - 2020 Copyright by rt-thread team\n"); } RTM_EXPORT(rt_show_version); diff --git a/src/thread.c b/src/thread.c index 3a3c97d0b67d8aaecd5473ab1825dcd2461f2845..19ab5549c82883adddfd4548f8edba08d0fd5abe 100644 --- a/src/thread.c +++ b/src/thread.c @@ -585,12 +585,12 @@ rt_err_t rt_thread_delay_until(rt_tick_t *tick, rt_tick_t inc_tick) return RT_EOK; } -RTM_EXPORT(rt_thread_delay_util); +RTM_EXPORT(rt_thread_delay_until); /** * This function will let current thread delay for some milliseconds. * - * @param tick the delay time + * @param ms the delay ms time * * @return RT_EOK */ diff --git a/src/timer.c b/src/timer.c index 3992cf6ff448c53bb912b58bc3a8f7d38a1bfd53..0034f0246c222041bd0c873db6df3c7a3b900524 100644 --- a/src/timer.c +++ b/src/timer.c @@ -108,14 +108,23 @@ static void _rt_timer_init(rt_timer_t timer, static rt_tick_t rt_timer_list_next_timeout(rt_list_t timer_list[]) { struct rt_timer *timer; + register rt_base_t level; + rt_tick_t timeout_tick = RT_TICK_MAX; - if (rt_list_isempty(&timer_list[RT_TIMER_SKIP_LIST_LEVEL - 1])) - return RT_TICK_MAX; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - timer = rt_list_entry(timer_list[RT_TIMER_SKIP_LIST_LEVEL - 1].next, - struct rt_timer, row[RT_TIMER_SKIP_LIST_LEVEL - 1]); + if (!rt_list_isempty(&timer_list[RT_TIMER_SKIP_LIST_LEVEL - 1])) + { + timer = rt_list_entry(timer_list[RT_TIMER_SKIP_LIST_LEVEL - 1].next, + struct rt_timer, row[RT_TIMER_SKIP_LIST_LEVEL - 1]); + timeout_tick = timer->timeout_tick; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); - return timer->timeout_tick; + return timeout_tick; } rt_inline void _rt_timer_remove(rt_timer_t timer) @@ -479,6 +488,19 @@ rt_err_t rt_timer_control(rt_timer_t timer, int cmd, void *arg) case RT_TIMER_CTRL_SET_PERIODIC: timer->parent.flag |= RT_TIMER_FLAG_PERIODIC; break; + /* zhaoshimin 20191204 add query the timer state */ + case RT_TIMER_CTRL_GET_STATE: + if(timer->parent.flag & RT_TIMER_FLAG_ACTIVATED) + { + /*timer is start and run*/ + *(rt_tick_t *)arg = RT_TIMER_FLAG_ACTIVATED; + } + else + { + /*timer is stop*/ + *(rt_tick_t *)arg = RT_TIMER_FLAG_DEACTIVATED; + } + break; } return RT_EOK; diff --git a/tools/eclipse.py b/tools/eclipse.py index 253db37bea35341f830c3a06c0c04253a55b0d14..0f001b8bb8f5f4fd1df794ddbed2b356251a696a 100644 --- a/tools/eclipse.py +++ b/tools/eclipse.py @@ -20,6 +20,10 @@ from utils import xml_indent import xml.etree.ElementTree as etree from xml.etree.ElementTree import SubElement +from building import * + +MODULE_VER_NUM = 0 + source_pattern = ['*.c', '*.cpp', '*.cxx', '*.s', '*.S', '*.asm'] def OSPath(path): @@ -134,57 +138,66 @@ def IsRttEclipsePathFormat(path): return True else : return False + + +def IsCppProject(): + return GetDepend('RT_USING_CPLUSPLUS') - + def HandleToolOption(tools, env, project, reset): + is_cpp_prj = IsCppProject() BSP_ROOT = os.path.abspath(env['BSP_ROOT']) CPPDEFINES = project['CPPDEFINES'] paths = [ConverToRttEclipsePathFormat(RelativeProjectPath(env, os.path.normpath(i)).replace('\\', '/')) for i in project['CPPPATH']] - compile_include_paths_option = None - compile_include_files_option = None - compile_defs_option = None + compile_include_paths_options = [] + compile_include_files_options = [] + compile_defs_options = [] linker_scriptfile_option = None linker_script_option = None linker_nostart_option = None linker_libs_option = None linker_paths_option = None + linker_newlib_nano_option = None for tool in tools: - if tool.get('id').find('c.compile') != 1: + if tool.get('id').find('compile') != 1: options = tool.findall('option') # find all compile options for option in options: - if option.get('id').find('c.compiler.include.paths') != -1 or option.get('id').find('c.compiler.option.includepaths') != -1: - compile_include_paths_option = option - elif option.get('id').find('c.compiler.include.files') != -1 or option.get('id').find('c.compiler.option.includefiles') != -1 : - compile_include_files_option = option - elif option.get('id').find('c.compiler.defs') != -1 or option.get('id').find('c.compiler.option.definedsymbols') != -1: - compile_defs_option = option - - if tool.get('id').find('c.linker') != -1: + if option.get('id').find('compiler.include.paths') != -1 or option.get('id').find('compiler.option.includepaths') != -1: + compile_include_paths_options += [option] + elif option.get('id').find('compiler.include.files') != -1 or option.get('id').find('compiler.option.includefiles') != -1 : + compile_include_files_options += [option] + elif option.get('id').find('compiler.defs') != -1 or option.get('id').find('compiler.option.definedsymbols') != -1: + compile_defs_options += [option] + + if tool.get('id').find('linker') != -1: options = tool.findall('option') # find all linker options for option in options: - if option.get('id').find('c.linker.scriptfile') != -1: + # the project type and option type must equal + if is_cpp_prj != (option.get('id').find('cpp.linker') != -1): + continue + + if option.get('id').find('linker.scriptfile') != -1: linker_scriptfile_option = option - elif option.get('id').find('c.linker.option.script') != -1: + elif option.get('id').find('linker.option.script') != -1: linker_script_option = option - elif option.get('id').find('c.linker.nostart') != -1: + elif option.get('id').find('linker.nostart') != -1: linker_nostart_option = option - elif option.get('id').find('c.linker.libs') != -1 and env.has_key('LIBS'): + elif option.get('id').find('linker.libs') != -1 and env.has_key('LIBS'): linker_libs_option = option - elif option.get('id').find('c.linker.paths') != -1 and env.has_key('LIBPATH'): + elif option.get('id').find('linker.paths') != -1 and env.has_key('LIBPATH'): linker_paths_option = option - elif option.get('id').find('c.linker.usenewlibnano') != -1: + elif option.get('id').find('linker.usenewlibnano') != -1: linker_newlib_nano_option = option # change the inclue path - if compile_include_paths_option is not None : - option = compile_include_paths_option + for option in compile_include_paths_options: # find all of paths in this project include_paths = option.findall('listOptionValue') for item in include_paths: @@ -196,8 +209,7 @@ def HandleToolOption(tools, env, project, reset): for item in paths: SubElement(option, 'listOptionValue', {'builtIn': 'false', 'value': item}) # change the inclue files (default) or definitions - if compile_include_files_option is not None: - option = compile_include_files_option + for option in compile_include_files_options: # add '_REENT_SMALL' to CPPDEFINES when --specs=nano.specs has select if linker_newlib_nano_option is not None and linker_newlib_nano_option.get('value') == 'true' and '_REENT_SMALL' not in CPPDEFINES: CPPDEFINES += ['_REENT_SMALL'] @@ -227,25 +239,25 @@ def HandleToolOption(tools, env, project, reset): break if find_ok is False: SubElement(option, 'listOptionValue', {'builtIn': 'false', 'value': rtt_pre_inc_item}) - elif compile_defs_option is not None : - option = compile_defs_option - defs = option.findall('listOptionValue') - project_defs = [] - for item in defs: - if reset is True: - # clean all old configuration - option.remove(item) + if len(compile_include_files_options) == 0: + for option in compile_defs_options: + defs = option.findall('listOptionValue') + project_defs = [] + for item in defs: + if reset is True: + # clean all old configuration + option.remove(item) + else: + project_defs += [item.get('value')] + if len(project_defs) > 0: + cproject_defs = set(CPPDEFINES) - set(project_defs) else: - project_defs += [item.get('value')] - if len(project_defs) > 0: - cproject_defs = set(CPPDEFINES) - set(project_defs) - else: - cproject_defs = CPPDEFINES + cproject_defs = CPPDEFINES - # print('c.compiler.defs') - cproject_defs = sorted(cproject_defs) - for item in cproject_defs: - SubElement(option, 'listOptionValue', {'builtIn': 'false', 'value': item}) + # print('c.compiler.defs') + cproject_defs = sorted(cproject_defs) + for item in cproject_defs: + SubElement(option, 'listOptionValue', {'builtIn': 'false', 'value': item}) # update linker script config if linker_scriptfile_option is not None : diff --git a/tools/gcc.py b/tools/gcc.py index 2e29c8f34b17793f117103d7884872a46af5a229..8c9685d52b9a9811c367ca26e95331a012f0deca 100644 --- a/tools/gcc.py +++ b/tools/gcc.py @@ -23,7 +23,7 @@ import os import re -import platform +import platform def GetGCCRoot(rtconfig): exec_path = rtconfig.EXEC_PATH @@ -63,7 +63,7 @@ def CheckHeader(rtconfig, filename): fn = os.path.join(root, prefix, 'include', filename) if os.path.isfile(fn): return True - + return False def GetNewLibVersion(rtconfig): @@ -98,18 +98,18 @@ def GCCResult(rtconfig, str): gcc_cmd = os.path.join(rtconfig.EXEC_PATH, rtconfig.CC) - # use temp file to get more information + # use temp file to get more information f = open('__tmp.c', 'w') if f: f.write(str) f.close() - # '-fdirectives-only', + # '-fdirectives-only', if(platform.system() == 'Windows'): child = subprocess.Popen([gcc_cmd, '-E', '-P', '__tmp.c'], stdout=subprocess.PIPE, stderr=subprocess.PIPE, shell=True) else: child = subprocess.Popen(gcc_cmd + ' -E -P __tmp.c', stdout=subprocess.PIPE, stderr=subprocess.PIPE, shell=True) - + stdout, stderr = child.communicate() # print(stdout) @@ -148,7 +148,7 @@ def GCCResult(rtconfig, str): if re.findall('pthread_create', line): posix_thread = 1 - + if have_fdset: result += '#define HAVE_FDSET 1\n' @@ -162,7 +162,7 @@ def GCCResult(rtconfig, str): result += '#define HAVE_SIGVAL 1\n' if version: - result += '#define GCC_VERSION "%s"\n' % version + result += '#define GCC_VERSION_STR "%s"\n' % version result += '#define STDC "%s"\n' % stdc