From aac6fe0fec3d01ae995328f1c38bae103e90ded4 Mon Sep 17 00:00:00 2001 From: William Chen Date: Wed, 7 Apr 2021 14:07:55 -0700 Subject: [PATCH 1/2] memlayout of struct param > 4 bytes should align at 8 bytes. --- src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp index c89a84fcfc..3e06f38bbd 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_memlayout.cpp @@ -206,6 +206,10 @@ void AArch64MemLayout::LayoutFormalParams() { SetSizeAlignForTypeIdx(ptyIdx, size, align); symLoc->SetMemSegment(GetSegArgsRegPassed()); /* the type's alignment requirement may be smaller than a registser's byte size */ + if (ty->GetPrimType() == PTY_agg && be.GetTypeSize(ptyIdx) > k4ByteSize) { + /* struct param aligned on 8 byte boundary unless it is small enough */ + align = kSizeOfPtr; + } segArgsRegPassed.SetSize(RoundUp(segArgsRegPassed.GetSize(), align)); symLoc->SetOffset(segArgsRegPassed.GetSize()); segArgsRegPassed.SetSize(segArgsRegPassed.GetSize() + size); -- Gitee From 0aa3f3f33cb0858393ead6df334a1bc7efcd932f Mon Sep 17 00:00:00 2001 From: William Chen Date: Wed, 7 Apr 2021 14:20:05 -0700 Subject: [PATCH 2/2] fix moveregargs where small struct's 2nd reg is missing --- .../maple_be/include/cg/aarch64/aarch64_args.h | 3 ++- .../maple_be/src/cg/aarch64/aarch64_args.cpp | 13 +++++++++---- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/src/mapleall/maple_be/include/cg/aarch64/aarch64_args.h b/src/mapleall/maple_be/include/cg/aarch64/aarch64_args.h index d7da2ecd87..8e65824e2e 100644 --- a/src/mapleall/maple_be/include/cg/aarch64/aarch64_args.h +++ b/src/mapleall/maple_be/include/cg/aarch64/aarch64_args.h @@ -31,7 +31,8 @@ struct ArgInfo { const AArch64SymbolAlloc *symLoc; uint8 memPairSecondRegSize; /* struct arg requiring two regs, size of 2nd reg */ bool doMemPairOpt; - bool CreateTwoStores; + bool createTwoStores; + bool isTwoRegParm; }; class AArch64MoveRegArgs : public MoveRegArgs { diff --git a/src/mapleall/maple_be/src/cg/aarch64/aarch64_args.cpp b/src/mapleall/maple_be/src/cg/aarch64/aarch64_args.cpp index faa728dec8..aad3631c0c 100644 --- a/src/mapleall/maple_be/src/cg/aarch64/aarch64_args.cpp +++ b/src/mapleall/maple_be/src/cg/aarch64/aarch64_args.cpp @@ -89,8 +89,10 @@ ArgInfo AArch64MoveRegArgs::GetArgInfo(std::map &argsList, s argInfo.symSize = aarchCGFunc->GetBecommon().GetTypeSize(argInfo.mirTy->GetTypeIndex()); argInfo.memPairSecondRegSize = 0; argInfo.doMemPairOpt = false; - argInfo.CreateTwoStores = false; + argInfo.createTwoStores = false; + argInfo.isTwoRegParm = false; if ((argInfo.symSize > k8ByteSize) && (argInfo.symSize <= k16ByteSize)) { + argInfo.isTwoRegParm = true; if (numFpRegs[argIndex] > kOneRegister) { argInfo.symSize = argInfo.stkSize = fpSize[argIndex]; } else { @@ -110,6 +112,7 @@ ArgInfo AArch64MoveRegArgs::GetArgInfo(std::map &argsList, s /* For small aggregate parameter, set to minimum of 4 bytes. */ argInfo.symSize = argInfo.stkSize = k4ByteSize; } else if (numFpRegs[argIndex] > kOneRegister) { + argInfo.isTwoRegParm = true; argInfo.symSize = argInfo.stkSize = fpSize[argIndex]; } else { argInfo.stkSize = (argInfo.symSize < k4ByteSize) ? k4ByteSize : argInfo.symSize; @@ -129,7 +132,7 @@ ArgInfo AArch64MoveRegArgs::GetArgInfo(std::map &argsList, s */ argInfo.symSize = kSizeOfPtr; argInfo.doMemPairOpt = false; - argInfo.CreateTwoStores = true; + argInfo.createTwoStores = true; } return argInfo; } @@ -256,7 +259,7 @@ void AArch64MoveRegArgs::GenerateStrInsn(ArgInfo &argInfo, AArch64reg reg2, uint } aarchCGFunc->GetCurBB()->AppendInsn(insn); - if (argInfo.CreateTwoStores || argInfo.doMemPairOpt) { + if (argInfo.createTwoStores || argInfo.doMemPairOpt) { /* second half of the struct passing by registers. */ uint32 part2BitSize = argInfo.memPairSecondRegSize * kBitsPerByte; GenOneInsn(argInfo, *baseOpnd, part2BitSize, reg2, (stOffset + kSizeOfPtr)); @@ -304,7 +307,9 @@ void AArch64MoveRegArgs::MoveRegisterArgs() { static_cast(aarchCGFunc->GetMemlayout()->GetSymAllocInfo( secondArgInfo.sym->GetStIndex())); /* Make sure they are in same segment if want to use stp */ - if (firstArgInfo.doMemPairOpt || IsInSameSegment(firstArgInfo, secondArgInfo)) { + if (((firstArgInfo.isTwoRegParm && secondArgInfo.isTwoRegParm) || + (firstArgInfo.isTwoRegParm == false && secondArgInfo.isTwoRegParm == false)) && + (firstArgInfo.doMemPairOpt || IsInSameSegment(firstArgInfo, secondArgInfo))) { GenerateStpInsn(firstArgInfo, secondArgInfo); if (firstArgInfo.doMemPairOpt == false) { it = next; -- Gitee