rematerialization opportunity

spec 502 ,  df-core.c  Function  df_worklist_dataflow_doublequeue

the third arg "considered" is used as "considered)->elms [(e->src->index) / ((unsigned) (8 * 8))]" in the inner-most loop before subcall bitmap_set_bit .

then we have an extra add to access elems before the loop

Basically we assign registers for both "considered" and  "&(considered->elms)", which the latter could be a perfect candidate of rematerialization.

```c
regassign ptr %542 (iaddrof ptr <* <$simple_bitmap_def>> 4 (regread ptr %529))
```

```c
=== BB  <BB_ft> <95> [Loop level 2, head BB 5]succs: 96 ===
frequency:0
< 1044 > ldr(196) (opnd0: vreg:R3994 class: [I] validBitNum: [64]) (opnd1: Mem:base: reg:R29 class: [I] validBitNum: [64]offset:ofst:24  intact)
< 1047 > mov(1) (opnd0: vreg:R741 class: [I] validBitNum: [64]) (opnd1: vreg:R3994 class: [I] validBitNum: [64])
< 1050 > add(19) (opnd0: vreg:R742 class: [I] validBitNum: [64]) (opnd1: vreg:R729 class: [I] validBitNum: [64]) (opnd2: imm:16)           ==================  here
=== BB  <BB_if[labeled with 213 ==> @@213]> <96> [Loop level 3, head BB 96]succs: 288 97 ===
frequency:0
< 1053 > ldr(196) (opnd0: vreg:R219 class: [I] validBitNum: [64]) (opnd1: Mem:base:vreg:R3886 class: [I] validBitNum: [64]offset:ofst:8  intact)
< 1056 > ldr(195) (opnd0: vreg:R220 class: [I] validBitNum: [32]) (opnd1: Mem:base:vreg:R219 class: [I] validBitNum: [64]offset:ofst:80  intact)
< 1059 > lsr(145) (opnd0: vreg:R3996 class: [I] validBitNum: [32]) (opnd1: vreg:R220 class: [I] validBitNum: [32]) (opnd2: imm:6)
< 1062 > ldr(196) (opnd0: vreg:R3995 class: [I] validBitNum: [64]) (opnd1: Mem:base:vreg:R742 class: [I] validBitNum: [64]offset:vreg:R3996 class: [I] validBitNum: [32] SXTW shift: 3)
< 1065 > and(103) (opnd0: vreg:R3997 class: [I] validBitNum: [32]) (opnd1: vreg:R220 class: [I] validBitNum: [32]) (opnd2: imm:63)
< 1068 > lsr(150) (opnd0: vreg:R4000 class: [I] validBitNum: [64]) (opnd1: vreg:R3995 class: [I] validBitNum: [64]) (opnd2: vreg:R3997 class: [I] validBitNum: [32])
< 0 > tbz(286) (opnd0: vreg:R4000 class: [I] validBitNum: [64]) (opnd1: imm:0) (opnd2: label:392)
=== BB  <BB_ft> <97> [Loop level 3, head BB 96]succs: 98 ===
frequency:0
< 1077 > //(428) (opnd0: # callassigned : bitmap_set_bit)
< 1080 > //(428) (opnd0: # bitmap_set_bit)
< 1083 > mov(1) (opnd0:  reg:R0 class: [I] validBitNum: [64]) (opnd1: vreg:R832 class: [I] validBitNum: [64])
< 1086 > mov(1) (opnd0: vreg:R4003 class: [I] validBitNum: [64]) (opnd1: vreg:R220 class: [I] validBitNum: [32])
< 1089 > ldr(195) (opnd0:  reg:R1 class: [I] validBitNum: [32]) (opnd1: Mem:base:vreg:R727 class: [I] validBitNum: [64]offset:vreg:R4003 class: [I] validBitNum: [64] LSL shift: 2)
< 1095 > bl(185) (opnd0: bitmap_set_bit) (opnd1:  reg:R0 class: [I] validBitNum: [64] reg:R1 class: [I] validBitNum: [32])
=== BB  <BB_if[labeled with 186 ==> @@186]> <98> [Loop level 3, head BB 96]succs: 289 99 ===

```

R742, R729 occupy two seperate callee save regs.

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GVP方舟编译器/OpenArkCompiler

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