# 数据转串行并行输出

**Repository Path**: koda_duck/data-to-serial-parallel-output

## Basic Information

- **Project Name**: 数据转串行并行输出
- **Description**: 8421BCD code to serial parallel output module！
- **Primary Language**: Unknown
- **License**: MulanPSL-2.0
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 2
- **Forks**: 0
- **Created**: 2022-06-23
- **Last Updated**: 2025-02-26

## Categories & Tags

**Categories**: Uncategorized

**Tags**: systemverilog, Verilog, uvm

## README

# 数据转串行并行输出

#### Description
8421BCD code to serial parallel output module！

#### Software Architecture
Software architecture description

#### Installation

1.  xxxx
2.  xxxx
3.  xxxx

#### Instructions

1.  xxxx
2.  xxxx
3.  xxxx

#### Contribution

1.  Fork the repository
2.  Create Feat_xxx branch
3.  Commit your code
4.  Create Pull Request


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