# rtsmart-rk3326 **Repository Path**: fuyun_lee/rtsmart-rk3326 ## Basic Information - **Project Name**: rtsmart-rk3326 - **Description**: ARM Cortex A35 4 core 64bit for RT-Thread - **Primary Language**: Unknown - **License**: WTFPL - **Default Branch**: master - **Homepage**: None - **GVP Project**: No ## Statistics - **Stars**: 0 - **Forks**: 7 - **Created**: 2021-10-21 - **Last Updated**: 2021-10-21 ## Categories & Tags **Categories**: Uncategorized **Tags**: None ## README # ODROID-GO-ADVANCE 2.0 开源掌机 BSP 说明 ## 简介 ODROID-GO-ADVANCE 2.0（简称OGA2，下文均使用简称）开源掌机是一块原理图、芯片手册、uboot、linux kernel 均开源的游戏掌机。 该 BSP 使用的 AARCH64 模式进行对接。 该 BSP 仅供娱乐，欢迎各位大佬尝试移植各种驱动和应用，本人为鸽子王随时可能鸽。 如果觉得该还有点点帮助的话，麻烦给颗星星~ ## 外观 掌机外观如下图所示： ![board](./figures/odroidgo2.png) ## 板载资源 该开发板常用 **板载资源** 如下： ![正面](./figures/oga_rev11_back.png) - A: Processor : - CPU : RockChip RK3326(Quad-Core ARM Cortex-A35 1.3GHz) - GPU : Mali-G31 Dvalin - B: RAM : 1GB (DDR3L 786Mhz, 32 Bits bus width) - C: SPI Flash (16Mbytes Boot) - D: MicroSD card slot - E: Forced SD card boot (without spirom) - F: UART port (But not mounted default) - G: Speaker connector - H: Battery connector - I: USB 2.0 type-A Host - J: Statue LED (charger, alive, power) - K: USB-C power Jack - L: 10pin expansion port - M: Audio jack - N: 20pin LCD connector - O: PWR switch - P: Analog joystick connector - Q: Left trigger button - R: Right trigger button - S: Wireless module ESP-WROOM-S2 ![反面](./figures/oga_rev11_front.png) - A: PMIC(RK817) including a charger and audio features - B: D-pad buttons - C: I ~ VI buttons (F1, F2, F3, F4, F5, F6) - D: X, Y, A, B buttons - E: Trigger Left2 - F: Trigger Right2 ## RK3326 架构图 ![arm1](./figures/arm1.png) ![arm2](./figures/arm2.png) ## RK3326 SDCARD 分区表 http://opensource.rock-chips.com/wiki_Partitions ![GPT](./figures/GPTPartitionTable.png) ## RK3326 内存性能测试数据 ``` msh />tinymemnench tinymembench v0.4 (simple benchmark for memory throughput and latency) ========================================================================== == Memory bandwidth tests == == == == Note 1: 1MB = 1000000 bytes == == Note 2: Results for 'copy' tests show how many bytes can be == == copied per second (adding together read and writen == == bytes would have provided twice higher numbers) == == Note 3: 2-pass copy means that we are using a small temporary buffer == == to first fetch data into it, and only then write it to the == == destination (source -> L1 cache, L1 cache -> destination) == == Note 4: If sample standard deviation exceeds 0.1%, it is shown in == == brackets == ========================================================================== C copy backwards : 851.6 MB/s C copy backwards (32 byte blocks) : 850.2 MB/s C copy backwards (64 byte blocks) : 829.2 MB/s C copy : 833.3 MB/s C copy prefetched (32 bytes step) : 881.5 MB/s C copy prefetched (64 bytes step) : 875.3 MB/s C 2-pass copy : 740.2 MB/s C 2-pass copy prefetched (32 bytes step) : 762.6 MB/s C 2-pass copy prefetched (64 bytes step) : 762.6 MB/s C fill : 2472.4 MB/s C fill (shuffle within 16 byte blocks) : 2475.3 MB/s C fill (shuffle within 32 byte blocks) : 2472.4 MB/s C fill (shuffle within 64 byte blocks) : 2472.4 MB/s --- standard memcpy : 854.5 MB/s standard memset : 2472.4 MB/s --- NEON LDP/STP copy : 900.4 MB/s NEON LD1/ST1 copy : 883.0 MB/s NEON STP fill : 2475.3 MB/s NEON STNP fill : 2441.0 MB/s ARM LDP/STP copy : 867.8 MB/s ARM STP fill : 2472.4 MB/s ARM STNP fill : 2443.8 MB/s ========================================================================== == Memory latency test == == == == Average time is measured for random memory accesses in the buffers == == of different sizes. The larger is the buffer, the more significant == == are relative contributions of TLB, L1/L2 cache misses and SDRAM == == accesses. For extremely large buffer sizes we are expecting to see == == page table walk with several requests to SDRAM for almost every == == memory access (though 64MiB is not nearly large enough to experience == == this effect to its fullest). == == == == Note 1: All the numbers are representing extra time, which needs to == == be added to L1 cache latency. The cycle timings for L1 cache == == latency can be usually found in the processor documentation. == == Note 2: Dual random read means that we are simultaneously performing == == two independent memory accesses at a time. In the case if == == the memory subsystem can't handle multiple outstanding == == requests, dual random read has the same timings as two == == single reads performed one after another. == ========================================================================== block size : single random read / dual random read 1024 : 0.0 ns / 0.0 ns 2048 : 0.0 ns / 0.0 ns 4096 : 0.0 ns / 0.0 ns 8192 : 0.0 ns / 0.0 ns 16384 : 0.0 ns / 0.0 ns 32768 : 0.1 ns / 0.1 ns 65536 : 11.4 ns / 18.5 ns 131072 : 17.4 ns / 25.6 ns 262144 : 21.6 ns / 29.9 ns 524288 : 128.6 ns / 196.1 ns 1048576 : 192.1 ns / 256.5 ns 2097152 : 224.9 ns / 276.6 ns 4194304 : 242.4 ns / 283.3 ns 8388608 : 251.3 ns / 286.0 ns 16777216 : 255.3 ns / 287.3 ns 33554432 : 257.3 ns / 287.9 ns 67108864 : 258.2 ns / 288.3 ns ```